1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Debug.h"
36 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
37 unsigned StackAlignOverride)
38 : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
39 STI.is64Bit() ? -8 : -4),
40 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
41 // Cache a bunch of frame-related predicates for this subtarget.
42 SlotSize = TRI->getSlotSize();
43 Is64Bit = STI.is64Bit();
44 IsLP64 = STI.isTarget64BitLP64();
45 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
46 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
47 StackPtr = TRI->getStackRegister();
50 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
51 return !MF.getFrameInfo()->hasVarSizedObjects() &&
52 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
55 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
56 /// call frame pseudos can be simplified. Having a FP, as in the default
57 /// implementation, is not sufficient here since we can't always use it.
58 /// Use a more nuanced condition.
60 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
61 return hasReservedCallFrame(MF) ||
62 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
63 TRI->hasBasePointer(MF);
66 // needsFrameIndexResolution - Do we need to perform FI resolution for
67 // this function. Normally, this is required only when the function
68 // has any stack objects. However, FI resolution actually has another job,
69 // not apparent from the title - it resolves callframesetup/destroy
70 // that were not simplified earlier.
71 // So, this is required for x86 functions that have push sequences even
72 // when there are no stack objects.
74 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
75 return MF.getFrameInfo()->hasStackObjects() ||
76 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
79 /// hasFP - Return true if the specified function should have a dedicated frame
80 /// pointer register. This is true if the function has variable sized allocas
81 /// or if frame pointer elimination is disabled.
82 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
83 const MachineFrameInfo *MFI = MF.getFrameInfo();
84 const MachineModuleInfo &MMI = MF.getMMI();
86 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
87 TRI->needsStackRealignment(MF) ||
88 MFI->hasVarSizedObjects() ||
89 MFI->isFrameAddressTaken() || MFI->hasOpaqueSPAdjustment() ||
90 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
91 MMI.callsUnwindInit() || MMI.callsEHReturn() ||
92 MFI->hasStackMap() || MFI->hasPatchPoint());
95 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
99 return X86::SUB64ri32;
102 return X86::SUB32ri8;
107 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
110 return X86::ADD64ri8;
111 return X86::ADD64ri32;
114 return X86::ADD32ri8;
119 static unsigned getSUBrrOpcode(unsigned isLP64) {
120 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
123 static unsigned getADDrrOpcode(unsigned isLP64) {
124 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
127 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
130 return X86::AND64ri8;
131 return X86::AND64ri32;
134 return X86::AND32ri8;
138 static unsigned getLEArOpcode(unsigned IsLP64) {
139 return IsLP64 ? X86::LEA64r : X86::LEA32r;
142 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
143 /// when it reaches the "return" instruction. We can then pop a stack object
144 /// to this register without worry about clobbering it.
145 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
146 MachineBasicBlock::iterator &MBBI,
147 const TargetRegisterInfo *TRI,
149 const MachineFunction *MF = MBB.getParent();
150 const Function *F = MF->getFunction();
151 if (!F || MF->getMMI().callsEHReturn())
154 static const uint16_t CallerSavedRegs32Bit[] = {
155 X86::EAX, X86::EDX, X86::ECX, 0
158 static const uint16_t CallerSavedRegs64Bit[] = {
159 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
160 X86::R8, X86::R9, X86::R10, X86::R11, 0
163 unsigned Opc = MBBI->getOpcode();
170 case X86::TCRETURNdi:
171 case X86::TCRETURNri:
172 case X86::TCRETURNmi:
173 case X86::TCRETURNdi64:
174 case X86::TCRETURNri64:
175 case X86::TCRETURNmi64:
177 case X86::EH_RETURN64: {
178 SmallSet<uint16_t, 8> Uses;
179 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
180 MachineOperand &MO = MBBI->getOperand(i);
181 if (!MO.isReg() || MO.isDef())
183 unsigned Reg = MO.getReg();
186 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
190 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
192 if (!Uses.count(*CS))
200 static bool isEAXLiveIn(MachineFunction &MF) {
201 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
202 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
203 unsigned Reg = II->first;
205 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
206 Reg == X86::AH || Reg == X86::AL)
213 /// Check whether or not the terminators of \p MBB needs to read EFLAGS.
214 static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
215 for (const MachineInstr &MI : MBB.terminators()) {
216 bool BreakNext = false;
217 for (const MachineOperand &MO : MI.operands()) {
220 unsigned Reg = MO.getReg();
221 if (Reg != X86::EFLAGS)
224 // This terminator needs an eflag that is not defined
225 // by a previous terminator.
236 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
237 /// stack pointer by a constant value.
238 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
239 MachineBasicBlock::iterator &MBBI,
240 int64_t NumBytes, bool InEpilogue) const {
241 bool isSub = NumBytes < 0;
242 uint64_t Offset = isSub ? -NumBytes : NumBytes;
244 uint64_t Chunk = (1LL << 31) - 1;
245 DebugLoc DL = MBB.findDebugLoc(MBBI);
248 if (Offset > Chunk) {
249 // Rather than emit a long series of instructions for large offsets,
250 // load the offset into a register and do one sub/add
253 if (isSub && !isEAXLiveIn(*MBB.getParent()))
254 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
256 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
259 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
260 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
263 ? getSUBrrOpcode(Is64Bit)
264 : getADDrrOpcode(Is64Bit);
265 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
268 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
274 uint64_t ThisVal = std::min(Offset, Chunk);
275 if (ThisVal == (Is64Bit ? 8 : 4)) {
276 // Use push / pop instead.
278 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
279 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
282 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
283 : (Is64Bit ? X86::POP64r : X86::POP32r);
284 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
285 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
287 MI->setFlag(MachineInstr::FrameSetup);
293 MachineInstrBuilder MI = BuildStackAdjustment(
294 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue);
296 MI.setMIFlag(MachineInstr::FrameSetup);
302 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
303 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
304 int64_t Offset, bool InEpilogue) const {
305 assert(Offset != 0 && "zero offset stack adjustment requested");
307 // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
311 UseLEA = STI.useLeaForSP();
313 // If we can use LEA for SP but we shouldn't, check that none
314 // of the terminators uses the eflags. Otherwise we will insert
315 // a ADD that will redefine the eflags and break the condition.
316 // Alternatively, we could move the ADD, but this may not be possible
317 // and is an optimization anyway.
318 UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
319 if (UseLEA && !STI.useLeaForSP())
320 UseLEA = terminatorsNeedFlagsAsInput(MBB);
321 // If that assert breaks, that means we do not do the right thing
322 // in canUseAsEpilogue.
323 assert((UseLEA || !terminatorsNeedFlagsAsInput(MBB)) &&
324 "We shouldn't have allowed this insertion point");
327 MachineInstrBuilder MI;
329 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
330 TII.get(getLEArOpcode(Uses64BitFramePtr)),
332 StackPtr, false, Offset);
334 bool IsSub = Offset < 0;
335 uint64_t AbsOffset = IsSub ? -Offset : Offset;
336 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
337 : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
338 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
341 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
346 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
347 MachineBasicBlock::iterator &MBBI,
348 bool doMergeWithPrevious) const {
349 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
350 (!doMergeWithPrevious && MBBI == MBB.end()))
353 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
354 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
356 unsigned Opc = PI->getOpcode();
359 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
360 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
361 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
362 PI->getOperand(0).getReg() == StackPtr){
363 Offset += PI->getOperand(2).getImm();
365 if (!doMergeWithPrevious) MBBI = NI;
366 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
367 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
368 PI->getOperand(0).getReg() == StackPtr) {
369 Offset -= PI->getOperand(2).getImm();
371 if (!doMergeWithPrevious) MBBI = NI;
377 void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
378 MachineBasicBlock::iterator MBBI, DebugLoc DL,
379 MCCFIInstruction CFIInst) const {
380 MachineFunction &MF = *MBB.getParent();
381 unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
382 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
383 .addCFIIndex(CFIIndex);
387 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
388 MachineBasicBlock::iterator MBBI,
390 MachineFunction &MF = *MBB.getParent();
391 MachineFrameInfo *MFI = MF.getFrameInfo();
392 MachineModuleInfo &MMI = MF.getMMI();
393 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
395 // Add callee saved registers to move list.
396 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
397 if (CSI.empty()) return;
399 // Calculate offsets.
400 for (std::vector<CalleeSavedInfo>::const_iterator
401 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
402 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
403 unsigned Reg = I->getReg();
405 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
406 BuildCFI(MBB, MBBI, DL,
407 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
411 /// usesTheStack - This function checks if any of the users of EFLAGS
412 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
413 /// to use the stack, and if we don't adjust the stack we clobber the first
415 /// See X86InstrInfo::copyPhysReg.
416 static bool usesTheStack(const MachineFunction &MF) {
417 const MachineRegisterInfo &MRI = MF.getRegInfo();
419 for (MachineRegisterInfo::reg_instr_iterator
420 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
428 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
429 MachineBasicBlock &MBB,
430 MachineBasicBlock::iterator MBBI,
432 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
436 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
438 CallOp = X86::CALLpcrel32;
442 if (STI.isTargetCygMing()) {
443 Symbol = "___chkstk_ms";
447 } else if (STI.isTargetCygMing())
452 MachineInstrBuilder CI;
454 // All current stack probes take AX and SP as input, clobber flags, and
455 // preserve all registers. x86_64 probes leave RSP unmodified.
456 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
457 // For the large code model, we have to call through a register. Use R11,
458 // as it is scratch in all supported calling conventions.
459 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
460 .addExternalSymbol(Symbol);
461 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
463 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
466 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
467 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
468 CI.addReg(AX, RegState::Implicit)
469 .addReg(SP, RegState::Implicit)
470 .addReg(AX, RegState::Define | RegState::Implicit)
471 .addReg(SP, RegState::Define | RegState::Implicit)
472 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
475 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
476 // themselves. It also does not clobber %rax so we can reuse it when
478 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
484 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
485 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
486 // and might require smaller successive adjustments.
487 const uint64_t Win64MaxSEHOffset = 128;
488 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
489 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
490 return SEHFrameOffset & -16;
493 // If we're forcing a stack realignment we can't rely on just the frame
494 // info, we need to know the ABI stack alignment as well in case we
495 // have a call out. Otherwise just make sure we have some alignment - we'll
496 // go with the minimum SlotSize.
497 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
498 const MachineFrameInfo *MFI = MF.getFrameInfo();
499 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
500 unsigned StackAlign = getStackAlignment();
501 if (ForceStackAlign) {
503 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
504 else if (MaxAlign < SlotSize)
510 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
511 MachineBasicBlock::iterator MBBI,
513 uint64_t MaxAlign) const {
514 uint64_t Val = -MaxAlign;
516 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
520 .setMIFlag(MachineInstr::FrameSetup);
522 // The EFLAGS implicit def is dead.
523 MI->getOperand(3).setIsDead();
526 /// emitPrologue - Push callee-saved registers onto the stack, which
527 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
528 /// space for local variables. Also emit labels used by the exception handler to
529 /// generate the exception handling frames.
532 Here's a gist of what gets emitted:
534 ; Establish frame pointer, if needed
537 .cfi_def_cfa_offset 16
538 .cfi_offset %rbp, -16
541 .cfi_def_cfa_register %rbp
543 ; Spill general-purpose registers
544 [for all callee-saved GPRs]
547 .cfi_def_cfa_offset (offset from RETADDR)
550 ; If the required stack alignment > default stack alignment
551 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
552 ; of unknown size in the stack frame.
553 [if stack needs re-alignment]
556 ; Allocate space for locals
557 [if target is Windows and allocated space > 4096 bytes]
558 ; Windows needs special care for allocations larger
561 call ___chkstk_ms/___chkstk
567 .seh_stackalloc (size of XMM spill slots)
568 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
573 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
574 ; they may get spilled on any platform, if the current function
575 ; calls @llvm.eh.unwind.init
577 [for all callee-saved XMM registers]
578 movaps %<xmm reg>, -MMM(%rbp)
579 [for all callee-saved XMM registers]
580 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
581 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
583 [for all callee-saved XMM registers]
584 movaps %<xmm reg>, KKK(%rsp)
585 [for all callee-saved XMM registers]
586 .seh_savexmm %<xmm reg>, KKK
590 [if needs base pointer]
592 [if needs to restore base pointer]
597 [for all callee-saved registers]
598 .cfi_offset %<reg>, (offset from %rbp)
600 .cfi_def_cfa_offset (offset from RETADDR)
601 [for all callee-saved registers]
602 .cfi_offset %<reg>, (offset from %rsp)
605 - .seh directives are emitted only for Windows 64 ABI
606 - .cfi directives are emitted for all other ABIs
607 - for 32-bit code, substitute %e?? registers for %r??
610 void X86FrameLowering::emitPrologue(MachineFunction &MF,
611 MachineBasicBlock &MBB) const {
612 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
613 "MF used frame lowering for wrong subtarget");
614 MachineBasicBlock::iterator MBBI = MBB.begin();
615 MachineFrameInfo *MFI = MF.getFrameInfo();
616 const Function *Fn = MF.getFunction();
617 MachineModuleInfo &MMI = MF.getMMI();
618 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
619 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
620 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
621 bool HasFP = hasFP(MF);
622 bool IsWin64CC = STI.isCallingConvWin64(Fn->getCallingConv());
623 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
624 bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();
626 !IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
627 unsigned FramePtr = TRI->getFrameRegister(MF);
628 const unsigned MachineFramePtr =
629 STI.isTarget64BitILP32()
630 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
632 unsigned BasePtr = TRI->getBaseRegister();
635 // Add RETADDR move area to callee saved frame size.
636 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
637 if (TailCallReturnAddrDelta && IsWin64Prologue)
638 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
640 if (TailCallReturnAddrDelta < 0)
641 X86FI->setCalleeSavedFrameSize(
642 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
644 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
646 // The default stack probe size is 4096 if the function has no stackprobesize
648 unsigned StackProbeSize = 4096;
649 if (Fn->hasFnAttribute("stack-probe-size"))
650 Fn->getFnAttribute("stack-probe-size")
652 .getAsInteger(0, StackProbeSize);
654 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
655 // function, and use up to 128 bytes of stack space, don't have a frame
656 // pointer, calls, or dynamic alloca then we do not need to adjust the
657 // stack pointer (we fit in the Red Zone). We also check that we don't
658 // push and pop from the stack.
659 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
660 !TRI->needsStackRealignment(MF) &&
661 !MFI->hasVarSizedObjects() && // No dynamic alloca.
662 !MFI->adjustsStack() && // No calls.
663 !IsWin64CC && // Win64 has no Red Zone
664 !usesTheStack(MF) && // Don't push and pop.
665 !MF.shouldSplitStack()) { // Regular stack
666 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
667 if (HasFP) MinSize += SlotSize;
668 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
669 MFI->setStackSize(StackSize);
672 // Insert stack pointer adjustment for later moving of return addr. Only
673 // applies to tail call optimized functions where the callee argument stack
674 // size is bigger than the callers.
675 if (TailCallReturnAddrDelta < 0) {
676 BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
677 /*InEpilogue=*/false)
678 .setMIFlag(MachineInstr::FrameSetup);
681 // Mapping for machine moves:
683 // DST: VirtualFP AND
684 // SRC: VirtualFP => DW_CFA_def_cfa_offset
685 // ELSE => DW_CFA_def_cfa
687 // SRC: VirtualFP AND
688 // DST: Register => DW_CFA_def_cfa_register
691 // OFFSET < 0 => DW_CFA_offset_extended_sf
692 // REG < 64 => DW_CFA_offset + Reg
693 // ELSE => DW_CFA_offset_extended
695 uint64_t NumBytes = 0;
696 int stackGrowth = -SlotSize;
699 // Calculate required stack adjustment.
700 uint64_t FrameSize = StackSize - SlotSize;
701 // If required, include space for extra hidden slot for stashing base pointer.
702 if (X86FI->getRestoreBasePointer())
703 FrameSize += SlotSize;
705 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
707 // Callee-saved registers are pushed on stack before the stack is realigned.
708 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
709 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
711 // Get the offset of the stack slot for the EBP register, which is
712 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
713 // Update the frame offset adjustment.
714 MFI->setOffsetAdjustment(-NumBytes);
716 // Save EBP/RBP into the appropriate stack slot.
717 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
718 .addReg(MachineFramePtr, RegState::Kill)
719 .setMIFlag(MachineInstr::FrameSetup);
722 // Mark the place where EBP/RBP was saved.
723 // Define the current CFA rule to use the provided offset.
725 BuildCFI(MBB, MBBI, DL,
726 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
728 // Change the rule for the FramePtr to be an "offset" rule.
729 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
730 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
731 nullptr, DwarfFramePtr, 2 * stackGrowth));
735 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
737 .setMIFlag(MachineInstr::FrameSetup);
740 if (!IsWin64Prologue) {
741 // Update EBP with the new base value.
742 BuildMI(MBB, MBBI, DL,
743 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
746 .setMIFlag(MachineInstr::FrameSetup);
750 // Mark effective beginning of when frame pointer becomes valid.
751 // Define the current CFA to use the EBP/RBP register.
752 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
753 BuildCFI(MBB, MBBI, DL,
754 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
757 // Mark the FramePtr as live-in in every block.
758 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
759 I->addLiveIn(MachineFramePtr);
761 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
764 // Skip the callee-saved push instructions.
765 bool PushedRegs = false;
766 int StackOffset = 2 * stackGrowth;
768 while (MBBI != MBB.end() &&
769 MBBI->getFlag(MachineInstr::FrameSetup) &&
770 (MBBI->getOpcode() == X86::PUSH32r ||
771 MBBI->getOpcode() == X86::PUSH64r)) {
773 unsigned Reg = MBBI->getOperand(0).getReg();
776 if (!HasFP && NeedsDwarfCFI) {
777 // Mark callee-saved push instruction.
778 // Define the current CFA rule to use the provided offset.
780 BuildCFI(MBB, MBBI, DL,
781 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
782 StackOffset += stackGrowth;
786 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
787 MachineInstr::FrameSetup);
791 // Realign stack after we pushed callee-saved registers (so that we'll be
792 // able to calculate their offsets from the frame pointer).
793 // Don't do this for Win64, it needs to realign the stack after the prologue.
794 if (!IsWin64Prologue && TRI->needsStackRealignment(MF)) {
795 assert(HasFP && "There should be a frame pointer if stack is realigned.");
796 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
799 // If there is an SUB32ri of ESP immediately before this instruction, merge
800 // the two. This can be the case when tail call elimination is enabled and
801 // the callee has more arguments then the caller.
802 NumBytes -= mergeSPUpdates(MBB, MBBI, true);
804 // Adjust stack pointer: ESP -= numbytes.
806 // Windows and cygwin/mingw require a prologue helper routine when allocating
807 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
808 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
809 // stack and adjust the stack pointer in one go. The 64-bit version of
810 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
811 // responsible for adjusting the stack pointer. Touching the stack at 4K
812 // increments is necessary to ensure that the guard pages used by the OS
813 // virtual memory manager are allocated in correct sequence.
814 uint64_t AlignedNumBytes = NumBytes;
815 if (IsWin64Prologue && TRI->needsStackRealignment(MF))
816 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
817 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
818 // Check whether EAX is livein for this function.
819 bool isEAXAlive = isEAXLiveIn(MF);
822 // Sanity check that EAX is not livein for this function.
823 // It should not be, so throw an assert.
824 assert(!Is64Bit && "EAX is livein in x64 case!");
827 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
828 .addReg(X86::EAX, RegState::Kill)
829 .setMIFlag(MachineInstr::FrameSetup);
833 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
834 // Function prologue is responsible for adjusting the stack pointer.
835 if (isUInt<32>(NumBytes)) {
836 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
838 .setMIFlag(MachineInstr::FrameSetup);
839 } else if (isInt<32>(NumBytes)) {
840 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
842 .setMIFlag(MachineInstr::FrameSetup);
844 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
846 .setMIFlag(MachineInstr::FrameSetup);
849 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
850 // We'll also use 4 already allocated bytes for EAX.
851 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
852 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
853 .setMIFlag(MachineInstr::FrameSetup);
856 // Save a pointer to the MI where we set AX.
857 MachineBasicBlock::iterator SetRAX = MBBI;
860 // Call __chkstk, __chkstk_ms, or __alloca.
861 emitStackProbeCall(MF, MBB, MBBI, DL);
863 // Apply the frame setup flag to all inserted instrs.
864 for (; SetRAX != MBBI; ++SetRAX)
865 SetRAX->setFlag(MachineInstr::FrameSetup);
869 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
871 StackPtr, false, NumBytes - 4);
872 MI->setFlag(MachineInstr::FrameSetup);
873 MBB.insert(MBBI, MI);
875 } else if (NumBytes) {
876 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
879 if (NeedsWinCFI && NumBytes)
880 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
882 .setMIFlag(MachineInstr::FrameSetup);
884 int SEHFrameOffset = 0;
885 if (IsWin64Prologue && HasFP) {
886 SEHFrameOffset = calculateSetFPREG(NumBytes);
888 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
889 StackPtr, false, SEHFrameOffset);
891 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr).addReg(StackPtr);
894 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
896 .addImm(SEHFrameOffset)
897 .setMIFlag(MachineInstr::FrameSetup);
900 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
901 const MachineInstr *FrameInstr = &*MBBI;
906 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
907 if (X86::FR64RegClass.contains(Reg)) {
908 int Offset = getFrameIndexOffset(MF, FI);
909 Offset += SEHFrameOffset;
911 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
914 .setMIFlag(MachineInstr::FrameSetup);
921 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
922 .setMIFlag(MachineInstr::FrameSetup);
924 // Realign stack after we spilled callee-saved registers (so that we'll be
925 // able to calculate their offsets from the frame pointer).
926 // Win64 requires aligning the stack after the prologue.
927 if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
928 assert(HasFP && "There should be a frame pointer if stack is realigned.");
929 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
932 // If we need a base pointer, set it up here. It's whatever the value
933 // of the stack pointer is at this point. Any variable size objects
934 // will be allocated after this, so we can still use the base pointer
935 // to reference locals.
936 if (TRI->hasBasePointer(MF)) {
937 // Update the base pointer with the current stack pointer.
938 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
939 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
941 .setMIFlag(MachineInstr::FrameSetup);
942 if (X86FI->getRestoreBasePointer()) {
943 // Stash value of base pointer. Saving RSP instead of EBP shortens
944 // dependence chain. Used by SjLj EH.
945 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
946 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
947 FramePtr, true, X86FI->getRestoreBasePointerOffset())
949 .setMIFlag(MachineInstr::FrameSetup);
952 if (X86FI->getHasSEHFramePtrSave()) {
953 // Stash the value of the frame pointer relative to the base pointer for
954 // Win32 EH. This supports Win32 EH, which does the inverse of the above:
955 // it recovers the frame pointer from the base pointer rather than the
957 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
958 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), BasePtr, true,
959 getFrameIndexOffset(MF, X86FI->getSEHFramePtrSaveIndex()))
961 .setMIFlag(MachineInstr::FrameSetup);
965 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
966 // Mark end of stack pointer adjustment.
967 if (!HasFP && NumBytes) {
968 // Define the current CFA rule to use the provided offset.
970 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
971 nullptr, -StackSize + stackGrowth));
974 // Emit DWARF info specifying the offsets of the callee-saved registers.
976 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
980 bool X86FrameLowering::canUseLEAForSPInEpilogue(
981 const MachineFunction &MF) const {
982 // We can't use LEA instructions for adjusting the stack pointer if this is a
983 // leaf function in the Win64 ABI. Only ADD instructions may be used to
984 // deallocate the stack.
985 // This means that we can use LEA for SP in two situations:
986 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
987 // 2. We *have* a frame pointer which means we are permitted to use LEA.
988 return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
991 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
992 MachineBasicBlock &MBB) const {
993 const MachineFrameInfo *MFI = MF.getFrameInfo();
994 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
995 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
997 if (MBBI != MBB.end())
998 DL = MBBI->getDebugLoc();
999 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1000 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1001 unsigned FramePtr = TRI->getFrameRegister(MF);
1002 unsigned MachineFramePtr =
1003 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1006 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1008 IsWin64Prologue && MF.getFunction()->needsUnwindTableEntry();
1010 // Get the number of bytes to allocate from the FrameInfo.
1011 uint64_t StackSize = MFI->getStackSize();
1012 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1013 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1014 uint64_t NumBytes = 0;
1017 // Calculate required stack adjustment.
1018 uint64_t FrameSize = StackSize - SlotSize;
1019 NumBytes = FrameSize - CSSize;
1021 // Callee-saved registers were pushed on stack before the stack was
1023 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1024 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1027 BuildMI(MBB, MBBI, DL,
1028 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
1030 NumBytes = StackSize - CSSize;
1032 uint64_t SEHStackAllocAmt = NumBytes;
1034 // Skip the callee-saved pop instructions.
1035 while (MBBI != MBB.begin()) {
1036 MachineBasicBlock::iterator PI = std::prev(MBBI);
1037 unsigned Opc = PI->getOpcode();
1039 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1040 !PI->isTerminator())
1045 MachineBasicBlock::iterator FirstCSPop = MBBI;
1047 if (MBBI != MBB.end())
1048 DL = MBBI->getDebugLoc();
1050 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1051 // instruction, merge the two instructions.
1052 if (NumBytes || MFI->hasVarSizedObjects())
1053 NumBytes += mergeSPUpdates(MBB, MBBI, true);
1055 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1056 // slot before popping them off! Same applies for the case, when stack was
1058 if (TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1059 if (TRI->needsStackRealignment(MF))
1061 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1062 uint64_t LEAAmount =
1063 IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1065 // There are only two legal forms of epilogue:
1066 // - add SEHAllocationSize, %rsp
1067 // - lea SEHAllocationSize(%FramePtr), %rsp
1069 // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1070 // However, we may use this sequence if we have a frame pointer because the
1071 // effects of the prologue can safely be undone.
1072 if (LEAAmount != 0) {
1073 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1074 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1075 FramePtr, false, LEAAmount);
1078 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1079 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1083 } else if (NumBytes) {
1084 // Adjust stack pointer back: ESP += numbytes.
1085 emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
1089 // Windows unwinder will not invoke function's exception handler if IP is
1090 // either in prologue or in epilogue. This behavior causes a problem when a
1091 // call immediately precedes an epilogue, because the return address points
1092 // into the epilogue. To cope with that, we insert an epilogue marker here,
1093 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1094 // final emitted code.
1096 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1098 // Add the return addr area delta back since we are not tail calling.
1099 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1100 assert(Offset >= 0 && "TCDelta should never be positive");
1102 MBBI = MBB.getFirstTerminator();
1104 // Check for possible merge with preceding ADD instruction.
1105 Offset += mergeSPUpdates(MBB, MBBI, true);
1106 emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
1110 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1112 const MachineFrameInfo *MFI = MF.getFrameInfo();
1113 // Offset will hold the offset from the stack pointer at function entry to the
1115 // We need to factor in additional offsets applied during the prologue to the
1116 // frame, base, and stack pointer depending on which is used.
1117 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1118 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1119 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1120 uint64_t StackSize = MFI->getStackSize();
1121 bool HasFP = hasFP(MF);
1122 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1123 int64_t FPDelta = 0;
1125 if (IsWin64Prologue) {
1126 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1128 // Calculate required stack adjustment.
1129 uint64_t FrameSize = StackSize - SlotSize;
1130 // If required, include space for extra hidden slot for stashing base pointer.
1131 if (X86FI->getRestoreBasePointer())
1132 FrameSize += SlotSize;
1133 uint64_t NumBytes = FrameSize - CSSize;
1135 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1136 if (FI && FI == X86FI->getFAIndex())
1137 return -SEHFrameOffset;
1139 // FPDelta is the offset from the "traditional" FP location of the old base
1140 // pointer followed by return address and the location required by the
1141 // restricted Win64 prologue.
1142 // Add FPDelta to all offsets below that go through the frame pointer.
1143 FPDelta = FrameSize - SEHFrameOffset;
1144 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1145 "FPDelta isn't aligned per the Win64 ABI!");
1149 if (TRI->hasBasePointer(MF)) {
1150 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1152 // Skip the saved EBP.
1153 return Offset + SlotSize + FPDelta;
1155 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1156 return Offset + StackSize;
1158 } else if (TRI->needsStackRealignment(MF)) {
1160 // Skip the saved EBP.
1161 return Offset + SlotSize + FPDelta;
1163 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1164 return Offset + StackSize;
1166 // FIXME: Support tail calls
1169 return Offset + StackSize;
1171 // Skip the saved EBP.
1174 // Skip the RETADDR move area
1175 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1176 if (TailCallReturnAddrDelta < 0)
1177 Offset -= TailCallReturnAddrDelta;
1180 return Offset + FPDelta;
1183 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1184 unsigned &FrameReg) const {
1185 // We can't calculate offset from frame pointer if the stack is realigned,
1186 // so enforce usage of stack/base pointer. The base pointer is used when we
1187 // have dynamic allocas in addition to dynamic realignment.
1188 if (TRI->hasBasePointer(MF))
1189 FrameReg = TRI->getBaseRegister();
1190 else if (TRI->needsStackRealignment(MF))
1191 FrameReg = TRI->getStackRegister();
1193 FrameReg = TRI->getFrameRegister(MF);
1194 return getFrameIndexOffset(MF, FI);
1197 // Simplified from getFrameIndexOffset keeping only StackPointer cases
1198 int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const {
1199 const MachineFrameInfo *MFI = MF.getFrameInfo();
1200 // Does not include any dynamic realign.
1201 const uint64_t StackSize = MFI->getStackSize();
1204 // Note: LLVM arranges the stack as:
1205 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1206 // > "Stack Slots" (<--SP)
1207 // We can always address StackSlots from RSP. We can usually (unless
1208 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1209 // address them from RBP. FixedObjects can be placed anywhere in the stack
1210 // frame depending on their specific requirements (i.e. we can actually
1211 // refer to arguments to the function which are stored in the *callers*
1212 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1213 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1215 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1217 // We don't handle tail calls, and shouldn't be seeing them
1219 int TailCallReturnAddrDelta =
1220 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1221 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1225 // This is how the math works out:
1227 // %rsp grows (i.e. gets lower) left to right. Each box below is
1228 // one word (eight bytes). Obj0 is the stack slot we're trying to
1231 // ----------------------------------
1232 // | BP | Obj0 | Obj1 | ... | ObjN |
1233 // ----------------------------------
1237 // A is the incoming stack pointer.
1238 // (B - A) is the local area offset (-8 for x86-64) [1]
1239 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1241 // |(E - B)| is the StackSize (absolute value, positive). For a
1242 // stack that grown down, this works out to be (B - E). [3]
1244 // E is also the value of %rsp after stack has been set up, and we
1245 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1246 // (C - E) == (C - A) - (B - A) + (B - E)
1247 // { Using [1], [2] and [3] above }
1248 // == getObjectOffset - LocalAreaOffset + StackSize
1251 // Get the Offset from the StackPointer
1252 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1254 return Offset + StackSize;
1256 // Simplified from getFrameIndexReference keeping only StackPointer cases
1257 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1259 unsigned &FrameReg) const {
1260 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1262 FrameReg = TRI->getStackRegister();
1263 return getFrameIndexOffsetFromSP(MF, FI);
1266 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1267 MachineFunction &MF, const TargetRegisterInfo *TRI,
1268 std::vector<CalleeSavedInfo> &CSI) const {
1269 MachineFrameInfo *MFI = MF.getFrameInfo();
1270 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1272 unsigned CalleeSavedFrameSize = 0;
1273 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1276 // emitPrologue always spills frame register the first thing.
1277 SpillSlotOffset -= SlotSize;
1278 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1280 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1281 // the frame register, we can delete it from CSI list and not have to worry
1282 // about avoiding it later.
1283 unsigned FPReg = TRI->getFrameRegister(MF);
1284 for (unsigned i = 0; i < CSI.size(); ++i) {
1285 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1286 CSI.erase(CSI.begin() + i);
1292 // Assign slots for GPRs. It increases frame size.
1293 for (unsigned i = CSI.size(); i != 0; --i) {
1294 unsigned Reg = CSI[i - 1].getReg();
1296 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1299 SpillSlotOffset -= SlotSize;
1300 CalleeSavedFrameSize += SlotSize;
1302 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1303 CSI[i - 1].setFrameIdx(SlotIndex);
1306 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1308 // Assign slots for XMMs.
1309 for (unsigned i = CSI.size(); i != 0; --i) {
1310 unsigned Reg = CSI[i - 1].getReg();
1311 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1314 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1316 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1318 SpillSlotOffset -= RC->getSize();
1320 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1321 CSI[i - 1].setFrameIdx(SlotIndex);
1322 MFI->ensureMaxAlignment(RC->getAlignment());
1328 bool X86FrameLowering::spillCalleeSavedRegisters(
1329 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1330 const std::vector<CalleeSavedInfo> &CSI,
1331 const TargetRegisterInfo *TRI) const {
1332 DebugLoc DL = MBB.findDebugLoc(MI);
1334 // Push GPRs. It increases frame size.
1335 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1336 for (unsigned i = CSI.size(); i != 0; --i) {
1337 unsigned Reg = CSI[i - 1].getReg();
1339 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1341 // Add the callee-saved register as live-in. It's killed at the spill.
1344 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1345 .setMIFlag(MachineInstr::FrameSetup);
1348 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1349 // It can be done by spilling XMMs to stack frame.
1350 for (unsigned i = CSI.size(); i != 0; --i) {
1351 unsigned Reg = CSI[i-1].getReg();
1352 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1354 // Add the callee-saved register as live-in. It's killed at the spill.
1356 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1358 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1361 MI->setFlag(MachineInstr::FrameSetup);
1368 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1369 MachineBasicBlock::iterator MI,
1370 const std::vector<CalleeSavedInfo> &CSI,
1371 const TargetRegisterInfo *TRI) const {
1375 DebugLoc DL = MBB.findDebugLoc(MI);
1377 // Reload XMMs from stack frame.
1378 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1379 unsigned Reg = CSI[i].getReg();
1380 if (X86::GR64RegClass.contains(Reg) ||
1381 X86::GR32RegClass.contains(Reg))
1384 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1385 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1389 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1390 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1391 unsigned Reg = CSI[i].getReg();
1392 if (!X86::GR64RegClass.contains(Reg) &&
1393 !X86::GR32RegClass.contains(Reg))
1396 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1401 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1402 BitVector &SavedRegs,
1403 RegScavenger *RS) const {
1404 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1406 MachineFrameInfo *MFI = MF.getFrameInfo();
1408 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1409 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1411 if (TailCallReturnAddrDelta < 0) {
1412 // create RETURNADDR area
1421 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1422 TailCallReturnAddrDelta - SlotSize, true);
1425 // Spill the BasePtr if it's used.
1426 if (TRI->hasBasePointer(MF))
1427 SavedRegs.set(TRI->getBaseRegister());
1431 HasNestArgument(const MachineFunction *MF) {
1432 const Function *F = MF->getFunction();
1433 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1435 if (I->hasNestAttr())
1441 /// GetScratchRegister - Get a temp register for performing work in the
1442 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1443 /// and the properties of the function either one or two registers will be
1444 /// needed. Set primary to true for the first register, false for the second.
1446 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1447 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1450 if (CallingConvention == CallingConv::HiPE) {
1452 return Primary ? X86::R14 : X86::R13;
1454 return Primary ? X86::EBX : X86::EDI;
1459 return Primary ? X86::R11 : X86::R12;
1461 return Primary ? X86::R11D : X86::R12D;
1464 bool IsNested = HasNestArgument(&MF);
1466 if (CallingConvention == CallingConv::X86_FastCall ||
1467 CallingConvention == CallingConv::Fast) {
1469 report_fatal_error("Segmented stacks does not support fastcall with "
1470 "nested function.");
1471 return Primary ? X86::EAX : X86::ECX;
1474 return Primary ? X86::EDX : X86::EAX;
1475 return Primary ? X86::ECX : X86::EAX;
1478 // The stack limit in the TCB is set to this many bytes above the actual stack
1480 static const uint64_t kSplitStackAvailable = 256;
1482 void X86FrameLowering::adjustForSegmentedStacks(
1483 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1484 MachineFrameInfo *MFI = MF.getFrameInfo();
1486 unsigned TlsReg, TlsOffset;
1489 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1490 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1491 "Scratch register is live-in");
1493 if (MF.getFunction()->isVarArg())
1494 report_fatal_error("Segmented stacks do not support vararg functions.");
1495 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1496 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1497 !STI.isTargetDragonFly())
1498 report_fatal_error("Segmented stacks not supported on this platform.");
1500 // Eventually StackSize will be calculated by a link-time pass; which will
1501 // also decide whether checking code needs to be injected into this particular
1503 StackSize = MFI->getStackSize();
1505 // Do not generate a prologue for functions with a stack of size zero
1509 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1510 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1511 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1512 bool IsNested = false;
1514 // We need to know if the function has a nest argument only in 64 bit mode.
1516 IsNested = HasNestArgument(&MF);
1518 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1519 // allocMBB needs to be last (terminating) instruction.
1521 for (MachineBasicBlock::livein_iterator i = PrologueMBB.livein_begin(),
1522 e = PrologueMBB.livein_end();
1524 allocMBB->addLiveIn(*i);
1525 checkMBB->addLiveIn(*i);
1529 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1531 MF.push_front(allocMBB);
1532 MF.push_front(checkMBB);
1534 // When the frame size is less than 256 we just compare the stack
1535 // boundary directly to the value of the stack pointer, per gcc.
1536 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1538 // Read the limit off the current stacklet off the stack_guard location.
1540 if (STI.isTargetLinux()) {
1542 TlsOffset = IsLP64 ? 0x70 : 0x40;
1543 } else if (STI.isTargetDarwin()) {
1545 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1546 } else if (STI.isTargetWin64()) {
1548 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1549 } else if (STI.isTargetFreeBSD()) {
1552 } else if (STI.isTargetDragonFly()) {
1554 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1556 report_fatal_error("Segmented stacks not supported on this platform.");
1559 if (CompareStackPointer)
1560 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1562 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1563 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1565 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1566 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1568 if (STI.isTargetLinux()) {
1571 } else if (STI.isTargetDarwin()) {
1573 TlsOffset = 0x48 + 90*4;
1574 } else if (STI.isTargetWin32()) {
1576 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1577 } else if (STI.isTargetDragonFly()) {
1579 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1580 } else if (STI.isTargetFreeBSD()) {
1581 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1583 report_fatal_error("Segmented stacks not supported on this platform.");
1586 if (CompareStackPointer)
1587 ScratchReg = X86::ESP;
1589 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1590 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1592 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1593 STI.isTargetDragonFly()) {
1594 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1595 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1596 } else if (STI.isTargetDarwin()) {
1598 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1599 unsigned ScratchReg2;
1601 if (CompareStackPointer) {
1602 // The primary scratch register is available for holding the TLS offset.
1603 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1604 SaveScratch2 = false;
1606 // Need to use a second register to hold the TLS offset
1607 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1609 // Unfortunately, with fastcc the second scratch register may hold an
1611 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1614 // If Scratch2 is live-in then it needs to be saved.
1615 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1616 "Scratch register is live-in and not saved");
1619 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1620 .addReg(ScratchReg2, RegState::Kill);
1622 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1624 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1626 .addReg(ScratchReg2).addImm(1).addReg(0)
1631 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1635 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1636 // It jumps to normal execution of the function body.
1637 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
1639 // On 32 bit we first push the arguments size and then the frame size. On 64
1640 // bit, we pass the stack frame size in r10 and the argument size in r11.
1642 // Functions with nested arguments use R10, so it needs to be saved across
1643 // the call to _morestack
1645 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1646 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1647 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1648 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1649 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1652 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1654 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1656 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1657 .addImm(X86FI->getArgumentStackSize());
1659 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1660 .addImm(X86FI->getArgumentStackSize());
1661 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1665 // __morestack is in libgcc
1666 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1667 // Under the large code model, we cannot assume that __morestack lives
1668 // within 2^31 bytes of the call site, so we cannot use pc-relative
1669 // addressing. We cannot perform the call via a temporary register,
1670 // as the rax register may be used to store the static chain, and all
1671 // other suitable registers may be either callee-save or used for
1672 // parameter passing. We cannot use the stack at this point either
1673 // because __morestack manipulates the stack directly.
1675 // To avoid these issues, perform an indirect call via a read-only memory
1676 // location containing the address.
1678 // This solution is not perfect, as it assumes that the .rodata section
1679 // is laid out within 2^31 bytes of each function body, but this seems
1680 // to be sufficient for JIT.
1681 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1685 .addExternalSymbol("__morestack_addr")
1687 MF.getMMI().setUsesMorestackAddr(true);
1690 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1691 .addExternalSymbol("__morestack");
1693 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1694 .addExternalSymbol("__morestack");
1698 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1700 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1702 allocMBB->addSuccessor(&PrologueMBB);
1704 checkMBB->addSuccessor(allocMBB);
1705 checkMBB->addSuccessor(&PrologueMBB);
1712 /// Erlang programs may need a special prologue to handle the stack size they
1713 /// might need at runtime. That is because Erlang/OTP does not implement a C
1714 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1715 /// (for more information see Eric Stenman's Ph.D. thesis:
1716 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1719 /// temp0 = sp - MaxStack
1720 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1724 /// call inc_stack # doubles the stack space
1725 /// temp0 = sp - MaxStack
1726 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1727 void X86FrameLowering::adjustForHiPEPrologue(
1728 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1729 MachineFrameInfo *MFI = MF.getFrameInfo();
1731 // HiPE-specific values
1732 const unsigned HipeLeafWords = 24;
1733 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1734 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1735 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1736 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1737 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1739 assert(STI.isTargetLinux() &&
1740 "HiPE prologue is only supported on Linux operating systems.");
1742 // Compute the largest caller's frame that is needed to fit the callees'
1743 // frames. This 'MaxStack' is computed from:
1745 // a) the fixed frame size, which is the space needed for all spilled temps,
1746 // b) outgoing on-stack parameter areas, and
1747 // c) the minimum stack space this function needs to make available for the
1748 // functions it calls (a tunable ABI property).
1749 if (MFI->hasCalls()) {
1750 unsigned MoreStackForCalls = 0;
1752 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1753 MBBI != MBBE; ++MBBI)
1754 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1759 // Get callee operand.
1760 const MachineOperand &MO = MI->getOperand(0);
1762 // Only take account of global function calls (no closures etc.).
1766 const Function *F = dyn_cast<Function>(MO.getGlobal());
1770 // Do not update 'MaxStack' for primitive and built-in functions
1771 // (encoded with names either starting with "erlang."/"bif_" or not
1772 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1773 // "_", such as the BIF "suspend_0") as they are executed on another
1775 if (F->getName().find("erlang.") != StringRef::npos ||
1776 F->getName().find("bif_") != StringRef::npos ||
1777 F->getName().find_first_of("._") == StringRef::npos)
1780 unsigned CalleeStkArity =
1781 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1782 if (HipeLeafWords - 1 > CalleeStkArity)
1783 MoreStackForCalls = std::max(MoreStackForCalls,
1784 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1786 MaxStack += MoreStackForCalls;
1789 // If the stack frame needed is larger than the guaranteed then runtime checks
1790 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1791 if (MaxStack > Guaranteed) {
1792 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1793 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1795 for (MachineBasicBlock::livein_iterator I = PrologueMBB.livein_begin(),
1796 E = PrologueMBB.livein_end();
1798 stackCheckMBB->addLiveIn(*I);
1799 incStackMBB->addLiveIn(*I);
1802 MF.push_front(incStackMBB);
1803 MF.push_front(stackCheckMBB);
1805 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1806 unsigned LEAop, CMPop, CALLop;
1810 LEAop = X86::LEA64r;
1811 CMPop = X86::CMP64rm;
1812 CALLop = X86::CALL64pcrel32;
1813 SPLimitOffset = 0x90;
1817 LEAop = X86::LEA32r;
1818 CMPop = X86::CMP32rm;
1819 CALLop = X86::CALLpcrel32;
1820 SPLimitOffset = 0x4c;
1823 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1824 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1825 "HiPE prologue scratch register is live-in");
1827 // Create new MBB for StackCheck:
1828 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1829 SPReg, false, -MaxStack);
1830 // SPLimitOffset is in a fixed heap location (pointed by BP).
1831 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1832 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1833 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
1835 // Create new MBB for IncStack:
1836 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1837 addExternalSymbol("inc_stack_0");
1838 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1839 SPReg, false, -MaxStack);
1840 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1841 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1842 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1844 stackCheckMBB->addSuccessor(&PrologueMBB, 99);
1845 stackCheckMBB->addSuccessor(incStackMBB, 1);
1846 incStackMBB->addSuccessor(&PrologueMBB, 99);
1847 incStackMBB->addSuccessor(incStackMBB, 1);
1854 void X86FrameLowering::
1855 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1856 MachineBasicBlock::iterator I) const {
1857 bool reserveCallFrame = hasReservedCallFrame(MF);
1858 unsigned Opcode = I->getOpcode();
1859 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1860 DebugLoc DL = I->getDebugLoc();
1861 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
1862 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
1865 if (!reserveCallFrame) {
1866 // If the stack pointer can be changed after prologue, turn the
1867 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1868 // adjcallstackdown instruction into 'add ESP, <amt>'
1872 // We need to keep the stack aligned properly. To do this, we round the
1873 // amount of space needed for the outgoing arguments up to the next
1874 // alignment boundary.
1875 unsigned StackAlign = getStackAlignment();
1876 Amount = RoundUpToAlignment(Amount, StackAlign);
1878 // Factor out the amount that gets handled inside the sequence
1879 // (Pushes of argument for frame setup, callee pops for frame destroy)
1880 Amount -= InternalAmt;
1883 // Add Amount to SP to destroy a frame, and subtract to setup.
1884 int Offset = isDestroy ? Amount : -Amount;
1885 BuildStackAdjustment(MBB, I, DL, Offset, /*InEpilogue=*/false);
1890 if (isDestroy && InternalAmt) {
1891 // If we are performing frame pointer elimination and if the callee pops
1892 // something off the stack pointer, add it back. We do this until we have
1893 // more advanced stack pointer tracking ability.
1894 // We are not tracking the stack pointer adjustment by the callee, so make
1895 // sure we restore the stack pointer immediately after the call, there may
1896 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1897 MachineBasicBlock::iterator B = MBB.begin();
1898 while (I != B && !std::prev(I)->isCall())
1900 BuildStackAdjustment(MBB, I, DL, -InternalAmt, /*InEpilogue=*/false);
1904 bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
1905 assert(MBB.getParent() && "Block is not attached to a function!");
1907 if (canUseLEAForSPInEpilogue(*MBB.getParent()))
1910 // If we cannot use LEA to adjust SP, we may need to use ADD, which
1911 // clobbers the EFLAGS. Check that none of the terminators reads the
1912 // EFLAGS, and if one uses it, conservatively assume this is not
1913 // safe to insert the epilogue here.
1914 return !terminatorsNeedFlagsAsInput(MBB);