1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
36 // FIXME: completely move here.
37 extern cl::opt<bool> ForceStackAlign;
39 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
40 return !MF.getFrameInfo()->hasVarSizedObjects();
43 /// hasFP - Return true if the specified function should have a dedicated frame
44 /// pointer register. This is true if the function has variable sized allocas
45 /// or if frame pointer elimination is disabled.
46 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
47 const MachineFrameInfo *MFI = MF.getFrameInfo();
48 const MachineModuleInfo &MMI = MF.getMMI();
49 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
51 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
52 RegInfo->needsStackRealignment(MF) ||
53 MFI->hasVarSizedObjects() ||
54 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
55 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
56 MMI.callsUnwindInit() || MMI.callsEHReturn() ||
57 MFI->hasStackMap() || MFI->hasPatchPoint());
60 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
64 return X86::SUB64ri32;
72 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
76 return X86::ADD64ri32;
84 static unsigned getLEArOpcode(unsigned IsLP64) {
85 return IsLP64 ? X86::LEA64r : X86::LEA32r;
88 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
89 /// when it reaches the "return" instruction. We can then pop a stack object
90 /// to this register without worry about clobbering it.
91 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
92 MachineBasicBlock::iterator &MBBI,
93 const TargetRegisterInfo &TRI,
95 const MachineFunction *MF = MBB.getParent();
96 const Function *F = MF->getFunction();
97 if (!F || MF->getMMI().callsEHReturn())
100 static const uint16_t CallerSavedRegs32Bit[] = {
101 X86::EAX, X86::EDX, X86::ECX, 0
104 static const uint16_t CallerSavedRegs64Bit[] = {
105 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
106 X86::R8, X86::R9, X86::R10, X86::R11, 0
109 unsigned Opc = MBBI->getOpcode();
116 case X86::TCRETURNdi:
117 case X86::TCRETURNri:
118 case X86::TCRETURNmi:
119 case X86::TCRETURNdi64:
120 case X86::TCRETURNri64:
121 case X86::TCRETURNmi64:
123 case X86::EH_RETURN64: {
124 SmallSet<uint16_t, 8> Uses;
125 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
126 MachineOperand &MO = MBBI->getOperand(i);
127 if (!MO.isReg() || MO.isDef())
129 unsigned Reg = MO.getReg();
132 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
136 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
138 if (!Uses.count(*CS))
147 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
148 /// stack pointer by a constant value.
150 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
151 unsigned StackPtr, int64_t NumBytes,
152 bool Is64BitTarget, bool Is64BitStackPtr, bool UseLEA,
153 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
154 bool isSub = NumBytes < 0;
155 uint64_t Offset = isSub ? -NumBytes : NumBytes;
158 Opc = getLEArOpcode(Is64BitStackPtr);
161 ? getSUBriOpcode(Is64BitStackPtr, Offset)
162 : getADDriOpcode(Is64BitStackPtr, Offset);
164 uint64_t Chunk = (1LL << 31) - 1;
165 DebugLoc DL = MBB.findDebugLoc(MBBI);
168 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
169 if (ThisVal == (Is64BitTarget ? 8 : 4)) {
170 // Use push / pop instead.
172 ? (unsigned)(Is64BitTarget ? X86::RAX : X86::EAX)
173 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64BitTarget);
176 ? (Is64BitTarget ? X86::PUSH64r : X86::PUSH32r)
177 : (Is64BitTarget ? X86::POP64r : X86::POP32r);
178 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
179 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
181 MI->setFlag(MachineInstr::FrameSetup);
187 MachineInstr *MI = nullptr;
190 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
191 StackPtr, false, isSub ? -ThisVal : ThisVal);
193 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
196 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
200 MI->setFlag(MachineInstr::FrameSetup);
206 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
208 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
209 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
210 if (MBBI == MBB.begin()) return;
212 MachineBasicBlock::iterator PI = std::prev(MBBI);
213 unsigned Opc = PI->getOpcode();
214 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
215 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
216 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
217 PI->getOperand(0).getReg() == StackPtr) {
219 *NumBytes += PI->getOperand(2).getImm();
221 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
222 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
223 PI->getOperand(0).getReg() == StackPtr) {
225 *NumBytes -= PI->getOperand(2).getImm();
230 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower
233 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
234 MachineBasicBlock::iterator &MBBI,
235 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
236 // FIXME: THIS ISN'T RUN!!!
239 if (MBBI == MBB.end()) return;
241 MachineBasicBlock::iterator NI = std::next(MBBI);
242 if (NI == MBB.end()) return;
244 unsigned Opc = NI->getOpcode();
245 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
246 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
247 NI->getOperand(0).getReg() == StackPtr) {
249 *NumBytes -= NI->getOperand(2).getImm();
252 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
253 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
254 NI->getOperand(0).getReg() == StackPtr) {
256 *NumBytes += NI->getOperand(2).getImm();
262 /// mergeSPUpdates - Checks the instruction before/after the passed
263 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
264 /// the stack adjustment is returned as a positive value for ADD/LEA and a
265 /// negative for SUB.
266 static int mergeSPUpdates(MachineBasicBlock &MBB,
267 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
268 bool doMergeWithPrevious) {
269 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
270 (!doMergeWithPrevious && MBBI == MBB.end()))
273 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
274 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
276 unsigned Opc = PI->getOpcode();
279 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
280 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
281 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
282 PI->getOperand(0).getReg() == StackPtr){
283 Offset += PI->getOperand(2).getImm();
285 if (!doMergeWithPrevious) MBBI = NI;
286 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
287 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
288 PI->getOperand(0).getReg() == StackPtr) {
289 Offset -= PI->getOperand(2).getImm();
291 if (!doMergeWithPrevious) MBBI = NI;
297 static bool isEAXLiveIn(MachineFunction &MF) {
298 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
299 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
300 unsigned Reg = II->first;
302 if (Reg == X86::EAX || Reg == X86::AX ||
303 Reg == X86::AH || Reg == X86::AL)
311 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
312 MachineBasicBlock::iterator MBBI,
314 MachineFunction &MF = *MBB.getParent();
315 MachineFrameInfo *MFI = MF.getFrameInfo();
316 MachineModuleInfo &MMI = MF.getMMI();
317 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
318 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
320 // Add callee saved registers to move list.
321 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
322 if (CSI.empty()) return;
324 // Calculate offsets.
325 for (std::vector<CalleeSavedInfo>::const_iterator
326 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
327 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
328 unsigned Reg = I->getReg();
330 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
332 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
334 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
335 .addCFIIndex(CFIIndex);
339 /// usesTheStack - This function checks if any of the users of EFLAGS
340 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
341 /// to use the stack, and if we don't adjust the stack we clobber the first
343 /// See X86InstrInfo::copyPhysReg.
344 static bool usesTheStack(const MachineFunction &MF) {
345 const MachineRegisterInfo &MRI = MF.getRegInfo();
347 for (MachineRegisterInfo::reg_instr_iterator
348 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
356 void X86FrameLowering::getStackProbeFunction(const X86Subtarget &STI,
358 const char *&Symbol) {
359 CallOp = STI.is64Bit() ? X86::W64ALLOCA : X86::CALLpcrel32;
362 if (STI.isTargetCygMing()) {
363 Symbol = "___chkstk_ms";
367 } else if (STI.isTargetCygMing())
373 /// emitPrologue - Push callee-saved registers onto the stack, which
374 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
375 /// space for local variables. Also emit labels used by the exception handler to
376 /// generate the exception handling frames.
379 Here's a gist of what gets emitted:
381 ; Establish frame pointer, if needed
384 .cfi_def_cfa_offset 16
385 .cfi_offset %rbp, -16
388 .cfi_def_cfa_register %rbp
390 ; Spill general-purpose registers
391 [for all callee-saved GPRs]
394 .cfi_def_cfa_offset (offset from RETADDR)
397 ; If the required stack alignment > default stack alignment
398 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
399 ; of unknown size in the stack frame.
400 [if stack needs re-alignment]
403 ; Allocate space for locals
404 [if target is Windows and allocated space > 4096 bytes]
405 ; Windows needs special care for allocations larger
408 call ___chkstk_ms/___chkstk
414 .seh_stackalloc (size of XMM spill slots)
415 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
420 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
421 ; they may get spilled on any platform, if the current function
422 ; calls @llvm.eh.unwind.init
424 [for all callee-saved XMM registers]
425 movaps %<xmm reg>, -MMM(%rbp)
426 [for all callee-saved XMM registers]
427 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
428 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
430 [for all callee-saved XMM registers]
431 movaps %<xmm reg>, KKK(%rsp)
432 [for all callee-saved XMM registers]
433 .seh_savexmm %<xmm reg>, KKK
437 [if needs base pointer]
442 [for all callee-saved registers]
443 .cfi_offset %<reg>, (offset from %rbp)
445 .cfi_def_cfa_offset (offset from RETADDR)
446 [for all callee-saved registers]
447 .cfi_offset %<reg>, (offset from %rsp)
450 - .seh directives are emitted only for Windows 64 ABI
451 - .cfi directives are emitted for all other ABIs
452 - for 32-bit code, substitute %e?? registers for %r??
455 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
456 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
457 MachineBasicBlock::iterator MBBI = MBB.begin();
458 MachineFrameInfo *MFI = MF.getFrameInfo();
459 const Function *Fn = MF.getFunction();
460 const X86RegisterInfo *RegInfo =
461 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
462 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
463 MachineModuleInfo &MMI = MF.getMMI();
464 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
465 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
466 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
467 bool HasFP = hasFP(MF);
468 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
469 bool Is64Bit = STI.is64Bit();
470 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
471 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
472 bool IsWin64 = STI.isTargetWin64();
474 MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
475 ExceptionHandling::WinEH; // Not necessarily synonymous with IsWin64.
476 bool NeedsWinEH = IsWinEH && Fn->needsUnwindTableEntry();
478 !IsWinEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
479 bool UseLEA = STI.useLeaForSP();
480 unsigned StackAlign = getStackAlignment();
481 unsigned SlotSize = RegInfo->getSlotSize();
482 unsigned FramePtr = RegInfo->getFrameRegister(MF);
483 const unsigned MachineFramePtr = STI.isTarget64BitILP32() ?
484 getX86SubSuperRegister(FramePtr, MVT::i64, false) : FramePtr;
485 unsigned StackPtr = RegInfo->getStackRegister();
486 unsigned BasePtr = RegInfo->getBaseRegister();
489 // If we're forcing a stack realignment we can't rely on just the frame
490 // info, we need to know the ABI stack alignment as well in case we
491 // have a call out. Otherwise just make sure we have some alignment - we'll
492 // go with the minimum SlotSize.
493 if (ForceStackAlign) {
495 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
496 else if (MaxAlign < SlotSize)
500 // Add RETADDR move area to callee saved frame size.
501 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
502 if (TailCallReturnAddrDelta < 0)
503 X86FI->setCalleeSavedFrameSize(
504 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
506 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMacho());
508 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
509 // function, and use up to 128 bytes of stack space, don't have a frame
510 // pointer, calls, or dynamic alloca then we do not need to adjust the
511 // stack pointer (we fit in the Red Zone). We also check that we don't
512 // push and pop from the stack.
513 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
514 Attribute::NoRedZone) &&
515 !RegInfo->needsStackRealignment(MF) &&
516 !MFI->hasVarSizedObjects() && // No dynamic alloca.
517 !MFI->adjustsStack() && // No calls.
518 !IsWin64 && // Win64 has no Red Zone
519 !usesTheStack(MF) && // Don't push and pop.
520 !MF.shouldSplitStack()) { // Regular stack
521 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
522 if (HasFP) MinSize += SlotSize;
523 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
524 MFI->setStackSize(StackSize);
527 // Insert stack pointer adjustment for later moving of return addr. Only
528 // applies to tail call optimized functions where the callee argument stack
529 // size is bigger than the callers.
530 if (TailCallReturnAddrDelta < 0) {
532 BuildMI(MBB, MBBI, DL,
533 TII.get(getSUBriOpcode(Uses64BitFramePtr, -TailCallReturnAddrDelta)),
536 .addImm(-TailCallReturnAddrDelta)
537 .setMIFlag(MachineInstr::FrameSetup);
538 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
541 // Mapping for machine moves:
543 // DST: VirtualFP AND
544 // SRC: VirtualFP => DW_CFA_def_cfa_offset
545 // ELSE => DW_CFA_def_cfa
547 // SRC: VirtualFP AND
548 // DST: Register => DW_CFA_def_cfa_register
551 // OFFSET < 0 => DW_CFA_offset_extended_sf
552 // REG < 64 => DW_CFA_offset + Reg
553 // ELSE => DW_CFA_offset_extended
555 uint64_t NumBytes = 0;
556 int stackGrowth = -SlotSize;
559 // Calculate required stack adjustment.
560 uint64_t FrameSize = StackSize - SlotSize;
561 if (RegInfo->needsStackRealignment(MF)) {
562 // Callee-saved registers are pushed on stack before the stack
564 FrameSize -= X86FI->getCalleeSavedFrameSize();
565 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
567 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
570 // Get the offset of the stack slot for the EBP register, which is
571 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
572 // Update the frame offset adjustment.
573 MFI->setOffsetAdjustment(-NumBytes);
575 // Save EBP/RBP into the appropriate stack slot.
576 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
577 .addReg(MachineFramePtr, RegState::Kill)
578 .setMIFlag(MachineInstr::FrameSetup);
581 // Mark the place where EBP/RBP was saved.
582 // Define the current CFA rule to use the provided offset.
584 unsigned CFIIndex = MMI.addFrameInst(
585 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
586 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
587 .addCFIIndex(CFIIndex);
589 // Change the rule for the FramePtr to be an "offset" rule.
590 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
591 CFIIndex = MMI.addFrameInst(
592 MCCFIInstruction::createOffset(nullptr,
593 DwarfFramePtr, 2 * stackGrowth));
594 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
595 .addCFIIndex(CFIIndex);
599 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
601 .setMIFlag(MachineInstr::FrameSetup);
604 // Update EBP with the new base value.
605 BuildMI(MBB, MBBI, DL,
606 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr), FramePtr)
608 .setMIFlag(MachineInstr::FrameSetup);
611 // Mark effective beginning of when frame pointer becomes valid.
612 // Define the current CFA to use the EBP/RBP register.
613 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
614 unsigned CFIIndex = MMI.addFrameInst(
615 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
616 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
617 .addCFIIndex(CFIIndex);
620 // Mark the FramePtr as live-in in every block.
621 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
622 I->addLiveIn(MachineFramePtr);
624 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
627 // Skip the callee-saved push instructions.
628 bool PushedRegs = false;
629 int StackOffset = 2 * stackGrowth;
631 while (MBBI != MBB.end() &&
632 (MBBI->getOpcode() == X86::PUSH32r ||
633 MBBI->getOpcode() == X86::PUSH64r)) {
635 unsigned Reg = MBBI->getOperand(0).getReg();
638 if (!HasFP && NeedsDwarfCFI) {
639 // Mark callee-saved push instruction.
640 // Define the current CFA rule to use the provided offset.
642 unsigned CFIIndex = MMI.addFrameInst(
643 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
644 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
645 .addCFIIndex(CFIIndex);
646 StackOffset += stackGrowth;
650 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
651 MachineInstr::FrameSetup);
655 // Realign stack after we pushed callee-saved registers (so that we'll be
656 // able to calculate their offsets from the frame pointer).
657 if (RegInfo->needsStackRealignment(MF)) {
658 assert(HasFP && "There should be a frame pointer if stack is realigned.");
660 BuildMI(MBB, MBBI, DL,
661 TII.get(Uses64BitFramePtr ? X86::AND64ri32 : X86::AND32ri), StackPtr)
664 .setMIFlag(MachineInstr::FrameSetup);
666 // The EFLAGS implicit def is dead.
667 MI->getOperand(3).setIsDead();
670 // If there is an SUB32ri of ESP immediately before this instruction, merge
671 // the two. This can be the case when tail call elimination is enabled and
672 // the callee has more arguments then the caller.
673 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
675 // If there is an ADD32ri or SUB32ri of ESP immediately after this
676 // instruction, merge the two instructions.
677 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
679 // Adjust stack pointer: ESP -= numbytes.
681 static const size_t PageSize = 4096;
683 // Windows and cygwin/mingw require a prologue helper routine when allocating
684 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
685 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
686 // stack and adjust the stack pointer in one go. The 64-bit version of
687 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
688 // responsible for adjusting the stack pointer. Touching the stack at 4K
689 // increments is necessary to ensure that the guard pages used by the OS
690 // virtual memory manager are allocated in correct sequence.
691 if (NumBytes >= PageSize && UseStackProbe) {
692 const char *StackProbeSymbol;
695 getStackProbeFunction(STI, CallOp, StackProbeSymbol);
697 // Check whether EAX is livein for this function.
698 bool isEAXAlive = isEAXLiveIn(MF);
701 // Sanity check that EAX is not livein for this function.
702 // It should not be, so throw an assert.
703 assert(!Is64Bit && "EAX is livein in x64 case!");
706 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
707 .addReg(X86::EAX, RegState::Kill)
708 .setMIFlag(MachineInstr::FrameSetup);
712 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
713 // Function prologue is responsible for adjusting the stack pointer.
714 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
716 .setMIFlag(MachineInstr::FrameSetup);
718 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
719 // We'll also use 4 already allocated bytes for EAX.
720 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
721 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
722 .setMIFlag(MachineInstr::FrameSetup);
725 BuildMI(MBB, MBBI, DL,
727 .addExternalSymbol(StackProbeSymbol)
728 .addReg(StackPtr, RegState::Define | RegState::Implicit)
729 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
730 .setMIFlag(MachineInstr::FrameSetup);
733 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
734 // themself. It also does not clobber %rax so we can reuse it when
736 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), StackPtr)
739 .setMIFlag(MachineInstr::FrameSetup);
743 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
745 StackPtr, false, NumBytes - 4);
746 MI->setFlag(MachineInstr::FrameSetup);
747 MBB.insert(MBBI, MI);
749 } else if (NumBytes) {
750 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, Uses64BitFramePtr,
751 UseLEA, TII, *RegInfo);
754 int SEHFrameOffset = 0;
757 // We need to set frame base offset low enough such that all saved
758 // register offsets would be positive relative to it, but we can't
759 // just use NumBytes, because .seh_setframe offset must be <=240.
760 // So we pretend to have only allocated enough space to spill the
761 // non-volatile registers.
762 // We don't care about the rest of stack allocation, because unwinder
763 // will restore SP to (BP - SEHFrameOffset)
764 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
765 int offset = MFI->getObjectOffset(Info.getFrameIdx());
766 SEHFrameOffset = std::max(SEHFrameOffset, abs(offset));
768 SEHFrameOffset += SEHFrameOffset % 16; // ensure alignmant
770 // This only needs to account for XMM spill slots, GPR slots
771 // are covered by the .seh_pushreg's emitted above.
772 unsigned Size = SEHFrameOffset - X86FI->getCalleeSavedFrameSize();
774 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
776 .setMIFlag(MachineInstr::FrameSetup);
779 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
781 .addImm(SEHFrameOffset)
782 .setMIFlag(MachineInstr::FrameSetup);
784 // SP will be the base register for restoring XMMs
786 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
788 .setMIFlag(MachineInstr::FrameSetup);
793 // Skip the rest of register spilling code
794 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
797 // Emit SEH info for non-GPRs
799 for (const CalleeSavedInfo &Info : MFI->getCalleeSavedInfo()) {
800 unsigned Reg = Info.getReg();
801 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
803 assert(X86::FR64RegClass.contains(Reg) && "Unexpected register class");
805 int Offset = getFrameIndexOffset(MF, Info.getFrameIdx());
806 Offset += SEHFrameOffset;
808 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
811 .setMIFlag(MachineInstr::FrameSetup);
814 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
815 .setMIFlag(MachineInstr::FrameSetup);
818 // If we need a base pointer, set it up here. It's whatever the value
819 // of the stack pointer is at this point. Any variable size objects
820 // will be allocated after this, so we can still use the base pointer
821 // to reference locals.
822 if (RegInfo->hasBasePointer(MF)) {
823 // Update the base pointer with the current stack pointer.
824 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
825 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
827 .setMIFlag(MachineInstr::FrameSetup);
830 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
831 // Mark end of stack pointer adjustment.
832 if (!HasFP && NumBytes) {
833 // Define the current CFA rule to use the provided offset.
835 unsigned CFIIndex = MMI.addFrameInst(
836 MCCFIInstruction::createDefCfaOffset(nullptr,
837 -StackSize + stackGrowth));
839 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
840 .addCFIIndex(CFIIndex);
843 // Emit DWARF info specifying the offsets of the callee-saved registers.
845 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
849 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
850 MachineBasicBlock &MBB) const {
851 const MachineFrameInfo *MFI = MF.getFrameInfo();
852 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
853 const X86RegisterInfo *RegInfo =
854 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
855 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
856 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
857 assert(MBBI != MBB.end() && "Returning block has no instructions");
858 unsigned RetOpcode = MBBI->getOpcode();
859 DebugLoc DL = MBBI->getDebugLoc();
860 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
861 bool Is64Bit = STI.is64Bit();
862 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
863 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
864 const bool Is64BitILP32 = STI.isTarget64BitILP32();
865 bool UseLEA = STI.useLeaForSP();
866 unsigned StackAlign = getStackAlignment();
867 unsigned SlotSize = RegInfo->getSlotSize();
868 unsigned FramePtr = RegInfo->getFrameRegister(MF);
869 unsigned MachineFramePtr = Is64BitILP32 ?
870 getX86SubSuperRegister(FramePtr, MVT::i64, false) : FramePtr;
871 unsigned StackPtr = RegInfo->getStackRegister();
874 MF.getTarget().getMCAsmInfo()->getExceptionHandlingType() ==
875 ExceptionHandling::WinEH;
876 bool NeedsWinEH = IsWinEH && MF.getFunction()->needsUnwindTableEntry();
880 llvm_unreachable("Can only insert epilog into returning blocks");
885 case X86::TCRETURNdi:
886 case X86::TCRETURNri:
887 case X86::TCRETURNmi:
888 case X86::TCRETURNdi64:
889 case X86::TCRETURNri64:
890 case X86::TCRETURNmi64:
892 case X86::EH_RETURN64:
893 break; // These are ok
896 // Get the number of bytes to allocate from the FrameInfo.
897 uint64_t StackSize = MFI->getStackSize();
898 uint64_t MaxAlign = MFI->getMaxAlignment();
899 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
900 uint64_t NumBytes = 0;
902 // If we're forcing a stack realignment we can't rely on just the frame
903 // info, we need to know the ABI stack alignment as well in case we
904 // have a call out. Otherwise just make sure we have some alignment - we'll
905 // go with the minimum.
906 if (ForceStackAlign) {
908 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
910 MaxAlign = MaxAlign ? MaxAlign : 4;
914 // Calculate required stack adjustment.
915 uint64_t FrameSize = StackSize - SlotSize;
916 if (RegInfo->needsStackRealignment(MF)) {
917 // Callee-saved registers were pushed on stack before the stack
920 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
922 NumBytes = FrameSize - CSSize;
926 BuildMI(MBB, MBBI, DL,
927 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
929 NumBytes = StackSize - CSSize;
932 // Skip the callee-saved pop instructions.
933 while (MBBI != MBB.begin()) {
934 MachineBasicBlock::iterator PI = std::prev(MBBI);
935 unsigned Opc = PI->getOpcode();
937 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
943 MachineBasicBlock::iterator FirstCSPop = MBBI;
945 DL = MBBI->getDebugLoc();
947 // If there is an ADD32ri or SUB32ri of ESP immediately before this
948 // instruction, merge the two instructions.
949 if (NumBytes || MFI->hasVarSizedObjects())
950 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
952 // If dynamic alloca is used, then reset esp to point to the last callee-saved
953 // slot before popping them off! Same applies for the case, when stack was
955 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
956 if (RegInfo->needsStackRealignment(MF))
959 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
960 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
961 FramePtr, false, -CSSize);
964 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
965 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
969 } else if (NumBytes) {
970 // Adjust stack pointer back: ESP += numbytes.
971 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, Uses64BitFramePtr, UseLEA,
976 // Windows unwinder will not invoke function's exception handler if IP is
977 // either in prologue or in epilogue. This behavior causes a problem when a
978 // call immediately precedes an epilogue, because the return address points
979 // into the epilogue. To cope with that, we insert an epilogue marker here,
980 // then replace it with a 'nop' if it ends up immediately after a CALL in the
981 // final emitted code.
983 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
985 // We're returning from function via eh_return.
986 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
987 MBBI = MBB.getLastNonDebugInstr();
988 MachineOperand &DestAddr = MBBI->getOperand(0);
989 assert(DestAddr.isReg() && "Offset should be in register!");
990 BuildMI(MBB, MBBI, DL,
991 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
992 StackPtr).addReg(DestAddr.getReg());
993 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
994 RetOpcode == X86::TCRETURNmi ||
995 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
996 RetOpcode == X86::TCRETURNmi64) {
997 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
998 // Tail call return: adjust the stack pointer and jump to callee.
999 MBBI = MBB.getLastNonDebugInstr();
1000 MachineOperand &JumpTarget = MBBI->getOperand(0);
1001 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1002 assert(StackAdjust.isImm() && "Expecting immediate value.");
1004 // Adjust stack pointer.
1005 int StackAdj = StackAdjust.getImm();
1006 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1008 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1010 // Incoporate the retaddr area.
1011 Offset = StackAdj-MaxTCDelta;
1012 assert(Offset >= 0 && "Offset should never be negative");
1015 // Check for possible merge with preceding ADD instruction.
1016 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1017 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, Uses64BitFramePtr,
1018 UseLEA, TII, *RegInfo);
1021 // Jump to label or value in register.
1022 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1023 MachineInstrBuilder MIB =
1024 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1025 ? X86::TAILJMPd : X86::TAILJMPd64));
1026 if (JumpTarget.isGlobal())
1027 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1028 JumpTarget.getTargetFlags());
1030 assert(JumpTarget.isSymbol());
1031 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1032 JumpTarget.getTargetFlags());
1034 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1035 MachineInstrBuilder MIB =
1036 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1037 ? X86::TAILJMPm : X86::TAILJMPm64));
1038 for (unsigned i = 0; i != 5; ++i)
1039 MIB.addOperand(MBBI->getOperand(i));
1040 } else if (RetOpcode == X86::TCRETURNri64) {
1041 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1042 addReg(JumpTarget.getReg(), RegState::Kill);
1044 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1045 addReg(JumpTarget.getReg(), RegState::Kill);
1048 MachineInstr *NewMI = std::prev(MBBI);
1049 NewMI->copyImplicitOps(MF, MBBI);
1051 // Delete the pseudo instruction TCRETURN.
1053 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
1054 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
1055 (X86FI->getTCReturnAddrDelta() < 0)) {
1056 // Add the return addr area delta back since we are not tail calling.
1057 int delta = -1*X86FI->getTCReturnAddrDelta();
1058 MBBI = MBB.getLastNonDebugInstr();
1060 // Check for possible merge with preceding ADD instruction.
1061 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1062 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, Uses64BitFramePtr, UseLEA, TII,
1067 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1069 const X86RegisterInfo *RegInfo =
1070 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1071 const MachineFrameInfo *MFI = MF.getFrameInfo();
1072 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1073 uint64_t StackSize = MFI->getStackSize();
1075 if (RegInfo->hasBasePointer(MF)) {
1076 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1078 // Skip the saved EBP.
1079 return Offset + RegInfo->getSlotSize();
1081 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1082 return Offset + StackSize;
1084 } else if (RegInfo->needsStackRealignment(MF)) {
1086 // Skip the saved EBP.
1087 return Offset + RegInfo->getSlotSize();
1089 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1090 return Offset + StackSize;
1092 // FIXME: Support tail calls
1095 return Offset + StackSize;
1097 // Skip the saved EBP.
1098 Offset += RegInfo->getSlotSize();
1100 // Skip the RETADDR move area
1101 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1102 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1103 if (TailCallReturnAddrDelta < 0)
1104 Offset -= TailCallReturnAddrDelta;
1110 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1111 unsigned &FrameReg) const {
1112 const X86RegisterInfo *RegInfo =
1113 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1114 // We can't calculate offset from frame pointer if the stack is realigned,
1115 // so enforce usage of stack/base pointer. The base pointer is used when we
1116 // have dynamic allocas in addition to dynamic realignment.
1117 if (RegInfo->hasBasePointer(MF))
1118 FrameReg = RegInfo->getBaseRegister();
1119 else if (RegInfo->needsStackRealignment(MF))
1120 FrameReg = RegInfo->getStackRegister();
1122 FrameReg = RegInfo->getFrameRegister(MF);
1123 return getFrameIndexOffset(MF, FI);
1126 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1127 MachineFunction &MF, const TargetRegisterInfo *TRI,
1128 std::vector<CalleeSavedInfo> &CSI) const {
1129 MachineFrameInfo *MFI = MF.getFrameInfo();
1130 const X86RegisterInfo *RegInfo =
1131 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1132 unsigned SlotSize = RegInfo->getSlotSize();
1133 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1135 unsigned CalleeSavedFrameSize = 0;
1136 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1139 // emitPrologue always spills frame register the first thing.
1140 SpillSlotOffset -= SlotSize;
1141 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1143 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1144 // the frame register, we can delete it from CSI list and not have to worry
1145 // about avoiding it later.
1146 unsigned FPReg = RegInfo->getFrameRegister(MF);
1147 for (unsigned i = 0; i < CSI.size(); ++i) {
1148 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1149 CSI.erase(CSI.begin() + i);
1155 // Assign slots for GPRs. It increases frame size.
1156 for (unsigned i = CSI.size(); i != 0; --i) {
1157 unsigned Reg = CSI[i - 1].getReg();
1159 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1162 SpillSlotOffset -= SlotSize;
1163 CalleeSavedFrameSize += SlotSize;
1165 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1166 CSI[i - 1].setFrameIdx(SlotIndex);
1169 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1171 // Assign slots for XMMs.
1172 for (unsigned i = CSI.size(); i != 0; --i) {
1173 unsigned Reg = CSI[i - 1].getReg();
1174 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1177 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1179 SpillSlotOffset -= abs(SpillSlotOffset) % RC->getAlignment();
1181 SpillSlotOffset -= RC->getSize();
1183 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1184 CSI[i - 1].setFrameIdx(SlotIndex);
1185 MFI->ensureMaxAlignment(RC->getAlignment());
1191 bool X86FrameLowering::spillCalleeSavedRegisters(
1192 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1193 const std::vector<CalleeSavedInfo> &CSI,
1194 const TargetRegisterInfo *TRI) const {
1195 DebugLoc DL = MBB.findDebugLoc(MI);
1197 MachineFunction &MF = *MBB.getParent();
1198 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1199 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1201 // Push GPRs. It increases frame size.
1202 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1203 for (unsigned i = CSI.size(); i != 0; --i) {
1204 unsigned Reg = CSI[i - 1].getReg();
1206 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1208 // Add the callee-saved register as live-in. It's killed at the spill.
1211 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1212 .setMIFlag(MachineInstr::FrameSetup);
1215 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1216 // It can be done by spilling XMMs to stack frame.
1217 for (unsigned i = CSI.size(); i != 0; --i) {
1218 unsigned Reg = CSI[i-1].getReg();
1219 if (X86::GR64RegClass.contains(Reg) ||
1220 X86::GR32RegClass.contains(Reg))
1222 // Add the callee-saved register as live-in. It's killed at the spill.
1224 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1226 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1229 MI->setFlag(MachineInstr::FrameSetup);
1236 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1237 MachineBasicBlock::iterator MI,
1238 const std::vector<CalleeSavedInfo> &CSI,
1239 const TargetRegisterInfo *TRI) const {
1243 DebugLoc DL = MBB.findDebugLoc(MI);
1245 MachineFunction &MF = *MBB.getParent();
1246 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1247 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1249 // Reload XMMs from stack frame.
1250 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1251 unsigned Reg = CSI[i].getReg();
1252 if (X86::GR64RegClass.contains(Reg) ||
1253 X86::GR32RegClass.contains(Reg))
1256 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1257 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1261 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1262 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1263 unsigned Reg = CSI[i].getReg();
1264 if (!X86::GR64RegClass.contains(Reg) &&
1265 !X86::GR32RegClass.contains(Reg))
1268 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1274 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1275 RegScavenger *RS) const {
1276 MachineFrameInfo *MFI = MF.getFrameInfo();
1277 const X86RegisterInfo *RegInfo =
1278 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo());
1279 unsigned SlotSize = RegInfo->getSlotSize();
1281 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1282 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1284 if (TailCallReturnAddrDelta < 0) {
1285 // create RETURNADDR area
1294 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1295 TailCallReturnAddrDelta - SlotSize, true);
1298 // Spill the BasePtr if it's used.
1299 if (RegInfo->hasBasePointer(MF))
1300 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1304 HasNestArgument(const MachineFunction *MF) {
1305 const Function *F = MF->getFunction();
1306 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1308 if (I->hasNestAttr())
1314 /// GetScratchRegister - Get a temp register for performing work in the
1315 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1316 /// and the properties of the function either one or two registers will be
1317 /// needed. Set primary to true for the first register, false for the second.
1319 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1320 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1323 if (CallingConvention == CallingConv::HiPE) {
1325 return Primary ? X86::R14 : X86::R13;
1327 return Primary ? X86::EBX : X86::EDI;
1332 return Primary ? X86::R11 : X86::R12;
1334 return Primary ? X86::R11D : X86::R12D;
1337 bool IsNested = HasNestArgument(&MF);
1339 if (CallingConvention == CallingConv::X86_FastCall ||
1340 CallingConvention == CallingConv::Fast) {
1342 report_fatal_error("Segmented stacks does not support fastcall with "
1343 "nested function.");
1344 return Primary ? X86::EAX : X86::ECX;
1347 return Primary ? X86::EDX : X86::EAX;
1348 return Primary ? X86::ECX : X86::EAX;
1351 // The stack limit in the TCB is set to this many bytes above the actual stack
1353 static const uint64_t kSplitStackAvailable = 256;
1356 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1357 MachineBasicBlock &prologueMBB = MF.front();
1358 MachineFrameInfo *MFI = MF.getFrameInfo();
1359 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1361 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1362 bool Is64Bit = STI.is64Bit();
1363 const bool IsLP64 = STI.isTarget64BitLP64();
1364 unsigned TlsReg, TlsOffset;
1367 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1368 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1369 "Scratch register is live-in");
1371 if (MF.getFunction()->isVarArg())
1372 report_fatal_error("Segmented stacks do not support vararg functions.");
1373 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1374 !STI.isTargetWin32() && !STI.isTargetWin64() && !STI.isTargetFreeBSD())
1375 report_fatal_error("Segmented stacks not supported on this platform.");
1377 // Eventually StackSize will be calculated by a link-time pass; which will
1378 // also decide whether checking code needs to be injected into this particular
1380 StackSize = MFI->getStackSize();
1382 // Do not generate a prologue for functions with a stack of size zero
1386 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1387 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1388 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1389 bool IsNested = false;
1391 // We need to know if the function has a nest argument only in 64 bit mode.
1393 IsNested = HasNestArgument(&MF);
1395 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1396 // allocMBB needs to be last (terminating) instruction.
1398 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1399 e = prologueMBB.livein_end(); i != e; i++) {
1400 allocMBB->addLiveIn(*i);
1401 checkMBB->addLiveIn(*i);
1405 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1407 MF.push_front(allocMBB);
1408 MF.push_front(checkMBB);
1410 // When the frame size is less than 256 we just compare the stack
1411 // boundary directly to the value of the stack pointer, per gcc.
1412 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1414 // Read the limit off the current stacklet off the stack_guard location.
1416 if (STI.isTargetLinux()) {
1418 TlsOffset = IsLP64 ? 0x70 : 0x40;
1419 } else if (STI.isTargetDarwin()) {
1421 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1422 } else if (STI.isTargetWin64()) {
1424 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1425 } else if (STI.isTargetFreeBSD()) {
1429 report_fatal_error("Segmented stacks not supported on this platform.");
1432 if (CompareStackPointer)
1433 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1435 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1436 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1438 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1439 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1441 if (STI.isTargetLinux()) {
1444 } else if (STI.isTargetDarwin()) {
1446 TlsOffset = 0x48 + 90*4;
1447 } else if (STI.isTargetWin32()) {
1449 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1450 } else if (STI.isTargetFreeBSD()) {
1451 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1453 report_fatal_error("Segmented stacks not supported on this platform.");
1456 if (CompareStackPointer)
1457 ScratchReg = X86::ESP;
1459 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1460 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1462 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64()) {
1463 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1464 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1465 } else if (STI.isTargetDarwin()) {
1467 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1468 unsigned ScratchReg2;
1470 if (CompareStackPointer) {
1471 // The primary scratch register is available for holding the TLS offset.
1472 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1473 SaveScratch2 = false;
1475 // Need to use a second register to hold the TLS offset
1476 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1478 // Unfortunately, with fastcc the second scratch register may hold an
1480 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1483 // If Scratch2 is live-in then it needs to be saved.
1484 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1485 "Scratch register is live-in and not saved");
1488 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1489 .addReg(ScratchReg2, RegState::Kill);
1491 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1493 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1495 .addReg(ScratchReg2).addImm(1).addReg(0)
1500 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1504 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1505 // It jumps to normal execution of the function body.
1506 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1508 // On 32 bit we first push the arguments size and then the frame size. On 64
1509 // bit, we pass the stack frame size in r10 and the argument size in r11.
1511 // Functions with nested arguments use R10, so it needs to be saved across
1512 // the call to _morestack
1514 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1515 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1516 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1517 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1518 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1521 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1523 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1525 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1526 .addImm(X86FI->getArgumentStackSize());
1527 MF.getRegInfo().setPhysRegUsed(Reg10);
1528 MF.getRegInfo().setPhysRegUsed(Reg11);
1530 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1531 .addImm(X86FI->getArgumentStackSize());
1532 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1536 // __morestack is in libgcc
1538 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1539 .addExternalSymbol("__morestack");
1541 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1542 .addExternalSymbol("__morestack");
1545 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1547 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1549 allocMBB->addSuccessor(&prologueMBB);
1551 checkMBB->addSuccessor(allocMBB);
1552 checkMBB->addSuccessor(&prologueMBB);
1559 /// Erlang programs may need a special prologue to handle the stack size they
1560 /// might need at runtime. That is because Erlang/OTP does not implement a C
1561 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1562 /// (for more information see Eric Stenman's Ph.D. thesis:
1563 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1566 /// temp0 = sp - MaxStack
1567 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1571 /// call inc_stack # doubles the stack space
1572 /// temp0 = sp - MaxStack
1573 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1574 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1575 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1576 MachineFrameInfo *MFI = MF.getFrameInfo();
1577 const unsigned SlotSize =
1578 static_cast<const X86RegisterInfo *>(MF.getSubtarget().getRegisterInfo())
1580 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1581 const bool Is64Bit = STI.is64Bit();
1582 const bool IsLP64 = STI.isTarget64BitLP64();
1584 // HiPE-specific values
1585 const unsigned HipeLeafWords = 24;
1586 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1587 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1588 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1589 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1590 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1592 assert(STI.isTargetLinux() &&
1593 "HiPE prologue is only supported on Linux operating systems.");
1595 // Compute the largest caller's frame that is needed to fit the callees'
1596 // frames. This 'MaxStack' is computed from:
1598 // a) the fixed frame size, which is the space needed for all spilled temps,
1599 // b) outgoing on-stack parameter areas, and
1600 // c) the minimum stack space this function needs to make available for the
1601 // functions it calls (a tunable ABI property).
1602 if (MFI->hasCalls()) {
1603 unsigned MoreStackForCalls = 0;
1605 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1606 MBBI != MBBE; ++MBBI)
1607 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1612 // Get callee operand.
1613 const MachineOperand &MO = MI->getOperand(0);
1615 // Only take account of global function calls (no closures etc.).
1619 const Function *F = dyn_cast<Function>(MO.getGlobal());
1623 // Do not update 'MaxStack' for primitive and built-in functions
1624 // (encoded with names either starting with "erlang."/"bif_" or not
1625 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1626 // "_", such as the BIF "suspend_0") as they are executed on another
1628 if (F->getName().find("erlang.") != StringRef::npos ||
1629 F->getName().find("bif_") != StringRef::npos ||
1630 F->getName().find_first_of("._") == StringRef::npos)
1633 unsigned CalleeStkArity =
1634 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1635 if (HipeLeafWords - 1 > CalleeStkArity)
1636 MoreStackForCalls = std::max(MoreStackForCalls,
1637 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1639 MaxStack += MoreStackForCalls;
1642 // If the stack frame needed is larger than the guaranteed then runtime checks
1643 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1644 if (MaxStack > Guaranteed) {
1645 MachineBasicBlock &prologueMBB = MF.front();
1646 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1647 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1649 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1650 E = prologueMBB.livein_end(); I != E; I++) {
1651 stackCheckMBB->addLiveIn(*I);
1652 incStackMBB->addLiveIn(*I);
1655 MF.push_front(incStackMBB);
1656 MF.push_front(stackCheckMBB);
1658 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1659 unsigned LEAop, CMPop, CALLop;
1663 LEAop = X86::LEA64r;
1664 CMPop = X86::CMP64rm;
1665 CALLop = X86::CALL64pcrel32;
1666 SPLimitOffset = 0x90;
1670 LEAop = X86::LEA32r;
1671 CMPop = X86::CMP32rm;
1672 CALLop = X86::CALLpcrel32;
1673 SPLimitOffset = 0x4c;
1676 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1677 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1678 "HiPE prologue scratch register is live-in");
1680 // Create new MBB for StackCheck:
1681 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1682 SPReg, false, -MaxStack);
1683 // SPLimitOffset is in a fixed heap location (pointed by BP).
1684 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1685 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1686 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1688 // Create new MBB for IncStack:
1689 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1690 addExternalSymbol("inc_stack_0");
1691 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1692 SPReg, false, -MaxStack);
1693 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1694 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1695 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1697 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1698 stackCheckMBB->addSuccessor(incStackMBB, 1);
1699 incStackMBB->addSuccessor(&prologueMBB, 99);
1700 incStackMBB->addSuccessor(incStackMBB, 1);
1707 void X86FrameLowering::
1708 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1709 MachineBasicBlock::iterator I) const {
1710 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
1711 const X86RegisterInfo &RegInfo = *static_cast<const X86RegisterInfo *>(
1712 MF.getSubtarget().getRegisterInfo());
1713 unsigned StackPtr = RegInfo.getStackRegister();
1714 bool reseveCallFrame = hasReservedCallFrame(MF);
1715 int Opcode = I->getOpcode();
1716 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1717 const X86Subtarget &STI = MF.getTarget().getSubtarget<X86Subtarget>();
1718 bool IsLP64 = STI.isTarget64BitLP64();
1719 DebugLoc DL = I->getDebugLoc();
1720 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1721 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1724 if (!reseveCallFrame) {
1725 // If the stack pointer can be changed after prologue, turn the
1726 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1727 // adjcallstackdown instruction into 'add ESP, <amt>'
1728 // TODO: consider using push / pop instead of sub + store / add
1732 // We need to keep the stack aligned properly. To do this, we round the
1733 // amount of space needed for the outgoing arguments up to the next
1734 // alignment boundary.
1735 unsigned StackAlign = MF.getTarget()
1737 ->getFrameLowering()
1738 ->getStackAlignment();
1739 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1741 MachineInstr *New = nullptr;
1742 if (Opcode == TII.getCallFrameSetupOpcode()) {
1743 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1748 assert(Opcode == TII.getCallFrameDestroyOpcode());
1750 // Factor out the amount the callee already popped.
1751 Amount -= CalleeAmt;
1754 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1755 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1756 .addReg(StackPtr).addImm(Amount);
1761 // The EFLAGS implicit def is dead.
1762 New->getOperand(3).setIsDead();
1764 // Replace the pseudo instruction with a new instruction.
1771 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1772 // If we are performing frame pointer elimination and if the callee pops
1773 // something off the stack pointer, add it back. We do this until we have
1774 // more advanced stack pointer tracking ability.
1775 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1776 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1777 .addReg(StackPtr).addImm(CalleeAmt);
1779 // The EFLAGS implicit def is dead.
1780 New->getOperand(3).setIsDead();
1782 // We are not tracking the stack pointer adjustment by the callee, so make
1783 // sure we restore the stack pointer immediately after the call, there may
1784 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1785 MachineBasicBlock::iterator B = MBB.begin();
1786 while (I != B && !std::prev(I)->isCall())