1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
37 // FIXME: completely move here.
38 extern cl::opt<bool> ForceStackAlign;
40 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
41 return !MF.getFrameInfo()->hasVarSizedObjects() &&
42 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
45 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
46 /// call frame pseudos can be simplified. Having a FP, as in the default
47 /// implementation, is not sufficient here since we can't always use it.
48 /// Use a more nuanced condition.
50 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
51 const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>
52 (MF.getSubtarget().getRegisterInfo());
53 return hasReservedCallFrame(MF) ||
54 (hasFP(MF) && !TRI->needsStackRealignment(MF))
55 || TRI->hasBasePointer(MF);
58 // needsFrameIndexResolution - Do we need to perform FI resolution for
59 // this function. Normally, this is required only when the function
60 // has any stack objects. However, FI resolution actually has another job,
61 // not apparent from the title - it resolves callframesetup/destroy
62 // that were not simplified earlier.
63 // So, this is required for x86 functions that have push sequences even
64 // when there are no stack objects.
66 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
67 return MF.getFrameInfo()->hasStackObjects() ||
68 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
71 /// hasFP - Return true if the specified function should have a dedicated frame
72 /// pointer register. This is true if the function has variable sized allocas
73 /// or if frame pointer elimination is disabled.
74 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
75 const MachineFrameInfo *MFI = MF.getFrameInfo();
76 const MachineModuleInfo &MMI = MF.getMMI();
77 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
79 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
80 RegInfo->needsStackRealignment(MF) ||
81 MFI->hasVarSizedObjects() ||
82 MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||
83 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
84 MMI.callsUnwindInit() || MMI.callsEHReturn() ||
85 MFI->hasStackMap() || MFI->hasPatchPoint());
88 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
92 return X86::SUB64ri32;
100 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
103 return X86::ADD64ri8;
104 return X86::ADD64ri32;
107 return X86::ADD32ri8;
112 static unsigned getSUBrrOpcode(unsigned isLP64) {
113 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
116 static unsigned getADDrrOpcode(unsigned isLP64) {
117 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
120 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
123 return X86::AND64ri8;
124 return X86::AND64ri32;
127 return X86::AND32ri8;
131 static unsigned getLEArOpcode(unsigned IsLP64) {
132 return IsLP64 ? X86::LEA64r : X86::LEA32r;
135 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
136 /// when it reaches the "return" instruction. We can then pop a stack object
137 /// to this register without worry about clobbering it.
138 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
139 MachineBasicBlock::iterator &MBBI,
140 const TargetRegisterInfo &TRI,
142 const MachineFunction *MF = MBB.getParent();
143 const Function *F = MF->getFunction();
144 if (!F || MF->getMMI().callsEHReturn())
147 static const uint16_t CallerSavedRegs32Bit[] = {
148 X86::EAX, X86::EDX, X86::ECX, 0
151 static const uint16_t CallerSavedRegs64Bit[] = {
152 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
153 X86::R8, X86::R9, X86::R10, X86::R11, 0
156 unsigned Opc = MBBI->getOpcode();
163 case X86::TCRETURNdi:
164 case X86::TCRETURNri:
165 case X86::TCRETURNmi:
166 case X86::TCRETURNdi64:
167 case X86::TCRETURNri64:
168 case X86::TCRETURNmi64:
170 case X86::EH_RETURN64: {
171 SmallSet<uint16_t, 8> Uses;
172 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
173 MachineOperand &MO = MBBI->getOperand(i);
174 if (!MO.isReg() || MO.isDef())
176 unsigned Reg = MO.getReg();
179 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
183 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
185 if (!Uses.count(*CS))
193 static bool isEAXLiveIn(MachineFunction &MF) {
194 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
195 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
196 unsigned Reg = II->first;
198 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
199 Reg == X86::AH || Reg == X86::AL)
206 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
207 /// stack pointer by a constant value.
209 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
210 unsigned StackPtr, int64_t NumBytes,
211 bool Is64BitTarget, bool Is64BitStackPtr, bool UseLEA,
212 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
213 bool isSub = NumBytes < 0;
214 uint64_t Offset = isSub ? -NumBytes : NumBytes;
217 Opc = getLEArOpcode(Is64BitStackPtr);
220 ? getSUBriOpcode(Is64BitStackPtr, Offset)
221 : getADDriOpcode(Is64BitStackPtr, Offset);
223 uint64_t Chunk = (1LL << 31) - 1;
224 DebugLoc DL = MBB.findDebugLoc(MBBI);
227 if (Offset > Chunk) {
228 // Rather than emit a long series of instructions for large offsets,
229 // load the offset into a register and do one sub/add
232 if (isSub && !isEAXLiveIn(*MBB.getParent()))
233 Reg = (unsigned)(Is64BitTarget ? X86::RAX : X86::EAX);
235 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64BitTarget);
238 Opc = Is64BitTarget ? X86::MOV64ri : X86::MOV32ri;
239 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
242 ? getSUBrrOpcode(Is64BitTarget)
243 : getADDrrOpcode(Is64BitTarget);
244 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
247 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
253 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
254 if (ThisVal == (Is64BitTarget ? 8 : 4)) {
255 // Use push / pop instead.
257 ? (unsigned)(Is64BitTarget ? X86::RAX : X86::EAX)
258 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64BitTarget);
261 ? (Is64BitTarget ? X86::PUSH64r : X86::PUSH32r)
262 : (Is64BitTarget ? X86::POP64r : X86::POP32r);
263 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
264 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
266 MI->setFlag(MachineInstr::FrameSetup);
272 MachineInstr *MI = nullptr;
275 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
276 StackPtr, false, isSub ? -ThisVal : ThisVal);
278 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
281 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
285 MI->setFlag(MachineInstr::FrameSetup);
291 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
293 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
294 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
295 if (MBBI == MBB.begin()) return;
297 MachineBasicBlock::iterator PI = std::prev(MBBI);
298 unsigned Opc = PI->getOpcode();
299 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
300 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
301 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
302 PI->getOperand(0).getReg() == StackPtr) {
304 *NumBytes += PI->getOperand(2).getImm();
306 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
307 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
308 PI->getOperand(0).getReg() == StackPtr) {
310 *NumBytes -= PI->getOperand(2).getImm();
315 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower
318 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
319 MachineBasicBlock::iterator &MBBI,
320 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
321 // FIXME: THIS ISN'T RUN!!!
324 if (MBBI == MBB.end()) return;
326 MachineBasicBlock::iterator NI = std::next(MBBI);
327 if (NI == MBB.end()) return;
329 unsigned Opc = NI->getOpcode();
330 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
331 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
332 NI->getOperand(0).getReg() == StackPtr) {
334 *NumBytes -= NI->getOperand(2).getImm();
337 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
338 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
339 NI->getOperand(0).getReg() == StackPtr) {
341 *NumBytes += NI->getOperand(2).getImm();
347 /// mergeSPUpdates - Checks the instruction before/after the passed
348 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and
349 /// the stack adjustment is returned as a positive value for ADD/LEA and a
350 /// negative for SUB.
351 static int mergeSPUpdates(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator &MBBI, unsigned StackPtr,
353 bool doMergeWithPrevious) {
354 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
355 (!doMergeWithPrevious && MBBI == MBB.end()))
358 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
359 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
361 unsigned Opc = PI->getOpcode();
364 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
365 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
366 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
367 PI->getOperand(0).getReg() == StackPtr){
368 Offset += PI->getOperand(2).getImm();
370 if (!doMergeWithPrevious) MBBI = NI;
371 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
372 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
373 PI->getOperand(0).getReg() == StackPtr) {
374 Offset -= PI->getOperand(2).getImm();
376 if (!doMergeWithPrevious) MBBI = NI;
383 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
384 MachineBasicBlock::iterator MBBI,
386 MachineFunction &MF = *MBB.getParent();
387 MachineFrameInfo *MFI = MF.getFrameInfo();
388 MachineModuleInfo &MMI = MF.getMMI();
389 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
390 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
392 // Add callee saved registers to move list.
393 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
394 if (CSI.empty()) return;
396 // Calculate offsets.
397 for (std::vector<CalleeSavedInfo>::const_iterator
398 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
399 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
400 unsigned Reg = I->getReg();
402 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
404 MMI.addFrameInst(MCCFIInstruction::createOffset(nullptr, DwarfReg,
406 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
407 .addCFIIndex(CFIIndex);
411 /// usesTheStack - This function checks if any of the users of EFLAGS
412 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
413 /// to use the stack, and if we don't adjust the stack we clobber the first
415 /// See X86InstrInfo::copyPhysReg.
416 static bool usesTheStack(const MachineFunction &MF) {
417 const MachineRegisterInfo &MRI = MF.getRegInfo();
419 for (MachineRegisterInfo::reg_instr_iterator
420 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
428 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
429 MachineBasicBlock &MBB,
430 MachineBasicBlock::iterator MBBI,
432 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
433 const TargetInstrInfo &TII = *STI.getInstrInfo();
434 bool Is64Bit = STI.is64Bit();
435 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
439 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
441 CallOp = X86::CALLpcrel32;
445 if (STI.isTargetCygMing()) {
446 Symbol = "___chkstk_ms";
450 } else if (STI.isTargetCygMing())
455 MachineInstrBuilder CI;
457 // All current stack probes take AX and SP as input, clobber flags, and
458 // preserve all registers. x86_64 probes leave RSP unmodified.
459 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
460 // For the large code model, we have to call through a register. Use R11,
461 // as it is scratch in all supported calling conventions.
462 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
463 .addExternalSymbol(Symbol);
464 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
466 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
469 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
470 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
471 CI.addReg(AX, RegState::Implicit)
472 .addReg(SP, RegState::Implicit)
473 .addReg(AX, RegState::Define | RegState::Implicit)
474 .addReg(SP, RegState::Define | RegState::Implicit)
475 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
478 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
479 // themselves. It also does not clobber %rax so we can reuse it when
481 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
487 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
488 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
489 // and might require smaller successive adjustments.
490 const uint64_t Win64MaxSEHOffset = 128;
491 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
492 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
493 return static_cast<unsigned>(RoundUpToAlignment(SEHFrameOffset, 16));
496 // If we're forcing a stack realignment we can't rely on just the frame
497 // info, we need to know the ABI stack alignment as well in case we
498 // have a call out. Otherwise just make sure we have some alignment - we'll
499 // go with the minimum SlotSize.
500 static uint64_t calculateMaxStackAlign(const MachineFunction &MF) {
501 const MachineFrameInfo *MFI = MF.getFrameInfo();
502 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
503 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
504 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
505 unsigned SlotSize = RegInfo->getSlotSize();
506 unsigned StackAlign = STI.getFrameLowering()->getStackAlignment();
507 if (ForceStackAlign) {
509 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
510 else if (MaxAlign < SlotSize)
516 /// emitPrologue - Push callee-saved registers onto the stack, which
517 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
518 /// space for local variables. Also emit labels used by the exception handler to
519 /// generate the exception handling frames.
522 Here's a gist of what gets emitted:
524 ; Establish frame pointer, if needed
527 .cfi_def_cfa_offset 16
528 .cfi_offset %rbp, -16
531 .cfi_def_cfa_register %rbp
533 ; Spill general-purpose registers
534 [for all callee-saved GPRs]
537 .cfi_def_cfa_offset (offset from RETADDR)
540 ; If the required stack alignment > default stack alignment
541 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
542 ; of unknown size in the stack frame.
543 [if stack needs re-alignment]
546 ; Allocate space for locals
547 [if target is Windows and allocated space > 4096 bytes]
548 ; Windows needs special care for allocations larger
551 call ___chkstk_ms/___chkstk
557 .seh_stackalloc (size of XMM spill slots)
558 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
563 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
564 ; they may get spilled on any platform, if the current function
565 ; calls @llvm.eh.unwind.init
567 [for all callee-saved XMM registers]
568 movaps %<xmm reg>, -MMM(%rbp)
569 [for all callee-saved XMM registers]
570 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
571 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
573 [for all callee-saved XMM registers]
574 movaps %<xmm reg>, KKK(%rsp)
575 [for all callee-saved XMM registers]
576 .seh_savexmm %<xmm reg>, KKK
580 [if needs base pointer]
582 [if needs to restore base pointer]
587 [for all callee-saved registers]
588 .cfi_offset %<reg>, (offset from %rbp)
590 .cfi_def_cfa_offset (offset from RETADDR)
591 [for all callee-saved registers]
592 .cfi_offset %<reg>, (offset from %rsp)
595 - .seh directives are emitted only for Windows 64 ABI
596 - .cfi directives are emitted for all other ABIs
597 - for 32-bit code, substitute %e?? registers for %r??
600 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
601 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
602 MachineBasicBlock::iterator MBBI = MBB.begin();
603 MachineFrameInfo *MFI = MF.getFrameInfo();
604 const Function *Fn = MF.getFunction();
605 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
606 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
607 const TargetInstrInfo &TII = *STI.getInstrInfo();
608 MachineModuleInfo &MMI = MF.getMMI();
609 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
610 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
611 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
612 bool HasFP = hasFP(MF);
613 bool Is64Bit = STI.is64Bit();
614 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
615 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
616 bool IsWin64 = STI.isTargetWin64();
617 // Not necessarily synonymous with IsWin64.
618 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
619 bool NeedsWinEH = IsWinEH && Fn->needsUnwindTableEntry();
621 !IsWinEH && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
622 bool UseLEA = STI.useLeaForSP();
623 unsigned SlotSize = RegInfo->getSlotSize();
624 unsigned FramePtr = RegInfo->getFrameRegister(MF);
625 const unsigned MachineFramePtr =
626 STI.isTarget64BitILP32()
627 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
629 unsigned StackPtr = RegInfo->getStackRegister();
630 unsigned BasePtr = RegInfo->getBaseRegister();
633 // Add RETADDR move area to callee saved frame size.
634 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
635 if (TailCallReturnAddrDelta && IsWinEH)
636 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
638 if (TailCallReturnAddrDelta < 0)
639 X86FI->setCalleeSavedFrameSize(
640 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
642 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
644 // The default stack probe size is 4096 if the function has no stackprobesize
646 unsigned StackProbeSize = 4096;
647 if (Fn->hasFnAttribute("stack-probe-size"))
648 Fn->getFnAttribute("stack-probe-size")
650 .getAsInteger(0, StackProbeSize);
652 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
653 // function, and use up to 128 bytes of stack space, don't have a frame
654 // pointer, calls, or dynamic alloca then we do not need to adjust the
655 // stack pointer (we fit in the Red Zone). We also check that we don't
656 // push and pop from the stack.
657 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
658 Attribute::NoRedZone) &&
659 !RegInfo->needsStackRealignment(MF) &&
660 !MFI->hasVarSizedObjects() && // No dynamic alloca.
661 !MFI->adjustsStack() && // No calls.
662 !IsWin64 && // Win64 has no Red Zone
663 !usesTheStack(MF) && // Don't push and pop.
664 !MF.shouldSplitStack()) { // Regular stack
665 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
666 if (HasFP) MinSize += SlotSize;
667 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
668 MFI->setStackSize(StackSize);
671 // Insert stack pointer adjustment for later moving of return addr. Only
672 // applies to tail call optimized functions where the callee argument stack
673 // size is bigger than the callers.
674 if (TailCallReturnAddrDelta < 0) {
676 BuildMI(MBB, MBBI, DL,
677 TII.get(getSUBriOpcode(Uses64BitFramePtr, -TailCallReturnAddrDelta)),
680 .addImm(-TailCallReturnAddrDelta)
681 .setMIFlag(MachineInstr::FrameSetup);
682 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
685 // Mapping for machine moves:
687 // DST: VirtualFP AND
688 // SRC: VirtualFP => DW_CFA_def_cfa_offset
689 // ELSE => DW_CFA_def_cfa
691 // SRC: VirtualFP AND
692 // DST: Register => DW_CFA_def_cfa_register
695 // OFFSET < 0 => DW_CFA_offset_extended_sf
696 // REG < 64 => DW_CFA_offset + Reg
697 // ELSE => DW_CFA_offset_extended
699 uint64_t NumBytes = 0;
700 int stackGrowth = -SlotSize;
703 // Calculate required stack adjustment.
704 uint64_t FrameSize = StackSize - SlotSize;
705 // If required, include space for extra hidden slot for stashing base pointer.
706 if (X86FI->getRestoreBasePointer())
707 FrameSize += SlotSize;
708 if (RegInfo->needsStackRealignment(MF)) {
709 // Callee-saved registers are pushed on stack before the stack
711 FrameSize -= X86FI->getCalleeSavedFrameSize();
712 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
714 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
717 // Get the offset of the stack slot for the EBP register, which is
718 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
719 // Update the frame offset adjustment.
720 MFI->setOffsetAdjustment(-NumBytes);
722 // Save EBP/RBP into the appropriate stack slot.
723 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
724 .addReg(MachineFramePtr, RegState::Kill)
725 .setMIFlag(MachineInstr::FrameSetup);
728 // Mark the place where EBP/RBP was saved.
729 // Define the current CFA rule to use the provided offset.
731 unsigned CFIIndex = MMI.addFrameInst(
732 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
733 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
734 .addCFIIndex(CFIIndex);
736 // Change the rule for the FramePtr to be an "offset" rule.
737 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
738 CFIIndex = MMI.addFrameInst(
739 MCCFIInstruction::createOffset(nullptr,
740 DwarfFramePtr, 2 * stackGrowth));
741 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
742 .addCFIIndex(CFIIndex);
746 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
748 .setMIFlag(MachineInstr::FrameSetup);
752 // Update EBP with the new base value.
753 BuildMI(MBB, MBBI, DL,
754 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
757 .setMIFlag(MachineInstr::FrameSetup);
761 // Mark effective beginning of when frame pointer becomes valid.
762 // Define the current CFA to use the EBP/RBP register.
763 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);
764 unsigned CFIIndex = MMI.addFrameInst(
765 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
766 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
767 .addCFIIndex(CFIIndex);
770 // Mark the FramePtr as live-in in every block.
771 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
772 I->addLiveIn(MachineFramePtr);
774 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
777 // Skip the callee-saved push instructions.
778 bool PushedRegs = false;
779 int StackOffset = 2 * stackGrowth;
781 while (MBBI != MBB.end() &&
782 (MBBI->getOpcode() == X86::PUSH32r ||
783 MBBI->getOpcode() == X86::PUSH64r)) {
785 unsigned Reg = MBBI->getOperand(0).getReg();
788 if (!HasFP && NeedsDwarfCFI) {
789 // Mark callee-saved push instruction.
790 // Define the current CFA rule to use the provided offset.
792 unsigned CFIIndex = MMI.addFrameInst(
793 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
794 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
795 .addCFIIndex(CFIIndex);
796 StackOffset += stackGrowth;
800 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
801 MachineInstr::FrameSetup);
805 // Realign stack after we pushed callee-saved registers (so that we'll be
806 // able to calculate their offsets from the frame pointer).
807 // Don't do this for Win64, it needs to realign the stack after the prologue.
808 if (!IsWinEH && RegInfo->needsStackRealignment(MF)) {
809 assert(HasFP && "There should be a frame pointer if stack is realigned.");
810 uint64_t Val = -MaxAlign;
812 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
816 .setMIFlag(MachineInstr::FrameSetup);
818 // The EFLAGS implicit def is dead.
819 MI->getOperand(3).setIsDead();
822 // If there is an SUB32ri of ESP immediately before this instruction, merge
823 // the two. This can be the case when tail call elimination is enabled and
824 // the callee has more arguments then the caller.
825 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
827 // If there is an ADD32ri or SUB32ri of ESP immediately after this
828 // instruction, merge the two instructions.
829 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
831 // Adjust stack pointer: ESP -= numbytes.
833 // Windows and cygwin/mingw require a prologue helper routine when allocating
834 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
835 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
836 // stack and adjust the stack pointer in one go. The 64-bit version of
837 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
838 // responsible for adjusting the stack pointer. Touching the stack at 4K
839 // increments is necessary to ensure that the guard pages used by the OS
840 // virtual memory manager are allocated in correct sequence.
841 if (NumBytes >= StackProbeSize && UseStackProbe) {
842 // Check whether EAX is livein for this function.
843 bool isEAXAlive = isEAXLiveIn(MF);
846 // Sanity check that EAX is not livein for this function.
847 // It should not be, so throw an assert.
848 assert(!Is64Bit && "EAX is livein in x64 case!");
851 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
852 .addReg(X86::EAX, RegState::Kill)
853 .setMIFlag(MachineInstr::FrameSetup);
857 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
858 // Function prologue is responsible for adjusting the stack pointer.
859 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
861 .setMIFlag(MachineInstr::FrameSetup);
863 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
864 // We'll also use 4 already allocated bytes for EAX.
865 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
866 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
867 .setMIFlag(MachineInstr::FrameSetup);
870 // Save a pointer to the MI where we set AX.
871 MachineBasicBlock::iterator SetRAX = MBBI;
874 // Call __chkstk, __chkstk_ms, or __alloca.
875 emitStackProbeCall(MF, MBB, MBBI, DL);
877 // Apply the frame setup flag to all inserted instrs.
878 for (; SetRAX != MBBI; ++SetRAX)
879 SetRAX->setFlag(MachineInstr::FrameSetup);
883 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
885 StackPtr, false, NumBytes - 4);
886 MI->setFlag(MachineInstr::FrameSetup);
887 MBB.insert(MBBI, MI);
889 } else if (NumBytes) {
890 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, Uses64BitFramePtr,
891 UseLEA, TII, *RegInfo);
894 if (NeedsWinEH && NumBytes)
895 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
897 .setMIFlag(MachineInstr::FrameSetup);
899 int SEHFrameOffset = 0;
900 if (IsWinEH && HasFP) {
901 SEHFrameOffset = calculateSetFPREG(NumBytes);
902 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
903 StackPtr, false, SEHFrameOffset);
906 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
908 .addImm(SEHFrameOffset)
909 .setMIFlag(MachineInstr::FrameSetup);
912 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
913 const MachineInstr *FrameInstr = &*MBBI;
918 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
919 if (X86::FR64RegClass.contains(Reg)) {
920 int Offset = getFrameIndexOffset(MF, FI);
921 Offset += SEHFrameOffset;
923 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
926 .setMIFlag(MachineInstr::FrameSetup);
933 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
934 .setMIFlag(MachineInstr::FrameSetup);
936 // Realign stack after we spilled callee-saved registers (so that we'll be
937 // able to calculate their offsets from the frame pointer).
938 // Win64 requires aligning the stack after the prologue.
939 if (IsWinEH && RegInfo->needsStackRealignment(MF)) {
940 assert(HasFP && "There should be a frame pointer if stack is realigned.");
941 uint64_t Val = -MaxAlign;
943 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
947 .setMIFlag(MachineInstr::FrameSetup);
949 // The EFLAGS implicit def is dead.
950 MI->getOperand(3).setIsDead();
953 // If we need a base pointer, set it up here. It's whatever the value
954 // of the stack pointer is at this point. Any variable size objects
955 // will be allocated after this, so we can still use the base pointer
956 // to reference locals.
957 if (RegInfo->hasBasePointer(MF)) {
958 // Update the base pointer with the current stack pointer.
959 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
960 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
962 .setMIFlag(MachineInstr::FrameSetup);
963 if (X86FI->getRestoreBasePointer()) {
964 // Stash value of base pointer. Saving RSP instead of EBP shortens dependence chain.
965 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
966 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
967 FramePtr, true, X86FI->getRestoreBasePointerOffset())
969 .setMIFlag(MachineInstr::FrameSetup);
973 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
974 // Mark end of stack pointer adjustment.
975 if (!HasFP && NumBytes) {
976 // Define the current CFA rule to use the provided offset.
978 unsigned CFIIndex = MMI.addFrameInst(
979 MCCFIInstruction::createDefCfaOffset(nullptr,
980 -StackSize + stackGrowth));
982 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
983 .addCFIIndex(CFIIndex);
986 // Emit DWARF info specifying the offsets of the callee-saved registers.
988 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
992 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
993 MachineBasicBlock &MBB) const {
994 const MachineFrameInfo *MFI = MF.getFrameInfo();
995 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
996 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
997 const X86RegisterInfo *RegInfo = STI.getRegisterInfo();
998 const TargetInstrInfo &TII = *STI.getInstrInfo();
999 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
1000 assert(MBBI != MBB.end() && "Returning block has no instructions");
1001 unsigned RetOpcode = MBBI->getOpcode();
1002 DebugLoc DL = MBBI->getDebugLoc();
1003 bool Is64Bit = STI.is64Bit();
1004 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1005 const bool Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
1006 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1007 bool UseLEA = STI.useLeaForSP();
1008 unsigned SlotSize = RegInfo->getSlotSize();
1009 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1010 unsigned MachineFramePtr =
1011 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1013 unsigned StackPtr = RegInfo->getStackRegister();
1015 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1016 bool NeedsWinEH = IsWinEH && MF.getFunction()->needsUnwindTableEntry();
1018 switch (RetOpcode) {
1020 llvm_unreachable("Can only insert epilog into returning blocks");
1025 case X86::TCRETURNdi:
1026 case X86::TCRETURNri:
1027 case X86::TCRETURNmi:
1028 case X86::TCRETURNdi64:
1029 case X86::TCRETURNri64:
1030 case X86::TCRETURNmi64:
1031 case X86::EH_RETURN:
1032 case X86::EH_RETURN64:
1033 break; // These are ok
1036 // Get the number of bytes to allocate from the FrameInfo.
1037 uint64_t StackSize = MFI->getStackSize();
1038 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1039 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1040 uint64_t NumBytes = 0;
1043 // Calculate required stack adjustment.
1044 uint64_t FrameSize = StackSize - SlotSize;
1045 if (RegInfo->needsStackRealignment(MF)) {
1046 // Callee-saved registers were pushed on stack before the stack
1048 FrameSize -= CSSize;
1049 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
1051 NumBytes = FrameSize - CSSize;
1055 BuildMI(MBB, MBBI, DL,
1056 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
1058 NumBytes = StackSize - CSSize;
1060 uint64_t SEHStackAllocAmt = NumBytes;
1062 // Skip the callee-saved pop instructions.
1063 while (MBBI != MBB.begin()) {
1064 MachineBasicBlock::iterator PI = std::prev(MBBI);
1065 unsigned Opc = PI->getOpcode();
1067 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1068 !PI->isTerminator())
1073 MachineBasicBlock::iterator FirstCSPop = MBBI;
1075 DL = MBBI->getDebugLoc();
1077 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1078 // instruction, merge the two instructions.
1079 if (NumBytes || MFI->hasVarSizedObjects())
1080 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1082 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1083 // slot before popping them off! Same applies for the case, when stack was
1085 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1086 if (RegInfo->needsStackRealignment(MF))
1089 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1090 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), StackPtr),
1091 FramePtr, false, SEHStackAllocAmt - SEHFrameOffset);
1093 } else if (CSSize != 0) {
1094 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1095 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1096 FramePtr, false, -CSSize);
1099 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1100 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1104 } else if (NumBytes) {
1105 // Adjust stack pointer back: ESP += numbytes.
1106 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, Uses64BitFramePtr, UseLEA,
1111 // Windows unwinder will not invoke function's exception handler if IP is
1112 // either in prologue or in epilogue. This behavior causes a problem when a
1113 // call immediately precedes an epilogue, because the return address points
1114 // into the epilogue. To cope with that, we insert an epilogue marker here,
1115 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1116 // final emitted code.
1118 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1120 // We're returning from function via eh_return.
1121 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1122 MBBI = MBB.getLastNonDebugInstr();
1123 MachineOperand &DestAddr = MBBI->getOperand(0);
1124 assert(DestAddr.isReg() && "Offset should be in register!");
1125 BuildMI(MBB, MBBI, DL,
1126 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1127 StackPtr).addReg(DestAddr.getReg());
1128 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1129 RetOpcode == X86::TCRETURNmi ||
1130 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1131 RetOpcode == X86::TCRETURNmi64) {
1132 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1133 // Tail call return: adjust the stack pointer and jump to callee.
1134 MBBI = MBB.getLastNonDebugInstr();
1135 MachineOperand &JumpTarget = MBBI->getOperand(0);
1136 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1137 assert(StackAdjust.isImm() && "Expecting immediate value.");
1139 // Adjust stack pointer.
1140 int StackAdj = StackAdjust.getImm();
1141 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1143 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1145 // Incoporate the retaddr area.
1146 Offset = StackAdj-MaxTCDelta;
1147 assert(Offset >= 0 && "Offset should never be negative");
1150 // Check for possible merge with preceding ADD instruction.
1151 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1152 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, Uses64BitFramePtr,
1153 UseLEA, TII, *RegInfo);
1156 // Jump to label or value in register.
1157 bool IsWin64 = STI.isTargetWin64();
1158 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1159 unsigned Op = (RetOpcode == X86::TCRETURNdi)
1161 : (IsWin64 ? X86::TAILJMPd64_REX : X86::TAILJMPd64);
1162 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(Op));
1163 if (JumpTarget.isGlobal())
1164 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1165 JumpTarget.getTargetFlags());
1167 assert(JumpTarget.isSymbol());
1168 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1169 JumpTarget.getTargetFlags());
1171 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1172 unsigned Op = (RetOpcode == X86::TCRETURNmi)
1174 : (IsWin64 ? X86::TAILJMPm64_REX : X86::TAILJMPm64);
1175 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(Op));
1176 for (unsigned i = 0; i != 5; ++i)
1177 MIB.addOperand(MBBI->getOperand(i));
1178 } else if (RetOpcode == X86::TCRETURNri64) {
1179 BuildMI(MBB, MBBI, DL,
1180 TII.get(IsWin64 ? X86::TAILJMPr64_REX : X86::TAILJMPr64))
1181 .addReg(JumpTarget.getReg(), RegState::Kill);
1183 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1184 addReg(JumpTarget.getReg(), RegState::Kill);
1187 MachineInstr *NewMI = std::prev(MBBI);
1188 NewMI->copyImplicitOps(MF, MBBI);
1190 // Delete the pseudo instruction TCRETURN.
1192 } else if ((RetOpcode == X86::RETQ || RetOpcode == X86::RETL ||
1193 RetOpcode == X86::RETIQ || RetOpcode == X86::RETIL) &&
1194 (X86FI->getTCReturnAddrDelta() < 0)) {
1195 // Add the return addr area delta back since we are not tail calling.
1196 int delta = -1*X86FI->getTCReturnAddrDelta();
1197 MBBI = MBB.getLastNonDebugInstr();
1199 // Check for possible merge with preceding ADD instruction.
1200 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1201 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, Uses64BitFramePtr, UseLEA, TII,
1206 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1208 const X86RegisterInfo *RegInfo =
1209 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1210 const MachineFrameInfo *MFI = MF.getFrameInfo();
1211 // Offset will hold the offset from the stack pointer at function entry to the
1213 // We need to factor in additional offsets applied during the prologue to the
1214 // frame, base, and stack pointer depending on which is used.
1215 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1216 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1217 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1218 uint64_t StackSize = MFI->getStackSize();
1219 unsigned SlotSize = RegInfo->getSlotSize();
1220 bool HasFP = hasFP(MF);
1221 bool IsWinEH = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1222 int64_t FPDelta = 0;
1225 uint64_t NumBytes = 0;
1226 // Calculate required stack adjustment.
1227 uint64_t FrameSize = StackSize - SlotSize;
1228 // If required, include space for extra hidden slot for stashing base pointer.
1229 if (X86FI->getRestoreBasePointer())
1230 FrameSize += SlotSize;
1231 uint64_t SEHStackAllocAmt = StackSize;
1232 if (RegInfo->needsStackRealignment(MF)) {
1233 // Callee-saved registers are pushed on stack before the stack
1235 FrameSize -= CSSize;
1238 calculateMaxStackAlign(MF); // Desired stack alignment.
1239 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1240 SEHStackAllocAmt = RoundUpToAlignment(SEHStackAllocAmt, 16);
1242 NumBytes = FrameSize - CSSize;
1244 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1245 if (FI && FI == X86FI->getFAIndex())
1246 return -SEHFrameOffset;
1248 // FPDelta is the offset from the "traditional" FP location of the old base
1249 // pointer followed by return address and the location required by the
1250 // restricted Win64 prologue.
1251 // Add FPDelta to all offsets below that go through the frame pointer.
1252 FPDelta = SEHStackAllocAmt - SEHFrameOffset;
1256 if (RegInfo->hasBasePointer(MF)) {
1257 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1259 // Skip the saved EBP.
1260 return Offset + SlotSize + FPDelta;
1262 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1263 return Offset + StackSize;
1265 } else if (RegInfo->needsStackRealignment(MF)) {
1267 // Skip the saved EBP.
1268 return Offset + SlotSize + FPDelta;
1270 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1271 return Offset + StackSize;
1273 // FIXME: Support tail calls
1276 return Offset + StackSize;
1278 return Offset + FPDelta;
1280 // Skip the saved EBP.
1283 // Skip the RETADDR move area
1284 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1285 if (TailCallReturnAddrDelta < 0)
1286 Offset -= TailCallReturnAddrDelta;
1292 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1293 unsigned &FrameReg) const {
1294 const X86RegisterInfo *RegInfo =
1295 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1296 // We can't calculate offset from frame pointer if the stack is realigned,
1297 // so enforce usage of stack/base pointer. The base pointer is used when we
1298 // have dynamic allocas in addition to dynamic realignment.
1299 if (RegInfo->hasBasePointer(MF))
1300 FrameReg = RegInfo->getBaseRegister();
1301 else if (RegInfo->needsStackRealignment(MF))
1302 FrameReg = RegInfo->getStackRegister();
1304 FrameReg = RegInfo->getFrameRegister(MF);
1305 return getFrameIndexOffset(MF, FI);
1308 // Simplified from getFrameIndexOffset keeping only StackPointer cases
1309 int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const {
1310 const MachineFrameInfo *MFI = MF.getFrameInfo();
1311 // Does not include any dynamic realign.
1312 const uint64_t StackSize = MFI->getStackSize();
1315 const X86RegisterInfo *RegInfo =
1316 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1317 // Note: LLVM arranges the stack as:
1318 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1319 // > "Stack Slots" (<--SP)
1320 // We can always address StackSlots from RSP. We can usually (unless
1321 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1322 // address them from RBP. FixedObjects can be placed anywhere in the stack
1323 // frame depending on their specific requirements (i.e. we can actually
1324 // refer to arguments to the function which are stored in the *callers*
1325 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1326 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1328 assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");
1330 // We don't handle tail calls, and shouldn't be seeing them
1332 int TailCallReturnAddrDelta =
1333 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1334 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1338 // This is how the math works out:
1340 // %rsp grows (i.e. gets lower) left to right. Each box below is
1341 // one word (eight bytes). Obj0 is the stack slot we're trying to
1344 // ----------------------------------
1345 // | BP | Obj0 | Obj1 | ... | ObjN |
1346 // ----------------------------------
1350 // A is the incoming stack pointer.
1351 // (B - A) is the local area offset (-8 for x86-64) [1]
1352 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1354 // |(E - B)| is the StackSize (absolute value, positive). For a
1355 // stack that grown down, this works out to be (B - E). [3]
1357 // E is also the value of %rsp after stack has been set up, and we
1358 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1359 // (C - E) == (C - A) - (B - A) + (B - E)
1360 // { Using [1], [2] and [3] above }
1361 // == getObjectOffset - LocalAreaOffset + StackSize
1364 // Get the Offset from the StackPointer
1365 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1367 return Offset + StackSize;
1369 // Simplified from getFrameIndexReference keeping only StackPointer cases
1370 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1372 unsigned &FrameReg) const {
1373 const X86RegisterInfo *RegInfo =
1374 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1375 assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");
1377 FrameReg = RegInfo->getStackRegister();
1378 return getFrameIndexOffsetFromSP(MF, FI);
1381 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1382 MachineFunction &MF, const TargetRegisterInfo *TRI,
1383 std::vector<CalleeSavedInfo> &CSI) const {
1384 MachineFrameInfo *MFI = MF.getFrameInfo();
1385 const X86RegisterInfo *RegInfo =
1386 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1387 unsigned SlotSize = RegInfo->getSlotSize();
1388 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1390 unsigned CalleeSavedFrameSize = 0;
1391 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1394 // emitPrologue always spills frame register the first thing.
1395 SpillSlotOffset -= SlotSize;
1396 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1398 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1399 // the frame register, we can delete it from CSI list and not have to worry
1400 // about avoiding it later.
1401 unsigned FPReg = RegInfo->getFrameRegister(MF);
1402 for (unsigned i = 0; i < CSI.size(); ++i) {
1403 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1404 CSI.erase(CSI.begin() + i);
1410 // Assign slots for GPRs. It increases frame size.
1411 for (unsigned i = CSI.size(); i != 0; --i) {
1412 unsigned Reg = CSI[i - 1].getReg();
1414 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1417 SpillSlotOffset -= SlotSize;
1418 CalleeSavedFrameSize += SlotSize;
1420 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1421 CSI[i - 1].setFrameIdx(SlotIndex);
1424 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1426 // Assign slots for XMMs.
1427 for (unsigned i = CSI.size(); i != 0; --i) {
1428 unsigned Reg = CSI[i - 1].getReg();
1429 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1432 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
1434 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1436 SpillSlotOffset -= RC->getSize();
1438 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1439 CSI[i - 1].setFrameIdx(SlotIndex);
1440 MFI->ensureMaxAlignment(RC->getAlignment());
1446 bool X86FrameLowering::spillCalleeSavedRegisters(
1447 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1448 const std::vector<CalleeSavedInfo> &CSI,
1449 const TargetRegisterInfo *TRI) const {
1450 DebugLoc DL = MBB.findDebugLoc(MI);
1452 MachineFunction &MF = *MBB.getParent();
1453 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1454 const TargetInstrInfo &TII = *STI.getInstrInfo();
1456 // Push GPRs. It increases frame size.
1457 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1458 for (unsigned i = CSI.size(); i != 0; --i) {
1459 unsigned Reg = CSI[i - 1].getReg();
1461 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1463 // Add the callee-saved register as live-in. It's killed at the spill.
1466 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1467 .setMIFlag(MachineInstr::FrameSetup);
1470 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1471 // It can be done by spilling XMMs to stack frame.
1472 for (unsigned i = CSI.size(); i != 0; --i) {
1473 unsigned Reg = CSI[i-1].getReg();
1474 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1476 // Add the callee-saved register as live-in. It's killed at the spill.
1478 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1480 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1483 MI->setFlag(MachineInstr::FrameSetup);
1490 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1491 MachineBasicBlock::iterator MI,
1492 const std::vector<CalleeSavedInfo> &CSI,
1493 const TargetRegisterInfo *TRI) const {
1497 DebugLoc DL = MBB.findDebugLoc(MI);
1499 MachineFunction &MF = *MBB.getParent();
1500 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1501 const TargetInstrInfo &TII = *STI.getInstrInfo();
1503 // Reload XMMs from stack frame.
1504 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1505 unsigned Reg = CSI[i].getReg();
1506 if (X86::GR64RegClass.contains(Reg) ||
1507 X86::GR32RegClass.contains(Reg))
1510 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1511 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1515 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1516 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1517 unsigned Reg = CSI[i].getReg();
1518 if (!X86::GR64RegClass.contains(Reg) &&
1519 !X86::GR32RegClass.contains(Reg))
1522 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1528 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1529 RegScavenger *RS) const {
1530 MachineFrameInfo *MFI = MF.getFrameInfo();
1531 const X86RegisterInfo *RegInfo =
1532 MF.getSubtarget<X86Subtarget>().getRegisterInfo();
1533 unsigned SlotSize = RegInfo->getSlotSize();
1535 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1536 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1538 if (TailCallReturnAddrDelta < 0) {
1539 // create RETURNADDR area
1548 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1549 TailCallReturnAddrDelta - SlotSize, true);
1552 // Spill the BasePtr if it's used.
1553 if (RegInfo->hasBasePointer(MF))
1554 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1558 HasNestArgument(const MachineFunction *MF) {
1559 const Function *F = MF->getFunction();
1560 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1562 if (I->hasNestAttr())
1568 /// GetScratchRegister - Get a temp register for performing work in the
1569 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1570 /// and the properties of the function either one or two registers will be
1571 /// needed. Set primary to true for the first register, false for the second.
1573 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1574 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1577 if (CallingConvention == CallingConv::HiPE) {
1579 return Primary ? X86::R14 : X86::R13;
1581 return Primary ? X86::EBX : X86::EDI;
1586 return Primary ? X86::R11 : X86::R12;
1588 return Primary ? X86::R11D : X86::R12D;
1591 bool IsNested = HasNestArgument(&MF);
1593 if (CallingConvention == CallingConv::X86_FastCall ||
1594 CallingConvention == CallingConv::Fast) {
1596 report_fatal_error("Segmented stacks does not support fastcall with "
1597 "nested function.");
1598 return Primary ? X86::EAX : X86::ECX;
1601 return Primary ? X86::EDX : X86::EAX;
1602 return Primary ? X86::ECX : X86::EAX;
1605 // The stack limit in the TCB is set to this many bytes above the actual stack
1607 static const uint64_t kSplitStackAvailable = 256;
1610 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1611 MachineBasicBlock &prologueMBB = MF.front();
1612 MachineFrameInfo *MFI = MF.getFrameInfo();
1613 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1614 const TargetInstrInfo &TII = *STI.getInstrInfo();
1616 bool Is64Bit = STI.is64Bit();
1617 const bool IsLP64 = STI.isTarget64BitLP64();
1618 unsigned TlsReg, TlsOffset;
1621 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1622 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1623 "Scratch register is live-in");
1625 if (MF.getFunction()->isVarArg())
1626 report_fatal_error("Segmented stacks do not support vararg functions.");
1627 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1628 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1629 !STI.isTargetDragonFly())
1630 report_fatal_error("Segmented stacks not supported on this platform.");
1632 // Eventually StackSize will be calculated by a link-time pass; which will
1633 // also decide whether checking code needs to be injected into this particular
1635 StackSize = MFI->getStackSize();
1637 // Do not generate a prologue for functions with a stack of size zero
1641 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1642 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1643 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1644 bool IsNested = false;
1646 // We need to know if the function has a nest argument only in 64 bit mode.
1648 IsNested = HasNestArgument(&MF);
1650 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1651 // allocMBB needs to be last (terminating) instruction.
1653 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1654 e = prologueMBB.livein_end(); i != e; i++) {
1655 allocMBB->addLiveIn(*i);
1656 checkMBB->addLiveIn(*i);
1660 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1662 MF.push_front(allocMBB);
1663 MF.push_front(checkMBB);
1665 // When the frame size is less than 256 we just compare the stack
1666 // boundary directly to the value of the stack pointer, per gcc.
1667 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1669 // Read the limit off the current stacklet off the stack_guard location.
1671 if (STI.isTargetLinux()) {
1673 TlsOffset = IsLP64 ? 0x70 : 0x40;
1674 } else if (STI.isTargetDarwin()) {
1676 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1677 } else if (STI.isTargetWin64()) {
1679 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1680 } else if (STI.isTargetFreeBSD()) {
1683 } else if (STI.isTargetDragonFly()) {
1685 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1687 report_fatal_error("Segmented stacks not supported on this platform.");
1690 if (CompareStackPointer)
1691 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1693 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1694 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1696 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1697 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1699 if (STI.isTargetLinux()) {
1702 } else if (STI.isTargetDarwin()) {
1704 TlsOffset = 0x48 + 90*4;
1705 } else if (STI.isTargetWin32()) {
1707 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1708 } else if (STI.isTargetDragonFly()) {
1710 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1711 } else if (STI.isTargetFreeBSD()) {
1712 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1714 report_fatal_error("Segmented stacks not supported on this platform.");
1717 if (CompareStackPointer)
1718 ScratchReg = X86::ESP;
1720 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1721 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1723 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1724 STI.isTargetDragonFly()) {
1725 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1726 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1727 } else if (STI.isTargetDarwin()) {
1729 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1730 unsigned ScratchReg2;
1732 if (CompareStackPointer) {
1733 // The primary scratch register is available for holding the TLS offset.
1734 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1735 SaveScratch2 = false;
1737 // Need to use a second register to hold the TLS offset
1738 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1740 // Unfortunately, with fastcc the second scratch register may hold an
1742 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1745 // If Scratch2 is live-in then it needs to be saved.
1746 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1747 "Scratch register is live-in and not saved");
1750 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1751 .addReg(ScratchReg2, RegState::Kill);
1753 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1755 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1757 .addReg(ScratchReg2).addImm(1).addReg(0)
1762 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1766 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1767 // It jumps to normal execution of the function body.
1768 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&prologueMBB);
1770 // On 32 bit we first push the arguments size and then the frame size. On 64
1771 // bit, we pass the stack frame size in r10 and the argument size in r11.
1773 // Functions with nested arguments use R10, so it needs to be saved across
1774 // the call to _morestack
1776 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1777 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1778 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1779 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1780 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1783 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1785 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1787 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1788 .addImm(X86FI->getArgumentStackSize());
1789 MF.getRegInfo().setPhysRegUsed(Reg10);
1790 MF.getRegInfo().setPhysRegUsed(Reg11);
1792 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1793 .addImm(X86FI->getArgumentStackSize());
1794 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1798 // __morestack is in libgcc
1799 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1800 // Under the large code model, we cannot assume that __morestack lives
1801 // within 2^31 bytes of the call site, so we cannot use pc-relative
1802 // addressing. We cannot perform the call via a temporary register,
1803 // as the rax register may be used to store the static chain, and all
1804 // other suitable registers may be either callee-save or used for
1805 // parameter passing. We cannot use the stack at this point either
1806 // because __morestack manipulates the stack directly.
1808 // To avoid these issues, perform an indirect call via a read-only memory
1809 // location containing the address.
1811 // This solution is not perfect, as it assumes that the .rodata section
1812 // is laid out within 2^31 bytes of each function body, but this seems
1813 // to be sufficient for JIT.
1814 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1818 .addExternalSymbol("__morestack_addr")
1820 MF.getMMI().setUsesMorestackAddr(true);
1823 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1824 .addExternalSymbol("__morestack");
1826 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1827 .addExternalSymbol("__morestack");
1831 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1833 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1835 allocMBB->addSuccessor(&prologueMBB);
1837 checkMBB->addSuccessor(allocMBB);
1838 checkMBB->addSuccessor(&prologueMBB);
1845 /// Erlang programs may need a special prologue to handle the stack size they
1846 /// might need at runtime. That is because Erlang/OTP does not implement a C
1847 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1848 /// (for more information see Eric Stenman's Ph.D. thesis:
1849 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1852 /// temp0 = sp - MaxStack
1853 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1857 /// call inc_stack # doubles the stack space
1858 /// temp0 = sp - MaxStack
1859 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1860 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1861 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1862 const TargetInstrInfo &TII = *STI.getInstrInfo();
1863 MachineFrameInfo *MFI = MF.getFrameInfo();
1864 const unsigned SlotSize = STI.getRegisterInfo()->getSlotSize();
1865 const bool Is64Bit = STI.is64Bit();
1866 const bool IsLP64 = STI.isTarget64BitLP64();
1868 // HiPE-specific values
1869 const unsigned HipeLeafWords = 24;
1870 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1871 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1872 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1873 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1874 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1876 assert(STI.isTargetLinux() &&
1877 "HiPE prologue is only supported on Linux operating systems.");
1879 // Compute the largest caller's frame that is needed to fit the callees'
1880 // frames. This 'MaxStack' is computed from:
1882 // a) the fixed frame size, which is the space needed for all spilled temps,
1883 // b) outgoing on-stack parameter areas, and
1884 // c) the minimum stack space this function needs to make available for the
1885 // functions it calls (a tunable ABI property).
1886 if (MFI->hasCalls()) {
1887 unsigned MoreStackForCalls = 0;
1889 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1890 MBBI != MBBE; ++MBBI)
1891 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1896 // Get callee operand.
1897 const MachineOperand &MO = MI->getOperand(0);
1899 // Only take account of global function calls (no closures etc.).
1903 const Function *F = dyn_cast<Function>(MO.getGlobal());
1907 // Do not update 'MaxStack' for primitive and built-in functions
1908 // (encoded with names either starting with "erlang."/"bif_" or not
1909 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1910 // "_", such as the BIF "suspend_0") as they are executed on another
1912 if (F->getName().find("erlang.") != StringRef::npos ||
1913 F->getName().find("bif_") != StringRef::npos ||
1914 F->getName().find_first_of("._") == StringRef::npos)
1917 unsigned CalleeStkArity =
1918 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1919 if (HipeLeafWords - 1 > CalleeStkArity)
1920 MoreStackForCalls = std::max(MoreStackForCalls,
1921 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1923 MaxStack += MoreStackForCalls;
1926 // If the stack frame needed is larger than the guaranteed then runtime checks
1927 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1928 if (MaxStack > Guaranteed) {
1929 MachineBasicBlock &prologueMBB = MF.front();
1930 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1931 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1933 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1934 E = prologueMBB.livein_end(); I != E; I++) {
1935 stackCheckMBB->addLiveIn(*I);
1936 incStackMBB->addLiveIn(*I);
1939 MF.push_front(incStackMBB);
1940 MF.push_front(stackCheckMBB);
1942 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1943 unsigned LEAop, CMPop, CALLop;
1947 LEAop = X86::LEA64r;
1948 CMPop = X86::CMP64rm;
1949 CALLop = X86::CALL64pcrel32;
1950 SPLimitOffset = 0x90;
1954 LEAop = X86::LEA32r;
1955 CMPop = X86::CMP32rm;
1956 CALLop = X86::CALLpcrel32;
1957 SPLimitOffset = 0x4c;
1960 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1961 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1962 "HiPE prologue scratch register is live-in");
1964 // Create new MBB for StackCheck:
1965 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1966 SPReg, false, -MaxStack);
1967 // SPLimitOffset is in a fixed heap location (pointed by BP).
1968 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1969 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1970 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&prologueMBB);
1972 // Create new MBB for IncStack:
1973 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1974 addExternalSymbol("inc_stack_0");
1975 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1976 SPReg, false, -MaxStack);
1977 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1978 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1979 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1981 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1982 stackCheckMBB->addSuccessor(incStackMBB, 1);
1983 incStackMBB->addSuccessor(&prologueMBB, 99);
1984 incStackMBB->addSuccessor(incStackMBB, 1);
1991 void X86FrameLowering::
1992 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1993 MachineBasicBlock::iterator I) const {
1994 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
1995 const TargetInstrInfo &TII = *STI.getInstrInfo();
1996 const X86RegisterInfo &RegInfo = *STI.getRegisterInfo();
1997 unsigned StackPtr = RegInfo.getStackRegister();
1998 bool reserveCallFrame = hasReservedCallFrame(MF);
1999 int Opcode = I->getOpcode();
2000 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2001 bool IsLP64 = STI.isTarget64BitLP64();
2002 DebugLoc DL = I->getDebugLoc();
2003 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
2004 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
2007 if (!reserveCallFrame) {
2008 // If the stack pointer can be changed after prologue, turn the
2009 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2010 // adjcallstackdown instruction into 'add ESP, <amt>'
2014 // We need to keep the stack aligned properly. To do this, we round the
2015 // amount of space needed for the outgoing arguments up to the next
2016 // alignment boundary.
2017 unsigned StackAlign = getStackAlignment();
2018 Amount = RoundUpToAlignment(Amount, StackAlign);
2020 MachineInstr *New = nullptr;
2022 // Factor out the amount that gets handled inside the sequence
2023 // (Pushes of argument for frame setup, callee pops for frame destroy)
2024 Amount -= InternalAmt;
2027 if (Opcode == TII.getCallFrameSetupOpcode()) {
2028 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)), StackPtr)
2029 .addReg(StackPtr).addImm(Amount);
2031 assert(Opcode == TII.getCallFrameDestroyOpcode());
2033 unsigned Opc = getADDriOpcode(IsLP64, Amount);
2034 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
2035 .addReg(StackPtr).addImm(Amount);
2040 // The EFLAGS implicit def is dead.
2041 New->getOperand(3).setIsDead();
2043 // Replace the pseudo instruction with a new instruction.
2050 if (Opcode == TII.getCallFrameDestroyOpcode() && InternalAmt) {
2051 // If we are performing frame pointer elimination and if the callee pops
2052 // something off the stack pointer, add it back. We do this until we have
2053 // more advanced stack pointer tracking ability.
2054 unsigned Opc = getSUBriOpcode(IsLP64, InternalAmt);
2055 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
2056 .addReg(StackPtr).addImm(InternalAmt);
2058 // The EFLAGS implicit def is dead.
2059 New->getOperand(3).setIsDead();
2061 // We are not tracking the stack pointer adjustment by the callee, so make
2062 // sure we restore the stack pointer immediately after the call, there may
2063 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2064 MachineBasicBlock::iterator B = MBB.begin();
2065 while (I != B && !std::prev(I)->isCall())