1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
37 // FIXME: completely move here.
38 extern cl::opt<bool> ForceStackAlign;
40 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
41 unsigned StackAlignOverride)
42 : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
43 STI.is64Bit() ? -8 : -4),
44 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
45 // Cache a bunch of frame-related predicates for this subtarget.
46 SlotSize = TRI->getSlotSize();
47 Is64Bit = STI.is64Bit();
48 IsLP64 = STI.isTarget64BitLP64();
49 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
50 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
51 StackPtr = TRI->getStackRegister();
54 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
55 return !MF.getFrameInfo()->hasVarSizedObjects() &&
56 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
59 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
60 /// call frame pseudos can be simplified. Having a FP, as in the default
61 /// implementation, is not sufficient here since we can't always use it.
62 /// Use a more nuanced condition.
64 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
65 return hasReservedCallFrame(MF) ||
66 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
67 TRI->hasBasePointer(MF);
70 // needsFrameIndexResolution - Do we need to perform FI resolution for
71 // this function. Normally, this is required only when the function
72 // has any stack objects. However, FI resolution actually has another job,
73 // not apparent from the title - it resolves callframesetup/destroy
74 // that were not simplified earlier.
75 // So, this is required for x86 functions that have push sequences even
76 // when there are no stack objects.
78 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
79 return MF.getFrameInfo()->hasStackObjects() ||
80 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
83 /// hasFP - Return true if the specified function should have a dedicated frame
84 /// pointer register. This is true if the function has variable sized allocas
85 /// or if frame pointer elimination is disabled.
86 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
87 const MachineFrameInfo *MFI = MF.getFrameInfo();
88 const MachineModuleInfo &MMI = MF.getMMI();
90 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
91 TRI->needsStackRealignment(MF) ||
92 MFI->hasVarSizedObjects() ||
93 MFI->isFrameAddressTaken() || MFI->hasOpaqueSPAdjustment() ||
94 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
95 MMI.callsUnwindInit() || MMI.callsEHReturn() ||
96 MFI->hasStackMap() || MFI->hasPatchPoint());
99 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
102 return X86::SUB64ri8;
103 return X86::SUB64ri32;
106 return X86::SUB32ri8;
111 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
114 return X86::ADD64ri8;
115 return X86::ADD64ri32;
118 return X86::ADD32ri8;
123 static unsigned getSUBrrOpcode(unsigned isLP64) {
124 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
127 static unsigned getADDrrOpcode(unsigned isLP64) {
128 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
131 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
134 return X86::AND64ri8;
135 return X86::AND64ri32;
138 return X86::AND32ri8;
142 static unsigned getLEArOpcode(unsigned IsLP64) {
143 return IsLP64 ? X86::LEA64r : X86::LEA32r;
146 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
147 /// when it reaches the "return" instruction. We can then pop a stack object
148 /// to this register without worry about clobbering it.
149 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
150 MachineBasicBlock::iterator &MBBI,
151 const TargetRegisterInfo *TRI,
153 const MachineFunction *MF = MBB.getParent();
154 const Function *F = MF->getFunction();
155 if (!F || MF->getMMI().callsEHReturn())
158 static const uint16_t CallerSavedRegs32Bit[] = {
159 X86::EAX, X86::EDX, X86::ECX, 0
162 static const uint16_t CallerSavedRegs64Bit[] = {
163 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
164 X86::R8, X86::R9, X86::R10, X86::R11, 0
167 unsigned Opc = MBBI->getOpcode();
174 case X86::TCRETURNdi:
175 case X86::TCRETURNri:
176 case X86::TCRETURNmi:
177 case X86::TCRETURNdi64:
178 case X86::TCRETURNri64:
179 case X86::TCRETURNmi64:
181 case X86::EH_RETURN64: {
182 SmallSet<uint16_t, 8> Uses;
183 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
184 MachineOperand &MO = MBBI->getOperand(i);
185 if (!MO.isReg() || MO.isDef())
187 unsigned Reg = MO.getReg();
190 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
194 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
196 if (!Uses.count(*CS))
204 static bool isEAXLiveIn(MachineFunction &MF) {
205 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
206 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
207 unsigned Reg = II->first;
209 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
210 Reg == X86::AH || Reg == X86::AL)
217 /// Check whether or not the terminators of \p MBB needs to read EFLAGS.
218 static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
219 for (const MachineInstr &MI : MBB.terminators()) {
220 bool BreakNext = false;
221 for (const MachineOperand &MO : MI.operands()) {
224 unsigned Reg = MO.getReg();
225 if (Reg != X86::EFLAGS)
228 // This terminator needs an eflag that is not defined
229 // by a previous terminator.
240 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
241 /// stack pointer by a constant value.
242 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
243 MachineBasicBlock::iterator &MBBI,
244 int64_t NumBytes, bool InEpilogue) const {
245 bool isSub = NumBytes < 0;
246 uint64_t Offset = isSub ? -NumBytes : NumBytes;
248 uint64_t Chunk = (1LL << 31) - 1;
249 DebugLoc DL = MBB.findDebugLoc(MBBI);
252 if (Offset > Chunk) {
253 // Rather than emit a long series of instructions for large offsets,
254 // load the offset into a register and do one sub/add
257 if (isSub && !isEAXLiveIn(*MBB.getParent()))
258 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
260 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
263 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
264 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
267 ? getSUBrrOpcode(Is64Bit)
268 : getADDrrOpcode(Is64Bit);
269 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
272 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
278 uint64_t ThisVal = std::min(Offset, Chunk);
279 if (ThisVal == (Is64Bit ? 8 : 4)) {
280 // Use push / pop instead.
282 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
283 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
286 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
287 : (Is64Bit ? X86::POP64r : X86::POP32r);
288 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
289 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
291 MI->setFlag(MachineInstr::FrameSetup);
297 MachineInstrBuilder MI = BuildStackAdjustment(
298 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue);
300 MI.setMIFlag(MachineInstr::FrameSetup);
306 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
307 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
308 int64_t Offset, bool InEpilogue) const {
309 assert(Offset != 0 && "zero offset stack adjustment requested");
311 // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
315 UseLEA = STI.useLeaForSP();
317 // If we can use LEA for SP but we shouldn't, check that none
318 // of the terminators uses the eflags. Otherwise we will insert
319 // a ADD that will redefine the eflags and break the condition.
320 // Alternatively, we could move the ADD, but this may not be possible
321 // and is an optimization anyway.
322 UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
323 if (UseLEA && !STI.useLeaForSP())
324 UseLEA = terminatorsNeedFlagsAsInput(MBB);
325 // If that assert breaks, that means we do not do the right thing
326 // in canUseAsEpilogue.
327 assert((UseLEA || !terminatorsNeedFlagsAsInput(MBB)) &&
328 "We shouldn't have allowed this insertion point");
331 MachineInstrBuilder MI;
333 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
334 TII.get(getLEArOpcode(Uses64BitFramePtr)),
336 StackPtr, false, Offset);
338 bool IsSub = Offset < 0;
339 uint64_t AbsOffset = IsSub ? -Offset : Offset;
340 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
341 : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
342 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
345 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
350 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
352 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
353 unsigned StackPtr, uint64_t *NumBytes = nullptr) {
354 if (MBBI == MBB.begin()) return;
356 MachineBasicBlock::iterator PI = std::prev(MBBI);
357 unsigned Opc = PI->getOpcode();
358 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
359 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
360 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
361 PI->getOperand(0).getReg() == StackPtr) {
363 *NumBytes += PI->getOperand(2).getImm();
365 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
366 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
367 PI->getOperand(0).getReg() == StackPtr) {
369 *NumBytes -= PI->getOperand(2).getImm();
374 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
375 MachineBasicBlock::iterator &MBBI,
376 bool doMergeWithPrevious) const {
377 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
378 (!doMergeWithPrevious && MBBI == MBB.end()))
381 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
382 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
384 unsigned Opc = PI->getOpcode();
387 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
388 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
389 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
390 PI->getOperand(0).getReg() == StackPtr){
391 Offset += PI->getOperand(2).getImm();
393 if (!doMergeWithPrevious) MBBI = NI;
394 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
395 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
396 PI->getOperand(0).getReg() == StackPtr) {
397 Offset -= PI->getOperand(2).getImm();
399 if (!doMergeWithPrevious) MBBI = NI;
405 void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
406 MachineBasicBlock::iterator MBBI, DebugLoc DL,
407 MCCFIInstruction CFIInst) const {
408 MachineFunction &MF = *MBB.getParent();
409 unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
410 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
411 .addCFIIndex(CFIIndex);
415 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
416 MachineBasicBlock::iterator MBBI,
418 MachineFunction &MF = *MBB.getParent();
419 MachineFrameInfo *MFI = MF.getFrameInfo();
420 MachineModuleInfo &MMI = MF.getMMI();
421 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
423 // Add callee saved registers to move list.
424 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
425 if (CSI.empty()) return;
427 // Calculate offsets.
428 for (std::vector<CalleeSavedInfo>::const_iterator
429 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
430 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
431 unsigned Reg = I->getReg();
433 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
434 BuildCFI(MBB, MBBI, DL,
435 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
439 /// usesTheStack - This function checks if any of the users of EFLAGS
440 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
441 /// to use the stack, and if we don't adjust the stack we clobber the first
443 /// See X86InstrInfo::copyPhysReg.
444 static bool usesTheStack(const MachineFunction &MF) {
445 const MachineRegisterInfo &MRI = MF.getRegInfo();
447 for (MachineRegisterInfo::reg_instr_iterator
448 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
456 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
457 MachineBasicBlock &MBB,
458 MachineBasicBlock::iterator MBBI,
460 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
464 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
466 CallOp = X86::CALLpcrel32;
470 if (STI.isTargetCygMing()) {
471 Symbol = "___chkstk_ms";
475 } else if (STI.isTargetCygMing())
480 MachineInstrBuilder CI;
482 // All current stack probes take AX and SP as input, clobber flags, and
483 // preserve all registers. x86_64 probes leave RSP unmodified.
484 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
485 // For the large code model, we have to call through a register. Use R11,
486 // as it is scratch in all supported calling conventions.
487 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
488 .addExternalSymbol(Symbol);
489 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
491 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
494 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
495 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
496 CI.addReg(AX, RegState::Implicit)
497 .addReg(SP, RegState::Implicit)
498 .addReg(AX, RegState::Define | RegState::Implicit)
499 .addReg(SP, RegState::Define | RegState::Implicit)
500 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
503 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
504 // themselves. It also does not clobber %rax so we can reuse it when
506 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
512 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
513 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
514 // and might require smaller successive adjustments.
515 const uint64_t Win64MaxSEHOffset = 128;
516 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
517 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
518 return SEHFrameOffset & -16;
521 // If we're forcing a stack realignment we can't rely on just the frame
522 // info, we need to know the ABI stack alignment as well in case we
523 // have a call out. Otherwise just make sure we have some alignment - we'll
524 // go with the minimum SlotSize.
525 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
526 const MachineFrameInfo *MFI = MF.getFrameInfo();
527 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
528 unsigned StackAlign = getStackAlignment();
529 if (ForceStackAlign) {
531 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
532 else if (MaxAlign < SlotSize)
538 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
539 MachineBasicBlock::iterator MBBI,
541 uint64_t MaxAlign) const {
542 uint64_t Val = -MaxAlign;
544 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
548 .setMIFlag(MachineInstr::FrameSetup);
550 // The EFLAGS implicit def is dead.
551 MI->getOperand(3).setIsDead();
554 /// emitPrologue - Push callee-saved registers onto the stack, which
555 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
556 /// space for local variables. Also emit labels used by the exception handler to
557 /// generate the exception handling frames.
560 Here's a gist of what gets emitted:
562 ; Establish frame pointer, if needed
565 .cfi_def_cfa_offset 16
566 .cfi_offset %rbp, -16
569 .cfi_def_cfa_register %rbp
571 ; Spill general-purpose registers
572 [for all callee-saved GPRs]
575 .cfi_def_cfa_offset (offset from RETADDR)
578 ; If the required stack alignment > default stack alignment
579 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
580 ; of unknown size in the stack frame.
581 [if stack needs re-alignment]
584 ; Allocate space for locals
585 [if target is Windows and allocated space > 4096 bytes]
586 ; Windows needs special care for allocations larger
589 call ___chkstk_ms/___chkstk
595 .seh_stackalloc (size of XMM spill slots)
596 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
601 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
602 ; they may get spilled on any platform, if the current function
603 ; calls @llvm.eh.unwind.init
605 [for all callee-saved XMM registers]
606 movaps %<xmm reg>, -MMM(%rbp)
607 [for all callee-saved XMM registers]
608 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
609 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
611 [for all callee-saved XMM registers]
612 movaps %<xmm reg>, KKK(%rsp)
613 [for all callee-saved XMM registers]
614 .seh_savexmm %<xmm reg>, KKK
618 [if needs base pointer]
620 [if needs to restore base pointer]
625 [for all callee-saved registers]
626 .cfi_offset %<reg>, (offset from %rbp)
628 .cfi_def_cfa_offset (offset from RETADDR)
629 [for all callee-saved registers]
630 .cfi_offset %<reg>, (offset from %rsp)
633 - .seh directives are emitted only for Windows 64 ABI
634 - .cfi directives are emitted for all other ABIs
635 - for 32-bit code, substitute %e?? registers for %r??
638 void X86FrameLowering::emitPrologue(MachineFunction &MF,
639 MachineBasicBlock &MBB) const {
640 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
641 "MF used frame lowering for wrong subtarget");
642 MachineBasicBlock::iterator MBBI = MBB.begin();
643 MachineFrameInfo *MFI = MF.getFrameInfo();
644 const Function *Fn = MF.getFunction();
645 MachineModuleInfo &MMI = MF.getMMI();
646 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
647 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
648 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
649 bool HasFP = hasFP(MF);
650 bool IsWin64CC = STI.isCallingConvWin64(Fn->getCallingConv());
651 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
652 bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();
654 !IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
655 unsigned FramePtr = TRI->getFrameRegister(MF);
656 const unsigned MachineFramePtr =
657 STI.isTarget64BitILP32()
658 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
660 unsigned BasePtr = TRI->getBaseRegister();
663 // Add RETADDR move area to callee saved frame size.
664 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
665 if (TailCallReturnAddrDelta && IsWin64Prologue)
666 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
668 if (TailCallReturnAddrDelta < 0)
669 X86FI->setCalleeSavedFrameSize(
670 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
672 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
674 // The default stack probe size is 4096 if the function has no stackprobesize
676 unsigned StackProbeSize = 4096;
677 if (Fn->hasFnAttribute("stack-probe-size"))
678 Fn->getFnAttribute("stack-probe-size")
680 .getAsInteger(0, StackProbeSize);
682 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
683 // function, and use up to 128 bytes of stack space, don't have a frame
684 // pointer, calls, or dynamic alloca then we do not need to adjust the
685 // stack pointer (we fit in the Red Zone). We also check that we don't
686 // push and pop from the stack.
687 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
688 !TRI->needsStackRealignment(MF) &&
689 !MFI->hasVarSizedObjects() && // No dynamic alloca.
690 !MFI->adjustsStack() && // No calls.
691 !IsWin64CC && // Win64 has no Red Zone
692 !usesTheStack(MF) && // Don't push and pop.
693 !MF.shouldSplitStack()) { // Regular stack
694 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
695 if (HasFP) MinSize += SlotSize;
696 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
697 MFI->setStackSize(StackSize);
700 // Insert stack pointer adjustment for later moving of return addr. Only
701 // applies to tail call optimized functions where the callee argument stack
702 // size is bigger than the callers.
703 if (TailCallReturnAddrDelta < 0) {
704 BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
705 /*InEpilogue=*/false)
706 .setMIFlag(MachineInstr::FrameSetup);
709 // Mapping for machine moves:
711 // DST: VirtualFP AND
712 // SRC: VirtualFP => DW_CFA_def_cfa_offset
713 // ELSE => DW_CFA_def_cfa
715 // SRC: VirtualFP AND
716 // DST: Register => DW_CFA_def_cfa_register
719 // OFFSET < 0 => DW_CFA_offset_extended_sf
720 // REG < 64 => DW_CFA_offset + Reg
721 // ELSE => DW_CFA_offset_extended
723 uint64_t NumBytes = 0;
724 int stackGrowth = -SlotSize;
727 // Calculate required stack adjustment.
728 uint64_t FrameSize = StackSize - SlotSize;
729 // If required, include space for extra hidden slot for stashing base pointer.
730 if (X86FI->getRestoreBasePointer())
731 FrameSize += SlotSize;
733 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
735 // Callee-saved registers are pushed on stack before the stack is realigned.
736 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
737 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
739 // Get the offset of the stack slot for the EBP register, which is
740 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
741 // Update the frame offset adjustment.
742 MFI->setOffsetAdjustment(-NumBytes);
744 // Save EBP/RBP into the appropriate stack slot.
745 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
746 .addReg(MachineFramePtr, RegState::Kill)
747 .setMIFlag(MachineInstr::FrameSetup);
750 // Mark the place where EBP/RBP was saved.
751 // Define the current CFA rule to use the provided offset.
753 BuildCFI(MBB, MBBI, DL,
754 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
756 // Change the rule for the FramePtr to be an "offset" rule.
757 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
758 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
759 nullptr, DwarfFramePtr, 2 * stackGrowth));
763 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
765 .setMIFlag(MachineInstr::FrameSetup);
768 if (!IsWin64Prologue) {
769 // Update EBP with the new base value.
770 BuildMI(MBB, MBBI, DL,
771 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
774 .setMIFlag(MachineInstr::FrameSetup);
778 // Mark effective beginning of when frame pointer becomes valid.
779 // Define the current CFA to use the EBP/RBP register.
780 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
781 BuildCFI(MBB, MBBI, DL,
782 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
785 // Mark the FramePtr as live-in in every block.
786 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
787 I->addLiveIn(MachineFramePtr);
789 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
792 // Skip the callee-saved push instructions.
793 bool PushedRegs = false;
794 int StackOffset = 2 * stackGrowth;
796 while (MBBI != MBB.end() &&
797 MBBI->getFlag(MachineInstr::FrameSetup) &&
798 (MBBI->getOpcode() == X86::PUSH32r ||
799 MBBI->getOpcode() == X86::PUSH64r)) {
801 unsigned Reg = MBBI->getOperand(0).getReg();
804 if (!HasFP && NeedsDwarfCFI) {
805 // Mark callee-saved push instruction.
806 // Define the current CFA rule to use the provided offset.
808 BuildCFI(MBB, MBBI, DL,
809 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
810 StackOffset += stackGrowth;
814 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
815 MachineInstr::FrameSetup);
819 // Realign stack after we pushed callee-saved registers (so that we'll be
820 // able to calculate their offsets from the frame pointer).
821 // Don't do this for Win64, it needs to realign the stack after the prologue.
822 if (!IsWin64Prologue && TRI->needsStackRealignment(MF)) {
823 assert(HasFP && "There should be a frame pointer if stack is realigned.");
824 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
827 // If there is an SUB32ri of ESP immediately before this instruction, merge
828 // the two. This can be the case when tail call elimination is enabled and
829 // the callee has more arguments then the caller.
830 NumBytes -= mergeSPUpdates(MBB, MBBI, true);
832 // Adjust stack pointer: ESP -= numbytes.
834 // Windows and cygwin/mingw require a prologue helper routine when allocating
835 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
836 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
837 // stack and adjust the stack pointer in one go. The 64-bit version of
838 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
839 // responsible for adjusting the stack pointer. Touching the stack at 4K
840 // increments is necessary to ensure that the guard pages used by the OS
841 // virtual memory manager are allocated in correct sequence.
842 uint64_t AlignedNumBytes = NumBytes;
843 if (IsWin64Prologue && TRI->needsStackRealignment(MF))
844 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
845 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
846 // Check whether EAX is livein for this function.
847 bool isEAXAlive = isEAXLiveIn(MF);
850 // Sanity check that EAX is not livein for this function.
851 // It should not be, so throw an assert.
852 assert(!Is64Bit && "EAX is livein in x64 case!");
855 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
856 .addReg(X86::EAX, RegState::Kill)
857 .setMIFlag(MachineInstr::FrameSetup);
861 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
862 // Function prologue is responsible for adjusting the stack pointer.
863 if (isUInt<32>(NumBytes)) {
864 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
866 .setMIFlag(MachineInstr::FrameSetup);
867 } else if (isInt<32>(NumBytes)) {
868 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
870 .setMIFlag(MachineInstr::FrameSetup);
872 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
874 .setMIFlag(MachineInstr::FrameSetup);
877 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
878 // We'll also use 4 already allocated bytes for EAX.
879 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
880 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
881 .setMIFlag(MachineInstr::FrameSetup);
884 // Save a pointer to the MI where we set AX.
885 MachineBasicBlock::iterator SetRAX = MBBI;
888 // Call __chkstk, __chkstk_ms, or __alloca.
889 emitStackProbeCall(MF, MBB, MBBI, DL);
891 // Apply the frame setup flag to all inserted instrs.
892 for (; SetRAX != MBBI; ++SetRAX)
893 SetRAX->setFlag(MachineInstr::FrameSetup);
897 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
899 StackPtr, false, NumBytes - 4);
900 MI->setFlag(MachineInstr::FrameSetup);
901 MBB.insert(MBBI, MI);
903 } else if (NumBytes) {
904 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
907 if (NeedsWinCFI && NumBytes)
908 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
910 .setMIFlag(MachineInstr::FrameSetup);
912 int SEHFrameOffset = 0;
913 if (IsWin64Prologue && HasFP) {
914 SEHFrameOffset = calculateSetFPREG(NumBytes);
916 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
917 StackPtr, false, SEHFrameOffset);
919 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr).addReg(StackPtr);
922 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
924 .addImm(SEHFrameOffset)
925 .setMIFlag(MachineInstr::FrameSetup);
928 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
929 const MachineInstr *FrameInstr = &*MBBI;
934 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
935 if (X86::FR64RegClass.contains(Reg)) {
936 int Offset = getFrameIndexOffset(MF, FI);
937 Offset += SEHFrameOffset;
939 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
942 .setMIFlag(MachineInstr::FrameSetup);
949 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
950 .setMIFlag(MachineInstr::FrameSetup);
952 // Realign stack after we spilled callee-saved registers (so that we'll be
953 // able to calculate their offsets from the frame pointer).
954 // Win64 requires aligning the stack after the prologue.
955 if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
956 assert(HasFP && "There should be a frame pointer if stack is realigned.");
957 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
960 // If we need a base pointer, set it up here. It's whatever the value
961 // of the stack pointer is at this point. Any variable size objects
962 // will be allocated after this, so we can still use the base pointer
963 // to reference locals.
964 if (TRI->hasBasePointer(MF)) {
965 // Update the base pointer with the current stack pointer.
966 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
967 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
969 .setMIFlag(MachineInstr::FrameSetup);
970 if (X86FI->getRestoreBasePointer()) {
971 // Stash value of base pointer. Saving RSP instead of EBP shortens
972 // dependence chain. Used by SjLj EH.
973 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
974 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
975 FramePtr, true, X86FI->getRestoreBasePointerOffset())
977 .setMIFlag(MachineInstr::FrameSetup);
980 if (X86FI->getHasSEHFramePtrSave()) {
981 // Stash the value of the frame pointer relative to the base pointer for
982 // Win32 EH. This supports Win32 EH, which does the inverse of the above:
983 // it recovers the frame pointer from the base pointer rather than the
985 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
986 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), BasePtr, true,
987 getFrameIndexOffset(MF, X86FI->getSEHFramePtrSaveIndex()))
989 .setMIFlag(MachineInstr::FrameSetup);
993 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
994 // Mark end of stack pointer adjustment.
995 if (!HasFP && NumBytes) {
996 // Define the current CFA rule to use the provided offset.
998 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
999 nullptr, -StackSize + stackGrowth));
1002 // Emit DWARF info specifying the offsets of the callee-saved registers.
1004 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1008 bool X86FrameLowering::canUseLEAForSPInEpilogue(
1009 const MachineFunction &MF) const {
1010 // We can't use LEA instructions for adjusting the stack pointer if this is a
1011 // leaf function in the Win64 ABI. Only ADD instructions may be used to
1012 // deallocate the stack.
1013 // This means that we can use LEA for SP in two situations:
1014 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1015 // 2. We *have* a frame pointer which means we are permitted to use LEA.
1016 return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1019 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
1020 MachineBasicBlock &MBB) const {
1021 const MachineFrameInfo *MFI = MF.getFrameInfo();
1022 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1023 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1025 if (MBBI != MBB.end())
1026 DL = MBBI->getDebugLoc();
1027 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1028 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1029 unsigned FramePtr = TRI->getFrameRegister(MF);
1030 unsigned MachineFramePtr =
1031 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1034 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1036 IsWin64Prologue && MF.getFunction()->needsUnwindTableEntry();
1038 // Get the number of bytes to allocate from the FrameInfo.
1039 uint64_t StackSize = MFI->getStackSize();
1040 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1041 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1042 uint64_t NumBytes = 0;
1045 // Calculate required stack adjustment.
1046 uint64_t FrameSize = StackSize - SlotSize;
1047 NumBytes = FrameSize - CSSize;
1049 // Callee-saved registers were pushed on stack before the stack was
1051 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1052 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1055 BuildMI(MBB, MBBI, DL,
1056 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr);
1058 NumBytes = StackSize - CSSize;
1060 uint64_t SEHStackAllocAmt = NumBytes;
1062 // Skip the callee-saved pop instructions.
1063 while (MBBI != MBB.begin()) {
1064 MachineBasicBlock::iterator PI = std::prev(MBBI);
1065 unsigned Opc = PI->getOpcode();
1067 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1068 !PI->isTerminator())
1073 MachineBasicBlock::iterator FirstCSPop = MBBI;
1075 if (MBBI != MBB.end())
1076 DL = MBBI->getDebugLoc();
1078 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1079 // instruction, merge the two instructions.
1080 if (NumBytes || MFI->hasVarSizedObjects())
1081 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1083 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1084 // slot before popping them off! Same applies for the case, when stack was
1086 if (TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1087 if (TRI->needsStackRealignment(MF))
1089 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1090 uint64_t LEAAmount =
1091 IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1093 // There are only two legal forms of epilogue:
1094 // - add SEHAllocationSize, %rsp
1095 // - lea SEHAllocationSize(%FramePtr), %rsp
1097 // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1098 // However, we may use this sequence if we have a frame pointer because the
1099 // effects of the prologue can safely be undone.
1100 if (LEAAmount != 0) {
1101 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1102 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1103 FramePtr, false, LEAAmount);
1106 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1107 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1111 } else if (NumBytes) {
1112 // Adjust stack pointer back: ESP += numbytes.
1113 emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
1117 // Windows unwinder will not invoke function's exception handler if IP is
1118 // either in prologue or in epilogue. This behavior causes a problem when a
1119 // call immediately precedes an epilogue, because the return address points
1120 // into the epilogue. To cope with that, we insert an epilogue marker here,
1121 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1122 // final emitted code.
1124 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1126 // Add the return addr area delta back since we are not tail calling.
1127 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1128 assert(Offset >= 0 && "TCDelta should never be positive");
1130 MBBI = MBB.getFirstTerminator();
1132 // Check for possible merge with preceding ADD instruction.
1133 Offset += mergeSPUpdates(MBB, MBBI, true);
1134 emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
1138 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF,
1140 const MachineFrameInfo *MFI = MF.getFrameInfo();
1141 // Offset will hold the offset from the stack pointer at function entry to the
1143 // We need to factor in additional offsets applied during the prologue to the
1144 // frame, base, and stack pointer depending on which is used.
1145 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1146 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1147 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1148 uint64_t StackSize = MFI->getStackSize();
1149 bool HasFP = hasFP(MF);
1150 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1151 int64_t FPDelta = 0;
1153 if (IsWin64Prologue) {
1154 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1156 // Calculate required stack adjustment.
1157 uint64_t FrameSize = StackSize - SlotSize;
1158 // If required, include space for extra hidden slot for stashing base pointer.
1159 if (X86FI->getRestoreBasePointer())
1160 FrameSize += SlotSize;
1161 uint64_t NumBytes = FrameSize - CSSize;
1163 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1164 if (FI && FI == X86FI->getFAIndex())
1165 return -SEHFrameOffset;
1167 // FPDelta is the offset from the "traditional" FP location of the old base
1168 // pointer followed by return address and the location required by the
1169 // restricted Win64 prologue.
1170 // Add FPDelta to all offsets below that go through the frame pointer.
1171 FPDelta = FrameSize - SEHFrameOffset;
1172 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1173 "FPDelta isn't aligned per the Win64 ABI!");
1177 if (TRI->hasBasePointer(MF)) {
1178 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1180 // Skip the saved EBP.
1181 return Offset + SlotSize + FPDelta;
1183 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1184 return Offset + StackSize;
1186 } else if (TRI->needsStackRealignment(MF)) {
1188 // Skip the saved EBP.
1189 return Offset + SlotSize + FPDelta;
1191 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1192 return Offset + StackSize;
1194 // FIXME: Support tail calls
1197 return Offset + StackSize;
1199 // Skip the saved EBP.
1202 // Skip the RETADDR move area
1203 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1204 if (TailCallReturnAddrDelta < 0)
1205 Offset -= TailCallReturnAddrDelta;
1208 return Offset + FPDelta;
1211 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1212 unsigned &FrameReg) const {
1213 // We can't calculate offset from frame pointer if the stack is realigned,
1214 // so enforce usage of stack/base pointer. The base pointer is used when we
1215 // have dynamic allocas in addition to dynamic realignment.
1216 if (TRI->hasBasePointer(MF))
1217 FrameReg = TRI->getBaseRegister();
1218 else if (TRI->needsStackRealignment(MF))
1219 FrameReg = TRI->getStackRegister();
1221 FrameReg = TRI->getFrameRegister(MF);
1222 return getFrameIndexOffset(MF, FI);
1225 // Simplified from getFrameIndexOffset keeping only StackPointer cases
1226 int X86FrameLowering::getFrameIndexOffsetFromSP(const MachineFunction &MF, int FI) const {
1227 const MachineFrameInfo *MFI = MF.getFrameInfo();
1228 // Does not include any dynamic realign.
1229 const uint64_t StackSize = MFI->getStackSize();
1232 // Note: LLVM arranges the stack as:
1233 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1234 // > "Stack Slots" (<--SP)
1235 // We can always address StackSlots from RSP. We can usually (unless
1236 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1237 // address them from RBP. FixedObjects can be placed anywhere in the stack
1238 // frame depending on their specific requirements (i.e. we can actually
1239 // refer to arguments to the function which are stored in the *callers*
1240 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1241 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1243 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1245 // We don't handle tail calls, and shouldn't be seeing them
1247 int TailCallReturnAddrDelta =
1248 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1249 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1253 // This is how the math works out:
1255 // %rsp grows (i.e. gets lower) left to right. Each box below is
1256 // one word (eight bytes). Obj0 is the stack slot we're trying to
1259 // ----------------------------------
1260 // | BP | Obj0 | Obj1 | ... | ObjN |
1261 // ----------------------------------
1265 // A is the incoming stack pointer.
1266 // (B - A) is the local area offset (-8 for x86-64) [1]
1267 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1269 // |(E - B)| is the StackSize (absolute value, positive). For a
1270 // stack that grown down, this works out to be (B - E). [3]
1272 // E is also the value of %rsp after stack has been set up, and we
1273 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1274 // (C - E) == (C - A) - (B - A) + (B - E)
1275 // { Using [1], [2] and [3] above }
1276 // == getObjectOffset - LocalAreaOffset + StackSize
1279 // Get the Offset from the StackPointer
1280 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1282 return Offset + StackSize;
1284 // Simplified from getFrameIndexReference keeping only StackPointer cases
1285 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1287 unsigned &FrameReg) const {
1288 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1290 FrameReg = TRI->getStackRegister();
1291 return getFrameIndexOffsetFromSP(MF, FI);
1294 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1295 MachineFunction &MF, const TargetRegisterInfo *TRI,
1296 std::vector<CalleeSavedInfo> &CSI) const {
1297 MachineFrameInfo *MFI = MF.getFrameInfo();
1298 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1300 unsigned CalleeSavedFrameSize = 0;
1301 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1304 // emitPrologue always spills frame register the first thing.
1305 SpillSlotOffset -= SlotSize;
1306 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1308 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1309 // the frame register, we can delete it from CSI list and not have to worry
1310 // about avoiding it later.
1311 unsigned FPReg = TRI->getFrameRegister(MF);
1312 for (unsigned i = 0; i < CSI.size(); ++i) {
1313 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1314 CSI.erase(CSI.begin() + i);
1320 // Assign slots for GPRs. It increases frame size.
1321 for (unsigned i = CSI.size(); i != 0; --i) {
1322 unsigned Reg = CSI[i - 1].getReg();
1324 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1327 SpillSlotOffset -= SlotSize;
1328 CalleeSavedFrameSize += SlotSize;
1330 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1331 CSI[i - 1].setFrameIdx(SlotIndex);
1334 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1336 // Assign slots for XMMs.
1337 for (unsigned i = CSI.size(); i != 0; --i) {
1338 unsigned Reg = CSI[i - 1].getReg();
1339 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1342 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1344 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1346 SpillSlotOffset -= RC->getSize();
1348 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1349 CSI[i - 1].setFrameIdx(SlotIndex);
1350 MFI->ensureMaxAlignment(RC->getAlignment());
1356 bool X86FrameLowering::spillCalleeSavedRegisters(
1357 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1358 const std::vector<CalleeSavedInfo> &CSI,
1359 const TargetRegisterInfo *TRI) const {
1360 DebugLoc DL = MBB.findDebugLoc(MI);
1362 // Push GPRs. It increases frame size.
1363 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1364 for (unsigned i = CSI.size(); i != 0; --i) {
1365 unsigned Reg = CSI[i - 1].getReg();
1367 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1369 // Add the callee-saved register as live-in. It's killed at the spill.
1372 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1373 .setMIFlag(MachineInstr::FrameSetup);
1376 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1377 // It can be done by spilling XMMs to stack frame.
1378 for (unsigned i = CSI.size(); i != 0; --i) {
1379 unsigned Reg = CSI[i-1].getReg();
1380 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1382 // Add the callee-saved register as live-in. It's killed at the spill.
1384 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1386 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1389 MI->setFlag(MachineInstr::FrameSetup);
1396 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1397 MachineBasicBlock::iterator MI,
1398 const std::vector<CalleeSavedInfo> &CSI,
1399 const TargetRegisterInfo *TRI) const {
1403 DebugLoc DL = MBB.findDebugLoc(MI);
1405 // Reload XMMs from stack frame.
1406 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1407 unsigned Reg = CSI[i].getReg();
1408 if (X86::GR64RegClass.contains(Reg) ||
1409 X86::GR32RegClass.contains(Reg))
1412 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1413 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1417 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1418 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1419 unsigned Reg = CSI[i].getReg();
1420 if (!X86::GR64RegClass.contains(Reg) &&
1421 !X86::GR32RegClass.contains(Reg))
1424 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1429 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1430 BitVector &SavedRegs,
1431 RegScavenger *RS) const {
1432 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1434 MachineFrameInfo *MFI = MF.getFrameInfo();
1436 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1437 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1439 if (TailCallReturnAddrDelta < 0) {
1440 // create RETURNADDR area
1449 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1450 TailCallReturnAddrDelta - SlotSize, true);
1453 // Spill the BasePtr if it's used.
1454 if (TRI->hasBasePointer(MF))
1455 SavedRegs.set(TRI->getBaseRegister());
1459 HasNestArgument(const MachineFunction *MF) {
1460 const Function *F = MF->getFunction();
1461 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1463 if (I->hasNestAttr())
1469 /// GetScratchRegister - Get a temp register for performing work in the
1470 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1471 /// and the properties of the function either one or two registers will be
1472 /// needed. Set primary to true for the first register, false for the second.
1474 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1475 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1478 if (CallingConvention == CallingConv::HiPE) {
1480 return Primary ? X86::R14 : X86::R13;
1482 return Primary ? X86::EBX : X86::EDI;
1487 return Primary ? X86::R11 : X86::R12;
1489 return Primary ? X86::R11D : X86::R12D;
1492 bool IsNested = HasNestArgument(&MF);
1494 if (CallingConvention == CallingConv::X86_FastCall ||
1495 CallingConvention == CallingConv::Fast) {
1497 report_fatal_error("Segmented stacks does not support fastcall with "
1498 "nested function.");
1499 return Primary ? X86::EAX : X86::ECX;
1502 return Primary ? X86::EDX : X86::EAX;
1503 return Primary ? X86::ECX : X86::EAX;
1506 // The stack limit in the TCB is set to this many bytes above the actual stack
1508 static const uint64_t kSplitStackAvailable = 256;
1510 void X86FrameLowering::adjustForSegmentedStacks(
1511 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1512 MachineFrameInfo *MFI = MF.getFrameInfo();
1514 unsigned TlsReg, TlsOffset;
1517 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1518 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1519 "Scratch register is live-in");
1521 if (MF.getFunction()->isVarArg())
1522 report_fatal_error("Segmented stacks do not support vararg functions.");
1523 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1524 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1525 !STI.isTargetDragonFly())
1526 report_fatal_error("Segmented stacks not supported on this platform.");
1528 // Eventually StackSize will be calculated by a link-time pass; which will
1529 // also decide whether checking code needs to be injected into this particular
1531 StackSize = MFI->getStackSize();
1533 // Do not generate a prologue for functions with a stack of size zero
1537 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1538 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1539 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1540 bool IsNested = false;
1542 // We need to know if the function has a nest argument only in 64 bit mode.
1544 IsNested = HasNestArgument(&MF);
1546 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1547 // allocMBB needs to be last (terminating) instruction.
1549 for (MachineBasicBlock::livein_iterator i = PrologueMBB.livein_begin(),
1550 e = PrologueMBB.livein_end();
1552 allocMBB->addLiveIn(*i);
1553 checkMBB->addLiveIn(*i);
1557 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1559 MF.push_front(allocMBB);
1560 MF.push_front(checkMBB);
1562 // When the frame size is less than 256 we just compare the stack
1563 // boundary directly to the value of the stack pointer, per gcc.
1564 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1566 // Read the limit off the current stacklet off the stack_guard location.
1568 if (STI.isTargetLinux()) {
1570 TlsOffset = IsLP64 ? 0x70 : 0x40;
1571 } else if (STI.isTargetDarwin()) {
1573 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1574 } else if (STI.isTargetWin64()) {
1576 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1577 } else if (STI.isTargetFreeBSD()) {
1580 } else if (STI.isTargetDragonFly()) {
1582 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1584 report_fatal_error("Segmented stacks not supported on this platform.");
1587 if (CompareStackPointer)
1588 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1590 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1591 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1593 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1594 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1596 if (STI.isTargetLinux()) {
1599 } else if (STI.isTargetDarwin()) {
1601 TlsOffset = 0x48 + 90*4;
1602 } else if (STI.isTargetWin32()) {
1604 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1605 } else if (STI.isTargetDragonFly()) {
1607 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1608 } else if (STI.isTargetFreeBSD()) {
1609 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1611 report_fatal_error("Segmented stacks not supported on this platform.");
1614 if (CompareStackPointer)
1615 ScratchReg = X86::ESP;
1617 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1618 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1620 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1621 STI.isTargetDragonFly()) {
1622 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1623 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1624 } else if (STI.isTargetDarwin()) {
1626 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1627 unsigned ScratchReg2;
1629 if (CompareStackPointer) {
1630 // The primary scratch register is available for holding the TLS offset.
1631 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1632 SaveScratch2 = false;
1634 // Need to use a second register to hold the TLS offset
1635 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1637 // Unfortunately, with fastcc the second scratch register may hold an
1639 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1642 // If Scratch2 is live-in then it needs to be saved.
1643 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1644 "Scratch register is live-in and not saved");
1647 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1648 .addReg(ScratchReg2, RegState::Kill);
1650 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1652 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1654 .addReg(ScratchReg2).addImm(1).addReg(0)
1659 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1663 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1664 // It jumps to normal execution of the function body.
1665 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
1667 // On 32 bit we first push the arguments size and then the frame size. On 64
1668 // bit, we pass the stack frame size in r10 and the argument size in r11.
1670 // Functions with nested arguments use R10, so it needs to be saved across
1671 // the call to _morestack
1673 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1674 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1675 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1676 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1677 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1680 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1682 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1684 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1685 .addImm(X86FI->getArgumentStackSize());
1687 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1688 .addImm(X86FI->getArgumentStackSize());
1689 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1693 // __morestack is in libgcc
1694 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1695 // Under the large code model, we cannot assume that __morestack lives
1696 // within 2^31 bytes of the call site, so we cannot use pc-relative
1697 // addressing. We cannot perform the call via a temporary register,
1698 // as the rax register may be used to store the static chain, and all
1699 // other suitable registers may be either callee-save or used for
1700 // parameter passing. We cannot use the stack at this point either
1701 // because __morestack manipulates the stack directly.
1703 // To avoid these issues, perform an indirect call via a read-only memory
1704 // location containing the address.
1706 // This solution is not perfect, as it assumes that the .rodata section
1707 // is laid out within 2^31 bytes of each function body, but this seems
1708 // to be sufficient for JIT.
1709 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1713 .addExternalSymbol("__morestack_addr")
1715 MF.getMMI().setUsesMorestackAddr(true);
1718 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1719 .addExternalSymbol("__morestack");
1721 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1722 .addExternalSymbol("__morestack");
1726 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1728 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1730 allocMBB->addSuccessor(&PrologueMBB);
1732 checkMBB->addSuccessor(allocMBB);
1733 checkMBB->addSuccessor(&PrologueMBB);
1740 /// Erlang programs may need a special prologue to handle the stack size they
1741 /// might need at runtime. That is because Erlang/OTP does not implement a C
1742 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1743 /// (for more information see Eric Stenman's Ph.D. thesis:
1744 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1747 /// temp0 = sp - MaxStack
1748 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1752 /// call inc_stack # doubles the stack space
1753 /// temp0 = sp - MaxStack
1754 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1755 void X86FrameLowering::adjustForHiPEPrologue(
1756 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1757 MachineFrameInfo *MFI = MF.getFrameInfo();
1759 // HiPE-specific values
1760 const unsigned HipeLeafWords = 24;
1761 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1762 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1763 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1764 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1765 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1767 assert(STI.isTargetLinux() &&
1768 "HiPE prologue is only supported on Linux operating systems.");
1770 // Compute the largest caller's frame that is needed to fit the callees'
1771 // frames. This 'MaxStack' is computed from:
1773 // a) the fixed frame size, which is the space needed for all spilled temps,
1774 // b) outgoing on-stack parameter areas, and
1775 // c) the minimum stack space this function needs to make available for the
1776 // functions it calls (a tunable ABI property).
1777 if (MFI->hasCalls()) {
1778 unsigned MoreStackForCalls = 0;
1780 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1781 MBBI != MBBE; ++MBBI)
1782 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1787 // Get callee operand.
1788 const MachineOperand &MO = MI->getOperand(0);
1790 // Only take account of global function calls (no closures etc.).
1794 const Function *F = dyn_cast<Function>(MO.getGlobal());
1798 // Do not update 'MaxStack' for primitive and built-in functions
1799 // (encoded with names either starting with "erlang."/"bif_" or not
1800 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1801 // "_", such as the BIF "suspend_0") as they are executed on another
1803 if (F->getName().find("erlang.") != StringRef::npos ||
1804 F->getName().find("bif_") != StringRef::npos ||
1805 F->getName().find_first_of("._") == StringRef::npos)
1808 unsigned CalleeStkArity =
1809 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1810 if (HipeLeafWords - 1 > CalleeStkArity)
1811 MoreStackForCalls = std::max(MoreStackForCalls,
1812 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1814 MaxStack += MoreStackForCalls;
1817 // If the stack frame needed is larger than the guaranteed then runtime checks
1818 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1819 if (MaxStack > Guaranteed) {
1820 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1821 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1823 for (MachineBasicBlock::livein_iterator I = PrologueMBB.livein_begin(),
1824 E = PrologueMBB.livein_end();
1826 stackCheckMBB->addLiveIn(*I);
1827 incStackMBB->addLiveIn(*I);
1830 MF.push_front(incStackMBB);
1831 MF.push_front(stackCheckMBB);
1833 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1834 unsigned LEAop, CMPop, CALLop;
1838 LEAop = X86::LEA64r;
1839 CMPop = X86::CMP64rm;
1840 CALLop = X86::CALL64pcrel32;
1841 SPLimitOffset = 0x90;
1845 LEAop = X86::LEA32r;
1846 CMPop = X86::CMP32rm;
1847 CALLop = X86::CALLpcrel32;
1848 SPLimitOffset = 0x4c;
1851 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1852 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1853 "HiPE prologue scratch register is live-in");
1855 // Create new MBB for StackCheck:
1856 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1857 SPReg, false, -MaxStack);
1858 // SPLimitOffset is in a fixed heap location (pointed by BP).
1859 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1860 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1861 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
1863 // Create new MBB for IncStack:
1864 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1865 addExternalSymbol("inc_stack_0");
1866 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1867 SPReg, false, -MaxStack);
1868 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1869 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1870 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1872 stackCheckMBB->addSuccessor(&PrologueMBB, 99);
1873 stackCheckMBB->addSuccessor(incStackMBB, 1);
1874 incStackMBB->addSuccessor(&PrologueMBB, 99);
1875 incStackMBB->addSuccessor(incStackMBB, 1);
1882 void X86FrameLowering::
1883 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1884 MachineBasicBlock::iterator I) const {
1885 bool reserveCallFrame = hasReservedCallFrame(MF);
1886 unsigned Opcode = I->getOpcode();
1887 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1888 DebugLoc DL = I->getDebugLoc();
1889 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
1890 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
1893 if (!reserveCallFrame) {
1894 // If the stack pointer can be changed after prologue, turn the
1895 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1896 // adjcallstackdown instruction into 'add ESP, <amt>'
1900 // We need to keep the stack aligned properly. To do this, we round the
1901 // amount of space needed for the outgoing arguments up to the next
1902 // alignment boundary.
1903 unsigned StackAlign = getStackAlignment();
1904 Amount = RoundUpToAlignment(Amount, StackAlign);
1906 // Factor out the amount that gets handled inside the sequence
1907 // (Pushes of argument for frame setup, callee pops for frame destroy)
1908 Amount -= InternalAmt;
1911 // Add Amount to SP to destroy a frame, and subtract to setup.
1912 int Offset = isDestroy ? Amount : -Amount;
1913 BuildStackAdjustment(MBB, I, DL, Offset, /*InEpilogue=*/false);
1918 if (isDestroy && InternalAmt) {
1919 // If we are performing frame pointer elimination and if the callee pops
1920 // something off the stack pointer, add it back. We do this until we have
1921 // more advanced stack pointer tracking ability.
1922 // We are not tracking the stack pointer adjustment by the callee, so make
1923 // sure we restore the stack pointer immediately after the call, there may
1924 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1925 MachineBasicBlock::iterator B = MBB.begin();
1926 while (I != B && !std::prev(I)->isCall())
1928 BuildStackAdjustment(MBB, I, DL, -InternalAmt, /*InEpilogue=*/false);
1932 bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
1933 assert(MBB.getParent() && "Block is not attached to a function!");
1935 if (canUseLEAForSPInEpilogue(*MBB.getParent()))
1938 // If we cannot use LEA to adjust SP, we may need to use ADD, which
1939 // clobbers the EFLAGS. Check that none of the terminators reads the
1940 // EFLAGS, and if one uses it, conservatively assume this is not
1941 // safe to insert the epilogue here.
1942 return !terminatorsNeedFlagsAsInput(MBB);