1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/WinEHFuncInfo.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCSymbol.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Debug.h"
37 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
38 unsigned StackAlignOverride)
39 : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
40 STI.is64Bit() ? -8 : -4),
41 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
42 // Cache a bunch of frame-related predicates for this subtarget.
43 SlotSize = TRI->getSlotSize();
44 Is64Bit = STI.is64Bit();
45 IsLP64 = STI.isTarget64BitLP64();
46 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
47 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
48 StackPtr = TRI->getStackRegister();
51 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
52 return !MF.getFrameInfo()->hasVarSizedObjects() &&
53 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
56 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
57 /// call frame pseudos can be simplified. Having a FP, as in the default
58 /// implementation, is not sufficient here since we can't always use it.
59 /// Use a more nuanced condition.
61 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
62 return hasReservedCallFrame(MF) ||
63 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
64 TRI->hasBasePointer(MF);
67 // needsFrameIndexResolution - Do we need to perform FI resolution for
68 // this function. Normally, this is required only when the function
69 // has any stack objects. However, FI resolution actually has another job,
70 // not apparent from the title - it resolves callframesetup/destroy
71 // that were not simplified earlier.
72 // So, this is required for x86 functions that have push sequences even
73 // when there are no stack objects.
75 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
76 return MF.getFrameInfo()->hasStackObjects() ||
77 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
80 /// hasFP - Return true if the specified function should have a dedicated frame
81 /// pointer register. This is true if the function has variable sized allocas
82 /// or if frame pointer elimination is disabled.
83 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
84 const MachineFrameInfo *MFI = MF.getFrameInfo();
85 const MachineModuleInfo &MMI = MF.getMMI();
87 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
88 TRI->needsStackRealignment(MF) ||
89 MFI->hasVarSizedObjects() ||
90 MFI->isFrameAddressTaken() || MFI->hasOpaqueSPAdjustment() ||
91 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
92 MMI.callsUnwindInit() || MMI.hasEHFunclets() || MMI.callsEHReturn() ||
93 MFI->hasStackMap() || MFI->hasPatchPoint());
96 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
100 return X86::SUB64ri32;
103 return X86::SUB32ri8;
108 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
111 return X86::ADD64ri8;
112 return X86::ADD64ri32;
115 return X86::ADD32ri8;
120 static unsigned getSUBrrOpcode(unsigned isLP64) {
121 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
124 static unsigned getADDrrOpcode(unsigned isLP64) {
125 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
128 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
131 return X86::AND64ri8;
132 return X86::AND64ri32;
135 return X86::AND32ri8;
139 static unsigned getLEArOpcode(unsigned IsLP64) {
140 return IsLP64 ? X86::LEA64r : X86::LEA32r;
143 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
144 /// when it reaches the "return" instruction. We can then pop a stack object
145 /// to this register without worry about clobbering it.
146 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator &MBBI,
148 const TargetRegisterInfo *TRI,
150 const MachineFunction *MF = MBB.getParent();
151 const Function *F = MF->getFunction();
152 if (!F || MF->getMMI().callsEHReturn())
155 static const uint16_t CallerSavedRegs32Bit[] = {
156 X86::EAX, X86::EDX, X86::ECX, 0
159 static const uint16_t CallerSavedRegs64Bit[] = {
160 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
161 X86::R8, X86::R9, X86::R10, X86::R11, 0
164 unsigned Opc = MBBI->getOpcode();
171 case X86::TCRETURNdi:
172 case X86::TCRETURNri:
173 case X86::TCRETURNmi:
174 case X86::TCRETURNdi64:
175 case X86::TCRETURNri64:
176 case X86::TCRETURNmi64:
178 case X86::EH_RETURN64: {
179 SmallSet<uint16_t, 8> Uses;
180 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
181 MachineOperand &MO = MBBI->getOperand(i);
182 if (!MO.isReg() || MO.isDef())
184 unsigned Reg = MO.getReg();
187 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
191 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
193 if (!Uses.count(*CS))
201 static bool isEAXLiveIn(MachineFunction &MF) {
202 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
203 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
204 unsigned Reg = II->first;
206 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
207 Reg == X86::AH || Reg == X86::AL)
214 /// Check whether or not the terminators of \p MBB needs to read EFLAGS.
215 static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
216 for (const MachineInstr &MI : MBB.terminators()) {
217 bool BreakNext = false;
218 for (const MachineOperand &MO : MI.operands()) {
221 unsigned Reg = MO.getReg();
222 if (Reg != X86::EFLAGS)
225 // This terminator needs an eflag that is not defined
226 // by a previous terminator.
237 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
238 /// stack pointer by a constant value.
239 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
240 MachineBasicBlock::iterator &MBBI,
241 int64_t NumBytes, bool InEpilogue) const {
242 bool isSub = NumBytes < 0;
243 uint64_t Offset = isSub ? -NumBytes : NumBytes;
245 uint64_t Chunk = (1LL << 31) - 1;
246 DebugLoc DL = MBB.findDebugLoc(MBBI);
249 if (Offset > Chunk) {
250 // Rather than emit a long series of instructions for large offsets,
251 // load the offset into a register and do one sub/add
254 if (isSub && !isEAXLiveIn(*MBB.getParent()))
255 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
257 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
260 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
261 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
264 ? getSUBrrOpcode(Is64Bit)
265 : getADDrrOpcode(Is64Bit);
266 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
269 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
275 uint64_t ThisVal = std::min(Offset, Chunk);
276 if (ThisVal == (Is64Bit ? 8 : 4)) {
277 // Use push / pop instead.
279 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
280 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
283 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
284 : (Is64Bit ? X86::POP64r : X86::POP32r);
285 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
286 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
288 MI->setFlag(MachineInstr::FrameSetup);
290 MI->setFlag(MachineInstr::FrameDestroy);
296 MachineInstrBuilder MI = BuildStackAdjustment(
297 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue);
299 MI.setMIFlag(MachineInstr::FrameSetup);
301 MI.setMIFlag(MachineInstr::FrameDestroy);
307 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
308 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
309 int64_t Offset, bool InEpilogue) const {
310 assert(Offset != 0 && "zero offset stack adjustment requested");
312 // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
316 UseLEA = STI.useLeaForSP();
318 // If we can use LEA for SP but we shouldn't, check that none
319 // of the terminators uses the eflags. Otherwise we will insert
320 // a ADD that will redefine the eflags and break the condition.
321 // Alternatively, we could move the ADD, but this may not be possible
322 // and is an optimization anyway.
323 UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
324 if (UseLEA && !STI.useLeaForSP())
325 UseLEA = terminatorsNeedFlagsAsInput(MBB);
326 // If that assert breaks, that means we do not do the right thing
327 // in canUseAsEpilogue.
328 assert((UseLEA || !terminatorsNeedFlagsAsInput(MBB)) &&
329 "We shouldn't have allowed this insertion point");
332 MachineInstrBuilder MI;
334 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
335 TII.get(getLEArOpcode(Uses64BitFramePtr)),
337 StackPtr, false, Offset);
339 bool IsSub = Offset < 0;
340 uint64_t AbsOffset = IsSub ? -Offset : Offset;
341 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
342 : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
343 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
346 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
351 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
352 MachineBasicBlock::iterator &MBBI,
353 bool doMergeWithPrevious) const {
354 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
355 (!doMergeWithPrevious && MBBI == MBB.end()))
358 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
359 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
361 unsigned Opc = PI->getOpcode();
364 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
365 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
366 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
367 PI->getOperand(0).getReg() == StackPtr){
368 Offset += PI->getOperand(2).getImm();
370 if (!doMergeWithPrevious) MBBI = NI;
371 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
372 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
373 PI->getOperand(0).getReg() == StackPtr) {
374 Offset -= PI->getOperand(2).getImm();
376 if (!doMergeWithPrevious) MBBI = NI;
382 void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
383 MachineBasicBlock::iterator MBBI, DebugLoc DL,
384 MCCFIInstruction CFIInst) const {
385 MachineFunction &MF = *MBB.getParent();
386 unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
387 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
388 .addCFIIndex(CFIIndex);
392 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
393 MachineBasicBlock::iterator MBBI,
395 MachineFunction &MF = *MBB.getParent();
396 MachineFrameInfo *MFI = MF.getFrameInfo();
397 MachineModuleInfo &MMI = MF.getMMI();
398 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
400 // Add callee saved registers to move list.
401 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
402 if (CSI.empty()) return;
404 // Calculate offsets.
405 for (std::vector<CalleeSavedInfo>::const_iterator
406 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
407 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
408 unsigned Reg = I->getReg();
410 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
411 BuildCFI(MBB, MBBI, DL,
412 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
416 /// usesTheStack - This function checks if any of the users of EFLAGS
417 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
418 /// to use the stack, and if we don't adjust the stack we clobber the first
420 /// See X86InstrInfo::copyPhysReg.
421 static bool usesTheStack(const MachineFunction &MF) {
422 const MachineRegisterInfo &MRI = MF.getRegInfo();
424 for (MachineRegisterInfo::reg_instr_iterator
425 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
433 void X86FrameLowering::emitStackProbeCall(MachineFunction &MF,
434 MachineBasicBlock &MBB,
435 MachineBasicBlock::iterator MBBI,
437 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
441 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
443 CallOp = X86::CALLpcrel32;
447 if (STI.isTargetCygMing()) {
448 Symbol = "___chkstk_ms";
452 } else if (STI.isTargetCygMing())
457 MachineInstrBuilder CI;
459 // All current stack probes take AX and SP as input, clobber flags, and
460 // preserve all registers. x86_64 probes leave RSP unmodified.
461 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
462 // For the large code model, we have to call through a register. Use R11,
463 // as it is scratch in all supported calling conventions.
464 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
465 .addExternalSymbol(Symbol);
466 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
468 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
471 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
472 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
473 CI.addReg(AX, RegState::Implicit)
474 .addReg(SP, RegState::Implicit)
475 .addReg(AX, RegState::Define | RegState::Implicit)
476 .addReg(SP, RegState::Define | RegState::Implicit)
477 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
480 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
481 // themselves. It also does not clobber %rax so we can reuse it when
483 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
489 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
490 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
491 // and might require smaller successive adjustments.
492 const uint64_t Win64MaxSEHOffset = 128;
493 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
494 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
495 return SEHFrameOffset & -16;
498 // If we're forcing a stack realignment we can't rely on just the frame
499 // info, we need to know the ABI stack alignment as well in case we
500 // have a call out. Otherwise just make sure we have some alignment - we'll
501 // go with the minimum SlotSize.
502 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
503 const MachineFrameInfo *MFI = MF.getFrameInfo();
504 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
505 unsigned StackAlign = getStackAlignment();
506 if (MF.getFunction()->hasFnAttribute("stackrealign")) {
508 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
509 else if (MaxAlign < SlotSize)
515 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
516 MachineBasicBlock::iterator MBBI,
518 uint64_t MaxAlign) const {
519 uint64_t Val = -MaxAlign;
521 BuildMI(MBB, MBBI, DL, TII.get(getANDriOpcode(Uses64BitFramePtr, Val)),
525 .setMIFlag(MachineInstr::FrameSetup);
527 // The EFLAGS implicit def is dead.
528 MI->getOperand(3).setIsDead();
531 /// emitPrologue - Push callee-saved registers onto the stack, which
532 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
533 /// space for local variables. Also emit labels used by the exception handler to
534 /// generate the exception handling frames.
537 Here's a gist of what gets emitted:
539 ; Establish frame pointer, if needed
542 .cfi_def_cfa_offset 16
543 .cfi_offset %rbp, -16
546 .cfi_def_cfa_register %rbp
548 ; Spill general-purpose registers
549 [for all callee-saved GPRs]
552 .cfi_def_cfa_offset (offset from RETADDR)
555 ; If the required stack alignment > default stack alignment
556 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
557 ; of unknown size in the stack frame.
558 [if stack needs re-alignment]
561 ; Allocate space for locals
562 [if target is Windows and allocated space > 4096 bytes]
563 ; Windows needs special care for allocations larger
566 call ___chkstk_ms/___chkstk
572 .seh_stackalloc (size of XMM spill slots)
573 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
578 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
579 ; they may get spilled on any platform, if the current function
580 ; calls @llvm.eh.unwind.init
582 [for all callee-saved XMM registers]
583 movaps %<xmm reg>, -MMM(%rbp)
584 [for all callee-saved XMM registers]
585 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
586 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
588 [for all callee-saved XMM registers]
589 movaps %<xmm reg>, KKK(%rsp)
590 [for all callee-saved XMM registers]
591 .seh_savexmm %<xmm reg>, KKK
595 [if needs base pointer]
597 [if needs to restore base pointer]
602 [for all callee-saved registers]
603 .cfi_offset %<reg>, (offset from %rbp)
605 .cfi_def_cfa_offset (offset from RETADDR)
606 [for all callee-saved registers]
607 .cfi_offset %<reg>, (offset from %rsp)
610 - .seh directives are emitted only for Windows 64 ABI
611 - .cfi directives are emitted for all other ABIs
612 - for 32-bit code, substitute %e?? registers for %r??
615 void X86FrameLowering::emitPrologue(MachineFunction &MF,
616 MachineBasicBlock &MBB) const {
617 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
618 "MF used frame lowering for wrong subtarget");
619 MachineBasicBlock::iterator MBBI = MBB.begin();
620 MachineFrameInfo *MFI = MF.getFrameInfo();
621 const Function *Fn = MF.getFunction();
622 MachineModuleInfo &MMI = MF.getMMI();
623 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
624 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
625 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
626 bool HasFP = hasFP(MF);
627 bool IsWin64CC = STI.isCallingConvWin64(Fn->getCallingConv());
628 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
629 bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();
631 !IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
632 unsigned FramePtr = TRI->getFrameRegister(MF);
633 const unsigned MachineFramePtr =
634 STI.isTarget64BitILP32()
635 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
637 unsigned BasePtr = TRI->getBaseRegister();
640 // Add RETADDR move area to callee saved frame size.
641 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
642 if (TailCallReturnAddrDelta && IsWin64Prologue)
643 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
645 if (TailCallReturnAddrDelta < 0)
646 X86FI->setCalleeSavedFrameSize(
647 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
649 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
651 // The default stack probe size is 4096 if the function has no stackprobesize
653 unsigned StackProbeSize = 4096;
654 if (Fn->hasFnAttribute("stack-probe-size"))
655 Fn->getFnAttribute("stack-probe-size")
657 .getAsInteger(0, StackProbeSize);
659 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
660 // function, and use up to 128 bytes of stack space, don't have a frame
661 // pointer, calls, or dynamic alloca then we do not need to adjust the
662 // stack pointer (we fit in the Red Zone). We also check that we don't
663 // push and pop from the stack.
664 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
665 !TRI->needsStackRealignment(MF) &&
666 !MFI->hasVarSizedObjects() && // No dynamic alloca.
667 !MFI->adjustsStack() && // No calls.
668 !IsWin64CC && // Win64 has no Red Zone
669 !usesTheStack(MF) && // Don't push and pop.
670 !MF.shouldSplitStack()) { // Regular stack
671 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
672 if (HasFP) MinSize += SlotSize;
673 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
674 MFI->setStackSize(StackSize);
677 // Insert stack pointer adjustment for later moving of return addr. Only
678 // applies to tail call optimized functions where the callee argument stack
679 // size is bigger than the callers.
680 if (TailCallReturnAddrDelta < 0) {
681 BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
682 /*InEpilogue=*/false)
683 .setMIFlag(MachineInstr::FrameSetup);
686 // Mapping for machine moves:
688 // DST: VirtualFP AND
689 // SRC: VirtualFP => DW_CFA_def_cfa_offset
690 // ELSE => DW_CFA_def_cfa
692 // SRC: VirtualFP AND
693 // DST: Register => DW_CFA_def_cfa_register
696 // OFFSET < 0 => DW_CFA_offset_extended_sf
697 // REG < 64 => DW_CFA_offset + Reg
698 // ELSE => DW_CFA_offset_extended
700 uint64_t NumBytes = 0;
701 int stackGrowth = -SlotSize;
703 if (MBB.isEHFuncletEntry()) {
704 assert(STI.isOSWindows() && "funclets only supported on Windows");
706 // Set up the FramePtr and BasePtr physical registers using the address
707 // passed as EBP or RDX by the MSVC EH runtime.
710 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
711 .addReg(MachineFramePtr, RegState::Kill)
712 .setMIFlag(MachineInstr::FrameSetup);
713 // Reset EBP / ESI to something good.
714 MBBI = restoreWin32EHFrameAndBasePtr(MBB, MBBI, DL);
716 // FIXME: Add SEH directives.
718 // Immediately spill RDX into the home slot. The runtime cares about this.
719 unsigned RDX = Uses64BitFramePtr ? X86::RDX : X86::EDX;
720 // MOV64mr %rdx, 16(%rsp)
721 unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
722 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)),
725 .setMIFlag(MachineInstr::FrameSetup);
727 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r))
728 .addReg(MachineFramePtr, RegState::Kill)
729 .setMIFlag(MachineInstr::FrameSetup);
730 // MOV64rr %rdx, %rbp
731 unsigned MOVrr = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
732 BuildMI(MBB, MBBI, DL, TII.get(MOVrr), FramePtr)
734 .setMIFlag(MachineInstr::FrameSetup);
735 assert(!TRI->hasBasePointer(MF) &&
736 "x64 funclets with base ptrs not yet implemented");
739 // For EH funclets, only allocate enough space for outgoing calls.
740 NumBytes = MFI->getMaxCallFrameSize();
742 // Calculate required stack adjustment.
743 uint64_t FrameSize = StackSize - SlotSize;
744 // If required, include space for extra hidden slot for stashing base pointer.
745 if (X86FI->getRestoreBasePointer())
746 FrameSize += SlotSize;
748 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
750 // Callee-saved registers are pushed on stack before the stack is realigned.
751 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
752 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
754 // Get the offset of the stack slot for the EBP register, which is
755 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
756 // Update the frame offset adjustment.
757 MFI->setOffsetAdjustment(-NumBytes);
759 // Save EBP/RBP into the appropriate stack slot.
760 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
761 .addReg(MachineFramePtr, RegState::Kill)
762 .setMIFlag(MachineInstr::FrameSetup);
765 // Mark the place where EBP/RBP was saved.
766 // Define the current CFA rule to use the provided offset.
768 BuildCFI(MBB, MBBI, DL,
769 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
771 // Change the rule for the FramePtr to be an "offset" rule.
772 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
773 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
774 nullptr, DwarfFramePtr, 2 * stackGrowth));
778 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
780 .setMIFlag(MachineInstr::FrameSetup);
783 if (!IsWin64Prologue) {
784 // Update EBP with the new base value.
785 BuildMI(MBB, MBBI, DL,
786 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
789 .setMIFlag(MachineInstr::FrameSetup);
793 // Mark effective beginning of when frame pointer becomes valid.
794 // Define the current CFA to use the EBP/RBP register.
795 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
796 BuildCFI(MBB, MBBI, DL,
797 MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));
800 // Mark the FramePtr as live-in in every block.
801 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
802 I->addLiveIn(MachineFramePtr);
804 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
807 // Skip the callee-saved push instructions.
808 bool PushedRegs = false;
809 int StackOffset = 2 * stackGrowth;
811 while (MBBI != MBB.end() &&
812 MBBI->getFlag(MachineInstr::FrameSetup) &&
813 (MBBI->getOpcode() == X86::PUSH32r ||
814 MBBI->getOpcode() == X86::PUSH64r)) {
816 unsigned Reg = MBBI->getOperand(0).getReg();
819 if (!HasFP && NeedsDwarfCFI) {
820 // Mark callee-saved push instruction.
821 // Define the current CFA rule to use the provided offset.
823 BuildCFI(MBB, MBBI, DL,
824 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
825 StackOffset += stackGrowth;
829 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
830 MachineInstr::FrameSetup);
834 // Realign stack after we pushed callee-saved registers (so that we'll be
835 // able to calculate their offsets from the frame pointer).
836 // Don't do this for Win64, it needs to realign the stack after the prologue.
837 if (!IsWin64Prologue && TRI->needsStackRealignment(MF)) {
838 assert(HasFP && "There should be a frame pointer if stack is realigned.");
839 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
842 // If there is an SUB32ri of ESP immediately before this instruction, merge
843 // the two. This can be the case when tail call elimination is enabled and
844 // the callee has more arguments then the caller.
845 NumBytes -= mergeSPUpdates(MBB, MBBI, true);
847 // Adjust stack pointer: ESP -= numbytes.
849 // Windows and cygwin/mingw require a prologue helper routine when allocating
850 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
851 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
852 // stack and adjust the stack pointer in one go. The 64-bit version of
853 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
854 // responsible for adjusting the stack pointer. Touching the stack at 4K
855 // increments is necessary to ensure that the guard pages used by the OS
856 // virtual memory manager are allocated in correct sequence.
857 uint64_t AlignedNumBytes = NumBytes;
858 if (IsWin64Prologue && TRI->needsStackRealignment(MF))
859 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
860 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
861 // Check whether EAX is livein for this function.
862 bool isEAXAlive = isEAXLiveIn(MF);
865 // Sanity check that EAX is not livein for this function.
866 // It should not be, so throw an assert.
867 assert(!Is64Bit && "EAX is livein in x64 case!");
870 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
871 .addReg(X86::EAX, RegState::Kill)
872 .setMIFlag(MachineInstr::FrameSetup);
876 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
877 // Function prologue is responsible for adjusting the stack pointer.
878 if (isUInt<32>(NumBytes)) {
879 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
881 .setMIFlag(MachineInstr::FrameSetup);
882 } else if (isInt<32>(NumBytes)) {
883 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
885 .setMIFlag(MachineInstr::FrameSetup);
887 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
889 .setMIFlag(MachineInstr::FrameSetup);
892 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
893 // We'll also use 4 already allocated bytes for EAX.
894 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
895 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
896 .setMIFlag(MachineInstr::FrameSetup);
899 // Save a pointer to the MI where we set AX.
900 MachineBasicBlock::iterator SetRAX = MBBI;
903 // Call __chkstk, __chkstk_ms, or __alloca.
904 emitStackProbeCall(MF, MBB, MBBI, DL);
906 // Apply the frame setup flag to all inserted instrs.
907 for (; SetRAX != MBBI; ++SetRAX)
908 SetRAX->setFlag(MachineInstr::FrameSetup);
912 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
914 StackPtr, false, NumBytes - 4);
915 MI->setFlag(MachineInstr::FrameSetup);
916 MBB.insert(MBBI, MI);
918 } else if (NumBytes) {
919 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
922 if (NeedsWinCFI && NumBytes)
923 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
925 .setMIFlag(MachineInstr::FrameSetup);
927 int SEHFrameOffset = 0;
928 if (IsWin64Prologue && HasFP) {
929 SEHFrameOffset = calculateSetFPREG(NumBytes);
931 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
932 StackPtr, false, SEHFrameOffset);
934 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr).addReg(StackPtr);
937 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
939 .addImm(SEHFrameOffset)
940 .setMIFlag(MachineInstr::FrameSetup);
943 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
944 const MachineInstr *FrameInstr = &*MBBI;
949 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
950 if (X86::FR64RegClass.contains(Reg)) {
951 unsigned IgnoredFrameReg;
952 int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
953 Offset += SEHFrameOffset;
955 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
958 .setMIFlag(MachineInstr::FrameSetup);
965 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
966 .setMIFlag(MachineInstr::FrameSetup);
968 // Realign stack after we spilled callee-saved registers (so that we'll be
969 // able to calculate their offsets from the frame pointer).
970 // Win64 requires aligning the stack after the prologue.
971 if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
972 assert(HasFP && "There should be a frame pointer if stack is realigned.");
973 BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);
976 // If we need a base pointer, set it up here. It's whatever the value
977 // of the stack pointer is at this point. Any variable size objects
978 // will be allocated after this, so we can still use the base pointer
979 // to reference locals.
980 if (TRI->hasBasePointer(MF)) {
981 // Update the base pointer with the current stack pointer.
982 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
983 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
985 .setMIFlag(MachineInstr::FrameSetup);
986 if (X86FI->getRestoreBasePointer()) {
987 // Stash value of base pointer. Saving RSP instead of EBP shortens
988 // dependence chain. Used by SjLj EH.
989 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
990 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
991 FramePtr, true, X86FI->getRestoreBasePointerOffset())
993 .setMIFlag(MachineInstr::FrameSetup);
996 if (X86FI->getHasSEHFramePtrSave()) {
997 // Stash the value of the frame pointer relative to the base pointer for
998 // Win32 EH. This supports Win32 EH, which does the inverse of the above:
999 // it recovers the frame pointer from the base pointer rather than the
1000 // other way around.
1001 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1004 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
1005 assert(UsedReg == BasePtr);
1006 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1008 .setMIFlag(MachineInstr::FrameSetup);
1012 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1013 // Mark end of stack pointer adjustment.
1014 if (!HasFP && NumBytes) {
1015 // Define the current CFA rule to use the provided offset.
1017 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
1018 nullptr, -StackSize + stackGrowth));
1021 // Emit DWARF info specifying the offsets of the callee-saved registers.
1023 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1027 bool X86FrameLowering::canUseLEAForSPInEpilogue(
1028 const MachineFunction &MF) const {
1029 // We can't use LEA instructions for adjusting the stack pointer if this is a
1030 // leaf function in the Win64 ABI. Only ADD instructions may be used to
1031 // deallocate the stack.
1032 // This means that we can use LEA for SP in two situations:
1033 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1034 // 2. We *have* a frame pointer which means we are permitted to use LEA.
1035 return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1038 static bool isFuncletReturnInstr(MachineInstr *MI) {
1039 switch (MI->getOpcode()) {
1041 case X86::CATCHRET64:
1042 case X86::CLEANUPRET:
1043 case X86::CLEANUPRET64:
1048 llvm_unreachable("impossible");
1051 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
1052 MachineBasicBlock &MBB) const {
1053 const MachineFrameInfo *MFI = MF.getFrameInfo();
1054 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1055 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1057 if (MBBI != MBB.end())
1058 DL = MBBI->getDebugLoc();
1059 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1060 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1061 unsigned FramePtr = TRI->getFrameRegister(MF);
1062 unsigned MachineFramePtr =
1063 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1066 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1068 IsWin64Prologue && MF.getFunction()->needsUnwindTableEntry();
1070 // Get the number of bytes to allocate from the FrameInfo.
1071 uint64_t StackSize = MFI->getStackSize();
1072 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1073 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1074 uint64_t NumBytes = 0;
1076 if (isFuncletReturnInstr(MBBI)) {
1077 NumBytes = MFI->getMaxCallFrameSize();
1078 assert(hasFP(MF) && "win64 EH funclets without FP not yet implemented");
1081 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1082 MachineFramePtr).setMIFlag(MachineInstr::FrameDestroy);
1083 } else if (hasFP(MF)) {
1084 // Calculate required stack adjustment.
1085 uint64_t FrameSize = StackSize - SlotSize;
1086 NumBytes = FrameSize - CSSize;
1088 // Callee-saved registers were pushed on stack before the stack was
1090 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1091 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1094 BuildMI(MBB, MBBI, DL,
1095 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr)
1096 .setMIFlag(MachineInstr::FrameDestroy);
1098 NumBytes = StackSize - CSSize;
1100 uint64_t SEHStackAllocAmt = NumBytes;
1102 // Skip the callee-saved pop instructions.
1103 while (MBBI != MBB.begin()) {
1104 MachineBasicBlock::iterator PI = std::prev(MBBI);
1105 unsigned Opc = PI->getOpcode();
1107 if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1108 (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1109 Opc != X86::DBG_VALUE && !PI->isTerminator())
1114 MachineBasicBlock::iterator FirstCSPop = MBBI;
1116 if (MBBI != MBB.end())
1117 DL = MBBI->getDebugLoc();
1119 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1120 // instruction, merge the two instructions.
1121 if (NumBytes || MFI->hasVarSizedObjects())
1122 NumBytes += mergeSPUpdates(MBB, MBBI, true);
1124 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1125 // slot before popping them off! Same applies for the case, when stack was
1127 if (TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1128 if (TRI->needsStackRealignment(MF))
1130 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1131 uint64_t LEAAmount =
1132 IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1134 // There are only two legal forms of epilogue:
1135 // - add SEHAllocationSize, %rsp
1136 // - lea SEHAllocationSize(%FramePtr), %rsp
1138 // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1139 // However, we may use this sequence if we have a frame pointer because the
1140 // effects of the prologue can safely be undone.
1141 if (LEAAmount != 0) {
1142 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1143 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1144 FramePtr, false, LEAAmount);
1147 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1148 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1152 } else if (NumBytes) {
1153 // Adjust stack pointer back: ESP += numbytes.
1154 emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
1158 // Windows unwinder will not invoke function's exception handler if IP is
1159 // either in prologue or in epilogue. This behavior causes a problem when a
1160 // call immediately precedes an epilogue, because the return address points
1161 // into the epilogue. To cope with that, we insert an epilogue marker here,
1162 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1163 // final emitted code.
1165 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1167 // Add the return addr area delta back since we are not tail calling.
1168 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1169 assert(Offset >= 0 && "TCDelta should never be positive");
1171 MBBI = MBB.getFirstTerminator();
1173 // Check for possible merge with preceding ADD instruction.
1174 Offset += mergeSPUpdates(MBB, MBBI, true);
1175 emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
1179 // NOTE: this only has a subset of the full frame index logic. In
1180 // particular, the FI < 0 and AfterFPPop logic is handled in
1181 // X86RegisterInfo::eliminateFrameIndex, but not here. Possibly
1182 // (probably?) it should be moved into here.
1183 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1184 unsigned &FrameReg) const {
1185 const MachineFrameInfo *MFI = MF.getFrameInfo();
1187 // We can't calculate offset from frame pointer if the stack is realigned,
1188 // so enforce usage of stack/base pointer. The base pointer is used when we
1189 // have dynamic allocas in addition to dynamic realignment.
1190 if (TRI->hasBasePointer(MF))
1191 FrameReg = TRI->getBaseRegister();
1192 else if (TRI->needsStackRealignment(MF))
1193 FrameReg = TRI->getStackRegister();
1195 FrameReg = TRI->getFrameRegister(MF);
1197 // Offset will hold the offset from the stack pointer at function entry to the
1199 // We need to factor in additional offsets applied during the prologue to the
1200 // frame, base, and stack pointer depending on which is used.
1201 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1202 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1203 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1204 uint64_t StackSize = MFI->getStackSize();
1205 bool HasFP = hasFP(MF);
1206 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1207 int64_t FPDelta = 0;
1209 if (IsWin64Prologue) {
1210 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1212 // Calculate required stack adjustment.
1213 uint64_t FrameSize = StackSize - SlotSize;
1214 // If required, include space for extra hidden slot for stashing base pointer.
1215 if (X86FI->getRestoreBasePointer())
1216 FrameSize += SlotSize;
1217 uint64_t NumBytes = FrameSize - CSSize;
1219 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1220 if (FI && FI == X86FI->getFAIndex())
1221 return -SEHFrameOffset;
1223 // FPDelta is the offset from the "traditional" FP location of the old base
1224 // pointer followed by return address and the location required by the
1225 // restricted Win64 prologue.
1226 // Add FPDelta to all offsets below that go through the frame pointer.
1227 FPDelta = FrameSize - SEHFrameOffset;
1228 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1229 "FPDelta isn't aligned per the Win64 ABI!");
1233 if (TRI->hasBasePointer(MF)) {
1234 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1236 // Skip the saved EBP.
1237 return Offset + SlotSize + FPDelta;
1239 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1240 return Offset + StackSize;
1242 } else if (TRI->needsStackRealignment(MF)) {
1244 // Skip the saved EBP.
1245 return Offset + SlotSize + FPDelta;
1247 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1248 return Offset + StackSize;
1250 // FIXME: Support tail calls
1253 return Offset + StackSize;
1255 // Skip the saved EBP.
1258 // Skip the RETADDR move area
1259 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1260 if (TailCallReturnAddrDelta < 0)
1261 Offset -= TailCallReturnAddrDelta;
1264 return Offset + FPDelta;
1267 // Simplified from getFrameIndexReference keeping only StackPointer cases
1268 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1270 unsigned &FrameReg) const {
1271 const MachineFrameInfo *MFI = MF.getFrameInfo();
1272 // Does not include any dynamic realign.
1273 const uint64_t StackSize = MFI->getStackSize();
1276 // Note: LLVM arranges the stack as:
1277 // Args > Saved RetPC (<--FP) > CSRs > dynamic alignment (<--BP)
1278 // > "Stack Slots" (<--SP)
1279 // We can always address StackSlots from RSP. We can usually (unless
1280 // needsStackRealignment) address CSRs from RSP, but sometimes need to
1281 // address them from RBP. FixedObjects can be placed anywhere in the stack
1282 // frame depending on their specific requirements (i.e. we can actually
1283 // refer to arguments to the function which are stored in the *callers*
1284 // frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs
1285 // AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.
1287 assert(!TRI->hasBasePointer(MF) && "we don't handle this case");
1289 // We don't handle tail calls, and shouldn't be seeing them
1291 int TailCallReturnAddrDelta =
1292 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1293 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1297 // Fill in FrameReg output argument.
1298 FrameReg = TRI->getStackRegister();
1300 // This is how the math works out:
1302 // %rsp grows (i.e. gets lower) left to right. Each box below is
1303 // one word (eight bytes). Obj0 is the stack slot we're trying to
1306 // ----------------------------------
1307 // | BP | Obj0 | Obj1 | ... | ObjN |
1308 // ----------------------------------
1312 // A is the incoming stack pointer.
1313 // (B - A) is the local area offset (-8 for x86-64) [1]
1314 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1316 // |(E - B)| is the StackSize (absolute value, positive). For a
1317 // stack that grown down, this works out to be (B - E). [3]
1319 // E is also the value of %rsp after stack has been set up, and we
1320 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1321 // (C - E) == (C - A) - (B - A) + (B - E)
1322 // { Using [1], [2] and [3] above }
1323 // == getObjectOffset - LocalAreaOffset + StackSize
1326 // Get the Offset from the StackPointer
1327 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1329 return Offset + StackSize;
1332 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1333 MachineFunction &MF, const TargetRegisterInfo *TRI,
1334 std::vector<CalleeSavedInfo> &CSI) const {
1335 MachineFrameInfo *MFI = MF.getFrameInfo();
1336 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1338 unsigned CalleeSavedFrameSize = 0;
1339 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1342 // emitPrologue always spills frame register the first thing.
1343 SpillSlotOffset -= SlotSize;
1344 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1346 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1347 // the frame register, we can delete it from CSI list and not have to worry
1348 // about avoiding it later.
1349 unsigned FPReg = TRI->getFrameRegister(MF);
1350 for (unsigned i = 0; i < CSI.size(); ++i) {
1351 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1352 CSI.erase(CSI.begin() + i);
1358 // Assign slots for GPRs. It increases frame size.
1359 for (unsigned i = CSI.size(); i != 0; --i) {
1360 unsigned Reg = CSI[i - 1].getReg();
1362 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1365 SpillSlotOffset -= SlotSize;
1366 CalleeSavedFrameSize += SlotSize;
1368 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1369 CSI[i - 1].setFrameIdx(SlotIndex);
1372 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1374 // Assign slots for XMMs.
1375 for (unsigned i = CSI.size(); i != 0; --i) {
1376 unsigned Reg = CSI[i - 1].getReg();
1377 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1380 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1382 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1384 SpillSlotOffset -= RC->getSize();
1386 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1387 CSI[i - 1].setFrameIdx(SlotIndex);
1388 MFI->ensureMaxAlignment(RC->getAlignment());
1394 bool X86FrameLowering::spillCalleeSavedRegisters(
1395 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1396 const std::vector<CalleeSavedInfo> &CSI,
1397 const TargetRegisterInfo *TRI) const {
1398 DebugLoc DL = MBB.findDebugLoc(MI);
1400 // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
1401 // for us, and there are no XMM CSRs on Win32.
1402 if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
1405 // Push GPRs. It increases frame size.
1406 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1407 for (unsigned i = CSI.size(); i != 0; --i) {
1408 unsigned Reg = CSI[i - 1].getReg();
1410 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1412 // Add the callee-saved register as live-in. It's killed at the spill.
1415 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1416 .setMIFlag(MachineInstr::FrameSetup);
1419 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1420 // It can be done by spilling XMMs to stack frame.
1421 for (unsigned i = CSI.size(); i != 0; --i) {
1422 unsigned Reg = CSI[i-1].getReg();
1423 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1425 // Add the callee-saved register as live-in. It's killed at the spill.
1427 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1429 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1432 MI->setFlag(MachineInstr::FrameSetup);
1439 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1440 MachineBasicBlock::iterator MI,
1441 const std::vector<CalleeSavedInfo> &CSI,
1442 const TargetRegisterInfo *TRI) const {
1446 // Don't restore CSRs in 32-bit EH funclets. Matches
1447 // spillCalleeSavedRegisters.
1448 if (isFuncletReturnInstr(MI) && STI.is32Bit() && STI.isOSWindows())
1451 DebugLoc DL = MBB.findDebugLoc(MI);
1453 // Reload XMMs from stack frame.
1454 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1455 unsigned Reg = CSI[i].getReg();
1456 if (X86::GR64RegClass.contains(Reg) ||
1457 X86::GR32RegClass.contains(Reg))
1460 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1461 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1465 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1466 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1467 unsigned Reg = CSI[i].getReg();
1468 if (!X86::GR64RegClass.contains(Reg) &&
1469 !X86::GR32RegClass.contains(Reg))
1472 BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
1473 .setMIFlag(MachineInstr::FrameDestroy);
1478 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1479 BitVector &SavedRegs,
1480 RegScavenger *RS) const {
1481 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1483 MachineFrameInfo *MFI = MF.getFrameInfo();
1485 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1486 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1488 if (TailCallReturnAddrDelta < 0) {
1489 // create RETURNADDR area
1498 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1499 TailCallReturnAddrDelta - SlotSize, true);
1502 // Spill the BasePtr if it's used.
1503 if (TRI->hasBasePointer(MF)) {
1504 SavedRegs.set(TRI->getBaseRegister());
1506 // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1507 if (MF.getMMI().hasEHFunclets()) {
1508 int FI = MFI->CreateSpillStackObject(SlotSize, SlotSize);
1509 X86FI->setHasSEHFramePtrSave(true);
1510 X86FI->setSEHFramePtrSaveIndex(FI);
1516 HasNestArgument(const MachineFunction *MF) {
1517 const Function *F = MF->getFunction();
1518 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1520 if (I->hasNestAttr())
1526 /// GetScratchRegister - Get a temp register for performing work in the
1527 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1528 /// and the properties of the function either one or two registers will be
1529 /// needed. Set primary to true for the first register, false for the second.
1531 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1532 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1535 if (CallingConvention == CallingConv::HiPE) {
1537 return Primary ? X86::R14 : X86::R13;
1539 return Primary ? X86::EBX : X86::EDI;
1544 return Primary ? X86::R11 : X86::R12;
1546 return Primary ? X86::R11D : X86::R12D;
1549 bool IsNested = HasNestArgument(&MF);
1551 if (CallingConvention == CallingConv::X86_FastCall ||
1552 CallingConvention == CallingConv::Fast) {
1554 report_fatal_error("Segmented stacks does not support fastcall with "
1555 "nested function.");
1556 return Primary ? X86::EAX : X86::ECX;
1559 return Primary ? X86::EDX : X86::EAX;
1560 return Primary ? X86::ECX : X86::EAX;
1563 // The stack limit in the TCB is set to this many bytes above the actual stack
1565 static const uint64_t kSplitStackAvailable = 256;
1567 void X86FrameLowering::adjustForSegmentedStacks(
1568 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1569 MachineFrameInfo *MFI = MF.getFrameInfo();
1571 unsigned TlsReg, TlsOffset;
1574 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1575 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1576 "Scratch register is live-in");
1578 if (MF.getFunction()->isVarArg())
1579 report_fatal_error("Segmented stacks do not support vararg functions.");
1580 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1581 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1582 !STI.isTargetDragonFly())
1583 report_fatal_error("Segmented stacks not supported on this platform.");
1585 // Eventually StackSize will be calculated by a link-time pass; which will
1586 // also decide whether checking code needs to be injected into this particular
1588 StackSize = MFI->getStackSize();
1590 // Do not generate a prologue for functions with a stack of size zero
1594 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1595 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1596 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1597 bool IsNested = false;
1599 // We need to know if the function has a nest argument only in 64 bit mode.
1601 IsNested = HasNestArgument(&MF);
1603 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1604 // allocMBB needs to be last (terminating) instruction.
1606 for (const auto &LI : PrologueMBB.liveins()) {
1607 allocMBB->addLiveIn(LI);
1608 checkMBB->addLiveIn(LI);
1612 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1614 MF.push_front(allocMBB);
1615 MF.push_front(checkMBB);
1617 // When the frame size is less than 256 we just compare the stack
1618 // boundary directly to the value of the stack pointer, per gcc.
1619 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1621 // Read the limit off the current stacklet off the stack_guard location.
1623 if (STI.isTargetLinux()) {
1625 TlsOffset = IsLP64 ? 0x70 : 0x40;
1626 } else if (STI.isTargetDarwin()) {
1628 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1629 } else if (STI.isTargetWin64()) {
1631 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1632 } else if (STI.isTargetFreeBSD()) {
1635 } else if (STI.isTargetDragonFly()) {
1637 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1639 report_fatal_error("Segmented stacks not supported on this platform.");
1642 if (CompareStackPointer)
1643 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
1645 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
1646 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1648 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
1649 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1651 if (STI.isTargetLinux()) {
1654 } else if (STI.isTargetDarwin()) {
1656 TlsOffset = 0x48 + 90*4;
1657 } else if (STI.isTargetWin32()) {
1659 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1660 } else if (STI.isTargetDragonFly()) {
1662 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
1663 } else if (STI.isTargetFreeBSD()) {
1664 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1666 report_fatal_error("Segmented stacks not supported on this platform.");
1669 if (CompareStackPointer)
1670 ScratchReg = X86::ESP;
1672 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1673 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1675 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
1676 STI.isTargetDragonFly()) {
1677 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1678 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1679 } else if (STI.isTargetDarwin()) {
1681 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
1682 unsigned ScratchReg2;
1684 if (CompareStackPointer) {
1685 // The primary scratch register is available for holding the TLS offset.
1686 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1687 SaveScratch2 = false;
1689 // Need to use a second register to hold the TLS offset
1690 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
1692 // Unfortunately, with fastcc the second scratch register may hold an
1694 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1697 // If Scratch2 is live-in then it needs to be saved.
1698 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1699 "Scratch register is live-in and not saved");
1702 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1703 .addReg(ScratchReg2, RegState::Kill);
1705 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1707 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1709 .addReg(ScratchReg2).addImm(1).addReg(0)
1714 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1718 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1719 // It jumps to normal execution of the function body.
1720 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
1722 // On 32 bit we first push the arguments size and then the frame size. On 64
1723 // bit, we pass the stack frame size in r10 and the argument size in r11.
1725 // Functions with nested arguments use R10, so it needs to be saved across
1726 // the call to _morestack
1728 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
1729 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
1730 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
1731 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
1732 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
1735 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
1737 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
1739 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
1740 .addImm(X86FI->getArgumentStackSize());
1742 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1743 .addImm(X86FI->getArgumentStackSize());
1744 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1748 // __morestack is in libgcc
1749 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
1750 // Under the large code model, we cannot assume that __morestack lives
1751 // within 2^31 bytes of the call site, so we cannot use pc-relative
1752 // addressing. We cannot perform the call via a temporary register,
1753 // as the rax register may be used to store the static chain, and all
1754 // other suitable registers may be either callee-save or used for
1755 // parameter passing. We cannot use the stack at this point either
1756 // because __morestack manipulates the stack directly.
1758 // To avoid these issues, perform an indirect call via a read-only memory
1759 // location containing the address.
1761 // This solution is not perfect, as it assumes that the .rodata section
1762 // is laid out within 2^31 bytes of each function body, but this seems
1763 // to be sufficient for JIT.
1764 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
1768 .addExternalSymbol("__morestack_addr")
1770 MF.getMMI().setUsesMorestackAddr(true);
1773 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1774 .addExternalSymbol("__morestack");
1776 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1777 .addExternalSymbol("__morestack");
1781 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1783 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1785 allocMBB->addSuccessor(&PrologueMBB);
1787 checkMBB->addSuccessor(allocMBB);
1788 checkMBB->addSuccessor(&PrologueMBB);
1795 /// Erlang programs may need a special prologue to handle the stack size they
1796 /// might need at runtime. That is because Erlang/OTP does not implement a C
1797 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1798 /// (for more information see Eric Stenman's Ph.D. thesis:
1799 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1802 /// temp0 = sp - MaxStack
1803 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1807 /// call inc_stack # doubles the stack space
1808 /// temp0 = sp - MaxStack
1809 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1810 void X86FrameLowering::adjustForHiPEPrologue(
1811 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1812 MachineFrameInfo *MFI = MF.getFrameInfo();
1814 // HiPE-specific values
1815 const unsigned HipeLeafWords = 24;
1816 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1817 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1818 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1819 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1820 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1822 assert(STI.isTargetLinux() &&
1823 "HiPE prologue is only supported on Linux operating systems.");
1825 // Compute the largest caller's frame that is needed to fit the callees'
1826 // frames. This 'MaxStack' is computed from:
1828 // a) the fixed frame size, which is the space needed for all spilled temps,
1829 // b) outgoing on-stack parameter areas, and
1830 // c) the minimum stack space this function needs to make available for the
1831 // functions it calls (a tunable ABI property).
1832 if (MFI->hasCalls()) {
1833 unsigned MoreStackForCalls = 0;
1835 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1836 MBBI != MBBE; ++MBBI)
1837 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1842 // Get callee operand.
1843 const MachineOperand &MO = MI->getOperand(0);
1845 // Only take account of global function calls (no closures etc.).
1849 const Function *F = dyn_cast<Function>(MO.getGlobal());
1853 // Do not update 'MaxStack' for primitive and built-in functions
1854 // (encoded with names either starting with "erlang."/"bif_" or not
1855 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1856 // "_", such as the BIF "suspend_0") as they are executed on another
1858 if (F->getName().find("erlang.") != StringRef::npos ||
1859 F->getName().find("bif_") != StringRef::npos ||
1860 F->getName().find_first_of("._") == StringRef::npos)
1863 unsigned CalleeStkArity =
1864 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1865 if (HipeLeafWords - 1 > CalleeStkArity)
1866 MoreStackForCalls = std::max(MoreStackForCalls,
1867 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1869 MaxStack += MoreStackForCalls;
1872 // If the stack frame needed is larger than the guaranteed then runtime checks
1873 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1874 if (MaxStack > Guaranteed) {
1875 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1876 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1878 for (const auto &LI : PrologueMBB.liveins()) {
1879 stackCheckMBB->addLiveIn(LI);
1880 incStackMBB->addLiveIn(LI);
1883 MF.push_front(incStackMBB);
1884 MF.push_front(stackCheckMBB);
1886 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1887 unsigned LEAop, CMPop, CALLop;
1891 LEAop = X86::LEA64r;
1892 CMPop = X86::CMP64rm;
1893 CALLop = X86::CALL64pcrel32;
1894 SPLimitOffset = 0x90;
1898 LEAop = X86::LEA32r;
1899 CMPop = X86::CMP32rm;
1900 CALLop = X86::CALLpcrel32;
1901 SPLimitOffset = 0x4c;
1904 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1905 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1906 "HiPE prologue scratch register is live-in");
1908 // Create new MBB for StackCheck:
1909 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1910 SPReg, false, -MaxStack);
1911 // SPLimitOffset is in a fixed heap location (pointed by BP).
1912 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1913 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1914 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
1916 // Create new MBB for IncStack:
1917 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1918 addExternalSymbol("inc_stack_0");
1919 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1920 SPReg, false, -MaxStack);
1921 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1922 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1923 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
1925 stackCheckMBB->addSuccessor(&PrologueMBB, 99);
1926 stackCheckMBB->addSuccessor(incStackMBB, 1);
1927 incStackMBB->addSuccessor(&PrologueMBB, 99);
1928 incStackMBB->addSuccessor(incStackMBB, 1);
1935 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
1936 MachineBasicBlock::iterator MBBI, DebugLoc DL, int Offset) const {
1938 if (Offset % SlotSize)
1941 int NumPops = Offset / SlotSize;
1942 // This is only worth it if we have at most 2 pops.
1943 if (NumPops != 1 && NumPops != 2)
1946 // Handle only the trivial case where the adjustment directly follows
1947 // a call. This is the most common one, anyway.
1948 if (MBBI == MBB.begin())
1950 MachineBasicBlock::iterator Prev = std::prev(MBBI);
1951 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
1955 unsigned FoundRegs = 0;
1957 auto RegMask = Prev->getOperand(1);
1959 // Try to find up to NumPops free registers.
1960 for (auto Candidate : X86::GR32_NOREX_NOSPRegClass) {
1962 // Poor man's liveness:
1963 // Since we're immediately after a call, any register that is clobbered
1964 // by the call and not defined by it can be considered dead.
1965 if (!RegMask.clobbersPhysReg(Candidate))
1969 for (const MachineOperand &MO : Prev->implicit_operands()) {
1970 if (MO.isReg() && MO.isDef() && MO.getReg() == Candidate) {
1979 Regs[FoundRegs++] = Candidate;
1980 if (FoundRegs == (unsigned)NumPops)
1987 // If we found only one free register, but need two, reuse the same one twice.
1988 while (FoundRegs < (unsigned)NumPops)
1989 Regs[FoundRegs++] = Regs[0];
1991 for (int i = 0; i < NumPops; ++i)
1992 BuildMI(MBB, MBBI, DL,
1993 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
1998 void X86FrameLowering::
1999 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
2000 MachineBasicBlock::iterator I) const {
2001 bool reserveCallFrame = hasReservedCallFrame(MF);
2002 unsigned Opcode = I->getOpcode();
2003 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2004 DebugLoc DL = I->getDebugLoc();
2005 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
2006 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
2009 if (!reserveCallFrame) {
2010 // If the stack pointer can be changed after prologue, turn the
2011 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2012 // adjcallstackdown instruction into 'add ESP, <amt>'
2016 // We need to keep the stack aligned properly. To do this, we round the
2017 // amount of space needed for the outgoing arguments up to the next
2018 // alignment boundary.
2019 unsigned StackAlign = getStackAlignment();
2020 Amount = RoundUpToAlignment(Amount, StackAlign);
2022 // Factor out the amount that gets handled inside the sequence
2023 // (Pushes of argument for frame setup, callee pops for frame destroy)
2024 Amount -= InternalAmt;
2027 // Add Amount to SP to destroy a frame, and subtract to setup.
2028 int Offset = isDestroy ? Amount : -Amount;
2030 if (!(MF.getFunction()->optForMinSize() &&
2031 adjustStackWithPops(MBB, I, DL, Offset)))
2032 BuildStackAdjustment(MBB, I, DL, Offset, /*InEpilogue=*/false);
2038 if (isDestroy && InternalAmt) {
2039 // If we are performing frame pointer elimination and if the callee pops
2040 // something off the stack pointer, add it back. We do this until we have
2041 // more advanced stack pointer tracking ability.
2042 // We are not tracking the stack pointer adjustment by the callee, so make
2043 // sure we restore the stack pointer immediately after the call, there may
2044 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2045 MachineBasicBlock::iterator B = MBB.begin();
2046 while (I != B && !std::prev(I)->isCall())
2048 BuildStackAdjustment(MBB, I, DL, -InternalAmt, /*InEpilogue=*/false);
2052 bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
2053 assert(MBB.getParent() && "Block is not attached to a function!");
2055 if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2058 // If we cannot use LEA to adjust SP, we may need to use ADD, which
2059 // clobbers the EFLAGS. Check that none of the terminators reads the
2060 // EFLAGS, and if one uses it, conservatively assume this is not
2061 // safe to insert the epilogue here.
2062 return !terminatorsNeedFlagsAsInput(MBB);
2065 MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHFrameAndBasePtr(
2066 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
2067 DebugLoc DL) const {
2068 assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2069 assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2070 assert(STI.is32Bit() && !Uses64BitFramePtr &&
2071 "restoring EBP/ESI on non-32-bit target");
2073 MachineFunction &MF = *MBB.getParent();
2074 unsigned FramePtr = TRI->getFrameRegister(MF);
2075 unsigned BasePtr = TRI->getBaseRegister();
2076 MachineModuleInfo &MMI = MF.getMMI();
2077 const Function *Fn = MF.getFunction();
2078 WinEHFuncInfo &FuncInfo = MMI.getWinEHFuncInfo(Fn);
2079 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2080 MachineFrameInfo *MFI = MF.getFrameInfo();
2082 // FIXME: Don't set FrameSetup flag in catchret case.
2084 int FI = FuncInfo.EHRegNodeFrameIndex;
2086 int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2087 int EHRegSize = MFI->getObjectSize(FI);
2088 int EndOffset = -EHRegOffset - EHRegSize;
2089 assert(EndOffset >= 0 &&
2090 "end of registration object above normal EBP position!");
2091 if (UsedReg == FramePtr) {
2092 // ADD $offset, %ebp
2093 assert(UsedReg == FramePtr);
2094 unsigned ADDri = getADDriOpcode(false, EndOffset);
2095 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2098 .setMIFlag(MachineInstr::FrameSetup)
2102 assert(UsedReg == BasePtr);
2103 // LEA offset(%ebp), %esi
2104 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2105 FramePtr, false, EndOffset)
2106 .setMIFlag(MachineInstr::FrameSetup);
2107 // MOV32mr SavedEBPOffset(%esi), %ebp
2108 assert(X86FI->getHasSEHFramePtrSave());
2110 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2111 assert(UsedReg == BasePtr);
2112 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32mr)), UsedReg, true,
2115 .setMIFlag(MachineInstr::FrameSetup);