1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/Analysis/LibCallSemantics.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/WinEHFuncInfo.h"
28 #include "llvm/IR/DataLayout.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/Debug.h"
38 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
39 unsigned StackAlignOverride)
40 : TargetFrameLowering(StackGrowsDown, StackAlignOverride,
41 STI.is64Bit() ? -8 : -4),
42 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
43 // Cache a bunch of frame-related predicates for this subtarget.
44 SlotSize = TRI->getSlotSize();
45 Is64Bit = STI.is64Bit();
46 IsLP64 = STI.isTarget64BitLP64();
47 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
48 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();
49 StackPtr = TRI->getStackRegister();
52 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
53 return !MF.getFrameInfo()->hasVarSizedObjects() &&
54 !MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
57 /// canSimplifyCallFramePseudos - If there is a reserved call frame, the
58 /// call frame pseudos can be simplified. Having a FP, as in the default
59 /// implementation, is not sufficient here since we can't always use it.
60 /// Use a more nuanced condition.
62 X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {
63 return hasReservedCallFrame(MF) ||
64 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
65 TRI->hasBasePointer(MF);
68 // needsFrameIndexResolution - Do we need to perform FI resolution for
69 // this function. Normally, this is required only when the function
70 // has any stack objects. However, FI resolution actually has another job,
71 // not apparent from the title - it resolves callframesetup/destroy
72 // that were not simplified earlier.
73 // So, this is required for x86 functions that have push sequences even
74 // when there are no stack objects.
76 X86FrameLowering::needsFrameIndexResolution(const MachineFunction &MF) const {
77 return MF.getFrameInfo()->hasStackObjects() ||
78 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences();
81 /// hasFP - Return true if the specified function should have a dedicated frame
82 /// pointer register. This is true if the function has variable sized allocas
83 /// or if frame pointer elimination is disabled.
84 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
85 const MachineFrameInfo *MFI = MF.getFrameInfo();
86 const MachineModuleInfo &MMI = MF.getMMI();
88 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
89 TRI->needsStackRealignment(MF) ||
90 MFI->hasVarSizedObjects() ||
91 MFI->isFrameAddressTaken() || MFI->hasOpaqueSPAdjustment() ||
92 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
93 MMI.callsUnwindInit() || MMI.hasEHFunclets() || MMI.callsEHReturn() ||
94 MFI->hasStackMap() || MFI->hasPatchPoint());
97 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
100 return X86::SUB64ri8;
101 return X86::SUB64ri32;
104 return X86::SUB32ri8;
109 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
112 return X86::ADD64ri8;
113 return X86::ADD64ri32;
116 return X86::ADD32ri8;
121 static unsigned getSUBrrOpcode(unsigned isLP64) {
122 return isLP64 ? X86::SUB64rr : X86::SUB32rr;
125 static unsigned getADDrrOpcode(unsigned isLP64) {
126 return isLP64 ? X86::ADD64rr : X86::ADD32rr;
129 static unsigned getANDriOpcode(bool IsLP64, int64_t Imm) {
132 return X86::AND64ri8;
133 return X86::AND64ri32;
136 return X86::AND32ri8;
140 static unsigned getLEArOpcode(unsigned IsLP64) {
141 return IsLP64 ? X86::LEA64r : X86::LEA32r;
144 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
145 /// when it reaches the "return" instruction. We can then pop a stack object
146 /// to this register without worry about clobbering it.
147 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
148 MachineBasicBlock::iterator &MBBI,
149 const TargetRegisterInfo *TRI,
151 const MachineFunction *MF = MBB.getParent();
152 const Function *F = MF->getFunction();
153 if (!F || MF->getMMI().callsEHReturn())
156 static const uint16_t CallerSavedRegs32Bit[] = {
157 X86::EAX, X86::EDX, X86::ECX, 0
160 static const uint16_t CallerSavedRegs64Bit[] = {
161 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
162 X86::R8, X86::R9, X86::R10, X86::R11, 0
165 unsigned Opc = MBBI->getOpcode();
172 case X86::TCRETURNdi:
173 case X86::TCRETURNri:
174 case X86::TCRETURNmi:
175 case X86::TCRETURNdi64:
176 case X86::TCRETURNri64:
177 case X86::TCRETURNmi64:
179 case X86::EH_RETURN64: {
180 SmallSet<uint16_t, 8> Uses;
181 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
182 MachineOperand &MO = MBBI->getOperand(i);
183 if (!MO.isReg() || MO.isDef())
185 unsigned Reg = MO.getReg();
188 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
192 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
194 if (!Uses.count(*CS))
202 static bool isEAXLiveIn(MachineFunction &MF) {
203 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
204 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
205 unsigned Reg = II->first;
207 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX ||
208 Reg == X86::AH || Reg == X86::AL)
215 /// Check whether or not the terminators of \p MBB needs to read EFLAGS.
216 static bool terminatorsNeedFlagsAsInput(const MachineBasicBlock &MBB) {
217 for (const MachineInstr &MI : MBB.terminators()) {
218 bool BreakNext = false;
219 for (const MachineOperand &MO : MI.operands()) {
222 unsigned Reg = MO.getReg();
223 if (Reg != X86::EFLAGS)
226 // This terminator needs an eflag that is not defined
227 // by a previous terminator.
238 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
239 /// stack pointer by a constant value.
240 void X86FrameLowering::emitSPUpdate(MachineBasicBlock &MBB,
241 MachineBasicBlock::iterator &MBBI,
242 int64_t NumBytes, bool InEpilogue) const {
243 bool isSub = NumBytes < 0;
244 uint64_t Offset = isSub ? -NumBytes : NumBytes;
246 uint64_t Chunk = (1LL << 31) - 1;
247 DebugLoc DL = MBB.findDebugLoc(MBBI);
250 if (Offset > Chunk) {
251 // Rather than emit a long series of instructions for large offsets,
252 // load the offset into a register and do one sub/add
255 if (isSub && !isEAXLiveIn(*MBB.getParent()))
256 Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);
258 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
261 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
262 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
265 ? getSUBrrOpcode(Is64Bit)
266 : getADDrrOpcode(Is64Bit);
267 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
270 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
276 uint64_t ThisVal = std::min(Offset, Chunk);
277 if (ThisVal == (Is64Bit ? 8 : 4)) {
278 // Use push / pop instead.
280 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
281 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
284 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
285 : (Is64Bit ? X86::POP64r : X86::POP32r);
286 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
287 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
289 MI->setFlag(MachineInstr::FrameSetup);
291 MI->setFlag(MachineInstr::FrameDestroy);
297 MachineInstrBuilder MI = BuildStackAdjustment(
298 MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue);
300 MI.setMIFlag(MachineInstr::FrameSetup);
302 MI.setMIFlag(MachineInstr::FrameDestroy);
308 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
309 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
310 int64_t Offset, bool InEpilogue) const {
311 assert(Offset != 0 && "zero offset stack adjustment requested");
313 // On Atom, using LEA to adjust SP is preferred, but using it in the epilogue
317 UseLEA = STI.useLeaForSP();
319 // If we can use LEA for SP but we shouldn't, check that none
320 // of the terminators uses the eflags. Otherwise we will insert
321 // a ADD that will redefine the eflags and break the condition.
322 // Alternatively, we could move the ADD, but this may not be possible
323 // and is an optimization anyway.
324 UseLEA = canUseLEAForSPInEpilogue(*MBB.getParent());
325 if (UseLEA && !STI.useLeaForSP())
326 UseLEA = terminatorsNeedFlagsAsInput(MBB);
327 // If that assert breaks, that means we do not do the right thing
328 // in canUseAsEpilogue.
329 assert((UseLEA || !terminatorsNeedFlagsAsInput(MBB)) &&
330 "We shouldn't have allowed this insertion point");
333 MachineInstrBuilder MI;
335 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
336 TII.get(getLEArOpcode(Uses64BitFramePtr)),
338 StackPtr, false, Offset);
340 bool IsSub = Offset < 0;
341 uint64_t AbsOffset = IsSub ? -Offset : Offset;
342 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
343 : getADDriOpcode(Uses64BitFramePtr, AbsOffset);
344 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
347 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
352 int X86FrameLowering::mergeSPUpdates(MachineBasicBlock &MBB,
353 MachineBasicBlock::iterator &MBBI,
354 bool doMergeWithPrevious) const {
355 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
356 (!doMergeWithPrevious && MBBI == MBB.end()))
359 MachineBasicBlock::iterator PI = doMergeWithPrevious ? std::prev(MBBI) : MBBI;
360 MachineBasicBlock::iterator NI = doMergeWithPrevious ? nullptr
362 unsigned Opc = PI->getOpcode();
365 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
366 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
367 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
368 PI->getOperand(0).getReg() == StackPtr){
369 Offset += PI->getOperand(2).getImm();
371 if (!doMergeWithPrevious) MBBI = NI;
372 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
373 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
374 PI->getOperand(0).getReg() == StackPtr) {
375 Offset -= PI->getOperand(2).getImm();
377 if (!doMergeWithPrevious) MBBI = NI;
383 void X86FrameLowering::BuildCFI(MachineBasicBlock &MBB,
384 MachineBasicBlock::iterator MBBI, DebugLoc DL,
385 MCCFIInstruction CFIInst) const {
386 MachineFunction &MF = *MBB.getParent();
387 unsigned CFIIndex = MF.getMMI().addFrameInst(CFIInst);
388 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
389 .addCFIIndex(CFIIndex);
393 X86FrameLowering::emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
394 MachineBasicBlock::iterator MBBI,
396 MachineFunction &MF = *MBB.getParent();
397 MachineFrameInfo *MFI = MF.getFrameInfo();
398 MachineModuleInfo &MMI = MF.getMMI();
399 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
401 // Add callee saved registers to move list.
402 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
403 if (CSI.empty()) return;
405 // Calculate offsets.
406 for (std::vector<CalleeSavedInfo>::const_iterator
407 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
408 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
409 unsigned Reg = I->getReg();
411 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
412 BuildCFI(MBB, MBBI, DL,
413 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
417 /// usesTheStack - This function checks if any of the users of EFLAGS
418 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
419 /// to use the stack, and if we don't adjust the stack we clobber the first
421 /// See X86InstrInfo::copyPhysReg.
422 static bool usesTheStack(const MachineFunction &MF) {
423 const MachineRegisterInfo &MRI = MF.getRegInfo();
425 for (MachineRegisterInfo::reg_instr_iterator
426 ri = MRI.reg_instr_begin(X86::EFLAGS), re = MRI.reg_instr_end();
434 MachineInstr *X86FrameLowering::emitStackProbe(MachineFunction &MF,
435 MachineBasicBlock &MBB,
436 MachineBasicBlock::iterator MBBI,
438 bool InProlog) const {
439 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
440 if (STI.isTargetWindowsCoreCLR()) {
442 return emitStackProbeInlineStub(MF, MBB, MBBI, DL, true);
444 return emitStackProbeInline(MF, MBB, MBBI, DL, false);
447 return emitStackProbeCall(MF, MBB, MBBI, DL, InProlog);
451 void X86FrameLowering::inlineStackProbe(MachineFunction &MF,
452 MachineBasicBlock &PrologMBB) const {
453 const StringRef ChkStkStubSymbol = "__chkstk_stub";
454 MachineInstr *ChkStkStub = nullptr;
456 for (MachineInstr &MI : PrologMBB) {
457 if (MI.isCall() && MI.getOperand(0).isSymbol() &&
458 ChkStkStubSymbol == MI.getOperand(0).getSymbolName()) {
464 if (ChkStkStub != nullptr) {
465 MachineBasicBlock::iterator MBBI = std::next(ChkStkStub->getIterator());
466 assert(std::prev(MBBI).operator==(ChkStkStub) &&
467 "MBBI expected after __chkstk_stub.");
468 DebugLoc DL = PrologMBB.findDebugLoc(MBBI);
469 emitStackProbeInline(MF, PrologMBB, MBBI, DL, true);
470 ChkStkStub->eraseFromParent();
474 MachineInstr *X86FrameLowering::emitStackProbeInline(
475 MachineFunction &MF, MachineBasicBlock &MBB,
476 MachineBasicBlock::iterator MBBI, DebugLoc DL, bool InProlog) const {
477 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
478 assert(STI.is64Bit() && "different expansion needed for 32 bit");
479 assert(STI.isTargetWindowsCoreCLR() && "custom expansion expects CoreCLR");
480 const TargetInstrInfo &TII = *STI.getInstrInfo();
481 const BasicBlock *LLVM_BB = MBB.getBasicBlock();
483 // RAX contains the number of bytes of desired stack adjustment.
484 // The handling here assumes this value has already been updated so as to
485 // maintain stack alignment.
487 // We need to exit with RSP modified by this amount and execute suitable
488 // page touches to notify the OS that we're growing the stack responsibly.
489 // All stack probing must be done without modifying RSP.
495 // Flags, TestReg = CopyReg - SizeReg
496 // FinalReg = !Flags.Ovf ? TestReg : ZeroReg
497 // LimitReg = gs magic thread env access
498 // if FinalReg >= LimitReg goto ContinueMBB
500 // RoundReg = page address of FinalReg
502 // LoopReg = PHI(LimitReg,ProbeReg)
503 // ProbeReg = LoopReg - PageSize
505 // if (ProbeReg > RoundReg) goto LoopMBB
508 // [rest of original MBB]
510 // Set up the new basic blocks
511 MachineBasicBlock *RoundMBB = MF.CreateMachineBasicBlock(LLVM_BB);
512 MachineBasicBlock *LoopMBB = MF.CreateMachineBasicBlock(LLVM_BB);
513 MachineBasicBlock *ContinueMBB = MF.CreateMachineBasicBlock(LLVM_BB);
515 MachineFunction::iterator MBBIter = std::next(MBB.getIterator());
516 MF.insert(MBBIter, RoundMBB);
517 MF.insert(MBBIter, LoopMBB);
518 MF.insert(MBBIter, ContinueMBB);
520 // Split MBB and move the tail portion down to ContinueMBB.
521 MachineBasicBlock::iterator BeforeMBBI = std::prev(MBBI);
522 ContinueMBB->splice(ContinueMBB->begin(), &MBB, MBBI, MBB.end());
523 ContinueMBB->transferSuccessorsAndUpdatePHIs(&MBB);
525 // Some useful constants
526 const int64_t ThreadEnvironmentStackLimit = 0x10;
527 const int64_t PageSize = 0x1000;
528 const int64_t PageMask = ~(PageSize - 1);
530 // Registers we need. For the normal case we use virtual
531 // registers. For the prolog expansion we use RAX, RCX and RDX.
532 MachineRegisterInfo &MRI = MF.getRegInfo();
533 const TargetRegisterClass *RegClass = &X86::GR64RegClass;
535 SizeReg = InProlog ? X86::RAX : MRI.createVirtualRegister(RegClass),
536 ZeroReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass),
537 CopyReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
538 TestReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
539 FinalReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
540 RoundedReg = InProlog ? X86::RDX : MRI.createVirtualRegister(RegClass),
541 LimitReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass),
542 JoinReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass),
543 ProbeReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass);
545 // SP-relative offsets where we can save RCX and RDX.
546 int64_t RCXShadowSlot = 0;
547 int64_t RDXShadowSlot = 0;
549 // If inlining in the prolog, save RCX and RDX.
550 // Future optimization: don't save or restore if not live in.
552 // Compute the offsets. We need to account for things already
553 // pushed onto the stack at this point: return address, frame
554 // pointer (if used), and callee saves.
555 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
556 const int64_t CalleeSaveSize = X86FI->getCalleeSavedFrameSize();
557 const bool HasFP = hasFP(MF);
558 RCXShadowSlot = 8 + CalleeSaveSize + (HasFP ? 8 : 0);
559 RDXShadowSlot = RCXShadowSlot + 8;
561 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
564 addRegOffset(BuildMI(&MBB, DL, TII.get(X86::MOV64mr)), X86::RSP, false,
568 // Not in the prolog. Copy RAX to a virtual reg.
569 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
572 // Add code to MBB to check for overflow and set the new target stack pointer
574 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg)
575 .addReg(ZeroReg, RegState::Undef)
576 .addReg(ZeroReg, RegState::Undef);
577 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
578 BuildMI(&MBB, DL, TII.get(X86::SUB64rr), TestReg)
581 BuildMI(&MBB, DL, TII.get(X86::CMOVB64rr), FinalReg)
585 // FinalReg now holds final stack pointer value, or zero if
586 // allocation would overflow. Compare against the current stack
587 // limit from the thread environment block. Note this limit is the
588 // lowest touched page on the stack, not the point at which the OS
589 // will cause an overflow exception, so this is just an optimization
590 // to avoid unnecessarily touching pages that are below the current
591 // SP but already commited to the stack by the OS.
592 BuildMI(&MBB, DL, TII.get(X86::MOV64rm), LimitReg)
596 .addImm(ThreadEnvironmentStackLimit)
598 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
599 // Jump if the desired stack pointer is at or above the stack limit.
600 BuildMI(&MBB, DL, TII.get(X86::JAE_1)).addMBB(ContinueMBB);
602 // Add code to roundMBB to round the final stack pointer to a page boundary.
603 BuildMI(RoundMBB, DL, TII.get(X86::AND64ri32), RoundedReg)
606 BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
608 // LimitReg now holds the current stack limit, RoundedReg page-rounded
609 // final RSP value. Add code to loopMBB to decrement LimitReg page-by-page
610 // and probe until we reach RoundedReg.
612 BuildMI(LoopMBB, DL, TII.get(X86::PHI), JoinReg)
619 addRegOffset(BuildMI(LoopMBB, DL, TII.get(X86::LEA64r), ProbeReg), JoinReg,
622 // Probe by storing a byte onto the stack.
623 BuildMI(LoopMBB, DL, TII.get(X86::MOV8mi))
630 BuildMI(LoopMBB, DL, TII.get(X86::CMP64rr))
633 BuildMI(LoopMBB, DL, TII.get(X86::JNE_1)).addMBB(LoopMBB);
635 MachineBasicBlock::iterator ContinueMBBI = ContinueMBB->getFirstNonPHI();
637 // If in prolog, restore RDX and RCX.
639 addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::MOV64rm),
641 X86::RSP, false, RCXShadowSlot);
642 addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::MOV64rm),
644 X86::RSP, false, RDXShadowSlot);
647 // Now that the probing is done, add code to continueMBB to update
648 // the stack pointer for real.
649 BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
653 // Add the control flow edges we need.
654 MBB.addSuccessor(ContinueMBB);
655 MBB.addSuccessor(RoundMBB);
656 RoundMBB->addSuccessor(LoopMBB);
657 LoopMBB->addSuccessor(ContinueMBB);
658 LoopMBB->addSuccessor(LoopMBB);
660 // Mark all the instructions added to the prolog as frame setup.
662 for (++BeforeMBBI; BeforeMBBI != MBB.end(); ++BeforeMBBI) {
663 BeforeMBBI->setFlag(MachineInstr::FrameSetup);
665 for (MachineInstr &MI : *RoundMBB) {
666 MI.setFlag(MachineInstr::FrameSetup);
668 for (MachineInstr &MI : *LoopMBB) {
669 MI.setFlag(MachineInstr::FrameSetup);
671 for (MachineBasicBlock::iterator CMBBI = ContinueMBB->begin();
672 CMBBI != ContinueMBBI; ++CMBBI) {
673 CMBBI->setFlag(MachineInstr::FrameSetup);
677 // Possible TODO: physreg liveness for InProlog case.
682 MachineInstr *X86FrameLowering::emitStackProbeCall(
683 MachineFunction &MF, MachineBasicBlock &MBB,
684 MachineBasicBlock::iterator MBBI, DebugLoc DL, bool InProlog) const {
685 bool IsLargeCodeModel = MF.getTarget().getCodeModel() == CodeModel::Large;
689 CallOp = IsLargeCodeModel ? X86::CALL64r : X86::CALL64pcrel32;
691 CallOp = X86::CALLpcrel32;
695 if (STI.isTargetCygMing()) {
696 Symbol = "___chkstk_ms";
700 } else if (STI.isTargetCygMing())
705 MachineInstrBuilder CI;
706 MachineBasicBlock::iterator ExpansionMBBI = std::prev(MBBI);
708 // All current stack probes take AX and SP as input, clobber flags, and
709 // preserve all registers. x86_64 probes leave RSP unmodified.
710 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
711 // For the large code model, we have to call through a register. Use R11,
712 // as it is scratch in all supported calling conventions.
713 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
714 .addExternalSymbol(Symbol);
715 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
717 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addExternalSymbol(Symbol);
720 unsigned AX = Is64Bit ? X86::RAX : X86::EAX;
721 unsigned SP = Is64Bit ? X86::RSP : X86::ESP;
722 CI.addReg(AX, RegState::Implicit)
723 .addReg(SP, RegState::Implicit)
724 .addReg(AX, RegState::Define | RegState::Implicit)
725 .addReg(SP, RegState::Define | RegState::Implicit)
726 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
729 // MSVC x64's __chkstk and cygwin/mingw's ___chkstk_ms do not adjust %rsp
730 // themselves. It also does not clobber %rax so we can reuse it when
732 BuildMI(MBB, MBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
738 // Apply the frame setup flag to all inserted instrs.
739 for (++ExpansionMBBI; ExpansionMBBI != MBBI; ++ExpansionMBBI)
740 ExpansionMBBI->setFlag(MachineInstr::FrameSetup);
746 MachineInstr *X86FrameLowering::emitStackProbeInlineStub(
747 MachineFunction &MF, MachineBasicBlock &MBB,
748 MachineBasicBlock::iterator MBBI, DebugLoc DL, bool InProlog) const {
750 assert(InProlog && "ChkStkStub called outside prolog!");
752 MachineInstrBuilder CI = BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
753 .addExternalSymbol("__chkstk_stub");
758 static unsigned calculateSetFPREG(uint64_t SPAdjust) {
759 // Win64 ABI has a less restrictive limitation of 240; 128 works equally well
760 // and might require smaller successive adjustments.
761 const uint64_t Win64MaxSEHOffset = 128;
762 uint64_t SEHFrameOffset = std::min(SPAdjust, Win64MaxSEHOffset);
763 // Win64 ABI requires 16-byte alignment for the UWOP_SET_FPREG opcode.
764 return SEHFrameOffset & -16;
767 // If we're forcing a stack realignment we can't rely on just the frame
768 // info, we need to know the ABI stack alignment as well in case we
769 // have a call out. Otherwise just make sure we have some alignment - we'll
770 // go with the minimum SlotSize.
771 uint64_t X86FrameLowering::calculateMaxStackAlign(const MachineFunction &MF) const {
772 const MachineFrameInfo *MFI = MF.getFrameInfo();
773 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
774 unsigned StackAlign = getStackAlignment();
775 if (MF.getFunction()->hasFnAttribute("stackrealign")) {
777 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
778 else if (MaxAlign < SlotSize)
784 void X86FrameLowering::BuildStackAlignAND(MachineBasicBlock &MBB,
785 MachineBasicBlock::iterator MBBI,
786 DebugLoc DL, unsigned Reg,
787 uint64_t MaxAlign) const {
788 uint64_t Val = -MaxAlign;
789 unsigned AndOp = getANDriOpcode(Uses64BitFramePtr, Val);
790 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
793 .setMIFlag(MachineInstr::FrameSetup);
795 // The EFLAGS implicit def is dead.
796 MI->getOperand(3).setIsDead();
799 /// emitPrologue - Push callee-saved registers onto the stack, which
800 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
801 /// space for local variables. Also emit labels used by the exception handler to
802 /// generate the exception handling frames.
805 Here's a gist of what gets emitted:
807 ; Establish frame pointer, if needed
810 .cfi_def_cfa_offset 16
811 .cfi_offset %rbp, -16
814 .cfi_def_cfa_register %rbp
816 ; Spill general-purpose registers
817 [for all callee-saved GPRs]
820 .cfi_def_cfa_offset (offset from RETADDR)
823 ; If the required stack alignment > default stack alignment
824 ; rsp needs to be re-aligned. This creates a "re-alignment gap"
825 ; of unknown size in the stack frame.
826 [if stack needs re-alignment]
829 ; Allocate space for locals
830 [if target is Windows and allocated space > 4096 bytes]
831 ; Windows needs special care for allocations larger
834 call ___chkstk_ms/___chkstk
840 .seh_stackalloc (size of XMM spill slots)
841 .seh_setframe %rbp, SEHFrameOffset ; = size of all spill slots
846 ; Note, that while only Windows 64 ABI specifies XMMs as callee-preserved,
847 ; they may get spilled on any platform, if the current function
848 ; calls @llvm.eh.unwind.init
850 [for all callee-saved XMM registers]
851 movaps %<xmm reg>, -MMM(%rbp)
852 [for all callee-saved XMM registers]
853 .seh_savexmm %<xmm reg>, (-MMM + SEHFrameOffset)
854 ; i.e. the offset relative to (%rbp - SEHFrameOffset)
856 [for all callee-saved XMM registers]
857 movaps %<xmm reg>, KKK(%rsp)
858 [for all callee-saved XMM registers]
859 .seh_savexmm %<xmm reg>, KKK
863 [if needs base pointer]
865 [if needs to restore base pointer]
870 [for all callee-saved registers]
871 .cfi_offset %<reg>, (offset from %rbp)
873 .cfi_def_cfa_offset (offset from RETADDR)
874 [for all callee-saved registers]
875 .cfi_offset %<reg>, (offset from %rsp)
878 - .seh directives are emitted only for Windows 64 ABI
879 - .cfi directives are emitted for all other ABIs
880 - for 32-bit code, substitute %e?? registers for %r??
883 void X86FrameLowering::emitPrologue(MachineFunction &MF,
884 MachineBasicBlock &MBB) const {
885 assert(&STI == &MF.getSubtarget<X86Subtarget>() &&
886 "MF used frame lowering for wrong subtarget");
887 MachineBasicBlock::iterator MBBI = MBB.begin();
888 MachineFrameInfo *MFI = MF.getFrameInfo();
889 const Function *Fn = MF.getFunction();
890 MachineModuleInfo &MMI = MF.getMMI();
891 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
892 uint64_t MaxAlign = calculateMaxStackAlign(MF); // Desired stack alignment.
893 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
894 bool IsFunclet = MBB.isEHFuncletEntry();
897 classifyEHPersonality(Fn->getPersonalityFn()) == EHPersonality::CoreCLR;
898 bool HasFP = hasFP(MF);
899 bool IsWin64CC = STI.isCallingConvWin64(Fn->getCallingConv());
900 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
901 bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();
903 !IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
904 unsigned FramePtr = TRI->getFrameRegister(MF);
905 const unsigned MachineFramePtr =
906 STI.isTarget64BitILP32()
907 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
909 unsigned BasePtr = TRI->getBaseRegister();
911 // Debug location must be unknown since the first debug location is used
912 // to determine the end of the prologue.
915 // Add RETADDR move area to callee saved frame size.
916 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
917 if (TailCallReturnAddrDelta && IsWin64Prologue)
918 report_fatal_error("Can't handle guaranteed tail call under win64 yet");
920 if (TailCallReturnAddrDelta < 0)
921 X86FI->setCalleeSavedFrameSize(
922 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
924 bool UseStackProbe = (STI.isOSWindows() && !STI.isTargetMachO());
926 // The default stack probe size is 4096 if the function has no stackprobesize
928 unsigned StackProbeSize = 4096;
929 if (Fn->hasFnAttribute("stack-probe-size"))
930 Fn->getFnAttribute("stack-probe-size")
932 .getAsInteger(0, StackProbeSize);
934 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
935 // function, and use up to 128 bytes of stack space, don't have a frame
936 // pointer, calls, or dynamic alloca then we do not need to adjust the
937 // stack pointer (we fit in the Red Zone). We also check that we don't
938 // push and pop from the stack.
939 if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&
940 !TRI->needsStackRealignment(MF) &&
941 !MFI->hasVarSizedObjects() && // No dynamic alloca.
942 !MFI->adjustsStack() && // No calls.
943 !IsWin64CC && // Win64 has no Red Zone
944 !usesTheStack(MF) && // Don't push and pop.
945 !MF.shouldSplitStack()) { // Regular stack
946 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
947 if (HasFP) MinSize += SlotSize;
948 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
949 MFI->setStackSize(StackSize);
952 // Insert stack pointer adjustment for later moving of return addr. Only
953 // applies to tail call optimized functions where the callee argument stack
954 // size is bigger than the callers.
955 if (TailCallReturnAddrDelta < 0) {
956 BuildStackAdjustment(MBB, MBBI, DL, TailCallReturnAddrDelta,
957 /*InEpilogue=*/false)
958 .setMIFlag(MachineInstr::FrameSetup);
961 // Mapping for machine moves:
963 // DST: VirtualFP AND
964 // SRC: VirtualFP => DW_CFA_def_cfa_offset
965 // ELSE => DW_CFA_def_cfa
967 // SRC: VirtualFP AND
968 // DST: Register => DW_CFA_def_cfa_register
971 // OFFSET < 0 => DW_CFA_offset_extended_sf
972 // REG < 64 => DW_CFA_offset + Reg
973 // ELSE => DW_CFA_offset_extended
975 uint64_t NumBytes = 0;
976 int stackGrowth = -SlotSize;
978 // Find the funclet establisher parameter
979 unsigned Establisher = X86::NoRegister;
981 Establisher = Uses64BitFramePtr ? X86::RCX : X86::ECX;
983 Establisher = Uses64BitFramePtr ? X86::RDX : X86::EDX;
985 if (IsWin64Prologue && IsFunclet & !IsClrFunclet) {
986 // Immediately spill establisher into the home slot.
987 // The runtime cares about this.
988 // MOV64mr %rdx, 16(%rsp)
989 unsigned MOVmr = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
990 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(MOVmr)), StackPtr, true, 16)
992 .setMIFlag(MachineInstr::FrameSetup);
993 MBB.addLiveIn(Establisher);
997 // Calculate required stack adjustment.
998 uint64_t FrameSize = StackSize - SlotSize;
999 // If required, include space for extra hidden slot for stashing base pointer.
1000 if (X86FI->getRestoreBasePointer())
1001 FrameSize += SlotSize;
1003 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
1005 // Callee-saved registers are pushed on stack before the stack is realigned.
1006 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1007 NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);
1009 // Get the offset of the stack slot for the EBP register, which is
1010 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1011 // Update the frame offset adjustment.
1013 MFI->setOffsetAdjustment(-NumBytes);
1015 assert(MFI->getOffsetAdjustment() == -(int)NumBytes &&
1016 "should calculate same local variable offset for funclets");
1018 // Save EBP/RBP into the appropriate stack slot.
1019 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1020 .addReg(MachineFramePtr, RegState::Kill)
1021 .setMIFlag(MachineInstr::FrameSetup);
1023 if (NeedsDwarfCFI) {
1024 // Mark the place where EBP/RBP was saved.
1025 // Define the current CFA rule to use the provided offset.
1027 BuildCFI(MBB, MBBI, DL,
1028 MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));
1030 // Change the rule for the FramePtr to be an "offset" rule.
1031 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1032 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(
1033 nullptr, DwarfFramePtr, 2 * stackGrowth));
1037 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg))
1039 .setMIFlag(MachineInstr::FrameSetup);
1042 if (!IsWin64Prologue && !IsFunclet) {
1043 // Update EBP with the new base value.
1044 BuildMI(MBB, MBBI, DL,
1045 TII.get(Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr),
1048 .setMIFlag(MachineInstr::FrameSetup);
1050 if (NeedsDwarfCFI) {
1051 // Mark effective beginning of when frame pointer becomes valid.
1052 // Define the current CFA to use the EBP/RBP register.
1053 unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);
1054 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaRegister(
1055 nullptr, DwarfFramePtr));
1059 // Mark the FramePtr as live-in in every block. Don't do this again for
1060 // funclet prologues.
1062 for (MachineBasicBlock &EveryMBB : MF)
1063 EveryMBB.addLiveIn(MachineFramePtr);
1066 assert(!IsFunclet && "funclets without FPs not yet implemented");
1067 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1070 // For EH funclets, only allocate enough space for outgoing calls. Save the
1071 // NumBytes value that we would've used for the parent frame.
1072 unsigned ParentFrameNumBytes = NumBytes;
1074 NumBytes = getWinEHFuncletFrameSize(MF);
1076 // Skip the callee-saved push instructions.
1077 bool PushedRegs = false;
1078 int StackOffset = 2 * stackGrowth;
1080 while (MBBI != MBB.end() &&
1081 MBBI->getFlag(MachineInstr::FrameSetup) &&
1082 (MBBI->getOpcode() == X86::PUSH32r ||
1083 MBBI->getOpcode() == X86::PUSH64r)) {
1085 unsigned Reg = MBBI->getOperand(0).getReg();
1088 if (!HasFP && NeedsDwarfCFI) {
1089 // Mark callee-saved push instruction.
1090 // Define the current CFA rule to use the provided offset.
1092 BuildCFI(MBB, MBBI, DL,
1093 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
1094 StackOffset += stackGrowth;
1098 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_PushReg)).addImm(Reg).setMIFlag(
1099 MachineInstr::FrameSetup);
1103 // Realign stack after we pushed callee-saved registers (so that we'll be
1104 // able to calculate their offsets from the frame pointer).
1105 // Don't do this for Win64, it needs to realign the stack after the prologue.
1106 if (!IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF)) {
1107 assert(HasFP && "There should be a frame pointer if stack is realigned.");
1108 BuildStackAlignAND(MBB, MBBI, DL, StackPtr, MaxAlign);
1111 // If there is an SUB32ri of ESP immediately before this instruction, merge
1112 // the two. This can be the case when tail call elimination is enabled and
1113 // the callee has more arguments then the caller.
1114 NumBytes -= mergeSPUpdates(MBB, MBBI, true);
1116 // Adjust stack pointer: ESP -= numbytes.
1118 // Windows and cygwin/mingw require a prologue helper routine when allocating
1119 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
1120 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
1121 // stack and adjust the stack pointer in one go. The 64-bit version of
1122 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
1123 // responsible for adjusting the stack pointer. Touching the stack at 4K
1124 // increments is necessary to ensure that the guard pages used by the OS
1125 // virtual memory manager are allocated in correct sequence.
1126 uint64_t AlignedNumBytes = NumBytes;
1127 if (IsWin64Prologue && !IsFunclet && TRI->needsStackRealignment(MF))
1128 AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);
1129 if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {
1130 // Check whether EAX is livein for this function.
1131 bool isEAXAlive = isEAXLiveIn(MF);
1134 // Sanity check that EAX is not livein for this function.
1135 // It should not be, so throw an assert.
1136 assert(!Is64Bit && "EAX is livein in x64 case!");
1139 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1140 .addReg(X86::EAX, RegState::Kill)
1141 .setMIFlag(MachineInstr::FrameSetup);
1145 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
1146 // Function prologue is responsible for adjusting the stack pointer.
1147 if (isUInt<32>(NumBytes)) {
1148 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1150 .setMIFlag(MachineInstr::FrameSetup);
1151 } else if (isInt<32>(NumBytes)) {
1152 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1154 .setMIFlag(MachineInstr::FrameSetup);
1156 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1158 .setMIFlag(MachineInstr::FrameSetup);
1161 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
1162 // We'll also use 4 already allocated bytes for EAX.
1163 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1164 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
1165 .setMIFlag(MachineInstr::FrameSetup);
1168 // Call __chkstk, __chkstk_ms, or __alloca.
1169 emitStackProbe(MF, MBB, MBBI, DL, true);
1174 addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), X86::EAX),
1175 StackPtr, false, NumBytes - 4);
1176 MI->setFlag(MachineInstr::FrameSetup);
1177 MBB.insert(MBBI, MI);
1179 } else if (NumBytes) {
1180 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, /*InEpilogue=*/false);
1183 if (NeedsWinCFI && NumBytes)
1184 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_StackAlloc))
1186 .setMIFlag(MachineInstr::FrameSetup);
1188 int SEHFrameOffset = 0;
1189 unsigned SPOrEstablisher = IsFunclet ? Establisher : StackPtr;
1190 if (IsWin64Prologue && HasFP) {
1191 // Set RBP to a small fixed offset from RSP. In the funclet case, we base
1192 // this calculation on the incoming establisher, which holds the value of
1193 // RSP from the parent frame at the end of the prologue.
1194 SEHFrameOffset = calculateSetFPREG(ParentFrameNumBytes);
1196 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1197 SPOrEstablisher, false, SEHFrameOffset);
1199 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1200 .addReg(SPOrEstablisher);
1202 // If this is not a funclet, emit the CFI describing our frame pointer.
1203 if (NeedsWinCFI && !IsFunclet)
1204 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SetFrame))
1206 .addImm(SEHFrameOffset)
1207 .setMIFlag(MachineInstr::FrameSetup);
1208 } else if (IsFunclet && STI.is32Bit()) {
1209 // Reset EBP / ESI to something good for funclets.
1210 MBBI = restoreWin32EHStackPointers(MBB, MBBI, DL);
1213 while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup)) {
1214 const MachineInstr *FrameInstr = &*MBBI;
1219 if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) {
1220 if (X86::FR64RegClass.contains(Reg)) {
1221 unsigned IgnoredFrameReg;
1222 int Offset = getFrameIndexReference(MF, FI, IgnoredFrameReg);
1223 Offset += SEHFrameOffset;
1225 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_SaveXMM))
1228 .setMIFlag(MachineInstr::FrameSetup);
1235 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_EndPrologue))
1236 .setMIFlag(MachineInstr::FrameSetup);
1238 // Realign stack after we spilled callee-saved registers (so that we'll be
1239 // able to calculate their offsets from the frame pointer).
1240 // Win64 requires aligning the stack after the prologue.
1241 if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {
1242 assert(HasFP && "There should be a frame pointer if stack is realigned.");
1243 BuildStackAlignAND(MBB, MBBI, DL, SPOrEstablisher, MaxAlign);
1246 // We already dealt with stack realignment and funclets above.
1247 if (IsFunclet && STI.is32Bit())
1250 // If we need a base pointer, set it up here. It's whatever the value
1251 // of the stack pointer is at this point. Any variable size objects
1252 // will be allocated after this, so we can still use the base pointer
1253 // to reference locals.
1254 if (TRI->hasBasePointer(MF)) {
1255 // Update the base pointer with the current stack pointer.
1256 unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;
1257 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1258 .addReg(SPOrEstablisher)
1259 .setMIFlag(MachineInstr::FrameSetup);
1260 if (X86FI->getRestoreBasePointer()) {
1261 // Stash value of base pointer. Saving RSP instead of EBP shortens
1262 // dependence chain. Used by SjLj EH.
1263 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1264 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)),
1265 FramePtr, true, X86FI->getRestoreBasePointerOffset())
1266 .addReg(SPOrEstablisher)
1267 .setMIFlag(MachineInstr::FrameSetup);
1270 if (X86FI->getHasSEHFramePtrSave() && !IsFunclet) {
1271 // Stash the value of the frame pointer relative to the base pointer for
1272 // Win32 EH. This supports Win32 EH, which does the inverse of the above:
1273 // it recovers the frame pointer from the base pointer rather than the
1274 // other way around.
1275 unsigned Opm = Uses64BitFramePtr ? X86::MOV64mr : X86::MOV32mr;
1278 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
1279 assert(UsedReg == BasePtr);
1280 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opm)), UsedReg, true, Offset)
1282 .setMIFlag(MachineInstr::FrameSetup);
1286 if (((!HasFP && NumBytes) || PushedRegs) && NeedsDwarfCFI) {
1287 // Mark end of stack pointer adjustment.
1288 if (!HasFP && NumBytes) {
1289 // Define the current CFA rule to use the provided offset.
1291 BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createDefCfaOffset(
1292 nullptr, -StackSize + stackGrowth));
1295 // Emit DWARF info specifying the offsets of the callee-saved registers.
1297 emitCalleeSavedFrameMoves(MBB, MBBI, DL);
1301 bool X86FrameLowering::canUseLEAForSPInEpilogue(
1302 const MachineFunction &MF) const {
1303 // We can't use LEA instructions for adjusting the stack pointer if this is a
1304 // leaf function in the Win64 ABI. Only ADD instructions may be used to
1305 // deallocate the stack.
1306 // This means that we can use LEA for SP in two situations:
1307 // 1. We *aren't* using the Win64 ABI which means we are free to use LEA.
1308 // 2. We *have* a frame pointer which means we are permitted to use LEA.
1309 return !MF.getTarget().getMCAsmInfo()->usesWindowsCFI() || hasFP(MF);
1312 static bool isFuncletReturnInstr(MachineInstr *MI) {
1313 switch (MI->getOpcode()) {
1315 case X86::CLEANUPRET:
1320 llvm_unreachable("impossible");
1323 unsigned X86FrameLowering::getWinEHFuncletFrameSize(const MachineFunction &MF) const {
1324 // This is the size of the pushed CSRs.
1326 MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
1327 // This is the amount of stack a funclet needs to allocate.
1328 unsigned MaxCallSize = MF.getFrameInfo()->getMaxCallFrameSize();
1329 // RBP is not included in the callee saved register block. After pushing RBP,
1330 // everything is 16 byte aligned. Everything we allocate before an outgoing
1331 // call must also be 16 byte aligned.
1332 unsigned FrameSizeMinusRBP =
1333 RoundUpToAlignment(CSSize + MaxCallSize, getStackAlignment());
1334 // Subtract out the size of the callee saved registers. This is how much stack
1335 // each funclet will allocate.
1336 return FrameSizeMinusRBP - CSSize;
1339 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
1340 MachineBasicBlock &MBB) const {
1341 const MachineFrameInfo *MFI = MF.getFrameInfo();
1342 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1343 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1345 if (MBBI != MBB.end())
1346 DL = MBBI->getDebugLoc();
1347 // standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.
1348 const bool Is64BitILP32 = STI.isTarget64BitILP32();
1349 unsigned FramePtr = TRI->getFrameRegister(MF);
1350 unsigned MachineFramePtr =
1351 Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)
1354 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1356 IsWin64Prologue && MF.getFunction()->needsUnwindTableEntry();
1357 bool IsFunclet = isFuncletReturnInstr(MBBI);
1358 MachineBasicBlock *TargetMBB = nullptr;
1360 // Get the number of bytes to allocate from the FrameInfo.
1361 uint64_t StackSize = MFI->getStackSize();
1362 uint64_t MaxAlign = calculateMaxStackAlign(MF);
1363 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1364 uint64_t NumBytes = 0;
1366 if (MBBI->getOpcode() == X86::CATCHRET) {
1367 // SEH shouldn't use catchret.
1368 assert(!isAsynchronousEHPersonality(
1369 classifyEHPersonality(MF.getFunction()->getPersonalityFn())) &&
1370 "SEH should not use CATCHRET");
1372 NumBytes = getWinEHFuncletFrameSize(MF);
1373 assert(hasFP(MF) && "EH funclets without FP not yet implemented");
1374 TargetMBB = MBBI->getOperand(0).getMBB();
1377 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1379 .setMIFlag(MachineInstr::FrameDestroy);
1380 } else if (MBBI->getOpcode() == X86::CLEANUPRET) {
1381 NumBytes = getWinEHFuncletFrameSize(MF);
1382 assert(hasFP(MF) && "EH funclets without FP not yet implemented");
1383 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1385 .setMIFlag(MachineInstr::FrameDestroy);
1386 } else if (hasFP(MF)) {
1387 // Calculate required stack adjustment.
1388 uint64_t FrameSize = StackSize - SlotSize;
1389 NumBytes = FrameSize - CSSize;
1391 // Callee-saved registers were pushed on stack before the stack was
1393 if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)
1394 NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);
1397 BuildMI(MBB, MBBI, DL,
1398 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), MachineFramePtr)
1399 .setMIFlag(MachineInstr::FrameDestroy);
1401 NumBytes = StackSize - CSSize;
1403 uint64_t SEHStackAllocAmt = NumBytes;
1405 // Skip the callee-saved pop instructions.
1406 while (MBBI != MBB.begin()) {
1407 MachineBasicBlock::iterator PI = std::prev(MBBI);
1408 unsigned Opc = PI->getOpcode();
1410 if ((Opc != X86::POP32r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1411 (Opc != X86::POP64r || !PI->getFlag(MachineInstr::FrameDestroy)) &&
1412 Opc != X86::DBG_VALUE && !PI->isTerminator())
1417 MachineBasicBlock::iterator FirstCSPop = MBBI;
1420 // Fill EAX/RAX with the address of the target block.
1421 unsigned ReturnReg = STI.is64Bit() ? X86::RAX : X86::EAX;
1422 if (STI.is64Bit()) {
1423 // LEA64r TargetMBB(%rip), %rax
1424 BuildMI(MBB, FirstCSPop, DL, TII.get(X86::LEA64r), ReturnReg)
1431 // MOV32ri $TargetMBB, %eax
1432 BuildMI(MBB, FirstCSPop, DL, TII.get(X86::MOV32ri), ReturnReg)
1435 // Record that we've taken the address of TargetMBB and no longer just
1436 // reference it in a terminator.
1437 TargetMBB->setHasAddressTaken();
1440 if (MBBI != MBB.end())
1441 DL = MBBI->getDebugLoc();
1443 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1444 // instruction, merge the two instructions.
1445 if (NumBytes || MFI->hasVarSizedObjects())
1446 NumBytes += mergeSPUpdates(MBB, MBBI, true);
1448 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1449 // slot before popping them off! Same applies for the case, when stack was
1450 // realigned. Don't do this if this was a funclet epilogue, since the funclets
1451 // will not do realignment or dynamic stack allocation.
1452 if ((TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) &&
1454 if (TRI->needsStackRealignment(MF))
1456 unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);
1457 uint64_t LEAAmount =
1458 IsWin64Prologue ? SEHStackAllocAmt - SEHFrameOffset : -CSSize;
1460 // There are only two legal forms of epilogue:
1461 // - add SEHAllocationSize, %rsp
1462 // - lea SEHAllocationSize(%FramePtr), %rsp
1464 // 'mov %FramePtr, %rsp' will not be recognized as an epilogue sequence.
1465 // However, we may use this sequence if we have a frame pointer because the
1466 // effects of the prologue can safely be undone.
1467 if (LEAAmount != 0) {
1468 unsigned Opc = getLEArOpcode(Uses64BitFramePtr);
1469 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1470 FramePtr, false, LEAAmount);
1473 unsigned Opc = (Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr);
1474 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1478 } else if (NumBytes) {
1479 // Adjust stack pointer back: ESP += numbytes.
1480 emitSPUpdate(MBB, MBBI, NumBytes, /*InEpilogue=*/true);
1484 // Windows unwinder will not invoke function's exception handler if IP is
1485 // either in prologue or in epilogue. This behavior causes a problem when a
1486 // call immediately precedes an epilogue, because the return address points
1487 // into the epilogue. To cope with that, we insert an epilogue marker here,
1488 // then replace it with a 'nop' if it ends up immediately after a CALL in the
1489 // final emitted code.
1491 BuildMI(MBB, MBBI, DL, TII.get(X86::SEH_Epilogue));
1493 // Add the return addr area delta back since we are not tail calling.
1494 int Offset = -1 * X86FI->getTCReturnAddrDelta();
1495 assert(Offset >= 0 && "TCDelta should never be positive");
1497 MBBI = MBB.getFirstTerminator();
1499 // Check for possible merge with preceding ADD instruction.
1500 Offset += mergeSPUpdates(MBB, MBBI, true);
1501 emitSPUpdate(MBB, MBBI, Offset, /*InEpilogue=*/true);
1505 // NOTE: this only has a subset of the full frame index logic. In
1506 // particular, the FI < 0 and AfterFPPop logic is handled in
1507 // X86RegisterInfo::eliminateFrameIndex, but not here. Possibly
1508 // (probably?) it should be moved into here.
1509 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1510 unsigned &FrameReg) const {
1511 const MachineFrameInfo *MFI = MF.getFrameInfo();
1513 // We can't calculate offset from frame pointer if the stack is realigned,
1514 // so enforce usage of stack/base pointer. The base pointer is used when we
1515 // have dynamic allocas in addition to dynamic realignment.
1516 if (TRI->hasBasePointer(MF))
1517 FrameReg = TRI->getBaseRegister();
1518 else if (TRI->needsStackRealignment(MF))
1519 FrameReg = TRI->getStackRegister();
1521 FrameReg = TRI->getFrameRegister(MF);
1523 // Offset will hold the offset from the stack pointer at function entry to the
1525 // We need to factor in additional offsets applied during the prologue to the
1526 // frame, base, and stack pointer depending on which is used.
1527 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1528 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1529 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1530 uint64_t StackSize = MFI->getStackSize();
1531 bool HasFP = hasFP(MF);
1532 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
1533 int64_t FPDelta = 0;
1535 if (IsWin64Prologue) {
1536 assert(!MFI->hasCalls() || (StackSize % 16) == 8);
1538 // Calculate required stack adjustment.
1539 uint64_t FrameSize = StackSize - SlotSize;
1540 // If required, include space for extra hidden slot for stashing base pointer.
1541 if (X86FI->getRestoreBasePointer())
1542 FrameSize += SlotSize;
1543 uint64_t NumBytes = FrameSize - CSSize;
1545 uint64_t SEHFrameOffset = calculateSetFPREG(NumBytes);
1546 if (FI && FI == X86FI->getFAIndex())
1547 return -SEHFrameOffset;
1549 // FPDelta is the offset from the "traditional" FP location of the old base
1550 // pointer followed by return address and the location required by the
1551 // restricted Win64 prologue.
1552 // Add FPDelta to all offsets below that go through the frame pointer.
1553 FPDelta = FrameSize - SEHFrameOffset;
1554 assert((!MFI->hasCalls() || (FPDelta % 16) == 0) &&
1555 "FPDelta isn't aligned per the Win64 ABI!");
1559 if (TRI->hasBasePointer(MF)) {
1560 assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");
1562 // Skip the saved EBP.
1563 return Offset + SlotSize + FPDelta;
1565 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1566 return Offset + StackSize;
1568 } else if (TRI->needsStackRealignment(MF)) {
1570 // Skip the saved EBP.
1571 return Offset + SlotSize + FPDelta;
1573 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1574 return Offset + StackSize;
1576 // FIXME: Support tail calls
1579 return Offset + StackSize;
1581 // Skip the saved EBP.
1584 // Skip the RETADDR move area
1585 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1586 if (TailCallReturnAddrDelta < 0)
1587 Offset -= TailCallReturnAddrDelta;
1590 return Offset + FPDelta;
1593 // Simplified from getFrameIndexReference keeping only StackPointer cases
1594 int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
1596 unsigned &FrameReg) const {
1597 const MachineFrameInfo *MFI = MF.getFrameInfo();
1598 // Does not include any dynamic realign.
1599 const uint64_t StackSize = MFI->getStackSize();
1602 // LLVM arranges the stack as follows:
1607 // PUSH RBP <-- RBP points here
1609 // ~~~~~~~ <-- optional stack realignment dynamic adjustment
1612 // ... <-- RSP after prologue points here
1614 // if (hasVarSizedObjects()):
1615 // ... <-- "base pointer" (ESI/RBX) points here
1617 // ... <-- RSP points here
1619 // Case 1: In the simple case of no stack realignment and no dynamic
1620 // allocas, both "fixed" stack objects (arguments and CSRs) are addressable
1621 // with fixed offsets from RSP.
1623 // Case 2: In the case of stack realignment with no dynamic allocas, fixed
1624 // stack objects are addressed with RBP and regular stack objects with RSP.
1626 // Case 3: In the case of dynamic allocas and stack realignment, RSP is used
1627 // to address stack arguments for outgoing calls and nothing else. The "base
1628 // pointer" points to local variables, and RBP points to fixed objects.
1630 // In cases 2 and 3, we can only answer for non-fixed stack objects, and the
1631 // answer we give is relative to the SP after the prologue, and not the
1632 // SP in the middle of the function.
1634 assert((!TRI->needsStackRealignment(MF) || !MFI->isFixedObjectIndex(FI)) &&
1635 "offset from fixed object to SP is not static");
1637 // We don't handle tail calls, and shouldn't be seeing them either.
1638 int TailCallReturnAddrDelta =
1639 MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta();
1640 assert(!(TailCallReturnAddrDelta < 0) && "we don't handle this case!");
1644 // Fill in FrameReg output argument.
1645 FrameReg = TRI->getStackRegister();
1647 // This is how the math works out:
1649 // %rsp grows (i.e. gets lower) left to right. Each box below is
1650 // one word (eight bytes). Obj0 is the stack slot we're trying to
1653 // ----------------------------------
1654 // | BP | Obj0 | Obj1 | ... | ObjN |
1655 // ----------------------------------
1659 // A is the incoming stack pointer.
1660 // (B - A) is the local area offset (-8 for x86-64) [1]
1661 // (C - A) is the Offset returned by MFI->getObjectOffset for Obj0 [2]
1663 // |(E - B)| is the StackSize (absolute value, positive). For a
1664 // stack that grown down, this works out to be (B - E). [3]
1666 // E is also the value of %rsp after stack has been set up, and we
1667 // want (C - E) -- the value we can add to %rsp to get to Obj0. Now
1668 // (C - E) == (C - A) - (B - A) + (B - E)
1669 // { Using [1], [2] and [3] above }
1670 // == getObjectOffset - LocalAreaOffset + StackSize
1673 // Get the Offset from the StackPointer
1674 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1676 return Offset + StackSize;
1679 bool X86FrameLowering::assignCalleeSavedSpillSlots(
1680 MachineFunction &MF, const TargetRegisterInfo *TRI,
1681 std::vector<CalleeSavedInfo> &CSI) const {
1682 MachineFrameInfo *MFI = MF.getFrameInfo();
1683 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1685 unsigned CalleeSavedFrameSize = 0;
1686 int SpillSlotOffset = getOffsetOfLocalArea() + X86FI->getTCReturnAddrDelta();
1689 // emitPrologue always spills frame register the first thing.
1690 SpillSlotOffset -= SlotSize;
1691 MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1693 // Since emitPrologue and emitEpilogue will handle spilling and restoring of
1694 // the frame register, we can delete it from CSI list and not have to worry
1695 // about avoiding it later.
1696 unsigned FPReg = TRI->getFrameRegister(MF);
1697 for (unsigned i = 0; i < CSI.size(); ++i) {
1698 if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
1699 CSI.erase(CSI.begin() + i);
1705 // Assign slots for GPRs. It increases frame size.
1706 for (unsigned i = CSI.size(); i != 0; --i) {
1707 unsigned Reg = CSI[i - 1].getReg();
1709 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1712 SpillSlotOffset -= SlotSize;
1713 CalleeSavedFrameSize += SlotSize;
1715 int SlotIndex = MFI->CreateFixedSpillStackObject(SlotSize, SpillSlotOffset);
1716 CSI[i - 1].setFrameIdx(SlotIndex);
1719 X86FI->setCalleeSavedFrameSize(CalleeSavedFrameSize);
1721 // Assign slots for XMMs.
1722 for (unsigned i = CSI.size(); i != 0; --i) {
1723 unsigned Reg = CSI[i - 1].getReg();
1724 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1727 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1729 SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();
1731 SpillSlotOffset -= RC->getSize();
1733 MFI->CreateFixedSpillStackObject(RC->getSize(), SpillSlotOffset);
1734 CSI[i - 1].setFrameIdx(SlotIndex);
1735 MFI->ensureMaxAlignment(RC->getAlignment());
1741 bool X86FrameLowering::spillCalleeSavedRegisters(
1742 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1743 const std::vector<CalleeSavedInfo> &CSI,
1744 const TargetRegisterInfo *TRI) const {
1745 DebugLoc DL = MBB.findDebugLoc(MI);
1747 // Don't save CSRs in 32-bit EH funclets. The caller saves EBX, EBP, ESI, EDI
1748 // for us, and there are no XMM CSRs on Win32.
1749 if (MBB.isEHFuncletEntry() && STI.is32Bit() && STI.isOSWindows())
1752 // Push GPRs. It increases frame size.
1753 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1754 for (unsigned i = CSI.size(); i != 0; --i) {
1755 unsigned Reg = CSI[i - 1].getReg();
1757 if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
1759 // Add the callee-saved register as live-in. It's killed at the spill.
1762 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1763 .setMIFlag(MachineInstr::FrameSetup);
1766 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1767 // It can be done by spilling XMMs to stack frame.
1768 for (unsigned i = CSI.size(); i != 0; --i) {
1769 unsigned Reg = CSI[i-1].getReg();
1770 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
1772 // Add the callee-saved register as live-in. It's killed at the spill.
1774 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1776 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i - 1].getFrameIdx(), RC,
1779 MI->setFlag(MachineInstr::FrameSetup);
1786 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1787 MachineBasicBlock::iterator MI,
1788 const std::vector<CalleeSavedInfo> &CSI,
1789 const TargetRegisterInfo *TRI) const {
1793 if (isFuncletReturnInstr(MI) && STI.isOSWindows()) {
1794 // Don't restore CSRs in 32-bit EH funclets. Matches
1795 // spillCalleeSavedRegisters.
1798 // Don't restore CSRs before an SEH catchret. SEH except blocks do not form
1799 // funclets. emitEpilogue transforms these to normal jumps.
1800 if (MI->getOpcode() == X86::CATCHRET) {
1801 const Function *Func = MBB.getParent()->getFunction();
1802 bool IsSEH = isAsynchronousEHPersonality(
1803 classifyEHPersonality(Func->getPersonalityFn()));
1809 DebugLoc DL = MBB.findDebugLoc(MI);
1811 // Reload XMMs from stack frame.
1812 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1813 unsigned Reg = CSI[i].getReg();
1814 if (X86::GR64RegClass.contains(Reg) ||
1815 X86::GR32RegClass.contains(Reg))
1818 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1819 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RC, TRI);
1823 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1824 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1825 unsigned Reg = CSI[i].getReg();
1826 if (!X86::GR64RegClass.contains(Reg) &&
1827 !X86::GR32RegClass.contains(Reg))
1830 BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
1831 .setMIFlag(MachineInstr::FrameDestroy);
1836 void X86FrameLowering::determineCalleeSaves(MachineFunction &MF,
1837 BitVector &SavedRegs,
1838 RegScavenger *RS) const {
1839 TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
1841 MachineFrameInfo *MFI = MF.getFrameInfo();
1843 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1844 int64_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1846 if (TailCallReturnAddrDelta < 0) {
1847 // create RETURNADDR area
1856 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1857 TailCallReturnAddrDelta - SlotSize, true);
1860 // Spill the BasePtr if it's used.
1861 if (TRI->hasBasePointer(MF)) {
1862 SavedRegs.set(TRI->getBaseRegister());
1864 // Allocate a spill slot for EBP if we have a base pointer and EH funclets.
1865 if (MF.getMMI().hasEHFunclets()) {
1866 int FI = MFI->CreateSpillStackObject(SlotSize, SlotSize);
1867 X86FI->setHasSEHFramePtrSave(true);
1868 X86FI->setSEHFramePtrSaveIndex(FI);
1874 HasNestArgument(const MachineFunction *MF) {
1875 const Function *F = MF->getFunction();
1876 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1878 if (I->hasNestAttr())
1884 /// GetScratchRegister - Get a temp register for performing work in the
1885 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1886 /// and the properties of the function either one or two registers will be
1887 /// needed. Set primary to true for the first register, false for the second.
1889 GetScratchRegister(bool Is64Bit, bool IsLP64, const MachineFunction &MF, bool Primary) {
1890 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1893 if (CallingConvention == CallingConv::HiPE) {
1895 return Primary ? X86::R14 : X86::R13;
1897 return Primary ? X86::EBX : X86::EDI;
1902 return Primary ? X86::R11 : X86::R12;
1904 return Primary ? X86::R11D : X86::R12D;
1907 bool IsNested = HasNestArgument(&MF);
1909 if (CallingConvention == CallingConv::X86_FastCall ||
1910 CallingConvention == CallingConv::Fast) {
1912 report_fatal_error("Segmented stacks does not support fastcall with "
1913 "nested function.");
1914 return Primary ? X86::EAX : X86::ECX;
1917 return Primary ? X86::EDX : X86::EAX;
1918 return Primary ? X86::ECX : X86::EAX;
1921 // The stack limit in the TCB is set to this many bytes above the actual stack
1923 static const uint64_t kSplitStackAvailable = 256;
1925 void X86FrameLowering::adjustForSegmentedStacks(
1926 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
1927 MachineFrameInfo *MFI = MF.getFrameInfo();
1929 unsigned TlsReg, TlsOffset;
1932 unsigned ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
1933 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1934 "Scratch register is live-in");
1936 if (MF.getFunction()->isVarArg())
1937 report_fatal_error("Segmented stacks do not support vararg functions.");
1938 if (!STI.isTargetLinux() && !STI.isTargetDarwin() && !STI.isTargetWin32() &&
1939 !STI.isTargetWin64() && !STI.isTargetFreeBSD() &&
1940 !STI.isTargetDragonFly())
1941 report_fatal_error("Segmented stacks not supported on this platform.");
1943 // Eventually StackSize will be calculated by a link-time pass; which will
1944 // also decide whether checking code needs to be injected into this particular
1946 StackSize = MFI->getStackSize();
1948 // Do not generate a prologue for functions with a stack of size zero
1952 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1953 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1954 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1955 bool IsNested = false;
1957 // We need to know if the function has a nest argument only in 64 bit mode.
1959 IsNested = HasNestArgument(&MF);
1961 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1962 // allocMBB needs to be last (terminating) instruction.
1964 for (const auto &LI : PrologueMBB.liveins()) {
1965 allocMBB->addLiveIn(LI);
1966 checkMBB->addLiveIn(LI);
1970 allocMBB->addLiveIn(IsLP64 ? X86::R10 : X86::R10D);
1972 MF.push_front(allocMBB);
1973 MF.push_front(checkMBB);
1975 // When the frame size is less than 256 we just compare the stack
1976 // boundary directly to the value of the stack pointer, per gcc.
1977 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1979 // Read the limit off the current stacklet off the stack_guard location.
1981 if (STI.isTargetLinux()) {
1983 TlsOffset = IsLP64 ? 0x70 : 0x40;
1984 } else if (STI.isTargetDarwin()) {
1986 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1987 } else if (STI.isTargetWin64()) {
1989 TlsOffset = 0x28; // pvArbitrary, reserved for application use
1990 } else if (STI.isTargetFreeBSD()) {
1993 } else if (STI.isTargetDragonFly()) {
1995 TlsOffset = 0x20; // use tls_tcb.tcb_segstack
1997 report_fatal_error("Segmented stacks not supported on this platform.");
2000 if (CompareStackPointer)
2001 ScratchReg = IsLP64 ? X86::RSP : X86::ESP;
2003 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2004 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2006 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2007 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2009 if (STI.isTargetLinux()) {
2012 } else if (STI.isTargetDarwin()) {
2014 TlsOffset = 0x48 + 90*4;
2015 } else if (STI.isTargetWin32()) {
2017 TlsOffset = 0x14; // pvArbitrary, reserved for application use
2018 } else if (STI.isTargetDragonFly()) {
2020 TlsOffset = 0x10; // use tls_tcb.tcb_segstack
2021 } else if (STI.isTargetFreeBSD()) {
2022 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
2024 report_fatal_error("Segmented stacks not supported on this platform.");
2027 if (CompareStackPointer)
2028 ScratchReg = X86::ESP;
2030 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2031 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2033 if (STI.isTargetLinux() || STI.isTargetWin32() || STI.isTargetWin64() ||
2034 STI.isTargetDragonFly()) {
2035 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2036 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2037 } else if (STI.isTargetDarwin()) {
2039 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register.
2040 unsigned ScratchReg2;
2042 if (CompareStackPointer) {
2043 // The primary scratch register is available for holding the TLS offset.
2044 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2045 SaveScratch2 = false;
2047 // Need to use a second register to hold the TLS offset
2048 ScratchReg2 = GetScratchRegister(Is64Bit, IsLP64, MF, false);
2050 // Unfortunately, with fastcc the second scratch register may hold an
2052 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
2055 // If Scratch2 is live-in then it needs to be saved.
2056 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
2057 "Scratch register is live-in and not saved");
2060 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
2061 .addReg(ScratchReg2, RegState::Kill);
2063 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
2065 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
2067 .addReg(ScratchReg2).addImm(1).addReg(0)
2072 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
2076 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
2077 // It jumps to normal execution of the function body.
2078 BuildMI(checkMBB, DL, TII.get(X86::JA_1)).addMBB(&PrologueMBB);
2080 // On 32 bit we first push the arguments size and then the frame size. On 64
2081 // bit, we pass the stack frame size in r10 and the argument size in r11.
2083 // Functions with nested arguments use R10, so it needs to be saved across
2084 // the call to _morestack
2086 const unsigned RegAX = IsLP64 ? X86::RAX : X86::EAX;
2087 const unsigned Reg10 = IsLP64 ? X86::R10 : X86::R10D;
2088 const unsigned Reg11 = IsLP64 ? X86::R11 : X86::R11D;
2089 const unsigned MOVrr = IsLP64 ? X86::MOV64rr : X86::MOV32rr;
2090 const unsigned MOVri = IsLP64 ? X86::MOV64ri : X86::MOV32ri;
2093 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2095 BuildMI(allocMBB, DL, TII.get(MOVri), Reg10)
2097 BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)
2098 .addImm(X86FI->getArgumentStackSize());
2100 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2101 .addImm(X86FI->getArgumentStackSize());
2102 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
2106 // __morestack is in libgcc
2107 if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
2108 // Under the large code model, we cannot assume that __morestack lives
2109 // within 2^31 bytes of the call site, so we cannot use pc-relative
2110 // addressing. We cannot perform the call via a temporary register,
2111 // as the rax register may be used to store the static chain, and all
2112 // other suitable registers may be either callee-save or used for
2113 // parameter passing. We cannot use the stack at this point either
2114 // because __morestack manipulates the stack directly.
2116 // To avoid these issues, perform an indirect call via a read-only memory
2117 // location containing the address.
2119 // This solution is not perfect, as it assumes that the .rodata section
2120 // is laid out within 2^31 bytes of each function body, but this seems
2121 // to be sufficient for JIT.
2122 BuildMI(allocMBB, DL, TII.get(X86::CALL64m))
2126 .addExternalSymbol("__morestack_addr")
2128 MF.getMMI().setUsesMorestackAddr(true);
2131 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
2132 .addExternalSymbol("__morestack");
2134 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
2135 .addExternalSymbol("__morestack");
2139 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
2141 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
2143 allocMBB->addSuccessor(&PrologueMBB);
2145 checkMBB->addSuccessor(allocMBB);
2146 checkMBB->addSuccessor(&PrologueMBB);
2153 /// Erlang programs may need a special prologue to handle the stack size they
2154 /// might need at runtime. That is because Erlang/OTP does not implement a C
2155 /// stack but uses a custom implementation of hybrid stack/heap architecture.
2156 /// (for more information see Eric Stenman's Ph.D. thesis:
2157 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
2160 /// temp0 = sp - MaxStack
2161 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2165 /// call inc_stack # doubles the stack space
2166 /// temp0 = sp - MaxStack
2167 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
2168 void X86FrameLowering::adjustForHiPEPrologue(
2169 MachineFunction &MF, MachineBasicBlock &PrologueMBB) const {
2170 MachineFrameInfo *MFI = MF.getFrameInfo();
2172 // HiPE-specific values
2173 const unsigned HipeLeafWords = 24;
2174 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
2175 const unsigned Guaranteed = HipeLeafWords * SlotSize;
2176 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
2177 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
2178 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
2180 assert(STI.isTargetLinux() &&
2181 "HiPE prologue is only supported on Linux operating systems.");
2183 // Compute the largest caller's frame that is needed to fit the callees'
2184 // frames. This 'MaxStack' is computed from:
2186 // a) the fixed frame size, which is the space needed for all spilled temps,
2187 // b) outgoing on-stack parameter areas, and
2188 // c) the minimum stack space this function needs to make available for the
2189 // functions it calls (a tunable ABI property).
2190 if (MFI->hasCalls()) {
2191 unsigned MoreStackForCalls = 0;
2193 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
2194 MBBI != MBBE; ++MBBI)
2195 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
2200 // Get callee operand.
2201 const MachineOperand &MO = MI->getOperand(0);
2203 // Only take account of global function calls (no closures etc.).
2207 const Function *F = dyn_cast<Function>(MO.getGlobal());
2211 // Do not update 'MaxStack' for primitive and built-in functions
2212 // (encoded with names either starting with "erlang."/"bif_" or not
2213 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
2214 // "_", such as the BIF "suspend_0") as they are executed on another
2216 if (F->getName().find("erlang.") != StringRef::npos ||
2217 F->getName().find("bif_") != StringRef::npos ||
2218 F->getName().find_first_of("._") == StringRef::npos)
2221 unsigned CalleeStkArity =
2222 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
2223 if (HipeLeafWords - 1 > CalleeStkArity)
2224 MoreStackForCalls = std::max(MoreStackForCalls,
2225 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
2227 MaxStack += MoreStackForCalls;
2230 // If the stack frame needed is larger than the guaranteed then runtime checks
2231 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
2232 if (MaxStack > Guaranteed) {
2233 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
2234 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
2236 for (const auto &LI : PrologueMBB.liveins()) {
2237 stackCheckMBB->addLiveIn(LI);
2238 incStackMBB->addLiveIn(LI);
2241 MF.push_front(incStackMBB);
2242 MF.push_front(stackCheckMBB);
2244 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
2245 unsigned LEAop, CMPop, CALLop;
2249 LEAop = X86::LEA64r;
2250 CMPop = X86::CMP64rm;
2251 CALLop = X86::CALL64pcrel32;
2252 SPLimitOffset = 0x90;
2256 LEAop = X86::LEA32r;
2257 CMPop = X86::CMP32rm;
2258 CALLop = X86::CALLpcrel32;
2259 SPLimitOffset = 0x4c;
2262 ScratchReg = GetScratchRegister(Is64Bit, IsLP64, MF, true);
2263 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
2264 "HiPE prologue scratch register is live-in");
2266 // Create new MBB for StackCheck:
2267 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
2268 SPReg, false, -MaxStack);
2269 // SPLimitOffset is in a fixed heap location (pointed by BP).
2270 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
2271 .addReg(ScratchReg), PReg, false, SPLimitOffset);
2272 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_1)).addMBB(&PrologueMBB);
2274 // Create new MBB for IncStack:
2275 BuildMI(incStackMBB, DL, TII.get(CALLop)).
2276 addExternalSymbol("inc_stack_0");
2277 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
2278 SPReg, false, -MaxStack);
2279 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
2280 .addReg(ScratchReg), PReg, false, SPLimitOffset);
2281 BuildMI(incStackMBB, DL, TII.get(X86::JLE_1)).addMBB(incStackMBB);
2283 stackCheckMBB->addSuccessor(&PrologueMBB, 99);
2284 stackCheckMBB->addSuccessor(incStackMBB, 1);
2285 incStackMBB->addSuccessor(&PrologueMBB, 99);
2286 incStackMBB->addSuccessor(incStackMBB, 1);
2293 bool X86FrameLowering::adjustStackWithPops(MachineBasicBlock &MBB,
2294 MachineBasicBlock::iterator MBBI, DebugLoc DL, int Offset) const {
2299 if (Offset % SlotSize)
2302 int NumPops = Offset / SlotSize;
2303 // This is only worth it if we have at most 2 pops.
2304 if (NumPops != 1 && NumPops != 2)
2307 // Handle only the trivial case where the adjustment directly follows
2308 // a call. This is the most common one, anyway.
2309 if (MBBI == MBB.begin())
2311 MachineBasicBlock::iterator Prev = std::prev(MBBI);
2312 if (!Prev->isCall() || !Prev->getOperand(1).isRegMask())
2316 unsigned FoundRegs = 0;
2318 auto RegMask = Prev->getOperand(1);
2321 Is64Bit ? X86::GR64_NOREX_NOSPRegClass : X86::GR32_NOREX_NOSPRegClass;
2322 // Try to find up to NumPops free registers.
2323 for (auto Candidate : RegClass) {
2325 // Poor man's liveness:
2326 // Since we're immediately after a call, any register that is clobbered
2327 // by the call and not defined by it can be considered dead.
2328 if (!RegMask.clobbersPhysReg(Candidate))
2332 for (const MachineOperand &MO : Prev->implicit_operands()) {
2333 if (MO.isReg() && MO.isDef() && MO.getReg() == Candidate) {
2342 Regs[FoundRegs++] = Candidate;
2343 if (FoundRegs == (unsigned)NumPops)
2350 // If we found only one free register, but need two, reuse the same one twice.
2351 while (FoundRegs < (unsigned)NumPops)
2352 Regs[FoundRegs++] = Regs[0];
2354 for (int i = 0; i < NumPops; ++i)
2355 BuildMI(MBB, MBBI, DL,
2356 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
2361 void X86FrameLowering::
2362 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
2363 MachineBasicBlock::iterator I) const {
2364 bool reserveCallFrame = hasReservedCallFrame(MF);
2365 unsigned Opcode = I->getOpcode();
2366 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
2367 DebugLoc DL = I->getDebugLoc();
2368 uint64_t Amount = !reserveCallFrame ? I->getOperand(0).getImm() : 0;
2369 uint64_t InternalAmt = (isDestroy || Amount) ? I->getOperand(1).getImm() : 0;
2372 if (!reserveCallFrame) {
2373 // If the stack pointer can be changed after prologue, turn the
2374 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
2375 // adjcallstackdown instruction into 'add ESP, <amt>'
2377 // We need to keep the stack aligned properly. To do this, we round the
2378 // amount of space needed for the outgoing arguments up to the next
2379 // alignment boundary.
2380 unsigned StackAlign = getStackAlignment();
2381 Amount = RoundUpToAlignment(Amount, StackAlign);
2383 MachineModuleInfo &MMI = MF.getMMI();
2384 const Function *Fn = MF.getFunction();
2385 bool WindowsCFI = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
2386 bool DwarfCFI = !WindowsCFI &&
2387 (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());
2389 // If we have any exception handlers in this function, and we adjust
2390 // the SP before calls, we may need to indicate this to the unwinder
2391 // using GNU_ARGS_SIZE. Note that this may be necessary even when
2392 // Amount == 0, because the preceding function may have set a non-0
2394 // TODO: We don't need to reset this between subsequent functions,
2395 // if it didn't change.
2396 bool HasDwarfEHHandlers = !WindowsCFI &&
2397 !MF.getMMI().getLandingPads().empty();
2399 if (HasDwarfEHHandlers && !isDestroy &&
2400 MF.getInfo<X86MachineFunctionInfo>()->getHasPushSequences())
2401 BuildCFI(MBB, I, DL,
2402 MCCFIInstruction::createGnuArgsSize(nullptr, Amount));
2407 // Factor out the amount that gets handled inside the sequence
2408 // (Pushes of argument for frame setup, callee pops for frame destroy)
2409 Amount -= InternalAmt;
2411 // If this is a callee-pop calling convention, and we're emitting precise
2412 // SP-based CFI, emit a CFA adjust for the amount the callee popped.
2413 if (isDestroy && InternalAmt && DwarfCFI && !hasFP(MF) &&
2414 MMI.usePreciseUnwindInfo())
2415 BuildCFI(MBB, I, DL,
2416 MCCFIInstruction::createAdjustCfaOffset(nullptr, -InternalAmt));
2419 // Add Amount to SP to destroy a frame, and subtract to setup.
2420 int Offset = isDestroy ? Amount : -Amount;
2422 if (!(Fn->optForMinSize() &&
2423 adjustStackWithPops(MBB, I, DL, Offset)))
2424 BuildStackAdjustment(MBB, I, DL, Offset, /*InEpilogue=*/false);
2427 if (DwarfCFI && !hasFP(MF)) {
2428 // If we don't have FP, but need to generate unwind information,
2429 // we need to set the correct CFA offset after the stack adjustment.
2430 // How much we adjust the CFA offset depends on whether we're emitting
2431 // CFI only for EH purposes or for debugging. EH only requires the CFA
2432 // offset to be correct at each call site, while for debugging we want
2433 // it to be more precise.
2434 int CFAOffset = Amount;
2435 if (!MMI.usePreciseUnwindInfo())
2436 CFAOffset += InternalAmt;
2437 CFAOffset = isDestroy ? -CFAOffset : CFAOffset;
2438 BuildCFI(MBB, I, DL,
2439 MCCFIInstruction::createAdjustCfaOffset(nullptr, CFAOffset));
2445 if (isDestroy && InternalAmt) {
2446 // If we are performing frame pointer elimination and if the callee pops
2447 // something off the stack pointer, add it back. We do this until we have
2448 // more advanced stack pointer tracking ability.
2449 // We are not tracking the stack pointer adjustment by the callee, so make
2450 // sure we restore the stack pointer immediately after the call, there may
2451 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
2452 MachineBasicBlock::iterator B = MBB.begin();
2453 while (I != B && !std::prev(I)->isCall())
2455 BuildStackAdjustment(MBB, I, DL, -InternalAmt, /*InEpilogue=*/false);
2459 bool X86FrameLowering::canUseAsEpilogue(const MachineBasicBlock &MBB) const {
2460 assert(MBB.getParent() && "Block is not attached to a function!");
2462 // Win64 has strict requirements in terms of epilogue and we are
2463 // not taking a chance at messing with them.
2464 // I.e., unless this block is already an exit block, we can't use
2465 // it as an epilogue.
2466 if (MBB.getParent()->getSubtarget<X86Subtarget>().isTargetWin64() &&
2467 !MBB.succ_empty() && !MBB.isReturnBlock())
2470 if (canUseLEAForSPInEpilogue(*MBB.getParent()))
2473 // If we cannot use LEA to adjust SP, we may need to use ADD, which
2474 // clobbers the EFLAGS. Check that none of the terminators reads the
2475 // EFLAGS, and if one uses it, conservatively assume this is not
2476 // safe to insert the epilogue here.
2477 return !terminatorsNeedFlagsAsInput(MBB);
2480 MachineBasicBlock::iterator X86FrameLowering::restoreWin32EHStackPointers(
2481 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
2482 DebugLoc DL, bool RestoreSP) const {
2483 assert(STI.isTargetWindowsMSVC() && "funclets only supported in MSVC env");
2484 assert(STI.isTargetWin32() && "EBP/ESI restoration only required on win32");
2485 assert(STI.is32Bit() && !Uses64BitFramePtr &&
2486 "restoring EBP/ESI on non-32-bit target");
2488 MachineFunction &MF = *MBB.getParent();
2489 unsigned FramePtr = TRI->getFrameRegister(MF);
2490 unsigned BasePtr = TRI->getBaseRegister();
2491 MachineModuleInfo &MMI = MF.getMMI();
2492 const Function *Fn = MF.getFunction();
2493 WinEHFuncInfo &FuncInfo = MMI.getWinEHFuncInfo(Fn);
2494 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2495 MachineFrameInfo *MFI = MF.getFrameInfo();
2497 // FIXME: Don't set FrameSetup flag in catchret case.
2499 int FI = FuncInfo.EHRegNodeFrameIndex;
2500 int EHRegSize = MFI->getObjectSize(FI);
2503 // MOV32rm -EHRegSize(%ebp), %esp
2504 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2505 X86::EBP, true, -EHRegSize)
2506 .setMIFlag(MachineInstr::FrameSetup);
2510 int EHRegOffset = getFrameIndexReference(MF, FI, UsedReg);
2511 int EndOffset = -EHRegOffset - EHRegSize;
2512 FuncInfo.EHRegNodeEndOffset = EndOffset;
2514 if (UsedReg == FramePtr) {
2515 // ADD $offset, %ebp
2516 unsigned ADDri = getADDriOpcode(false, EndOffset);
2517 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2520 .setMIFlag(MachineInstr::FrameSetup)
2523 assert(EndOffset >= 0 &&
2524 "end of registration object above normal EBP position!");
2525 } else if (UsedReg == BasePtr) {
2526 // LEA offset(%ebp), %esi
2527 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2528 FramePtr, false, EndOffset)
2529 .setMIFlag(MachineInstr::FrameSetup);
2530 // MOV32rm SavedEBPOffset(%esi), %ebp
2531 assert(X86FI->getHasSEHFramePtrSave());
2533 getFrameIndexReference(MF, X86FI->getSEHFramePtrSaveIndex(), UsedReg);
2534 assert(UsedReg == BasePtr);
2535 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
2536 UsedReg, true, Offset)
2537 .setMIFlag(MachineInstr::FrameSetup);
2539 llvm_unreachable("32-bit frames with WinEH must use FramePtr or BasePtr");
2544 unsigned X86FrameLowering::getWinEHParentFrameOffset(const MachineFunction &MF) const {
2545 // RDX, the parent frame pointer, is homed into 16(%rsp) in the prologue.
2546 unsigned Offset = 16;
2547 // RBP is immediately pushed.
2549 // All callee-saved registers are then pushed.
2550 Offset += MF.getInfo<X86MachineFunctionInfo>()->getCalleeSavedFrameSize();
2551 // Every funclet allocates enough stack space for the largest outgoing call.
2552 Offset += getWinEHFuncletFrameSize(MF);