1 //===-- X86FrameLowering.cpp - X86 Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "X86FrameLowering.h"
15 #include "X86InstrBuilder.h"
16 #include "X86InstrInfo.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/MC/MCAsmInfo.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Target/TargetOptions.h"
35 // FIXME: completely move here.
36 extern cl::opt<bool> ForceStackAlign;
38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {
39 return !MF.getFrameInfo()->hasVarSizedObjects();
42 /// hasFP - Return true if the specified function should have a dedicated frame
43 /// pointer register. This is true if the function has variable sized allocas
44 /// or if frame pointer elimination is disabled.
45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const {
46 const MachineFrameInfo *MFI = MF.getFrameInfo();
47 const MachineModuleInfo &MMI = MF.getMMI();
48 const TargetRegisterInfo *RegInfo = TM.getRegisterInfo();
50 return (MF.getTarget().Options.DisableFramePointerElim(MF) ||
51 RegInfo->needsStackRealignment(MF) ||
52 MFI->hasVarSizedObjects() ||
53 MFI->isFrameAddressTaken() || MF.hasMSInlineAsm() ||
54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
55 MMI.callsUnwindInit() || MMI.callsEHReturn());
58 static unsigned getSUBriOpcode(unsigned IsLP64, int64_t Imm) {
62 return X86::SUB64ri32;
70 static unsigned getADDriOpcode(unsigned IsLP64, int64_t Imm) {
74 return X86::ADD64ri32;
82 static unsigned getLEArOpcode(unsigned IsLP64) {
83 return IsLP64 ? X86::LEA64r : X86::LEA32r;
86 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live
87 /// when it reaches the "return" instruction. We can then pop a stack object
88 /// to this register without worry about clobbering it.
89 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,
90 MachineBasicBlock::iterator &MBBI,
91 const TargetRegisterInfo &TRI,
93 const MachineFunction *MF = MBB.getParent();
94 const Function *F = MF->getFunction();
95 if (!F || MF->getMMI().callsEHReturn())
98 static const uint16_t CallerSavedRegs32Bit[] = {
99 X86::EAX, X86::EDX, X86::ECX, 0
102 static const uint16_t CallerSavedRegs64Bit[] = {
103 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI,
104 X86::R8, X86::R9, X86::R10, X86::R11, 0
107 unsigned Opc = MBBI->getOpcode();
112 case X86::TCRETURNdi:
113 case X86::TCRETURNri:
114 case X86::TCRETURNmi:
115 case X86::TCRETURNdi64:
116 case X86::TCRETURNri64:
117 case X86::TCRETURNmi64:
119 case X86::EH_RETURN64: {
120 SmallSet<uint16_t, 8> Uses;
121 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) {
122 MachineOperand &MO = MBBI->getOperand(i);
123 if (!MO.isReg() || MO.isDef())
125 unsigned Reg = MO.getReg();
128 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
132 const uint16_t *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit;
134 if (!Uses.count(*CS))
143 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
144 /// stack pointer by a constant value.
146 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
147 unsigned StackPtr, int64_t NumBytes,
148 bool Is64Bit, bool IsLP64, bool UseLEA,
149 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
150 bool isSub = NumBytes < 0;
151 uint64_t Offset = isSub ? -NumBytes : NumBytes;
154 Opc = getLEArOpcode(IsLP64);
157 ? getSUBriOpcode(IsLP64, Offset)
158 : getADDriOpcode(IsLP64, Offset);
160 uint64_t Chunk = (1LL << 31) - 1;
161 DebugLoc DL = MBB.findDebugLoc(MBBI);
164 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
165 if (ThisVal == (Is64Bit ? 8 : 4)) {
166 // Use push / pop instead.
168 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)
169 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
172 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)
173 : (Is64Bit ? X86::POP64r : X86::POP32r);
174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
177 MI->setFlag(MachineInstr::FrameSetup);
183 MachineInstr *MI = NULL;
186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
187 StackPtr, false, isSub ? -ThisVal : ThisVal);
189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
192 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
196 MI->setFlag(MachineInstr::FrameSetup);
202 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
204 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
205 unsigned StackPtr, uint64_t *NumBytes = NULL) {
206 if (MBBI == MBB.begin()) return;
208 MachineBasicBlock::iterator PI = prior(MBBI);
209 unsigned Opc = PI->getOpcode();
210 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
211 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
212 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
213 PI->getOperand(0).getReg() == StackPtr) {
215 *NumBytes += PI->getOperand(2).getImm();
217 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
218 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
219 PI->getOperand(0).getReg() == StackPtr) {
221 *NumBytes -= PI->getOperand(2).getImm();
226 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator.
228 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
229 MachineBasicBlock::iterator &MBBI,
230 unsigned StackPtr, uint64_t *NumBytes = NULL) {
231 // FIXME: THIS ISN'T RUN!!!
234 if (MBBI == MBB.end()) return;
236 MachineBasicBlock::iterator NI = llvm::next(MBBI);
237 if (NI == MBB.end()) return;
239 unsigned Opc = NI->getOpcode();
240 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
241 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
242 NI->getOperand(0).getReg() == StackPtr) {
244 *NumBytes -= NI->getOperand(2).getImm();
247 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
248 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
249 NI->getOperand(0).getReg() == StackPtr) {
251 *NumBytes += NI->getOperand(2).getImm();
257 /// mergeSPUpdates - Checks the instruction before/after the passed
258 /// instruction. If it is an ADD/SUB/LEA instruction it is deleted argument and the
259 /// stack adjustment is returned as a positive value for ADD/LEA and a negative for
261 static int mergeSPUpdates(MachineBasicBlock &MBB,
262 MachineBasicBlock::iterator &MBBI,
264 bool doMergeWithPrevious) {
265 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
266 (!doMergeWithPrevious && MBBI == MBB.end()))
269 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
270 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
271 unsigned Opc = PI->getOpcode();
274 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
275 Opc == X86::ADD32ri || Opc == X86::ADD32ri8 ||
276 Opc == X86::LEA32r || Opc == X86::LEA64_32r) &&
277 PI->getOperand(0).getReg() == StackPtr){
278 Offset += PI->getOperand(2).getImm();
280 if (!doMergeWithPrevious) MBBI = NI;
281 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
282 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
283 PI->getOperand(0).getReg() == StackPtr) {
284 Offset -= PI->getOperand(2).getImm();
286 if (!doMergeWithPrevious) MBBI = NI;
292 static bool isEAXLiveIn(MachineFunction &MF) {
293 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(),
294 EE = MF.getRegInfo().livein_end(); II != EE; ++II) {
295 unsigned Reg = II->first;
297 if (Reg == X86::EAX || Reg == X86::AX ||
298 Reg == X86::AH || Reg == X86::AL)
305 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
307 unsigned FramePtr) const {
308 MachineFrameInfo *MFI = MF.getFrameInfo();
309 MachineModuleInfo &MMI = MF.getMMI();
311 // Add callee saved registers to move list.
312 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
313 if (CSI.empty()) return;
315 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
316 bool HasFP = hasFP(MF);
318 // Calculate amount of bytes used for return address storing.
319 int stackGrowth = -RegInfo->getSlotSize();
321 // FIXME: This is dirty hack. The code itself is pretty mess right now.
322 // It should be rewritten from scratch and generalized sometimes.
324 // Determine maximum offset (minimum due to stack growth).
325 int64_t MaxOffset = 0;
326 for (std::vector<CalleeSavedInfo>::const_iterator
327 I = CSI.begin(), E = CSI.end(); I != E; ++I)
328 MaxOffset = std::min(MaxOffset,
329 MFI->getObjectOffset(I->getFrameIdx()));
331 // Calculate offsets.
332 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
333 for (std::vector<CalleeSavedInfo>::const_iterator
334 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
335 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
336 unsigned Reg = I->getReg();
337 Offset = MaxOffset - Offset + saveAreaOffset;
339 // Don't output a new machine move if we're re-saving the frame
340 // pointer. This happens when the PrologEpilogInserter has inserted an extra
341 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
342 // generates one when frame pointers are used. If we generate a "machine
343 // move" for this extra "PUSH", the linker will lose track of the fact that
344 // the frame pointer should have the value of the first "PUSH" when it's
347 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
348 // another bug. I.e., one where we generate a prolog like this:
356 // The immediate re-push of EBP is unnecessary. At the least, it's an
357 // optimization bug. EBP can be used as a scratch register in certain
358 // cases, but probably not when we have a frame pointer.
359 if (HasFP && FramePtr == Reg)
362 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
363 MachineLocation CSSrc(Reg);
364 MMI.addFrameMove(Label, CSDst, CSSrc);
368 /// getCompactUnwindRegNum - Get the compact unwind number for a given
369 /// register. The number corresponds to the enum lists in
370 /// compact_unwind_encoding.h.
371 static int getCompactUnwindRegNum(unsigned Reg, bool is64Bit) {
372 static const uint16_t CU32BitRegs[] = {
373 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0
375 static const uint16_t CU64BitRegs[] = {
376 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
378 const uint16_t *CURegs = is64Bit ? CU64BitRegs : CU32BitRegs;
379 for (int Idx = 1; *CURegs; ++CURegs, ++Idx)
386 // Number of registers that can be saved in a compact unwind encoding.
387 #define CU_NUM_SAVED_REGS 6
389 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding
390 /// used with frameless stacks. It is passed the number of registers to be saved
391 /// and an array of the registers saved.
393 encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
394 unsigned RegCount, bool Is64Bit) {
395 // The saved registers are numbered from 1 to 6. In order to encode the order
396 // in which they were saved, we re-number them according to their place in the
397 // register order. The re-numbering is relative to the last re-numbered
398 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order:
407 for (unsigned i = 0; i != CU_NUM_SAVED_REGS; ++i) {
408 int CUReg = getCompactUnwindRegNum(SavedRegs[i], Is64Bit);
409 if (CUReg == -1) return ~0U;
410 SavedRegs[i] = CUReg;
414 std::swap(SavedRegs[0], SavedRegs[5]);
415 std::swap(SavedRegs[1], SavedRegs[4]);
416 std::swap(SavedRegs[2], SavedRegs[3]);
418 uint32_t RenumRegs[CU_NUM_SAVED_REGS];
419 for (unsigned i = CU_NUM_SAVED_REGS - RegCount; i < CU_NUM_SAVED_REGS; ++i) {
420 unsigned Countless = 0;
421 for (unsigned j = CU_NUM_SAVED_REGS - RegCount; j < i; ++j)
422 if (SavedRegs[j] < SavedRegs[i])
425 RenumRegs[i] = SavedRegs[i] - Countless - 1;
428 // Take the renumbered values and encode them into a 10-bit number.
429 uint32_t permutationEncoding = 0;
432 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1]
433 + 6 * RenumRegs[2] + 2 * RenumRegs[3]
437 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2]
438 + 6 * RenumRegs[3] + 2 * RenumRegs[4]
442 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3]
443 + 3 * RenumRegs[4] + RenumRegs[5];
446 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4]
450 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5];
453 permutationEncoding |= RenumRegs[5];
457 assert((permutationEncoding & 0x3FF) == permutationEncoding &&
458 "Invalid compact register encoding!");
459 return permutationEncoding;
462 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a
463 /// compact encoding with a frame pointer.
465 encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[CU_NUM_SAVED_REGS],
467 // Encode the registers in the order they were saved, 3-bits per register. The
468 // registers are numbered from 1 to CU_NUM_SAVED_REGS.
470 for (int I = CU_NUM_SAVED_REGS - 1, Idx = 0; I != -1; --I) {
471 unsigned Reg = SavedRegs[I];
472 if (Reg == 0) continue;
474 int CURegNum = getCompactUnwindRegNum(Reg, Is64Bit);
475 if (CURegNum == -1) return ~0U;
477 // Encode the 3-bit register number in order, skipping over 3-bits for each
479 RegEnc |= (CURegNum & 0x7) << (Idx++ * 3);
482 assert((RegEnc & 0x3FFFF) == RegEnc && "Invalid compact register encoding!");
486 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const {
487 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
488 unsigned FramePtr = RegInfo->getFrameRegister(MF);
489 unsigned StackPtr = RegInfo->getStackRegister();
491 bool Is64Bit = STI.is64Bit();
492 bool HasFP = hasFP(MF);
494 unsigned SavedRegs[CU_NUM_SAVED_REGS] = { 0, 0, 0, 0, 0, 0 };
495 unsigned SavedRegIdx = 0;
497 unsigned OffsetSize = (Is64Bit ? 8 : 4);
499 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r);
500 unsigned PushInstrSize = 1;
501 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
502 unsigned MoveInstrSize = (Is64Bit ? 3 : 2);
503 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2);
505 unsigned StackDivide = (Is64Bit ? 8 : 4);
507 unsigned InstrOffset = 0;
508 unsigned StackAdjust = 0;
509 unsigned StackSize = 0;
511 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB.
512 bool ExpectEnd = false;
513 for (MachineBasicBlock::iterator
514 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) {
515 MachineInstr &MI = *MBBI;
516 unsigned Opc = MI.getOpcode();
517 if (Opc == X86::PROLOG_LABEL) continue;
518 if (!MI.getFlag(MachineInstr::FrameSetup)) break;
520 // We don't exect any more prolog instructions.
521 if (ExpectEnd) return CU::UNWIND_MODE_DWARF;
523 if (Opc == PushInstr) {
524 // If there are too many saved registers, we cannot use compact encoding.
525 if (SavedRegIdx >= CU_NUM_SAVED_REGS) return CU::UNWIND_MODE_DWARF;
527 unsigned Reg = MI.getOperand(0).getReg();
528 if (Reg == (Is64Bit ? X86::RAX : X86::EAX)) {
533 SavedRegs[SavedRegIdx++] = MI.getOperand(0).getReg();
534 StackAdjust += OffsetSize;
535 InstrOffset += PushInstrSize;
536 } else if (Opc == MoveInstr) {
537 unsigned SrcReg = MI.getOperand(1).getReg();
538 unsigned DstReg = MI.getOperand(0).getReg();
540 if (DstReg != FramePtr || SrcReg != StackPtr)
541 return CU::UNWIND_MODE_DWARF;
544 memset(SavedRegs, 0, sizeof(SavedRegs));
546 InstrOffset += MoveInstrSize;
547 } else if (Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
548 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) {
550 // We already have a stack size.
551 return CU::UNWIND_MODE_DWARF;
553 if (!MI.getOperand(0).isReg() ||
554 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() ||
555 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm())
556 // We need this to be a stack adjustment pointer. Something like:
558 // %RSP<def> = SUB64ri8 %RSP, 48
559 return CU::UNWIND_MODE_DWARF;
561 StackSize = MI.getOperand(2).getImm() / StackDivide;
562 SubtractInstrIdx += InstrOffset;
567 // Encode that we are using EBP/RBP as the frame pointer.
568 uint32_t CompactUnwindEncoding = 0;
569 StackAdjust /= StackDivide;
571 if ((StackAdjust & 0xFF) != StackAdjust)
572 // Offset was too big for compact encoding.
573 return CU::UNWIND_MODE_DWARF;
575 // Get the encoding of the saved registers when we have a frame pointer.
576 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit);
577 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
579 CompactUnwindEncoding |= CU::UNWIND_MODE_BP_FRAME;
580 CompactUnwindEncoding |= (StackAdjust & 0xFF) << 16;
581 CompactUnwindEncoding |= RegEnc & CU::UNWIND_BP_FRAME_REGISTERS;
584 uint32_t TotalStackSize = StackAdjust + StackSize;
585 if ((TotalStackSize & 0xFF) == TotalStackSize) {
586 // Frameless stack with a small stack size.
587 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IMMD;
589 // Encode the stack size.
590 CompactUnwindEncoding |= (TotalStackSize & 0xFF) << 16;
592 if ((StackAdjust & 0x7) != StackAdjust)
593 // The extra stack adjustments are too big for us to handle.
594 return CU::UNWIND_MODE_DWARF;
596 // Frameless stack with an offset too large for us to encode compactly.
597 CompactUnwindEncoding |= CU::UNWIND_MODE_STACK_IND;
599 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP'
601 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16;
603 // Encode any extra stack stack adjustments (done via push instructions).
604 CompactUnwindEncoding |= (StackAdjust & 0x7) << 13;
607 // Encode the number of registers saved.
608 CompactUnwindEncoding |= (SavedRegIdx & 0x7) << 10;
610 // Get the encoding of the saved registers when we don't have a frame
613 encodeCompactUnwindRegistersWithoutFrame(SavedRegs, SavedRegIdx,
615 if (RegEnc == ~0U) return CU::UNWIND_MODE_DWARF;
617 // Encode the register encoding.
618 CompactUnwindEncoding |=
619 RegEnc & CU::UNWIND_FRAMELESS_STACK_REG_PERMUTATION;
622 return CompactUnwindEncoding;
625 /// usesTheStack - This function checks if any of the users of EFLAGS
626 /// copies the EFLAGS. We know that the code that lowers COPY of EFLAGS has
627 /// to use the stack, and if we don't adjust the stack we clobber the first
629 /// See X86InstrInfo::copyPhysReg.
630 static bool usesTheStack(MachineFunction &MF) {
631 MachineRegisterInfo &MRI = MF.getRegInfo();
633 for (MachineRegisterInfo::reg_iterator ri = MRI.reg_begin(X86::EFLAGS),
634 re = MRI.reg_end(); ri != re; ++ri)
641 /// emitPrologue - Push callee-saved registers onto the stack, which
642 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
643 /// space for local variables. Also emit labels used by the exception handler to
644 /// generate the exception handling frames.
645 void X86FrameLowering::emitPrologue(MachineFunction &MF) const {
646 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
647 MachineBasicBlock::iterator MBBI = MBB.begin();
648 MachineFrameInfo *MFI = MF.getFrameInfo();
649 const Function *Fn = MF.getFunction();
650 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
651 const X86InstrInfo &TII = *TM.getInstrInfo();
652 MachineModuleInfo &MMI = MF.getMMI();
653 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
654 bool needsFrameMoves = MMI.hasDebugInfo() ||
655 Fn->needsUnwindTableEntry();
656 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
657 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
658 bool HasFP = hasFP(MF);
659 bool Is64Bit = STI.is64Bit();
660 bool IsLP64 = STI.isTarget64BitLP64();
661 bool IsWin64 = STI.isTargetWin64();
662 bool UseLEA = STI.useLeaForSP();
663 unsigned StackAlign = getStackAlignment();
664 unsigned SlotSize = RegInfo->getSlotSize();
665 unsigned FramePtr = RegInfo->getFrameRegister(MF);
666 unsigned StackPtr = RegInfo->getStackRegister();
667 unsigned BasePtr = RegInfo->getBaseRegister();
670 // If we're forcing a stack realignment we can't rely on just the frame
671 // info, we need to know the ABI stack alignment as well in case we
672 // have a call out. Otherwise just make sure we have some alignment - we'll
673 // go with the minimum SlotSize.
674 if (ForceStackAlign) {
676 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
677 else if (MaxAlign < SlotSize)
681 // Add RETADDR move area to callee saved frame size.
682 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
683 if (TailCallReturnAddrDelta < 0)
684 X86FI->setCalleeSavedFrameSize(
685 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
687 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
688 // function, and use up to 128 bytes of stack space, don't have a frame
689 // pointer, calls, or dynamic alloca then we do not need to adjust the
690 // stack pointer (we fit in the Red Zone). We also check that we don't
691 // push and pop from the stack.
692 if (Is64Bit && !Fn->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
693 Attribute::NoRedZone) &&
694 !RegInfo->needsStackRealignment(MF) &&
695 !MFI->hasVarSizedObjects() && // No dynamic alloca.
696 !MFI->adjustsStack() && // No calls.
697 !IsWin64 && // Win64 has no Red Zone
698 !usesTheStack(MF) && // Don't push and pop.
699 !MF.getTarget().Options.EnableSegmentedStacks) { // Regular stack
700 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
701 if (HasFP) MinSize += SlotSize;
702 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
703 MFI->setStackSize(StackSize);
706 // Insert stack pointer adjustment for later moving of return addr. Only
707 // applies to tail call optimized functions where the callee argument stack
708 // size is bigger than the callers.
709 if (TailCallReturnAddrDelta < 0) {
711 BuildMI(MBB, MBBI, DL,
712 TII.get(getSUBriOpcode(IsLP64, -TailCallReturnAddrDelta)),
715 .addImm(-TailCallReturnAddrDelta)
716 .setMIFlag(MachineInstr::FrameSetup);
717 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
720 // Mapping for machine moves:
722 // DST: VirtualFP AND
723 // SRC: VirtualFP => DW_CFA_def_cfa_offset
724 // ELSE => DW_CFA_def_cfa
726 // SRC: VirtualFP AND
727 // DST: Register => DW_CFA_def_cfa_register
730 // OFFSET < 0 => DW_CFA_offset_extended_sf
731 // REG < 64 => DW_CFA_offset + Reg
732 // ELSE => DW_CFA_offset_extended
734 uint64_t NumBytes = 0;
735 int stackGrowth = -SlotSize;
738 // Calculate required stack adjustment.
739 uint64_t FrameSize = StackSize - SlotSize;
740 if (RegInfo->needsStackRealignment(MF)) {
741 // Callee-saved registers are pushed on stack before the stack
743 FrameSize -= X86FI->getCalleeSavedFrameSize();
744 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
746 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
749 // Get the offset of the stack slot for the EBP register, which is
750 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
751 // Update the frame offset adjustment.
752 MFI->setOffsetAdjustment(-NumBytes);
754 // Save EBP/RBP into the appropriate stack slot.
755 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
756 .addReg(FramePtr, RegState::Kill)
757 .setMIFlag(MachineInstr::FrameSetup);
759 if (needsFrameMoves) {
760 // Mark the place where EBP/RBP was saved.
761 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
762 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
765 // Define the current CFA rule to use the provided offset.
767 MachineLocation SPDst(MachineLocation::VirtualFP);
768 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
769 MMI.addFrameMove(FrameLabel, SPDst, SPSrc);
771 MachineLocation SPDst(StackPtr);
772 MachineLocation SPSrc(StackPtr, stackGrowth);
773 MMI.addFrameMove(FrameLabel, SPDst, SPSrc);
776 // Change the rule for the FramePtr to be an "offset" rule.
777 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
778 MachineLocation FPSrc(FramePtr);
779 MMI.addFrameMove(FrameLabel, FPDst, FPSrc);
782 // Update EBP with the new base value.
783 BuildMI(MBB, MBBI, DL,
784 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
786 .setMIFlag(MachineInstr::FrameSetup);
788 if (needsFrameMoves) {
789 // Mark effective beginning of when frame pointer becomes valid.
790 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
791 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
794 // Define the current CFA to use the EBP/RBP register.
795 MachineLocation FPDst(FramePtr);
796 MachineLocation FPSrc(MachineLocation::VirtualFP);
797 MMI.addFrameMove(FrameLabel, FPDst, FPSrc);
800 // Mark the FramePtr as live-in in every block except the entry.
801 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
803 I->addLiveIn(FramePtr);
805 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
808 // Skip the callee-saved push instructions.
809 bool PushedRegs = false;
810 int StackOffset = 2 * stackGrowth;
812 while (MBBI != MBB.end() &&
813 (MBBI->getOpcode() == X86::PUSH32r ||
814 MBBI->getOpcode() == X86::PUSH64r)) {
816 MBBI->setFlag(MachineInstr::FrameSetup);
819 if (!HasFP && needsFrameMoves) {
820 // Mark callee-saved push instruction.
821 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
822 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
824 // Define the current CFA rule to use the provided offset.
825 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr;
826 MachineLocation SPDst(Ptr);
827 MachineLocation SPSrc(Ptr, StackOffset);
828 MMI.addFrameMove(Label, SPDst, SPSrc);
829 StackOffset += stackGrowth;
833 // Realign stack after we pushed callee-saved registers (so that we'll be
834 // able to calculate their offsets from the frame pointer).
836 // NOTE: We push the registers before realigning the stack, so
837 // vector callee-saved (xmm) registers may be saved w/o proper
838 // alignment in this way. However, currently these regs are saved in
839 // stack slots (see X86FrameLowering::spillCalleeSavedRegisters()), so
840 // this shouldn't be a problem.
841 if (RegInfo->needsStackRealignment(MF)) {
842 assert(HasFP && "There should be a frame pointer if stack is realigned.");
844 BuildMI(MBB, MBBI, DL,
845 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr)
848 .setMIFlag(MachineInstr::FrameSetup);
850 // The EFLAGS implicit def is dead.
851 MI->getOperand(3).setIsDead();
854 // If there is an SUB32ri of ESP immediately before this instruction, merge
855 // the two. This can be the case when tail call elimination is enabled and
856 // the callee has more arguments then the caller.
857 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
859 // If there is an ADD32ri or SUB32ri of ESP immediately after this
860 // instruction, merge the two instructions.
861 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
863 // Adjust stack pointer: ESP -= numbytes.
865 // Windows and cygwin/mingw require a prologue helper routine when allocating
866 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw
867 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the
868 // stack and adjust the stack pointer in one go. The 64-bit version of
869 // __chkstk is only responsible for probing the stack. The 64-bit prologue is
870 // responsible for adjusting the stack pointer. Touching the stack at 4K
871 // increments is necessary to ensure that the guard pages used by the OS
872 // virtual memory manager are allocated in correct sequence.
873 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) {
874 const char *StackProbeSymbol;
875 bool isSPUpdateNeeded = false;
878 if (STI.isTargetCygMing())
879 StackProbeSymbol = "___chkstk";
881 StackProbeSymbol = "__chkstk";
882 isSPUpdateNeeded = true;
884 } else if (STI.isTargetCygMing())
885 StackProbeSymbol = "_alloca";
887 StackProbeSymbol = "_chkstk";
889 // Check whether EAX is livein for this function.
890 bool isEAXAlive = isEAXLiveIn(MF);
893 // Sanity check that EAX is not livein for this function.
894 // It should not be, so throw an assert.
895 assert(!Is64Bit && "EAX is livein in x64 case!");
898 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
899 .addReg(X86::EAX, RegState::Kill)
900 .setMIFlag(MachineInstr::FrameSetup);
904 // Handle the 64-bit Windows ABI case where we need to call __chkstk.
905 // Function prologue is responsible for adjusting the stack pointer.
906 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
908 .setMIFlag(MachineInstr::FrameSetup);
910 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive.
911 // We'll also use 4 already allocated bytes for EAX.
912 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
913 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes)
914 .setMIFlag(MachineInstr::FrameSetup);
917 BuildMI(MBB, MBBI, DL,
918 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32))
919 .addExternalSymbol(StackProbeSymbol)
920 .addReg(StackPtr, RegState::Define | RegState::Implicit)
921 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit)
922 .setMIFlag(MachineInstr::FrameSetup);
924 // MSVC x64's __chkstk needs to adjust %rsp.
925 // FIXME: %rax preserves the offset and should be available.
926 if (isSPUpdateNeeded)
927 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
928 UseLEA, TII, *RegInfo);
932 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
934 StackPtr, false, NumBytes - 4);
935 MI->setFlag(MachineInstr::FrameSetup);
936 MBB.insert(MBBI, MI);
939 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, IsLP64,
940 UseLEA, TII, *RegInfo);
942 // If we need a base pointer, set it up here. It's whatever the value
943 // of the stack pointer is at this point. Any variable size objects
944 // will be allocated after this, so we can still use the base pointer
945 // to reference locals.
946 if (RegInfo->hasBasePointer(MF)) {
947 // Update the frame pointer with the current stack pointer.
948 unsigned Opc = Is64Bit ? X86::MOV64rr : X86::MOV32rr;
949 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
951 .setMIFlag(MachineInstr::FrameSetup);
954 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
955 // Mark end of stack pointer adjustment.
956 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
957 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
960 if (!HasFP && NumBytes) {
961 // Define the current CFA rule to use the provided offset.
963 MachineLocation SPDst(MachineLocation::VirtualFP);
964 MachineLocation SPSrc(MachineLocation::VirtualFP,
965 -StackSize + stackGrowth);
966 MMI.addFrameMove(Label, SPDst, SPSrc);
968 MachineLocation SPDst(StackPtr);
969 MachineLocation SPSrc(StackPtr, stackGrowth);
970 MMI.addFrameMove(Label, SPDst, SPSrc);
974 // Emit DWARF info specifying the offsets of the callee-saved registers.
976 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
979 // Darwin 10.7 and greater has support for compact unwind encoding.
980 if (STI.getTargetTriple().isMacOSX() &&
981 !STI.getTargetTriple().isMacOSXVersionLT(10, 7))
982 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF));
985 void X86FrameLowering::emitEpilogue(MachineFunction &MF,
986 MachineBasicBlock &MBB) const {
987 const MachineFrameInfo *MFI = MF.getFrameInfo();
988 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
989 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
990 const X86InstrInfo &TII = *TM.getInstrInfo();
991 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
992 assert(MBBI != MBB.end() && "Returning block has no instructions");
993 unsigned RetOpcode = MBBI->getOpcode();
994 DebugLoc DL = MBBI->getDebugLoc();
995 bool Is64Bit = STI.is64Bit();
996 bool IsLP64 = STI.isTarget64BitLP64();
997 bool UseLEA = STI.useLeaForSP();
998 unsigned StackAlign = getStackAlignment();
999 unsigned SlotSize = RegInfo->getSlotSize();
1000 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1001 unsigned StackPtr = RegInfo->getStackRegister();
1003 switch (RetOpcode) {
1005 llvm_unreachable("Can only insert epilog into returning blocks");
1008 case X86::TCRETURNdi:
1009 case X86::TCRETURNri:
1010 case X86::TCRETURNmi:
1011 case X86::TCRETURNdi64:
1012 case X86::TCRETURNri64:
1013 case X86::TCRETURNmi64:
1014 case X86::EH_RETURN:
1015 case X86::EH_RETURN64:
1016 break; // These are ok
1019 // Get the number of bytes to allocate from the FrameInfo.
1020 uint64_t StackSize = MFI->getStackSize();
1021 uint64_t MaxAlign = MFI->getMaxAlignment();
1022 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1023 uint64_t NumBytes = 0;
1025 // If we're forcing a stack realignment we can't rely on just the frame
1026 // info, we need to know the ABI stack alignment as well in case we
1027 // have a call out. Otherwise just make sure we have some alignment - we'll
1028 // go with the minimum.
1029 if (ForceStackAlign) {
1030 if (MFI->hasCalls())
1031 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign;
1033 MaxAlign = MaxAlign ? MaxAlign : 4;
1037 // Calculate required stack adjustment.
1038 uint64_t FrameSize = StackSize - SlotSize;
1039 if (RegInfo->needsStackRealignment(MF)) {
1040 // Callee-saved registers were pushed on stack before the stack
1042 FrameSize -= CSSize;
1043 NumBytes = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
1045 NumBytes = FrameSize - CSSize;
1049 BuildMI(MBB, MBBI, DL,
1050 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1052 NumBytes = StackSize - CSSize;
1055 // Skip the callee-saved pop instructions.
1056 while (MBBI != MBB.begin()) {
1057 MachineBasicBlock::iterator PI = prior(MBBI);
1058 unsigned Opc = PI->getOpcode();
1060 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE &&
1061 !PI->isTerminator())
1066 MachineBasicBlock::iterator FirstCSPop = MBBI;
1068 DL = MBBI->getDebugLoc();
1070 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1071 // instruction, merge the two instructions.
1072 if (NumBytes || MFI->hasVarSizedObjects())
1073 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1075 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1076 // slot before popping them off! Same applies for the case, when stack was
1078 if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {
1079 if (RegInfo->needsStackRealignment(MF))
1082 unsigned Opc = getLEArOpcode(IsLP64);
1083 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1084 FramePtr, false, -CSSize);
1086 unsigned Opc = (Is64Bit ? X86::MOV64rr : X86::MOV32rr);
1087 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
1090 } else if (NumBytes) {
1091 // Adjust stack pointer back: ESP += numbytes.
1092 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, IsLP64, UseLEA,
1096 // We're returning from function via eh_return.
1097 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1098 MBBI = MBB.getLastNonDebugInstr();
1099 MachineOperand &DestAddr = MBBI->getOperand(0);
1100 assert(DestAddr.isReg() && "Offset should be in register!");
1101 BuildMI(MBB, MBBI, DL,
1102 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1103 StackPtr).addReg(DestAddr.getReg());
1104 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1105 RetOpcode == X86::TCRETURNmi ||
1106 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1107 RetOpcode == X86::TCRETURNmi64) {
1108 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1109 // Tail call return: adjust the stack pointer and jump to callee.
1110 MBBI = MBB.getLastNonDebugInstr();
1111 MachineOperand &JumpTarget = MBBI->getOperand(0);
1112 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1113 assert(StackAdjust.isImm() && "Expecting immediate value.");
1115 // Adjust stack pointer.
1116 int StackAdj = StackAdjust.getImm();
1117 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1119 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1121 // Incoporate the retaddr area.
1122 Offset = StackAdj-MaxTCDelta;
1123 assert(Offset >= 0 && "Offset should never be negative");
1126 // Check for possible merge with preceding ADD instruction.
1127 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1128 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, IsLP64,
1129 UseLEA, TII, *RegInfo);
1132 // Jump to label or value in register.
1133 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1134 MachineInstrBuilder MIB =
1135 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1136 ? X86::TAILJMPd : X86::TAILJMPd64));
1137 if (JumpTarget.isGlobal())
1138 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1139 JumpTarget.getTargetFlags());
1141 assert(JumpTarget.isSymbol());
1142 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1143 JumpTarget.getTargetFlags());
1145 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1146 MachineInstrBuilder MIB =
1147 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1148 ? X86::TAILJMPm : X86::TAILJMPm64));
1149 for (unsigned i = 0; i != 5; ++i)
1150 MIB.addOperand(MBBI->getOperand(i));
1151 } else if (RetOpcode == X86::TCRETURNri64) {
1152 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)).
1153 addReg(JumpTarget.getReg(), RegState::Kill);
1155 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)).
1156 addReg(JumpTarget.getReg(), RegState::Kill);
1159 MachineInstr *NewMI = prior(MBBI);
1160 NewMI->copyImplicitOps(MF, MBBI);
1162 // Delete the pseudo instruction TCRETURN.
1164 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1165 (X86FI->getTCReturnAddrDelta() < 0)) {
1166 // Add the return addr area delta back since we are not tail calling.
1167 int delta = -1*X86FI->getTCReturnAddrDelta();
1168 MBBI = MBB.getLastNonDebugInstr();
1170 // Check for possible merge with preceding ADD instruction.
1171 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1172 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, IsLP64, UseLEA, TII,
1177 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
1178 const X86RegisterInfo *RegInfo =
1179 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1180 const MachineFrameInfo *MFI = MF.getFrameInfo();
1181 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea();
1182 uint64_t StackSize = MFI->getStackSize();
1184 if (RegInfo->hasBasePointer(MF)) {
1185 assert (hasFP(MF) && "VLAs and dynamic stack realign, but no FP?!");
1187 // Skip the saved EBP.
1188 return Offset + RegInfo->getSlotSize();
1190 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1191 return Offset + StackSize;
1193 } else if (RegInfo->needsStackRealignment(MF)) {
1195 // Skip the saved EBP.
1196 return Offset + RegInfo->getSlotSize();
1198 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);
1199 return Offset + StackSize;
1201 // FIXME: Support tail calls
1204 return Offset + StackSize;
1206 // Skip the saved EBP.
1207 Offset += RegInfo->getSlotSize();
1209 // Skip the RETADDR move area
1210 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1211 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1212 if (TailCallReturnAddrDelta < 0)
1213 Offset -= TailCallReturnAddrDelta;
1219 int X86FrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
1220 unsigned &FrameReg) const {
1221 const X86RegisterInfo *RegInfo =
1222 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo());
1223 // We can't calculate offset from frame pointer if the stack is realigned,
1224 // so enforce usage of stack/base pointer. The base pointer is used when we
1225 // have dynamic allocas in addition to dynamic realignment.
1226 if (RegInfo->hasBasePointer(MF))
1227 FrameReg = RegInfo->getBaseRegister();
1228 else if (RegInfo->needsStackRealignment(MF))
1229 FrameReg = RegInfo->getStackRegister();
1231 FrameReg = RegInfo->getFrameRegister(MF);
1232 return getFrameIndexOffset(MF, FI);
1235 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1236 MachineBasicBlock::iterator MI,
1237 const std::vector<CalleeSavedInfo> &CSI,
1238 const TargetRegisterInfo *TRI) const {
1242 DebugLoc DL = MBB.findDebugLoc(MI);
1244 MachineFunction &MF = *MBB.getParent();
1246 unsigned SlotSize = STI.is64Bit() ? 8 : 4;
1247 unsigned FPReg = TRI->getFrameRegister(MF);
1248 unsigned CalleeFrameSize = 0;
1250 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1251 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1253 // Push GPRs. It increases frame size.
1254 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r;
1255 for (unsigned i = CSI.size(); i != 0; --i) {
1256 unsigned Reg = CSI[i-1].getReg();
1257 if (!X86::GR64RegClass.contains(Reg) &&
1258 !X86::GR32RegClass.contains(Reg))
1260 // Add the callee-saved register as live-in. It's killed at the spill.
1263 // X86RegisterInfo::emitPrologue will handle spilling of frame register.
1265 CalleeFrameSize += SlotSize;
1266 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill)
1267 .setMIFlag(MachineInstr::FrameSetup);
1270 X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
1272 // Make XMM regs spilled. X86 does not have ability of push/pop XMM.
1273 // It can be done by spilling XMMs to stack frame.
1274 // Note that only Win64 ABI might spill XMMs.
1275 for (unsigned i = CSI.size(); i != 0; --i) {
1276 unsigned Reg = CSI[i-1].getReg();
1277 if (X86::GR64RegClass.contains(Reg) ||
1278 X86::GR32RegClass.contains(Reg))
1280 // Add the callee-saved register as live-in. It's killed at the spill.
1282 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1283 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(),
1290 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1291 MachineBasicBlock::iterator MI,
1292 const std::vector<CalleeSavedInfo> &CSI,
1293 const TargetRegisterInfo *TRI) const {
1297 DebugLoc DL = MBB.findDebugLoc(MI);
1299 MachineFunction &MF = *MBB.getParent();
1300 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
1302 // Reload XMMs from stack frame.
1303 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1304 unsigned Reg = CSI[i].getReg();
1305 if (X86::GR64RegClass.contains(Reg) ||
1306 X86::GR32RegClass.contains(Reg))
1308 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1309 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
1314 unsigned FPReg = TRI->getFrameRegister(MF);
1315 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r;
1316 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1317 unsigned Reg = CSI[i].getReg();
1318 if (!X86::GR64RegClass.contains(Reg) &&
1319 !X86::GR32RegClass.contains(Reg))
1322 // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
1324 BuildMI(MBB, MI, DL, TII.get(Opc), Reg);
1330 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
1331 RegScavenger *RS) const {
1332 MachineFrameInfo *MFI = MF.getFrameInfo();
1333 const X86RegisterInfo *RegInfo = TM.getRegisterInfo();
1334 unsigned SlotSize = RegInfo->getSlotSize();
1336 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1337 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
1339 if (TailCallReturnAddrDelta < 0) {
1340 // create RETURNADDR area
1349 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
1350 (-1U*SlotSize)+TailCallReturnAddrDelta, true);
1354 assert((TailCallReturnAddrDelta <= 0) &&
1355 "The Delta should always be zero or negative");
1356 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering();
1358 // Create a frame entry for the EBP register that must be saved.
1359 int FrameIdx = MFI->CreateFixedObject(SlotSize,
1361 TFI.getOffsetOfLocalArea() +
1362 TailCallReturnAddrDelta,
1364 assert(FrameIdx == MFI->getObjectIndexBegin() &&
1365 "Slot for EBP register must be last in order to be found!");
1369 // Spill the BasePtr if it's used.
1370 if (RegInfo->hasBasePointer(MF))
1371 MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());
1375 HasNestArgument(const MachineFunction *MF) {
1376 const Function *F = MF->getFunction();
1377 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
1379 if (I->hasNestAttr())
1385 /// GetScratchRegister - Get a temp register for performing work in the
1386 /// segmented stack and the Erlang/HiPE stack prologue. Depending on platform
1387 /// and the properties of the function either one or two registers will be
1388 /// needed. Set primary to true for the first register, false for the second.
1390 GetScratchRegister(bool Is64Bit, const MachineFunction &MF, bool Primary) {
1391 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv();
1394 if (CallingConvention == CallingConv::HiPE) {
1396 return Primary ? X86::R14 : X86::R13;
1398 return Primary ? X86::EBX : X86::EDI;
1402 return Primary ? X86::R11 : X86::R12;
1404 bool IsNested = HasNestArgument(&MF);
1406 if (CallingConvention == CallingConv::X86_FastCall ||
1407 CallingConvention == CallingConv::Fast) {
1409 report_fatal_error("Segmented stacks does not support fastcall with "
1410 "nested function.");
1411 return Primary ? X86::EAX : X86::ECX;
1414 return Primary ? X86::EDX : X86::EAX;
1415 return Primary ? X86::ECX : X86::EAX;
1418 // The stack limit in the TCB is set to this many bytes above the actual stack
1420 static const uint64_t kSplitStackAvailable = 256;
1423 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
1424 MachineBasicBlock &prologueMBB = MF.front();
1425 MachineFrameInfo *MFI = MF.getFrameInfo();
1426 const X86InstrInfo &TII = *TM.getInstrInfo();
1428 bool Is64Bit = STI.is64Bit();
1429 unsigned TlsReg, TlsOffset;
1432 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1433 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1434 "Scratch register is live-in");
1436 if (MF.getFunction()->isVarArg())
1437 report_fatal_error("Segmented stacks do not support vararg functions.");
1438 if (!STI.isTargetLinux() && !STI.isTargetDarwin() &&
1439 !STI.isTargetWin32() && !STI.isTargetFreeBSD())
1440 report_fatal_error("Segmented stacks not supported on this platform.");
1442 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock();
1443 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock();
1444 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1445 bool IsNested = false;
1447 // We need to know if the function has a nest argument only in 64 bit mode.
1449 IsNested = HasNestArgument(&MF);
1451 // The MOV R10, RAX needs to be in a different block, since the RET we emit in
1452 // allocMBB needs to be last (terminating) instruction.
1454 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
1455 e = prologueMBB.livein_end(); i != e; i++) {
1456 allocMBB->addLiveIn(*i);
1457 checkMBB->addLiveIn(*i);
1461 allocMBB->addLiveIn(X86::R10);
1463 MF.push_front(allocMBB);
1464 MF.push_front(checkMBB);
1466 // Eventually StackSize will be calculated by a link-time pass; which will
1467 // also decide whether checking code needs to be injected into this particular
1469 StackSize = MFI->getStackSize();
1471 // When the frame size is less than 256 we just compare the stack
1472 // boundary directly to the value of the stack pointer, per gcc.
1473 bool CompareStackPointer = StackSize < kSplitStackAvailable;
1475 // Read the limit off the current stacklet off the stack_guard location.
1477 if (STI.isTargetLinux()) {
1480 } else if (STI.isTargetDarwin()) {
1482 TlsOffset = 0x60 + 90*8; // See pthread_machdep.h. Steal TLS slot 90.
1483 } else if (STI.isTargetFreeBSD()) {
1487 report_fatal_error("Segmented stacks not supported on this platform.");
1490 if (CompareStackPointer)
1491 ScratchReg = X86::RSP;
1493 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP)
1494 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1496 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg)
1497 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1499 if (STI.isTargetLinux()) {
1502 } else if (STI.isTargetDarwin()) {
1504 TlsOffset = 0x48 + 90*4;
1505 } else if (STI.isTargetWin32()) {
1507 TlsOffset = 0x14; // pvArbitrary, reserved for application use
1508 } else if (STI.isTargetFreeBSD()) {
1509 report_fatal_error("Segmented stacks not supported on FreeBSD i386.");
1511 report_fatal_error("Segmented stacks not supported on this platform.");
1514 if (CompareStackPointer)
1515 ScratchReg = X86::ESP;
1517 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
1518 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
1520 if (STI.isTargetLinux() || STI.isTargetWin32()) {
1521 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
1522 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
1523 } else if (STI.isTargetDarwin()) {
1525 // TlsOffset doesn't fit into a mod r/m byte so we need an extra register
1526 unsigned ScratchReg2;
1528 if (CompareStackPointer) {
1529 // The primary scratch register is available for holding the TLS offset
1530 ScratchReg2 = GetScratchRegister(Is64Bit, MF, true);
1531 SaveScratch2 = false;
1533 // Need to use a second register to hold the TLS offset
1534 ScratchReg2 = GetScratchRegister(Is64Bit, MF, false);
1536 // Unfortunately, with fastcc the second scratch register may hold an arg
1537 SaveScratch2 = MF.getRegInfo().isLiveIn(ScratchReg2);
1540 // If Scratch2 is live-in then it needs to be saved
1541 assert((!MF.getRegInfo().isLiveIn(ScratchReg2) || SaveScratch2) &&
1542 "Scratch register is live-in and not saved");
1545 BuildMI(checkMBB, DL, TII.get(X86::PUSH32r))
1546 .addReg(ScratchReg2, RegState::Kill);
1548 BuildMI(checkMBB, DL, TII.get(X86::MOV32ri), ScratchReg2)
1550 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm))
1552 .addReg(ScratchReg2).addImm(1).addReg(0)
1557 BuildMI(checkMBB, DL, TII.get(X86::POP32r), ScratchReg2);
1561 // This jump is taken if SP >= (Stacklet Limit + Stack Space required).
1562 // It jumps to normal execution of the function body.
1563 BuildMI(checkMBB, DL, TII.get(X86::JA_4)).addMBB(&prologueMBB);
1565 // On 32 bit we first push the arguments size and then the frame size. On 64
1566 // bit, we pass the stack frame size in r10 and the argument size in r11.
1568 // Functions with nested arguments use R10, so it needs to be saved across
1569 // the call to _morestack
1572 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10);
1574 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10)
1576 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11)
1577 .addImm(X86FI->getArgumentStackSize());
1578 MF.getRegInfo().setPhysRegUsed(X86::R10);
1579 MF.getRegInfo().setPhysRegUsed(X86::R11);
1581 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1582 .addImm(X86FI->getArgumentStackSize());
1583 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
1587 // __morestack is in libgcc
1589 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32))
1590 .addExternalSymbol("__morestack");
1592 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32))
1593 .addExternalSymbol("__morestack");
1596 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
1598 BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
1600 allocMBB->addSuccessor(&prologueMBB);
1602 checkMBB->addSuccessor(allocMBB);
1603 checkMBB->addSuccessor(&prologueMBB);
1610 /// Erlang programs may need a special prologue to handle the stack size they
1611 /// might need at runtime. That is because Erlang/OTP does not implement a C
1612 /// stack but uses a custom implementation of hybrid stack/heap architecture.
1613 /// (for more information see Eric Stenman's Ph.D. thesis:
1614 /// http://publications.uu.se/uu/fulltext/nbn_se_uu_diva-2688.pdf)
1617 /// temp0 = sp - MaxStack
1618 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1622 /// call inc_stack # doubles the stack space
1623 /// temp0 = sp - MaxStack
1624 /// if( temp0 < SP_LIMIT(P) ) goto IncStack else goto OldStart
1625 void X86FrameLowering::adjustForHiPEPrologue(MachineFunction &MF) const {
1626 const X86InstrInfo &TII = *TM.getInstrInfo();
1627 MachineFrameInfo *MFI = MF.getFrameInfo();
1628 const unsigned SlotSize = TM.getRegisterInfo()->getSlotSize();
1629 const bool Is64Bit = STI.is64Bit();
1631 // HiPE-specific values
1632 const unsigned HipeLeafWords = 24;
1633 const unsigned CCRegisteredArgs = Is64Bit ? 6 : 5;
1634 const unsigned Guaranteed = HipeLeafWords * SlotSize;
1635 unsigned CallerStkArity = MF.getFunction()->arg_size() > CCRegisteredArgs ?
1636 MF.getFunction()->arg_size() - CCRegisteredArgs : 0;
1637 unsigned MaxStack = MFI->getStackSize() + CallerStkArity*SlotSize + SlotSize;
1639 assert(STI.isTargetLinux() &&
1640 "HiPE prologue is only supported on Linux operating systems.");
1642 // Compute the largest caller's frame that is needed to fit the callees'
1643 // frames. This 'MaxStack' is computed from:
1645 // a) the fixed frame size, which is the space needed for all spilled temps,
1646 // b) outgoing on-stack parameter areas, and
1647 // c) the minimum stack space this function needs to make available for the
1648 // functions it calls (a tunable ABI property).
1649 if (MFI->hasCalls()) {
1650 unsigned MoreStackForCalls = 0;
1652 for (MachineFunction::iterator MBBI = MF.begin(), MBBE = MF.end();
1653 MBBI != MBBE; ++MBBI)
1654 for (MachineBasicBlock::iterator MI = MBBI->begin(), ME = MBBI->end();
1659 // Get callee operand.
1660 const MachineOperand &MO = MI->getOperand(0);
1662 // Only take account of global function calls (no closures etc.).
1666 const Function *F = dyn_cast<Function>(MO.getGlobal());
1670 // Do not update 'MaxStack' for primitive and built-in functions
1671 // (encoded with names either starting with "erlang."/"bif_" or not
1672 // having a ".", such as a simple <Module>.<Function>.<Arity>, or an
1673 // "_", such as the BIF "suspend_0") as they are executed on another
1675 if (F->getName().find("erlang.") != StringRef::npos ||
1676 F->getName().find("bif_") != StringRef::npos ||
1677 F->getName().find_first_of("._") == StringRef::npos)
1680 unsigned CalleeStkArity =
1681 F->arg_size() > CCRegisteredArgs ? F->arg_size()-CCRegisteredArgs : 0;
1682 if (HipeLeafWords - 1 > CalleeStkArity)
1683 MoreStackForCalls = std::max(MoreStackForCalls,
1684 (HipeLeafWords - 1 - CalleeStkArity) * SlotSize);
1686 MaxStack += MoreStackForCalls;
1689 // If the stack frame needed is larger than the guaranteed then runtime checks
1690 // and calls to "inc_stack_0" BIF should be inserted in the assembly prologue.
1691 if (MaxStack > Guaranteed) {
1692 MachineBasicBlock &prologueMBB = MF.front();
1693 MachineBasicBlock *stackCheckMBB = MF.CreateMachineBasicBlock();
1694 MachineBasicBlock *incStackMBB = MF.CreateMachineBasicBlock();
1696 for (MachineBasicBlock::livein_iterator I = prologueMBB.livein_begin(),
1697 E = prologueMBB.livein_end(); I != E; I++) {
1698 stackCheckMBB->addLiveIn(*I);
1699 incStackMBB->addLiveIn(*I);
1702 MF.push_front(incStackMBB);
1703 MF.push_front(stackCheckMBB);
1705 unsigned ScratchReg, SPReg, PReg, SPLimitOffset;
1706 unsigned LEAop, CMPop, CALLop;
1710 LEAop = X86::LEA64r;
1711 CMPop = X86::CMP64rm;
1712 CALLop = X86::CALL64pcrel32;
1713 SPLimitOffset = 0x90;
1717 LEAop = X86::LEA32r;
1718 CMPop = X86::CMP32rm;
1719 CALLop = X86::CALLpcrel32;
1720 SPLimitOffset = 0x4c;
1723 ScratchReg = GetScratchRegister(Is64Bit, MF, true);
1724 assert(!MF.getRegInfo().isLiveIn(ScratchReg) &&
1725 "HiPE prologue scratch register is live-in");
1727 // Create new MBB for StackCheck:
1728 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(LEAop), ScratchReg),
1729 SPReg, false, -MaxStack);
1730 // SPLimitOffset is in a fixed heap location (pointed by BP).
1731 addRegOffset(BuildMI(stackCheckMBB, DL, TII.get(CMPop))
1732 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1733 BuildMI(stackCheckMBB, DL, TII.get(X86::JAE_4)).addMBB(&prologueMBB);
1735 // Create new MBB for IncStack:
1736 BuildMI(incStackMBB, DL, TII.get(CALLop)).
1737 addExternalSymbol("inc_stack_0");
1738 addRegOffset(BuildMI(incStackMBB, DL, TII.get(LEAop), ScratchReg),
1739 SPReg, false, -MaxStack);
1740 addRegOffset(BuildMI(incStackMBB, DL, TII.get(CMPop))
1741 .addReg(ScratchReg), PReg, false, SPLimitOffset);
1742 BuildMI(incStackMBB, DL, TII.get(X86::JLE_4)).addMBB(incStackMBB);
1744 stackCheckMBB->addSuccessor(&prologueMBB, 99);
1745 stackCheckMBB->addSuccessor(incStackMBB, 1);
1746 incStackMBB->addSuccessor(&prologueMBB, 99);
1747 incStackMBB->addSuccessor(incStackMBB, 1);
1754 void X86FrameLowering::
1755 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1756 MachineBasicBlock::iterator I) const {
1757 const X86InstrInfo &TII = *TM.getInstrInfo();
1758 const X86RegisterInfo &RegInfo = *TM.getRegisterInfo();
1759 unsigned StackPtr = RegInfo.getStackRegister();
1760 bool reseveCallFrame = hasReservedCallFrame(MF);
1761 int Opcode = I->getOpcode();
1762 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode();
1763 bool IsLP64 = STI.isTarget64BitLP64();
1764 DebugLoc DL = I->getDebugLoc();
1765 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0;
1766 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0;
1769 if (!reseveCallFrame) {
1770 // If the stack pointer can be changed after prologue, turn the
1771 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
1772 // adjcallstackdown instruction into 'add ESP, <amt>'
1773 // TODO: consider using push / pop instead of sub + store / add
1777 // We need to keep the stack aligned properly. To do this, we round the
1778 // amount of space needed for the outgoing arguments up to the next
1779 // alignment boundary.
1780 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1781 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
1783 MachineInstr *New = 0;
1784 if (Opcode == TII.getCallFrameSetupOpcode()) {
1785 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(IsLP64, Amount)),
1790 assert(Opcode == TII.getCallFrameDestroyOpcode());
1792 // Factor out the amount the callee already popped.
1793 Amount -= CalleeAmt;
1796 unsigned Opc = getADDriOpcode(IsLP64, Amount);
1797 New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1798 .addReg(StackPtr).addImm(Amount);
1803 // The EFLAGS implicit def is dead.
1804 New->getOperand(3).setIsDead();
1806 // Replace the pseudo instruction with a new instruction.
1813 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) {
1814 // If we are performing frame pointer elimination and if the callee pops
1815 // something off the stack pointer, add it back. We do this until we have
1816 // more advanced stack pointer tracking ability.
1817 unsigned Opc = getSUBriOpcode(IsLP64, CalleeAmt);
1818 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr)
1819 .addReg(StackPtr).addImm(CalleeAmt);
1821 // The EFLAGS implicit def is dead.
1822 New->getOperand(3).setIsDead();
1824 // We are not tracking the stack pointer adjustment by the callee, so make
1825 // sure we restore the stack pointer immediately after the call, there may
1826 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions.
1827 MachineBasicBlock::iterator B = MBB.begin();
1828 while (I != B && !llvm::prior(I)->isCall())