1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Support/CFG.h"
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
77 SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
84 bool hasBaseOrIndexReg() const {
85 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
88 /// isRIPRelative - Return true if this addressing mode is already RIP
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
104 dbgs() << "X86ISelAddressMode " << this << '\n';
105 dbgs() << "Base_Reg ";
106 if (Base_Reg.getNode() != 0)
107 Base_Reg.getNode()->dump();
110 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
111 << " Scale" << Scale << '\n'
113 if (IndexReg.getNode() != 0)
114 IndexReg.getNode()->dump();
117 dbgs() << " Disp " << Disp << '\n'
134 dbgs() << " JT" << JT << " Align" << Align << '\n';
140 //===--------------------------------------------------------------------===//
141 /// ISel - X86 specific code to select X86 machine instructions for
142 /// SelectionDAG operations.
144 class X86DAGToDAGISel : public SelectionDAGISel {
145 /// X86Lowering - This object fully describes how to lower LLVM code to an
146 /// X86-specific SelectionDAG.
147 const X86TargetLowering &X86Lowering;
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel),
160 X86Lowering(*tm.getTargetLowering()),
161 Subtarget(&tm.getSubtarget<X86Subtarget>()),
164 virtual const char *getPassName() const {
165 return "X86 DAG->DAG Instruction Selection";
168 virtual void EmitFunctionEntryCode();
170 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
172 virtual void PreprocessISelDAG();
174 inline bool immSext8(SDNode *N) const {
175 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
178 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
179 // sign extended field.
180 inline bool i64immSExt32(SDNode *N) const {
181 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
182 return (int64_t)v == (int32_t)v;
185 // Include the pieces autogenerated from the target description.
186 #include "X86GenDAGISel.inc"
189 SDNode *Select(SDNode *N);
190 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
191 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
192 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT);
194 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
195 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
196 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
197 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
199 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
200 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
201 SDValue &Scale, SDValue &Index, SDValue &Disp,
203 bool SelectLEAAddr(SDValue N, SDValue &Base,
204 SDValue &Scale, SDValue &Index, SDValue &Disp,
206 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
207 SDValue &Scale, SDValue &Index, SDValue &Disp,
209 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
210 SDValue &Base, SDValue &Scale,
211 SDValue &Index, SDValue &Disp,
213 SDValue &NodeWithChain);
215 bool TryFoldLoad(SDNode *P, SDValue N,
216 SDValue &Base, SDValue &Scale,
217 SDValue &Index, SDValue &Disp,
220 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
221 /// inline asm expressions.
222 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
224 std::vector<SDValue> &OutOps);
226 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
228 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
229 SDValue &Scale, SDValue &Index,
230 SDValue &Disp, SDValue &Segment) {
231 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
232 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
234 Scale = getI8Imm(AM.Scale);
236 // These are 32-bit even in 64-bit mode since RIP relative offset
239 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(),
243 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
244 AM.Align, AM.Disp, AM.SymbolFlags);
246 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
247 else if (AM.JT != -1)
248 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
249 else if (AM.BlockAddr)
250 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
251 true, AM.SymbolFlags);
253 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
255 if (AM.Segment.getNode())
256 Segment = AM.Segment;
258 Segment = CurDAG->getRegister(0, MVT::i32);
261 /// getI8Imm - Return a target constant with the specified value, of type
263 inline SDValue getI8Imm(unsigned Imm) {
264 return CurDAG->getTargetConstant(Imm, MVT::i8);
267 /// getI32Imm - Return a target constant with the specified value, of type
269 inline SDValue getI32Imm(unsigned Imm) {
270 return CurDAG->getTargetConstant(Imm, MVT::i32);
273 /// getGlobalBaseReg - Return an SDNode that returns the value of
274 /// the global base register. Output instructions required to
275 /// initialize the global base register, if necessary.
277 SDNode *getGlobalBaseReg();
279 /// getTargetMachine - Return a reference to the TargetMachine, casted
280 /// to the target-specific type.
281 const X86TargetMachine &getTargetMachine() {
282 return static_cast<const X86TargetMachine &>(TM);
285 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
286 /// to the target-specific type.
287 const X86InstrInfo *getInstrInfo() {
288 return getTargetMachine().getInstrInfo();
295 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
296 if (OptLevel == CodeGenOpt::None) return false;
301 if (N.getOpcode() != ISD::LOAD)
304 // If N is a load, do additional profitability checks.
306 switch (U->getOpcode()) {
319 SDValue Op1 = U->getOperand(1);
321 // If the other operand is a 8-bit immediate we should fold the immediate
322 // instead. This reduces code size.
324 // movl 4(%esp), %eax
328 // addl 4(%esp), %eax
329 // The former is 2 bytes shorter. In case where the increment is 1, then
330 // the saving can be 4 bytes (by using incl %eax).
331 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
332 if (Imm->getAPIntValue().isSignedIntN(8))
335 // If the other operand is a TLS address, we should fold it instead.
338 // leal i@NTPOFF(%eax), %eax
340 // movl $i@NTPOFF, %eax
342 // if the block also has an access to a second TLS address this will save
344 // FIXME: This is probably also true for non TLS addresses.
345 if (Op1.getOpcode() == X86ISD::Wrapper) {
346 SDValue Val = Op1.getOperand(0);
347 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
357 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
358 /// load's chain operand and move load below the call's chain operand.
359 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
360 SDValue Call, SDValue OrigChain) {
361 SmallVector<SDValue, 8> Ops;
362 SDValue Chain = OrigChain.getOperand(0);
363 if (Chain.getNode() == Load.getNode())
364 Ops.push_back(Load.getOperand(0));
366 assert(Chain.getOpcode() == ISD::TokenFactor &&
367 "Unexpected chain operand");
368 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
369 if (Chain.getOperand(i).getNode() == Load.getNode())
370 Ops.push_back(Load.getOperand(0));
372 Ops.push_back(Chain.getOperand(i));
374 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
375 MVT::Other, &Ops[0], Ops.size());
377 Ops.push_back(NewChain);
379 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
380 Ops.push_back(OrigChain.getOperand(i));
381 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
382 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
383 Load.getOperand(1), Load.getOperand(2));
385 Ops.push_back(SDValue(Load.getNode(), 1));
386 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
387 Ops.push_back(Call.getOperand(i));
388 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size());
391 /// isCalleeLoad - Return true if call address is a load and it can be
392 /// moved below CALLSEQ_START and the chains leading up to the call.
393 /// Return the CALLSEQ_START by reference as a second output.
394 /// In the case of a tail call, there isn't a callseq node between the call
395 /// chain and the load.
396 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
397 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
399 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
402 LD->getAddressingMode() != ISD::UNINDEXED ||
403 LD->getExtensionType() != ISD::NON_EXTLOAD)
406 // Now let's find the callseq_start.
407 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
408 if (!Chain.hasOneUse())
410 Chain = Chain.getOperand(0);
413 if (!Chain.getNumOperands())
415 if (Chain.getOperand(0).getNode() == Callee.getNode())
417 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
418 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
419 Callee.getValue(1).hasOneUse())
424 void X86DAGToDAGISel::PreprocessISelDAG() {
425 // OptForSize is used in pattern predicates that isel is matching.
426 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
428 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
429 E = CurDAG->allnodes_end(); I != E; ) {
430 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
432 if (OptLevel != CodeGenOpt::None &&
433 (N->getOpcode() == X86ISD::CALL ||
434 N->getOpcode() == X86ISD::TC_RETURN)) {
435 /// Also try moving call address load from outside callseq_start to just
436 /// before the call to allow it to be folded.
454 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
455 SDValue Chain = N->getOperand(0);
456 SDValue Load = N->getOperand(1);
457 if (!isCalleeLoad(Load, Chain, HasCallSeq))
459 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
464 // Lower fpround and fpextend nodes that target the FP stack to be store and
465 // load to the stack. This is a gross hack. We would like to simply mark
466 // these as being illegal, but when we do that, legalize produces these when
467 // it expands calls, then expands these in the same legalize pass. We would
468 // like dag combine to be able to hack on these between the call expansion
469 // and the node legalization. As such this pass basically does "really
470 // late" legalization of these inline with the X86 isel pass.
471 // FIXME: This should only happen when not compiled with -O0.
472 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
475 // If the source and destination are SSE registers, then this is a legal
476 // conversion that should not be lowered.
477 EVT SrcVT = N->getOperand(0).getValueType();
478 EVT DstVT = N->getValueType(0);
479 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
480 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
481 if (SrcIsSSE && DstIsSSE)
484 if (!SrcIsSSE && !DstIsSSE) {
485 // If this is an FPStack extension, it is a noop.
486 if (N->getOpcode() == ISD::FP_EXTEND)
488 // If this is a value-preserving FPStack truncation, it is a noop.
489 if (N->getConstantOperandVal(1))
493 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
494 // FPStack has extload and truncstore. SSE can fold direct loads into other
495 // operations. Based on this, decide what we want to do.
497 if (N->getOpcode() == ISD::FP_ROUND)
498 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
500 MemVT = SrcIsSSE ? SrcVT : DstVT;
502 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
503 DebugLoc dl = N->getDebugLoc();
505 // FIXME: optimize the case where the src/dest is a load or store?
506 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
508 MemTmp, MachinePointerInfo(), MemVT,
510 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
511 MachinePointerInfo(),
512 MemVT, false, false, 0);
514 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
515 // extload we created. This will cause general havok on the dag because
516 // anything below the conversion could be folded into other existing nodes.
517 // To avoid invalidating 'I', back it up to the convert node.
519 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
521 // Now that we did that, the node is dead. Increment the iterator to the
522 // next node to process, then delete N.
524 CurDAG->DeleteNode(N);
529 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
530 /// the main function.
531 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
532 MachineFrameInfo *MFI) {
533 const TargetInstrInfo *TII = TM.getInstrInfo();
534 if (Subtarget->isTargetCygMing()) {
536 Subtarget->is64Bit() ? X86::WINCALL64pcrel32 : X86::CALLpcrel32;
537 BuildMI(BB, DebugLoc(),
538 TII->get(CallOp)).addExternalSymbol("__main");
542 void X86DAGToDAGISel::EmitFunctionEntryCode() {
543 // If this is main, emit special code for main.
544 if (const Function *Fn = MF->getFunction())
545 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
546 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
550 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
551 SDValue Address = N->getOperand(1);
553 // load gs:0 -> GS segment register.
554 // load fs:0 -> FS segment register.
556 // This optimization is valid because the GNU TLS model defines that
557 // gs:0 (or fs:0 on X86-64) contains its own address.
558 // For more information see http://people.redhat.com/drepper/tls.pdf
559 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
560 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
561 Subtarget->isTargetELF())
562 switch (N->getPointerInfo().getAddrSpace()) {
564 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
567 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
574 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
575 /// into an addressing mode. These wrap things that will resolve down into a
576 /// symbol reference. If no match is possible, this returns true, otherwise it
578 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
579 // If the addressing mode already has a symbol as the displacement, we can
580 // never match another symbol.
581 if (AM.hasSymbolicDisplacement())
584 SDValue N0 = N.getOperand(0);
585 CodeModel::Model M = TM.getCodeModel();
587 // Handle X86-64 rip-relative addresses. We check this before checking direct
588 // folding because RIP is preferable to non-RIP accesses.
589 if (Subtarget->is64Bit() &&
590 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
591 // they cannot be folded into immediate fields.
592 // FIXME: This can be improved for kernel and other models?
593 (M == CodeModel::Small || M == CodeModel::Kernel) &&
594 // Base and index reg must be 0 in order to use %rip as base and lowering
596 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
597 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
598 int64_t Offset = AM.Disp + G->getOffset();
599 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
600 AM.GV = G->getGlobal();
602 AM.SymbolFlags = G->getTargetFlags();
603 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
604 int64_t Offset = AM.Disp + CP->getOffset();
605 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
606 AM.CP = CP->getConstVal();
607 AM.Align = CP->getAlignment();
609 AM.SymbolFlags = CP->getTargetFlags();
610 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
611 AM.ES = S->getSymbol();
612 AM.SymbolFlags = S->getTargetFlags();
613 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
614 AM.JT = J->getIndex();
615 AM.SymbolFlags = J->getTargetFlags();
617 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
618 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
621 if (N.getOpcode() == X86ISD::WrapperRIP)
622 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
626 // Handle the case when globals fit in our immediate field: This is true for
627 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit
628 // mode, this results in a non-RIP-relative computation.
629 if (!Subtarget->is64Bit() ||
630 ((M == CodeModel::Small || M == CodeModel::Kernel) &&
631 TM.getRelocationModel() == Reloc::Static)) {
632 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
633 AM.GV = G->getGlobal();
634 AM.Disp += G->getOffset();
635 AM.SymbolFlags = G->getTargetFlags();
636 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
637 AM.CP = CP->getConstVal();
638 AM.Align = CP->getAlignment();
639 AM.Disp += CP->getOffset();
640 AM.SymbolFlags = CP->getTargetFlags();
641 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
642 AM.ES = S->getSymbol();
643 AM.SymbolFlags = S->getTargetFlags();
644 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
645 AM.JT = J->getIndex();
646 AM.SymbolFlags = J->getTargetFlags();
648 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
649 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
657 /// MatchAddress - Add the specified node to the specified addressing mode,
658 /// returning true if it cannot be done. This just pattern matches for the
660 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
661 if (MatchAddressRecursively(N, AM, 0))
664 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
665 // a smaller encoding and avoids a scaled-index.
667 AM.BaseType == X86ISelAddressMode::RegBase &&
668 AM.Base_Reg.getNode() == 0) {
669 AM.Base_Reg = AM.IndexReg;
673 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
674 // because it has a smaller encoding.
675 // TODO: Which other code models can use this?
676 if (TM.getCodeModel() == CodeModel::Small &&
677 Subtarget->is64Bit() &&
679 AM.BaseType == X86ISelAddressMode::RegBase &&
680 AM.Base_Reg.getNode() == 0 &&
681 AM.IndexReg.getNode() == 0 &&
682 AM.SymbolFlags == X86II::MO_NO_FLAG &&
683 AM.hasSymbolicDisplacement())
684 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
689 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
691 bool is64Bit = Subtarget->is64Bit();
692 DebugLoc dl = N.getDebugLoc();
694 dbgs() << "MatchAddress: ";
699 return MatchAddressBase(N, AM);
701 CodeModel::Model M = TM.getCodeModel();
703 // If this is already a %rip relative address, we can only merge immediates
704 // into it. Instead of handling this in every case, we handle it here.
705 // RIP relative addressing: %rip + 32-bit displacement!
706 if (AM.isRIPRelative()) {
707 // FIXME: JumpTable and ExternalSymbol address currently don't like
708 // displacements. It isn't very important, but this should be fixed for
710 if (!AM.ES && AM.JT != -1) return true;
712 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) {
713 int64_t Val = AM.Disp + Cst->getSExtValue();
714 if (X86::isOffsetSuitableForCodeModel(Val, M,
715 AM.hasSymbolicDisplacement())) {
723 switch (N.getOpcode()) {
725 case ISD::Constant: {
726 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
728 X86::isOffsetSuitableForCodeModel(AM.Disp + Val, M,
729 AM.hasSymbolicDisplacement())) {
736 case X86ISD::Wrapper:
737 case X86ISD::WrapperRIP:
738 if (!MatchWrapper(N, AM))
743 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
747 case ISD::FrameIndex:
748 if (AM.BaseType == X86ISelAddressMode::RegBase
749 && AM.Base_Reg.getNode() == 0) {
750 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
751 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
757 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
761 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
762 unsigned Val = CN->getZExtValue();
763 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
764 // that the base operand remains free for further matching. If
765 // the base doesn't end up getting used, a post-processing step
766 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
767 if (Val == 1 || Val == 2 || Val == 3) {
769 SDValue ShVal = N.getNode()->getOperand(0);
771 // Okay, we know that we have a scale by now. However, if the scaled
772 // value is an add of something and a constant, we can fold the
773 // constant into the disp field here.
774 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
775 AM.IndexReg = ShVal.getNode()->getOperand(0);
776 ConstantSDNode *AddVal =
777 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
778 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
780 X86::isOffsetSuitableForCodeModel(Disp, M,
781 AM.hasSymbolicDisplacement()))
795 // A mul_lohi where we need the low part can be folded as a plain multiply.
796 if (N.getResNo() != 0) break;
799 case X86ISD::MUL_IMM:
800 // X*[3,5,9] -> X+X*[2,4,8]
801 if (AM.BaseType == X86ISelAddressMode::RegBase &&
802 AM.Base_Reg.getNode() == 0 &&
803 AM.IndexReg.getNode() == 0) {
805 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
806 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
807 CN->getZExtValue() == 9) {
808 AM.Scale = unsigned(CN->getZExtValue())-1;
810 SDValue MulVal = N.getNode()->getOperand(0);
813 // Okay, we know that we have a scale by now. However, if the scaled
814 // value is an add of something and a constant, we can fold the
815 // constant into the disp field here.
816 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
817 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
818 Reg = MulVal.getNode()->getOperand(0);
819 ConstantSDNode *AddVal =
820 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
821 uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
824 X86::isOffsetSuitableForCodeModel(Disp, M,
825 AM.hasSymbolicDisplacement()))
828 Reg = N.getNode()->getOperand(0);
830 Reg = N.getNode()->getOperand(0);
833 AM.IndexReg = AM.Base_Reg = Reg;
840 // Given A-B, if A can be completely folded into the address and
841 // the index field with the index field unused, use -B as the index.
842 // This is a win if a has multiple parts that can be folded into
843 // the address. Also, this saves a mov if the base register has
844 // other uses, since it avoids a two-address sub instruction, however
845 // it costs an additional mov if the index register has other uses.
847 // Add an artificial use to this node so that we can keep track of
848 // it if it gets CSE'd with a different node.
849 HandleSDNode Handle(N);
851 // Test if the LHS of the sub can be folded.
852 X86ISelAddressMode Backup = AM;
853 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
857 // Test if the index field is free for use.
858 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
864 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
865 // If the RHS involves a register with multiple uses, this
866 // transformation incurs an extra mov, due to the neg instruction
867 // clobbering its operand.
868 if (!RHS.getNode()->hasOneUse() ||
869 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
870 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
871 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
872 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
873 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
875 // If the base is a register with multiple uses, this
876 // transformation may save a mov.
877 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
878 AM.Base_Reg.getNode() &&
879 !AM.Base_Reg.getNode()->hasOneUse()) ||
880 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
882 // If the folded LHS was interesting, this transformation saves
883 // address arithmetic.
884 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
885 ((AM.Disp != 0) && (Backup.Disp == 0)) +
886 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
888 // If it doesn't look like it may be an overall win, don't do it.
894 // Ok, the transformation is legal and appears profitable. Go for it.
895 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
896 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
900 // Insert the new nodes into the topological ordering.
901 if (Zero.getNode()->getNodeId() == -1 ||
902 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
903 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
904 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
906 if (Neg.getNode()->getNodeId() == -1 ||
907 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
908 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
909 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
915 // Add an artificial use to this node so that we can keep track of
916 // it if it gets CSE'd with a different node.
917 HandleSDNode Handle(N);
919 X86ISelAddressMode Backup = AM;
920 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
921 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
925 // Try again after commuting the operands.
926 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
927 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
931 // If we couldn't fold both operands into the address at the same time,
932 // see if we can just put each operand into a register and fold at least
934 if (AM.BaseType == X86ISelAddressMode::RegBase &&
935 !AM.Base_Reg.getNode() &&
936 !AM.IndexReg.getNode()) {
937 N = Handle.getValue();
938 AM.Base_Reg = N.getOperand(0);
939 AM.IndexReg = N.getOperand(1);
943 N = Handle.getValue();
948 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
949 if (CurDAG->isBaseWithConstantOffset(N)) {
950 X86ISelAddressMode Backup = AM;
951 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
952 uint64_t Offset = CN->getSExtValue();
954 // Start with the LHS as an addr mode.
955 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
956 // Address could not have picked a GV address for the displacement.
958 // On x86-64, the resultant disp must fit in 32-bits.
960 X86::isOffsetSuitableForCodeModel(AM.Disp + Offset, M,
961 AM.hasSymbolicDisplacement()))) {
970 // Perform some heroic transforms on an and of a constant-count shift
971 // with a constant to enable use of the scaled offset field.
973 SDValue Shift = N.getOperand(0);
974 if (Shift.getNumOperands() != 2) break;
976 // Scale must not be used already.
977 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
979 SDValue X = Shift.getOperand(0);
980 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
981 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
982 if (!C1 || !C2) break;
984 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This
985 // allows us to convert the shift and and into an h-register extract and
987 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) {
988 unsigned ScaleLog = 8 - C1->getZExtValue();
989 if (ScaleLog > 0 && ScaleLog < 4 &&
990 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
991 SDValue Eight = CurDAG->getConstant(8, MVT::i8);
992 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
993 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
995 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
997 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
998 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1001 // Insert the new nodes into the topological ordering.
1002 if (Eight.getNode()->getNodeId() == -1 ||
1003 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1004 CurDAG->RepositionNode(X.getNode(), Eight.getNode());
1005 Eight.getNode()->setNodeId(X.getNode()->getNodeId());
1007 if (Mask.getNode()->getNodeId() == -1 ||
1008 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1009 CurDAG->RepositionNode(X.getNode(), Mask.getNode());
1010 Mask.getNode()->setNodeId(X.getNode()->getNodeId());
1012 if (Srl.getNode()->getNodeId() == -1 ||
1013 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1014 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode());
1015 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId());
1017 if (And.getNode()->getNodeId() == -1 ||
1018 And.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1019 CurDAG->RepositionNode(N.getNode(), And.getNode());
1020 And.getNode()->setNodeId(N.getNode()->getNodeId());
1022 if (ShlCount.getNode()->getNodeId() == -1 ||
1023 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1024 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode());
1025 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId());
1027 if (Shl.getNode()->getNodeId() == -1 ||
1028 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1029 CurDAG->RepositionNode(N.getNode(), Shl.getNode());
1030 Shl.getNode()->setNodeId(N.getNode()->getNodeId());
1032 CurDAG->ReplaceAllUsesWith(N, Shl);
1034 AM.Scale = (1 << ScaleLog);
1039 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
1040 // allows us to fold the shift into this addressing mode.
1041 if (Shift.getOpcode() != ISD::SHL) break;
1043 // Not likely to be profitable if either the AND or SHIFT node has more
1044 // than one use (unless all uses are for address computation). Besides,
1045 // isel mechanism requires their node ids to be reused.
1046 if (!N.hasOneUse() || !Shift.hasOneUse())
1049 // Verify that the shift amount is something we can fold.
1050 unsigned ShiftCst = C1->getZExtValue();
1051 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
1054 // Get the new AND mask, this folds to a constant.
1055 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1056 SDValue(C2, 0), SDValue(C1, 0));
1057 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
1059 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1060 NewAND, SDValue(C1, 0));
1062 // Insert the new nodes into the topological ordering.
1063 if (C1->getNodeId() > X.getNode()->getNodeId()) {
1064 CurDAG->RepositionNode(X.getNode(), C1);
1065 C1->setNodeId(X.getNode()->getNodeId());
1067 if (NewANDMask.getNode()->getNodeId() == -1 ||
1068 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1069 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
1070 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
1072 if (NewAND.getNode()->getNodeId() == -1 ||
1073 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1074 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
1075 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
1077 if (NewSHIFT.getNode()->getNodeId() == -1 ||
1078 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1079 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
1080 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
1083 CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
1085 AM.Scale = 1 << ShiftCst;
1086 AM.IndexReg = NewAND;
1091 return MatchAddressBase(N, AM);
1094 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1095 /// specified addressing mode without any further recursion.
1096 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1097 // Is the base register already occupied?
1098 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1099 // If so, check to see if the scale index register is set.
1100 if (AM.IndexReg.getNode() == 0) {
1106 // Otherwise, we cannot select it.
1110 // Default, generate it as a register.
1111 AM.BaseType = X86ISelAddressMode::RegBase;
1116 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1117 /// It returns the operands which make up the maximal addressing mode it can
1118 /// match by reference.
1120 /// Parent is the parent node of the addr operand that is being matched. It
1121 /// is always a load, store, atomic node, or null. It is only null when
1122 /// checking memory operands for inline asm nodes.
1123 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1124 SDValue &Scale, SDValue &Index,
1125 SDValue &Disp, SDValue &Segment) {
1126 X86ISelAddressMode AM;
1129 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1130 // that are not a MemSDNode, and thus don't have proper addrspace info.
1131 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1132 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1133 Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme
1134 unsigned AddrSpace =
1135 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1136 // AddrSpace 256 -> GS, 257 -> FS.
1137 if (AddrSpace == 256)
1138 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1139 if (AddrSpace == 257)
1140 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1143 if (MatchAddress(N, AM))
1146 EVT VT = N.getValueType();
1147 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1148 if (!AM.Base_Reg.getNode())
1149 AM.Base_Reg = CurDAG->getRegister(0, VT);
1152 if (!AM.IndexReg.getNode())
1153 AM.IndexReg = CurDAG->getRegister(0, VT);
1155 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1159 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1160 /// match a load whose top elements are either undef or zeros. The load flavor
1161 /// is derived from the type of N, which is either v4f32 or v2f64.
1164 /// PatternChainNode: this is the matched node that has a chain input and
1166 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1167 SDValue N, SDValue &Base,
1168 SDValue &Scale, SDValue &Index,
1169 SDValue &Disp, SDValue &Segment,
1170 SDValue &PatternNodeWithChain) {
1171 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1172 PatternNodeWithChain = N.getOperand(0);
1173 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1174 PatternNodeWithChain.hasOneUse() &&
1175 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1176 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1177 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1178 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1184 // Also handle the case where we explicitly require zeros in the top
1185 // elements. This is a vector shuffle from the zero vector.
1186 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1187 // Check to see if the top elements are all zeros (or bitcast of zeros).
1188 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1189 N.getOperand(0).getNode()->hasOneUse() &&
1190 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1191 N.getOperand(0).getOperand(0).hasOneUse() &&
1192 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1193 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1194 // Okay, this is a zero extending load. Fold it.
1195 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1196 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1198 PatternNodeWithChain = SDValue(LD, 0);
1205 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1206 /// mode it matches can be cost effectively emitted as an LEA instruction.
1207 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1208 SDValue &Base, SDValue &Scale,
1209 SDValue &Index, SDValue &Disp,
1211 X86ISelAddressMode AM;
1213 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1215 SDValue Copy = AM.Segment;
1216 SDValue T = CurDAG->getRegister(0, MVT::i32);
1218 if (MatchAddress(N, AM))
1220 assert (T == AM.Segment);
1223 EVT VT = N.getValueType();
1224 unsigned Complexity = 0;
1225 if (AM.BaseType == X86ISelAddressMode::RegBase)
1226 if (AM.Base_Reg.getNode())
1229 AM.Base_Reg = CurDAG->getRegister(0, VT);
1230 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1233 if (AM.IndexReg.getNode())
1236 AM.IndexReg = CurDAG->getRegister(0, VT);
1238 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1243 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1244 // to a LEA. This is determined with some expermentation but is by no means
1245 // optimal (especially for code size consideration). LEA is nice because of
1246 // its three-address nature. Tweak the cost function again when we can run
1247 // convertToThreeAddress() at register allocation time.
1248 if (AM.hasSymbolicDisplacement()) {
1249 // For X86-64, we should always use lea to materialize RIP relative
1251 if (Subtarget->is64Bit())
1257 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1260 // If it isn't worth using an LEA, reject it.
1261 if (Complexity <= 2)
1264 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1268 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1269 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1270 SDValue &Scale, SDValue &Index,
1271 SDValue &Disp, SDValue &Segment) {
1272 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1273 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1275 X86ISelAddressMode AM;
1276 AM.GV = GA->getGlobal();
1277 AM.Disp += GA->getOffset();
1278 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1279 AM.SymbolFlags = GA->getTargetFlags();
1281 if (N.getValueType() == MVT::i32) {
1283 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1285 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1288 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1293 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1294 SDValue &Base, SDValue &Scale,
1295 SDValue &Index, SDValue &Disp,
1297 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1298 !IsProfitableToFold(N, P, P) ||
1299 !IsLegalToFold(N, P, P, OptLevel))
1302 return SelectAddr(N.getNode(),
1303 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1306 /// getGlobalBaseReg - Return an SDNode that returns the value of
1307 /// the global base register. Output instructions required to
1308 /// initialize the global base register, if necessary.
1310 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1311 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1312 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1315 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1316 SDValue Chain = Node->getOperand(0);
1317 SDValue In1 = Node->getOperand(1);
1318 SDValue In2L = Node->getOperand(2);
1319 SDValue In2H = Node->getOperand(3);
1320 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1321 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1323 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1324 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1325 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1326 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1327 MVT::i32, MVT::i32, MVT::Other, Ops,
1328 array_lengthof(Ops));
1329 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1333 // FIXME: Figure out some way to unify this with the 'or' and other code
1335 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1336 if (Node->hasAnyUseOfValue(0))
1339 // Optimize common patterns for __sync_add_and_fetch and
1340 // __sync_sub_and_fetch where the result is not used. This allows us
1341 // to use "lock" version of add, sub, inc, dec instructions.
1342 // FIXME: Do not use special instructions but instead add the "lock"
1343 // prefix to the target node somehow. The extra information will then be
1344 // transferred to machine instruction and it denotes the prefix.
1345 SDValue Chain = Node->getOperand(0);
1346 SDValue Ptr = Node->getOperand(1);
1347 SDValue Val = Node->getOperand(2);
1348 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1349 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1352 bool isInc = false, isDec = false, isSub = false, isCN = false;
1353 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1356 int64_t CNVal = CN->getSExtValue();
1359 else if (CNVal == -1)
1361 else if (CNVal >= 0)
1362 Val = CurDAG->getTargetConstant(CNVal, NVT);
1365 Val = CurDAG->getTargetConstant(-CNVal, NVT);
1367 } else if (Val.hasOneUse() &&
1368 Val.getOpcode() == ISD::SUB &&
1369 X86::isZeroNode(Val.getOperand(0))) {
1371 Val = Val.getOperand(1);
1375 switch (NVT.getSimpleVT().SimpleTy) {
1379 Opc = X86::LOCK_INC8m;
1381 Opc = X86::LOCK_DEC8m;
1384 Opc = X86::LOCK_SUB8mi;
1386 Opc = X86::LOCK_SUB8mr;
1389 Opc = X86::LOCK_ADD8mi;
1391 Opc = X86::LOCK_ADD8mr;
1396 Opc = X86::LOCK_INC16m;
1398 Opc = X86::LOCK_DEC16m;
1401 if (immSext8(Val.getNode()))
1402 Opc = X86::LOCK_SUB16mi8;
1404 Opc = X86::LOCK_SUB16mi;
1406 Opc = X86::LOCK_SUB16mr;
1409 if (immSext8(Val.getNode()))
1410 Opc = X86::LOCK_ADD16mi8;
1412 Opc = X86::LOCK_ADD16mi;
1414 Opc = X86::LOCK_ADD16mr;
1419 Opc = X86::LOCK_INC32m;
1421 Opc = X86::LOCK_DEC32m;
1424 if (immSext8(Val.getNode()))
1425 Opc = X86::LOCK_SUB32mi8;
1427 Opc = X86::LOCK_SUB32mi;
1429 Opc = X86::LOCK_SUB32mr;
1432 if (immSext8(Val.getNode()))
1433 Opc = X86::LOCK_ADD32mi8;
1435 Opc = X86::LOCK_ADD32mi;
1437 Opc = X86::LOCK_ADD32mr;
1442 Opc = X86::LOCK_INC64m;
1444 Opc = X86::LOCK_DEC64m;
1446 Opc = X86::LOCK_SUB64mr;
1448 if (immSext8(Val.getNode()))
1449 Opc = X86::LOCK_SUB64mi8;
1450 else if (i64immSExt32(Val.getNode()))
1451 Opc = X86::LOCK_SUB64mi32;
1454 Opc = X86::LOCK_ADD64mr;
1456 if (immSext8(Val.getNode()))
1457 Opc = X86::LOCK_ADD64mi8;
1458 else if (i64immSExt32(Val.getNode()))
1459 Opc = X86::LOCK_ADD64mi32;
1465 DebugLoc dl = Node->getDebugLoc();
1466 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1468 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1469 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1470 if (isInc || isDec) {
1471 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1472 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
1473 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1474 SDValue RetVals[] = { Undef, Ret };
1475 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1477 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1478 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1479 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1480 SDValue RetVals[] = { Undef, Ret };
1481 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1507 static const unsigned int AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1531 X86::LOCK_AND64mi32,
1544 X86::LOCK_XOR64mi32,
1549 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
1550 if (Node->hasAnyUseOfValue(0))
1553 // Optimize common patterns for __sync_or_and_fetch and similar arith
1554 // operations where the result is not used. This allows us to use the "lock"
1555 // version of the arithmetic instruction.
1556 // FIXME: Same as for 'add' and 'sub', try to merge those down here.
1557 SDValue Chain = Node->getOperand(0);
1558 SDValue Ptr = Node->getOperand(1);
1559 SDValue Val = Node->getOperand(2);
1560 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1561 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1564 // Which index into the table.
1566 switch (Node->getOpcode()) {
1567 case ISD::ATOMIC_LOAD_OR:
1570 case ISD::ATOMIC_LOAD_AND:
1573 case ISD::ATOMIC_LOAD_XOR:
1581 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1584 Val = CurDAG->getTargetConstant(CN->getSExtValue(), NVT);
1588 switch (NVT.getSimpleVT().SimpleTy) {
1592 Opc = AtomicOpcTbl[Op][ConstantI8];
1594 Opc = AtomicOpcTbl[Op][I8];
1598 if (immSext8(Val.getNode()))
1599 Opc = AtomicOpcTbl[Op][SextConstantI16];
1601 Opc = AtomicOpcTbl[Op][ConstantI16];
1603 Opc = AtomicOpcTbl[Op][I16];
1607 if (immSext8(Val.getNode()))
1608 Opc = AtomicOpcTbl[Op][SextConstantI32];
1610 Opc = AtomicOpcTbl[Op][ConstantI32];
1612 Opc = AtomicOpcTbl[Op][I32];
1616 if (immSext8(Val.getNode()))
1617 Opc = AtomicOpcTbl[Op][SextConstantI64];
1618 else if (i64immSExt32(Val.getNode()))
1619 Opc = AtomicOpcTbl[Op][ConstantI64];
1621 Opc = AtomicOpcTbl[Op][I64];
1625 DebugLoc dl = Node->getDebugLoc();
1626 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1628 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1629 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1630 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1631 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1632 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1633 SDValue RetVals[] = { Undef, Ret };
1634 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1637 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1638 /// any uses which require the SF or OF bits to be accurate.
1639 static bool HasNoSignedComparisonUses(SDNode *N) {
1640 // Examine each user of the node.
1641 for (SDNode::use_iterator UI = N->use_begin(),
1642 UE = N->use_end(); UI != UE; ++UI) {
1643 // Only examine CopyToReg uses.
1644 if (UI->getOpcode() != ISD::CopyToReg)
1646 // Only examine CopyToReg uses that copy to EFLAGS.
1647 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1650 // Examine each user of the CopyToReg use.
1651 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1652 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1653 // Only examine the Flag result.
1654 if (FlagUI.getUse().getResNo() != 1) continue;
1655 // Anything unusual: assume conservatively.
1656 if (!FlagUI->isMachineOpcode()) return false;
1657 // Examine the opcode of the user.
1658 switch (FlagUI->getMachineOpcode()) {
1659 // These comparisons don't treat the most significant bit specially.
1660 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1661 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1662 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1663 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1664 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1665 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1666 case X86::CMOVA16rr: case X86::CMOVA16rm:
1667 case X86::CMOVA32rr: case X86::CMOVA32rm:
1668 case X86::CMOVA64rr: case X86::CMOVA64rm:
1669 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1670 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1671 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1672 case X86::CMOVB16rr: case X86::CMOVB16rm:
1673 case X86::CMOVB32rr: case X86::CMOVB32rm:
1674 case X86::CMOVB64rr: case X86::CMOVB64rm:
1675 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1676 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1677 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1678 case X86::CMOVE16rr: case X86::CMOVE16rm:
1679 case X86::CMOVE32rr: case X86::CMOVE32rm:
1680 case X86::CMOVE64rr: case X86::CMOVE64rm:
1681 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1682 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1683 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1684 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1685 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1686 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1687 case X86::CMOVP16rr: case X86::CMOVP16rm:
1688 case X86::CMOVP32rr: case X86::CMOVP32rm:
1689 case X86::CMOVP64rr: case X86::CMOVP64rm:
1691 // Anything else: assume conservatively.
1692 default: return false;
1699 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
1700 EVT NVT = Node->getValueType(0);
1702 unsigned Opcode = Node->getOpcode();
1703 DebugLoc dl = Node->getDebugLoc();
1705 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
1707 if (Node->isMachineOpcode()) {
1708 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
1709 return NULL; // Already selected.
1714 case X86ISD::GlobalBaseReg:
1715 return getGlobalBaseReg();
1717 case X86ISD::ATOMOR64_DAG:
1718 return SelectAtomic64(Node, X86::ATOMOR6432);
1719 case X86ISD::ATOMXOR64_DAG:
1720 return SelectAtomic64(Node, X86::ATOMXOR6432);
1721 case X86ISD::ATOMADD64_DAG:
1722 return SelectAtomic64(Node, X86::ATOMADD6432);
1723 case X86ISD::ATOMSUB64_DAG:
1724 return SelectAtomic64(Node, X86::ATOMSUB6432);
1725 case X86ISD::ATOMNAND64_DAG:
1726 return SelectAtomic64(Node, X86::ATOMNAND6432);
1727 case X86ISD::ATOMAND64_DAG:
1728 return SelectAtomic64(Node, X86::ATOMAND6432);
1729 case X86ISD::ATOMSWAP64_DAG:
1730 return SelectAtomic64(Node, X86::ATOMSWAP6432);
1732 case ISD::ATOMIC_LOAD_ADD: {
1733 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
1738 case ISD::ATOMIC_LOAD_XOR:
1739 case ISD::ATOMIC_LOAD_AND:
1740 case ISD::ATOMIC_LOAD_OR: {
1741 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
1749 // For operations of the form (x << C1) op C2, check if we can use a smaller
1750 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
1751 SDValue N0 = Node->getOperand(0);
1752 SDValue N1 = Node->getOperand(1);
1754 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
1757 // i8 is unshrinkable, i16 should be promoted to i32.
1758 if (NVT != MVT::i32 && NVT != MVT::i64)
1761 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
1762 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
1763 if (!Cst || !ShlCst)
1766 int64_t Val = Cst->getSExtValue();
1767 uint64_t ShlVal = ShlCst->getZExtValue();
1769 // Make sure that we don't change the operation by removing bits.
1770 // This only matters for OR and XOR, AND is unaffected.
1771 if (Opcode != ISD::AND && ((Val >> ShlVal) << ShlVal) != Val)
1774 unsigned ShlOp, Op = 0;
1777 // Check the minimum bitwidth for the new constant.
1778 // TODO: AND32ri is the same as AND64ri32 with zext imm.
1779 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
1780 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
1781 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
1783 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
1786 // Bail if there is no smaller encoding.
1790 switch (NVT.getSimpleVT().SimpleTy) {
1791 default: llvm_unreachable("Unsupported VT!");
1793 assert(CstVT == MVT::i8);
1794 ShlOp = X86::SHL32ri;
1797 case ISD::AND: Op = X86::AND32ri8; break;
1798 case ISD::OR: Op = X86::OR32ri8; break;
1799 case ISD::XOR: Op = X86::XOR32ri8; break;
1803 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
1804 ShlOp = X86::SHL64ri;
1807 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
1808 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
1809 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
1814 // Emit the smaller op and the shift.
1815 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
1816 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
1817 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
1821 case X86ISD::UMUL: {
1822 SDValue N0 = Node->getOperand(0);
1823 SDValue N1 = Node->getOperand(1);
1826 switch (NVT.getSimpleVT().SimpleTy) {
1827 default: llvm_unreachable("Unsupported VT!");
1828 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
1829 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
1830 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
1831 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
1834 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1835 N0, SDValue()).getValue(1);
1837 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
1838 SDValue Ops[] = {N1, InFlag};
1839 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops, 2);
1841 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
1842 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
1843 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
1847 case ISD::SMUL_LOHI:
1848 case ISD::UMUL_LOHI: {
1849 SDValue N0 = Node->getOperand(0);
1850 SDValue N1 = Node->getOperand(1);
1852 bool isSigned = Opcode == ISD::SMUL_LOHI;
1854 switch (NVT.getSimpleVT().SimpleTy) {
1855 default: llvm_unreachable("Unsupported VT!");
1856 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1857 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1858 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1859 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1862 switch (NVT.getSimpleVT().SimpleTy) {
1863 default: llvm_unreachable("Unsupported VT!");
1864 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1865 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1866 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1867 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1871 unsigned LoReg, HiReg;
1872 switch (NVT.getSimpleVT().SimpleTy) {
1873 default: llvm_unreachable("Unsupported VT!");
1874 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1875 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1876 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1877 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1880 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1881 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1882 // Multiply is commmutative.
1884 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1889 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1890 N0, SDValue()).getValue(1);
1893 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1896 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
1897 array_lengthof(Ops));
1898 InFlag = SDValue(CNode, 1);
1900 // Update the chain.
1901 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1903 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag);
1904 InFlag = SDValue(CNode, 0);
1907 // Prevent use of AH in a REX instruction by referencing AX instead.
1908 if (HiReg == X86::AH && Subtarget->is64Bit() &&
1909 !SDValue(Node, 1).use_empty()) {
1910 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1911 X86::AX, MVT::i16, InFlag);
1912 InFlag = Result.getValue(2);
1913 // Get the low part if needed. Don't use getCopyFromReg for aliasing
1915 if (!SDValue(Node, 0).use_empty())
1916 ReplaceUses(SDValue(Node, 1),
1917 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1919 // Shift AX down 8 bits.
1920 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
1922 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1923 // Then truncate it down to i8.
1924 ReplaceUses(SDValue(Node, 1),
1925 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
1927 // Copy the low half of the result, if it is needed.
1928 if (!SDValue(Node, 0).use_empty()) {
1929 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1930 LoReg, NVT, InFlag);
1931 InFlag = Result.getValue(2);
1932 ReplaceUses(SDValue(Node, 0), Result);
1933 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1935 // Copy the high half of the result, if it is needed.
1936 if (!SDValue(Node, 1).use_empty()) {
1937 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1938 HiReg, NVT, InFlag);
1939 InFlag = Result.getValue(2);
1940 ReplaceUses(SDValue(Node, 1), Result);
1941 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
1948 case ISD::UDIVREM: {
1949 SDValue N0 = Node->getOperand(0);
1950 SDValue N1 = Node->getOperand(1);
1952 bool isSigned = Opcode == ISD::SDIVREM;
1954 switch (NVT.getSimpleVT().SimpleTy) {
1955 default: llvm_unreachable("Unsupported VT!");
1956 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1957 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1958 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1959 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1962 switch (NVT.getSimpleVT().SimpleTy) {
1963 default: llvm_unreachable("Unsupported VT!");
1964 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1965 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1966 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1967 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1971 unsigned LoReg, HiReg, ClrReg;
1972 unsigned ClrOpcode, SExtOpcode;
1973 switch (NVT.getSimpleVT().SimpleTy) {
1974 default: llvm_unreachable("Unsupported VT!");
1976 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
1978 SExtOpcode = X86::CBW;
1981 LoReg = X86::AX; HiReg = X86::DX;
1982 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
1983 SExtOpcode = X86::CWD;
1986 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
1987 ClrOpcode = X86::MOV32r0;
1988 SExtOpcode = X86::CDQ;
1991 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
1992 ClrOpcode = X86::MOV64r0;
1993 SExtOpcode = X86::CQO;
1997 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1998 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1999 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2002 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2003 // Special case for div8, just use a move with zero extension to AX to
2004 // clear the upper 8 bits (AH).
2005 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2006 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2007 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2009 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2011 array_lengthof(Ops)), 0);
2012 Chain = Move.getValue(1);
2013 ReplaceUses(N0.getValue(1), Chain);
2016 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2017 Chain = CurDAG->getEntryNode();
2019 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2020 InFlag = Chain.getValue(1);
2023 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2024 LoReg, N0, SDValue()).getValue(1);
2025 if (isSigned && !signBitIsZero) {
2026 // Sign extend the low part into the high part.
2028 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2030 // Zero out the high part, effectively zero extending the input.
2032 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
2033 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2034 ClrNode, InFlag).getValue(1);
2039 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2042 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
2043 array_lengthof(Ops));
2044 InFlag = SDValue(CNode, 1);
2045 // Update the chain.
2046 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2049 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2052 // Prevent use of AH in a REX instruction by referencing AX instead.
2053 // Shift it down 8 bits.
2054 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2055 !SDValue(Node, 1).use_empty()) {
2056 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2057 X86::AX, MVT::i16, InFlag);
2058 InFlag = Result.getValue(2);
2060 // If we also need AL (the quotient), get it by extracting a subreg from
2061 // Result. The fast register allocator does not like multiple CopyFromReg
2062 // nodes using aliasing registers.
2063 if (!SDValue(Node, 0).use_empty())
2064 ReplaceUses(SDValue(Node, 0),
2065 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2067 // Shift AX right by 8 bits instead of using AH.
2068 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2070 CurDAG->getTargetConstant(8, MVT::i8)),
2072 ReplaceUses(SDValue(Node, 1),
2073 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2075 // Copy the division (low) result, if it is needed.
2076 if (!SDValue(Node, 0).use_empty()) {
2077 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2078 LoReg, NVT, InFlag);
2079 InFlag = Result.getValue(2);
2080 ReplaceUses(SDValue(Node, 0), Result);
2081 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2083 // Copy the remainder (high) result, if it is needed.
2084 if (!SDValue(Node, 1).use_empty()) {
2085 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2086 HiReg, NVT, InFlag);
2087 InFlag = Result.getValue(2);
2088 ReplaceUses(SDValue(Node, 1), Result);
2089 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2095 SDValue N0 = Node->getOperand(0);
2096 SDValue N1 = Node->getOperand(1);
2098 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2099 // use a smaller encoding.
2100 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2101 HasNoSignedComparisonUses(Node))
2102 // Look past the truncate if CMP is the only use of it.
2103 N0 = N0.getOperand(0);
2104 if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2105 N0.getValueType() != MVT::i8 &&
2106 X86::isZeroNode(N1)) {
2107 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2110 // For example, convert "testl %eax, $8" to "testb %al, $8"
2111 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2112 (!(C->getZExtValue() & 0x80) ||
2113 HasNoSignedComparisonUses(Node))) {
2114 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2115 SDValue Reg = N0.getNode()->getOperand(0);
2117 // On x86-32, only the ABCD registers have 8-bit subregisters.
2118 if (!Subtarget->is64Bit()) {
2119 TargetRegisterClass *TRC = 0;
2120 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2121 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2122 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2123 default: llvm_unreachable("Unsupported TEST operand type!");
2125 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2126 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2127 Reg.getValueType(), Reg, RC), 0);
2130 // Extract the l-register.
2131 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2135 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
2138 // For example, "testl %eax, $2048" to "testb %ah, $8".
2139 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2140 (!(C->getZExtValue() & 0x8000) ||
2141 HasNoSignedComparisonUses(Node))) {
2142 // Shift the immediate right by 8 bits.
2143 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2145 SDValue Reg = N0.getNode()->getOperand(0);
2147 // Put the value in an ABCD register.
2148 TargetRegisterClass *TRC = 0;
2149 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2150 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2151 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2152 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2153 default: llvm_unreachable("Unsupported TEST operand type!");
2155 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2156 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2157 Reg.getValueType(), Reg, RC), 0);
2159 // Extract the h-register.
2160 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2163 // Emit a testb. No special NOREX tricks are needed since there's
2164 // only one GPR operand!
2165 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2166 Subreg, ShiftedImm);
2169 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2170 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2171 N0.getValueType() != MVT::i16 &&
2172 (!(C->getZExtValue() & 0x8000) ||
2173 HasNoSignedComparisonUses(Node))) {
2174 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2175 SDValue Reg = N0.getNode()->getOperand(0);
2177 // Extract the 16-bit subregister.
2178 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2182 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
2185 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2186 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2187 N0.getValueType() == MVT::i64 &&
2188 (!(C->getZExtValue() & 0x80000000) ||
2189 HasNoSignedComparisonUses(Node))) {
2190 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2191 SDValue Reg = N0.getNode()->getOperand(0);
2193 // Extract the 32-bit subregister.
2194 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2198 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
2205 SDNode *ResNode = SelectCode(Node);
2207 DEBUG(dbgs() << "=> ";
2208 if (ResNode == NULL || ResNode == Node)
2211 ResNode->dump(CurDAG);
2217 bool X86DAGToDAGISel::
2218 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2219 std::vector<SDValue> &OutOps) {
2220 SDValue Op0, Op1, Op2, Op3, Op4;
2221 switch (ConstraintCode) {
2222 case 'o': // offsetable ??
2223 case 'v': // not offsetable ??
2224 default: return true;
2226 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
2231 OutOps.push_back(Op0);
2232 OutOps.push_back(Op1);
2233 OutOps.push_back(Op2);
2234 OutOps.push_back(Op3);
2235 OutOps.push_back(Op4);
2239 /// createX86ISelDag - This pass converts a legalized DAG into a
2240 /// X86-specific DAG, ready for instruction scheduling.
2242 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2243 llvm::CodeGenOpt::Level OptLevel) {
2244 return new X86DAGToDAGISel(TM, OptLevel);