1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
39 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
41 //===----------------------------------------------------------------------===//
42 // Pattern Matcher Implementation
43 //===----------------------------------------------------------------------===//
46 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
47 /// SDValue's instead of register numbers for the leaves of the matched
49 struct X86ISelAddressMode {
55 // This is really a union, discriminated by BaseType!
63 const GlobalValue *GV;
65 const BlockAddress *BlockAddr;
68 unsigned Align; // CP alignment.
69 unsigned char SymbolFlags; // X86II::MO_*
72 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
73 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
74 SymbolFlags(X86II::MO_NO_FLAG) {
77 bool hasSymbolicDisplacement() const {
78 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
81 bool hasBaseOrIndexReg() const {
82 return BaseType == FrameIndexBase ||
83 IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
86 /// isRIPRelative - Return true if this addressing mode is already RIP
88 bool isRIPRelative() const {
89 if (BaseType != RegBase) return false;
90 if (RegisterSDNode *RegNode =
91 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
92 return RegNode->getReg() == X86::RIP;
96 void setBaseReg(SDValue Reg) {
101 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
103 dbgs() << "X86ISelAddressMode " << this << '\n';
104 dbgs() << "Base_Reg ";
105 if (Base_Reg.getNode() != 0)
106 Base_Reg.getNode()->dump();
109 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
110 << " Scale" << Scale << '\n'
112 if (IndexReg.getNode() != 0)
113 IndexReg.getNode()->dump();
116 dbgs() << " Disp " << Disp << '\n'
133 dbgs() << " JT" << JT << " Align" << Align << '\n';
140 //===--------------------------------------------------------------------===//
141 /// ISel - X86 specific code to select X86 machine instructions for
142 /// SelectionDAG operations.
144 class X86DAGToDAGISel final : public SelectionDAGISel {
145 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
146 /// make the right decision when generating code for different targets.
147 const X86Subtarget *Subtarget;
149 /// OptForSize - If true, selector should try to optimize for code size
150 /// instead of performance.
154 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
155 : SelectionDAGISel(tm, OptLevel),
156 Subtarget(&tm.getSubtarget<X86Subtarget>()),
159 const char *getPassName() const override {
160 return "X86 DAG->DAG Instruction Selection";
163 void EmitFunctionEntryCode() override;
165 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
167 void PreprocessISelDAG() override;
169 inline bool immSext8(SDNode *N) const {
170 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
173 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
174 // sign extended field.
175 inline bool i64immSExt32(SDNode *N) const {
176 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
177 return (int64_t)v == (int32_t)v;
180 // Include the pieces autogenerated from the target description.
181 #include "X86GenDAGISel.inc"
184 SDNode *Select(SDNode *N) override;
185 SDNode *SelectGather(SDNode *N, unsigned Opc);
186 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
187 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
189 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
190 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
191 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
192 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
193 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
195 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
196 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
197 SDValue &Scale, SDValue &Index, SDValue &Disp,
199 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
200 bool SelectLEAAddr(SDValue N, SDValue &Base,
201 SDValue &Scale, SDValue &Index, SDValue &Disp,
203 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
204 SDValue &Scale, SDValue &Index, SDValue &Disp,
206 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
207 SDValue &Scale, SDValue &Index, SDValue &Disp,
209 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
210 SDValue &Base, SDValue &Scale,
211 SDValue &Index, SDValue &Disp,
213 SDValue &NodeWithChain);
215 bool TryFoldLoad(SDNode *P, SDValue N,
216 SDValue &Base, SDValue &Scale,
217 SDValue &Index, SDValue &Disp,
220 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
221 /// inline asm expressions.
222 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
224 std::vector<SDValue> &OutOps) override;
226 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
228 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
229 SDValue &Scale, SDValue &Index,
230 SDValue &Disp, SDValue &Segment) {
231 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
232 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
233 getTargetLowering()->getPointerTy()) :
235 Scale = getI8Imm(AM.Scale);
237 // These are 32-bit even in 64-bit mode since RIP relative offset
240 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
244 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
245 AM.Align, AM.Disp, AM.SymbolFlags);
247 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
248 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
249 } else if (AM.JT != -1) {
250 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
251 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
252 } else if (AM.BlockAddr)
253 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
256 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
258 if (AM.Segment.getNode())
259 Segment = AM.Segment;
261 Segment = CurDAG->getRegister(0, MVT::i32);
264 /// getI8Imm - Return a target constant with the specified value, of type
266 inline SDValue getI8Imm(unsigned Imm) {
267 return CurDAG->getTargetConstant(Imm, MVT::i8);
270 /// getI32Imm - Return a target constant with the specified value, of type
272 inline SDValue getI32Imm(unsigned Imm) {
273 return CurDAG->getTargetConstant(Imm, MVT::i32);
276 /// getGlobalBaseReg - Return an SDNode that returns the value of
277 /// the global base register. Output instructions required to
278 /// initialize the global base register, if necessary.
280 SDNode *getGlobalBaseReg();
282 /// getTargetMachine - Return a reference to the TargetMachine, casted
283 /// to the target-specific type.
284 const X86TargetMachine &getTargetMachine() const {
285 return static_cast<const X86TargetMachine &>(TM);
288 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
289 /// to the target-specific type.
290 const X86InstrInfo *getInstrInfo() const {
291 return getTargetMachine().getInstrInfo();
298 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
299 if (OptLevel == CodeGenOpt::None) return false;
304 if (N.getOpcode() != ISD::LOAD)
307 // If N is a load, do additional profitability checks.
309 switch (U->getOpcode()) {
322 SDValue Op1 = U->getOperand(1);
324 // If the other operand is a 8-bit immediate we should fold the immediate
325 // instead. This reduces code size.
327 // movl 4(%esp), %eax
331 // addl 4(%esp), %eax
332 // The former is 2 bytes shorter. In case where the increment is 1, then
333 // the saving can be 4 bytes (by using incl %eax).
334 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
335 if (Imm->getAPIntValue().isSignedIntN(8))
338 // If the other operand is a TLS address, we should fold it instead.
341 // leal i@NTPOFF(%eax), %eax
343 // movl $i@NTPOFF, %eax
345 // if the block also has an access to a second TLS address this will save
347 // FIXME: This is probably also true for non-TLS addresses.
348 if (Op1.getOpcode() == X86ISD::Wrapper) {
349 SDValue Val = Op1.getOperand(0);
350 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
360 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
361 /// load's chain operand and move load below the call's chain operand.
362 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
363 SDValue Call, SDValue OrigChain) {
364 SmallVector<SDValue, 8> Ops;
365 SDValue Chain = OrigChain.getOperand(0);
366 if (Chain.getNode() == Load.getNode())
367 Ops.push_back(Load.getOperand(0));
369 assert(Chain.getOpcode() == ISD::TokenFactor &&
370 "Unexpected chain operand");
371 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
372 if (Chain.getOperand(i).getNode() == Load.getNode())
373 Ops.push_back(Load.getOperand(0));
375 Ops.push_back(Chain.getOperand(i));
377 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load),
378 MVT::Other, &Ops[0], Ops.size());
380 Ops.push_back(NewChain);
382 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
383 Ops.push_back(OrigChain.getOperand(i));
384 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
385 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
386 Load.getOperand(1), Load.getOperand(2));
388 unsigned NumOps = Call.getNode()->getNumOperands();
390 Ops.push_back(SDValue(Load.getNode(), 1));
391 for (unsigned i = 1, e = NumOps; i != e; ++i)
392 Ops.push_back(Call.getOperand(i));
393 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], NumOps);
396 /// isCalleeLoad - Return true if call address is a load and it can be
397 /// moved below CALLSEQ_START and the chains leading up to the call.
398 /// Return the CALLSEQ_START by reference as a second output.
399 /// In the case of a tail call, there isn't a callseq node between the call
400 /// chain and the load.
401 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
402 // The transformation is somewhat dangerous if the call's chain was glued to
403 // the call. After MoveBelowOrigChain the load is moved between the call and
404 // the chain, this can create a cycle if the load is not folded. So it is
405 // *really* important that we are sure the load will be folded.
406 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
408 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
411 LD->getAddressingMode() != ISD::UNINDEXED ||
412 LD->getExtensionType() != ISD::NON_EXTLOAD)
415 // Now let's find the callseq_start.
416 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
417 if (!Chain.hasOneUse())
419 Chain = Chain.getOperand(0);
422 if (!Chain.getNumOperands())
424 // Since we are not checking for AA here, conservatively abort if the chain
425 // writes to memory. It's not safe to move the callee (a load) across a store.
426 if (isa<MemSDNode>(Chain.getNode()) &&
427 cast<MemSDNode>(Chain.getNode())->writeMem())
429 if (Chain.getOperand(0).getNode() == Callee.getNode())
431 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
432 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
433 Callee.getValue(1).hasOneUse())
438 void X86DAGToDAGISel::PreprocessISelDAG() {
439 // OptForSize is used in pattern predicates that isel is matching.
440 OptForSize = MF->getFunction()->getAttributes().
441 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
443 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
444 E = CurDAG->allnodes_end(); I != E; ) {
445 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
447 if (OptLevel != CodeGenOpt::None &&
448 // Only does this when target favors doesn't favor register indirect
450 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
451 (N->getOpcode() == X86ISD::TC_RETURN &&
452 // Only does this if load can be folded into TC_RETURN.
453 (Subtarget->is64Bit() ||
454 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
455 /// Also try moving call address load from outside callseq_start to just
456 /// before the call to allow it to be folded.
474 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
475 SDValue Chain = N->getOperand(0);
476 SDValue Load = N->getOperand(1);
477 if (!isCalleeLoad(Load, Chain, HasCallSeq))
479 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
484 // Lower fpround and fpextend nodes that target the FP stack to be store and
485 // load to the stack. This is a gross hack. We would like to simply mark
486 // these as being illegal, but when we do that, legalize produces these when
487 // it expands calls, then expands these in the same legalize pass. We would
488 // like dag combine to be able to hack on these between the call expansion
489 // and the node legalization. As such this pass basically does "really
490 // late" legalization of these inline with the X86 isel pass.
491 // FIXME: This should only happen when not compiled with -O0.
492 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
495 MVT SrcVT = N->getOperand(0).getSimpleValueType();
496 MVT DstVT = N->getSimpleValueType(0);
498 // If any of the sources are vectors, no fp stack involved.
499 if (SrcVT.isVector() || DstVT.isVector())
502 // If the source and destination are SSE registers, then this is a legal
503 // conversion that should not be lowered.
504 const X86TargetLowering *X86Lowering =
505 static_cast<const X86TargetLowering *>(getTargetLowering());
506 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
507 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
508 if (SrcIsSSE && DstIsSSE)
511 if (!SrcIsSSE && !DstIsSSE) {
512 // If this is an FPStack extension, it is a noop.
513 if (N->getOpcode() == ISD::FP_EXTEND)
515 // If this is a value-preserving FPStack truncation, it is a noop.
516 if (N->getConstantOperandVal(1))
520 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
521 // FPStack has extload and truncstore. SSE can fold direct loads into other
522 // operations. Based on this, decide what we want to do.
524 if (N->getOpcode() == ISD::FP_ROUND)
525 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
527 MemVT = SrcIsSSE ? SrcVT : DstVT;
529 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
532 // FIXME: optimize the case where the src/dest is a load or store?
533 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
535 MemTmp, MachinePointerInfo(), MemVT,
537 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
538 MachinePointerInfo(),
539 MemVT, false, false, 0);
541 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
542 // extload we created. This will cause general havok on the dag because
543 // anything below the conversion could be folded into other existing nodes.
544 // To avoid invalidating 'I', back it up to the convert node.
546 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
548 // Now that we did that, the node is dead. Increment the iterator to the
549 // next node to process, then delete N.
551 CurDAG->DeleteNode(N);
556 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
557 /// the main function.
558 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
559 MachineFrameInfo *MFI) {
560 const TargetInstrInfo *TII = TM.getInstrInfo();
561 if (Subtarget->isTargetCygMing()) {
563 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
564 BuildMI(BB, DebugLoc(),
565 TII->get(CallOp)).addExternalSymbol("__main");
569 void X86DAGToDAGISel::EmitFunctionEntryCode() {
570 // If this is main, emit special code for main.
571 if (const Function *Fn = MF->getFunction())
572 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
573 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
576 static bool isDispSafeForFrameIndex(int64_t Val) {
577 // On 64-bit platforms, we can run into an issue where a frame index
578 // includes a displacement that, when added to the explicit displacement,
579 // will overflow the displacement field. Assuming that the frame index
580 // displacement fits into a 31-bit integer (which is only slightly more
581 // aggressive than the current fundamental assumption that it fits into
582 // a 32-bit integer), a 31-bit disp should always be safe.
583 return isInt<31>(Val);
586 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
587 X86ISelAddressMode &AM) {
588 int64_t Val = AM.Disp + Offset;
589 CodeModel::Model M = TM.getCodeModel();
590 if (Subtarget->is64Bit()) {
591 if (!X86::isOffsetSuitableForCodeModel(Val, M,
592 AM.hasSymbolicDisplacement()))
594 // In addition to the checks required for a register base, check that
595 // we do not try to use an unsafe Disp with a frame index.
596 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
597 !isDispSafeForFrameIndex(Val))
605 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
606 SDValue Address = N->getOperand(1);
608 // load gs:0 -> GS segment register.
609 // load fs:0 -> FS segment register.
611 // This optimization is valid because the GNU TLS model defines that
612 // gs:0 (or fs:0 on X86-64) contains its own address.
613 // For more information see http://people.redhat.com/drepper/tls.pdf
614 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
615 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
616 Subtarget->isTargetLinux())
617 switch (N->getPointerInfo().getAddrSpace()) {
619 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
622 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
629 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
630 /// into an addressing mode. These wrap things that will resolve down into a
631 /// symbol reference. If no match is possible, this returns true, otherwise it
633 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
634 // If the addressing mode already has a symbol as the displacement, we can
635 // never match another symbol.
636 if (AM.hasSymbolicDisplacement())
639 SDValue N0 = N.getOperand(0);
640 CodeModel::Model M = TM.getCodeModel();
642 // Handle X86-64 rip-relative addresses. We check this before checking direct
643 // folding because RIP is preferable to non-RIP accesses.
644 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
645 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
646 // they cannot be folded into immediate fields.
647 // FIXME: This can be improved for kernel and other models?
648 (M == CodeModel::Small || M == CodeModel::Kernel)) {
649 // Base and index reg must be 0 in order to use %rip as base.
650 if (AM.hasBaseOrIndexReg())
652 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
653 X86ISelAddressMode Backup = AM;
654 AM.GV = G->getGlobal();
655 AM.SymbolFlags = G->getTargetFlags();
656 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
660 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
661 X86ISelAddressMode Backup = AM;
662 AM.CP = CP->getConstVal();
663 AM.Align = CP->getAlignment();
664 AM.SymbolFlags = CP->getTargetFlags();
665 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
669 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
670 AM.ES = S->getSymbol();
671 AM.SymbolFlags = S->getTargetFlags();
672 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
673 AM.JT = J->getIndex();
674 AM.SymbolFlags = J->getTargetFlags();
675 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
676 X86ISelAddressMode Backup = AM;
677 AM.BlockAddr = BA->getBlockAddress();
678 AM.SymbolFlags = BA->getTargetFlags();
679 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
684 llvm_unreachable("Unhandled symbol reference node.");
686 if (N.getOpcode() == X86ISD::WrapperRIP)
687 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
691 // Handle the case when globals fit in our immediate field: This is true for
692 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
693 // mode, this only applies to a non-RIP-relative computation.
694 if (!Subtarget->is64Bit() ||
695 M == CodeModel::Small || M == CodeModel::Kernel) {
696 assert(N.getOpcode() != X86ISD::WrapperRIP &&
697 "RIP-relative addressing already handled");
698 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
699 AM.GV = G->getGlobal();
700 AM.Disp += G->getOffset();
701 AM.SymbolFlags = G->getTargetFlags();
702 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
703 AM.CP = CP->getConstVal();
704 AM.Align = CP->getAlignment();
705 AM.Disp += CP->getOffset();
706 AM.SymbolFlags = CP->getTargetFlags();
707 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
708 AM.ES = S->getSymbol();
709 AM.SymbolFlags = S->getTargetFlags();
710 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
711 AM.JT = J->getIndex();
712 AM.SymbolFlags = J->getTargetFlags();
713 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
714 AM.BlockAddr = BA->getBlockAddress();
715 AM.Disp += BA->getOffset();
716 AM.SymbolFlags = BA->getTargetFlags();
718 llvm_unreachable("Unhandled symbol reference node.");
725 /// MatchAddress - Add the specified node to the specified addressing mode,
726 /// returning true if it cannot be done. This just pattern matches for the
728 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
729 if (MatchAddressRecursively(N, AM, 0))
732 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
733 // a smaller encoding and avoids a scaled-index.
735 AM.BaseType == X86ISelAddressMode::RegBase &&
736 AM.Base_Reg.getNode() == 0) {
737 AM.Base_Reg = AM.IndexReg;
741 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
742 // because it has a smaller encoding.
743 // TODO: Which other code models can use this?
744 if (TM.getCodeModel() == CodeModel::Small &&
745 Subtarget->is64Bit() &&
747 AM.BaseType == X86ISelAddressMode::RegBase &&
748 AM.Base_Reg.getNode() == 0 &&
749 AM.IndexReg.getNode() == 0 &&
750 AM.SymbolFlags == X86II::MO_NO_FLAG &&
751 AM.hasSymbolicDisplacement())
752 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
757 // Insert a node into the DAG at least before the Pos node's position. This
758 // will reposition the node as needed, and will assign it a node ID that is <=
759 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
760 // IDs! The selection DAG must no longer depend on their uniqueness when this
762 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
763 if (N.getNode()->getNodeId() == -1 ||
764 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
765 DAG.RepositionNode(Pos.getNode(), N.getNode());
766 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
770 // Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
771 // allows us to convert the shift and and into an h-register extract and
772 // a scaled index. Returns false if the simplification is performed.
773 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
775 SDValue Shift, SDValue X,
776 X86ISelAddressMode &AM) {
777 if (Shift.getOpcode() != ISD::SRL ||
778 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
782 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
783 if (ScaleLog <= 0 || ScaleLog >= 4 ||
784 Mask != (0xffu << ScaleLog))
787 MVT VT = N.getSimpleValueType();
789 SDValue Eight = DAG.getConstant(8, MVT::i8);
790 SDValue NewMask = DAG.getConstant(0xff, VT);
791 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
792 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
793 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
794 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
796 // Insert the new nodes into the topological ordering. We must do this in
797 // a valid topological ordering as nothing is going to go back and re-sort
798 // these nodes. We continually insert before 'N' in sequence as this is
799 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
800 // hierarchy left to express.
801 InsertDAGNode(DAG, N, Eight);
802 InsertDAGNode(DAG, N, Srl);
803 InsertDAGNode(DAG, N, NewMask);
804 InsertDAGNode(DAG, N, And);
805 InsertDAGNode(DAG, N, ShlCount);
806 InsertDAGNode(DAG, N, Shl);
807 DAG.ReplaceAllUsesWith(N, Shl);
809 AM.Scale = (1 << ScaleLog);
813 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
814 // allows us to fold the shift into this addressing mode. Returns false if the
815 // transform succeeded.
816 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
818 SDValue Shift, SDValue X,
819 X86ISelAddressMode &AM) {
820 if (Shift.getOpcode() != ISD::SHL ||
821 !isa<ConstantSDNode>(Shift.getOperand(1)))
824 // Not likely to be profitable if either the AND or SHIFT node has more
825 // than one use (unless all uses are for address computation). Besides,
826 // isel mechanism requires their node ids to be reused.
827 if (!N.hasOneUse() || !Shift.hasOneUse())
830 // Verify that the shift amount is something we can fold.
831 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
832 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
835 MVT VT = N.getSimpleValueType();
837 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
838 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
839 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
841 // Insert the new nodes into the topological ordering. We must do this in
842 // a valid topological ordering as nothing is going to go back and re-sort
843 // these nodes. We continually insert before 'N' in sequence as this is
844 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
845 // hierarchy left to express.
846 InsertDAGNode(DAG, N, NewMask);
847 InsertDAGNode(DAG, N, NewAnd);
848 InsertDAGNode(DAG, N, NewShift);
849 DAG.ReplaceAllUsesWith(N, NewShift);
851 AM.Scale = 1 << ShiftAmt;
852 AM.IndexReg = NewAnd;
856 // Implement some heroics to detect shifts of masked values where the mask can
857 // be replaced by extending the shift and undoing that in the addressing mode
858 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
859 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
860 // the addressing mode. This results in code such as:
862 // int f(short *y, int *lookup_table) {
864 // return *y + lookup_table[*y >> 11];
868 // movzwl (%rdi), %eax
871 // addl (%rsi,%rcx,4), %eax
874 // movzwl (%rdi), %eax
878 // addl (%rsi,%rcx), %eax
880 // Note that this function assumes the mask is provided as a mask *after* the
881 // value is shifted. The input chain may or may not match that, but computing
882 // such a mask is trivial.
883 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
885 SDValue Shift, SDValue X,
886 X86ISelAddressMode &AM) {
887 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
888 !isa<ConstantSDNode>(Shift.getOperand(1)))
891 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
892 unsigned MaskLZ = countLeadingZeros(Mask);
893 unsigned MaskTZ = countTrailingZeros(Mask);
895 // The amount of shift we're trying to fit into the addressing mode is taken
896 // from the trailing zeros of the mask.
897 unsigned AMShiftAmt = MaskTZ;
899 // There is nothing we can do here unless the mask is removing some bits.
900 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
901 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
903 // We also need to ensure that mask is a continuous run of bits.
904 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
906 // Scale the leading zero count down based on the actual size of the value.
907 // Also scale it down based on the size of the shift.
908 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
910 // The final check is to ensure that any masked out high bits of X are
911 // already known to be zero. Otherwise, the mask has a semantic impact
912 // other than masking out a couple of low bits. Unfortunately, because of
913 // the mask, zero extensions will be removed from operands in some cases.
914 // This code works extra hard to look through extensions because we can
915 // replace them with zero extensions cheaply if necessary.
916 bool ReplacingAnyExtend = false;
917 if (X.getOpcode() == ISD::ANY_EXTEND) {
918 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
919 X.getOperand(0).getSimpleValueType().getSizeInBits();
920 // Assume that we'll replace the any-extend with a zero-extend, and
921 // narrow the search to the extended value.
923 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
924 ReplacingAnyExtend = true;
926 APInt MaskedHighBits =
927 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
928 APInt KnownZero, KnownOne;
929 DAG.ComputeMaskedBits(X, KnownZero, KnownOne);
930 if (MaskedHighBits != KnownZero) return true;
932 // We've identified a pattern that can be transformed into a single shift
933 // and an addressing mode. Make it so.
934 MVT VT = N.getSimpleValueType();
935 if (ReplacingAnyExtend) {
936 assert(X.getValueType() != VT);
937 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
938 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
939 InsertDAGNode(DAG, N, NewX);
943 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
944 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
945 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
946 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
948 // Insert the new nodes into the topological ordering. We must do this in
949 // a valid topological ordering as nothing is going to go back and re-sort
950 // these nodes. We continually insert before 'N' in sequence as this is
951 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
952 // hierarchy left to express.
953 InsertDAGNode(DAG, N, NewSRLAmt);
954 InsertDAGNode(DAG, N, NewSRL);
955 InsertDAGNode(DAG, N, NewSHLAmt);
956 InsertDAGNode(DAG, N, NewSHL);
957 DAG.ReplaceAllUsesWith(N, NewSHL);
959 AM.Scale = 1 << AMShiftAmt;
960 AM.IndexReg = NewSRL;
964 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
968 dbgs() << "MatchAddress: ";
973 return MatchAddressBase(N, AM);
975 // If this is already a %rip relative address, we can only merge immediates
976 // into it. Instead of handling this in every case, we handle it here.
977 // RIP relative addressing: %rip + 32-bit displacement!
978 if (AM.isRIPRelative()) {
979 // FIXME: JumpTable and ExternalSymbol address currently don't like
980 // displacements. It isn't very important, but this should be fixed for
982 if (!AM.ES && AM.JT != -1) return true;
984 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
985 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
990 switch (N.getOpcode()) {
992 case ISD::Constant: {
993 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
994 if (!FoldOffsetIntoAddress(Val, AM))
999 case X86ISD::Wrapper:
1000 case X86ISD::WrapperRIP:
1001 if (!MatchWrapper(N, AM))
1006 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1010 case ISD::FrameIndex:
1011 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1012 AM.Base_Reg.getNode() == 0 &&
1013 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1014 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1015 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1021 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
1025 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1026 unsigned Val = CN->getZExtValue();
1027 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1028 // that the base operand remains free for further matching. If
1029 // the base doesn't end up getting used, a post-processing step
1030 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1031 if (Val == 1 || Val == 2 || Val == 3) {
1032 AM.Scale = 1 << Val;
1033 SDValue ShVal = N.getNode()->getOperand(0);
1035 // Okay, we know that we have a scale by now. However, if the scaled
1036 // value is an add of something and a constant, we can fold the
1037 // constant into the disp field here.
1038 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1039 AM.IndexReg = ShVal.getNode()->getOperand(0);
1040 ConstantSDNode *AddVal =
1041 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1042 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1043 if (!FoldOffsetIntoAddress(Disp, AM))
1047 AM.IndexReg = ShVal;
1054 // Scale must not be used already.
1055 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1057 SDValue And = N.getOperand(0);
1058 if (And.getOpcode() != ISD::AND) break;
1059 SDValue X = And.getOperand(0);
1061 // We only handle up to 64-bit values here as those are what matter for
1062 // addressing mode optimizations.
1063 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1065 // The mask used for the transform is expected to be post-shift, but we
1066 // found the shift first so just apply the shift to the mask before passing
1068 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1069 !isa<ConstantSDNode>(And.getOperand(1)))
1071 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1073 // Try to fold the mask and shift into the scale, and return false if we
1075 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1080 case ISD::SMUL_LOHI:
1081 case ISD::UMUL_LOHI:
1082 // A mul_lohi where we need the low part can be folded as a plain multiply.
1083 if (N.getResNo() != 0) break;
1086 case X86ISD::MUL_IMM:
1087 // X*[3,5,9] -> X+X*[2,4,8]
1088 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1089 AM.Base_Reg.getNode() == 0 &&
1090 AM.IndexReg.getNode() == 0) {
1092 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1093 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1094 CN->getZExtValue() == 9) {
1095 AM.Scale = unsigned(CN->getZExtValue())-1;
1097 SDValue MulVal = N.getNode()->getOperand(0);
1100 // Okay, we know that we have a scale by now. However, if the scaled
1101 // value is an add of something and a constant, we can fold the
1102 // constant into the disp field here.
1103 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1104 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1105 Reg = MulVal.getNode()->getOperand(0);
1106 ConstantSDNode *AddVal =
1107 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1108 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1109 if (FoldOffsetIntoAddress(Disp, AM))
1110 Reg = N.getNode()->getOperand(0);
1112 Reg = N.getNode()->getOperand(0);
1115 AM.IndexReg = AM.Base_Reg = Reg;
1122 // Given A-B, if A can be completely folded into the address and
1123 // the index field with the index field unused, use -B as the index.
1124 // This is a win if a has multiple parts that can be folded into
1125 // the address. Also, this saves a mov if the base register has
1126 // other uses, since it avoids a two-address sub instruction, however
1127 // it costs an additional mov if the index register has other uses.
1129 // Add an artificial use to this node so that we can keep track of
1130 // it if it gets CSE'd with a different node.
1131 HandleSDNode Handle(N);
1133 // Test if the LHS of the sub can be folded.
1134 X86ISelAddressMode Backup = AM;
1135 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1139 // Test if the index field is free for use.
1140 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1146 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1147 // If the RHS involves a register with multiple uses, this
1148 // transformation incurs an extra mov, due to the neg instruction
1149 // clobbering its operand.
1150 if (!RHS.getNode()->hasOneUse() ||
1151 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1152 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1153 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1154 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1155 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1157 // If the base is a register with multiple uses, this
1158 // transformation may save a mov.
1159 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1160 AM.Base_Reg.getNode() &&
1161 !AM.Base_Reg.getNode()->hasOneUse()) ||
1162 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1164 // If the folded LHS was interesting, this transformation saves
1165 // address arithmetic.
1166 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1167 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1168 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1170 // If it doesn't look like it may be an overall win, don't do it.
1176 // Ok, the transformation is legal and appears profitable. Go for it.
1177 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1178 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1182 // Insert the new nodes into the topological ordering.
1183 InsertDAGNode(*CurDAG, N, Zero);
1184 InsertDAGNode(*CurDAG, N, Neg);
1189 // Add an artificial use to this node so that we can keep track of
1190 // it if it gets CSE'd with a different node.
1191 HandleSDNode Handle(N);
1193 X86ISelAddressMode Backup = AM;
1194 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1195 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1199 // Try again after commuting the operands.
1200 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1201 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1205 // If we couldn't fold both operands into the address at the same time,
1206 // see if we can just put each operand into a register and fold at least
1208 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1209 !AM.Base_Reg.getNode() &&
1210 !AM.IndexReg.getNode()) {
1211 N = Handle.getValue();
1212 AM.Base_Reg = N.getOperand(0);
1213 AM.IndexReg = N.getOperand(1);
1217 N = Handle.getValue();
1222 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1223 if (CurDAG->isBaseWithConstantOffset(N)) {
1224 X86ISelAddressMode Backup = AM;
1225 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1227 // Start with the LHS as an addr mode.
1228 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1229 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1236 // Perform some heroic transforms on an and of a constant-count shift
1237 // with a constant to enable use of the scaled offset field.
1239 // Scale must not be used already.
1240 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1242 SDValue Shift = N.getOperand(0);
1243 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1244 SDValue X = Shift.getOperand(0);
1246 // We only handle up to 64-bit values here as those are what matter for
1247 // addressing mode optimizations.
1248 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1250 if (!isa<ConstantSDNode>(N.getOperand(1)))
1252 uint64_t Mask = N.getConstantOperandVal(1);
1254 // Try to fold the mask and shift into an extract and scale.
1255 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1258 // Try to fold the mask and shift directly into the scale.
1259 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1262 // Try to swap the mask and shift to place shifts which can be done as
1263 // a scale on the outside of the mask.
1264 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1270 return MatchAddressBase(N, AM);
1273 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1274 /// specified addressing mode without any further recursion.
1275 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1276 // Is the base register already occupied?
1277 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1278 // If so, check to see if the scale index register is set.
1279 if (AM.IndexReg.getNode() == 0) {
1285 // Otherwise, we cannot select it.
1289 // Default, generate it as a register.
1290 AM.BaseType = X86ISelAddressMode::RegBase;
1295 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1296 /// It returns the operands which make up the maximal addressing mode it can
1297 /// match by reference.
1299 /// Parent is the parent node of the addr operand that is being matched. It
1300 /// is always a load, store, atomic node, or null. It is only null when
1301 /// checking memory operands for inline asm nodes.
1302 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1303 SDValue &Scale, SDValue &Index,
1304 SDValue &Disp, SDValue &Segment) {
1305 X86ISelAddressMode AM;
1308 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1309 // that are not a MemSDNode, and thus don't have proper addrspace info.
1310 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1311 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1312 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1313 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1314 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1315 unsigned AddrSpace =
1316 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1317 // AddrSpace 256 -> GS, 257 -> FS.
1318 if (AddrSpace == 256)
1319 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1320 if (AddrSpace == 257)
1321 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1324 if (MatchAddress(N, AM))
1327 MVT VT = N.getSimpleValueType();
1328 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1329 if (!AM.Base_Reg.getNode())
1330 AM.Base_Reg = CurDAG->getRegister(0, VT);
1333 if (!AM.IndexReg.getNode())
1334 AM.IndexReg = CurDAG->getRegister(0, VT);
1336 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1340 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1341 /// match a load whose top elements are either undef or zeros. The load flavor
1342 /// is derived from the type of N, which is either v4f32 or v2f64.
1345 /// PatternChainNode: this is the matched node that has a chain input and
1347 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1348 SDValue N, SDValue &Base,
1349 SDValue &Scale, SDValue &Index,
1350 SDValue &Disp, SDValue &Segment,
1351 SDValue &PatternNodeWithChain) {
1352 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1353 PatternNodeWithChain = N.getOperand(0);
1354 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1355 PatternNodeWithChain.hasOneUse() &&
1356 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1357 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1358 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1359 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1365 // Also handle the case where we explicitly require zeros in the top
1366 // elements. This is a vector shuffle from the zero vector.
1367 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1368 // Check to see if the top elements are all zeros (or bitcast of zeros).
1369 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1370 N.getOperand(0).getNode()->hasOneUse() &&
1371 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1372 N.getOperand(0).getOperand(0).hasOneUse() &&
1373 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1374 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1375 // Okay, this is a zero extending load. Fold it.
1376 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1377 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1379 PatternNodeWithChain = SDValue(LD, 0);
1386 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1387 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1388 uint64_t ImmVal = CN->getZExtValue();
1389 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1392 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
1396 // In static codegen with small code model, we can get the address of a label
1397 // into a register with 'movl'. TableGen has already made sure we're looking
1398 // at a label of some kind.
1399 assert(N->getOpcode() == X86ISD::Wrapper &&
1400 "Unexpected node type for MOV32ri64");
1401 N = N.getOperand(0);
1403 if (N->getOpcode() != ISD::TargetConstantPool &&
1404 N->getOpcode() != ISD::TargetJumpTable &&
1405 N->getOpcode() != ISD::TargetGlobalAddress &&
1406 N->getOpcode() != ISD::TargetExternalSymbol &&
1407 N->getOpcode() != ISD::TargetBlockAddress)
1411 return TM.getCodeModel() == CodeModel::Small;
1414 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1415 SDValue &Scale, SDValue &Index,
1416 SDValue &Disp, SDValue &Segment) {
1417 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1421 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1422 if (RN && RN->getReg() == 0)
1423 Base = CurDAG->getRegister(0, MVT::i64);
1424 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(N)) {
1425 // Base could already be %rip, particularly in the x32 ABI.
1426 Base = SDValue(CurDAG->getMachineNode(
1427 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1428 CurDAG->getTargetConstant(0, MVT::i64),
1430 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1434 RN = dyn_cast<RegisterSDNode>(Index);
1435 if (RN && RN->getReg() == 0)
1436 Index = CurDAG->getRegister(0, MVT::i64);
1438 assert(Index.getValueType() == MVT::i32 &&
1439 "Expect to be extending 32-bit registers for use in LEA");
1440 Index = SDValue(CurDAG->getMachineNode(
1441 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1442 CurDAG->getTargetConstant(0, MVT::i64),
1444 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1451 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1452 /// mode it matches can be cost effectively emitted as an LEA instruction.
1453 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1454 SDValue &Base, SDValue &Scale,
1455 SDValue &Index, SDValue &Disp,
1457 X86ISelAddressMode AM;
1459 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1461 SDValue Copy = AM.Segment;
1462 SDValue T = CurDAG->getRegister(0, MVT::i32);
1464 if (MatchAddress(N, AM))
1466 assert (T == AM.Segment);
1469 MVT VT = N.getSimpleValueType();
1470 unsigned Complexity = 0;
1471 if (AM.BaseType == X86ISelAddressMode::RegBase)
1472 if (AM.Base_Reg.getNode())
1475 AM.Base_Reg = CurDAG->getRegister(0, VT);
1476 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1479 if (AM.IndexReg.getNode())
1482 AM.IndexReg = CurDAG->getRegister(0, VT);
1484 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1489 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1490 // to a LEA. This is determined with some expermentation but is by no means
1491 // optimal (especially for code size consideration). LEA is nice because of
1492 // its three-address nature. Tweak the cost function again when we can run
1493 // convertToThreeAddress() at register allocation time.
1494 if (AM.hasSymbolicDisplacement()) {
1495 // For X86-64, we should always use lea to materialize RIP relative
1497 if (Subtarget->is64Bit())
1503 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1506 // If it isn't worth using an LEA, reject it.
1507 if (Complexity <= 2)
1510 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1514 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1515 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1516 SDValue &Scale, SDValue &Index,
1517 SDValue &Disp, SDValue &Segment) {
1518 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1519 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1521 X86ISelAddressMode AM;
1522 AM.GV = GA->getGlobal();
1523 AM.Disp += GA->getOffset();
1524 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1525 AM.SymbolFlags = GA->getTargetFlags();
1527 if (N.getValueType() == MVT::i32) {
1529 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1531 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1534 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1539 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1540 SDValue &Base, SDValue &Scale,
1541 SDValue &Index, SDValue &Disp,
1543 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1544 !IsProfitableToFold(N, P, P) ||
1545 !IsLegalToFold(N, P, P, OptLevel))
1548 return SelectAddr(N.getNode(),
1549 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1552 /// getGlobalBaseReg - Return an SDNode that returns the value of
1553 /// the global base register. Output instructions required to
1554 /// initialize the global base register, if necessary.
1556 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1557 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1558 return CurDAG->getRegister(GlobalBaseReg,
1559 getTargetLowering()->getPointerTy()).getNode();
1562 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1563 SDValue Chain = Node->getOperand(0);
1564 SDValue In1 = Node->getOperand(1);
1565 SDValue In2L = Node->getOperand(2);
1566 SDValue In2H = Node->getOperand(3);
1568 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1569 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1571 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1572 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1573 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1574 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node),
1575 MVT::i32, MVT::i32, MVT::Other, Ops);
1576 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1580 /// Atomic opcode table
1608 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1619 X86::LOCK_ADD64mi32,
1632 X86::LOCK_SUB64mi32,
1684 X86::LOCK_AND64mi32,
1697 X86::LOCK_XOR64mi32,
1702 // Return the target constant operand for atomic-load-op and do simple
1703 // translations, such as from atomic-load-add to lock-sub. The return value is
1704 // one of the following 3 cases:
1705 // + target-constant, the operand could be supported as a target constant.
1706 // + empty, the operand is not needed any more with the new op selected.
1707 // + non-empty, otherwise.
1708 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1710 enum AtomicOpc &Op, MVT NVT,
1712 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1713 int64_t CNVal = CN->getSExtValue();
1714 // Quit if not 32-bit imm.
1715 if ((int32_t)CNVal != CNVal)
1717 // For atomic-load-add, we could do some optimizations.
1719 // Translate to INC/DEC if ADD by 1 or -1.
1720 if ((CNVal == 1) || (CNVal == -1)) {
1721 Op = (CNVal == 1) ? INC : DEC;
1722 // No more constant operand after being translated into INC/DEC.
1725 // Translate to SUB if ADD by negative value.
1731 return CurDAG->getTargetConstant(CNVal, NVT);
1734 // If the value operand is single-used, try to optimize it.
1735 if (Op == ADD && Val.hasOneUse()) {
1736 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1737 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1739 return Val.getOperand(1);
1741 // A special case for i16, which needs truncating as, in most cases, it's
1742 // promoted to i32. We will translate
1743 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1744 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1745 Val.getOperand(0).getOpcode() == ISD::SUB &&
1746 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1748 Val = Val.getOperand(0);
1749 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1757 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1758 if (Node->hasAnyUseOfValue(0))
1763 // Optimize common patterns for __sync_or_and_fetch and similar arith
1764 // operations where the result is not used. This allows us to use the "lock"
1765 // version of the arithmetic instruction.
1766 SDValue Chain = Node->getOperand(0);
1767 SDValue Ptr = Node->getOperand(1);
1768 SDValue Val = Node->getOperand(2);
1769 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1770 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1773 // Which index into the table.
1775 switch (Node->getOpcode()) {
1778 case ISD::ATOMIC_LOAD_OR:
1781 case ISD::ATOMIC_LOAD_AND:
1784 case ISD::ATOMIC_LOAD_XOR:
1787 case ISD::ATOMIC_LOAD_ADD:
1792 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val);
1793 bool isUnOp = !Val.getNode();
1794 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1797 switch (NVT.SimpleTy) {
1801 Opc = AtomicOpcTbl[Op][ConstantI8];
1803 Opc = AtomicOpcTbl[Op][I8];
1807 if (immSext8(Val.getNode()))
1808 Opc = AtomicOpcTbl[Op][SextConstantI16];
1810 Opc = AtomicOpcTbl[Op][ConstantI16];
1812 Opc = AtomicOpcTbl[Op][I16];
1816 if (immSext8(Val.getNode()))
1817 Opc = AtomicOpcTbl[Op][SextConstantI32];
1819 Opc = AtomicOpcTbl[Op][ConstantI32];
1821 Opc = AtomicOpcTbl[Op][I32];
1824 Opc = AtomicOpcTbl[Op][I64];
1826 if (immSext8(Val.getNode()))
1827 Opc = AtomicOpcTbl[Op][SextConstantI64];
1828 else if (i64immSExt32(Val.getNode()))
1829 Opc = AtomicOpcTbl[Op][ConstantI64];
1834 assert(Opc != 0 && "Invalid arith lock transform!");
1837 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1839 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1840 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1842 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1843 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1845 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1846 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1848 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1849 SDValue RetVals[] = { Undef, Ret };
1850 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1853 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1854 /// any uses which require the SF or OF bits to be accurate.
1855 static bool HasNoSignedComparisonUses(SDNode *N) {
1856 // Examine each user of the node.
1857 for (SDNode::use_iterator UI = N->use_begin(),
1858 UE = N->use_end(); UI != UE; ++UI) {
1859 // Only examine CopyToReg uses.
1860 if (UI->getOpcode() != ISD::CopyToReg)
1862 // Only examine CopyToReg uses that copy to EFLAGS.
1863 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1866 // Examine each user of the CopyToReg use.
1867 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1868 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1869 // Only examine the Flag result.
1870 if (FlagUI.getUse().getResNo() != 1) continue;
1871 // Anything unusual: assume conservatively.
1872 if (!FlagUI->isMachineOpcode()) return false;
1873 // Examine the opcode of the user.
1874 switch (FlagUI->getMachineOpcode()) {
1875 // These comparisons don't treat the most significant bit specially.
1876 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1877 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1878 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1879 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1880 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1881 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1882 case X86::CMOVA16rr: case X86::CMOVA16rm:
1883 case X86::CMOVA32rr: case X86::CMOVA32rm:
1884 case X86::CMOVA64rr: case X86::CMOVA64rm:
1885 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1886 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1887 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1888 case X86::CMOVB16rr: case X86::CMOVB16rm:
1889 case X86::CMOVB32rr: case X86::CMOVB32rm:
1890 case X86::CMOVB64rr: case X86::CMOVB64rm:
1891 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1892 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1893 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1894 case X86::CMOVE16rr: case X86::CMOVE16rm:
1895 case X86::CMOVE32rr: case X86::CMOVE32rm:
1896 case X86::CMOVE64rr: case X86::CMOVE64rm:
1897 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1898 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1899 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1900 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1901 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1902 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1903 case X86::CMOVP16rr: case X86::CMOVP16rm:
1904 case X86::CMOVP32rr: case X86::CMOVP32rm:
1905 case X86::CMOVP64rr: case X86::CMOVP64rm:
1907 // Anything else: assume conservatively.
1908 default: return false;
1915 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1916 /// is suitable for doing the {load; increment or decrement; store} to modify
1918 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1919 SDValue StoredVal, SelectionDAG *CurDAG,
1920 LoadSDNode* &LoadNode, SDValue &InputChain) {
1922 // is the value stored the result of a DEC or INC?
1923 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1925 // is the stored value result 0 of the load?
1926 if (StoredVal.getResNo() != 0) return false;
1928 // are there other uses of the loaded value than the inc or dec?
1929 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1931 // is the store non-extending and non-indexed?
1932 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1935 SDValue Load = StoredVal->getOperand(0);
1936 // Is the stored value a non-extending and non-indexed load?
1937 if (!ISD::isNormalLoad(Load.getNode())) return false;
1939 // Return LoadNode by reference.
1940 LoadNode = cast<LoadSDNode>(Load);
1941 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1942 EVT LdVT = LoadNode->getMemoryVT();
1943 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1947 // Is store the only read of the loaded value?
1948 if (!Load.hasOneUse())
1951 // Is the address of the store the same as the load?
1952 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1953 LoadNode->getOffset() != StoreNode->getOffset())
1956 // Check if the chain is produced by the load or is a TokenFactor with
1957 // the load output chain as an operand. Return InputChain by reference.
1958 SDValue Chain = StoreNode->getChain();
1960 bool ChainCheck = false;
1961 if (Chain == Load.getValue(1)) {
1963 InputChain = LoadNode->getChain();
1964 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1965 SmallVector<SDValue, 4> ChainOps;
1966 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1967 SDValue Op = Chain.getOperand(i);
1968 if (Op == Load.getValue(1)) {
1973 // Make sure using Op as part of the chain would not cause a cycle here.
1974 // In theory, we could check whether the chain node is a predecessor of
1975 // the load. But that can be very expensive. Instead visit the uses and
1976 // make sure they all have smaller node id than the load.
1977 int LoadId = LoadNode->getNodeId();
1978 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1979 UE = UI->use_end(); UI != UE; ++UI) {
1980 if (UI.getUse().getResNo() != 0)
1982 if (UI->getNodeId() > LoadId)
1986 ChainOps.push_back(Op);
1990 // Make a new TokenFactor with all the other input chains except
1992 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
1993 MVT::Other, &ChainOps[0], ChainOps.size());
2001 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2002 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2003 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2004 if (Opc == X86ISD::DEC) {
2005 if (LdVT == MVT::i64) return X86::DEC64m;
2006 if (LdVT == MVT::i32) return X86::DEC32m;
2007 if (LdVT == MVT::i16) return X86::DEC16m;
2008 if (LdVT == MVT::i8) return X86::DEC8m;
2010 assert(Opc == X86ISD::INC && "unrecognized opcode");
2011 if (LdVT == MVT::i64) return X86::INC64m;
2012 if (LdVT == MVT::i32) return X86::INC32m;
2013 if (LdVT == MVT::i16) return X86::INC16m;
2014 if (LdVT == MVT::i8) return X86::INC8m;
2016 llvm_unreachable("unrecognized size for LdVT");
2019 /// SelectGather - Customized ISel for GATHER operations.
2021 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2022 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2023 SDValue Chain = Node->getOperand(0);
2024 SDValue VSrc = Node->getOperand(2);
2025 SDValue Base = Node->getOperand(3);
2026 SDValue VIdx = Node->getOperand(4);
2027 SDValue VMask = Node->getOperand(5);
2028 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2032 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2035 // Memory Operands: Base, Scale, Index, Disp, Segment
2036 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
2037 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2038 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
2039 Disp, Segment, VMask, Chain};
2040 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
2041 // Node has 2 outputs: VDst and MVT::Other.
2042 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2043 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2045 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2046 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2050 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2051 MVT NVT = Node->getSimpleValueType(0);
2053 unsigned Opcode = Node->getOpcode();
2056 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2058 if (Node->isMachineOpcode()) {
2059 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2060 Node->setNodeId(-1);
2061 return NULL; // Already selected.
2066 case ISD::INTRINSIC_W_CHAIN: {
2067 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2070 case Intrinsic::x86_avx2_gather_d_pd:
2071 case Intrinsic::x86_avx2_gather_d_pd_256:
2072 case Intrinsic::x86_avx2_gather_q_pd:
2073 case Intrinsic::x86_avx2_gather_q_pd_256:
2074 case Intrinsic::x86_avx2_gather_d_ps:
2075 case Intrinsic::x86_avx2_gather_d_ps_256:
2076 case Intrinsic::x86_avx2_gather_q_ps:
2077 case Intrinsic::x86_avx2_gather_q_ps_256:
2078 case Intrinsic::x86_avx2_gather_d_q:
2079 case Intrinsic::x86_avx2_gather_d_q_256:
2080 case Intrinsic::x86_avx2_gather_q_q:
2081 case Intrinsic::x86_avx2_gather_q_q_256:
2082 case Intrinsic::x86_avx2_gather_d_d:
2083 case Intrinsic::x86_avx2_gather_d_d_256:
2084 case Intrinsic::x86_avx2_gather_q_d:
2085 case Intrinsic::x86_avx2_gather_q_d_256: {
2086 if (!Subtarget->hasAVX2())
2090 default: llvm_unreachable("Impossible intrinsic");
2091 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2092 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2093 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2094 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2095 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2096 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2097 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2098 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2099 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2100 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2101 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2102 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2103 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2104 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2105 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2106 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2108 SDNode *RetVal = SelectGather(Node, Opc);
2110 // We already called ReplaceUses inside SelectGather.
2117 case X86ISD::GlobalBaseReg:
2118 return getGlobalBaseReg();
2121 case X86ISD::ATOMOR64_DAG:
2122 case X86ISD::ATOMXOR64_DAG:
2123 case X86ISD::ATOMADD64_DAG:
2124 case X86ISD::ATOMSUB64_DAG:
2125 case X86ISD::ATOMNAND64_DAG:
2126 case X86ISD::ATOMAND64_DAG:
2127 case X86ISD::ATOMMAX64_DAG:
2128 case X86ISD::ATOMMIN64_DAG:
2129 case X86ISD::ATOMUMAX64_DAG:
2130 case X86ISD::ATOMUMIN64_DAG:
2131 case X86ISD::ATOMSWAP64_DAG: {
2134 default: llvm_unreachable("Impossible opcode");
2135 case X86ISD::ATOMOR64_DAG: Opc = X86::ATOMOR6432; break;
2136 case X86ISD::ATOMXOR64_DAG: Opc = X86::ATOMXOR6432; break;
2137 case X86ISD::ATOMADD64_DAG: Opc = X86::ATOMADD6432; break;
2138 case X86ISD::ATOMSUB64_DAG: Opc = X86::ATOMSUB6432; break;
2139 case X86ISD::ATOMNAND64_DAG: Opc = X86::ATOMNAND6432; break;
2140 case X86ISD::ATOMAND64_DAG: Opc = X86::ATOMAND6432; break;
2141 case X86ISD::ATOMMAX64_DAG: Opc = X86::ATOMMAX6432; break;
2142 case X86ISD::ATOMMIN64_DAG: Opc = X86::ATOMMIN6432; break;
2143 case X86ISD::ATOMUMAX64_DAG: Opc = X86::ATOMUMAX6432; break;
2144 case X86ISD::ATOMUMIN64_DAG: Opc = X86::ATOMUMIN6432; break;
2145 case X86ISD::ATOMSWAP64_DAG: Opc = X86::ATOMSWAP6432; break;
2147 SDNode *RetVal = SelectAtomic64(Node, Opc);
2153 case ISD::ATOMIC_LOAD_XOR:
2154 case ISD::ATOMIC_LOAD_AND:
2155 case ISD::ATOMIC_LOAD_OR:
2156 case ISD::ATOMIC_LOAD_ADD: {
2157 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2165 // For operations of the form (x << C1) op C2, check if we can use a smaller
2166 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2167 SDValue N0 = Node->getOperand(0);
2168 SDValue N1 = Node->getOperand(1);
2170 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2173 // i8 is unshrinkable, i16 should be promoted to i32.
2174 if (NVT != MVT::i32 && NVT != MVT::i64)
2177 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2178 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2179 if (!Cst || !ShlCst)
2182 int64_t Val = Cst->getSExtValue();
2183 uint64_t ShlVal = ShlCst->getZExtValue();
2185 // Make sure that we don't change the operation by removing bits.
2186 // This only matters for OR and XOR, AND is unaffected.
2187 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2188 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2194 // Check the minimum bitwidth for the new constant.
2195 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2196 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2197 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2198 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2200 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2203 // Bail if there is no smaller encoding.
2207 switch (NVT.SimpleTy) {
2208 default: llvm_unreachable("Unsupported VT!");
2210 assert(CstVT == MVT::i8);
2211 ShlOp = X86::SHL32ri;
2214 default: llvm_unreachable("Impossible opcode");
2215 case ISD::AND: Op = X86::AND32ri8; break;
2216 case ISD::OR: Op = X86::OR32ri8; break;
2217 case ISD::XOR: Op = X86::XOR32ri8; break;
2221 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2222 ShlOp = X86::SHL64ri;
2225 default: llvm_unreachable("Impossible opcode");
2226 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2227 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2228 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2233 // Emit the smaller op and the shift.
2234 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2235 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2236 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2239 case X86ISD::UMUL: {
2240 SDValue N0 = Node->getOperand(0);
2241 SDValue N1 = Node->getOperand(1);
2244 switch (NVT.SimpleTy) {
2245 default: llvm_unreachable("Unsupported VT!");
2246 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2247 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2248 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2249 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2252 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2253 N0, SDValue()).getValue(1);
2255 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2256 SDValue Ops[] = {N1, InFlag};
2257 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2259 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2260 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2261 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2265 case ISD::SMUL_LOHI:
2266 case ISD::UMUL_LOHI: {
2267 SDValue N0 = Node->getOperand(0);
2268 SDValue N1 = Node->getOperand(1);
2270 bool isSigned = Opcode == ISD::SMUL_LOHI;
2271 bool hasBMI2 = Subtarget->hasBMI2();
2273 switch (NVT.SimpleTy) {
2274 default: llvm_unreachable("Unsupported VT!");
2275 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2276 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2277 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2278 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2279 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2280 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2283 switch (NVT.SimpleTy) {
2284 default: llvm_unreachable("Unsupported VT!");
2285 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2286 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2287 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2288 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2292 unsigned SrcReg, LoReg, HiReg;
2294 default: llvm_unreachable("Unknown MUL opcode!");
2297 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2301 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2305 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2309 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2312 SrcReg = X86::EDX; LoReg = HiReg = 0;
2315 SrcReg = X86::RDX; LoReg = HiReg = 0;
2319 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2320 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2321 // Multiply is commmutative.
2323 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2328 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2329 N0, SDValue()).getValue(1);
2330 SDValue ResHi, ResLo;
2334 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2336 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2337 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2338 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2339 ResHi = SDValue(CNode, 0);
2340 ResLo = SDValue(CNode, 1);
2341 Chain = SDValue(CNode, 2);
2342 InFlag = SDValue(CNode, 3);
2344 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2345 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2346 Chain = SDValue(CNode, 0);
2347 InFlag = SDValue(CNode, 1);
2350 // Update the chain.
2351 ReplaceUses(N1.getValue(1), Chain);
2353 SDValue Ops[] = { N1, InFlag };
2354 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2355 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2356 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2357 ResHi = SDValue(CNode, 0);
2358 ResLo = SDValue(CNode, 1);
2359 InFlag = SDValue(CNode, 2);
2361 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2362 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2363 InFlag = SDValue(CNode, 0);
2367 // Prevent use of AH in a REX instruction by referencing AX instead.
2368 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2369 !SDValue(Node, 1).use_empty()) {
2370 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2371 X86::AX, MVT::i16, InFlag);
2372 InFlag = Result.getValue(2);
2373 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2375 if (!SDValue(Node, 0).use_empty())
2376 ReplaceUses(SDValue(Node, 1),
2377 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2379 // Shift AX down 8 bits.
2380 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2382 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2383 // Then truncate it down to i8.
2384 ReplaceUses(SDValue(Node, 1),
2385 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2387 // Copy the low half of the result, if it is needed.
2388 if (!SDValue(Node, 0).use_empty()) {
2389 if (ResLo.getNode() == 0) {
2390 assert(LoReg && "Register for low half is not defined!");
2391 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2393 InFlag = ResLo.getValue(2);
2395 ReplaceUses(SDValue(Node, 0), ResLo);
2396 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2398 // Copy the high half of the result, if it is needed.
2399 if (!SDValue(Node, 1).use_empty()) {
2400 if (ResHi.getNode() == 0) {
2401 assert(HiReg && "Register for high half is not defined!");
2402 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2404 InFlag = ResHi.getValue(2);
2406 ReplaceUses(SDValue(Node, 1), ResHi);
2407 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2414 case ISD::UDIVREM: {
2415 SDValue N0 = Node->getOperand(0);
2416 SDValue N1 = Node->getOperand(1);
2418 bool isSigned = Opcode == ISD::SDIVREM;
2420 switch (NVT.SimpleTy) {
2421 default: llvm_unreachable("Unsupported VT!");
2422 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2423 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2424 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2425 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2428 switch (NVT.SimpleTy) {
2429 default: llvm_unreachable("Unsupported VT!");
2430 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2431 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2432 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2433 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2437 unsigned LoReg, HiReg, ClrReg;
2438 unsigned SExtOpcode;
2439 switch (NVT.SimpleTy) {
2440 default: llvm_unreachable("Unsupported VT!");
2442 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2443 SExtOpcode = X86::CBW;
2446 LoReg = X86::AX; HiReg = X86::DX;
2448 SExtOpcode = X86::CWD;
2451 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2452 SExtOpcode = X86::CDQ;
2455 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2456 SExtOpcode = X86::CQO;
2460 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2461 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2462 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2465 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2466 // Special case for div8, just use a move with zero extension to AX to
2467 // clear the upper 8 bits (AH).
2468 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2469 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2470 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2472 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2473 MVT::Other, Ops), 0);
2474 Chain = Move.getValue(1);
2475 ReplaceUses(N0.getValue(1), Chain);
2478 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2479 Chain = CurDAG->getEntryNode();
2481 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2482 InFlag = Chain.getValue(1);
2485 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2486 LoReg, N0, SDValue()).getValue(1);
2487 if (isSigned && !signBitIsZero) {
2488 // Sign extend the low part into the high part.
2490 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2492 // Zero out the high part, effectively zero extending the input.
2493 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2494 switch (NVT.SimpleTy) {
2497 SDValue(CurDAG->getMachineNode(
2498 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2499 CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
2506 SDValue(CurDAG->getMachineNode(
2507 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2508 CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
2509 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2513 llvm_unreachable("Unexpected division source");
2516 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2517 ClrNode, InFlag).getValue(1);
2522 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2525 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2526 InFlag = SDValue(CNode, 1);
2527 // Update the chain.
2528 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2531 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2534 // Prevent use of AH in a REX instruction by referencing AX instead.
2535 // Shift it down 8 bits.
2537 // The current assumption of the register allocator is that isel
2538 // won't generate explicit references to the GPR8_NOREX registers. If
2539 // the allocator and/or the backend get enhanced to be more robust in
2540 // that regard, this can be, and should be, removed.
2541 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2542 !SDValue(Node, 1).use_empty()) {
2543 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2544 X86::AX, MVT::i16, InFlag);
2545 InFlag = Result.getValue(2);
2547 // If we also need AL (the quotient), get it by extracting a subreg from
2548 // Result. The fast register allocator does not like multiple CopyFromReg
2549 // nodes using aliasing registers.
2550 if (!SDValue(Node, 0).use_empty())
2551 ReplaceUses(SDValue(Node, 0),
2552 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2554 // Shift AX right by 8 bits instead of using AH.
2555 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2557 CurDAG->getTargetConstant(8, MVT::i8)),
2559 ReplaceUses(SDValue(Node, 1),
2560 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2562 // Copy the division (low) result, if it is needed.
2563 if (!SDValue(Node, 0).use_empty()) {
2564 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2565 LoReg, NVT, InFlag);
2566 InFlag = Result.getValue(2);
2567 ReplaceUses(SDValue(Node, 0), Result);
2568 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2570 // Copy the remainder (high) result, if it is needed.
2571 if (!SDValue(Node, 1).use_empty()) {
2572 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2573 HiReg, NVT, InFlag);
2574 InFlag = Result.getValue(2);
2575 ReplaceUses(SDValue(Node, 1), Result);
2576 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2583 // Sometimes a SUB is used to perform comparison.
2584 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2585 // This node is not a CMP.
2587 SDValue N0 = Node->getOperand(0);
2588 SDValue N1 = Node->getOperand(1);
2590 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2591 // use a smaller encoding.
2592 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2593 HasNoSignedComparisonUses(Node))
2594 // Look past the truncate if CMP is the only use of it.
2595 N0 = N0.getOperand(0);
2596 if ((N0.getNode()->getOpcode() == ISD::AND ||
2597 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2598 N0.getNode()->hasOneUse() &&
2599 N0.getValueType() != MVT::i8 &&
2600 X86::isZeroNode(N1)) {
2601 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2604 // For example, convert "testl %eax, $8" to "testb %al, $8"
2605 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2606 (!(C->getZExtValue() & 0x80) ||
2607 HasNoSignedComparisonUses(Node))) {
2608 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2609 SDValue Reg = N0.getNode()->getOperand(0);
2611 // On x86-32, only the ABCD registers have 8-bit subregisters.
2612 if (!Subtarget->is64Bit()) {
2613 const TargetRegisterClass *TRC;
2614 switch (N0.getSimpleValueType().SimpleTy) {
2615 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2616 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2617 default: llvm_unreachable("Unsupported TEST operand type!");
2619 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2620 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2621 Reg.getValueType(), Reg, RC), 0);
2624 // Extract the l-register.
2625 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2629 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2631 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2632 // one, do not call ReplaceAllUsesWith.
2633 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2634 SDValue(NewNode, 0));
2638 // For example, "testl %eax, $2048" to "testb %ah, $8".
2639 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2640 (!(C->getZExtValue() & 0x8000) ||
2641 HasNoSignedComparisonUses(Node))) {
2642 // Shift the immediate right by 8 bits.
2643 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2645 SDValue Reg = N0.getNode()->getOperand(0);
2647 // Put the value in an ABCD register.
2648 const TargetRegisterClass *TRC;
2649 switch (N0.getSimpleValueType().SimpleTy) {
2650 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2651 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2652 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2653 default: llvm_unreachable("Unsupported TEST operand type!");
2655 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2656 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2657 Reg.getValueType(), Reg, RC), 0);
2659 // Extract the h-register.
2660 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2663 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2664 // target GR8_NOREX registers, so make sure the register class is
2666 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2667 MVT::i32, Subreg, ShiftedImm);
2668 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2669 // one, do not call ReplaceAllUsesWith.
2670 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2671 SDValue(NewNode, 0));
2675 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2676 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2677 N0.getValueType() != MVT::i16 &&
2678 (!(C->getZExtValue() & 0x8000) ||
2679 HasNoSignedComparisonUses(Node))) {
2680 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2681 SDValue Reg = N0.getNode()->getOperand(0);
2683 // Extract the 16-bit subregister.
2684 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2688 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2690 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2691 // one, do not call ReplaceAllUsesWith.
2692 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2693 SDValue(NewNode, 0));
2697 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2698 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2699 N0.getValueType() == MVT::i64 &&
2700 (!(C->getZExtValue() & 0x80000000) ||
2701 HasNoSignedComparisonUses(Node))) {
2702 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2703 SDValue Reg = N0.getNode()->getOperand(0);
2705 // Extract the 32-bit subregister.
2706 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2710 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2712 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2713 // one, do not call ReplaceAllUsesWith.
2714 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2715 SDValue(NewNode, 0));
2722 // Change a chain of {load; incr or dec; store} of the same value into
2723 // a simple increment or decrement through memory of that value, if the
2724 // uses of the modified value and its address are suitable.
2725 // The DEC64m tablegen pattern is currently not able to match the case where
2726 // the EFLAGS on the original DEC are used. (This also applies to
2727 // {INC,DEC}X{64,32,16,8}.)
2728 // We'll need to improve tablegen to allow flags to be transferred from a
2729 // node in the pattern to the result node. probably with a new keyword
2730 // for example, we have this
2731 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2732 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2733 // (implicit EFLAGS)]>;
2734 // but maybe need something like this
2735 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2736 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2737 // (transferrable EFLAGS)]>;
2739 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2740 SDValue StoredVal = StoreNode->getOperand(1);
2741 unsigned Opc = StoredVal->getOpcode();
2743 LoadSDNode *LoadNode = 0;
2745 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2746 LoadNode, InputChain))
2749 SDValue Base, Scale, Index, Disp, Segment;
2750 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2751 Base, Scale, Index, Disp, Segment))
2754 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2755 MemOp[0] = StoreNode->getMemOperand();
2756 MemOp[1] = LoadNode->getMemOperand();
2757 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2758 EVT LdVT = LoadNode->getMemoryVT();
2759 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2760 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2762 MVT::i32, MVT::Other, Ops);
2763 Result->setMemRefs(MemOp, MemOp + 2);
2765 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2766 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2772 SDNode *ResNode = SelectCode(Node);
2774 DEBUG(dbgs() << "=> ";
2775 if (ResNode == NULL || ResNode == Node)
2778 ResNode->dump(CurDAG);
2784 bool X86DAGToDAGISel::
2785 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2786 std::vector<SDValue> &OutOps) {
2787 SDValue Op0, Op1, Op2, Op3, Op4;
2788 switch (ConstraintCode) {
2789 case 'o': // offsetable ??
2790 case 'v': // not offsetable ??
2791 default: return true;
2793 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
2798 OutOps.push_back(Op0);
2799 OutOps.push_back(Op1);
2800 OutOps.push_back(Op2);
2801 OutOps.push_back(Op3);
2802 OutOps.push_back(Op4);
2806 /// createX86ISelDag - This pass converts a legalized DAG into a
2807 /// X86-specific DAG, ready for instruction scheduling.
2809 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2810 CodeGenOpt::Level OptLevel) {
2811 return new X86DAGToDAGISel(TM, OptLevel);