1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SSARegMap.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/ADT/Statistic.h"
39 //===----------------------------------------------------------------------===//
40 // Pattern Matcher Implementation
41 //===----------------------------------------------------------------------===//
44 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
45 /// SDOperand's instead of register numbers for the leaves of the matched
47 struct X86ISelAddressMode {
53 struct { // This is really a union, discriminated by BaseType!
63 unsigned Align; // CP alignment.
66 : BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0),
74 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
76 //===--------------------------------------------------------------------===//
77 /// ISel - X86 specific code to select X86 machine instructions for
78 /// SelectionDAG operations.
80 class X86DAGToDAGISel : public SelectionDAGISel {
81 /// ContainsFPCode - Every instruction we select that uses or defines a FP
82 /// register should set this to true.
85 /// X86Lowering - This object fully describes how to lower LLVM code to an
86 /// X86-specific SelectionDAG.
87 X86TargetLowering X86Lowering;
89 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
90 /// make the right decision when generating code for different targets.
91 const X86Subtarget *Subtarget;
93 unsigned GlobalBaseReg;
95 X86DAGToDAGISel(X86TargetMachine &TM)
96 : SelectionDAGISel(X86Lowering),
97 X86Lowering(*TM.getTargetLowering()) {
98 Subtarget = &TM.getSubtarget<X86Subtarget>();
101 virtual bool runOnFunction(Function &Fn) {
102 // Make sure we re-emit a set of the global base reg if necessary
104 return SelectionDAGISel::runOnFunction(Fn);
107 virtual const char *getPassName() const {
108 return "X86 DAG->DAG Instruction Selection";
111 /// InstructionSelectBasicBlock - This callback is invoked by
112 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
113 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
115 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
117 // Include the pieces autogenerated from the target description.
118 #include "X86GenDAGISel.inc"
121 void Select(SDOperand &Result, SDOperand N);
123 bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
124 bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
125 SDOperand &Index, SDOperand &Disp);
126 bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
127 SDOperand &Index, SDOperand &Disp);
128 bool TryFoldLoad(SDOperand P, SDOperand N,
129 SDOperand &Base, SDOperand &Scale,
130 SDOperand &Index, SDOperand &Disp);
132 inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
133 SDOperand &Scale, SDOperand &Index,
135 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
136 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
137 Scale = getI8Imm(AM.Scale);
139 Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
141 CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp)
142 : getI32Imm(AM.Disp));
145 /// getI8Imm - Return a target constant with the specified value, of type
147 inline SDOperand getI8Imm(unsigned Imm) {
148 return CurDAG->getTargetConstant(Imm, MVT::i8);
151 /// getI16Imm - Return a target constant with the specified value, of type
153 inline SDOperand getI16Imm(unsigned Imm) {
154 return CurDAG->getTargetConstant(Imm, MVT::i16);
157 /// getI32Imm - Return a target constant with the specified value, of type
159 inline SDOperand getI32Imm(unsigned Imm) {
160 return CurDAG->getTargetConstant(Imm, MVT::i32);
163 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
164 /// base register. Return the virtual register that holds this value.
165 SDOperand getGlobalBaseReg();
173 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
174 /// when it has created a SelectionDAG for us to codegen.
175 void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
177 MachineFunction::iterator FirstMBB = BB;
179 // Codegen the basic block.
181 DEBUG(std::cerr << "===== Instruction selection begins:\n");
184 DAG.setRoot(SelectRoot(DAG.getRoot()));
186 DEBUG(std::cerr << "===== Instruction selection ends:\n");
189 DAG.RemoveDeadNodes();
191 // Emit machine code to BB.
192 ScheduleAndEmitDAG(DAG);
194 // If we are emitting FP stack code, scan the basic block to determine if this
195 // block defines any FP values. If so, put an FP_REG_KILL instruction before
196 // the terminator of the block.
197 if (!Subtarget->hasSSE2()) {
198 // Note that FP stack instructions *are* used in SSE code when returning
199 // values, but these are not live out of the basic block, so we don't need
200 // an FP_REG_KILL in this case either.
201 bool ContainsFPCode = false;
203 // Scan all of the machine instructions in these MBBs, checking for FP
205 MachineFunction::iterator MBBI = FirstMBB;
207 for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
208 !ContainsFPCode && I != E; ++I) {
209 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
210 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
211 MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
212 RegMap->getRegClass(I->getOperand(0).getReg()) ==
213 X86::RFPRegisterClass) {
214 ContainsFPCode = true;
219 } while (!ContainsFPCode && &*(MBBI++) != BB);
221 // Check PHI nodes in successor blocks. These PHI's will be lowered to have
222 // a copy of the input value in this block.
223 if (!ContainsFPCode) {
224 // Final check, check LLVM BB's that are successors to the LLVM BB
225 // corresponding to BB for FP PHI nodes.
226 const BasicBlock *LLVMBB = BB->getBasicBlock();
228 for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
229 !ContainsFPCode && SI != E; ++SI) {
230 for (BasicBlock::const_iterator II = SI->begin();
231 (PN = dyn_cast<PHINode>(II)); ++II) {
232 if (PN->getType()->isFloatingPoint()) {
233 ContainsFPCode = true;
240 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
241 if (ContainsFPCode) {
242 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
248 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
249 /// the main function.
250 static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
251 MachineFrameInfo *MFI) {
252 // Switch the FPU to 64-bit precision mode for better compatibility and speed.
253 int CWFrameIdx = MFI->CreateStackObject(2, 2);
254 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
256 // Set the high part to be 64-bit precision.
257 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
258 CWFrameIdx, 1).addImm(2);
260 // Reload the modified control word now.
261 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
264 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
265 // If this is main, emit special code for main.
266 MachineBasicBlock *BB = MF.begin();
267 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
268 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
271 /// MatchAddress - Add the specified node to the specified addressing mode,
272 /// returning true if it cannot be done. This just pattern matches for the
274 bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
276 bool Available = false;
277 // If N has already been selected, reuse the result unless in some very
279 std::map<SDOperand, SDOperand>::iterator CGMI= CodeGenMap.find(N.getValue(0));
280 if (CGMI != CodeGenMap.end()) {
284 switch (N.getOpcode()) {
287 AM.Disp += cast<ConstantSDNode>(N)->getValue();
290 case X86ISD::Wrapper:
291 // If both base and index components have been picked, we can't fit
292 // the result available in the register in the addressing mode. Duplicate
293 // GlobalAddress or ConstantPool as displacement.
294 if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
295 if (ConstantPoolSDNode *CP =
296 dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
299 AM.Align = CP->getAlignment();
300 AM.Disp += CP->getOffset();
303 } else if (GlobalAddressSDNode *G =
304 dyn_cast<GlobalAddressSDNode>(N.getOperand(0))) {
306 AM.GV = G->getGlobal();
307 AM.Disp += G->getOffset();
314 case ISD::FrameIndex:
315 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
316 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
317 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
323 if (!Available && AM.IndexReg.Val == 0 && AM.Scale == 1)
324 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
325 unsigned Val = CN->getValue();
326 if (Val == 1 || Val == 2 || Val == 3) {
328 SDOperand ShVal = N.Val->getOperand(0);
330 // Okay, we know that we have a scale by now. However, if the scaled
331 // value is an add of something and a constant, we can fold the
332 // constant into the disp field here.
333 if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
334 isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
335 AM.IndexReg = ShVal.Val->getOperand(0);
336 ConstantSDNode *AddVal =
337 cast<ConstantSDNode>(ShVal.Val->getOperand(1));
338 AM.Disp += AddVal->getValue() << Val;
348 // X*[3,5,9] -> X+X*[2,4,8]
350 AM.BaseType == X86ISelAddressMode::RegBase &&
351 AM.Base.Reg.Val == 0 &&
352 AM.IndexReg.Val == 0)
353 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
354 if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
355 AM.Scale = unsigned(CN->getValue())-1;
357 SDOperand MulVal = N.Val->getOperand(0);
360 // Okay, we know that we have a scale by now. However, if the scaled
361 // value is an add of something and a constant, we can fold the
362 // constant into the disp field here.
363 if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
364 isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
365 Reg = MulVal.Val->getOperand(0);
366 ConstantSDNode *AddVal =
367 cast<ConstantSDNode>(MulVal.Val->getOperand(1));
368 AM.Disp += AddVal->getValue() * CN->getValue();
370 Reg = N.Val->getOperand(0);
373 AM.IndexReg = AM.Base.Reg = Reg;
380 X86ISelAddressMode Backup = AM;
381 if (!MatchAddress(N.Val->getOperand(0), AM, false) &&
382 !MatchAddress(N.Val->getOperand(1), AM, false))
385 if (!MatchAddress(N.Val->getOperand(1), AM, false) &&
386 !MatchAddress(N.Val->getOperand(0), AM, false))
394 // Is the base register already occupied?
395 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
396 // If so, check to see if the scale index register is set.
397 if (AM.IndexReg.Val == 0) {
403 // Otherwise, we cannot select it.
407 // Default, generate it as a register.
408 AM.BaseType = X86ISelAddressMode::RegBase;
413 /// SelectAddr - returns true if it is able pattern match an addressing mode.
414 /// It returns the operands which make up the maximal addressing mode it can
415 /// match by reference.
416 bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
417 SDOperand &Index, SDOperand &Disp) {
418 X86ISelAddressMode AM;
419 if (MatchAddress(N, AM))
422 if (AM.BaseType == X86ISelAddressMode::RegBase) {
423 if (!AM.Base.Reg.Val)
424 AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
427 if (!AM.IndexReg.Val)
428 AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
430 getAddressOperands(AM, Base, Scale, Index, Disp);
435 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
436 /// mode it matches can be cost effectively emitted as an LEA instruction.
437 /// For X86, it always is unless it's just a (Reg + const).
438 bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
440 SDOperand &Index, SDOperand &Disp) {
441 X86ISelAddressMode AM;
442 if (MatchAddress(N, AM))
445 unsigned Complexity = 0;
446 if (AM.BaseType == X86ISelAddressMode::RegBase)
450 AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
451 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
457 AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
461 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg
462 else if (AM.Scale > 1)
465 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
466 // to a LEA. This is determined with some expermentation but is by no means
467 // optimal (especially for code size consideration). LEA is nice because of
468 // its three-address nature. Tweak the cost function again when we can run
469 // convertToThreeAddress() at register allocation time.
473 if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
476 if (Complexity > 2) {
477 getAddressOperands(AM, Base, Scale, Index, Disp);
484 bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
485 SDOperand &Base, SDOperand &Scale,
486 SDOperand &Index, SDOperand &Disp) {
487 if (N.getOpcode() == ISD::LOAD &&
489 !CodeGenMap.count(N.getValue(0)) &&
490 (P.getNumOperands() == 1 || !isNonImmUse(P.Val, N.Val)))
491 return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
495 static bool isRegister0(SDOperand Op) {
496 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
497 return (R->getReg() == 0);
501 /// getGlobalBaseReg - Output the instructions required to put the
502 /// base address to use for accessing globals into a register.
504 SDOperand X86DAGToDAGISel::getGlobalBaseReg() {
505 if (!GlobalBaseReg) {
506 // Insert the set of GlobalBaseReg into the first MBB of the function
507 MachineBasicBlock &FirstMBB = BB->getParent()->front();
508 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
509 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
510 // FIXME: when we get to LP64, we will need to create the appropriate
511 // type of register here.
512 GlobalBaseReg = RegMap->createVirtualRegister(X86::R32RegisterClass);
513 BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
514 BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
516 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
519 void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
520 SDNode *Node = N.Val;
521 MVT::ValueType NVT = Node->getValueType(0);
523 unsigned Opcode = Node->getOpcode();
526 DEBUG(std::cerr << std::string(Indent, ' '));
527 DEBUG(std::cerr << "Selecting: ");
528 DEBUG(Node->dump(CurDAG));
529 DEBUG(std::cerr << "\n");
533 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) {
536 DEBUG(std::cerr << std::string(Indent-2, ' '));
537 DEBUG(std::cerr << "== ");
538 DEBUG(Node->dump(CurDAG));
539 DEBUG(std::cerr << "\n");
542 return; // Already selected.
545 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
546 if (CGMI != CodeGenMap.end()) {
547 Result = CGMI->second;
549 DEBUG(std::cerr << std::string(Indent-2, ' '));
550 DEBUG(std::cerr << "== ");
551 DEBUG(Result.Val->dump(CurDAG));
552 DEBUG(std::cerr << "\n");
560 case X86ISD::GlobalBaseReg:
561 Result = getGlobalBaseReg();
565 // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
566 // code and is matched first so to prevent it from being turned into
568 SDOperand N0 = N.getOperand(0);
569 SDOperand N1 = N.getOperand(1);
570 if (N.Val->getValueType(0) == MVT::i32 &&
571 N0.getOpcode() == X86ISD::Wrapper &&
572 N1.getOpcode() == ISD::Constant) {
573 unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
575 // TODO: handle ExternalSymbolSDNode.
576 if (GlobalAddressSDNode *G =
577 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
578 C = CurDAG->getTargetGlobalAddress(G->getGlobal(), MVT::i32,
579 G->getOffset() + Offset);
580 } else if (ConstantPoolSDNode *CP =
581 dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
582 C = CurDAG->getTargetConstantPool(CP->get(), MVT::i32,
584 CP->getOffset()+Offset);
588 if (N.Val->hasOneUse()) {
589 Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
591 SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C);
592 Result = CodeGenMap[N] = SDOperand(ResNode, 0);
598 // Other cases are handled by auto-generated code.
604 if (Opcode == ISD::MULHU)
606 default: assert(0 && "Unsupported VT!");
607 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
608 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
609 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
613 default: assert(0 && "Unsupported VT!");
614 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
615 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
616 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
619 unsigned LoReg, HiReg;
621 default: assert(0 && "Unsupported VT!");
622 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
623 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
624 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
627 SDOperand N0 = Node->getOperand(0);
628 SDOperand N1 = Node->getOperand(1);
630 bool foldedLoad = false;
631 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
632 foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
633 // MULHU and MULHS are commmutative
635 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
637 N0 = Node->getOperand(1);
638 N1 = Node->getOperand(0);
644 Select(Chain, N1.getOperand(0));
646 Chain = CurDAG->getEntryNode();
648 SDOperand InFlag(0, 0);
650 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
652 InFlag = Chain.getValue(1);
660 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
661 Tmp2, Tmp3, Chain, InFlag);
662 Chain = SDOperand(CNode, 0);
663 InFlag = SDOperand(CNode, 1);
667 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
670 Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
671 CodeGenMap[N.getValue(0)] = Result;
673 CodeGenMap[N1.getValue(1)] = Result.getValue(1);
674 AddHandleReplacement(N1.Val, 1, Result.Val, 1);
678 DEBUG(std::cerr << std::string(Indent-2, ' '));
679 DEBUG(std::cerr << "== ");
680 DEBUG(Result.Val->dump(CurDAG));
681 DEBUG(std::cerr << "\n");
691 bool isSigned = Opcode == ISD::SDIV || Opcode == ISD::SREM;
692 bool isDiv = Opcode == ISD::SDIV || Opcode == ISD::UDIV;
695 default: assert(0 && "Unsupported VT!");
696 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
697 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
698 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
702 default: assert(0 && "Unsupported VT!");
703 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
704 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
705 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
708 unsigned LoReg, HiReg;
709 unsigned ClrOpcode, SExtOpcode;
711 default: assert(0 && "Unsupported VT!");
713 LoReg = X86::AL; HiReg = X86::AH;
714 ClrOpcode = X86::MOV8ri;
715 SExtOpcode = X86::CBW;
718 LoReg = X86::AX; HiReg = X86::DX;
719 ClrOpcode = X86::MOV16ri;
720 SExtOpcode = X86::CWD;
723 LoReg = X86::EAX; HiReg = X86::EDX;
724 ClrOpcode = X86::MOV32ri;
725 SExtOpcode = X86::CDQ;
729 SDOperand N0 = Node->getOperand(0);
730 SDOperand N1 = Node->getOperand(1);
732 bool foldedLoad = false;
733 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
734 foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
737 Select(Chain, N1.getOperand(0));
739 Chain = CurDAG->getEntryNode();
741 SDOperand InFlag(0, 0);
743 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
745 InFlag = Chain.getValue(1);
748 // Sign extend the low part into the high part.
750 SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
752 // Zero out the high part, effectively zero extending the input.
754 SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT,
755 CurDAG->getTargetConstant(0, NVT)), 0);
756 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT),
758 InFlag = Chain.getValue(1);
767 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
768 Tmp2, Tmp3, Chain, InFlag);
769 Chain = SDOperand(CNode, 0);
770 InFlag = SDOperand(CNode, 1);
774 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
777 Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
779 CodeGenMap[N.getValue(0)] = Result;
781 CodeGenMap[N1.getValue(1)] = Result.getValue(1);
782 AddHandleReplacement(N1.Val, 1, Result.Val, 1);
786 DEBUG(std::cerr << std::string(Indent-2, ' '));
787 DEBUG(std::cerr << "== ");
788 DEBUG(Result.Val->dump(CurDAG));
789 DEBUG(std::cerr << "\n");
795 case ISD::TRUNCATE: {
798 switch (Node->getOperand(0).getValueType()) {
799 default: assert(0 && "Unknown truncate!");
800 case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
801 case MVT::i32: Reg = X86::EAX; Opc = X86::MOV32rr; VT = MVT::i32; break;
803 SDOperand Tmp0, Tmp1;
804 Select(Tmp0, Node->getOperand(0));
805 Select(Tmp1, SDOperand(CurDAG->getTargetNode(Opc, VT, Tmp0), 0));
806 SDOperand InFlag = SDOperand(0,0);
807 Result = CurDAG->getCopyToReg(CurDAG->getEntryNode(), Reg, Tmp1, InFlag);
808 SDOperand Chain = Result.getValue(0);
809 InFlag = Result.getValue(1);
812 default: assert(0 && "Unknown truncate!");
813 case MVT::i8: Reg = X86::AL; Opc = X86::MOV8rr; VT = MVT::i8; break;
814 case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
817 Result = CurDAG->getCopyFromReg(Chain, Reg, VT, InFlag);
818 if (N.Val->hasOneUse())
819 Result = CurDAG->SelectNodeTo(N.Val, Opc, VT, Result);
821 Result = CodeGenMap[N] =
822 SDOperand(CurDAG->getTargetNode(Opc, VT, Result), 0);
825 DEBUG(std::cerr << std::string(Indent-2, ' '));
826 DEBUG(std::cerr << "== ");
827 DEBUG(Result.Val->dump(CurDAG));
828 DEBUG(std::cerr << "\n");
835 SelectCode(Result, N);
837 DEBUG(std::cerr << std::string(Indent-2, ' '));
838 DEBUG(std::cerr << "=> ");
839 DEBUG(Result.Val->dump(CurDAG));
840 DEBUG(std::cerr << "\n");
845 /// createX86ISelDag - This pass converts a legalized DAG into a
846 /// X86-specific DAG, ready for instruction scheduling.
848 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM) {
849 return new X86DAGToDAGISel(TM);