1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "X86TargetMachine.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/CFG.h"
27 #include "llvm/Type.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/Streams.h"
40 #include "llvm/ADT/SmallPtrSet.h"
41 #include "llvm/ADT/Statistic.h"
44 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
46 //===----------------------------------------------------------------------===//
47 // Pattern Matcher Implementation
48 //===----------------------------------------------------------------------===//
51 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
52 /// SDValue's instead of register numbers for the leaves of the matched
54 struct X86ISelAddressMode {
60 struct { // This is really a union, discriminated by BaseType!
65 bool isRIPRel; // RIP as base?
73 unsigned Align; // CP alignment.
76 : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
77 GV(0), CP(0), ES(0), JT(-1), Align(0) {
80 cerr << "X86ISelAddressMode " << this << "\n";
82 if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
84 cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
85 cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n";
87 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
89 cerr << " Disp " << Disp << "\n";
90 cerr << "GV "; if (GV) GV->dump();
92 cerr << " CP "; if (CP) CP->dump();
95 cerr << "ES "; if (ES) cerr << ES; else cerr << "nul";
96 cerr << " JT" << JT << " Align" << Align << "\n";
102 //===--------------------------------------------------------------------===//
103 /// ISel - X86 specific code to select X86 machine instructions for
104 /// SelectionDAG operations.
106 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
107 /// TM - Keep a reference to X86TargetMachine.
109 X86TargetMachine &TM;
111 /// X86Lowering - This object fully describes how to lower LLVM code to an
112 /// X86-specific SelectionDAG.
113 X86TargetLowering &X86Lowering;
115 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
116 /// make the right decision when generating code for different targets.
117 const X86Subtarget *Subtarget;
119 /// CurBB - Current BB being isel'd.
121 MachineBasicBlock *CurBB;
123 /// OptForSize - If true, selector should try to optimize for code size
124 /// instead of performance.
128 X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
129 : SelectionDAGISel(tm, fast),
130 TM(tm), X86Lowering(*TM.getTargetLowering()),
131 Subtarget(&TM.getSubtarget<X86Subtarget>()),
134 virtual const char *getPassName() const {
135 return "X86 DAG->DAG Instruction Selection";
138 /// InstructionSelect - This callback is invoked by
139 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
140 virtual void InstructionSelect();
142 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
145 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
147 // Include the pieces autogenerated from the target description.
148 #include "X86GenDAGISel.inc"
151 SDNode *Select(SDValue N);
152 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
154 bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
155 bool isRoot = true, unsigned Depth = 0);
156 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
157 bool isRoot, unsigned Depth);
158 bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
159 SDValue &Scale, SDValue &Index, SDValue &Disp);
160 bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
161 SDValue &Scale, SDValue &Index, SDValue &Disp);
162 bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
163 SDValue N, SDValue &Base, SDValue &Scale,
164 SDValue &Index, SDValue &Disp,
165 SDValue &InChain, SDValue &OutChain);
166 bool TryFoldLoad(SDValue P, SDValue N,
167 SDValue &Base, SDValue &Scale,
168 SDValue &Index, SDValue &Disp);
169 void PreprocessForRMW();
170 void PreprocessForFPConvert();
172 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
173 /// inline asm expressions.
174 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
176 std::vector<SDValue> &OutOps);
178 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
180 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
181 SDValue &Scale, SDValue &Index,
183 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
184 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
186 Scale = getI8Imm(AM.Scale);
188 // These are 32-bit even in 64-bit mode since RIP relative offset
191 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp);
193 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
196 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32);
197 else if (AM.JT != -1)
198 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
200 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
203 /// getI8Imm - Return a target constant with the specified value, of type
205 inline SDValue getI8Imm(unsigned Imm) {
206 return CurDAG->getTargetConstant(Imm, MVT::i8);
209 /// getI16Imm - Return a target constant with the specified value, of type
211 inline SDValue getI16Imm(unsigned Imm) {
212 return CurDAG->getTargetConstant(Imm, MVT::i16);
215 /// getI32Imm - Return a target constant with the specified value, of type
217 inline SDValue getI32Imm(unsigned Imm) {
218 return CurDAG->getTargetConstant(Imm, MVT::i32);
221 /// getGlobalBaseReg - Return an SDNode that returns the value of
222 /// the global base register. Output instructions required to
223 /// initialize the global base register, if necessary.
225 SDNode *getGlobalBaseReg();
227 /// getTruncateTo8Bit - return an SDNode that implements a subreg based
228 /// truncate of the specified operand to i8. This can be done with tablegen,
229 /// except that this code uses MVT::Flag in a tricky way that happens to
230 /// improve scheduling in some cases.
231 SDNode *getTruncateTo8Bit(SDValue N0);
239 /// findFlagUse - Return use of MVT::Flag value produced by the specified
242 static SDNode *findFlagUse(SDNode *N) {
243 unsigned FlagResNo = N->getNumValues()-1;
244 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
245 SDUse &Use = I.getUse();
246 if (Use.getResNo() == FlagResNo)
247 return Use.getUser();
252 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
253 /// This function recursively traverses up the operand chain, ignoring
255 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
257 SmallPtrSet<SDNode*, 16> &Visited) {
258 if (Use->getNodeId() < Def->getNodeId() ||
259 !Visited.insert(Use))
262 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
263 SDNode *N = Use->getOperand(i).getNode();
265 if (Use == ImmedUse || Use == Root)
266 continue; // We are not looking for immediate use.
271 // Traverse up the operand chain.
272 if (findNonImmUse(N, Def, ImmedUse, Root, Visited))
278 /// isNonImmUse - Start searching from Root up the DAG to check is Def can
279 /// be reached. Return true if that's the case. However, ignore direct uses
280 /// by ImmedUse (which would be U in the example illustrated in
281 /// IsLegalAndProfitableToFold) and by Root (which can happen in the store
283 /// FIXME: to be really generic, we should allow direct use by any node
284 /// that is being folded. But realisticly since we only fold loads which
285 /// have one non-chain use, we only need to watch out for load/op/store
286 /// and load/op/cmp case where the root (store / cmp) may reach the load via
287 /// its chain operand.
288 static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
289 SmallPtrSet<SDNode*, 16> Visited;
290 return findNonImmUse(Root, Def, ImmedUse, Root, Visited);
294 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
295 SDNode *Root) const {
296 if (Fast) return false;
299 switch (U->getOpcode()) {
307 // If the other operand is a 8-bit immediate we should fold the immediate
308 // instead. This reduces code size.
310 // movl 4(%esp), %eax
314 // addl 4(%esp), %eax
315 // The former is 2 bytes shorter. In case where the increment is 1, then
316 // the saving can be 4 bytes (by using incl %eax).
317 ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(U->getOperand(1));
319 if (U->getValueType(0) == MVT::i64) {
320 if ((int32_t)Imm->getZExtValue() == (int64_t)Imm->getZExtValue())
323 if ((int8_t)Imm->getZExtValue() == (int64_t)Imm->getZExtValue())
330 // If Root use can somehow reach N through a path that that doesn't contain
331 // U then folding N would create a cycle. e.g. In the following
332 // diagram, Root can reach N through X. If N is folded into into Root, then
333 // X is both a predecessor and a successor of U.
344 // * indicates nodes to be folded together.
346 // If Root produces a flag, then it gets (even more) interesting. Since it
347 // will be "glued" together with its flag use in the scheduler, we need to
348 // check if it might reach N.
367 // If FU (flag use) indirectly reaches N (the load), and Root folds N
368 // (call it Fold), then X is a predecessor of FU and a successor of
369 // Fold. But since Fold and FU are flagged together, this will create
370 // a cycle in the scheduling graph.
372 MVT VT = Root->getValueType(Root->getNumValues()-1);
373 while (VT == MVT::Flag) {
374 SDNode *FU = findFlagUse(Root);
378 VT = Root->getValueType(Root->getNumValues()-1);
381 return !isNonImmUse(Root, N, U);
384 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
385 /// and move load below the TokenFactor. Replace store's chain operand with
386 /// load's chain result.
387 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
388 SDValue Store, SDValue TF) {
389 SmallVector<SDValue, 4> Ops;
390 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
391 if (Load.getNode() == TF.getOperand(i).getNode())
392 Ops.push_back(Load.getOperand(0));
394 Ops.push_back(TF.getOperand(i));
395 CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
396 CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
397 CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
398 Store.getOperand(2), Store.getOperand(3));
401 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
403 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
405 if (N.getOpcode() == ISD::BIT_CONVERT)
408 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
409 if (!LD || LD->isVolatile())
411 if (LD->getAddressingMode() != ISD::UNINDEXED)
414 ISD::LoadExtType ExtType = LD->getExtensionType();
415 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
419 N.getOperand(1) == Address &&
420 N.getNode()->isOperandOf(Chain.getNode())) {
427 /// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
428 /// operand and move load below the call's chain operand.
429 static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
430 SDValue Call, SDValue CallSeqStart) {
431 SmallVector<SDValue, 8> Ops;
432 SDValue Chain = CallSeqStart.getOperand(0);
433 if (Chain.getNode() == Load.getNode())
434 Ops.push_back(Load.getOperand(0));
436 assert(Chain.getOpcode() == ISD::TokenFactor &&
437 "Unexpected CallSeqStart chain operand");
438 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
439 if (Chain.getOperand(i).getNode() == Load.getNode())
440 Ops.push_back(Load.getOperand(0));
442 Ops.push_back(Chain.getOperand(i));
444 CurDAG->getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
446 Ops.push_back(NewChain);
448 for (unsigned i = 1, e = CallSeqStart.getNumOperands(); i != e; ++i)
449 Ops.push_back(CallSeqStart.getOperand(i));
450 CurDAG->UpdateNodeOperands(CallSeqStart, &Ops[0], Ops.size());
451 CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
452 Load.getOperand(1), Load.getOperand(2));
454 Ops.push_back(SDValue(Load.getNode(), 1));
455 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
456 Ops.push_back(Call.getOperand(i));
457 CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
460 /// isCalleeLoad - Return true if call address is a load and it can be
461 /// moved below CALLSEQ_START and the chains leading up to the call.
462 /// Return the CALLSEQ_START by reference as a second output.
463 static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
464 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
466 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
469 LD->getAddressingMode() != ISD::UNINDEXED ||
470 LD->getExtensionType() != ISD::NON_EXTLOAD)
473 // Now let's find the callseq_start.
474 while (Chain.getOpcode() != ISD::CALLSEQ_START) {
475 if (!Chain.hasOneUse())
477 Chain = Chain.getOperand(0);
480 if (Chain.getOperand(0).getNode() == Callee.getNode())
482 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
483 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()))
489 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
490 /// This is only run if not in -fast mode (aka -O0).
491 /// This allows the instruction selector to pick more read-modify-write
492 /// instructions. This is a common case:
502 /// [TokenFactor] [Op]
509 /// The fact the store's chain operand != load's chain will prevent the
510 /// (store (op (load))) instruction from being selected. We can transform it to:
529 void X86DAGToDAGISel::PreprocessForRMW() {
530 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
531 E = CurDAG->allnodes_end(); I != E; ++I) {
532 if (I->getOpcode() == X86ISD::CALL) {
533 /// Also try moving call address load from outside callseq_start to just
534 /// before the call to allow it to be folded.
552 SDValue Chain = I->getOperand(0);
553 SDValue Load = I->getOperand(1);
554 if (!isCalleeLoad(Load, Chain))
556 MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
561 if (!ISD::isNON_TRUNCStore(I))
563 SDValue Chain = I->getOperand(0);
565 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
568 SDValue N1 = I->getOperand(1);
569 SDValue N2 = I->getOperand(2);
570 if ((N1.getValueType().isFloatingPoint() &&
571 !N1.getValueType().isVector()) ||
577 unsigned Opcode = N1.getNode()->getOpcode();
586 case ISD::VECTOR_SHUFFLE: {
587 SDValue N10 = N1.getOperand(0);
588 SDValue N11 = N1.getOperand(1);
589 RModW = isRMWLoad(N10, Chain, N2, Load);
591 RModW = isRMWLoad(N11, Chain, N2, Load);
604 SDValue N10 = N1.getOperand(0);
605 RModW = isRMWLoad(N10, Chain, N2, Load);
611 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
618 /// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend
619 /// nodes that target the FP stack to be store and load to the stack. This is a
620 /// gross hack. We would like to simply mark these as being illegal, but when
621 /// we do that, legalize produces these when it expands calls, then expands
622 /// these in the same legalize pass. We would like dag combine to be able to
623 /// hack on these between the call expansion and the node legalization. As such
624 /// this pass basically does "really late" legalization of these inline with the
626 void X86DAGToDAGISel::PreprocessForFPConvert() {
627 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
628 E = CurDAG->allnodes_end(); I != E; ) {
629 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
630 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
633 // If the source and destination are SSE registers, then this is a legal
634 // conversion that should not be lowered.
635 MVT SrcVT = N->getOperand(0).getValueType();
636 MVT DstVT = N->getValueType(0);
637 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
638 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
639 if (SrcIsSSE && DstIsSSE)
642 if (!SrcIsSSE && !DstIsSSE) {
643 // If this is an FPStack extension, it is a noop.
644 if (N->getOpcode() == ISD::FP_EXTEND)
646 // If this is a value-preserving FPStack truncation, it is a noop.
647 if (N->getConstantOperandVal(1))
651 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
652 // FPStack has extload and truncstore. SSE can fold direct loads into other
653 // operations. Based on this, decide what we want to do.
655 if (N->getOpcode() == ISD::FP_ROUND)
656 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
658 MemVT = SrcIsSSE ? SrcVT : DstVT;
660 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
662 // FIXME: optimize the case where the src/dest is a load or store?
663 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(),
665 MemTmp, NULL, 0, MemVT);
666 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
669 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
670 // extload we created. This will cause general havok on the dag because
671 // anything below the conversion could be folded into other existing nodes.
672 // To avoid invalidating 'I', back it up to the convert node.
674 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
676 // Now that we did that, the node is dead. Increment the iterator to the
677 // next node to process, then delete N.
679 CurDAG->DeleteNode(N);
683 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
684 /// when it has created a SelectionDAG for us to codegen.
685 void X86DAGToDAGISel::InstructionSelect() {
686 CurBB = BB; // BB can change as result of isel.
687 const Function *F = CurDAG->getMachineFunction().getFunction();
688 OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
694 // FIXME: This should only happen when not -fast.
695 PreprocessForFPConvert();
697 // Codegen the basic block.
699 DOUT << "===== Instruction selection begins:\n";
704 DOUT << "===== Instruction selection ends:\n";
707 CurDAG->RemoveDeadNodes();
710 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
711 /// the main function.
712 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
713 MachineFrameInfo *MFI) {
714 const TargetInstrInfo *TII = TM.getInstrInfo();
715 if (Subtarget->isTargetCygMing())
716 BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
719 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
720 // If this is main, emit special code for main.
721 MachineBasicBlock *BB = MF.begin();
722 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
723 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
726 /// MatchAddress - Add the specified node to the specified addressing mode,
727 /// returning true if it cannot be done. This just pattern matches for the
729 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
730 bool isRoot, unsigned Depth) {
731 bool is64Bit = Subtarget->is64Bit();
732 DOUT << "MatchAddress: "; DEBUG(AM.dump());
735 return MatchAddressBase(N, AM, isRoot, Depth);
737 // RIP relative addressing: %rip + 32-bit displacement!
739 if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
740 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
741 if (!is64Bit || isInt32(AM.Disp + Val)) {
749 switch (N.getOpcode()) {
751 case ISD::Constant: {
752 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
753 if (!is64Bit || isInt32(AM.Disp + Val)) {
760 case X86ISD::Wrapper: {
761 DOUT << "Wrapper: 64bit " << is64Bit;
762 DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
763 // Under X86-64 non-small code model, GV (and friends) are 64-bits.
764 // Also, base and index reg must be 0 in order to use rip as base.
765 if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
766 AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
768 if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
770 // If value is available in a register both base and index components have
771 // been picked, we can't fit the result available in the register in the
772 // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
774 SDValue N0 = N.getOperand(0);
775 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
776 uint64_t Offset = G->getOffset();
777 if (!is64Bit || isInt32(AM.Disp + Offset)) {
778 GlobalValue *GV = G->getGlobal();
781 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
784 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
785 uint64_t Offset = CP->getOffset();
786 if (!is64Bit || isInt32(AM.Disp + Offset)) {
787 AM.CP = CP->getConstVal();
788 AM.Align = CP->getAlignment();
790 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
793 } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
794 AM.ES = S->getSymbol();
795 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
797 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
798 AM.JT = J->getIndex();
799 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
806 case ISD::FrameIndex:
807 if (AM.BaseType == X86ISelAddressMode::RegBase
808 && AM.Base.Reg.getNode() == 0) {
809 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
810 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
816 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1 || AM.isRIPRel)
820 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
821 unsigned Val = CN->getZExtValue();
822 if (Val == 1 || Val == 2 || Val == 3) {
824 SDValue ShVal = N.getNode()->getOperand(0);
826 // Okay, we know that we have a scale by now. However, if the scaled
827 // value is an add of something and a constant, we can fold the
828 // constant into the disp field here.
829 if (ShVal.getNode()->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
830 isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
831 AM.IndexReg = ShVal.getNode()->getOperand(0);
832 ConstantSDNode *AddVal =
833 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
834 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
835 if (!is64Bit || isInt32(Disp))
849 // A mul_lohi where we need the low part can be folded as a plain multiply.
850 if (N.getResNo() != 0) break;
853 // X*[3,5,9] -> X+X*[2,4,8]
854 if (AM.BaseType == X86ISelAddressMode::RegBase &&
855 AM.Base.Reg.getNode() == 0 &&
856 AM.IndexReg.getNode() == 0 &&
859 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
860 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
861 CN->getZExtValue() == 9) {
862 AM.Scale = unsigned(CN->getZExtValue())-1;
864 SDValue MulVal = N.getNode()->getOperand(0);
867 // Okay, we know that we have a scale by now. However, if the scaled
868 // value is an add of something and a constant, we can fold the
869 // constant into the disp field here.
870 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
871 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
872 Reg = MulVal.getNode()->getOperand(0);
873 ConstantSDNode *AddVal =
874 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
875 uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
877 if (!is64Bit || isInt32(Disp))
880 Reg = N.getNode()->getOperand(0);
882 Reg = N.getNode()->getOperand(0);
885 AM.IndexReg = AM.Base.Reg = Reg;
892 X86ISelAddressMode Backup = AM;
893 if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) &&
894 !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1))
897 if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) &&
898 !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1))
905 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
906 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
907 X86ISelAddressMode Backup = AM;
908 uint64_t Offset = CN->getSExtValue();
909 // Start with the LHS as an addr mode.
910 if (!MatchAddress(N.getOperand(0), AM, false) &&
911 // Address could not have picked a GV address for the displacement.
913 // On x86-64, the resultant disp must fit in 32-bits.
914 (!is64Bit || isInt32(AM.Disp + Offset)) &&
915 // Check to see if the LHS & C is zero.
916 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
925 // Handle "(x << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
926 // allows us to fold the shift into this addressing mode.
927 SDValue Shift = N.getOperand(0);
928 if (Shift.getOpcode() != ISD::SHL) break;
930 // Scale must not be used already.
931 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
933 // Not when RIP is used as the base.
934 if (AM.isRIPRel) break;
936 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
937 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
938 if (!C1 || !C2) break;
940 // Not likely to be profitable if either the AND or SHIFT node has more
941 // than one use (unless all uses are for address computation). Besides,
942 // isel mechanism requires their node ids to be reused.
943 if (!N.hasOneUse() || !Shift.hasOneUse())
946 // Verify that the shift amount is something we can fold.
947 unsigned ShiftCst = C1->getZExtValue();
948 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
951 // Get the new AND mask, this folds to a constant.
952 SDValue X = Shift.getOperand(0);
953 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
954 SDValue(C2, 0), SDValue(C1, 0));
955 SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(), X, NewANDMask);
956 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, N.getValueType(),
957 NewAND, SDValue(C1, 0));
959 // Insert the new nodes into the topological ordering.
960 if (C1->getNodeId() > X.getNode()->getNodeId()) {
961 CurDAG->RepositionNode(X.getNode(), C1);
962 C1->setNodeId(X.getNode()->getNodeId());
964 if (NewANDMask.getNode()->getNodeId() == -1 ||
965 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
966 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
967 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
969 if (NewAND.getNode()->getNodeId() == -1 ||
970 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
971 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
972 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
974 if (NewSHIFT.getNode()->getNodeId() == -1 ||
975 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
976 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
977 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
980 CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
982 AM.Scale = 1 << ShiftCst;
983 AM.IndexReg = NewAND;
988 return MatchAddressBase(N, AM, isRoot, Depth);
991 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
992 /// specified addressing mode without any further recursion.
993 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
994 bool isRoot, unsigned Depth) {
995 // Is the base register already occupied?
996 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
997 // If so, check to see if the scale index register is set.
998 if (AM.IndexReg.getNode() == 0 && !AM.isRIPRel) {
1004 // Otherwise, we cannot select it.
1008 // Default, generate it as a register.
1009 AM.BaseType = X86ISelAddressMode::RegBase;
1014 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1015 /// It returns the operands which make up the maximal addressing mode it can
1016 /// match by reference.
1017 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
1018 SDValue &Scale, SDValue &Index,
1020 X86ISelAddressMode AM;
1021 if (MatchAddress(N, AM))
1024 MVT VT = N.getValueType();
1025 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1026 if (!AM.Base.Reg.getNode())
1027 AM.Base.Reg = CurDAG->getRegister(0, VT);
1030 if (!AM.IndexReg.getNode())
1031 AM.IndexReg = CurDAG->getRegister(0, VT);
1033 getAddressOperands(AM, Base, Scale, Index, Disp);
1037 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1038 /// match a load whose top elements are either undef or zeros. The load flavor
1039 /// is derived from the type of N, which is either v4f32 or v2f64.
1040 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
1041 SDValue N, SDValue &Base,
1042 SDValue &Scale, SDValue &Index,
1043 SDValue &Disp, SDValue &InChain,
1044 SDValue &OutChain) {
1045 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1046 InChain = N.getOperand(0).getValue(1);
1047 if (ISD::isNON_EXTLoad(InChain.getNode()) &&
1048 InChain.getValue(0).hasOneUse() &&
1050 IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
1051 LoadSDNode *LD = cast<LoadSDNode>(InChain);
1052 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
1054 OutChain = LD->getChain();
1059 // Also handle the case where we explicitly require zeros in the top
1060 // elements. This is a vector shuffle from the zero vector.
1061 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1062 // Check to see if the top elements are all zeros (or bitcast of zeros).
1063 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1064 N.getOperand(0).getNode()->hasOneUse() &&
1065 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1066 N.getOperand(0).getOperand(0).hasOneUse()) {
1067 // Okay, this is a zero extending load. Fold it.
1068 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1069 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
1071 OutChain = LD->getChain();
1072 InChain = SDValue(LD, 1);
1079 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1080 /// mode it matches can be cost effectively emitted as an LEA instruction.
1081 bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
1082 SDValue &Base, SDValue &Scale,
1083 SDValue &Index, SDValue &Disp) {
1084 X86ISelAddressMode AM;
1085 if (MatchAddress(N, AM))
1088 MVT VT = N.getValueType();
1089 unsigned Complexity = 0;
1090 if (AM.BaseType == X86ISelAddressMode::RegBase)
1091 if (AM.Base.Reg.getNode())
1094 AM.Base.Reg = CurDAG->getRegister(0, VT);
1095 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1098 if (AM.IndexReg.getNode())
1101 AM.IndexReg = CurDAG->getRegister(0, VT);
1103 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1108 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1109 // to a LEA. This is determined with some expermentation but is by no means
1110 // optimal (especially for code size consideration). LEA is nice because of
1111 // its three-address nature. Tweak the cost function again when we can run
1112 // convertToThreeAddress() at register allocation time.
1113 if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
1114 // For X86-64, we should always use lea to materialize RIP relative
1116 if (Subtarget->is64Bit())
1122 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
1125 if (Complexity > 2) {
1126 getAddressOperands(AM, Base, Scale, Index, Disp);
1132 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
1133 SDValue &Base, SDValue &Scale,
1134 SDValue &Index, SDValue &Disp) {
1135 if (ISD::isNON_EXTLoad(N.getNode()) &&
1137 IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
1138 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
1142 /// getGlobalBaseReg - Return an SDNode that returns the value of
1143 /// the global base register. Output instructions required to
1144 /// initialize the global base register, if necessary.
1146 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1147 MachineFunction *MF = CurBB->getParent();
1148 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
1149 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1152 static SDNode *FindCallStartFromCall(SDNode *Node) {
1153 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1154 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1155 "Node doesn't have a token chain argument!");
1156 return FindCallStartFromCall(Node->getOperand(0).getNode());
1159 /// getTruncateTo8Bit - return an SDNode that implements a subreg based
1160 /// truncate of the specified operand to i8. This can be done with tablegen,
1161 /// except that this code uses MVT::Flag in a tricky way that happens to
1162 /// improve scheduling in some cases.
1163 SDNode *X86DAGToDAGISel::getTruncateTo8Bit(SDValue N0) {
1164 assert(!Subtarget->is64Bit() &&
1165 "getTruncateTo8Bit is only needed on x86-32!");
1166 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1168 // Ensure that the source register has an 8-bit subreg on 32-bit targets
1170 MVT N0VT = N0.getValueType();
1171 switch (N0VT.getSimpleVT()) {
1172 default: assert(0 && "Unknown truncate!");
1174 Opc = X86::MOV16to16_;
1177 Opc = X86::MOV32to32_;
1181 // The use of MVT::Flag here is not strictly accurate, but it helps
1182 // scheduling in some cases.
1183 N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
1184 return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1185 MVT::i8, N0, SRIdx, N0.getValue(1));
1188 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1189 SDValue Chain = Node->getOperand(0);
1190 SDValue In1 = Node->getOperand(1);
1191 SDValue In2L = Node->getOperand(2);
1192 SDValue In2H = Node->getOperand(3);
1193 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
1194 if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
1196 SDValue LSI = Node->getOperand(4); // MemOperand
1197 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
1198 return CurDAG->getTargetNode(Opc, MVT::i32, MVT::i32, MVT::Other, Ops, 8);
1201 SDNode *X86DAGToDAGISel::Select(SDValue N) {
1202 SDNode *Node = N.getNode();
1203 MVT NVT = Node->getValueType(0);
1205 unsigned Opcode = Node->getOpcode();
1208 DOUT << std::string(Indent, ' ') << "Selecting: ";
1209 DEBUG(Node->dump(CurDAG));
1214 if (Node->isMachineOpcode()) {
1216 DOUT << std::string(Indent-2, ' ') << "== ";
1217 DEBUG(Node->dump(CurDAG));
1221 return NULL; // Already selected.
1226 case X86ISD::GlobalBaseReg:
1227 return getGlobalBaseReg();
1229 case X86ISD::ATOMOR64_DAG:
1230 return SelectAtomic64(Node, X86::ATOMOR6432);
1231 case X86ISD::ATOMXOR64_DAG:
1232 return SelectAtomic64(Node, X86::ATOMXOR6432);
1233 case X86ISD::ATOMADD64_DAG:
1234 return SelectAtomic64(Node, X86::ATOMADD6432);
1235 case X86ISD::ATOMSUB64_DAG:
1236 return SelectAtomic64(Node, X86::ATOMSUB6432);
1237 case X86ISD::ATOMNAND64_DAG:
1238 return SelectAtomic64(Node, X86::ATOMNAND6432);
1239 case X86ISD::ATOMAND64_DAG:
1240 return SelectAtomic64(Node, X86::ATOMAND6432);
1241 case X86ISD::ATOMSWAP64_DAG:
1242 return SelectAtomic64(Node, X86::ATOMSWAP6432);
1244 case ISD::SMUL_LOHI:
1245 case ISD::UMUL_LOHI: {
1246 SDValue N0 = Node->getOperand(0);
1247 SDValue N1 = Node->getOperand(1);
1249 bool isSigned = Opcode == ISD::SMUL_LOHI;
1251 switch (NVT.getSimpleVT()) {
1252 default: assert(0 && "Unsupported VT!");
1253 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1254 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1255 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1256 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1259 switch (NVT.getSimpleVT()) {
1260 default: assert(0 && "Unsupported VT!");
1261 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1262 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1263 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1264 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1267 unsigned LoReg, HiReg;
1268 switch (NVT.getSimpleVT()) {
1269 default: assert(0 && "Unsupported VT!");
1270 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1271 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1272 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1273 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1276 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
1277 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1278 // multiplty is commmutative
1280 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
1285 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
1286 N0, SDValue()).getValue(1);
1289 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1291 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
1292 InFlag = SDValue(CNode, 1);
1293 // Update the chain.
1294 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1297 SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
1300 // Copy the low half of the result, if it is needed.
1301 if (!N.getValue(0).use_empty()) {
1302 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1303 LoReg, NVT, InFlag);
1304 InFlag = Result.getValue(2);
1305 ReplaceUses(N.getValue(0), Result);
1307 DOUT << std::string(Indent-2, ' ') << "=> ";
1308 DEBUG(Result.getNode()->dump(CurDAG));
1312 // Copy the high half of the result, if it is needed.
1313 if (!N.getValue(1).use_empty()) {
1315 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1316 // Prevent use of AH in a REX instruction by referencing AX instead.
1317 // Shift it down 8 bits.
1318 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1319 X86::AX, MVT::i16, InFlag);
1320 InFlag = Result.getValue(2);
1321 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
1322 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1323 // Then truncate it down to i8.
1324 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1325 Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1326 MVT::i8, Result, SRIdx), 0);
1328 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1329 HiReg, NVT, InFlag);
1330 InFlag = Result.getValue(2);
1332 ReplaceUses(N.getValue(1), Result);
1334 DOUT << std::string(Indent-2, ' ') << "=> ";
1335 DEBUG(Result.getNode()->dump(CurDAG));
1348 case ISD::UDIVREM: {
1349 SDValue N0 = Node->getOperand(0);
1350 SDValue N1 = Node->getOperand(1);
1352 bool isSigned = Opcode == ISD::SDIVREM;
1354 switch (NVT.getSimpleVT()) {
1355 default: assert(0 && "Unsupported VT!");
1356 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1357 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1358 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1359 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1362 switch (NVT.getSimpleVT()) {
1363 default: assert(0 && "Unsupported VT!");
1364 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1365 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1366 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1367 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1370 unsigned LoReg, HiReg;
1371 unsigned ClrOpcode, SExtOpcode;
1372 switch (NVT.getSimpleVT()) {
1373 default: assert(0 && "Unsupported VT!");
1375 LoReg = X86::AL; HiReg = X86::AH;
1377 SExtOpcode = X86::CBW;
1380 LoReg = X86::AX; HiReg = X86::DX;
1381 ClrOpcode = X86::MOV16r0;
1382 SExtOpcode = X86::CWD;
1385 LoReg = X86::EAX; HiReg = X86::EDX;
1386 ClrOpcode = X86::MOV32r0;
1387 SExtOpcode = X86::CDQ;
1390 LoReg = X86::RAX; HiReg = X86::RDX;
1391 ClrOpcode = X86::MOV64r0;
1392 SExtOpcode = X86::CQO;
1396 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
1397 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1398 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
1401 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
1402 // Special case for div8, just use a move with zero extension to AX to
1403 // clear the upper 8 bits (AH).
1404 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
1405 if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
1406 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
1408 SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
1410 Chain = Move.getValue(1);
1411 ReplaceUses(N0.getValue(1), Chain);
1414 SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
1415 Chain = CurDAG->getEntryNode();
1417 Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue());
1418 InFlag = Chain.getValue(1);
1421 CurDAG->getCopyToReg(CurDAG->getEntryNode(),
1422 LoReg, N0, SDValue()).getValue(1);
1423 if (isSigned && !signBitIsZero) {
1424 // Sign extend the low part into the high part.
1426 SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
1428 // Zero out the high part, effectively zero extending the input.
1429 SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
1430 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
1431 ClrNode, InFlag).getValue(1);
1436 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1438 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
1439 InFlag = SDValue(CNode, 1);
1440 // Update the chain.
1441 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1444 SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
1447 // Copy the division (low) result, if it is needed.
1448 if (!N.getValue(0).use_empty()) {
1449 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1450 LoReg, NVT, InFlag);
1451 InFlag = Result.getValue(2);
1452 ReplaceUses(N.getValue(0), Result);
1454 DOUT << std::string(Indent-2, ' ') << "=> ";
1455 DEBUG(Result.getNode()->dump(CurDAG));
1459 // Copy the remainder (high) result, if it is needed.
1460 if (!N.getValue(1).use_empty()) {
1462 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1463 // Prevent use of AH in a REX instruction by referencing AX instead.
1464 // Shift it down 8 bits.
1465 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1466 X86::AX, MVT::i16, InFlag);
1467 InFlag = Result.getValue(2);
1468 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
1469 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1470 // Then truncate it down to i8.
1471 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1472 Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1473 MVT::i8, Result, SRIdx), 0);
1475 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1476 HiReg, NVT, InFlag);
1477 InFlag = Result.getValue(2);
1479 ReplaceUses(N.getValue(1), Result);
1481 DOUT << std::string(Indent-2, ' ') << "=> ";
1482 DEBUG(Result.getNode()->dump(CurDAG));
1494 case ISD::SIGN_EXTEND_INREG: {
1495 MVT SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
1496 if (SVT == MVT::i8 && !Subtarget->is64Bit()) {
1497 SDValue N0 = Node->getOperand(0);
1499 SDValue TruncOp = SDValue(getTruncateTo8Bit(N0), 0);
1501 switch (NVT.getSimpleVT()) {
1502 default: assert(0 && "Unknown sign_extend_inreg!");
1504 Opc = X86::MOVSX16rr8;
1507 Opc = X86::MOVSX32rr8;
1511 SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);
1514 DOUT << std::string(Indent-2, ' ') << "=> ";
1515 DEBUG(TruncOp.getNode()->dump(CurDAG));
1517 DOUT << std::string(Indent-2, ' ') << "=> ";
1518 DEBUG(ResNode->dump(CurDAG));
1527 case ISD::TRUNCATE: {
1528 if (NVT == MVT::i8 && !Subtarget->is64Bit()) {
1529 SDValue Input = Node->getOperand(0);
1530 SDNode *ResNode = getTruncateTo8Bit(Input);
1533 DOUT << std::string(Indent-2, ' ') << "=> ";
1534 DEBUG(ResNode->dump(CurDAG));
1543 case ISD::DECLARE: {
1544 // Handle DECLARE nodes here because the second operand may have been
1545 // wrapped in X86ISD::Wrapper.
1546 SDValue Chain = Node->getOperand(0);
1547 SDValue N1 = Node->getOperand(1);
1548 SDValue N2 = Node->getOperand(2);
1549 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1552 if (N2.getOpcode() == ISD::ADD &&
1553 N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg)
1554 N2 = N2.getOperand(1);
1555 if (N2.getOpcode() != X86ISD::Wrapper)
1557 GlobalAddressSDNode *GVNode =
1558 dyn_cast<GlobalAddressSDNode>(N2.getOperand(0));
1561 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1562 TLI.getPointerTy());
1563 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(),
1564 TLI.getPointerTy());
1565 SDValue Ops[] = { Tmp1, Tmp2, Chain };
1566 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE,
1567 MVT::Other, Ops, 3);
1572 SDNode *ResNode = SelectCode(N);
1575 DOUT << std::string(Indent-2, ' ') << "=> ";
1576 if (ResNode == NULL || ResNode == N.getNode())
1577 DEBUG(N.getNode()->dump(CurDAG));
1579 DEBUG(ResNode->dump(CurDAG));
1587 bool X86DAGToDAGISel::
1588 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1589 std::vector<SDValue> &OutOps) {
1590 SDValue Op0, Op1, Op2, Op3;
1591 switch (ConstraintCode) {
1592 case 'o': // offsetable ??
1593 case 'v': // not offsetable ??
1594 default: return true;
1596 if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
1601 OutOps.push_back(Op0);
1602 OutOps.push_back(Op1);
1603 OutOps.push_back(Op2);
1604 OutOps.push_back(Op3);
1608 /// createX86ISelDag - This pass converts a legalized DAG into a
1609 /// X86-specific DAG, ready for instruction scheduling.
1611 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
1612 return new X86DAGToDAGISel(TM, Fast);