1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CFG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/Statistic.h"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
77 SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
84 bool hasBaseOrIndexReg() const {
85 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
88 /// isRIPRelative - Return true if this addressing mode is already RIP
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
104 dbgs() << "X86ISelAddressMode " << this << '\n';
105 dbgs() << "Base_Reg ";
106 if (Base_Reg.getNode() != 0)
107 Base_Reg.getNode()->dump();
110 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
111 << " Scale" << Scale << '\n'
113 if (IndexReg.getNode() != 0)
114 IndexReg.getNode()->dump();
117 dbgs() << " Disp " << Disp << '\n'
134 dbgs() << " JT" << JT << " Align" << Align << '\n';
140 //===--------------------------------------------------------------------===//
141 /// ISel - X86 specific code to select X86 machine instructions for
142 /// SelectionDAG operations.
144 class X86DAGToDAGISel : public SelectionDAGISel {
145 /// X86Lowering - This object fully describes how to lower LLVM code to an
146 /// X86-specific SelectionDAG.
147 const X86TargetLowering &X86Lowering;
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel),
160 X86Lowering(*tm.getTargetLowering()),
161 Subtarget(&tm.getSubtarget<X86Subtarget>()),
164 virtual const char *getPassName() const {
165 return "X86 DAG->DAG Instruction Selection";
168 virtual void EmitFunctionEntryCode();
170 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
172 virtual void PreprocessISelDAG();
174 inline bool immSext8(SDNode *N) const {
175 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
178 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
179 // sign extended field.
180 inline bool i64immSExt32(SDNode *N) const {
181 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
182 return (int64_t)v == (int32_t)v;
185 // Include the pieces autogenerated from the target description.
186 #include "X86GenDAGISel.inc"
189 SDNode *Select(SDNode *N);
190 SDNode *SelectGather(SDNode *N, unsigned Opc);
191 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
192 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
193 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT);
195 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
196 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
197 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
198 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
199 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
201 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
202 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
203 SDValue &Scale, SDValue &Index, SDValue &Disp,
205 bool SelectLEAAddr(SDValue N, SDValue &Base,
206 SDValue &Scale, SDValue &Index, SDValue &Disp,
208 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
209 SDValue &Scale, SDValue &Index, SDValue &Disp,
211 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
212 SDValue &Base, SDValue &Scale,
213 SDValue &Index, SDValue &Disp,
215 SDValue &NodeWithChain);
217 bool TryFoldLoad(SDNode *P, SDValue N,
218 SDValue &Base, SDValue &Scale,
219 SDValue &Index, SDValue &Disp,
222 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
223 /// inline asm expressions.
224 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
226 std::vector<SDValue> &OutOps);
228 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
230 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
231 SDValue &Scale, SDValue &Index,
232 SDValue &Disp, SDValue &Segment) {
233 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
234 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
236 Scale = getI8Imm(AM.Scale);
238 // These are 32-bit even in 64-bit mode since RIP relative offset
241 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(),
245 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
246 AM.Align, AM.Disp, AM.SymbolFlags);
248 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
249 else if (AM.JT != -1)
250 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
251 else if (AM.BlockAddr)
252 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
253 true, AM.SymbolFlags);
255 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
257 if (AM.Segment.getNode())
258 Segment = AM.Segment;
260 Segment = CurDAG->getRegister(0, MVT::i32);
263 /// getI8Imm - Return a target constant with the specified value, of type
265 inline SDValue getI8Imm(unsigned Imm) {
266 return CurDAG->getTargetConstant(Imm, MVT::i8);
269 /// getI32Imm - Return a target constant with the specified value, of type
271 inline SDValue getI32Imm(unsigned Imm) {
272 return CurDAG->getTargetConstant(Imm, MVT::i32);
275 /// getGlobalBaseReg - Return an SDNode that returns the value of
276 /// the global base register. Output instructions required to
277 /// initialize the global base register, if necessary.
279 SDNode *getGlobalBaseReg();
281 /// getTargetMachine - Return a reference to the TargetMachine, casted
282 /// to the target-specific type.
283 const X86TargetMachine &getTargetMachine() {
284 return static_cast<const X86TargetMachine &>(TM);
287 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
288 /// to the target-specific type.
289 const X86InstrInfo *getInstrInfo() {
290 return getTargetMachine().getInstrInfo();
297 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
298 if (OptLevel == CodeGenOpt::None) return false;
303 if (N.getOpcode() != ISD::LOAD)
306 // If N is a load, do additional profitability checks.
308 switch (U->getOpcode()) {
321 SDValue Op1 = U->getOperand(1);
323 // If the other operand is a 8-bit immediate we should fold the immediate
324 // instead. This reduces code size.
326 // movl 4(%esp), %eax
330 // addl 4(%esp), %eax
331 // The former is 2 bytes shorter. In case where the increment is 1, then
332 // the saving can be 4 bytes (by using incl %eax).
333 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
334 if (Imm->getAPIntValue().isSignedIntN(8))
337 // If the other operand is a TLS address, we should fold it instead.
340 // leal i@NTPOFF(%eax), %eax
342 // movl $i@NTPOFF, %eax
344 // if the block also has an access to a second TLS address this will save
346 // FIXME: This is probably also true for non TLS addresses.
347 if (Op1.getOpcode() == X86ISD::Wrapper) {
348 SDValue Val = Op1.getOperand(0);
349 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
359 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
360 /// load's chain operand and move load below the call's chain operand.
361 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
362 SDValue Call, SDValue OrigChain) {
363 SmallVector<SDValue, 8> Ops;
364 SDValue Chain = OrigChain.getOperand(0);
365 if (Chain.getNode() == Load.getNode())
366 Ops.push_back(Load.getOperand(0));
368 assert(Chain.getOpcode() == ISD::TokenFactor &&
369 "Unexpected chain operand");
370 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
371 if (Chain.getOperand(i).getNode() == Load.getNode())
372 Ops.push_back(Load.getOperand(0));
374 Ops.push_back(Chain.getOperand(i));
376 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
377 MVT::Other, &Ops[0], Ops.size());
379 Ops.push_back(NewChain);
381 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
382 Ops.push_back(OrigChain.getOperand(i));
383 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
384 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
385 Load.getOperand(1), Load.getOperand(2));
387 Ops.push_back(SDValue(Load.getNode(), 1));
388 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
389 Ops.push_back(Call.getOperand(i));
390 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size());
393 /// isCalleeLoad - Return true if call address is a load and it can be
394 /// moved below CALLSEQ_START and the chains leading up to the call.
395 /// Return the CALLSEQ_START by reference as a second output.
396 /// In the case of a tail call, there isn't a callseq node between the call
397 /// chain and the load.
398 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
399 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
401 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
404 LD->getAddressingMode() != ISD::UNINDEXED ||
405 LD->getExtensionType() != ISD::NON_EXTLOAD)
408 // Now let's find the callseq_start.
409 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
410 if (!Chain.hasOneUse())
412 Chain = Chain.getOperand(0);
415 if (!Chain.getNumOperands())
417 if (Chain.getOperand(0).getNode() == Callee.getNode())
419 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
420 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
421 Callee.getValue(1).hasOneUse())
426 void X86DAGToDAGISel::PreprocessISelDAG() {
427 // OptForSize is used in pattern predicates that isel is matching.
428 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
430 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
431 E = CurDAG->allnodes_end(); I != E; ) {
432 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
434 if (OptLevel != CodeGenOpt::None &&
435 (N->getOpcode() == X86ISD::CALL ||
436 N->getOpcode() == X86ISD::TC_RETURN)) {
437 /// Also try moving call address load from outside callseq_start to just
438 /// before the call to allow it to be folded.
456 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
457 SDValue Chain = N->getOperand(0);
458 SDValue Load = N->getOperand(1);
459 if (!isCalleeLoad(Load, Chain, HasCallSeq))
461 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
466 // Lower fpround and fpextend nodes that target the FP stack to be store and
467 // load to the stack. This is a gross hack. We would like to simply mark
468 // these as being illegal, but when we do that, legalize produces these when
469 // it expands calls, then expands these in the same legalize pass. We would
470 // like dag combine to be able to hack on these between the call expansion
471 // and the node legalization. As such this pass basically does "really
472 // late" legalization of these inline with the X86 isel pass.
473 // FIXME: This should only happen when not compiled with -O0.
474 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
477 EVT SrcVT = N->getOperand(0).getValueType();
478 EVT DstVT = N->getValueType(0);
480 // If any of the sources are vectors, no fp stack involved.
481 if (SrcVT.isVector() || DstVT.isVector())
484 // If the source and destination are SSE registers, then this is a legal
485 // conversion that should not be lowered.
486 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
487 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
488 if (SrcIsSSE && DstIsSSE)
491 if (!SrcIsSSE && !DstIsSSE) {
492 // If this is an FPStack extension, it is a noop.
493 if (N->getOpcode() == ISD::FP_EXTEND)
495 // If this is a value-preserving FPStack truncation, it is a noop.
496 if (N->getConstantOperandVal(1))
500 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
501 // FPStack has extload and truncstore. SSE can fold direct loads into other
502 // operations. Based on this, decide what we want to do.
504 if (N->getOpcode() == ISD::FP_ROUND)
505 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
507 MemVT = SrcIsSSE ? SrcVT : DstVT;
509 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
510 DebugLoc dl = N->getDebugLoc();
512 // FIXME: optimize the case where the src/dest is a load or store?
513 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
515 MemTmp, MachinePointerInfo(), MemVT,
517 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
518 MachinePointerInfo(),
519 MemVT, false, false, 0);
521 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
522 // extload we created. This will cause general havok on the dag because
523 // anything below the conversion could be folded into other existing nodes.
524 // To avoid invalidating 'I', back it up to the convert node.
526 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
528 // Now that we did that, the node is dead. Increment the iterator to the
529 // next node to process, then delete N.
531 CurDAG->DeleteNode(N);
536 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
537 /// the main function.
538 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
539 MachineFrameInfo *MFI) {
540 const TargetInstrInfo *TII = TM.getInstrInfo();
541 if (Subtarget->isTargetCygMing()) {
543 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
544 BuildMI(BB, DebugLoc(),
545 TII->get(CallOp)).addExternalSymbol("__main");
549 void X86DAGToDAGISel::EmitFunctionEntryCode() {
550 // If this is main, emit special code for main.
551 if (const Function *Fn = MF->getFunction())
552 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
553 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
556 static bool isDispSafeForFrameIndex(int64_t Val) {
557 // On 64-bit platforms, we can run into an issue where a frame index
558 // includes a displacement that, when added to the explicit displacement,
559 // will overflow the displacement field. Assuming that the frame index
560 // displacement fits into a 31-bit integer (which is only slightly more
561 // aggressive than the current fundamental assumption that it fits into
562 // a 32-bit integer), a 31-bit disp should always be safe.
563 return isInt<31>(Val);
566 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
567 X86ISelAddressMode &AM) {
568 int64_t Val = AM.Disp + Offset;
569 CodeModel::Model M = TM.getCodeModel();
570 if (Subtarget->is64Bit()) {
571 if (!X86::isOffsetSuitableForCodeModel(Val, M,
572 AM.hasSymbolicDisplacement()))
574 // In addition to the checks required for a register base, check that
575 // we do not try to use an unsafe Disp with a frame index.
576 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
577 !isDispSafeForFrameIndex(Val))
585 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
586 SDValue Address = N->getOperand(1);
588 // load gs:0 -> GS segment register.
589 // load fs:0 -> FS segment register.
591 // This optimization is valid because the GNU TLS model defines that
592 // gs:0 (or fs:0 on X86-64) contains its own address.
593 // For more information see http://people.redhat.com/drepper/tls.pdf
594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
595 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
596 Subtarget->isTargetLinux())
597 switch (N->getPointerInfo().getAddrSpace()) {
599 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
602 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
609 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
610 /// into an addressing mode. These wrap things that will resolve down into a
611 /// symbol reference. If no match is possible, this returns true, otherwise it
613 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
614 // If the addressing mode already has a symbol as the displacement, we can
615 // never match another symbol.
616 if (AM.hasSymbolicDisplacement())
619 SDValue N0 = N.getOperand(0);
620 CodeModel::Model M = TM.getCodeModel();
622 // Handle X86-64 rip-relative addresses. We check this before checking direct
623 // folding because RIP is preferable to non-RIP accesses.
624 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
625 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
626 // they cannot be folded into immediate fields.
627 // FIXME: This can be improved for kernel and other models?
628 (M == CodeModel::Small || M == CodeModel::Kernel)) {
629 // Base and index reg must be 0 in order to use %rip as base.
630 if (AM.hasBaseOrIndexReg())
632 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
633 X86ISelAddressMode Backup = AM;
634 AM.GV = G->getGlobal();
635 AM.SymbolFlags = G->getTargetFlags();
636 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
640 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
641 X86ISelAddressMode Backup = AM;
642 AM.CP = CP->getConstVal();
643 AM.Align = CP->getAlignment();
644 AM.SymbolFlags = CP->getTargetFlags();
645 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
649 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
650 AM.ES = S->getSymbol();
651 AM.SymbolFlags = S->getTargetFlags();
652 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
653 AM.JT = J->getIndex();
654 AM.SymbolFlags = J->getTargetFlags();
656 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
657 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
660 if (N.getOpcode() == X86ISD::WrapperRIP)
661 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
665 // Handle the case when globals fit in our immediate field: This is true for
666 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
667 // mode, this only applies to a non-RIP-relative computation.
668 if (!Subtarget->is64Bit() ||
669 M == CodeModel::Small || M == CodeModel::Kernel) {
670 assert(N.getOpcode() != X86ISD::WrapperRIP &&
671 "RIP-relative addressing already handled");
672 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
673 AM.GV = G->getGlobal();
674 AM.Disp += G->getOffset();
675 AM.SymbolFlags = G->getTargetFlags();
676 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
677 AM.CP = CP->getConstVal();
678 AM.Align = CP->getAlignment();
679 AM.Disp += CP->getOffset();
680 AM.SymbolFlags = CP->getTargetFlags();
681 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
682 AM.ES = S->getSymbol();
683 AM.SymbolFlags = S->getTargetFlags();
684 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
685 AM.JT = J->getIndex();
686 AM.SymbolFlags = J->getTargetFlags();
688 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
689 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
697 /// MatchAddress - Add the specified node to the specified addressing mode,
698 /// returning true if it cannot be done. This just pattern matches for the
700 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
701 if (MatchAddressRecursively(N, AM, 0))
704 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
705 // a smaller encoding and avoids a scaled-index.
707 AM.BaseType == X86ISelAddressMode::RegBase &&
708 AM.Base_Reg.getNode() == 0) {
709 AM.Base_Reg = AM.IndexReg;
713 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
714 // because it has a smaller encoding.
715 // TODO: Which other code models can use this?
716 if (TM.getCodeModel() == CodeModel::Small &&
717 Subtarget->is64Bit() &&
719 AM.BaseType == X86ISelAddressMode::RegBase &&
720 AM.Base_Reg.getNode() == 0 &&
721 AM.IndexReg.getNode() == 0 &&
722 AM.SymbolFlags == X86II::MO_NO_FLAG &&
723 AM.hasSymbolicDisplacement())
724 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
729 // Insert a node into the DAG at least before the Pos node's position. This
730 // will reposition the node as needed, and will assign it a node ID that is <=
731 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
732 // IDs! The selection DAG must no longer depend on their uniqueness when this
734 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
735 if (N.getNode()->getNodeId() == -1 ||
736 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
737 DAG.RepositionNode(Pos.getNode(), N.getNode());
738 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
742 // Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
743 // allows us to convert the shift and and into an h-register extract and
744 // a scaled index. Returns false if the simplification is performed.
745 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
747 SDValue Shift, SDValue X,
748 X86ISelAddressMode &AM) {
749 if (Shift.getOpcode() != ISD::SRL ||
750 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
754 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
755 if (ScaleLog <= 0 || ScaleLog >= 4 ||
756 Mask != (0xffu << ScaleLog))
759 EVT VT = N.getValueType();
760 DebugLoc DL = N.getDebugLoc();
761 SDValue Eight = DAG.getConstant(8, MVT::i8);
762 SDValue NewMask = DAG.getConstant(0xff, VT);
763 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
764 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
765 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
766 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
768 // Insert the new nodes into the topological ordering. We must do this in
769 // a valid topological ordering as nothing is going to go back and re-sort
770 // these nodes. We continually insert before 'N' in sequence as this is
771 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
772 // hierarchy left to express.
773 InsertDAGNode(DAG, N, Eight);
774 InsertDAGNode(DAG, N, Srl);
775 InsertDAGNode(DAG, N, NewMask);
776 InsertDAGNode(DAG, N, And);
777 InsertDAGNode(DAG, N, ShlCount);
778 InsertDAGNode(DAG, N, Shl);
779 DAG.ReplaceAllUsesWith(N, Shl);
781 AM.Scale = (1 << ScaleLog);
785 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
786 // allows us to fold the shift into this addressing mode. Returns false if the
787 // transform succeeded.
788 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
790 SDValue Shift, SDValue X,
791 X86ISelAddressMode &AM) {
792 if (Shift.getOpcode() != ISD::SHL ||
793 !isa<ConstantSDNode>(Shift.getOperand(1)))
796 // Not likely to be profitable if either the AND or SHIFT node has more
797 // than one use (unless all uses are for address computation). Besides,
798 // isel mechanism requires their node ids to be reused.
799 if (!N.hasOneUse() || !Shift.hasOneUse())
802 // Verify that the shift amount is something we can fold.
803 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
804 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
807 EVT VT = N.getValueType();
808 DebugLoc DL = N.getDebugLoc();
809 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
810 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
811 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
813 // Insert the new nodes into the topological ordering. We must do this in
814 // a valid topological ordering as nothing is going to go back and re-sort
815 // these nodes. We continually insert before 'N' in sequence as this is
816 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
817 // hierarchy left to express.
818 InsertDAGNode(DAG, N, NewMask);
819 InsertDAGNode(DAG, N, NewAnd);
820 InsertDAGNode(DAG, N, NewShift);
821 DAG.ReplaceAllUsesWith(N, NewShift);
823 AM.Scale = 1 << ShiftAmt;
824 AM.IndexReg = NewAnd;
828 // Implement some heroics to detect shifts of masked values where the mask can
829 // be replaced by extending the shift and undoing that in the addressing mode
830 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
831 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
832 // the addressing mode. This results in code such as:
834 // int f(short *y, int *lookup_table) {
836 // return *y + lookup_table[*y >> 11];
840 // movzwl (%rdi), %eax
843 // addl (%rsi,%rcx,4), %eax
846 // movzwl (%rdi), %eax
850 // addl (%rsi,%rcx), %eax
852 // Note that this function assumes the mask is provided as a mask *after* the
853 // value is shifted. The input chain may or may not match that, but computing
854 // such a mask is trivial.
855 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
857 SDValue Shift, SDValue X,
858 X86ISelAddressMode &AM) {
859 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
860 !isa<ConstantSDNode>(Shift.getOperand(1)))
863 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
864 unsigned MaskLZ = CountLeadingZeros_64(Mask);
865 unsigned MaskTZ = CountTrailingZeros_64(Mask);
867 // The amount of shift we're trying to fit into the addressing mode is taken
868 // from the trailing zeros of the mask.
869 unsigned AMShiftAmt = MaskTZ;
871 // There is nothing we can do here unless the mask is removing some bits.
872 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
873 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
875 // We also need to ensure that mask is a continuous run of bits.
876 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
878 // Scale the leading zero count down based on the actual size of the value.
879 // Also scale it down based on the size of the shift.
880 MaskLZ -= (64 - X.getValueSizeInBits()) + ShiftAmt;
882 // The final check is to ensure that any masked out high bits of X are
883 // already known to be zero. Otherwise, the mask has a semantic impact
884 // other than masking out a couple of low bits. Unfortunately, because of
885 // the mask, zero extensions will be removed from operands in some cases.
886 // This code works extra hard to look through extensions because we can
887 // replace them with zero extensions cheaply if necessary.
888 bool ReplacingAnyExtend = false;
889 if (X.getOpcode() == ISD::ANY_EXTEND) {
890 unsigned ExtendBits =
891 X.getValueSizeInBits() - X.getOperand(0).getValueSizeInBits();
892 // Assume that we'll replace the any-extend with a zero-extend, and
893 // narrow the search to the extended value.
895 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
896 ReplacingAnyExtend = true;
898 APInt MaskedHighBits = APInt::getHighBitsSet(X.getValueSizeInBits(),
900 APInt KnownZero, KnownOne;
901 DAG.ComputeMaskedBits(X, KnownZero, KnownOne);
902 if (MaskedHighBits != KnownZero) return true;
904 // We've identified a pattern that can be transformed into a single shift
905 // and an addressing mode. Make it so.
906 EVT VT = N.getValueType();
907 if (ReplacingAnyExtend) {
908 assert(X.getValueType() != VT);
909 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
910 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, X.getDebugLoc(), VT, X);
911 InsertDAGNode(DAG, N, NewX);
914 DebugLoc DL = N.getDebugLoc();
915 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
916 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
917 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
918 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
920 // Insert the new nodes into the topological ordering. We must do this in
921 // a valid topological ordering as nothing is going to go back and re-sort
922 // these nodes. We continually insert before 'N' in sequence as this is
923 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
924 // hierarchy left to express.
925 InsertDAGNode(DAG, N, NewSRLAmt);
926 InsertDAGNode(DAG, N, NewSRL);
927 InsertDAGNode(DAG, N, NewSHLAmt);
928 InsertDAGNode(DAG, N, NewSHL);
929 DAG.ReplaceAllUsesWith(N, NewSHL);
931 AM.Scale = 1 << AMShiftAmt;
932 AM.IndexReg = NewSRL;
936 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
938 DebugLoc dl = N.getDebugLoc();
940 dbgs() << "MatchAddress: ";
945 return MatchAddressBase(N, AM);
947 // If this is already a %rip relative address, we can only merge immediates
948 // into it. Instead of handling this in every case, we handle it here.
949 // RIP relative addressing: %rip + 32-bit displacement!
950 if (AM.isRIPRelative()) {
951 // FIXME: JumpTable and ExternalSymbol address currently don't like
952 // displacements. It isn't very important, but this should be fixed for
954 if (!AM.ES && AM.JT != -1) return true;
956 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
957 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
962 switch (N.getOpcode()) {
964 case ISD::Constant: {
965 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
966 if (!FoldOffsetIntoAddress(Val, AM))
971 case X86ISD::Wrapper:
972 case X86ISD::WrapperRIP:
973 if (!MatchWrapper(N, AM))
978 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
982 case ISD::FrameIndex:
983 if (AM.BaseType == X86ISelAddressMode::RegBase &&
984 AM.Base_Reg.getNode() == 0 &&
985 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
986 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
987 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
993 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
997 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
998 unsigned Val = CN->getZExtValue();
999 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1000 // that the base operand remains free for further matching. If
1001 // the base doesn't end up getting used, a post-processing step
1002 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1003 if (Val == 1 || Val == 2 || Val == 3) {
1004 AM.Scale = 1 << Val;
1005 SDValue ShVal = N.getNode()->getOperand(0);
1007 // Okay, we know that we have a scale by now. However, if the scaled
1008 // value is an add of something and a constant, we can fold the
1009 // constant into the disp field here.
1010 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1011 AM.IndexReg = ShVal.getNode()->getOperand(0);
1012 ConstantSDNode *AddVal =
1013 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1014 uint64_t Disp = AddVal->getSExtValue() << Val;
1015 if (!FoldOffsetIntoAddress(Disp, AM))
1019 AM.IndexReg = ShVal;
1026 // Scale must not be used already.
1027 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1029 SDValue And = N.getOperand(0);
1030 if (And.getOpcode() != ISD::AND) break;
1031 SDValue X = And.getOperand(0);
1033 // We only handle up to 64-bit values here as those are what matter for
1034 // addressing mode optimizations.
1035 if (X.getValueSizeInBits() > 64) break;
1037 // The mask used for the transform is expected to be post-shift, but we
1038 // found the shift first so just apply the shift to the mask before passing
1040 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1041 !isa<ConstantSDNode>(And.getOperand(1)))
1043 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1045 // Try to fold the mask and shift into the scale, and return false if we
1047 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1052 case ISD::SMUL_LOHI:
1053 case ISD::UMUL_LOHI:
1054 // A mul_lohi where we need the low part can be folded as a plain multiply.
1055 if (N.getResNo() != 0) break;
1058 case X86ISD::MUL_IMM:
1059 // X*[3,5,9] -> X+X*[2,4,8]
1060 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1061 AM.Base_Reg.getNode() == 0 &&
1062 AM.IndexReg.getNode() == 0) {
1064 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1065 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1066 CN->getZExtValue() == 9) {
1067 AM.Scale = unsigned(CN->getZExtValue())-1;
1069 SDValue MulVal = N.getNode()->getOperand(0);
1072 // Okay, we know that we have a scale by now. However, if the scaled
1073 // value is an add of something and a constant, we can fold the
1074 // constant into the disp field here.
1075 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1076 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1077 Reg = MulVal.getNode()->getOperand(0);
1078 ConstantSDNode *AddVal =
1079 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1080 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1081 if (FoldOffsetIntoAddress(Disp, AM))
1082 Reg = N.getNode()->getOperand(0);
1084 Reg = N.getNode()->getOperand(0);
1087 AM.IndexReg = AM.Base_Reg = Reg;
1094 // Given A-B, if A can be completely folded into the address and
1095 // the index field with the index field unused, use -B as the index.
1096 // This is a win if a has multiple parts that can be folded into
1097 // the address. Also, this saves a mov if the base register has
1098 // other uses, since it avoids a two-address sub instruction, however
1099 // it costs an additional mov if the index register has other uses.
1101 // Add an artificial use to this node so that we can keep track of
1102 // it if it gets CSE'd with a different node.
1103 HandleSDNode Handle(N);
1105 // Test if the LHS of the sub can be folded.
1106 X86ISelAddressMode Backup = AM;
1107 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1111 // Test if the index field is free for use.
1112 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1118 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1119 // If the RHS involves a register with multiple uses, this
1120 // transformation incurs an extra mov, due to the neg instruction
1121 // clobbering its operand.
1122 if (!RHS.getNode()->hasOneUse() ||
1123 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1124 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1125 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1126 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1127 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1129 // If the base is a register with multiple uses, this
1130 // transformation may save a mov.
1131 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1132 AM.Base_Reg.getNode() &&
1133 !AM.Base_Reg.getNode()->hasOneUse()) ||
1134 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1136 // If the folded LHS was interesting, this transformation saves
1137 // address arithmetic.
1138 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1139 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1140 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1142 // If it doesn't look like it may be an overall win, don't do it.
1148 // Ok, the transformation is legal and appears profitable. Go for it.
1149 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1150 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1154 // Insert the new nodes into the topological ordering.
1155 InsertDAGNode(*CurDAG, N, Zero);
1156 InsertDAGNode(*CurDAG, N, Neg);
1161 // Add an artificial use to this node so that we can keep track of
1162 // it if it gets CSE'd with a different node.
1163 HandleSDNode Handle(N);
1165 X86ISelAddressMode Backup = AM;
1166 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1167 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1171 // Try again after commuting the operands.
1172 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1173 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1177 // If we couldn't fold both operands into the address at the same time,
1178 // see if we can just put each operand into a register and fold at least
1180 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1181 !AM.Base_Reg.getNode() &&
1182 !AM.IndexReg.getNode()) {
1183 N = Handle.getValue();
1184 AM.Base_Reg = N.getOperand(0);
1185 AM.IndexReg = N.getOperand(1);
1189 N = Handle.getValue();
1194 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1195 if (CurDAG->isBaseWithConstantOffset(N)) {
1196 X86ISelAddressMode Backup = AM;
1197 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1199 // Start with the LHS as an addr mode.
1200 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1201 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1208 // Perform some heroic transforms on an and of a constant-count shift
1209 // with a constant to enable use of the scaled offset field.
1211 // Scale must not be used already.
1212 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1214 SDValue Shift = N.getOperand(0);
1215 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1216 SDValue X = Shift.getOperand(0);
1218 // We only handle up to 64-bit values here as those are what matter for
1219 // addressing mode optimizations.
1220 if (X.getValueSizeInBits() > 64) break;
1222 if (!isa<ConstantSDNode>(N.getOperand(1)))
1224 uint64_t Mask = N.getConstantOperandVal(1);
1226 // Try to fold the mask and shift into an extract and scale.
1227 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1230 // Try to fold the mask and shift directly into the scale.
1231 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1234 // Try to swap the mask and shift to place shifts which can be done as
1235 // a scale on the outside of the mask.
1236 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1242 return MatchAddressBase(N, AM);
1245 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1246 /// specified addressing mode without any further recursion.
1247 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1248 // Is the base register already occupied?
1249 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1250 // If so, check to see if the scale index register is set.
1251 if (AM.IndexReg.getNode() == 0) {
1257 // Otherwise, we cannot select it.
1261 // Default, generate it as a register.
1262 AM.BaseType = X86ISelAddressMode::RegBase;
1267 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1268 /// It returns the operands which make up the maximal addressing mode it can
1269 /// match by reference.
1271 /// Parent is the parent node of the addr operand that is being matched. It
1272 /// is always a load, store, atomic node, or null. It is only null when
1273 /// checking memory operands for inline asm nodes.
1274 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1275 SDValue &Scale, SDValue &Index,
1276 SDValue &Disp, SDValue &Segment) {
1277 X86ISelAddressMode AM;
1280 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1281 // that are not a MemSDNode, and thus don't have proper addrspace info.
1282 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1283 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1284 Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme
1285 unsigned AddrSpace =
1286 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1287 // AddrSpace 256 -> GS, 257 -> FS.
1288 if (AddrSpace == 256)
1289 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1290 if (AddrSpace == 257)
1291 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1294 if (MatchAddress(N, AM))
1297 EVT VT = N.getValueType();
1298 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1299 if (!AM.Base_Reg.getNode())
1300 AM.Base_Reg = CurDAG->getRegister(0, VT);
1303 if (!AM.IndexReg.getNode())
1304 AM.IndexReg = CurDAG->getRegister(0, VT);
1306 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1310 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1311 /// match a load whose top elements are either undef or zeros. The load flavor
1312 /// is derived from the type of N, which is either v4f32 or v2f64.
1315 /// PatternChainNode: this is the matched node that has a chain input and
1317 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1318 SDValue N, SDValue &Base,
1319 SDValue &Scale, SDValue &Index,
1320 SDValue &Disp, SDValue &Segment,
1321 SDValue &PatternNodeWithChain) {
1322 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1323 PatternNodeWithChain = N.getOperand(0);
1324 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1325 PatternNodeWithChain.hasOneUse() &&
1326 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1327 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1328 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1329 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1335 // Also handle the case where we explicitly require zeros in the top
1336 // elements. This is a vector shuffle from the zero vector.
1337 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1338 // Check to see if the top elements are all zeros (or bitcast of zeros).
1339 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1340 N.getOperand(0).getNode()->hasOneUse() &&
1341 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1342 N.getOperand(0).getOperand(0).hasOneUse() &&
1343 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1344 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1345 // Okay, this is a zero extending load. Fold it.
1346 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1347 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1349 PatternNodeWithChain = SDValue(LD, 0);
1356 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1357 /// mode it matches can be cost effectively emitted as an LEA instruction.
1358 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1359 SDValue &Base, SDValue &Scale,
1360 SDValue &Index, SDValue &Disp,
1362 X86ISelAddressMode AM;
1364 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1366 SDValue Copy = AM.Segment;
1367 SDValue T = CurDAG->getRegister(0, MVT::i32);
1369 if (MatchAddress(N, AM))
1371 assert (T == AM.Segment);
1374 EVT VT = N.getValueType();
1375 unsigned Complexity = 0;
1376 if (AM.BaseType == X86ISelAddressMode::RegBase)
1377 if (AM.Base_Reg.getNode())
1380 AM.Base_Reg = CurDAG->getRegister(0, VT);
1381 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1384 if (AM.IndexReg.getNode())
1387 AM.IndexReg = CurDAG->getRegister(0, VT);
1389 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1394 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1395 // to a LEA. This is determined with some expermentation but is by no means
1396 // optimal (especially for code size consideration). LEA is nice because of
1397 // its three-address nature. Tweak the cost function again when we can run
1398 // convertToThreeAddress() at register allocation time.
1399 if (AM.hasSymbolicDisplacement()) {
1400 // For X86-64, we should always use lea to materialize RIP relative
1402 if (Subtarget->is64Bit())
1408 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1411 // If it isn't worth using an LEA, reject it.
1412 if (Complexity <= 2)
1415 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1419 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1420 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1421 SDValue &Scale, SDValue &Index,
1422 SDValue &Disp, SDValue &Segment) {
1423 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1424 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1426 X86ISelAddressMode AM;
1427 AM.GV = GA->getGlobal();
1428 AM.Disp += GA->getOffset();
1429 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1430 AM.SymbolFlags = GA->getTargetFlags();
1432 if (N.getValueType() == MVT::i32) {
1434 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1436 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1439 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1444 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1445 SDValue &Base, SDValue &Scale,
1446 SDValue &Index, SDValue &Disp,
1448 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1449 !IsProfitableToFold(N, P, P) ||
1450 !IsLegalToFold(N, P, P, OptLevel))
1453 return SelectAddr(N.getNode(),
1454 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1457 /// getGlobalBaseReg - Return an SDNode that returns the value of
1458 /// the global base register. Output instructions required to
1459 /// initialize the global base register, if necessary.
1461 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1462 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1463 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1466 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1467 SDValue Chain = Node->getOperand(0);
1468 SDValue In1 = Node->getOperand(1);
1469 SDValue In2L = Node->getOperand(2);
1470 SDValue In2H = Node->getOperand(3);
1471 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1472 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1474 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1475 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1476 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1477 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1478 MVT::i32, MVT::i32, MVT::Other, Ops,
1479 array_lengthof(Ops));
1480 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1484 // FIXME: Figure out some way to unify this with the 'or' and other code
1486 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1487 if (Node->hasAnyUseOfValue(0))
1490 // Optimize common patterns for __sync_add_and_fetch and
1491 // __sync_sub_and_fetch where the result is not used. This allows us
1492 // to use "lock" version of add, sub, inc, dec instructions.
1493 // FIXME: Do not use special instructions but instead add the "lock"
1494 // prefix to the target node somehow. The extra information will then be
1495 // transferred to machine instruction and it denotes the prefix.
1496 SDValue Chain = Node->getOperand(0);
1497 SDValue Ptr = Node->getOperand(1);
1498 SDValue Val = Node->getOperand(2);
1499 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1500 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1503 bool isInc = false, isDec = false, isSub = false, isCN = false;
1504 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1505 if (CN && CN->getSExtValue() == (int32_t)CN->getSExtValue()) {
1507 int64_t CNVal = CN->getSExtValue();
1510 else if (CNVal == -1)
1512 else if (CNVal >= 0)
1513 Val = CurDAG->getTargetConstant(CNVal, NVT);
1516 Val = CurDAG->getTargetConstant(-CNVal, NVT);
1518 } else if (Val.hasOneUse() &&
1519 Val.getOpcode() == ISD::SUB &&
1520 X86::isZeroNode(Val.getOperand(0))) {
1522 Val = Val.getOperand(1);
1525 DebugLoc dl = Node->getDebugLoc();
1527 switch (NVT.getSimpleVT().SimpleTy) {
1531 Opc = X86::LOCK_INC8m;
1533 Opc = X86::LOCK_DEC8m;
1536 Opc = X86::LOCK_SUB8mi;
1538 Opc = X86::LOCK_SUB8mr;
1541 Opc = X86::LOCK_ADD8mi;
1543 Opc = X86::LOCK_ADD8mr;
1548 Opc = X86::LOCK_INC16m;
1550 Opc = X86::LOCK_DEC16m;
1553 if (immSext8(Val.getNode()))
1554 Opc = X86::LOCK_SUB16mi8;
1556 Opc = X86::LOCK_SUB16mi;
1558 Opc = X86::LOCK_SUB16mr;
1561 if (immSext8(Val.getNode()))
1562 Opc = X86::LOCK_ADD16mi8;
1564 Opc = X86::LOCK_ADD16mi;
1566 Opc = X86::LOCK_ADD16mr;
1571 Opc = X86::LOCK_INC32m;
1573 Opc = X86::LOCK_DEC32m;
1576 if (immSext8(Val.getNode()))
1577 Opc = X86::LOCK_SUB32mi8;
1579 Opc = X86::LOCK_SUB32mi;
1581 Opc = X86::LOCK_SUB32mr;
1584 if (immSext8(Val.getNode()))
1585 Opc = X86::LOCK_ADD32mi8;
1587 Opc = X86::LOCK_ADD32mi;
1589 Opc = X86::LOCK_ADD32mr;
1594 Opc = X86::LOCK_INC64m;
1596 Opc = X86::LOCK_DEC64m;
1598 Opc = X86::LOCK_SUB64mr;
1600 if (immSext8(Val.getNode()))
1601 Opc = X86::LOCK_SUB64mi8;
1602 else if (i64immSExt32(Val.getNode()))
1603 Opc = X86::LOCK_SUB64mi32;
1606 Opc = X86::LOCK_ADD64mr;
1608 if (immSext8(Val.getNode()))
1609 Opc = X86::LOCK_ADD64mi8;
1610 else if (i64immSExt32(Val.getNode()))
1611 Opc = X86::LOCK_ADD64mi32;
1617 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1619 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1620 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1621 if (isInc || isDec) {
1622 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1623 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
1624 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1625 SDValue RetVals[] = { Undef, Ret };
1626 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1628 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1629 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1630 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1631 SDValue RetVals[] = { Undef, Ret };
1632 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1658 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1682 X86::LOCK_AND64mi32,
1695 X86::LOCK_XOR64mi32,
1700 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
1701 if (Node->hasAnyUseOfValue(0))
1704 // Optimize common patterns for __sync_or_and_fetch and similar arith
1705 // operations where the result is not used. This allows us to use the "lock"
1706 // version of the arithmetic instruction.
1707 // FIXME: Same as for 'add' and 'sub', try to merge those down here.
1708 SDValue Chain = Node->getOperand(0);
1709 SDValue Ptr = Node->getOperand(1);
1710 SDValue Val = Node->getOperand(2);
1711 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1712 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1715 // Which index into the table.
1717 switch (Node->getOpcode()) {
1718 case ISD::ATOMIC_LOAD_OR:
1721 case ISD::ATOMIC_LOAD_AND:
1724 case ISD::ATOMIC_LOAD_XOR:
1732 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1733 if (CN && (int32_t)CN->getSExtValue() == CN->getSExtValue()) {
1735 Val = CurDAG->getTargetConstant(CN->getSExtValue(), NVT);
1739 switch (NVT.getSimpleVT().SimpleTy) {
1743 Opc = AtomicOpcTbl[Op][ConstantI8];
1745 Opc = AtomicOpcTbl[Op][I8];
1749 if (immSext8(Val.getNode()))
1750 Opc = AtomicOpcTbl[Op][SextConstantI16];
1752 Opc = AtomicOpcTbl[Op][ConstantI16];
1754 Opc = AtomicOpcTbl[Op][I16];
1758 if (immSext8(Val.getNode()))
1759 Opc = AtomicOpcTbl[Op][SextConstantI32];
1761 Opc = AtomicOpcTbl[Op][ConstantI32];
1763 Opc = AtomicOpcTbl[Op][I32];
1766 Opc = AtomicOpcTbl[Op][I64];
1768 if (immSext8(Val.getNode()))
1769 Opc = AtomicOpcTbl[Op][SextConstantI64];
1770 else if (i64immSExt32(Val.getNode()))
1771 Opc = AtomicOpcTbl[Op][ConstantI64];
1776 assert(Opc != 0 && "Invalid arith lock transform!");
1778 DebugLoc dl = Node->getDebugLoc();
1779 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1781 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1782 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1783 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1784 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1785 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1786 SDValue RetVals[] = { Undef, Ret };
1787 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1790 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1791 /// any uses which require the SF or OF bits to be accurate.
1792 static bool HasNoSignedComparisonUses(SDNode *N) {
1793 // Examine each user of the node.
1794 for (SDNode::use_iterator UI = N->use_begin(),
1795 UE = N->use_end(); UI != UE; ++UI) {
1796 // Only examine CopyToReg uses.
1797 if (UI->getOpcode() != ISD::CopyToReg)
1799 // Only examine CopyToReg uses that copy to EFLAGS.
1800 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1803 // Examine each user of the CopyToReg use.
1804 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1805 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1806 // Only examine the Flag result.
1807 if (FlagUI.getUse().getResNo() != 1) continue;
1808 // Anything unusual: assume conservatively.
1809 if (!FlagUI->isMachineOpcode()) return false;
1810 // Examine the opcode of the user.
1811 switch (FlagUI->getMachineOpcode()) {
1812 // These comparisons don't treat the most significant bit specially.
1813 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1814 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1815 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1816 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1817 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1818 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1819 case X86::CMOVA16rr: case X86::CMOVA16rm:
1820 case X86::CMOVA32rr: case X86::CMOVA32rm:
1821 case X86::CMOVA64rr: case X86::CMOVA64rm:
1822 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1823 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1824 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1825 case X86::CMOVB16rr: case X86::CMOVB16rm:
1826 case X86::CMOVB32rr: case X86::CMOVB32rm:
1827 case X86::CMOVB64rr: case X86::CMOVB64rm:
1828 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1829 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1830 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1831 case X86::CMOVE16rr: case X86::CMOVE16rm:
1832 case X86::CMOVE32rr: case X86::CMOVE32rm:
1833 case X86::CMOVE64rr: case X86::CMOVE64rm:
1834 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1835 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1836 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1837 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1838 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1839 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1840 case X86::CMOVP16rr: case X86::CMOVP16rm:
1841 case X86::CMOVP32rr: case X86::CMOVP32rm:
1842 case X86::CMOVP64rr: case X86::CMOVP64rm:
1844 // Anything else: assume conservatively.
1845 default: return false;
1852 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1853 /// is suitable for doing the {load; increment or decrement; store} to modify
1855 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1856 SDValue StoredVal, SelectionDAG *CurDAG,
1857 LoadSDNode* &LoadNode, SDValue &InputChain) {
1859 // is the value stored the result of a DEC or INC?
1860 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1862 // is the stored value result 0 of the load?
1863 if (StoredVal.getResNo() != 0) return false;
1865 // are there other uses of the loaded value than the inc or dec?
1866 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1868 // is the store non-extending and non-indexed?
1869 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1872 SDValue Load = StoredVal->getOperand(0);
1873 // Is the stored value a non-extending and non-indexed load?
1874 if (!ISD::isNormalLoad(Load.getNode())) return false;
1876 // Return LoadNode by reference.
1877 LoadNode = cast<LoadSDNode>(Load);
1878 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1879 EVT LdVT = LoadNode->getMemoryVT();
1880 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1884 // Is store the only read of the loaded value?
1885 if (!Load.hasOneUse())
1888 // Is the address of the store the same as the load?
1889 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1890 LoadNode->getOffset() != StoreNode->getOffset())
1893 // Check if the chain is produced by the load or is a TokenFactor with
1894 // the load output chain as an operand. Return InputChain by reference.
1895 SDValue Chain = StoreNode->getChain();
1897 bool ChainCheck = false;
1898 if (Chain == Load.getValue(1)) {
1900 InputChain = LoadNode->getChain();
1901 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1902 SmallVector<SDValue, 4> ChainOps;
1903 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1904 SDValue Op = Chain.getOperand(i);
1905 if (Op == Load.getValue(1)) {
1910 // Make sure using Op as part of the chain would not cause a cycle here.
1911 // In theory, we could check whether the chain node is a predecessor of
1912 // the load. But that can be very expensive. Instead visit the uses and
1913 // make sure they all have smaller node id than the load.
1914 int LoadId = LoadNode->getNodeId();
1915 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1916 UE = UI->use_end(); UI != UE; ++UI) {
1917 if (UI.getUse().getResNo() != 0)
1919 if (UI->getNodeId() > LoadId)
1923 ChainOps.push_back(Op);
1927 // Make a new TokenFactor with all the other input chains except
1929 InputChain = CurDAG->getNode(ISD::TokenFactor, Chain.getDebugLoc(),
1930 MVT::Other, &ChainOps[0], ChainOps.size());
1938 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
1939 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
1940 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
1941 if (Opc == X86ISD::DEC) {
1942 if (LdVT == MVT::i64) return X86::DEC64m;
1943 if (LdVT == MVT::i32) return X86::DEC32m;
1944 if (LdVT == MVT::i16) return X86::DEC16m;
1945 if (LdVT == MVT::i8) return X86::DEC8m;
1947 assert(Opc == X86ISD::INC && "unrecognized opcode");
1948 if (LdVT == MVT::i64) return X86::INC64m;
1949 if (LdVT == MVT::i32) return X86::INC32m;
1950 if (LdVT == MVT::i16) return X86::INC16m;
1951 if (LdVT == MVT::i8) return X86::INC8m;
1953 llvm_unreachable("unrecognized size for LdVT");
1956 /// SelectGather - Customized ISel for GATHER operations.
1958 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
1959 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
1960 SDValue Chain = Node->getOperand(0);
1961 SDValue VSrc = Node->getOperand(2);
1962 SDValue Base = Node->getOperand(3);
1963 SDValue VIdx = Node->getOperand(4);
1964 SDValue VMask = Node->getOperand(5);
1965 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
1969 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
1972 // Memory Operands: Base, Scale, Index, Disp, Segment
1973 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
1974 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
1975 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
1976 Disp, Segment, VMask, Chain};
1977 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1978 VTs, Ops, array_lengthof(Ops));
1979 // Node has 2 outputs: VDst and MVT::Other.
1980 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
1981 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
1983 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
1984 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
1988 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
1989 EVT NVT = Node->getValueType(0);
1991 unsigned Opcode = Node->getOpcode();
1992 DebugLoc dl = Node->getDebugLoc();
1994 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
1996 if (Node->isMachineOpcode()) {
1997 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
1998 return NULL; // Already selected.
2003 case ISD::INTRINSIC_W_CHAIN: {
2004 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2007 case Intrinsic::x86_avx2_gather_d_pd:
2008 case Intrinsic::x86_avx2_gather_d_pd_256:
2009 case Intrinsic::x86_avx2_gather_q_pd:
2010 case Intrinsic::x86_avx2_gather_q_pd_256:
2011 case Intrinsic::x86_avx2_gather_d_ps:
2012 case Intrinsic::x86_avx2_gather_d_ps_256:
2013 case Intrinsic::x86_avx2_gather_q_ps:
2014 case Intrinsic::x86_avx2_gather_q_ps_256:
2015 case Intrinsic::x86_avx2_gather_d_q:
2016 case Intrinsic::x86_avx2_gather_d_q_256:
2017 case Intrinsic::x86_avx2_gather_q_q:
2018 case Intrinsic::x86_avx2_gather_q_q_256:
2019 case Intrinsic::x86_avx2_gather_d_d:
2020 case Intrinsic::x86_avx2_gather_d_d_256:
2021 case Intrinsic::x86_avx2_gather_q_d:
2022 case Intrinsic::x86_avx2_gather_q_d_256: {
2025 default: llvm_unreachable("Impossible intrinsic");
2026 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2027 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2028 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2029 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2030 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2031 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2032 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2033 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2034 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2035 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2036 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2037 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2038 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2039 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2040 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2041 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2043 SDNode *RetVal = SelectGather(Node, Opc);
2045 // We already called ReplaceUses inside SelectGather.
2052 case X86ISD::GlobalBaseReg:
2053 return getGlobalBaseReg();
2056 case X86ISD::ATOMOR64_DAG:
2057 case X86ISD::ATOMXOR64_DAG:
2058 case X86ISD::ATOMADD64_DAG:
2059 case X86ISD::ATOMSUB64_DAG:
2060 case X86ISD::ATOMNAND64_DAG:
2061 case X86ISD::ATOMAND64_DAG:
2062 case X86ISD::ATOMSWAP64_DAG: {
2065 default: llvm_unreachable("Impossible intrinsic");
2066 case X86ISD::ATOMOR64_DAG: Opc = X86::ATOMOR6432; break;
2067 case X86ISD::ATOMXOR64_DAG: Opc = X86::ATOMXOR6432; break;
2068 case X86ISD::ATOMADD64_DAG: Opc = X86::ATOMADD6432; break;
2069 case X86ISD::ATOMSUB64_DAG: Opc = X86::ATOMSUB6432; break;
2070 case X86ISD::ATOMNAND64_DAG: Opc = X86::ATOMNAND6432; break;
2071 case X86ISD::ATOMAND64_DAG: Opc = X86::ATOMAND6432; break;
2072 case X86ISD::ATOMSWAP64_DAG: Opc = X86::ATOMSWAP6432; break;
2074 SDNode *RetVal = SelectAtomic64(Node, Opc);
2080 case ISD::ATOMIC_LOAD_ADD: {
2081 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
2086 case ISD::ATOMIC_LOAD_XOR:
2087 case ISD::ATOMIC_LOAD_AND:
2088 case ISD::ATOMIC_LOAD_OR: {
2089 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2097 // For operations of the form (x << C1) op C2, check if we can use a smaller
2098 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2099 SDValue N0 = Node->getOperand(0);
2100 SDValue N1 = Node->getOperand(1);
2102 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2105 // i8 is unshrinkable, i16 should be promoted to i32.
2106 if (NVT != MVT::i32 && NVT != MVT::i64)
2109 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2110 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2111 if (!Cst || !ShlCst)
2114 int64_t Val = Cst->getSExtValue();
2115 uint64_t ShlVal = ShlCst->getZExtValue();
2117 // Make sure that we don't change the operation by removing bits.
2118 // This only matters for OR and XOR, AND is unaffected.
2119 if (Opcode != ISD::AND && ((Val >> ShlVal) << ShlVal) != Val)
2122 unsigned ShlOp, Op = 0;
2125 // Check the minimum bitwidth for the new constant.
2126 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2127 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2128 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2129 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2131 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2134 // Bail if there is no smaller encoding.
2138 switch (NVT.getSimpleVT().SimpleTy) {
2139 default: llvm_unreachable("Unsupported VT!");
2141 assert(CstVT == MVT::i8);
2142 ShlOp = X86::SHL32ri;
2145 case ISD::AND: Op = X86::AND32ri8; break;
2146 case ISD::OR: Op = X86::OR32ri8; break;
2147 case ISD::XOR: Op = X86::XOR32ri8; break;
2151 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2152 ShlOp = X86::SHL64ri;
2155 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2156 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2157 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2162 // Emit the smaller op and the shift.
2163 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2164 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2165 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2168 case X86ISD::UMUL: {
2169 SDValue N0 = Node->getOperand(0);
2170 SDValue N1 = Node->getOperand(1);
2173 switch (NVT.getSimpleVT().SimpleTy) {
2174 default: llvm_unreachable("Unsupported VT!");
2175 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2176 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2177 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2178 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2181 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2182 N0, SDValue()).getValue(1);
2184 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2185 SDValue Ops[] = {N1, InFlag};
2186 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops, 2);
2188 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2189 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2190 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2194 case ISD::SMUL_LOHI:
2195 case ISD::UMUL_LOHI: {
2196 SDValue N0 = Node->getOperand(0);
2197 SDValue N1 = Node->getOperand(1);
2199 bool isSigned = Opcode == ISD::SMUL_LOHI;
2201 switch (NVT.getSimpleVT().SimpleTy) {
2202 default: llvm_unreachable("Unsupported VT!");
2203 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2204 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2205 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
2206 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
2209 switch (NVT.getSimpleVT().SimpleTy) {
2210 default: llvm_unreachable("Unsupported VT!");
2211 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2212 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2213 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2214 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2218 unsigned LoReg, HiReg;
2219 switch (NVT.getSimpleVT().SimpleTy) {
2220 default: llvm_unreachable("Unsupported VT!");
2221 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
2222 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
2223 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
2224 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
2227 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2228 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2229 // Multiply is commmutative.
2231 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2236 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2237 N0, SDValue()).getValue(1);
2240 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2243 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
2244 array_lengthof(Ops));
2245 InFlag = SDValue(CNode, 1);
2247 // Update the chain.
2248 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2250 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag);
2251 InFlag = SDValue(CNode, 0);
2254 // Prevent use of AH in a REX instruction by referencing AX instead.
2255 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2256 !SDValue(Node, 1).use_empty()) {
2257 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2258 X86::AX, MVT::i16, InFlag);
2259 InFlag = Result.getValue(2);
2260 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2262 if (!SDValue(Node, 0).use_empty())
2263 ReplaceUses(SDValue(Node, 1),
2264 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2266 // Shift AX down 8 bits.
2267 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2269 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2270 // Then truncate it down to i8.
2271 ReplaceUses(SDValue(Node, 1),
2272 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2274 // Copy the low half of the result, if it is needed.
2275 if (!SDValue(Node, 0).use_empty()) {
2276 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2277 LoReg, NVT, InFlag);
2278 InFlag = Result.getValue(2);
2279 ReplaceUses(SDValue(Node, 0), Result);
2280 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2282 // Copy the high half of the result, if it is needed.
2283 if (!SDValue(Node, 1).use_empty()) {
2284 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2285 HiReg, NVT, InFlag);
2286 InFlag = Result.getValue(2);
2287 ReplaceUses(SDValue(Node, 1), Result);
2288 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2295 case ISD::UDIVREM: {
2296 SDValue N0 = Node->getOperand(0);
2297 SDValue N1 = Node->getOperand(1);
2299 bool isSigned = Opcode == ISD::SDIVREM;
2301 switch (NVT.getSimpleVT().SimpleTy) {
2302 default: llvm_unreachable("Unsupported VT!");
2303 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2304 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2305 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2306 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2309 switch (NVT.getSimpleVT().SimpleTy) {
2310 default: llvm_unreachable("Unsupported VT!");
2311 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2312 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2313 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2314 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2318 unsigned LoReg, HiReg, ClrReg;
2319 unsigned ClrOpcode, SExtOpcode;
2320 switch (NVT.getSimpleVT().SimpleTy) {
2321 default: llvm_unreachable("Unsupported VT!");
2323 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2325 SExtOpcode = X86::CBW;
2328 LoReg = X86::AX; HiReg = X86::DX;
2329 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
2330 SExtOpcode = X86::CWD;
2333 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2334 ClrOpcode = X86::MOV32r0;
2335 SExtOpcode = X86::CDQ;
2338 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2339 ClrOpcode = X86::MOV64r0;
2340 SExtOpcode = X86::CQO;
2344 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2345 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2346 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2349 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2350 // Special case for div8, just use a move with zero extension to AX to
2351 // clear the upper 8 bits (AH).
2352 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2353 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2354 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2356 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2358 array_lengthof(Ops)), 0);
2359 Chain = Move.getValue(1);
2360 ReplaceUses(N0.getValue(1), Chain);
2363 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2364 Chain = CurDAG->getEntryNode();
2366 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2367 InFlag = Chain.getValue(1);
2370 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2371 LoReg, N0, SDValue()).getValue(1);
2372 if (isSigned && !signBitIsZero) {
2373 // Sign extend the low part into the high part.
2375 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2377 // Zero out the high part, effectively zero extending the input.
2379 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
2380 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2381 ClrNode, InFlag).getValue(1);
2386 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2389 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
2390 array_lengthof(Ops));
2391 InFlag = SDValue(CNode, 1);
2392 // Update the chain.
2393 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2396 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2399 // Prevent use of AH in a REX instruction by referencing AX instead.
2400 // Shift it down 8 bits.
2401 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2402 !SDValue(Node, 1).use_empty()) {
2403 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2404 X86::AX, MVT::i16, InFlag);
2405 InFlag = Result.getValue(2);
2407 // If we also need AL (the quotient), get it by extracting a subreg from
2408 // Result. The fast register allocator does not like multiple CopyFromReg
2409 // nodes using aliasing registers.
2410 if (!SDValue(Node, 0).use_empty())
2411 ReplaceUses(SDValue(Node, 0),
2412 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2414 // Shift AX right by 8 bits instead of using AH.
2415 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2417 CurDAG->getTargetConstant(8, MVT::i8)),
2419 ReplaceUses(SDValue(Node, 1),
2420 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2422 // Copy the division (low) result, if it is needed.
2423 if (!SDValue(Node, 0).use_empty()) {
2424 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2425 LoReg, NVT, InFlag);
2426 InFlag = Result.getValue(2);
2427 ReplaceUses(SDValue(Node, 0), Result);
2428 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2430 // Copy the remainder (high) result, if it is needed.
2431 if (!SDValue(Node, 1).use_empty()) {
2432 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2433 HiReg, NVT, InFlag);
2434 InFlag = Result.getValue(2);
2435 ReplaceUses(SDValue(Node, 1), Result);
2436 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2442 SDValue N0 = Node->getOperand(0);
2443 SDValue N1 = Node->getOperand(1);
2445 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2446 // use a smaller encoding.
2447 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2448 HasNoSignedComparisonUses(Node))
2449 // Look past the truncate if CMP is the only use of it.
2450 N0 = N0.getOperand(0);
2451 if ((N0.getNode()->getOpcode() == ISD::AND ||
2452 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2453 N0.getNode()->hasOneUse() &&
2454 N0.getValueType() != MVT::i8 &&
2455 X86::isZeroNode(N1)) {
2456 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2459 // For example, convert "testl %eax, $8" to "testb %al, $8"
2460 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2461 (!(C->getZExtValue() & 0x80) ||
2462 HasNoSignedComparisonUses(Node))) {
2463 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2464 SDValue Reg = N0.getNode()->getOperand(0);
2466 // On x86-32, only the ABCD registers have 8-bit subregisters.
2467 if (!Subtarget->is64Bit()) {
2468 const TargetRegisterClass *TRC;
2469 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2470 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2471 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2472 default: llvm_unreachable("Unsupported TEST operand type!");
2474 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2475 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2476 Reg.getValueType(), Reg, RC), 0);
2479 // Extract the l-register.
2480 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2484 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
2487 // For example, "testl %eax, $2048" to "testb %ah, $8".
2488 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2489 (!(C->getZExtValue() & 0x8000) ||
2490 HasNoSignedComparisonUses(Node))) {
2491 // Shift the immediate right by 8 bits.
2492 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2494 SDValue Reg = N0.getNode()->getOperand(0);
2496 // Put the value in an ABCD register.
2497 const TargetRegisterClass *TRC;
2498 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2499 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2500 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2501 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2502 default: llvm_unreachable("Unsupported TEST operand type!");
2504 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2505 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2506 Reg.getValueType(), Reg, RC), 0);
2508 // Extract the h-register.
2509 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2512 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2513 // target GR8_NOREX registers, so make sure the register class is
2515 return CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl, MVT::i32,
2516 Subreg, ShiftedImm);
2519 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2520 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2521 N0.getValueType() != MVT::i16 &&
2522 (!(C->getZExtValue() & 0x8000) ||
2523 HasNoSignedComparisonUses(Node))) {
2524 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2525 SDValue Reg = N0.getNode()->getOperand(0);
2527 // Extract the 16-bit subregister.
2528 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2532 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
2535 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2536 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2537 N0.getValueType() == MVT::i64 &&
2538 (!(C->getZExtValue() & 0x80000000) ||
2539 HasNoSignedComparisonUses(Node))) {
2540 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2541 SDValue Reg = N0.getNode()->getOperand(0);
2543 // Extract the 32-bit subregister.
2544 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2548 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
2554 // Change a chain of {load; incr or dec; store} of the same value into
2555 // a simple increment or decrement through memory of that value, if the
2556 // uses of the modified value and its address are suitable.
2557 // The DEC64m tablegen pattern is currently not able to match the case where
2558 // the EFLAGS on the original DEC are used. (This also applies to
2559 // {INC,DEC}X{64,32,16,8}.)
2560 // We'll need to improve tablegen to allow flags to be transferred from a
2561 // node in the pattern to the result node. probably with a new keyword
2562 // for example, we have this
2563 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2564 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2565 // (implicit EFLAGS)]>;
2566 // but maybe need something like this
2567 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2568 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2569 // (transferrable EFLAGS)]>;
2571 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2572 SDValue StoredVal = StoreNode->getOperand(1);
2573 unsigned Opc = StoredVal->getOpcode();
2575 LoadSDNode *LoadNode = 0;
2577 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2578 LoadNode, InputChain))
2581 SDValue Base, Scale, Index, Disp, Segment;
2582 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2583 Base, Scale, Index, Disp, Segment))
2586 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2587 MemOp[0] = StoreNode->getMemOperand();
2588 MemOp[1] = LoadNode->getMemOperand();
2589 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2590 EVT LdVT = LoadNode->getMemoryVT();
2591 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2592 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2593 Node->getDebugLoc(),
2594 MVT::i32, MVT::Other, Ops,
2595 array_lengthof(Ops));
2596 Result->setMemRefs(MemOp, MemOp + 2);
2598 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2599 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2605 SDNode *ResNode = SelectCode(Node);
2607 DEBUG(dbgs() << "=> ";
2608 if (ResNode == NULL || ResNode == Node)
2611 ResNode->dump(CurDAG);
2617 bool X86DAGToDAGISel::
2618 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2619 std::vector<SDValue> &OutOps) {
2620 SDValue Op0, Op1, Op2, Op3, Op4;
2621 switch (ConstraintCode) {
2622 case 'o': // offsetable ??
2623 case 'v': // not offsetable ??
2624 default: return true;
2626 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
2631 OutOps.push_back(Op0);
2632 OutOps.push_back(Op1);
2633 OutOps.push_back(Op2);
2634 OutOps.push_back(Op3);
2635 OutOps.push_back(Op4);
2639 /// createX86ISelDag - This pass converts a legalized DAG into a
2640 /// X86-specific DAG, ready for instruction scheduling.
2642 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2643 CodeGenOpt::Level OptLevel) {
2644 return new X86DAGToDAGISel(TM, OptLevel);