1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
39 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
41 //===----------------------------------------------------------------------===//
42 // Pattern Matcher Implementation
43 //===----------------------------------------------------------------------===//
46 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
47 /// SDValue's instead of register numbers for the leaves of the matched
49 struct X86ISelAddressMode {
55 // This is really a union, discriminated by BaseType!
63 const GlobalValue *GV;
65 const BlockAddress *BlockAddr;
68 unsigned Align; // CP alignment.
69 unsigned char SymbolFlags; // X86II::MO_*
72 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
73 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
74 SymbolFlags(X86II::MO_NO_FLAG) {
77 bool hasSymbolicDisplacement() const {
78 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
81 bool hasBaseOrIndexReg() const {
82 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
85 /// isRIPRelative - Return true if this addressing mode is already RIP
87 bool isRIPRelative() const {
88 if (BaseType != RegBase) return false;
89 if (RegisterSDNode *RegNode =
90 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
91 return RegNode->getReg() == X86::RIP;
95 void setBaseReg(SDValue Reg) {
100 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
102 dbgs() << "X86ISelAddressMode " << this << '\n';
103 dbgs() << "Base_Reg ";
104 if (Base_Reg.getNode() != 0)
105 Base_Reg.getNode()->dump();
108 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
109 << " Scale" << Scale << '\n'
111 if (IndexReg.getNode() != 0)
112 IndexReg.getNode()->dump();
115 dbgs() << " Disp " << Disp << '\n'
132 dbgs() << " JT" << JT << " Align" << Align << '\n';
139 //===--------------------------------------------------------------------===//
140 /// ISel - X86 specific code to select X86 machine instructions for
141 /// SelectionDAG operations.
143 class X86DAGToDAGISel : public SelectionDAGISel {
144 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
145 /// make the right decision when generating code for different targets.
146 const X86Subtarget *Subtarget;
148 /// OptForSize - If true, selector should try to optimize for code size
149 /// instead of performance.
153 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
154 : SelectionDAGISel(tm, OptLevel),
155 Subtarget(&tm.getSubtarget<X86Subtarget>()),
158 virtual const char *getPassName() const {
159 return "X86 DAG->DAG Instruction Selection";
162 virtual void EmitFunctionEntryCode();
164 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
166 virtual void PreprocessISelDAG();
168 inline bool immSext8(SDNode *N) const {
169 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
172 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
173 // sign extended field.
174 inline bool i64immSExt32(SDNode *N) const {
175 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
176 return (int64_t)v == (int32_t)v;
179 // Include the pieces autogenerated from the target description.
180 #include "X86GenDAGISel.inc"
183 SDNode *Select(SDNode *N);
184 SDNode *SelectGather(SDNode *N, unsigned Opc);
185 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
186 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT);
188 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
189 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
190 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
191 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
192 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
194 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
195 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
196 SDValue &Scale, SDValue &Index, SDValue &Disp,
198 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
199 bool SelectLEAAddr(SDValue N, SDValue &Base,
200 SDValue &Scale, SDValue &Index, SDValue &Disp,
202 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
203 SDValue &Scale, SDValue &Index, SDValue &Disp,
205 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
206 SDValue &Scale, SDValue &Index, SDValue &Disp,
208 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
209 SDValue &Base, SDValue &Scale,
210 SDValue &Index, SDValue &Disp,
212 SDValue &NodeWithChain);
214 bool TryFoldLoad(SDNode *P, SDValue N,
215 SDValue &Base, SDValue &Scale,
216 SDValue &Index, SDValue &Disp,
219 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
220 /// inline asm expressions.
221 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
223 std::vector<SDValue> &OutOps);
225 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
227 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
228 SDValue &Scale, SDValue &Index,
229 SDValue &Disp, SDValue &Segment) {
230 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
231 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
232 getTargetLowering()->getPointerTy()) :
234 Scale = getI8Imm(AM.Scale);
236 // These are 32-bit even in 64-bit mode since RIP relative offset
239 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
243 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
244 AM.Align, AM.Disp, AM.SymbolFlags);
246 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
247 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
248 } else if (AM.JT != -1) {
249 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
250 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
251 } else if (AM.BlockAddr)
252 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
255 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
257 if (AM.Segment.getNode())
258 Segment = AM.Segment;
260 Segment = CurDAG->getRegister(0, MVT::i32);
263 /// getI8Imm - Return a target constant with the specified value, of type
265 inline SDValue getI8Imm(unsigned Imm) {
266 return CurDAG->getTargetConstant(Imm, MVT::i8);
269 /// getI32Imm - Return a target constant with the specified value, of type
271 inline SDValue getI32Imm(unsigned Imm) {
272 return CurDAG->getTargetConstant(Imm, MVT::i32);
275 /// getGlobalBaseReg - Return an SDNode that returns the value of
276 /// the global base register. Output instructions required to
277 /// initialize the global base register, if necessary.
279 SDNode *getGlobalBaseReg();
281 /// getTargetMachine - Return a reference to the TargetMachine, casted
282 /// to the target-specific type.
283 const X86TargetMachine &getTargetMachine() const {
284 return static_cast<const X86TargetMachine &>(TM);
287 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
288 /// to the target-specific type.
289 const X86InstrInfo *getInstrInfo() const {
290 return getTargetMachine().getInstrInfo();
297 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
298 if (OptLevel == CodeGenOpt::None) return false;
303 if (N.getOpcode() != ISD::LOAD)
306 // If N is a load, do additional profitability checks.
308 switch (U->getOpcode()) {
321 SDValue Op1 = U->getOperand(1);
323 // If the other operand is a 8-bit immediate we should fold the immediate
324 // instead. This reduces code size.
326 // movl 4(%esp), %eax
330 // addl 4(%esp), %eax
331 // The former is 2 bytes shorter. In case where the increment is 1, then
332 // the saving can be 4 bytes (by using incl %eax).
333 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
334 if (Imm->getAPIntValue().isSignedIntN(8))
337 // If the other operand is a TLS address, we should fold it instead.
340 // leal i@NTPOFF(%eax), %eax
342 // movl $i@NTPOFF, %eax
344 // if the block also has an access to a second TLS address this will save
346 // FIXME: This is probably also true for non TLS addresses.
347 if (Op1.getOpcode() == X86ISD::Wrapper) {
348 SDValue Val = Op1.getOperand(0);
349 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
359 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
360 /// load's chain operand and move load below the call's chain operand.
361 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
362 SDValue Call, SDValue OrigChain) {
363 SmallVector<SDValue, 8> Ops;
364 SDValue Chain = OrigChain.getOperand(0);
365 if (Chain.getNode() == Load.getNode())
366 Ops.push_back(Load.getOperand(0));
368 assert(Chain.getOpcode() == ISD::TokenFactor &&
369 "Unexpected chain operand");
370 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
371 if (Chain.getOperand(i).getNode() == Load.getNode())
372 Ops.push_back(Load.getOperand(0));
374 Ops.push_back(Chain.getOperand(i));
376 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load),
377 MVT::Other, &Ops[0], Ops.size());
379 Ops.push_back(NewChain);
381 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
382 Ops.push_back(OrigChain.getOperand(i));
383 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
384 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
385 Load.getOperand(1), Load.getOperand(2));
387 unsigned NumOps = Call.getNode()->getNumOperands();
389 Ops.push_back(SDValue(Load.getNode(), 1));
390 for (unsigned i = 1, e = NumOps; i != e; ++i)
391 Ops.push_back(Call.getOperand(i));
392 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], NumOps);
395 /// isCalleeLoad - Return true if call address is a load and it can be
396 /// moved below CALLSEQ_START and the chains leading up to the call.
397 /// Return the CALLSEQ_START by reference as a second output.
398 /// In the case of a tail call, there isn't a callseq node between the call
399 /// chain and the load.
400 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
401 // The transformation is somewhat dangerous if the call's chain was glued to
402 // the call. After MoveBelowOrigChain the load is moved between the call and
403 // the chain, this can create a cycle if the load is not folded. So it is
404 // *really* important that we are sure the load will be folded.
405 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
407 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
410 LD->getAddressingMode() != ISD::UNINDEXED ||
411 LD->getExtensionType() != ISD::NON_EXTLOAD)
414 // Now let's find the callseq_start.
415 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
416 if (!Chain.hasOneUse())
418 Chain = Chain.getOperand(0);
421 if (!Chain.getNumOperands())
423 // Since we are not checking for AA here, conservatively abort if the chain
424 // writes to memory. It's not safe to move the callee (a load) across a store.
425 if (isa<MemSDNode>(Chain.getNode()) &&
426 cast<MemSDNode>(Chain.getNode())->writeMem())
428 if (Chain.getOperand(0).getNode() == Callee.getNode())
430 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
431 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
432 Callee.getValue(1).hasOneUse())
437 void X86DAGToDAGISel::PreprocessISelDAG() {
438 // OptForSize is used in pattern predicates that isel is matching.
439 OptForSize = MF->getFunction()->getAttributes().
440 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
442 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
443 E = CurDAG->allnodes_end(); I != E; ) {
444 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
446 if (OptLevel != CodeGenOpt::None &&
447 // Only does this when target favors doesn't favor register indirect
449 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
450 (N->getOpcode() == X86ISD::TC_RETURN &&
451 // Only does this if load can be folded into TC_RETURN.
452 (Subtarget->is64Bit() ||
453 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
454 /// Also try moving call address load from outside callseq_start to just
455 /// before the call to allow it to be folded.
473 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
474 SDValue Chain = N->getOperand(0);
475 SDValue Load = N->getOperand(1);
476 if (!isCalleeLoad(Load, Chain, HasCallSeq))
478 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
483 // Lower fpround and fpextend nodes that target the FP stack to be store and
484 // load to the stack. This is a gross hack. We would like to simply mark
485 // these as being illegal, but when we do that, legalize produces these when
486 // it expands calls, then expands these in the same legalize pass. We would
487 // like dag combine to be able to hack on these between the call expansion
488 // and the node legalization. As such this pass basically does "really
489 // late" legalization of these inline with the X86 isel pass.
490 // FIXME: This should only happen when not compiled with -O0.
491 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
494 EVT SrcVT = N->getOperand(0).getValueType();
495 EVT DstVT = N->getValueType(0);
497 // If any of the sources are vectors, no fp stack involved.
498 if (SrcVT.isVector() || DstVT.isVector())
501 // If the source and destination are SSE registers, then this is a legal
502 // conversion that should not be lowered.
503 const X86TargetLowering *X86Lowering =
504 static_cast<const X86TargetLowering *>(getTargetLowering());
505 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
506 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
507 if (SrcIsSSE && DstIsSSE)
510 if (!SrcIsSSE && !DstIsSSE) {
511 // If this is an FPStack extension, it is a noop.
512 if (N->getOpcode() == ISD::FP_EXTEND)
514 // If this is a value-preserving FPStack truncation, it is a noop.
515 if (N->getConstantOperandVal(1))
519 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
520 // FPStack has extload and truncstore. SSE can fold direct loads into other
521 // operations. Based on this, decide what we want to do.
523 if (N->getOpcode() == ISD::FP_ROUND)
524 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
526 MemVT = SrcIsSSE ? SrcVT : DstVT;
528 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
531 // FIXME: optimize the case where the src/dest is a load or store?
532 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
534 MemTmp, MachinePointerInfo(), MemVT,
536 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
537 MachinePointerInfo(),
538 MemVT, false, false, 0);
540 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
541 // extload we created. This will cause general havok on the dag because
542 // anything below the conversion could be folded into other existing nodes.
543 // To avoid invalidating 'I', back it up to the convert node.
545 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
547 // Now that we did that, the node is dead. Increment the iterator to the
548 // next node to process, then delete N.
550 CurDAG->DeleteNode(N);
555 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
556 /// the main function.
557 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
558 MachineFrameInfo *MFI) {
559 const TargetInstrInfo *TII = TM.getInstrInfo();
560 if (Subtarget->isTargetCygMing()) {
562 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
563 BuildMI(BB, DebugLoc(),
564 TII->get(CallOp)).addExternalSymbol("__main");
568 void X86DAGToDAGISel::EmitFunctionEntryCode() {
569 // If this is main, emit special code for main.
570 if (const Function *Fn = MF->getFunction())
571 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
572 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
575 static bool isDispSafeForFrameIndex(int64_t Val) {
576 // On 64-bit platforms, we can run into an issue where a frame index
577 // includes a displacement that, when added to the explicit displacement,
578 // will overflow the displacement field. Assuming that the frame index
579 // displacement fits into a 31-bit integer (which is only slightly more
580 // aggressive than the current fundamental assumption that it fits into
581 // a 32-bit integer), a 31-bit disp should always be safe.
582 return isInt<31>(Val);
585 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
586 X86ISelAddressMode &AM) {
587 int64_t Val = AM.Disp + Offset;
588 CodeModel::Model M = TM.getCodeModel();
589 if (Subtarget->is64Bit()) {
590 if (!X86::isOffsetSuitableForCodeModel(Val, M,
591 AM.hasSymbolicDisplacement()))
593 // In addition to the checks required for a register base, check that
594 // we do not try to use an unsafe Disp with a frame index.
595 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
596 !isDispSafeForFrameIndex(Val))
604 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
605 SDValue Address = N->getOperand(1);
607 // load gs:0 -> GS segment register.
608 // load fs:0 -> FS segment register.
610 // This optimization is valid because the GNU TLS model defines that
611 // gs:0 (or fs:0 on X86-64) contains its own address.
612 // For more information see http://people.redhat.com/drepper/tls.pdf
613 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
614 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
615 Subtarget->isTargetLinux())
616 switch (N->getPointerInfo().getAddrSpace()) {
618 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
621 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
628 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
629 /// into an addressing mode. These wrap things that will resolve down into a
630 /// symbol reference. If no match is possible, this returns true, otherwise it
632 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
633 // If the addressing mode already has a symbol as the displacement, we can
634 // never match another symbol.
635 if (AM.hasSymbolicDisplacement())
638 SDValue N0 = N.getOperand(0);
639 CodeModel::Model M = TM.getCodeModel();
641 // Handle X86-64 rip-relative addresses. We check this before checking direct
642 // folding because RIP is preferable to non-RIP accesses.
643 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
644 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
645 // they cannot be folded into immediate fields.
646 // FIXME: This can be improved for kernel and other models?
647 (M == CodeModel::Small || M == CodeModel::Kernel)) {
648 // Base and index reg must be 0 in order to use %rip as base.
649 if (AM.hasBaseOrIndexReg())
651 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
652 X86ISelAddressMode Backup = AM;
653 AM.GV = G->getGlobal();
654 AM.SymbolFlags = G->getTargetFlags();
655 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
659 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
660 X86ISelAddressMode Backup = AM;
661 AM.CP = CP->getConstVal();
662 AM.Align = CP->getAlignment();
663 AM.SymbolFlags = CP->getTargetFlags();
664 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
668 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
669 AM.ES = S->getSymbol();
670 AM.SymbolFlags = S->getTargetFlags();
671 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
672 AM.JT = J->getIndex();
673 AM.SymbolFlags = J->getTargetFlags();
674 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
675 X86ISelAddressMode Backup = AM;
676 AM.BlockAddr = BA->getBlockAddress();
677 AM.SymbolFlags = BA->getTargetFlags();
678 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
683 llvm_unreachable("Unhandled symbol reference node.");
685 if (N.getOpcode() == X86ISD::WrapperRIP)
686 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
690 // Handle the case when globals fit in our immediate field: This is true for
691 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
692 // mode, this only applies to a non-RIP-relative computation.
693 if (!Subtarget->is64Bit() ||
694 M == CodeModel::Small || M == CodeModel::Kernel) {
695 assert(N.getOpcode() != X86ISD::WrapperRIP &&
696 "RIP-relative addressing already handled");
697 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
698 AM.GV = G->getGlobal();
699 AM.Disp += G->getOffset();
700 AM.SymbolFlags = G->getTargetFlags();
701 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
702 AM.CP = CP->getConstVal();
703 AM.Align = CP->getAlignment();
704 AM.Disp += CP->getOffset();
705 AM.SymbolFlags = CP->getTargetFlags();
706 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
707 AM.ES = S->getSymbol();
708 AM.SymbolFlags = S->getTargetFlags();
709 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
710 AM.JT = J->getIndex();
711 AM.SymbolFlags = J->getTargetFlags();
712 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
713 AM.BlockAddr = BA->getBlockAddress();
714 AM.Disp += BA->getOffset();
715 AM.SymbolFlags = BA->getTargetFlags();
717 llvm_unreachable("Unhandled symbol reference node.");
724 /// MatchAddress - Add the specified node to the specified addressing mode,
725 /// returning true if it cannot be done. This just pattern matches for the
727 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
728 if (MatchAddressRecursively(N, AM, 0))
731 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
732 // a smaller encoding and avoids a scaled-index.
734 AM.BaseType == X86ISelAddressMode::RegBase &&
735 AM.Base_Reg.getNode() == 0) {
736 AM.Base_Reg = AM.IndexReg;
740 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
741 // because it has a smaller encoding.
742 // TODO: Which other code models can use this?
743 if (TM.getCodeModel() == CodeModel::Small &&
744 Subtarget->is64Bit() &&
746 AM.BaseType == X86ISelAddressMode::RegBase &&
747 AM.Base_Reg.getNode() == 0 &&
748 AM.IndexReg.getNode() == 0 &&
749 AM.SymbolFlags == X86II::MO_NO_FLAG &&
750 AM.hasSymbolicDisplacement())
751 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
756 // Insert a node into the DAG at least before the Pos node's position. This
757 // will reposition the node as needed, and will assign it a node ID that is <=
758 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
759 // IDs! The selection DAG must no longer depend on their uniqueness when this
761 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
762 if (N.getNode()->getNodeId() == -1 ||
763 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
764 DAG.RepositionNode(Pos.getNode(), N.getNode());
765 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
769 // Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
770 // allows us to convert the shift and and into an h-register extract and
771 // a scaled index. Returns false if the simplification is performed.
772 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
774 SDValue Shift, SDValue X,
775 X86ISelAddressMode &AM) {
776 if (Shift.getOpcode() != ISD::SRL ||
777 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
781 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
782 if (ScaleLog <= 0 || ScaleLog >= 4 ||
783 Mask != (0xffu << ScaleLog))
786 EVT VT = N.getValueType();
788 SDValue Eight = DAG.getConstant(8, MVT::i8);
789 SDValue NewMask = DAG.getConstant(0xff, VT);
790 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
791 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
792 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
793 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
795 // Insert the new nodes into the topological ordering. We must do this in
796 // a valid topological ordering as nothing is going to go back and re-sort
797 // these nodes. We continually insert before 'N' in sequence as this is
798 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
799 // hierarchy left to express.
800 InsertDAGNode(DAG, N, Eight);
801 InsertDAGNode(DAG, N, Srl);
802 InsertDAGNode(DAG, N, NewMask);
803 InsertDAGNode(DAG, N, And);
804 InsertDAGNode(DAG, N, ShlCount);
805 InsertDAGNode(DAG, N, Shl);
806 DAG.ReplaceAllUsesWith(N, Shl);
808 AM.Scale = (1 << ScaleLog);
812 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
813 // allows us to fold the shift into this addressing mode. Returns false if the
814 // transform succeeded.
815 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
817 SDValue Shift, SDValue X,
818 X86ISelAddressMode &AM) {
819 if (Shift.getOpcode() != ISD::SHL ||
820 !isa<ConstantSDNode>(Shift.getOperand(1)))
823 // Not likely to be profitable if either the AND or SHIFT node has more
824 // than one use (unless all uses are for address computation). Besides,
825 // isel mechanism requires their node ids to be reused.
826 if (!N.hasOneUse() || !Shift.hasOneUse())
829 // Verify that the shift amount is something we can fold.
830 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
831 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
834 EVT VT = N.getValueType();
836 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
837 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
838 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
840 // Insert the new nodes into the topological ordering. We must do this in
841 // a valid topological ordering as nothing is going to go back and re-sort
842 // these nodes. We continually insert before 'N' in sequence as this is
843 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
844 // hierarchy left to express.
845 InsertDAGNode(DAG, N, NewMask);
846 InsertDAGNode(DAG, N, NewAnd);
847 InsertDAGNode(DAG, N, NewShift);
848 DAG.ReplaceAllUsesWith(N, NewShift);
850 AM.Scale = 1 << ShiftAmt;
851 AM.IndexReg = NewAnd;
855 // Implement some heroics to detect shifts of masked values where the mask can
856 // be replaced by extending the shift and undoing that in the addressing mode
857 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
858 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
859 // the addressing mode. This results in code such as:
861 // int f(short *y, int *lookup_table) {
863 // return *y + lookup_table[*y >> 11];
867 // movzwl (%rdi), %eax
870 // addl (%rsi,%rcx,4), %eax
873 // movzwl (%rdi), %eax
877 // addl (%rsi,%rcx), %eax
879 // Note that this function assumes the mask is provided as a mask *after* the
880 // value is shifted. The input chain may or may not match that, but computing
881 // such a mask is trivial.
882 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
884 SDValue Shift, SDValue X,
885 X86ISelAddressMode &AM) {
886 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
887 !isa<ConstantSDNode>(Shift.getOperand(1)))
890 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
891 unsigned MaskLZ = countLeadingZeros(Mask);
892 unsigned MaskTZ = countTrailingZeros(Mask);
894 // The amount of shift we're trying to fit into the addressing mode is taken
895 // from the trailing zeros of the mask.
896 unsigned AMShiftAmt = MaskTZ;
898 // There is nothing we can do here unless the mask is removing some bits.
899 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
900 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
902 // We also need to ensure that mask is a continuous run of bits.
903 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
905 // Scale the leading zero count down based on the actual size of the value.
906 // Also scale it down based on the size of the shift.
907 MaskLZ -= (64 - X.getValueSizeInBits()) + ShiftAmt;
909 // The final check is to ensure that any masked out high bits of X are
910 // already known to be zero. Otherwise, the mask has a semantic impact
911 // other than masking out a couple of low bits. Unfortunately, because of
912 // the mask, zero extensions will be removed from operands in some cases.
913 // This code works extra hard to look through extensions because we can
914 // replace them with zero extensions cheaply if necessary.
915 bool ReplacingAnyExtend = false;
916 if (X.getOpcode() == ISD::ANY_EXTEND) {
917 unsigned ExtendBits =
918 X.getValueSizeInBits() - X.getOperand(0).getValueSizeInBits();
919 // Assume that we'll replace the any-extend with a zero-extend, and
920 // narrow the search to the extended value.
922 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
923 ReplacingAnyExtend = true;
925 APInt MaskedHighBits = APInt::getHighBitsSet(X.getValueSizeInBits(),
927 APInt KnownZero, KnownOne;
928 DAG.ComputeMaskedBits(X, KnownZero, KnownOne);
929 if (MaskedHighBits != KnownZero) return true;
931 // We've identified a pattern that can be transformed into a single shift
932 // and an addressing mode. Make it so.
933 EVT VT = N.getValueType();
934 if (ReplacingAnyExtend) {
935 assert(X.getValueType() != VT);
936 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
937 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
938 InsertDAGNode(DAG, N, NewX);
942 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
943 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
944 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
945 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
947 // Insert the new nodes into the topological ordering. We must do this in
948 // a valid topological ordering as nothing is going to go back and re-sort
949 // these nodes. We continually insert before 'N' in sequence as this is
950 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
951 // hierarchy left to express.
952 InsertDAGNode(DAG, N, NewSRLAmt);
953 InsertDAGNode(DAG, N, NewSRL);
954 InsertDAGNode(DAG, N, NewSHLAmt);
955 InsertDAGNode(DAG, N, NewSHL);
956 DAG.ReplaceAllUsesWith(N, NewSHL);
958 AM.Scale = 1 << AMShiftAmt;
959 AM.IndexReg = NewSRL;
963 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
967 dbgs() << "MatchAddress: ";
972 return MatchAddressBase(N, AM);
974 // If this is already a %rip relative address, we can only merge immediates
975 // into it. Instead of handling this in every case, we handle it here.
976 // RIP relative addressing: %rip + 32-bit displacement!
977 if (AM.isRIPRelative()) {
978 // FIXME: JumpTable and ExternalSymbol address currently don't like
979 // displacements. It isn't very important, but this should be fixed for
981 if (!AM.ES && AM.JT != -1) return true;
983 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
984 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
989 switch (N.getOpcode()) {
991 case ISD::Constant: {
992 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
993 if (!FoldOffsetIntoAddress(Val, AM))
998 case X86ISD::Wrapper:
999 case X86ISD::WrapperRIP:
1000 if (!MatchWrapper(N, AM))
1005 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1009 case ISD::FrameIndex:
1010 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1011 AM.Base_Reg.getNode() == 0 &&
1012 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1013 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1014 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1020 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
1024 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1025 unsigned Val = CN->getZExtValue();
1026 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1027 // that the base operand remains free for further matching. If
1028 // the base doesn't end up getting used, a post-processing step
1029 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1030 if (Val == 1 || Val == 2 || Val == 3) {
1031 AM.Scale = 1 << Val;
1032 SDValue ShVal = N.getNode()->getOperand(0);
1034 // Okay, we know that we have a scale by now. However, if the scaled
1035 // value is an add of something and a constant, we can fold the
1036 // constant into the disp field here.
1037 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1038 AM.IndexReg = ShVal.getNode()->getOperand(0);
1039 ConstantSDNode *AddVal =
1040 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1041 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1042 if (!FoldOffsetIntoAddress(Disp, AM))
1046 AM.IndexReg = ShVal;
1053 // Scale must not be used already.
1054 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1056 SDValue And = N.getOperand(0);
1057 if (And.getOpcode() != ISD::AND) break;
1058 SDValue X = And.getOperand(0);
1060 // We only handle up to 64-bit values here as those are what matter for
1061 // addressing mode optimizations.
1062 if (X.getValueSizeInBits() > 64) break;
1064 // The mask used for the transform is expected to be post-shift, but we
1065 // found the shift first so just apply the shift to the mask before passing
1067 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1068 !isa<ConstantSDNode>(And.getOperand(1)))
1070 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1072 // Try to fold the mask and shift into the scale, and return false if we
1074 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1079 case ISD::SMUL_LOHI:
1080 case ISD::UMUL_LOHI:
1081 // A mul_lohi where we need the low part can be folded as a plain multiply.
1082 if (N.getResNo() != 0) break;
1085 case X86ISD::MUL_IMM:
1086 // X*[3,5,9] -> X+X*[2,4,8]
1087 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1088 AM.Base_Reg.getNode() == 0 &&
1089 AM.IndexReg.getNode() == 0) {
1091 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1092 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1093 CN->getZExtValue() == 9) {
1094 AM.Scale = unsigned(CN->getZExtValue())-1;
1096 SDValue MulVal = N.getNode()->getOperand(0);
1099 // Okay, we know that we have a scale by now. However, if the scaled
1100 // value is an add of something and a constant, we can fold the
1101 // constant into the disp field here.
1102 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1103 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1104 Reg = MulVal.getNode()->getOperand(0);
1105 ConstantSDNode *AddVal =
1106 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1107 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1108 if (FoldOffsetIntoAddress(Disp, AM))
1109 Reg = N.getNode()->getOperand(0);
1111 Reg = N.getNode()->getOperand(0);
1114 AM.IndexReg = AM.Base_Reg = Reg;
1121 // Given A-B, if A can be completely folded into the address and
1122 // the index field with the index field unused, use -B as the index.
1123 // This is a win if a has multiple parts that can be folded into
1124 // the address. Also, this saves a mov if the base register has
1125 // other uses, since it avoids a two-address sub instruction, however
1126 // it costs an additional mov if the index register has other uses.
1128 // Add an artificial use to this node so that we can keep track of
1129 // it if it gets CSE'd with a different node.
1130 HandleSDNode Handle(N);
1132 // Test if the LHS of the sub can be folded.
1133 X86ISelAddressMode Backup = AM;
1134 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1138 // Test if the index field is free for use.
1139 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1145 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1146 // If the RHS involves a register with multiple uses, this
1147 // transformation incurs an extra mov, due to the neg instruction
1148 // clobbering its operand.
1149 if (!RHS.getNode()->hasOneUse() ||
1150 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1151 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1152 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1153 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1154 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1156 // If the base is a register with multiple uses, this
1157 // transformation may save a mov.
1158 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1159 AM.Base_Reg.getNode() &&
1160 !AM.Base_Reg.getNode()->hasOneUse()) ||
1161 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1163 // If the folded LHS was interesting, this transformation saves
1164 // address arithmetic.
1165 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1166 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1167 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1169 // If it doesn't look like it may be an overall win, don't do it.
1175 // Ok, the transformation is legal and appears profitable. Go for it.
1176 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1177 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1181 // Insert the new nodes into the topological ordering.
1182 InsertDAGNode(*CurDAG, N, Zero);
1183 InsertDAGNode(*CurDAG, N, Neg);
1188 // Add an artificial use to this node so that we can keep track of
1189 // it if it gets CSE'd with a different node.
1190 HandleSDNode Handle(N);
1192 X86ISelAddressMode Backup = AM;
1193 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1194 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1198 // Try again after commuting the operands.
1199 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1200 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1204 // If we couldn't fold both operands into the address at the same time,
1205 // see if we can just put each operand into a register and fold at least
1207 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1208 !AM.Base_Reg.getNode() &&
1209 !AM.IndexReg.getNode()) {
1210 N = Handle.getValue();
1211 AM.Base_Reg = N.getOperand(0);
1212 AM.IndexReg = N.getOperand(1);
1216 N = Handle.getValue();
1221 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1222 if (CurDAG->isBaseWithConstantOffset(N)) {
1223 X86ISelAddressMode Backup = AM;
1224 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1226 // Start with the LHS as an addr mode.
1227 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1228 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1235 // Perform some heroic transforms on an and of a constant-count shift
1236 // with a constant to enable use of the scaled offset field.
1238 // Scale must not be used already.
1239 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1241 SDValue Shift = N.getOperand(0);
1242 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1243 SDValue X = Shift.getOperand(0);
1245 // We only handle up to 64-bit values here as those are what matter for
1246 // addressing mode optimizations.
1247 if (X.getValueSizeInBits() > 64) break;
1249 if (!isa<ConstantSDNode>(N.getOperand(1)))
1251 uint64_t Mask = N.getConstantOperandVal(1);
1253 // Try to fold the mask and shift into an extract and scale.
1254 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1257 // Try to fold the mask and shift directly into the scale.
1258 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1261 // Try to swap the mask and shift to place shifts which can be done as
1262 // a scale on the outside of the mask.
1263 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1269 return MatchAddressBase(N, AM);
1272 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1273 /// specified addressing mode without any further recursion.
1274 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1275 // Is the base register already occupied?
1276 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1277 // If so, check to see if the scale index register is set.
1278 if (AM.IndexReg.getNode() == 0) {
1284 // Otherwise, we cannot select it.
1288 // Default, generate it as a register.
1289 AM.BaseType = X86ISelAddressMode::RegBase;
1294 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1295 /// It returns the operands which make up the maximal addressing mode it can
1296 /// match by reference.
1298 /// Parent is the parent node of the addr operand that is being matched. It
1299 /// is always a load, store, atomic node, or null. It is only null when
1300 /// checking memory operands for inline asm nodes.
1301 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1302 SDValue &Scale, SDValue &Index,
1303 SDValue &Disp, SDValue &Segment) {
1304 X86ISelAddressMode AM;
1307 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1308 // that are not a MemSDNode, and thus don't have proper addrspace info.
1309 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1310 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1311 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1312 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1313 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1314 unsigned AddrSpace =
1315 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1316 // AddrSpace 256 -> GS, 257 -> FS.
1317 if (AddrSpace == 256)
1318 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1319 if (AddrSpace == 257)
1320 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1323 if (MatchAddress(N, AM))
1326 EVT VT = N.getValueType();
1327 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1328 if (!AM.Base_Reg.getNode())
1329 AM.Base_Reg = CurDAG->getRegister(0, VT);
1332 if (!AM.IndexReg.getNode())
1333 AM.IndexReg = CurDAG->getRegister(0, VT);
1335 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1339 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1340 /// match a load whose top elements are either undef or zeros. The load flavor
1341 /// is derived from the type of N, which is either v4f32 or v2f64.
1344 /// PatternChainNode: this is the matched node that has a chain input and
1346 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1347 SDValue N, SDValue &Base,
1348 SDValue &Scale, SDValue &Index,
1349 SDValue &Disp, SDValue &Segment,
1350 SDValue &PatternNodeWithChain) {
1351 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1352 PatternNodeWithChain = N.getOperand(0);
1353 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1354 PatternNodeWithChain.hasOneUse() &&
1355 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1356 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1357 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1358 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1364 // Also handle the case where we explicitly require zeros in the top
1365 // elements. This is a vector shuffle from the zero vector.
1366 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1367 // Check to see if the top elements are all zeros (or bitcast of zeros).
1368 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1369 N.getOperand(0).getNode()->hasOneUse() &&
1370 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1371 N.getOperand(0).getOperand(0).hasOneUse() &&
1372 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1373 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1374 // Okay, this is a zero extending load. Fold it.
1375 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1376 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1378 PatternNodeWithChain = SDValue(LD, 0);
1385 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1386 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1387 uint64_t ImmVal = CN->getZExtValue();
1388 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1391 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
1395 // In static codegen with small code model, we can get the address of a label
1396 // into a register with 'movl'. TableGen has already made sure we're looking
1397 // at a label of some kind.
1398 assert(N->getOpcode() == X86ISD::Wrapper &&
1399 "Unexpected node type for MOV32ri64");
1400 N = N.getOperand(0);
1402 if (N->getOpcode() != ISD::TargetConstantPool &&
1403 N->getOpcode() != ISD::TargetJumpTable &&
1404 N->getOpcode() != ISD::TargetGlobalAddress &&
1405 N->getOpcode() != ISD::TargetExternalSymbol &&
1406 N->getOpcode() != ISD::TargetBlockAddress)
1410 return TM.getCodeModel() == CodeModel::Small;
1413 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1414 SDValue &Scale, SDValue &Index,
1415 SDValue &Disp, SDValue &Segment) {
1416 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1420 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1421 if (RN && RN->getReg() == 0)
1422 Base = CurDAG->getRegister(0, MVT::i64);
1423 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(N)) {
1424 // Base could already be %rip, particularly in the x32 ABI.
1425 Base = SDValue(CurDAG->getMachineNode(
1426 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1427 CurDAG->getTargetConstant(0, MVT::i64),
1429 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1433 RN = dyn_cast<RegisterSDNode>(Index);
1434 if (RN && RN->getReg() == 0)
1435 Index = CurDAG->getRegister(0, MVT::i64);
1437 assert(Index.getValueType() == MVT::i32 &&
1438 "Expect to be extending 32-bit registers for use in LEA");
1439 Index = SDValue(CurDAG->getMachineNode(
1440 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1441 CurDAG->getTargetConstant(0, MVT::i64),
1443 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1450 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1451 /// mode it matches can be cost effectively emitted as an LEA instruction.
1452 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1453 SDValue &Base, SDValue &Scale,
1454 SDValue &Index, SDValue &Disp,
1456 X86ISelAddressMode AM;
1458 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1460 SDValue Copy = AM.Segment;
1461 SDValue T = CurDAG->getRegister(0, MVT::i32);
1463 if (MatchAddress(N, AM))
1465 assert (T == AM.Segment);
1468 EVT VT = N.getValueType();
1469 unsigned Complexity = 0;
1470 if (AM.BaseType == X86ISelAddressMode::RegBase)
1471 if (AM.Base_Reg.getNode())
1474 AM.Base_Reg = CurDAG->getRegister(0, VT);
1475 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1478 if (AM.IndexReg.getNode())
1481 AM.IndexReg = CurDAG->getRegister(0, VT);
1483 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1488 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1489 // to a LEA. This is determined with some expermentation but is by no means
1490 // optimal (especially for code size consideration). LEA is nice because of
1491 // its three-address nature. Tweak the cost function again when we can run
1492 // convertToThreeAddress() at register allocation time.
1493 if (AM.hasSymbolicDisplacement()) {
1494 // For X86-64, we should always use lea to materialize RIP relative
1496 if (Subtarget->is64Bit())
1502 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1505 // If it isn't worth using an LEA, reject it.
1506 if (Complexity <= 2)
1509 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1513 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1514 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1515 SDValue &Scale, SDValue &Index,
1516 SDValue &Disp, SDValue &Segment) {
1517 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1518 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1520 X86ISelAddressMode AM;
1521 AM.GV = GA->getGlobal();
1522 AM.Disp += GA->getOffset();
1523 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1524 AM.SymbolFlags = GA->getTargetFlags();
1526 if (N.getValueType() == MVT::i32) {
1528 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1530 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1533 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1538 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1539 SDValue &Base, SDValue &Scale,
1540 SDValue &Index, SDValue &Disp,
1542 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1543 !IsProfitableToFold(N, P, P) ||
1544 !IsLegalToFold(N, P, P, OptLevel))
1547 return SelectAddr(N.getNode(),
1548 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1551 /// getGlobalBaseReg - Return an SDNode that returns the value of
1552 /// the global base register. Output instructions required to
1553 /// initialize the global base register, if necessary.
1555 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1556 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1557 return CurDAG->getRegister(GlobalBaseReg,
1558 getTargetLowering()->getPointerTy()).getNode();
1561 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1562 SDValue Chain = Node->getOperand(0);
1563 SDValue In1 = Node->getOperand(1);
1564 SDValue In2L = Node->getOperand(2);
1565 SDValue In2H = Node->getOperand(3);
1567 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1568 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1570 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1571 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1572 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1573 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node),
1574 MVT::i32, MVT::i32, MVT::Other, Ops);
1575 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1579 /// Atomic opcode table
1607 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1618 X86::LOCK_ADD64mi32,
1631 X86::LOCK_SUB64mi32,
1683 X86::LOCK_AND64mi32,
1696 X86::LOCK_XOR64mi32,
1701 // Return the target constant operand for atomic-load-op and do simple
1702 // translations, such as from atomic-load-add to lock-sub. The return value is
1703 // one of the following 3 cases:
1704 // + target-constant, the operand could be supported as a target constant.
1705 // + empty, the operand is not needed any more with the new op selected.
1706 // + non-empty, otherwise.
1707 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1709 enum AtomicOpc &Op, EVT NVT,
1711 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1712 int64_t CNVal = CN->getSExtValue();
1713 // Quit if not 32-bit imm.
1714 if ((int32_t)CNVal != CNVal)
1716 // For atomic-load-add, we could do some optimizations.
1718 // Translate to INC/DEC if ADD by 1 or -1.
1719 if ((CNVal == 1) || (CNVal == -1)) {
1720 Op = (CNVal == 1) ? INC : DEC;
1721 // No more constant operand after being translated into INC/DEC.
1724 // Translate to SUB if ADD by negative value.
1730 return CurDAG->getTargetConstant(CNVal, NVT);
1733 // If the value operand is single-used, try to optimize it.
1734 if (Op == ADD && Val.hasOneUse()) {
1735 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1736 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1738 return Val.getOperand(1);
1740 // A special case for i16, which needs truncating as, in most cases, it's
1741 // promoted to i32. We will translate
1742 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1743 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1744 Val.getOperand(0).getOpcode() == ISD::SUB &&
1745 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1747 Val = Val.getOperand(0);
1748 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1756 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
1757 if (Node->hasAnyUseOfValue(0))
1762 // Optimize common patterns for __sync_or_and_fetch and similar arith
1763 // operations where the result is not used. This allows us to use the "lock"
1764 // version of the arithmetic instruction.
1765 SDValue Chain = Node->getOperand(0);
1766 SDValue Ptr = Node->getOperand(1);
1767 SDValue Val = Node->getOperand(2);
1768 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1769 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1772 // Which index into the table.
1774 switch (Node->getOpcode()) {
1777 case ISD::ATOMIC_LOAD_OR:
1780 case ISD::ATOMIC_LOAD_AND:
1783 case ISD::ATOMIC_LOAD_XOR:
1786 case ISD::ATOMIC_LOAD_ADD:
1791 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val);
1792 bool isUnOp = !Val.getNode();
1793 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1796 switch (NVT.getSimpleVT().SimpleTy) {
1800 Opc = AtomicOpcTbl[Op][ConstantI8];
1802 Opc = AtomicOpcTbl[Op][I8];
1806 if (immSext8(Val.getNode()))
1807 Opc = AtomicOpcTbl[Op][SextConstantI16];
1809 Opc = AtomicOpcTbl[Op][ConstantI16];
1811 Opc = AtomicOpcTbl[Op][I16];
1815 if (immSext8(Val.getNode()))
1816 Opc = AtomicOpcTbl[Op][SextConstantI32];
1818 Opc = AtomicOpcTbl[Op][ConstantI32];
1820 Opc = AtomicOpcTbl[Op][I32];
1823 Opc = AtomicOpcTbl[Op][I64];
1825 if (immSext8(Val.getNode()))
1826 Opc = AtomicOpcTbl[Op][SextConstantI64];
1827 else if (i64immSExt32(Val.getNode()))
1828 Opc = AtomicOpcTbl[Op][ConstantI64];
1833 assert(Opc != 0 && "Invalid arith lock transform!");
1836 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1838 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1839 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1841 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1842 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1844 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1845 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1847 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1848 SDValue RetVals[] = { Undef, Ret };
1849 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1852 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1853 /// any uses which require the SF or OF bits to be accurate.
1854 static bool HasNoSignedComparisonUses(SDNode *N) {
1855 // Examine each user of the node.
1856 for (SDNode::use_iterator UI = N->use_begin(),
1857 UE = N->use_end(); UI != UE; ++UI) {
1858 // Only examine CopyToReg uses.
1859 if (UI->getOpcode() != ISD::CopyToReg)
1861 // Only examine CopyToReg uses that copy to EFLAGS.
1862 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1865 // Examine each user of the CopyToReg use.
1866 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1867 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1868 // Only examine the Flag result.
1869 if (FlagUI.getUse().getResNo() != 1) continue;
1870 // Anything unusual: assume conservatively.
1871 if (!FlagUI->isMachineOpcode()) return false;
1872 // Examine the opcode of the user.
1873 switch (FlagUI->getMachineOpcode()) {
1874 // These comparisons don't treat the most significant bit specially.
1875 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1876 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1877 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1878 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1879 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1880 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1881 case X86::CMOVA16rr: case X86::CMOVA16rm:
1882 case X86::CMOVA32rr: case X86::CMOVA32rm:
1883 case X86::CMOVA64rr: case X86::CMOVA64rm:
1884 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1885 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1886 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1887 case X86::CMOVB16rr: case X86::CMOVB16rm:
1888 case X86::CMOVB32rr: case X86::CMOVB32rm:
1889 case X86::CMOVB64rr: case X86::CMOVB64rm:
1890 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1891 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1892 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1893 case X86::CMOVE16rr: case X86::CMOVE16rm:
1894 case X86::CMOVE32rr: case X86::CMOVE32rm:
1895 case X86::CMOVE64rr: case X86::CMOVE64rm:
1896 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1897 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1898 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1899 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1900 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1901 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1902 case X86::CMOVP16rr: case X86::CMOVP16rm:
1903 case X86::CMOVP32rr: case X86::CMOVP32rm:
1904 case X86::CMOVP64rr: case X86::CMOVP64rm:
1906 // Anything else: assume conservatively.
1907 default: return false;
1914 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1915 /// is suitable for doing the {load; increment or decrement; store} to modify
1917 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1918 SDValue StoredVal, SelectionDAG *CurDAG,
1919 LoadSDNode* &LoadNode, SDValue &InputChain) {
1921 // is the value stored the result of a DEC or INC?
1922 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1924 // is the stored value result 0 of the load?
1925 if (StoredVal.getResNo() != 0) return false;
1927 // are there other uses of the loaded value than the inc or dec?
1928 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1930 // is the store non-extending and non-indexed?
1931 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1934 SDValue Load = StoredVal->getOperand(0);
1935 // Is the stored value a non-extending and non-indexed load?
1936 if (!ISD::isNormalLoad(Load.getNode())) return false;
1938 // Return LoadNode by reference.
1939 LoadNode = cast<LoadSDNode>(Load);
1940 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1941 EVT LdVT = LoadNode->getMemoryVT();
1942 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1946 // Is store the only read of the loaded value?
1947 if (!Load.hasOneUse())
1950 // Is the address of the store the same as the load?
1951 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1952 LoadNode->getOffset() != StoreNode->getOffset())
1955 // Check if the chain is produced by the load or is a TokenFactor with
1956 // the load output chain as an operand. Return InputChain by reference.
1957 SDValue Chain = StoreNode->getChain();
1959 bool ChainCheck = false;
1960 if (Chain == Load.getValue(1)) {
1962 InputChain = LoadNode->getChain();
1963 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1964 SmallVector<SDValue, 4> ChainOps;
1965 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1966 SDValue Op = Chain.getOperand(i);
1967 if (Op == Load.getValue(1)) {
1972 // Make sure using Op as part of the chain would not cause a cycle here.
1973 // In theory, we could check whether the chain node is a predecessor of
1974 // the load. But that can be very expensive. Instead visit the uses and
1975 // make sure they all have smaller node id than the load.
1976 int LoadId = LoadNode->getNodeId();
1977 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1978 UE = UI->use_end(); UI != UE; ++UI) {
1979 if (UI.getUse().getResNo() != 0)
1981 if (UI->getNodeId() > LoadId)
1985 ChainOps.push_back(Op);
1989 // Make a new TokenFactor with all the other input chains except
1991 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
1992 MVT::Other, &ChainOps[0], ChainOps.size());
2000 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2001 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2002 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2003 if (Opc == X86ISD::DEC) {
2004 if (LdVT == MVT::i64) return X86::DEC64m;
2005 if (LdVT == MVT::i32) return X86::DEC32m;
2006 if (LdVT == MVT::i16) return X86::DEC16m;
2007 if (LdVT == MVT::i8) return X86::DEC8m;
2009 assert(Opc == X86ISD::INC && "unrecognized opcode");
2010 if (LdVT == MVT::i64) return X86::INC64m;
2011 if (LdVT == MVT::i32) return X86::INC32m;
2012 if (LdVT == MVT::i16) return X86::INC16m;
2013 if (LdVT == MVT::i8) return X86::INC8m;
2015 llvm_unreachable("unrecognized size for LdVT");
2018 /// SelectGather - Customized ISel for GATHER operations.
2020 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2021 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2022 SDValue Chain = Node->getOperand(0);
2023 SDValue VSrc = Node->getOperand(2);
2024 SDValue Base = Node->getOperand(3);
2025 SDValue VIdx = Node->getOperand(4);
2026 SDValue VMask = Node->getOperand(5);
2027 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2031 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2034 // Memory Operands: Base, Scale, Index, Disp, Segment
2035 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
2036 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2037 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
2038 Disp, Segment, VMask, Chain};
2039 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
2040 // Node has 2 outputs: VDst and MVT::Other.
2041 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2042 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2044 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2045 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2049 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2050 EVT NVT = Node->getValueType(0);
2052 unsigned Opcode = Node->getOpcode();
2055 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2057 if (Node->isMachineOpcode()) {
2058 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2059 return NULL; // Already selected.
2064 case ISD::INTRINSIC_W_CHAIN: {
2065 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2068 case Intrinsic::x86_avx2_gather_d_pd:
2069 case Intrinsic::x86_avx2_gather_d_pd_256:
2070 case Intrinsic::x86_avx2_gather_q_pd:
2071 case Intrinsic::x86_avx2_gather_q_pd_256:
2072 case Intrinsic::x86_avx2_gather_d_ps:
2073 case Intrinsic::x86_avx2_gather_d_ps_256:
2074 case Intrinsic::x86_avx2_gather_q_ps:
2075 case Intrinsic::x86_avx2_gather_q_ps_256:
2076 case Intrinsic::x86_avx2_gather_d_q:
2077 case Intrinsic::x86_avx2_gather_d_q_256:
2078 case Intrinsic::x86_avx2_gather_q_q:
2079 case Intrinsic::x86_avx2_gather_q_q_256:
2080 case Intrinsic::x86_avx2_gather_d_d:
2081 case Intrinsic::x86_avx2_gather_d_d_256:
2082 case Intrinsic::x86_avx2_gather_q_d:
2083 case Intrinsic::x86_avx2_gather_q_d_256: {
2084 if (!Subtarget->hasAVX2())
2088 default: llvm_unreachable("Impossible intrinsic");
2089 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2090 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2091 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2092 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2093 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2094 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2095 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2096 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2097 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2098 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2099 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2100 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2101 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2102 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2103 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2104 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2106 SDNode *RetVal = SelectGather(Node, Opc);
2108 // We already called ReplaceUses inside SelectGather.
2115 case X86ISD::GlobalBaseReg:
2116 return getGlobalBaseReg();
2119 case X86ISD::ATOMOR64_DAG:
2120 case X86ISD::ATOMXOR64_DAG:
2121 case X86ISD::ATOMADD64_DAG:
2122 case X86ISD::ATOMSUB64_DAG:
2123 case X86ISD::ATOMNAND64_DAG:
2124 case X86ISD::ATOMAND64_DAG:
2125 case X86ISD::ATOMMAX64_DAG:
2126 case X86ISD::ATOMMIN64_DAG:
2127 case X86ISD::ATOMUMAX64_DAG:
2128 case X86ISD::ATOMUMIN64_DAG:
2129 case X86ISD::ATOMSWAP64_DAG: {
2132 default: llvm_unreachable("Impossible opcode");
2133 case X86ISD::ATOMOR64_DAG: Opc = X86::ATOMOR6432; break;
2134 case X86ISD::ATOMXOR64_DAG: Opc = X86::ATOMXOR6432; break;
2135 case X86ISD::ATOMADD64_DAG: Opc = X86::ATOMADD6432; break;
2136 case X86ISD::ATOMSUB64_DAG: Opc = X86::ATOMSUB6432; break;
2137 case X86ISD::ATOMNAND64_DAG: Opc = X86::ATOMNAND6432; break;
2138 case X86ISD::ATOMAND64_DAG: Opc = X86::ATOMAND6432; break;
2139 case X86ISD::ATOMMAX64_DAG: Opc = X86::ATOMMAX6432; break;
2140 case X86ISD::ATOMMIN64_DAG: Opc = X86::ATOMMIN6432; break;
2141 case X86ISD::ATOMUMAX64_DAG: Opc = X86::ATOMUMAX6432; break;
2142 case X86ISD::ATOMUMIN64_DAG: Opc = X86::ATOMUMIN6432; break;
2143 case X86ISD::ATOMSWAP64_DAG: Opc = X86::ATOMSWAP6432; break;
2145 SDNode *RetVal = SelectAtomic64(Node, Opc);
2151 case ISD::ATOMIC_LOAD_XOR:
2152 case ISD::ATOMIC_LOAD_AND:
2153 case ISD::ATOMIC_LOAD_OR:
2154 case ISD::ATOMIC_LOAD_ADD: {
2155 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2163 // For operations of the form (x << C1) op C2, check if we can use a smaller
2164 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2165 SDValue N0 = Node->getOperand(0);
2166 SDValue N1 = Node->getOperand(1);
2168 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2171 // i8 is unshrinkable, i16 should be promoted to i32.
2172 if (NVT != MVT::i32 && NVT != MVT::i64)
2175 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2176 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2177 if (!Cst || !ShlCst)
2180 int64_t Val = Cst->getSExtValue();
2181 uint64_t ShlVal = ShlCst->getZExtValue();
2183 // Make sure that we don't change the operation by removing bits.
2184 // This only matters for OR and XOR, AND is unaffected.
2185 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2186 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2192 // Check the minimum bitwidth for the new constant.
2193 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2194 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2195 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2196 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2198 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2201 // Bail if there is no smaller encoding.
2205 switch (NVT.getSimpleVT().SimpleTy) {
2206 default: llvm_unreachable("Unsupported VT!");
2208 assert(CstVT == MVT::i8);
2209 ShlOp = X86::SHL32ri;
2212 default: llvm_unreachable("Impossible opcode");
2213 case ISD::AND: Op = X86::AND32ri8; break;
2214 case ISD::OR: Op = X86::OR32ri8; break;
2215 case ISD::XOR: Op = X86::XOR32ri8; break;
2219 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2220 ShlOp = X86::SHL64ri;
2223 default: llvm_unreachable("Impossible opcode");
2224 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2225 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2226 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2231 // Emit the smaller op and the shift.
2232 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2233 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2234 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2237 case X86ISD::UMUL: {
2238 SDValue N0 = Node->getOperand(0);
2239 SDValue N1 = Node->getOperand(1);
2242 switch (NVT.getSimpleVT().SimpleTy) {
2243 default: llvm_unreachable("Unsupported VT!");
2244 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2245 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2246 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2247 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2250 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2251 N0, SDValue()).getValue(1);
2253 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2254 SDValue Ops[] = {N1, InFlag};
2255 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2257 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2258 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2259 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2263 case ISD::SMUL_LOHI:
2264 case ISD::UMUL_LOHI: {
2265 SDValue N0 = Node->getOperand(0);
2266 SDValue N1 = Node->getOperand(1);
2268 bool isSigned = Opcode == ISD::SMUL_LOHI;
2269 bool hasBMI2 = Subtarget->hasBMI2();
2271 switch (NVT.getSimpleVT().SimpleTy) {
2272 default: llvm_unreachable("Unsupported VT!");
2273 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2274 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2275 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2276 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2277 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2278 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2281 switch (NVT.getSimpleVT().SimpleTy) {
2282 default: llvm_unreachable("Unsupported VT!");
2283 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2284 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2285 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2286 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2290 unsigned SrcReg, LoReg, HiReg;
2292 default: llvm_unreachable("Unknown MUL opcode!");
2295 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2299 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2303 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2307 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2310 SrcReg = X86::EDX; LoReg = HiReg = 0;
2313 SrcReg = X86::RDX; LoReg = HiReg = 0;
2317 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2318 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2319 // Multiply is commmutative.
2321 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2326 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2327 N0, SDValue()).getValue(1);
2328 SDValue ResHi, ResLo;
2332 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2334 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2335 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2336 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2337 ResHi = SDValue(CNode, 0);
2338 ResLo = SDValue(CNode, 1);
2339 Chain = SDValue(CNode, 2);
2340 InFlag = SDValue(CNode, 3);
2342 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2343 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2344 Chain = SDValue(CNode, 0);
2345 InFlag = SDValue(CNode, 1);
2348 // Update the chain.
2349 ReplaceUses(N1.getValue(1), Chain);
2351 SDValue Ops[] = { N1, InFlag };
2352 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2353 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2354 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2355 ResHi = SDValue(CNode, 0);
2356 ResLo = SDValue(CNode, 1);
2357 InFlag = SDValue(CNode, 2);
2359 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2360 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2361 InFlag = SDValue(CNode, 0);
2365 // Prevent use of AH in a REX instruction by referencing AX instead.
2366 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2367 !SDValue(Node, 1).use_empty()) {
2368 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2369 X86::AX, MVT::i16, InFlag);
2370 InFlag = Result.getValue(2);
2371 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2373 if (!SDValue(Node, 0).use_empty())
2374 ReplaceUses(SDValue(Node, 1),
2375 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2377 // Shift AX down 8 bits.
2378 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2380 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2381 // Then truncate it down to i8.
2382 ReplaceUses(SDValue(Node, 1),
2383 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2385 // Copy the low half of the result, if it is needed.
2386 if (!SDValue(Node, 0).use_empty()) {
2387 if (ResLo.getNode() == 0) {
2388 assert(LoReg && "Register for low half is not defined!");
2389 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2391 InFlag = ResLo.getValue(2);
2393 ReplaceUses(SDValue(Node, 0), ResLo);
2394 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2396 // Copy the high half of the result, if it is needed.
2397 if (!SDValue(Node, 1).use_empty()) {
2398 if (ResHi.getNode() == 0) {
2399 assert(HiReg && "Register for high half is not defined!");
2400 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2402 InFlag = ResHi.getValue(2);
2404 ReplaceUses(SDValue(Node, 1), ResHi);
2405 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2412 case ISD::UDIVREM: {
2413 SDValue N0 = Node->getOperand(0);
2414 SDValue N1 = Node->getOperand(1);
2416 bool isSigned = Opcode == ISD::SDIVREM;
2418 switch (NVT.getSimpleVT().SimpleTy) {
2419 default: llvm_unreachable("Unsupported VT!");
2420 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2421 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2422 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2423 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2426 switch (NVT.getSimpleVT().SimpleTy) {
2427 default: llvm_unreachable("Unsupported VT!");
2428 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2429 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2430 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2431 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2435 unsigned LoReg, HiReg, ClrReg;
2436 unsigned SExtOpcode;
2437 switch (NVT.getSimpleVT().SimpleTy) {
2438 default: llvm_unreachable("Unsupported VT!");
2440 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2441 SExtOpcode = X86::CBW;
2444 LoReg = X86::AX; HiReg = X86::DX;
2446 SExtOpcode = X86::CWD;
2449 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2450 SExtOpcode = X86::CDQ;
2453 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2454 SExtOpcode = X86::CQO;
2458 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2459 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2460 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2463 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2464 // Special case for div8, just use a move with zero extension to AX to
2465 // clear the upper 8 bits (AH).
2466 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2467 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2468 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2470 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2471 MVT::Other, Ops), 0);
2472 Chain = Move.getValue(1);
2473 ReplaceUses(N0.getValue(1), Chain);
2476 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2477 Chain = CurDAG->getEntryNode();
2479 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2480 InFlag = Chain.getValue(1);
2483 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2484 LoReg, N0, SDValue()).getValue(1);
2485 if (isSigned && !signBitIsZero) {
2486 // Sign extend the low part into the high part.
2488 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2490 // Zero out the high part, effectively zero extending the input.
2491 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2492 switch (NVT.getSimpleVT().SimpleTy) {
2495 SDValue(CurDAG->getMachineNode(
2496 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2497 CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
2504 SDValue(CurDAG->getMachineNode(
2505 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2506 CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
2507 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2511 llvm_unreachable("Unexpected division source");
2514 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2515 ClrNode, InFlag).getValue(1);
2520 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2523 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2524 InFlag = SDValue(CNode, 1);
2525 // Update the chain.
2526 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2529 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2532 // Prevent use of AH in a REX instruction by referencing AX instead.
2533 // Shift it down 8 bits.
2534 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2535 !SDValue(Node, 1).use_empty()) {
2536 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2537 X86::AX, MVT::i16, InFlag);
2538 InFlag = Result.getValue(2);
2540 // If we also need AL (the quotient), get it by extracting a subreg from
2541 // Result. The fast register allocator does not like multiple CopyFromReg
2542 // nodes using aliasing registers.
2543 if (!SDValue(Node, 0).use_empty())
2544 ReplaceUses(SDValue(Node, 0),
2545 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2547 // Shift AX right by 8 bits instead of using AH.
2548 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2550 CurDAG->getTargetConstant(8, MVT::i8)),
2552 ReplaceUses(SDValue(Node, 1),
2553 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2555 // Copy the division (low) result, if it is needed.
2556 if (!SDValue(Node, 0).use_empty()) {
2557 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2558 LoReg, NVT, InFlag);
2559 InFlag = Result.getValue(2);
2560 ReplaceUses(SDValue(Node, 0), Result);
2561 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2563 // Copy the remainder (high) result, if it is needed.
2564 if (!SDValue(Node, 1).use_empty()) {
2565 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2566 HiReg, NVT, InFlag);
2567 InFlag = Result.getValue(2);
2568 ReplaceUses(SDValue(Node, 1), Result);
2569 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2576 // Sometimes a SUB is used to perform comparison.
2577 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2578 // This node is not a CMP.
2580 SDValue N0 = Node->getOperand(0);
2581 SDValue N1 = Node->getOperand(1);
2583 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2584 // use a smaller encoding.
2585 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2586 HasNoSignedComparisonUses(Node))
2587 // Look past the truncate if CMP is the only use of it.
2588 N0 = N0.getOperand(0);
2589 if ((N0.getNode()->getOpcode() == ISD::AND ||
2590 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2591 N0.getNode()->hasOneUse() &&
2592 N0.getValueType() != MVT::i8 &&
2593 X86::isZeroNode(N1)) {
2594 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2597 // For example, convert "testl %eax, $8" to "testb %al, $8"
2598 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2599 (!(C->getZExtValue() & 0x80) ||
2600 HasNoSignedComparisonUses(Node))) {
2601 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2602 SDValue Reg = N0.getNode()->getOperand(0);
2604 // On x86-32, only the ABCD registers have 8-bit subregisters.
2605 if (!Subtarget->is64Bit()) {
2606 const TargetRegisterClass *TRC;
2607 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2608 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2609 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2610 default: llvm_unreachable("Unsupported TEST operand type!");
2612 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2613 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2614 Reg.getValueType(), Reg, RC), 0);
2617 // Extract the l-register.
2618 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2622 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2624 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2625 // one, do not call ReplaceAllUsesWith.
2626 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2627 SDValue(NewNode, 0));
2631 // For example, "testl %eax, $2048" to "testb %ah, $8".
2632 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2633 (!(C->getZExtValue() & 0x8000) ||
2634 HasNoSignedComparisonUses(Node))) {
2635 // Shift the immediate right by 8 bits.
2636 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2638 SDValue Reg = N0.getNode()->getOperand(0);
2640 // Put the value in an ABCD register.
2641 const TargetRegisterClass *TRC;
2642 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2643 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2644 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2645 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2646 default: llvm_unreachable("Unsupported TEST operand type!");
2648 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2649 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2650 Reg.getValueType(), Reg, RC), 0);
2652 // Extract the h-register.
2653 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2656 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2657 // target GR8_NOREX registers, so make sure the register class is
2659 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2660 MVT::i32, Subreg, ShiftedImm);
2661 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2662 // one, do not call ReplaceAllUsesWith.
2663 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2664 SDValue(NewNode, 0));
2668 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2669 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2670 N0.getValueType() != MVT::i16 &&
2671 (!(C->getZExtValue() & 0x8000) ||
2672 HasNoSignedComparisonUses(Node))) {
2673 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2674 SDValue Reg = N0.getNode()->getOperand(0);
2676 // Extract the 16-bit subregister.
2677 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2681 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2683 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2684 // one, do not call ReplaceAllUsesWith.
2685 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2686 SDValue(NewNode, 0));
2690 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2691 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2692 N0.getValueType() == MVT::i64 &&
2693 (!(C->getZExtValue() & 0x80000000) ||
2694 HasNoSignedComparisonUses(Node))) {
2695 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2696 SDValue Reg = N0.getNode()->getOperand(0);
2698 // Extract the 32-bit subregister.
2699 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2703 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2705 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2706 // one, do not call ReplaceAllUsesWith.
2707 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2708 SDValue(NewNode, 0));
2715 // Change a chain of {load; incr or dec; store} of the same value into
2716 // a simple increment or decrement through memory of that value, if the
2717 // uses of the modified value and its address are suitable.
2718 // The DEC64m tablegen pattern is currently not able to match the case where
2719 // the EFLAGS on the original DEC are used. (This also applies to
2720 // {INC,DEC}X{64,32,16,8}.)
2721 // We'll need to improve tablegen to allow flags to be transferred from a
2722 // node in the pattern to the result node. probably with a new keyword
2723 // for example, we have this
2724 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2725 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2726 // (implicit EFLAGS)]>;
2727 // but maybe need something like this
2728 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2729 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2730 // (transferrable EFLAGS)]>;
2732 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2733 SDValue StoredVal = StoreNode->getOperand(1);
2734 unsigned Opc = StoredVal->getOpcode();
2736 LoadSDNode *LoadNode = 0;
2738 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2739 LoadNode, InputChain))
2742 SDValue Base, Scale, Index, Disp, Segment;
2743 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2744 Base, Scale, Index, Disp, Segment))
2747 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2748 MemOp[0] = StoreNode->getMemOperand();
2749 MemOp[1] = LoadNode->getMemOperand();
2750 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2751 EVT LdVT = LoadNode->getMemoryVT();
2752 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2753 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2755 MVT::i32, MVT::Other, Ops);
2756 Result->setMemRefs(MemOp, MemOp + 2);
2758 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2759 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2765 SDNode *ResNode = SelectCode(Node);
2767 DEBUG(dbgs() << "=> ";
2768 if (ResNode == NULL || ResNode == Node)
2771 ResNode->dump(CurDAG);
2777 bool X86DAGToDAGISel::
2778 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2779 std::vector<SDValue> &OutOps) {
2780 SDValue Op0, Op1, Op2, Op3, Op4;
2781 switch (ConstraintCode) {
2782 case 'o': // offsetable ??
2783 case 'v': // not offsetable ??
2784 default: return true;
2786 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
2791 OutOps.push_back(Op0);
2792 OutOps.push_back(Op1);
2793 OutOps.push_back(Op2);
2794 OutOps.push_back(Op3);
2795 OutOps.push_back(Op4);
2799 /// createX86ISelDag - This pass converts a legalized DAG into a
2800 /// X86-specific DAG, ready for instruction scheduling.
2802 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2803 CodeGenOpt::Level OptLevel) {
2804 return new X86DAGToDAGISel(TM, OptLevel);