1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
39 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
41 //===----------------------------------------------------------------------===//
42 // Pattern Matcher Implementation
43 //===----------------------------------------------------------------------===//
46 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
47 /// SDValue's instead of register numbers for the leaves of the matched
49 struct X86ISelAddressMode {
55 // This is really a union, discriminated by BaseType!
63 const GlobalValue *GV;
65 const BlockAddress *BlockAddr;
68 unsigned Align; // CP alignment.
69 unsigned char SymbolFlags; // X86II::MO_*
72 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
73 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
74 SymbolFlags(X86II::MO_NO_FLAG) {
77 bool hasSymbolicDisplacement() const {
78 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
81 bool hasBaseOrIndexReg() const {
82 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
85 /// isRIPRelative - Return true if this addressing mode is already RIP
87 bool isRIPRelative() const {
88 if (BaseType != RegBase) return false;
89 if (RegisterSDNode *RegNode =
90 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
91 return RegNode->getReg() == X86::RIP;
95 void setBaseReg(SDValue Reg) {
100 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
102 dbgs() << "X86ISelAddressMode " << this << '\n';
103 dbgs() << "Base_Reg ";
104 if (Base_Reg.getNode() != 0)
105 Base_Reg.getNode()->dump();
108 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
109 << " Scale" << Scale << '\n'
111 if (IndexReg.getNode() != 0)
112 IndexReg.getNode()->dump();
115 dbgs() << " Disp " << Disp << '\n'
132 dbgs() << " JT" << JT << " Align" << Align << '\n';
139 //===--------------------------------------------------------------------===//
140 /// ISel - X86 specific code to select X86 machine instructions for
141 /// SelectionDAG operations.
143 class X86DAGToDAGISel : public SelectionDAGISel {
144 /// X86Lowering - This object fully describes how to lower LLVM code to an
145 /// X86-specific SelectionDAG.
146 const X86TargetLowering &X86Lowering;
148 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
149 /// make the right decision when generating code for different targets.
150 const X86Subtarget *Subtarget;
152 /// OptForSize - If true, selector should try to optimize for code size
153 /// instead of performance.
157 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
158 : SelectionDAGISel(tm, OptLevel),
159 X86Lowering(*tm.getTargetLowering()),
160 Subtarget(&tm.getSubtarget<X86Subtarget>()),
163 virtual const char *getPassName() const {
164 return "X86 DAG->DAG Instruction Selection";
167 virtual void EmitFunctionEntryCode();
169 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
171 virtual void PreprocessISelDAG();
173 inline bool immSext8(SDNode *N) const {
174 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
177 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
178 // sign extended field.
179 inline bool i64immSExt32(SDNode *N) const {
180 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
181 return (int64_t)v == (int32_t)v;
184 // Include the pieces autogenerated from the target description.
185 #include "X86GenDAGISel.inc"
188 SDNode *Select(SDNode *N);
189 SDNode *SelectGather(SDNode *N, unsigned Opc);
190 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
191 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT);
193 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
194 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
195 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
196 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
197 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
199 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
200 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
201 SDValue &Scale, SDValue &Index, SDValue &Disp,
203 bool SelectLEAAddr(SDValue N, SDValue &Base,
204 SDValue &Scale, SDValue &Index, SDValue &Disp,
206 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
207 SDValue &Scale, SDValue &Index, SDValue &Disp,
209 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
210 SDValue &Base, SDValue &Scale,
211 SDValue &Index, SDValue &Disp,
213 SDValue &NodeWithChain);
215 bool TryFoldLoad(SDNode *P, SDValue N,
216 SDValue &Base, SDValue &Scale,
217 SDValue &Index, SDValue &Disp,
220 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
221 /// inline asm expressions.
222 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
224 std::vector<SDValue> &OutOps);
226 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
228 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
229 SDValue &Scale, SDValue &Index,
230 SDValue &Disp, SDValue &Segment) {
231 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
232 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
234 Scale = getI8Imm(AM.Scale);
236 // These are 32-bit even in 64-bit mode since RIP relative offset
239 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(),
243 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
244 AM.Align, AM.Disp, AM.SymbolFlags);
246 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
247 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
248 } else if (AM.JT != -1) {
249 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
250 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
251 } else if (AM.BlockAddr)
252 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
255 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
257 if (AM.Segment.getNode())
258 Segment = AM.Segment;
260 Segment = CurDAG->getRegister(0, MVT::i32);
263 /// getI8Imm - Return a target constant with the specified value, of type
265 inline SDValue getI8Imm(unsigned Imm) {
266 return CurDAG->getTargetConstant(Imm, MVT::i8);
269 /// getI32Imm - Return a target constant with the specified value, of type
271 inline SDValue getI32Imm(unsigned Imm) {
272 return CurDAG->getTargetConstant(Imm, MVT::i32);
275 /// getGlobalBaseReg - Return an SDNode that returns the value of
276 /// the global base register. Output instructions required to
277 /// initialize the global base register, if necessary.
279 SDNode *getGlobalBaseReg();
281 /// getTargetMachine - Return a reference to the TargetMachine, casted
282 /// to the target-specific type.
283 const X86TargetMachine &getTargetMachine() const {
284 return static_cast<const X86TargetMachine &>(TM);
287 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
288 /// to the target-specific type.
289 const X86InstrInfo *getInstrInfo() const {
290 return getTargetMachine().getInstrInfo();
297 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
298 if (OptLevel == CodeGenOpt::None) return false;
303 if (N.getOpcode() != ISD::LOAD)
306 // If N is a load, do additional profitability checks.
308 switch (U->getOpcode()) {
321 SDValue Op1 = U->getOperand(1);
323 // If the other operand is a 8-bit immediate we should fold the immediate
324 // instead. This reduces code size.
326 // movl 4(%esp), %eax
330 // addl 4(%esp), %eax
331 // The former is 2 bytes shorter. In case where the increment is 1, then
332 // the saving can be 4 bytes (by using incl %eax).
333 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
334 if (Imm->getAPIntValue().isSignedIntN(8))
337 // If the other operand is a TLS address, we should fold it instead.
340 // leal i@NTPOFF(%eax), %eax
342 // movl $i@NTPOFF, %eax
344 // if the block also has an access to a second TLS address this will save
346 // FIXME: This is probably also true for non TLS addresses.
347 if (Op1.getOpcode() == X86ISD::Wrapper) {
348 SDValue Val = Op1.getOperand(0);
349 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
359 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
360 /// load's chain operand and move load below the call's chain operand.
361 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
362 SDValue Call, SDValue OrigChain) {
363 SmallVector<SDValue, 8> Ops;
364 SDValue Chain = OrigChain.getOperand(0);
365 if (Chain.getNode() == Load.getNode())
366 Ops.push_back(Load.getOperand(0));
368 assert(Chain.getOpcode() == ISD::TokenFactor &&
369 "Unexpected chain operand");
370 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
371 if (Chain.getOperand(i).getNode() == Load.getNode())
372 Ops.push_back(Load.getOperand(0));
374 Ops.push_back(Chain.getOperand(i));
376 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
377 MVT::Other, &Ops[0], Ops.size());
379 Ops.push_back(NewChain);
381 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
382 Ops.push_back(OrigChain.getOperand(i));
383 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
384 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
385 Load.getOperand(1), Load.getOperand(2));
387 unsigned NumOps = Call.getNode()->getNumOperands();
389 Ops.push_back(SDValue(Load.getNode(), 1));
390 for (unsigned i = 1, e = NumOps; i != e; ++i)
391 Ops.push_back(Call.getOperand(i));
392 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], NumOps);
395 /// isCalleeLoad - Return true if call address is a load and it can be
396 /// moved below CALLSEQ_START and the chains leading up to the call.
397 /// Return the CALLSEQ_START by reference as a second output.
398 /// In the case of a tail call, there isn't a callseq node between the call
399 /// chain and the load.
400 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
401 // The transformation is somewhat dangerous if the call's chain was glued to
402 // the call. After MoveBelowOrigChain the load is moved between the call and
403 // the chain, this can create a cycle if the load is not folded. So it is
404 // *really* important that we are sure the load will be folded.
405 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
407 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
410 LD->getAddressingMode() != ISD::UNINDEXED ||
411 LD->getExtensionType() != ISD::NON_EXTLOAD)
414 // Now let's find the callseq_start.
415 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
416 if (!Chain.hasOneUse())
418 Chain = Chain.getOperand(0);
421 if (!Chain.getNumOperands())
423 // Since we are not checking for AA here, conservatively abort if the chain
424 // writes to memory. It's not safe to move the callee (a load) across a store.
425 if (isa<MemSDNode>(Chain.getNode()) &&
426 cast<MemSDNode>(Chain.getNode())->writeMem())
428 if (Chain.getOperand(0).getNode() == Callee.getNode())
430 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
431 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
432 Callee.getValue(1).hasOneUse())
437 void X86DAGToDAGISel::PreprocessISelDAG() {
438 // OptForSize is used in pattern predicates that isel is matching.
439 OptForSize = MF->getFunction()->getAttributes().
440 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
442 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
443 E = CurDAG->allnodes_end(); I != E; ) {
444 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
446 if (OptLevel != CodeGenOpt::None &&
447 // Only does this when target favors doesn't favor register indirect
449 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
450 (N->getOpcode() == X86ISD::TC_RETURN &&
451 // Only does this if load can be folded into TC_RETURN.
452 (Subtarget->is64Bit() ||
453 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
454 /// Also try moving call address load from outside callseq_start to just
455 /// before the call to allow it to be folded.
473 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
474 SDValue Chain = N->getOperand(0);
475 SDValue Load = N->getOperand(1);
476 if (!isCalleeLoad(Load, Chain, HasCallSeq))
478 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
483 // Lower fpround and fpextend nodes that target the FP stack to be store and
484 // load to the stack. This is a gross hack. We would like to simply mark
485 // these as being illegal, but when we do that, legalize produces these when
486 // it expands calls, then expands these in the same legalize pass. We would
487 // like dag combine to be able to hack on these between the call expansion
488 // and the node legalization. As such this pass basically does "really
489 // late" legalization of these inline with the X86 isel pass.
490 // FIXME: This should only happen when not compiled with -O0.
491 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
494 EVT SrcVT = N->getOperand(0).getValueType();
495 EVT DstVT = N->getValueType(0);
497 // If any of the sources are vectors, no fp stack involved.
498 if (SrcVT.isVector() || DstVT.isVector())
501 // If the source and destination are SSE registers, then this is a legal
502 // conversion that should not be lowered.
503 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
504 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
505 if (SrcIsSSE && DstIsSSE)
508 if (!SrcIsSSE && !DstIsSSE) {
509 // If this is an FPStack extension, it is a noop.
510 if (N->getOpcode() == ISD::FP_EXTEND)
512 // If this is a value-preserving FPStack truncation, it is a noop.
513 if (N->getConstantOperandVal(1))
517 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
518 // FPStack has extload and truncstore. SSE can fold direct loads into other
519 // operations. Based on this, decide what we want to do.
521 if (N->getOpcode() == ISD::FP_ROUND)
522 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
524 MemVT = SrcIsSSE ? SrcVT : DstVT;
526 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
527 DebugLoc dl = N->getDebugLoc();
529 // FIXME: optimize the case where the src/dest is a load or store?
530 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
532 MemTmp, MachinePointerInfo(), MemVT,
534 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
535 MachinePointerInfo(),
536 MemVT, false, false, 0);
538 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
539 // extload we created. This will cause general havok on the dag because
540 // anything below the conversion could be folded into other existing nodes.
541 // To avoid invalidating 'I', back it up to the convert node.
543 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
545 // Now that we did that, the node is dead. Increment the iterator to the
546 // next node to process, then delete N.
548 CurDAG->DeleteNode(N);
553 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
554 /// the main function.
555 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
556 MachineFrameInfo *MFI) {
557 const TargetInstrInfo *TII = TM.getInstrInfo();
558 if (Subtarget->isTargetCygMing()) {
560 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
561 BuildMI(BB, DebugLoc(),
562 TII->get(CallOp)).addExternalSymbol("__main");
566 void X86DAGToDAGISel::EmitFunctionEntryCode() {
567 // If this is main, emit special code for main.
568 if (const Function *Fn = MF->getFunction())
569 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
570 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
573 static bool isDispSafeForFrameIndex(int64_t Val) {
574 // On 64-bit platforms, we can run into an issue where a frame index
575 // includes a displacement that, when added to the explicit displacement,
576 // will overflow the displacement field. Assuming that the frame index
577 // displacement fits into a 31-bit integer (which is only slightly more
578 // aggressive than the current fundamental assumption that it fits into
579 // a 32-bit integer), a 31-bit disp should always be safe.
580 return isInt<31>(Val);
583 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
584 X86ISelAddressMode &AM) {
585 int64_t Val = AM.Disp + Offset;
586 CodeModel::Model M = TM.getCodeModel();
587 if (Subtarget->is64Bit()) {
588 if (!X86::isOffsetSuitableForCodeModel(Val, M,
589 AM.hasSymbolicDisplacement()))
591 // In addition to the checks required for a register base, check that
592 // we do not try to use an unsafe Disp with a frame index.
593 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
594 !isDispSafeForFrameIndex(Val))
602 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
603 SDValue Address = N->getOperand(1);
605 // load gs:0 -> GS segment register.
606 // load fs:0 -> FS segment register.
608 // This optimization is valid because the GNU TLS model defines that
609 // gs:0 (or fs:0 on X86-64) contains its own address.
610 // For more information see http://people.redhat.com/drepper/tls.pdf
611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
612 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
613 Subtarget->isTargetLinux())
614 switch (N->getPointerInfo().getAddrSpace()) {
616 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
619 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
626 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
627 /// into an addressing mode. These wrap things that will resolve down into a
628 /// symbol reference. If no match is possible, this returns true, otherwise it
630 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
631 // If the addressing mode already has a symbol as the displacement, we can
632 // never match another symbol.
633 if (AM.hasSymbolicDisplacement())
636 SDValue N0 = N.getOperand(0);
637 CodeModel::Model M = TM.getCodeModel();
639 // Handle X86-64 rip-relative addresses. We check this before checking direct
640 // folding because RIP is preferable to non-RIP accesses.
641 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
642 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
643 // they cannot be folded into immediate fields.
644 // FIXME: This can be improved for kernel and other models?
645 (M == CodeModel::Small || M == CodeModel::Kernel)) {
646 // Base and index reg must be 0 in order to use %rip as base.
647 if (AM.hasBaseOrIndexReg())
649 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
650 X86ISelAddressMode Backup = AM;
651 AM.GV = G->getGlobal();
652 AM.SymbolFlags = G->getTargetFlags();
653 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
657 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
658 X86ISelAddressMode Backup = AM;
659 AM.CP = CP->getConstVal();
660 AM.Align = CP->getAlignment();
661 AM.SymbolFlags = CP->getTargetFlags();
662 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
666 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
667 AM.ES = S->getSymbol();
668 AM.SymbolFlags = S->getTargetFlags();
669 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
670 AM.JT = J->getIndex();
671 AM.SymbolFlags = J->getTargetFlags();
672 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
673 X86ISelAddressMode Backup = AM;
674 AM.BlockAddr = BA->getBlockAddress();
675 AM.SymbolFlags = BA->getTargetFlags();
676 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
681 llvm_unreachable("Unhandled symbol reference node.");
683 if (N.getOpcode() == X86ISD::WrapperRIP)
684 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
688 // Handle the case when globals fit in our immediate field: This is true for
689 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
690 // mode, this only applies to a non-RIP-relative computation.
691 if (!Subtarget->is64Bit() ||
692 M == CodeModel::Small || M == CodeModel::Kernel) {
693 assert(N.getOpcode() != X86ISD::WrapperRIP &&
694 "RIP-relative addressing already handled");
695 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
696 AM.GV = G->getGlobal();
697 AM.Disp += G->getOffset();
698 AM.SymbolFlags = G->getTargetFlags();
699 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
700 AM.CP = CP->getConstVal();
701 AM.Align = CP->getAlignment();
702 AM.Disp += CP->getOffset();
703 AM.SymbolFlags = CP->getTargetFlags();
704 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
705 AM.ES = S->getSymbol();
706 AM.SymbolFlags = S->getTargetFlags();
707 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
708 AM.JT = J->getIndex();
709 AM.SymbolFlags = J->getTargetFlags();
710 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
711 AM.BlockAddr = BA->getBlockAddress();
712 AM.Disp += BA->getOffset();
713 AM.SymbolFlags = BA->getTargetFlags();
715 llvm_unreachable("Unhandled symbol reference node.");
722 /// MatchAddress - Add the specified node to the specified addressing mode,
723 /// returning true if it cannot be done. This just pattern matches for the
725 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
726 if (MatchAddressRecursively(N, AM, 0))
729 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
730 // a smaller encoding and avoids a scaled-index.
732 AM.BaseType == X86ISelAddressMode::RegBase &&
733 AM.Base_Reg.getNode() == 0) {
734 AM.Base_Reg = AM.IndexReg;
738 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
739 // because it has a smaller encoding.
740 // TODO: Which other code models can use this?
741 if (TM.getCodeModel() == CodeModel::Small &&
742 Subtarget->is64Bit() &&
744 AM.BaseType == X86ISelAddressMode::RegBase &&
745 AM.Base_Reg.getNode() == 0 &&
746 AM.IndexReg.getNode() == 0 &&
747 AM.SymbolFlags == X86II::MO_NO_FLAG &&
748 AM.hasSymbolicDisplacement())
749 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
754 // Insert a node into the DAG at least before the Pos node's position. This
755 // will reposition the node as needed, and will assign it a node ID that is <=
756 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
757 // IDs! The selection DAG must no longer depend on their uniqueness when this
759 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
760 if (N.getNode()->getNodeId() == -1 ||
761 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
762 DAG.RepositionNode(Pos.getNode(), N.getNode());
763 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
767 // Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
768 // allows us to convert the shift and and into an h-register extract and
769 // a scaled index. Returns false if the simplification is performed.
770 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
772 SDValue Shift, SDValue X,
773 X86ISelAddressMode &AM) {
774 if (Shift.getOpcode() != ISD::SRL ||
775 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
779 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
780 if (ScaleLog <= 0 || ScaleLog >= 4 ||
781 Mask != (0xffu << ScaleLog))
784 EVT VT = N.getValueType();
785 DebugLoc DL = N.getDebugLoc();
786 SDValue Eight = DAG.getConstant(8, MVT::i8);
787 SDValue NewMask = DAG.getConstant(0xff, VT);
788 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
789 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
790 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
791 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
793 // Insert the new nodes into the topological ordering. We must do this in
794 // a valid topological ordering as nothing is going to go back and re-sort
795 // these nodes. We continually insert before 'N' in sequence as this is
796 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
797 // hierarchy left to express.
798 InsertDAGNode(DAG, N, Eight);
799 InsertDAGNode(DAG, N, Srl);
800 InsertDAGNode(DAG, N, NewMask);
801 InsertDAGNode(DAG, N, And);
802 InsertDAGNode(DAG, N, ShlCount);
803 InsertDAGNode(DAG, N, Shl);
804 DAG.ReplaceAllUsesWith(N, Shl);
806 AM.Scale = (1 << ScaleLog);
810 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
811 // allows us to fold the shift into this addressing mode. Returns false if the
812 // transform succeeded.
813 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
815 SDValue Shift, SDValue X,
816 X86ISelAddressMode &AM) {
817 if (Shift.getOpcode() != ISD::SHL ||
818 !isa<ConstantSDNode>(Shift.getOperand(1)))
821 // Not likely to be profitable if either the AND or SHIFT node has more
822 // than one use (unless all uses are for address computation). Besides,
823 // isel mechanism requires their node ids to be reused.
824 if (!N.hasOneUse() || !Shift.hasOneUse())
827 // Verify that the shift amount is something we can fold.
828 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
829 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
832 EVT VT = N.getValueType();
833 DebugLoc DL = N.getDebugLoc();
834 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
835 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
836 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
838 // Insert the new nodes into the topological ordering. We must do this in
839 // a valid topological ordering as nothing is going to go back and re-sort
840 // these nodes. We continually insert before 'N' in sequence as this is
841 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
842 // hierarchy left to express.
843 InsertDAGNode(DAG, N, NewMask);
844 InsertDAGNode(DAG, N, NewAnd);
845 InsertDAGNode(DAG, N, NewShift);
846 DAG.ReplaceAllUsesWith(N, NewShift);
848 AM.Scale = 1 << ShiftAmt;
849 AM.IndexReg = NewAnd;
853 // Implement some heroics to detect shifts of masked values where the mask can
854 // be replaced by extending the shift and undoing that in the addressing mode
855 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
856 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
857 // the addressing mode. This results in code such as:
859 // int f(short *y, int *lookup_table) {
861 // return *y + lookup_table[*y >> 11];
865 // movzwl (%rdi), %eax
868 // addl (%rsi,%rcx,4), %eax
871 // movzwl (%rdi), %eax
875 // addl (%rsi,%rcx), %eax
877 // Note that this function assumes the mask is provided as a mask *after* the
878 // value is shifted. The input chain may or may not match that, but computing
879 // such a mask is trivial.
880 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
882 SDValue Shift, SDValue X,
883 X86ISelAddressMode &AM) {
884 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
885 !isa<ConstantSDNode>(Shift.getOperand(1)))
888 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
889 unsigned MaskLZ = CountLeadingZeros_64(Mask);
890 unsigned MaskTZ = CountTrailingZeros_64(Mask);
892 // The amount of shift we're trying to fit into the addressing mode is taken
893 // from the trailing zeros of the mask.
894 unsigned AMShiftAmt = MaskTZ;
896 // There is nothing we can do here unless the mask is removing some bits.
897 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
898 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
900 // We also need to ensure that mask is a continuous run of bits.
901 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
903 // Scale the leading zero count down based on the actual size of the value.
904 // Also scale it down based on the size of the shift.
905 MaskLZ -= (64 - X.getValueSizeInBits()) + ShiftAmt;
907 // The final check is to ensure that any masked out high bits of X are
908 // already known to be zero. Otherwise, the mask has a semantic impact
909 // other than masking out a couple of low bits. Unfortunately, because of
910 // the mask, zero extensions will be removed from operands in some cases.
911 // This code works extra hard to look through extensions because we can
912 // replace them with zero extensions cheaply if necessary.
913 bool ReplacingAnyExtend = false;
914 if (X.getOpcode() == ISD::ANY_EXTEND) {
915 unsigned ExtendBits =
916 X.getValueSizeInBits() - X.getOperand(0).getValueSizeInBits();
917 // Assume that we'll replace the any-extend with a zero-extend, and
918 // narrow the search to the extended value.
920 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
921 ReplacingAnyExtend = true;
923 APInt MaskedHighBits = APInt::getHighBitsSet(X.getValueSizeInBits(),
925 APInt KnownZero, KnownOne;
926 DAG.ComputeMaskedBits(X, KnownZero, KnownOne);
927 if (MaskedHighBits != KnownZero) return true;
929 // We've identified a pattern that can be transformed into a single shift
930 // and an addressing mode. Make it so.
931 EVT VT = N.getValueType();
932 if (ReplacingAnyExtend) {
933 assert(X.getValueType() != VT);
934 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
935 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, X.getDebugLoc(), VT, X);
936 InsertDAGNode(DAG, N, NewX);
939 DebugLoc DL = N.getDebugLoc();
940 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
941 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
942 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
943 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
945 // Insert the new nodes into the topological ordering. We must do this in
946 // a valid topological ordering as nothing is going to go back and re-sort
947 // these nodes. We continually insert before 'N' in sequence as this is
948 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
949 // hierarchy left to express.
950 InsertDAGNode(DAG, N, NewSRLAmt);
951 InsertDAGNode(DAG, N, NewSRL);
952 InsertDAGNode(DAG, N, NewSHLAmt);
953 InsertDAGNode(DAG, N, NewSHL);
954 DAG.ReplaceAllUsesWith(N, NewSHL);
956 AM.Scale = 1 << AMShiftAmt;
957 AM.IndexReg = NewSRL;
961 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
963 DebugLoc dl = N.getDebugLoc();
965 dbgs() << "MatchAddress: ";
970 return MatchAddressBase(N, AM);
972 // If this is already a %rip relative address, we can only merge immediates
973 // into it. Instead of handling this in every case, we handle it here.
974 // RIP relative addressing: %rip + 32-bit displacement!
975 if (AM.isRIPRelative()) {
976 // FIXME: JumpTable and ExternalSymbol address currently don't like
977 // displacements. It isn't very important, but this should be fixed for
979 if (!AM.ES && AM.JT != -1) return true;
981 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
982 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
987 switch (N.getOpcode()) {
989 case ISD::Constant: {
990 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
991 if (!FoldOffsetIntoAddress(Val, AM))
996 case X86ISD::Wrapper:
997 case X86ISD::WrapperRIP:
998 if (!MatchWrapper(N, AM))
1003 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1007 case ISD::FrameIndex:
1008 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1009 AM.Base_Reg.getNode() == 0 &&
1010 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1011 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1012 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1018 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
1022 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1023 unsigned Val = CN->getZExtValue();
1024 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1025 // that the base operand remains free for further matching. If
1026 // the base doesn't end up getting used, a post-processing step
1027 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1028 if (Val == 1 || Val == 2 || Val == 3) {
1029 AM.Scale = 1 << Val;
1030 SDValue ShVal = N.getNode()->getOperand(0);
1032 // Okay, we know that we have a scale by now. However, if the scaled
1033 // value is an add of something and a constant, we can fold the
1034 // constant into the disp field here.
1035 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1036 AM.IndexReg = ShVal.getNode()->getOperand(0);
1037 ConstantSDNode *AddVal =
1038 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1039 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1040 if (!FoldOffsetIntoAddress(Disp, AM))
1044 AM.IndexReg = ShVal;
1051 // Scale must not be used already.
1052 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1054 SDValue And = N.getOperand(0);
1055 if (And.getOpcode() != ISD::AND) break;
1056 SDValue X = And.getOperand(0);
1058 // We only handle up to 64-bit values here as those are what matter for
1059 // addressing mode optimizations.
1060 if (X.getValueSizeInBits() > 64) break;
1062 // The mask used for the transform is expected to be post-shift, but we
1063 // found the shift first so just apply the shift to the mask before passing
1065 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1066 !isa<ConstantSDNode>(And.getOperand(1)))
1068 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1070 // Try to fold the mask and shift into the scale, and return false if we
1072 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1077 case ISD::SMUL_LOHI:
1078 case ISD::UMUL_LOHI:
1079 // A mul_lohi where we need the low part can be folded as a plain multiply.
1080 if (N.getResNo() != 0) break;
1083 case X86ISD::MUL_IMM:
1084 // X*[3,5,9] -> X+X*[2,4,8]
1085 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1086 AM.Base_Reg.getNode() == 0 &&
1087 AM.IndexReg.getNode() == 0) {
1089 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1090 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1091 CN->getZExtValue() == 9) {
1092 AM.Scale = unsigned(CN->getZExtValue())-1;
1094 SDValue MulVal = N.getNode()->getOperand(0);
1097 // Okay, we know that we have a scale by now. However, if the scaled
1098 // value is an add of something and a constant, we can fold the
1099 // constant into the disp field here.
1100 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1101 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1102 Reg = MulVal.getNode()->getOperand(0);
1103 ConstantSDNode *AddVal =
1104 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1105 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1106 if (FoldOffsetIntoAddress(Disp, AM))
1107 Reg = N.getNode()->getOperand(0);
1109 Reg = N.getNode()->getOperand(0);
1112 AM.IndexReg = AM.Base_Reg = Reg;
1119 // Given A-B, if A can be completely folded into the address and
1120 // the index field with the index field unused, use -B as the index.
1121 // This is a win if a has multiple parts that can be folded into
1122 // the address. Also, this saves a mov if the base register has
1123 // other uses, since it avoids a two-address sub instruction, however
1124 // it costs an additional mov if the index register has other uses.
1126 // Add an artificial use to this node so that we can keep track of
1127 // it if it gets CSE'd with a different node.
1128 HandleSDNode Handle(N);
1130 // Test if the LHS of the sub can be folded.
1131 X86ISelAddressMode Backup = AM;
1132 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1136 // Test if the index field is free for use.
1137 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1143 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1144 // If the RHS involves a register with multiple uses, this
1145 // transformation incurs an extra mov, due to the neg instruction
1146 // clobbering its operand.
1147 if (!RHS.getNode()->hasOneUse() ||
1148 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1149 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1150 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1151 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1152 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1154 // If the base is a register with multiple uses, this
1155 // transformation may save a mov.
1156 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1157 AM.Base_Reg.getNode() &&
1158 !AM.Base_Reg.getNode()->hasOneUse()) ||
1159 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1161 // If the folded LHS was interesting, this transformation saves
1162 // address arithmetic.
1163 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1164 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1165 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1167 // If it doesn't look like it may be an overall win, don't do it.
1173 // Ok, the transformation is legal and appears profitable. Go for it.
1174 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1175 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1179 // Insert the new nodes into the topological ordering.
1180 InsertDAGNode(*CurDAG, N, Zero);
1181 InsertDAGNode(*CurDAG, N, Neg);
1186 // Add an artificial use to this node so that we can keep track of
1187 // it if it gets CSE'd with a different node.
1188 HandleSDNode Handle(N);
1190 X86ISelAddressMode Backup = AM;
1191 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1192 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1196 // Try again after commuting the operands.
1197 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1198 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1202 // If we couldn't fold both operands into the address at the same time,
1203 // see if we can just put each operand into a register and fold at least
1205 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1206 !AM.Base_Reg.getNode() &&
1207 !AM.IndexReg.getNode()) {
1208 N = Handle.getValue();
1209 AM.Base_Reg = N.getOperand(0);
1210 AM.IndexReg = N.getOperand(1);
1214 N = Handle.getValue();
1219 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1220 if (CurDAG->isBaseWithConstantOffset(N)) {
1221 X86ISelAddressMode Backup = AM;
1222 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1224 // Start with the LHS as an addr mode.
1225 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1226 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1233 // Perform some heroic transforms on an and of a constant-count shift
1234 // with a constant to enable use of the scaled offset field.
1236 // Scale must not be used already.
1237 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1239 SDValue Shift = N.getOperand(0);
1240 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1241 SDValue X = Shift.getOperand(0);
1243 // We only handle up to 64-bit values here as those are what matter for
1244 // addressing mode optimizations.
1245 if (X.getValueSizeInBits() > 64) break;
1247 if (!isa<ConstantSDNode>(N.getOperand(1)))
1249 uint64_t Mask = N.getConstantOperandVal(1);
1251 // Try to fold the mask and shift into an extract and scale.
1252 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1255 // Try to fold the mask and shift directly into the scale.
1256 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1259 // Try to swap the mask and shift to place shifts which can be done as
1260 // a scale on the outside of the mask.
1261 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1267 return MatchAddressBase(N, AM);
1270 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1271 /// specified addressing mode without any further recursion.
1272 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1273 // Is the base register already occupied?
1274 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1275 // If so, check to see if the scale index register is set.
1276 if (AM.IndexReg.getNode() == 0) {
1282 // Otherwise, we cannot select it.
1286 // Default, generate it as a register.
1287 AM.BaseType = X86ISelAddressMode::RegBase;
1292 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1293 /// It returns the operands which make up the maximal addressing mode it can
1294 /// match by reference.
1296 /// Parent is the parent node of the addr operand that is being matched. It
1297 /// is always a load, store, atomic node, or null. It is only null when
1298 /// checking memory operands for inline asm nodes.
1299 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1300 SDValue &Scale, SDValue &Index,
1301 SDValue &Disp, SDValue &Segment) {
1302 X86ISelAddressMode AM;
1305 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1306 // that are not a MemSDNode, and thus don't have proper addrspace info.
1307 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1308 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1309 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1310 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1311 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1312 unsigned AddrSpace =
1313 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1314 // AddrSpace 256 -> GS, 257 -> FS.
1315 if (AddrSpace == 256)
1316 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1317 if (AddrSpace == 257)
1318 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1321 if (MatchAddress(N, AM))
1324 EVT VT = N.getValueType();
1325 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1326 if (!AM.Base_Reg.getNode())
1327 AM.Base_Reg = CurDAG->getRegister(0, VT);
1330 if (!AM.IndexReg.getNode())
1331 AM.IndexReg = CurDAG->getRegister(0, VT);
1333 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1337 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1338 /// match a load whose top elements are either undef or zeros. The load flavor
1339 /// is derived from the type of N, which is either v4f32 or v2f64.
1342 /// PatternChainNode: this is the matched node that has a chain input and
1344 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1345 SDValue N, SDValue &Base,
1346 SDValue &Scale, SDValue &Index,
1347 SDValue &Disp, SDValue &Segment,
1348 SDValue &PatternNodeWithChain) {
1349 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1350 PatternNodeWithChain = N.getOperand(0);
1351 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1352 PatternNodeWithChain.hasOneUse() &&
1353 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1354 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1355 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1356 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1362 // Also handle the case where we explicitly require zeros in the top
1363 // elements. This is a vector shuffle from the zero vector.
1364 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1365 // Check to see if the top elements are all zeros (or bitcast of zeros).
1366 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1367 N.getOperand(0).getNode()->hasOneUse() &&
1368 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1369 N.getOperand(0).getOperand(0).hasOneUse() &&
1370 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1371 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1372 // Okay, this is a zero extending load. Fold it.
1373 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1374 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1376 PatternNodeWithChain = SDValue(LD, 0);
1383 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1384 /// mode it matches can be cost effectively emitted as an LEA instruction.
1385 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1386 SDValue &Base, SDValue &Scale,
1387 SDValue &Index, SDValue &Disp,
1389 X86ISelAddressMode AM;
1391 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1393 SDValue Copy = AM.Segment;
1394 SDValue T = CurDAG->getRegister(0, MVT::i32);
1396 if (MatchAddress(N, AM))
1398 assert (T == AM.Segment);
1401 EVT VT = N.getValueType();
1402 unsigned Complexity = 0;
1403 if (AM.BaseType == X86ISelAddressMode::RegBase)
1404 if (AM.Base_Reg.getNode())
1407 AM.Base_Reg = CurDAG->getRegister(0, VT);
1408 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1411 if (AM.IndexReg.getNode())
1414 AM.IndexReg = CurDAG->getRegister(0, VT);
1416 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1421 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1422 // to a LEA. This is determined with some expermentation but is by no means
1423 // optimal (especially for code size consideration). LEA is nice because of
1424 // its three-address nature. Tweak the cost function again when we can run
1425 // convertToThreeAddress() at register allocation time.
1426 if (AM.hasSymbolicDisplacement()) {
1427 // For X86-64, we should always use lea to materialize RIP relative
1429 if (Subtarget->is64Bit())
1435 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1438 // If it isn't worth using an LEA, reject it.
1439 if (Complexity <= 2)
1442 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1446 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1447 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1448 SDValue &Scale, SDValue &Index,
1449 SDValue &Disp, SDValue &Segment) {
1450 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1451 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1453 X86ISelAddressMode AM;
1454 AM.GV = GA->getGlobal();
1455 AM.Disp += GA->getOffset();
1456 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1457 AM.SymbolFlags = GA->getTargetFlags();
1459 if (N.getValueType() == MVT::i32) {
1461 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1463 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1466 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1471 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1472 SDValue &Base, SDValue &Scale,
1473 SDValue &Index, SDValue &Disp,
1475 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1476 !IsProfitableToFold(N, P, P) ||
1477 !IsLegalToFold(N, P, P, OptLevel))
1480 return SelectAddr(N.getNode(),
1481 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1484 /// getGlobalBaseReg - Return an SDNode that returns the value of
1485 /// the global base register. Output instructions required to
1486 /// initialize the global base register, if necessary.
1488 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1489 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1490 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1493 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1494 SDValue Chain = Node->getOperand(0);
1495 SDValue In1 = Node->getOperand(1);
1496 SDValue In2L = Node->getOperand(2);
1497 SDValue In2H = Node->getOperand(3);
1499 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1500 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1502 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1503 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1504 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1505 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1506 MVT::i32, MVT::i32, MVT::Other, Ops,
1507 array_lengthof(Ops));
1508 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1512 /// Atomic opcode table
1540 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1551 X86::LOCK_ADD64mi32,
1564 X86::LOCK_SUB64mi32,
1616 X86::LOCK_AND64mi32,
1629 X86::LOCK_XOR64mi32,
1634 // Return the target constant operand for atomic-load-op and do simple
1635 // translations, such as from atomic-load-add to lock-sub. The return value is
1636 // one of the following 3 cases:
1637 // + target-constant, the operand could be supported as a target constant.
1638 // + empty, the operand is not needed any more with the new op selected.
1639 // + non-empty, otherwise.
1640 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1642 enum AtomicOpc &Op, EVT NVT,
1644 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1645 int64_t CNVal = CN->getSExtValue();
1646 // Quit if not 32-bit imm.
1647 if ((int32_t)CNVal != CNVal)
1649 // For atomic-load-add, we could do some optimizations.
1651 // Translate to INC/DEC if ADD by 1 or -1.
1652 if ((CNVal == 1) || (CNVal == -1)) {
1653 Op = (CNVal == 1) ? INC : DEC;
1654 // No more constant operand after being translated into INC/DEC.
1657 // Translate to SUB if ADD by negative value.
1663 return CurDAG->getTargetConstant(CNVal, NVT);
1666 // If the value operand is single-used, try to optimize it.
1667 if (Op == ADD && Val.hasOneUse()) {
1668 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1669 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1671 return Val.getOperand(1);
1673 // A special case for i16, which needs truncating as, in most cases, it's
1674 // promoted to i32. We will translate
1675 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1676 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1677 Val.getOperand(0).getOpcode() == ISD::SUB &&
1678 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1680 Val = Val.getOperand(0);
1681 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1689 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
1690 if (Node->hasAnyUseOfValue(0))
1693 DebugLoc dl = Node->getDebugLoc();
1695 // Optimize common patterns for __sync_or_and_fetch and similar arith
1696 // operations where the result is not used. This allows us to use the "lock"
1697 // version of the arithmetic instruction.
1698 SDValue Chain = Node->getOperand(0);
1699 SDValue Ptr = Node->getOperand(1);
1700 SDValue Val = Node->getOperand(2);
1701 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1702 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1705 // Which index into the table.
1707 switch (Node->getOpcode()) {
1710 case ISD::ATOMIC_LOAD_OR:
1713 case ISD::ATOMIC_LOAD_AND:
1716 case ISD::ATOMIC_LOAD_XOR:
1719 case ISD::ATOMIC_LOAD_ADD:
1724 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val);
1725 bool isUnOp = !Val.getNode();
1726 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1729 switch (NVT.getSimpleVT().SimpleTy) {
1733 Opc = AtomicOpcTbl[Op][ConstantI8];
1735 Opc = AtomicOpcTbl[Op][I8];
1739 if (immSext8(Val.getNode()))
1740 Opc = AtomicOpcTbl[Op][SextConstantI16];
1742 Opc = AtomicOpcTbl[Op][ConstantI16];
1744 Opc = AtomicOpcTbl[Op][I16];
1748 if (immSext8(Val.getNode()))
1749 Opc = AtomicOpcTbl[Op][SextConstantI32];
1751 Opc = AtomicOpcTbl[Op][ConstantI32];
1753 Opc = AtomicOpcTbl[Op][I32];
1756 Opc = AtomicOpcTbl[Op][I64];
1758 if (immSext8(Val.getNode()))
1759 Opc = AtomicOpcTbl[Op][SextConstantI64];
1760 else if (i64immSExt32(Val.getNode()))
1761 Opc = AtomicOpcTbl[Op][ConstantI64];
1766 assert(Opc != 0 && "Invalid arith lock transform!");
1769 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1771 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1772 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1774 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1775 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops,
1776 array_lengthof(Ops)), 0);
1778 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1779 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops,
1780 array_lengthof(Ops)), 0);
1782 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1783 SDValue RetVals[] = { Undef, Ret };
1784 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1787 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1788 /// any uses which require the SF or OF bits to be accurate.
1789 static bool HasNoSignedComparisonUses(SDNode *N) {
1790 // Examine each user of the node.
1791 for (SDNode::use_iterator UI = N->use_begin(),
1792 UE = N->use_end(); UI != UE; ++UI) {
1793 // Only examine CopyToReg uses.
1794 if (UI->getOpcode() != ISD::CopyToReg)
1796 // Only examine CopyToReg uses that copy to EFLAGS.
1797 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1800 // Examine each user of the CopyToReg use.
1801 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1802 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1803 // Only examine the Flag result.
1804 if (FlagUI.getUse().getResNo() != 1) continue;
1805 // Anything unusual: assume conservatively.
1806 if (!FlagUI->isMachineOpcode()) return false;
1807 // Examine the opcode of the user.
1808 switch (FlagUI->getMachineOpcode()) {
1809 // These comparisons don't treat the most significant bit specially.
1810 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1811 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1812 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1813 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1814 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1815 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1816 case X86::CMOVA16rr: case X86::CMOVA16rm:
1817 case X86::CMOVA32rr: case X86::CMOVA32rm:
1818 case X86::CMOVA64rr: case X86::CMOVA64rm:
1819 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1820 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1821 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1822 case X86::CMOVB16rr: case X86::CMOVB16rm:
1823 case X86::CMOVB32rr: case X86::CMOVB32rm:
1824 case X86::CMOVB64rr: case X86::CMOVB64rm:
1825 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1826 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1827 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1828 case X86::CMOVE16rr: case X86::CMOVE16rm:
1829 case X86::CMOVE32rr: case X86::CMOVE32rm:
1830 case X86::CMOVE64rr: case X86::CMOVE64rm:
1831 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1832 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1833 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1834 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1835 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1836 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1837 case X86::CMOVP16rr: case X86::CMOVP16rm:
1838 case X86::CMOVP32rr: case X86::CMOVP32rm:
1839 case X86::CMOVP64rr: case X86::CMOVP64rm:
1841 // Anything else: assume conservatively.
1842 default: return false;
1849 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1850 /// is suitable for doing the {load; increment or decrement; store} to modify
1852 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1853 SDValue StoredVal, SelectionDAG *CurDAG,
1854 LoadSDNode* &LoadNode, SDValue &InputChain) {
1856 // is the value stored the result of a DEC or INC?
1857 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1859 // is the stored value result 0 of the load?
1860 if (StoredVal.getResNo() != 0) return false;
1862 // are there other uses of the loaded value than the inc or dec?
1863 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1865 // is the store non-extending and non-indexed?
1866 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1869 SDValue Load = StoredVal->getOperand(0);
1870 // Is the stored value a non-extending and non-indexed load?
1871 if (!ISD::isNormalLoad(Load.getNode())) return false;
1873 // Return LoadNode by reference.
1874 LoadNode = cast<LoadSDNode>(Load);
1875 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1876 EVT LdVT = LoadNode->getMemoryVT();
1877 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1881 // Is store the only read of the loaded value?
1882 if (!Load.hasOneUse())
1885 // Is the address of the store the same as the load?
1886 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1887 LoadNode->getOffset() != StoreNode->getOffset())
1890 // Check if the chain is produced by the load or is a TokenFactor with
1891 // the load output chain as an operand. Return InputChain by reference.
1892 SDValue Chain = StoreNode->getChain();
1894 bool ChainCheck = false;
1895 if (Chain == Load.getValue(1)) {
1897 InputChain = LoadNode->getChain();
1898 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1899 SmallVector<SDValue, 4> ChainOps;
1900 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1901 SDValue Op = Chain.getOperand(i);
1902 if (Op == Load.getValue(1)) {
1907 // Make sure using Op as part of the chain would not cause a cycle here.
1908 // In theory, we could check whether the chain node is a predecessor of
1909 // the load. But that can be very expensive. Instead visit the uses and
1910 // make sure they all have smaller node id than the load.
1911 int LoadId = LoadNode->getNodeId();
1912 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1913 UE = UI->use_end(); UI != UE; ++UI) {
1914 if (UI.getUse().getResNo() != 0)
1916 if (UI->getNodeId() > LoadId)
1920 ChainOps.push_back(Op);
1924 // Make a new TokenFactor with all the other input chains except
1926 InputChain = CurDAG->getNode(ISD::TokenFactor, Chain.getDebugLoc(),
1927 MVT::Other, &ChainOps[0], ChainOps.size());
1935 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
1936 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
1937 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
1938 if (Opc == X86ISD::DEC) {
1939 if (LdVT == MVT::i64) return X86::DEC64m;
1940 if (LdVT == MVT::i32) return X86::DEC32m;
1941 if (LdVT == MVT::i16) return X86::DEC16m;
1942 if (LdVT == MVT::i8) return X86::DEC8m;
1944 assert(Opc == X86ISD::INC && "unrecognized opcode");
1945 if (LdVT == MVT::i64) return X86::INC64m;
1946 if (LdVT == MVT::i32) return X86::INC32m;
1947 if (LdVT == MVT::i16) return X86::INC16m;
1948 if (LdVT == MVT::i8) return X86::INC8m;
1950 llvm_unreachable("unrecognized size for LdVT");
1953 /// SelectGather - Customized ISel for GATHER operations.
1955 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
1956 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
1957 SDValue Chain = Node->getOperand(0);
1958 SDValue VSrc = Node->getOperand(2);
1959 SDValue Base = Node->getOperand(3);
1960 SDValue VIdx = Node->getOperand(4);
1961 SDValue VMask = Node->getOperand(5);
1962 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
1966 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
1969 // Memory Operands: Base, Scale, Index, Disp, Segment
1970 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
1971 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
1972 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
1973 Disp, Segment, VMask, Chain};
1974 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1975 VTs, Ops, array_lengthof(Ops));
1976 // Node has 2 outputs: VDst and MVT::Other.
1977 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
1978 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
1980 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
1981 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
1985 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
1986 EVT NVT = Node->getValueType(0);
1988 unsigned Opcode = Node->getOpcode();
1989 DebugLoc dl = Node->getDebugLoc();
1991 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
1993 if (Node->isMachineOpcode()) {
1994 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
1995 return NULL; // Already selected.
2000 case ISD::INTRINSIC_W_CHAIN: {
2001 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2004 case Intrinsic::x86_avx2_gather_d_pd:
2005 case Intrinsic::x86_avx2_gather_d_pd_256:
2006 case Intrinsic::x86_avx2_gather_q_pd:
2007 case Intrinsic::x86_avx2_gather_q_pd_256:
2008 case Intrinsic::x86_avx2_gather_d_ps:
2009 case Intrinsic::x86_avx2_gather_d_ps_256:
2010 case Intrinsic::x86_avx2_gather_q_ps:
2011 case Intrinsic::x86_avx2_gather_q_ps_256:
2012 case Intrinsic::x86_avx2_gather_d_q:
2013 case Intrinsic::x86_avx2_gather_d_q_256:
2014 case Intrinsic::x86_avx2_gather_q_q:
2015 case Intrinsic::x86_avx2_gather_q_q_256:
2016 case Intrinsic::x86_avx2_gather_d_d:
2017 case Intrinsic::x86_avx2_gather_d_d_256:
2018 case Intrinsic::x86_avx2_gather_q_d:
2019 case Intrinsic::x86_avx2_gather_q_d_256: {
2022 default: llvm_unreachable("Impossible intrinsic");
2023 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2024 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2025 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2026 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2027 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2028 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2029 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2030 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2031 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2032 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2033 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2034 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2035 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2036 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2037 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2038 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2040 SDNode *RetVal = SelectGather(Node, Opc);
2042 // We already called ReplaceUses inside SelectGather.
2049 case X86ISD::GlobalBaseReg:
2050 return getGlobalBaseReg();
2053 case X86ISD::ATOMOR64_DAG:
2054 case X86ISD::ATOMXOR64_DAG:
2055 case X86ISD::ATOMADD64_DAG:
2056 case X86ISD::ATOMSUB64_DAG:
2057 case X86ISD::ATOMNAND64_DAG:
2058 case X86ISD::ATOMAND64_DAG:
2059 case X86ISD::ATOMMAX64_DAG:
2060 case X86ISD::ATOMMIN64_DAG:
2061 case X86ISD::ATOMUMAX64_DAG:
2062 case X86ISD::ATOMUMIN64_DAG:
2063 case X86ISD::ATOMSWAP64_DAG: {
2066 default: llvm_unreachable("Impossible opcode");
2067 case X86ISD::ATOMOR64_DAG: Opc = X86::ATOMOR6432; break;
2068 case X86ISD::ATOMXOR64_DAG: Opc = X86::ATOMXOR6432; break;
2069 case X86ISD::ATOMADD64_DAG: Opc = X86::ATOMADD6432; break;
2070 case X86ISD::ATOMSUB64_DAG: Opc = X86::ATOMSUB6432; break;
2071 case X86ISD::ATOMNAND64_DAG: Opc = X86::ATOMNAND6432; break;
2072 case X86ISD::ATOMAND64_DAG: Opc = X86::ATOMAND6432; break;
2073 case X86ISD::ATOMMAX64_DAG: Opc = X86::ATOMMAX6432; break;
2074 case X86ISD::ATOMMIN64_DAG: Opc = X86::ATOMMIN6432; break;
2075 case X86ISD::ATOMUMAX64_DAG: Opc = X86::ATOMUMAX6432; break;
2076 case X86ISD::ATOMUMIN64_DAG: Opc = X86::ATOMUMIN6432; break;
2077 case X86ISD::ATOMSWAP64_DAG: Opc = X86::ATOMSWAP6432; break;
2079 SDNode *RetVal = SelectAtomic64(Node, Opc);
2085 case ISD::ATOMIC_LOAD_XOR:
2086 case ISD::ATOMIC_LOAD_AND:
2087 case ISD::ATOMIC_LOAD_OR:
2088 case ISD::ATOMIC_LOAD_ADD: {
2089 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2097 // For operations of the form (x << C1) op C2, check if we can use a smaller
2098 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2099 SDValue N0 = Node->getOperand(0);
2100 SDValue N1 = Node->getOperand(1);
2102 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2105 // i8 is unshrinkable, i16 should be promoted to i32.
2106 if (NVT != MVT::i32 && NVT != MVT::i64)
2109 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2110 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2111 if (!Cst || !ShlCst)
2114 int64_t Val = Cst->getSExtValue();
2115 uint64_t ShlVal = ShlCst->getZExtValue();
2117 // Make sure that we don't change the operation by removing bits.
2118 // This only matters for OR and XOR, AND is unaffected.
2119 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2120 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2126 // Check the minimum bitwidth for the new constant.
2127 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2128 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2129 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2130 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2132 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2135 // Bail if there is no smaller encoding.
2139 switch (NVT.getSimpleVT().SimpleTy) {
2140 default: llvm_unreachable("Unsupported VT!");
2142 assert(CstVT == MVT::i8);
2143 ShlOp = X86::SHL32ri;
2146 default: llvm_unreachable("Impossible opcode");
2147 case ISD::AND: Op = X86::AND32ri8; break;
2148 case ISD::OR: Op = X86::OR32ri8; break;
2149 case ISD::XOR: Op = X86::XOR32ri8; break;
2153 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2154 ShlOp = X86::SHL64ri;
2157 default: llvm_unreachable("Impossible opcode");
2158 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2159 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2160 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2165 // Emit the smaller op and the shift.
2166 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2167 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2168 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2171 case X86ISD::UMUL: {
2172 SDValue N0 = Node->getOperand(0);
2173 SDValue N1 = Node->getOperand(1);
2176 switch (NVT.getSimpleVT().SimpleTy) {
2177 default: llvm_unreachable("Unsupported VT!");
2178 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2179 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2180 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2181 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2184 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2185 N0, SDValue()).getValue(1);
2187 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2188 SDValue Ops[] = {N1, InFlag};
2189 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops, 2);
2191 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2192 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2193 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2197 case ISD::SMUL_LOHI:
2198 case ISD::UMUL_LOHI: {
2199 SDValue N0 = Node->getOperand(0);
2200 SDValue N1 = Node->getOperand(1);
2202 bool isSigned = Opcode == ISD::SMUL_LOHI;
2203 bool hasBMI2 = Subtarget->hasBMI2();
2205 switch (NVT.getSimpleVT().SimpleTy) {
2206 default: llvm_unreachable("Unsupported VT!");
2207 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2208 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2209 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2210 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2211 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2212 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2215 switch (NVT.getSimpleVT().SimpleTy) {
2216 default: llvm_unreachable("Unsupported VT!");
2217 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2218 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2219 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2220 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2224 unsigned SrcReg, LoReg, HiReg;
2226 default: llvm_unreachable("Unknown MUL opcode!");
2229 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2233 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2237 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2241 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2244 SrcReg = X86::EDX; LoReg = HiReg = 0;
2247 SrcReg = X86::RDX; LoReg = HiReg = 0;
2251 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2252 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2253 // Multiply is commmutative.
2255 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2260 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2261 N0, SDValue()).getValue(1);
2262 SDValue ResHi, ResLo;
2266 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2268 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2269 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2270 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops,
2271 array_lengthof(Ops));
2272 ResHi = SDValue(CNode, 0);
2273 ResLo = SDValue(CNode, 1);
2274 Chain = SDValue(CNode, 2);
2275 InFlag = SDValue(CNode, 3);
2277 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2278 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops,
2279 array_lengthof(Ops));
2280 Chain = SDValue(CNode, 0);
2281 InFlag = SDValue(CNode, 1);
2284 // Update the chain.
2285 ReplaceUses(N1.getValue(1), Chain);
2287 SDValue Ops[] = { N1, InFlag };
2288 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2289 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2290 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops,
2291 array_lengthof(Ops));
2292 ResHi = SDValue(CNode, 0);
2293 ResLo = SDValue(CNode, 1);
2294 InFlag = SDValue(CNode, 2);
2296 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2297 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops,
2298 array_lengthof(Ops));
2299 InFlag = SDValue(CNode, 0);
2303 // Prevent use of AH in a REX instruction by referencing AX instead.
2304 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2305 !SDValue(Node, 1).use_empty()) {
2306 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2307 X86::AX, MVT::i16, InFlag);
2308 InFlag = Result.getValue(2);
2309 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2311 if (!SDValue(Node, 0).use_empty())
2312 ReplaceUses(SDValue(Node, 1),
2313 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2315 // Shift AX down 8 bits.
2316 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2318 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2319 // Then truncate it down to i8.
2320 ReplaceUses(SDValue(Node, 1),
2321 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2323 // Copy the low half of the result, if it is needed.
2324 if (!SDValue(Node, 0).use_empty()) {
2325 if (ResLo.getNode() == 0) {
2326 assert(LoReg && "Register for low half is not defined!");
2327 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2329 InFlag = ResLo.getValue(2);
2331 ReplaceUses(SDValue(Node, 0), ResLo);
2332 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2334 // Copy the high half of the result, if it is needed.
2335 if (!SDValue(Node, 1).use_empty()) {
2336 if (ResHi.getNode() == 0) {
2337 assert(HiReg && "Register for high half is not defined!");
2338 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2340 InFlag = ResHi.getValue(2);
2342 ReplaceUses(SDValue(Node, 1), ResHi);
2343 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2346 // Propagate ordering to the last node, for now.
2347 CurDAG->AssignOrdering(InFlag.getNode(), CurDAG->GetOrdering(Node));
2353 case ISD::UDIVREM: {
2354 SDValue N0 = Node->getOperand(0);
2355 SDValue N1 = Node->getOperand(1);
2357 bool isSigned = Opcode == ISD::SDIVREM;
2359 switch (NVT.getSimpleVT().SimpleTy) {
2360 default: llvm_unreachable("Unsupported VT!");
2361 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2362 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2363 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2364 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2367 switch (NVT.getSimpleVT().SimpleTy) {
2368 default: llvm_unreachable("Unsupported VT!");
2369 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2370 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2371 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2372 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2376 unsigned LoReg, HiReg, ClrReg;
2377 unsigned ClrOpcode, SExtOpcode;
2378 switch (NVT.getSimpleVT().SimpleTy) {
2379 default: llvm_unreachable("Unsupported VT!");
2381 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2383 SExtOpcode = X86::CBW;
2386 LoReg = X86::AX; HiReg = X86::DX;
2387 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
2388 SExtOpcode = X86::CWD;
2391 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2392 ClrOpcode = X86::MOV32r0;
2393 SExtOpcode = X86::CDQ;
2396 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2397 ClrOpcode = X86::MOV64r0;
2398 SExtOpcode = X86::CQO;
2402 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2403 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2404 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2407 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2408 // Special case for div8, just use a move with zero extension to AX to
2409 // clear the upper 8 bits (AH).
2410 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2411 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2412 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2414 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2416 array_lengthof(Ops)), 0);
2417 Chain = Move.getValue(1);
2418 ReplaceUses(N0.getValue(1), Chain);
2421 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2422 Chain = CurDAG->getEntryNode();
2424 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2425 InFlag = Chain.getValue(1);
2428 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2429 LoReg, N0, SDValue()).getValue(1);
2430 if (isSigned && !signBitIsZero) {
2431 // Sign extend the low part into the high part.
2433 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2435 // Zero out the high part, effectively zero extending the input.
2437 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
2438 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2439 ClrNode, InFlag).getValue(1);
2444 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2447 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
2448 array_lengthof(Ops));
2449 InFlag = SDValue(CNode, 1);
2450 // Update the chain.
2451 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2454 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2457 // Prevent use of AH in a REX instruction by referencing AX instead.
2458 // Shift it down 8 bits.
2459 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2460 !SDValue(Node, 1).use_empty()) {
2461 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2462 X86::AX, MVT::i16, InFlag);
2463 InFlag = Result.getValue(2);
2465 // If we also need AL (the quotient), get it by extracting a subreg from
2466 // Result. The fast register allocator does not like multiple CopyFromReg
2467 // nodes using aliasing registers.
2468 if (!SDValue(Node, 0).use_empty())
2469 ReplaceUses(SDValue(Node, 0),
2470 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2472 // Shift AX right by 8 bits instead of using AH.
2473 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2475 CurDAG->getTargetConstant(8, MVT::i8)),
2477 ReplaceUses(SDValue(Node, 1),
2478 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2480 // Copy the division (low) result, if it is needed.
2481 if (!SDValue(Node, 0).use_empty()) {
2482 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2483 LoReg, NVT, InFlag);
2484 InFlag = Result.getValue(2);
2485 ReplaceUses(SDValue(Node, 0), Result);
2486 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2488 // Copy the remainder (high) result, if it is needed.
2489 if (!SDValue(Node, 1).use_empty()) {
2490 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2491 HiReg, NVT, InFlag);
2492 InFlag = Result.getValue(2);
2493 ReplaceUses(SDValue(Node, 1), Result);
2494 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2501 // Sometimes a SUB is used to perform comparison.
2502 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2503 // This node is not a CMP.
2505 SDValue N0 = Node->getOperand(0);
2506 SDValue N1 = Node->getOperand(1);
2508 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2509 // use a smaller encoding.
2510 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2511 HasNoSignedComparisonUses(Node))
2512 // Look past the truncate if CMP is the only use of it.
2513 N0 = N0.getOperand(0);
2514 if ((N0.getNode()->getOpcode() == ISD::AND ||
2515 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2516 N0.getNode()->hasOneUse() &&
2517 N0.getValueType() != MVT::i8 &&
2518 X86::isZeroNode(N1)) {
2519 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2522 // For example, convert "testl %eax, $8" to "testb %al, $8"
2523 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2524 (!(C->getZExtValue() & 0x80) ||
2525 HasNoSignedComparisonUses(Node))) {
2526 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2527 SDValue Reg = N0.getNode()->getOperand(0);
2529 // On x86-32, only the ABCD registers have 8-bit subregisters.
2530 if (!Subtarget->is64Bit()) {
2531 const TargetRegisterClass *TRC;
2532 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2533 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2534 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2535 default: llvm_unreachable("Unsupported TEST operand type!");
2537 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2538 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2539 Reg.getValueType(), Reg, RC), 0);
2542 // Extract the l-register.
2543 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2547 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2549 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2550 // one, do not call ReplaceAllUsesWith.
2551 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2552 SDValue(NewNode, 0));
2556 // For example, "testl %eax, $2048" to "testb %ah, $8".
2557 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2558 (!(C->getZExtValue() & 0x8000) ||
2559 HasNoSignedComparisonUses(Node))) {
2560 // Shift the immediate right by 8 bits.
2561 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2563 SDValue Reg = N0.getNode()->getOperand(0);
2565 // Put the value in an ABCD register.
2566 const TargetRegisterClass *TRC;
2567 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2568 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2569 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2570 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2571 default: llvm_unreachable("Unsupported TEST operand type!");
2573 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2574 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2575 Reg.getValueType(), Reg, RC), 0);
2577 // Extract the h-register.
2578 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2581 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2582 // target GR8_NOREX registers, so make sure the register class is
2584 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2585 MVT::i32, Subreg, ShiftedImm);
2586 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2587 // one, do not call ReplaceAllUsesWith.
2588 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2589 SDValue(NewNode, 0));
2593 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2594 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2595 N0.getValueType() != MVT::i16 &&
2596 (!(C->getZExtValue() & 0x8000) ||
2597 HasNoSignedComparisonUses(Node))) {
2598 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2599 SDValue Reg = N0.getNode()->getOperand(0);
2601 // Extract the 16-bit subregister.
2602 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2606 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2608 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2609 // one, do not call ReplaceAllUsesWith.
2610 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2611 SDValue(NewNode, 0));
2615 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2616 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2617 N0.getValueType() == MVT::i64 &&
2618 (!(C->getZExtValue() & 0x80000000) ||
2619 HasNoSignedComparisonUses(Node))) {
2620 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2621 SDValue Reg = N0.getNode()->getOperand(0);
2623 // Extract the 32-bit subregister.
2624 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2628 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2630 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2631 // one, do not call ReplaceAllUsesWith.
2632 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2633 SDValue(NewNode, 0));
2640 // Change a chain of {load; incr or dec; store} of the same value into
2641 // a simple increment or decrement through memory of that value, if the
2642 // uses of the modified value and its address are suitable.
2643 // The DEC64m tablegen pattern is currently not able to match the case where
2644 // the EFLAGS on the original DEC are used. (This also applies to
2645 // {INC,DEC}X{64,32,16,8}.)
2646 // We'll need to improve tablegen to allow flags to be transferred from a
2647 // node in the pattern to the result node. probably with a new keyword
2648 // for example, we have this
2649 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2650 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2651 // (implicit EFLAGS)]>;
2652 // but maybe need something like this
2653 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2654 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2655 // (transferrable EFLAGS)]>;
2657 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2658 SDValue StoredVal = StoreNode->getOperand(1);
2659 unsigned Opc = StoredVal->getOpcode();
2661 LoadSDNode *LoadNode = 0;
2663 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2664 LoadNode, InputChain))
2667 SDValue Base, Scale, Index, Disp, Segment;
2668 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2669 Base, Scale, Index, Disp, Segment))
2672 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2673 MemOp[0] = StoreNode->getMemOperand();
2674 MemOp[1] = LoadNode->getMemOperand();
2675 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2676 EVT LdVT = LoadNode->getMemoryVT();
2677 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2678 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2679 Node->getDebugLoc(),
2680 MVT::i32, MVT::Other, Ops,
2681 array_lengthof(Ops));
2682 Result->setMemRefs(MemOp, MemOp + 2);
2684 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2685 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2691 SDNode *ResNode = SelectCode(Node);
2693 DEBUG(dbgs() << "=> ";
2694 if (ResNode == NULL || ResNode == Node)
2697 ResNode->dump(CurDAG);
2703 bool X86DAGToDAGISel::
2704 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2705 std::vector<SDValue> &OutOps) {
2706 SDValue Op0, Op1, Op2, Op3, Op4;
2707 switch (ConstraintCode) {
2708 case 'o': // offsetable ??
2709 case 'v': // not offsetable ??
2710 default: return true;
2712 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
2717 OutOps.push_back(Op0);
2718 OutOps.push_back(Op1);
2719 OutOps.push_back(Op2);
2720 OutOps.push_back(Op3);
2721 OutOps.push_back(Op4);
2725 /// createX86ISelDag - This pass converts a legalized DAG into a
2726 /// X86-specific DAG, ready for instruction scheduling.
2728 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2729 CodeGenOpt::Level OptLevel) {
2730 return new X86DAGToDAGISel(TM, OptLevel);