1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 // Force NDEBUG on in any optimized build on Darwin.
17 // FIXME: This is a huge hack, to work around ridiculously awful compile times
18 // on this file with gcc-4.2 on Darwin, in Release mode.
19 #if (!defined(__llvm__) && defined(__APPLE__) && \
20 defined(__OPTIMIZE__) && !defined(NDEBUG))
24 #define DEBUG_TYPE "x86-isel"
26 #include "X86InstrBuilder.h"
27 #include "X86ISelLowering.h"
28 #include "X86MachineFunctionInfo.h"
29 #include "X86RegisterInfo.h"
30 #include "X86Subtarget.h"
31 #include "X86TargetMachine.h"
32 #include "llvm/GlobalValue.h"
33 #include "llvm/Instructions.h"
34 #include "llvm/Intrinsics.h"
35 #include "llvm/Support/CFG.h"
36 #include "llvm/Type.h"
37 #include "llvm/CodeGen/MachineConstantPool.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineFrameInfo.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/SelectionDAGISel.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
49 #include "llvm/ADT/SmallPtrSet.h"
50 #include "llvm/ADT/Statistic.h"
53 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
55 //===----------------------------------------------------------------------===//
56 // Pattern Matcher Implementation
57 //===----------------------------------------------------------------------===//
60 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
61 /// SDValue's instead of register numbers for the leaves of the matched
63 struct X86ISelAddressMode {
69 struct { // This is really a union, discriminated by BaseType!
80 BlockAddress *BlockAddr;
83 unsigned Align; // CP alignment.
84 unsigned char SymbolFlags; // X86II::MO_*
87 : BaseType(RegBase), Scale(1), IndexReg(), Disp(0),
88 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
89 SymbolFlags(X86II::MO_NO_FLAG) {
92 bool hasSymbolicDisplacement() const {
93 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
96 bool hasBaseOrIndexReg() const {
97 return IndexReg.getNode() != 0 || Base.Reg.getNode() != 0;
100 /// isRIPRelative - Return true if this addressing mode is already RIP
102 bool isRIPRelative() const {
103 if (BaseType != RegBase) return false;
104 if (RegisterSDNode *RegNode =
105 dyn_cast_or_null<RegisterSDNode>(Base.Reg.getNode()))
106 return RegNode->getReg() == X86::RIP;
110 void setBaseReg(SDValue Reg) {
116 errs() << "X86ISelAddressMode " << this << '\n';
117 errs() << "Base.Reg ";
118 if (Base.Reg.getNode() != 0)
119 Base.Reg.getNode()->dump();
122 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n'
123 << " Scale" << Scale << '\n'
125 if (IndexReg.getNode() != 0)
126 IndexReg.getNode()->dump();
129 errs() << " Disp " << Disp << '\n'
146 errs() << " JT" << JT << " Align" << Align << '\n';
152 //===--------------------------------------------------------------------===//
153 /// ISel - X86 specific code to select X86 machine instructions for
154 /// SelectionDAG operations.
156 class X86DAGToDAGISel : public SelectionDAGISel {
157 /// X86Lowering - This object fully describes how to lower LLVM code to an
158 /// X86-specific SelectionDAG.
159 X86TargetLowering &X86Lowering;
161 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
162 /// make the right decision when generating code for different targets.
163 const X86Subtarget *Subtarget;
165 /// OptForSize - If true, selector should try to optimize for code size
166 /// instead of performance.
170 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
171 : SelectionDAGISel(tm, OptLevel),
172 X86Lowering(*tm.getTargetLowering()),
173 Subtarget(&tm.getSubtarget<X86Subtarget>()),
176 virtual const char *getPassName() const {
177 return "X86 DAG->DAG Instruction Selection";
180 /// InstructionSelect - This callback is invoked by
181 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
182 virtual void InstructionSelect();
184 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
187 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
189 // Include the pieces autogenerated from the target description.
190 #include "X86GenDAGISel.inc"
193 SDNode *Select(SDValue N);
194 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
195 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
197 bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
198 bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
204 bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
208 SDValue &Scale, SDValue &Index, SDValue &Disp);
209 bool SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
210 SDValue &Scale, SDValue &Index, SDValue &Disp);
211 bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
212 SDValue N, SDValue &Base, SDValue &Scale,
213 SDValue &Index, SDValue &Disp,
215 SDValue &InChain, SDValue &OutChain);
216 bool TryFoldLoad(SDValue P, SDValue N,
217 SDValue &Base, SDValue &Scale,
218 SDValue &Index, SDValue &Disp,
220 void PreprocessForRMW();
221 void PreprocessForFPConvert();
223 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
224 /// inline asm expressions.
225 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
227 std::vector<SDValue> &OutOps);
229 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
231 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
232 SDValue &Scale, SDValue &Index,
233 SDValue &Disp, SDValue &Segment) {
234 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
235 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
237 Scale = getI8Imm(AM.Scale);
239 // These are 32-bit even in 64-bit mode since RIP relative offset
242 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp,
245 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
246 AM.Align, AM.Disp, AM.SymbolFlags);
248 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
249 else if (AM.JT != -1)
250 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
251 else if (AM.BlockAddr)
252 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
253 true, AM.SymbolFlags);
255 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
257 if (AM.Segment.getNode())
258 Segment = AM.Segment;
260 Segment = CurDAG->getRegister(0, MVT::i32);
263 /// getI8Imm - Return a target constant with the specified value, of type
265 inline SDValue getI8Imm(unsigned Imm) {
266 return CurDAG->getTargetConstant(Imm, MVT::i8);
269 /// getI16Imm - Return a target constant with the specified value, of type
271 inline SDValue getI16Imm(unsigned Imm) {
272 return CurDAG->getTargetConstant(Imm, MVT::i16);
275 /// getI32Imm - Return a target constant with the specified value, of type
277 inline SDValue getI32Imm(unsigned Imm) {
278 return CurDAG->getTargetConstant(Imm, MVT::i32);
281 /// getGlobalBaseReg - Return an SDNode that returns the value of
282 /// the global base register. Output instructions required to
283 /// initialize the global base register, if necessary.
285 SDNode *getGlobalBaseReg();
287 /// getTargetMachine - Return a reference to the TargetMachine, casted
288 /// to the target-specific type.
289 const X86TargetMachine &getTargetMachine() {
290 return static_cast<const X86TargetMachine &>(TM);
293 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
294 /// to the target-specific type.
295 const X86InstrInfo *getInstrInfo() {
296 return getTargetMachine().getInstrInfo();
306 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
307 SDNode *Root) const {
308 if (OptLevel == CodeGenOpt::None) return false;
311 switch (U->getOpcode()) {
319 SDValue Op1 = U->getOperand(1);
321 // If the other operand is a 8-bit immediate we should fold the immediate
322 // instead. This reduces code size.
324 // movl 4(%esp), %eax
328 // addl 4(%esp), %eax
329 // The former is 2 bytes shorter. In case where the increment is 1, then
330 // the saving can be 4 bytes (by using incl %eax).
331 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
332 if (Imm->getAPIntValue().isSignedIntN(8))
335 // If the other operand is a TLS address, we should fold it instead.
338 // leal i@NTPOFF(%eax), %eax
340 // movl $i@NTPOFF, %eax
342 // if the block also has an access to a second TLS address this will save
344 // FIXME: This is probably also true for non TLS addresses.
345 if (Op1.getOpcode() == X86ISD::Wrapper) {
346 SDValue Val = Op1.getOperand(0);
347 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
353 // Proceed to 'generic' cycle finder code
354 return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root);
357 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
358 /// and move load below the TokenFactor. Replace store's chain operand with
359 /// load's chain result.
360 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
361 SDValue Store, SDValue TF) {
362 SmallVector<SDValue, 4> Ops;
363 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
364 if (Load.getNode() == TF.getOperand(i).getNode())
365 Ops.push_back(Load.getOperand(0));
367 Ops.push_back(TF.getOperand(i));
368 SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
369 SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
372 CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
373 Store.getOperand(2), Store.getOperand(3));
376 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG. The
377 /// chain produced by the load must only be used by the store's chain operand,
378 /// otherwise this may produce a cycle in the DAG.
380 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
382 if (N.getOpcode() == ISD::BIT_CONVERT)
385 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
386 if (!LD || LD->isVolatile())
388 if (LD->getAddressingMode() != ISD::UNINDEXED)
391 ISD::LoadExtType ExtType = LD->getExtensionType();
392 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
396 LD->hasNUsesOfValue(1, 1) &&
397 N.getOperand(1) == Address &&
398 LD->isOperandOf(Chain.getNode())) {
405 /// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
406 /// operand and move load below the call's chain operand.
407 static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
408 SDValue Call, SDValue CallSeqStart) {
409 SmallVector<SDValue, 8> Ops;
410 SDValue Chain = CallSeqStart.getOperand(0);
411 if (Chain.getNode() == Load.getNode())
412 Ops.push_back(Load.getOperand(0));
414 assert(Chain.getOpcode() == ISD::TokenFactor &&
415 "Unexpected CallSeqStart chain operand");
416 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
417 if (Chain.getOperand(i).getNode() == Load.getNode())
418 Ops.push_back(Load.getOperand(0));
420 Ops.push_back(Chain.getOperand(i));
422 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
423 MVT::Other, &Ops[0], Ops.size());
425 Ops.push_back(NewChain);
427 for (unsigned i = 1, e = CallSeqStart.getNumOperands(); i != e; ++i)
428 Ops.push_back(CallSeqStart.getOperand(i));
429 CurDAG->UpdateNodeOperands(CallSeqStart, &Ops[0], Ops.size());
430 CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
431 Load.getOperand(1), Load.getOperand(2));
433 Ops.push_back(SDValue(Load.getNode(), 1));
434 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
435 Ops.push_back(Call.getOperand(i));
436 CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
439 /// isCalleeLoad - Return true if call address is a load and it can be
440 /// moved below CALLSEQ_START and the chains leading up to the call.
441 /// Return the CALLSEQ_START by reference as a second output.
442 static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
443 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
445 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
448 LD->getAddressingMode() != ISD::UNINDEXED ||
449 LD->getExtensionType() != ISD::NON_EXTLOAD)
452 // Now let's find the callseq_start.
453 while (Chain.getOpcode() != ISD::CALLSEQ_START) {
454 if (!Chain.hasOneUse())
456 Chain = Chain.getOperand(0);
459 if (Chain.getOperand(0).getNode() == Callee.getNode())
461 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
462 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
463 Callee.getValue(1).hasOneUse())
469 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
470 /// This is only run if not in -O0 mode.
471 /// This allows the instruction selector to pick more read-modify-write
472 /// instructions. This is a common case:
482 /// [TokenFactor] [Op]
489 /// The fact the store's chain operand != load's chain will prevent the
490 /// (store (op (load))) instruction from being selected. We can transform it to:
509 void X86DAGToDAGISel::PreprocessForRMW() {
510 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
511 E = CurDAG->allnodes_end(); I != E; ++I) {
512 if (I->getOpcode() == X86ISD::CALL) {
513 /// Also try moving call address load from outside callseq_start to just
514 /// before the call to allow it to be folded.
532 SDValue Chain = I->getOperand(0);
533 SDValue Load = I->getOperand(1);
534 if (!isCalleeLoad(Load, Chain))
536 MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
541 if (!ISD::isNON_TRUNCStore(I))
543 SDValue Chain = I->getOperand(0);
545 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
548 SDValue N1 = I->getOperand(1);
549 SDValue N2 = I->getOperand(2);
550 if ((N1.getValueType().isFloatingPoint() &&
551 !N1.getValueType().isVector()) ||
557 unsigned Opcode = N1.getNode()->getOpcode();
566 case ISD::VECTOR_SHUFFLE: {
567 SDValue N10 = N1.getOperand(0);
568 SDValue N11 = N1.getOperand(1);
569 RModW = isRMWLoad(N10, Chain, N2, Load);
571 RModW = isRMWLoad(N11, Chain, N2, Load);
584 SDValue N10 = N1.getOperand(0);
585 RModW = isRMWLoad(N10, Chain, N2, Load);
591 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
598 /// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend
599 /// nodes that target the FP stack to be store and load to the stack. This is a
600 /// gross hack. We would like to simply mark these as being illegal, but when
601 /// we do that, legalize produces these when it expands calls, then expands
602 /// these in the same legalize pass. We would like dag combine to be able to
603 /// hack on these between the call expansion and the node legalization. As such
604 /// this pass basically does "really late" legalization of these inline with the
606 void X86DAGToDAGISel::PreprocessForFPConvert() {
607 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
608 E = CurDAG->allnodes_end(); I != E; ) {
609 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
610 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
613 // If the source and destination are SSE registers, then this is a legal
614 // conversion that should not be lowered.
615 EVT SrcVT = N->getOperand(0).getValueType();
616 EVT DstVT = N->getValueType(0);
617 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
618 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
619 if (SrcIsSSE && DstIsSSE)
622 if (!SrcIsSSE && !DstIsSSE) {
623 // If this is an FPStack extension, it is a noop.
624 if (N->getOpcode() == ISD::FP_EXTEND)
626 // If this is a value-preserving FPStack truncation, it is a noop.
627 if (N->getConstantOperandVal(1))
631 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
632 // FPStack has extload and truncstore. SSE can fold direct loads into other
633 // operations. Based on this, decide what we want to do.
635 if (N->getOpcode() == ISD::FP_ROUND)
636 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
638 MemVT = SrcIsSSE ? SrcVT : DstVT;
640 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
641 DebugLoc dl = N->getDebugLoc();
643 // FIXME: optimize the case where the src/dest is a load or store?
644 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
646 MemTmp, NULL, 0, MemVT);
647 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
650 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
651 // extload we created. This will cause general havok on the dag because
652 // anything below the conversion could be folded into other existing nodes.
653 // To avoid invalidating 'I', back it up to the convert node.
655 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
657 // Now that we did that, the node is dead. Increment the iterator to the
658 // next node to process, then delete N.
660 CurDAG->DeleteNode(N);
664 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
665 /// when it has created a SelectionDAG for us to codegen.
666 void X86DAGToDAGISel::InstructionSelect() {
667 const Function *F = MF->getFunction();
668 OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
670 if (OptLevel != CodeGenOpt::None)
673 // FIXME: This should only happen when not compiled with -O0.
674 PreprocessForFPConvert();
676 // Codegen the basic block.
678 DEBUG(errs() << "===== Instruction selection begins:\n");
683 DEBUG(errs() << "===== Instruction selection ends:\n");
686 CurDAG->RemoveDeadNodes();
689 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
690 /// the main function.
691 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
692 MachineFrameInfo *MFI) {
693 const TargetInstrInfo *TII = TM.getInstrInfo();
694 if (Subtarget->isTargetCygMing())
695 BuildMI(BB, DebugLoc::getUnknownLoc(),
696 TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
699 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
700 // If this is main, emit special code for main.
701 MachineBasicBlock *BB = MF.begin();
702 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
703 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
707 bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
708 X86ISelAddressMode &AM) {
709 assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
710 SDValue Segment = N.getOperand(0);
712 if (AM.Segment.getNode() == 0) {
713 AM.Segment = Segment;
720 bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
721 // This optimization is valid because the GNU TLS model defines that
722 // gs:0 (or fs:0 on X86-64) contains its own address.
723 // For more information see http://people.redhat.com/drepper/tls.pdf
725 SDValue Address = N.getOperand(1);
726 if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
727 !MatchSegmentBaseAddress (Address, AM))
733 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
734 /// into an addressing mode. These wrap things that will resolve down into a
735 /// symbol reference. If no match is possible, this returns true, otherwise it
737 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
738 // If the addressing mode already has a symbol as the displacement, we can
739 // never match another symbol.
740 if (AM.hasSymbolicDisplacement())
743 SDValue N0 = N.getOperand(0);
744 CodeModel::Model M = TM.getCodeModel();
746 // Handle X86-64 rip-relative addresses. We check this before checking direct
747 // folding because RIP is preferable to non-RIP accesses.
748 if (Subtarget->is64Bit() &&
749 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
750 // they cannot be folded into immediate fields.
751 // FIXME: This can be improved for kernel and other models?
752 (M == CodeModel::Small || M == CodeModel::Kernel) &&
753 // Base and index reg must be 0 in order to use %rip as base and lowering
755 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
756 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
757 int64_t Offset = AM.Disp + G->getOffset();
758 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
759 AM.GV = G->getGlobal();
761 AM.SymbolFlags = G->getTargetFlags();
762 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
763 int64_t Offset = AM.Disp + CP->getOffset();
764 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
765 AM.CP = CP->getConstVal();
766 AM.Align = CP->getAlignment();
768 AM.SymbolFlags = CP->getTargetFlags();
769 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
770 AM.ES = S->getSymbol();
771 AM.SymbolFlags = S->getTargetFlags();
772 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
773 AM.JT = J->getIndex();
774 AM.SymbolFlags = J->getTargetFlags();
776 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
777 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
780 if (N.getOpcode() == X86ISD::WrapperRIP)
781 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
785 // Handle the case when globals fit in our immediate field: This is true for
786 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit
787 // mode, this results in a non-RIP-relative computation.
788 if (!Subtarget->is64Bit() ||
789 ((M == CodeModel::Small || M == CodeModel::Kernel) &&
790 TM.getRelocationModel() == Reloc::Static)) {
791 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
792 AM.GV = G->getGlobal();
793 AM.Disp += G->getOffset();
794 AM.SymbolFlags = G->getTargetFlags();
795 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
796 AM.CP = CP->getConstVal();
797 AM.Align = CP->getAlignment();
798 AM.Disp += CP->getOffset();
799 AM.SymbolFlags = CP->getTargetFlags();
800 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
801 AM.ES = S->getSymbol();
802 AM.SymbolFlags = S->getTargetFlags();
803 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
804 AM.JT = J->getIndex();
805 AM.SymbolFlags = J->getTargetFlags();
807 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
808 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
816 /// MatchAddress - Add the specified node to the specified addressing mode,
817 /// returning true if it cannot be done. This just pattern matches for the
819 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
820 if (MatchAddressRecursively(N, AM, 0))
823 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
824 // a smaller encoding and avoids a scaled-index.
826 AM.BaseType == X86ISelAddressMode::RegBase &&
827 AM.Base.Reg.getNode() == 0) {
828 AM.Base.Reg = AM.IndexReg;
832 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
833 // because it has a smaller encoding.
834 // TODO: Which other code models can use this?
835 if (TM.getCodeModel() == CodeModel::Small &&
836 Subtarget->is64Bit() &&
838 AM.BaseType == X86ISelAddressMode::RegBase &&
839 AM.Base.Reg.getNode() == 0 &&
840 AM.IndexReg.getNode() == 0 &&
841 AM.SymbolFlags == X86II::MO_NO_FLAG &&
842 AM.hasSymbolicDisplacement())
843 AM.Base.Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
848 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
850 bool is64Bit = Subtarget->is64Bit();
851 DebugLoc dl = N.getDebugLoc();
853 errs() << "MatchAddress: ";
858 return MatchAddressBase(N, AM);
860 CodeModel::Model M = TM.getCodeModel();
862 // If this is already a %rip relative address, we can only merge immediates
863 // into it. Instead of handling this in every case, we handle it here.
864 // RIP relative addressing: %rip + 32-bit displacement!
865 if (AM.isRIPRelative()) {
866 // FIXME: JumpTable and ExternalSymbol address currently don't like
867 // displacements. It isn't very important, but this should be fixed for
869 if (!AM.ES && AM.JT != -1) return true;
871 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) {
872 int64_t Val = AM.Disp + Cst->getSExtValue();
873 if (X86::isOffsetSuitableForCodeModel(Val, M,
874 AM.hasSymbolicDisplacement())) {
882 switch (N.getOpcode()) {
884 case ISD::Constant: {
885 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
887 X86::isOffsetSuitableForCodeModel(AM.Disp + Val, M,
888 AM.hasSymbolicDisplacement())) {
895 case X86ISD::SegmentBaseAddress:
896 if (!MatchSegmentBaseAddress(N, AM))
900 case X86ISD::Wrapper:
901 case X86ISD::WrapperRIP:
902 if (!MatchWrapper(N, AM))
907 if (!MatchLoad(N, AM))
911 case ISD::FrameIndex:
912 if (AM.BaseType == X86ISelAddressMode::RegBase
913 && AM.Base.Reg.getNode() == 0) {
914 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
915 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
921 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
925 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
926 unsigned Val = CN->getZExtValue();
927 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
928 // that the base operand remains free for further matching. If
929 // the base doesn't end up getting used, a post-processing step
930 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
931 if (Val == 1 || Val == 2 || Val == 3) {
933 SDValue ShVal = N.getNode()->getOperand(0);
935 // Okay, we know that we have a scale by now. However, if the scaled
936 // value is an add of something and a constant, we can fold the
937 // constant into the disp field here.
938 if (ShVal.getNode()->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
939 isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
940 AM.IndexReg = ShVal.getNode()->getOperand(0);
941 ConstantSDNode *AddVal =
942 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
943 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
945 X86::isOffsetSuitableForCodeModel(Disp, M,
946 AM.hasSymbolicDisplacement()))
960 // A mul_lohi where we need the low part can be folded as a plain multiply.
961 if (N.getResNo() != 0) break;
964 case X86ISD::MUL_IMM:
965 // X*[3,5,9] -> X+X*[2,4,8]
966 if (AM.BaseType == X86ISelAddressMode::RegBase &&
967 AM.Base.Reg.getNode() == 0 &&
968 AM.IndexReg.getNode() == 0) {
970 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
971 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
972 CN->getZExtValue() == 9) {
973 AM.Scale = unsigned(CN->getZExtValue())-1;
975 SDValue MulVal = N.getNode()->getOperand(0);
978 // Okay, we know that we have a scale by now. However, if the scaled
979 // value is an add of something and a constant, we can fold the
980 // constant into the disp field here.
981 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
982 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
983 Reg = MulVal.getNode()->getOperand(0);
984 ConstantSDNode *AddVal =
985 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
986 uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
989 X86::isOffsetSuitableForCodeModel(Disp, M,
990 AM.hasSymbolicDisplacement()))
993 Reg = N.getNode()->getOperand(0);
995 Reg = N.getNode()->getOperand(0);
998 AM.IndexReg = AM.Base.Reg = Reg;
1005 // Given A-B, if A can be completely folded into the address and
1006 // the index field with the index field unused, use -B as the index.
1007 // This is a win if a has multiple parts that can be folded into
1008 // the address. Also, this saves a mov if the base register has
1009 // other uses, since it avoids a two-address sub instruction, however
1010 // it costs an additional mov if the index register has other uses.
1012 // Test if the LHS of the sub can be folded.
1013 X86ISelAddressMode Backup = AM;
1014 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1018 // Test if the index field is free for use.
1019 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1024 SDValue RHS = N.getNode()->getOperand(1);
1025 // If the RHS involves a register with multiple uses, this
1026 // transformation incurs an extra mov, due to the neg instruction
1027 // clobbering its operand.
1028 if (!RHS.getNode()->hasOneUse() ||
1029 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1030 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1031 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1032 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1033 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1035 // If the base is a register with multiple uses, this
1036 // transformation may save a mov.
1037 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1038 AM.Base.Reg.getNode() &&
1039 !AM.Base.Reg.getNode()->hasOneUse()) ||
1040 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1042 // If the folded LHS was interesting, this transformation saves
1043 // address arithmetic.
1044 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1045 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1046 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1048 // If it doesn't look like it may be an overall win, don't do it.
1054 // Ok, the transformation is legal and appears profitable. Go for it.
1055 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1056 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1060 // Insert the new nodes into the topological ordering.
1061 if (Zero.getNode()->getNodeId() == -1 ||
1062 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1063 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
1064 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
1066 if (Neg.getNode()->getNodeId() == -1 ||
1067 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1068 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
1069 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
1075 X86ISelAddressMode Backup = AM;
1076 if (!MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1) &&
1077 !MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1))
1080 if (!MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1) &&
1081 !MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1))
1085 // If we couldn't fold both operands into the address at the same time,
1086 // see if we can just put each operand into a register and fold at least
1088 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1089 !AM.Base.Reg.getNode() &&
1090 !AM.IndexReg.getNode()) {
1091 AM.Base.Reg = N.getNode()->getOperand(0);
1092 AM.IndexReg = N.getNode()->getOperand(1);
1100 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1101 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1102 X86ISelAddressMode Backup = AM;
1103 uint64_t Offset = CN->getSExtValue();
1104 // Start with the LHS as an addr mode.
1105 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1106 // Address could not have picked a GV address for the displacement.
1108 // On x86-64, the resultant disp must fit in 32-bits.
1110 X86::isOffsetSuitableForCodeModel(AM.Disp + Offset, M,
1111 AM.hasSymbolicDisplacement())) &&
1112 // Check to see if the LHS & C is zero.
1113 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
1122 // Perform some heroic transforms on an and of a constant-count shift
1123 // with a constant to enable use of the scaled offset field.
1125 SDValue Shift = N.getOperand(0);
1126 if (Shift.getNumOperands() != 2) break;
1128 // Scale must not be used already.
1129 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1131 SDValue X = Shift.getOperand(0);
1132 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
1133 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
1134 if (!C1 || !C2) break;
1136 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This
1137 // allows us to convert the shift and and into an h-register extract and
1139 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) {
1140 unsigned ScaleLog = 8 - C1->getZExtValue();
1141 if (ScaleLog > 0 && ScaleLog < 4 &&
1142 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
1143 SDValue Eight = CurDAG->getConstant(8, MVT::i8);
1144 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
1145 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1147 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
1149 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
1150 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1153 // Insert the new nodes into the topological ordering.
1154 if (Eight.getNode()->getNodeId() == -1 ||
1155 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1156 CurDAG->RepositionNode(X.getNode(), Eight.getNode());
1157 Eight.getNode()->setNodeId(X.getNode()->getNodeId());
1159 if (Mask.getNode()->getNodeId() == -1 ||
1160 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1161 CurDAG->RepositionNode(X.getNode(), Mask.getNode());
1162 Mask.getNode()->setNodeId(X.getNode()->getNodeId());
1164 if (Srl.getNode()->getNodeId() == -1 ||
1165 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1166 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode());
1167 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId());
1169 if (And.getNode()->getNodeId() == -1 ||
1170 And.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1171 CurDAG->RepositionNode(N.getNode(), And.getNode());
1172 And.getNode()->setNodeId(N.getNode()->getNodeId());
1174 if (ShlCount.getNode()->getNodeId() == -1 ||
1175 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1176 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode());
1177 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId());
1179 if (Shl.getNode()->getNodeId() == -1 ||
1180 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1181 CurDAG->RepositionNode(N.getNode(), Shl.getNode());
1182 Shl.getNode()->setNodeId(N.getNode()->getNodeId());
1184 CurDAG->ReplaceAllUsesWith(N, Shl);
1186 AM.Scale = (1 << ScaleLog);
1191 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
1192 // allows us to fold the shift into this addressing mode.
1193 if (Shift.getOpcode() != ISD::SHL) break;
1195 // Not likely to be profitable if either the AND or SHIFT node has more
1196 // than one use (unless all uses are for address computation). Besides,
1197 // isel mechanism requires their node ids to be reused.
1198 if (!N.hasOneUse() || !Shift.hasOneUse())
1201 // Verify that the shift amount is something we can fold.
1202 unsigned ShiftCst = C1->getZExtValue();
1203 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
1206 // Get the new AND mask, this folds to a constant.
1207 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1208 SDValue(C2, 0), SDValue(C1, 0));
1209 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
1211 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1212 NewAND, SDValue(C1, 0));
1214 // Insert the new nodes into the topological ordering.
1215 if (C1->getNodeId() > X.getNode()->getNodeId()) {
1216 CurDAG->RepositionNode(X.getNode(), C1);
1217 C1->setNodeId(X.getNode()->getNodeId());
1219 if (NewANDMask.getNode()->getNodeId() == -1 ||
1220 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1221 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
1222 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
1224 if (NewAND.getNode()->getNodeId() == -1 ||
1225 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1226 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
1227 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
1229 if (NewSHIFT.getNode()->getNodeId() == -1 ||
1230 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1231 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
1232 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
1235 CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
1237 AM.Scale = 1 << ShiftCst;
1238 AM.IndexReg = NewAND;
1243 return MatchAddressBase(N, AM);
1246 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1247 /// specified addressing mode without any further recursion.
1248 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1249 // Is the base register already occupied?
1250 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
1251 // If so, check to see if the scale index register is set.
1252 if (AM.IndexReg.getNode() == 0) {
1258 // Otherwise, we cannot select it.
1262 // Default, generate it as a register.
1263 AM.BaseType = X86ISelAddressMode::RegBase;
1268 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1269 /// It returns the operands which make up the maximal addressing mode it can
1270 /// match by reference.
1271 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
1272 SDValue &Scale, SDValue &Index,
1273 SDValue &Disp, SDValue &Segment) {
1274 X86ISelAddressMode AM;
1275 if (MatchAddress(N, AM))
1278 EVT VT = N.getValueType();
1279 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1280 if (!AM.Base.Reg.getNode())
1281 AM.Base.Reg = CurDAG->getRegister(0, VT);
1284 if (!AM.IndexReg.getNode())
1285 AM.IndexReg = CurDAG->getRegister(0, VT);
1287 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1291 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1292 /// match a load whose top elements are either undef or zeros. The load flavor
1293 /// is derived from the type of N, which is either v4f32 or v2f64.
1294 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
1295 SDValue N, SDValue &Base,
1296 SDValue &Scale, SDValue &Index,
1297 SDValue &Disp, SDValue &Segment,
1299 SDValue &OutChain) {
1300 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1301 InChain = N.getOperand(0).getValue(1);
1302 if (ISD::isNON_EXTLoad(InChain.getNode()) &&
1303 InChain.getValue(0).hasOneUse() &&
1305 IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
1306 LoadSDNode *LD = cast<LoadSDNode>(InChain);
1307 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1309 OutChain = LD->getChain();
1314 // Also handle the case where we explicitly require zeros in the top
1315 // elements. This is a vector shuffle from the zero vector.
1316 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1317 // Check to see if the top elements are all zeros (or bitcast of zeros).
1318 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1319 N.getOperand(0).getNode()->hasOneUse() &&
1320 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1321 N.getOperand(0).getOperand(0).hasOneUse()) {
1322 // Okay, this is a zero extending load. Fold it.
1323 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1324 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1326 OutChain = LD->getChain();
1327 InChain = SDValue(LD, 1);
1334 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1335 /// mode it matches can be cost effectively emitted as an LEA instruction.
1336 bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
1337 SDValue &Base, SDValue &Scale,
1338 SDValue &Index, SDValue &Disp) {
1339 X86ISelAddressMode AM;
1341 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1343 SDValue Copy = AM.Segment;
1344 SDValue T = CurDAG->getRegister(0, MVT::i32);
1346 if (MatchAddress(N, AM))
1348 assert (T == AM.Segment);
1351 EVT VT = N.getValueType();
1352 unsigned Complexity = 0;
1353 if (AM.BaseType == X86ISelAddressMode::RegBase)
1354 if (AM.Base.Reg.getNode())
1357 AM.Base.Reg = CurDAG->getRegister(0, VT);
1358 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1361 if (AM.IndexReg.getNode())
1364 AM.IndexReg = CurDAG->getRegister(0, VT);
1366 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1371 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1372 // to a LEA. This is determined with some expermentation but is by no means
1373 // optimal (especially for code size consideration). LEA is nice because of
1374 // its three-address nature. Tweak the cost function again when we can run
1375 // convertToThreeAddress() at register allocation time.
1376 if (AM.hasSymbolicDisplacement()) {
1377 // For X86-64, we should always use lea to materialize RIP relative
1379 if (Subtarget->is64Bit())
1385 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
1388 // If it isn't worth using an LEA, reject it.
1389 if (Complexity <= 2)
1393 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1397 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1398 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
1399 SDValue &Scale, SDValue &Index,
1401 assert(Op.getOpcode() == X86ISD::TLSADDR);
1402 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1403 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1405 X86ISelAddressMode AM;
1406 AM.GV = GA->getGlobal();
1407 AM.Disp += GA->getOffset();
1408 AM.Base.Reg = CurDAG->getRegister(0, N.getValueType());
1409 AM.SymbolFlags = GA->getTargetFlags();
1411 if (N.getValueType() == MVT::i32) {
1413 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1415 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1419 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1424 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
1425 SDValue &Base, SDValue &Scale,
1426 SDValue &Index, SDValue &Disp,
1428 if (ISD::isNON_EXTLoad(N.getNode()) &&
1430 IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
1431 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
1435 /// getGlobalBaseReg - Return an SDNode that returns the value of
1436 /// the global base register. Output instructions required to
1437 /// initialize the global base register, if necessary.
1439 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1440 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1441 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1444 static SDNode *FindCallStartFromCall(SDNode *Node) {
1445 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1446 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1447 "Node doesn't have a token chain argument!");
1448 return FindCallStartFromCall(Node->getOperand(0).getNode());
1451 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1452 SDValue Chain = Node->getOperand(0);
1453 SDValue In1 = Node->getOperand(1);
1454 SDValue In2L = Node->getOperand(2);
1455 SDValue In2H = Node->getOperand(3);
1456 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1457 if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1459 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1460 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1461 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1462 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1463 MVT::i32, MVT::i32, MVT::Other, Ops,
1464 array_lengthof(Ops));
1465 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1469 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1470 if (Node->hasAnyUseOfValue(0))
1473 // Optimize common patterns for __sync_add_and_fetch and
1474 // __sync_sub_and_fetch where the result is not used. This allows us
1475 // to use "lock" version of add, sub, inc, dec instructions.
1476 // FIXME: Do not use special instructions but instead add the "lock"
1477 // prefix to the target node somehow. The extra information will then be
1478 // transferred to machine instruction and it denotes the prefix.
1479 SDValue Chain = Node->getOperand(0);
1480 SDValue Ptr = Node->getOperand(1);
1481 SDValue Val = Node->getOperand(2);
1482 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1483 if (!SelectAddr(Ptr, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1486 bool isInc = false, isDec = false, isSub = false, isCN = false;
1487 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1490 int64_t CNVal = CN->getSExtValue();
1493 else if (CNVal == -1)
1495 else if (CNVal >= 0)
1496 Val = CurDAG->getTargetConstant(CNVal, NVT);
1499 Val = CurDAG->getTargetConstant(-CNVal, NVT);
1501 } else if (Val.hasOneUse() &&
1502 Val.getOpcode() == ISD::SUB &&
1503 X86::isZeroNode(Val.getOperand(0))) {
1505 Val = Val.getOperand(1);
1509 switch (NVT.getSimpleVT().SimpleTy) {
1513 Opc = X86::LOCK_INC8m;
1515 Opc = X86::LOCK_DEC8m;
1518 Opc = X86::LOCK_SUB8mi;
1520 Opc = X86::LOCK_SUB8mr;
1523 Opc = X86::LOCK_ADD8mi;
1525 Opc = X86::LOCK_ADD8mr;
1530 Opc = X86::LOCK_INC16m;
1532 Opc = X86::LOCK_DEC16m;
1535 if (Predicate_i16immSExt8(Val.getNode()))
1536 Opc = X86::LOCK_SUB16mi8;
1538 Opc = X86::LOCK_SUB16mi;
1540 Opc = X86::LOCK_SUB16mr;
1543 if (Predicate_i16immSExt8(Val.getNode()))
1544 Opc = X86::LOCK_ADD16mi8;
1546 Opc = X86::LOCK_ADD16mi;
1548 Opc = X86::LOCK_ADD16mr;
1553 Opc = X86::LOCK_INC32m;
1555 Opc = X86::LOCK_DEC32m;
1558 if (Predicate_i32immSExt8(Val.getNode()))
1559 Opc = X86::LOCK_SUB32mi8;
1561 Opc = X86::LOCK_SUB32mi;
1563 Opc = X86::LOCK_SUB32mr;
1566 if (Predicate_i32immSExt8(Val.getNode()))
1567 Opc = X86::LOCK_ADD32mi8;
1569 Opc = X86::LOCK_ADD32mi;
1571 Opc = X86::LOCK_ADD32mr;
1576 Opc = X86::LOCK_INC64m;
1578 Opc = X86::LOCK_DEC64m;
1580 Opc = X86::LOCK_SUB64mr;
1582 if (Predicate_i64immSExt8(Val.getNode()))
1583 Opc = X86::LOCK_SUB64mi8;
1584 else if (Predicate_i64immSExt32(Val.getNode()))
1585 Opc = X86::LOCK_SUB64mi32;
1588 Opc = X86::LOCK_ADD64mr;
1590 if (Predicate_i64immSExt8(Val.getNode()))
1591 Opc = X86::LOCK_ADD64mi8;
1592 else if (Predicate_i64immSExt32(Val.getNode()))
1593 Opc = X86::LOCK_ADD64mi32;
1599 DebugLoc dl = Node->getDebugLoc();
1600 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
1602 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1603 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1604 if (isInc || isDec) {
1605 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1606 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
1607 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1608 SDValue RetVals[] = { Undef, Ret };
1609 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1611 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1612 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1613 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1614 SDValue RetVals[] = { Undef, Ret };
1615 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1619 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1620 /// any uses which require the SF or OF bits to be accurate.
1621 static bool HasNoSignedComparisonUses(SDNode *N) {
1622 // Examine each user of the node.
1623 for (SDNode::use_iterator UI = N->use_begin(),
1624 UE = N->use_end(); UI != UE; ++UI) {
1625 // Only examine CopyToReg uses.
1626 if (UI->getOpcode() != ISD::CopyToReg)
1628 // Only examine CopyToReg uses that copy to EFLAGS.
1629 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1632 // Examine each user of the CopyToReg use.
1633 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1634 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1635 // Only examine the Flag result.
1636 if (FlagUI.getUse().getResNo() != 1) continue;
1637 // Anything unusual: assume conservatively.
1638 if (!FlagUI->isMachineOpcode()) return false;
1639 // Examine the opcode of the user.
1640 switch (FlagUI->getMachineOpcode()) {
1641 // These comparisons don't treat the most significant bit specially.
1642 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1643 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1644 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1645 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1646 case X86::JA: case X86::JAE: case X86::JB: case X86::JBE:
1647 case X86::JE: case X86::JNE: case X86::JP: case X86::JNP:
1648 case X86::CMOVA16rr: case X86::CMOVA16rm:
1649 case X86::CMOVA32rr: case X86::CMOVA32rm:
1650 case X86::CMOVA64rr: case X86::CMOVA64rm:
1651 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1652 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1653 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1654 case X86::CMOVB16rr: case X86::CMOVB16rm:
1655 case X86::CMOVB32rr: case X86::CMOVB32rm:
1656 case X86::CMOVB64rr: case X86::CMOVB64rm:
1657 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1658 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1659 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1660 case X86::CMOVE16rr: case X86::CMOVE16rm:
1661 case X86::CMOVE32rr: case X86::CMOVE32rm:
1662 case X86::CMOVE64rr: case X86::CMOVE64rm:
1663 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1664 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1665 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1666 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1667 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1668 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1669 case X86::CMOVP16rr: case X86::CMOVP16rm:
1670 case X86::CMOVP32rr: case X86::CMOVP32rm:
1671 case X86::CMOVP64rr: case X86::CMOVP64rm:
1673 // Anything else: assume conservatively.
1674 default: return false;
1681 SDNode *X86DAGToDAGISel::Select(SDValue N) {
1682 SDNode *Node = N.getNode();
1683 EVT NVT = Node->getValueType(0);
1685 unsigned Opcode = Node->getOpcode();
1686 DebugLoc dl = Node->getDebugLoc();
1690 errs() << std::string(Indent, ' ') << "Selecting: ";
1697 if (Node->isMachineOpcode()) {
1700 errs() << std::string(Indent-2, ' ') << "== ";
1706 return NULL; // Already selected.
1711 case X86ISD::GlobalBaseReg:
1712 return getGlobalBaseReg();
1714 case X86ISD::ATOMOR64_DAG:
1715 return SelectAtomic64(Node, X86::ATOMOR6432);
1716 case X86ISD::ATOMXOR64_DAG:
1717 return SelectAtomic64(Node, X86::ATOMXOR6432);
1718 case X86ISD::ATOMADD64_DAG:
1719 return SelectAtomic64(Node, X86::ATOMADD6432);
1720 case X86ISD::ATOMSUB64_DAG:
1721 return SelectAtomic64(Node, X86::ATOMSUB6432);
1722 case X86ISD::ATOMNAND64_DAG:
1723 return SelectAtomic64(Node, X86::ATOMNAND6432);
1724 case X86ISD::ATOMAND64_DAG:
1725 return SelectAtomic64(Node, X86::ATOMAND6432);
1726 case X86ISD::ATOMSWAP64_DAG:
1727 return SelectAtomic64(Node, X86::ATOMSWAP6432);
1729 case ISD::ATOMIC_LOAD_ADD: {
1730 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
1736 case ISD::SMUL_LOHI:
1737 case ISD::UMUL_LOHI: {
1738 SDValue N0 = Node->getOperand(0);
1739 SDValue N1 = Node->getOperand(1);
1741 bool isSigned = Opcode == ISD::SMUL_LOHI;
1743 switch (NVT.getSimpleVT().SimpleTy) {
1744 default: llvm_unreachable("Unsupported VT!");
1745 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1746 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1747 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1748 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1751 switch (NVT.getSimpleVT().SimpleTy) {
1752 default: llvm_unreachable("Unsupported VT!");
1753 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1754 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1755 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1756 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1760 unsigned LoReg, HiReg;
1761 switch (NVT.getSimpleVT().SimpleTy) {
1762 default: llvm_unreachable("Unsupported VT!");
1763 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1764 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1765 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1766 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1769 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1770 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1771 // Multiply is commmutative.
1773 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1778 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1779 N0, SDValue()).getValue(1);
1782 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1785 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1786 array_lengthof(Ops));
1787 InFlag = SDValue(CNode, 1);
1788 // Update the chain.
1789 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1792 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1795 // Copy the low half of the result, if it is needed.
1796 if (!N.getValue(0).use_empty()) {
1797 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1798 LoReg, NVT, InFlag);
1799 InFlag = Result.getValue(2);
1800 ReplaceUses(N.getValue(0), Result);
1803 errs() << std::string(Indent-2, ' ') << "=> ";
1804 Result.getNode()->dump(CurDAG);
1809 // Copy the high half of the result, if it is needed.
1810 if (!N.getValue(1).use_empty()) {
1812 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1813 // Prevent use of AH in a REX instruction by referencing AX instead.
1814 // Shift it down 8 bits.
1815 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1816 X86::AX, MVT::i16, InFlag);
1817 InFlag = Result.getValue(2);
1818 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
1820 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1821 // Then truncate it down to i8.
1822 Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
1825 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1826 HiReg, NVT, InFlag);
1827 InFlag = Result.getValue(2);
1829 ReplaceUses(N.getValue(1), Result);
1832 errs() << std::string(Indent-2, ' ') << "=> ";
1833 Result.getNode()->dump(CurDAG);
1847 case ISD::UDIVREM: {
1848 SDValue N0 = Node->getOperand(0);
1849 SDValue N1 = Node->getOperand(1);
1851 bool isSigned = Opcode == ISD::SDIVREM;
1853 switch (NVT.getSimpleVT().SimpleTy) {
1854 default: llvm_unreachable("Unsupported VT!");
1855 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1856 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1857 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1858 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1861 switch (NVT.getSimpleVT().SimpleTy) {
1862 default: llvm_unreachable("Unsupported VT!");
1863 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1864 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1865 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1866 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1870 unsigned LoReg, HiReg, ClrReg;
1871 unsigned ClrOpcode, SExtOpcode;
1873 switch (NVT.getSimpleVT().SimpleTy) {
1874 default: llvm_unreachable("Unsupported VT!");
1876 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
1878 SExtOpcode = X86::CBW;
1881 LoReg = X86::AX; HiReg = X86::DX;
1882 ClrOpcode = X86::MOV32r0; ClrReg = X86::EDX; ClrVT = MVT::i32;
1883 SExtOpcode = X86::CWD;
1886 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
1887 ClrOpcode = X86::MOV32r0;
1888 SExtOpcode = X86::CDQ;
1891 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
1892 ClrOpcode = ~0U; // NOT USED.
1893 SExtOpcode = X86::CQO;
1897 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1898 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1899 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
1902 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
1903 // Special case for div8, just use a move with zero extension to AX to
1904 // clear the upper 8 bits (AH).
1905 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
1906 if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
1907 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
1909 SDValue(CurDAG->getMachineNode(X86::MOVZX16rm8, dl, MVT::i16,
1911 array_lengthof(Ops)), 0);
1912 Chain = Move.getValue(1);
1913 ReplaceUses(N0.getValue(1), Chain);
1916 SDValue(CurDAG->getMachineNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
1917 Chain = CurDAG->getEntryNode();
1919 Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
1920 InFlag = Chain.getValue(1);
1923 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
1924 LoReg, N0, SDValue()).getValue(1);
1925 if (isSigned && !signBitIsZero) {
1926 // Sign extend the low part into the high part.
1928 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
1930 // Zero out the high part, effectively zero extending the input.
1933 if (NVT.getSimpleVT() == MVT::i64) {
1934 ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, MVT::i32),
1936 // We just did a 32-bit clear, insert it into a 64-bit register to
1937 // clear the whole 64-bit reg.
1938 SDValue Zero = CurDAG->getTargetConstant(0, MVT::i64);
1940 CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
1942 SDValue(CurDAG->getMachineNode(TargetInstrInfo::SUBREG_TO_REG, dl,
1943 MVT::i64, Zero, ClrNode, SubRegNo),
1946 ClrNode = SDValue(CurDAG->getMachineNode(ClrOpcode, dl, ClrVT), 0);
1949 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
1950 ClrNode, InFlag).getValue(1);
1955 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1958 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1959 array_lengthof(Ops));
1960 InFlag = SDValue(CNode, 1);
1961 // Update the chain.
1962 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1965 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1968 // Copy the division (low) result, if it is needed.
1969 if (!N.getValue(0).use_empty()) {
1970 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1971 LoReg, NVT, InFlag);
1972 InFlag = Result.getValue(2);
1973 ReplaceUses(N.getValue(0), Result);
1976 errs() << std::string(Indent-2, ' ') << "=> ";
1977 Result.getNode()->dump(CurDAG);
1982 // Copy the remainder (high) result, if it is needed.
1983 if (!N.getValue(1).use_empty()) {
1985 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1986 // Prevent use of AH in a REX instruction by referencing AX instead.
1987 // Shift it down 8 bits.
1988 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1989 X86::AX, MVT::i16, InFlag);
1990 InFlag = Result.getValue(2);
1991 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
1993 CurDAG->getTargetConstant(8, MVT::i8)),
1995 // Then truncate it down to i8.
1996 Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
1999 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2000 HiReg, NVT, InFlag);
2001 InFlag = Result.getValue(2);
2003 ReplaceUses(N.getValue(1), Result);
2006 errs() << std::string(Indent-2, ' ') << "=> ";
2007 Result.getNode()->dump(CurDAG);
2021 SDValue N0 = Node->getOperand(0);
2022 SDValue N1 = Node->getOperand(1);
2024 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2025 // use a smaller encoding.
2026 if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2027 N0.getValueType() != MVT::i8 &&
2028 X86::isZeroNode(N1)) {
2029 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2032 // For example, convert "testl %eax, $8" to "testb %al, $8"
2033 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2034 (!(C->getZExtValue() & 0x80) ||
2035 HasNoSignedComparisonUses(Node))) {
2036 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2037 SDValue Reg = N0.getNode()->getOperand(0);
2039 // On x86-32, only the ABCD registers have 8-bit subregisters.
2040 if (!Subtarget->is64Bit()) {
2041 TargetRegisterClass *TRC = 0;
2042 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2043 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2044 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2045 default: llvm_unreachable("Unsupported TEST operand type!");
2047 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2048 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2049 Reg.getValueType(), Reg, RC), 0);
2052 // Extract the l-register.
2053 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
2057 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
2060 // For example, "testl %eax, $2048" to "testb %ah, $8".
2061 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2062 (!(C->getZExtValue() & 0x8000) ||
2063 HasNoSignedComparisonUses(Node))) {
2064 // Shift the immediate right by 8 bits.
2065 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2067 SDValue Reg = N0.getNode()->getOperand(0);
2069 // Put the value in an ABCD register.
2070 TargetRegisterClass *TRC = 0;
2071 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2072 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2073 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2074 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2075 default: llvm_unreachable("Unsupported TEST operand type!");
2077 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2078 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2079 Reg.getValueType(), Reg, RC), 0);
2081 // Extract the h-register.
2082 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT_HI, dl,
2085 // Emit a testb. No special NOREX tricks are needed since there's
2086 // only one GPR operand!
2087 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2088 Subreg, ShiftedImm);
2091 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2092 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2093 N0.getValueType() != MVT::i16 &&
2094 (!(C->getZExtValue() & 0x8000) ||
2095 HasNoSignedComparisonUses(Node))) {
2096 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2097 SDValue Reg = N0.getNode()->getOperand(0);
2099 // Extract the 16-bit subregister.
2100 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_16BIT, dl,
2104 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
2107 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2108 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2109 N0.getValueType() == MVT::i64 &&
2110 (!(C->getZExtValue() & 0x80000000) ||
2111 HasNoSignedComparisonUses(Node))) {
2112 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2113 SDValue Reg = N0.getNode()->getOperand(0);
2115 // Extract the 32-bit subregister.
2116 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_32BIT, dl,
2120 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
2127 SDNode *ResNode = SelectCode(N);
2131 errs() << std::string(Indent-2, ' ') << "=> ";
2132 if (ResNode == NULL || ResNode == N.getNode())
2133 N.getNode()->dump(CurDAG);
2135 ResNode->dump(CurDAG);
2144 bool X86DAGToDAGISel::
2145 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2146 std::vector<SDValue> &OutOps) {
2147 SDValue Op0, Op1, Op2, Op3, Op4;
2148 switch (ConstraintCode) {
2149 case 'o': // offsetable ??
2150 case 'v': // not offsetable ??
2151 default: return true;
2153 if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
2158 OutOps.push_back(Op0);
2159 OutOps.push_back(Op1);
2160 OutOps.push_back(Op2);
2161 OutOps.push_back(Op3);
2162 OutOps.push_back(Op4);
2166 /// createX86ISelDag - This pass converts a legalized DAG into a
2167 /// X86-specific DAG, ready for instruction scheduling.
2169 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2170 llvm::CodeGenOpt::Level OptLevel) {
2171 return new X86DAGToDAGISel(TM, OptLevel);