1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CFG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/Statistic.h"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
77 SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
84 bool hasBaseOrIndexReg() const {
85 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
88 /// isRIPRelative - Return true if this addressing mode is already RIP
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
103 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
105 dbgs() << "X86ISelAddressMode " << this << '\n';
106 dbgs() << "Base_Reg ";
107 if (Base_Reg.getNode() != 0)
108 Base_Reg.getNode()->dump();
111 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
112 << " Scale" << Scale << '\n'
114 if (IndexReg.getNode() != 0)
115 IndexReg.getNode()->dump();
118 dbgs() << " Disp " << Disp << '\n'
135 dbgs() << " JT" << JT << " Align" << Align << '\n';
142 //===--------------------------------------------------------------------===//
143 /// ISel - X86 specific code to select X86 machine instructions for
144 /// SelectionDAG operations.
146 class X86DAGToDAGISel : public SelectionDAGISel {
147 /// X86Lowering - This object fully describes how to lower LLVM code to an
148 /// X86-specific SelectionDAG.
149 const X86TargetLowering &X86Lowering;
151 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
152 /// make the right decision when generating code for different targets.
153 const X86Subtarget *Subtarget;
155 /// OptForSize - If true, selector should try to optimize for code size
156 /// instead of performance.
160 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
161 : SelectionDAGISel(tm, OptLevel),
162 X86Lowering(*tm.getTargetLowering()),
163 Subtarget(&tm.getSubtarget<X86Subtarget>()),
166 virtual const char *getPassName() const {
167 return "X86 DAG->DAG Instruction Selection";
170 virtual void EmitFunctionEntryCode();
172 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
174 virtual void PreprocessISelDAG();
176 inline bool immSext8(SDNode *N) const {
177 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
180 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
181 // sign extended field.
182 inline bool i64immSExt32(SDNode *N) const {
183 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
184 return (int64_t)v == (int32_t)v;
187 // Include the pieces autogenerated from the target description.
188 #include "X86GenDAGISel.inc"
191 SDNode *Select(SDNode *N);
192 SDNode *SelectGather(SDNode *N, unsigned Opc);
193 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
194 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
195 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT);
197 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
198 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
204 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectLEAAddr(SDValue N, SDValue &Base,
208 SDValue &Scale, SDValue &Index, SDValue &Disp,
210 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
211 SDValue &Scale, SDValue &Index, SDValue &Disp,
213 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
214 SDValue &Base, SDValue &Scale,
215 SDValue &Index, SDValue &Disp,
217 SDValue &NodeWithChain);
219 bool TryFoldLoad(SDNode *P, SDValue N,
220 SDValue &Base, SDValue &Scale,
221 SDValue &Index, SDValue &Disp,
224 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
225 /// inline asm expressions.
226 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
228 std::vector<SDValue> &OutOps);
230 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
232 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
233 SDValue &Scale, SDValue &Index,
234 SDValue &Disp, SDValue &Segment) {
235 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
236 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
238 Scale = getI8Imm(AM.Scale);
240 // These are 32-bit even in 64-bit mode since RIP relative offset
243 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(),
247 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
248 AM.Align, AM.Disp, AM.SymbolFlags);
250 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
251 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
252 } else if (AM.JT != -1) {
253 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
254 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
255 } else if (AM.BlockAddr)
256 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
259 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
261 if (AM.Segment.getNode())
262 Segment = AM.Segment;
264 Segment = CurDAG->getRegister(0, MVT::i32);
267 /// getI8Imm - Return a target constant with the specified value, of type
269 inline SDValue getI8Imm(unsigned Imm) {
270 return CurDAG->getTargetConstant(Imm, MVT::i8);
273 /// getI32Imm - Return a target constant with the specified value, of type
275 inline SDValue getI32Imm(unsigned Imm) {
276 return CurDAG->getTargetConstant(Imm, MVT::i32);
279 /// getGlobalBaseReg - Return an SDNode that returns the value of
280 /// the global base register. Output instructions required to
281 /// initialize the global base register, if necessary.
283 SDNode *getGlobalBaseReg();
285 /// getTargetMachine - Return a reference to the TargetMachine, casted
286 /// to the target-specific type.
287 const X86TargetMachine &getTargetMachine() {
288 return static_cast<const X86TargetMachine &>(TM);
291 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
292 /// to the target-specific type.
293 const X86InstrInfo *getInstrInfo() {
294 return getTargetMachine().getInstrInfo();
301 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
302 if (OptLevel == CodeGenOpt::None) return false;
307 if (N.getOpcode() != ISD::LOAD)
310 // If N is a load, do additional profitability checks.
312 switch (U->getOpcode()) {
325 SDValue Op1 = U->getOperand(1);
327 // If the other operand is a 8-bit immediate we should fold the immediate
328 // instead. This reduces code size.
330 // movl 4(%esp), %eax
334 // addl 4(%esp), %eax
335 // The former is 2 bytes shorter. In case where the increment is 1, then
336 // the saving can be 4 bytes (by using incl %eax).
337 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
338 if (Imm->getAPIntValue().isSignedIntN(8))
341 // If the other operand is a TLS address, we should fold it instead.
344 // leal i@NTPOFF(%eax), %eax
346 // movl $i@NTPOFF, %eax
348 // if the block also has an access to a second TLS address this will save
350 // FIXME: This is probably also true for non TLS addresses.
351 if (Op1.getOpcode() == X86ISD::Wrapper) {
352 SDValue Val = Op1.getOperand(0);
353 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
363 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
364 /// load's chain operand and move load below the call's chain operand.
365 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
366 SDValue Call, SDValue OrigChain) {
367 SmallVector<SDValue, 8> Ops;
368 SDValue Chain = OrigChain.getOperand(0);
369 if (Chain.getNode() == Load.getNode())
370 Ops.push_back(Load.getOperand(0));
372 assert(Chain.getOpcode() == ISD::TokenFactor &&
373 "Unexpected chain operand");
374 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
375 if (Chain.getOperand(i).getNode() == Load.getNode())
376 Ops.push_back(Load.getOperand(0));
378 Ops.push_back(Chain.getOperand(i));
380 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
381 MVT::Other, &Ops[0], Ops.size());
383 Ops.push_back(NewChain);
385 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
386 Ops.push_back(OrigChain.getOperand(i));
387 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
388 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
389 Load.getOperand(1), Load.getOperand(2));
391 Ops.push_back(SDValue(Load.getNode(), 1));
392 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
393 Ops.push_back(Call.getOperand(i));
394 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size());
397 /// isCalleeLoad - Return true if call address is a load and it can be
398 /// moved below CALLSEQ_START and the chains leading up to the call.
399 /// Return the CALLSEQ_START by reference as a second output.
400 /// In the case of a tail call, there isn't a callseq node between the call
401 /// chain and the load.
402 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
403 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
405 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
408 LD->getAddressingMode() != ISD::UNINDEXED ||
409 LD->getExtensionType() != ISD::NON_EXTLOAD)
412 // Now let's find the callseq_start.
413 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
414 if (!Chain.hasOneUse())
416 Chain = Chain.getOperand(0);
419 if (!Chain.getNumOperands())
421 if (Chain.getOperand(0).getNode() == Callee.getNode())
423 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
424 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
425 Callee.getValue(1).hasOneUse())
430 void X86DAGToDAGISel::PreprocessISelDAG() {
431 // OptForSize is used in pattern predicates that isel is matching.
432 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
434 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
435 E = CurDAG->allnodes_end(); I != E; ) {
436 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
438 if (OptLevel != CodeGenOpt::None &&
439 (N->getOpcode() == X86ISD::CALL ||
440 N->getOpcode() == X86ISD::TC_RETURN)) {
441 /// Also try moving call address load from outside callseq_start to just
442 /// before the call to allow it to be folded.
460 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
461 SDValue Chain = N->getOperand(0);
462 SDValue Load = N->getOperand(1);
463 if (!isCalleeLoad(Load, Chain, HasCallSeq))
465 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
470 // Lower fpround and fpextend nodes that target the FP stack to be store and
471 // load to the stack. This is a gross hack. We would like to simply mark
472 // these as being illegal, but when we do that, legalize produces these when
473 // it expands calls, then expands these in the same legalize pass. We would
474 // like dag combine to be able to hack on these between the call expansion
475 // and the node legalization. As such this pass basically does "really
476 // late" legalization of these inline with the X86 isel pass.
477 // FIXME: This should only happen when not compiled with -O0.
478 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
481 EVT SrcVT = N->getOperand(0).getValueType();
482 EVT DstVT = N->getValueType(0);
484 // If any of the sources are vectors, no fp stack involved.
485 if (SrcVT.isVector() || DstVT.isVector())
488 // If the source and destination are SSE registers, then this is a legal
489 // conversion that should not be lowered.
490 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
491 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
492 if (SrcIsSSE && DstIsSSE)
495 if (!SrcIsSSE && !DstIsSSE) {
496 // If this is an FPStack extension, it is a noop.
497 if (N->getOpcode() == ISD::FP_EXTEND)
499 // If this is a value-preserving FPStack truncation, it is a noop.
500 if (N->getConstantOperandVal(1))
504 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
505 // FPStack has extload and truncstore. SSE can fold direct loads into other
506 // operations. Based on this, decide what we want to do.
508 if (N->getOpcode() == ISD::FP_ROUND)
509 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
511 MemVT = SrcIsSSE ? SrcVT : DstVT;
513 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
514 DebugLoc dl = N->getDebugLoc();
516 // FIXME: optimize the case where the src/dest is a load or store?
517 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
519 MemTmp, MachinePointerInfo(), MemVT,
521 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
522 MachinePointerInfo(),
523 MemVT, false, false, 0);
525 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
526 // extload we created. This will cause general havok on the dag because
527 // anything below the conversion could be folded into other existing nodes.
528 // To avoid invalidating 'I', back it up to the convert node.
530 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
532 // Now that we did that, the node is dead. Increment the iterator to the
533 // next node to process, then delete N.
535 CurDAG->DeleteNode(N);
540 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
541 /// the main function.
542 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
543 MachineFrameInfo *MFI) {
544 const TargetInstrInfo *TII = TM.getInstrInfo();
545 if (Subtarget->isTargetCygMing()) {
547 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
548 BuildMI(BB, DebugLoc(),
549 TII->get(CallOp)).addExternalSymbol("__main");
553 void X86DAGToDAGISel::EmitFunctionEntryCode() {
554 // If this is main, emit special code for main.
555 if (const Function *Fn = MF->getFunction())
556 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
557 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
560 static bool isDispSafeForFrameIndex(int64_t Val) {
561 // On 64-bit platforms, we can run into an issue where a frame index
562 // includes a displacement that, when added to the explicit displacement,
563 // will overflow the displacement field. Assuming that the frame index
564 // displacement fits into a 31-bit integer (which is only slightly more
565 // aggressive than the current fundamental assumption that it fits into
566 // a 32-bit integer), a 31-bit disp should always be safe.
567 return isInt<31>(Val);
570 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
571 X86ISelAddressMode &AM) {
572 int64_t Val = AM.Disp + Offset;
573 CodeModel::Model M = TM.getCodeModel();
574 if (Subtarget->is64Bit()) {
575 if (!X86::isOffsetSuitableForCodeModel(Val, M,
576 AM.hasSymbolicDisplacement()))
578 // In addition to the checks required for a register base, check that
579 // we do not try to use an unsafe Disp with a frame index.
580 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
581 !isDispSafeForFrameIndex(Val))
589 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
590 SDValue Address = N->getOperand(1);
592 // load gs:0 -> GS segment register.
593 // load fs:0 -> FS segment register.
595 // This optimization is valid because the GNU TLS model defines that
596 // gs:0 (or fs:0 on X86-64) contains its own address.
597 // For more information see http://people.redhat.com/drepper/tls.pdf
598 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
599 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
600 Subtarget->isTargetLinux())
601 switch (N->getPointerInfo().getAddrSpace()) {
603 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
606 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
613 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
614 /// into an addressing mode. These wrap things that will resolve down into a
615 /// symbol reference. If no match is possible, this returns true, otherwise it
617 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
618 // If the addressing mode already has a symbol as the displacement, we can
619 // never match another symbol.
620 if (AM.hasSymbolicDisplacement())
623 SDValue N0 = N.getOperand(0);
624 CodeModel::Model M = TM.getCodeModel();
626 // Handle X86-64 rip-relative addresses. We check this before checking direct
627 // folding because RIP is preferable to non-RIP accesses.
628 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
629 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
630 // they cannot be folded into immediate fields.
631 // FIXME: This can be improved for kernel and other models?
632 (M == CodeModel::Small || M == CodeModel::Kernel)) {
633 // Base and index reg must be 0 in order to use %rip as base.
634 if (AM.hasBaseOrIndexReg())
636 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
637 X86ISelAddressMode Backup = AM;
638 AM.GV = G->getGlobal();
639 AM.SymbolFlags = G->getTargetFlags();
640 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
644 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
645 X86ISelAddressMode Backup = AM;
646 AM.CP = CP->getConstVal();
647 AM.Align = CP->getAlignment();
648 AM.SymbolFlags = CP->getTargetFlags();
649 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
653 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
654 AM.ES = S->getSymbol();
655 AM.SymbolFlags = S->getTargetFlags();
656 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
657 AM.JT = J->getIndex();
658 AM.SymbolFlags = J->getTargetFlags();
659 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
660 X86ISelAddressMode Backup = AM;
661 AM.BlockAddr = BA->getBlockAddress();
662 AM.SymbolFlags = BA->getTargetFlags();
663 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
668 llvm_unreachable("Unhandled symbol reference node.");
670 if (N.getOpcode() == X86ISD::WrapperRIP)
671 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
675 // Handle the case when globals fit in our immediate field: This is true for
676 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
677 // mode, this only applies to a non-RIP-relative computation.
678 if (!Subtarget->is64Bit() ||
679 M == CodeModel::Small || M == CodeModel::Kernel) {
680 assert(N.getOpcode() != X86ISD::WrapperRIP &&
681 "RIP-relative addressing already handled");
682 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
683 AM.GV = G->getGlobal();
684 AM.Disp += G->getOffset();
685 AM.SymbolFlags = G->getTargetFlags();
686 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
687 AM.CP = CP->getConstVal();
688 AM.Align = CP->getAlignment();
689 AM.Disp += CP->getOffset();
690 AM.SymbolFlags = CP->getTargetFlags();
691 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
692 AM.ES = S->getSymbol();
693 AM.SymbolFlags = S->getTargetFlags();
694 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
695 AM.JT = J->getIndex();
696 AM.SymbolFlags = J->getTargetFlags();
697 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
698 AM.BlockAddr = BA->getBlockAddress();
699 AM.Disp += BA->getOffset();
700 AM.SymbolFlags = BA->getTargetFlags();
702 llvm_unreachable("Unhandled symbol reference node.");
709 /// MatchAddress - Add the specified node to the specified addressing mode,
710 /// returning true if it cannot be done. This just pattern matches for the
712 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
713 if (MatchAddressRecursively(N, AM, 0))
716 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
717 // a smaller encoding and avoids a scaled-index.
719 AM.BaseType == X86ISelAddressMode::RegBase &&
720 AM.Base_Reg.getNode() == 0) {
721 AM.Base_Reg = AM.IndexReg;
725 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
726 // because it has a smaller encoding.
727 // TODO: Which other code models can use this?
728 if (TM.getCodeModel() == CodeModel::Small &&
729 Subtarget->is64Bit() &&
731 AM.BaseType == X86ISelAddressMode::RegBase &&
732 AM.Base_Reg.getNode() == 0 &&
733 AM.IndexReg.getNode() == 0 &&
734 AM.SymbolFlags == X86II::MO_NO_FLAG &&
735 AM.hasSymbolicDisplacement())
736 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
741 // Insert a node into the DAG at least before the Pos node's position. This
742 // will reposition the node as needed, and will assign it a node ID that is <=
743 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
744 // IDs! The selection DAG must no longer depend on their uniqueness when this
746 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
747 if (N.getNode()->getNodeId() == -1 ||
748 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
749 DAG.RepositionNode(Pos.getNode(), N.getNode());
750 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
754 // Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
755 // allows us to convert the shift and and into an h-register extract and
756 // a scaled index. Returns false if the simplification is performed.
757 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
759 SDValue Shift, SDValue X,
760 X86ISelAddressMode &AM) {
761 if (Shift.getOpcode() != ISD::SRL ||
762 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
766 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
767 if (ScaleLog <= 0 || ScaleLog >= 4 ||
768 Mask != (0xffu << ScaleLog))
771 EVT VT = N.getValueType();
772 DebugLoc DL = N.getDebugLoc();
773 SDValue Eight = DAG.getConstant(8, MVT::i8);
774 SDValue NewMask = DAG.getConstant(0xff, VT);
775 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
776 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
777 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
778 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
780 // Insert the new nodes into the topological ordering. We must do this in
781 // a valid topological ordering as nothing is going to go back and re-sort
782 // these nodes. We continually insert before 'N' in sequence as this is
783 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
784 // hierarchy left to express.
785 InsertDAGNode(DAG, N, Eight);
786 InsertDAGNode(DAG, N, Srl);
787 InsertDAGNode(DAG, N, NewMask);
788 InsertDAGNode(DAG, N, And);
789 InsertDAGNode(DAG, N, ShlCount);
790 InsertDAGNode(DAG, N, Shl);
791 DAG.ReplaceAllUsesWith(N, Shl);
793 AM.Scale = (1 << ScaleLog);
797 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
798 // allows us to fold the shift into this addressing mode. Returns false if the
799 // transform succeeded.
800 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
802 SDValue Shift, SDValue X,
803 X86ISelAddressMode &AM) {
804 if (Shift.getOpcode() != ISD::SHL ||
805 !isa<ConstantSDNode>(Shift.getOperand(1)))
808 // Not likely to be profitable if either the AND or SHIFT node has more
809 // than one use (unless all uses are for address computation). Besides,
810 // isel mechanism requires their node ids to be reused.
811 if (!N.hasOneUse() || !Shift.hasOneUse())
814 // Verify that the shift amount is something we can fold.
815 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
816 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
819 EVT VT = N.getValueType();
820 DebugLoc DL = N.getDebugLoc();
821 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
822 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
823 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
825 // Insert the new nodes into the topological ordering. We must do this in
826 // a valid topological ordering as nothing is going to go back and re-sort
827 // these nodes. We continually insert before 'N' in sequence as this is
828 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
829 // hierarchy left to express.
830 InsertDAGNode(DAG, N, NewMask);
831 InsertDAGNode(DAG, N, NewAnd);
832 InsertDAGNode(DAG, N, NewShift);
833 DAG.ReplaceAllUsesWith(N, NewShift);
835 AM.Scale = 1 << ShiftAmt;
836 AM.IndexReg = NewAnd;
840 // Implement some heroics to detect shifts of masked values where the mask can
841 // be replaced by extending the shift and undoing that in the addressing mode
842 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
843 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
844 // the addressing mode. This results in code such as:
846 // int f(short *y, int *lookup_table) {
848 // return *y + lookup_table[*y >> 11];
852 // movzwl (%rdi), %eax
855 // addl (%rsi,%rcx,4), %eax
858 // movzwl (%rdi), %eax
862 // addl (%rsi,%rcx), %eax
864 // Note that this function assumes the mask is provided as a mask *after* the
865 // value is shifted. The input chain may or may not match that, but computing
866 // such a mask is trivial.
867 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
869 SDValue Shift, SDValue X,
870 X86ISelAddressMode &AM) {
871 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
872 !isa<ConstantSDNode>(Shift.getOperand(1)))
875 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
876 unsigned MaskLZ = CountLeadingZeros_64(Mask);
877 unsigned MaskTZ = CountTrailingZeros_64(Mask);
879 // The amount of shift we're trying to fit into the addressing mode is taken
880 // from the trailing zeros of the mask.
881 unsigned AMShiftAmt = MaskTZ;
883 // There is nothing we can do here unless the mask is removing some bits.
884 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
885 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
887 // We also need to ensure that mask is a continuous run of bits.
888 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
890 // Scale the leading zero count down based on the actual size of the value.
891 // Also scale it down based on the size of the shift.
892 MaskLZ -= (64 - X.getValueSizeInBits()) + ShiftAmt;
894 // The final check is to ensure that any masked out high bits of X are
895 // already known to be zero. Otherwise, the mask has a semantic impact
896 // other than masking out a couple of low bits. Unfortunately, because of
897 // the mask, zero extensions will be removed from operands in some cases.
898 // This code works extra hard to look through extensions because we can
899 // replace them with zero extensions cheaply if necessary.
900 bool ReplacingAnyExtend = false;
901 if (X.getOpcode() == ISD::ANY_EXTEND) {
902 unsigned ExtendBits =
903 X.getValueSizeInBits() - X.getOperand(0).getValueSizeInBits();
904 // Assume that we'll replace the any-extend with a zero-extend, and
905 // narrow the search to the extended value.
907 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
908 ReplacingAnyExtend = true;
910 APInt MaskedHighBits = APInt::getHighBitsSet(X.getValueSizeInBits(),
912 APInt KnownZero, KnownOne;
913 DAG.ComputeMaskedBits(X, KnownZero, KnownOne);
914 if (MaskedHighBits != KnownZero) return true;
916 // We've identified a pattern that can be transformed into a single shift
917 // and an addressing mode. Make it so.
918 EVT VT = N.getValueType();
919 if (ReplacingAnyExtend) {
920 assert(X.getValueType() != VT);
921 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
922 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, X.getDebugLoc(), VT, X);
923 InsertDAGNode(DAG, N, NewX);
926 DebugLoc DL = N.getDebugLoc();
927 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
928 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
929 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
930 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
932 // Insert the new nodes into the topological ordering. We must do this in
933 // a valid topological ordering as nothing is going to go back and re-sort
934 // these nodes. We continually insert before 'N' in sequence as this is
935 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
936 // hierarchy left to express.
937 InsertDAGNode(DAG, N, NewSRLAmt);
938 InsertDAGNode(DAG, N, NewSRL);
939 InsertDAGNode(DAG, N, NewSHLAmt);
940 InsertDAGNode(DAG, N, NewSHL);
941 DAG.ReplaceAllUsesWith(N, NewSHL);
943 AM.Scale = 1 << AMShiftAmt;
944 AM.IndexReg = NewSRL;
948 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
950 DebugLoc dl = N.getDebugLoc();
952 dbgs() << "MatchAddress: ";
957 return MatchAddressBase(N, AM);
959 // If this is already a %rip relative address, we can only merge immediates
960 // into it. Instead of handling this in every case, we handle it here.
961 // RIP relative addressing: %rip + 32-bit displacement!
962 if (AM.isRIPRelative()) {
963 // FIXME: JumpTable and ExternalSymbol address currently don't like
964 // displacements. It isn't very important, but this should be fixed for
966 if (!AM.ES && AM.JT != -1) return true;
968 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
969 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
974 switch (N.getOpcode()) {
976 case ISD::Constant: {
977 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
978 if (!FoldOffsetIntoAddress(Val, AM))
983 case X86ISD::Wrapper:
984 case X86ISD::WrapperRIP:
985 if (!MatchWrapper(N, AM))
990 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
994 case ISD::FrameIndex:
995 if (AM.BaseType == X86ISelAddressMode::RegBase &&
996 AM.Base_Reg.getNode() == 0 &&
997 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
998 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
999 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1005 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
1009 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1010 unsigned Val = CN->getZExtValue();
1011 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1012 // that the base operand remains free for further matching. If
1013 // the base doesn't end up getting used, a post-processing step
1014 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1015 if (Val == 1 || Val == 2 || Val == 3) {
1016 AM.Scale = 1 << Val;
1017 SDValue ShVal = N.getNode()->getOperand(0);
1019 // Okay, we know that we have a scale by now. However, if the scaled
1020 // value is an add of something and a constant, we can fold the
1021 // constant into the disp field here.
1022 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1023 AM.IndexReg = ShVal.getNode()->getOperand(0);
1024 ConstantSDNode *AddVal =
1025 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1026 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1027 if (!FoldOffsetIntoAddress(Disp, AM))
1031 AM.IndexReg = ShVal;
1038 // Scale must not be used already.
1039 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1041 SDValue And = N.getOperand(0);
1042 if (And.getOpcode() != ISD::AND) break;
1043 SDValue X = And.getOperand(0);
1045 // We only handle up to 64-bit values here as those are what matter for
1046 // addressing mode optimizations.
1047 if (X.getValueSizeInBits() > 64) break;
1049 // The mask used for the transform is expected to be post-shift, but we
1050 // found the shift first so just apply the shift to the mask before passing
1052 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1053 !isa<ConstantSDNode>(And.getOperand(1)))
1055 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1057 // Try to fold the mask and shift into the scale, and return false if we
1059 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1064 case ISD::SMUL_LOHI:
1065 case ISD::UMUL_LOHI:
1066 // A mul_lohi where we need the low part can be folded as a plain multiply.
1067 if (N.getResNo() != 0) break;
1070 case X86ISD::MUL_IMM:
1071 // X*[3,5,9] -> X+X*[2,4,8]
1072 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1073 AM.Base_Reg.getNode() == 0 &&
1074 AM.IndexReg.getNode() == 0) {
1076 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1077 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1078 CN->getZExtValue() == 9) {
1079 AM.Scale = unsigned(CN->getZExtValue())-1;
1081 SDValue MulVal = N.getNode()->getOperand(0);
1084 // Okay, we know that we have a scale by now. However, if the scaled
1085 // value is an add of something and a constant, we can fold the
1086 // constant into the disp field here.
1087 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1088 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1089 Reg = MulVal.getNode()->getOperand(0);
1090 ConstantSDNode *AddVal =
1091 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1092 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1093 if (FoldOffsetIntoAddress(Disp, AM))
1094 Reg = N.getNode()->getOperand(0);
1096 Reg = N.getNode()->getOperand(0);
1099 AM.IndexReg = AM.Base_Reg = Reg;
1106 // Given A-B, if A can be completely folded into the address and
1107 // the index field with the index field unused, use -B as the index.
1108 // This is a win if a has multiple parts that can be folded into
1109 // the address. Also, this saves a mov if the base register has
1110 // other uses, since it avoids a two-address sub instruction, however
1111 // it costs an additional mov if the index register has other uses.
1113 // Add an artificial use to this node so that we can keep track of
1114 // it if it gets CSE'd with a different node.
1115 HandleSDNode Handle(N);
1117 // Test if the LHS of the sub can be folded.
1118 X86ISelAddressMode Backup = AM;
1119 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1123 // Test if the index field is free for use.
1124 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1130 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1131 // If the RHS involves a register with multiple uses, this
1132 // transformation incurs an extra mov, due to the neg instruction
1133 // clobbering its operand.
1134 if (!RHS.getNode()->hasOneUse() ||
1135 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1136 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1137 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1138 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1139 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1141 // If the base is a register with multiple uses, this
1142 // transformation may save a mov.
1143 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1144 AM.Base_Reg.getNode() &&
1145 !AM.Base_Reg.getNode()->hasOneUse()) ||
1146 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1148 // If the folded LHS was interesting, this transformation saves
1149 // address arithmetic.
1150 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1151 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1152 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1154 // If it doesn't look like it may be an overall win, don't do it.
1160 // Ok, the transformation is legal and appears profitable. Go for it.
1161 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1162 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1166 // Insert the new nodes into the topological ordering.
1167 InsertDAGNode(*CurDAG, N, Zero);
1168 InsertDAGNode(*CurDAG, N, Neg);
1173 // Add an artificial use to this node so that we can keep track of
1174 // it if it gets CSE'd with a different node.
1175 HandleSDNode Handle(N);
1177 X86ISelAddressMode Backup = AM;
1178 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1179 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1183 // Try again after commuting the operands.
1184 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1185 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1189 // If we couldn't fold both operands into the address at the same time,
1190 // see if we can just put each operand into a register and fold at least
1192 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1193 !AM.Base_Reg.getNode() &&
1194 !AM.IndexReg.getNode()) {
1195 N = Handle.getValue();
1196 AM.Base_Reg = N.getOperand(0);
1197 AM.IndexReg = N.getOperand(1);
1201 N = Handle.getValue();
1206 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1207 if (CurDAG->isBaseWithConstantOffset(N)) {
1208 X86ISelAddressMode Backup = AM;
1209 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1211 // Start with the LHS as an addr mode.
1212 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1213 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1220 // Perform some heroic transforms on an and of a constant-count shift
1221 // with a constant to enable use of the scaled offset field.
1223 // Scale must not be used already.
1224 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1226 SDValue Shift = N.getOperand(0);
1227 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1228 SDValue X = Shift.getOperand(0);
1230 // We only handle up to 64-bit values here as those are what matter for
1231 // addressing mode optimizations.
1232 if (X.getValueSizeInBits() > 64) break;
1234 if (!isa<ConstantSDNode>(N.getOperand(1)))
1236 uint64_t Mask = N.getConstantOperandVal(1);
1238 // Try to fold the mask and shift into an extract and scale.
1239 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1242 // Try to fold the mask and shift directly into the scale.
1243 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1246 // Try to swap the mask and shift to place shifts which can be done as
1247 // a scale on the outside of the mask.
1248 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1254 return MatchAddressBase(N, AM);
1257 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1258 /// specified addressing mode without any further recursion.
1259 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1260 // Is the base register already occupied?
1261 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1262 // If so, check to see if the scale index register is set.
1263 if (AM.IndexReg.getNode() == 0) {
1269 // Otherwise, we cannot select it.
1273 // Default, generate it as a register.
1274 AM.BaseType = X86ISelAddressMode::RegBase;
1279 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1280 /// It returns the operands which make up the maximal addressing mode it can
1281 /// match by reference.
1283 /// Parent is the parent node of the addr operand that is being matched. It
1284 /// is always a load, store, atomic node, or null. It is only null when
1285 /// checking memory operands for inline asm nodes.
1286 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1287 SDValue &Scale, SDValue &Index,
1288 SDValue &Disp, SDValue &Segment) {
1289 X86ISelAddressMode AM;
1292 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1293 // that are not a MemSDNode, and thus don't have proper addrspace info.
1294 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1295 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1296 Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme
1297 unsigned AddrSpace =
1298 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1299 // AddrSpace 256 -> GS, 257 -> FS.
1300 if (AddrSpace == 256)
1301 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1302 if (AddrSpace == 257)
1303 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1306 if (MatchAddress(N, AM))
1309 EVT VT = N.getValueType();
1310 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1311 if (!AM.Base_Reg.getNode())
1312 AM.Base_Reg = CurDAG->getRegister(0, VT);
1315 if (!AM.IndexReg.getNode())
1316 AM.IndexReg = CurDAG->getRegister(0, VT);
1318 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1322 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1323 /// match a load whose top elements are either undef or zeros. The load flavor
1324 /// is derived from the type of N, which is either v4f32 or v2f64.
1327 /// PatternChainNode: this is the matched node that has a chain input and
1329 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1330 SDValue N, SDValue &Base,
1331 SDValue &Scale, SDValue &Index,
1332 SDValue &Disp, SDValue &Segment,
1333 SDValue &PatternNodeWithChain) {
1334 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1335 PatternNodeWithChain = N.getOperand(0);
1336 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1337 PatternNodeWithChain.hasOneUse() &&
1338 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1339 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1340 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1341 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1347 // Also handle the case where we explicitly require zeros in the top
1348 // elements. This is a vector shuffle from the zero vector.
1349 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1350 // Check to see if the top elements are all zeros (or bitcast of zeros).
1351 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1352 N.getOperand(0).getNode()->hasOneUse() &&
1353 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1354 N.getOperand(0).getOperand(0).hasOneUse() &&
1355 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1356 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1357 // Okay, this is a zero extending load. Fold it.
1358 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1359 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1361 PatternNodeWithChain = SDValue(LD, 0);
1368 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1369 /// mode it matches can be cost effectively emitted as an LEA instruction.
1370 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1371 SDValue &Base, SDValue &Scale,
1372 SDValue &Index, SDValue &Disp,
1374 X86ISelAddressMode AM;
1376 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1378 SDValue Copy = AM.Segment;
1379 SDValue T = CurDAG->getRegister(0, MVT::i32);
1381 if (MatchAddress(N, AM))
1383 assert (T == AM.Segment);
1386 EVT VT = N.getValueType();
1387 unsigned Complexity = 0;
1388 if (AM.BaseType == X86ISelAddressMode::RegBase)
1389 if (AM.Base_Reg.getNode())
1392 AM.Base_Reg = CurDAG->getRegister(0, VT);
1393 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1396 if (AM.IndexReg.getNode())
1399 AM.IndexReg = CurDAG->getRegister(0, VT);
1401 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1406 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1407 // to a LEA. This is determined with some expermentation but is by no means
1408 // optimal (especially for code size consideration). LEA is nice because of
1409 // its three-address nature. Tweak the cost function again when we can run
1410 // convertToThreeAddress() at register allocation time.
1411 if (AM.hasSymbolicDisplacement()) {
1412 // For X86-64, we should always use lea to materialize RIP relative
1414 if (Subtarget->is64Bit())
1420 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1423 // If it isn't worth using an LEA, reject it.
1424 if (Complexity <= 2)
1427 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1431 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1432 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1433 SDValue &Scale, SDValue &Index,
1434 SDValue &Disp, SDValue &Segment) {
1435 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1436 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1438 X86ISelAddressMode AM;
1439 AM.GV = GA->getGlobal();
1440 AM.Disp += GA->getOffset();
1441 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1442 AM.SymbolFlags = GA->getTargetFlags();
1444 if (N.getValueType() == MVT::i32) {
1446 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1448 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1451 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1456 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1457 SDValue &Base, SDValue &Scale,
1458 SDValue &Index, SDValue &Disp,
1460 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1461 !IsProfitableToFold(N, P, P) ||
1462 !IsLegalToFold(N, P, P, OptLevel))
1465 return SelectAddr(N.getNode(),
1466 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1469 /// getGlobalBaseReg - Return an SDNode that returns the value of
1470 /// the global base register. Output instructions required to
1471 /// initialize the global base register, if necessary.
1473 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1474 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1475 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1478 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1479 SDValue Chain = Node->getOperand(0);
1480 SDValue In1 = Node->getOperand(1);
1481 SDValue In2L = Node->getOperand(2);
1482 SDValue In2H = Node->getOperand(3);
1483 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1484 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1486 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1487 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1488 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1489 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1490 MVT::i32, MVT::i32, MVT::Other, Ops,
1491 array_lengthof(Ops));
1492 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1496 // FIXME: Figure out some way to unify this with the 'or' and other code
1498 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1499 if (Node->hasAnyUseOfValue(0))
1502 // Optimize common patterns for __sync_add_and_fetch and
1503 // __sync_sub_and_fetch where the result is not used. This allows us
1504 // to use "lock" version of add, sub, inc, dec instructions.
1505 // FIXME: Do not use special instructions but instead add the "lock"
1506 // prefix to the target node somehow. The extra information will then be
1507 // transferred to machine instruction and it denotes the prefix.
1508 SDValue Chain = Node->getOperand(0);
1509 SDValue Ptr = Node->getOperand(1);
1510 SDValue Val = Node->getOperand(2);
1511 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1512 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1515 bool isInc = false, isDec = false, isSub = false, isCN = false;
1516 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1517 if (CN && CN->getSExtValue() == (int32_t)CN->getSExtValue()) {
1519 int64_t CNVal = CN->getSExtValue();
1522 else if (CNVal == -1)
1524 else if (CNVal >= 0)
1525 Val = CurDAG->getTargetConstant(CNVal, NVT);
1528 Val = CurDAG->getTargetConstant(-CNVal, NVT);
1530 } else if (Val.hasOneUse() &&
1531 Val.getOpcode() == ISD::SUB &&
1532 X86::isZeroNode(Val.getOperand(0))) {
1534 Val = Val.getOperand(1);
1537 DebugLoc dl = Node->getDebugLoc();
1539 switch (NVT.getSimpleVT().SimpleTy) {
1543 Opc = X86::LOCK_INC8m;
1545 Opc = X86::LOCK_DEC8m;
1548 Opc = X86::LOCK_SUB8mi;
1550 Opc = X86::LOCK_SUB8mr;
1553 Opc = X86::LOCK_ADD8mi;
1555 Opc = X86::LOCK_ADD8mr;
1560 Opc = X86::LOCK_INC16m;
1562 Opc = X86::LOCK_DEC16m;
1565 if (immSext8(Val.getNode()))
1566 Opc = X86::LOCK_SUB16mi8;
1568 Opc = X86::LOCK_SUB16mi;
1570 Opc = X86::LOCK_SUB16mr;
1573 if (immSext8(Val.getNode()))
1574 Opc = X86::LOCK_ADD16mi8;
1576 Opc = X86::LOCK_ADD16mi;
1578 Opc = X86::LOCK_ADD16mr;
1583 Opc = X86::LOCK_INC32m;
1585 Opc = X86::LOCK_DEC32m;
1588 if (immSext8(Val.getNode()))
1589 Opc = X86::LOCK_SUB32mi8;
1591 Opc = X86::LOCK_SUB32mi;
1593 Opc = X86::LOCK_SUB32mr;
1596 if (immSext8(Val.getNode()))
1597 Opc = X86::LOCK_ADD32mi8;
1599 Opc = X86::LOCK_ADD32mi;
1601 Opc = X86::LOCK_ADD32mr;
1606 Opc = X86::LOCK_INC64m;
1608 Opc = X86::LOCK_DEC64m;
1610 Opc = X86::LOCK_SUB64mr;
1612 if (immSext8(Val.getNode()))
1613 Opc = X86::LOCK_SUB64mi8;
1614 else if (i64immSExt32(Val.getNode()))
1615 Opc = X86::LOCK_SUB64mi32;
1618 Opc = X86::LOCK_ADD64mr;
1620 if (immSext8(Val.getNode()))
1621 Opc = X86::LOCK_ADD64mi8;
1622 else if (i64immSExt32(Val.getNode()))
1623 Opc = X86::LOCK_ADD64mi32;
1629 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1631 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1632 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1633 if (isInc || isDec) {
1634 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1635 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
1636 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1637 SDValue RetVals[] = { Undef, Ret };
1638 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1640 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1641 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1642 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1643 SDValue RetVals[] = { Undef, Ret };
1644 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1670 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1694 X86::LOCK_AND64mi32,
1707 X86::LOCK_XOR64mi32,
1712 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
1713 if (Node->hasAnyUseOfValue(0))
1716 // Optimize common patterns for __sync_or_and_fetch and similar arith
1717 // operations where the result is not used. This allows us to use the "lock"
1718 // version of the arithmetic instruction.
1719 // FIXME: Same as for 'add' and 'sub', try to merge those down here.
1720 SDValue Chain = Node->getOperand(0);
1721 SDValue Ptr = Node->getOperand(1);
1722 SDValue Val = Node->getOperand(2);
1723 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1724 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1727 // Which index into the table.
1729 switch (Node->getOpcode()) {
1730 case ISD::ATOMIC_LOAD_OR:
1733 case ISD::ATOMIC_LOAD_AND:
1736 case ISD::ATOMIC_LOAD_XOR:
1744 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1745 if (CN && (int32_t)CN->getSExtValue() == CN->getSExtValue()) {
1747 Val = CurDAG->getTargetConstant(CN->getSExtValue(), NVT);
1751 switch (NVT.getSimpleVT().SimpleTy) {
1755 Opc = AtomicOpcTbl[Op][ConstantI8];
1757 Opc = AtomicOpcTbl[Op][I8];
1761 if (immSext8(Val.getNode()))
1762 Opc = AtomicOpcTbl[Op][SextConstantI16];
1764 Opc = AtomicOpcTbl[Op][ConstantI16];
1766 Opc = AtomicOpcTbl[Op][I16];
1770 if (immSext8(Val.getNode()))
1771 Opc = AtomicOpcTbl[Op][SextConstantI32];
1773 Opc = AtomicOpcTbl[Op][ConstantI32];
1775 Opc = AtomicOpcTbl[Op][I32];
1778 Opc = AtomicOpcTbl[Op][I64];
1780 if (immSext8(Val.getNode()))
1781 Opc = AtomicOpcTbl[Op][SextConstantI64];
1782 else if (i64immSExt32(Val.getNode()))
1783 Opc = AtomicOpcTbl[Op][ConstantI64];
1788 assert(Opc != 0 && "Invalid arith lock transform!");
1790 DebugLoc dl = Node->getDebugLoc();
1791 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1793 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1794 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1795 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1796 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1797 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1798 SDValue RetVals[] = { Undef, Ret };
1799 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1802 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1803 /// any uses which require the SF or OF bits to be accurate.
1804 static bool HasNoSignedComparisonUses(SDNode *N) {
1805 // Examine each user of the node.
1806 for (SDNode::use_iterator UI = N->use_begin(),
1807 UE = N->use_end(); UI != UE; ++UI) {
1808 // Only examine CopyToReg uses.
1809 if (UI->getOpcode() != ISD::CopyToReg)
1811 // Only examine CopyToReg uses that copy to EFLAGS.
1812 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1815 // Examine each user of the CopyToReg use.
1816 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1817 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1818 // Only examine the Flag result.
1819 if (FlagUI.getUse().getResNo() != 1) continue;
1820 // Anything unusual: assume conservatively.
1821 if (!FlagUI->isMachineOpcode()) return false;
1822 // Examine the opcode of the user.
1823 switch (FlagUI->getMachineOpcode()) {
1824 // These comparisons don't treat the most significant bit specially.
1825 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1826 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1827 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1828 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1829 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1830 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1831 case X86::CMOVA16rr: case X86::CMOVA16rm:
1832 case X86::CMOVA32rr: case X86::CMOVA32rm:
1833 case X86::CMOVA64rr: case X86::CMOVA64rm:
1834 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1835 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1836 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1837 case X86::CMOVB16rr: case X86::CMOVB16rm:
1838 case X86::CMOVB32rr: case X86::CMOVB32rm:
1839 case X86::CMOVB64rr: case X86::CMOVB64rm:
1840 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1841 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1842 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1843 case X86::CMOVE16rr: case X86::CMOVE16rm:
1844 case X86::CMOVE32rr: case X86::CMOVE32rm:
1845 case X86::CMOVE64rr: case X86::CMOVE64rm:
1846 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1847 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1848 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1849 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1850 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1851 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1852 case X86::CMOVP16rr: case X86::CMOVP16rm:
1853 case X86::CMOVP32rr: case X86::CMOVP32rm:
1854 case X86::CMOVP64rr: case X86::CMOVP64rm:
1856 // Anything else: assume conservatively.
1857 default: return false;
1864 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1865 /// is suitable for doing the {load; increment or decrement; store} to modify
1867 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1868 SDValue StoredVal, SelectionDAG *CurDAG,
1869 LoadSDNode* &LoadNode, SDValue &InputChain) {
1871 // is the value stored the result of a DEC or INC?
1872 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1874 // is the stored value result 0 of the load?
1875 if (StoredVal.getResNo() != 0) return false;
1877 // are there other uses of the loaded value than the inc or dec?
1878 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1880 // is the store non-extending and non-indexed?
1881 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1884 SDValue Load = StoredVal->getOperand(0);
1885 // Is the stored value a non-extending and non-indexed load?
1886 if (!ISD::isNormalLoad(Load.getNode())) return false;
1888 // Return LoadNode by reference.
1889 LoadNode = cast<LoadSDNode>(Load);
1890 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1891 EVT LdVT = LoadNode->getMemoryVT();
1892 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1896 // Is store the only read of the loaded value?
1897 if (!Load.hasOneUse())
1900 // Is the address of the store the same as the load?
1901 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1902 LoadNode->getOffset() != StoreNode->getOffset())
1905 // Check if the chain is produced by the load or is a TokenFactor with
1906 // the load output chain as an operand. Return InputChain by reference.
1907 SDValue Chain = StoreNode->getChain();
1909 bool ChainCheck = false;
1910 if (Chain == Load.getValue(1)) {
1912 InputChain = LoadNode->getChain();
1913 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1914 SmallVector<SDValue, 4> ChainOps;
1915 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1916 SDValue Op = Chain.getOperand(i);
1917 if (Op == Load.getValue(1)) {
1922 // Make sure using Op as part of the chain would not cause a cycle here.
1923 // In theory, we could check whether the chain node is a predecessor of
1924 // the load. But that can be very expensive. Instead visit the uses and
1925 // make sure they all have smaller node id than the load.
1926 int LoadId = LoadNode->getNodeId();
1927 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1928 UE = UI->use_end(); UI != UE; ++UI) {
1929 if (UI.getUse().getResNo() != 0)
1931 if (UI->getNodeId() > LoadId)
1935 ChainOps.push_back(Op);
1939 // Make a new TokenFactor with all the other input chains except
1941 InputChain = CurDAG->getNode(ISD::TokenFactor, Chain.getDebugLoc(),
1942 MVT::Other, &ChainOps[0], ChainOps.size());
1950 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
1951 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
1952 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
1953 if (Opc == X86ISD::DEC) {
1954 if (LdVT == MVT::i64) return X86::DEC64m;
1955 if (LdVT == MVT::i32) return X86::DEC32m;
1956 if (LdVT == MVT::i16) return X86::DEC16m;
1957 if (LdVT == MVT::i8) return X86::DEC8m;
1959 assert(Opc == X86ISD::INC && "unrecognized opcode");
1960 if (LdVT == MVT::i64) return X86::INC64m;
1961 if (LdVT == MVT::i32) return X86::INC32m;
1962 if (LdVT == MVT::i16) return X86::INC16m;
1963 if (LdVT == MVT::i8) return X86::INC8m;
1965 llvm_unreachable("unrecognized size for LdVT");
1968 /// SelectGather - Customized ISel for GATHER operations.
1970 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
1971 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
1972 SDValue Chain = Node->getOperand(0);
1973 SDValue VSrc = Node->getOperand(2);
1974 SDValue Base = Node->getOperand(3);
1975 SDValue VIdx = Node->getOperand(4);
1976 SDValue VMask = Node->getOperand(5);
1977 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
1981 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
1984 // Memory Operands: Base, Scale, Index, Disp, Segment
1985 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
1986 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
1987 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
1988 Disp, Segment, VMask, Chain};
1989 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1990 VTs, Ops, array_lengthof(Ops));
1991 // Node has 2 outputs: VDst and MVT::Other.
1992 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
1993 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
1995 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
1996 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2000 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2001 EVT NVT = Node->getValueType(0);
2003 unsigned Opcode = Node->getOpcode();
2004 DebugLoc dl = Node->getDebugLoc();
2006 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2008 if (Node->isMachineOpcode()) {
2009 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2010 return NULL; // Already selected.
2015 case ISD::INTRINSIC_W_CHAIN: {
2016 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2019 case Intrinsic::x86_avx2_gather_d_pd:
2020 case Intrinsic::x86_avx2_gather_d_pd_256:
2021 case Intrinsic::x86_avx2_gather_q_pd:
2022 case Intrinsic::x86_avx2_gather_q_pd_256:
2023 case Intrinsic::x86_avx2_gather_d_ps:
2024 case Intrinsic::x86_avx2_gather_d_ps_256:
2025 case Intrinsic::x86_avx2_gather_q_ps:
2026 case Intrinsic::x86_avx2_gather_q_ps_256:
2027 case Intrinsic::x86_avx2_gather_d_q:
2028 case Intrinsic::x86_avx2_gather_d_q_256:
2029 case Intrinsic::x86_avx2_gather_q_q:
2030 case Intrinsic::x86_avx2_gather_q_q_256:
2031 case Intrinsic::x86_avx2_gather_d_d:
2032 case Intrinsic::x86_avx2_gather_d_d_256:
2033 case Intrinsic::x86_avx2_gather_q_d:
2034 case Intrinsic::x86_avx2_gather_q_d_256: {
2037 default: llvm_unreachable("Impossible intrinsic");
2038 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2039 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2040 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2041 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2042 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2043 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2044 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2045 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2046 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2047 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2048 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2049 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2050 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2051 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2052 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2053 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2055 SDNode *RetVal = SelectGather(Node, Opc);
2057 // We already called ReplaceUses inside SelectGather.
2064 case X86ISD::GlobalBaseReg:
2065 return getGlobalBaseReg();
2068 case X86ISD::ATOMOR64_DAG:
2069 case X86ISD::ATOMXOR64_DAG:
2070 case X86ISD::ATOMADD64_DAG:
2071 case X86ISD::ATOMSUB64_DAG:
2072 case X86ISD::ATOMNAND64_DAG:
2073 case X86ISD::ATOMAND64_DAG:
2074 case X86ISD::ATOMSWAP64_DAG: {
2077 default: llvm_unreachable("Impossible opcode");
2078 case X86ISD::ATOMOR64_DAG: Opc = X86::ATOMOR6432; break;
2079 case X86ISD::ATOMXOR64_DAG: Opc = X86::ATOMXOR6432; break;
2080 case X86ISD::ATOMADD64_DAG: Opc = X86::ATOMADD6432; break;
2081 case X86ISD::ATOMSUB64_DAG: Opc = X86::ATOMSUB6432; break;
2082 case X86ISD::ATOMNAND64_DAG: Opc = X86::ATOMNAND6432; break;
2083 case X86ISD::ATOMAND64_DAG: Opc = X86::ATOMAND6432; break;
2084 case X86ISD::ATOMSWAP64_DAG: Opc = X86::ATOMSWAP6432; break;
2086 SDNode *RetVal = SelectAtomic64(Node, Opc);
2092 case ISD::ATOMIC_LOAD_ADD: {
2093 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
2098 case ISD::ATOMIC_LOAD_XOR:
2099 case ISD::ATOMIC_LOAD_AND:
2100 case ISD::ATOMIC_LOAD_OR: {
2101 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2109 // For operations of the form (x << C1) op C2, check if we can use a smaller
2110 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2111 SDValue N0 = Node->getOperand(0);
2112 SDValue N1 = Node->getOperand(1);
2114 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2117 // i8 is unshrinkable, i16 should be promoted to i32.
2118 if (NVT != MVT::i32 && NVT != MVT::i64)
2121 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2122 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2123 if (!Cst || !ShlCst)
2126 int64_t Val = Cst->getSExtValue();
2127 uint64_t ShlVal = ShlCst->getZExtValue();
2129 // Make sure that we don't change the operation by removing bits.
2130 // This only matters for OR and XOR, AND is unaffected.
2131 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2132 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2138 // Check the minimum bitwidth for the new constant.
2139 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2140 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2141 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2142 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2144 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2147 // Bail if there is no smaller encoding.
2151 switch (NVT.getSimpleVT().SimpleTy) {
2152 default: llvm_unreachable("Unsupported VT!");
2154 assert(CstVT == MVT::i8);
2155 ShlOp = X86::SHL32ri;
2158 default: llvm_unreachable("Impossible opcode");
2159 case ISD::AND: Op = X86::AND32ri8; break;
2160 case ISD::OR: Op = X86::OR32ri8; break;
2161 case ISD::XOR: Op = X86::XOR32ri8; break;
2165 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2166 ShlOp = X86::SHL64ri;
2169 default: llvm_unreachable("Impossible opcode");
2170 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2171 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2172 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2177 // Emit the smaller op and the shift.
2178 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2179 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2180 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2183 case X86ISD::UMUL: {
2184 SDValue N0 = Node->getOperand(0);
2185 SDValue N1 = Node->getOperand(1);
2188 switch (NVT.getSimpleVT().SimpleTy) {
2189 default: llvm_unreachable("Unsupported VT!");
2190 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2191 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2192 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2193 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2196 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2197 N0, SDValue()).getValue(1);
2199 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2200 SDValue Ops[] = {N1, InFlag};
2201 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops, 2);
2203 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2204 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2205 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2209 case ISD::SMUL_LOHI:
2210 case ISD::UMUL_LOHI: {
2211 SDValue N0 = Node->getOperand(0);
2212 SDValue N1 = Node->getOperand(1);
2214 bool isSigned = Opcode == ISD::SMUL_LOHI;
2216 switch (NVT.getSimpleVT().SimpleTy) {
2217 default: llvm_unreachable("Unsupported VT!");
2218 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2219 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2220 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
2221 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
2224 switch (NVT.getSimpleVT().SimpleTy) {
2225 default: llvm_unreachable("Unsupported VT!");
2226 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2227 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2228 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2229 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2233 unsigned LoReg, HiReg;
2234 switch (NVT.getSimpleVT().SimpleTy) {
2235 default: llvm_unreachable("Unsupported VT!");
2236 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
2237 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
2238 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
2239 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
2242 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2243 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2244 // Multiply is commmutative.
2246 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2251 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2252 N0, SDValue()).getValue(1);
2255 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2258 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
2259 array_lengthof(Ops));
2260 InFlag = SDValue(CNode, 1);
2262 // Update the chain.
2263 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2265 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag);
2266 InFlag = SDValue(CNode, 0);
2269 // Prevent use of AH in a REX instruction by referencing AX instead.
2270 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2271 !SDValue(Node, 1).use_empty()) {
2272 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2273 X86::AX, MVT::i16, InFlag);
2274 InFlag = Result.getValue(2);
2275 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2277 if (!SDValue(Node, 0).use_empty())
2278 ReplaceUses(SDValue(Node, 1),
2279 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2281 // Shift AX down 8 bits.
2282 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2284 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2285 // Then truncate it down to i8.
2286 ReplaceUses(SDValue(Node, 1),
2287 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2289 // Copy the low half of the result, if it is needed.
2290 if (!SDValue(Node, 0).use_empty()) {
2291 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2292 LoReg, NVT, InFlag);
2293 InFlag = Result.getValue(2);
2294 ReplaceUses(SDValue(Node, 0), Result);
2295 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2297 // Copy the high half of the result, if it is needed.
2298 if (!SDValue(Node, 1).use_empty()) {
2299 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2300 HiReg, NVT, InFlag);
2301 InFlag = Result.getValue(2);
2302 ReplaceUses(SDValue(Node, 1), Result);
2303 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2310 case ISD::UDIVREM: {
2311 SDValue N0 = Node->getOperand(0);
2312 SDValue N1 = Node->getOperand(1);
2314 bool isSigned = Opcode == ISD::SDIVREM;
2316 switch (NVT.getSimpleVT().SimpleTy) {
2317 default: llvm_unreachable("Unsupported VT!");
2318 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2319 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2320 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2321 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2324 switch (NVT.getSimpleVT().SimpleTy) {
2325 default: llvm_unreachable("Unsupported VT!");
2326 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2327 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2328 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2329 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2333 unsigned LoReg, HiReg, ClrReg;
2334 unsigned ClrOpcode, SExtOpcode;
2335 switch (NVT.getSimpleVT().SimpleTy) {
2336 default: llvm_unreachable("Unsupported VT!");
2338 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2340 SExtOpcode = X86::CBW;
2343 LoReg = X86::AX; HiReg = X86::DX;
2344 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
2345 SExtOpcode = X86::CWD;
2348 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2349 ClrOpcode = X86::MOV32r0;
2350 SExtOpcode = X86::CDQ;
2353 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2354 ClrOpcode = X86::MOV64r0;
2355 SExtOpcode = X86::CQO;
2359 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2360 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2361 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2364 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2365 // Special case for div8, just use a move with zero extension to AX to
2366 // clear the upper 8 bits (AH).
2367 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2368 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2369 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2371 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2373 array_lengthof(Ops)), 0);
2374 Chain = Move.getValue(1);
2375 ReplaceUses(N0.getValue(1), Chain);
2378 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2379 Chain = CurDAG->getEntryNode();
2381 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2382 InFlag = Chain.getValue(1);
2385 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2386 LoReg, N0, SDValue()).getValue(1);
2387 if (isSigned && !signBitIsZero) {
2388 // Sign extend the low part into the high part.
2390 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2392 // Zero out the high part, effectively zero extending the input.
2394 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
2395 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2396 ClrNode, InFlag).getValue(1);
2401 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2404 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
2405 array_lengthof(Ops));
2406 InFlag = SDValue(CNode, 1);
2407 // Update the chain.
2408 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2411 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2414 // Prevent use of AH in a REX instruction by referencing AX instead.
2415 // Shift it down 8 bits.
2416 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2417 !SDValue(Node, 1).use_empty()) {
2418 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2419 X86::AX, MVT::i16, InFlag);
2420 InFlag = Result.getValue(2);
2422 // If we also need AL (the quotient), get it by extracting a subreg from
2423 // Result. The fast register allocator does not like multiple CopyFromReg
2424 // nodes using aliasing registers.
2425 if (!SDValue(Node, 0).use_empty())
2426 ReplaceUses(SDValue(Node, 0),
2427 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2429 // Shift AX right by 8 bits instead of using AH.
2430 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2432 CurDAG->getTargetConstant(8, MVT::i8)),
2434 ReplaceUses(SDValue(Node, 1),
2435 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2437 // Copy the division (low) result, if it is needed.
2438 if (!SDValue(Node, 0).use_empty()) {
2439 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2440 LoReg, NVT, InFlag);
2441 InFlag = Result.getValue(2);
2442 ReplaceUses(SDValue(Node, 0), Result);
2443 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2445 // Copy the remainder (high) result, if it is needed.
2446 if (!SDValue(Node, 1).use_empty()) {
2447 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2448 HiReg, NVT, InFlag);
2449 InFlag = Result.getValue(2);
2450 ReplaceUses(SDValue(Node, 1), Result);
2451 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2458 // Sometimes a SUB is used to perform comparison.
2459 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2460 // This node is not a CMP.
2462 SDValue N0 = Node->getOperand(0);
2463 SDValue N1 = Node->getOperand(1);
2465 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2466 // use a smaller encoding.
2467 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2468 HasNoSignedComparisonUses(Node))
2469 // Look past the truncate if CMP is the only use of it.
2470 N0 = N0.getOperand(0);
2471 if ((N0.getNode()->getOpcode() == ISD::AND ||
2472 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2473 N0.getNode()->hasOneUse() &&
2474 N0.getValueType() != MVT::i8 &&
2475 X86::isZeroNode(N1)) {
2476 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2479 // For example, convert "testl %eax, $8" to "testb %al, $8"
2480 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2481 (!(C->getZExtValue() & 0x80) ||
2482 HasNoSignedComparisonUses(Node))) {
2483 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2484 SDValue Reg = N0.getNode()->getOperand(0);
2486 // On x86-32, only the ABCD registers have 8-bit subregisters.
2487 if (!Subtarget->is64Bit()) {
2488 const TargetRegisterClass *TRC;
2489 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2490 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2491 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2492 default: llvm_unreachable("Unsupported TEST operand type!");
2494 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2495 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2496 Reg.getValueType(), Reg, RC), 0);
2499 // Extract the l-register.
2500 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2504 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
2507 // For example, "testl %eax, $2048" to "testb %ah, $8".
2508 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2509 (!(C->getZExtValue() & 0x8000) ||
2510 HasNoSignedComparisonUses(Node))) {
2511 // Shift the immediate right by 8 bits.
2512 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2514 SDValue Reg = N0.getNode()->getOperand(0);
2516 // Put the value in an ABCD register.
2517 const TargetRegisterClass *TRC;
2518 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2519 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2520 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2521 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2522 default: llvm_unreachable("Unsupported TEST operand type!");
2524 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2525 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2526 Reg.getValueType(), Reg, RC), 0);
2528 // Extract the h-register.
2529 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2532 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2533 // target GR8_NOREX registers, so make sure the register class is
2535 return CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl, MVT::i32,
2536 Subreg, ShiftedImm);
2539 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2540 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2541 N0.getValueType() != MVT::i16 &&
2542 (!(C->getZExtValue() & 0x8000) ||
2543 HasNoSignedComparisonUses(Node))) {
2544 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2545 SDValue Reg = N0.getNode()->getOperand(0);
2547 // Extract the 16-bit subregister.
2548 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2552 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
2555 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2556 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2557 N0.getValueType() == MVT::i64 &&
2558 (!(C->getZExtValue() & 0x80000000) ||
2559 HasNoSignedComparisonUses(Node))) {
2560 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2561 SDValue Reg = N0.getNode()->getOperand(0);
2563 // Extract the 32-bit subregister.
2564 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2568 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
2574 // Change a chain of {load; incr or dec; store} of the same value into
2575 // a simple increment or decrement through memory of that value, if the
2576 // uses of the modified value and its address are suitable.
2577 // The DEC64m tablegen pattern is currently not able to match the case where
2578 // the EFLAGS on the original DEC are used. (This also applies to
2579 // {INC,DEC}X{64,32,16,8}.)
2580 // We'll need to improve tablegen to allow flags to be transferred from a
2581 // node in the pattern to the result node. probably with a new keyword
2582 // for example, we have this
2583 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2584 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2585 // (implicit EFLAGS)]>;
2586 // but maybe need something like this
2587 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2588 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2589 // (transferrable EFLAGS)]>;
2591 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2592 SDValue StoredVal = StoreNode->getOperand(1);
2593 unsigned Opc = StoredVal->getOpcode();
2595 LoadSDNode *LoadNode = 0;
2597 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2598 LoadNode, InputChain))
2601 SDValue Base, Scale, Index, Disp, Segment;
2602 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2603 Base, Scale, Index, Disp, Segment))
2606 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2607 MemOp[0] = StoreNode->getMemOperand();
2608 MemOp[1] = LoadNode->getMemOperand();
2609 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2610 EVT LdVT = LoadNode->getMemoryVT();
2611 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2612 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2613 Node->getDebugLoc(),
2614 MVT::i32, MVT::Other, Ops,
2615 array_lengthof(Ops));
2616 Result->setMemRefs(MemOp, MemOp + 2);
2618 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2619 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2624 // FIXME: Custom handling because TableGen doesn't support multiple implicit
2625 // defs in an instruction pattern
2626 case X86ISD::PCMPESTRI: {
2627 SDValue N0 = Node->getOperand(0);
2628 SDValue N1 = Node->getOperand(1);
2629 SDValue N2 = Node->getOperand(2);
2630 SDValue N3 = Node->getOperand(3);
2631 SDValue N4 = Node->getOperand(4);
2633 // Make sure last argument is a constant
2634 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N4);
2638 uint64_t Imm = Cst->getZExtValue();
2640 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2641 X86::EAX, N1, SDValue()).getValue(1);
2642 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::EDX,
2643 N3, InFlag).getValue(1);
2645 SDValue Ops[] = { N0, N2, getI8Imm(Imm), InFlag };
2646 unsigned Opc = Subtarget->hasAVX() ? X86::VPCMPESTRIrr :
2648 InFlag = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Ops,
2649 array_lengthof(Ops)), 0);
2651 if (!SDValue(Node, 0).use_empty()) {
2652 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2653 X86::ECX, NVT, InFlag);
2654 InFlag = Result.getValue(2);
2655 ReplaceUses(SDValue(Node, 0), Result);
2657 if (!SDValue(Node, 1).use_empty()) {
2658 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2659 X86::EFLAGS, NVT, InFlag);
2660 InFlag = Result.getValue(2);
2661 ReplaceUses(SDValue(Node, 1), Result);
2667 // FIXME: Custom handling because TableGen doesn't support multiple implicit
2668 // defs in an instruction pattern
2669 case X86ISD::PCMPISTRI: {
2670 SDValue N0 = Node->getOperand(0);
2671 SDValue N1 = Node->getOperand(1);
2672 SDValue N2 = Node->getOperand(2);
2674 // Make sure last argument is a constant
2675 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N2);
2679 uint64_t Imm = Cst->getZExtValue();
2681 SDValue Ops[] = { N0, N1, getI8Imm(Imm) };
2682 unsigned Opc = Subtarget->hasAVX() ? X86::VPCMPISTRIrr :
2684 SDValue InFlag = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Ops,
2685 array_lengthof(Ops)), 0);
2687 if (!SDValue(Node, 0).use_empty()) {
2688 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2689 X86::ECX, NVT, InFlag);
2690 InFlag = Result.getValue(2);
2691 ReplaceUses(SDValue(Node, 0), Result);
2693 if (!SDValue(Node, 1).use_empty()) {
2694 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2695 X86::EFLAGS, NVT, InFlag);
2696 InFlag = Result.getValue(2);
2697 ReplaceUses(SDValue(Node, 1), Result);
2704 SDNode *ResNode = SelectCode(Node);
2706 DEBUG(dbgs() << "=> ";
2707 if (ResNode == NULL || ResNode == Node)
2710 ResNode->dump(CurDAG);
2716 bool X86DAGToDAGISel::
2717 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2718 std::vector<SDValue> &OutOps) {
2719 SDValue Op0, Op1, Op2, Op3, Op4;
2720 switch (ConstraintCode) {
2721 case 'o': // offsetable ??
2722 case 'v': // not offsetable ??
2723 default: return true;
2725 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
2730 OutOps.push_back(Op0);
2731 OutOps.push_back(Op1);
2732 OutOps.push_back(Op2);
2733 OutOps.push_back(Op3);
2734 OutOps.push_back(Op4);
2738 /// createX86ISelDag - This pass converts a legalized DAG into a
2739 /// X86-specific DAG, ready for instruction scheduling.
2741 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2742 CodeGenOpt::Level OptLevel) {
2743 return new X86DAGToDAGISel(TM, OptLevel);