1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "x86-isel"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
77 JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != nullptr || CP != nullptr || ES != nullptr ||
82 JT != -1 || BlockAddr != nullptr;
85 bool hasBaseOrIndexReg() const {
86 return BaseType == FrameIndexBase ||
87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
90 /// isRIPRelative - Return true if this addressing mode is already RIP
92 bool isRIPRelative() const {
93 if (BaseType != RegBase) return false;
94 if (RegisterSDNode *RegNode =
95 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
96 return RegNode->getReg() == X86::RIP;
100 void setBaseReg(SDValue Reg) {
105 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
107 dbgs() << "X86ISelAddressMode " << this << '\n';
108 dbgs() << "Base_Reg ";
109 if (Base_Reg.getNode())
110 Base_Reg.getNode()->dump();
113 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
114 << " Scale" << Scale << '\n'
116 if (IndexReg.getNode())
117 IndexReg.getNode()->dump();
120 dbgs() << " Disp " << Disp << '\n'
137 dbgs() << " JT" << JT << " Align" << Align << '\n';
144 //===--------------------------------------------------------------------===//
145 /// ISel - X86 specific code to select X86 machine instructions for
146 /// SelectionDAG operations.
148 class X86DAGToDAGISel final : public SelectionDAGISel {
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel), OptForSize(false) {}
161 const char *getPassName() const override {
162 return "X86 DAG->DAG Instruction Selection";
165 bool runOnMachineFunction(MachineFunction &MF) override {
166 // Reset the subtarget each time through.
167 Subtarget = &MF.getSubtarget<X86Subtarget>();
168 SelectionDAGISel::runOnMachineFunction(MF);
172 void EmitFunctionEntryCode() override;
174 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
176 void PreprocessISelDAG() override;
178 inline bool immSext8(SDNode *N) const {
179 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
182 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
183 // sign extended field.
184 inline bool i64immSExt32(SDNode *N) const {
185 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
186 return (int64_t)v == (int32_t)v;
189 // Include the pieces autogenerated from the target description.
190 #include "X86GenDAGISel.inc"
193 SDNode *Select(SDNode *N) override;
194 SDNode *SelectGather(SDNode *N, unsigned Opc);
195 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
197 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
198 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
204 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
208 SDValue &Scale, SDValue &Index, SDValue &Disp,
210 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
211 bool SelectLEAAddr(SDValue N, SDValue &Base,
212 SDValue &Scale, SDValue &Index, SDValue &Disp,
214 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
215 SDValue &Scale, SDValue &Index, SDValue &Disp,
217 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
218 SDValue &Scale, SDValue &Index, SDValue &Disp,
220 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
221 SDValue &Base, SDValue &Scale,
222 SDValue &Index, SDValue &Disp,
224 SDValue &NodeWithChain);
226 bool TryFoldLoad(SDNode *P, SDValue N,
227 SDValue &Base, SDValue &Scale,
228 SDValue &Index, SDValue &Disp,
231 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
232 /// inline asm expressions.
233 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
234 unsigned ConstraintID,
235 std::vector<SDValue> &OutOps) override;
237 void EmitSpecialCodeForMain();
239 inline void getAddressOperands(X86ISelAddressMode &AM, SDLoc DL,
240 SDValue &Base, SDValue &Scale,
241 SDValue &Index, SDValue &Disp,
243 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
244 ? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
247 Scale = getI8Imm(AM.Scale, DL);
249 // These are 32-bit even in 64-bit mode since RIP relative offset
252 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
256 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
257 AM.Align, AM.Disp, AM.SymbolFlags);
259 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
260 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
261 } else if (AM.JT != -1) {
262 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
263 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
264 } else if (AM.BlockAddr)
265 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
268 Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32);
270 if (AM.Segment.getNode())
271 Segment = AM.Segment;
273 Segment = CurDAG->getRegister(0, MVT::i32);
276 /// getI8Imm - Return a target constant with the specified value, of type
278 inline SDValue getI8Imm(unsigned Imm, SDLoc DL) {
279 return CurDAG->getTargetConstant(Imm, DL, MVT::i8);
282 /// getI32Imm - Return a target constant with the specified value, of type
284 inline SDValue getI32Imm(unsigned Imm, SDLoc DL) {
285 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
288 /// getGlobalBaseReg - Return an SDNode that returns the value of
289 /// the global base register. Output instructions required to
290 /// initialize the global base register, if necessary.
292 SDNode *getGlobalBaseReg();
294 /// getTargetMachine - Return a reference to the TargetMachine, casted
295 /// to the target-specific type.
296 const X86TargetMachine &getTargetMachine() const {
297 return static_cast<const X86TargetMachine &>(TM);
300 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
301 /// to the target-specific type.
302 const X86InstrInfo *getInstrInfo() const {
303 return Subtarget->getInstrInfo();
306 /// \brief Address-mode matching performs shift-of-and to and-of-shift
307 /// reassociation in order to expose more scaled addressing
309 bool ComplexPatternFuncMutatesDAG() const override {
317 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
318 if (OptLevel == CodeGenOpt::None) return false;
323 if (N.getOpcode() != ISD::LOAD)
326 // If N is a load, do additional profitability checks.
328 switch (U->getOpcode()) {
341 SDValue Op1 = U->getOperand(1);
343 // If the other operand is a 8-bit immediate we should fold the immediate
344 // instead. This reduces code size.
346 // movl 4(%esp), %eax
350 // addl 4(%esp), %eax
351 // The former is 2 bytes shorter. In case where the increment is 1, then
352 // the saving can be 4 bytes (by using incl %eax).
353 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
354 if (Imm->getAPIntValue().isSignedIntN(8))
357 // If the other operand is a TLS address, we should fold it instead.
360 // leal i@NTPOFF(%eax), %eax
362 // movl $i@NTPOFF, %eax
364 // if the block also has an access to a second TLS address this will save
366 // FIXME: This is probably also true for non-TLS addresses.
367 if (Op1.getOpcode() == X86ISD::Wrapper) {
368 SDValue Val = Op1.getOperand(0);
369 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
379 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
380 /// load's chain operand and move load below the call's chain operand.
381 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
382 SDValue Call, SDValue OrigChain) {
383 SmallVector<SDValue, 8> Ops;
384 SDValue Chain = OrigChain.getOperand(0);
385 if (Chain.getNode() == Load.getNode())
386 Ops.push_back(Load.getOperand(0));
388 assert(Chain.getOpcode() == ISD::TokenFactor &&
389 "Unexpected chain operand");
390 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
391 if (Chain.getOperand(i).getNode() == Load.getNode())
392 Ops.push_back(Load.getOperand(0));
394 Ops.push_back(Chain.getOperand(i));
396 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
398 Ops.push_back(NewChain);
400 Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end());
401 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
402 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
403 Load.getOperand(1), Load.getOperand(2));
406 Ops.push_back(SDValue(Load.getNode(), 1));
407 Ops.append(Call->op_begin() + 1, Call->op_end());
408 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
411 /// isCalleeLoad - Return true if call address is a load and it can be
412 /// moved below CALLSEQ_START and the chains leading up to the call.
413 /// Return the CALLSEQ_START by reference as a second output.
414 /// In the case of a tail call, there isn't a callseq node between the call
415 /// chain and the load.
416 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
417 // The transformation is somewhat dangerous if the call's chain was glued to
418 // the call. After MoveBelowOrigChain the load is moved between the call and
419 // the chain, this can create a cycle if the load is not folded. So it is
420 // *really* important that we are sure the load will be folded.
421 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
423 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
426 LD->getAddressingMode() != ISD::UNINDEXED ||
427 LD->getExtensionType() != ISD::NON_EXTLOAD)
430 // Now let's find the callseq_start.
431 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
432 if (!Chain.hasOneUse())
434 Chain = Chain.getOperand(0);
437 if (!Chain.getNumOperands())
439 // Since we are not checking for AA here, conservatively abort if the chain
440 // writes to memory. It's not safe to move the callee (a load) across a store.
441 if (isa<MemSDNode>(Chain.getNode()) &&
442 cast<MemSDNode>(Chain.getNode())->writeMem())
444 if (Chain.getOperand(0).getNode() == Callee.getNode())
446 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
447 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
448 Callee.getValue(1).hasOneUse())
453 void X86DAGToDAGISel::PreprocessISelDAG() {
454 // OptForSize is used in pattern predicates that isel is matching.
455 OptForSize = MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
457 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
458 E = CurDAG->allnodes_end(); I != E; ) {
459 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
461 if (OptLevel != CodeGenOpt::None &&
462 // Only does this when target favors doesn't favor register indirect
464 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
465 (N->getOpcode() == X86ISD::TC_RETURN &&
466 // Only does this if load can be folded into TC_RETURN.
467 (Subtarget->is64Bit() ||
468 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
469 /// Also try moving call address load from outside callseq_start to just
470 /// before the call to allow it to be folded.
488 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
489 SDValue Chain = N->getOperand(0);
490 SDValue Load = N->getOperand(1);
491 if (!isCalleeLoad(Load, Chain, HasCallSeq))
493 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
498 // Lower fpround and fpextend nodes that target the FP stack to be store and
499 // load to the stack. This is a gross hack. We would like to simply mark
500 // these as being illegal, but when we do that, legalize produces these when
501 // it expands calls, then expands these in the same legalize pass. We would
502 // like dag combine to be able to hack on these between the call expansion
503 // and the node legalization. As such this pass basically does "really
504 // late" legalization of these inline with the X86 isel pass.
505 // FIXME: This should only happen when not compiled with -O0.
506 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
509 MVT SrcVT = N->getOperand(0).getSimpleValueType();
510 MVT DstVT = N->getSimpleValueType(0);
512 // If any of the sources are vectors, no fp stack involved.
513 if (SrcVT.isVector() || DstVT.isVector())
516 // If the source and destination are SSE registers, then this is a legal
517 // conversion that should not be lowered.
518 const X86TargetLowering *X86Lowering =
519 static_cast<const X86TargetLowering *>(TLI);
520 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
521 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
522 if (SrcIsSSE && DstIsSSE)
525 if (!SrcIsSSE && !DstIsSSE) {
526 // If this is an FPStack extension, it is a noop.
527 if (N->getOpcode() == ISD::FP_EXTEND)
529 // If this is a value-preserving FPStack truncation, it is a noop.
530 if (N->getConstantOperandVal(1))
534 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
535 // FPStack has extload and truncstore. SSE can fold direct loads into other
536 // operations. Based on this, decide what we want to do.
538 if (N->getOpcode() == ISD::FP_ROUND)
539 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
541 MemVT = SrcIsSSE ? SrcVT : DstVT;
543 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
546 // FIXME: optimize the case where the src/dest is a load or store?
547 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
549 MemTmp, MachinePointerInfo(), MemVT,
551 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
552 MachinePointerInfo(),
553 MemVT, false, false, false, 0);
555 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
556 // extload we created. This will cause general havok on the dag because
557 // anything below the conversion could be folded into other existing nodes.
558 // To avoid invalidating 'I', back it up to the convert node.
560 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
562 // Now that we did that, the node is dead. Increment the iterator to the
563 // next node to process, then delete N.
565 CurDAG->DeleteNode(N);
570 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
571 /// the main function.
572 void X86DAGToDAGISel::EmitSpecialCodeForMain() {
573 if (Subtarget->isTargetCygMing()) {
574 TargetLowering::ArgListTy Args;
576 TargetLowering::CallLoweringInfo CLI(*CurDAG);
577 CLI.setChain(CurDAG->getRoot())
578 .setCallee(CallingConv::C, Type::getVoidTy(*CurDAG->getContext()),
579 CurDAG->getExternalSymbol("__main", TLI->getPointerTy()),
581 const TargetLowering &TLI = CurDAG->getTargetLoweringInfo();
582 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
583 CurDAG->setRoot(Result.second);
587 void X86DAGToDAGISel::EmitFunctionEntryCode() {
588 // If this is main, emit special code for main.
589 if (const Function *Fn = MF->getFunction())
590 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
591 EmitSpecialCodeForMain();
594 static bool isDispSafeForFrameIndex(int64_t Val) {
595 // On 64-bit platforms, we can run into an issue where a frame index
596 // includes a displacement that, when added to the explicit displacement,
597 // will overflow the displacement field. Assuming that the frame index
598 // displacement fits into a 31-bit integer (which is only slightly more
599 // aggressive than the current fundamental assumption that it fits into
600 // a 32-bit integer), a 31-bit disp should always be safe.
601 return isInt<31>(Val);
604 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
605 X86ISelAddressMode &AM) {
606 // Cannot combine ExternalSymbol displacements with integer offsets.
607 if (Offset != 0 && AM.ES)
609 int64_t Val = AM.Disp + Offset;
610 CodeModel::Model M = TM.getCodeModel();
611 if (Subtarget->is64Bit()) {
612 if (!X86::isOffsetSuitableForCodeModel(Val, M,
613 AM.hasSymbolicDisplacement()))
615 // In addition to the checks required for a register base, check that
616 // we do not try to use an unsafe Disp with a frame index.
617 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
618 !isDispSafeForFrameIndex(Val))
626 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
627 SDValue Address = N->getOperand(1);
629 // load gs:0 -> GS segment register.
630 // load fs:0 -> FS segment register.
632 // This optimization is valid because the GNU TLS model defines that
633 // gs:0 (or fs:0 on X86-64) contains its own address.
634 // For more information see http://people.redhat.com/drepper/tls.pdf
635 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
636 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
637 Subtarget->isTargetLinux())
638 switch (N->getPointerInfo().getAddrSpace()) {
640 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
643 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
650 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
651 /// into an addressing mode. These wrap things that will resolve down into a
652 /// symbol reference. If no match is possible, this returns true, otherwise it
654 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
655 // If the addressing mode already has a symbol as the displacement, we can
656 // never match another symbol.
657 if (AM.hasSymbolicDisplacement())
660 SDValue N0 = N.getOperand(0);
661 CodeModel::Model M = TM.getCodeModel();
663 // Handle X86-64 rip-relative addresses. We check this before checking direct
664 // folding because RIP is preferable to non-RIP accesses.
665 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
666 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
667 // they cannot be folded into immediate fields.
668 // FIXME: This can be improved for kernel and other models?
669 (M == CodeModel::Small || M == CodeModel::Kernel)) {
670 // Base and index reg must be 0 in order to use %rip as base.
671 if (AM.hasBaseOrIndexReg())
673 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
674 X86ISelAddressMode Backup = AM;
675 AM.GV = G->getGlobal();
676 AM.SymbolFlags = G->getTargetFlags();
677 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
681 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
682 X86ISelAddressMode Backup = AM;
683 AM.CP = CP->getConstVal();
684 AM.Align = CP->getAlignment();
685 AM.SymbolFlags = CP->getTargetFlags();
686 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
690 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
691 AM.ES = S->getSymbol();
692 AM.SymbolFlags = S->getTargetFlags();
693 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
694 AM.JT = J->getIndex();
695 AM.SymbolFlags = J->getTargetFlags();
696 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
697 X86ISelAddressMode Backup = AM;
698 AM.BlockAddr = BA->getBlockAddress();
699 AM.SymbolFlags = BA->getTargetFlags();
700 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
705 llvm_unreachable("Unhandled symbol reference node.");
707 if (N.getOpcode() == X86ISD::WrapperRIP)
708 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
712 // Handle the case when globals fit in our immediate field: This is true for
713 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
714 // mode, this only applies to a non-RIP-relative computation.
715 if (!Subtarget->is64Bit() ||
716 M == CodeModel::Small || M == CodeModel::Kernel) {
717 assert(N.getOpcode() != X86ISD::WrapperRIP &&
718 "RIP-relative addressing already handled");
719 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
720 AM.GV = G->getGlobal();
721 AM.Disp += G->getOffset();
722 AM.SymbolFlags = G->getTargetFlags();
723 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
724 AM.CP = CP->getConstVal();
725 AM.Align = CP->getAlignment();
726 AM.Disp += CP->getOffset();
727 AM.SymbolFlags = CP->getTargetFlags();
728 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
729 AM.ES = S->getSymbol();
730 AM.SymbolFlags = S->getTargetFlags();
731 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
732 AM.JT = J->getIndex();
733 AM.SymbolFlags = J->getTargetFlags();
734 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
735 AM.BlockAddr = BA->getBlockAddress();
736 AM.Disp += BA->getOffset();
737 AM.SymbolFlags = BA->getTargetFlags();
739 llvm_unreachable("Unhandled symbol reference node.");
746 /// MatchAddress - Add the specified node to the specified addressing mode,
747 /// returning true if it cannot be done. This just pattern matches for the
749 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
750 if (MatchAddressRecursively(N, AM, 0))
753 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
754 // a smaller encoding and avoids a scaled-index.
756 AM.BaseType == X86ISelAddressMode::RegBase &&
757 AM.Base_Reg.getNode() == nullptr) {
758 AM.Base_Reg = AM.IndexReg;
762 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
763 // because it has a smaller encoding.
764 // TODO: Which other code models can use this?
765 if (TM.getCodeModel() == CodeModel::Small &&
766 Subtarget->is64Bit() &&
768 AM.BaseType == X86ISelAddressMode::RegBase &&
769 AM.Base_Reg.getNode() == nullptr &&
770 AM.IndexReg.getNode() == nullptr &&
771 AM.SymbolFlags == X86II::MO_NO_FLAG &&
772 AM.hasSymbolicDisplacement())
773 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
778 // Insert a node into the DAG at least before the Pos node's position. This
779 // will reposition the node as needed, and will assign it a node ID that is <=
780 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
781 // IDs! The selection DAG must no longer depend on their uniqueness when this
783 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
784 if (N.getNode()->getNodeId() == -1 ||
785 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
786 DAG.RepositionNode(Pos.getNode(), N.getNode());
787 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
791 // Transform "(X >> (8-C1)) & (0xff << C1)" to "((X >> 8) & 0xff) << C1" if
792 // safe. This allows us to convert the shift and and into an h-register
793 // extract and a scaled index. Returns false if the simplification is
795 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
797 SDValue Shift, SDValue X,
798 X86ISelAddressMode &AM) {
799 if (Shift.getOpcode() != ISD::SRL ||
800 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
804 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
805 if (ScaleLog <= 0 || ScaleLog >= 4 ||
806 Mask != (0xffu << ScaleLog))
809 MVT VT = N.getSimpleValueType();
811 SDValue Eight = DAG.getConstant(8, DL, MVT::i8);
812 SDValue NewMask = DAG.getConstant(0xff, DL, VT);
813 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
814 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
815 SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8);
816 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
818 // Insert the new nodes into the topological ordering. We must do this in
819 // a valid topological ordering as nothing is going to go back and re-sort
820 // these nodes. We continually insert before 'N' in sequence as this is
821 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
822 // hierarchy left to express.
823 InsertDAGNode(DAG, N, Eight);
824 InsertDAGNode(DAG, N, Srl);
825 InsertDAGNode(DAG, N, NewMask);
826 InsertDAGNode(DAG, N, And);
827 InsertDAGNode(DAG, N, ShlCount);
828 InsertDAGNode(DAG, N, Shl);
829 DAG.ReplaceAllUsesWith(N, Shl);
831 AM.Scale = (1 << ScaleLog);
835 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
836 // allows us to fold the shift into this addressing mode. Returns false if the
837 // transform succeeded.
838 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
840 SDValue Shift, SDValue X,
841 X86ISelAddressMode &AM) {
842 if (Shift.getOpcode() != ISD::SHL ||
843 !isa<ConstantSDNode>(Shift.getOperand(1)))
846 // Not likely to be profitable if either the AND or SHIFT node has more
847 // than one use (unless all uses are for address computation). Besides,
848 // isel mechanism requires their node ids to be reused.
849 if (!N.hasOneUse() || !Shift.hasOneUse())
852 // Verify that the shift amount is something we can fold.
853 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
854 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
857 MVT VT = N.getSimpleValueType();
859 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);
860 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
861 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
863 // Insert the new nodes into the topological ordering. We must do this in
864 // a valid topological ordering as nothing is going to go back and re-sort
865 // these nodes. We continually insert before 'N' in sequence as this is
866 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
867 // hierarchy left to express.
868 InsertDAGNode(DAG, N, NewMask);
869 InsertDAGNode(DAG, N, NewAnd);
870 InsertDAGNode(DAG, N, NewShift);
871 DAG.ReplaceAllUsesWith(N, NewShift);
873 AM.Scale = 1 << ShiftAmt;
874 AM.IndexReg = NewAnd;
878 // Implement some heroics to detect shifts of masked values where the mask can
879 // be replaced by extending the shift and undoing that in the addressing mode
880 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
881 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
882 // the addressing mode. This results in code such as:
884 // int f(short *y, int *lookup_table) {
886 // return *y + lookup_table[*y >> 11];
890 // movzwl (%rdi), %eax
893 // addl (%rsi,%rcx,4), %eax
896 // movzwl (%rdi), %eax
900 // addl (%rsi,%rcx), %eax
902 // Note that this function assumes the mask is provided as a mask *after* the
903 // value is shifted. The input chain may or may not match that, but computing
904 // such a mask is trivial.
905 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
907 SDValue Shift, SDValue X,
908 X86ISelAddressMode &AM) {
909 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
910 !isa<ConstantSDNode>(Shift.getOperand(1)))
913 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
914 unsigned MaskLZ = countLeadingZeros(Mask);
915 unsigned MaskTZ = countTrailingZeros(Mask);
917 // The amount of shift we're trying to fit into the addressing mode is taken
918 // from the trailing zeros of the mask.
919 unsigned AMShiftAmt = MaskTZ;
921 // There is nothing we can do here unless the mask is removing some bits.
922 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
923 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
925 // We also need to ensure that mask is a continuous run of bits.
926 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
928 // Scale the leading zero count down based on the actual size of the value.
929 // Also scale it down based on the size of the shift.
930 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
932 // The final check is to ensure that any masked out high bits of X are
933 // already known to be zero. Otherwise, the mask has a semantic impact
934 // other than masking out a couple of low bits. Unfortunately, because of
935 // the mask, zero extensions will be removed from operands in some cases.
936 // This code works extra hard to look through extensions because we can
937 // replace them with zero extensions cheaply if necessary.
938 bool ReplacingAnyExtend = false;
939 if (X.getOpcode() == ISD::ANY_EXTEND) {
940 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
941 X.getOperand(0).getSimpleValueType().getSizeInBits();
942 // Assume that we'll replace the any-extend with a zero-extend, and
943 // narrow the search to the extended value.
945 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
946 ReplacingAnyExtend = true;
948 APInt MaskedHighBits =
949 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
950 APInt KnownZero, KnownOne;
951 DAG.computeKnownBits(X, KnownZero, KnownOne);
952 if (MaskedHighBits != KnownZero) return true;
954 // We've identified a pattern that can be transformed into a single shift
955 // and an addressing mode. Make it so.
956 MVT VT = N.getSimpleValueType();
957 if (ReplacingAnyExtend) {
958 assert(X.getValueType() != VT);
959 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
960 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
961 InsertDAGNode(DAG, N, NewX);
965 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);
966 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
967 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8);
968 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
970 // Insert the new nodes into the topological ordering. We must do this in
971 // a valid topological ordering as nothing is going to go back and re-sort
972 // these nodes. We continually insert before 'N' in sequence as this is
973 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
974 // hierarchy left to express.
975 InsertDAGNode(DAG, N, NewSRLAmt);
976 InsertDAGNode(DAG, N, NewSRL);
977 InsertDAGNode(DAG, N, NewSHLAmt);
978 InsertDAGNode(DAG, N, NewSHL);
979 DAG.ReplaceAllUsesWith(N, NewSHL);
981 AM.Scale = 1 << AMShiftAmt;
982 AM.IndexReg = NewSRL;
986 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
990 dbgs() << "MatchAddress: ";
995 return MatchAddressBase(N, AM);
997 // If this is already a %rip relative address, we can only merge immediates
998 // into it. Instead of handling this in every case, we handle it here.
999 // RIP relative addressing: %rip + 32-bit displacement!
1000 if (AM.isRIPRelative()) {
1001 // FIXME: JumpTable and ExternalSymbol address currently don't like
1002 // displacements. It isn't very important, but this should be fixed for
1004 if (!AM.ES && AM.JT != -1) return true;
1006 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
1007 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
1012 switch (N.getOpcode()) {
1014 case ISD::FRAME_ALLOC_RECOVER: {
1015 if (!AM.hasSymbolicDisplacement() && AM.Disp == 0)
1016 if (const auto *ESNode = dyn_cast<ExternalSymbolSDNode>(N.getOperand(0)))
1017 if (ESNode->getOpcode() == ISD::TargetExternalSymbol) {
1018 // Use the symbol and don't prefix it.
1019 AM.ES = ESNode->getSymbol();
1020 AM.SymbolFlags = X86II::MO_NOPREFIX;
1025 case ISD::Constant: {
1026 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1027 if (!FoldOffsetIntoAddress(Val, AM))
1032 case X86ISD::Wrapper:
1033 case X86ISD::WrapperRIP:
1034 if (!MatchWrapper(N, AM))
1039 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1043 case ISD::FrameIndex:
1044 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1045 AM.Base_Reg.getNode() == nullptr &&
1046 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1047 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1048 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1054 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1058 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1059 unsigned Val = CN->getZExtValue();
1060 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1061 // that the base operand remains free for further matching. If
1062 // the base doesn't end up getting used, a post-processing step
1063 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1064 if (Val == 1 || Val == 2 || Val == 3) {
1065 AM.Scale = 1 << Val;
1066 SDValue ShVal = N.getNode()->getOperand(0);
1068 // Okay, we know that we have a scale by now. However, if the scaled
1069 // value is an add of something and a constant, we can fold the
1070 // constant into the disp field here.
1071 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1072 AM.IndexReg = ShVal.getNode()->getOperand(0);
1073 ConstantSDNode *AddVal =
1074 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1075 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1076 if (!FoldOffsetIntoAddress(Disp, AM))
1080 AM.IndexReg = ShVal;
1087 // Scale must not be used already.
1088 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1090 SDValue And = N.getOperand(0);
1091 if (And.getOpcode() != ISD::AND) break;
1092 SDValue X = And.getOperand(0);
1094 // We only handle up to 64-bit values here as those are what matter for
1095 // addressing mode optimizations.
1096 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1098 // The mask used for the transform is expected to be post-shift, but we
1099 // found the shift first so just apply the shift to the mask before passing
1101 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1102 !isa<ConstantSDNode>(And.getOperand(1)))
1104 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1106 // Try to fold the mask and shift into the scale, and return false if we
1108 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1113 case ISD::SMUL_LOHI:
1114 case ISD::UMUL_LOHI:
1115 // A mul_lohi where we need the low part can be folded as a plain multiply.
1116 if (N.getResNo() != 0) break;
1119 case X86ISD::MUL_IMM:
1120 // X*[3,5,9] -> X+X*[2,4,8]
1121 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1122 AM.Base_Reg.getNode() == nullptr &&
1123 AM.IndexReg.getNode() == nullptr) {
1125 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1126 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1127 CN->getZExtValue() == 9) {
1128 AM.Scale = unsigned(CN->getZExtValue())-1;
1130 SDValue MulVal = N.getNode()->getOperand(0);
1133 // Okay, we know that we have a scale by now. However, if the scaled
1134 // value is an add of something and a constant, we can fold the
1135 // constant into the disp field here.
1136 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1137 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1138 Reg = MulVal.getNode()->getOperand(0);
1139 ConstantSDNode *AddVal =
1140 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1141 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1142 if (FoldOffsetIntoAddress(Disp, AM))
1143 Reg = N.getNode()->getOperand(0);
1145 Reg = N.getNode()->getOperand(0);
1148 AM.IndexReg = AM.Base_Reg = Reg;
1155 // Given A-B, if A can be completely folded into the address and
1156 // the index field with the index field unused, use -B as the index.
1157 // This is a win if a has multiple parts that can be folded into
1158 // the address. Also, this saves a mov if the base register has
1159 // other uses, since it avoids a two-address sub instruction, however
1160 // it costs an additional mov if the index register has other uses.
1162 // Add an artificial use to this node so that we can keep track of
1163 // it if it gets CSE'd with a different node.
1164 HandleSDNode Handle(N);
1166 // Test if the LHS of the sub can be folded.
1167 X86ISelAddressMode Backup = AM;
1168 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1172 // Test if the index field is free for use.
1173 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1179 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1180 // If the RHS involves a register with multiple uses, this
1181 // transformation incurs an extra mov, due to the neg instruction
1182 // clobbering its operand.
1183 if (!RHS.getNode()->hasOneUse() ||
1184 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1185 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1186 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1187 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1188 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1190 // If the base is a register with multiple uses, this
1191 // transformation may save a mov.
1192 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1193 AM.Base_Reg.getNode() &&
1194 !AM.Base_Reg.getNode()->hasOneUse()) ||
1195 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1197 // If the folded LHS was interesting, this transformation saves
1198 // address arithmetic.
1199 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1200 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1201 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1203 // If it doesn't look like it may be an overall win, don't do it.
1209 // Ok, the transformation is legal and appears profitable. Go for it.
1210 SDValue Zero = CurDAG->getConstant(0, dl, N.getValueType());
1211 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1215 // Insert the new nodes into the topological ordering.
1216 InsertDAGNode(*CurDAG, N, Zero);
1217 InsertDAGNode(*CurDAG, N, Neg);
1222 // Add an artificial use to this node so that we can keep track of
1223 // it if it gets CSE'd with a different node.
1224 HandleSDNode Handle(N);
1226 X86ISelAddressMode Backup = AM;
1227 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1228 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1232 // Try again after commuting the operands.
1233 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1234 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1238 // If we couldn't fold both operands into the address at the same time,
1239 // see if we can just put each operand into a register and fold at least
1241 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1242 !AM.Base_Reg.getNode() &&
1243 !AM.IndexReg.getNode()) {
1244 N = Handle.getValue();
1245 AM.Base_Reg = N.getOperand(0);
1246 AM.IndexReg = N.getOperand(1);
1250 N = Handle.getValue();
1255 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1256 if (CurDAG->isBaseWithConstantOffset(N)) {
1257 X86ISelAddressMode Backup = AM;
1258 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1260 // Start with the LHS as an addr mode.
1261 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1262 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1269 // Perform some heroic transforms on an and of a constant-count shift
1270 // with a constant to enable use of the scaled offset field.
1272 // Scale must not be used already.
1273 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1275 SDValue Shift = N.getOperand(0);
1276 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1277 SDValue X = Shift.getOperand(0);
1279 // We only handle up to 64-bit values here as those are what matter for
1280 // addressing mode optimizations.
1281 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1283 if (!isa<ConstantSDNode>(N.getOperand(1)))
1285 uint64_t Mask = N.getConstantOperandVal(1);
1287 // Try to fold the mask and shift into an extract and scale.
1288 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1291 // Try to fold the mask and shift directly into the scale.
1292 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1295 // Try to swap the mask and shift to place shifts which can be done as
1296 // a scale on the outside of the mask.
1297 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1303 return MatchAddressBase(N, AM);
1306 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1307 /// specified addressing mode without any further recursion.
1308 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1309 // Is the base register already occupied?
1310 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1311 // If so, check to see if the scale index register is set.
1312 if (!AM.IndexReg.getNode()) {
1318 // Otherwise, we cannot select it.
1322 // Default, generate it as a register.
1323 AM.BaseType = X86ISelAddressMode::RegBase;
1328 bool X86DAGToDAGISel::SelectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
1329 SDValue &Scale, SDValue &Index,
1330 SDValue &Disp, SDValue &Segment) {
1332 MaskedGatherScatterSDNode *Mgs = dyn_cast<MaskedGatherScatterSDNode>(Parent);
1335 X86ISelAddressMode AM;
1336 unsigned AddrSpace = Mgs->getPointerInfo().getAddrSpace();
1337 // AddrSpace 256 -> GS, 257 -> FS.
1338 if (AddrSpace == 256)
1339 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1340 if (AddrSpace == 257)
1341 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1344 Base = Mgs->getBasePtr();
1345 Index = Mgs->getIndex();
1346 unsigned ScalarSize = Mgs->getValue().getValueType().getScalarSizeInBits();
1347 Scale = getI8Imm(ScalarSize/8, DL);
1349 // If Base is 0, the whole address is in index and the Scale is 1
1350 if (isa<ConstantSDNode>(Base)) {
1351 assert(dyn_cast<ConstantSDNode>(Base)->isNullValue() &&
1352 "Unexpected base in gather/scatter");
1353 Scale = getI8Imm(1, DL);
1354 Base = CurDAG->getRegister(0, MVT::i32);
1356 if (AM.Segment.getNode())
1357 Segment = AM.Segment;
1359 Segment = CurDAG->getRegister(0, MVT::i32);
1360 Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1364 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1365 /// It returns the operands which make up the maximal addressing mode it can
1366 /// match by reference.
1368 /// Parent is the parent node of the addr operand that is being matched. It
1369 /// is always a load, store, atomic node, or null. It is only null when
1370 /// checking memory operands for inline asm nodes.
1371 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1372 SDValue &Scale, SDValue &Index,
1373 SDValue &Disp, SDValue &Segment) {
1374 X86ISelAddressMode AM;
1377 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1378 // that are not a MemSDNode, and thus don't have proper addrspace info.
1379 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1380 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1381 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1382 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1383 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1384 unsigned AddrSpace =
1385 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1386 // AddrSpace 256 -> GS, 257 -> FS.
1387 if (AddrSpace == 256)
1388 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1389 if (AddrSpace == 257)
1390 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1393 if (MatchAddress(N, AM))
1396 MVT VT = N.getSimpleValueType();
1397 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1398 if (!AM.Base_Reg.getNode())
1399 AM.Base_Reg = CurDAG->getRegister(0, VT);
1402 if (!AM.IndexReg.getNode())
1403 AM.IndexReg = CurDAG->getRegister(0, VT);
1405 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1409 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1410 /// match a load whose top elements are either undef or zeros. The load flavor
1411 /// is derived from the type of N, which is either v4f32 or v2f64.
1414 /// PatternChainNode: this is the matched node that has a chain input and
1416 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1417 SDValue N, SDValue &Base,
1418 SDValue &Scale, SDValue &Index,
1419 SDValue &Disp, SDValue &Segment,
1420 SDValue &PatternNodeWithChain) {
1421 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1422 PatternNodeWithChain = N.getOperand(0);
1423 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1424 PatternNodeWithChain.hasOneUse() &&
1425 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1426 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1427 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1428 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1434 // Also handle the case where we explicitly require zeros in the top
1435 // elements. This is a vector shuffle from the zero vector.
1436 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1437 // Check to see if the top elements are all zeros (or bitcast of zeros).
1438 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1439 N.getOperand(0).getNode()->hasOneUse() &&
1440 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1441 N.getOperand(0).getOperand(0).hasOneUse() &&
1442 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1443 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1444 // Okay, this is a zero extending load. Fold it.
1445 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1446 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1448 PatternNodeWithChain = SDValue(LD, 0);
1455 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1456 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1457 uint64_t ImmVal = CN->getZExtValue();
1458 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1461 Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i64);
1465 // In static codegen with small code model, we can get the address of a label
1466 // into a register with 'movl'. TableGen has already made sure we're looking
1467 // at a label of some kind.
1468 assert(N->getOpcode() == X86ISD::Wrapper &&
1469 "Unexpected node type for MOV32ri64");
1470 N = N.getOperand(0);
1472 if (N->getOpcode() != ISD::TargetConstantPool &&
1473 N->getOpcode() != ISD::TargetJumpTable &&
1474 N->getOpcode() != ISD::TargetGlobalAddress &&
1475 N->getOpcode() != ISD::TargetExternalSymbol &&
1476 N->getOpcode() != ISD::TargetBlockAddress)
1480 return TM.getCodeModel() == CodeModel::Small;
1483 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1484 SDValue &Scale, SDValue &Index,
1485 SDValue &Disp, SDValue &Segment) {
1486 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1490 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1491 if (RN && RN->getReg() == 0)
1492 Base = CurDAG->getRegister(0, MVT::i64);
1493 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
1494 // Base could already be %rip, particularly in the x32 ABI.
1495 Base = SDValue(CurDAG->getMachineNode(
1496 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1497 CurDAG->getTargetConstant(0, DL, MVT::i64),
1499 CurDAG->getTargetConstant(X86::sub_32bit, DL, MVT::i32)),
1503 RN = dyn_cast<RegisterSDNode>(Index);
1504 if (RN && RN->getReg() == 0)
1505 Index = CurDAG->getRegister(0, MVT::i64);
1507 assert(Index.getValueType() == MVT::i32 &&
1508 "Expect to be extending 32-bit registers for use in LEA");
1509 Index = SDValue(CurDAG->getMachineNode(
1510 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1511 CurDAG->getTargetConstant(0, DL, MVT::i64),
1513 CurDAG->getTargetConstant(X86::sub_32bit, DL,
1521 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1522 /// mode it matches can be cost effectively emitted as an LEA instruction.
1523 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1524 SDValue &Base, SDValue &Scale,
1525 SDValue &Index, SDValue &Disp,
1527 X86ISelAddressMode AM;
1529 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1531 SDValue Copy = AM.Segment;
1532 SDValue T = CurDAG->getRegister(0, MVT::i32);
1534 if (MatchAddress(N, AM))
1536 assert (T == AM.Segment);
1539 MVT VT = N.getSimpleValueType();
1540 unsigned Complexity = 0;
1541 if (AM.BaseType == X86ISelAddressMode::RegBase)
1542 if (AM.Base_Reg.getNode())
1545 AM.Base_Reg = CurDAG->getRegister(0, VT);
1546 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1549 if (AM.IndexReg.getNode())
1552 AM.IndexReg = CurDAG->getRegister(0, VT);
1554 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1559 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1560 // to a LEA. This is determined with some expermentation but is by no means
1561 // optimal (especially for code size consideration). LEA is nice because of
1562 // its three-address nature. Tweak the cost function again when we can run
1563 // convertToThreeAddress() at register allocation time.
1564 if (AM.hasSymbolicDisplacement()) {
1565 // For X86-64, we should always use lea to materialize RIP relative
1567 if (Subtarget->is64Bit())
1573 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1576 // If it isn't worth using an LEA, reject it.
1577 if (Complexity <= 2)
1580 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1584 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1585 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1586 SDValue &Scale, SDValue &Index,
1587 SDValue &Disp, SDValue &Segment) {
1588 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1589 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1591 X86ISelAddressMode AM;
1592 AM.GV = GA->getGlobal();
1593 AM.Disp += GA->getOffset();
1594 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1595 AM.SymbolFlags = GA->getTargetFlags();
1597 if (N.getValueType() == MVT::i32) {
1599 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1601 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1604 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1609 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1610 SDValue &Base, SDValue &Scale,
1611 SDValue &Index, SDValue &Disp,
1613 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1614 !IsProfitableToFold(N, P, P) ||
1615 !IsLegalToFold(N, P, P, OptLevel))
1618 return SelectAddr(N.getNode(),
1619 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1622 /// getGlobalBaseReg - Return an SDNode that returns the value of
1623 /// the global base register. Output instructions required to
1624 /// initialize the global base register, if necessary.
1626 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1627 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1628 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode();
1631 /// Atomic opcode table
1659 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1670 X86::LOCK_ADD64mi32,
1683 X86::LOCK_SUB64mi32,
1735 X86::LOCK_AND64mi32,
1748 X86::LOCK_XOR64mi32,
1753 // Return the target constant operand for atomic-load-op and do simple
1754 // translations, such as from atomic-load-add to lock-sub. The return value is
1755 // one of the following 3 cases:
1756 // + target-constant, the operand could be supported as a target constant.
1757 // + empty, the operand is not needed any more with the new op selected.
1758 // + non-empty, otherwise.
1759 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1761 enum AtomicOpc &Op, MVT NVT,
1763 const X86Subtarget *Subtarget) {
1764 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1765 int64_t CNVal = CN->getSExtValue();
1766 // Quit if not 32-bit imm.
1767 if ((int32_t)CNVal != CNVal)
1769 // Quit if INT32_MIN: it would be negated as it is negative and overflow,
1770 // producing an immediate that does not fit in the 32 bits available for
1771 // an immediate operand to sub. However, it still fits in 32 bits for the
1772 // add (since it is not negated) so we can return target-constant.
1773 if (CNVal == INT32_MIN)
1774 return CurDAG->getTargetConstant(CNVal, dl, NVT);
1775 // For atomic-load-add, we could do some optimizations.
1777 // Translate to INC/DEC if ADD by 1 or -1.
1778 if (((CNVal == 1) || (CNVal == -1)) && !Subtarget->slowIncDec()) {
1779 Op = (CNVal == 1) ? INC : DEC;
1780 // No more constant operand after being translated into INC/DEC.
1783 // Translate to SUB if ADD by negative value.
1789 return CurDAG->getTargetConstant(CNVal, dl, NVT);
1792 // If the value operand is single-used, try to optimize it.
1793 if (Op == ADD && Val.hasOneUse()) {
1794 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1795 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1797 return Val.getOperand(1);
1799 // A special case for i16, which needs truncating as, in most cases, it's
1800 // promoted to i32. We will translate
1801 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1802 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1803 Val.getOperand(0).getOpcode() == ISD::SUB &&
1804 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1806 Val = Val.getOperand(0);
1807 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1815 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1816 if (Node->hasAnyUseOfValue(0))
1821 // Optimize common patterns for __sync_or_and_fetch and similar arith
1822 // operations where the result is not used. This allows us to use the "lock"
1823 // version of the arithmetic instruction.
1824 SDValue Chain = Node->getOperand(0);
1825 SDValue Ptr = Node->getOperand(1);
1826 SDValue Val = Node->getOperand(2);
1827 SDValue Base, Scale, Index, Disp, Segment;
1828 if (!SelectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
1831 // Which index into the table.
1833 switch (Node->getOpcode()) {
1836 case ISD::ATOMIC_LOAD_OR:
1839 case ISD::ATOMIC_LOAD_AND:
1842 case ISD::ATOMIC_LOAD_XOR:
1845 case ISD::ATOMIC_LOAD_ADD:
1850 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val, Subtarget);
1851 bool isUnOp = !Val.getNode();
1852 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1855 switch (NVT.SimpleTy) {
1856 default: return nullptr;
1859 Opc = AtomicOpcTbl[Op][ConstantI8];
1861 Opc = AtomicOpcTbl[Op][I8];
1865 if (immSext8(Val.getNode()))
1866 Opc = AtomicOpcTbl[Op][SextConstantI16];
1868 Opc = AtomicOpcTbl[Op][ConstantI16];
1870 Opc = AtomicOpcTbl[Op][I16];
1874 if (immSext8(Val.getNode()))
1875 Opc = AtomicOpcTbl[Op][SextConstantI32];
1877 Opc = AtomicOpcTbl[Op][ConstantI32];
1879 Opc = AtomicOpcTbl[Op][I32];
1883 if (immSext8(Val.getNode()))
1884 Opc = AtomicOpcTbl[Op][SextConstantI64];
1885 else if (i64immSExt32(Val.getNode()))
1886 Opc = AtomicOpcTbl[Op][ConstantI64];
1888 llvm_unreachable("True 64 bits constant in SelectAtomicLoadArith");
1890 Opc = AtomicOpcTbl[Op][I64];
1894 assert(Opc != 0 && "Invalid arith lock transform!");
1896 // Building the new node.
1899 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Chain };
1900 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1902 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Val, Chain };
1903 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1906 // Copying the MachineMemOperand.
1907 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1908 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1909 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1911 // We need to have two outputs as that is what the original instruction had.
1912 // So we add a dummy, undefined output. This is safe as we checked first
1913 // that no-one uses our output anyway.
1914 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1916 SDValue RetVals[] = { Undef, Ret };
1917 return CurDAG->getMergeValues(RetVals, dl).getNode();
1920 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1921 /// any uses which require the SF or OF bits to be accurate.
1922 static bool HasNoSignedComparisonUses(SDNode *N) {
1923 // Examine each user of the node.
1924 for (SDNode::use_iterator UI = N->use_begin(),
1925 UE = N->use_end(); UI != UE; ++UI) {
1926 // Only examine CopyToReg uses.
1927 if (UI->getOpcode() != ISD::CopyToReg)
1929 // Only examine CopyToReg uses that copy to EFLAGS.
1930 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1933 // Examine each user of the CopyToReg use.
1934 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1935 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1936 // Only examine the Flag result.
1937 if (FlagUI.getUse().getResNo() != 1) continue;
1938 // Anything unusual: assume conservatively.
1939 if (!FlagUI->isMachineOpcode()) return false;
1940 // Examine the opcode of the user.
1941 switch (FlagUI->getMachineOpcode()) {
1942 // These comparisons don't treat the most significant bit specially.
1943 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1944 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1945 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1946 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1947 case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
1948 case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
1949 case X86::CMOVA16rr: case X86::CMOVA16rm:
1950 case X86::CMOVA32rr: case X86::CMOVA32rm:
1951 case X86::CMOVA64rr: case X86::CMOVA64rm:
1952 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1953 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1954 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1955 case X86::CMOVB16rr: case X86::CMOVB16rm:
1956 case X86::CMOVB32rr: case X86::CMOVB32rm:
1957 case X86::CMOVB64rr: case X86::CMOVB64rm:
1958 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1959 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1960 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1961 case X86::CMOVE16rr: case X86::CMOVE16rm:
1962 case X86::CMOVE32rr: case X86::CMOVE32rm:
1963 case X86::CMOVE64rr: case X86::CMOVE64rm:
1964 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1965 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1966 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1967 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1968 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1969 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1970 case X86::CMOVP16rr: case X86::CMOVP16rm:
1971 case X86::CMOVP32rr: case X86::CMOVP32rm:
1972 case X86::CMOVP64rr: case X86::CMOVP64rm:
1974 // Anything else: assume conservatively.
1975 default: return false;
1982 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1983 /// is suitable for doing the {load; increment or decrement; store} to modify
1985 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1986 SDValue StoredVal, SelectionDAG *CurDAG,
1987 LoadSDNode* &LoadNode, SDValue &InputChain) {
1989 // is the value stored the result of a DEC or INC?
1990 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1992 // is the stored value result 0 of the load?
1993 if (StoredVal.getResNo() != 0) return false;
1995 // are there other uses of the loaded value than the inc or dec?
1996 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1998 // is the store non-extending and non-indexed?
1999 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
2002 SDValue Load = StoredVal->getOperand(0);
2003 // Is the stored value a non-extending and non-indexed load?
2004 if (!ISD::isNormalLoad(Load.getNode())) return false;
2006 // Return LoadNode by reference.
2007 LoadNode = cast<LoadSDNode>(Load);
2008 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
2009 EVT LdVT = LoadNode->getMemoryVT();
2010 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
2014 // Is store the only read of the loaded value?
2015 if (!Load.hasOneUse())
2018 // Is the address of the store the same as the load?
2019 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
2020 LoadNode->getOffset() != StoreNode->getOffset())
2023 // Check if the chain is produced by the load or is a TokenFactor with
2024 // the load output chain as an operand. Return InputChain by reference.
2025 SDValue Chain = StoreNode->getChain();
2027 bool ChainCheck = false;
2028 if (Chain == Load.getValue(1)) {
2030 InputChain = LoadNode->getChain();
2031 } else if (Chain.getOpcode() == ISD::TokenFactor) {
2032 SmallVector<SDValue, 4> ChainOps;
2033 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
2034 SDValue Op = Chain.getOperand(i);
2035 if (Op == Load.getValue(1)) {
2040 // Make sure using Op as part of the chain would not cause a cycle here.
2041 // In theory, we could check whether the chain node is a predecessor of
2042 // the load. But that can be very expensive. Instead visit the uses and
2043 // make sure they all have smaller node id than the load.
2044 int LoadId = LoadNode->getNodeId();
2045 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
2046 UE = UI->use_end(); UI != UE; ++UI) {
2047 if (UI.getUse().getResNo() != 0)
2049 if (UI->getNodeId() > LoadId)
2053 ChainOps.push_back(Op);
2057 // Make a new TokenFactor with all the other input chains except
2059 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
2060 MVT::Other, ChainOps);
2068 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2069 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2070 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2071 if (Opc == X86ISD::DEC) {
2072 if (LdVT == MVT::i64) return X86::DEC64m;
2073 if (LdVT == MVT::i32) return X86::DEC32m;
2074 if (LdVT == MVT::i16) return X86::DEC16m;
2075 if (LdVT == MVT::i8) return X86::DEC8m;
2077 assert(Opc == X86ISD::INC && "unrecognized opcode");
2078 if (LdVT == MVT::i64) return X86::INC64m;
2079 if (LdVT == MVT::i32) return X86::INC32m;
2080 if (LdVT == MVT::i16) return X86::INC16m;
2081 if (LdVT == MVT::i8) return X86::INC8m;
2083 llvm_unreachable("unrecognized size for LdVT");
2086 /// SelectGather - Customized ISel for GATHER operations.
2088 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2089 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2090 SDValue Chain = Node->getOperand(0);
2091 SDValue VSrc = Node->getOperand(2);
2092 SDValue Base = Node->getOperand(3);
2093 SDValue VIdx = Node->getOperand(4);
2094 SDValue VMask = Node->getOperand(5);
2095 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2099 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2104 // Memory Operands: Base, Scale, Index, Disp, Segment
2105 SDValue Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
2106 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2107 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue(), DL), VIdx,
2108 Disp, Segment, VMask, Chain};
2109 SDNode *ResNode = CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2110 // Node has 2 outputs: VDst and MVT::Other.
2111 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2112 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2114 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2115 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2119 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2120 MVT NVT = Node->getSimpleValueType(0);
2122 unsigned Opcode = Node->getOpcode();
2125 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2127 if (Node->isMachineOpcode()) {
2128 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2129 Node->setNodeId(-1);
2130 return nullptr; // Already selected.
2135 case ISD::INTRINSIC_W_CHAIN: {
2136 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2139 case Intrinsic::x86_avx2_gather_d_pd:
2140 case Intrinsic::x86_avx2_gather_d_pd_256:
2141 case Intrinsic::x86_avx2_gather_q_pd:
2142 case Intrinsic::x86_avx2_gather_q_pd_256:
2143 case Intrinsic::x86_avx2_gather_d_ps:
2144 case Intrinsic::x86_avx2_gather_d_ps_256:
2145 case Intrinsic::x86_avx2_gather_q_ps:
2146 case Intrinsic::x86_avx2_gather_q_ps_256:
2147 case Intrinsic::x86_avx2_gather_d_q:
2148 case Intrinsic::x86_avx2_gather_d_q_256:
2149 case Intrinsic::x86_avx2_gather_q_q:
2150 case Intrinsic::x86_avx2_gather_q_q_256:
2151 case Intrinsic::x86_avx2_gather_d_d:
2152 case Intrinsic::x86_avx2_gather_d_d_256:
2153 case Intrinsic::x86_avx2_gather_q_d:
2154 case Intrinsic::x86_avx2_gather_q_d_256: {
2155 if (!Subtarget->hasAVX2())
2159 default: llvm_unreachable("Impossible intrinsic");
2160 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2161 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2162 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2163 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2164 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2165 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2166 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2167 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2168 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2169 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2170 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2171 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2172 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2173 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2174 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2175 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2177 SDNode *RetVal = SelectGather(Node, Opc);
2179 // We already called ReplaceUses inside SelectGather.
2186 case X86ISD::GlobalBaseReg:
2187 return getGlobalBaseReg();
2189 case X86ISD::SHRUNKBLEND: {
2190 // SHRUNKBLEND selects like a regular VSELECT.
2191 SDValue VSelect = CurDAG->getNode(
2192 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
2193 Node->getOperand(1), Node->getOperand(2));
2194 ReplaceUses(SDValue(Node, 0), VSelect);
2195 SelectCode(VSelect.getNode());
2196 // We already called ReplaceUses.
2200 case ISD::ATOMIC_LOAD_XOR:
2201 case ISD::ATOMIC_LOAD_AND:
2202 case ISD::ATOMIC_LOAD_OR:
2203 case ISD::ATOMIC_LOAD_ADD: {
2204 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2212 // For operations of the form (x << C1) op C2, check if we can use a smaller
2213 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2214 SDValue N0 = Node->getOperand(0);
2215 SDValue N1 = Node->getOperand(1);
2217 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2220 // i8 is unshrinkable, i16 should be promoted to i32.
2221 if (NVT != MVT::i32 && NVT != MVT::i64)
2224 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2225 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2226 if (!Cst || !ShlCst)
2229 int64_t Val = Cst->getSExtValue();
2230 uint64_t ShlVal = ShlCst->getZExtValue();
2232 // Make sure that we don't change the operation by removing bits.
2233 // This only matters for OR and XOR, AND is unaffected.
2234 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2235 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2238 unsigned ShlOp, AddOp, Op;
2241 // Check the minimum bitwidth for the new constant.
2242 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2243 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2244 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2245 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2247 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2250 // Bail if there is no smaller encoding.
2254 switch (NVT.SimpleTy) {
2255 default: llvm_unreachable("Unsupported VT!");
2257 assert(CstVT == MVT::i8);
2258 ShlOp = X86::SHL32ri;
2259 AddOp = X86::ADD32rr;
2262 default: llvm_unreachable("Impossible opcode");
2263 case ISD::AND: Op = X86::AND32ri8; break;
2264 case ISD::OR: Op = X86::OR32ri8; break;
2265 case ISD::XOR: Op = X86::XOR32ri8; break;
2269 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2270 ShlOp = X86::SHL64ri;
2271 AddOp = X86::ADD64rr;
2274 default: llvm_unreachable("Impossible opcode");
2275 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2276 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2277 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2282 // Emit the smaller op and the shift.
2283 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, dl, CstVT);
2284 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2286 return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),
2288 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2289 getI8Imm(ShlVal, dl));
2292 case X86ISD::SMUL8: {
2293 SDValue N0 = Node->getOperand(0);
2294 SDValue N1 = Node->getOperand(1);
2296 Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
2298 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
2299 N0, SDValue()).getValue(1);
2301 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
2302 SDValue Ops[] = {N1, InFlag};
2303 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2305 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2306 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2310 case X86ISD::UMUL: {
2311 SDValue N0 = Node->getOperand(0);
2312 SDValue N1 = Node->getOperand(1);
2315 switch (NVT.SimpleTy) {
2316 default: llvm_unreachable("Unsupported VT!");
2317 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2318 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2319 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2320 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2323 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2324 N0, SDValue()).getValue(1);
2326 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2327 SDValue Ops[] = {N1, InFlag};
2328 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2330 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2331 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2332 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2336 case ISD::SMUL_LOHI:
2337 case ISD::UMUL_LOHI: {
2338 SDValue N0 = Node->getOperand(0);
2339 SDValue N1 = Node->getOperand(1);
2341 bool isSigned = Opcode == ISD::SMUL_LOHI;
2342 bool hasBMI2 = Subtarget->hasBMI2();
2344 switch (NVT.SimpleTy) {
2345 default: llvm_unreachable("Unsupported VT!");
2346 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2347 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2348 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2349 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2350 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2351 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2354 switch (NVT.SimpleTy) {
2355 default: llvm_unreachable("Unsupported VT!");
2356 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2357 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2358 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2359 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2363 unsigned SrcReg, LoReg, HiReg;
2365 default: llvm_unreachable("Unknown MUL opcode!");
2368 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2372 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2376 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2380 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2383 SrcReg = X86::EDX; LoReg = HiReg = 0;
2386 SrcReg = X86::RDX; LoReg = HiReg = 0;
2390 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2391 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2392 // Multiply is commmutative.
2394 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2399 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2400 N0, SDValue()).getValue(1);
2401 SDValue ResHi, ResLo;
2405 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2407 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2408 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2409 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2410 ResHi = SDValue(CNode, 0);
2411 ResLo = SDValue(CNode, 1);
2412 Chain = SDValue(CNode, 2);
2413 InFlag = SDValue(CNode, 3);
2415 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2416 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2417 Chain = SDValue(CNode, 0);
2418 InFlag = SDValue(CNode, 1);
2421 // Update the chain.
2422 ReplaceUses(N1.getValue(1), Chain);
2424 SDValue Ops[] = { N1, InFlag };
2425 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2426 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2427 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2428 ResHi = SDValue(CNode, 0);
2429 ResLo = SDValue(CNode, 1);
2430 InFlag = SDValue(CNode, 2);
2432 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2433 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2434 InFlag = SDValue(CNode, 0);
2438 // Prevent use of AH in a REX instruction by referencing AX instead.
2439 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2440 !SDValue(Node, 1).use_empty()) {
2441 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2442 X86::AX, MVT::i16, InFlag);
2443 InFlag = Result.getValue(2);
2444 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2446 if (!SDValue(Node, 0).use_empty())
2447 ReplaceUses(SDValue(Node, 1),
2448 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2450 // Shift AX down 8 bits.
2451 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2453 CurDAG->getTargetConstant(8, dl, MVT::i8)),
2455 // Then truncate it down to i8.
2456 ReplaceUses(SDValue(Node, 1),
2457 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2459 // Copy the low half of the result, if it is needed.
2460 if (!SDValue(Node, 0).use_empty()) {
2461 if (!ResLo.getNode()) {
2462 assert(LoReg && "Register for low half is not defined!");
2463 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2465 InFlag = ResLo.getValue(2);
2467 ReplaceUses(SDValue(Node, 0), ResLo);
2468 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2470 // Copy the high half of the result, if it is needed.
2471 if (!SDValue(Node, 1).use_empty()) {
2472 if (!ResHi.getNode()) {
2473 assert(HiReg && "Register for high half is not defined!");
2474 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2476 InFlag = ResHi.getValue(2);
2478 ReplaceUses(SDValue(Node, 1), ResHi);
2479 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2487 case X86ISD::SDIVREM8_SEXT_HREG:
2488 case X86ISD::UDIVREM8_ZEXT_HREG: {
2489 SDValue N0 = Node->getOperand(0);
2490 SDValue N1 = Node->getOperand(1);
2492 bool isSigned = (Opcode == ISD::SDIVREM ||
2493 Opcode == X86ISD::SDIVREM8_SEXT_HREG);
2495 switch (NVT.SimpleTy) {
2496 default: llvm_unreachable("Unsupported VT!");
2497 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2498 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2499 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2500 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2503 switch (NVT.SimpleTy) {
2504 default: llvm_unreachable("Unsupported VT!");
2505 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2506 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2507 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2508 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2512 unsigned LoReg, HiReg, ClrReg;
2513 unsigned SExtOpcode;
2514 switch (NVT.SimpleTy) {
2515 default: llvm_unreachable("Unsupported VT!");
2517 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2518 SExtOpcode = X86::CBW;
2521 LoReg = X86::AX; HiReg = X86::DX;
2523 SExtOpcode = X86::CWD;
2526 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2527 SExtOpcode = X86::CDQ;
2530 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2531 SExtOpcode = X86::CQO;
2535 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2536 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2537 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2540 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2541 // Special case for div8, just use a move with zero extension to AX to
2542 // clear the upper 8 bits (AH).
2543 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2544 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2545 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2547 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2548 MVT::Other, Ops), 0);
2549 Chain = Move.getValue(1);
2550 ReplaceUses(N0.getValue(1), Chain);
2553 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2554 Chain = CurDAG->getEntryNode();
2556 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2557 InFlag = Chain.getValue(1);
2560 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2561 LoReg, N0, SDValue()).getValue(1);
2562 if (isSigned && !signBitIsZero) {
2563 // Sign extend the low part into the high part.
2565 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2567 // Zero out the high part, effectively zero extending the input.
2568 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2569 switch (NVT.SimpleTy) {
2572 SDValue(CurDAG->getMachineNode(
2573 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2574 CurDAG->getTargetConstant(X86::sub_16bit, dl,
2582 SDValue(CurDAG->getMachineNode(
2583 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2584 CurDAG->getTargetConstant(0, dl, MVT::i64), ClrNode,
2585 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2590 llvm_unreachable("Unexpected division source");
2593 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2594 ClrNode, InFlag).getValue(1);
2599 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2602 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2603 InFlag = SDValue(CNode, 1);
2604 // Update the chain.
2605 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2608 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2611 // Prevent use of AH in a REX instruction by explicitly copying it to
2612 // an ABCD_L register.
2614 // The current assumption of the register allocator is that isel
2615 // won't generate explicit references to the GR8_ABCD_H registers. If
2616 // the allocator and/or the backend get enhanced to be more robust in
2617 // that regard, this can be, and should be, removed.
2618 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
2619 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
2620 unsigned AHExtOpcode =
2621 isSigned ? X86::MOVSX32_NOREXrr8 : X86::MOVZX32_NOREXrr8;
2623 SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,
2624 MVT::Glue, AHCopy, InFlag);
2625 SDValue Result(RNode, 0);
2626 InFlag = SDValue(RNode, 1);
2628 if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
2629 Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
2630 if (Node->getValueType(1) == MVT::i64) {
2631 // It's not possible to directly movsx AH to a 64bit register, because
2632 // the latter needs the REX prefix, but the former can't have it.
2633 assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
2634 "Unexpected i64 sext of h-register");
2636 SDValue(CurDAG->getMachineNode(
2637 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2638 CurDAG->getTargetConstant(0, dl, MVT::i64), Result,
2639 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2645 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
2647 ReplaceUses(SDValue(Node, 1), Result);
2648 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2650 // Copy the division (low) result, if it is needed.
2651 if (!SDValue(Node, 0).use_empty()) {
2652 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2653 LoReg, NVT, InFlag);
2654 InFlag = Result.getValue(2);
2655 ReplaceUses(SDValue(Node, 0), Result);
2656 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2658 // Copy the remainder (high) result, if it is needed.
2659 if (!SDValue(Node, 1).use_empty()) {
2660 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2661 HiReg, NVT, InFlag);
2662 InFlag = Result.getValue(2);
2663 ReplaceUses(SDValue(Node, 1), Result);
2664 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2671 // Sometimes a SUB is used to perform comparison.
2672 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2673 // This node is not a CMP.
2675 SDValue N0 = Node->getOperand(0);
2676 SDValue N1 = Node->getOperand(1);
2678 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2679 HasNoSignedComparisonUses(Node))
2680 N0 = N0.getOperand(0);
2682 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2683 // use a smaller encoding.
2684 // Look past the truncate if CMP is the only use of it.
2685 if ((N0.getNode()->getOpcode() == ISD::AND ||
2686 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2687 N0.getNode()->hasOneUse() &&
2688 N0.getValueType() != MVT::i8 &&
2689 X86::isZeroNode(N1)) {
2690 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2693 // For example, convert "testl %eax, $8" to "testb %al, $8"
2694 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2695 (!(C->getZExtValue() & 0x80) ||
2696 HasNoSignedComparisonUses(Node))) {
2697 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, MVT::i8);
2698 SDValue Reg = N0.getNode()->getOperand(0);
2700 // On x86-32, only the ABCD registers have 8-bit subregisters.
2701 if (!Subtarget->is64Bit()) {
2702 const TargetRegisterClass *TRC;
2703 switch (N0.getSimpleValueType().SimpleTy) {
2704 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2705 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2706 default: llvm_unreachable("Unsupported TEST operand type!");
2708 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2709 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2710 Reg.getValueType(), Reg, RC), 0);
2713 // Extract the l-register.
2714 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2718 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2720 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2721 // one, do not call ReplaceAllUsesWith.
2722 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2723 SDValue(NewNode, 0));
2727 // For example, "testl %eax, $2048" to "testb %ah, $8".
2728 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2729 (!(C->getZExtValue() & 0x8000) ||
2730 HasNoSignedComparisonUses(Node))) {
2731 // Shift the immediate right by 8 bits.
2732 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2734 SDValue Reg = N0.getNode()->getOperand(0);
2736 // Put the value in an ABCD register.
2737 const TargetRegisterClass *TRC;
2738 switch (N0.getSimpleValueType().SimpleTy) {
2739 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2740 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2741 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2742 default: llvm_unreachable("Unsupported TEST operand type!");
2744 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2745 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2746 Reg.getValueType(), Reg, RC), 0);
2748 // Extract the h-register.
2749 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2752 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2753 // target GR8_NOREX registers, so make sure the register class is
2755 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2756 MVT::i32, Subreg, ShiftedImm);
2757 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2758 // one, do not call ReplaceAllUsesWith.
2759 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2760 SDValue(NewNode, 0));
2764 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2765 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2766 N0.getValueType() != MVT::i16 &&
2767 (!(C->getZExtValue() & 0x8000) ||
2768 HasNoSignedComparisonUses(Node))) {
2769 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2771 SDValue Reg = N0.getNode()->getOperand(0);
2773 // Extract the 16-bit subregister.
2774 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2778 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2780 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2781 // one, do not call ReplaceAllUsesWith.
2782 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2783 SDValue(NewNode, 0));
2787 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2788 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2789 N0.getValueType() == MVT::i64 &&
2790 (!(C->getZExtValue() & 0x80000000) ||
2791 HasNoSignedComparisonUses(Node))) {
2792 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2794 SDValue Reg = N0.getNode()->getOperand(0);
2796 // Extract the 32-bit subregister.
2797 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2801 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2803 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2804 // one, do not call ReplaceAllUsesWith.
2805 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2806 SDValue(NewNode, 0));
2813 // Change a chain of {load; incr or dec; store} of the same value into
2814 // a simple increment or decrement through memory of that value, if the
2815 // uses of the modified value and its address are suitable.
2816 // The DEC64m tablegen pattern is currently not able to match the case where
2817 // the EFLAGS on the original DEC are used. (This also applies to
2818 // {INC,DEC}X{64,32,16,8}.)
2819 // We'll need to improve tablegen to allow flags to be transferred from a
2820 // node in the pattern to the result node. probably with a new keyword
2821 // for example, we have this
2822 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2823 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2824 // (implicit EFLAGS)]>;
2825 // but maybe need something like this
2826 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2827 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2828 // (transferrable EFLAGS)]>;
2830 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2831 SDValue StoredVal = StoreNode->getOperand(1);
2832 unsigned Opc = StoredVal->getOpcode();
2834 LoadSDNode *LoadNode = nullptr;
2836 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2837 LoadNode, InputChain))
2840 SDValue Base, Scale, Index, Disp, Segment;
2841 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2842 Base, Scale, Index, Disp, Segment))
2845 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2846 MemOp[0] = StoreNode->getMemOperand();
2847 MemOp[1] = LoadNode->getMemOperand();
2848 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2849 EVT LdVT = LoadNode->getMemoryVT();
2850 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2851 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2853 MVT::i32, MVT::Other, Ops);
2854 Result->setMemRefs(MemOp, MemOp + 2);
2856 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2857 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2863 SDNode *ResNode = SelectCode(Node);
2865 DEBUG(dbgs() << "=> ";
2866 if (ResNode == nullptr || ResNode == Node)
2869 ResNode->dump(CurDAG);
2875 bool X86DAGToDAGISel::
2876 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
2877 std::vector<SDValue> &OutOps) {
2878 SDValue Op0, Op1, Op2, Op3, Op4;
2879 switch (ConstraintID) {
2881 llvm_unreachable("Unexpected asm memory constraint");
2882 case InlineAsm::Constraint_i:
2883 // FIXME: It seems strange that 'i' is needed here since it's supposed to
2884 // be an immediate and not a memory constraint.
2886 case InlineAsm::Constraint_o: // offsetable ??
2887 case InlineAsm::Constraint_v: // not offsetable ??
2888 case InlineAsm::Constraint_m: // memory
2889 case InlineAsm::Constraint_X:
2890 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2895 OutOps.push_back(Op0);
2896 OutOps.push_back(Op1);
2897 OutOps.push_back(Op2);
2898 OutOps.push_back(Op3);
2899 OutOps.push_back(Op4);
2903 /// createX86ISelDag - This pass converts a legalized DAG into a
2904 /// X86-specific DAG, ready for instruction scheduling.
2906 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2907 CodeGenOpt::Level OptLevel) {
2908 return new X86DAGToDAGISel(TM, OptLevel);