1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "x86-isel"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
77 JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != nullptr || CP != nullptr || ES != nullptr ||
82 JT != -1 || BlockAddr != nullptr;
85 bool hasBaseOrIndexReg() const {
86 return BaseType == FrameIndexBase ||
87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
90 /// isRIPRelative - Return true if this addressing mode is already RIP
92 bool isRIPRelative() const {
93 if (BaseType != RegBase) return false;
94 if (RegisterSDNode *RegNode =
95 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
96 return RegNode->getReg() == X86::RIP;
100 void setBaseReg(SDValue Reg) {
105 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
107 dbgs() << "X86ISelAddressMode " << this << '\n';
108 dbgs() << "Base_Reg ";
109 if (Base_Reg.getNode())
110 Base_Reg.getNode()->dump();
113 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
114 << " Scale" << Scale << '\n'
116 if (IndexReg.getNode())
117 IndexReg.getNode()->dump();
120 dbgs() << " Disp " << Disp << '\n'
137 dbgs() << " JT" << JT << " Align" << Align << '\n';
144 //===--------------------------------------------------------------------===//
145 /// ISel - X86 specific code to select X86 machine instructions for
146 /// SelectionDAG operations.
148 class X86DAGToDAGISel final : public SelectionDAGISel {
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel), OptForSize(false) {}
161 const char *getPassName() const override {
162 return "X86 DAG->DAG Instruction Selection";
165 bool runOnMachineFunction(MachineFunction &MF) override {
166 // Reset the subtarget each time through.
167 Subtarget = &MF.getSubtarget<X86Subtarget>();
168 SelectionDAGISel::runOnMachineFunction(MF);
172 void EmitFunctionEntryCode() override;
174 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
176 void PreprocessISelDAG() override;
178 inline bool immSext8(SDNode *N) const {
179 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
182 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
183 // sign extended field.
184 inline bool i64immSExt32(SDNode *N) const {
185 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
186 return (int64_t)v == (int32_t)v;
189 // Include the pieces autogenerated from the target description.
190 #include "X86GenDAGISel.inc"
193 SDNode *Select(SDNode *N) override;
194 SDNode *SelectGather(SDNode *N, unsigned Opc);
195 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
197 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
198 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
204 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
208 bool SelectLEAAddr(SDValue N, SDValue &Base,
209 SDValue &Scale, SDValue &Index, SDValue &Disp,
211 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
212 SDValue &Scale, SDValue &Index, SDValue &Disp,
214 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
215 SDValue &Scale, SDValue &Index, SDValue &Disp,
217 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
218 SDValue &Base, SDValue &Scale,
219 SDValue &Index, SDValue &Disp,
221 SDValue &NodeWithChain);
223 bool TryFoldLoad(SDNode *P, SDValue N,
224 SDValue &Base, SDValue &Scale,
225 SDValue &Index, SDValue &Disp,
228 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
229 /// inline asm expressions.
230 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
231 unsigned ConstraintID,
232 std::vector<SDValue> &OutOps) override;
234 void EmitSpecialCodeForMain();
236 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
237 SDValue &Scale, SDValue &Index,
238 SDValue &Disp, SDValue &Segment) {
239 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
240 ? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
243 Scale = getI8Imm(AM.Scale);
245 // These are 32-bit even in 64-bit mode since RIP relative offset
248 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
252 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
253 AM.Align, AM.Disp, AM.SymbolFlags);
255 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
256 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
257 } else if (AM.JT != -1) {
258 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
259 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
260 } else if (AM.BlockAddr)
261 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
264 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
266 if (AM.Segment.getNode())
267 Segment = AM.Segment;
269 Segment = CurDAG->getRegister(0, MVT::i32);
272 /// getI8Imm - Return a target constant with the specified value, of type
274 inline SDValue getI8Imm(unsigned Imm) {
275 return CurDAG->getTargetConstant(Imm, MVT::i8);
278 /// getI32Imm - Return a target constant with the specified value, of type
280 inline SDValue getI32Imm(unsigned Imm) {
281 return CurDAG->getTargetConstant(Imm, MVT::i32);
284 /// getGlobalBaseReg - Return an SDNode that returns the value of
285 /// the global base register. Output instructions required to
286 /// initialize the global base register, if necessary.
288 SDNode *getGlobalBaseReg();
290 /// getTargetMachine - Return a reference to the TargetMachine, casted
291 /// to the target-specific type.
292 const X86TargetMachine &getTargetMachine() const {
293 return static_cast<const X86TargetMachine &>(TM);
296 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
297 /// to the target-specific type.
298 const X86InstrInfo *getInstrInfo() const {
299 return Subtarget->getInstrInfo();
302 /// \brief Address-mode matching performs shift-of-and to and-of-shift
303 /// reassociation in order to expose more scaled addressing
305 bool ComplexPatternFuncMutatesDAG() const override {
313 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
314 if (OptLevel == CodeGenOpt::None) return false;
319 if (N.getOpcode() != ISD::LOAD)
322 // If N is a load, do additional profitability checks.
324 switch (U->getOpcode()) {
337 SDValue Op1 = U->getOperand(1);
339 // If the other operand is a 8-bit immediate we should fold the immediate
340 // instead. This reduces code size.
342 // movl 4(%esp), %eax
346 // addl 4(%esp), %eax
347 // The former is 2 bytes shorter. In case where the increment is 1, then
348 // the saving can be 4 bytes (by using incl %eax).
349 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
350 if (Imm->getAPIntValue().isSignedIntN(8))
353 // If the other operand is a TLS address, we should fold it instead.
356 // leal i@NTPOFF(%eax), %eax
358 // movl $i@NTPOFF, %eax
360 // if the block also has an access to a second TLS address this will save
362 // FIXME: This is probably also true for non-TLS addresses.
363 if (Op1.getOpcode() == X86ISD::Wrapper) {
364 SDValue Val = Op1.getOperand(0);
365 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
375 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
376 /// load's chain operand and move load below the call's chain operand.
377 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
378 SDValue Call, SDValue OrigChain) {
379 SmallVector<SDValue, 8> Ops;
380 SDValue Chain = OrigChain.getOperand(0);
381 if (Chain.getNode() == Load.getNode())
382 Ops.push_back(Load.getOperand(0));
384 assert(Chain.getOpcode() == ISD::TokenFactor &&
385 "Unexpected chain operand");
386 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
387 if (Chain.getOperand(i).getNode() == Load.getNode())
388 Ops.push_back(Load.getOperand(0));
390 Ops.push_back(Chain.getOperand(i));
392 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
394 Ops.push_back(NewChain);
396 Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end());
397 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
398 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
399 Load.getOperand(1), Load.getOperand(2));
402 Ops.push_back(SDValue(Load.getNode(), 1));
403 Ops.append(Call->op_begin() + 1, Call->op_end());
404 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
407 /// isCalleeLoad - Return true if call address is a load and it can be
408 /// moved below CALLSEQ_START and the chains leading up to the call.
409 /// Return the CALLSEQ_START by reference as a second output.
410 /// In the case of a tail call, there isn't a callseq node between the call
411 /// chain and the load.
412 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
413 // The transformation is somewhat dangerous if the call's chain was glued to
414 // the call. After MoveBelowOrigChain the load is moved between the call and
415 // the chain, this can create a cycle if the load is not folded. So it is
416 // *really* important that we are sure the load will be folded.
417 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
419 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
422 LD->getAddressingMode() != ISD::UNINDEXED ||
423 LD->getExtensionType() != ISD::NON_EXTLOAD)
426 // Now let's find the callseq_start.
427 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
428 if (!Chain.hasOneUse())
430 Chain = Chain.getOperand(0);
433 if (!Chain.getNumOperands())
435 // Since we are not checking for AA here, conservatively abort if the chain
436 // writes to memory. It's not safe to move the callee (a load) across a store.
437 if (isa<MemSDNode>(Chain.getNode()) &&
438 cast<MemSDNode>(Chain.getNode())->writeMem())
440 if (Chain.getOperand(0).getNode() == Callee.getNode())
442 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
443 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
444 Callee.getValue(1).hasOneUse())
449 void X86DAGToDAGISel::PreprocessISelDAG() {
450 // OptForSize is used in pattern predicates that isel is matching.
451 OptForSize = MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
453 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
454 E = CurDAG->allnodes_end(); I != E; ) {
455 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
457 if (OptLevel != CodeGenOpt::None &&
458 // Only does this when target favors doesn't favor register indirect
460 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
461 (N->getOpcode() == X86ISD::TC_RETURN &&
462 // Only does this if load can be folded into TC_RETURN.
463 (Subtarget->is64Bit() ||
464 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
465 /// Also try moving call address load from outside callseq_start to just
466 /// before the call to allow it to be folded.
484 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
485 SDValue Chain = N->getOperand(0);
486 SDValue Load = N->getOperand(1);
487 if (!isCalleeLoad(Load, Chain, HasCallSeq))
489 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
494 // Lower fpround and fpextend nodes that target the FP stack to be store and
495 // load to the stack. This is a gross hack. We would like to simply mark
496 // these as being illegal, but when we do that, legalize produces these when
497 // it expands calls, then expands these in the same legalize pass. We would
498 // like dag combine to be able to hack on these between the call expansion
499 // and the node legalization. As such this pass basically does "really
500 // late" legalization of these inline with the X86 isel pass.
501 // FIXME: This should only happen when not compiled with -O0.
502 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
505 MVT SrcVT = N->getOperand(0).getSimpleValueType();
506 MVT DstVT = N->getSimpleValueType(0);
508 // If any of the sources are vectors, no fp stack involved.
509 if (SrcVT.isVector() || DstVT.isVector())
512 // If the source and destination are SSE registers, then this is a legal
513 // conversion that should not be lowered.
514 const X86TargetLowering *X86Lowering =
515 static_cast<const X86TargetLowering *>(TLI);
516 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
517 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
518 if (SrcIsSSE && DstIsSSE)
521 if (!SrcIsSSE && !DstIsSSE) {
522 // If this is an FPStack extension, it is a noop.
523 if (N->getOpcode() == ISD::FP_EXTEND)
525 // If this is a value-preserving FPStack truncation, it is a noop.
526 if (N->getConstantOperandVal(1))
530 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
531 // FPStack has extload and truncstore. SSE can fold direct loads into other
532 // operations. Based on this, decide what we want to do.
534 if (N->getOpcode() == ISD::FP_ROUND)
535 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
537 MemVT = SrcIsSSE ? SrcVT : DstVT;
539 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
542 // FIXME: optimize the case where the src/dest is a load or store?
543 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
545 MemTmp, MachinePointerInfo(), MemVT,
547 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
548 MachinePointerInfo(),
549 MemVT, false, false, false, 0);
551 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
552 // extload we created. This will cause general havok on the dag because
553 // anything below the conversion could be folded into other existing nodes.
554 // To avoid invalidating 'I', back it up to the convert node.
556 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
558 // Now that we did that, the node is dead. Increment the iterator to the
559 // next node to process, then delete N.
561 CurDAG->DeleteNode(N);
566 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
567 /// the main function.
568 void X86DAGToDAGISel::EmitSpecialCodeForMain() {
569 if (Subtarget->isTargetCygMing()) {
570 TargetLowering::ArgListTy Args;
572 TargetLowering::CallLoweringInfo CLI(*CurDAG);
573 CLI.setChain(CurDAG->getRoot())
574 .setCallee(CallingConv::C, Type::getVoidTy(*CurDAG->getContext()),
575 CurDAG->getExternalSymbol("__main", TLI->getPointerTy()),
577 const TargetLowering &TLI = CurDAG->getTargetLoweringInfo();
578 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
579 CurDAG->setRoot(Result.second);
583 void X86DAGToDAGISel::EmitFunctionEntryCode() {
584 // If this is main, emit special code for main.
585 if (const Function *Fn = MF->getFunction())
586 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
587 EmitSpecialCodeForMain();
590 static bool isDispSafeForFrameIndex(int64_t Val) {
591 // On 64-bit platforms, we can run into an issue where a frame index
592 // includes a displacement that, when added to the explicit displacement,
593 // will overflow the displacement field. Assuming that the frame index
594 // displacement fits into a 31-bit integer (which is only slightly more
595 // aggressive than the current fundamental assumption that it fits into
596 // a 32-bit integer), a 31-bit disp should always be safe.
597 return isInt<31>(Val);
600 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
601 X86ISelAddressMode &AM) {
602 int64_t Val = AM.Disp + Offset;
603 CodeModel::Model M = TM.getCodeModel();
604 if (Subtarget->is64Bit()) {
605 if (!X86::isOffsetSuitableForCodeModel(Val, M,
606 AM.hasSymbolicDisplacement()))
608 // In addition to the checks required for a register base, check that
609 // we do not try to use an unsafe Disp with a frame index.
610 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
611 !isDispSafeForFrameIndex(Val))
619 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
620 SDValue Address = N->getOperand(1);
622 // load gs:0 -> GS segment register.
623 // load fs:0 -> FS segment register.
625 // This optimization is valid because the GNU TLS model defines that
626 // gs:0 (or fs:0 on X86-64) contains its own address.
627 // For more information see http://people.redhat.com/drepper/tls.pdf
628 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
629 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
630 Subtarget->isTargetLinux())
631 switch (N->getPointerInfo().getAddrSpace()) {
633 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
636 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
643 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
644 /// into an addressing mode. These wrap things that will resolve down into a
645 /// symbol reference. If no match is possible, this returns true, otherwise it
647 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
648 // If the addressing mode already has a symbol as the displacement, we can
649 // never match another symbol.
650 if (AM.hasSymbolicDisplacement())
653 SDValue N0 = N.getOperand(0);
654 CodeModel::Model M = TM.getCodeModel();
656 // Handle X86-64 rip-relative addresses. We check this before checking direct
657 // folding because RIP is preferable to non-RIP accesses.
658 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
659 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
660 // they cannot be folded into immediate fields.
661 // FIXME: This can be improved for kernel and other models?
662 (M == CodeModel::Small || M == CodeModel::Kernel)) {
663 // Base and index reg must be 0 in order to use %rip as base.
664 if (AM.hasBaseOrIndexReg())
666 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
667 X86ISelAddressMode Backup = AM;
668 AM.GV = G->getGlobal();
669 AM.SymbolFlags = G->getTargetFlags();
670 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
674 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
675 X86ISelAddressMode Backup = AM;
676 AM.CP = CP->getConstVal();
677 AM.Align = CP->getAlignment();
678 AM.SymbolFlags = CP->getTargetFlags();
679 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
683 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
684 AM.ES = S->getSymbol();
685 AM.SymbolFlags = S->getTargetFlags();
686 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
687 AM.JT = J->getIndex();
688 AM.SymbolFlags = J->getTargetFlags();
689 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
690 X86ISelAddressMode Backup = AM;
691 AM.BlockAddr = BA->getBlockAddress();
692 AM.SymbolFlags = BA->getTargetFlags();
693 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
698 llvm_unreachable("Unhandled symbol reference node.");
700 if (N.getOpcode() == X86ISD::WrapperRIP)
701 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
705 // Handle the case when globals fit in our immediate field: This is true for
706 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
707 // mode, this only applies to a non-RIP-relative computation.
708 if (!Subtarget->is64Bit() ||
709 M == CodeModel::Small || M == CodeModel::Kernel) {
710 assert(N.getOpcode() != X86ISD::WrapperRIP &&
711 "RIP-relative addressing already handled");
712 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
713 AM.GV = G->getGlobal();
714 AM.Disp += G->getOffset();
715 AM.SymbolFlags = G->getTargetFlags();
716 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
717 AM.CP = CP->getConstVal();
718 AM.Align = CP->getAlignment();
719 AM.Disp += CP->getOffset();
720 AM.SymbolFlags = CP->getTargetFlags();
721 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
722 AM.ES = S->getSymbol();
723 AM.SymbolFlags = S->getTargetFlags();
724 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
725 AM.JT = J->getIndex();
726 AM.SymbolFlags = J->getTargetFlags();
727 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
728 AM.BlockAddr = BA->getBlockAddress();
729 AM.Disp += BA->getOffset();
730 AM.SymbolFlags = BA->getTargetFlags();
732 llvm_unreachable("Unhandled symbol reference node.");
739 /// MatchAddress - Add the specified node to the specified addressing mode,
740 /// returning true if it cannot be done. This just pattern matches for the
742 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
743 if (MatchAddressRecursively(N, AM, 0))
746 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
747 // a smaller encoding and avoids a scaled-index.
749 AM.BaseType == X86ISelAddressMode::RegBase &&
750 AM.Base_Reg.getNode() == nullptr) {
751 AM.Base_Reg = AM.IndexReg;
755 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
756 // because it has a smaller encoding.
757 // TODO: Which other code models can use this?
758 if (TM.getCodeModel() == CodeModel::Small &&
759 Subtarget->is64Bit() &&
761 AM.BaseType == X86ISelAddressMode::RegBase &&
762 AM.Base_Reg.getNode() == nullptr &&
763 AM.IndexReg.getNode() == nullptr &&
764 AM.SymbolFlags == X86II::MO_NO_FLAG &&
765 AM.hasSymbolicDisplacement())
766 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
771 // Insert a node into the DAG at least before the Pos node's position. This
772 // will reposition the node as needed, and will assign it a node ID that is <=
773 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
774 // IDs! The selection DAG must no longer depend on their uniqueness when this
776 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
777 if (N.getNode()->getNodeId() == -1 ||
778 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
779 DAG.RepositionNode(Pos.getNode(), N.getNode());
780 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
784 // Transform "(X >> (8-C1)) & (0xff << C1)" to "((X >> 8) & 0xff) << C1" if
785 // safe. This allows us to convert the shift and and into an h-register
786 // extract and a scaled index. Returns false if the simplification is
788 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
790 SDValue Shift, SDValue X,
791 X86ISelAddressMode &AM) {
792 if (Shift.getOpcode() != ISD::SRL ||
793 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
797 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
798 if (ScaleLog <= 0 || ScaleLog >= 4 ||
799 Mask != (0xffu << ScaleLog))
802 MVT VT = N.getSimpleValueType();
804 SDValue Eight = DAG.getConstant(8, MVT::i8);
805 SDValue NewMask = DAG.getConstant(0xff, VT);
806 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
807 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
808 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
809 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
811 // Insert the new nodes into the topological ordering. We must do this in
812 // a valid topological ordering as nothing is going to go back and re-sort
813 // these nodes. We continually insert before 'N' in sequence as this is
814 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
815 // hierarchy left to express.
816 InsertDAGNode(DAG, N, Eight);
817 InsertDAGNode(DAG, N, Srl);
818 InsertDAGNode(DAG, N, NewMask);
819 InsertDAGNode(DAG, N, And);
820 InsertDAGNode(DAG, N, ShlCount);
821 InsertDAGNode(DAG, N, Shl);
822 DAG.ReplaceAllUsesWith(N, Shl);
824 AM.Scale = (1 << ScaleLog);
828 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
829 // allows us to fold the shift into this addressing mode. Returns false if the
830 // transform succeeded.
831 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
833 SDValue Shift, SDValue X,
834 X86ISelAddressMode &AM) {
835 if (Shift.getOpcode() != ISD::SHL ||
836 !isa<ConstantSDNode>(Shift.getOperand(1)))
839 // Not likely to be profitable if either the AND or SHIFT node has more
840 // than one use (unless all uses are for address computation). Besides,
841 // isel mechanism requires their node ids to be reused.
842 if (!N.hasOneUse() || !Shift.hasOneUse())
845 // Verify that the shift amount is something we can fold.
846 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
847 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
850 MVT VT = N.getSimpleValueType();
852 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
853 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
854 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
856 // Insert the new nodes into the topological ordering. We must do this in
857 // a valid topological ordering as nothing is going to go back and re-sort
858 // these nodes. We continually insert before 'N' in sequence as this is
859 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
860 // hierarchy left to express.
861 InsertDAGNode(DAG, N, NewMask);
862 InsertDAGNode(DAG, N, NewAnd);
863 InsertDAGNode(DAG, N, NewShift);
864 DAG.ReplaceAllUsesWith(N, NewShift);
866 AM.Scale = 1 << ShiftAmt;
867 AM.IndexReg = NewAnd;
871 // Implement some heroics to detect shifts of masked values where the mask can
872 // be replaced by extending the shift and undoing that in the addressing mode
873 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
874 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
875 // the addressing mode. This results in code such as:
877 // int f(short *y, int *lookup_table) {
879 // return *y + lookup_table[*y >> 11];
883 // movzwl (%rdi), %eax
886 // addl (%rsi,%rcx,4), %eax
889 // movzwl (%rdi), %eax
893 // addl (%rsi,%rcx), %eax
895 // Note that this function assumes the mask is provided as a mask *after* the
896 // value is shifted. The input chain may or may not match that, but computing
897 // such a mask is trivial.
898 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
900 SDValue Shift, SDValue X,
901 X86ISelAddressMode &AM) {
902 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
903 !isa<ConstantSDNode>(Shift.getOperand(1)))
906 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
907 unsigned MaskLZ = countLeadingZeros(Mask);
908 unsigned MaskTZ = countTrailingZeros(Mask);
910 // The amount of shift we're trying to fit into the addressing mode is taken
911 // from the trailing zeros of the mask.
912 unsigned AMShiftAmt = MaskTZ;
914 // There is nothing we can do here unless the mask is removing some bits.
915 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
916 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
918 // We also need to ensure that mask is a continuous run of bits.
919 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
921 // Scale the leading zero count down based on the actual size of the value.
922 // Also scale it down based on the size of the shift.
923 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
925 // The final check is to ensure that any masked out high bits of X are
926 // already known to be zero. Otherwise, the mask has a semantic impact
927 // other than masking out a couple of low bits. Unfortunately, because of
928 // the mask, zero extensions will be removed from operands in some cases.
929 // This code works extra hard to look through extensions because we can
930 // replace them with zero extensions cheaply if necessary.
931 bool ReplacingAnyExtend = false;
932 if (X.getOpcode() == ISD::ANY_EXTEND) {
933 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
934 X.getOperand(0).getSimpleValueType().getSizeInBits();
935 // Assume that we'll replace the any-extend with a zero-extend, and
936 // narrow the search to the extended value.
938 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
939 ReplacingAnyExtend = true;
941 APInt MaskedHighBits =
942 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
943 APInt KnownZero, KnownOne;
944 DAG.computeKnownBits(X, KnownZero, KnownOne);
945 if (MaskedHighBits != KnownZero) return true;
947 // We've identified a pattern that can be transformed into a single shift
948 // and an addressing mode. Make it so.
949 MVT VT = N.getSimpleValueType();
950 if (ReplacingAnyExtend) {
951 assert(X.getValueType() != VT);
952 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
953 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
954 InsertDAGNode(DAG, N, NewX);
958 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
959 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
960 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
961 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
963 // Insert the new nodes into the topological ordering. We must do this in
964 // a valid topological ordering as nothing is going to go back and re-sort
965 // these nodes. We continually insert before 'N' in sequence as this is
966 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
967 // hierarchy left to express.
968 InsertDAGNode(DAG, N, NewSRLAmt);
969 InsertDAGNode(DAG, N, NewSRL);
970 InsertDAGNode(DAG, N, NewSHLAmt);
971 InsertDAGNode(DAG, N, NewSHL);
972 DAG.ReplaceAllUsesWith(N, NewSHL);
974 AM.Scale = 1 << AMShiftAmt;
975 AM.IndexReg = NewSRL;
979 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
983 dbgs() << "MatchAddress: ";
988 return MatchAddressBase(N, AM);
990 // If this is already a %rip relative address, we can only merge immediates
991 // into it. Instead of handling this in every case, we handle it here.
992 // RIP relative addressing: %rip + 32-bit displacement!
993 if (AM.isRIPRelative()) {
994 // FIXME: JumpTable and ExternalSymbol address currently don't like
995 // displacements. It isn't very important, but this should be fixed for
997 if (!AM.ES && AM.JT != -1) return true;
999 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
1000 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
1005 switch (N.getOpcode()) {
1007 case ISD::FRAME_ALLOC_RECOVER: {
1008 if (!AM.hasSymbolicDisplacement())
1009 if (const auto *ESNode = dyn_cast<ExternalSymbolSDNode>(N.getOperand(0)))
1010 if (ESNode->getOpcode() == ISD::TargetExternalSymbol) {
1011 AM.ES = ESNode->getSymbol();
1016 case ISD::Constant: {
1017 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1018 if (!FoldOffsetIntoAddress(Val, AM))
1023 case X86ISD::Wrapper:
1024 case X86ISD::WrapperRIP:
1025 if (!MatchWrapper(N, AM))
1030 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1034 case ISD::FrameIndex:
1035 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1036 AM.Base_Reg.getNode() == nullptr &&
1037 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1038 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1039 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1045 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1049 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1050 unsigned Val = CN->getZExtValue();
1051 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1052 // that the base operand remains free for further matching. If
1053 // the base doesn't end up getting used, a post-processing step
1054 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1055 if (Val == 1 || Val == 2 || Val == 3) {
1056 AM.Scale = 1 << Val;
1057 SDValue ShVal = N.getNode()->getOperand(0);
1059 // Okay, we know that we have a scale by now. However, if the scaled
1060 // value is an add of something and a constant, we can fold the
1061 // constant into the disp field here.
1062 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1063 AM.IndexReg = ShVal.getNode()->getOperand(0);
1064 ConstantSDNode *AddVal =
1065 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1066 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1067 if (!FoldOffsetIntoAddress(Disp, AM))
1071 AM.IndexReg = ShVal;
1078 // Scale must not be used already.
1079 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1081 SDValue And = N.getOperand(0);
1082 if (And.getOpcode() != ISD::AND) break;
1083 SDValue X = And.getOperand(0);
1085 // We only handle up to 64-bit values here as those are what matter for
1086 // addressing mode optimizations.
1087 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1089 // The mask used for the transform is expected to be post-shift, but we
1090 // found the shift first so just apply the shift to the mask before passing
1092 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1093 !isa<ConstantSDNode>(And.getOperand(1)))
1095 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1097 // Try to fold the mask and shift into the scale, and return false if we
1099 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1104 case ISD::SMUL_LOHI:
1105 case ISD::UMUL_LOHI:
1106 // A mul_lohi where we need the low part can be folded as a plain multiply.
1107 if (N.getResNo() != 0) break;
1110 case X86ISD::MUL_IMM:
1111 // X*[3,5,9] -> X+X*[2,4,8]
1112 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1113 AM.Base_Reg.getNode() == nullptr &&
1114 AM.IndexReg.getNode() == nullptr) {
1116 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1117 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1118 CN->getZExtValue() == 9) {
1119 AM.Scale = unsigned(CN->getZExtValue())-1;
1121 SDValue MulVal = N.getNode()->getOperand(0);
1124 // Okay, we know that we have a scale by now. However, if the scaled
1125 // value is an add of something and a constant, we can fold the
1126 // constant into the disp field here.
1127 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1128 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1129 Reg = MulVal.getNode()->getOperand(0);
1130 ConstantSDNode *AddVal =
1131 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1132 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1133 if (FoldOffsetIntoAddress(Disp, AM))
1134 Reg = N.getNode()->getOperand(0);
1136 Reg = N.getNode()->getOperand(0);
1139 AM.IndexReg = AM.Base_Reg = Reg;
1146 // Given A-B, if A can be completely folded into the address and
1147 // the index field with the index field unused, use -B as the index.
1148 // This is a win if a has multiple parts that can be folded into
1149 // the address. Also, this saves a mov if the base register has
1150 // other uses, since it avoids a two-address sub instruction, however
1151 // it costs an additional mov if the index register has other uses.
1153 // Add an artificial use to this node so that we can keep track of
1154 // it if it gets CSE'd with a different node.
1155 HandleSDNode Handle(N);
1157 // Test if the LHS of the sub can be folded.
1158 X86ISelAddressMode Backup = AM;
1159 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1163 // Test if the index field is free for use.
1164 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1170 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1171 // If the RHS involves a register with multiple uses, this
1172 // transformation incurs an extra mov, due to the neg instruction
1173 // clobbering its operand.
1174 if (!RHS.getNode()->hasOneUse() ||
1175 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1176 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1177 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1178 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1179 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1181 // If the base is a register with multiple uses, this
1182 // transformation may save a mov.
1183 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1184 AM.Base_Reg.getNode() &&
1185 !AM.Base_Reg.getNode()->hasOneUse()) ||
1186 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1188 // If the folded LHS was interesting, this transformation saves
1189 // address arithmetic.
1190 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1191 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1192 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1194 // If it doesn't look like it may be an overall win, don't do it.
1200 // Ok, the transformation is legal and appears profitable. Go for it.
1201 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1202 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1206 // Insert the new nodes into the topological ordering.
1207 InsertDAGNode(*CurDAG, N, Zero);
1208 InsertDAGNode(*CurDAG, N, Neg);
1213 // Add an artificial use to this node so that we can keep track of
1214 // it if it gets CSE'd with a different node.
1215 HandleSDNode Handle(N);
1217 X86ISelAddressMode Backup = AM;
1218 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1219 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1223 // Try again after commuting the operands.
1224 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1225 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1229 // If we couldn't fold both operands into the address at the same time,
1230 // see if we can just put each operand into a register and fold at least
1232 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1233 !AM.Base_Reg.getNode() &&
1234 !AM.IndexReg.getNode()) {
1235 N = Handle.getValue();
1236 AM.Base_Reg = N.getOperand(0);
1237 AM.IndexReg = N.getOperand(1);
1241 N = Handle.getValue();
1246 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1247 if (CurDAG->isBaseWithConstantOffset(N)) {
1248 X86ISelAddressMode Backup = AM;
1249 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1251 // Start with the LHS as an addr mode.
1252 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1253 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1260 // Perform some heroic transforms on an and of a constant-count shift
1261 // with a constant to enable use of the scaled offset field.
1263 // Scale must not be used already.
1264 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1266 SDValue Shift = N.getOperand(0);
1267 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1268 SDValue X = Shift.getOperand(0);
1270 // We only handle up to 64-bit values here as those are what matter for
1271 // addressing mode optimizations.
1272 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1274 if (!isa<ConstantSDNode>(N.getOperand(1)))
1276 uint64_t Mask = N.getConstantOperandVal(1);
1278 // Try to fold the mask and shift into an extract and scale.
1279 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1282 // Try to fold the mask and shift directly into the scale.
1283 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1286 // Try to swap the mask and shift to place shifts which can be done as
1287 // a scale on the outside of the mask.
1288 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1294 return MatchAddressBase(N, AM);
1297 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1298 /// specified addressing mode without any further recursion.
1299 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1300 // Is the base register already occupied?
1301 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1302 // If so, check to see if the scale index register is set.
1303 if (!AM.IndexReg.getNode()) {
1309 // Otherwise, we cannot select it.
1313 // Default, generate it as a register.
1314 AM.BaseType = X86ISelAddressMode::RegBase;
1319 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1320 /// It returns the operands which make up the maximal addressing mode it can
1321 /// match by reference.
1323 /// Parent is the parent node of the addr operand that is being matched. It
1324 /// is always a load, store, atomic node, or null. It is only null when
1325 /// checking memory operands for inline asm nodes.
1326 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1327 SDValue &Scale, SDValue &Index,
1328 SDValue &Disp, SDValue &Segment) {
1329 X86ISelAddressMode AM;
1332 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1333 // that are not a MemSDNode, and thus don't have proper addrspace info.
1334 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1335 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1336 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1337 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1338 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1339 unsigned AddrSpace =
1340 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1341 // AddrSpace 256 -> GS, 257 -> FS.
1342 if (AddrSpace == 256)
1343 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1344 if (AddrSpace == 257)
1345 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1348 if (MatchAddress(N, AM))
1351 MVT VT = N.getSimpleValueType();
1352 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1353 if (!AM.Base_Reg.getNode())
1354 AM.Base_Reg = CurDAG->getRegister(0, VT);
1357 if (!AM.IndexReg.getNode())
1358 AM.IndexReg = CurDAG->getRegister(0, VT);
1360 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1364 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1365 /// match a load whose top elements are either undef or zeros. The load flavor
1366 /// is derived from the type of N, which is either v4f32 or v2f64.
1369 /// PatternChainNode: this is the matched node that has a chain input and
1371 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1372 SDValue N, SDValue &Base,
1373 SDValue &Scale, SDValue &Index,
1374 SDValue &Disp, SDValue &Segment,
1375 SDValue &PatternNodeWithChain) {
1376 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1377 PatternNodeWithChain = N.getOperand(0);
1378 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1379 PatternNodeWithChain.hasOneUse() &&
1380 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1381 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1382 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1383 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1389 // Also handle the case where we explicitly require zeros in the top
1390 // elements. This is a vector shuffle from the zero vector.
1391 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1392 // Check to see if the top elements are all zeros (or bitcast of zeros).
1393 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1394 N.getOperand(0).getNode()->hasOneUse() &&
1395 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1396 N.getOperand(0).getOperand(0).hasOneUse() &&
1397 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1398 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1399 // Okay, this is a zero extending load. Fold it.
1400 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1401 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1403 PatternNodeWithChain = SDValue(LD, 0);
1410 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1411 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1412 uint64_t ImmVal = CN->getZExtValue();
1413 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1416 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
1420 // In static codegen with small code model, we can get the address of a label
1421 // into a register with 'movl'. TableGen has already made sure we're looking
1422 // at a label of some kind.
1423 assert(N->getOpcode() == X86ISD::Wrapper &&
1424 "Unexpected node type for MOV32ri64");
1425 N = N.getOperand(0);
1427 if (N->getOpcode() != ISD::TargetConstantPool &&
1428 N->getOpcode() != ISD::TargetJumpTable &&
1429 N->getOpcode() != ISD::TargetGlobalAddress &&
1430 N->getOpcode() != ISD::TargetExternalSymbol &&
1431 N->getOpcode() != ISD::TargetBlockAddress)
1435 return TM.getCodeModel() == CodeModel::Small;
1438 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1439 SDValue &Scale, SDValue &Index,
1440 SDValue &Disp, SDValue &Segment) {
1441 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1445 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1446 if (RN && RN->getReg() == 0)
1447 Base = CurDAG->getRegister(0, MVT::i64);
1448 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
1449 // Base could already be %rip, particularly in the x32 ABI.
1450 Base = SDValue(CurDAG->getMachineNode(
1451 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1452 CurDAG->getTargetConstant(0, MVT::i64),
1454 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1458 RN = dyn_cast<RegisterSDNode>(Index);
1459 if (RN && RN->getReg() == 0)
1460 Index = CurDAG->getRegister(0, MVT::i64);
1462 assert(Index.getValueType() == MVT::i32 &&
1463 "Expect to be extending 32-bit registers for use in LEA");
1464 Index = SDValue(CurDAG->getMachineNode(
1465 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1466 CurDAG->getTargetConstant(0, MVT::i64),
1468 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1475 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1476 /// mode it matches can be cost effectively emitted as an LEA instruction.
1477 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1478 SDValue &Base, SDValue &Scale,
1479 SDValue &Index, SDValue &Disp,
1481 X86ISelAddressMode AM;
1483 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1485 SDValue Copy = AM.Segment;
1486 SDValue T = CurDAG->getRegister(0, MVT::i32);
1488 if (MatchAddress(N, AM))
1490 assert (T == AM.Segment);
1493 MVT VT = N.getSimpleValueType();
1494 unsigned Complexity = 0;
1495 if (AM.BaseType == X86ISelAddressMode::RegBase)
1496 if (AM.Base_Reg.getNode())
1499 AM.Base_Reg = CurDAG->getRegister(0, VT);
1500 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1503 if (AM.IndexReg.getNode())
1506 AM.IndexReg = CurDAG->getRegister(0, VT);
1508 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1513 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1514 // to a LEA. This is determined with some expermentation but is by no means
1515 // optimal (especially for code size consideration). LEA is nice because of
1516 // its three-address nature. Tweak the cost function again when we can run
1517 // convertToThreeAddress() at register allocation time.
1518 if (AM.hasSymbolicDisplacement()) {
1519 // For X86-64, we should always use lea to materialize RIP relative
1521 if (Subtarget->is64Bit())
1527 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1530 // If it isn't worth using an LEA, reject it.
1531 if (Complexity <= 2)
1534 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1538 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1539 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1540 SDValue &Scale, SDValue &Index,
1541 SDValue &Disp, SDValue &Segment) {
1542 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1543 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1545 X86ISelAddressMode AM;
1546 AM.GV = GA->getGlobal();
1547 AM.Disp += GA->getOffset();
1548 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1549 AM.SymbolFlags = GA->getTargetFlags();
1551 if (N.getValueType() == MVT::i32) {
1553 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1555 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1558 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1563 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1564 SDValue &Base, SDValue &Scale,
1565 SDValue &Index, SDValue &Disp,
1567 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1568 !IsProfitableToFold(N, P, P) ||
1569 !IsLegalToFold(N, P, P, OptLevel))
1572 return SelectAddr(N.getNode(),
1573 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1576 /// getGlobalBaseReg - Return an SDNode that returns the value of
1577 /// the global base register. Output instructions required to
1578 /// initialize the global base register, if necessary.
1580 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1581 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1582 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode();
1585 /// Atomic opcode table
1613 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1624 X86::LOCK_ADD64mi32,
1637 X86::LOCK_SUB64mi32,
1689 X86::LOCK_AND64mi32,
1702 X86::LOCK_XOR64mi32,
1707 // Return the target constant operand for atomic-load-op and do simple
1708 // translations, such as from atomic-load-add to lock-sub. The return value is
1709 // one of the following 3 cases:
1710 // + target-constant, the operand could be supported as a target constant.
1711 // + empty, the operand is not needed any more with the new op selected.
1712 // + non-empty, otherwise.
1713 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1715 enum AtomicOpc &Op, MVT NVT,
1717 const X86Subtarget *Subtarget) {
1718 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1719 int64_t CNVal = CN->getSExtValue();
1720 // Quit if not 32-bit imm.
1721 if ((int32_t)CNVal != CNVal)
1723 // Quit if INT32_MIN: it would be negated as it is negative and overflow,
1724 // producing an immediate that does not fit in the 32 bits available for
1725 // an immediate operand to sub. However, it still fits in 32 bits for the
1726 // add (since it is not negated) so we can return target-constant.
1727 if (CNVal == INT32_MIN)
1728 return CurDAG->getTargetConstant(CNVal, NVT);
1729 // For atomic-load-add, we could do some optimizations.
1731 // Translate to INC/DEC if ADD by 1 or -1.
1732 if (((CNVal == 1) || (CNVal == -1)) && !Subtarget->slowIncDec()) {
1733 Op = (CNVal == 1) ? INC : DEC;
1734 // No more constant operand after being translated into INC/DEC.
1737 // Translate to SUB if ADD by negative value.
1743 return CurDAG->getTargetConstant(CNVal, NVT);
1746 // If the value operand is single-used, try to optimize it.
1747 if (Op == ADD && Val.hasOneUse()) {
1748 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1749 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1751 return Val.getOperand(1);
1753 // A special case for i16, which needs truncating as, in most cases, it's
1754 // promoted to i32. We will translate
1755 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1756 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1757 Val.getOperand(0).getOpcode() == ISD::SUB &&
1758 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1760 Val = Val.getOperand(0);
1761 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1769 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1770 if (Node->hasAnyUseOfValue(0))
1775 // Optimize common patterns for __sync_or_and_fetch and similar arith
1776 // operations where the result is not used. This allows us to use the "lock"
1777 // version of the arithmetic instruction.
1778 SDValue Chain = Node->getOperand(0);
1779 SDValue Ptr = Node->getOperand(1);
1780 SDValue Val = Node->getOperand(2);
1781 SDValue Base, Scale, Index, Disp, Segment;
1782 if (!SelectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
1785 // Which index into the table.
1787 switch (Node->getOpcode()) {
1790 case ISD::ATOMIC_LOAD_OR:
1793 case ISD::ATOMIC_LOAD_AND:
1796 case ISD::ATOMIC_LOAD_XOR:
1799 case ISD::ATOMIC_LOAD_ADD:
1804 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val, Subtarget);
1805 bool isUnOp = !Val.getNode();
1806 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1809 switch (NVT.SimpleTy) {
1810 default: return nullptr;
1813 Opc = AtomicOpcTbl[Op][ConstantI8];
1815 Opc = AtomicOpcTbl[Op][I8];
1819 if (immSext8(Val.getNode()))
1820 Opc = AtomicOpcTbl[Op][SextConstantI16];
1822 Opc = AtomicOpcTbl[Op][ConstantI16];
1824 Opc = AtomicOpcTbl[Op][I16];
1828 if (immSext8(Val.getNode()))
1829 Opc = AtomicOpcTbl[Op][SextConstantI32];
1831 Opc = AtomicOpcTbl[Op][ConstantI32];
1833 Opc = AtomicOpcTbl[Op][I32];
1837 if (immSext8(Val.getNode()))
1838 Opc = AtomicOpcTbl[Op][SextConstantI64];
1839 else if (i64immSExt32(Val.getNode()))
1840 Opc = AtomicOpcTbl[Op][ConstantI64];
1842 llvm_unreachable("True 64 bits constant in SelectAtomicLoadArith");
1844 Opc = AtomicOpcTbl[Op][I64];
1848 assert(Opc != 0 && "Invalid arith lock transform!");
1850 // Building the new node.
1853 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Chain };
1854 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1856 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Val, Chain };
1857 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1860 // Copying the MachineMemOperand.
1861 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1862 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1863 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1865 // We need to have two outputs as that is what the original instruction had.
1866 // So we add a dummy, undefined output. This is safe as we checked first
1867 // that no-one uses our output anyway.
1868 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1870 SDValue RetVals[] = { Undef, Ret };
1871 return CurDAG->getMergeValues(RetVals, dl).getNode();
1874 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1875 /// any uses which require the SF or OF bits to be accurate.
1876 static bool HasNoSignedComparisonUses(SDNode *N) {
1877 // Examine each user of the node.
1878 for (SDNode::use_iterator UI = N->use_begin(),
1879 UE = N->use_end(); UI != UE; ++UI) {
1880 // Only examine CopyToReg uses.
1881 if (UI->getOpcode() != ISD::CopyToReg)
1883 // Only examine CopyToReg uses that copy to EFLAGS.
1884 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1887 // Examine each user of the CopyToReg use.
1888 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1889 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1890 // Only examine the Flag result.
1891 if (FlagUI.getUse().getResNo() != 1) continue;
1892 // Anything unusual: assume conservatively.
1893 if (!FlagUI->isMachineOpcode()) return false;
1894 // Examine the opcode of the user.
1895 switch (FlagUI->getMachineOpcode()) {
1896 // These comparisons don't treat the most significant bit specially.
1897 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1898 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1899 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1900 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1901 case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
1902 case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
1903 case X86::CMOVA16rr: case X86::CMOVA16rm:
1904 case X86::CMOVA32rr: case X86::CMOVA32rm:
1905 case X86::CMOVA64rr: case X86::CMOVA64rm:
1906 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1907 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1908 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1909 case X86::CMOVB16rr: case X86::CMOVB16rm:
1910 case X86::CMOVB32rr: case X86::CMOVB32rm:
1911 case X86::CMOVB64rr: case X86::CMOVB64rm:
1912 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1913 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1914 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1915 case X86::CMOVE16rr: case X86::CMOVE16rm:
1916 case X86::CMOVE32rr: case X86::CMOVE32rm:
1917 case X86::CMOVE64rr: case X86::CMOVE64rm:
1918 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1919 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1920 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1921 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1922 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1923 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1924 case X86::CMOVP16rr: case X86::CMOVP16rm:
1925 case X86::CMOVP32rr: case X86::CMOVP32rm:
1926 case X86::CMOVP64rr: case X86::CMOVP64rm:
1928 // Anything else: assume conservatively.
1929 default: return false;
1936 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1937 /// is suitable for doing the {load; increment or decrement; store} to modify
1939 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1940 SDValue StoredVal, SelectionDAG *CurDAG,
1941 LoadSDNode* &LoadNode, SDValue &InputChain) {
1943 // is the value stored the result of a DEC or INC?
1944 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1946 // is the stored value result 0 of the load?
1947 if (StoredVal.getResNo() != 0) return false;
1949 // are there other uses of the loaded value than the inc or dec?
1950 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1952 // is the store non-extending and non-indexed?
1953 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1956 SDValue Load = StoredVal->getOperand(0);
1957 // Is the stored value a non-extending and non-indexed load?
1958 if (!ISD::isNormalLoad(Load.getNode())) return false;
1960 // Return LoadNode by reference.
1961 LoadNode = cast<LoadSDNode>(Load);
1962 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1963 EVT LdVT = LoadNode->getMemoryVT();
1964 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1968 // Is store the only read of the loaded value?
1969 if (!Load.hasOneUse())
1972 // Is the address of the store the same as the load?
1973 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1974 LoadNode->getOffset() != StoreNode->getOffset())
1977 // Check if the chain is produced by the load or is a TokenFactor with
1978 // the load output chain as an operand. Return InputChain by reference.
1979 SDValue Chain = StoreNode->getChain();
1981 bool ChainCheck = false;
1982 if (Chain == Load.getValue(1)) {
1984 InputChain = LoadNode->getChain();
1985 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1986 SmallVector<SDValue, 4> ChainOps;
1987 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1988 SDValue Op = Chain.getOperand(i);
1989 if (Op == Load.getValue(1)) {
1994 // Make sure using Op as part of the chain would not cause a cycle here.
1995 // In theory, we could check whether the chain node is a predecessor of
1996 // the load. But that can be very expensive. Instead visit the uses and
1997 // make sure they all have smaller node id than the load.
1998 int LoadId = LoadNode->getNodeId();
1999 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
2000 UE = UI->use_end(); UI != UE; ++UI) {
2001 if (UI.getUse().getResNo() != 0)
2003 if (UI->getNodeId() > LoadId)
2007 ChainOps.push_back(Op);
2011 // Make a new TokenFactor with all the other input chains except
2013 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
2014 MVT::Other, ChainOps);
2022 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2023 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2024 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2025 if (Opc == X86ISD::DEC) {
2026 if (LdVT == MVT::i64) return X86::DEC64m;
2027 if (LdVT == MVT::i32) return X86::DEC32m;
2028 if (LdVT == MVT::i16) return X86::DEC16m;
2029 if (LdVT == MVT::i8) return X86::DEC8m;
2031 assert(Opc == X86ISD::INC && "unrecognized opcode");
2032 if (LdVT == MVT::i64) return X86::INC64m;
2033 if (LdVT == MVT::i32) return X86::INC32m;
2034 if (LdVT == MVT::i16) return X86::INC16m;
2035 if (LdVT == MVT::i8) return X86::INC8m;
2037 llvm_unreachable("unrecognized size for LdVT");
2040 /// SelectGather - Customized ISel for GATHER operations.
2042 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2043 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2044 SDValue Chain = Node->getOperand(0);
2045 SDValue VSrc = Node->getOperand(2);
2046 SDValue Base = Node->getOperand(3);
2047 SDValue VIdx = Node->getOperand(4);
2048 SDValue VMask = Node->getOperand(5);
2049 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2053 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2056 // Memory Operands: Base, Scale, Index, Disp, Segment
2057 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
2058 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2059 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
2060 Disp, Segment, VMask, Chain};
2061 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
2062 // Node has 2 outputs: VDst and MVT::Other.
2063 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2064 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2066 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2067 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2071 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2072 MVT NVT = Node->getSimpleValueType(0);
2074 unsigned Opcode = Node->getOpcode();
2077 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2079 if (Node->isMachineOpcode()) {
2080 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2081 Node->setNodeId(-1);
2082 return nullptr; // Already selected.
2087 case ISD::INTRINSIC_W_CHAIN: {
2088 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2091 case Intrinsic::x86_avx2_gather_d_pd:
2092 case Intrinsic::x86_avx2_gather_d_pd_256:
2093 case Intrinsic::x86_avx2_gather_q_pd:
2094 case Intrinsic::x86_avx2_gather_q_pd_256:
2095 case Intrinsic::x86_avx2_gather_d_ps:
2096 case Intrinsic::x86_avx2_gather_d_ps_256:
2097 case Intrinsic::x86_avx2_gather_q_ps:
2098 case Intrinsic::x86_avx2_gather_q_ps_256:
2099 case Intrinsic::x86_avx2_gather_d_q:
2100 case Intrinsic::x86_avx2_gather_d_q_256:
2101 case Intrinsic::x86_avx2_gather_q_q:
2102 case Intrinsic::x86_avx2_gather_q_q_256:
2103 case Intrinsic::x86_avx2_gather_d_d:
2104 case Intrinsic::x86_avx2_gather_d_d_256:
2105 case Intrinsic::x86_avx2_gather_q_d:
2106 case Intrinsic::x86_avx2_gather_q_d_256: {
2107 if (!Subtarget->hasAVX2())
2111 default: llvm_unreachable("Impossible intrinsic");
2112 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2113 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2114 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2115 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2116 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2117 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2118 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2119 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2120 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2121 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2122 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2123 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2124 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2125 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2126 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2127 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2129 SDNode *RetVal = SelectGather(Node, Opc);
2131 // We already called ReplaceUses inside SelectGather.
2138 case X86ISD::GlobalBaseReg:
2139 return getGlobalBaseReg();
2141 case X86ISD::SHRUNKBLEND: {
2142 // SHRUNKBLEND selects like a regular VSELECT.
2143 SDValue VSelect = CurDAG->getNode(
2144 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
2145 Node->getOperand(1), Node->getOperand(2));
2146 ReplaceUses(SDValue(Node, 0), VSelect);
2147 SelectCode(VSelect.getNode());
2148 // We already called ReplaceUses.
2152 case ISD::ATOMIC_LOAD_XOR:
2153 case ISD::ATOMIC_LOAD_AND:
2154 case ISD::ATOMIC_LOAD_OR:
2155 case ISD::ATOMIC_LOAD_ADD: {
2156 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2164 // For operations of the form (x << C1) op C2, check if we can use a smaller
2165 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2166 SDValue N0 = Node->getOperand(0);
2167 SDValue N1 = Node->getOperand(1);
2169 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2172 // i8 is unshrinkable, i16 should be promoted to i32.
2173 if (NVT != MVT::i32 && NVT != MVT::i64)
2176 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2177 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2178 if (!Cst || !ShlCst)
2181 int64_t Val = Cst->getSExtValue();
2182 uint64_t ShlVal = ShlCst->getZExtValue();
2184 // Make sure that we don't change the operation by removing bits.
2185 // This only matters for OR and XOR, AND is unaffected.
2186 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2187 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2193 // Check the minimum bitwidth for the new constant.
2194 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2195 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2196 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2197 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2199 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2202 // Bail if there is no smaller encoding.
2206 switch (NVT.SimpleTy) {
2207 default: llvm_unreachable("Unsupported VT!");
2209 assert(CstVT == MVT::i8);
2210 ShlOp = X86::SHL32ri;
2213 default: llvm_unreachable("Impossible opcode");
2214 case ISD::AND: Op = X86::AND32ri8; break;
2215 case ISD::OR: Op = X86::OR32ri8; break;
2216 case ISD::XOR: Op = X86::XOR32ri8; break;
2220 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2221 ShlOp = X86::SHL64ri;
2224 default: llvm_unreachable("Impossible opcode");
2225 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2226 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2227 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2232 // Emit the smaller op and the shift.
2233 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2234 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2235 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2239 case X86ISD::SMUL8: {
2240 SDValue N0 = Node->getOperand(0);
2241 SDValue N1 = Node->getOperand(1);
2243 Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
2245 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
2246 N0, SDValue()).getValue(1);
2248 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
2249 SDValue Ops[] = {N1, InFlag};
2250 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2252 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2253 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2257 case X86ISD::UMUL: {
2258 SDValue N0 = Node->getOperand(0);
2259 SDValue N1 = Node->getOperand(1);
2262 switch (NVT.SimpleTy) {
2263 default: llvm_unreachable("Unsupported VT!");
2264 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2265 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2266 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2267 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2270 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2271 N0, SDValue()).getValue(1);
2273 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2274 SDValue Ops[] = {N1, InFlag};
2275 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2277 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2278 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2279 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2283 case ISD::SMUL_LOHI:
2284 case ISD::UMUL_LOHI: {
2285 SDValue N0 = Node->getOperand(0);
2286 SDValue N1 = Node->getOperand(1);
2288 bool isSigned = Opcode == ISD::SMUL_LOHI;
2289 bool hasBMI2 = Subtarget->hasBMI2();
2291 switch (NVT.SimpleTy) {
2292 default: llvm_unreachable("Unsupported VT!");
2293 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2294 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2295 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2296 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2297 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2298 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2301 switch (NVT.SimpleTy) {
2302 default: llvm_unreachable("Unsupported VT!");
2303 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2304 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2305 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2306 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2310 unsigned SrcReg, LoReg, HiReg;
2312 default: llvm_unreachable("Unknown MUL opcode!");
2315 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2319 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2323 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2327 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2330 SrcReg = X86::EDX; LoReg = HiReg = 0;
2333 SrcReg = X86::RDX; LoReg = HiReg = 0;
2337 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2338 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2339 // Multiply is commmutative.
2341 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2346 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2347 N0, SDValue()).getValue(1);
2348 SDValue ResHi, ResLo;
2352 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2354 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2355 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2356 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2357 ResHi = SDValue(CNode, 0);
2358 ResLo = SDValue(CNode, 1);
2359 Chain = SDValue(CNode, 2);
2360 InFlag = SDValue(CNode, 3);
2362 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2363 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2364 Chain = SDValue(CNode, 0);
2365 InFlag = SDValue(CNode, 1);
2368 // Update the chain.
2369 ReplaceUses(N1.getValue(1), Chain);
2371 SDValue Ops[] = { N1, InFlag };
2372 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2373 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2374 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2375 ResHi = SDValue(CNode, 0);
2376 ResLo = SDValue(CNode, 1);
2377 InFlag = SDValue(CNode, 2);
2379 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2380 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2381 InFlag = SDValue(CNode, 0);
2385 // Prevent use of AH in a REX instruction by referencing AX instead.
2386 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2387 !SDValue(Node, 1).use_empty()) {
2388 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2389 X86::AX, MVT::i16, InFlag);
2390 InFlag = Result.getValue(2);
2391 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2393 if (!SDValue(Node, 0).use_empty())
2394 ReplaceUses(SDValue(Node, 1),
2395 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2397 // Shift AX down 8 bits.
2398 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2400 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2401 // Then truncate it down to i8.
2402 ReplaceUses(SDValue(Node, 1),
2403 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2405 // Copy the low half of the result, if it is needed.
2406 if (!SDValue(Node, 0).use_empty()) {
2407 if (!ResLo.getNode()) {
2408 assert(LoReg && "Register for low half is not defined!");
2409 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2411 InFlag = ResLo.getValue(2);
2413 ReplaceUses(SDValue(Node, 0), ResLo);
2414 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2416 // Copy the high half of the result, if it is needed.
2417 if (!SDValue(Node, 1).use_empty()) {
2418 if (!ResHi.getNode()) {
2419 assert(HiReg && "Register for high half is not defined!");
2420 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2422 InFlag = ResHi.getValue(2);
2424 ReplaceUses(SDValue(Node, 1), ResHi);
2425 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2433 case X86ISD::SDIVREM8_SEXT_HREG:
2434 case X86ISD::UDIVREM8_ZEXT_HREG: {
2435 SDValue N0 = Node->getOperand(0);
2436 SDValue N1 = Node->getOperand(1);
2438 bool isSigned = (Opcode == ISD::SDIVREM ||
2439 Opcode == X86ISD::SDIVREM8_SEXT_HREG);
2441 switch (NVT.SimpleTy) {
2442 default: llvm_unreachable("Unsupported VT!");
2443 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2444 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2445 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2446 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2449 switch (NVT.SimpleTy) {
2450 default: llvm_unreachable("Unsupported VT!");
2451 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2452 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2453 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2454 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2458 unsigned LoReg, HiReg, ClrReg;
2459 unsigned SExtOpcode;
2460 switch (NVT.SimpleTy) {
2461 default: llvm_unreachable("Unsupported VT!");
2463 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2464 SExtOpcode = X86::CBW;
2467 LoReg = X86::AX; HiReg = X86::DX;
2469 SExtOpcode = X86::CWD;
2472 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2473 SExtOpcode = X86::CDQ;
2476 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2477 SExtOpcode = X86::CQO;
2481 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2482 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2483 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2486 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2487 // Special case for div8, just use a move with zero extension to AX to
2488 // clear the upper 8 bits (AH).
2489 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2490 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2491 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2493 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2494 MVT::Other, Ops), 0);
2495 Chain = Move.getValue(1);
2496 ReplaceUses(N0.getValue(1), Chain);
2499 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2500 Chain = CurDAG->getEntryNode();
2502 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2503 InFlag = Chain.getValue(1);
2506 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2507 LoReg, N0, SDValue()).getValue(1);
2508 if (isSigned && !signBitIsZero) {
2509 // Sign extend the low part into the high part.
2511 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2513 // Zero out the high part, effectively zero extending the input.
2514 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2515 switch (NVT.SimpleTy) {
2518 SDValue(CurDAG->getMachineNode(
2519 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2520 CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
2527 SDValue(CurDAG->getMachineNode(
2528 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2529 CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
2530 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2534 llvm_unreachable("Unexpected division source");
2537 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2538 ClrNode, InFlag).getValue(1);
2543 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2546 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2547 InFlag = SDValue(CNode, 1);
2548 // Update the chain.
2549 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2552 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2555 // Prevent use of AH in a REX instruction by explicitly copying it to
2556 // an ABCD_L register.
2558 // The current assumption of the register allocator is that isel
2559 // won't generate explicit references to the GR8_ABCD_H registers. If
2560 // the allocator and/or the backend get enhanced to be more robust in
2561 // that regard, this can be, and should be, removed.
2562 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
2563 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
2564 unsigned AHExtOpcode =
2565 isSigned ? X86::MOVSX32_NOREXrr8 : X86::MOVZX32_NOREXrr8;
2567 SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,
2568 MVT::Glue, AHCopy, InFlag);
2569 SDValue Result(RNode, 0);
2570 InFlag = SDValue(RNode, 1);
2572 if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
2573 Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
2574 if (Node->getValueType(1) == MVT::i64) {
2575 // It's not possible to directly movsx AH to a 64bit register, because
2576 // the latter needs the REX prefix, but the former can't have it.
2577 assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
2578 "Unexpected i64 sext of h-register");
2580 SDValue(CurDAG->getMachineNode(
2581 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2582 CurDAG->getTargetConstant(0, MVT::i64), Result,
2583 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2588 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
2590 ReplaceUses(SDValue(Node, 1), Result);
2591 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2593 // Copy the division (low) result, if it is needed.
2594 if (!SDValue(Node, 0).use_empty()) {
2595 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2596 LoReg, NVT, InFlag);
2597 InFlag = Result.getValue(2);
2598 ReplaceUses(SDValue(Node, 0), Result);
2599 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2601 // Copy the remainder (high) result, if it is needed.
2602 if (!SDValue(Node, 1).use_empty()) {
2603 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2604 HiReg, NVT, InFlag);
2605 InFlag = Result.getValue(2);
2606 ReplaceUses(SDValue(Node, 1), Result);
2607 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2614 // Sometimes a SUB is used to perform comparison.
2615 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2616 // This node is not a CMP.
2618 SDValue N0 = Node->getOperand(0);
2619 SDValue N1 = Node->getOperand(1);
2621 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2622 HasNoSignedComparisonUses(Node))
2623 N0 = N0.getOperand(0);
2625 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2626 // use a smaller encoding.
2627 // Look past the truncate if CMP is the only use of it.
2628 if ((N0.getNode()->getOpcode() == ISD::AND ||
2629 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2630 N0.getNode()->hasOneUse() &&
2631 N0.getValueType() != MVT::i8 &&
2632 X86::isZeroNode(N1)) {
2633 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2636 // For example, convert "testl %eax, $8" to "testb %al, $8"
2637 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2638 (!(C->getZExtValue() & 0x80) ||
2639 HasNoSignedComparisonUses(Node))) {
2640 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2641 SDValue Reg = N0.getNode()->getOperand(0);
2643 // On x86-32, only the ABCD registers have 8-bit subregisters.
2644 if (!Subtarget->is64Bit()) {
2645 const TargetRegisterClass *TRC;
2646 switch (N0.getSimpleValueType().SimpleTy) {
2647 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2648 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2649 default: llvm_unreachable("Unsupported TEST operand type!");
2651 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2652 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2653 Reg.getValueType(), Reg, RC), 0);
2656 // Extract the l-register.
2657 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2661 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2663 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2664 // one, do not call ReplaceAllUsesWith.
2665 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2666 SDValue(NewNode, 0));
2670 // For example, "testl %eax, $2048" to "testb %ah, $8".
2671 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2672 (!(C->getZExtValue() & 0x8000) ||
2673 HasNoSignedComparisonUses(Node))) {
2674 // Shift the immediate right by 8 bits.
2675 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2677 SDValue Reg = N0.getNode()->getOperand(0);
2679 // Put the value in an ABCD register.
2680 const TargetRegisterClass *TRC;
2681 switch (N0.getSimpleValueType().SimpleTy) {
2682 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2683 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2684 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2685 default: llvm_unreachable("Unsupported TEST operand type!");
2687 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2688 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2689 Reg.getValueType(), Reg, RC), 0);
2691 // Extract the h-register.
2692 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2695 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2696 // target GR8_NOREX registers, so make sure the register class is
2698 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2699 MVT::i32, Subreg, ShiftedImm);
2700 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2701 // one, do not call ReplaceAllUsesWith.
2702 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2703 SDValue(NewNode, 0));
2707 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2708 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2709 N0.getValueType() != MVT::i16 &&
2710 (!(C->getZExtValue() & 0x8000) ||
2711 HasNoSignedComparisonUses(Node))) {
2712 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2713 SDValue Reg = N0.getNode()->getOperand(0);
2715 // Extract the 16-bit subregister.
2716 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2720 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2722 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2723 // one, do not call ReplaceAllUsesWith.
2724 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2725 SDValue(NewNode, 0));
2729 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2730 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2731 N0.getValueType() == MVT::i64 &&
2732 (!(C->getZExtValue() & 0x80000000) ||
2733 HasNoSignedComparisonUses(Node))) {
2734 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2735 SDValue Reg = N0.getNode()->getOperand(0);
2737 // Extract the 32-bit subregister.
2738 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2742 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2744 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2745 // one, do not call ReplaceAllUsesWith.
2746 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2747 SDValue(NewNode, 0));
2754 // Change a chain of {load; incr or dec; store} of the same value into
2755 // a simple increment or decrement through memory of that value, if the
2756 // uses of the modified value and its address are suitable.
2757 // The DEC64m tablegen pattern is currently not able to match the case where
2758 // the EFLAGS on the original DEC are used. (This also applies to
2759 // {INC,DEC}X{64,32,16,8}.)
2760 // We'll need to improve tablegen to allow flags to be transferred from a
2761 // node in the pattern to the result node. probably with a new keyword
2762 // for example, we have this
2763 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2764 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2765 // (implicit EFLAGS)]>;
2766 // but maybe need something like this
2767 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2768 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2769 // (transferrable EFLAGS)]>;
2771 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2772 SDValue StoredVal = StoreNode->getOperand(1);
2773 unsigned Opc = StoredVal->getOpcode();
2775 LoadSDNode *LoadNode = nullptr;
2777 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2778 LoadNode, InputChain))
2781 SDValue Base, Scale, Index, Disp, Segment;
2782 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2783 Base, Scale, Index, Disp, Segment))
2786 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2787 MemOp[0] = StoreNode->getMemOperand();
2788 MemOp[1] = LoadNode->getMemOperand();
2789 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2790 EVT LdVT = LoadNode->getMemoryVT();
2791 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2792 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2794 MVT::i32, MVT::Other, Ops);
2795 Result->setMemRefs(MemOp, MemOp + 2);
2797 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2798 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2804 SDNode *ResNode = SelectCode(Node);
2806 DEBUG(dbgs() << "=> ";
2807 if (ResNode == nullptr || ResNode == Node)
2810 ResNode->dump(CurDAG);
2816 bool X86DAGToDAGISel::
2817 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
2818 std::vector<SDValue> &OutOps) {
2819 SDValue Op0, Op1, Op2, Op3, Op4;
2820 switch (ConstraintID) {
2821 case InlineAsm::Constraint_o: // offsetable ??
2822 case InlineAsm::Constraint_v: // not offsetable ??
2823 default: return true;
2824 case InlineAsm::Constraint_m: // memory
2825 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2830 OutOps.push_back(Op0);
2831 OutOps.push_back(Op1);
2832 OutOps.push_back(Op2);
2833 OutOps.push_back(Op3);
2834 OutOps.push_back(Op4);
2838 /// createX86ISelDag - This pass converts a legalized DAG into a
2839 /// X86-specific DAG, ready for instruction scheduling.
2841 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2842 CodeGenOpt::Level OptLevel) {
2843 return new X86DAGToDAGISel(TM, OptLevel);