1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CFG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/Statistic.h"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
77 SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
84 bool hasBaseOrIndexReg() const {
85 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
88 /// isRIPRelative - Return true if this addressing mode is already RIP
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
103 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
105 dbgs() << "X86ISelAddressMode " << this << '\n';
106 dbgs() << "Base_Reg ";
107 if (Base_Reg.getNode() != 0)
108 Base_Reg.getNode()->dump();
111 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
112 << " Scale" << Scale << '\n'
114 if (IndexReg.getNode() != 0)
115 IndexReg.getNode()->dump();
118 dbgs() << " Disp " << Disp << '\n'
135 dbgs() << " JT" << JT << " Align" << Align << '\n';
142 //===--------------------------------------------------------------------===//
143 /// ISel - X86 specific code to select X86 machine instructions for
144 /// SelectionDAG operations.
146 class X86DAGToDAGISel : public SelectionDAGISel {
147 /// X86Lowering - This object fully describes how to lower LLVM code to an
148 /// X86-specific SelectionDAG.
149 const X86TargetLowering &X86Lowering;
151 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
152 /// make the right decision when generating code for different targets.
153 const X86Subtarget *Subtarget;
155 /// OptForSize - If true, selector should try to optimize for code size
156 /// instead of performance.
160 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
161 : SelectionDAGISel(tm, OptLevel),
162 X86Lowering(*tm.getTargetLowering()),
163 Subtarget(&tm.getSubtarget<X86Subtarget>()),
166 virtual const char *getPassName() const {
167 return "X86 DAG->DAG Instruction Selection";
170 virtual void EmitFunctionEntryCode();
172 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
174 virtual void PreprocessISelDAG();
176 inline bool immSext8(SDNode *N) const {
177 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
180 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
181 // sign extended field.
182 inline bool i64immSExt32(SDNode *N) const {
183 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
184 return (int64_t)v == (int32_t)v;
187 // Include the pieces autogenerated from the target description.
188 #include "X86GenDAGISel.inc"
191 SDNode *Select(SDNode *N);
192 SDNode *SelectGather(SDNode *N, unsigned Opc);
193 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
194 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT);
196 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
197 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
198 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
199 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
202 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
203 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
204 SDValue &Scale, SDValue &Index, SDValue &Disp,
206 bool SelectLEAAddr(SDValue N, SDValue &Base,
207 SDValue &Scale, SDValue &Index, SDValue &Disp,
209 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
210 SDValue &Scale, SDValue &Index, SDValue &Disp,
212 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
213 SDValue &Base, SDValue &Scale,
214 SDValue &Index, SDValue &Disp,
216 SDValue &NodeWithChain);
218 bool TryFoldLoad(SDNode *P, SDValue N,
219 SDValue &Base, SDValue &Scale,
220 SDValue &Index, SDValue &Disp,
223 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
224 /// inline asm expressions.
225 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
227 std::vector<SDValue> &OutOps);
229 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
231 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
232 SDValue &Scale, SDValue &Index,
233 SDValue &Disp, SDValue &Segment) {
234 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
235 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
237 Scale = getI8Imm(AM.Scale);
239 // These are 32-bit even in 64-bit mode since RIP relative offset
242 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(),
246 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
247 AM.Align, AM.Disp, AM.SymbolFlags);
249 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
250 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
251 } else if (AM.JT != -1) {
252 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
253 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
254 } else if (AM.BlockAddr)
255 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
258 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
260 if (AM.Segment.getNode())
261 Segment = AM.Segment;
263 Segment = CurDAG->getRegister(0, MVT::i32);
266 /// getI8Imm - Return a target constant with the specified value, of type
268 inline SDValue getI8Imm(unsigned Imm) {
269 return CurDAG->getTargetConstant(Imm, MVT::i8);
272 /// getI32Imm - Return a target constant with the specified value, of type
274 inline SDValue getI32Imm(unsigned Imm) {
275 return CurDAG->getTargetConstant(Imm, MVT::i32);
278 /// getGlobalBaseReg - Return an SDNode that returns the value of
279 /// the global base register. Output instructions required to
280 /// initialize the global base register, if necessary.
282 SDNode *getGlobalBaseReg();
284 /// getTargetMachine - Return a reference to the TargetMachine, casted
285 /// to the target-specific type.
286 const X86TargetMachine &getTargetMachine() {
287 return static_cast<const X86TargetMachine &>(TM);
290 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
291 /// to the target-specific type.
292 const X86InstrInfo *getInstrInfo() {
293 return getTargetMachine().getInstrInfo();
300 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
301 if (OptLevel == CodeGenOpt::None) return false;
306 if (N.getOpcode() != ISD::LOAD)
309 // If N is a load, do additional profitability checks.
311 switch (U->getOpcode()) {
324 SDValue Op1 = U->getOperand(1);
326 // If the other operand is a 8-bit immediate we should fold the immediate
327 // instead. This reduces code size.
329 // movl 4(%esp), %eax
333 // addl 4(%esp), %eax
334 // The former is 2 bytes shorter. In case where the increment is 1, then
335 // the saving can be 4 bytes (by using incl %eax).
336 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
337 if (Imm->getAPIntValue().isSignedIntN(8))
340 // If the other operand is a TLS address, we should fold it instead.
343 // leal i@NTPOFF(%eax), %eax
345 // movl $i@NTPOFF, %eax
347 // if the block also has an access to a second TLS address this will save
349 // FIXME: This is probably also true for non TLS addresses.
350 if (Op1.getOpcode() == X86ISD::Wrapper) {
351 SDValue Val = Op1.getOperand(0);
352 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
362 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
363 /// load's chain operand and move load below the call's chain operand.
364 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
365 SDValue Call, SDValue OrigChain) {
366 SmallVector<SDValue, 8> Ops;
367 SDValue Chain = OrigChain.getOperand(0);
368 if (Chain.getNode() == Load.getNode())
369 Ops.push_back(Load.getOperand(0));
371 assert(Chain.getOpcode() == ISD::TokenFactor &&
372 "Unexpected chain operand");
373 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
374 if (Chain.getOperand(i).getNode() == Load.getNode())
375 Ops.push_back(Load.getOperand(0));
377 Ops.push_back(Chain.getOperand(i));
379 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
380 MVT::Other, &Ops[0], Ops.size());
382 Ops.push_back(NewChain);
384 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
385 Ops.push_back(OrigChain.getOperand(i));
386 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
387 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
388 Load.getOperand(1), Load.getOperand(2));
390 Ops.push_back(SDValue(Load.getNode(), 1));
391 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
392 Ops.push_back(Call.getOperand(i));
393 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size());
396 /// isCalleeLoad - Return true if call address is a load and it can be
397 /// moved below CALLSEQ_START and the chains leading up to the call.
398 /// Return the CALLSEQ_START by reference as a second output.
399 /// In the case of a tail call, there isn't a callseq node between the call
400 /// chain and the load.
401 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
402 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
404 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
407 LD->getAddressingMode() != ISD::UNINDEXED ||
408 LD->getExtensionType() != ISD::NON_EXTLOAD)
411 // Now let's find the callseq_start.
412 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
413 if (!Chain.hasOneUse())
415 Chain = Chain.getOperand(0);
418 if (!Chain.getNumOperands())
420 if (Chain.getOperand(0).getNode() == Callee.getNode())
422 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
423 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
424 Callee.getValue(1).hasOneUse())
429 void X86DAGToDAGISel::PreprocessISelDAG() {
430 // OptForSize is used in pattern predicates that isel is matching.
431 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
433 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
434 E = CurDAG->allnodes_end(); I != E; ) {
435 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
437 if (OptLevel != CodeGenOpt::None &&
438 (N->getOpcode() == X86ISD::CALL ||
439 N->getOpcode() == X86ISD::TC_RETURN)) {
440 /// Also try moving call address load from outside callseq_start to just
441 /// before the call to allow it to be folded.
459 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
460 SDValue Chain = N->getOperand(0);
461 SDValue Load = N->getOperand(1);
462 if (!isCalleeLoad(Load, Chain, HasCallSeq))
464 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
469 // Lower fpround and fpextend nodes that target the FP stack to be store and
470 // load to the stack. This is a gross hack. We would like to simply mark
471 // these as being illegal, but when we do that, legalize produces these when
472 // it expands calls, then expands these in the same legalize pass. We would
473 // like dag combine to be able to hack on these between the call expansion
474 // and the node legalization. As such this pass basically does "really
475 // late" legalization of these inline with the X86 isel pass.
476 // FIXME: This should only happen when not compiled with -O0.
477 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
480 EVT SrcVT = N->getOperand(0).getValueType();
481 EVT DstVT = N->getValueType(0);
483 // If any of the sources are vectors, no fp stack involved.
484 if (SrcVT.isVector() || DstVT.isVector())
487 // If the source and destination are SSE registers, then this is a legal
488 // conversion that should not be lowered.
489 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
490 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
491 if (SrcIsSSE && DstIsSSE)
494 if (!SrcIsSSE && !DstIsSSE) {
495 // If this is an FPStack extension, it is a noop.
496 if (N->getOpcode() == ISD::FP_EXTEND)
498 // If this is a value-preserving FPStack truncation, it is a noop.
499 if (N->getConstantOperandVal(1))
503 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
504 // FPStack has extload and truncstore. SSE can fold direct loads into other
505 // operations. Based on this, decide what we want to do.
507 if (N->getOpcode() == ISD::FP_ROUND)
508 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
510 MemVT = SrcIsSSE ? SrcVT : DstVT;
512 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
513 DebugLoc dl = N->getDebugLoc();
515 // FIXME: optimize the case where the src/dest is a load or store?
516 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
518 MemTmp, MachinePointerInfo(), MemVT,
520 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
521 MachinePointerInfo(),
522 MemVT, false, false, 0);
524 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
525 // extload we created. This will cause general havok on the dag because
526 // anything below the conversion could be folded into other existing nodes.
527 // To avoid invalidating 'I', back it up to the convert node.
529 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
531 // Now that we did that, the node is dead. Increment the iterator to the
532 // next node to process, then delete N.
534 CurDAG->DeleteNode(N);
539 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
540 /// the main function.
541 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
542 MachineFrameInfo *MFI) {
543 const TargetInstrInfo *TII = TM.getInstrInfo();
544 if (Subtarget->isTargetCygMing()) {
546 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
547 BuildMI(BB, DebugLoc(),
548 TII->get(CallOp)).addExternalSymbol("__main");
552 void X86DAGToDAGISel::EmitFunctionEntryCode() {
553 // If this is main, emit special code for main.
554 if (const Function *Fn = MF->getFunction())
555 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
556 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
559 static bool isDispSafeForFrameIndex(int64_t Val) {
560 // On 64-bit platforms, we can run into an issue where a frame index
561 // includes a displacement that, when added to the explicit displacement,
562 // will overflow the displacement field. Assuming that the frame index
563 // displacement fits into a 31-bit integer (which is only slightly more
564 // aggressive than the current fundamental assumption that it fits into
565 // a 32-bit integer), a 31-bit disp should always be safe.
566 return isInt<31>(Val);
569 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
570 X86ISelAddressMode &AM) {
571 int64_t Val = AM.Disp + Offset;
572 CodeModel::Model M = TM.getCodeModel();
573 if (Subtarget->is64Bit()) {
574 if (!X86::isOffsetSuitableForCodeModel(Val, M,
575 AM.hasSymbolicDisplacement()))
577 // In addition to the checks required for a register base, check that
578 // we do not try to use an unsafe Disp with a frame index.
579 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
580 !isDispSafeForFrameIndex(Val))
588 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
589 SDValue Address = N->getOperand(1);
591 // load gs:0 -> GS segment register.
592 // load fs:0 -> FS segment register.
594 // This optimization is valid because the GNU TLS model defines that
595 // gs:0 (or fs:0 on X86-64) contains its own address.
596 // For more information see http://people.redhat.com/drepper/tls.pdf
597 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
598 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
599 Subtarget->isTargetLinux())
600 switch (N->getPointerInfo().getAddrSpace()) {
602 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
605 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
612 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
613 /// into an addressing mode. These wrap things that will resolve down into a
614 /// symbol reference. If no match is possible, this returns true, otherwise it
616 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
617 // If the addressing mode already has a symbol as the displacement, we can
618 // never match another symbol.
619 if (AM.hasSymbolicDisplacement())
622 SDValue N0 = N.getOperand(0);
623 CodeModel::Model M = TM.getCodeModel();
625 // Handle X86-64 rip-relative addresses. We check this before checking direct
626 // folding because RIP is preferable to non-RIP accesses.
627 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
628 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
629 // they cannot be folded into immediate fields.
630 // FIXME: This can be improved for kernel and other models?
631 (M == CodeModel::Small || M == CodeModel::Kernel)) {
632 // Base and index reg must be 0 in order to use %rip as base.
633 if (AM.hasBaseOrIndexReg())
635 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
636 X86ISelAddressMode Backup = AM;
637 AM.GV = G->getGlobal();
638 AM.SymbolFlags = G->getTargetFlags();
639 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
643 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
644 X86ISelAddressMode Backup = AM;
645 AM.CP = CP->getConstVal();
646 AM.Align = CP->getAlignment();
647 AM.SymbolFlags = CP->getTargetFlags();
648 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
652 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
653 AM.ES = S->getSymbol();
654 AM.SymbolFlags = S->getTargetFlags();
655 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
656 AM.JT = J->getIndex();
657 AM.SymbolFlags = J->getTargetFlags();
658 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
659 X86ISelAddressMode Backup = AM;
660 AM.BlockAddr = BA->getBlockAddress();
661 AM.SymbolFlags = BA->getTargetFlags();
662 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
667 llvm_unreachable("Unhandled symbol reference node.");
669 if (N.getOpcode() == X86ISD::WrapperRIP)
670 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
674 // Handle the case when globals fit in our immediate field: This is true for
675 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
676 // mode, this only applies to a non-RIP-relative computation.
677 if (!Subtarget->is64Bit() ||
678 M == CodeModel::Small || M == CodeModel::Kernel) {
679 assert(N.getOpcode() != X86ISD::WrapperRIP &&
680 "RIP-relative addressing already handled");
681 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
682 AM.GV = G->getGlobal();
683 AM.Disp += G->getOffset();
684 AM.SymbolFlags = G->getTargetFlags();
685 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
686 AM.CP = CP->getConstVal();
687 AM.Align = CP->getAlignment();
688 AM.Disp += CP->getOffset();
689 AM.SymbolFlags = CP->getTargetFlags();
690 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
691 AM.ES = S->getSymbol();
692 AM.SymbolFlags = S->getTargetFlags();
693 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
694 AM.JT = J->getIndex();
695 AM.SymbolFlags = J->getTargetFlags();
696 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
697 AM.BlockAddr = BA->getBlockAddress();
698 AM.Disp += BA->getOffset();
699 AM.SymbolFlags = BA->getTargetFlags();
701 llvm_unreachable("Unhandled symbol reference node.");
708 /// MatchAddress - Add the specified node to the specified addressing mode,
709 /// returning true if it cannot be done. This just pattern matches for the
711 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
712 if (MatchAddressRecursively(N, AM, 0))
715 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
716 // a smaller encoding and avoids a scaled-index.
718 AM.BaseType == X86ISelAddressMode::RegBase &&
719 AM.Base_Reg.getNode() == 0) {
720 AM.Base_Reg = AM.IndexReg;
724 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
725 // because it has a smaller encoding.
726 // TODO: Which other code models can use this?
727 if (TM.getCodeModel() == CodeModel::Small &&
728 Subtarget->is64Bit() &&
730 AM.BaseType == X86ISelAddressMode::RegBase &&
731 AM.Base_Reg.getNode() == 0 &&
732 AM.IndexReg.getNode() == 0 &&
733 AM.SymbolFlags == X86II::MO_NO_FLAG &&
734 AM.hasSymbolicDisplacement())
735 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
740 // Insert a node into the DAG at least before the Pos node's position. This
741 // will reposition the node as needed, and will assign it a node ID that is <=
742 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
743 // IDs! The selection DAG must no longer depend on their uniqueness when this
745 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
746 if (N.getNode()->getNodeId() == -1 ||
747 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
748 DAG.RepositionNode(Pos.getNode(), N.getNode());
749 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
753 // Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
754 // allows us to convert the shift and and into an h-register extract and
755 // a scaled index. Returns false if the simplification is performed.
756 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
758 SDValue Shift, SDValue X,
759 X86ISelAddressMode &AM) {
760 if (Shift.getOpcode() != ISD::SRL ||
761 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
765 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
766 if (ScaleLog <= 0 || ScaleLog >= 4 ||
767 Mask != (0xffu << ScaleLog))
770 EVT VT = N.getValueType();
771 DebugLoc DL = N.getDebugLoc();
772 SDValue Eight = DAG.getConstant(8, MVT::i8);
773 SDValue NewMask = DAG.getConstant(0xff, VT);
774 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
775 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
776 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
777 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
779 // Insert the new nodes into the topological ordering. We must do this in
780 // a valid topological ordering as nothing is going to go back and re-sort
781 // these nodes. We continually insert before 'N' in sequence as this is
782 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
783 // hierarchy left to express.
784 InsertDAGNode(DAG, N, Eight);
785 InsertDAGNode(DAG, N, Srl);
786 InsertDAGNode(DAG, N, NewMask);
787 InsertDAGNode(DAG, N, And);
788 InsertDAGNode(DAG, N, ShlCount);
789 InsertDAGNode(DAG, N, Shl);
790 DAG.ReplaceAllUsesWith(N, Shl);
792 AM.Scale = (1 << ScaleLog);
796 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
797 // allows us to fold the shift into this addressing mode. Returns false if the
798 // transform succeeded.
799 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
801 SDValue Shift, SDValue X,
802 X86ISelAddressMode &AM) {
803 if (Shift.getOpcode() != ISD::SHL ||
804 !isa<ConstantSDNode>(Shift.getOperand(1)))
807 // Not likely to be profitable if either the AND or SHIFT node has more
808 // than one use (unless all uses are for address computation). Besides,
809 // isel mechanism requires their node ids to be reused.
810 if (!N.hasOneUse() || !Shift.hasOneUse())
813 // Verify that the shift amount is something we can fold.
814 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
815 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
818 EVT VT = N.getValueType();
819 DebugLoc DL = N.getDebugLoc();
820 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
821 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
822 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
824 // Insert the new nodes into the topological ordering. We must do this in
825 // a valid topological ordering as nothing is going to go back and re-sort
826 // these nodes. We continually insert before 'N' in sequence as this is
827 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
828 // hierarchy left to express.
829 InsertDAGNode(DAG, N, NewMask);
830 InsertDAGNode(DAG, N, NewAnd);
831 InsertDAGNode(DAG, N, NewShift);
832 DAG.ReplaceAllUsesWith(N, NewShift);
834 AM.Scale = 1 << ShiftAmt;
835 AM.IndexReg = NewAnd;
839 // Implement some heroics to detect shifts of masked values where the mask can
840 // be replaced by extending the shift and undoing that in the addressing mode
841 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
842 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
843 // the addressing mode. This results in code such as:
845 // int f(short *y, int *lookup_table) {
847 // return *y + lookup_table[*y >> 11];
851 // movzwl (%rdi), %eax
854 // addl (%rsi,%rcx,4), %eax
857 // movzwl (%rdi), %eax
861 // addl (%rsi,%rcx), %eax
863 // Note that this function assumes the mask is provided as a mask *after* the
864 // value is shifted. The input chain may or may not match that, but computing
865 // such a mask is trivial.
866 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
868 SDValue Shift, SDValue X,
869 X86ISelAddressMode &AM) {
870 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
871 !isa<ConstantSDNode>(Shift.getOperand(1)))
874 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
875 unsigned MaskLZ = CountLeadingZeros_64(Mask);
876 unsigned MaskTZ = CountTrailingZeros_64(Mask);
878 // The amount of shift we're trying to fit into the addressing mode is taken
879 // from the trailing zeros of the mask.
880 unsigned AMShiftAmt = MaskTZ;
882 // There is nothing we can do here unless the mask is removing some bits.
883 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
884 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
886 // We also need to ensure that mask is a continuous run of bits.
887 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
889 // Scale the leading zero count down based on the actual size of the value.
890 // Also scale it down based on the size of the shift.
891 MaskLZ -= (64 - X.getValueSizeInBits()) + ShiftAmt;
893 // The final check is to ensure that any masked out high bits of X are
894 // already known to be zero. Otherwise, the mask has a semantic impact
895 // other than masking out a couple of low bits. Unfortunately, because of
896 // the mask, zero extensions will be removed from operands in some cases.
897 // This code works extra hard to look through extensions because we can
898 // replace them with zero extensions cheaply if necessary.
899 bool ReplacingAnyExtend = false;
900 if (X.getOpcode() == ISD::ANY_EXTEND) {
901 unsigned ExtendBits =
902 X.getValueSizeInBits() - X.getOperand(0).getValueSizeInBits();
903 // Assume that we'll replace the any-extend with a zero-extend, and
904 // narrow the search to the extended value.
906 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
907 ReplacingAnyExtend = true;
909 APInt MaskedHighBits = APInt::getHighBitsSet(X.getValueSizeInBits(),
911 APInt KnownZero, KnownOne;
912 DAG.ComputeMaskedBits(X, KnownZero, KnownOne);
913 if (MaskedHighBits != KnownZero) return true;
915 // We've identified a pattern that can be transformed into a single shift
916 // and an addressing mode. Make it so.
917 EVT VT = N.getValueType();
918 if (ReplacingAnyExtend) {
919 assert(X.getValueType() != VT);
920 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
921 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, X.getDebugLoc(), VT, X);
922 InsertDAGNode(DAG, N, NewX);
925 DebugLoc DL = N.getDebugLoc();
926 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
927 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
928 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
929 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
931 // Insert the new nodes into the topological ordering. We must do this in
932 // a valid topological ordering as nothing is going to go back and re-sort
933 // these nodes. We continually insert before 'N' in sequence as this is
934 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
935 // hierarchy left to express.
936 InsertDAGNode(DAG, N, NewSRLAmt);
937 InsertDAGNode(DAG, N, NewSRL);
938 InsertDAGNode(DAG, N, NewSHLAmt);
939 InsertDAGNode(DAG, N, NewSHL);
940 DAG.ReplaceAllUsesWith(N, NewSHL);
942 AM.Scale = 1 << AMShiftAmt;
943 AM.IndexReg = NewSRL;
947 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
949 DebugLoc dl = N.getDebugLoc();
951 dbgs() << "MatchAddress: ";
956 return MatchAddressBase(N, AM);
958 // If this is already a %rip relative address, we can only merge immediates
959 // into it. Instead of handling this in every case, we handle it here.
960 // RIP relative addressing: %rip + 32-bit displacement!
961 if (AM.isRIPRelative()) {
962 // FIXME: JumpTable and ExternalSymbol address currently don't like
963 // displacements. It isn't very important, but this should be fixed for
965 if (!AM.ES && AM.JT != -1) return true;
967 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
968 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
973 switch (N.getOpcode()) {
975 case ISD::Constant: {
976 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
977 if (!FoldOffsetIntoAddress(Val, AM))
982 case X86ISD::Wrapper:
983 case X86ISD::WrapperRIP:
984 if (!MatchWrapper(N, AM))
989 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
993 case ISD::FrameIndex:
994 if (AM.BaseType == X86ISelAddressMode::RegBase &&
995 AM.Base_Reg.getNode() == 0 &&
996 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
997 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
998 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1004 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
1008 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1009 unsigned Val = CN->getZExtValue();
1010 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1011 // that the base operand remains free for further matching. If
1012 // the base doesn't end up getting used, a post-processing step
1013 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1014 if (Val == 1 || Val == 2 || Val == 3) {
1015 AM.Scale = 1 << Val;
1016 SDValue ShVal = N.getNode()->getOperand(0);
1018 // Okay, we know that we have a scale by now. However, if the scaled
1019 // value is an add of something and a constant, we can fold the
1020 // constant into the disp field here.
1021 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1022 AM.IndexReg = ShVal.getNode()->getOperand(0);
1023 ConstantSDNode *AddVal =
1024 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1025 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1026 if (!FoldOffsetIntoAddress(Disp, AM))
1030 AM.IndexReg = ShVal;
1037 // Scale must not be used already.
1038 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1040 SDValue And = N.getOperand(0);
1041 if (And.getOpcode() != ISD::AND) break;
1042 SDValue X = And.getOperand(0);
1044 // We only handle up to 64-bit values here as those are what matter for
1045 // addressing mode optimizations.
1046 if (X.getValueSizeInBits() > 64) break;
1048 // The mask used for the transform is expected to be post-shift, but we
1049 // found the shift first so just apply the shift to the mask before passing
1051 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1052 !isa<ConstantSDNode>(And.getOperand(1)))
1054 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1056 // Try to fold the mask and shift into the scale, and return false if we
1058 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1063 case ISD::SMUL_LOHI:
1064 case ISD::UMUL_LOHI:
1065 // A mul_lohi where we need the low part can be folded as a plain multiply.
1066 if (N.getResNo() != 0) break;
1069 case X86ISD::MUL_IMM:
1070 // X*[3,5,9] -> X+X*[2,4,8]
1071 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1072 AM.Base_Reg.getNode() == 0 &&
1073 AM.IndexReg.getNode() == 0) {
1075 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1076 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1077 CN->getZExtValue() == 9) {
1078 AM.Scale = unsigned(CN->getZExtValue())-1;
1080 SDValue MulVal = N.getNode()->getOperand(0);
1083 // Okay, we know that we have a scale by now. However, if the scaled
1084 // value is an add of something and a constant, we can fold the
1085 // constant into the disp field here.
1086 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1087 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1088 Reg = MulVal.getNode()->getOperand(0);
1089 ConstantSDNode *AddVal =
1090 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1091 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1092 if (FoldOffsetIntoAddress(Disp, AM))
1093 Reg = N.getNode()->getOperand(0);
1095 Reg = N.getNode()->getOperand(0);
1098 AM.IndexReg = AM.Base_Reg = Reg;
1105 // Given A-B, if A can be completely folded into the address and
1106 // the index field with the index field unused, use -B as the index.
1107 // This is a win if a has multiple parts that can be folded into
1108 // the address. Also, this saves a mov if the base register has
1109 // other uses, since it avoids a two-address sub instruction, however
1110 // it costs an additional mov if the index register has other uses.
1112 // Add an artificial use to this node so that we can keep track of
1113 // it if it gets CSE'd with a different node.
1114 HandleSDNode Handle(N);
1116 // Test if the LHS of the sub can be folded.
1117 X86ISelAddressMode Backup = AM;
1118 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1122 // Test if the index field is free for use.
1123 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1129 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1130 // If the RHS involves a register with multiple uses, this
1131 // transformation incurs an extra mov, due to the neg instruction
1132 // clobbering its operand.
1133 if (!RHS.getNode()->hasOneUse() ||
1134 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1135 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1136 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1137 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1138 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1140 // If the base is a register with multiple uses, this
1141 // transformation may save a mov.
1142 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1143 AM.Base_Reg.getNode() &&
1144 !AM.Base_Reg.getNode()->hasOneUse()) ||
1145 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1147 // If the folded LHS was interesting, this transformation saves
1148 // address arithmetic.
1149 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1150 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1151 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1153 // If it doesn't look like it may be an overall win, don't do it.
1159 // Ok, the transformation is legal and appears profitable. Go for it.
1160 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1161 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1165 // Insert the new nodes into the topological ordering.
1166 InsertDAGNode(*CurDAG, N, Zero);
1167 InsertDAGNode(*CurDAG, N, Neg);
1172 // Add an artificial use to this node so that we can keep track of
1173 // it if it gets CSE'd with a different node.
1174 HandleSDNode Handle(N);
1176 X86ISelAddressMode Backup = AM;
1177 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1178 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1182 // Try again after commuting the operands.
1183 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1184 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1188 // If we couldn't fold both operands into the address at the same time,
1189 // see if we can just put each operand into a register and fold at least
1191 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1192 !AM.Base_Reg.getNode() &&
1193 !AM.IndexReg.getNode()) {
1194 N = Handle.getValue();
1195 AM.Base_Reg = N.getOperand(0);
1196 AM.IndexReg = N.getOperand(1);
1200 N = Handle.getValue();
1205 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1206 if (CurDAG->isBaseWithConstantOffset(N)) {
1207 X86ISelAddressMode Backup = AM;
1208 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1210 // Start with the LHS as an addr mode.
1211 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1212 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1219 // Perform some heroic transforms on an and of a constant-count shift
1220 // with a constant to enable use of the scaled offset field.
1222 // Scale must not be used already.
1223 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1225 SDValue Shift = N.getOperand(0);
1226 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1227 SDValue X = Shift.getOperand(0);
1229 // We only handle up to 64-bit values here as those are what matter for
1230 // addressing mode optimizations.
1231 if (X.getValueSizeInBits() > 64) break;
1233 if (!isa<ConstantSDNode>(N.getOperand(1)))
1235 uint64_t Mask = N.getConstantOperandVal(1);
1237 // Try to fold the mask and shift into an extract and scale.
1238 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1241 // Try to fold the mask and shift directly into the scale.
1242 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1245 // Try to swap the mask and shift to place shifts which can be done as
1246 // a scale on the outside of the mask.
1247 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1253 return MatchAddressBase(N, AM);
1256 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1257 /// specified addressing mode without any further recursion.
1258 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1259 // Is the base register already occupied?
1260 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1261 // If so, check to see if the scale index register is set.
1262 if (AM.IndexReg.getNode() == 0) {
1268 // Otherwise, we cannot select it.
1272 // Default, generate it as a register.
1273 AM.BaseType = X86ISelAddressMode::RegBase;
1278 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1279 /// It returns the operands which make up the maximal addressing mode it can
1280 /// match by reference.
1282 /// Parent is the parent node of the addr operand that is being matched. It
1283 /// is always a load, store, atomic node, or null. It is only null when
1284 /// checking memory operands for inline asm nodes.
1285 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1286 SDValue &Scale, SDValue &Index,
1287 SDValue &Disp, SDValue &Segment) {
1288 X86ISelAddressMode AM;
1291 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1292 // that are not a MemSDNode, and thus don't have proper addrspace info.
1293 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1294 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1295 Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme
1296 unsigned AddrSpace =
1297 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1298 // AddrSpace 256 -> GS, 257 -> FS.
1299 if (AddrSpace == 256)
1300 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1301 if (AddrSpace == 257)
1302 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1305 if (MatchAddress(N, AM))
1308 EVT VT = N.getValueType();
1309 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1310 if (!AM.Base_Reg.getNode())
1311 AM.Base_Reg = CurDAG->getRegister(0, VT);
1314 if (!AM.IndexReg.getNode())
1315 AM.IndexReg = CurDAG->getRegister(0, VT);
1317 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1321 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1322 /// match a load whose top elements are either undef or zeros. The load flavor
1323 /// is derived from the type of N, which is either v4f32 or v2f64.
1326 /// PatternChainNode: this is the matched node that has a chain input and
1328 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1329 SDValue N, SDValue &Base,
1330 SDValue &Scale, SDValue &Index,
1331 SDValue &Disp, SDValue &Segment,
1332 SDValue &PatternNodeWithChain) {
1333 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1334 PatternNodeWithChain = N.getOperand(0);
1335 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1336 PatternNodeWithChain.hasOneUse() &&
1337 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1338 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1339 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1340 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1346 // Also handle the case where we explicitly require zeros in the top
1347 // elements. This is a vector shuffle from the zero vector.
1348 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1349 // Check to see if the top elements are all zeros (or bitcast of zeros).
1350 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1351 N.getOperand(0).getNode()->hasOneUse() &&
1352 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1353 N.getOperand(0).getOperand(0).hasOneUse() &&
1354 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1355 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1356 // Okay, this is a zero extending load. Fold it.
1357 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1358 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1360 PatternNodeWithChain = SDValue(LD, 0);
1367 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1368 /// mode it matches can be cost effectively emitted as an LEA instruction.
1369 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1370 SDValue &Base, SDValue &Scale,
1371 SDValue &Index, SDValue &Disp,
1373 X86ISelAddressMode AM;
1375 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1377 SDValue Copy = AM.Segment;
1378 SDValue T = CurDAG->getRegister(0, MVT::i32);
1380 if (MatchAddress(N, AM))
1382 assert (T == AM.Segment);
1385 EVT VT = N.getValueType();
1386 unsigned Complexity = 0;
1387 if (AM.BaseType == X86ISelAddressMode::RegBase)
1388 if (AM.Base_Reg.getNode())
1391 AM.Base_Reg = CurDAG->getRegister(0, VT);
1392 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1395 if (AM.IndexReg.getNode())
1398 AM.IndexReg = CurDAG->getRegister(0, VT);
1400 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1405 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1406 // to a LEA. This is determined with some expermentation but is by no means
1407 // optimal (especially for code size consideration). LEA is nice because of
1408 // its three-address nature. Tweak the cost function again when we can run
1409 // convertToThreeAddress() at register allocation time.
1410 if (AM.hasSymbolicDisplacement()) {
1411 // For X86-64, we should always use lea to materialize RIP relative
1413 if (Subtarget->is64Bit())
1419 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1422 // If it isn't worth using an LEA, reject it.
1423 if (Complexity <= 2)
1426 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1430 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1431 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1432 SDValue &Scale, SDValue &Index,
1433 SDValue &Disp, SDValue &Segment) {
1434 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1435 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1437 X86ISelAddressMode AM;
1438 AM.GV = GA->getGlobal();
1439 AM.Disp += GA->getOffset();
1440 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1441 AM.SymbolFlags = GA->getTargetFlags();
1443 if (N.getValueType() == MVT::i32) {
1445 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1447 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1450 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1455 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1456 SDValue &Base, SDValue &Scale,
1457 SDValue &Index, SDValue &Disp,
1459 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1460 !IsProfitableToFold(N, P, P) ||
1461 !IsLegalToFold(N, P, P, OptLevel))
1464 return SelectAddr(N.getNode(),
1465 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1468 /// getGlobalBaseReg - Return an SDNode that returns the value of
1469 /// the global base register. Output instructions required to
1470 /// initialize the global base register, if necessary.
1472 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1473 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1474 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1477 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1478 SDValue Chain = Node->getOperand(0);
1479 SDValue In1 = Node->getOperand(1);
1480 SDValue In2L = Node->getOperand(2);
1481 SDValue In2H = Node->getOperand(3);
1483 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1484 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1486 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1487 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1488 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1489 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1490 MVT::i32, MVT::i32, MVT::Other, Ops,
1491 array_lengthof(Ops));
1492 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1496 /// Atomic opcode table
1524 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1535 X86::LOCK_ADD64mi32,
1548 X86::LOCK_SUB64mi32,
1600 X86::LOCK_AND64mi32,
1613 X86::LOCK_XOR64mi32,
1618 // Return the target constant operand for atomic-load-op and do simple
1619 // translations, such as from atomic-load-add to lock-sub. The return value is
1620 // one of the following 3 cases:
1621 // + target-constant, the operand could be supported as a target constant.
1622 // + empty, the operand is not needed any more with the new op selected.
1623 // + non-empty, otherwise.
1624 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1626 enum AtomicOpc &Op, EVT NVT,
1628 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1629 int64_t CNVal = CN->getSExtValue();
1630 // Quit if not 32-bit imm.
1631 if ((int32_t)CNVal != CNVal)
1633 // For atomic-load-add, we could do some optimizations.
1635 // Translate to INC/DEC if ADD by 1 or -1.
1636 if ((CNVal == 1) || (CNVal == -1)) {
1637 Op = (CNVal == 1) ? INC : DEC;
1638 // No more constant operand after being translated into INC/DEC.
1641 // Translate to SUB if ADD by negative value.
1647 return CurDAG->getTargetConstant(CNVal, NVT);
1650 // If the value operand is single-used, try to optimize it.
1651 if (Op == ADD && Val.hasOneUse()) {
1652 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1653 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1655 return Val.getOperand(1);
1657 // A special case for i16, which needs truncating as, in most cases, it's
1658 // promoted to i32. We will translate
1659 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1660 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1661 Val.getOperand(0).getOpcode() == ISD::SUB &&
1662 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1664 Val = Val.getOperand(0);
1665 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1673 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
1674 if (Node->hasAnyUseOfValue(0))
1677 DebugLoc dl = Node->getDebugLoc();
1679 // Optimize common patterns for __sync_or_and_fetch and similar arith
1680 // operations where the result is not used. This allows us to use the "lock"
1681 // version of the arithmetic instruction.
1682 SDValue Chain = Node->getOperand(0);
1683 SDValue Ptr = Node->getOperand(1);
1684 SDValue Val = Node->getOperand(2);
1685 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1686 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1689 // Which index into the table.
1691 switch (Node->getOpcode()) {
1694 case ISD::ATOMIC_LOAD_OR:
1697 case ISD::ATOMIC_LOAD_AND:
1700 case ISD::ATOMIC_LOAD_XOR:
1703 case ISD::ATOMIC_LOAD_ADD:
1708 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val);
1709 bool isUnOp = !Val.getNode();
1710 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1713 switch (NVT.getSimpleVT().SimpleTy) {
1717 Opc = AtomicOpcTbl[Op][ConstantI8];
1719 Opc = AtomicOpcTbl[Op][I8];
1723 if (immSext8(Val.getNode()))
1724 Opc = AtomicOpcTbl[Op][SextConstantI16];
1726 Opc = AtomicOpcTbl[Op][ConstantI16];
1728 Opc = AtomicOpcTbl[Op][I16];
1732 if (immSext8(Val.getNode()))
1733 Opc = AtomicOpcTbl[Op][SextConstantI32];
1735 Opc = AtomicOpcTbl[Op][ConstantI32];
1737 Opc = AtomicOpcTbl[Op][I32];
1740 Opc = AtomicOpcTbl[Op][I64];
1742 if (immSext8(Val.getNode()))
1743 Opc = AtomicOpcTbl[Op][SextConstantI64];
1744 else if (i64immSExt32(Val.getNode()))
1745 Opc = AtomicOpcTbl[Op][ConstantI64];
1750 assert(Opc != 0 && "Invalid arith lock transform!");
1753 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1755 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1756 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1758 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1759 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops,
1760 array_lengthof(Ops)), 0);
1762 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1763 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops,
1764 array_lengthof(Ops)), 0);
1766 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1767 SDValue RetVals[] = { Undef, Ret };
1768 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1771 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1772 /// any uses which require the SF or OF bits to be accurate.
1773 static bool HasNoSignedComparisonUses(SDNode *N) {
1774 // Examine each user of the node.
1775 for (SDNode::use_iterator UI = N->use_begin(),
1776 UE = N->use_end(); UI != UE; ++UI) {
1777 // Only examine CopyToReg uses.
1778 if (UI->getOpcode() != ISD::CopyToReg)
1780 // Only examine CopyToReg uses that copy to EFLAGS.
1781 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1784 // Examine each user of the CopyToReg use.
1785 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1786 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1787 // Only examine the Flag result.
1788 if (FlagUI.getUse().getResNo() != 1) continue;
1789 // Anything unusual: assume conservatively.
1790 if (!FlagUI->isMachineOpcode()) return false;
1791 // Examine the opcode of the user.
1792 switch (FlagUI->getMachineOpcode()) {
1793 // These comparisons don't treat the most significant bit specially.
1794 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1795 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1796 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1797 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1798 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1799 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1800 case X86::CMOVA16rr: case X86::CMOVA16rm:
1801 case X86::CMOVA32rr: case X86::CMOVA32rm:
1802 case X86::CMOVA64rr: case X86::CMOVA64rm:
1803 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1804 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1805 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1806 case X86::CMOVB16rr: case X86::CMOVB16rm:
1807 case X86::CMOVB32rr: case X86::CMOVB32rm:
1808 case X86::CMOVB64rr: case X86::CMOVB64rm:
1809 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1810 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1811 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1812 case X86::CMOVE16rr: case X86::CMOVE16rm:
1813 case X86::CMOVE32rr: case X86::CMOVE32rm:
1814 case X86::CMOVE64rr: case X86::CMOVE64rm:
1815 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1816 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1817 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1818 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1819 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1820 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1821 case X86::CMOVP16rr: case X86::CMOVP16rm:
1822 case X86::CMOVP32rr: case X86::CMOVP32rm:
1823 case X86::CMOVP64rr: case X86::CMOVP64rm:
1825 // Anything else: assume conservatively.
1826 default: return false;
1833 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1834 /// is suitable for doing the {load; increment or decrement; store} to modify
1836 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1837 SDValue StoredVal, SelectionDAG *CurDAG,
1838 LoadSDNode* &LoadNode, SDValue &InputChain) {
1840 // is the value stored the result of a DEC or INC?
1841 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1843 // is the stored value result 0 of the load?
1844 if (StoredVal.getResNo() != 0) return false;
1846 // are there other uses of the loaded value than the inc or dec?
1847 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1849 // is the store non-extending and non-indexed?
1850 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1853 SDValue Load = StoredVal->getOperand(0);
1854 // Is the stored value a non-extending and non-indexed load?
1855 if (!ISD::isNormalLoad(Load.getNode())) return false;
1857 // Return LoadNode by reference.
1858 LoadNode = cast<LoadSDNode>(Load);
1859 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1860 EVT LdVT = LoadNode->getMemoryVT();
1861 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1865 // Is store the only read of the loaded value?
1866 if (!Load.hasOneUse())
1869 // Is the address of the store the same as the load?
1870 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1871 LoadNode->getOffset() != StoreNode->getOffset())
1874 // Check if the chain is produced by the load or is a TokenFactor with
1875 // the load output chain as an operand. Return InputChain by reference.
1876 SDValue Chain = StoreNode->getChain();
1878 bool ChainCheck = false;
1879 if (Chain == Load.getValue(1)) {
1881 InputChain = LoadNode->getChain();
1882 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1883 SmallVector<SDValue, 4> ChainOps;
1884 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1885 SDValue Op = Chain.getOperand(i);
1886 if (Op == Load.getValue(1)) {
1891 // Make sure using Op as part of the chain would not cause a cycle here.
1892 // In theory, we could check whether the chain node is a predecessor of
1893 // the load. But that can be very expensive. Instead visit the uses and
1894 // make sure they all have smaller node id than the load.
1895 int LoadId = LoadNode->getNodeId();
1896 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1897 UE = UI->use_end(); UI != UE; ++UI) {
1898 if (UI.getUse().getResNo() != 0)
1900 if (UI->getNodeId() > LoadId)
1904 ChainOps.push_back(Op);
1908 // Make a new TokenFactor with all the other input chains except
1910 InputChain = CurDAG->getNode(ISD::TokenFactor, Chain.getDebugLoc(),
1911 MVT::Other, &ChainOps[0], ChainOps.size());
1919 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
1920 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
1921 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
1922 if (Opc == X86ISD::DEC) {
1923 if (LdVT == MVT::i64) return X86::DEC64m;
1924 if (LdVT == MVT::i32) return X86::DEC32m;
1925 if (LdVT == MVT::i16) return X86::DEC16m;
1926 if (LdVT == MVT::i8) return X86::DEC8m;
1928 assert(Opc == X86ISD::INC && "unrecognized opcode");
1929 if (LdVT == MVT::i64) return X86::INC64m;
1930 if (LdVT == MVT::i32) return X86::INC32m;
1931 if (LdVT == MVT::i16) return X86::INC16m;
1932 if (LdVT == MVT::i8) return X86::INC8m;
1934 llvm_unreachable("unrecognized size for LdVT");
1937 /// SelectGather - Customized ISel for GATHER operations.
1939 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
1940 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
1941 SDValue Chain = Node->getOperand(0);
1942 SDValue VSrc = Node->getOperand(2);
1943 SDValue Base = Node->getOperand(3);
1944 SDValue VIdx = Node->getOperand(4);
1945 SDValue VMask = Node->getOperand(5);
1946 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
1950 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
1953 // Memory Operands: Base, Scale, Index, Disp, Segment
1954 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
1955 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
1956 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
1957 Disp, Segment, VMask, Chain};
1958 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1959 VTs, Ops, array_lengthof(Ops));
1960 // Node has 2 outputs: VDst and MVT::Other.
1961 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
1962 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
1964 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
1965 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
1969 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
1970 EVT NVT = Node->getValueType(0);
1972 unsigned Opcode = Node->getOpcode();
1973 DebugLoc dl = Node->getDebugLoc();
1975 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
1977 if (Node->isMachineOpcode()) {
1978 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
1979 return NULL; // Already selected.
1984 case ISD::INTRINSIC_W_CHAIN: {
1985 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
1988 case Intrinsic::x86_avx2_gather_d_pd:
1989 case Intrinsic::x86_avx2_gather_d_pd_256:
1990 case Intrinsic::x86_avx2_gather_q_pd:
1991 case Intrinsic::x86_avx2_gather_q_pd_256:
1992 case Intrinsic::x86_avx2_gather_d_ps:
1993 case Intrinsic::x86_avx2_gather_d_ps_256:
1994 case Intrinsic::x86_avx2_gather_q_ps:
1995 case Intrinsic::x86_avx2_gather_q_ps_256:
1996 case Intrinsic::x86_avx2_gather_d_q:
1997 case Intrinsic::x86_avx2_gather_d_q_256:
1998 case Intrinsic::x86_avx2_gather_q_q:
1999 case Intrinsic::x86_avx2_gather_q_q_256:
2000 case Intrinsic::x86_avx2_gather_d_d:
2001 case Intrinsic::x86_avx2_gather_d_d_256:
2002 case Intrinsic::x86_avx2_gather_q_d:
2003 case Intrinsic::x86_avx2_gather_q_d_256: {
2006 default: llvm_unreachable("Impossible intrinsic");
2007 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2008 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2009 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2010 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2011 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2012 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2013 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2014 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2015 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2016 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2017 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2018 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2019 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2020 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2021 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2022 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2024 SDNode *RetVal = SelectGather(Node, Opc);
2026 // We already called ReplaceUses inside SelectGather.
2033 case X86ISD::GlobalBaseReg:
2034 return getGlobalBaseReg();
2037 case X86ISD::ATOMOR64_DAG:
2038 case X86ISD::ATOMXOR64_DAG:
2039 case X86ISD::ATOMADD64_DAG:
2040 case X86ISD::ATOMSUB64_DAG:
2041 case X86ISD::ATOMNAND64_DAG:
2042 case X86ISD::ATOMAND64_DAG:
2043 case X86ISD::ATOMMAX64_DAG:
2044 case X86ISD::ATOMMIN64_DAG:
2045 case X86ISD::ATOMUMAX64_DAG:
2046 case X86ISD::ATOMUMIN64_DAG:
2047 case X86ISD::ATOMSWAP64_DAG: {
2050 default: llvm_unreachable("Impossible opcode");
2051 case X86ISD::ATOMOR64_DAG: Opc = X86::ATOMOR6432; break;
2052 case X86ISD::ATOMXOR64_DAG: Opc = X86::ATOMXOR6432; break;
2053 case X86ISD::ATOMADD64_DAG: Opc = X86::ATOMADD6432; break;
2054 case X86ISD::ATOMSUB64_DAG: Opc = X86::ATOMSUB6432; break;
2055 case X86ISD::ATOMNAND64_DAG: Opc = X86::ATOMNAND6432; break;
2056 case X86ISD::ATOMAND64_DAG: Opc = X86::ATOMAND6432; break;
2057 case X86ISD::ATOMMAX64_DAG: Opc = X86::ATOMMAX6432; break;
2058 case X86ISD::ATOMMIN64_DAG: Opc = X86::ATOMMIN6432; break;
2059 case X86ISD::ATOMUMAX64_DAG: Opc = X86::ATOMUMAX6432; break;
2060 case X86ISD::ATOMUMIN64_DAG: Opc = X86::ATOMUMIN6432; break;
2061 case X86ISD::ATOMSWAP64_DAG: Opc = X86::ATOMSWAP6432; break;
2063 SDNode *RetVal = SelectAtomic64(Node, Opc);
2069 case ISD::ATOMIC_LOAD_XOR:
2070 case ISD::ATOMIC_LOAD_AND:
2071 case ISD::ATOMIC_LOAD_OR:
2072 case ISD::ATOMIC_LOAD_ADD: {
2073 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2081 // For operations of the form (x << C1) op C2, check if we can use a smaller
2082 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2083 SDValue N0 = Node->getOperand(0);
2084 SDValue N1 = Node->getOperand(1);
2086 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2089 // i8 is unshrinkable, i16 should be promoted to i32.
2090 if (NVT != MVT::i32 && NVT != MVT::i64)
2093 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2094 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2095 if (!Cst || !ShlCst)
2098 int64_t Val = Cst->getSExtValue();
2099 uint64_t ShlVal = ShlCst->getZExtValue();
2101 // Make sure that we don't change the operation by removing bits.
2102 // This only matters for OR and XOR, AND is unaffected.
2103 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2104 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2110 // Check the minimum bitwidth for the new constant.
2111 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2112 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2113 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2114 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2116 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2119 // Bail if there is no smaller encoding.
2123 switch (NVT.getSimpleVT().SimpleTy) {
2124 default: llvm_unreachable("Unsupported VT!");
2126 assert(CstVT == MVT::i8);
2127 ShlOp = X86::SHL32ri;
2130 default: llvm_unreachable("Impossible opcode");
2131 case ISD::AND: Op = X86::AND32ri8; break;
2132 case ISD::OR: Op = X86::OR32ri8; break;
2133 case ISD::XOR: Op = X86::XOR32ri8; break;
2137 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2138 ShlOp = X86::SHL64ri;
2141 default: llvm_unreachable("Impossible opcode");
2142 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2143 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2144 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2149 // Emit the smaller op and the shift.
2150 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2151 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2152 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2155 case X86ISD::UMUL: {
2156 SDValue N0 = Node->getOperand(0);
2157 SDValue N1 = Node->getOperand(1);
2160 switch (NVT.getSimpleVT().SimpleTy) {
2161 default: llvm_unreachable("Unsupported VT!");
2162 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2163 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2164 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2165 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2168 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2169 N0, SDValue()).getValue(1);
2171 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2172 SDValue Ops[] = {N1, InFlag};
2173 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops, 2);
2175 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2176 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2177 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2181 case ISD::SMUL_LOHI:
2182 case ISD::UMUL_LOHI: {
2183 SDValue N0 = Node->getOperand(0);
2184 SDValue N1 = Node->getOperand(1);
2186 bool isSigned = Opcode == ISD::SMUL_LOHI;
2187 bool hasBMI2 = Subtarget->hasBMI2();
2189 switch (NVT.getSimpleVT().SimpleTy) {
2190 default: llvm_unreachable("Unsupported VT!");
2191 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2192 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2193 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2194 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2195 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2196 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2199 switch (NVT.getSimpleVT().SimpleTy) {
2200 default: llvm_unreachable("Unsupported VT!");
2201 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2202 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2203 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2204 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2208 unsigned SrcReg, LoReg, HiReg;
2210 default: llvm_unreachable("Unknown MUL opcode!");
2213 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2217 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2221 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2225 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2228 SrcReg = X86::EDX; LoReg = HiReg = 0;
2231 SrcReg = X86::RDX; LoReg = HiReg = 0;
2235 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2236 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2237 // Multiply is commmutative.
2239 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2244 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2245 N0, SDValue()).getValue(1);
2246 SDValue ResHi, ResLo;
2250 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2252 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2253 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2254 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops,
2255 array_lengthof(Ops));
2256 ResHi = SDValue(CNode, 0);
2257 ResLo = SDValue(CNode, 1);
2258 Chain = SDValue(CNode, 2);
2259 InFlag = SDValue(CNode, 3);
2261 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2262 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops,
2263 array_lengthof(Ops));
2264 Chain = SDValue(CNode, 0);
2265 InFlag = SDValue(CNode, 1);
2268 // Update the chain.
2269 ReplaceUses(N1.getValue(1), Chain);
2271 SDValue Ops[] = { N1, InFlag };
2272 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2273 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2274 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops,
2275 array_lengthof(Ops));
2276 ResHi = SDValue(CNode, 0);
2277 ResLo = SDValue(CNode, 1);
2278 InFlag = SDValue(CNode, 2);
2280 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2281 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops,
2282 array_lengthof(Ops));
2283 InFlag = SDValue(CNode, 0);
2287 // Prevent use of AH in a REX instruction by referencing AX instead.
2288 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2289 !SDValue(Node, 1).use_empty()) {
2290 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2291 X86::AX, MVT::i16, InFlag);
2292 InFlag = Result.getValue(2);
2293 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2295 if (!SDValue(Node, 0).use_empty())
2296 ReplaceUses(SDValue(Node, 1),
2297 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2299 // Shift AX down 8 bits.
2300 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2302 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2303 // Then truncate it down to i8.
2304 ReplaceUses(SDValue(Node, 1),
2305 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2307 // Copy the low half of the result, if it is needed.
2308 if (!SDValue(Node, 0).use_empty()) {
2309 if (ResLo.getNode() == 0) {
2310 assert(LoReg && "Register for low half is not defined!");
2311 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2313 InFlag = ResLo.getValue(2);
2315 ReplaceUses(SDValue(Node, 0), ResLo);
2316 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2318 // Copy the high half of the result, if it is needed.
2319 if (!SDValue(Node, 1).use_empty()) {
2320 if (ResHi.getNode() == 0) {
2321 assert(HiReg && "Register for high half is not defined!");
2322 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2324 InFlag = ResHi.getValue(2);
2326 ReplaceUses(SDValue(Node, 1), ResHi);
2327 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2334 case ISD::UDIVREM: {
2335 SDValue N0 = Node->getOperand(0);
2336 SDValue N1 = Node->getOperand(1);
2338 bool isSigned = Opcode == ISD::SDIVREM;
2340 switch (NVT.getSimpleVT().SimpleTy) {
2341 default: llvm_unreachable("Unsupported VT!");
2342 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2343 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2344 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2345 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2348 switch (NVT.getSimpleVT().SimpleTy) {
2349 default: llvm_unreachable("Unsupported VT!");
2350 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2351 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2352 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2353 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2357 unsigned LoReg, HiReg, ClrReg;
2358 unsigned ClrOpcode, SExtOpcode;
2359 switch (NVT.getSimpleVT().SimpleTy) {
2360 default: llvm_unreachable("Unsupported VT!");
2362 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2364 SExtOpcode = X86::CBW;
2367 LoReg = X86::AX; HiReg = X86::DX;
2368 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
2369 SExtOpcode = X86::CWD;
2372 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2373 ClrOpcode = X86::MOV32r0;
2374 SExtOpcode = X86::CDQ;
2377 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2378 ClrOpcode = X86::MOV64r0;
2379 SExtOpcode = X86::CQO;
2383 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2384 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2385 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2388 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2389 // Special case for div8, just use a move with zero extension to AX to
2390 // clear the upper 8 bits (AH).
2391 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2392 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2393 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2395 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2397 array_lengthof(Ops)), 0);
2398 Chain = Move.getValue(1);
2399 ReplaceUses(N0.getValue(1), Chain);
2402 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2403 Chain = CurDAG->getEntryNode();
2405 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2406 InFlag = Chain.getValue(1);
2409 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2410 LoReg, N0, SDValue()).getValue(1);
2411 if (isSigned && !signBitIsZero) {
2412 // Sign extend the low part into the high part.
2414 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2416 // Zero out the high part, effectively zero extending the input.
2418 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
2419 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2420 ClrNode, InFlag).getValue(1);
2425 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2428 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
2429 array_lengthof(Ops));
2430 InFlag = SDValue(CNode, 1);
2431 // Update the chain.
2432 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2435 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2438 // Prevent use of AH in a REX instruction by referencing AX instead.
2439 // Shift it down 8 bits.
2440 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2441 !SDValue(Node, 1).use_empty()) {
2442 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2443 X86::AX, MVT::i16, InFlag);
2444 InFlag = Result.getValue(2);
2446 // If we also need AL (the quotient), get it by extracting a subreg from
2447 // Result. The fast register allocator does not like multiple CopyFromReg
2448 // nodes using aliasing registers.
2449 if (!SDValue(Node, 0).use_empty())
2450 ReplaceUses(SDValue(Node, 0),
2451 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2453 // Shift AX right by 8 bits instead of using AH.
2454 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2456 CurDAG->getTargetConstant(8, MVT::i8)),
2458 ReplaceUses(SDValue(Node, 1),
2459 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2461 // Copy the division (low) result, if it is needed.
2462 if (!SDValue(Node, 0).use_empty()) {
2463 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2464 LoReg, NVT, InFlag);
2465 InFlag = Result.getValue(2);
2466 ReplaceUses(SDValue(Node, 0), Result);
2467 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2469 // Copy the remainder (high) result, if it is needed.
2470 if (!SDValue(Node, 1).use_empty()) {
2471 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2472 HiReg, NVT, InFlag);
2473 InFlag = Result.getValue(2);
2474 ReplaceUses(SDValue(Node, 1), Result);
2475 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2482 // Sometimes a SUB is used to perform comparison.
2483 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2484 // This node is not a CMP.
2486 SDValue N0 = Node->getOperand(0);
2487 SDValue N1 = Node->getOperand(1);
2489 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2490 // use a smaller encoding.
2491 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2492 HasNoSignedComparisonUses(Node))
2493 // Look past the truncate if CMP is the only use of it.
2494 N0 = N0.getOperand(0);
2495 if ((N0.getNode()->getOpcode() == ISD::AND ||
2496 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2497 N0.getNode()->hasOneUse() &&
2498 N0.getValueType() != MVT::i8 &&
2499 X86::isZeroNode(N1)) {
2500 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2503 // For example, convert "testl %eax, $8" to "testb %al, $8"
2504 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2505 (!(C->getZExtValue() & 0x80) ||
2506 HasNoSignedComparisonUses(Node))) {
2507 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2508 SDValue Reg = N0.getNode()->getOperand(0);
2510 // On x86-32, only the ABCD registers have 8-bit subregisters.
2511 if (!Subtarget->is64Bit()) {
2512 const TargetRegisterClass *TRC;
2513 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2514 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2515 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2516 default: llvm_unreachable("Unsupported TEST operand type!");
2518 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2519 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2520 Reg.getValueType(), Reg, RC), 0);
2523 // Extract the l-register.
2524 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2528 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
2531 // For example, "testl %eax, $2048" to "testb %ah, $8".
2532 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2533 (!(C->getZExtValue() & 0x8000) ||
2534 HasNoSignedComparisonUses(Node))) {
2535 // Shift the immediate right by 8 bits.
2536 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2538 SDValue Reg = N0.getNode()->getOperand(0);
2540 // Put the value in an ABCD register.
2541 const TargetRegisterClass *TRC;
2542 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2543 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2544 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2545 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2546 default: llvm_unreachable("Unsupported TEST operand type!");
2548 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2549 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2550 Reg.getValueType(), Reg, RC), 0);
2552 // Extract the h-register.
2553 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2556 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2557 // target GR8_NOREX registers, so make sure the register class is
2559 return CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl, MVT::i32,
2560 Subreg, ShiftedImm);
2563 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2564 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2565 N0.getValueType() != MVT::i16 &&
2566 (!(C->getZExtValue() & 0x8000) ||
2567 HasNoSignedComparisonUses(Node))) {
2568 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2569 SDValue Reg = N0.getNode()->getOperand(0);
2571 // Extract the 16-bit subregister.
2572 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2576 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
2579 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2580 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2581 N0.getValueType() == MVT::i64 &&
2582 (!(C->getZExtValue() & 0x80000000) ||
2583 HasNoSignedComparisonUses(Node))) {
2584 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2585 SDValue Reg = N0.getNode()->getOperand(0);
2587 // Extract the 32-bit subregister.
2588 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2592 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
2598 // Change a chain of {load; incr or dec; store} of the same value into
2599 // a simple increment or decrement through memory of that value, if the
2600 // uses of the modified value and its address are suitable.
2601 // The DEC64m tablegen pattern is currently not able to match the case where
2602 // the EFLAGS on the original DEC are used. (This also applies to
2603 // {INC,DEC}X{64,32,16,8}.)
2604 // We'll need to improve tablegen to allow flags to be transferred from a
2605 // node in the pattern to the result node. probably with a new keyword
2606 // for example, we have this
2607 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2608 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2609 // (implicit EFLAGS)]>;
2610 // but maybe need something like this
2611 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2612 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2613 // (transferrable EFLAGS)]>;
2615 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2616 SDValue StoredVal = StoreNode->getOperand(1);
2617 unsigned Opc = StoredVal->getOpcode();
2619 LoadSDNode *LoadNode = 0;
2621 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2622 LoadNode, InputChain))
2625 SDValue Base, Scale, Index, Disp, Segment;
2626 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2627 Base, Scale, Index, Disp, Segment))
2630 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2631 MemOp[0] = StoreNode->getMemOperand();
2632 MemOp[1] = LoadNode->getMemOperand();
2633 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2634 EVT LdVT = LoadNode->getMemoryVT();
2635 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2636 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2637 Node->getDebugLoc(),
2638 MVT::i32, MVT::Other, Ops,
2639 array_lengthof(Ops));
2640 Result->setMemRefs(MemOp, MemOp + 2);
2642 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2643 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2648 // FIXME: Custom handling because TableGen doesn't support multiple implicit
2649 // defs in an instruction pattern
2650 case X86ISD::PCMPESTRI: {
2651 SDValue N0 = Node->getOperand(0);
2652 SDValue N1 = Node->getOperand(1);
2653 SDValue N2 = Node->getOperand(2);
2654 SDValue N3 = Node->getOperand(3);
2655 SDValue N4 = Node->getOperand(4);
2657 // Make sure last argument is a constant
2658 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N4);
2662 uint64_t Imm = Cst->getZExtValue();
2664 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2665 X86::EAX, N1, SDValue()).getValue(1);
2666 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::EDX,
2667 N3, InFlag).getValue(1);
2669 SDValue Ops[] = { N0, N2, getI8Imm(Imm), InFlag };
2670 unsigned Opc = Subtarget->hasAVX() ? X86::VPCMPESTRIrr :
2672 InFlag = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Ops,
2673 array_lengthof(Ops)), 0);
2675 if (!SDValue(Node, 0).use_empty()) {
2676 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2677 X86::ECX, NVT, InFlag);
2678 InFlag = Result.getValue(2);
2679 ReplaceUses(SDValue(Node, 0), Result);
2681 if (!SDValue(Node, 1).use_empty()) {
2682 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2683 X86::EFLAGS, NVT, InFlag);
2684 InFlag = Result.getValue(2);
2685 ReplaceUses(SDValue(Node, 1), Result);
2691 // FIXME: Custom handling because TableGen doesn't support multiple implicit
2692 // defs in an instruction pattern
2693 case X86ISD::PCMPISTRI: {
2694 SDValue N0 = Node->getOperand(0);
2695 SDValue N1 = Node->getOperand(1);
2696 SDValue N2 = Node->getOperand(2);
2698 // Make sure last argument is a constant
2699 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N2);
2703 uint64_t Imm = Cst->getZExtValue();
2705 SDValue Ops[] = { N0, N1, getI8Imm(Imm) };
2706 unsigned Opc = Subtarget->hasAVX() ? X86::VPCMPISTRIrr :
2708 SDValue InFlag = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Ops,
2709 array_lengthof(Ops)), 0);
2711 if (!SDValue(Node, 0).use_empty()) {
2712 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2713 X86::ECX, NVT, InFlag);
2714 InFlag = Result.getValue(2);
2715 ReplaceUses(SDValue(Node, 0), Result);
2717 if (!SDValue(Node, 1).use_empty()) {
2718 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2719 X86::EFLAGS, NVT, InFlag);
2720 InFlag = Result.getValue(2);
2721 ReplaceUses(SDValue(Node, 1), Result);
2728 SDNode *ResNode = SelectCode(Node);
2730 DEBUG(dbgs() << "=> ";
2731 if (ResNode == NULL || ResNode == Node)
2734 ResNode->dump(CurDAG);
2740 bool X86DAGToDAGISel::
2741 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2742 std::vector<SDValue> &OutOps) {
2743 SDValue Op0, Op1, Op2, Op3, Op4;
2744 switch (ConstraintCode) {
2745 case 'o': // offsetable ??
2746 case 'v': // not offsetable ??
2747 default: return true;
2749 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
2754 OutOps.push_back(Op0);
2755 OutOps.push_back(Op1);
2756 OutOps.push_back(Op2);
2757 OutOps.push_back(Op3);
2758 OutOps.push_back(Op4);
2762 /// createX86ISelDag - This pass converts a legalized DAG into a
2763 /// X86-specific DAG, ready for instruction scheduling.
2765 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2766 CodeGenOpt::Level OptLevel) {
2767 return new X86DAGToDAGISel(TM, OptLevel);