1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SSARegMap.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/Statistic.h"
43 //===----------------------------------------------------------------------===//
44 // Pattern Matcher Implementation
45 //===----------------------------------------------------------------------===//
48 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
49 /// SDOperand's instead of register numbers for the leaves of the matched
51 struct X86ISelAddressMode {
57 struct { // This is really a union, discriminated by BaseType!
62 bool isRIPRel; // RIP relative?
70 unsigned Align; // CP alignment.
73 : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
74 GV(0), CP(0), ES(0), JT(-1), Align(0) {
81 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
84 NumLoadMoved("x86-codegen", "Number of loads moved below TokenFactor");
86 //===--------------------------------------------------------------------===//
87 /// ISel - X86 specific code to select X86 machine instructions for
88 /// SelectionDAG operations.
90 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
91 /// ContainsFPCode - Every instruction we select that uses or defines a FP
92 /// register should set this to true.
95 /// FastISel - Enable fast(er) instruction selection.
99 /// TM - Keep a reference to X86TargetMachine.
101 X86TargetMachine &TM;
103 /// X86Lowering - This object fully describes how to lower LLVM code to an
104 /// X86-specific SelectionDAG.
105 X86TargetLowering X86Lowering;
107 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
108 /// make the right decision when generating code for different targets.
109 const X86Subtarget *Subtarget;
111 /// GlobalBaseReg - keeps track of the virtual register mapped onto global
113 unsigned GlobalBaseReg;
116 X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
117 : SelectionDAGISel(X86Lowering),
118 ContainsFPCode(false), FastISel(fast), TM(tm),
119 X86Lowering(*TM.getTargetLowering()),
120 Subtarget(&TM.getSubtarget<X86Subtarget>()) {}
122 virtual bool runOnFunction(Function &Fn) {
123 // Make sure we re-emit a set of the global base reg if necessary
125 return SelectionDAGISel::runOnFunction(Fn);
128 virtual const char *getPassName() const {
129 return "X86 DAG->DAG Instruction Selection";
132 /// InstructionSelectBasicBlock - This callback is invoked by
133 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
134 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
136 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
138 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U);
140 // Include the pieces autogenerated from the target description.
141 #include "X86GenDAGISel.inc"
144 SDNode *Select(SDOperand N);
146 bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
147 bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
148 SDOperand &Index, SDOperand &Disp);
149 bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
150 SDOperand &Index, SDOperand &Disp);
151 bool TryFoldLoad(SDOperand P, SDOperand N,
152 SDOperand &Base, SDOperand &Scale,
153 SDOperand &Index, SDOperand &Disp);
154 void InstructionSelectPreprocess(SelectionDAG &DAG);
156 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
157 /// inline asm expressions.
158 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
160 std::vector<SDOperand> &OutOps,
163 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
165 inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
166 SDOperand &Scale, SDOperand &Index,
168 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
169 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
171 Scale = getI8Imm(AM.Scale);
173 // These are 32-bit even in 64-bit mode since RIP relative offset
176 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp);
178 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp);
180 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32);
181 else if (AM.JT != -1)
182 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
184 Disp = getI32Imm(AM.Disp);
187 /// getI8Imm - Return a target constant with the specified value, of type
189 inline SDOperand getI8Imm(unsigned Imm) {
190 return CurDAG->getTargetConstant(Imm, MVT::i8);
193 /// getI16Imm - Return a target constant with the specified value, of type
195 inline SDOperand getI16Imm(unsigned Imm) {
196 return CurDAG->getTargetConstant(Imm, MVT::i16);
199 /// getI32Imm - Return a target constant with the specified value, of type
201 inline SDOperand getI32Imm(unsigned Imm) {
202 return CurDAG->getTargetConstant(Imm, MVT::i32);
205 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
206 /// base register. Return the virtual register that holds this value.
207 SDNode *getGlobalBaseReg();
215 static void findNonImmUse(SDNode* Use, SDNode* Def, bool &found,
216 std::set<SDNode *> &Visited) {
218 Use->getNodeId() > Def->getNodeId() ||
219 !Visited.insert(Use).second)
222 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
223 SDNode *N = Use->getOperand(i).Val;
225 findNonImmUse(N, Def, found, Visited);
233 static inline bool isNonImmUse(SDNode* Use, SDNode* Def) {
234 std::set<SDNode *> Visited;
236 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
237 SDNode *N = Use->getOperand(i).Val;
239 findNonImmUse(N, Def, found, Visited);
247 bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U) {
248 // If U use can somehow reach N through another path then U can't fold N or
249 // it will create a cycle. e.g. In the following diagram, U can reach N
250 // through X. If N is folded into into U, then X is both a predecessor and
260 return !FastISel && !isNonImmUse(U, N);
263 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
264 /// and move load below the TokenFactor. Replace store's chain operand with
265 /// load's chain result.
266 static void MoveBelowTokenFactor(SelectionDAG &DAG, SDOperand Load,
267 SDOperand Store, SDOperand TF) {
268 std::vector<SDOperand> Ops;
269 for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
270 if (Load.Val == TF.Val->getOperand(i).Val)
271 Ops.push_back(Load.Val->getOperand(0));
273 Ops.push_back(TF.Val->getOperand(i));
274 DAG.UpdateNodeOperands(TF, &Ops[0], Ops.size());
275 DAG.UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
276 DAG.UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
277 Store.getOperand(2), Store.getOperand(3));
280 /// InstructionSelectPreprocess - Preprocess the DAG to allow the instruction
281 /// selector to pick more load-modify-store instructions. This is a common
292 /// [TokenFactor] [Op]
299 /// The fact the store's chain operand != load's chain will prevent the
300 /// (store (op (load))) instruction from being selected. We can transform it to:
319 void X86DAGToDAGISel::InstructionSelectPreprocess(SelectionDAG &DAG) {
320 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
321 E = DAG.allnodes_end(); I != E; ++I) {
322 if (I->getOpcode() != ISD::STORE)
324 SDOperand Chain = I->getOperand(0);
325 if (Chain.Val->getOpcode() != ISD::TokenFactor)
328 SDOperand N1 = I->getOperand(1);
329 SDOperand N2 = I->getOperand(2);
330 if (MVT::isFloatingPoint(N1.getValueType()) ||
331 MVT::isVector(N1.getValueType()) ||
337 unsigned Opcode = N1.Val->getOpcode();
346 SDOperand N10 = N1.getOperand(0);
347 SDOperand N11 = N1.getOperand(1);
348 if (N10.Val->getOpcode() == ISD::LOAD)
350 else if (N11.Val->getOpcode() == ISD::LOAD) {
354 RModW = RModW && N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
355 (N10.getOperand(1) == N2) &&
356 (N10.Val->getValueType(0) == N1.getValueType());
371 SDOperand N10 = N1.getOperand(0);
372 if (N10.Val->getOpcode() == ISD::LOAD)
373 RModW = N10.Val->isOperand(Chain.Val) && N10.hasOneUse() &&
374 (N10.getOperand(1) == N2) &&
375 (N10.Val->getValueType(0) == N1.getValueType());
383 MoveBelowTokenFactor(DAG, Load, SDOperand(I, 0), Chain);
389 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
390 /// when it has created a SelectionDAG for us to codegen.
391 void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
393 MachineFunction::iterator FirstMBB = BB;
396 InstructionSelectPreprocess(DAG);
398 // Codegen the basic block.
400 DEBUG(std::cerr << "===== Instruction selection begins:\n");
403 DAG.setRoot(SelectRoot(DAG.getRoot()));
405 DEBUG(std::cerr << "===== Instruction selection ends:\n");
408 DAG.RemoveDeadNodes();
410 // Emit machine code to BB.
411 ScheduleAndEmitDAG(DAG);
413 // If we are emitting FP stack code, scan the basic block to determine if this
414 // block defines any FP values. If so, put an FP_REG_KILL instruction before
415 // the terminator of the block.
416 if (!Subtarget->hasSSE2()) {
417 // Note that FP stack instructions *are* used in SSE code when returning
418 // values, but these are not live out of the basic block, so we don't need
419 // an FP_REG_KILL in this case either.
420 bool ContainsFPCode = false;
422 // Scan all of the machine instructions in these MBBs, checking for FP
424 MachineFunction::iterator MBBI = FirstMBB;
426 for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
427 !ContainsFPCode && I != E; ++I) {
428 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
429 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
430 MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
431 RegMap->getRegClass(I->getOperand(0).getReg()) ==
432 X86::RFPRegisterClass) {
433 ContainsFPCode = true;
438 } while (!ContainsFPCode && &*(MBBI++) != BB);
440 // Check PHI nodes in successor blocks. These PHI's will be lowered to have
441 // a copy of the input value in this block.
442 if (!ContainsFPCode) {
443 // Final check, check LLVM BB's that are successors to the LLVM BB
444 // corresponding to BB for FP PHI nodes.
445 const BasicBlock *LLVMBB = BB->getBasicBlock();
447 for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
448 !ContainsFPCode && SI != E; ++SI) {
449 for (BasicBlock::const_iterator II = SI->begin();
450 (PN = dyn_cast<PHINode>(II)); ++II) {
451 if (PN->getType()->isFloatingPoint()) {
452 ContainsFPCode = true;
459 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
460 if (ContainsFPCode) {
461 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
467 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
468 /// the main function.
469 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
470 MachineFrameInfo *MFI) {
471 if (Subtarget->TargetType == X86Subtarget::isCygwin)
472 BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("__main");
474 // Switch the FPU to 64-bit precision mode for better compatibility and speed.
475 int CWFrameIdx = MFI->CreateStackObject(2, 2);
476 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
478 // Set the high part to be 64-bit precision.
479 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
480 CWFrameIdx, 1).addImm(2);
482 // Reload the modified control word now.
483 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
486 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
487 // If this is main, emit special code for main.
488 MachineBasicBlock *BB = MF.begin();
489 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
490 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
493 /// MatchAddress - Add the specified node to the specified addressing mode,
494 /// returning true if it cannot be done. This just pattern matches for the
496 bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
498 // RIP relative addressing: %rip + 32-bit displacement!
500 if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
501 int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
502 if (isInt32(AM.Disp + Val)) {
510 int id = N.Val->getNodeId();
511 bool Available = isSelected(id);
513 switch (N.getOpcode()) {
515 case ISD::Constant: {
516 int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
517 if (isInt32(AM.Disp + Val)) {
524 case X86ISD::Wrapper:
525 // If value is available in a register both base and index components have
526 // been picked, we can't fit the result available in the register in the
527 // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
529 // Can't fit GV or CP in addressing mode for X86-64 medium or large code
530 // model since the displacement field is 32-bit. Ok for small code model.
532 // For X86-64 PIC code, only allow GV / CP + displacement so we can use RIP
533 // relative addressing mode.
534 if ((!Subtarget->is64Bit() || TM.getCodeModel() == CodeModel::Small) &&
535 (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val))) {
536 bool isRIP = Subtarget->is64Bit();
537 if (isRIP && (AM.Base.Reg.Val || AM.Scale > 1 || AM.IndexReg.Val ||
538 AM.BaseType == X86ISelAddressMode::FrameIndexBase))
540 if (ConstantPoolSDNode *CP =
541 dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
543 AM.CP = CP->getConstVal();
544 AM.Align = CP->getAlignment();
545 AM.Disp += CP->getOffset();
550 } else if (GlobalAddressSDNode *G =
551 dyn_cast<GlobalAddressSDNode>(N.getOperand(0))) {
553 AM.GV = G->getGlobal();
554 AM.Disp += G->getOffset();
559 } else if (isRoot && isRIP) {
560 if (ExternalSymbolSDNode *S =
561 dyn_cast<ExternalSymbolSDNode>(N.getOperand(0))) {
562 AM.ES = S->getSymbol();
565 } else if (JumpTableSDNode *J =
566 dyn_cast<JumpTableSDNode>(N.getOperand(0))) {
567 AM.JT = J->getIndex();
575 case ISD::FrameIndex:
576 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
577 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
578 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
584 if (!Available && AM.IndexReg.Val == 0 && AM.Scale == 1)
585 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
586 unsigned Val = CN->getValue();
587 if (Val == 1 || Val == 2 || Val == 3) {
589 SDOperand ShVal = N.Val->getOperand(0);
591 // Okay, we know that we have a scale by now. However, if the scaled
592 // value is an add of something and a constant, we can fold the
593 // constant into the disp field here.
594 if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
595 isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
596 AM.IndexReg = ShVal.Val->getOperand(0);
597 ConstantSDNode *AddVal =
598 cast<ConstantSDNode>(ShVal.Val->getOperand(1));
599 uint64_t Disp = AM.Disp + AddVal->getValue() << Val;
613 // X*[3,5,9] -> X+X*[2,4,8]
615 AM.BaseType == X86ISelAddressMode::RegBase &&
616 AM.Base.Reg.Val == 0 &&
617 AM.IndexReg.Val == 0)
618 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
619 if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
620 AM.Scale = unsigned(CN->getValue())-1;
622 SDOperand MulVal = N.Val->getOperand(0);
625 // Okay, we know that we have a scale by now. However, if the scaled
626 // value is an add of something and a constant, we can fold the
627 // constant into the disp field here.
628 if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
629 isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
630 Reg = MulVal.Val->getOperand(0);
631 ConstantSDNode *AddVal =
632 cast<ConstantSDNode>(MulVal.Val->getOperand(1));
633 uint64_t Disp = AM.Disp + AddVal->getValue() * CN->getValue();
637 Reg = N.Val->getOperand(0);
639 Reg = N.Val->getOperand(0);
642 AM.IndexReg = AM.Base.Reg = Reg;
649 X86ISelAddressMode Backup = AM;
650 if (!MatchAddress(N.Val->getOperand(0), AM, false) &&
651 !MatchAddress(N.Val->getOperand(1), AM, false))
654 if (!MatchAddress(N.Val->getOperand(1), AM, false) &&
655 !MatchAddress(N.Val->getOperand(0), AM, false))
664 X86ISelAddressMode Backup = AM;
665 // Look for (x << c1) | c2 where (c2 < c1)
666 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(0));
667 if (CN && !MatchAddress(N.Val->getOperand(1), AM, false)) {
668 if (AM.GV == NULL && AM.Disp == 0 && CN->getValue() < AM.Scale) {
669 AM.Disp = CN->getValue();
674 CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1));
675 if (CN && !MatchAddress(N.Val->getOperand(0), AM, false)) {
676 if (AM.GV == NULL && AM.Disp == 0 && CN->getValue() < AM.Scale) {
677 AM.Disp = CN->getValue();
687 // Is the base register already occupied?
688 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
689 // If so, check to see if the scale index register is set.
690 if (AM.IndexReg.Val == 0) {
696 // Otherwise, we cannot select it.
700 // Default, generate it as a register.
701 AM.BaseType = X86ISelAddressMode::RegBase;
706 /// SelectAddr - returns true if it is able pattern match an addressing mode.
707 /// It returns the operands which make up the maximal addressing mode it can
708 /// match by reference.
709 bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
710 SDOperand &Index, SDOperand &Disp) {
711 X86ISelAddressMode AM;
712 if (MatchAddress(N, AM))
715 MVT::ValueType VT = N.getValueType();
716 if (AM.BaseType == X86ISelAddressMode::RegBase) {
717 if (!AM.Base.Reg.Val)
718 AM.Base.Reg = CurDAG->getRegister(0, VT);
721 if (!AM.IndexReg.Val)
722 AM.IndexReg = CurDAG->getRegister(0, VT);
724 getAddressOperands(AM, Base, Scale, Index, Disp);
728 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
729 /// mode it matches can be cost effectively emitted as an LEA instruction.
730 bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
732 SDOperand &Index, SDOperand &Disp) {
733 X86ISelAddressMode AM;
734 if (MatchAddress(N, AM))
737 MVT::ValueType VT = N.getValueType();
738 unsigned Complexity = 0;
739 if (AM.BaseType == X86ISelAddressMode::RegBase)
743 AM.Base.Reg = CurDAG->getRegister(0, VT);
744 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
750 AM.IndexReg = CurDAG->getRegister(0, VT);
754 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg
755 else if (AM.Scale > 1)
758 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
759 // to a LEA. This is determined with some expermentation but is by no means
760 // optimal (especially for code size consideration). LEA is nice because of
761 // its three-address nature. Tweak the cost function again when we can run
762 // convertToThreeAddress() at register allocation time.
763 if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
764 // For X86-64, we should always use lea to materialize RIP relative
766 if (Subtarget->is64Bit())
772 if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
775 if (Complexity > 2) {
776 getAddressOperands(AM, Base, Scale, Index, Disp);
782 bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
783 SDOperand &Base, SDOperand &Scale,
784 SDOperand &Index, SDOperand &Disp) {
785 if (N.getOpcode() == ISD::LOAD &&
787 P.Val->isOnlyUse(N.Val) &&
788 CanBeFoldedBy(N.Val, P.Val))
789 return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
793 static bool isRegister0(SDOperand Op) {
794 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
795 return (R->getReg() == 0);
799 /// getGlobalBaseReg - Output the instructions required to put the
800 /// base address to use for accessing globals into a register.
802 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
803 assert(!Subtarget->is64Bit() && "X86-64 PIC uses RIP relative addressing");
804 if (!GlobalBaseReg) {
805 // Insert the set of GlobalBaseReg into the first MBB of the function
806 MachineBasicBlock &FirstMBB = BB->getParent()->front();
807 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
808 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
809 // FIXME: when we get to LP64, we will need to create the appropriate
810 // type of register here.
811 GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
812 BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
813 BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
815 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).Val;
818 static SDNode *FindCallStartFromCall(SDNode *Node) {
819 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
820 assert(Node->getOperand(0).getValueType() == MVT::Other &&
821 "Node doesn't have a token chain argument!");
822 return FindCallStartFromCall(Node->getOperand(0).Val);
825 SDNode *X86DAGToDAGISel::Select(SDOperand N) {
826 SDNode *Node = N.Val;
827 MVT::ValueType NVT = Node->getValueType(0);
829 unsigned Opcode = Node->getOpcode();
832 DEBUG(std::cerr << std::string(Indent, ' '));
833 DEBUG(std::cerr << "Selecting: ");
834 DEBUG(Node->dump(CurDAG));
835 DEBUG(std::cerr << "\n");
839 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) {
841 DEBUG(std::cerr << std::string(Indent-2, ' '));
842 DEBUG(std::cerr << "== ");
843 DEBUG(Node->dump(CurDAG));
844 DEBUG(std::cerr << "\n");
847 return NULL; // Already selected.
852 case X86ISD::GlobalBaseReg:
853 return getGlobalBaseReg();
856 // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
857 // code and is matched first so to prevent it from being turned into
859 // In 64-bit mode, use LEA to take advantage of RIP-relative addressing.
860 MVT::ValueType PtrVT = TLI.getPointerTy();
861 SDOperand N0 = N.getOperand(0);
862 SDOperand N1 = N.getOperand(1);
863 if (N.Val->getValueType(0) == PtrVT &&
864 N0.getOpcode() == X86ISD::Wrapper &&
865 N1.getOpcode() == ISD::Constant) {
866 unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
868 // TODO: handle ExternalSymbolSDNode.
869 if (GlobalAddressSDNode *G =
870 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
871 C = CurDAG->getTargetGlobalAddress(G->getGlobal(), PtrVT,
872 G->getOffset() + Offset);
873 } else if (ConstantPoolSDNode *CP =
874 dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
875 C = CurDAG->getTargetConstantPool(CP->getConstVal(), PtrVT,
877 CP->getOffset()+Offset);
881 if (Subtarget->is64Bit()) {
882 SDOperand Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
883 CurDAG->getRegister(0, PtrVT), C };
884 return CurDAG->SelectNodeTo(N.Val, X86::LEA64r, MVT::i64, Ops, 4);
886 return CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, PtrVT, C);
890 // Other cases are handled by auto-generated code.
896 if (Opcode == ISD::MULHU)
898 default: assert(0 && "Unsupported VT!");
899 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
900 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
901 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
902 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
906 default: assert(0 && "Unsupported VT!");
907 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
908 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
909 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
910 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
913 unsigned LoReg, HiReg;
915 default: assert(0 && "Unsupported VT!");
916 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
917 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
918 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
919 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
922 SDOperand N0 = Node->getOperand(0);
923 SDOperand N1 = Node->getOperand(1);
925 bool foldedLoad = false;
926 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
927 foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
928 // MULHU and MULHS are commmutative
930 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
932 N0 = Node->getOperand(1);
933 N1 = Node->getOperand(0);
939 Chain = N1.getOperand(0);
940 AddToISelQueue(Chain);
942 Chain = CurDAG->getEntryNode();
944 SDOperand InFlag(0, 0);
946 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
948 InFlag = Chain.getValue(1);
951 AddToISelQueue(Tmp0);
952 AddToISelQueue(Tmp1);
953 AddToISelQueue(Tmp2);
954 AddToISelQueue(Tmp3);
955 SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
957 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
958 Chain = SDOperand(CNode, 0);
959 InFlag = SDOperand(CNode, 1);
963 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
966 SDOperand Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
967 ReplaceUses(N.getValue(0), Result);
969 ReplaceUses(N1.getValue(1), Result.getValue(1));
972 DEBUG(std::cerr << std::string(Indent-2, ' '));
973 DEBUG(std::cerr << "=> ");
974 DEBUG(Result.Val->dump(CurDAG));
975 DEBUG(std::cerr << "\n");
985 bool isSigned = Opcode == ISD::SDIV || Opcode == ISD::SREM;
986 bool isDiv = Opcode == ISD::SDIV || Opcode == ISD::UDIV;
989 default: assert(0 && "Unsupported VT!");
990 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
991 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
992 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
993 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
997 default: assert(0 && "Unsupported VT!");
998 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
999 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1000 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1001 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1004 unsigned LoReg, HiReg;
1005 unsigned ClrOpcode, SExtOpcode;
1007 default: assert(0 && "Unsupported VT!");
1009 LoReg = X86::AL; HiReg = X86::AH;
1010 ClrOpcode = X86::MOV8r0;
1011 SExtOpcode = X86::CBW;
1014 LoReg = X86::AX; HiReg = X86::DX;
1015 ClrOpcode = X86::MOV16r0;
1016 SExtOpcode = X86::CWD;
1019 LoReg = X86::EAX; HiReg = X86::EDX;
1020 ClrOpcode = X86::MOV32r0;
1021 SExtOpcode = X86::CDQ;
1024 LoReg = X86::RAX; HiReg = X86::RDX;
1025 ClrOpcode = X86::MOV64r0;
1026 SExtOpcode = X86::CQO;
1030 SDOperand N0 = Node->getOperand(0);
1031 SDOperand N1 = Node->getOperand(1);
1033 bool foldedLoad = false;
1034 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
1035 foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1038 Chain = N1.getOperand(0);
1039 AddToISelQueue(Chain);
1041 Chain = CurDAG->getEntryNode();
1043 SDOperand InFlag(0, 0);
1045 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
1047 InFlag = Chain.getValue(1);
1050 // Sign extend the low part into the high part.
1052 SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
1054 // Zero out the high part, effectively zero extending the input.
1055 SDOperand ClrNode = SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
1056 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT),
1058 InFlag = Chain.getValue(1);
1062 AddToISelQueue(Tmp0);
1063 AddToISelQueue(Tmp1);
1064 AddToISelQueue(Tmp2);
1065 AddToISelQueue(Tmp3);
1066 SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
1068 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
1069 Chain = SDOperand(CNode, 0);
1070 InFlag = SDOperand(CNode, 1);
1074 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
1077 SDOperand Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
1079 ReplaceUses(N.getValue(0), Result);
1081 ReplaceUses(N1.getValue(1), Result.getValue(1));
1084 DEBUG(std::cerr << std::string(Indent-2, ' '));
1085 DEBUG(std::cerr << "=> ");
1086 DEBUG(Result.Val->dump(CurDAG));
1087 DEBUG(std::cerr << "\n");
1094 case ISD::TRUNCATE: {
1095 if (!Subtarget->is64Bit() && NVT == MVT::i8) {
1098 switch (Node->getOperand(0).getValueType()) {
1099 default: assert(0 && "Unknown truncate!");
1101 Opc = X86::MOV16to16_;
1103 Opc2 = X86::TRUNC_16_to8;
1106 Opc = X86::MOV32to32_;
1108 Opc2 = X86::TRUNC_32_to8;
1112 AddToISelQueue(Node->getOperand(0));
1114 SDOperand(CurDAG->getTargetNode(Opc, VT, Node->getOperand(0)), 0);
1115 SDNode *ResNode = CurDAG->getTargetNode(Opc2, NVT, Tmp);
1118 DEBUG(std::cerr << std::string(Indent-2, ' '));
1119 DEBUG(std::cerr << "=> ");
1120 DEBUG(ResNode->dump(CurDAG));
1121 DEBUG(std::cerr << "\n");
1131 SDNode *ResNode = SelectCode(N);
1134 DEBUG(std::cerr << std::string(Indent-2, ' '));
1135 DEBUG(std::cerr << "=> ");
1136 if (ResNode == NULL || ResNode == N.Val)
1137 DEBUG(N.Val->dump(CurDAG));
1139 DEBUG(ResNode->dump(CurDAG));
1140 DEBUG(std::cerr << "\n");
1147 bool X86DAGToDAGISel::
1148 SelectInlineAsmMemoryOperand(const SDOperand &Op, char ConstraintCode,
1149 std::vector<SDOperand> &OutOps, SelectionDAG &DAG){
1150 SDOperand Op0, Op1, Op2, Op3;
1151 switch (ConstraintCode) {
1152 case 'o': // offsetable ??
1153 case 'v': // not offsetable ??
1154 default: return true;
1156 if (!SelectAddr(Op, Op0, Op1, Op2, Op3))
1161 OutOps.push_back(Op0);
1162 OutOps.push_back(Op1);
1163 OutOps.push_back(Op2);
1164 OutOps.push_back(Op3);
1165 AddToISelQueue(Op0);
1166 AddToISelQueue(Op1);
1167 AddToISelQueue(Op2);
1168 AddToISelQueue(Op3);
1172 /// createX86ISelDag - This pass converts a legalized DAG into a
1173 /// X86-specific DAG, ready for instruction scheduling.
1175 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
1176 return new X86DAGToDAGISel(TM, Fast);