1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "x86-isel"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
77 JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != nullptr || CP != nullptr || ES != nullptr ||
82 JT != -1 || BlockAddr != nullptr;
85 bool hasBaseOrIndexReg() const {
86 return BaseType == FrameIndexBase ||
87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
90 /// isRIPRelative - Return true if this addressing mode is already RIP
92 bool isRIPRelative() const {
93 if (BaseType != RegBase) return false;
94 if (RegisterSDNode *RegNode =
95 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
96 return RegNode->getReg() == X86::RIP;
100 void setBaseReg(SDValue Reg) {
105 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
107 dbgs() << "X86ISelAddressMode " << this << '\n';
108 dbgs() << "Base_Reg ";
109 if (Base_Reg.getNode())
110 Base_Reg.getNode()->dump();
113 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
114 << " Scale" << Scale << '\n'
116 if (IndexReg.getNode())
117 IndexReg.getNode()->dump();
120 dbgs() << " Disp " << Disp << '\n'
137 dbgs() << " JT" << JT << " Align" << Align << '\n';
144 //===--------------------------------------------------------------------===//
145 /// ISel - X86 specific code to select X86 machine instructions for
146 /// SelectionDAG operations.
148 class X86DAGToDAGISel final : public SelectionDAGISel {
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel), OptForSize(false) {}
161 const char *getPassName() const override {
162 return "X86 DAG->DAG Instruction Selection";
165 bool runOnMachineFunction(MachineFunction &MF) override {
166 // Reset the subtarget each time through.
167 Subtarget = &MF.getSubtarget<X86Subtarget>();
168 SelectionDAGISel::runOnMachineFunction(MF);
172 void EmitFunctionEntryCode() override;
174 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
176 void PreprocessISelDAG() override;
178 inline bool immSext8(SDNode *N) const {
179 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
182 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
183 // sign extended field.
184 inline bool i64immSExt32(SDNode *N) const {
185 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
186 return (int64_t)v == (int32_t)v;
189 // Include the pieces autogenerated from the target description.
190 #include "X86GenDAGISel.inc"
193 SDNode *Select(SDNode *N) override;
194 SDNode *SelectGather(SDNode *N, unsigned Opc);
195 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
197 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
198 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
199 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
200 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
201 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
203 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
204 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
208 bool SelectLEAAddr(SDValue N, SDValue &Base,
209 SDValue &Scale, SDValue &Index, SDValue &Disp,
211 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
212 SDValue &Scale, SDValue &Index, SDValue &Disp,
214 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
215 SDValue &Scale, SDValue &Index, SDValue &Disp,
217 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
218 SDValue &Base, SDValue &Scale,
219 SDValue &Index, SDValue &Disp,
221 SDValue &NodeWithChain);
223 bool TryFoldLoad(SDNode *P, SDValue N,
224 SDValue &Base, SDValue &Scale,
225 SDValue &Index, SDValue &Disp,
228 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
229 /// inline asm expressions.
230 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
232 std::vector<SDValue> &OutOps) override;
234 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
236 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
237 SDValue &Scale, SDValue &Index,
238 SDValue &Disp, SDValue &Segment) {
239 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
240 ? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
243 Scale = getI8Imm(AM.Scale);
245 // These are 32-bit even in 64-bit mode since RIP relative offset
248 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
252 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
253 AM.Align, AM.Disp, AM.SymbolFlags);
255 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
256 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
257 } else if (AM.JT != -1) {
258 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
259 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
260 } else if (AM.BlockAddr)
261 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
264 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
266 if (AM.Segment.getNode())
267 Segment = AM.Segment;
269 Segment = CurDAG->getRegister(0, MVT::i32);
272 /// getI8Imm - Return a target constant with the specified value, of type
274 inline SDValue getI8Imm(unsigned Imm) {
275 return CurDAG->getTargetConstant(Imm, MVT::i8);
278 /// getI32Imm - Return a target constant with the specified value, of type
280 inline SDValue getI32Imm(unsigned Imm) {
281 return CurDAG->getTargetConstant(Imm, MVT::i32);
284 /// getGlobalBaseReg - Return an SDNode that returns the value of
285 /// the global base register. Output instructions required to
286 /// initialize the global base register, if necessary.
288 SDNode *getGlobalBaseReg();
290 /// getTargetMachine - Return a reference to the TargetMachine, casted
291 /// to the target-specific type.
292 const X86TargetMachine &getTargetMachine() const {
293 return static_cast<const X86TargetMachine &>(TM);
296 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
297 /// to the target-specific type.
298 const X86InstrInfo *getInstrInfo() const {
299 return Subtarget->getInstrInfo();
302 /// \brief Address-mode matching performs shift-of-and to and-of-shift
303 /// reassociation in order to expose more scaled addressing
305 bool ComplexPatternFuncMutatesDAG() const override {
313 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
314 if (OptLevel == CodeGenOpt::None) return false;
319 if (N.getOpcode() != ISD::LOAD)
322 // If N is a load, do additional profitability checks.
324 switch (U->getOpcode()) {
337 SDValue Op1 = U->getOperand(1);
339 // If the other operand is a 8-bit immediate we should fold the immediate
340 // instead. This reduces code size.
342 // movl 4(%esp), %eax
346 // addl 4(%esp), %eax
347 // The former is 2 bytes shorter. In case where the increment is 1, then
348 // the saving can be 4 bytes (by using incl %eax).
349 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
350 if (Imm->getAPIntValue().isSignedIntN(8))
353 // If the other operand is a TLS address, we should fold it instead.
356 // leal i@NTPOFF(%eax), %eax
358 // movl $i@NTPOFF, %eax
360 // if the block also has an access to a second TLS address this will save
362 // FIXME: This is probably also true for non-TLS addresses.
363 if (Op1.getOpcode() == X86ISD::Wrapper) {
364 SDValue Val = Op1.getOperand(0);
365 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
375 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
376 /// load's chain operand and move load below the call's chain operand.
377 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
378 SDValue Call, SDValue OrigChain) {
379 SmallVector<SDValue, 8> Ops;
380 SDValue Chain = OrigChain.getOperand(0);
381 if (Chain.getNode() == Load.getNode())
382 Ops.push_back(Load.getOperand(0));
384 assert(Chain.getOpcode() == ISD::TokenFactor &&
385 "Unexpected chain operand");
386 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
387 if (Chain.getOperand(i).getNode() == Load.getNode())
388 Ops.push_back(Load.getOperand(0));
390 Ops.push_back(Chain.getOperand(i));
392 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
394 Ops.push_back(NewChain);
396 Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end());
397 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
398 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
399 Load.getOperand(1), Load.getOperand(2));
402 Ops.push_back(SDValue(Load.getNode(), 1));
403 Ops.append(Call->op_begin() + 1, Call->op_end());
404 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
407 /// isCalleeLoad - Return true if call address is a load and it can be
408 /// moved below CALLSEQ_START and the chains leading up to the call.
409 /// Return the CALLSEQ_START by reference as a second output.
410 /// In the case of a tail call, there isn't a callseq node between the call
411 /// chain and the load.
412 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
413 // The transformation is somewhat dangerous if the call's chain was glued to
414 // the call. After MoveBelowOrigChain the load is moved between the call and
415 // the chain, this can create a cycle if the load is not folded. So it is
416 // *really* important that we are sure the load will be folded.
417 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
419 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
422 LD->getAddressingMode() != ISD::UNINDEXED ||
423 LD->getExtensionType() != ISD::NON_EXTLOAD)
426 // Now let's find the callseq_start.
427 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
428 if (!Chain.hasOneUse())
430 Chain = Chain.getOperand(0);
433 if (!Chain.getNumOperands())
435 // Since we are not checking for AA here, conservatively abort if the chain
436 // writes to memory. It's not safe to move the callee (a load) across a store.
437 if (isa<MemSDNode>(Chain.getNode()) &&
438 cast<MemSDNode>(Chain.getNode())->writeMem())
440 if (Chain.getOperand(0).getNode() == Callee.getNode())
442 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
443 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
444 Callee.getValue(1).hasOneUse())
449 void X86DAGToDAGISel::PreprocessISelDAG() {
450 // OptForSize is used in pattern predicates that isel is matching.
451 OptForSize = MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
453 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
454 E = CurDAG->allnodes_end(); I != E; ) {
455 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
457 if (OptLevel != CodeGenOpt::None &&
458 // Only does this when target favors doesn't favor register indirect
460 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
461 (N->getOpcode() == X86ISD::TC_RETURN &&
462 // Only does this if load can be folded into TC_RETURN.
463 (Subtarget->is64Bit() ||
464 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
465 /// Also try moving call address load from outside callseq_start to just
466 /// before the call to allow it to be folded.
484 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
485 SDValue Chain = N->getOperand(0);
486 SDValue Load = N->getOperand(1);
487 if (!isCalleeLoad(Load, Chain, HasCallSeq))
489 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
494 // Lower fpround and fpextend nodes that target the FP stack to be store and
495 // load to the stack. This is a gross hack. We would like to simply mark
496 // these as being illegal, but when we do that, legalize produces these when
497 // it expands calls, then expands these in the same legalize pass. We would
498 // like dag combine to be able to hack on these between the call expansion
499 // and the node legalization. As such this pass basically does "really
500 // late" legalization of these inline with the X86 isel pass.
501 // FIXME: This should only happen when not compiled with -O0.
502 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
505 MVT SrcVT = N->getOperand(0).getSimpleValueType();
506 MVT DstVT = N->getSimpleValueType(0);
508 // If any of the sources are vectors, no fp stack involved.
509 if (SrcVT.isVector() || DstVT.isVector())
512 // If the source and destination are SSE registers, then this is a legal
513 // conversion that should not be lowered.
514 const X86TargetLowering *X86Lowering =
515 static_cast<const X86TargetLowering *>(TLI);
516 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
517 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
518 if (SrcIsSSE && DstIsSSE)
521 if (!SrcIsSSE && !DstIsSSE) {
522 // If this is an FPStack extension, it is a noop.
523 if (N->getOpcode() == ISD::FP_EXTEND)
525 // If this is a value-preserving FPStack truncation, it is a noop.
526 if (N->getConstantOperandVal(1))
530 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
531 // FPStack has extload and truncstore. SSE can fold direct loads into other
532 // operations. Based on this, decide what we want to do.
534 if (N->getOpcode() == ISD::FP_ROUND)
535 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
537 MemVT = SrcIsSSE ? SrcVT : DstVT;
539 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
542 // FIXME: optimize the case where the src/dest is a load or store?
543 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
545 MemTmp, MachinePointerInfo(), MemVT,
547 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
548 MachinePointerInfo(),
549 MemVT, false, false, false, 0);
551 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
552 // extload we created. This will cause general havok on the dag because
553 // anything below the conversion could be folded into other existing nodes.
554 // To avoid invalidating 'I', back it up to the convert node.
556 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
558 // Now that we did that, the node is dead. Increment the iterator to the
559 // next node to process, then delete N.
561 CurDAG->DeleteNode(N);
566 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
567 /// the main function.
568 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
569 MachineFrameInfo *MFI) {
570 const TargetInstrInfo *TII = getInstrInfo();
571 if (Subtarget->isTargetCygMing()) {
573 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
574 BuildMI(BB, DebugLoc(),
575 TII->get(CallOp)).addExternalSymbol("__main");
579 void X86DAGToDAGISel::EmitFunctionEntryCode() {
580 // If this is main, emit special code for main.
581 if (const Function *Fn = MF->getFunction())
582 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
583 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
586 static bool isDispSafeForFrameIndex(int64_t Val) {
587 // On 64-bit platforms, we can run into an issue where a frame index
588 // includes a displacement that, when added to the explicit displacement,
589 // will overflow the displacement field. Assuming that the frame index
590 // displacement fits into a 31-bit integer (which is only slightly more
591 // aggressive than the current fundamental assumption that it fits into
592 // a 32-bit integer), a 31-bit disp should always be safe.
593 return isInt<31>(Val);
596 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
597 X86ISelAddressMode &AM) {
598 int64_t Val = AM.Disp + Offset;
599 CodeModel::Model M = TM.getCodeModel();
600 if (Subtarget->is64Bit()) {
601 if (!X86::isOffsetSuitableForCodeModel(Val, M,
602 AM.hasSymbolicDisplacement()))
604 // In addition to the checks required for a register base, check that
605 // we do not try to use an unsafe Disp with a frame index.
606 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
607 !isDispSafeForFrameIndex(Val))
615 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
616 SDValue Address = N->getOperand(1);
618 // load gs:0 -> GS segment register.
619 // load fs:0 -> FS segment register.
621 // This optimization is valid because the GNU TLS model defines that
622 // gs:0 (or fs:0 on X86-64) contains its own address.
623 // For more information see http://people.redhat.com/drepper/tls.pdf
624 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
625 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
626 Subtarget->isTargetLinux())
627 switch (N->getPointerInfo().getAddrSpace()) {
629 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
632 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
639 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
640 /// into an addressing mode. These wrap things that will resolve down into a
641 /// symbol reference. If no match is possible, this returns true, otherwise it
643 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
644 // If the addressing mode already has a symbol as the displacement, we can
645 // never match another symbol.
646 if (AM.hasSymbolicDisplacement())
649 SDValue N0 = N.getOperand(0);
650 CodeModel::Model M = TM.getCodeModel();
652 // Handle X86-64 rip-relative addresses. We check this before checking direct
653 // folding because RIP is preferable to non-RIP accesses.
654 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
655 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
656 // they cannot be folded into immediate fields.
657 // FIXME: This can be improved for kernel and other models?
658 (M == CodeModel::Small || M == CodeModel::Kernel)) {
659 // Base and index reg must be 0 in order to use %rip as base.
660 if (AM.hasBaseOrIndexReg())
662 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
663 X86ISelAddressMode Backup = AM;
664 AM.GV = G->getGlobal();
665 AM.SymbolFlags = G->getTargetFlags();
666 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
670 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
671 X86ISelAddressMode Backup = AM;
672 AM.CP = CP->getConstVal();
673 AM.Align = CP->getAlignment();
674 AM.SymbolFlags = CP->getTargetFlags();
675 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
679 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
680 AM.ES = S->getSymbol();
681 AM.SymbolFlags = S->getTargetFlags();
682 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
683 AM.JT = J->getIndex();
684 AM.SymbolFlags = J->getTargetFlags();
685 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
686 X86ISelAddressMode Backup = AM;
687 AM.BlockAddr = BA->getBlockAddress();
688 AM.SymbolFlags = BA->getTargetFlags();
689 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
694 llvm_unreachable("Unhandled symbol reference node.");
696 if (N.getOpcode() == X86ISD::WrapperRIP)
697 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
701 // Handle the case when globals fit in our immediate field: This is true for
702 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
703 // mode, this only applies to a non-RIP-relative computation.
704 if (!Subtarget->is64Bit() ||
705 M == CodeModel::Small || M == CodeModel::Kernel) {
706 assert(N.getOpcode() != X86ISD::WrapperRIP &&
707 "RIP-relative addressing already handled");
708 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
709 AM.GV = G->getGlobal();
710 AM.Disp += G->getOffset();
711 AM.SymbolFlags = G->getTargetFlags();
712 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
713 AM.CP = CP->getConstVal();
714 AM.Align = CP->getAlignment();
715 AM.Disp += CP->getOffset();
716 AM.SymbolFlags = CP->getTargetFlags();
717 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
718 AM.ES = S->getSymbol();
719 AM.SymbolFlags = S->getTargetFlags();
720 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
721 AM.JT = J->getIndex();
722 AM.SymbolFlags = J->getTargetFlags();
723 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
724 AM.BlockAddr = BA->getBlockAddress();
725 AM.Disp += BA->getOffset();
726 AM.SymbolFlags = BA->getTargetFlags();
728 llvm_unreachable("Unhandled symbol reference node.");
735 /// MatchAddress - Add the specified node to the specified addressing mode,
736 /// returning true if it cannot be done. This just pattern matches for the
738 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
739 if (MatchAddressRecursively(N, AM, 0))
742 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
743 // a smaller encoding and avoids a scaled-index.
745 AM.BaseType == X86ISelAddressMode::RegBase &&
746 AM.Base_Reg.getNode() == nullptr) {
747 AM.Base_Reg = AM.IndexReg;
751 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
752 // because it has a smaller encoding.
753 // TODO: Which other code models can use this?
754 if (TM.getCodeModel() == CodeModel::Small &&
755 Subtarget->is64Bit() &&
757 AM.BaseType == X86ISelAddressMode::RegBase &&
758 AM.Base_Reg.getNode() == nullptr &&
759 AM.IndexReg.getNode() == nullptr &&
760 AM.SymbolFlags == X86II::MO_NO_FLAG &&
761 AM.hasSymbolicDisplacement())
762 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
767 // Insert a node into the DAG at least before the Pos node's position. This
768 // will reposition the node as needed, and will assign it a node ID that is <=
769 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
770 // IDs! The selection DAG must no longer depend on their uniqueness when this
772 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
773 if (N.getNode()->getNodeId() == -1 ||
774 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
775 DAG.RepositionNode(Pos.getNode(), N.getNode());
776 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
780 // Transform "(X >> (8-C1)) & (0xff << C1)" to "((X >> 8) & 0xff) << C1" if
781 // safe. This allows us to convert the shift and and into an h-register
782 // extract and a scaled index. Returns false if the simplification is
784 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
786 SDValue Shift, SDValue X,
787 X86ISelAddressMode &AM) {
788 if (Shift.getOpcode() != ISD::SRL ||
789 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
793 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
794 if (ScaleLog <= 0 || ScaleLog >= 4 ||
795 Mask != (0xffu << ScaleLog))
798 MVT VT = N.getSimpleValueType();
800 SDValue Eight = DAG.getConstant(8, MVT::i8);
801 SDValue NewMask = DAG.getConstant(0xff, VT);
802 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
803 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
804 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
805 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
807 // Insert the new nodes into the topological ordering. We must do this in
808 // a valid topological ordering as nothing is going to go back and re-sort
809 // these nodes. We continually insert before 'N' in sequence as this is
810 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
811 // hierarchy left to express.
812 InsertDAGNode(DAG, N, Eight);
813 InsertDAGNode(DAG, N, Srl);
814 InsertDAGNode(DAG, N, NewMask);
815 InsertDAGNode(DAG, N, And);
816 InsertDAGNode(DAG, N, ShlCount);
817 InsertDAGNode(DAG, N, Shl);
818 DAG.ReplaceAllUsesWith(N, Shl);
820 AM.Scale = (1 << ScaleLog);
824 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
825 // allows us to fold the shift into this addressing mode. Returns false if the
826 // transform succeeded.
827 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
829 SDValue Shift, SDValue X,
830 X86ISelAddressMode &AM) {
831 if (Shift.getOpcode() != ISD::SHL ||
832 !isa<ConstantSDNode>(Shift.getOperand(1)))
835 // Not likely to be profitable if either the AND or SHIFT node has more
836 // than one use (unless all uses are for address computation). Besides,
837 // isel mechanism requires their node ids to be reused.
838 if (!N.hasOneUse() || !Shift.hasOneUse())
841 // Verify that the shift amount is something we can fold.
842 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
843 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
846 MVT VT = N.getSimpleValueType();
848 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
849 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
850 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
852 // Insert the new nodes into the topological ordering. We must do this in
853 // a valid topological ordering as nothing is going to go back and re-sort
854 // these nodes. We continually insert before 'N' in sequence as this is
855 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
856 // hierarchy left to express.
857 InsertDAGNode(DAG, N, NewMask);
858 InsertDAGNode(DAG, N, NewAnd);
859 InsertDAGNode(DAG, N, NewShift);
860 DAG.ReplaceAllUsesWith(N, NewShift);
862 AM.Scale = 1 << ShiftAmt;
863 AM.IndexReg = NewAnd;
867 // Implement some heroics to detect shifts of masked values where the mask can
868 // be replaced by extending the shift and undoing that in the addressing mode
869 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
870 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
871 // the addressing mode. This results in code such as:
873 // int f(short *y, int *lookup_table) {
875 // return *y + lookup_table[*y >> 11];
879 // movzwl (%rdi), %eax
882 // addl (%rsi,%rcx,4), %eax
885 // movzwl (%rdi), %eax
889 // addl (%rsi,%rcx), %eax
891 // Note that this function assumes the mask is provided as a mask *after* the
892 // value is shifted. The input chain may or may not match that, but computing
893 // such a mask is trivial.
894 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
896 SDValue Shift, SDValue X,
897 X86ISelAddressMode &AM) {
898 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
899 !isa<ConstantSDNode>(Shift.getOperand(1)))
902 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
903 unsigned MaskLZ = countLeadingZeros(Mask);
904 unsigned MaskTZ = countTrailingZeros(Mask);
906 // The amount of shift we're trying to fit into the addressing mode is taken
907 // from the trailing zeros of the mask.
908 unsigned AMShiftAmt = MaskTZ;
910 // There is nothing we can do here unless the mask is removing some bits.
911 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
912 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
914 // We also need to ensure that mask is a continuous run of bits.
915 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
917 // Scale the leading zero count down based on the actual size of the value.
918 // Also scale it down based on the size of the shift.
919 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
921 // The final check is to ensure that any masked out high bits of X are
922 // already known to be zero. Otherwise, the mask has a semantic impact
923 // other than masking out a couple of low bits. Unfortunately, because of
924 // the mask, zero extensions will be removed from operands in some cases.
925 // This code works extra hard to look through extensions because we can
926 // replace them with zero extensions cheaply if necessary.
927 bool ReplacingAnyExtend = false;
928 if (X.getOpcode() == ISD::ANY_EXTEND) {
929 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
930 X.getOperand(0).getSimpleValueType().getSizeInBits();
931 // Assume that we'll replace the any-extend with a zero-extend, and
932 // narrow the search to the extended value.
934 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
935 ReplacingAnyExtend = true;
937 APInt MaskedHighBits =
938 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
939 APInt KnownZero, KnownOne;
940 DAG.computeKnownBits(X, KnownZero, KnownOne);
941 if (MaskedHighBits != KnownZero) return true;
943 // We've identified a pattern that can be transformed into a single shift
944 // and an addressing mode. Make it so.
945 MVT VT = N.getSimpleValueType();
946 if (ReplacingAnyExtend) {
947 assert(X.getValueType() != VT);
948 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
949 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
950 InsertDAGNode(DAG, N, NewX);
954 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
955 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
956 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
957 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
959 // Insert the new nodes into the topological ordering. We must do this in
960 // a valid topological ordering as nothing is going to go back and re-sort
961 // these nodes. We continually insert before 'N' in sequence as this is
962 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
963 // hierarchy left to express.
964 InsertDAGNode(DAG, N, NewSRLAmt);
965 InsertDAGNode(DAG, N, NewSRL);
966 InsertDAGNode(DAG, N, NewSHLAmt);
967 InsertDAGNode(DAG, N, NewSHL);
968 DAG.ReplaceAllUsesWith(N, NewSHL);
970 AM.Scale = 1 << AMShiftAmt;
971 AM.IndexReg = NewSRL;
975 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
979 dbgs() << "MatchAddress: ";
984 return MatchAddressBase(N, AM);
986 // If this is already a %rip relative address, we can only merge immediates
987 // into it. Instead of handling this in every case, we handle it here.
988 // RIP relative addressing: %rip + 32-bit displacement!
989 if (AM.isRIPRelative()) {
990 // FIXME: JumpTable and ExternalSymbol address currently don't like
991 // displacements. It isn't very important, but this should be fixed for
993 if (!AM.ES && AM.JT != -1) return true;
995 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
996 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
1001 switch (N.getOpcode()) {
1003 case ISD::Constant: {
1004 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1005 if (!FoldOffsetIntoAddress(Val, AM))
1010 case X86ISD::Wrapper:
1011 case X86ISD::WrapperRIP:
1012 if (!MatchWrapper(N, AM))
1017 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1021 case ISD::FrameIndex:
1022 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1023 AM.Base_Reg.getNode() == nullptr &&
1024 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1025 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1026 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1032 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1036 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1037 unsigned Val = CN->getZExtValue();
1038 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1039 // that the base operand remains free for further matching. If
1040 // the base doesn't end up getting used, a post-processing step
1041 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1042 if (Val == 1 || Val == 2 || Val == 3) {
1043 AM.Scale = 1 << Val;
1044 SDValue ShVal = N.getNode()->getOperand(0);
1046 // Okay, we know that we have a scale by now. However, if the scaled
1047 // value is an add of something and a constant, we can fold the
1048 // constant into the disp field here.
1049 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1050 AM.IndexReg = ShVal.getNode()->getOperand(0);
1051 ConstantSDNode *AddVal =
1052 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1053 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1054 if (!FoldOffsetIntoAddress(Disp, AM))
1058 AM.IndexReg = ShVal;
1065 // Scale must not be used already.
1066 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1068 SDValue And = N.getOperand(0);
1069 if (And.getOpcode() != ISD::AND) break;
1070 SDValue X = And.getOperand(0);
1072 // We only handle up to 64-bit values here as those are what matter for
1073 // addressing mode optimizations.
1074 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1076 // The mask used for the transform is expected to be post-shift, but we
1077 // found the shift first so just apply the shift to the mask before passing
1079 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1080 !isa<ConstantSDNode>(And.getOperand(1)))
1082 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1084 // Try to fold the mask and shift into the scale, and return false if we
1086 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1091 case ISD::SMUL_LOHI:
1092 case ISD::UMUL_LOHI:
1093 // A mul_lohi where we need the low part can be folded as a plain multiply.
1094 if (N.getResNo() != 0) break;
1097 case X86ISD::MUL_IMM:
1098 // X*[3,5,9] -> X+X*[2,4,8]
1099 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1100 AM.Base_Reg.getNode() == nullptr &&
1101 AM.IndexReg.getNode() == nullptr) {
1103 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1104 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1105 CN->getZExtValue() == 9) {
1106 AM.Scale = unsigned(CN->getZExtValue())-1;
1108 SDValue MulVal = N.getNode()->getOperand(0);
1111 // Okay, we know that we have a scale by now. However, if the scaled
1112 // value is an add of something and a constant, we can fold the
1113 // constant into the disp field here.
1114 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1115 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1116 Reg = MulVal.getNode()->getOperand(0);
1117 ConstantSDNode *AddVal =
1118 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1119 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1120 if (FoldOffsetIntoAddress(Disp, AM))
1121 Reg = N.getNode()->getOperand(0);
1123 Reg = N.getNode()->getOperand(0);
1126 AM.IndexReg = AM.Base_Reg = Reg;
1133 // Given A-B, if A can be completely folded into the address and
1134 // the index field with the index field unused, use -B as the index.
1135 // This is a win if a has multiple parts that can be folded into
1136 // the address. Also, this saves a mov if the base register has
1137 // other uses, since it avoids a two-address sub instruction, however
1138 // it costs an additional mov if the index register has other uses.
1140 // Add an artificial use to this node so that we can keep track of
1141 // it if it gets CSE'd with a different node.
1142 HandleSDNode Handle(N);
1144 // Test if the LHS of the sub can be folded.
1145 X86ISelAddressMode Backup = AM;
1146 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1150 // Test if the index field is free for use.
1151 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1157 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1158 // If the RHS involves a register with multiple uses, this
1159 // transformation incurs an extra mov, due to the neg instruction
1160 // clobbering its operand.
1161 if (!RHS.getNode()->hasOneUse() ||
1162 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1163 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1164 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1165 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1166 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1168 // If the base is a register with multiple uses, this
1169 // transformation may save a mov.
1170 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1171 AM.Base_Reg.getNode() &&
1172 !AM.Base_Reg.getNode()->hasOneUse()) ||
1173 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1175 // If the folded LHS was interesting, this transformation saves
1176 // address arithmetic.
1177 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1178 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1179 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1181 // If it doesn't look like it may be an overall win, don't do it.
1187 // Ok, the transformation is legal and appears profitable. Go for it.
1188 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1189 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1193 // Insert the new nodes into the topological ordering.
1194 InsertDAGNode(*CurDAG, N, Zero);
1195 InsertDAGNode(*CurDAG, N, Neg);
1200 // Add an artificial use to this node so that we can keep track of
1201 // it if it gets CSE'd with a different node.
1202 HandleSDNode Handle(N);
1204 X86ISelAddressMode Backup = AM;
1205 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1206 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1210 // Try again after commuting the operands.
1211 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1212 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1216 // If we couldn't fold both operands into the address at the same time,
1217 // see if we can just put each operand into a register and fold at least
1219 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1220 !AM.Base_Reg.getNode() &&
1221 !AM.IndexReg.getNode()) {
1222 N = Handle.getValue();
1223 AM.Base_Reg = N.getOperand(0);
1224 AM.IndexReg = N.getOperand(1);
1228 N = Handle.getValue();
1233 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1234 if (CurDAG->isBaseWithConstantOffset(N)) {
1235 X86ISelAddressMode Backup = AM;
1236 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1238 // Start with the LHS as an addr mode.
1239 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1240 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1247 // Perform some heroic transforms on an and of a constant-count shift
1248 // with a constant to enable use of the scaled offset field.
1250 // Scale must not be used already.
1251 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1253 SDValue Shift = N.getOperand(0);
1254 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1255 SDValue X = Shift.getOperand(0);
1257 // We only handle up to 64-bit values here as those are what matter for
1258 // addressing mode optimizations.
1259 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1261 if (!isa<ConstantSDNode>(N.getOperand(1)))
1263 uint64_t Mask = N.getConstantOperandVal(1);
1265 // Try to fold the mask and shift into an extract and scale.
1266 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1269 // Try to fold the mask and shift directly into the scale.
1270 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1273 // Try to swap the mask and shift to place shifts which can be done as
1274 // a scale on the outside of the mask.
1275 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1281 return MatchAddressBase(N, AM);
1284 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1285 /// specified addressing mode without any further recursion.
1286 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1287 // Is the base register already occupied?
1288 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1289 // If so, check to see if the scale index register is set.
1290 if (!AM.IndexReg.getNode()) {
1296 // Otherwise, we cannot select it.
1300 // Default, generate it as a register.
1301 AM.BaseType = X86ISelAddressMode::RegBase;
1306 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1307 /// It returns the operands which make up the maximal addressing mode it can
1308 /// match by reference.
1310 /// Parent is the parent node of the addr operand that is being matched. It
1311 /// is always a load, store, atomic node, or null. It is only null when
1312 /// checking memory operands for inline asm nodes.
1313 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1314 SDValue &Scale, SDValue &Index,
1315 SDValue &Disp, SDValue &Segment) {
1316 X86ISelAddressMode AM;
1319 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1320 // that are not a MemSDNode, and thus don't have proper addrspace info.
1321 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1322 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1323 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1324 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1325 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1326 unsigned AddrSpace =
1327 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1328 // AddrSpace 256 -> GS, 257 -> FS.
1329 if (AddrSpace == 256)
1330 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1331 if (AddrSpace == 257)
1332 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1335 if (MatchAddress(N, AM))
1338 MVT VT = N.getSimpleValueType();
1339 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1340 if (!AM.Base_Reg.getNode())
1341 AM.Base_Reg = CurDAG->getRegister(0, VT);
1344 if (!AM.IndexReg.getNode())
1345 AM.IndexReg = CurDAG->getRegister(0, VT);
1347 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1351 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1352 /// match a load whose top elements are either undef or zeros. The load flavor
1353 /// is derived from the type of N, which is either v4f32 or v2f64.
1356 /// PatternChainNode: this is the matched node that has a chain input and
1358 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1359 SDValue N, SDValue &Base,
1360 SDValue &Scale, SDValue &Index,
1361 SDValue &Disp, SDValue &Segment,
1362 SDValue &PatternNodeWithChain) {
1363 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1364 PatternNodeWithChain = N.getOperand(0);
1365 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1366 PatternNodeWithChain.hasOneUse() &&
1367 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1368 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1369 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1370 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1376 // Also handle the case where we explicitly require zeros in the top
1377 // elements. This is a vector shuffle from the zero vector.
1378 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1379 // Check to see if the top elements are all zeros (or bitcast of zeros).
1380 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1381 N.getOperand(0).getNode()->hasOneUse() &&
1382 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1383 N.getOperand(0).getOperand(0).hasOneUse() &&
1384 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1385 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1386 // Okay, this is a zero extending load. Fold it.
1387 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1388 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1390 PatternNodeWithChain = SDValue(LD, 0);
1397 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1398 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1399 uint64_t ImmVal = CN->getZExtValue();
1400 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1403 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
1407 // In static codegen with small code model, we can get the address of a label
1408 // into a register with 'movl'. TableGen has already made sure we're looking
1409 // at a label of some kind.
1410 assert(N->getOpcode() == X86ISD::Wrapper &&
1411 "Unexpected node type for MOV32ri64");
1412 N = N.getOperand(0);
1414 if (N->getOpcode() != ISD::TargetConstantPool &&
1415 N->getOpcode() != ISD::TargetJumpTable &&
1416 N->getOpcode() != ISD::TargetGlobalAddress &&
1417 N->getOpcode() != ISD::TargetExternalSymbol &&
1418 N->getOpcode() != ISD::TargetBlockAddress)
1422 return TM.getCodeModel() == CodeModel::Small;
1425 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1426 SDValue &Scale, SDValue &Index,
1427 SDValue &Disp, SDValue &Segment) {
1428 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1432 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1433 if (RN && RN->getReg() == 0)
1434 Base = CurDAG->getRegister(0, MVT::i64);
1435 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
1436 // Base could already be %rip, particularly in the x32 ABI.
1437 Base = SDValue(CurDAG->getMachineNode(
1438 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1439 CurDAG->getTargetConstant(0, MVT::i64),
1441 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1445 RN = dyn_cast<RegisterSDNode>(Index);
1446 if (RN && RN->getReg() == 0)
1447 Index = CurDAG->getRegister(0, MVT::i64);
1449 assert(Index.getValueType() == MVT::i32 &&
1450 "Expect to be extending 32-bit registers for use in LEA");
1451 Index = SDValue(CurDAG->getMachineNode(
1452 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1453 CurDAG->getTargetConstant(0, MVT::i64),
1455 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1462 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1463 /// mode it matches can be cost effectively emitted as an LEA instruction.
1464 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1465 SDValue &Base, SDValue &Scale,
1466 SDValue &Index, SDValue &Disp,
1468 X86ISelAddressMode AM;
1470 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1472 SDValue Copy = AM.Segment;
1473 SDValue T = CurDAG->getRegister(0, MVT::i32);
1475 if (MatchAddress(N, AM))
1477 assert (T == AM.Segment);
1480 MVT VT = N.getSimpleValueType();
1481 unsigned Complexity = 0;
1482 if (AM.BaseType == X86ISelAddressMode::RegBase)
1483 if (AM.Base_Reg.getNode())
1486 AM.Base_Reg = CurDAG->getRegister(0, VT);
1487 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1490 if (AM.IndexReg.getNode())
1493 AM.IndexReg = CurDAG->getRegister(0, VT);
1495 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1500 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1501 // to a LEA. This is determined with some expermentation but is by no means
1502 // optimal (especially for code size consideration). LEA is nice because of
1503 // its three-address nature. Tweak the cost function again when we can run
1504 // convertToThreeAddress() at register allocation time.
1505 if (AM.hasSymbolicDisplacement()) {
1506 // For X86-64, we should always use lea to materialize RIP relative
1508 if (Subtarget->is64Bit())
1514 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1517 // If it isn't worth using an LEA, reject it.
1518 if (Complexity <= 2)
1521 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1525 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1526 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1527 SDValue &Scale, SDValue &Index,
1528 SDValue &Disp, SDValue &Segment) {
1529 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1530 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1532 X86ISelAddressMode AM;
1533 AM.GV = GA->getGlobal();
1534 AM.Disp += GA->getOffset();
1535 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1536 AM.SymbolFlags = GA->getTargetFlags();
1538 if (N.getValueType() == MVT::i32) {
1540 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1542 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1545 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1550 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1551 SDValue &Base, SDValue &Scale,
1552 SDValue &Index, SDValue &Disp,
1554 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1555 !IsProfitableToFold(N, P, P) ||
1556 !IsLegalToFold(N, P, P, OptLevel))
1559 return SelectAddr(N.getNode(),
1560 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1563 /// getGlobalBaseReg - Return an SDNode that returns the value of
1564 /// the global base register. Output instructions required to
1565 /// initialize the global base register, if necessary.
1567 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1568 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1569 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode();
1572 /// Atomic opcode table
1600 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1611 X86::LOCK_ADD64mi32,
1624 X86::LOCK_SUB64mi32,
1676 X86::LOCK_AND64mi32,
1689 X86::LOCK_XOR64mi32,
1694 // Return the target constant operand for atomic-load-op and do simple
1695 // translations, such as from atomic-load-add to lock-sub. The return value is
1696 // one of the following 3 cases:
1697 // + target-constant, the operand could be supported as a target constant.
1698 // + empty, the operand is not needed any more with the new op selected.
1699 // + non-empty, otherwise.
1700 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1702 enum AtomicOpc &Op, MVT NVT,
1704 const X86Subtarget *Subtarget) {
1705 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1706 int64_t CNVal = CN->getSExtValue();
1707 // Quit if not 32-bit imm.
1708 if ((int32_t)CNVal != CNVal)
1710 // Quit if INT32_MIN: it would be negated as it is negative and overflow,
1711 // producing an immediate that does not fit in the 32 bits available for
1712 // an immediate operand to sub. However, it still fits in 32 bits for the
1713 // add (since it is not negated) so we can return target-constant.
1714 if (CNVal == INT32_MIN)
1715 return CurDAG->getTargetConstant(CNVal, NVT);
1716 // For atomic-load-add, we could do some optimizations.
1718 // Translate to INC/DEC if ADD by 1 or -1.
1719 if (((CNVal == 1) || (CNVal == -1)) && !Subtarget->slowIncDec()) {
1720 Op = (CNVal == 1) ? INC : DEC;
1721 // No more constant operand after being translated into INC/DEC.
1724 // Translate to SUB if ADD by negative value.
1730 return CurDAG->getTargetConstant(CNVal, NVT);
1733 // If the value operand is single-used, try to optimize it.
1734 if (Op == ADD && Val.hasOneUse()) {
1735 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1736 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1738 return Val.getOperand(1);
1740 // A special case for i16, which needs truncating as, in most cases, it's
1741 // promoted to i32. We will translate
1742 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1743 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1744 Val.getOperand(0).getOpcode() == ISD::SUB &&
1745 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1747 Val = Val.getOperand(0);
1748 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1756 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1757 if (Node->hasAnyUseOfValue(0))
1762 // Optimize common patterns for __sync_or_and_fetch and similar arith
1763 // operations where the result is not used. This allows us to use the "lock"
1764 // version of the arithmetic instruction.
1765 SDValue Chain = Node->getOperand(0);
1766 SDValue Ptr = Node->getOperand(1);
1767 SDValue Val = Node->getOperand(2);
1768 SDValue Base, Scale, Index, Disp, Segment;
1769 if (!SelectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
1772 // Which index into the table.
1774 switch (Node->getOpcode()) {
1777 case ISD::ATOMIC_LOAD_OR:
1780 case ISD::ATOMIC_LOAD_AND:
1783 case ISD::ATOMIC_LOAD_XOR:
1786 case ISD::ATOMIC_LOAD_ADD:
1791 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val, Subtarget);
1792 bool isUnOp = !Val.getNode();
1793 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1796 switch (NVT.SimpleTy) {
1797 default: return nullptr;
1800 Opc = AtomicOpcTbl[Op][ConstantI8];
1802 Opc = AtomicOpcTbl[Op][I8];
1806 if (immSext8(Val.getNode()))
1807 Opc = AtomicOpcTbl[Op][SextConstantI16];
1809 Opc = AtomicOpcTbl[Op][ConstantI16];
1811 Opc = AtomicOpcTbl[Op][I16];
1815 if (immSext8(Val.getNode()))
1816 Opc = AtomicOpcTbl[Op][SextConstantI32];
1818 Opc = AtomicOpcTbl[Op][ConstantI32];
1820 Opc = AtomicOpcTbl[Op][I32];
1824 if (immSext8(Val.getNode()))
1825 Opc = AtomicOpcTbl[Op][SextConstantI64];
1826 else if (i64immSExt32(Val.getNode()))
1827 Opc = AtomicOpcTbl[Op][ConstantI64];
1829 llvm_unreachable("True 64 bits constant in SelectAtomicLoadArith");
1831 Opc = AtomicOpcTbl[Op][I64];
1835 assert(Opc != 0 && "Invalid arith lock transform!");
1837 // Building the new node.
1840 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Chain };
1841 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1843 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Val, Chain };
1844 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1847 // Copying the MachineMemOperand.
1848 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1849 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1850 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1852 // We need to have two outputs as that is what the original instruction had.
1853 // So we add a dummy, undefined output. This is safe as we checked first
1854 // that no-one uses our output anyway.
1855 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1857 SDValue RetVals[] = { Undef, Ret };
1858 return CurDAG->getMergeValues(RetVals, dl).getNode();
1861 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1862 /// any uses which require the SF or OF bits to be accurate.
1863 static bool HasNoSignedComparisonUses(SDNode *N) {
1864 // Examine each user of the node.
1865 for (SDNode::use_iterator UI = N->use_begin(),
1866 UE = N->use_end(); UI != UE; ++UI) {
1867 // Only examine CopyToReg uses.
1868 if (UI->getOpcode() != ISD::CopyToReg)
1870 // Only examine CopyToReg uses that copy to EFLAGS.
1871 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1874 // Examine each user of the CopyToReg use.
1875 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1876 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1877 // Only examine the Flag result.
1878 if (FlagUI.getUse().getResNo() != 1) continue;
1879 // Anything unusual: assume conservatively.
1880 if (!FlagUI->isMachineOpcode()) return false;
1881 // Examine the opcode of the user.
1882 switch (FlagUI->getMachineOpcode()) {
1883 // These comparisons don't treat the most significant bit specially.
1884 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1885 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1886 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1887 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1888 case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
1889 case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
1890 case X86::CMOVA16rr: case X86::CMOVA16rm:
1891 case X86::CMOVA32rr: case X86::CMOVA32rm:
1892 case X86::CMOVA64rr: case X86::CMOVA64rm:
1893 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1894 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1895 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1896 case X86::CMOVB16rr: case X86::CMOVB16rm:
1897 case X86::CMOVB32rr: case X86::CMOVB32rm:
1898 case X86::CMOVB64rr: case X86::CMOVB64rm:
1899 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1900 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1901 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1902 case X86::CMOVE16rr: case X86::CMOVE16rm:
1903 case X86::CMOVE32rr: case X86::CMOVE32rm:
1904 case X86::CMOVE64rr: case X86::CMOVE64rm:
1905 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1906 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1907 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1908 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1909 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1910 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1911 case X86::CMOVP16rr: case X86::CMOVP16rm:
1912 case X86::CMOVP32rr: case X86::CMOVP32rm:
1913 case X86::CMOVP64rr: case X86::CMOVP64rm:
1915 // Anything else: assume conservatively.
1916 default: return false;
1923 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1924 /// is suitable for doing the {load; increment or decrement; store} to modify
1926 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1927 SDValue StoredVal, SelectionDAG *CurDAG,
1928 LoadSDNode* &LoadNode, SDValue &InputChain) {
1930 // is the value stored the result of a DEC or INC?
1931 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1933 // is the stored value result 0 of the load?
1934 if (StoredVal.getResNo() != 0) return false;
1936 // are there other uses of the loaded value than the inc or dec?
1937 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1939 // is the store non-extending and non-indexed?
1940 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1943 SDValue Load = StoredVal->getOperand(0);
1944 // Is the stored value a non-extending and non-indexed load?
1945 if (!ISD::isNormalLoad(Load.getNode())) return false;
1947 // Return LoadNode by reference.
1948 LoadNode = cast<LoadSDNode>(Load);
1949 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1950 EVT LdVT = LoadNode->getMemoryVT();
1951 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1955 // Is store the only read of the loaded value?
1956 if (!Load.hasOneUse())
1959 // Is the address of the store the same as the load?
1960 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1961 LoadNode->getOffset() != StoreNode->getOffset())
1964 // Check if the chain is produced by the load or is a TokenFactor with
1965 // the load output chain as an operand. Return InputChain by reference.
1966 SDValue Chain = StoreNode->getChain();
1968 bool ChainCheck = false;
1969 if (Chain == Load.getValue(1)) {
1971 InputChain = LoadNode->getChain();
1972 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1973 SmallVector<SDValue, 4> ChainOps;
1974 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1975 SDValue Op = Chain.getOperand(i);
1976 if (Op == Load.getValue(1)) {
1981 // Make sure using Op as part of the chain would not cause a cycle here.
1982 // In theory, we could check whether the chain node is a predecessor of
1983 // the load. But that can be very expensive. Instead visit the uses and
1984 // make sure they all have smaller node id than the load.
1985 int LoadId = LoadNode->getNodeId();
1986 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1987 UE = UI->use_end(); UI != UE; ++UI) {
1988 if (UI.getUse().getResNo() != 0)
1990 if (UI->getNodeId() > LoadId)
1994 ChainOps.push_back(Op);
1998 // Make a new TokenFactor with all the other input chains except
2000 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
2001 MVT::Other, ChainOps);
2009 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2010 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2011 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2012 if (Opc == X86ISD::DEC) {
2013 if (LdVT == MVT::i64) return X86::DEC64m;
2014 if (LdVT == MVT::i32) return X86::DEC32m;
2015 if (LdVT == MVT::i16) return X86::DEC16m;
2016 if (LdVT == MVT::i8) return X86::DEC8m;
2018 assert(Opc == X86ISD::INC && "unrecognized opcode");
2019 if (LdVT == MVT::i64) return X86::INC64m;
2020 if (LdVT == MVT::i32) return X86::INC32m;
2021 if (LdVT == MVT::i16) return X86::INC16m;
2022 if (LdVT == MVT::i8) return X86::INC8m;
2024 llvm_unreachable("unrecognized size for LdVT");
2027 /// SelectGather - Customized ISel for GATHER operations.
2029 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2030 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2031 SDValue Chain = Node->getOperand(0);
2032 SDValue VSrc = Node->getOperand(2);
2033 SDValue Base = Node->getOperand(3);
2034 SDValue VIdx = Node->getOperand(4);
2035 SDValue VMask = Node->getOperand(5);
2036 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2040 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2043 // Memory Operands: Base, Scale, Index, Disp, Segment
2044 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
2045 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2046 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
2047 Disp, Segment, VMask, Chain};
2048 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
2049 // Node has 2 outputs: VDst and MVT::Other.
2050 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2051 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2053 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2054 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2058 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2059 MVT NVT = Node->getSimpleValueType(0);
2061 unsigned Opcode = Node->getOpcode();
2064 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2066 if (Node->isMachineOpcode()) {
2067 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2068 Node->setNodeId(-1);
2069 return nullptr; // Already selected.
2074 case ISD::INTRINSIC_W_CHAIN: {
2075 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2078 case Intrinsic::x86_avx2_gather_d_pd:
2079 case Intrinsic::x86_avx2_gather_d_pd_256:
2080 case Intrinsic::x86_avx2_gather_q_pd:
2081 case Intrinsic::x86_avx2_gather_q_pd_256:
2082 case Intrinsic::x86_avx2_gather_d_ps:
2083 case Intrinsic::x86_avx2_gather_d_ps_256:
2084 case Intrinsic::x86_avx2_gather_q_ps:
2085 case Intrinsic::x86_avx2_gather_q_ps_256:
2086 case Intrinsic::x86_avx2_gather_d_q:
2087 case Intrinsic::x86_avx2_gather_d_q_256:
2088 case Intrinsic::x86_avx2_gather_q_q:
2089 case Intrinsic::x86_avx2_gather_q_q_256:
2090 case Intrinsic::x86_avx2_gather_d_d:
2091 case Intrinsic::x86_avx2_gather_d_d_256:
2092 case Intrinsic::x86_avx2_gather_q_d:
2093 case Intrinsic::x86_avx2_gather_q_d_256: {
2094 if (!Subtarget->hasAVX2())
2098 default: llvm_unreachable("Impossible intrinsic");
2099 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2100 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2101 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2102 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2103 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2104 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2105 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2106 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2107 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2108 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2109 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2110 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2111 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2112 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2113 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2114 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2116 SDNode *RetVal = SelectGather(Node, Opc);
2118 // We already called ReplaceUses inside SelectGather.
2125 case X86ISD::GlobalBaseReg:
2126 return getGlobalBaseReg();
2128 case X86ISD::SHRUNKBLEND: {
2129 // SHRUNKBLEND selects like a regular VSELECT.
2130 SDValue VSelect = CurDAG->getNode(
2131 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
2132 Node->getOperand(1), Node->getOperand(2));
2133 ReplaceUses(SDValue(Node, 0), VSelect);
2134 SelectCode(VSelect.getNode());
2135 // We already called ReplaceUses.
2139 case ISD::ATOMIC_LOAD_XOR:
2140 case ISD::ATOMIC_LOAD_AND:
2141 case ISD::ATOMIC_LOAD_OR:
2142 case ISD::ATOMIC_LOAD_ADD: {
2143 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2151 // For operations of the form (x << C1) op C2, check if we can use a smaller
2152 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2153 SDValue N0 = Node->getOperand(0);
2154 SDValue N1 = Node->getOperand(1);
2156 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2159 // i8 is unshrinkable, i16 should be promoted to i32.
2160 if (NVT != MVT::i32 && NVT != MVT::i64)
2163 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2164 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2165 if (!Cst || !ShlCst)
2168 int64_t Val = Cst->getSExtValue();
2169 uint64_t ShlVal = ShlCst->getZExtValue();
2171 // Make sure that we don't change the operation by removing bits.
2172 // This only matters for OR and XOR, AND is unaffected.
2173 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2174 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2180 // Check the minimum bitwidth for the new constant.
2181 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2182 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2183 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2184 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2186 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2189 // Bail if there is no smaller encoding.
2193 switch (NVT.SimpleTy) {
2194 default: llvm_unreachable("Unsupported VT!");
2196 assert(CstVT == MVT::i8);
2197 ShlOp = X86::SHL32ri;
2200 default: llvm_unreachable("Impossible opcode");
2201 case ISD::AND: Op = X86::AND32ri8; break;
2202 case ISD::OR: Op = X86::OR32ri8; break;
2203 case ISD::XOR: Op = X86::XOR32ri8; break;
2207 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2208 ShlOp = X86::SHL64ri;
2211 default: llvm_unreachable("Impossible opcode");
2212 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2213 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2214 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2219 // Emit the smaller op and the shift.
2220 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2221 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2222 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2226 case X86ISD::SMUL8: {
2227 SDValue N0 = Node->getOperand(0);
2228 SDValue N1 = Node->getOperand(1);
2230 Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
2232 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
2233 N0, SDValue()).getValue(1);
2235 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
2236 SDValue Ops[] = {N1, InFlag};
2237 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2239 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2240 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2244 case X86ISD::UMUL: {
2245 SDValue N0 = Node->getOperand(0);
2246 SDValue N1 = Node->getOperand(1);
2249 switch (NVT.SimpleTy) {
2250 default: llvm_unreachable("Unsupported VT!");
2251 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2252 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2253 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2254 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2257 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2258 N0, SDValue()).getValue(1);
2260 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2261 SDValue Ops[] = {N1, InFlag};
2262 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2264 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2265 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2266 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2270 case ISD::SMUL_LOHI:
2271 case ISD::UMUL_LOHI: {
2272 SDValue N0 = Node->getOperand(0);
2273 SDValue N1 = Node->getOperand(1);
2275 bool isSigned = Opcode == ISD::SMUL_LOHI;
2276 bool hasBMI2 = Subtarget->hasBMI2();
2278 switch (NVT.SimpleTy) {
2279 default: llvm_unreachable("Unsupported VT!");
2280 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2281 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2282 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2283 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2284 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2285 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2288 switch (NVT.SimpleTy) {
2289 default: llvm_unreachable("Unsupported VT!");
2290 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2291 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2292 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2293 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2297 unsigned SrcReg, LoReg, HiReg;
2299 default: llvm_unreachable("Unknown MUL opcode!");
2302 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2306 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2310 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2314 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2317 SrcReg = X86::EDX; LoReg = HiReg = 0;
2320 SrcReg = X86::RDX; LoReg = HiReg = 0;
2324 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2325 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2326 // Multiply is commmutative.
2328 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2333 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2334 N0, SDValue()).getValue(1);
2335 SDValue ResHi, ResLo;
2339 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2341 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2342 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2343 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2344 ResHi = SDValue(CNode, 0);
2345 ResLo = SDValue(CNode, 1);
2346 Chain = SDValue(CNode, 2);
2347 InFlag = SDValue(CNode, 3);
2349 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2350 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2351 Chain = SDValue(CNode, 0);
2352 InFlag = SDValue(CNode, 1);
2355 // Update the chain.
2356 ReplaceUses(N1.getValue(1), Chain);
2358 SDValue Ops[] = { N1, InFlag };
2359 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2360 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2361 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2362 ResHi = SDValue(CNode, 0);
2363 ResLo = SDValue(CNode, 1);
2364 InFlag = SDValue(CNode, 2);
2366 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2367 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2368 InFlag = SDValue(CNode, 0);
2372 // Prevent use of AH in a REX instruction by referencing AX instead.
2373 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2374 !SDValue(Node, 1).use_empty()) {
2375 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2376 X86::AX, MVT::i16, InFlag);
2377 InFlag = Result.getValue(2);
2378 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2380 if (!SDValue(Node, 0).use_empty())
2381 ReplaceUses(SDValue(Node, 1),
2382 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2384 // Shift AX down 8 bits.
2385 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2387 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2388 // Then truncate it down to i8.
2389 ReplaceUses(SDValue(Node, 1),
2390 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2392 // Copy the low half of the result, if it is needed.
2393 if (!SDValue(Node, 0).use_empty()) {
2394 if (!ResLo.getNode()) {
2395 assert(LoReg && "Register for low half is not defined!");
2396 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2398 InFlag = ResLo.getValue(2);
2400 ReplaceUses(SDValue(Node, 0), ResLo);
2401 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2403 // Copy the high half of the result, if it is needed.
2404 if (!SDValue(Node, 1).use_empty()) {
2405 if (!ResHi.getNode()) {
2406 assert(HiReg && "Register for high half is not defined!");
2407 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2409 InFlag = ResHi.getValue(2);
2411 ReplaceUses(SDValue(Node, 1), ResHi);
2412 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2420 case X86ISD::SDIVREM8_SEXT_HREG:
2421 case X86ISD::UDIVREM8_ZEXT_HREG: {
2422 SDValue N0 = Node->getOperand(0);
2423 SDValue N1 = Node->getOperand(1);
2425 bool isSigned = (Opcode == ISD::SDIVREM ||
2426 Opcode == X86ISD::SDIVREM8_SEXT_HREG);
2428 switch (NVT.SimpleTy) {
2429 default: llvm_unreachable("Unsupported VT!");
2430 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2431 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2432 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2433 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2436 switch (NVT.SimpleTy) {
2437 default: llvm_unreachable("Unsupported VT!");
2438 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2439 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2440 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2441 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2445 unsigned LoReg, HiReg, ClrReg;
2446 unsigned SExtOpcode;
2447 switch (NVT.SimpleTy) {
2448 default: llvm_unreachable("Unsupported VT!");
2450 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2451 SExtOpcode = X86::CBW;
2454 LoReg = X86::AX; HiReg = X86::DX;
2456 SExtOpcode = X86::CWD;
2459 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2460 SExtOpcode = X86::CDQ;
2463 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2464 SExtOpcode = X86::CQO;
2468 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2469 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2470 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2473 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2474 // Special case for div8, just use a move with zero extension to AX to
2475 // clear the upper 8 bits (AH).
2476 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2477 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2478 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2480 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2481 MVT::Other, Ops), 0);
2482 Chain = Move.getValue(1);
2483 ReplaceUses(N0.getValue(1), Chain);
2486 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2487 Chain = CurDAG->getEntryNode();
2489 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2490 InFlag = Chain.getValue(1);
2493 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2494 LoReg, N0, SDValue()).getValue(1);
2495 if (isSigned && !signBitIsZero) {
2496 // Sign extend the low part into the high part.
2498 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2500 // Zero out the high part, effectively zero extending the input.
2501 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2502 switch (NVT.SimpleTy) {
2505 SDValue(CurDAG->getMachineNode(
2506 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2507 CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
2514 SDValue(CurDAG->getMachineNode(
2515 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2516 CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
2517 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2521 llvm_unreachable("Unexpected division source");
2524 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2525 ClrNode, InFlag).getValue(1);
2530 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2533 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2534 InFlag = SDValue(CNode, 1);
2535 // Update the chain.
2536 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2539 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2542 // Prevent use of AH in a REX instruction by explicitly copying it to
2543 // an ABCD_L register.
2545 // The current assumption of the register allocator is that isel
2546 // won't generate explicit references to the GR8_ABCD_H registers. If
2547 // the allocator and/or the backend get enhanced to be more robust in
2548 // that regard, this can be, and should be, removed.
2549 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
2550 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
2551 unsigned AHExtOpcode =
2552 isSigned ? X86::MOVSX32_NOREXrr8 : X86::MOVZX32_NOREXrr8;
2554 SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,
2555 MVT::Glue, AHCopy, InFlag);
2556 SDValue Result(RNode, 0);
2557 InFlag = SDValue(RNode, 1);
2559 if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
2560 Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
2561 if (Node->getValueType(1) == MVT::i64) {
2562 // It's not possible to directly movsx AH to a 64bit register, because
2563 // the latter needs the REX prefix, but the former can't have it.
2564 assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
2565 "Unexpected i64 sext of h-register");
2567 SDValue(CurDAG->getMachineNode(
2568 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2569 CurDAG->getTargetConstant(0, MVT::i64), Result,
2570 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2575 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
2577 ReplaceUses(SDValue(Node, 1), Result);
2578 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2580 // Copy the division (low) result, if it is needed.
2581 if (!SDValue(Node, 0).use_empty()) {
2582 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2583 LoReg, NVT, InFlag);
2584 InFlag = Result.getValue(2);
2585 ReplaceUses(SDValue(Node, 0), Result);
2586 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2588 // Copy the remainder (high) result, if it is needed.
2589 if (!SDValue(Node, 1).use_empty()) {
2590 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2591 HiReg, NVT, InFlag);
2592 InFlag = Result.getValue(2);
2593 ReplaceUses(SDValue(Node, 1), Result);
2594 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2601 // Sometimes a SUB is used to perform comparison.
2602 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2603 // This node is not a CMP.
2605 SDValue N0 = Node->getOperand(0);
2606 SDValue N1 = Node->getOperand(1);
2608 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2609 HasNoSignedComparisonUses(Node))
2610 N0 = N0.getOperand(0);
2612 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2613 // use a smaller encoding.
2614 // Look past the truncate if CMP is the only use of it.
2615 if ((N0.getNode()->getOpcode() == ISD::AND ||
2616 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2617 N0.getNode()->hasOneUse() &&
2618 N0.getValueType() != MVT::i8 &&
2619 X86::isZeroNode(N1)) {
2620 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2623 // For example, convert "testl %eax, $8" to "testb %al, $8"
2624 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2625 (!(C->getZExtValue() & 0x80) ||
2626 HasNoSignedComparisonUses(Node))) {
2627 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2628 SDValue Reg = N0.getNode()->getOperand(0);
2630 // On x86-32, only the ABCD registers have 8-bit subregisters.
2631 if (!Subtarget->is64Bit()) {
2632 const TargetRegisterClass *TRC;
2633 switch (N0.getSimpleValueType().SimpleTy) {
2634 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2635 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2636 default: llvm_unreachable("Unsupported TEST operand type!");
2638 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2639 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2640 Reg.getValueType(), Reg, RC), 0);
2643 // Extract the l-register.
2644 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2648 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2650 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2651 // one, do not call ReplaceAllUsesWith.
2652 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2653 SDValue(NewNode, 0));
2657 // For example, "testl %eax, $2048" to "testb %ah, $8".
2658 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2659 (!(C->getZExtValue() & 0x8000) ||
2660 HasNoSignedComparisonUses(Node))) {
2661 // Shift the immediate right by 8 bits.
2662 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2664 SDValue Reg = N0.getNode()->getOperand(0);
2666 // Put the value in an ABCD register.
2667 const TargetRegisterClass *TRC;
2668 switch (N0.getSimpleValueType().SimpleTy) {
2669 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2670 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2671 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2672 default: llvm_unreachable("Unsupported TEST operand type!");
2674 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2675 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2676 Reg.getValueType(), Reg, RC), 0);
2678 // Extract the h-register.
2679 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2682 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2683 // target GR8_NOREX registers, so make sure the register class is
2685 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2686 MVT::i32, Subreg, ShiftedImm);
2687 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2688 // one, do not call ReplaceAllUsesWith.
2689 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2690 SDValue(NewNode, 0));
2694 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2695 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2696 N0.getValueType() != MVT::i16 &&
2697 (!(C->getZExtValue() & 0x8000) ||
2698 HasNoSignedComparisonUses(Node))) {
2699 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2700 SDValue Reg = N0.getNode()->getOperand(0);
2702 // Extract the 16-bit subregister.
2703 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2707 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2709 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2710 // one, do not call ReplaceAllUsesWith.
2711 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2712 SDValue(NewNode, 0));
2716 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2717 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2718 N0.getValueType() == MVT::i64 &&
2719 (!(C->getZExtValue() & 0x80000000) ||
2720 HasNoSignedComparisonUses(Node))) {
2721 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2722 SDValue Reg = N0.getNode()->getOperand(0);
2724 // Extract the 32-bit subregister.
2725 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2729 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2731 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2732 // one, do not call ReplaceAllUsesWith.
2733 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2734 SDValue(NewNode, 0));
2741 // Change a chain of {load; incr or dec; store} of the same value into
2742 // a simple increment or decrement through memory of that value, if the
2743 // uses of the modified value and its address are suitable.
2744 // The DEC64m tablegen pattern is currently not able to match the case where
2745 // the EFLAGS on the original DEC are used. (This also applies to
2746 // {INC,DEC}X{64,32,16,8}.)
2747 // We'll need to improve tablegen to allow flags to be transferred from a
2748 // node in the pattern to the result node. probably with a new keyword
2749 // for example, we have this
2750 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2751 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2752 // (implicit EFLAGS)]>;
2753 // but maybe need something like this
2754 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2755 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2756 // (transferrable EFLAGS)]>;
2758 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2759 SDValue StoredVal = StoreNode->getOperand(1);
2760 unsigned Opc = StoredVal->getOpcode();
2762 LoadSDNode *LoadNode = nullptr;
2764 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2765 LoadNode, InputChain))
2768 SDValue Base, Scale, Index, Disp, Segment;
2769 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2770 Base, Scale, Index, Disp, Segment))
2773 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2774 MemOp[0] = StoreNode->getMemOperand();
2775 MemOp[1] = LoadNode->getMemOperand();
2776 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2777 EVT LdVT = LoadNode->getMemoryVT();
2778 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2779 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2781 MVT::i32, MVT::Other, Ops);
2782 Result->setMemRefs(MemOp, MemOp + 2);
2784 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2785 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2791 SDNode *ResNode = SelectCode(Node);
2793 DEBUG(dbgs() << "=> ";
2794 if (ResNode == nullptr || ResNode == Node)
2797 ResNode->dump(CurDAG);
2803 bool X86DAGToDAGISel::
2804 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2805 std::vector<SDValue> &OutOps) {
2806 SDValue Op0, Op1, Op2, Op3, Op4;
2807 switch (ConstraintCode) {
2808 case 'o': // offsetable ??
2809 case 'v': // not offsetable ??
2810 default: return true;
2812 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2817 OutOps.push_back(Op0);
2818 OutOps.push_back(Op1);
2819 OutOps.push_back(Op2);
2820 OutOps.push_back(Op3);
2821 OutOps.push_back(Op4);
2825 /// createX86ISelDag - This pass converts a legalized DAG into a
2826 /// X86-specific DAG, ready for instruction scheduling.
2828 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2829 CodeGenOpt::Level OptLevel) {
2830 return new X86DAGToDAGISel(TM, OptLevel);