1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "X86TargetMachine.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/CFG.h"
27 #include "llvm/Type.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/Streams.h"
41 #include "llvm/Support/raw_ostream.h"
42 #include "llvm/ADT/SmallPtrSet.h"
43 #include "llvm/ADT/Statistic.h"
46 #include "llvm/Support/CommandLine.h"
47 static cl::opt<bool> AvoidDupAddrCompute("x86-avoid-dup-address", cl::Hidden);
49 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
51 //===----------------------------------------------------------------------===//
52 // Pattern Matcher Implementation
53 //===----------------------------------------------------------------------===//
56 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
57 /// SDValue's instead of register numbers for the leaves of the matched
59 struct X86ISelAddressMode {
65 struct { // This is really a union, discriminated by BaseType!
78 unsigned Align; // CP alignment.
79 unsigned char SymbolFlags; // X86II::MO_*
82 : BaseType(RegBase), Scale(1), IndexReg(), Disp(0),
83 Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0), SymbolFlags(0) {
86 bool hasSymbolicDisplacement() const {
87 return GV != 0 || CP != 0 || ES != 0 || JT != -1;
90 bool hasBaseOrIndexReg() const {
91 return IndexReg.getNode() != 0 || Base.Reg.getNode() != 0;
94 /// isRIPRelative - Return true if this addressing mode is already RIP
96 bool isRIPRelative() const {
97 if (BaseType != RegBase) return false;
98 if (RegisterSDNode *RegNode =
99 dyn_cast_or_null<RegisterSDNode>(Base.Reg.getNode()))
100 return RegNode->getReg() == X86::RIP;
104 void setBaseReg(SDValue Reg) {
110 cerr << "X86ISelAddressMode " << this << '\n';
112 if (Base.Reg.getNode() != 0)
113 Base.Reg.getNode()->dump();
116 cerr << " Base.FrameIndex " << Base.FrameIndex << '\n';
117 cerr << " Scale" << Scale << '\n';
119 if (IndexReg.getNode() != 0)
120 IndexReg.getNode()->dump();
123 cerr << " Disp " << Disp << '\n';
140 cerr << " JT" << JT << " Align" << Align << '\n';
146 //===--------------------------------------------------------------------===//
147 /// ISel - X86 specific code to select X86 machine instructions for
148 /// SelectionDAG operations.
150 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
151 /// X86Lowering - This object fully describes how to lower LLVM code to an
152 /// X86-specific SelectionDAG.
153 X86TargetLowering &X86Lowering;
155 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
156 /// make the right decision when generating code for different targets.
157 const X86Subtarget *Subtarget;
159 /// OptForSize - If true, selector should try to optimize for code size
160 /// instead of performance.
164 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
165 : SelectionDAGISel(tm, OptLevel),
166 X86Lowering(*tm.getTargetLowering()),
167 Subtarget(&tm.getSubtarget<X86Subtarget>()),
170 virtual const char *getPassName() const {
171 return "X86 DAG->DAG Instruction Selection";
174 /// InstructionSelect - This callback is invoked by
175 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
176 virtual void InstructionSelect();
178 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
181 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
183 // Include the pieces autogenerated from the target description.
184 #include "X86GenDAGISel.inc"
187 SDNode *Select(SDValue N);
188 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
189 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
191 bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
192 bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
193 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
194 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
195 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
197 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
198 bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
199 SDValue &Scale, SDValue &Index, SDValue &Disp,
201 bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
202 SDValue &Scale, SDValue &Index, SDValue &Disp);
203 bool SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
204 SDValue &Scale, SDValue &Index, SDValue &Disp);
205 bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
206 SDValue N, SDValue &Base, SDValue &Scale,
207 SDValue &Index, SDValue &Disp,
209 SDValue &InChain, SDValue &OutChain);
210 bool TryFoldLoad(SDValue P, SDValue N,
211 SDValue &Base, SDValue &Scale,
212 SDValue &Index, SDValue &Disp,
214 void PreprocessForRMW();
215 void PreprocessForFPConvert();
217 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
218 /// inline asm expressions.
219 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
221 std::vector<SDValue> &OutOps);
223 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
225 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
226 SDValue &Scale, SDValue &Index,
227 SDValue &Disp, SDValue &Segment) {
228 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
229 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
231 Scale = getI8Imm(AM.Scale);
233 // These are 32-bit even in 64-bit mode since RIP relative offset
236 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp,
239 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
240 AM.Align, AM.Disp, AM.SymbolFlags);
242 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
243 else if (AM.JT != -1)
244 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
246 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
248 if (AM.Segment.getNode())
249 Segment = AM.Segment;
251 Segment = CurDAG->getRegister(0, MVT::i32);
254 /// getI8Imm - Return a target constant with the specified value, of type
256 inline SDValue getI8Imm(unsigned Imm) {
257 return CurDAG->getTargetConstant(Imm, MVT::i8);
260 /// getI16Imm - Return a target constant with the specified value, of type
262 inline SDValue getI16Imm(unsigned Imm) {
263 return CurDAG->getTargetConstant(Imm, MVT::i16);
266 /// getI32Imm - Return a target constant with the specified value, of type
268 inline SDValue getI32Imm(unsigned Imm) {
269 return CurDAG->getTargetConstant(Imm, MVT::i32);
272 /// getGlobalBaseReg - Return an SDNode that returns the value of
273 /// the global base register. Output instructions required to
274 /// initialize the global base register, if necessary.
276 SDNode *getGlobalBaseReg();
278 /// getTargetMachine - Return a reference to the TargetMachine, casted
279 /// to the target-specific type.
280 const X86TargetMachine &getTargetMachine() {
281 return static_cast<const X86TargetMachine &>(TM);
284 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
285 /// to the target-specific type.
286 const X86InstrInfo *getInstrInfo() {
287 return getTargetMachine().getInstrInfo();
297 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
298 SDNode *Root) const {
299 if (OptLevel == CodeGenOpt::None) return false;
302 switch (U->getOpcode()) {
310 SDValue Op1 = U->getOperand(1);
312 // If the other operand is a 8-bit immediate we should fold the immediate
313 // instead. This reduces code size.
315 // movl 4(%esp), %eax
319 // addl 4(%esp), %eax
320 // The former is 2 bytes shorter. In case where the increment is 1, then
321 // the saving can be 4 bytes (by using incl %eax).
322 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
323 if (Imm->getAPIntValue().isSignedIntN(8))
326 // If the other operand is a TLS address, we should fold it instead.
329 // leal i@NTPOFF(%eax), %eax
331 // movl $i@NTPOFF, %eax
333 // if the block also has an access to a second TLS address this will save
335 // FIXME: This is probably also true for non TLS addresses.
336 if (Op1.getOpcode() == X86ISD::Wrapper) {
337 SDValue Val = Op1.getOperand(0);
338 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
344 // Proceed to 'generic' cycle finder code
345 return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root);
348 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
349 /// and move load below the TokenFactor. Replace store's chain operand with
350 /// load's chain result.
351 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
352 SDValue Store, SDValue TF) {
353 SmallVector<SDValue, 4> Ops;
354 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
355 if (Load.getNode() == TF.getOperand(i).getNode())
356 Ops.push_back(Load.getOperand(0));
358 Ops.push_back(TF.getOperand(i));
359 SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
360 SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
363 CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
364 Store.getOperand(2), Store.getOperand(3));
367 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
369 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
371 if (N.getOpcode() == ISD::BIT_CONVERT)
374 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
375 if (!LD || LD->isVolatile())
377 if (LD->getAddressingMode() != ISD::UNINDEXED)
380 ISD::LoadExtType ExtType = LD->getExtensionType();
381 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
385 N.getOperand(1) == Address &&
386 N.getNode()->isOperandOf(Chain.getNode())) {
393 /// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
394 /// operand and move load below the call's chain operand.
395 static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
396 SDValue Call, SDValue CallSeqStart) {
397 SmallVector<SDValue, 8> Ops;
398 SDValue Chain = CallSeqStart.getOperand(0);
399 if (Chain.getNode() == Load.getNode())
400 Ops.push_back(Load.getOperand(0));
402 assert(Chain.getOpcode() == ISD::TokenFactor &&
403 "Unexpected CallSeqStart chain operand");
404 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
405 if (Chain.getOperand(i).getNode() == Load.getNode())
406 Ops.push_back(Load.getOperand(0));
408 Ops.push_back(Chain.getOperand(i));
410 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
411 MVT::Other, &Ops[0], Ops.size());
413 Ops.push_back(NewChain);
415 for (unsigned i = 1, e = CallSeqStart.getNumOperands(); i != e; ++i)
416 Ops.push_back(CallSeqStart.getOperand(i));
417 CurDAG->UpdateNodeOperands(CallSeqStart, &Ops[0], Ops.size());
418 CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
419 Load.getOperand(1), Load.getOperand(2));
421 Ops.push_back(SDValue(Load.getNode(), 1));
422 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
423 Ops.push_back(Call.getOperand(i));
424 CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
427 /// isCalleeLoad - Return true if call address is a load and it can be
428 /// moved below CALLSEQ_START and the chains leading up to the call.
429 /// Return the CALLSEQ_START by reference as a second output.
430 static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
431 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
433 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
436 LD->getAddressingMode() != ISD::UNINDEXED ||
437 LD->getExtensionType() != ISD::NON_EXTLOAD)
440 // Now let's find the callseq_start.
441 while (Chain.getOpcode() != ISD::CALLSEQ_START) {
442 if (!Chain.hasOneUse())
444 Chain = Chain.getOperand(0);
447 if (Chain.getOperand(0).getNode() == Callee.getNode())
449 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
450 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()))
456 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
457 /// This is only run if not in -O0 mode.
458 /// This allows the instruction selector to pick more read-modify-write
459 /// instructions. This is a common case:
469 /// [TokenFactor] [Op]
476 /// The fact the store's chain operand != load's chain will prevent the
477 /// (store (op (load))) instruction from being selected. We can transform it to:
496 void X86DAGToDAGISel::PreprocessForRMW() {
497 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
498 E = CurDAG->allnodes_end(); I != E; ++I) {
499 if (I->getOpcode() == X86ISD::CALL) {
500 /// Also try moving call address load from outside callseq_start to just
501 /// before the call to allow it to be folded.
519 SDValue Chain = I->getOperand(0);
520 SDValue Load = I->getOperand(1);
521 if (!isCalleeLoad(Load, Chain))
523 MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
528 if (!ISD::isNON_TRUNCStore(I))
530 SDValue Chain = I->getOperand(0);
532 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
535 SDValue N1 = I->getOperand(1);
536 SDValue N2 = I->getOperand(2);
537 if ((N1.getValueType().isFloatingPoint() &&
538 !N1.getValueType().isVector()) ||
544 unsigned Opcode = N1.getNode()->getOpcode();
553 case ISD::VECTOR_SHUFFLE: {
554 SDValue N10 = N1.getOperand(0);
555 SDValue N11 = N1.getOperand(1);
556 RModW = isRMWLoad(N10, Chain, N2, Load);
558 RModW = isRMWLoad(N11, Chain, N2, Load);
571 SDValue N10 = N1.getOperand(0);
572 RModW = isRMWLoad(N10, Chain, N2, Load);
578 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
585 /// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend
586 /// nodes that target the FP stack to be store and load to the stack. This is a
587 /// gross hack. We would like to simply mark these as being illegal, but when
588 /// we do that, legalize produces these when it expands calls, then expands
589 /// these in the same legalize pass. We would like dag combine to be able to
590 /// hack on these between the call expansion and the node legalization. As such
591 /// this pass basically does "really late" legalization of these inline with the
593 void X86DAGToDAGISel::PreprocessForFPConvert() {
594 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
595 E = CurDAG->allnodes_end(); I != E; ) {
596 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
597 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
600 // If the source and destination are SSE registers, then this is a legal
601 // conversion that should not be lowered.
602 EVT SrcVT = N->getOperand(0).getValueType();
603 EVT DstVT = N->getValueType(0);
604 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
605 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
606 if (SrcIsSSE && DstIsSSE)
609 if (!SrcIsSSE && !DstIsSSE) {
610 // If this is an FPStack extension, it is a noop.
611 if (N->getOpcode() == ISD::FP_EXTEND)
613 // If this is a value-preserving FPStack truncation, it is a noop.
614 if (N->getConstantOperandVal(1))
618 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
619 // FPStack has extload and truncstore. SSE can fold direct loads into other
620 // operations. Based on this, decide what we want to do.
622 if (N->getOpcode() == ISD::FP_ROUND)
623 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
625 MemVT = SrcIsSSE ? SrcVT : DstVT;
627 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
628 DebugLoc dl = N->getDebugLoc();
630 // FIXME: optimize the case where the src/dest is a load or store?
631 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
633 MemTmp, NULL, 0, MemVT);
634 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
637 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
638 // extload we created. This will cause general havok on the dag because
639 // anything below the conversion could be folded into other existing nodes.
640 // To avoid invalidating 'I', back it up to the convert node.
642 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
644 // Now that we did that, the node is dead. Increment the iterator to the
645 // next node to process, then delete N.
647 CurDAG->DeleteNode(N);
651 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
652 /// when it has created a SelectionDAG for us to codegen.
653 void X86DAGToDAGISel::InstructionSelect() {
654 const Function *F = MF->getFunction();
655 OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
658 if (OptLevel != CodeGenOpt::None)
661 // FIXME: This should only happen when not compiled with -O0.
662 PreprocessForFPConvert();
664 // Codegen the basic block.
666 DEBUG(errs() << "===== Instruction selection begins:\n");
671 DEBUG(errs() << "===== Instruction selection ends:\n");
674 CurDAG->RemoveDeadNodes();
677 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
678 /// the main function.
679 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
680 MachineFrameInfo *MFI) {
681 const TargetInstrInfo *TII = TM.getInstrInfo();
682 if (Subtarget->isTargetCygMing())
683 BuildMI(BB, DebugLoc::getUnknownLoc(),
684 TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
687 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
688 // If this is main, emit special code for main.
689 MachineBasicBlock *BB = MF.begin();
690 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
691 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
695 bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
696 X86ISelAddressMode &AM) {
697 assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
698 SDValue Segment = N.getOperand(0);
700 if (AM.Segment.getNode() == 0) {
701 AM.Segment = Segment;
708 bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
709 // This optimization is valid because the GNU TLS model defines that
710 // gs:0 (or fs:0 on X86-64) contains its own address.
711 // For more information see http://people.redhat.com/drepper/tls.pdf
713 SDValue Address = N.getOperand(1);
714 if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
715 !MatchSegmentBaseAddress (Address, AM))
721 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
722 /// into an addressing mode. These wrap things that will resolve down into a
723 /// symbol reference. If no match is possible, this returns true, otherwise it
725 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
726 // If the addressing mode already has a symbol as the displacement, we can
727 // never match another symbol.
728 if (AM.hasSymbolicDisplacement())
731 SDValue N0 = N.getOperand(0);
732 CodeModel::Model M = TM.getCodeModel();
734 // Handle X86-64 rip-relative addresses. We check this before checking direct
735 // folding because RIP is preferable to non-RIP accesses.
736 if (Subtarget->is64Bit() &&
737 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
738 // they cannot be folded into immediate fields.
739 // FIXME: This can be improved for kernel and other models?
740 (M == CodeModel::Small || M == CodeModel::Kernel) &&
741 // Base and index reg must be 0 in order to use %rip as base and lowering
743 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
744 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
745 int64_t Offset = AM.Disp + G->getOffset();
746 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
747 AM.GV = G->getGlobal();
749 AM.SymbolFlags = G->getTargetFlags();
750 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
751 int64_t Offset = AM.Disp + CP->getOffset();
752 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
753 AM.CP = CP->getConstVal();
754 AM.Align = CP->getAlignment();
756 AM.SymbolFlags = CP->getTargetFlags();
757 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
758 AM.ES = S->getSymbol();
759 AM.SymbolFlags = S->getTargetFlags();
761 JumpTableSDNode *J = cast<JumpTableSDNode>(N0);
762 AM.JT = J->getIndex();
763 AM.SymbolFlags = J->getTargetFlags();
766 if (N.getOpcode() == X86ISD::WrapperRIP)
767 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
771 // Handle the case when globals fit in our immediate field: This is true for
772 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit
773 // mode, this results in a non-RIP-relative computation.
774 if (!Subtarget->is64Bit() ||
775 ((M == CodeModel::Small || M == CodeModel::Kernel) &&
776 TM.getRelocationModel() == Reloc::Static)) {
777 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
778 AM.GV = G->getGlobal();
779 AM.Disp += G->getOffset();
780 AM.SymbolFlags = G->getTargetFlags();
781 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
782 AM.CP = CP->getConstVal();
783 AM.Align = CP->getAlignment();
784 AM.Disp += CP->getOffset();
785 AM.SymbolFlags = CP->getTargetFlags();
786 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
787 AM.ES = S->getSymbol();
788 AM.SymbolFlags = S->getTargetFlags();
790 JumpTableSDNode *J = cast<JumpTableSDNode>(N0);
791 AM.JT = J->getIndex();
792 AM.SymbolFlags = J->getTargetFlags();
800 /// MatchAddress - Add the specified node to the specified addressing mode,
801 /// returning true if it cannot be done. This just pattern matches for the
803 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
804 if (MatchAddressRecursively(N, AM, 0))
807 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
808 // a smaller encoding and avoids a scaled-index.
810 AM.BaseType == X86ISelAddressMode::RegBase &&
811 AM.Base.Reg.getNode() == 0) {
812 AM.Base.Reg = AM.IndexReg;
816 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
817 // because it has a smaller encoding.
818 // TODO: Which other code models can use this?
819 if (TM.getCodeModel() == CodeModel::Small &&
820 Subtarget->is64Bit() &&
822 AM.BaseType == X86ISelAddressMode::RegBase &&
823 AM.Base.Reg.getNode() == 0 &&
824 AM.IndexReg.getNode() == 0 &&
825 AM.SymbolFlags == 0 &&
826 AM.hasSymbolicDisplacement())
827 AM.Base.Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
832 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
834 bool is64Bit = Subtarget->is64Bit();
835 DebugLoc dl = N.getDebugLoc();
837 errs() << "MatchAddress: ";
842 return MatchAddressBase(N, AM);
844 CodeModel::Model M = TM.getCodeModel();
846 // If this is already a %rip relative address, we can only merge immediates
847 // into it. Instead of handling this in every case, we handle it here.
848 // RIP relative addressing: %rip + 32-bit displacement!
849 if (AM.isRIPRelative()) {
850 // FIXME: JumpTable and ExternalSymbol address currently don't like
851 // displacements. It isn't very important, but this should be fixed for
853 if (!AM.ES && AM.JT != -1) return true;
855 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) {
856 int64_t Val = AM.Disp + Cst->getSExtValue();
857 if (X86::isOffsetSuitableForCodeModel(Val, M,
858 AM.hasSymbolicDisplacement())) {
866 switch (N.getOpcode()) {
868 case ISD::Constant: {
869 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
871 X86::isOffsetSuitableForCodeModel(AM.Disp + Val, M,
872 AM.hasSymbolicDisplacement())) {
879 case X86ISD::SegmentBaseAddress:
880 if (!MatchSegmentBaseAddress(N, AM))
884 case X86ISD::Wrapper:
885 case X86ISD::WrapperRIP:
886 if (!MatchWrapper(N, AM))
891 if (!MatchLoad(N, AM))
895 case ISD::FrameIndex:
896 if (AM.BaseType == X86ISelAddressMode::RegBase
897 && AM.Base.Reg.getNode() == 0) {
898 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
899 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
905 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
909 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
910 unsigned Val = CN->getZExtValue();
911 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
912 // that the base operand remains free for further matching. If
913 // the base doesn't end up getting used, a post-processing step
914 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
915 if (Val == 1 || Val == 2 || Val == 3) {
917 SDValue ShVal = N.getNode()->getOperand(0);
919 // Okay, we know that we have a scale by now. However, if the scaled
920 // value is an add of something and a constant, we can fold the
921 // constant into the disp field here.
922 if (ShVal.getNode()->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
923 isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
924 AM.IndexReg = ShVal.getNode()->getOperand(0);
925 ConstantSDNode *AddVal =
926 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
927 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
929 X86::isOffsetSuitableForCodeModel(Disp, M,
930 AM.hasSymbolicDisplacement()))
944 // A mul_lohi where we need the low part can be folded as a plain multiply.
945 if (N.getResNo() != 0) break;
948 case X86ISD::MUL_IMM:
949 // X*[3,5,9] -> X+X*[2,4,8]
950 if (AM.BaseType == X86ISelAddressMode::RegBase &&
951 AM.Base.Reg.getNode() == 0 &&
952 AM.IndexReg.getNode() == 0) {
954 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
955 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
956 CN->getZExtValue() == 9) {
957 AM.Scale = unsigned(CN->getZExtValue())-1;
959 SDValue MulVal = N.getNode()->getOperand(0);
962 // Okay, we know that we have a scale by now. However, if the scaled
963 // value is an add of something and a constant, we can fold the
964 // constant into the disp field here.
965 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
966 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
967 Reg = MulVal.getNode()->getOperand(0);
968 ConstantSDNode *AddVal =
969 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
970 uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
973 X86::isOffsetSuitableForCodeModel(Disp, M,
974 AM.hasSymbolicDisplacement()))
977 Reg = N.getNode()->getOperand(0);
979 Reg = N.getNode()->getOperand(0);
982 AM.IndexReg = AM.Base.Reg = Reg;
989 // Given A-B, if A can be completely folded into the address and
990 // the index field with the index field unused, use -B as the index.
991 // This is a win if a has multiple parts that can be folded into
992 // the address. Also, this saves a mov if the base register has
993 // other uses, since it avoids a two-address sub instruction, however
994 // it costs an additional mov if the index register has other uses.
996 // Test if the LHS of the sub can be folded.
997 X86ISelAddressMode Backup = AM;
998 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1002 // Test if the index field is free for use.
1003 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1008 SDValue RHS = N.getNode()->getOperand(1);
1009 // If the RHS involves a register with multiple uses, this
1010 // transformation incurs an extra mov, due to the neg instruction
1011 // clobbering its operand.
1012 if (!RHS.getNode()->hasOneUse() ||
1013 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1014 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1015 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1016 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1017 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1019 // If the base is a register with multiple uses, this
1020 // transformation may save a mov.
1021 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1022 AM.Base.Reg.getNode() &&
1023 !AM.Base.Reg.getNode()->hasOneUse()) ||
1024 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1026 // If the folded LHS was interesting, this transformation saves
1027 // address arithmetic.
1028 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1029 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1030 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1032 // If it doesn't look like it may be an overall win, don't do it.
1038 // Ok, the transformation is legal and appears profitable. Go for it.
1039 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1040 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1044 // Insert the new nodes into the topological ordering.
1045 if (Zero.getNode()->getNodeId() == -1 ||
1046 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1047 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
1048 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
1050 if (Neg.getNode()->getNodeId() == -1 ||
1051 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1052 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
1053 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
1059 X86ISelAddressMode Backup = AM;
1060 if (!MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1) &&
1061 !MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1))
1064 if (!MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1) &&
1065 !MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1))
1069 // If we couldn't fold both operands into the address at the same time,
1070 // see if we can just put each operand into a register and fold at least
1072 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1073 !AM.Base.Reg.getNode() &&
1074 !AM.IndexReg.getNode()) {
1075 AM.Base.Reg = N.getNode()->getOperand(0);
1076 AM.IndexReg = N.getNode()->getOperand(1);
1084 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1085 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1086 X86ISelAddressMode Backup = AM;
1087 uint64_t Offset = CN->getSExtValue();
1088 // Start with the LHS as an addr mode.
1089 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1090 // Address could not have picked a GV address for the displacement.
1092 // On x86-64, the resultant disp must fit in 32-bits.
1094 X86::isOffsetSuitableForCodeModel(AM.Disp + Offset, M,
1095 AM.hasSymbolicDisplacement())) &&
1096 // Check to see if the LHS & C is zero.
1097 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
1106 // Perform some heroic transforms on an and of a constant-count shift
1107 // with a constant to enable use of the scaled offset field.
1109 SDValue Shift = N.getOperand(0);
1110 if (Shift.getNumOperands() != 2) break;
1112 // Scale must not be used already.
1113 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1115 SDValue X = Shift.getOperand(0);
1116 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
1117 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
1118 if (!C1 || !C2) break;
1120 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This
1121 // allows us to convert the shift and and into an h-register extract and
1123 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) {
1124 unsigned ScaleLog = 8 - C1->getZExtValue();
1125 if (ScaleLog > 0 && ScaleLog < 4 &&
1126 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
1127 SDValue Eight = CurDAG->getConstant(8, MVT::i8);
1128 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
1129 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1131 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
1133 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
1134 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1137 // Insert the new nodes into the topological ordering.
1138 if (Eight.getNode()->getNodeId() == -1 ||
1139 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1140 CurDAG->RepositionNode(X.getNode(), Eight.getNode());
1141 Eight.getNode()->setNodeId(X.getNode()->getNodeId());
1143 if (Mask.getNode()->getNodeId() == -1 ||
1144 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1145 CurDAG->RepositionNode(X.getNode(), Mask.getNode());
1146 Mask.getNode()->setNodeId(X.getNode()->getNodeId());
1148 if (Srl.getNode()->getNodeId() == -1 ||
1149 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1150 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode());
1151 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId());
1153 if (And.getNode()->getNodeId() == -1 ||
1154 And.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1155 CurDAG->RepositionNode(N.getNode(), And.getNode());
1156 And.getNode()->setNodeId(N.getNode()->getNodeId());
1158 if (ShlCount.getNode()->getNodeId() == -1 ||
1159 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1160 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode());
1161 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId());
1163 if (Shl.getNode()->getNodeId() == -1 ||
1164 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1165 CurDAG->RepositionNode(N.getNode(), Shl.getNode());
1166 Shl.getNode()->setNodeId(N.getNode()->getNodeId());
1168 CurDAG->ReplaceAllUsesWith(N, Shl);
1170 AM.Scale = (1 << ScaleLog);
1175 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
1176 // allows us to fold the shift into this addressing mode.
1177 if (Shift.getOpcode() != ISD::SHL) break;
1179 // Not likely to be profitable if either the AND or SHIFT node has more
1180 // than one use (unless all uses are for address computation). Besides,
1181 // isel mechanism requires their node ids to be reused.
1182 if (!N.hasOneUse() || !Shift.hasOneUse())
1185 // Verify that the shift amount is something we can fold.
1186 unsigned ShiftCst = C1->getZExtValue();
1187 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
1190 // Get the new AND mask, this folds to a constant.
1191 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1192 SDValue(C2, 0), SDValue(C1, 0));
1193 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
1195 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1196 NewAND, SDValue(C1, 0));
1198 // Insert the new nodes into the topological ordering.
1199 if (C1->getNodeId() > X.getNode()->getNodeId()) {
1200 CurDAG->RepositionNode(X.getNode(), C1);
1201 C1->setNodeId(X.getNode()->getNodeId());
1203 if (NewANDMask.getNode()->getNodeId() == -1 ||
1204 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1205 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
1206 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
1208 if (NewAND.getNode()->getNodeId() == -1 ||
1209 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1210 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
1211 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
1213 if (NewSHIFT.getNode()->getNodeId() == -1 ||
1214 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1215 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
1216 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
1219 CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
1221 AM.Scale = 1 << ShiftCst;
1222 AM.IndexReg = NewAND;
1227 return MatchAddressBase(N, AM);
1230 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1231 /// specified addressing mode without any further recursion.
1232 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1233 // Is the base register already occupied?
1234 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
1235 // If so, check to see if the scale index register is set.
1236 if (AM.IndexReg.getNode() == 0) {
1242 // Otherwise, we cannot select it.
1246 // Default, generate it as a register.
1247 AM.BaseType = X86ISelAddressMode::RegBase;
1252 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1253 /// It returns the operands which make up the maximal addressing mode it can
1254 /// match by reference.
1255 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
1256 SDValue &Scale, SDValue &Index,
1257 SDValue &Disp, SDValue &Segment) {
1258 X86ISelAddressMode AM;
1260 if (AvoidDupAddrCompute && !N.hasOneUse()) {
1261 unsigned Opcode = N.getOpcode();
1262 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex &&
1263 Opcode != X86ISD::Wrapper && Opcode != X86ISD::WrapperRIP) {
1264 // If we are able to fold N into addressing mode, then we'll allow it even
1265 // if N has multiple uses. In general, addressing computation is used as
1266 // addresses by all of its uses. But watch out for CopyToReg uses, that
1267 // means the address computation is liveout. It will be computed by a LEA
1268 // so we want to avoid computing the address twice.
1269 for (SDNode::use_iterator UI = N.getNode()->use_begin(),
1270 UE = N.getNode()->use_end(); UI != UE; ++UI) {
1271 if (UI->getOpcode() == ISD::CopyToReg) {
1272 MatchAddressBase(N, AM);
1280 if (!Done && MatchAddress(N, AM))
1283 EVT VT = N.getValueType();
1284 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1285 if (!AM.Base.Reg.getNode())
1286 AM.Base.Reg = CurDAG->getRegister(0, VT);
1289 if (!AM.IndexReg.getNode())
1290 AM.IndexReg = CurDAG->getRegister(0, VT);
1292 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1296 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1297 /// match a load whose top elements are either undef or zeros. The load flavor
1298 /// is derived from the type of N, which is either v4f32 or v2f64.
1299 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
1300 SDValue N, SDValue &Base,
1301 SDValue &Scale, SDValue &Index,
1302 SDValue &Disp, SDValue &Segment,
1304 SDValue &OutChain) {
1305 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1306 InChain = N.getOperand(0).getValue(1);
1307 if (ISD::isNON_EXTLoad(InChain.getNode()) &&
1308 InChain.getValue(0).hasOneUse() &&
1310 IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
1311 LoadSDNode *LD = cast<LoadSDNode>(InChain);
1312 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1314 OutChain = LD->getChain();
1319 // Also handle the case where we explicitly require zeros in the top
1320 // elements. This is a vector shuffle from the zero vector.
1321 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1322 // Check to see if the top elements are all zeros (or bitcast of zeros).
1323 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1324 N.getOperand(0).getNode()->hasOneUse() &&
1325 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1326 N.getOperand(0).getOperand(0).hasOneUse()) {
1327 // Okay, this is a zero extending load. Fold it.
1328 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1329 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1331 OutChain = LD->getChain();
1332 InChain = SDValue(LD, 1);
1339 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1340 /// mode it matches can be cost effectively emitted as an LEA instruction.
1341 bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
1342 SDValue &Base, SDValue &Scale,
1343 SDValue &Index, SDValue &Disp) {
1344 X86ISelAddressMode AM;
1346 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1348 SDValue Copy = AM.Segment;
1349 SDValue T = CurDAG->getRegister(0, MVT::i32);
1351 if (MatchAddress(N, AM))
1353 assert (T == AM.Segment);
1356 EVT VT = N.getValueType();
1357 unsigned Complexity = 0;
1358 if (AM.BaseType == X86ISelAddressMode::RegBase)
1359 if (AM.Base.Reg.getNode())
1362 AM.Base.Reg = CurDAG->getRegister(0, VT);
1363 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1366 if (AM.IndexReg.getNode())
1369 AM.IndexReg = CurDAG->getRegister(0, VT);
1371 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1376 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1377 // to a LEA. This is determined with some expermentation but is by no means
1378 // optimal (especially for code size consideration). LEA is nice because of
1379 // its three-address nature. Tweak the cost function again when we can run
1380 // convertToThreeAddress() at register allocation time.
1381 if (AM.hasSymbolicDisplacement()) {
1382 // For X86-64, we should always use lea to materialize RIP relative
1384 if (Subtarget->is64Bit())
1390 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
1393 // If it isn't worth using an LEA, reject it.
1394 if (Complexity <= 2)
1398 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1402 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1403 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
1404 SDValue &Scale, SDValue &Index,
1406 assert(Op.getOpcode() == X86ISD::TLSADDR);
1407 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1408 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1410 X86ISelAddressMode AM;
1411 AM.GV = GA->getGlobal();
1412 AM.Disp += GA->getOffset();
1413 AM.Base.Reg = CurDAG->getRegister(0, N.getValueType());
1414 AM.SymbolFlags = GA->getTargetFlags();
1416 if (N.getValueType() == MVT::i32) {
1418 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1420 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1424 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1429 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
1430 SDValue &Base, SDValue &Scale,
1431 SDValue &Index, SDValue &Disp,
1433 if (ISD::isNON_EXTLoad(N.getNode()) &&
1435 IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
1436 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
1440 /// getGlobalBaseReg - Return an SDNode that returns the value of
1441 /// the global base register. Output instructions required to
1442 /// initialize the global base register, if necessary.
1444 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1445 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1446 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1449 static SDNode *FindCallStartFromCall(SDNode *Node) {
1450 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1451 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1452 "Node doesn't have a token chain argument!");
1453 return FindCallStartFromCall(Node->getOperand(0).getNode());
1456 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1457 SDValue Chain = Node->getOperand(0);
1458 SDValue In1 = Node->getOperand(1);
1459 SDValue In2L = Node->getOperand(2);
1460 SDValue In2H = Node->getOperand(3);
1461 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1462 if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1464 SDValue LSI = Node->getOperand(4); // MemOperand
1465 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain};
1466 return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
1467 MVT::i32, MVT::i32, MVT::Other, Ops,
1468 array_lengthof(Ops));
1471 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1472 if (Node->hasAnyUseOfValue(0))
1475 // Optimize common patterns for __sync_add_and_fetch and
1476 // __sync_sub_and_fetch where the result is not used. This allows us
1477 // to use "lock" version of add, sub, inc, dec instructions.
1478 // FIXME: Do not use special instructions but instead add the "lock"
1479 // prefix to the target node somehow. The extra information will then be
1480 // transferred to machine instruction and it denotes the prefix.
1481 SDValue Chain = Node->getOperand(0);
1482 SDValue Ptr = Node->getOperand(1);
1483 SDValue Val = Node->getOperand(2);
1484 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1485 if (!SelectAddr(Ptr, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1488 bool isInc = false, isDec = false, isSub = false, isCN = false;
1489 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1492 int64_t CNVal = CN->getSExtValue();
1495 else if (CNVal == -1)
1497 else if (CNVal >= 0)
1498 Val = CurDAG->getTargetConstant(CNVal, NVT);
1501 Val = CurDAG->getTargetConstant(-CNVal, NVT);
1503 } else if (Val.hasOneUse() &&
1504 Val.getOpcode() == ISD::SUB &&
1505 X86::isZeroNode(Val.getOperand(0))) {
1507 Val = Val.getOperand(1);
1511 switch (NVT.getSimpleVT().SimpleTy) {
1515 Opc = X86::LOCK_INC8m;
1517 Opc = X86::LOCK_DEC8m;
1520 Opc = X86::LOCK_SUB8mi;
1522 Opc = X86::LOCK_SUB8mr;
1525 Opc = X86::LOCK_ADD8mi;
1527 Opc = X86::LOCK_ADD8mr;
1532 Opc = X86::LOCK_INC16m;
1534 Opc = X86::LOCK_DEC16m;
1537 if (Predicate_i16immSExt8(Val.getNode()))
1538 Opc = X86::LOCK_SUB16mi8;
1540 Opc = X86::LOCK_SUB16mi;
1542 Opc = X86::LOCK_SUB16mr;
1545 if (Predicate_i16immSExt8(Val.getNode()))
1546 Opc = X86::LOCK_ADD16mi8;
1548 Opc = X86::LOCK_ADD16mi;
1550 Opc = X86::LOCK_ADD16mr;
1555 Opc = X86::LOCK_INC32m;
1557 Opc = X86::LOCK_DEC32m;
1560 if (Predicate_i32immSExt8(Val.getNode()))
1561 Opc = X86::LOCK_SUB32mi8;
1563 Opc = X86::LOCK_SUB32mi;
1565 Opc = X86::LOCK_SUB32mr;
1568 if (Predicate_i32immSExt8(Val.getNode()))
1569 Opc = X86::LOCK_ADD32mi8;
1571 Opc = X86::LOCK_ADD32mi;
1573 Opc = X86::LOCK_ADD32mr;
1578 Opc = X86::LOCK_INC64m;
1580 Opc = X86::LOCK_DEC64m;
1582 Opc = X86::LOCK_SUB64mr;
1584 if (Predicate_i64immSExt8(Val.getNode()))
1585 Opc = X86::LOCK_SUB64mi8;
1586 else if (Predicate_i64immSExt32(Val.getNode()))
1587 Opc = X86::LOCK_SUB64mi32;
1590 Opc = X86::LOCK_ADD64mr;
1592 if (Predicate_i64immSExt8(Val.getNode()))
1593 Opc = X86::LOCK_ADD64mi8;
1594 else if (Predicate_i64immSExt32(Val.getNode()))
1595 Opc = X86::LOCK_ADD64mi32;
1601 DebugLoc dl = Node->getDebugLoc();
1602 SDValue Undef = SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
1604 SDValue MemOp = CurDAG->getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
1605 if (isInc || isDec) {
1606 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, MemOp, Chain };
1607 SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7), 0);
1608 SDValue RetVals[] = { Undef, Ret };
1609 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1611 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, MemOp, Chain };
1612 SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8), 0);
1613 SDValue RetVals[] = { Undef, Ret };
1614 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1618 SDNode *X86DAGToDAGISel::Select(SDValue N) {
1619 SDNode *Node = N.getNode();
1620 EVT NVT = Node->getValueType(0);
1622 unsigned Opcode = Node->getOpcode();
1623 DebugLoc dl = Node->getDebugLoc();
1627 errs() << std::string(Indent, ' ') << "Selecting: ";
1634 if (Node->isMachineOpcode()) {
1637 errs() << std::string(Indent-2, ' ') << "== ";
1643 return NULL; // Already selected.
1648 case X86ISD::GlobalBaseReg:
1649 return getGlobalBaseReg();
1651 case X86ISD::ATOMOR64_DAG:
1652 return SelectAtomic64(Node, X86::ATOMOR6432);
1653 case X86ISD::ATOMXOR64_DAG:
1654 return SelectAtomic64(Node, X86::ATOMXOR6432);
1655 case X86ISD::ATOMADD64_DAG:
1656 return SelectAtomic64(Node, X86::ATOMADD6432);
1657 case X86ISD::ATOMSUB64_DAG:
1658 return SelectAtomic64(Node, X86::ATOMSUB6432);
1659 case X86ISD::ATOMNAND64_DAG:
1660 return SelectAtomic64(Node, X86::ATOMNAND6432);
1661 case X86ISD::ATOMAND64_DAG:
1662 return SelectAtomic64(Node, X86::ATOMAND6432);
1663 case X86ISD::ATOMSWAP64_DAG:
1664 return SelectAtomic64(Node, X86::ATOMSWAP6432);
1666 case ISD::ATOMIC_LOAD_ADD: {
1667 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
1673 case ISD::SMUL_LOHI:
1674 case ISD::UMUL_LOHI: {
1675 SDValue N0 = Node->getOperand(0);
1676 SDValue N1 = Node->getOperand(1);
1678 bool isSigned = Opcode == ISD::SMUL_LOHI;
1680 switch (NVT.getSimpleVT().SimpleTy) {
1681 default: llvm_unreachable("Unsupported VT!");
1682 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1683 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1684 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1685 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1688 switch (NVT.getSimpleVT().SimpleTy) {
1689 default: llvm_unreachable("Unsupported VT!");
1690 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1691 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1692 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1693 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1697 unsigned LoReg, HiReg;
1698 switch (NVT.getSimpleVT().SimpleTy) {
1699 default: llvm_unreachable("Unsupported VT!");
1700 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1701 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1702 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1703 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1706 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1707 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1708 // Multiply is commmutative.
1710 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1715 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1716 N0, SDValue()).getValue(1);
1719 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1722 CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1723 array_lengthof(Ops));
1724 InFlag = SDValue(CNode, 1);
1725 // Update the chain.
1726 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1729 SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1732 // Copy the low half of the result, if it is needed.
1733 if (!N.getValue(0).use_empty()) {
1734 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1735 LoReg, NVT, InFlag);
1736 InFlag = Result.getValue(2);
1737 ReplaceUses(N.getValue(0), Result);
1740 errs() << std::string(Indent-2, ' ') << "=> ";
1741 Result.getNode()->dump(CurDAG);
1746 // Copy the high half of the result, if it is needed.
1747 if (!N.getValue(1).use_empty()) {
1749 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1750 // Prevent use of AH in a REX instruction by referencing AX instead.
1751 // Shift it down 8 bits.
1752 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1753 X86::AX, MVT::i16, InFlag);
1754 InFlag = Result.getValue(2);
1755 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
1757 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1758 // Then truncate it down to i8.
1759 Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
1762 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1763 HiReg, NVT, InFlag);
1764 InFlag = Result.getValue(2);
1766 ReplaceUses(N.getValue(1), Result);
1769 errs() << std::string(Indent-2, ' ') << "=> ";
1770 Result.getNode()->dump(CurDAG);
1784 case ISD::UDIVREM: {
1785 SDValue N0 = Node->getOperand(0);
1786 SDValue N1 = Node->getOperand(1);
1788 bool isSigned = Opcode == ISD::SDIVREM;
1790 switch (NVT.getSimpleVT().SimpleTy) {
1791 default: llvm_unreachable("Unsupported VT!");
1792 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1793 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1794 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1795 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1798 switch (NVT.getSimpleVT().SimpleTy) {
1799 default: llvm_unreachable("Unsupported VT!");
1800 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1801 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1802 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1803 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1807 unsigned LoReg, HiReg;
1808 unsigned ClrOpcode, SExtOpcode;
1809 switch (NVT.getSimpleVT().SimpleTy) {
1810 default: llvm_unreachable("Unsupported VT!");
1812 LoReg = X86::AL; HiReg = X86::AH;
1814 SExtOpcode = X86::CBW;
1817 LoReg = X86::AX; HiReg = X86::DX;
1818 ClrOpcode = X86::MOV16r0;
1819 SExtOpcode = X86::CWD;
1822 LoReg = X86::EAX; HiReg = X86::EDX;
1823 ClrOpcode = X86::MOV32r0;
1824 SExtOpcode = X86::CDQ;
1827 LoReg = X86::RAX; HiReg = X86::RDX;
1828 ClrOpcode = ~0U; // NOT USED.
1829 SExtOpcode = X86::CQO;
1833 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1834 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1835 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
1838 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
1839 // Special case for div8, just use a move with zero extension to AX to
1840 // clear the upper 8 bits (AH).
1841 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
1842 if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
1843 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
1845 SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
1847 array_lengthof(Ops)), 0);
1848 Chain = Move.getValue(1);
1849 ReplaceUses(N0.getValue(1), Chain);
1852 SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
1853 Chain = CurDAG->getEntryNode();
1855 Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
1856 InFlag = Chain.getValue(1);
1859 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
1860 LoReg, N0, SDValue()).getValue(1);
1861 if (isSigned && !signBitIsZero) {
1862 // Sign extend the low part into the high part.
1864 SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
1866 // Zero out the high part, effectively zero extending the input.
1869 if (NVT.getSimpleVT() == MVT::i64) {
1870 ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, MVT::i32),
1872 // We just did a 32-bit clear, insert it into a 64-bit register to
1873 // clear the whole 64-bit reg.
1875 SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
1878 CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
1880 SDValue(CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl,
1881 MVT::i64, Undef, ClrNode, SubRegNo),
1884 ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 0);
1887 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg,
1888 ClrNode, InFlag).getValue(1);
1893 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1896 CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1897 array_lengthof(Ops));
1898 InFlag = SDValue(CNode, 1);
1899 // Update the chain.
1900 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1903 SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1906 // Copy the division (low) result, if it is needed.
1907 if (!N.getValue(0).use_empty()) {
1908 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1909 LoReg, NVT, InFlag);
1910 InFlag = Result.getValue(2);
1911 ReplaceUses(N.getValue(0), Result);
1914 errs() << std::string(Indent-2, ' ') << "=> ";
1915 Result.getNode()->dump(CurDAG);
1920 // Copy the remainder (high) result, if it is needed.
1921 if (!N.getValue(1).use_empty()) {
1923 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1924 // Prevent use of AH in a REX instruction by referencing AX instead.
1925 // Shift it down 8 bits.
1926 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1927 X86::AX, MVT::i16, InFlag);
1928 InFlag = Result.getValue(2);
1929 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
1931 CurDAG->getTargetConstant(8, MVT::i8)),
1933 // Then truncate it down to i8.
1934 Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
1937 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1938 HiReg, NVT, InFlag);
1939 InFlag = Result.getValue(2);
1941 ReplaceUses(N.getValue(1), Result);
1944 errs() << std::string(Indent-2, ' ') << "=> ";
1945 Result.getNode()->dump(CurDAG);
1959 SDValue N0 = Node->getOperand(0);
1960 SDValue N1 = Node->getOperand(1);
1962 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
1963 // use a smaller encoding.
1964 if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
1965 N0.getValueType() != MVT::i8 &&
1966 X86::isZeroNode(N1)) {
1967 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
1970 // For example, convert "testl %eax, $8" to "testb %al, $8"
1971 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0) {
1972 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
1973 SDValue Reg = N0.getNode()->getOperand(0);
1975 // On x86-32, only the ABCD registers have 8-bit subregisters.
1976 if (!Subtarget->is64Bit()) {
1977 TargetRegisterClass *TRC = 0;
1978 switch (N0.getValueType().getSimpleVT().SimpleTy) {
1979 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
1980 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
1981 default: llvm_unreachable("Unsupported TEST operand type!");
1983 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
1984 Reg = SDValue(CurDAG->getTargetNode(X86::COPY_TO_REGCLASS, dl,
1985 Reg.getValueType(), Reg, RC), 0);
1988 // Extract the l-register.
1989 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
1993 return CurDAG->getTargetNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
1996 // For example, "testl %eax, $2048" to "testb %ah, $8".
1997 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0) {
1998 // Shift the immediate right by 8 bits.
1999 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2001 SDValue Reg = N0.getNode()->getOperand(0);
2003 // Put the value in an ABCD register.
2004 TargetRegisterClass *TRC = 0;
2005 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2006 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2007 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2008 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2009 default: llvm_unreachable("Unsupported TEST operand type!");
2011 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2012 Reg = SDValue(CurDAG->getTargetNode(X86::COPY_TO_REGCLASS, dl,
2013 Reg.getValueType(), Reg, RC), 0);
2015 // Extract the h-register.
2016 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT_HI, dl,
2019 // Emit a testb. No special NOREX tricks are needed since there's
2020 // only one GPR operand!
2021 return CurDAG->getTargetNode(X86::TEST8ri, dl, MVT::i32,
2022 Subreg, ShiftedImm);
2025 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2026 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2027 N0.getValueType() != MVT::i16) {
2028 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2029 SDValue Reg = N0.getNode()->getOperand(0);
2031 // Extract the 16-bit subregister.
2032 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_16BIT, dl,
2036 return CurDAG->getTargetNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
2039 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2040 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2041 N0.getValueType() == MVT::i64) {
2042 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2043 SDValue Reg = N0.getNode()->getOperand(0);
2045 // Extract the 32-bit subregister.
2046 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_32BIT, dl,
2050 return CurDAG->getTargetNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
2056 case ISD::DECLARE: {
2057 // Handle DECLARE nodes here because the second operand may have been
2058 // wrapped in X86ISD::Wrapper.
2059 SDValue Chain = Node->getOperand(0);
2060 SDValue N1 = Node->getOperand(1);
2061 SDValue N2 = Node->getOperand(2);
2062 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
2064 // FIXME: We need to handle this for VLAs.
2066 ReplaceUses(N.getValue(0), Chain);
2070 if (N2.getOpcode() == ISD::ADD &&
2071 N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg)
2072 N2 = N2.getOperand(1);
2074 // If N2 is not Wrapper(decriptor) then the llvm.declare is mangled
2075 // somehow, just ignore it.
2076 if (N2.getOpcode() != X86ISD::Wrapper &&
2077 N2.getOpcode() != X86ISD::WrapperRIP) {
2078 ReplaceUses(N.getValue(0), Chain);
2081 GlobalAddressSDNode *GVNode =
2082 dyn_cast<GlobalAddressSDNode>(N2.getOperand(0));
2084 ReplaceUses(N.getValue(0), Chain);
2087 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
2088 TLI.getPointerTy());
2089 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(),
2090 TLI.getPointerTy());
2091 SDValue Ops[] = { Tmp1, Tmp2, Chain };
2092 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
2094 array_lengthof(Ops));
2098 SDNode *ResNode = SelectCode(N);
2102 errs() << std::string(Indent-2, ' ') << "=> ";
2103 if (ResNode == NULL || ResNode == N.getNode())
2104 N.getNode()->dump(CurDAG);
2106 ResNode->dump(CurDAG);
2115 bool X86DAGToDAGISel::
2116 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2117 std::vector<SDValue> &OutOps) {
2118 SDValue Op0, Op1, Op2, Op3, Op4;
2119 switch (ConstraintCode) {
2120 case 'o': // offsetable ??
2121 case 'v': // not offsetable ??
2122 default: return true;
2124 if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
2129 OutOps.push_back(Op0);
2130 OutOps.push_back(Op1);
2131 OutOps.push_back(Op2);
2132 OutOps.push_back(Op3);
2133 OutOps.push_back(Op4);
2137 /// createX86ISelDag - This pass converts a legalized DAG into a
2138 /// X86-specific DAG, ready for instruction scheduling.
2140 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2141 llvm::CodeGenOpt::Level OptLevel) {
2142 return new X86DAGToDAGISel(TM, OptLevel);