1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "X86TargetMachine.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/CFG.h"
27 #include "llvm/Type.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/ADT/SmallPtrSet.h"
42 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 static cl::opt<bool> AvoidDupAddrCompute("x86-avoid-dup-address", cl::Hidden);
48 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
50 //===----------------------------------------------------------------------===//
51 // Pattern Matcher Implementation
52 //===----------------------------------------------------------------------===//
55 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
56 /// SDValue's instead of register numbers for the leaves of the matched
58 struct X86ISelAddressMode {
64 struct { // This is really a union, discriminated by BaseType!
77 unsigned Align; // CP alignment.
78 unsigned char SymbolFlags; // X86II::MO_*
81 : BaseType(RegBase), Scale(1), IndexReg(), Disp(0),
82 Segment(), GV(0), CP(0), ES(0), JT(-1), Align(0),
83 SymbolFlags(X86II::MO_NO_FLAG) {
86 bool hasSymbolicDisplacement() const {
87 return GV != 0 || CP != 0 || ES != 0 || JT != -1;
90 bool hasBaseOrIndexReg() const {
91 return IndexReg.getNode() != 0 || Base.Reg.getNode() != 0;
94 /// isRIPRelative - Return true if this addressing mode is already RIP
96 bool isRIPRelative() const {
97 if (BaseType != RegBase) return false;
98 if (RegisterSDNode *RegNode =
99 dyn_cast_or_null<RegisterSDNode>(Base.Reg.getNode()))
100 return RegNode->getReg() == X86::RIP;
104 void setBaseReg(SDValue Reg) {
110 errs() << "X86ISelAddressMode " << this << '\n';
111 errs() << "Base.Reg ";
112 if (Base.Reg.getNode() != 0)
113 Base.Reg.getNode()->dump();
116 errs() << " Base.FrameIndex " << Base.FrameIndex << '\n'
117 << " Scale" << Scale << '\n'
119 if (IndexReg.getNode() != 0)
120 IndexReg.getNode()->dump();
123 errs() << " Disp " << Disp << '\n'
140 errs() << " JT" << JT << " Align" << Align << '\n';
146 //===--------------------------------------------------------------------===//
147 /// ISel - X86 specific code to select X86 machine instructions for
148 /// SelectionDAG operations.
150 class X86DAGToDAGISel : public SelectionDAGISel {
151 /// X86Lowering - This object fully describes how to lower LLVM code to an
152 /// X86-specific SelectionDAG.
153 X86TargetLowering &X86Lowering;
155 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
156 /// make the right decision when generating code for different targets.
157 const X86Subtarget *Subtarget;
159 /// OptForSize - If true, selector should try to optimize for code size
160 /// instead of performance.
164 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
165 : SelectionDAGISel(tm, OptLevel),
166 X86Lowering(*tm.getTargetLowering()),
167 Subtarget(&tm.getSubtarget<X86Subtarget>()),
170 virtual const char *getPassName() const {
171 return "X86 DAG->DAG Instruction Selection";
174 /// InstructionSelect - This callback is invoked by
175 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
176 virtual void InstructionSelect();
178 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
181 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
183 // Include the pieces autogenerated from the target description.
184 #include "X86GenDAGISel.inc"
187 SDNode *Select(SDValue N);
188 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
189 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
191 bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM);
192 bool MatchLoad(SDValue N, X86ISelAddressMode &AM);
193 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
194 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
195 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
197 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
198 bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
199 SDValue &Scale, SDValue &Index, SDValue &Disp,
201 bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
202 SDValue &Scale, SDValue &Index, SDValue &Disp);
203 bool SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
204 SDValue &Scale, SDValue &Index, SDValue &Disp);
205 bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
206 SDValue N, SDValue &Base, SDValue &Scale,
207 SDValue &Index, SDValue &Disp,
209 SDValue &InChain, SDValue &OutChain);
210 bool TryFoldLoad(SDValue P, SDValue N,
211 SDValue &Base, SDValue &Scale,
212 SDValue &Index, SDValue &Disp,
214 void PreprocessForRMW();
215 void PreprocessForFPConvert();
217 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
218 /// inline asm expressions.
219 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
221 std::vector<SDValue> &OutOps);
223 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
225 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
226 SDValue &Scale, SDValue &Index,
227 SDValue &Disp, SDValue &Segment) {
228 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
229 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
231 Scale = getI8Imm(AM.Scale);
233 // These are 32-bit even in 64-bit mode since RIP relative offset
236 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp,
239 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
240 AM.Align, AM.Disp, AM.SymbolFlags);
242 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
243 else if (AM.JT != -1)
244 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
246 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
248 if (AM.Segment.getNode())
249 Segment = AM.Segment;
251 Segment = CurDAG->getRegister(0, MVT::i32);
254 /// getI8Imm - Return a target constant with the specified value, of type
256 inline SDValue getI8Imm(unsigned Imm) {
257 return CurDAG->getTargetConstant(Imm, MVT::i8);
260 /// getI16Imm - Return a target constant with the specified value, of type
262 inline SDValue getI16Imm(unsigned Imm) {
263 return CurDAG->getTargetConstant(Imm, MVT::i16);
266 /// getI32Imm - Return a target constant with the specified value, of type
268 inline SDValue getI32Imm(unsigned Imm) {
269 return CurDAG->getTargetConstant(Imm, MVT::i32);
272 /// getGlobalBaseReg - Return an SDNode that returns the value of
273 /// the global base register. Output instructions required to
274 /// initialize the global base register, if necessary.
276 SDNode *getGlobalBaseReg();
278 /// getTargetMachine - Return a reference to the TargetMachine, casted
279 /// to the target-specific type.
280 const X86TargetMachine &getTargetMachine() {
281 return static_cast<const X86TargetMachine &>(TM);
284 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
285 /// to the target-specific type.
286 const X86InstrInfo *getInstrInfo() {
287 return getTargetMachine().getInstrInfo();
297 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
298 SDNode *Root) const {
299 if (OptLevel == CodeGenOpt::None) return false;
302 switch (U->getOpcode()) {
310 SDValue Op1 = U->getOperand(1);
312 // If the other operand is a 8-bit immediate we should fold the immediate
313 // instead. This reduces code size.
315 // movl 4(%esp), %eax
319 // addl 4(%esp), %eax
320 // The former is 2 bytes shorter. In case where the increment is 1, then
321 // the saving can be 4 bytes (by using incl %eax).
322 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
323 if (Imm->getAPIntValue().isSignedIntN(8))
326 // If the other operand is a TLS address, we should fold it instead.
329 // leal i@NTPOFF(%eax), %eax
331 // movl $i@NTPOFF, %eax
333 // if the block also has an access to a second TLS address this will save
335 // FIXME: This is probably also true for non TLS addresses.
336 if (Op1.getOpcode() == X86ISD::Wrapper) {
337 SDValue Val = Op1.getOperand(0);
338 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
344 // Proceed to 'generic' cycle finder code
345 return SelectionDAGISel::IsLegalAndProfitableToFold(N, U, Root);
348 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
349 /// and move load below the TokenFactor. Replace store's chain operand with
350 /// load's chain result.
351 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
352 SDValue Store, SDValue TF) {
353 SmallVector<SDValue, 4> Ops;
354 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
355 if (Load.getNode() == TF.getOperand(i).getNode())
356 Ops.push_back(Load.getOperand(0));
358 Ops.push_back(TF.getOperand(i));
359 SDValue NewTF = CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
360 SDValue NewLoad = CurDAG->UpdateNodeOperands(Load, NewTF,
363 CurDAG->UpdateNodeOperands(Store, NewLoad.getValue(1), Store.getOperand(1),
364 Store.getOperand(2), Store.getOperand(3));
367 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG. The
368 /// chain produced by the load must only be used by the store's chain operand,
369 /// otherwise this may produce a cycle in the DAG.
371 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
373 if (N.getOpcode() == ISD::BIT_CONVERT)
376 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
377 if (!LD || LD->isVolatile())
379 if (LD->getAddressingMode() != ISD::UNINDEXED)
382 ISD::LoadExtType ExtType = LD->getExtensionType();
383 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
387 LD->hasNUsesOfValue(1, 1) &&
388 N.getOperand(1) == Address &&
389 LD->isOperandOf(Chain.getNode())) {
396 /// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
397 /// operand and move load below the call's chain operand.
398 static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
399 SDValue Call, SDValue CallSeqStart) {
400 SmallVector<SDValue, 8> Ops;
401 SDValue Chain = CallSeqStart.getOperand(0);
402 if (Chain.getNode() == Load.getNode())
403 Ops.push_back(Load.getOperand(0));
405 assert(Chain.getOpcode() == ISD::TokenFactor &&
406 "Unexpected CallSeqStart chain operand");
407 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
408 if (Chain.getOperand(i).getNode() == Load.getNode())
409 Ops.push_back(Load.getOperand(0));
411 Ops.push_back(Chain.getOperand(i));
413 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
414 MVT::Other, &Ops[0], Ops.size());
416 Ops.push_back(NewChain);
418 for (unsigned i = 1, e = CallSeqStart.getNumOperands(); i != e; ++i)
419 Ops.push_back(CallSeqStart.getOperand(i));
420 CurDAG->UpdateNodeOperands(CallSeqStart, &Ops[0], Ops.size());
421 CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
422 Load.getOperand(1), Load.getOperand(2));
424 Ops.push_back(SDValue(Load.getNode(), 1));
425 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
426 Ops.push_back(Call.getOperand(i));
427 CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
430 /// isCalleeLoad - Return true if call address is a load and it can be
431 /// moved below CALLSEQ_START and the chains leading up to the call.
432 /// Return the CALLSEQ_START by reference as a second output.
433 static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
434 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
436 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
439 LD->getAddressingMode() != ISD::UNINDEXED ||
440 LD->getExtensionType() != ISD::NON_EXTLOAD)
443 // Now let's find the callseq_start.
444 while (Chain.getOpcode() != ISD::CALLSEQ_START) {
445 if (!Chain.hasOneUse())
447 Chain = Chain.getOperand(0);
450 if (Chain.getOperand(0).getNode() == Callee.getNode())
452 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
453 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
454 Callee.getValue(1).hasOneUse())
460 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
461 /// This is only run if not in -O0 mode.
462 /// This allows the instruction selector to pick more read-modify-write
463 /// instructions. This is a common case:
473 /// [TokenFactor] [Op]
480 /// The fact the store's chain operand != load's chain will prevent the
481 /// (store (op (load))) instruction from being selected. We can transform it to:
500 void X86DAGToDAGISel::PreprocessForRMW() {
501 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
502 E = CurDAG->allnodes_end(); I != E; ++I) {
503 if (I->getOpcode() == X86ISD::CALL) {
504 /// Also try moving call address load from outside callseq_start to just
505 /// before the call to allow it to be folded.
523 SDValue Chain = I->getOperand(0);
524 SDValue Load = I->getOperand(1);
525 if (!isCalleeLoad(Load, Chain))
527 MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
532 if (!ISD::isNON_TRUNCStore(I))
534 SDValue Chain = I->getOperand(0);
536 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
539 SDValue N1 = I->getOperand(1);
540 SDValue N2 = I->getOperand(2);
541 if ((N1.getValueType().isFloatingPoint() &&
542 !N1.getValueType().isVector()) ||
548 unsigned Opcode = N1.getNode()->getOpcode();
557 case ISD::VECTOR_SHUFFLE: {
558 SDValue N10 = N1.getOperand(0);
559 SDValue N11 = N1.getOperand(1);
560 RModW = isRMWLoad(N10, Chain, N2, Load);
562 RModW = isRMWLoad(N11, Chain, N2, Load);
575 SDValue N10 = N1.getOperand(0);
576 RModW = isRMWLoad(N10, Chain, N2, Load);
582 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
589 /// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend
590 /// nodes that target the FP stack to be store and load to the stack. This is a
591 /// gross hack. We would like to simply mark these as being illegal, but when
592 /// we do that, legalize produces these when it expands calls, then expands
593 /// these in the same legalize pass. We would like dag combine to be able to
594 /// hack on these between the call expansion and the node legalization. As such
595 /// this pass basically does "really late" legalization of these inline with the
597 void X86DAGToDAGISel::PreprocessForFPConvert() {
598 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
599 E = CurDAG->allnodes_end(); I != E; ) {
600 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
601 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
604 // If the source and destination are SSE registers, then this is a legal
605 // conversion that should not be lowered.
606 EVT SrcVT = N->getOperand(0).getValueType();
607 EVT DstVT = N->getValueType(0);
608 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
609 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
610 if (SrcIsSSE && DstIsSSE)
613 if (!SrcIsSSE && !DstIsSSE) {
614 // If this is an FPStack extension, it is a noop.
615 if (N->getOpcode() == ISD::FP_EXTEND)
617 // If this is a value-preserving FPStack truncation, it is a noop.
618 if (N->getConstantOperandVal(1))
622 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
623 // FPStack has extload and truncstore. SSE can fold direct loads into other
624 // operations. Based on this, decide what we want to do.
626 if (N->getOpcode() == ISD::FP_ROUND)
627 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
629 MemVT = SrcIsSSE ? SrcVT : DstVT;
631 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
632 DebugLoc dl = N->getDebugLoc();
634 // FIXME: optimize the case where the src/dest is a load or store?
635 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
637 MemTmp, NULL, 0, MemVT);
638 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
641 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
642 // extload we created. This will cause general havok on the dag because
643 // anything below the conversion could be folded into other existing nodes.
644 // To avoid invalidating 'I', back it up to the convert node.
646 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
648 // Now that we did that, the node is dead. Increment the iterator to the
649 // next node to process, then delete N.
651 CurDAG->DeleteNode(N);
655 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
656 /// when it has created a SelectionDAG for us to codegen.
657 void X86DAGToDAGISel::InstructionSelect() {
658 const Function *F = MF->getFunction();
659 OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
662 if (OptLevel != CodeGenOpt::None)
665 // FIXME: This should only happen when not compiled with -O0.
666 PreprocessForFPConvert();
668 // Codegen the basic block.
670 DEBUG(errs() << "===== Instruction selection begins:\n");
675 DEBUG(errs() << "===== Instruction selection ends:\n");
678 CurDAG->RemoveDeadNodes();
681 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
682 /// the main function.
683 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
684 MachineFrameInfo *MFI) {
685 const TargetInstrInfo *TII = TM.getInstrInfo();
686 if (Subtarget->isTargetCygMing())
687 BuildMI(BB, DebugLoc::getUnknownLoc(),
688 TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
691 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
692 // If this is main, emit special code for main.
693 MachineBasicBlock *BB = MF.begin();
694 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
695 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
699 bool X86DAGToDAGISel::MatchSegmentBaseAddress(SDValue N,
700 X86ISelAddressMode &AM) {
701 assert(N.getOpcode() == X86ISD::SegmentBaseAddress);
702 SDValue Segment = N.getOperand(0);
704 if (AM.Segment.getNode() == 0) {
705 AM.Segment = Segment;
712 bool X86DAGToDAGISel::MatchLoad(SDValue N, X86ISelAddressMode &AM) {
713 // This optimization is valid because the GNU TLS model defines that
714 // gs:0 (or fs:0 on X86-64) contains its own address.
715 // For more information see http://people.redhat.com/drepper/tls.pdf
717 SDValue Address = N.getOperand(1);
718 if (Address.getOpcode() == X86ISD::SegmentBaseAddress &&
719 !MatchSegmentBaseAddress (Address, AM))
725 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
726 /// into an addressing mode. These wrap things that will resolve down into a
727 /// symbol reference. If no match is possible, this returns true, otherwise it
729 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
730 // If the addressing mode already has a symbol as the displacement, we can
731 // never match another symbol.
732 if (AM.hasSymbolicDisplacement())
735 SDValue N0 = N.getOperand(0);
736 CodeModel::Model M = TM.getCodeModel();
738 // Handle X86-64 rip-relative addresses. We check this before checking direct
739 // folding because RIP is preferable to non-RIP accesses.
740 if (Subtarget->is64Bit() &&
741 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
742 // they cannot be folded into immediate fields.
743 // FIXME: This can be improved for kernel and other models?
744 (M == CodeModel::Small || M == CodeModel::Kernel) &&
745 // Base and index reg must be 0 in order to use %rip as base and lowering
747 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
748 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
749 int64_t Offset = AM.Disp + G->getOffset();
750 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
751 AM.GV = G->getGlobal();
753 AM.SymbolFlags = G->getTargetFlags();
754 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
755 int64_t Offset = AM.Disp + CP->getOffset();
756 if (!X86::isOffsetSuitableForCodeModel(Offset, M)) return true;
757 AM.CP = CP->getConstVal();
758 AM.Align = CP->getAlignment();
760 AM.SymbolFlags = CP->getTargetFlags();
761 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
762 AM.ES = S->getSymbol();
763 AM.SymbolFlags = S->getTargetFlags();
765 JumpTableSDNode *J = cast<JumpTableSDNode>(N0);
766 AM.JT = J->getIndex();
767 AM.SymbolFlags = J->getTargetFlags();
770 if (N.getOpcode() == X86ISD::WrapperRIP)
771 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
775 // Handle the case when globals fit in our immediate field: This is true for
776 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit
777 // mode, this results in a non-RIP-relative computation.
778 if (!Subtarget->is64Bit() ||
779 ((M == CodeModel::Small || M == CodeModel::Kernel) &&
780 TM.getRelocationModel() == Reloc::Static)) {
781 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
782 AM.GV = G->getGlobal();
783 AM.Disp += G->getOffset();
784 AM.SymbolFlags = G->getTargetFlags();
785 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
786 AM.CP = CP->getConstVal();
787 AM.Align = CP->getAlignment();
788 AM.Disp += CP->getOffset();
789 AM.SymbolFlags = CP->getTargetFlags();
790 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
791 AM.ES = S->getSymbol();
792 AM.SymbolFlags = S->getTargetFlags();
794 JumpTableSDNode *J = cast<JumpTableSDNode>(N0);
795 AM.JT = J->getIndex();
796 AM.SymbolFlags = J->getTargetFlags();
804 /// MatchAddress - Add the specified node to the specified addressing mode,
805 /// returning true if it cannot be done. This just pattern matches for the
807 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
808 if (MatchAddressRecursively(N, AM, 0))
811 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
812 // a smaller encoding and avoids a scaled-index.
814 AM.BaseType == X86ISelAddressMode::RegBase &&
815 AM.Base.Reg.getNode() == 0) {
816 AM.Base.Reg = AM.IndexReg;
820 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
821 // because it has a smaller encoding.
822 // TODO: Which other code models can use this?
823 if (TM.getCodeModel() == CodeModel::Small &&
824 Subtarget->is64Bit() &&
826 AM.BaseType == X86ISelAddressMode::RegBase &&
827 AM.Base.Reg.getNode() == 0 &&
828 AM.IndexReg.getNode() == 0 &&
829 AM.SymbolFlags == X86II::MO_NO_FLAG &&
830 AM.hasSymbolicDisplacement())
831 AM.Base.Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
836 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
838 bool is64Bit = Subtarget->is64Bit();
839 DebugLoc dl = N.getDebugLoc();
841 errs() << "MatchAddress: ";
846 return MatchAddressBase(N, AM);
848 CodeModel::Model M = TM.getCodeModel();
850 // If this is already a %rip relative address, we can only merge immediates
851 // into it. Instead of handling this in every case, we handle it here.
852 // RIP relative addressing: %rip + 32-bit displacement!
853 if (AM.isRIPRelative()) {
854 // FIXME: JumpTable and ExternalSymbol address currently don't like
855 // displacements. It isn't very important, but this should be fixed for
857 if (!AM.ES && AM.JT != -1) return true;
859 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) {
860 int64_t Val = AM.Disp + Cst->getSExtValue();
861 if (X86::isOffsetSuitableForCodeModel(Val, M,
862 AM.hasSymbolicDisplacement())) {
870 switch (N.getOpcode()) {
872 case ISD::Constant: {
873 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
875 X86::isOffsetSuitableForCodeModel(AM.Disp + Val, M,
876 AM.hasSymbolicDisplacement())) {
883 case X86ISD::SegmentBaseAddress:
884 if (!MatchSegmentBaseAddress(N, AM))
888 case X86ISD::Wrapper:
889 case X86ISD::WrapperRIP:
890 if (!MatchWrapper(N, AM))
895 if (!MatchLoad(N, AM))
899 case ISD::FrameIndex:
900 if (AM.BaseType == X86ISelAddressMode::RegBase
901 && AM.Base.Reg.getNode() == 0) {
902 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
903 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
909 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
913 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
914 unsigned Val = CN->getZExtValue();
915 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
916 // that the base operand remains free for further matching. If
917 // the base doesn't end up getting used, a post-processing step
918 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
919 if (Val == 1 || Val == 2 || Val == 3) {
921 SDValue ShVal = N.getNode()->getOperand(0);
923 // Okay, we know that we have a scale by now. However, if the scaled
924 // value is an add of something and a constant, we can fold the
925 // constant into the disp field here.
926 if (ShVal.getNode()->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
927 isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
928 AM.IndexReg = ShVal.getNode()->getOperand(0);
929 ConstantSDNode *AddVal =
930 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
931 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
933 X86::isOffsetSuitableForCodeModel(Disp, M,
934 AM.hasSymbolicDisplacement()))
948 // A mul_lohi where we need the low part can be folded as a plain multiply.
949 if (N.getResNo() != 0) break;
952 case X86ISD::MUL_IMM:
953 // X*[3,5,9] -> X+X*[2,4,8]
954 if (AM.BaseType == X86ISelAddressMode::RegBase &&
955 AM.Base.Reg.getNode() == 0 &&
956 AM.IndexReg.getNode() == 0) {
958 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
959 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
960 CN->getZExtValue() == 9) {
961 AM.Scale = unsigned(CN->getZExtValue())-1;
963 SDValue MulVal = N.getNode()->getOperand(0);
966 // Okay, we know that we have a scale by now. However, if the scaled
967 // value is an add of something and a constant, we can fold the
968 // constant into the disp field here.
969 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
970 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
971 Reg = MulVal.getNode()->getOperand(0);
972 ConstantSDNode *AddVal =
973 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
974 uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
977 X86::isOffsetSuitableForCodeModel(Disp, M,
978 AM.hasSymbolicDisplacement()))
981 Reg = N.getNode()->getOperand(0);
983 Reg = N.getNode()->getOperand(0);
986 AM.IndexReg = AM.Base.Reg = Reg;
993 // Given A-B, if A can be completely folded into the address and
994 // the index field with the index field unused, use -B as the index.
995 // This is a win if a has multiple parts that can be folded into
996 // the address. Also, this saves a mov if the base register has
997 // other uses, since it avoids a two-address sub instruction, however
998 // it costs an additional mov if the index register has other uses.
1000 // Test if the LHS of the sub can be folded.
1001 X86ISelAddressMode Backup = AM;
1002 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1006 // Test if the index field is free for use.
1007 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1012 SDValue RHS = N.getNode()->getOperand(1);
1013 // If the RHS involves a register with multiple uses, this
1014 // transformation incurs an extra mov, due to the neg instruction
1015 // clobbering its operand.
1016 if (!RHS.getNode()->hasOneUse() ||
1017 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1018 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1019 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1020 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1021 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1023 // If the base is a register with multiple uses, this
1024 // transformation may save a mov.
1025 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1026 AM.Base.Reg.getNode() &&
1027 !AM.Base.Reg.getNode()->hasOneUse()) ||
1028 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1030 // If the folded LHS was interesting, this transformation saves
1031 // address arithmetic.
1032 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1033 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1034 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1036 // If it doesn't look like it may be an overall win, don't do it.
1042 // Ok, the transformation is legal and appears profitable. Go for it.
1043 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1044 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1048 // Insert the new nodes into the topological ordering.
1049 if (Zero.getNode()->getNodeId() == -1 ||
1050 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1051 CurDAG->RepositionNode(N.getNode(), Zero.getNode());
1052 Zero.getNode()->setNodeId(N.getNode()->getNodeId());
1054 if (Neg.getNode()->getNodeId() == -1 ||
1055 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1056 CurDAG->RepositionNode(N.getNode(), Neg.getNode());
1057 Neg.getNode()->setNodeId(N.getNode()->getNodeId());
1063 X86ISelAddressMode Backup = AM;
1064 if (!MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1) &&
1065 !MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1))
1068 if (!MatchAddressRecursively(N.getNode()->getOperand(1), AM, Depth+1) &&
1069 !MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1))
1073 // If we couldn't fold both operands into the address at the same time,
1074 // see if we can just put each operand into a register and fold at least
1076 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1077 !AM.Base.Reg.getNode() &&
1078 !AM.IndexReg.getNode()) {
1079 AM.Base.Reg = N.getNode()->getOperand(0);
1080 AM.IndexReg = N.getNode()->getOperand(1);
1088 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1089 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1090 X86ISelAddressMode Backup = AM;
1091 uint64_t Offset = CN->getSExtValue();
1092 // Start with the LHS as an addr mode.
1093 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1094 // Address could not have picked a GV address for the displacement.
1096 // On x86-64, the resultant disp must fit in 32-bits.
1098 X86::isOffsetSuitableForCodeModel(AM.Disp + Offset, M,
1099 AM.hasSymbolicDisplacement())) &&
1100 // Check to see if the LHS & C is zero.
1101 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
1110 // Perform some heroic transforms on an and of a constant-count shift
1111 // with a constant to enable use of the scaled offset field.
1113 SDValue Shift = N.getOperand(0);
1114 if (Shift.getNumOperands() != 2) break;
1116 // Scale must not be used already.
1117 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1119 SDValue X = Shift.getOperand(0);
1120 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
1121 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
1122 if (!C1 || !C2) break;
1124 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This
1125 // allows us to convert the shift and and into an h-register extract and
1127 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) {
1128 unsigned ScaleLog = 8 - C1->getZExtValue();
1129 if (ScaleLog > 0 && ScaleLog < 4 &&
1130 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) {
1131 SDValue Eight = CurDAG->getConstant(8, MVT::i8);
1132 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType());
1133 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1135 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(),
1137 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8);
1138 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1141 // Insert the new nodes into the topological ordering.
1142 if (Eight.getNode()->getNodeId() == -1 ||
1143 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1144 CurDAG->RepositionNode(X.getNode(), Eight.getNode());
1145 Eight.getNode()->setNodeId(X.getNode()->getNodeId());
1147 if (Mask.getNode()->getNodeId() == -1 ||
1148 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1149 CurDAG->RepositionNode(X.getNode(), Mask.getNode());
1150 Mask.getNode()->setNodeId(X.getNode()->getNodeId());
1152 if (Srl.getNode()->getNodeId() == -1 ||
1153 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1154 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode());
1155 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId());
1157 if (And.getNode()->getNodeId() == -1 ||
1158 And.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1159 CurDAG->RepositionNode(N.getNode(), And.getNode());
1160 And.getNode()->setNodeId(N.getNode()->getNodeId());
1162 if (ShlCount.getNode()->getNodeId() == -1 ||
1163 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1164 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode());
1165 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId());
1167 if (Shl.getNode()->getNodeId() == -1 ||
1168 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1169 CurDAG->RepositionNode(N.getNode(), Shl.getNode());
1170 Shl.getNode()->setNodeId(N.getNode()->getNodeId());
1172 CurDAG->ReplaceAllUsesWith(N, Shl);
1174 AM.Scale = (1 << ScaleLog);
1179 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
1180 // allows us to fold the shift into this addressing mode.
1181 if (Shift.getOpcode() != ISD::SHL) break;
1183 // Not likely to be profitable if either the AND or SHIFT node has more
1184 // than one use (unless all uses are for address computation). Besides,
1185 // isel mechanism requires their node ids to be reused.
1186 if (!N.hasOneUse() || !Shift.hasOneUse())
1189 // Verify that the shift amount is something we can fold.
1190 unsigned ShiftCst = C1->getZExtValue();
1191 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
1194 // Get the new AND mask, this folds to a constant.
1195 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
1196 SDValue(C2, 0), SDValue(C1, 0));
1197 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
1199 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
1200 NewAND, SDValue(C1, 0));
1202 // Insert the new nodes into the topological ordering.
1203 if (C1->getNodeId() > X.getNode()->getNodeId()) {
1204 CurDAG->RepositionNode(X.getNode(), C1);
1205 C1->setNodeId(X.getNode()->getNodeId());
1207 if (NewANDMask.getNode()->getNodeId() == -1 ||
1208 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
1209 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
1210 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
1212 if (NewAND.getNode()->getNodeId() == -1 ||
1213 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
1214 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
1215 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
1217 if (NewSHIFT.getNode()->getNodeId() == -1 ||
1218 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
1219 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
1220 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
1223 CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
1225 AM.Scale = 1 << ShiftCst;
1226 AM.IndexReg = NewAND;
1231 return MatchAddressBase(N, AM);
1234 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1235 /// specified addressing mode without any further recursion.
1236 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1237 // Is the base register already occupied?
1238 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
1239 // If so, check to see if the scale index register is set.
1240 if (AM.IndexReg.getNode() == 0) {
1246 // Otherwise, we cannot select it.
1250 // Default, generate it as a register.
1251 AM.BaseType = X86ISelAddressMode::RegBase;
1256 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1257 /// It returns the operands which make up the maximal addressing mode it can
1258 /// match by reference.
1259 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
1260 SDValue &Scale, SDValue &Index,
1261 SDValue &Disp, SDValue &Segment) {
1262 X86ISelAddressMode AM;
1264 if (AvoidDupAddrCompute && !N.hasOneUse()) {
1265 unsigned Opcode = N.getOpcode();
1266 if (Opcode != ISD::Constant && Opcode != ISD::FrameIndex &&
1267 Opcode != X86ISD::Wrapper && Opcode != X86ISD::WrapperRIP) {
1268 // If we are able to fold N into addressing mode, then we'll allow it even
1269 // if N has multiple uses. In general, addressing computation is used as
1270 // addresses by all of its uses. But watch out for CopyToReg uses, that
1271 // means the address computation is liveout. It will be computed by a LEA
1272 // so we want to avoid computing the address twice.
1273 for (SDNode::use_iterator UI = N.getNode()->use_begin(),
1274 UE = N.getNode()->use_end(); UI != UE; ++UI) {
1275 if (UI->getOpcode() == ISD::CopyToReg) {
1276 MatchAddressBase(N, AM);
1284 if (!Done && MatchAddress(N, AM))
1287 EVT VT = N.getValueType();
1288 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1289 if (!AM.Base.Reg.getNode())
1290 AM.Base.Reg = CurDAG->getRegister(0, VT);
1293 if (!AM.IndexReg.getNode())
1294 AM.IndexReg = CurDAG->getRegister(0, VT);
1296 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1300 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1301 /// match a load whose top elements are either undef or zeros. The load flavor
1302 /// is derived from the type of N, which is either v4f32 or v2f64.
1303 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
1304 SDValue N, SDValue &Base,
1305 SDValue &Scale, SDValue &Index,
1306 SDValue &Disp, SDValue &Segment,
1308 SDValue &OutChain) {
1309 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1310 InChain = N.getOperand(0).getValue(1);
1311 if (ISD::isNON_EXTLoad(InChain.getNode()) &&
1312 InChain.getValue(0).hasOneUse() &&
1314 IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
1315 LoadSDNode *LD = cast<LoadSDNode>(InChain);
1316 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1318 OutChain = LD->getChain();
1323 // Also handle the case where we explicitly require zeros in the top
1324 // elements. This is a vector shuffle from the zero vector.
1325 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1326 // Check to see if the top elements are all zeros (or bitcast of zeros).
1327 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1328 N.getOperand(0).getNode()->hasOneUse() &&
1329 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1330 N.getOperand(0).getOperand(0).hasOneUse()) {
1331 // Okay, this is a zero extending load. Fold it.
1332 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1333 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1335 OutChain = LD->getChain();
1336 InChain = SDValue(LD, 1);
1343 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1344 /// mode it matches can be cost effectively emitted as an LEA instruction.
1345 bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
1346 SDValue &Base, SDValue &Scale,
1347 SDValue &Index, SDValue &Disp) {
1348 X86ISelAddressMode AM;
1350 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1352 SDValue Copy = AM.Segment;
1353 SDValue T = CurDAG->getRegister(0, MVT::i32);
1355 if (MatchAddress(N, AM))
1357 assert (T == AM.Segment);
1360 EVT VT = N.getValueType();
1361 unsigned Complexity = 0;
1362 if (AM.BaseType == X86ISelAddressMode::RegBase)
1363 if (AM.Base.Reg.getNode())
1366 AM.Base.Reg = CurDAG->getRegister(0, VT);
1367 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1370 if (AM.IndexReg.getNode())
1373 AM.IndexReg = CurDAG->getRegister(0, VT);
1375 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1380 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1381 // to a LEA. This is determined with some expermentation but is by no means
1382 // optimal (especially for code size consideration). LEA is nice because of
1383 // its three-address nature. Tweak the cost function again when we can run
1384 // convertToThreeAddress() at register allocation time.
1385 if (AM.hasSymbolicDisplacement()) {
1386 // For X86-64, we should always use lea to materialize RIP relative
1388 if (Subtarget->is64Bit())
1394 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
1397 // If it isn't worth using an LEA, reject it.
1398 if (Complexity <= 2)
1402 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1406 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1407 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base,
1408 SDValue &Scale, SDValue &Index,
1410 assert(Op.getOpcode() == X86ISD::TLSADDR);
1411 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1412 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1414 X86ISelAddressMode AM;
1415 AM.GV = GA->getGlobal();
1416 AM.Disp += GA->getOffset();
1417 AM.Base.Reg = CurDAG->getRegister(0, N.getValueType());
1418 AM.SymbolFlags = GA->getTargetFlags();
1420 if (N.getValueType() == MVT::i32) {
1422 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1424 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1428 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1433 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
1434 SDValue &Base, SDValue &Scale,
1435 SDValue &Index, SDValue &Disp,
1437 if (ISD::isNON_EXTLoad(N.getNode()) &&
1439 IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
1440 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp, Segment);
1444 /// getGlobalBaseReg - Return an SDNode that returns the value of
1445 /// the global base register. Output instructions required to
1446 /// initialize the global base register, if necessary.
1448 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1449 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1450 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1453 static SDNode *FindCallStartFromCall(SDNode *Node) {
1454 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1455 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1456 "Node doesn't have a token chain argument!");
1457 return FindCallStartFromCall(Node->getOperand(0).getNode());
1460 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1461 SDValue Chain = Node->getOperand(0);
1462 SDValue In1 = Node->getOperand(1);
1463 SDValue In2L = Node->getOperand(2);
1464 SDValue In2H = Node->getOperand(3);
1465 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1466 if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1468 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1469 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1470 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1471 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1472 MVT::i32, MVT::i32, MVT::Other, Ops,
1473 array_lengthof(Ops));
1474 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1478 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1479 if (Node->hasAnyUseOfValue(0))
1482 // Optimize common patterns for __sync_add_and_fetch and
1483 // __sync_sub_and_fetch where the result is not used. This allows us
1484 // to use "lock" version of add, sub, inc, dec instructions.
1485 // FIXME: Do not use special instructions but instead add the "lock"
1486 // prefix to the target node somehow. The extra information will then be
1487 // transferred to machine instruction and it denotes the prefix.
1488 SDValue Chain = Node->getOperand(0);
1489 SDValue Ptr = Node->getOperand(1);
1490 SDValue Val = Node->getOperand(2);
1491 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1492 if (!SelectAddr(Ptr, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1495 bool isInc = false, isDec = false, isSub = false, isCN = false;
1496 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1499 int64_t CNVal = CN->getSExtValue();
1502 else if (CNVal == -1)
1504 else if (CNVal >= 0)
1505 Val = CurDAG->getTargetConstant(CNVal, NVT);
1508 Val = CurDAG->getTargetConstant(-CNVal, NVT);
1510 } else if (Val.hasOneUse() &&
1511 Val.getOpcode() == ISD::SUB &&
1512 X86::isZeroNode(Val.getOperand(0))) {
1514 Val = Val.getOperand(1);
1518 switch (NVT.getSimpleVT().SimpleTy) {
1522 Opc = X86::LOCK_INC8m;
1524 Opc = X86::LOCK_DEC8m;
1527 Opc = X86::LOCK_SUB8mi;
1529 Opc = X86::LOCK_SUB8mr;
1532 Opc = X86::LOCK_ADD8mi;
1534 Opc = X86::LOCK_ADD8mr;
1539 Opc = X86::LOCK_INC16m;
1541 Opc = X86::LOCK_DEC16m;
1544 if (Predicate_i16immSExt8(Val.getNode()))
1545 Opc = X86::LOCK_SUB16mi8;
1547 Opc = X86::LOCK_SUB16mi;
1549 Opc = X86::LOCK_SUB16mr;
1552 if (Predicate_i16immSExt8(Val.getNode()))
1553 Opc = X86::LOCK_ADD16mi8;
1555 Opc = X86::LOCK_ADD16mi;
1557 Opc = X86::LOCK_ADD16mr;
1562 Opc = X86::LOCK_INC32m;
1564 Opc = X86::LOCK_DEC32m;
1567 if (Predicate_i32immSExt8(Val.getNode()))
1568 Opc = X86::LOCK_SUB32mi8;
1570 Opc = X86::LOCK_SUB32mi;
1572 Opc = X86::LOCK_SUB32mr;
1575 if (Predicate_i32immSExt8(Val.getNode()))
1576 Opc = X86::LOCK_ADD32mi8;
1578 Opc = X86::LOCK_ADD32mi;
1580 Opc = X86::LOCK_ADD32mr;
1585 Opc = X86::LOCK_INC64m;
1587 Opc = X86::LOCK_DEC64m;
1589 Opc = X86::LOCK_SUB64mr;
1591 if (Predicate_i64immSExt8(Val.getNode()))
1592 Opc = X86::LOCK_SUB64mi8;
1593 else if (Predicate_i64immSExt32(Val.getNode()))
1594 Opc = X86::LOCK_SUB64mi32;
1597 Opc = X86::LOCK_ADD64mr;
1599 if (Predicate_i64immSExt8(Val.getNode()))
1600 Opc = X86::LOCK_ADD64mi8;
1601 else if (Predicate_i64immSExt32(Val.getNode()))
1602 Opc = X86::LOCK_ADD64mi32;
1608 DebugLoc dl = Node->getDebugLoc();
1609 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
1611 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1612 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1613 if (isInc || isDec) {
1614 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1615 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
1616 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1617 SDValue RetVals[] = { Undef, Ret };
1618 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1620 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1621 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1622 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1623 SDValue RetVals[] = { Undef, Ret };
1624 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1628 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1629 /// any uses which require the SF or OF bits to be accurate.
1630 static bool HasNoSignedComparisonUses(SDNode *N) {
1631 // Examine each user of the node.
1632 for (SDNode::use_iterator UI = N->use_begin(),
1633 UE = N->use_end(); UI != UE; ++UI) {
1634 // Only examine CopyToReg uses.
1635 if (UI->getOpcode() != ISD::CopyToReg)
1637 // Only examine CopyToReg uses that copy to EFLAGS.
1638 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1641 // Examine each user of the CopyToReg use.
1642 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1643 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1644 // Only examine the Flag result.
1645 if (FlagUI.getUse().getResNo() != 1) continue;
1646 // Anything unusual: assume conservatively.
1647 if (!FlagUI->isMachineOpcode()) return false;
1648 // Examine the opcode of the user.
1649 switch (FlagUI->getMachineOpcode()) {
1650 // These comparisons don't treat the most significant bit specially.
1651 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1652 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1653 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1654 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1655 case X86::JA: case X86::JAE: case X86::JB: case X86::JBE:
1656 case X86::JE: case X86::JNE: case X86::JP: case X86::JNP:
1657 case X86::CMOVA16rr: case X86::CMOVA16rm:
1658 case X86::CMOVA32rr: case X86::CMOVA32rm:
1659 case X86::CMOVA64rr: case X86::CMOVA64rm:
1660 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1661 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1662 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1663 case X86::CMOVB16rr: case X86::CMOVB16rm:
1664 case X86::CMOVB32rr: case X86::CMOVB32rm:
1665 case X86::CMOVB64rr: case X86::CMOVB64rm:
1666 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1667 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1668 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1669 case X86::CMOVE16rr: case X86::CMOVE16rm:
1670 case X86::CMOVE32rr: case X86::CMOVE32rm:
1671 case X86::CMOVE64rr: case X86::CMOVE64rm:
1672 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1673 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1674 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1675 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1676 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1677 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1678 case X86::CMOVP16rr: case X86::CMOVP16rm:
1679 case X86::CMOVP32rr: case X86::CMOVP32rm:
1680 case X86::CMOVP64rr: case X86::CMOVP64rm:
1682 // Anything else: assume conservatively.
1683 default: return false;
1690 SDNode *X86DAGToDAGISel::Select(SDValue N) {
1691 SDNode *Node = N.getNode();
1692 EVT NVT = Node->getValueType(0);
1694 unsigned Opcode = Node->getOpcode();
1695 DebugLoc dl = Node->getDebugLoc();
1699 errs() << std::string(Indent, ' ') << "Selecting: ";
1706 if (Node->isMachineOpcode()) {
1709 errs() << std::string(Indent-2, ' ') << "== ";
1715 return NULL; // Already selected.
1720 case X86ISD::GlobalBaseReg:
1721 return getGlobalBaseReg();
1723 case X86ISD::ATOMOR64_DAG:
1724 return SelectAtomic64(Node, X86::ATOMOR6432);
1725 case X86ISD::ATOMXOR64_DAG:
1726 return SelectAtomic64(Node, X86::ATOMXOR6432);
1727 case X86ISD::ATOMADD64_DAG:
1728 return SelectAtomic64(Node, X86::ATOMADD6432);
1729 case X86ISD::ATOMSUB64_DAG:
1730 return SelectAtomic64(Node, X86::ATOMSUB6432);
1731 case X86ISD::ATOMNAND64_DAG:
1732 return SelectAtomic64(Node, X86::ATOMNAND6432);
1733 case X86ISD::ATOMAND64_DAG:
1734 return SelectAtomic64(Node, X86::ATOMAND6432);
1735 case X86ISD::ATOMSWAP64_DAG:
1736 return SelectAtomic64(Node, X86::ATOMSWAP6432);
1738 case ISD::ATOMIC_LOAD_ADD: {
1739 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
1745 case ISD::SMUL_LOHI:
1746 case ISD::UMUL_LOHI: {
1747 SDValue N0 = Node->getOperand(0);
1748 SDValue N1 = Node->getOperand(1);
1750 bool isSigned = Opcode == ISD::SMUL_LOHI;
1752 switch (NVT.getSimpleVT().SimpleTy) {
1753 default: llvm_unreachable("Unsupported VT!");
1754 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1755 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1756 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1757 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1760 switch (NVT.getSimpleVT().SimpleTy) {
1761 default: llvm_unreachable("Unsupported VT!");
1762 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1763 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1764 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1765 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1769 unsigned LoReg, HiReg;
1770 switch (NVT.getSimpleVT().SimpleTy) {
1771 default: llvm_unreachable("Unsupported VT!");
1772 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1773 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1774 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1775 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1778 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1779 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1780 // Multiply is commmutative.
1782 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1787 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1788 N0, SDValue()).getValue(1);
1791 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1794 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1795 array_lengthof(Ops));
1796 InFlag = SDValue(CNode, 1);
1797 // Update the chain.
1798 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1801 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1804 // Copy the low half of the result, if it is needed.
1805 if (!N.getValue(0).use_empty()) {
1806 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1807 LoReg, NVT, InFlag);
1808 InFlag = Result.getValue(2);
1809 ReplaceUses(N.getValue(0), Result);
1812 errs() << std::string(Indent-2, ' ') << "=> ";
1813 Result.getNode()->dump(CurDAG);
1818 // Copy the high half of the result, if it is needed.
1819 if (!N.getValue(1).use_empty()) {
1821 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1822 // Prevent use of AH in a REX instruction by referencing AX instead.
1823 // Shift it down 8 bits.
1824 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1825 X86::AX, MVT::i16, InFlag);
1826 InFlag = Result.getValue(2);
1827 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
1829 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1830 // Then truncate it down to i8.
1831 Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
1834 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1835 HiReg, NVT, InFlag);
1836 InFlag = Result.getValue(2);
1838 ReplaceUses(N.getValue(1), Result);
1841 errs() << std::string(Indent-2, ' ') << "=> ";
1842 Result.getNode()->dump(CurDAG);
1856 case ISD::UDIVREM: {
1857 SDValue N0 = Node->getOperand(0);
1858 SDValue N1 = Node->getOperand(1);
1860 bool isSigned = Opcode == ISD::SDIVREM;
1862 switch (NVT.getSimpleVT().SimpleTy) {
1863 default: llvm_unreachable("Unsupported VT!");
1864 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1865 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1866 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1867 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1870 switch (NVT.getSimpleVT().SimpleTy) {
1871 default: llvm_unreachable("Unsupported VT!");
1872 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1873 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1874 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1875 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1879 unsigned LoReg, HiReg;
1880 unsigned ClrOpcode, SExtOpcode;
1881 switch (NVT.getSimpleVT().SimpleTy) {
1882 default: llvm_unreachable("Unsupported VT!");
1884 LoReg = X86::AL; HiReg = X86::AH;
1886 SExtOpcode = X86::CBW;
1889 LoReg = X86::AX; HiReg = X86::DX;
1890 ClrOpcode = X86::MOV16r0;
1891 SExtOpcode = X86::CWD;
1894 LoReg = X86::EAX; HiReg = X86::EDX;
1895 ClrOpcode = X86::MOV32r0;
1896 SExtOpcode = X86::CDQ;
1899 LoReg = X86::RAX; HiReg = X86::RDX;
1900 ClrOpcode = ~0U; // NOT USED.
1901 SExtOpcode = X86::CQO;
1905 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1906 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
1907 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
1910 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
1911 // Special case for div8, just use a move with zero extension to AX to
1912 // clear the upper 8 bits (AH).
1913 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
1914 if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
1915 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
1917 SDValue(CurDAG->getMachineNode(X86::MOVZX16rm8, dl, MVT::i16,
1919 array_lengthof(Ops)), 0);
1920 Chain = Move.getValue(1);
1921 ReplaceUses(N0.getValue(1), Chain);
1924 SDValue(CurDAG->getMachineNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
1925 Chain = CurDAG->getEntryNode();
1927 Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
1928 InFlag = Chain.getValue(1);
1931 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
1932 LoReg, N0, SDValue()).getValue(1);
1933 if (isSigned && !signBitIsZero) {
1934 // Sign extend the low part into the high part.
1936 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
1938 // Zero out the high part, effectively zero extending the input.
1941 if (NVT.getSimpleVT() == MVT::i64) {
1942 ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, MVT::i32),
1944 // We just did a 32-bit clear, insert it into a 64-bit register to
1945 // clear the whole 64-bit reg.
1947 SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF,
1950 CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
1952 SDValue(CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
1953 MVT::i64, Undef, ClrNode, SubRegNo),
1956 ClrNode = SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
1959 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg,
1960 ClrNode, InFlag).getValue(1);
1965 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
1968 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Flag, Ops,
1969 array_lengthof(Ops));
1970 InFlag = SDValue(CNode, 1);
1971 // Update the chain.
1972 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1975 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1978 // Copy the division (low) result, if it is needed.
1979 if (!N.getValue(0).use_empty()) {
1980 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1981 LoReg, NVT, InFlag);
1982 InFlag = Result.getValue(2);
1983 ReplaceUses(N.getValue(0), Result);
1986 errs() << std::string(Indent-2, ' ') << "=> ";
1987 Result.getNode()->dump(CurDAG);
1992 // Copy the remainder (high) result, if it is needed.
1993 if (!N.getValue(1).use_empty()) {
1995 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1996 // Prevent use of AH in a REX instruction by referencing AX instead.
1997 // Shift it down 8 bits.
1998 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1999 X86::AX, MVT::i16, InFlag);
2000 InFlag = Result.getValue(2);
2001 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2003 CurDAG->getTargetConstant(8, MVT::i8)),
2005 // Then truncate it down to i8.
2006 Result = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
2009 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2010 HiReg, NVT, InFlag);
2011 InFlag = Result.getValue(2);
2013 ReplaceUses(N.getValue(1), Result);
2016 errs() << std::string(Indent-2, ' ') << "=> ";
2017 Result.getNode()->dump(CurDAG);
2031 SDValue N0 = Node->getOperand(0);
2032 SDValue N1 = Node->getOperand(1);
2034 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2035 // use a smaller encoding.
2036 if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2037 N0.getValueType() != MVT::i8 &&
2038 X86::isZeroNode(N1)) {
2039 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2042 // For example, convert "testl %eax, $8" to "testb %al, $8"
2043 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2044 (!(C->getZExtValue() & 0x80) ||
2045 HasNoSignedComparisonUses(Node))) {
2046 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2047 SDValue Reg = N0.getNode()->getOperand(0);
2049 // On x86-32, only the ABCD registers have 8-bit subregisters.
2050 if (!Subtarget->is64Bit()) {
2051 TargetRegisterClass *TRC = 0;
2052 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2053 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2054 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2055 default: llvm_unreachable("Unsupported TEST operand type!");
2057 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2058 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2059 Reg.getValueType(), Reg, RC), 0);
2062 // Extract the l-register.
2063 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT, dl,
2067 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
2070 // For example, "testl %eax, $2048" to "testb %ah, $8".
2071 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2072 (!(C->getZExtValue() & 0x8000) ||
2073 HasNoSignedComparisonUses(Node))) {
2074 // Shift the immediate right by 8 bits.
2075 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2077 SDValue Reg = N0.getNode()->getOperand(0);
2079 // Put the value in an ABCD register.
2080 TargetRegisterClass *TRC = 0;
2081 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2082 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2083 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2084 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2085 default: llvm_unreachable("Unsupported TEST operand type!");
2087 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2088 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2089 Reg.getValueType(), Reg, RC), 0);
2091 // Extract the h-register.
2092 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_8BIT_HI, dl,
2095 // Emit a testb. No special NOREX tricks are needed since there's
2096 // only one GPR operand!
2097 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2098 Subreg, ShiftedImm);
2101 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2102 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2103 N0.getValueType() != MVT::i16 &&
2104 (!(C->getZExtValue() & 0x8000) ||
2105 HasNoSignedComparisonUses(Node))) {
2106 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2107 SDValue Reg = N0.getNode()->getOperand(0);
2109 // Extract the 16-bit subregister.
2110 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_16BIT, dl,
2114 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
2117 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2118 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2119 N0.getValueType() == MVT::i64 &&
2120 (!(C->getZExtValue() & 0x80000000) ||
2121 HasNoSignedComparisonUses(Node))) {
2122 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2123 SDValue Reg = N0.getNode()->getOperand(0);
2125 // Extract the 32-bit subregister.
2126 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::SUBREG_32BIT, dl,
2130 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
2137 SDNode *ResNode = SelectCode(N);
2141 errs() << std::string(Indent-2, ' ') << "=> ";
2142 if (ResNode == NULL || ResNode == N.getNode())
2143 N.getNode()->dump(CurDAG);
2145 ResNode->dump(CurDAG);
2154 bool X86DAGToDAGISel::
2155 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2156 std::vector<SDValue> &OutOps) {
2157 SDValue Op0, Op1, Op2, Op3, Op4;
2158 switch (ConstraintCode) {
2159 case 'o': // offsetable ??
2160 case 'v': // not offsetable ??
2161 default: return true;
2163 if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3, Op4))
2168 OutOps.push_back(Op0);
2169 OutOps.push_back(Op1);
2170 OutOps.push_back(Op2);
2171 OutOps.push_back(Op3);
2172 OutOps.push_back(Op4);
2176 /// createX86ISelDag - This pass converts a legalized DAG into a
2177 /// X86-specific DAG, ready for instruction scheduling.
2179 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2180 llvm::CodeGenOpt::Level OptLevel) {
2181 return new X86DAGToDAGISel(TM, OptLevel);