1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "X86TargetMachine.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/CFG.h"
27 #include "llvm/Type.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/Streams.h"
40 #include "llvm/ADT/SmallPtrSet.h"
41 #include "llvm/ADT/Statistic.h"
44 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
46 //===----------------------------------------------------------------------===//
47 // Pattern Matcher Implementation
48 //===----------------------------------------------------------------------===//
51 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
52 /// SDValue's instead of register numbers for the leaves of the matched
54 struct X86ISelAddressMode {
60 struct { // This is really a union, discriminated by BaseType!
65 bool isRIPRel; // RIP as base?
73 unsigned Align; // CP alignment.
76 : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
77 GV(0), CP(0), ES(0), JT(-1), Align(0) {
80 bool hasSymbolicDisplacement() const {
81 return GV != 0 || CP != 0 || ES != 0 || JT != -1;
85 cerr << "X86ISelAddressMode " << this << "\n";
87 if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
89 cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
90 cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n";
92 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
94 cerr << " Disp " << Disp << "\n";
95 cerr << "GV "; if (GV) GV->dump();
97 cerr << " CP "; if (CP) CP->dump();
100 cerr << "ES "; if (ES) cerr << ES; else cerr << "nul";
101 cerr << " JT" << JT << " Align" << Align << "\n";
107 //===--------------------------------------------------------------------===//
108 /// ISel - X86 specific code to select X86 machine instructions for
109 /// SelectionDAG operations.
111 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
112 /// TM - Keep a reference to X86TargetMachine.
114 X86TargetMachine &TM;
116 /// X86Lowering - This object fully describes how to lower LLVM code to an
117 /// X86-specific SelectionDAG.
118 X86TargetLowering &X86Lowering;
120 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
121 /// make the right decision when generating code for different targets.
122 const X86Subtarget *Subtarget;
124 /// CurBB - Current BB being isel'd.
126 MachineBasicBlock *CurBB;
128 /// OptForSize - If true, selector should try to optimize for code size
129 /// instead of performance.
133 X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
134 : SelectionDAGISel(tm, fast),
135 TM(tm), X86Lowering(*TM.getTargetLowering()),
136 Subtarget(&TM.getSubtarget<X86Subtarget>()),
139 virtual const char *getPassName() const {
140 return "X86 DAG->DAG Instruction Selection";
143 /// InstructionSelect - This callback is invoked by
144 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
145 virtual void InstructionSelect();
147 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
150 bool IsLegalAndProfitableToFold(SDNode *N, SDNode *U, SDNode *Root) const;
152 // Include the pieces autogenerated from the target description.
153 #include "X86GenDAGISel.inc"
156 SDNode *Select(SDValue N);
157 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
159 bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
160 bool isRoot = true, unsigned Depth = 0);
161 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
162 bool isRoot, unsigned Depth);
163 bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
164 SDValue &Scale, SDValue &Index, SDValue &Disp);
165 bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
166 SDValue &Scale, SDValue &Index, SDValue &Disp);
167 bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
168 SDValue N, SDValue &Base, SDValue &Scale,
169 SDValue &Index, SDValue &Disp,
170 SDValue &InChain, SDValue &OutChain);
171 bool TryFoldLoad(SDValue P, SDValue N,
172 SDValue &Base, SDValue &Scale,
173 SDValue &Index, SDValue &Disp);
174 void PreprocessForRMW();
175 void PreprocessForFPConvert();
177 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
178 /// inline asm expressions.
179 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
181 std::vector<SDValue> &OutOps);
183 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
185 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
186 SDValue &Scale, SDValue &Index,
188 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
189 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
191 Scale = getI8Imm(AM.Scale);
193 // These are 32-bit even in 64-bit mode since RIP relative offset
196 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp);
198 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
201 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32);
202 else if (AM.JT != -1)
203 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
205 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
208 /// getI8Imm - Return a target constant with the specified value, of type
210 inline SDValue getI8Imm(unsigned Imm) {
211 return CurDAG->getTargetConstant(Imm, MVT::i8);
214 /// getI16Imm - Return a target constant with the specified value, of type
216 inline SDValue getI16Imm(unsigned Imm) {
217 return CurDAG->getTargetConstant(Imm, MVT::i16);
220 /// getI32Imm - Return a target constant with the specified value, of type
222 inline SDValue getI32Imm(unsigned Imm) {
223 return CurDAG->getTargetConstant(Imm, MVT::i32);
226 /// getGlobalBaseReg - Return an SDNode that returns the value of
227 /// the global base register. Output instructions required to
228 /// initialize the global base register, if necessary.
230 SDNode *getGlobalBaseReg();
232 /// getTruncateTo8Bit - return an SDNode that implements a subreg based
233 /// truncate of the specified operand to i8. This can be done with tablegen,
234 /// except that this code uses MVT::Flag in a tricky way that happens to
235 /// improve scheduling in some cases.
236 SDNode *getTruncateTo8Bit(SDValue N0);
244 /// findFlagUse - Return use of MVT::Flag value produced by the specified
247 static SDNode *findFlagUse(SDNode *N) {
248 unsigned FlagResNo = N->getNumValues()-1;
249 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
250 SDUse &Use = I.getUse();
251 if (Use.getResNo() == FlagResNo)
252 return Use.getUser();
257 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def".
258 /// This function recursively traverses up the operand chain, ignoring
260 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
262 SmallPtrSet<SDNode*, 16> &Visited) {
263 if (Use->getNodeId() < Def->getNodeId() ||
264 !Visited.insert(Use))
267 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
268 SDNode *N = Use->getOperand(i).getNode();
270 if (Use == ImmedUse || Use == Root)
271 continue; // We are not looking for immediate use.
276 // Traverse up the operand chain.
277 if (findNonImmUse(N, Def, ImmedUse, Root, Visited))
283 /// isNonImmUse - Start searching from Root up the DAG to check is Def can
284 /// be reached. Return true if that's the case. However, ignore direct uses
285 /// by ImmedUse (which would be U in the example illustrated in
286 /// IsLegalAndProfitableToFold) and by Root (which can happen in the store
288 /// FIXME: to be really generic, we should allow direct use by any node
289 /// that is being folded. But realisticly since we only fold loads which
290 /// have one non-chain use, we only need to watch out for load/op/store
291 /// and load/op/cmp case where the root (store / cmp) may reach the load via
292 /// its chain operand.
293 static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
294 SmallPtrSet<SDNode*, 16> Visited;
295 return findNonImmUse(Root, Def, ImmedUse, Root, Visited);
299 bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
300 SDNode *Root) const {
301 if (Fast) return false;
304 switch (U->getOpcode()) {
312 // If the other operand is a 8-bit immediate we should fold the immediate
313 // instead. This reduces code size.
315 // movl 4(%esp), %eax
319 // addl 4(%esp), %eax
320 // The former is 2 bytes shorter. In case where the increment is 1, then
321 // the saving can be 4 bytes (by using incl %eax).
322 ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(U->getOperand(1));
324 if (U->getValueType(0) == MVT::i64) {
325 if ((int32_t)Imm->getZExtValue() == (int64_t)Imm->getZExtValue())
328 if ((int8_t)Imm->getZExtValue() == (int64_t)Imm->getZExtValue())
335 // If Root use can somehow reach N through a path that that doesn't contain
336 // U then folding N would create a cycle. e.g. In the following
337 // diagram, Root can reach N through X. If N is folded into into Root, then
338 // X is both a predecessor and a successor of U.
349 // * indicates nodes to be folded together.
351 // If Root produces a flag, then it gets (even more) interesting. Since it
352 // will be "glued" together with its flag use in the scheduler, we need to
353 // check if it might reach N.
372 // If FU (flag use) indirectly reaches N (the load), and Root folds N
373 // (call it Fold), then X is a predecessor of FU and a successor of
374 // Fold. But since Fold and FU are flagged together, this will create
375 // a cycle in the scheduling graph.
377 MVT VT = Root->getValueType(Root->getNumValues()-1);
378 while (VT == MVT::Flag) {
379 SDNode *FU = findFlagUse(Root);
383 VT = Root->getValueType(Root->getNumValues()-1);
386 return !isNonImmUse(Root, N, U);
389 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
390 /// and move load below the TokenFactor. Replace store's chain operand with
391 /// load's chain result.
392 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
393 SDValue Store, SDValue TF) {
394 SmallVector<SDValue, 4> Ops;
395 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
396 if (Load.getNode() == TF.getOperand(i).getNode())
397 Ops.push_back(Load.getOperand(0));
399 Ops.push_back(TF.getOperand(i));
400 CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
401 CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
402 CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
403 Store.getOperand(2), Store.getOperand(3));
406 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
408 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
410 if (N.getOpcode() == ISD::BIT_CONVERT)
413 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
414 if (!LD || LD->isVolatile())
416 if (LD->getAddressingMode() != ISD::UNINDEXED)
419 ISD::LoadExtType ExtType = LD->getExtensionType();
420 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
424 N.getOperand(1) == Address &&
425 N.getNode()->isOperandOf(Chain.getNode())) {
432 /// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
433 /// operand and move load below the call's chain operand.
434 static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
435 SDValue Call, SDValue CallSeqStart) {
436 SmallVector<SDValue, 8> Ops;
437 SDValue Chain = CallSeqStart.getOperand(0);
438 if (Chain.getNode() == Load.getNode())
439 Ops.push_back(Load.getOperand(0));
441 assert(Chain.getOpcode() == ISD::TokenFactor &&
442 "Unexpected CallSeqStart chain operand");
443 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
444 if (Chain.getOperand(i).getNode() == Load.getNode())
445 Ops.push_back(Load.getOperand(0));
447 Ops.push_back(Chain.getOperand(i));
449 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
450 MVT::Other, &Ops[0], Ops.size());
452 Ops.push_back(NewChain);
454 for (unsigned i = 1, e = CallSeqStart.getNumOperands(); i != e; ++i)
455 Ops.push_back(CallSeqStart.getOperand(i));
456 CurDAG->UpdateNodeOperands(CallSeqStart, &Ops[0], Ops.size());
457 CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
458 Load.getOperand(1), Load.getOperand(2));
460 Ops.push_back(SDValue(Load.getNode(), 1));
461 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
462 Ops.push_back(Call.getOperand(i));
463 CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
466 /// isCalleeLoad - Return true if call address is a load and it can be
467 /// moved below CALLSEQ_START and the chains leading up to the call.
468 /// Return the CALLSEQ_START by reference as a second output.
469 static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
470 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
472 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
475 LD->getAddressingMode() != ISD::UNINDEXED ||
476 LD->getExtensionType() != ISD::NON_EXTLOAD)
479 // Now let's find the callseq_start.
480 while (Chain.getOpcode() != ISD::CALLSEQ_START) {
481 if (!Chain.hasOneUse())
483 Chain = Chain.getOperand(0);
486 if (Chain.getOperand(0).getNode() == Callee.getNode())
488 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
489 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()))
495 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
496 /// This is only run if not in -fast mode (aka -O0).
497 /// This allows the instruction selector to pick more read-modify-write
498 /// instructions. This is a common case:
508 /// [TokenFactor] [Op]
515 /// The fact the store's chain operand != load's chain will prevent the
516 /// (store (op (load))) instruction from being selected. We can transform it to:
535 void X86DAGToDAGISel::PreprocessForRMW() {
536 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
537 E = CurDAG->allnodes_end(); I != E; ++I) {
538 if (I->getOpcode() == X86ISD::CALL) {
539 /// Also try moving call address load from outside callseq_start to just
540 /// before the call to allow it to be folded.
558 SDValue Chain = I->getOperand(0);
559 SDValue Load = I->getOperand(1);
560 if (!isCalleeLoad(Load, Chain))
562 MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
567 if (!ISD::isNON_TRUNCStore(I))
569 SDValue Chain = I->getOperand(0);
571 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
574 SDValue N1 = I->getOperand(1);
575 SDValue N2 = I->getOperand(2);
576 if ((N1.getValueType().isFloatingPoint() &&
577 !N1.getValueType().isVector()) ||
583 unsigned Opcode = N1.getNode()->getOpcode();
592 case ISD::VECTOR_SHUFFLE: {
593 SDValue N10 = N1.getOperand(0);
594 SDValue N11 = N1.getOperand(1);
595 RModW = isRMWLoad(N10, Chain, N2, Load);
597 RModW = isRMWLoad(N11, Chain, N2, Load);
610 SDValue N10 = N1.getOperand(0);
611 RModW = isRMWLoad(N10, Chain, N2, Load);
617 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
624 /// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend
625 /// nodes that target the FP stack to be store and load to the stack. This is a
626 /// gross hack. We would like to simply mark these as being illegal, but when
627 /// we do that, legalize produces these when it expands calls, then expands
628 /// these in the same legalize pass. We would like dag combine to be able to
629 /// hack on these between the call expansion and the node legalization. As such
630 /// this pass basically does "really late" legalization of these inline with the
632 void X86DAGToDAGISel::PreprocessForFPConvert() {
633 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
634 E = CurDAG->allnodes_end(); I != E; ) {
635 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
636 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
639 // If the source and destination are SSE registers, then this is a legal
640 // conversion that should not be lowered.
641 MVT SrcVT = N->getOperand(0).getValueType();
642 MVT DstVT = N->getValueType(0);
643 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
644 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
645 if (SrcIsSSE && DstIsSSE)
648 if (!SrcIsSSE && !DstIsSSE) {
649 // If this is an FPStack extension, it is a noop.
650 if (N->getOpcode() == ISD::FP_EXTEND)
652 // If this is a value-preserving FPStack truncation, it is a noop.
653 if (N->getConstantOperandVal(1))
657 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
658 // FPStack has extload and truncstore. SSE can fold direct loads into other
659 // operations. Based on this, decide what we want to do.
661 if (N->getOpcode() == ISD::FP_ROUND)
662 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
664 MemVT = SrcIsSSE ? SrcVT : DstVT;
666 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
667 DebugLoc dl = N->getDebugLoc();
669 // FIXME: optimize the case where the src/dest is a load or store?
670 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
672 MemTmp, NULL, 0, MemVT);
673 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
676 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
677 // extload we created. This will cause general havok on the dag because
678 // anything below the conversion could be folded into other existing nodes.
679 // To avoid invalidating 'I', back it up to the convert node.
681 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
683 // Now that we did that, the node is dead. Increment the iterator to the
684 // next node to process, then delete N.
686 CurDAG->DeleteNode(N);
690 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
691 /// when it has created a SelectionDAG for us to codegen.
692 void X86DAGToDAGISel::InstructionSelect() {
693 CurBB = BB; // BB can change as result of isel.
694 const Function *F = CurDAG->getMachineFunction().getFunction();
695 OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
701 // FIXME: This should only happen when not -fast.
702 PreprocessForFPConvert();
704 // Codegen the basic block.
706 DOUT << "===== Instruction selection begins:\n";
711 DOUT << "===== Instruction selection ends:\n";
714 CurDAG->RemoveDeadNodes();
717 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
718 /// the main function.
719 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
720 MachineFrameInfo *MFI) {
721 const TargetInstrInfo *TII = TM.getInstrInfo();
722 if (Subtarget->isTargetCygMing())
723 BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
726 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
727 // If this is main, emit special code for main.
728 MachineBasicBlock *BB = MF.begin();
729 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
730 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
733 /// MatchAddress - Add the specified node to the specified addressing mode,
734 /// returning true if it cannot be done. This just pattern matches for the
736 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
737 bool isRoot, unsigned Depth) {
738 bool is64Bit = Subtarget->is64Bit();
739 DebugLoc dl = N.getDebugLoc();
740 DOUT << "MatchAddress: "; DEBUG(AM.dump());
743 return MatchAddressBase(N, AM, isRoot, Depth);
745 // RIP relative addressing: %rip + 32-bit displacement!
747 if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
748 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
749 if (!is64Bit || isInt32(AM.Disp + Val)) {
757 switch (N.getOpcode()) {
759 case ISD::Constant: {
760 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
761 if (!is64Bit || isInt32(AM.Disp + Val)) {
768 case X86ISD::Wrapper: {
769 DOUT << "Wrapper: 64bit " << is64Bit;
770 DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
771 // Under X86-64 non-small code model, GV (and friends) are 64-bits.
772 // Also, base and index reg must be 0 in order to use rip as base.
773 if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
774 AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
776 if (AM.hasSymbolicDisplacement())
778 // If value is available in a register both base and index components have
779 // been picked, we can't fit the result available in the register in the
780 // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
782 SDValue N0 = N.getOperand(0);
783 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
784 uint64_t Offset = G->getOffset();
785 if (!is64Bit || isInt32(AM.Disp + Offset)) {
786 GlobalValue *GV = G->getGlobal();
789 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
792 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
793 uint64_t Offset = CP->getOffset();
794 if (!is64Bit || isInt32(AM.Disp + Offset)) {
795 AM.CP = CP->getConstVal();
796 AM.Align = CP->getAlignment();
798 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
801 } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
802 AM.ES = S->getSymbol();
803 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
805 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
806 AM.JT = J->getIndex();
807 AM.isRIPRel = TM.symbolicAddressesAreRIPRel();
814 case ISD::FrameIndex:
815 if (AM.BaseType == X86ISelAddressMode::RegBase
816 && AM.Base.Reg.getNode() == 0) {
817 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
818 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
824 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1 || AM.isRIPRel)
828 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
829 unsigned Val = CN->getZExtValue();
830 if (Val == 1 || Val == 2 || Val == 3) {
832 SDValue ShVal = N.getNode()->getOperand(0);
834 // Okay, we know that we have a scale by now. However, if the scaled
835 // value is an add of something and a constant, we can fold the
836 // constant into the disp field here.
837 if (ShVal.getNode()->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
838 isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
839 AM.IndexReg = ShVal.getNode()->getOperand(0);
840 ConstantSDNode *AddVal =
841 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
842 uint64_t Disp = AM.Disp + (AddVal->getSExtValue() << Val);
843 if (!is64Bit || isInt32(Disp))
857 // A mul_lohi where we need the low part can be folded as a plain multiply.
858 if (N.getResNo() != 0) break;
861 // X*[3,5,9] -> X+X*[2,4,8]
862 if (AM.BaseType == X86ISelAddressMode::RegBase &&
863 AM.Base.Reg.getNode() == 0 &&
864 AM.IndexReg.getNode() == 0 &&
867 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
868 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
869 CN->getZExtValue() == 9) {
870 AM.Scale = unsigned(CN->getZExtValue())-1;
872 SDValue MulVal = N.getNode()->getOperand(0);
875 // Okay, we know that we have a scale by now. However, if the scaled
876 // value is an add of something and a constant, we can fold the
877 // constant into the disp field here.
878 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
879 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
880 Reg = MulVal.getNode()->getOperand(0);
881 ConstantSDNode *AddVal =
882 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
883 uint64_t Disp = AM.Disp + AddVal->getSExtValue() *
885 if (!is64Bit || isInt32(Disp))
888 Reg = N.getNode()->getOperand(0);
890 Reg = N.getNode()->getOperand(0);
893 AM.IndexReg = AM.Base.Reg = Reg;
900 X86ISelAddressMode Backup = AM;
901 if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) &&
902 !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1))
905 if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) &&
906 !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1))
913 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
914 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
915 X86ISelAddressMode Backup = AM;
916 uint64_t Offset = CN->getSExtValue();
917 // Start with the LHS as an addr mode.
918 if (!MatchAddress(N.getOperand(0), AM, false) &&
919 // Address could not have picked a GV address for the displacement.
921 // On x86-64, the resultant disp must fit in 32-bits.
922 (!is64Bit || isInt32(AM.Disp + Offset)) &&
923 // Check to see if the LHS & C is zero.
924 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
933 // Handle "(x << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
934 // allows us to fold the shift into this addressing mode.
935 SDValue Shift = N.getOperand(0);
936 if (Shift.getOpcode() != ISD::SHL) break;
938 // Scale must not be used already.
939 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
941 // Not when RIP is used as the base.
942 if (AM.isRIPRel) break;
944 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
945 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
946 if (!C1 || !C2) break;
948 // Not likely to be profitable if either the AND or SHIFT node has more
949 // than one use (unless all uses are for address computation). Besides,
950 // isel mechanism requires their node ids to be reused.
951 if (!N.hasOneUse() || !Shift.hasOneUse())
954 // Verify that the shift amount is something we can fold.
955 unsigned ShiftCst = C1->getZExtValue();
956 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
959 // Get the new AND mask, this folds to a constant.
960 SDValue X = Shift.getOperand(0);
961 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(),
962 SDValue(C2, 0), SDValue(C1, 0));
963 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X,
965 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(),
966 NewAND, SDValue(C1, 0));
968 // Insert the new nodes into the topological ordering.
969 if (C1->getNodeId() > X.getNode()->getNodeId()) {
970 CurDAG->RepositionNode(X.getNode(), C1);
971 C1->setNodeId(X.getNode()->getNodeId());
973 if (NewANDMask.getNode()->getNodeId() == -1 ||
974 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) {
975 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode());
976 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId());
978 if (NewAND.getNode()->getNodeId() == -1 ||
979 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) {
980 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode());
981 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId());
983 if (NewSHIFT.getNode()->getNodeId() == -1 ||
984 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) {
985 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode());
986 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId());
989 CurDAG->ReplaceAllUsesWith(N, NewSHIFT);
991 AM.Scale = 1 << ShiftCst;
992 AM.IndexReg = NewAND;
997 return MatchAddressBase(N, AM, isRoot, Depth);
1000 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1001 /// specified addressing mode without any further recursion.
1002 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
1003 bool isRoot, unsigned Depth) {
1004 // Is the base register already occupied?
1005 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
1006 // If so, check to see if the scale index register is set.
1007 if (AM.IndexReg.getNode() == 0 && !AM.isRIPRel) {
1013 // Otherwise, we cannot select it.
1017 // Default, generate it as a register.
1018 AM.BaseType = X86ISelAddressMode::RegBase;
1023 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1024 /// It returns the operands which make up the maximal addressing mode it can
1025 /// match by reference.
1026 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
1027 SDValue &Scale, SDValue &Index,
1029 X86ISelAddressMode AM;
1030 if (MatchAddress(N, AM))
1033 MVT VT = N.getValueType();
1034 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1035 if (!AM.Base.Reg.getNode())
1036 AM.Base.Reg = CurDAG->getRegister(0, VT);
1039 if (!AM.IndexReg.getNode())
1040 AM.IndexReg = CurDAG->getRegister(0, VT);
1042 getAddressOperands(AM, Base, Scale, Index, Disp);
1046 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1047 /// match a load whose top elements are either undef or zeros. The load flavor
1048 /// is derived from the type of N, which is either v4f32 or v2f64.
1049 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
1050 SDValue N, SDValue &Base,
1051 SDValue &Scale, SDValue &Index,
1052 SDValue &Disp, SDValue &InChain,
1053 SDValue &OutChain) {
1054 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1055 InChain = N.getOperand(0).getValue(1);
1056 if (ISD::isNON_EXTLoad(InChain.getNode()) &&
1057 InChain.getValue(0).hasOneUse() &&
1059 IsLegalAndProfitableToFold(N.getNode(), Pred.getNode(), Op.getNode())) {
1060 LoadSDNode *LD = cast<LoadSDNode>(InChain);
1061 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
1063 OutChain = LD->getChain();
1068 // Also handle the case where we explicitly require zeros in the top
1069 // elements. This is a vector shuffle from the zero vector.
1070 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1071 // Check to see if the top elements are all zeros (or bitcast of zeros).
1072 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1073 N.getOperand(0).getNode()->hasOneUse() &&
1074 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1075 N.getOperand(0).getOperand(0).hasOneUse()) {
1076 // Okay, this is a zero extending load. Fold it.
1077 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1078 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
1080 OutChain = LD->getChain();
1081 InChain = SDValue(LD, 1);
1088 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1089 /// mode it matches can be cost effectively emitted as an LEA instruction.
1090 bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
1091 SDValue &Base, SDValue &Scale,
1092 SDValue &Index, SDValue &Disp) {
1093 X86ISelAddressMode AM;
1094 if (MatchAddress(N, AM))
1097 MVT VT = N.getValueType();
1098 unsigned Complexity = 0;
1099 if (AM.BaseType == X86ISelAddressMode::RegBase)
1100 if (AM.Base.Reg.getNode())
1103 AM.Base.Reg = CurDAG->getRegister(0, VT);
1104 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1107 if (AM.IndexReg.getNode())
1110 AM.IndexReg = CurDAG->getRegister(0, VT);
1112 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1117 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1118 // to a LEA. This is determined with some expermentation but is by no means
1119 // optimal (especially for code size consideration). LEA is nice because of
1120 // its three-address nature. Tweak the cost function again when we can run
1121 // convertToThreeAddress() at register allocation time.
1122 if (AM.hasSymbolicDisplacement()) {
1123 // For X86-64, we should always use lea to materialize RIP relative
1125 if (Subtarget->is64Bit())
1131 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
1134 if (Complexity > 2) {
1135 getAddressOperands(AM, Base, Scale, Index, Disp);
1141 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
1142 SDValue &Base, SDValue &Scale,
1143 SDValue &Index, SDValue &Disp) {
1144 if (ISD::isNON_EXTLoad(N.getNode()) &&
1146 IsLegalAndProfitableToFold(N.getNode(), P.getNode(), P.getNode()))
1147 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
1151 /// getGlobalBaseReg - Return an SDNode that returns the value of
1152 /// the global base register. Output instructions required to
1153 /// initialize the global base register, if necessary.
1155 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1156 MachineFunction *MF = CurBB->getParent();
1157 unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF);
1158 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1161 static SDNode *FindCallStartFromCall(SDNode *Node) {
1162 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1163 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1164 "Node doesn't have a token chain argument!");
1165 return FindCallStartFromCall(Node->getOperand(0).getNode());
1168 /// getTruncateTo8Bit - return an SDNode that implements a subreg based
1169 /// truncate of the specified operand to i8. This can be done with tablegen,
1170 /// except that this code uses MVT::Flag in a tricky way that happens to
1171 /// improve scheduling in some cases.
1172 SDNode *X86DAGToDAGISel::getTruncateTo8Bit(SDValue N0) {
1173 assert(!Subtarget->is64Bit() &&
1174 "getTruncateTo8Bit is only needed on x86-32!");
1175 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1176 DebugLoc dl = N0.getDebugLoc();
1178 // Ensure that the source register has an 8-bit subreg on 32-bit targets
1180 MVT N0VT = N0.getValueType();
1181 switch (N0VT.getSimpleVT()) {
1182 default: assert(0 && "Unknown truncate!");
1184 Opc = X86::MOV16to16_;
1187 Opc = X86::MOV32to32_;
1191 // The use of MVT::Flag here is not strictly accurate, but it helps
1192 // scheduling in some cases.
1193 N0 = SDValue(CurDAG->getTargetNode(Opc, dl, N0VT, MVT::Flag, N0), 0);
1194 return CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
1195 MVT::i8, N0, SRIdx, N0.getValue(1));
1198 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1199 SDValue Chain = Node->getOperand(0);
1200 SDValue In1 = Node->getOperand(1);
1201 SDValue In2L = Node->getOperand(2);
1202 SDValue In2H = Node->getOperand(3);
1203 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
1204 if (!SelectAddr(In1, In1, Tmp0, Tmp1, Tmp2, Tmp3))
1206 SDValue LSI = Node->getOperand(4); // MemOperand
1207 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, In2L, In2H, LSI, Chain };
1208 return CurDAG->getTargetNode(Opc, Node->getDebugLoc(),
1209 MVT::i32, MVT::i32, MVT::Other, Ops, 8);
1212 SDNode *X86DAGToDAGISel::Select(SDValue N) {
1213 SDNode *Node = N.getNode();
1214 MVT NVT = Node->getValueType(0);
1216 unsigned Opcode = Node->getOpcode();
1217 DebugLoc dl = Node->getDebugLoc();
1220 DOUT << std::string(Indent, ' ') << "Selecting: ";
1221 DEBUG(Node->dump(CurDAG));
1226 if (Node->isMachineOpcode()) {
1228 DOUT << std::string(Indent-2, ' ') << "== ";
1229 DEBUG(Node->dump(CurDAG));
1233 return NULL; // Already selected.
1238 case X86ISD::GlobalBaseReg:
1239 return getGlobalBaseReg();
1241 case X86ISD::ATOMOR64_DAG:
1242 return SelectAtomic64(Node, X86::ATOMOR6432);
1243 case X86ISD::ATOMXOR64_DAG:
1244 return SelectAtomic64(Node, X86::ATOMXOR6432);
1245 case X86ISD::ATOMADD64_DAG:
1246 return SelectAtomic64(Node, X86::ATOMADD6432);
1247 case X86ISD::ATOMSUB64_DAG:
1248 return SelectAtomic64(Node, X86::ATOMSUB6432);
1249 case X86ISD::ATOMNAND64_DAG:
1250 return SelectAtomic64(Node, X86::ATOMNAND6432);
1251 case X86ISD::ATOMAND64_DAG:
1252 return SelectAtomic64(Node, X86::ATOMAND6432);
1253 case X86ISD::ATOMSWAP64_DAG:
1254 return SelectAtomic64(Node, X86::ATOMSWAP6432);
1256 case ISD::SMUL_LOHI:
1257 case ISD::UMUL_LOHI: {
1258 SDValue N0 = Node->getOperand(0);
1259 SDValue N1 = Node->getOperand(1);
1261 bool isSigned = Opcode == ISD::SMUL_LOHI;
1263 switch (NVT.getSimpleVT()) {
1264 default: assert(0 && "Unsupported VT!");
1265 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1266 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1267 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1268 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1271 switch (NVT.getSimpleVT()) {
1272 default: assert(0 && "Unsupported VT!");
1273 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1274 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1275 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1276 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1279 unsigned LoReg, HiReg;
1280 switch (NVT.getSimpleVT()) {
1281 default: assert(0 && "Unsupported VT!");
1282 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1283 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1284 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1285 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1288 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
1289 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1290 // multiplty is commmutative
1292 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
1297 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1298 N0, SDValue()).getValue(1);
1301 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1303 CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 6);
1304 InFlag = SDValue(CNode, 1);
1305 // Update the chain.
1306 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1309 SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1312 // Copy the low half of the result, if it is needed.
1313 if (!N.getValue(0).use_empty()) {
1314 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1315 LoReg, NVT, InFlag);
1316 InFlag = Result.getValue(2);
1317 ReplaceUses(N.getValue(0), Result);
1319 DOUT << std::string(Indent-2, ' ') << "=> ";
1320 DEBUG(Result.getNode()->dump(CurDAG));
1324 // Copy the high half of the result, if it is needed.
1325 if (!N.getValue(1).use_empty()) {
1327 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1328 // Prevent use of AH in a REX instruction by referencing AX instead.
1329 // Shift it down 8 bits.
1330 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1331 X86::AX, MVT::i16, InFlag);
1332 InFlag = Result.getValue(2);
1333 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
1335 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1336 // Then truncate it down to i8.
1337 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1338 Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
1339 MVT::i8, Result, SRIdx), 0);
1341 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1342 HiReg, NVT, InFlag);
1343 InFlag = Result.getValue(2);
1345 ReplaceUses(N.getValue(1), Result);
1347 DOUT << std::string(Indent-2, ' ') << "=> ";
1348 DEBUG(Result.getNode()->dump(CurDAG));
1361 case ISD::UDIVREM: {
1362 SDValue N0 = Node->getOperand(0);
1363 SDValue N1 = Node->getOperand(1);
1365 bool isSigned = Opcode == ISD::SDIVREM;
1367 switch (NVT.getSimpleVT()) {
1368 default: assert(0 && "Unsupported VT!");
1369 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1370 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1371 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1372 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1375 switch (NVT.getSimpleVT()) {
1376 default: assert(0 && "Unsupported VT!");
1377 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1378 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1379 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1380 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1383 unsigned LoReg, HiReg;
1384 unsigned ClrOpcode, SExtOpcode;
1385 switch (NVT.getSimpleVT()) {
1386 default: assert(0 && "Unsupported VT!");
1388 LoReg = X86::AL; HiReg = X86::AH;
1390 SExtOpcode = X86::CBW;
1393 LoReg = X86::AX; HiReg = X86::DX;
1394 ClrOpcode = X86::MOV16r0;
1395 SExtOpcode = X86::CWD;
1398 LoReg = X86::EAX; HiReg = X86::EDX;
1399 ClrOpcode = X86::MOV32r0;
1400 SExtOpcode = X86::CDQ;
1403 LoReg = X86::RAX; HiReg = X86::RDX;
1404 ClrOpcode = X86::MOV64r0;
1405 SExtOpcode = X86::CQO;
1409 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
1410 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1411 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
1414 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
1415 // Special case for div8, just use a move with zero extension to AX to
1416 // clear the upper 8 bits (AH).
1417 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
1418 if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
1419 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
1421 SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16,
1422 MVT::Other, Ops, 5), 0);
1423 Chain = Move.getValue(1);
1424 ReplaceUses(N0.getValue(1), Chain);
1427 SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0);
1428 Chain = CurDAG->getEntryNode();
1430 Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue());
1431 InFlag = Chain.getValue(1);
1434 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
1435 LoReg, N0, SDValue()).getValue(1);
1436 if (isSigned && !signBitIsZero) {
1437 // Sign extend the low part into the high part.
1439 SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0);
1441 // Zero out the high part, effectively zero extending the input.
1442 SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT),
1444 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, HiReg,
1445 ClrNode, InFlag).getValue(1);
1450 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1452 CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, 6);
1453 InFlag = SDValue(CNode, 1);
1454 // Update the chain.
1455 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1458 SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0);
1461 // Copy the division (low) result, if it is needed.
1462 if (!N.getValue(0).use_empty()) {
1463 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1464 LoReg, NVT, InFlag);
1465 InFlag = Result.getValue(2);
1466 ReplaceUses(N.getValue(0), Result);
1468 DOUT << std::string(Indent-2, ' ') << "=> ";
1469 DEBUG(Result.getNode()->dump(CurDAG));
1473 // Copy the remainder (high) result, if it is needed.
1474 if (!N.getValue(1).use_empty()) {
1476 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1477 // Prevent use of AH in a REX instruction by referencing AX instead.
1478 // Shift it down 8 bits.
1479 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1480 X86::AX, MVT::i16, InFlag);
1481 InFlag = Result.getValue(2);
1482 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16,
1484 CurDAG->getTargetConstant(8, MVT::i8)),
1486 // Then truncate it down to i8.
1487 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1488 Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl,
1489 MVT::i8, Result, SRIdx), 0);
1491 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
1492 HiReg, NVT, InFlag);
1493 InFlag = Result.getValue(2);
1495 ReplaceUses(N.getValue(1), Result);
1497 DOUT << std::string(Indent-2, ' ') << "=> ";
1498 DEBUG(Result.getNode()->dump(CurDAG));
1510 case ISD::SIGN_EXTEND_INREG: {
1511 MVT SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
1512 if (SVT == MVT::i8 && !Subtarget->is64Bit()) {
1513 SDValue N0 = Node->getOperand(0);
1515 SDValue TruncOp = SDValue(getTruncateTo8Bit(N0), 0);
1517 switch (NVT.getSimpleVT()) {
1518 default: assert(0 && "Unknown sign_extend_inreg!");
1520 Opc = X86::MOVSX16rr8;
1523 Opc = X86::MOVSX32rr8;
1527 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, NVT, TruncOp);
1530 DOUT << std::string(Indent-2, ' ') << "=> ";
1531 DEBUG(TruncOp.getNode()->dump(CurDAG));
1533 DOUT << std::string(Indent-2, ' ') << "=> ";
1534 DEBUG(ResNode->dump(CurDAG));
1543 case ISD::TRUNCATE: {
1544 if (NVT == MVT::i8 && !Subtarget->is64Bit()) {
1545 SDValue Input = Node->getOperand(0);
1546 SDNode *ResNode = getTruncateTo8Bit(Input);
1549 DOUT << std::string(Indent-2, ' ') << "=> ";
1550 DEBUG(ResNode->dump(CurDAG));
1559 case ISD::DECLARE: {
1560 // Handle DECLARE nodes here because the second operand may have been
1561 // wrapped in X86ISD::Wrapper.
1562 SDValue Chain = Node->getOperand(0);
1563 SDValue N1 = Node->getOperand(1);
1564 SDValue N2 = Node->getOperand(2);
1565 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1568 if (N2.getOpcode() == ISD::ADD &&
1569 N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg)
1570 N2 = N2.getOperand(1);
1571 if (N2.getOpcode() != X86ISD::Wrapper)
1573 GlobalAddressSDNode *GVNode =
1574 dyn_cast<GlobalAddressSDNode>(N2.getOperand(0));
1577 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1578 TLI.getPointerTy());
1579 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GVNode->getGlobal(),
1580 TLI.getPointerTy());
1581 SDValue Ops[] = { Tmp1, Tmp2, Chain };
1582 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
1583 MVT::Other, Ops, 3);
1588 SDNode *ResNode = SelectCode(N);
1591 DOUT << std::string(Indent-2, ' ') << "=> ";
1592 if (ResNode == NULL || ResNode == N.getNode())
1593 DEBUG(N.getNode()->dump(CurDAG));
1595 DEBUG(ResNode->dump(CurDAG));
1603 bool X86DAGToDAGISel::
1604 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1605 std::vector<SDValue> &OutOps) {
1606 SDValue Op0, Op1, Op2, Op3;
1607 switch (ConstraintCode) {
1608 case 'o': // offsetable ??
1609 case 'v': // not offsetable ??
1610 default: return true;
1612 if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
1617 OutOps.push_back(Op0);
1618 OutOps.push_back(Op1);
1619 OutOps.push_back(Op2);
1620 OutOps.push_back(Op3);
1624 /// createX86ISelDag - This pass converts a legalized DAG into a
1625 /// X86-specific DAG, ready for instruction scheduling.
1627 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
1628 return new X86DAGToDAGISel(TM, Fast);