1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86RegisterInfo.h"
21 #include "X86Subtarget.h"
22 #include "X86TargetMachine.h"
23 #include "llvm/GlobalValue.h"
24 #include "llvm/Instructions.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/CFG.h"
27 #include "llvm/Type.h"
28 #include "llvm/CodeGen/MachineConstantPool.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAGISel.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Support/Compiler.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/Streams.h"
39 #include "llvm/ADT/SmallPtrSet.h"
40 #include "llvm/ADT/Statistic.h"
45 STATISTIC(NumFPKill , "Number of FP_REG_KILL instructions added");
46 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
48 //===----------------------------------------------------------------------===//
49 // Pattern Matcher Implementation
50 //===----------------------------------------------------------------------===//
53 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
54 /// SDValue's instead of register numbers for the leaves of the matched
56 struct X86ISelAddressMode {
62 struct { // This is really a union, discriminated by BaseType!
67 bool isRIPRel; // RIP as base?
75 unsigned Align; // CP alignment.
78 : BaseType(RegBase), isRIPRel(false), Scale(1), IndexReg(), Disp(0),
79 GV(0), CP(0), ES(0), JT(-1), Align(0) {
82 cerr << "X86ISelAddressMode " << this << "\n";
84 if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
86 cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
87 cerr << "isRIPRel " << isRIPRel << " Scale" << Scale << "\n";
89 if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
91 cerr << " Disp " << Disp << "\n";
92 cerr << "GV "; if (GV) GV->dump();
94 cerr << " CP "; if (CP) CP->dump();
97 cerr << "ES "; if (ES) cerr << ES; else cerr << "nul";
98 cerr << " JT" << JT << " Align" << Align << "\n";
104 //===--------------------------------------------------------------------===//
105 /// ISel - X86 specific code to select X86 machine instructions for
106 /// SelectionDAG operations.
108 class VISIBILITY_HIDDEN X86DAGToDAGISel : public SelectionDAGISel {
109 /// ContainsFPCode - Every instruction we select that uses or defines a FP
110 /// register should set this to true.
113 /// TM - Keep a reference to X86TargetMachine.
115 X86TargetMachine &TM;
117 /// X86Lowering - This object fully describes how to lower LLVM code to an
118 /// X86-specific SelectionDAG.
119 X86TargetLowering X86Lowering;
121 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
122 /// make the right decision when generating code for different targets.
123 const X86Subtarget *Subtarget;
125 /// GlobalBaseReg - keeps track of the virtual register mapped onto global
127 unsigned GlobalBaseReg;
129 /// CurBB - Current BB being isel'd.
131 MachineBasicBlock *CurBB;
134 X86DAGToDAGISel(X86TargetMachine &tm, bool fast)
135 : SelectionDAGISel(X86Lowering, fast),
136 ContainsFPCode(false), TM(tm),
137 X86Lowering(*TM.getTargetLowering()),
138 Subtarget(&TM.getSubtarget<X86Subtarget>()) {}
140 virtual bool runOnFunction(Function &Fn) {
141 // Make sure we re-emit a set of the global base reg if necessary
143 return SelectionDAGISel::runOnFunction(Fn);
146 virtual const char *getPassName() const {
147 return "X86 DAG->DAG Instruction Selection";
150 /// InstructionSelect - This callback is invoked by
151 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
152 virtual void InstructionSelect();
154 /// InstructionSelectPostProcessing - Post processing of selected and
155 /// scheduled basic blocks.
156 virtual void InstructionSelectPostProcessing();
158 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
160 virtual bool CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const;
162 // Include the pieces autogenerated from the target description.
163 #include "X86GenDAGISel.inc"
166 SDNode *Select(SDValue N);
168 bool MatchAddress(SDValue N, X86ISelAddressMode &AM,
169 bool isRoot = true, unsigned Depth = 0);
170 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
171 bool isRoot, unsigned Depth);
172 bool SelectAddr(SDValue Op, SDValue N, SDValue &Base,
173 SDValue &Scale, SDValue &Index, SDValue &Disp);
174 bool SelectLEAAddr(SDValue Op, SDValue N, SDValue &Base,
175 SDValue &Scale, SDValue &Index, SDValue &Disp);
176 bool SelectScalarSSELoad(SDValue Op, SDValue Pred,
177 SDValue N, SDValue &Base, SDValue &Scale,
178 SDValue &Index, SDValue &Disp,
179 SDValue &InChain, SDValue &OutChain);
180 bool TryFoldLoad(SDValue P, SDValue N,
181 SDValue &Base, SDValue &Scale,
182 SDValue &Index, SDValue &Disp);
183 void PreprocessForRMW();
184 void PreprocessForFPConvert();
186 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
187 /// inline asm expressions.
188 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
190 std::vector<SDValue> &OutOps);
192 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
194 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
195 SDValue &Scale, SDValue &Index,
197 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
198 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()) :
200 Scale = getI8Imm(AM.Scale);
202 // These are 32-bit even in 64-bit mode since RIP relative offset
205 Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp);
207 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
210 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32);
211 else if (AM.JT != -1)
212 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32);
214 Disp = getI32Imm(AM.Disp);
217 /// getI8Imm - Return a target constant with the specified value, of type
219 inline SDValue getI8Imm(unsigned Imm) {
220 return CurDAG->getTargetConstant(Imm, MVT::i8);
223 /// getI16Imm - Return a target constant with the specified value, of type
225 inline SDValue getI16Imm(unsigned Imm) {
226 return CurDAG->getTargetConstant(Imm, MVT::i16);
229 /// getI32Imm - Return a target constant with the specified value, of type
231 inline SDValue getI32Imm(unsigned Imm) {
232 return CurDAG->getTargetConstant(Imm, MVT::i32);
235 /// getGlobalBaseReg - Return an SDNode that returns the value of
236 /// the global base register. Output instructions required to
237 /// initialize the global base register, if necessary.
239 SDNode *getGlobalBaseReg();
241 /// getTruncateTo8Bit - return an SDNode that implements a subreg based
242 /// truncate of the specified operand to i8. This can be done with tablegen,
243 /// except that this code uses MVT::Flag in a tricky way that happens to
244 /// improve scheduling in some cases.
245 SDNode *getTruncateTo8Bit(SDValue N0);
253 /// findFlagUse - Return use of MVT::Flag value produced by the specified
256 static SDNode *findFlagUse(SDNode *N) {
257 unsigned FlagResNo = N->getNumValues()-1;
258 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
260 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
261 SDValue Op = User->getOperand(i);
262 if (Op.getNode() == N && Op.getResNo() == FlagResNo)
269 /// findNonImmUse - Return true by reference in "found" if "Use" is an
270 /// non-immediate use of "Def". This function recursively traversing
271 /// up the operand chain ignoring certain nodes.
272 static void findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse,
273 SDNode *Root, bool &found,
274 SmallPtrSet<SDNode*, 16> &Visited) {
276 Use->getNodeId() > Def->getNodeId() ||
277 !Visited.insert(Use))
280 for (unsigned i = 0, e = Use->getNumOperands(); !found && i != e; ++i) {
281 SDNode *N = Use->getOperand(i).getNode();
283 if (Use == ImmedUse || Use == Root)
284 continue; // We are not looking for immediate use.
290 // Traverse up the operand chain.
291 findNonImmUse(N, Def, ImmedUse, Root, found, Visited);
295 /// isNonImmUse - Start searching from Root up the DAG to check is Def can
296 /// be reached. Return true if that's the case. However, ignore direct uses
297 /// by ImmedUse (which would be U in the example illustrated in
298 /// CanBeFoldedBy) and by Root (which can happen in the store case).
299 /// FIXME: to be really generic, we should allow direct use by any node
300 /// that is being folded. But realisticly since we only fold loads which
301 /// have one non-chain use, we only need to watch out for load/op/store
302 /// and load/op/cmp case where the root (store / cmp) may reach the load via
303 /// its chain operand.
304 static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
305 SmallPtrSet<SDNode*, 16> Visited;
307 findNonImmUse(Root, Def, ImmedUse, Root, found, Visited);
312 bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
313 if (Fast) return false;
315 // If Root use can somehow reach N through a path that that doesn't contain
316 // U then folding N would create a cycle. e.g. In the following
317 // diagram, Root can reach N through X. If N is folded into into Root, then
318 // X is both a predecessor and a successor of U.
329 // * indicates nodes to be folded together.
331 // If Root produces a flag, then it gets (even more) interesting. Since it
332 // will be "glued" together with its flag use in the scheduler, we need to
333 // check if it might reach N.
352 // If FU (flag use) indirectly reaches N (the load), and Root folds N
353 // (call it Fold), then X is a predecessor of FU and a successor of
354 // Fold. But since Fold and FU are flagged together, this will create
355 // a cycle in the scheduling graph.
357 MVT VT = Root->getValueType(Root->getNumValues()-1);
358 while (VT == MVT::Flag) {
359 SDNode *FU = findFlagUse(Root);
363 VT = Root->getValueType(Root->getNumValues()-1);
366 return !isNonImmUse(Root, N, U);
369 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
370 /// and move load below the TokenFactor. Replace store's chain operand with
371 /// load's chain result.
372 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
373 SDValue Store, SDValue TF) {
374 SmallVector<SDValue, 4> Ops;
375 for (unsigned i = 0, e = TF.getNode()->getNumOperands(); i != e; ++i)
376 if (Load.getNode() == TF.getOperand(i).getNode())
377 Ops.push_back(Load.getOperand(0));
379 Ops.push_back(TF.getOperand(i));
380 CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
381 CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
382 CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
383 Store.getOperand(2), Store.getOperand(3));
386 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
388 static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
390 if (N.getOpcode() == ISD::BIT_CONVERT)
393 LoadSDNode *LD = dyn_cast<LoadSDNode>(N);
394 if (!LD || LD->isVolatile())
396 if (LD->getAddressingMode() != ISD::UNINDEXED)
399 ISD::LoadExtType ExtType = LD->getExtensionType();
400 if (ExtType != ISD::NON_EXTLOAD && ExtType != ISD::EXTLOAD)
404 N.getOperand(1) == Address &&
405 N.getNode()->isOperandOf(Chain.getNode())) {
412 /// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
413 /// operand and move load below the call's chain operand.
414 static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
415 SDValue Call, SDValue Chain) {
416 SmallVector<SDValue, 8> Ops;
417 for (unsigned i = 0, e = Chain.getNode()->getNumOperands(); i != e; ++i)
418 if (Load.getNode() == Chain.getOperand(i).getNode())
419 Ops.push_back(Load.getOperand(0));
421 Ops.push_back(Chain.getOperand(i));
422 CurDAG->UpdateNodeOperands(Chain, &Ops[0], Ops.size());
423 CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
424 Load.getOperand(1), Load.getOperand(2));
426 Ops.push_back(SDValue(Load.getNode(), 1));
427 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
428 Ops.push_back(Call.getOperand(i));
429 CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
432 /// isCalleeLoad - Return true if call address is a load and it can be
433 /// moved below CALLSEQ_START and the chains leading up to the call.
434 /// Return the CALLSEQ_START by reference as a second output.
435 static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
436 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
438 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
441 LD->getAddressingMode() != ISD::UNINDEXED ||
442 LD->getExtensionType() != ISD::NON_EXTLOAD)
445 // Now let's find the callseq_start.
446 while (Chain.getOpcode() != ISD::CALLSEQ_START) {
447 if (!Chain.hasOneUse())
449 Chain = Chain.getOperand(0);
451 return Chain.getOperand(0).getNode() == Callee.getNode();
455 /// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
456 /// This is only run if not in -fast mode (aka -O0).
457 /// This allows the instruction selector to pick more read-modify-write
458 /// instructions. This is a common case:
468 /// [TokenFactor] [Op]
475 /// The fact the store's chain operand != load's chain will prevent the
476 /// (store (op (load))) instruction from being selected. We can transform it to:
495 void X86DAGToDAGISel::PreprocessForRMW() {
496 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
497 E = CurDAG->allnodes_end(); I != E; ++I) {
498 if (I->getOpcode() == X86ISD::CALL) {
499 /// Also try moving call address load from outside callseq_start to just
500 /// before the call to allow it to be folded.
518 SDValue Chain = I->getOperand(0);
519 SDValue Load = I->getOperand(1);
520 if (!isCalleeLoad(Load, Chain))
522 MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
527 if (!ISD::isNON_TRUNCStore(I))
529 SDValue Chain = I->getOperand(0);
531 if (Chain.getNode()->getOpcode() != ISD::TokenFactor)
534 SDValue N1 = I->getOperand(1);
535 SDValue N2 = I->getOperand(2);
536 if ((N1.getValueType().isFloatingPoint() &&
537 !N1.getValueType().isVector()) ||
543 unsigned Opcode = N1.getNode()->getOpcode();
552 case ISD::VECTOR_SHUFFLE: {
553 SDValue N10 = N1.getOperand(0);
554 SDValue N11 = N1.getOperand(1);
555 RModW = isRMWLoad(N10, Chain, N2, Load);
557 RModW = isRMWLoad(N11, Chain, N2, Load);
570 SDValue N10 = N1.getOperand(0);
571 RModW = isRMWLoad(N10, Chain, N2, Load);
577 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
584 /// PreprocessForFPConvert - Walk over the dag lowering fpround and fpextend
585 /// nodes that target the FP stack to be store and load to the stack. This is a
586 /// gross hack. We would like to simply mark these as being illegal, but when
587 /// we do that, legalize produces these when it expands calls, then expands
588 /// these in the same legalize pass. We would like dag combine to be able to
589 /// hack on these between the call expansion and the node legalization. As such
590 /// this pass basically does "really late" legalization of these inline with the
592 void X86DAGToDAGISel::PreprocessForFPConvert() {
593 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
594 E = CurDAG->allnodes_end(); I != E; ) {
595 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
596 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
599 // If the source and destination are SSE registers, then this is a legal
600 // conversion that should not be lowered.
601 MVT SrcVT = N->getOperand(0).getValueType();
602 MVT DstVT = N->getValueType(0);
603 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
604 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
605 if (SrcIsSSE && DstIsSSE)
608 if (!SrcIsSSE && !DstIsSSE) {
609 // If this is an FPStack extension, it is a noop.
610 if (N->getOpcode() == ISD::FP_EXTEND)
612 // If this is a value-preserving FPStack truncation, it is a noop.
613 if (N->getConstantOperandVal(1))
617 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
618 // FPStack has extload and truncstore. SSE can fold direct loads into other
619 // operations. Based on this, decide what we want to do.
621 if (N->getOpcode() == ISD::FP_ROUND)
622 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
624 MemVT = SrcIsSSE ? SrcVT : DstVT;
626 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
628 // FIXME: optimize the case where the src/dest is a load or store?
629 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(),
631 MemTmp, NULL, 0, MemVT);
632 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
635 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
636 // extload we created. This will cause general havok on the dag because
637 // anything below the conversion could be folded into other existing nodes.
638 // To avoid invalidating 'I', back it up to the convert node.
640 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
642 // Now that we did that, the node is dead. Increment the iterator to the
643 // next node to process, then delete N.
645 CurDAG->DeleteNode(N);
649 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
650 /// when it has created a SelectionDAG for us to codegen.
651 void X86DAGToDAGISel::InstructionSelect() {
652 CurBB = BB; // BB can change as result of isel.
658 // FIXME: This should only happen when not -fast.
659 PreprocessForFPConvert();
661 // Codegen the basic block.
663 DOUT << "===== Instruction selection begins:\n";
668 DOUT << "===== Instruction selection ends:\n";
671 CurDAG->RemoveDeadNodes();
674 void X86DAGToDAGISel::InstructionSelectPostProcessing() {
675 // If we are emitting FP stack code, scan the basic block to determine if this
676 // block defines any FP values. If so, put an FP_REG_KILL instruction before
677 // the terminator of the block.
679 // Note that FP stack instructions are used in all modes for long double,
680 // so we always need to do this check.
681 // Also note that it's possible for an FP stack register to be live across
682 // an instruction that produces multiple basic blocks (SSE CMOV) so we
683 // must check all the generated basic blocks.
685 // Scan all of the machine instructions in these MBBs, checking for FP
686 // stores. (RFP32 and RFP64 will not exist in SSE mode, but RFP80 might.)
687 MachineFunction::iterator MBBI = CurBB;
688 MachineFunction::iterator EndMBB = BB; ++EndMBB;
689 for (; MBBI != EndMBB; ++MBBI) {
690 MachineBasicBlock *MBB = MBBI;
692 // If this block returns, ignore it. We don't want to insert an FP_REG_KILL
693 // before the return.
695 MachineBasicBlock::iterator EndI = MBB->end();
697 if (EndI->getDesc().isReturn())
701 bool ContainsFPCode = false;
702 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
703 !ContainsFPCode && I != E; ++I) {
704 if (I->getNumOperands() != 0 && I->getOperand(0).isRegister()) {
705 const TargetRegisterClass *clas;
706 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
707 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
708 TargetRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
709 ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) ==
710 X86::RFP32RegisterClass ||
711 clas == X86::RFP64RegisterClass ||
712 clas == X86::RFP80RegisterClass)) {
713 ContainsFPCode = true;
719 // Check PHI nodes in successor blocks. These PHI's will be lowered to have
720 // a copy of the input value in this block. In SSE mode, we only care about
722 if (!ContainsFPCode) {
723 // Final check, check LLVM BB's that are successors to the LLVM BB
724 // corresponding to BB for FP PHI nodes.
725 const BasicBlock *LLVMBB = BB->getBasicBlock();
727 for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
728 !ContainsFPCode && SI != E; ++SI) {
729 for (BasicBlock::const_iterator II = SI->begin();
730 (PN = dyn_cast<PHINode>(II)); ++II) {
731 if (PN->getType()==Type::X86_FP80Ty ||
732 (!Subtarget->hasSSE1() && PN->getType()->isFloatingPoint()) ||
733 (!Subtarget->hasSSE2() && PN->getType()==Type::DoubleTy)) {
734 ContainsFPCode = true;
740 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
741 if (ContainsFPCode) {
742 BuildMI(*MBB, MBBI->getFirstTerminator(),
743 TM.getInstrInfo()->get(X86::FP_REG_KILL));
749 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
750 /// the main function.
751 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
752 MachineFrameInfo *MFI) {
753 const TargetInstrInfo *TII = TM.getInstrInfo();
754 if (Subtarget->isTargetCygMing())
755 BuildMI(BB, TII->get(X86::CALLpcrel32)).addExternalSymbol("__main");
758 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
759 // If this is main, emit special code for main.
760 MachineBasicBlock *BB = MF.begin();
761 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
762 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
765 /// MatchAddress - Add the specified node to the specified addressing mode,
766 /// returning true if it cannot be done. This just pattern matches for the
768 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM,
769 bool isRoot, unsigned Depth) {
770 DOUT << "MatchAddress: "; DEBUG(AM.dump());
773 return MatchAddressBase(N, AM, isRoot, Depth);
775 // RIP relative addressing: %rip + 32-bit displacement!
777 if (!AM.ES && AM.JT != -1 && N.getOpcode() == ISD::Constant) {
778 int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
779 if (isInt32(AM.Disp + Val)) {
787 int id = N.getNode()->getNodeId();
788 bool AlreadySelected = isSelected(id); // Already selected, not yet replaced.
790 switch (N.getOpcode()) {
792 case ISD::Constant: {
793 int64_t Val = cast<ConstantSDNode>(N)->getSignExtended();
794 if (isInt32(AM.Disp + Val)) {
801 case X86ISD::Wrapper: {
802 DOUT << "Wrapper: 64bit " << Subtarget->is64Bit();
803 DOUT << " AM "; DEBUG(AM.dump()); DOUT << "\n";
804 DOUT << "AlreadySelected " << AlreadySelected << "\n";
805 bool is64Bit = Subtarget->is64Bit();
806 // Under X86-64 non-small code model, GV (and friends) are 64-bits.
807 // Also, base and index reg must be 0 in order to use rip as base.
808 if (is64Bit && (TM.getCodeModel() != CodeModel::Small ||
809 AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
811 if (AM.GV != 0 || AM.CP != 0 || AM.ES != 0 || AM.JT != -1)
813 // If value is available in a register both base and index components have
814 // been picked, we can't fit the result available in the register in the
815 // addressing mode. Duplicate GlobalAddress or ConstantPool as displacement.
816 if (!AlreadySelected || (AM.Base.Reg.getNode() && AM.IndexReg.getNode())) {
817 SDValue N0 = N.getOperand(0);
818 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
819 GlobalValue *GV = G->getGlobal();
821 AM.Disp += G->getOffset();
822 AM.isRIPRel = TM.getRelocationModel() != Reloc::Static &&
823 Subtarget->isPICStyleRIPRel();
825 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
826 AM.CP = CP->getConstVal();
827 AM.Align = CP->getAlignment();
828 AM.Disp += CP->getOffset();
829 AM.isRIPRel = TM.getRelocationModel() != Reloc::Static &&
830 Subtarget->isPICStyleRIPRel();
832 } else if (ExternalSymbolSDNode *S =dyn_cast<ExternalSymbolSDNode>(N0)) {
833 AM.ES = S->getSymbol();
834 AM.isRIPRel = TM.getRelocationModel() != Reloc::Static &&
835 Subtarget->isPICStyleRIPRel();
837 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
838 AM.JT = J->getIndex();
839 AM.isRIPRel = TM.getRelocationModel() != Reloc::Static &&
840 Subtarget->isPICStyleRIPRel();
847 case ISD::FrameIndex:
848 if (AM.BaseType == X86ISelAddressMode::RegBase
849 && AM.Base.Reg.getNode() == 0) {
850 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
851 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
857 if (AlreadySelected || AM.IndexReg.getNode() != 0
858 || AM.Scale != 1 || AM.isRIPRel)
862 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
863 unsigned Val = CN->getZExtValue();
864 if (Val == 1 || Val == 2 || Val == 3) {
866 SDValue ShVal = N.getNode()->getOperand(0);
868 // Okay, we know that we have a scale by now. However, if the scaled
869 // value is an add of something and a constant, we can fold the
870 // constant into the disp field here.
871 if (ShVal.getNode()->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
872 isa<ConstantSDNode>(ShVal.getNode()->getOperand(1))) {
873 AM.IndexReg = ShVal.getNode()->getOperand(0);
874 ConstantSDNode *AddVal =
875 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
876 uint64_t Disp = AM.Disp + (AddVal->getZExtValue() << Val);
891 // A mul_lohi where we need the low part can be folded as a plain multiply.
892 if (N.getResNo() != 0) break;
895 // X*[3,5,9] -> X+X*[2,4,8]
896 if (!AlreadySelected &&
897 AM.BaseType == X86ISelAddressMode::RegBase &&
898 AM.Base.Reg.getNode() == 0 &&
899 AM.IndexReg.getNode() == 0 &&
902 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
903 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
904 CN->getZExtValue() == 9) {
905 AM.Scale = unsigned(CN->getZExtValue())-1;
907 SDValue MulVal = N.getNode()->getOperand(0);
910 // Okay, we know that we have a scale by now. However, if the scaled
911 // value is an add of something and a constant, we can fold the
912 // constant into the disp field here.
913 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
914 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
915 Reg = MulVal.getNode()->getOperand(0);
916 ConstantSDNode *AddVal =
917 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
918 uint64_t Disp = AM.Disp + AddVal->getZExtValue() *
923 Reg = N.getNode()->getOperand(0);
925 Reg = N.getNode()->getOperand(0);
928 AM.IndexReg = AM.Base.Reg = Reg;
935 if (!AlreadySelected) {
936 X86ISelAddressMode Backup = AM;
937 if (!MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1) &&
938 !MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1))
941 if (!MatchAddress(N.getNode()->getOperand(1), AM, false, Depth+1) &&
942 !MatchAddress(N.getNode()->getOperand(0), AM, false, Depth+1))
949 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
950 if (AlreadySelected) break;
952 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
953 X86ISelAddressMode Backup = AM;
954 // Start with the LHS as an addr mode.
955 if (!MatchAddress(N.getOperand(0), AM, false) &&
956 // Address could not have picked a GV address for the displacement.
958 // On x86-64, the resultant disp must fit in 32-bits.
959 isInt32(AM.Disp + CN->getSignExtended()) &&
960 // Check to see if the LHS & C is zero.
961 CurDAG->MaskedValueIsZero(N.getOperand(0), CN->getAPIntValue())) {
962 AM.Disp += CN->getZExtValue();
970 // Handle "(x << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this
971 // allows us to fold the shift into this addressing mode.
972 if (AlreadySelected) break;
973 SDValue Shift = N.getOperand(0);
974 if (Shift.getOpcode() != ISD::SHL) break;
976 // Scale must not be used already.
977 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
979 // Not when RIP is used as the base.
980 if (AM.isRIPRel) break;
982 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1));
983 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
984 if (!C1 || !C2) break;
986 // Not likely to be profitable if either the AND or SHIFT node has more
987 // than one use (unless all uses are for address computation). Besides,
988 // isel mechanism requires their node ids to be reused.
989 if (!N.hasOneUse() || !Shift.hasOneUse())
992 // Verify that the shift amount is something we can fold.
993 unsigned ShiftCst = C1->getZExtValue();
994 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3)
997 // Get the new AND mask, this folds to a constant.
998 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, N.getValueType(),
999 SDValue(C2, 0), SDValue(C1, 0));
1000 SDValue NewAND = CurDAG->getNode(ISD::AND, N.getValueType(),
1001 Shift.getOperand(0), NewANDMask);
1002 NewANDMask.getNode()->setNodeId(Shift.getNode()->getNodeId());
1003 NewAND.getNode()->setNodeId(N.getNode()->getNodeId());
1005 AM.Scale = 1 << ShiftCst;
1006 AM.IndexReg = NewAND;
1011 return MatchAddressBase(N, AM, isRoot, Depth);
1014 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1015 /// specified addressing mode without any further recursion.
1016 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM,
1017 bool isRoot, unsigned Depth) {
1018 // Is the base register already occupied?
1019 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.getNode()) {
1020 // If so, check to see if the scale index register is set.
1021 if (AM.IndexReg.getNode() == 0 && !AM.isRIPRel) {
1027 // Otherwise, we cannot select it.
1031 // Default, generate it as a register.
1032 AM.BaseType = X86ISelAddressMode::RegBase;
1037 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1038 /// It returns the operands which make up the maximal addressing mode it can
1039 /// match by reference.
1040 bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base,
1041 SDValue &Scale, SDValue &Index,
1043 X86ISelAddressMode AM;
1044 if (MatchAddress(N, AM))
1047 MVT VT = N.getValueType();
1048 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1049 if (!AM.Base.Reg.getNode())
1050 AM.Base.Reg = CurDAG->getRegister(0, VT);
1053 if (!AM.IndexReg.getNode())
1054 AM.IndexReg = CurDAG->getRegister(0, VT);
1056 getAddressOperands(AM, Base, Scale, Index, Disp);
1060 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
1062 static inline bool isZeroNode(SDValue Elt) {
1063 return ((isa<ConstantSDNode>(Elt) &&
1064 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
1065 (isa<ConstantFPSDNode>(Elt) &&
1066 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
1070 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1071 /// match a load whose top elements are either undef or zeros. The load flavor
1072 /// is derived from the type of N, which is either v4f32 or v2f64.
1073 bool X86DAGToDAGISel::SelectScalarSSELoad(SDValue Op, SDValue Pred,
1074 SDValue N, SDValue &Base,
1075 SDValue &Scale, SDValue &Index,
1076 SDValue &Disp, SDValue &InChain,
1077 SDValue &OutChain) {
1078 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1079 InChain = N.getOperand(0).getValue(1);
1080 if (ISD::isNON_EXTLoad(InChain.getNode()) &&
1081 InChain.getValue(0).hasOneUse() &&
1083 CanBeFoldedBy(N.getNode(), Pred.getNode(), Op.getNode())) {
1084 LoadSDNode *LD = cast<LoadSDNode>(InChain);
1085 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
1087 OutChain = LD->getChain();
1092 // Also handle the case where we explicitly require zeros in the top
1093 // elements. This is a vector shuffle from the zero vector.
1094 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1095 // Check to see if the top elements are all zeros (or bitcast of zeros).
1096 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1097 N.getOperand(0).getNode()->hasOneUse() &&
1098 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1099 N.getOperand(0).getOperand(0).hasOneUse()) {
1100 // Okay, this is a zero extending load. Fold it.
1101 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1102 if (!SelectAddr(Op, LD->getBasePtr(), Base, Scale, Index, Disp))
1104 OutChain = LD->getChain();
1105 InChain = SDValue(LD, 1);
1112 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1113 /// mode it matches can be cost effectively emitted as an LEA instruction.
1114 bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N,
1115 SDValue &Base, SDValue &Scale,
1116 SDValue &Index, SDValue &Disp) {
1117 X86ISelAddressMode AM;
1118 if (MatchAddress(N, AM))
1121 MVT VT = N.getValueType();
1122 unsigned Complexity = 0;
1123 if (AM.BaseType == X86ISelAddressMode::RegBase)
1124 if (AM.Base.Reg.getNode())
1127 AM.Base.Reg = CurDAG->getRegister(0, VT);
1128 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1131 if (AM.IndexReg.getNode())
1134 AM.IndexReg = CurDAG->getRegister(0, VT);
1136 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1141 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1142 // to a LEA. This is determined with some expermentation but is by no means
1143 // optimal (especially for code size consideration). LEA is nice because of
1144 // its three-address nature. Tweak the cost function again when we can run
1145 // convertToThreeAddress() at register allocation time.
1146 if (AM.GV || AM.CP || AM.ES || AM.JT != -1) {
1147 // For X86-64, we should always use lea to materialize RIP relative
1149 if (Subtarget->is64Bit())
1155 if (AM.Disp && (AM.Base.Reg.getNode() || AM.IndexReg.getNode()))
1158 if (Complexity > 2) {
1159 getAddressOperands(AM, Base, Scale, Index, Disp);
1165 bool X86DAGToDAGISel::TryFoldLoad(SDValue P, SDValue N,
1166 SDValue &Base, SDValue &Scale,
1167 SDValue &Index, SDValue &Disp) {
1168 if (ISD::isNON_EXTLoad(N.getNode()) &&
1170 CanBeFoldedBy(N.getNode(), P.getNode(), P.getNode()))
1171 return SelectAddr(P, N.getOperand(1), Base, Scale, Index, Disp);
1175 /// getGlobalBaseReg - Return an SDNode that returns the value of
1176 /// the global base register. Output instructions required to
1177 /// initialize the global base register, if necessary.
1179 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1180 assert(!Subtarget->is64Bit() && "X86-64 PIC uses RIP relative addressing");
1182 GlobalBaseReg = TM.getInstrInfo()->initializeGlobalBaseReg(BB->getParent());
1183 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1186 static SDNode *FindCallStartFromCall(SDNode *Node) {
1187 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
1188 assert(Node->getOperand(0).getValueType() == MVT::Other &&
1189 "Node doesn't have a token chain argument!");
1190 return FindCallStartFromCall(Node->getOperand(0).getNode());
1193 /// getTruncateTo8Bit - return an SDNode that implements a subreg based
1194 /// truncate of the specified operand to i8. This can be done with tablegen,
1195 /// except that this code uses MVT::Flag in a tricky way that happens to
1196 /// improve scheduling in some cases.
1197 SDNode *X86DAGToDAGISel::getTruncateTo8Bit(SDValue N0) {
1198 assert(!Subtarget->is64Bit() &&
1199 "getTruncateTo8Bit is only needed on x86-32!");
1200 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1202 // Ensure that the source register has an 8-bit subreg on 32-bit targets
1204 MVT N0VT = N0.getValueType();
1205 switch (N0VT.getSimpleVT()) {
1206 default: assert(0 && "Unknown truncate!");
1208 Opc = X86::MOV16to16_;
1211 Opc = X86::MOV32to32_;
1215 // The use of MVT::Flag here is not strictly accurate, but it helps
1216 // scheduling in some cases.
1217 N0 = SDValue(CurDAG->getTargetNode(Opc, N0VT, MVT::Flag, N0), 0);
1218 return CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1219 MVT::i8, N0, SRIdx, N0.getValue(1));
1223 SDNode *X86DAGToDAGISel::Select(SDValue N) {
1224 SDNode *Node = N.getNode();
1225 MVT NVT = Node->getValueType(0);
1227 unsigned Opcode = Node->getOpcode();
1230 DOUT << std::string(Indent, ' ') << "Selecting: ";
1231 DEBUG(Node->dump(CurDAG));
1236 if (Node->isMachineOpcode()) {
1238 DOUT << std::string(Indent-2, ' ') << "== ";
1239 DEBUG(Node->dump(CurDAG));
1243 return NULL; // Already selected.
1248 case X86ISD::GlobalBaseReg:
1249 return getGlobalBaseReg();
1252 // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
1253 // code and is matched first so to prevent it from being turned into
1255 // In 64-bit small code size mode, use LEA to take advantage of
1256 // RIP-relative addressing.
1257 if (TM.getCodeModel() != CodeModel::Small)
1259 MVT PtrVT = TLI.getPointerTy();
1260 SDValue N0 = N.getOperand(0);
1261 SDValue N1 = N.getOperand(1);
1262 if (N.getNode()->getValueType(0) == PtrVT &&
1263 N0.getOpcode() == X86ISD::Wrapper &&
1264 N1.getOpcode() == ISD::Constant) {
1265 unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getZExtValue();
1267 // TODO: handle ExternalSymbolSDNode.
1268 if (GlobalAddressSDNode *G =
1269 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
1270 C = CurDAG->getTargetGlobalAddress(G->getGlobal(), PtrVT,
1271 G->getOffset() + Offset);
1272 } else if (ConstantPoolSDNode *CP =
1273 dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
1274 C = CurDAG->getTargetConstantPool(CP->getConstVal(), PtrVT,
1276 CP->getOffset()+Offset);
1280 if (Subtarget->is64Bit()) {
1281 SDValue Ops[] = { CurDAG->getRegister(0, PtrVT), getI8Imm(1),
1282 CurDAG->getRegister(0, PtrVT), C };
1283 return CurDAG->SelectNodeTo(N.getNode(), X86::LEA64r,
1286 return CurDAG->SelectNodeTo(N.getNode(), X86::MOV32ri, PtrVT, C);
1290 // Other cases are handled by auto-generated code.
1294 case ISD::SMUL_LOHI:
1295 case ISD::UMUL_LOHI: {
1296 SDValue N0 = Node->getOperand(0);
1297 SDValue N1 = Node->getOperand(1);
1299 bool isSigned = Opcode == ISD::SMUL_LOHI;
1301 switch (NVT.getSimpleVT()) {
1302 default: assert(0 && "Unsupported VT!");
1303 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
1304 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
1305 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
1306 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
1309 switch (NVT.getSimpleVT()) {
1310 default: assert(0 && "Unsupported VT!");
1311 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
1312 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
1313 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
1314 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
1317 unsigned LoReg, HiReg;
1318 switch (NVT.getSimpleVT()) {
1319 default: assert(0 && "Unsupported VT!");
1320 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
1321 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
1322 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
1323 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
1326 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
1327 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1328 // multiplty is commmutative
1330 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
1336 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), LoReg,
1337 N0, SDValue()).getValue(1);
1340 AddToISelQueue(N1.getOperand(0));
1341 AddToISelQueue(Tmp0);
1342 AddToISelQueue(Tmp1);
1343 AddToISelQueue(Tmp2);
1344 AddToISelQueue(Tmp3);
1345 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1347 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
1348 InFlag = SDValue(CNode, 1);
1349 // Update the chain.
1350 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1354 SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
1357 // Copy the low half of the result, if it is needed.
1358 if (!N.getValue(0).use_empty()) {
1359 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1360 LoReg, NVT, InFlag);
1361 InFlag = Result.getValue(2);
1362 ReplaceUses(N.getValue(0), Result);
1364 DOUT << std::string(Indent-2, ' ') << "=> ";
1365 DEBUG(Result.getNode()->dump(CurDAG));
1369 // Copy the high half of the result, if it is needed.
1370 if (!N.getValue(1).use_empty()) {
1372 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1373 // Prevent use of AH in a REX instruction by referencing AX instead.
1374 // Shift it down 8 bits.
1375 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1376 X86::AX, MVT::i16, InFlag);
1377 InFlag = Result.getValue(2);
1378 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
1379 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1380 // Then truncate it down to i8.
1381 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1382 Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1383 MVT::i8, Result, SRIdx), 0);
1385 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1386 HiReg, NVT, InFlag);
1387 InFlag = Result.getValue(2);
1389 ReplaceUses(N.getValue(1), Result);
1391 DOUT << std::string(Indent-2, ' ') << "=> ";
1392 DEBUG(Result.getNode()->dump(CurDAG));
1405 case ISD::UDIVREM: {
1406 SDValue N0 = Node->getOperand(0);
1407 SDValue N1 = Node->getOperand(1);
1409 bool isSigned = Opcode == ISD::SDIVREM;
1411 switch (NVT.getSimpleVT()) {
1412 default: assert(0 && "Unsupported VT!");
1413 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
1414 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
1415 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
1416 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
1419 switch (NVT.getSimpleVT()) {
1420 default: assert(0 && "Unsupported VT!");
1421 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
1422 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
1423 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
1424 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
1427 unsigned LoReg, HiReg;
1428 unsigned ClrOpcode, SExtOpcode;
1429 switch (NVT.getSimpleVT()) {
1430 default: assert(0 && "Unsupported VT!");
1432 LoReg = X86::AL; HiReg = X86::AH;
1434 SExtOpcode = X86::CBW;
1437 LoReg = X86::AX; HiReg = X86::DX;
1438 ClrOpcode = X86::MOV16r0;
1439 SExtOpcode = X86::CWD;
1442 LoReg = X86::EAX; HiReg = X86::EDX;
1443 ClrOpcode = X86::MOV32r0;
1444 SExtOpcode = X86::CDQ;
1447 LoReg = X86::RAX; HiReg = X86::RDX;
1448 ClrOpcode = X86::MOV64r0;
1449 SExtOpcode = X86::CQO;
1453 SDValue Tmp0, Tmp1, Tmp2, Tmp3;
1454 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1457 if (NVT == MVT::i8 && !isSigned) {
1458 // Special case for div8, just use a move with zero extension to AX to
1459 // clear the upper 8 bits (AH).
1460 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Move, Chain;
1461 if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3)) {
1462 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N0.getOperand(0) };
1463 AddToISelQueue(N0.getOperand(0));
1464 AddToISelQueue(Tmp0);
1465 AddToISelQueue(Tmp1);
1466 AddToISelQueue(Tmp2);
1467 AddToISelQueue(Tmp3);
1469 SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, MVT::i16, MVT::Other,
1471 Chain = Move.getValue(1);
1472 ReplaceUses(N0.getValue(1), Chain);
1476 SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, MVT::i16, N0), 0);
1477 Chain = CurDAG->getEntryNode();
1479 Chain = CurDAG->getCopyToReg(Chain, X86::AX, Move, SDValue());
1480 InFlag = Chain.getValue(1);
1484 CurDAG->getCopyToReg(CurDAG->getEntryNode(),
1485 LoReg, N0, SDValue()).getValue(1);
1487 // Sign extend the low part into the high part.
1489 SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
1491 // Zero out the high part, effectively zero extending the input.
1492 SDValue ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, NVT), 0);
1493 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), HiReg,
1494 ClrNode, InFlag).getValue(1);
1499 AddToISelQueue(N1.getOperand(0));
1500 AddToISelQueue(Tmp0);
1501 AddToISelQueue(Tmp1);
1502 AddToISelQueue(Tmp2);
1503 AddToISelQueue(Tmp3);
1504 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, N1.getOperand(0), InFlag };
1506 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Ops, 6);
1507 InFlag = SDValue(CNode, 1);
1508 // Update the chain.
1509 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
1513 SDValue(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
1516 // Copy the division (low) result, if it is needed.
1517 if (!N.getValue(0).use_empty()) {
1518 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1519 LoReg, NVT, InFlag);
1520 InFlag = Result.getValue(2);
1521 ReplaceUses(N.getValue(0), Result);
1523 DOUT << std::string(Indent-2, ' ') << "=> ";
1524 DEBUG(Result.getNode()->dump(CurDAG));
1528 // Copy the remainder (high) result, if it is needed.
1529 if (!N.getValue(1).use_empty()) {
1531 if (HiReg == X86::AH && Subtarget->is64Bit()) {
1532 // Prevent use of AH in a REX instruction by referencing AX instead.
1533 // Shift it down 8 bits.
1534 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1535 X86::AX, MVT::i16, InFlag);
1536 InFlag = Result.getValue(2);
1537 Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, MVT::i16, Result,
1538 CurDAG->getTargetConstant(8, MVT::i8)), 0);
1539 // Then truncate it down to i8.
1540 SDValue SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
1541 Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG,
1542 MVT::i8, Result, SRIdx), 0);
1544 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
1545 HiReg, NVT, InFlag);
1546 InFlag = Result.getValue(2);
1548 ReplaceUses(N.getValue(1), Result);
1550 DOUT << std::string(Indent-2, ' ') << "=> ";
1551 DEBUG(Result.getNode()->dump(CurDAG));
1563 case ISD::SIGN_EXTEND_INREG: {
1564 MVT SVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
1565 if (SVT == MVT::i8 && !Subtarget->is64Bit()) {
1566 SDValue N0 = Node->getOperand(0);
1569 SDValue TruncOp = SDValue(getTruncateTo8Bit(N0), 0);
1571 switch (NVT.getSimpleVT()) {
1572 default: assert(0 && "Unknown sign_extend_inreg!");
1574 Opc = X86::MOVSX16rr8;
1577 Opc = X86::MOVSX32rr8;
1581 SDNode *ResNode = CurDAG->getTargetNode(Opc, NVT, TruncOp);
1584 DOUT << std::string(Indent-2, ' ') << "=> ";
1585 DEBUG(TruncOp.getNode()->dump(CurDAG));
1587 DOUT << std::string(Indent-2, ' ') << "=> ";
1588 DEBUG(ResNode->dump(CurDAG));
1597 case ISD::TRUNCATE: {
1598 if (NVT == MVT::i8 && !Subtarget->is64Bit()) {
1599 SDValue Input = Node->getOperand(0);
1600 AddToISelQueue(Node->getOperand(0));
1601 SDNode *ResNode = getTruncateTo8Bit(Input);
1604 DOUT << std::string(Indent-2, ' ') << "=> ";
1605 DEBUG(ResNode->dump(CurDAG));
1614 case ISD::DECLARE: {
1615 // Handle DECLARE nodes here because the second operand may have been
1616 // wrapped in X86ISD::Wrapper.
1617 SDValue Chain = Node->getOperand(0);
1618 SDValue N1 = Node->getOperand(1);
1619 SDValue N2 = Node->getOperand(2);
1620 if (!isa<FrameIndexSDNode>(N1))
1622 int FI = cast<FrameIndexSDNode>(N1)->getIndex();
1623 if (N2.getOpcode() == ISD::ADD &&
1624 N2.getOperand(0).getOpcode() == X86ISD::GlobalBaseReg)
1625 N2 = N2.getOperand(1);
1626 if (N2.getOpcode() == X86ISD::Wrapper &&
1627 isa<GlobalAddressSDNode>(N2.getOperand(0))) {
1629 cast<GlobalAddressSDNode>(N2.getOperand(0))->getGlobal();
1630 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1631 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1632 AddToISelQueue(Chain);
1633 SDValue Ops[] = { Tmp1, Tmp2, Chain };
1634 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE,
1635 MVT::Other, Ops, 3);
1641 SDNode *ResNode = SelectCode(N);
1644 DOUT << std::string(Indent-2, ' ') << "=> ";
1645 if (ResNode == NULL || ResNode == N.getNode())
1646 DEBUG(N.getNode()->dump(CurDAG));
1648 DEBUG(ResNode->dump(CurDAG));
1656 bool X86DAGToDAGISel::
1657 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1658 std::vector<SDValue> &OutOps) {
1659 SDValue Op0, Op1, Op2, Op3;
1660 switch (ConstraintCode) {
1661 case 'o': // offsetable ??
1662 case 'v': // not offsetable ??
1663 default: return true;
1665 if (!SelectAddr(Op, Op, Op0, Op1, Op2, Op3))
1670 OutOps.push_back(Op0);
1671 OutOps.push_back(Op1);
1672 OutOps.push_back(Op2);
1673 OutOps.push_back(Op3);
1674 AddToISelQueue(Op0);
1675 AddToISelQueue(Op1);
1676 AddToISelQueue(Op2);
1677 AddToISelQueue(Op3);
1681 /// createX86ISelDag - This pass converts a legalized DAG into a
1682 /// X86-specific DAG, ready for instruction scheduling.
1684 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, bool Fast) {
1685 return new X86DAGToDAGISel(TM, Fast);