1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/Type.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
38 #define DEBUG_TYPE "x86-isel"
40 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
42 //===----------------------------------------------------------------------===//
43 // Pattern Matcher Implementation
44 //===----------------------------------------------------------------------===//
47 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
48 /// SDValue's instead of register numbers for the leaves of the matched
50 struct X86ISelAddressMode {
56 // This is really a union, discriminated by BaseType!
64 const GlobalValue *GV;
66 const BlockAddress *BlockAddr;
69 unsigned Align; // CP alignment.
70 unsigned char SymbolFlags; // X86II::MO_*
73 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
74 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
75 JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {
78 bool hasSymbolicDisplacement() const {
79 return GV != nullptr || CP != nullptr || ES != nullptr ||
80 JT != -1 || BlockAddr != nullptr;
83 bool hasBaseOrIndexReg() const {
84 return BaseType == FrameIndexBase ||
85 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
88 /// isRIPRelative - Return true if this addressing mode is already RIP
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
103 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
105 dbgs() << "X86ISelAddressMode " << this << '\n';
106 dbgs() << "Base_Reg ";
107 if (Base_Reg.getNode())
108 Base_Reg.getNode()->dump();
111 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
112 << " Scale" << Scale << '\n'
114 if (IndexReg.getNode())
115 IndexReg.getNode()->dump();
118 dbgs() << " Disp " << Disp << '\n'
135 dbgs() << " JT" << JT << " Align" << Align << '\n';
142 //===--------------------------------------------------------------------===//
143 /// ISel - X86 specific code to select X86 machine instructions for
144 /// SelectionDAG operations.
146 class X86DAGToDAGISel final : public SelectionDAGISel {
147 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
148 /// make the right decision when generating code for different targets.
149 const X86Subtarget *Subtarget;
151 /// OptForSize - If true, selector should try to optimize for code size
152 /// instead of performance.
156 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
157 : SelectionDAGISel(tm, OptLevel),
158 Subtarget(&tm.getSubtarget<X86Subtarget>()),
161 const char *getPassName() const override {
162 return "X86 DAG->DAG Instruction Selection";
165 void EmitFunctionEntryCode() override;
167 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
169 void PreprocessISelDAG() override;
171 inline bool immSext8(SDNode *N) const {
172 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
175 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
176 // sign extended field.
177 inline bool i64immSExt32(SDNode *N) const {
178 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
179 return (int64_t)v == (int32_t)v;
182 // Include the pieces autogenerated from the target description.
183 #include "X86GenDAGISel.inc"
186 SDNode *Select(SDNode *N) override;
187 SDNode *SelectGather(SDNode *N, unsigned Opc);
188 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
189 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
191 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
192 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
193 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
194 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
195 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
197 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
198 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
199 SDValue &Scale, SDValue &Index, SDValue &Disp,
201 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
202 bool SelectLEAAddr(SDValue N, SDValue &Base,
203 SDValue &Scale, SDValue &Index, SDValue &Disp,
205 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
206 SDValue &Scale, SDValue &Index, SDValue &Disp,
208 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
209 SDValue &Scale, SDValue &Index, SDValue &Disp,
211 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
212 SDValue &Base, SDValue &Scale,
213 SDValue &Index, SDValue &Disp,
215 SDValue &NodeWithChain);
217 bool TryFoldLoad(SDNode *P, SDValue N,
218 SDValue &Base, SDValue &Scale,
219 SDValue &Index, SDValue &Disp,
222 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
223 /// inline asm expressions.
224 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
226 std::vector<SDValue> &OutOps) override;
228 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
230 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
231 SDValue &Scale, SDValue &Index,
232 SDValue &Disp, SDValue &Segment) {
233 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
234 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,
235 getTargetLowering()->getPointerTy()) :
237 Scale = getI8Imm(AM.Scale);
239 // These are 32-bit even in 64-bit mode since RIP relative offset
242 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
246 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
247 AM.Align, AM.Disp, AM.SymbolFlags);
249 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
250 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
251 } else if (AM.JT != -1) {
252 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
253 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
254 } else if (AM.BlockAddr)
255 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
258 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
260 if (AM.Segment.getNode())
261 Segment = AM.Segment;
263 Segment = CurDAG->getRegister(0, MVT::i32);
266 /// getI8Imm - Return a target constant with the specified value, of type
268 inline SDValue getI8Imm(unsigned Imm) {
269 return CurDAG->getTargetConstant(Imm, MVT::i8);
272 /// getI32Imm - Return a target constant with the specified value, of type
274 inline SDValue getI32Imm(unsigned Imm) {
275 return CurDAG->getTargetConstant(Imm, MVT::i32);
278 /// getGlobalBaseReg - Return an SDNode that returns the value of
279 /// the global base register. Output instructions required to
280 /// initialize the global base register, if necessary.
282 SDNode *getGlobalBaseReg();
284 /// getTargetMachine - Return a reference to the TargetMachine, casted
285 /// to the target-specific type.
286 const X86TargetMachine &getTargetMachine() const {
287 return static_cast<const X86TargetMachine &>(TM);
290 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
291 /// to the target-specific type.
292 const X86InstrInfo *getInstrInfo() const {
293 return getTargetMachine().getInstrInfo();
300 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
301 if (OptLevel == CodeGenOpt::None) return false;
306 if (N.getOpcode() != ISD::LOAD)
309 // If N is a load, do additional profitability checks.
311 switch (U->getOpcode()) {
324 SDValue Op1 = U->getOperand(1);
326 // If the other operand is a 8-bit immediate we should fold the immediate
327 // instead. This reduces code size.
329 // movl 4(%esp), %eax
333 // addl 4(%esp), %eax
334 // The former is 2 bytes shorter. In case where the increment is 1, then
335 // the saving can be 4 bytes (by using incl %eax).
336 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
337 if (Imm->getAPIntValue().isSignedIntN(8))
340 // If the other operand is a TLS address, we should fold it instead.
343 // leal i@NTPOFF(%eax), %eax
345 // movl $i@NTPOFF, %eax
347 // if the block also has an access to a second TLS address this will save
349 // FIXME: This is probably also true for non-TLS addresses.
350 if (Op1.getOpcode() == X86ISD::Wrapper) {
351 SDValue Val = Op1.getOperand(0);
352 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
362 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
363 /// load's chain operand and move load below the call's chain operand.
364 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
365 SDValue Call, SDValue OrigChain) {
366 SmallVector<SDValue, 8> Ops;
367 SDValue Chain = OrigChain.getOperand(0);
368 if (Chain.getNode() == Load.getNode())
369 Ops.push_back(Load.getOperand(0));
371 assert(Chain.getOpcode() == ISD::TokenFactor &&
372 "Unexpected chain operand");
373 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
374 if (Chain.getOperand(i).getNode() == Load.getNode())
375 Ops.push_back(Load.getOperand(0));
377 Ops.push_back(Chain.getOperand(i));
379 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
381 Ops.push_back(NewChain);
383 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
384 Ops.push_back(OrigChain.getOperand(i));
385 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
386 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
387 Load.getOperand(1), Load.getOperand(2));
389 unsigned NumOps = Call.getNode()->getNumOperands();
391 Ops.push_back(SDValue(Load.getNode(), 1));
392 for (unsigned i = 1, e = NumOps; i != e; ++i)
393 Ops.push_back(Call.getOperand(i));
394 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], NumOps);
397 /// isCalleeLoad - Return true if call address is a load and it can be
398 /// moved below CALLSEQ_START and the chains leading up to the call.
399 /// Return the CALLSEQ_START by reference as a second output.
400 /// In the case of a tail call, there isn't a callseq node between the call
401 /// chain and the load.
402 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
403 // The transformation is somewhat dangerous if the call's chain was glued to
404 // the call. After MoveBelowOrigChain the load is moved between the call and
405 // the chain, this can create a cycle if the load is not folded. So it is
406 // *really* important that we are sure the load will be folded.
407 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
409 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
412 LD->getAddressingMode() != ISD::UNINDEXED ||
413 LD->getExtensionType() != ISD::NON_EXTLOAD)
416 // Now let's find the callseq_start.
417 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
418 if (!Chain.hasOneUse())
420 Chain = Chain.getOperand(0);
423 if (!Chain.getNumOperands())
425 // Since we are not checking for AA here, conservatively abort if the chain
426 // writes to memory. It's not safe to move the callee (a load) across a store.
427 if (isa<MemSDNode>(Chain.getNode()) &&
428 cast<MemSDNode>(Chain.getNode())->writeMem())
430 if (Chain.getOperand(0).getNode() == Callee.getNode())
432 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
433 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
434 Callee.getValue(1).hasOneUse())
439 void X86DAGToDAGISel::PreprocessISelDAG() {
440 // OptForSize is used in pattern predicates that isel is matching.
441 OptForSize = MF->getFunction()->getAttributes().
442 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
444 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
445 E = CurDAG->allnodes_end(); I != E; ) {
446 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
448 if (OptLevel != CodeGenOpt::None &&
449 // Only does this when target favors doesn't favor register indirect
451 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
452 (N->getOpcode() == X86ISD::TC_RETURN &&
453 // Only does this if load can be folded into TC_RETURN.
454 (Subtarget->is64Bit() ||
455 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
456 /// Also try moving call address load from outside callseq_start to just
457 /// before the call to allow it to be folded.
475 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
476 SDValue Chain = N->getOperand(0);
477 SDValue Load = N->getOperand(1);
478 if (!isCalleeLoad(Load, Chain, HasCallSeq))
480 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
485 // Lower fpround and fpextend nodes that target the FP stack to be store and
486 // load to the stack. This is a gross hack. We would like to simply mark
487 // these as being illegal, but when we do that, legalize produces these when
488 // it expands calls, then expands these in the same legalize pass. We would
489 // like dag combine to be able to hack on these between the call expansion
490 // and the node legalization. As such this pass basically does "really
491 // late" legalization of these inline with the X86 isel pass.
492 // FIXME: This should only happen when not compiled with -O0.
493 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
496 MVT SrcVT = N->getOperand(0).getSimpleValueType();
497 MVT DstVT = N->getSimpleValueType(0);
499 // If any of the sources are vectors, no fp stack involved.
500 if (SrcVT.isVector() || DstVT.isVector())
503 // If the source and destination are SSE registers, then this is a legal
504 // conversion that should not be lowered.
505 const X86TargetLowering *X86Lowering =
506 static_cast<const X86TargetLowering *>(getTargetLowering());
507 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
508 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
509 if (SrcIsSSE && DstIsSSE)
512 if (!SrcIsSSE && !DstIsSSE) {
513 // If this is an FPStack extension, it is a noop.
514 if (N->getOpcode() == ISD::FP_EXTEND)
516 // If this is a value-preserving FPStack truncation, it is a noop.
517 if (N->getConstantOperandVal(1))
521 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
522 // FPStack has extload and truncstore. SSE can fold direct loads into other
523 // operations. Based on this, decide what we want to do.
525 if (N->getOpcode() == ISD::FP_ROUND)
526 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
528 MemVT = SrcIsSSE ? SrcVT : DstVT;
530 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
533 // FIXME: optimize the case where the src/dest is a load or store?
534 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
536 MemTmp, MachinePointerInfo(), MemVT,
538 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
539 MachinePointerInfo(),
540 MemVT, false, false, 0);
542 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
543 // extload we created. This will cause general havok on the dag because
544 // anything below the conversion could be folded into other existing nodes.
545 // To avoid invalidating 'I', back it up to the convert node.
547 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
549 // Now that we did that, the node is dead. Increment the iterator to the
550 // next node to process, then delete N.
552 CurDAG->DeleteNode(N);
557 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
558 /// the main function.
559 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
560 MachineFrameInfo *MFI) {
561 const TargetInstrInfo *TII = TM.getInstrInfo();
562 if (Subtarget->isTargetCygMing()) {
564 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
565 BuildMI(BB, DebugLoc(),
566 TII->get(CallOp)).addExternalSymbol("__main");
570 void X86DAGToDAGISel::EmitFunctionEntryCode() {
571 // If this is main, emit special code for main.
572 if (const Function *Fn = MF->getFunction())
573 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
574 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
577 static bool isDispSafeForFrameIndex(int64_t Val) {
578 // On 64-bit platforms, we can run into an issue where a frame index
579 // includes a displacement that, when added to the explicit displacement,
580 // will overflow the displacement field. Assuming that the frame index
581 // displacement fits into a 31-bit integer (which is only slightly more
582 // aggressive than the current fundamental assumption that it fits into
583 // a 32-bit integer), a 31-bit disp should always be safe.
584 return isInt<31>(Val);
587 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
588 X86ISelAddressMode &AM) {
589 int64_t Val = AM.Disp + Offset;
590 CodeModel::Model M = TM.getCodeModel();
591 if (Subtarget->is64Bit()) {
592 if (!X86::isOffsetSuitableForCodeModel(Val, M,
593 AM.hasSymbolicDisplacement()))
595 // In addition to the checks required for a register base, check that
596 // we do not try to use an unsafe Disp with a frame index.
597 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
598 !isDispSafeForFrameIndex(Val))
606 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
607 SDValue Address = N->getOperand(1);
609 // load gs:0 -> GS segment register.
610 // load fs:0 -> FS segment register.
612 // This optimization is valid because the GNU TLS model defines that
613 // gs:0 (or fs:0 on X86-64) contains its own address.
614 // For more information see http://people.redhat.com/drepper/tls.pdf
615 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
616 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
617 Subtarget->isTargetLinux())
618 switch (N->getPointerInfo().getAddrSpace()) {
620 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
623 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
630 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
631 /// into an addressing mode. These wrap things that will resolve down into a
632 /// symbol reference. If no match is possible, this returns true, otherwise it
634 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
635 // If the addressing mode already has a symbol as the displacement, we can
636 // never match another symbol.
637 if (AM.hasSymbolicDisplacement())
640 SDValue N0 = N.getOperand(0);
641 CodeModel::Model M = TM.getCodeModel();
643 // Handle X86-64 rip-relative addresses. We check this before checking direct
644 // folding because RIP is preferable to non-RIP accesses.
645 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
646 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
647 // they cannot be folded into immediate fields.
648 // FIXME: This can be improved for kernel and other models?
649 (M == CodeModel::Small || M == CodeModel::Kernel)) {
650 // Base and index reg must be 0 in order to use %rip as base.
651 if (AM.hasBaseOrIndexReg())
653 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
654 X86ISelAddressMode Backup = AM;
655 AM.GV = G->getGlobal();
656 AM.SymbolFlags = G->getTargetFlags();
657 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
661 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
662 X86ISelAddressMode Backup = AM;
663 AM.CP = CP->getConstVal();
664 AM.Align = CP->getAlignment();
665 AM.SymbolFlags = CP->getTargetFlags();
666 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
670 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
671 AM.ES = S->getSymbol();
672 AM.SymbolFlags = S->getTargetFlags();
673 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
674 AM.JT = J->getIndex();
675 AM.SymbolFlags = J->getTargetFlags();
676 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
677 X86ISelAddressMode Backup = AM;
678 AM.BlockAddr = BA->getBlockAddress();
679 AM.SymbolFlags = BA->getTargetFlags();
680 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
685 llvm_unreachable("Unhandled symbol reference node.");
687 if (N.getOpcode() == X86ISD::WrapperRIP)
688 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
692 // Handle the case when globals fit in our immediate field: This is true for
693 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
694 // mode, this only applies to a non-RIP-relative computation.
695 if (!Subtarget->is64Bit() ||
696 M == CodeModel::Small || M == CodeModel::Kernel) {
697 assert(N.getOpcode() != X86ISD::WrapperRIP &&
698 "RIP-relative addressing already handled");
699 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
700 AM.GV = G->getGlobal();
701 AM.Disp += G->getOffset();
702 AM.SymbolFlags = G->getTargetFlags();
703 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
704 AM.CP = CP->getConstVal();
705 AM.Align = CP->getAlignment();
706 AM.Disp += CP->getOffset();
707 AM.SymbolFlags = CP->getTargetFlags();
708 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
709 AM.ES = S->getSymbol();
710 AM.SymbolFlags = S->getTargetFlags();
711 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
712 AM.JT = J->getIndex();
713 AM.SymbolFlags = J->getTargetFlags();
714 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
715 AM.BlockAddr = BA->getBlockAddress();
716 AM.Disp += BA->getOffset();
717 AM.SymbolFlags = BA->getTargetFlags();
719 llvm_unreachable("Unhandled symbol reference node.");
726 /// MatchAddress - Add the specified node to the specified addressing mode,
727 /// returning true if it cannot be done. This just pattern matches for the
729 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
730 if (MatchAddressRecursively(N, AM, 0))
733 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
734 // a smaller encoding and avoids a scaled-index.
736 AM.BaseType == X86ISelAddressMode::RegBase &&
737 AM.Base_Reg.getNode() == nullptr) {
738 AM.Base_Reg = AM.IndexReg;
742 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
743 // because it has a smaller encoding.
744 // TODO: Which other code models can use this?
745 if (TM.getCodeModel() == CodeModel::Small &&
746 Subtarget->is64Bit() &&
748 AM.BaseType == X86ISelAddressMode::RegBase &&
749 AM.Base_Reg.getNode() == nullptr &&
750 AM.IndexReg.getNode() == nullptr &&
751 AM.SymbolFlags == X86II::MO_NO_FLAG &&
752 AM.hasSymbolicDisplacement())
753 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
758 // Insert a node into the DAG at least before the Pos node's position. This
759 // will reposition the node as needed, and will assign it a node ID that is <=
760 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
761 // IDs! The selection DAG must no longer depend on their uniqueness when this
763 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
764 if (N.getNode()->getNodeId() == -1 ||
765 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
766 DAG.RepositionNode(Pos.getNode(), N.getNode());
767 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
771 // Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
772 // allows us to convert the shift and and into an h-register extract and
773 // a scaled index. Returns false if the simplification is performed.
774 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
776 SDValue Shift, SDValue X,
777 X86ISelAddressMode &AM) {
778 if (Shift.getOpcode() != ISD::SRL ||
779 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
783 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
784 if (ScaleLog <= 0 || ScaleLog >= 4 ||
785 Mask != (0xffu << ScaleLog))
788 MVT VT = N.getSimpleValueType();
790 SDValue Eight = DAG.getConstant(8, MVT::i8);
791 SDValue NewMask = DAG.getConstant(0xff, VT);
792 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
793 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
794 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
795 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
797 // Insert the new nodes into the topological ordering. We must do this in
798 // a valid topological ordering as nothing is going to go back and re-sort
799 // these nodes. We continually insert before 'N' in sequence as this is
800 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
801 // hierarchy left to express.
802 InsertDAGNode(DAG, N, Eight);
803 InsertDAGNode(DAG, N, Srl);
804 InsertDAGNode(DAG, N, NewMask);
805 InsertDAGNode(DAG, N, And);
806 InsertDAGNode(DAG, N, ShlCount);
807 InsertDAGNode(DAG, N, Shl);
808 DAG.ReplaceAllUsesWith(N, Shl);
810 AM.Scale = (1 << ScaleLog);
814 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
815 // allows us to fold the shift into this addressing mode. Returns false if the
816 // transform succeeded.
817 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
819 SDValue Shift, SDValue X,
820 X86ISelAddressMode &AM) {
821 if (Shift.getOpcode() != ISD::SHL ||
822 !isa<ConstantSDNode>(Shift.getOperand(1)))
825 // Not likely to be profitable if either the AND or SHIFT node has more
826 // than one use (unless all uses are for address computation). Besides,
827 // isel mechanism requires their node ids to be reused.
828 if (!N.hasOneUse() || !Shift.hasOneUse())
831 // Verify that the shift amount is something we can fold.
832 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
833 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
836 MVT VT = N.getSimpleValueType();
838 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
839 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
840 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
842 // Insert the new nodes into the topological ordering. We must do this in
843 // a valid topological ordering as nothing is going to go back and re-sort
844 // these nodes. We continually insert before 'N' in sequence as this is
845 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
846 // hierarchy left to express.
847 InsertDAGNode(DAG, N, NewMask);
848 InsertDAGNode(DAG, N, NewAnd);
849 InsertDAGNode(DAG, N, NewShift);
850 DAG.ReplaceAllUsesWith(N, NewShift);
852 AM.Scale = 1 << ShiftAmt;
853 AM.IndexReg = NewAnd;
857 // Implement some heroics to detect shifts of masked values where the mask can
858 // be replaced by extending the shift and undoing that in the addressing mode
859 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
860 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
861 // the addressing mode. This results in code such as:
863 // int f(short *y, int *lookup_table) {
865 // return *y + lookup_table[*y >> 11];
869 // movzwl (%rdi), %eax
872 // addl (%rsi,%rcx,4), %eax
875 // movzwl (%rdi), %eax
879 // addl (%rsi,%rcx), %eax
881 // Note that this function assumes the mask is provided as a mask *after* the
882 // value is shifted. The input chain may or may not match that, but computing
883 // such a mask is trivial.
884 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
886 SDValue Shift, SDValue X,
887 X86ISelAddressMode &AM) {
888 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
889 !isa<ConstantSDNode>(Shift.getOperand(1)))
892 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
893 unsigned MaskLZ = countLeadingZeros(Mask);
894 unsigned MaskTZ = countTrailingZeros(Mask);
896 // The amount of shift we're trying to fit into the addressing mode is taken
897 // from the trailing zeros of the mask.
898 unsigned AMShiftAmt = MaskTZ;
900 // There is nothing we can do here unless the mask is removing some bits.
901 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
902 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
904 // We also need to ensure that mask is a continuous run of bits.
905 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
907 // Scale the leading zero count down based on the actual size of the value.
908 // Also scale it down based on the size of the shift.
909 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
911 // The final check is to ensure that any masked out high bits of X are
912 // already known to be zero. Otherwise, the mask has a semantic impact
913 // other than masking out a couple of low bits. Unfortunately, because of
914 // the mask, zero extensions will be removed from operands in some cases.
915 // This code works extra hard to look through extensions because we can
916 // replace them with zero extensions cheaply if necessary.
917 bool ReplacingAnyExtend = false;
918 if (X.getOpcode() == ISD::ANY_EXTEND) {
919 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
920 X.getOperand(0).getSimpleValueType().getSizeInBits();
921 // Assume that we'll replace the any-extend with a zero-extend, and
922 // narrow the search to the extended value.
924 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
925 ReplacingAnyExtend = true;
927 APInt MaskedHighBits =
928 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
929 APInt KnownZero, KnownOne;
930 DAG.ComputeMaskedBits(X, KnownZero, KnownOne);
931 if (MaskedHighBits != KnownZero) return true;
933 // We've identified a pattern that can be transformed into a single shift
934 // and an addressing mode. Make it so.
935 MVT VT = N.getSimpleValueType();
936 if (ReplacingAnyExtend) {
937 assert(X.getValueType() != VT);
938 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
939 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
940 InsertDAGNode(DAG, N, NewX);
944 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
945 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
946 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
947 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
949 // Insert the new nodes into the topological ordering. We must do this in
950 // a valid topological ordering as nothing is going to go back and re-sort
951 // these nodes. We continually insert before 'N' in sequence as this is
952 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
953 // hierarchy left to express.
954 InsertDAGNode(DAG, N, NewSRLAmt);
955 InsertDAGNode(DAG, N, NewSRL);
956 InsertDAGNode(DAG, N, NewSHLAmt);
957 InsertDAGNode(DAG, N, NewSHL);
958 DAG.ReplaceAllUsesWith(N, NewSHL);
960 AM.Scale = 1 << AMShiftAmt;
961 AM.IndexReg = NewSRL;
965 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
969 dbgs() << "MatchAddress: ";
974 return MatchAddressBase(N, AM);
976 // If this is already a %rip relative address, we can only merge immediates
977 // into it. Instead of handling this in every case, we handle it here.
978 // RIP relative addressing: %rip + 32-bit displacement!
979 if (AM.isRIPRelative()) {
980 // FIXME: JumpTable and ExternalSymbol address currently don't like
981 // displacements. It isn't very important, but this should be fixed for
983 if (!AM.ES && AM.JT != -1) return true;
985 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
986 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
991 switch (N.getOpcode()) {
993 case ISD::Constant: {
994 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
995 if (!FoldOffsetIntoAddress(Val, AM))
1000 case X86ISD::Wrapper:
1001 case X86ISD::WrapperRIP:
1002 if (!MatchWrapper(N, AM))
1007 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1011 case ISD::FrameIndex:
1012 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1013 AM.Base_Reg.getNode() == nullptr &&
1014 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1015 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1016 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1022 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1026 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1027 unsigned Val = CN->getZExtValue();
1028 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1029 // that the base operand remains free for further matching. If
1030 // the base doesn't end up getting used, a post-processing step
1031 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1032 if (Val == 1 || Val == 2 || Val == 3) {
1033 AM.Scale = 1 << Val;
1034 SDValue ShVal = N.getNode()->getOperand(0);
1036 // Okay, we know that we have a scale by now. However, if the scaled
1037 // value is an add of something and a constant, we can fold the
1038 // constant into the disp field here.
1039 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1040 AM.IndexReg = ShVal.getNode()->getOperand(0);
1041 ConstantSDNode *AddVal =
1042 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1043 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1044 if (!FoldOffsetIntoAddress(Disp, AM))
1048 AM.IndexReg = ShVal;
1055 // Scale must not be used already.
1056 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1058 SDValue And = N.getOperand(0);
1059 if (And.getOpcode() != ISD::AND) break;
1060 SDValue X = And.getOperand(0);
1062 // We only handle up to 64-bit values here as those are what matter for
1063 // addressing mode optimizations.
1064 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1066 // The mask used for the transform is expected to be post-shift, but we
1067 // found the shift first so just apply the shift to the mask before passing
1069 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1070 !isa<ConstantSDNode>(And.getOperand(1)))
1072 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1074 // Try to fold the mask and shift into the scale, and return false if we
1076 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1081 case ISD::SMUL_LOHI:
1082 case ISD::UMUL_LOHI:
1083 // A mul_lohi where we need the low part can be folded as a plain multiply.
1084 if (N.getResNo() != 0) break;
1087 case X86ISD::MUL_IMM:
1088 // X*[3,5,9] -> X+X*[2,4,8]
1089 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1090 AM.Base_Reg.getNode() == nullptr &&
1091 AM.IndexReg.getNode() == nullptr) {
1093 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1094 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1095 CN->getZExtValue() == 9) {
1096 AM.Scale = unsigned(CN->getZExtValue())-1;
1098 SDValue MulVal = N.getNode()->getOperand(0);
1101 // Okay, we know that we have a scale by now. However, if the scaled
1102 // value is an add of something and a constant, we can fold the
1103 // constant into the disp field here.
1104 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1105 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1106 Reg = MulVal.getNode()->getOperand(0);
1107 ConstantSDNode *AddVal =
1108 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1109 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1110 if (FoldOffsetIntoAddress(Disp, AM))
1111 Reg = N.getNode()->getOperand(0);
1113 Reg = N.getNode()->getOperand(0);
1116 AM.IndexReg = AM.Base_Reg = Reg;
1123 // Given A-B, if A can be completely folded into the address and
1124 // the index field with the index field unused, use -B as the index.
1125 // This is a win if a has multiple parts that can be folded into
1126 // the address. Also, this saves a mov if the base register has
1127 // other uses, since it avoids a two-address sub instruction, however
1128 // it costs an additional mov if the index register has other uses.
1130 // Add an artificial use to this node so that we can keep track of
1131 // it if it gets CSE'd with a different node.
1132 HandleSDNode Handle(N);
1134 // Test if the LHS of the sub can be folded.
1135 X86ISelAddressMode Backup = AM;
1136 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1140 // Test if the index field is free for use.
1141 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1147 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1148 // If the RHS involves a register with multiple uses, this
1149 // transformation incurs an extra mov, due to the neg instruction
1150 // clobbering its operand.
1151 if (!RHS.getNode()->hasOneUse() ||
1152 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1153 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1154 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1155 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1156 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1158 // If the base is a register with multiple uses, this
1159 // transformation may save a mov.
1160 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1161 AM.Base_Reg.getNode() &&
1162 !AM.Base_Reg.getNode()->hasOneUse()) ||
1163 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1165 // If the folded LHS was interesting, this transformation saves
1166 // address arithmetic.
1167 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1168 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1169 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1171 // If it doesn't look like it may be an overall win, don't do it.
1177 // Ok, the transformation is legal and appears profitable. Go for it.
1178 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1179 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1183 // Insert the new nodes into the topological ordering.
1184 InsertDAGNode(*CurDAG, N, Zero);
1185 InsertDAGNode(*CurDAG, N, Neg);
1190 // Add an artificial use to this node so that we can keep track of
1191 // it if it gets CSE'd with a different node.
1192 HandleSDNode Handle(N);
1194 X86ISelAddressMode Backup = AM;
1195 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1196 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1200 // Try again after commuting the operands.
1201 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1202 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1206 // If we couldn't fold both operands into the address at the same time,
1207 // see if we can just put each operand into a register and fold at least
1209 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1210 !AM.Base_Reg.getNode() &&
1211 !AM.IndexReg.getNode()) {
1212 N = Handle.getValue();
1213 AM.Base_Reg = N.getOperand(0);
1214 AM.IndexReg = N.getOperand(1);
1218 N = Handle.getValue();
1223 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1224 if (CurDAG->isBaseWithConstantOffset(N)) {
1225 X86ISelAddressMode Backup = AM;
1226 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1228 // Start with the LHS as an addr mode.
1229 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1230 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1237 // Perform some heroic transforms on an and of a constant-count shift
1238 // with a constant to enable use of the scaled offset field.
1240 // Scale must not be used already.
1241 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1243 SDValue Shift = N.getOperand(0);
1244 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1245 SDValue X = Shift.getOperand(0);
1247 // We only handle up to 64-bit values here as those are what matter for
1248 // addressing mode optimizations.
1249 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1251 if (!isa<ConstantSDNode>(N.getOperand(1)))
1253 uint64_t Mask = N.getConstantOperandVal(1);
1255 // Try to fold the mask and shift into an extract and scale.
1256 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1259 // Try to fold the mask and shift directly into the scale.
1260 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1263 // Try to swap the mask and shift to place shifts which can be done as
1264 // a scale on the outside of the mask.
1265 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1271 return MatchAddressBase(N, AM);
1274 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1275 /// specified addressing mode without any further recursion.
1276 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1277 // Is the base register already occupied?
1278 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1279 // If so, check to see if the scale index register is set.
1280 if (!AM.IndexReg.getNode()) {
1286 // Otherwise, we cannot select it.
1290 // Default, generate it as a register.
1291 AM.BaseType = X86ISelAddressMode::RegBase;
1296 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1297 /// It returns the operands which make up the maximal addressing mode it can
1298 /// match by reference.
1300 /// Parent is the parent node of the addr operand that is being matched. It
1301 /// is always a load, store, atomic node, or null. It is only null when
1302 /// checking memory operands for inline asm nodes.
1303 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1304 SDValue &Scale, SDValue &Index,
1305 SDValue &Disp, SDValue &Segment) {
1306 X86ISelAddressMode AM;
1309 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1310 // that are not a MemSDNode, and thus don't have proper addrspace info.
1311 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1312 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1313 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1314 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1315 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1316 unsigned AddrSpace =
1317 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1318 // AddrSpace 256 -> GS, 257 -> FS.
1319 if (AddrSpace == 256)
1320 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1321 if (AddrSpace == 257)
1322 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1325 if (MatchAddress(N, AM))
1328 MVT VT = N.getSimpleValueType();
1329 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1330 if (!AM.Base_Reg.getNode())
1331 AM.Base_Reg = CurDAG->getRegister(0, VT);
1334 if (!AM.IndexReg.getNode())
1335 AM.IndexReg = CurDAG->getRegister(0, VT);
1337 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1341 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1342 /// match a load whose top elements are either undef or zeros. The load flavor
1343 /// is derived from the type of N, which is either v4f32 or v2f64.
1346 /// PatternChainNode: this is the matched node that has a chain input and
1348 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1349 SDValue N, SDValue &Base,
1350 SDValue &Scale, SDValue &Index,
1351 SDValue &Disp, SDValue &Segment,
1352 SDValue &PatternNodeWithChain) {
1353 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1354 PatternNodeWithChain = N.getOperand(0);
1355 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1356 PatternNodeWithChain.hasOneUse() &&
1357 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1358 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1359 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1360 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1366 // Also handle the case where we explicitly require zeros in the top
1367 // elements. This is a vector shuffle from the zero vector.
1368 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1369 // Check to see if the top elements are all zeros (or bitcast of zeros).
1370 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1371 N.getOperand(0).getNode()->hasOneUse() &&
1372 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1373 N.getOperand(0).getOperand(0).hasOneUse() &&
1374 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1375 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1376 // Okay, this is a zero extending load. Fold it.
1377 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1378 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1380 PatternNodeWithChain = SDValue(LD, 0);
1387 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1388 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1389 uint64_t ImmVal = CN->getZExtValue();
1390 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1393 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
1397 // In static codegen with small code model, we can get the address of a label
1398 // into a register with 'movl'. TableGen has already made sure we're looking
1399 // at a label of some kind.
1400 assert(N->getOpcode() == X86ISD::Wrapper &&
1401 "Unexpected node type for MOV32ri64");
1402 N = N.getOperand(0);
1404 if (N->getOpcode() != ISD::TargetConstantPool &&
1405 N->getOpcode() != ISD::TargetJumpTable &&
1406 N->getOpcode() != ISD::TargetGlobalAddress &&
1407 N->getOpcode() != ISD::TargetExternalSymbol &&
1408 N->getOpcode() != ISD::TargetBlockAddress)
1412 return TM.getCodeModel() == CodeModel::Small;
1415 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1416 SDValue &Scale, SDValue &Index,
1417 SDValue &Disp, SDValue &Segment) {
1418 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1422 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1423 if (RN && RN->getReg() == 0)
1424 Base = CurDAG->getRegister(0, MVT::i64);
1425 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(N)) {
1426 // Base could already be %rip, particularly in the x32 ABI.
1427 Base = SDValue(CurDAG->getMachineNode(
1428 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1429 CurDAG->getTargetConstant(0, MVT::i64),
1431 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1435 RN = dyn_cast<RegisterSDNode>(Index);
1436 if (RN && RN->getReg() == 0)
1437 Index = CurDAG->getRegister(0, MVT::i64);
1439 assert(Index.getValueType() == MVT::i32 &&
1440 "Expect to be extending 32-bit registers for use in LEA");
1441 Index = SDValue(CurDAG->getMachineNode(
1442 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1443 CurDAG->getTargetConstant(0, MVT::i64),
1445 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
1452 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1453 /// mode it matches can be cost effectively emitted as an LEA instruction.
1454 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1455 SDValue &Base, SDValue &Scale,
1456 SDValue &Index, SDValue &Disp,
1458 X86ISelAddressMode AM;
1460 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1462 SDValue Copy = AM.Segment;
1463 SDValue T = CurDAG->getRegister(0, MVT::i32);
1465 if (MatchAddress(N, AM))
1467 assert (T == AM.Segment);
1470 MVT VT = N.getSimpleValueType();
1471 unsigned Complexity = 0;
1472 if (AM.BaseType == X86ISelAddressMode::RegBase)
1473 if (AM.Base_Reg.getNode())
1476 AM.Base_Reg = CurDAG->getRegister(0, VT);
1477 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1480 if (AM.IndexReg.getNode())
1483 AM.IndexReg = CurDAG->getRegister(0, VT);
1485 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1490 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1491 // to a LEA. This is determined with some expermentation but is by no means
1492 // optimal (especially for code size consideration). LEA is nice because of
1493 // its three-address nature. Tweak the cost function again when we can run
1494 // convertToThreeAddress() at register allocation time.
1495 if (AM.hasSymbolicDisplacement()) {
1496 // For X86-64, we should always use lea to materialize RIP relative
1498 if (Subtarget->is64Bit())
1504 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1507 // If it isn't worth using an LEA, reject it.
1508 if (Complexity <= 2)
1511 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1515 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1516 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1517 SDValue &Scale, SDValue &Index,
1518 SDValue &Disp, SDValue &Segment) {
1519 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1520 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1522 X86ISelAddressMode AM;
1523 AM.GV = GA->getGlobal();
1524 AM.Disp += GA->getOffset();
1525 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1526 AM.SymbolFlags = GA->getTargetFlags();
1528 if (N.getValueType() == MVT::i32) {
1530 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1532 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1535 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1540 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1541 SDValue &Base, SDValue &Scale,
1542 SDValue &Index, SDValue &Disp,
1544 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1545 !IsProfitableToFold(N, P, P) ||
1546 !IsLegalToFold(N, P, P, OptLevel))
1549 return SelectAddr(N.getNode(),
1550 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1553 /// getGlobalBaseReg - Return an SDNode that returns the value of
1554 /// the global base register. Output instructions required to
1555 /// initialize the global base register, if necessary.
1557 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1558 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1559 return CurDAG->getRegister(GlobalBaseReg,
1560 getTargetLowering()->getPointerTy()).getNode();
1563 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1564 SDValue Chain = Node->getOperand(0);
1565 SDValue In1 = Node->getOperand(1);
1566 SDValue In2L = Node->getOperand(2);
1567 SDValue In2H = Node->getOperand(3);
1569 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1570 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1572 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1573 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1574 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1575 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node),
1576 MVT::i32, MVT::i32, MVT::Other, Ops);
1577 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1581 /// Atomic opcode table
1609 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1620 X86::LOCK_ADD64mi32,
1633 X86::LOCK_SUB64mi32,
1685 X86::LOCK_AND64mi32,
1698 X86::LOCK_XOR64mi32,
1703 // Return the target constant operand for atomic-load-op and do simple
1704 // translations, such as from atomic-load-add to lock-sub. The return value is
1705 // one of the following 3 cases:
1706 // + target-constant, the operand could be supported as a target constant.
1707 // + empty, the operand is not needed any more with the new op selected.
1708 // + non-empty, otherwise.
1709 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1711 enum AtomicOpc &Op, MVT NVT,
1713 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1714 int64_t CNVal = CN->getSExtValue();
1715 // Quit if not 32-bit imm.
1716 if ((int32_t)CNVal != CNVal)
1718 // For atomic-load-add, we could do some optimizations.
1720 // Translate to INC/DEC if ADD by 1 or -1.
1721 if ((CNVal == 1) || (CNVal == -1)) {
1722 Op = (CNVal == 1) ? INC : DEC;
1723 // No more constant operand after being translated into INC/DEC.
1726 // Translate to SUB if ADD by negative value.
1732 return CurDAG->getTargetConstant(CNVal, NVT);
1735 // If the value operand is single-used, try to optimize it.
1736 if (Op == ADD && Val.hasOneUse()) {
1737 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1738 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1740 return Val.getOperand(1);
1742 // A special case for i16, which needs truncating as, in most cases, it's
1743 // promoted to i32. We will translate
1744 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1745 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1746 Val.getOperand(0).getOpcode() == ISD::SUB &&
1747 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1749 Val = Val.getOperand(0);
1750 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1758 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1759 if (Node->hasAnyUseOfValue(0))
1764 // Optimize common patterns for __sync_or_and_fetch and similar arith
1765 // operations where the result is not used. This allows us to use the "lock"
1766 // version of the arithmetic instruction.
1767 SDValue Chain = Node->getOperand(0);
1768 SDValue Ptr = Node->getOperand(1);
1769 SDValue Val = Node->getOperand(2);
1770 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1771 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1774 // Which index into the table.
1776 switch (Node->getOpcode()) {
1779 case ISD::ATOMIC_LOAD_OR:
1782 case ISD::ATOMIC_LOAD_AND:
1785 case ISD::ATOMIC_LOAD_XOR:
1788 case ISD::ATOMIC_LOAD_ADD:
1793 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val);
1794 bool isUnOp = !Val.getNode();
1795 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1798 switch (NVT.SimpleTy) {
1799 default: return nullptr;
1802 Opc = AtomicOpcTbl[Op][ConstantI8];
1804 Opc = AtomicOpcTbl[Op][I8];
1808 if (immSext8(Val.getNode()))
1809 Opc = AtomicOpcTbl[Op][SextConstantI16];
1811 Opc = AtomicOpcTbl[Op][ConstantI16];
1813 Opc = AtomicOpcTbl[Op][I16];
1817 if (immSext8(Val.getNode()))
1818 Opc = AtomicOpcTbl[Op][SextConstantI32];
1820 Opc = AtomicOpcTbl[Op][ConstantI32];
1822 Opc = AtomicOpcTbl[Op][I32];
1825 Opc = AtomicOpcTbl[Op][I64];
1827 if (immSext8(Val.getNode()))
1828 Opc = AtomicOpcTbl[Op][SextConstantI64];
1829 else if (i64immSExt32(Val.getNode()))
1830 Opc = AtomicOpcTbl[Op][ConstantI64];
1835 assert(Opc != 0 && "Invalid arith lock transform!");
1838 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1840 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1841 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1843 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1844 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1846 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1847 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1849 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1850 SDValue RetVals[] = { Undef, Ret };
1851 return CurDAG->getMergeValues(RetVals, dl).getNode();
1854 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1855 /// any uses which require the SF or OF bits to be accurate.
1856 static bool HasNoSignedComparisonUses(SDNode *N) {
1857 // Examine each user of the node.
1858 for (SDNode::use_iterator UI = N->use_begin(),
1859 UE = N->use_end(); UI != UE; ++UI) {
1860 // Only examine CopyToReg uses.
1861 if (UI->getOpcode() != ISD::CopyToReg)
1863 // Only examine CopyToReg uses that copy to EFLAGS.
1864 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1867 // Examine each user of the CopyToReg use.
1868 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1869 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1870 // Only examine the Flag result.
1871 if (FlagUI.getUse().getResNo() != 1) continue;
1872 // Anything unusual: assume conservatively.
1873 if (!FlagUI->isMachineOpcode()) return false;
1874 // Examine the opcode of the user.
1875 switch (FlagUI->getMachineOpcode()) {
1876 // These comparisons don't treat the most significant bit specially.
1877 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1878 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1879 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1880 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1881 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1882 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1883 case X86::CMOVA16rr: case X86::CMOVA16rm:
1884 case X86::CMOVA32rr: case X86::CMOVA32rm:
1885 case X86::CMOVA64rr: case X86::CMOVA64rm:
1886 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1887 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1888 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1889 case X86::CMOVB16rr: case X86::CMOVB16rm:
1890 case X86::CMOVB32rr: case X86::CMOVB32rm:
1891 case X86::CMOVB64rr: case X86::CMOVB64rm:
1892 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1893 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1894 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1895 case X86::CMOVE16rr: case X86::CMOVE16rm:
1896 case X86::CMOVE32rr: case X86::CMOVE32rm:
1897 case X86::CMOVE64rr: case X86::CMOVE64rm:
1898 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1899 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1900 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1901 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1902 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1903 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1904 case X86::CMOVP16rr: case X86::CMOVP16rm:
1905 case X86::CMOVP32rr: case X86::CMOVP32rm:
1906 case X86::CMOVP64rr: case X86::CMOVP64rm:
1908 // Anything else: assume conservatively.
1909 default: return false;
1916 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1917 /// is suitable for doing the {load; increment or decrement; store} to modify
1919 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
1920 SDValue StoredVal, SelectionDAG *CurDAG,
1921 LoadSDNode* &LoadNode, SDValue &InputChain) {
1923 // is the value stored the result of a DEC or INC?
1924 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
1926 // is the stored value result 0 of the load?
1927 if (StoredVal.getResNo() != 0) return false;
1929 // are there other uses of the loaded value than the inc or dec?
1930 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
1932 // is the store non-extending and non-indexed?
1933 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
1936 SDValue Load = StoredVal->getOperand(0);
1937 // Is the stored value a non-extending and non-indexed load?
1938 if (!ISD::isNormalLoad(Load.getNode())) return false;
1940 // Return LoadNode by reference.
1941 LoadNode = cast<LoadSDNode>(Load);
1942 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
1943 EVT LdVT = LoadNode->getMemoryVT();
1944 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
1948 // Is store the only read of the loaded value?
1949 if (!Load.hasOneUse())
1952 // Is the address of the store the same as the load?
1953 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
1954 LoadNode->getOffset() != StoreNode->getOffset())
1957 // Check if the chain is produced by the load or is a TokenFactor with
1958 // the load output chain as an operand. Return InputChain by reference.
1959 SDValue Chain = StoreNode->getChain();
1961 bool ChainCheck = false;
1962 if (Chain == Load.getValue(1)) {
1964 InputChain = LoadNode->getChain();
1965 } else if (Chain.getOpcode() == ISD::TokenFactor) {
1966 SmallVector<SDValue, 4> ChainOps;
1967 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
1968 SDValue Op = Chain.getOperand(i);
1969 if (Op == Load.getValue(1)) {
1974 // Make sure using Op as part of the chain would not cause a cycle here.
1975 // In theory, we could check whether the chain node is a predecessor of
1976 // the load. But that can be very expensive. Instead visit the uses and
1977 // make sure they all have smaller node id than the load.
1978 int LoadId = LoadNode->getNodeId();
1979 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
1980 UE = UI->use_end(); UI != UE; ++UI) {
1981 if (UI.getUse().getResNo() != 0)
1983 if (UI->getNodeId() > LoadId)
1987 ChainOps.push_back(Op);
1991 // Make a new TokenFactor with all the other input chains except
1993 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
1994 MVT::Other, ChainOps);
2002 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2003 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2004 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2005 if (Opc == X86ISD::DEC) {
2006 if (LdVT == MVT::i64) return X86::DEC64m;
2007 if (LdVT == MVT::i32) return X86::DEC32m;
2008 if (LdVT == MVT::i16) return X86::DEC16m;
2009 if (LdVT == MVT::i8) return X86::DEC8m;
2011 assert(Opc == X86ISD::INC && "unrecognized opcode");
2012 if (LdVT == MVT::i64) return X86::INC64m;
2013 if (LdVT == MVT::i32) return X86::INC32m;
2014 if (LdVT == MVT::i16) return X86::INC16m;
2015 if (LdVT == MVT::i8) return X86::INC8m;
2017 llvm_unreachable("unrecognized size for LdVT");
2020 /// SelectGather - Customized ISel for GATHER operations.
2022 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2023 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2024 SDValue Chain = Node->getOperand(0);
2025 SDValue VSrc = Node->getOperand(2);
2026 SDValue Base = Node->getOperand(3);
2027 SDValue VIdx = Node->getOperand(4);
2028 SDValue VMask = Node->getOperand(5);
2029 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2033 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2036 // Memory Operands: Base, Scale, Index, Disp, Segment
2037 SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);
2038 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2039 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,
2040 Disp, Segment, VMask, Chain};
2041 SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);
2042 // Node has 2 outputs: VDst and MVT::Other.
2043 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2044 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2046 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2047 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2051 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2052 MVT NVT = Node->getSimpleValueType(0);
2054 unsigned Opcode = Node->getOpcode();
2057 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2059 if (Node->isMachineOpcode()) {
2060 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2061 Node->setNodeId(-1);
2062 return nullptr; // Already selected.
2067 case ISD::INTRINSIC_W_CHAIN: {
2068 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2071 case Intrinsic::x86_avx2_gather_d_pd:
2072 case Intrinsic::x86_avx2_gather_d_pd_256:
2073 case Intrinsic::x86_avx2_gather_q_pd:
2074 case Intrinsic::x86_avx2_gather_q_pd_256:
2075 case Intrinsic::x86_avx2_gather_d_ps:
2076 case Intrinsic::x86_avx2_gather_d_ps_256:
2077 case Intrinsic::x86_avx2_gather_q_ps:
2078 case Intrinsic::x86_avx2_gather_q_ps_256:
2079 case Intrinsic::x86_avx2_gather_d_q:
2080 case Intrinsic::x86_avx2_gather_d_q_256:
2081 case Intrinsic::x86_avx2_gather_q_q:
2082 case Intrinsic::x86_avx2_gather_q_q_256:
2083 case Intrinsic::x86_avx2_gather_d_d:
2084 case Intrinsic::x86_avx2_gather_d_d_256:
2085 case Intrinsic::x86_avx2_gather_q_d:
2086 case Intrinsic::x86_avx2_gather_q_d_256: {
2087 if (!Subtarget->hasAVX2())
2091 default: llvm_unreachable("Impossible intrinsic");
2092 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2093 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2094 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2095 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2096 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2097 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2098 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2099 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2100 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2101 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2102 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2103 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2104 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2105 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2106 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2107 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2109 SDNode *RetVal = SelectGather(Node, Opc);
2111 // We already called ReplaceUses inside SelectGather.
2118 case X86ISD::GlobalBaseReg:
2119 return getGlobalBaseReg();
2122 case X86ISD::ATOMOR64_DAG:
2123 case X86ISD::ATOMXOR64_DAG:
2124 case X86ISD::ATOMADD64_DAG:
2125 case X86ISD::ATOMSUB64_DAG:
2126 case X86ISD::ATOMNAND64_DAG:
2127 case X86ISD::ATOMAND64_DAG:
2128 case X86ISD::ATOMMAX64_DAG:
2129 case X86ISD::ATOMMIN64_DAG:
2130 case X86ISD::ATOMUMAX64_DAG:
2131 case X86ISD::ATOMUMIN64_DAG:
2132 case X86ISD::ATOMSWAP64_DAG: {
2135 default: llvm_unreachable("Impossible opcode");
2136 case X86ISD::ATOMOR64_DAG: Opc = X86::ATOMOR6432; break;
2137 case X86ISD::ATOMXOR64_DAG: Opc = X86::ATOMXOR6432; break;
2138 case X86ISD::ATOMADD64_DAG: Opc = X86::ATOMADD6432; break;
2139 case X86ISD::ATOMSUB64_DAG: Opc = X86::ATOMSUB6432; break;
2140 case X86ISD::ATOMNAND64_DAG: Opc = X86::ATOMNAND6432; break;
2141 case X86ISD::ATOMAND64_DAG: Opc = X86::ATOMAND6432; break;
2142 case X86ISD::ATOMMAX64_DAG: Opc = X86::ATOMMAX6432; break;
2143 case X86ISD::ATOMMIN64_DAG: Opc = X86::ATOMMIN6432; break;
2144 case X86ISD::ATOMUMAX64_DAG: Opc = X86::ATOMUMAX6432; break;
2145 case X86ISD::ATOMUMIN64_DAG: Opc = X86::ATOMUMIN6432; break;
2146 case X86ISD::ATOMSWAP64_DAG: Opc = X86::ATOMSWAP6432; break;
2148 SDNode *RetVal = SelectAtomic64(Node, Opc);
2154 case ISD::ATOMIC_LOAD_XOR:
2155 case ISD::ATOMIC_LOAD_AND:
2156 case ISD::ATOMIC_LOAD_OR:
2157 case ISD::ATOMIC_LOAD_ADD: {
2158 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2166 // For operations of the form (x << C1) op C2, check if we can use a smaller
2167 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2168 SDValue N0 = Node->getOperand(0);
2169 SDValue N1 = Node->getOperand(1);
2171 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2174 // i8 is unshrinkable, i16 should be promoted to i32.
2175 if (NVT != MVT::i32 && NVT != MVT::i64)
2178 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2179 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2180 if (!Cst || !ShlCst)
2183 int64_t Val = Cst->getSExtValue();
2184 uint64_t ShlVal = ShlCst->getZExtValue();
2186 // Make sure that we don't change the operation by removing bits.
2187 // This only matters for OR and XOR, AND is unaffected.
2188 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2189 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2195 // Check the minimum bitwidth for the new constant.
2196 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2197 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2198 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2199 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2201 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2204 // Bail if there is no smaller encoding.
2208 switch (NVT.SimpleTy) {
2209 default: llvm_unreachable("Unsupported VT!");
2211 assert(CstVT == MVT::i8);
2212 ShlOp = X86::SHL32ri;
2215 default: llvm_unreachable("Impossible opcode");
2216 case ISD::AND: Op = X86::AND32ri8; break;
2217 case ISD::OR: Op = X86::OR32ri8; break;
2218 case ISD::XOR: Op = X86::XOR32ri8; break;
2222 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2223 ShlOp = X86::SHL64ri;
2226 default: llvm_unreachable("Impossible opcode");
2227 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2228 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2229 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2234 // Emit the smaller op and the shift.
2235 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
2236 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2237 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2240 case X86ISD::UMUL: {
2241 SDValue N0 = Node->getOperand(0);
2242 SDValue N1 = Node->getOperand(1);
2245 switch (NVT.SimpleTy) {
2246 default: llvm_unreachable("Unsupported VT!");
2247 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2248 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2249 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2250 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2253 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2254 N0, SDValue()).getValue(1);
2256 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2257 SDValue Ops[] = {N1, InFlag};
2258 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2260 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2261 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2262 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2266 case ISD::SMUL_LOHI:
2267 case ISD::UMUL_LOHI: {
2268 SDValue N0 = Node->getOperand(0);
2269 SDValue N1 = Node->getOperand(1);
2271 bool isSigned = Opcode == ISD::SMUL_LOHI;
2272 bool hasBMI2 = Subtarget->hasBMI2();
2274 switch (NVT.SimpleTy) {
2275 default: llvm_unreachable("Unsupported VT!");
2276 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2277 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2278 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2279 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2280 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2281 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2284 switch (NVT.SimpleTy) {
2285 default: llvm_unreachable("Unsupported VT!");
2286 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2287 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2288 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2289 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2293 unsigned SrcReg, LoReg, HiReg;
2295 default: llvm_unreachable("Unknown MUL opcode!");
2298 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2302 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2306 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2310 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2313 SrcReg = X86::EDX; LoReg = HiReg = 0;
2316 SrcReg = X86::RDX; LoReg = HiReg = 0;
2320 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2321 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2322 // Multiply is commmutative.
2324 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2329 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2330 N0, SDValue()).getValue(1);
2331 SDValue ResHi, ResLo;
2335 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2337 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2338 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2339 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2340 ResHi = SDValue(CNode, 0);
2341 ResLo = SDValue(CNode, 1);
2342 Chain = SDValue(CNode, 2);
2343 InFlag = SDValue(CNode, 3);
2345 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2346 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2347 Chain = SDValue(CNode, 0);
2348 InFlag = SDValue(CNode, 1);
2351 // Update the chain.
2352 ReplaceUses(N1.getValue(1), Chain);
2354 SDValue Ops[] = { N1, InFlag };
2355 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2356 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2357 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2358 ResHi = SDValue(CNode, 0);
2359 ResLo = SDValue(CNode, 1);
2360 InFlag = SDValue(CNode, 2);
2362 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2363 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2364 InFlag = SDValue(CNode, 0);
2368 // Prevent use of AH in a REX instruction by referencing AX instead.
2369 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2370 !SDValue(Node, 1).use_empty()) {
2371 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2372 X86::AX, MVT::i16, InFlag);
2373 InFlag = Result.getValue(2);
2374 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2376 if (!SDValue(Node, 0).use_empty())
2377 ReplaceUses(SDValue(Node, 1),
2378 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2380 // Shift AX down 8 bits.
2381 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2383 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2384 // Then truncate it down to i8.
2385 ReplaceUses(SDValue(Node, 1),
2386 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2388 // Copy the low half of the result, if it is needed.
2389 if (!SDValue(Node, 0).use_empty()) {
2390 if (!ResLo.getNode()) {
2391 assert(LoReg && "Register for low half is not defined!");
2392 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2394 InFlag = ResLo.getValue(2);
2396 ReplaceUses(SDValue(Node, 0), ResLo);
2397 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2399 // Copy the high half of the result, if it is needed.
2400 if (!SDValue(Node, 1).use_empty()) {
2401 if (!ResHi.getNode()) {
2402 assert(HiReg && "Register for high half is not defined!");
2403 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2405 InFlag = ResHi.getValue(2);
2407 ReplaceUses(SDValue(Node, 1), ResHi);
2408 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2415 case ISD::UDIVREM: {
2416 SDValue N0 = Node->getOperand(0);
2417 SDValue N1 = Node->getOperand(1);
2419 bool isSigned = Opcode == ISD::SDIVREM;
2421 switch (NVT.SimpleTy) {
2422 default: llvm_unreachable("Unsupported VT!");
2423 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2424 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2425 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2426 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2429 switch (NVT.SimpleTy) {
2430 default: llvm_unreachable("Unsupported VT!");
2431 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2432 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2433 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2434 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2438 unsigned LoReg, HiReg, ClrReg;
2439 unsigned SExtOpcode;
2440 switch (NVT.SimpleTy) {
2441 default: llvm_unreachable("Unsupported VT!");
2443 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2444 SExtOpcode = X86::CBW;
2447 LoReg = X86::AX; HiReg = X86::DX;
2449 SExtOpcode = X86::CWD;
2452 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2453 SExtOpcode = X86::CDQ;
2456 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2457 SExtOpcode = X86::CQO;
2461 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2462 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2463 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2466 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2467 // Special case for div8, just use a move with zero extension to AX to
2468 // clear the upper 8 bits (AH).
2469 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2470 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2471 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2473 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2474 MVT::Other, Ops), 0);
2475 Chain = Move.getValue(1);
2476 ReplaceUses(N0.getValue(1), Chain);
2479 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2480 Chain = CurDAG->getEntryNode();
2482 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2483 InFlag = Chain.getValue(1);
2486 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2487 LoReg, N0, SDValue()).getValue(1);
2488 if (isSigned && !signBitIsZero) {
2489 // Sign extend the low part into the high part.
2491 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2493 // Zero out the high part, effectively zero extending the input.
2494 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2495 switch (NVT.SimpleTy) {
2498 SDValue(CurDAG->getMachineNode(
2499 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2500 CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),
2507 SDValue(CurDAG->getMachineNode(
2508 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2509 CurDAG->getTargetConstant(0, MVT::i64), ClrNode,
2510 CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),
2514 llvm_unreachable("Unexpected division source");
2517 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2518 ClrNode, InFlag).getValue(1);
2523 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2526 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2527 InFlag = SDValue(CNode, 1);
2528 // Update the chain.
2529 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2532 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2535 // Prevent use of AH in a REX instruction by referencing AX instead.
2536 // Shift it down 8 bits.
2538 // The current assumption of the register allocator is that isel
2539 // won't generate explicit references to the GPR8_NOREX registers. If
2540 // the allocator and/or the backend get enhanced to be more robust in
2541 // that regard, this can be, and should be, removed.
2542 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2543 !SDValue(Node, 1).use_empty()) {
2544 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2545 X86::AX, MVT::i16, InFlag);
2546 InFlag = Result.getValue(2);
2548 // If we also need AL (the quotient), get it by extracting a subreg from
2549 // Result. The fast register allocator does not like multiple CopyFromReg
2550 // nodes using aliasing registers.
2551 if (!SDValue(Node, 0).use_empty())
2552 ReplaceUses(SDValue(Node, 0),
2553 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2555 // Shift AX right by 8 bits instead of using AH.
2556 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2558 CurDAG->getTargetConstant(8, MVT::i8)),
2560 ReplaceUses(SDValue(Node, 1),
2561 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2563 // Copy the division (low) result, if it is needed.
2564 if (!SDValue(Node, 0).use_empty()) {
2565 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2566 LoReg, NVT, InFlag);
2567 InFlag = Result.getValue(2);
2568 ReplaceUses(SDValue(Node, 0), Result);
2569 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2571 // Copy the remainder (high) result, if it is needed.
2572 if (!SDValue(Node, 1).use_empty()) {
2573 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2574 HiReg, NVT, InFlag);
2575 InFlag = Result.getValue(2);
2576 ReplaceUses(SDValue(Node, 1), Result);
2577 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2584 // Sometimes a SUB is used to perform comparison.
2585 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2586 // This node is not a CMP.
2588 SDValue N0 = Node->getOperand(0);
2589 SDValue N1 = Node->getOperand(1);
2591 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2592 // use a smaller encoding.
2593 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2594 HasNoSignedComparisonUses(Node))
2595 // Look past the truncate if CMP is the only use of it.
2596 N0 = N0.getOperand(0);
2597 if ((N0.getNode()->getOpcode() == ISD::AND ||
2598 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2599 N0.getNode()->hasOneUse() &&
2600 N0.getValueType() != MVT::i8 &&
2601 X86::isZeroNode(N1)) {
2602 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2605 // For example, convert "testl %eax, $8" to "testb %al, $8"
2606 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2607 (!(C->getZExtValue() & 0x80) ||
2608 HasNoSignedComparisonUses(Node))) {
2609 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2610 SDValue Reg = N0.getNode()->getOperand(0);
2612 // On x86-32, only the ABCD registers have 8-bit subregisters.
2613 if (!Subtarget->is64Bit()) {
2614 const TargetRegisterClass *TRC;
2615 switch (N0.getSimpleValueType().SimpleTy) {
2616 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2617 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2618 default: llvm_unreachable("Unsupported TEST operand type!");
2620 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2621 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2622 Reg.getValueType(), Reg, RC), 0);
2625 // Extract the l-register.
2626 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2630 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2632 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2633 // one, do not call ReplaceAllUsesWith.
2634 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2635 SDValue(NewNode, 0));
2639 // For example, "testl %eax, $2048" to "testb %ah, $8".
2640 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2641 (!(C->getZExtValue() & 0x8000) ||
2642 HasNoSignedComparisonUses(Node))) {
2643 // Shift the immediate right by 8 bits.
2644 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2646 SDValue Reg = N0.getNode()->getOperand(0);
2648 // Put the value in an ABCD register.
2649 const TargetRegisterClass *TRC;
2650 switch (N0.getSimpleValueType().SimpleTy) {
2651 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2652 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2653 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2654 default: llvm_unreachable("Unsupported TEST operand type!");
2656 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2657 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2658 Reg.getValueType(), Reg, RC), 0);
2660 // Extract the h-register.
2661 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2664 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2665 // target GR8_NOREX registers, so make sure the register class is
2667 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2668 MVT::i32, Subreg, ShiftedImm);
2669 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2670 // one, do not call ReplaceAllUsesWith.
2671 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2672 SDValue(NewNode, 0));
2676 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2677 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2678 N0.getValueType() != MVT::i16 &&
2679 (!(C->getZExtValue() & 0x8000) ||
2680 HasNoSignedComparisonUses(Node))) {
2681 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2682 SDValue Reg = N0.getNode()->getOperand(0);
2684 // Extract the 16-bit subregister.
2685 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2689 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2691 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2692 // one, do not call ReplaceAllUsesWith.
2693 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2694 SDValue(NewNode, 0));
2698 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2699 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2700 N0.getValueType() == MVT::i64 &&
2701 (!(C->getZExtValue() & 0x80000000) ||
2702 HasNoSignedComparisonUses(Node))) {
2703 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2704 SDValue Reg = N0.getNode()->getOperand(0);
2706 // Extract the 32-bit subregister.
2707 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2711 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2713 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2714 // one, do not call ReplaceAllUsesWith.
2715 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2716 SDValue(NewNode, 0));
2723 // Change a chain of {load; incr or dec; store} of the same value into
2724 // a simple increment or decrement through memory of that value, if the
2725 // uses of the modified value and its address are suitable.
2726 // The DEC64m tablegen pattern is currently not able to match the case where
2727 // the EFLAGS on the original DEC are used. (This also applies to
2728 // {INC,DEC}X{64,32,16,8}.)
2729 // We'll need to improve tablegen to allow flags to be transferred from a
2730 // node in the pattern to the result node. probably with a new keyword
2731 // for example, we have this
2732 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2733 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2734 // (implicit EFLAGS)]>;
2735 // but maybe need something like this
2736 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2737 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2738 // (transferrable EFLAGS)]>;
2740 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2741 SDValue StoredVal = StoreNode->getOperand(1);
2742 unsigned Opc = StoredVal->getOpcode();
2744 LoadSDNode *LoadNode = nullptr;
2746 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2747 LoadNode, InputChain))
2750 SDValue Base, Scale, Index, Disp, Segment;
2751 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2752 Base, Scale, Index, Disp, Segment))
2755 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2756 MemOp[0] = StoreNode->getMemOperand();
2757 MemOp[1] = LoadNode->getMemOperand();
2758 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2759 EVT LdVT = LoadNode->getMemoryVT();
2760 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2761 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2763 MVT::i32, MVT::Other, Ops);
2764 Result->setMemRefs(MemOp, MemOp + 2);
2766 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2767 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2773 SDNode *ResNode = SelectCode(Node);
2775 DEBUG(dbgs() << "=> ";
2776 if (ResNode == nullptr || ResNode == Node)
2779 ResNode->dump(CurDAG);
2785 bool X86DAGToDAGISel::
2786 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2787 std::vector<SDValue> &OutOps) {
2788 SDValue Op0, Op1, Op2, Op3, Op4;
2789 switch (ConstraintCode) {
2790 case 'o': // offsetable ??
2791 case 'v': // not offsetable ??
2792 default: return true;
2794 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2799 OutOps.push_back(Op0);
2800 OutOps.push_back(Op1);
2801 OutOps.push_back(Op2);
2802 OutOps.push_back(Op3);
2803 OutOps.push_back(Op4);
2807 /// createX86ISelDag - This pass converts a legalized DAG into a
2808 /// X86-specific DAG, ready for instruction scheduling.
2810 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2811 CodeGenOpt::Level OptLevel) {
2812 return new X86DAGToDAGISel(TM, OptLevel);