1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86RegisterInfo.h"
18 #include "X86Subtarget.h"
19 #include "X86ISelLowering.h"
20 #include "llvm/GlobalValue.h"
21 #include "llvm/Instructions.h"
22 #include "llvm/Support/CFG.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/ADT/Statistic.h"
34 //===----------------------------------------------------------------------===//
35 // Pattern Matcher Implementation
36 //===----------------------------------------------------------------------===//
39 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
40 /// SDOperand's instead of register numbers for the leaves of the matched
42 struct X86ISelAddressMode {
49 struct { // This is really a union, discriminated by BaseType!
60 : BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0) {
67 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
69 //===--------------------------------------------------------------------===//
70 /// ISel - X86 specific code to select X86 machine instructions for
71 /// SelectionDAG operations.
73 class X86DAGToDAGISel : public SelectionDAGISel {
74 /// ContainsFPCode - Every instruction we select that uses or defines a FP
75 /// register should set this to true.
78 /// X86Lowering - This object fully describes how to lower LLVM code to an
79 /// X86-specific SelectionDAG.
80 X86TargetLowering X86Lowering;
82 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
83 /// make the right decision when generating code for different targets.
84 const X86Subtarget *Subtarget;
86 X86DAGToDAGISel(TargetMachine &TM)
87 : SelectionDAGISel(X86Lowering), X86Lowering(TM) {
88 Subtarget = &TM.getSubtarget<X86Subtarget>();
91 virtual const char *getPassName() const {
92 return "X86 DAG->DAG Instruction Selection";
95 /// InstructionSelectBasicBlock - This callback is invoked by
96 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
97 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
99 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
101 // Include the pieces autogenerated from the target description.
102 #include "X86GenDAGISel.inc"
105 SDOperand Select(SDOperand N);
107 bool MatchAddress(SDOperand N, X86ISelAddressMode &AM);
108 bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
109 SDOperand &Index, SDOperand &Disp);
110 bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
111 SDOperand &Index, SDOperand &Disp);
112 bool TryFoldLoad(SDOperand N, SDOperand &Base, SDOperand &Scale,
113 SDOperand &Index, SDOperand &Disp);
115 inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
116 SDOperand &Scale, SDOperand &Index,
118 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
119 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
120 Scale = getI8Imm(AM.Scale);
122 Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
123 : getI32Imm(AM.Disp);
126 /// getI8Imm - Return a target constant with the specified value, of type
128 inline SDOperand getI8Imm(unsigned Imm) {
129 return CurDAG->getTargetConstant(Imm, MVT::i8);
132 /// getI16Imm - Return a target constant with the specified value, of type
134 inline SDOperand getI16Imm(unsigned Imm) {
135 return CurDAG->getTargetConstant(Imm, MVT::i16);
138 /// getI32Imm - Return a target constant with the specified value, of type
140 inline SDOperand getI32Imm(unsigned Imm) {
141 return CurDAG->getTargetConstant(Imm, MVT::i32);
146 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
147 /// when it has created a SelectionDAG for us to codegen.
148 void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
150 MachineFunction::iterator FirstMBB = BB;
152 // Codegen the basic block.
153 DAG.setRoot(Select(DAG.getRoot()));
155 DAG.RemoveDeadNodes();
157 // Emit machine code to BB.
158 ScheduleAndEmitDAG(DAG);
160 // If we are emitting FP stack code, scan the basic block to determine if this
161 // block defines any FP values. If so, put an FP_REG_KILL instruction before
162 // the terminator of the block.
163 if (X86Vector < SSE2) {
164 // Note that FP stack instructions *are* used in SSE code when returning
165 // values, but these are not live out of the basic block, so we don't need
166 // an FP_REG_KILL in this case either.
167 bool ContainsFPCode = false;
169 // Scan all of the machine instructions in these MBBs, checking for FP
171 MachineFunction::iterator MBBI = FirstMBB;
173 for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
174 !ContainsFPCode && I != E; ++I) {
175 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
176 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
177 MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
178 RegMap->getRegClass(I->getOperand(0).getReg()) ==
179 X86::RFPRegisterClass) {
180 ContainsFPCode = true;
185 } while (!ContainsFPCode && &*(MBBI++) != BB);
187 // Check PHI nodes in successor blocks. These PHI's will be lowered to have
188 // a copy of the input value in this block.
189 if (!ContainsFPCode) {
190 // Final check, check LLVM BB's that are successors to the LLVM BB
191 // corresponding to BB for FP PHI nodes.
192 const BasicBlock *LLVMBB = BB->getBasicBlock();
194 for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
195 !ContainsFPCode && SI != E; ++SI) {
196 for (BasicBlock::const_iterator II = SI->begin();
197 (PN = dyn_cast<PHINode>(II)); ++II) {
198 if (PN->getType()->isFloatingPoint()) {
199 ContainsFPCode = true;
206 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
207 if (ContainsFPCode) {
208 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
214 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
215 /// the main function.
216 static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
217 MachineFrameInfo *MFI) {
218 // Switch the FPU to 64-bit precision mode for better compatibility and speed.
219 int CWFrameIdx = MFI->CreateStackObject(2, 2);
220 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
222 // Set the high part to be 64-bit precision.
223 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
224 CWFrameIdx, 1).addImm(2);
226 // Reload the modified control word now.
227 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
230 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
231 // If this is main, emit special code for main.
232 MachineBasicBlock *BB = MF.begin();
233 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
234 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
237 /// MatchAddress - Add the specified node to the specified addressing mode,
238 /// returning true if it cannot be done. This just pattern matches for the
240 bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM) {
241 switch (N.getOpcode()) {
243 case ISD::FrameIndex:
244 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
245 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
246 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
251 case ISD::ConstantPool:
252 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
253 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N)) {
254 AM.BaseType = X86ISelAddressMode::ConstantPoolBase;
255 AM.Base.Reg = CurDAG->getTargetConstantPool(CP->get(), MVT::i32);
261 case ISD::GlobalAddress:
262 case ISD::TargetGlobalAddress:
264 AM.GV = cast<GlobalAddressSDNode>(N)->getGlobal();
270 AM.Disp += cast<ConstantSDNode>(N)->getValue();
274 if (AM.IndexReg.Val == 0 && AM.Scale == 1)
275 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
276 unsigned Val = CN->getValue();
277 if (Val == 1 || Val == 2 || Val == 3) {
279 SDOperand ShVal = N.Val->getOperand(0);
281 // Okay, we know that we have a scale by now. However, if the scaled
282 // value is an add of something and a constant, we can fold the
283 // constant into the disp field here.
284 if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
285 isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
286 AM.IndexReg = ShVal.Val->getOperand(0);
287 ConstantSDNode *AddVal =
288 cast<ConstantSDNode>(ShVal.Val->getOperand(1));
289 AM.Disp += AddVal->getValue() << Val;
299 // X*[3,5,9] -> X+X*[2,4,8]
300 if (AM.IndexReg.Val == 0 && AM.BaseType == X86ISelAddressMode::RegBase &&
301 AM.Base.Reg.Val == 0)
302 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
303 if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
304 AM.Scale = unsigned(CN->getValue())-1;
306 SDOperand MulVal = N.Val->getOperand(0);
309 // Okay, we know that we have a scale by now. However, if the scaled
310 // value is an add of something and a constant, we can fold the
311 // constant into the disp field here.
312 if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
313 isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
314 Reg = MulVal.Val->getOperand(0);
315 ConstantSDNode *AddVal =
316 cast<ConstantSDNode>(MulVal.Val->getOperand(1));
317 AM.Disp += AddVal->getValue() * CN->getValue();
319 Reg = N.Val->getOperand(0);
322 AM.IndexReg = AM.Base.Reg = Reg;
328 X86ISelAddressMode Backup = AM;
329 if (!MatchAddress(N.Val->getOperand(0), AM) &&
330 !MatchAddress(N.Val->getOperand(1), AM))
333 if (!MatchAddress(N.Val->getOperand(1), AM) &&
334 !MatchAddress(N.Val->getOperand(0), AM))
341 // Is the base register already occupied?
342 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
343 // If so, check to see if the scale index register is set.
344 if (AM.IndexReg.Val == 0) {
350 // Otherwise, we cannot select it.
354 // Default, generate it as a register.
355 AM.BaseType = X86ISelAddressMode::RegBase;
360 /// SelectAddr - returns true if it is able pattern match an addressing mode.
361 /// It returns the operands which make up the maximal addressing mode it can
362 /// match by reference.
363 bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
364 SDOperand &Index, SDOperand &Disp) {
365 X86ISelAddressMode AM;
366 if (MatchAddress(N, AM))
369 if (AM.BaseType == X86ISelAddressMode::RegBase) {
370 if (AM.Base.Reg.Val) {
371 if (AM.Base.Reg.getOpcode() != ISD::Register)
372 AM.Base.Reg = Select(AM.Base.Reg);
374 AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
379 AM.IndexReg = Select(AM.IndexReg);
381 AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
383 getAddressOperands(AM, Base, Scale, Index, Disp);
387 bool X86DAGToDAGISel::TryFoldLoad(SDOperand N, SDOperand &Base,
388 SDOperand &Scale, SDOperand &Index,
390 if (N.getOpcode() == ISD::LOAD && N.hasOneUse() &&
391 CodeGenMap.count(N.getValue(1)) == 0)
392 return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
396 static bool isRegister0(SDOperand Op) {
397 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
398 return (R->getReg() == 0);
402 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
403 /// mode it matches can be cost effectively emitted as an LEA instruction.
404 /// For X86, it always is unless it's just a (Reg + const).
405 bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
407 SDOperand &Index, SDOperand &Disp) {
408 X86ISelAddressMode AM;
409 if (!MatchAddress(N, AM)) {
410 bool SelectBase = false;
411 bool SelectIndex = false;
413 if (AM.BaseType == X86ISelAddressMode::RegBase) {
414 if (AM.Base.Reg.Val) {
418 AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
422 if (AM.IndexReg.Val) {
425 AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
429 unsigned Complexity = 0;
436 else if (AM.Disp > 1)
443 AM.Base.Reg = Select(AM.Base.Reg);
445 AM.IndexReg = Select(AM.IndexReg);
447 getAddressOperands(AM, Base, Scale, Index, Disp);
453 SDOperand X86DAGToDAGISel::Select(SDOperand N) {
454 SDNode *Node = N.Val;
455 MVT::ValueType NVT = Node->getValueType(0);
457 unsigned Opcode = Node->getOpcode();
459 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER)
460 return N; // Already selected.
462 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
463 if (CGMI != CodeGenMap.end()) return CGMI->second;
469 if (Opcode == ISD::MULHU)
471 default: assert(0 && "Unsupported VT!");
472 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
473 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
474 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
478 default: assert(0 && "Unsupported VT!");
479 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
480 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
481 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
484 unsigned LoReg, HiReg;
486 default: assert(0 && "Unsupported VT!");
487 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
488 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
489 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
492 SDOperand N0 = Node->getOperand(0);
493 SDOperand N1 = Node->getOperand(1);
495 bool foldedLoad = false;
496 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
497 foldedLoad = TryFoldLoad(N1, Tmp0, Tmp1, Tmp2, Tmp3);
498 // MULHU and MULHS are commmutative
500 foldedLoad = TryFoldLoad(N0, Tmp0, Tmp1, Tmp2, Tmp3);
502 N0 = Node->getOperand(1);
503 N1 = Node->getOperand(0);
507 SDOperand Chain = foldedLoad ? Select(N1.getOperand(0))
508 : CurDAG->getEntryNode();
511 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
513 InFlag = Chain.getValue(1);
516 Chain = CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
517 Tmp2, Tmp3, Chain, InFlag);
518 InFlag = Chain.getValue(1);
520 InFlag = CurDAG->getTargetNode(Opc, MVT::Flag, Select(N1), InFlag);
523 SDOperand Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
524 CodeGenMap[N.getValue(0)] = Result;
526 CodeGenMap[N1.getValue(1)] = Result.getValue(1);
534 bool isSigned = Opcode == ISD::SDIV || Opcode == ISD::SREM;
535 bool isDiv = Opcode == ISD::SDIV || Opcode == ISD::UDIV;
538 default: assert(0 && "Unsupported VT!");
539 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
540 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
541 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
545 default: assert(0 && "Unsupported VT!");
546 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
547 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
548 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
551 unsigned LoReg, HiReg;
552 unsigned ClrOpcode, SExtOpcode;
554 default: assert(0 && "Unsupported VT!");
556 LoReg = X86::AL; HiReg = X86::AH;
557 ClrOpcode = X86::MOV8ri;
558 SExtOpcode = X86::CBW;
561 LoReg = X86::AX; HiReg = X86::DX;
562 ClrOpcode = X86::MOV16ri;
563 SExtOpcode = X86::CWD;
566 LoReg = X86::EAX; HiReg = X86::EDX;
567 ClrOpcode = X86::MOV32ri;
568 SExtOpcode = X86::CDQ;
572 SDOperand N0 = Node->getOperand(0);
573 SDOperand N1 = Node->getOperand(1);
575 bool foldedLoad = false;
576 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
577 foldedLoad = TryFoldLoad(N1, Tmp0, Tmp1, Tmp2, Tmp3);
578 SDOperand Chain = foldedLoad ? Select(N1.getOperand(0))
579 : CurDAG->getEntryNode();
582 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
584 InFlag = Chain.getValue(1);
587 // Sign extend the low part into the high part.
588 InFlag = CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag);
590 // Zero out the high part, effectively zero extending the input.
592 CurDAG->getTargetNode(ClrOpcode, NVT,
593 CurDAG->getTargetConstant(0, NVT));
594 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT),
596 InFlag = Chain.getValue(1);
600 Chain = CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
601 Tmp2, Tmp3, Chain, InFlag);
602 InFlag = Chain.getValue(1);
604 InFlag = CurDAG->getTargetNode(Opc, MVT::Flag, Select(N1), InFlag);
607 SDOperand Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
609 CodeGenMap[N.getValue(0)] = Result;
611 CodeGenMap[N1.getValue(1)] = Result.getValue(1);
615 case ISD::TRUNCATE: {
618 switch (Node->getOperand(0).getValueType()) {
619 default: assert(0 && "Unknown truncate!");
620 case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
621 case MVT::i32: Reg = X86::EAX; Opc = X86::MOV32rr; VT = MVT::i32; break;
623 SDOperand Tmp0 = Select(Node->getOperand(0));
624 SDOperand Tmp1 = CurDAG->getTargetNode(Opc, VT, Tmp0);
625 SDOperand InFlag = SDOperand(0,0);
626 SDOperand Result = CurDAG->getCopyToReg(CurDAG->getEntryNode(),
628 SDOperand Chain = Result.getValue(0);
629 InFlag = Result.getValue(1);
632 default: assert(0 && "Unknown truncate!");
633 case MVT::i8: Reg = X86::AL; Opc = X86::MOV8rr; VT = MVT::i8; break;
634 case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
637 Result = CurDAG->getCopyFromReg(Chain,
639 if (N.Val->hasOneUse())
640 return CurDAG->SelectNodeTo(N.Val, Opc, VT, Result);
642 return CodeGenMap[N] = CurDAG->getTargetNode(Opc, VT, Result);
647 return SelectCode(N);
650 /// createX86ISelDag - This pass converts a legalized DAG into a
651 /// X86-specific DAG, ready for instruction scheduling.
653 FunctionPass *llvm::createX86ISelDag(TargetMachine &TM) {
654 return new X86DAGToDAGISel(TM);