1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/GlobalValue.h"
23 #include "llvm/Instructions.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/Support/CFG.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SSARegMap.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/ADT/Statistic.h"
39 //===----------------------------------------------------------------------===//
40 // Pattern Matcher Implementation
41 //===----------------------------------------------------------------------===//
44 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
45 /// SDOperand's instead of register numbers for the leaves of the matched
47 struct X86ISelAddressMode {
53 struct { // This is really a union, discriminated by BaseType!
63 unsigned Align; // CP alignment.
66 : BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0),
74 NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
76 //===--------------------------------------------------------------------===//
77 /// ISel - X86 specific code to select X86 machine instructions for
78 /// SelectionDAG operations.
80 class X86DAGToDAGISel : public SelectionDAGISel {
81 /// ContainsFPCode - Every instruction we select that uses or defines a FP
82 /// register should set this to true.
85 /// X86Lowering - This object fully describes how to lower LLVM code to an
86 /// X86-specific SelectionDAG.
87 X86TargetLowering X86Lowering;
89 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
90 /// make the right decision when generating code for different targets.
91 const X86Subtarget *Subtarget;
93 unsigned GlobalBaseReg;
95 X86DAGToDAGISel(X86TargetMachine &TM)
96 : SelectionDAGISel(X86Lowering),
97 X86Lowering(*TM.getTargetLowering()) {
98 Subtarget = &TM.getSubtarget<X86Subtarget>();
101 virtual bool runOnFunction(Function &Fn) {
102 // Make sure we re-emit a set of the global base reg if necessary
104 return SelectionDAGISel::runOnFunction(Fn);
107 virtual const char *getPassName() const {
108 return "X86 DAG->DAG Instruction Selection";
111 /// InstructionSelectBasicBlock - This callback is invoked by
112 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
113 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
115 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
117 // Include the pieces autogenerated from the target description.
118 #include "X86GenDAGISel.inc"
121 void Select(SDOperand &Result, SDOperand N);
123 bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
124 bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
125 SDOperand &Index, SDOperand &Disp);
126 bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
127 SDOperand &Index, SDOperand &Disp);
128 bool TryFoldLoad(SDOperand P, SDOperand N,
129 SDOperand &Base, SDOperand &Scale,
130 SDOperand &Index, SDOperand &Disp);
132 inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
133 SDOperand &Scale, SDOperand &Index,
135 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
136 CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
137 Scale = getI8Imm(AM.Scale);
139 Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
141 CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp)
142 : getI32Imm(AM.Disp));
145 /// getI8Imm - Return a target constant with the specified value, of type
147 inline SDOperand getI8Imm(unsigned Imm) {
148 return CurDAG->getTargetConstant(Imm, MVT::i8);
151 /// getI16Imm - Return a target constant with the specified value, of type
153 inline SDOperand getI16Imm(unsigned Imm) {
154 return CurDAG->getTargetConstant(Imm, MVT::i16);
157 /// getI32Imm - Return a target constant with the specified value, of type
159 inline SDOperand getI32Imm(unsigned Imm) {
160 return CurDAG->getTargetConstant(Imm, MVT::i32);
163 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
164 /// base register. Return the virtual register that holds this value.
165 SDOperand getGlobalBaseReg();
173 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
174 /// when it has created a SelectionDAG for us to codegen.
175 void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
177 MachineFunction::iterator FirstMBB = BB;
179 // Codegen the basic block.
181 DEBUG(std::cerr << "===== Instruction selection begins:\n");
184 DAG.setRoot(SelectRoot(DAG.getRoot()));
185 assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!");
187 DEBUG(std::cerr << "===== Instruction selection ends:\n");
192 DAG.RemoveDeadNodes();
194 // Emit machine code to BB.
195 ScheduleAndEmitDAG(DAG);
197 // If we are emitting FP stack code, scan the basic block to determine if this
198 // block defines any FP values. If so, put an FP_REG_KILL instruction before
199 // the terminator of the block.
200 if (!Subtarget->hasSSE2()) {
201 // Note that FP stack instructions *are* used in SSE code when returning
202 // values, but these are not live out of the basic block, so we don't need
203 // an FP_REG_KILL in this case either.
204 bool ContainsFPCode = false;
206 // Scan all of the machine instructions in these MBBs, checking for FP
208 MachineFunction::iterator MBBI = FirstMBB;
210 for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
211 !ContainsFPCode && I != E; ++I) {
212 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
213 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
214 MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
215 RegMap->getRegClass(I->getOperand(0).getReg()) ==
216 X86::RFPRegisterClass) {
217 ContainsFPCode = true;
222 } while (!ContainsFPCode && &*(MBBI++) != BB);
224 // Check PHI nodes in successor blocks. These PHI's will be lowered to have
225 // a copy of the input value in this block.
226 if (!ContainsFPCode) {
227 // Final check, check LLVM BB's that are successors to the LLVM BB
228 // corresponding to BB for FP PHI nodes.
229 const BasicBlock *LLVMBB = BB->getBasicBlock();
231 for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
232 !ContainsFPCode && SI != E; ++SI) {
233 for (BasicBlock::const_iterator II = SI->begin();
234 (PN = dyn_cast<PHINode>(II)); ++II) {
235 if (PN->getType()->isFloatingPoint()) {
236 ContainsFPCode = true;
243 // Finally, if we found any FP code, emit the FP_REG_KILL instruction.
244 if (ContainsFPCode) {
245 BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
251 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
252 /// the main function.
253 static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
254 MachineFrameInfo *MFI) {
255 // Switch the FPU to 64-bit precision mode for better compatibility and speed.
256 int CWFrameIdx = MFI->CreateStackObject(2, 2);
257 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
259 // Set the high part to be 64-bit precision.
260 addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
261 CWFrameIdx, 1).addImm(2);
263 // Reload the modified control word now.
264 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
267 void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
268 // If this is main, emit special code for main.
269 MachineBasicBlock *BB = MF.begin();
270 if (Fn.hasExternalLinkage() && Fn.getName() == "main")
271 EmitSpecialCodeForMain(BB, MF.getFrameInfo());
274 /// MatchAddress - Add the specified node to the specified addressing mode,
275 /// returning true if it cannot be done. This just pattern matches for the
277 bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
279 bool Available = false;
280 // If N has already been selected, reuse the result unless in some very
282 std::map<SDOperand, SDOperand>::iterator CGMI= CodeGenMap.find(N.getValue(0));
283 if (CGMI != CodeGenMap.end()) {
287 switch (N.getOpcode()) {
290 AM.Disp += cast<ConstantSDNode>(N)->getValue();
293 case X86ISD::Wrapper:
294 // If both base and index components have been picked, we can't fit
295 // the result available in the register in the addressing mode. Duplicate
296 // GlobalAddress or ConstantPool as displacement.
297 if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
298 if (ConstantPoolSDNode *CP =
299 dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
302 AM.Align = CP->getAlignment();
303 AM.Disp += CP->getOffset();
306 } else if (GlobalAddressSDNode *G =
307 dyn_cast<GlobalAddressSDNode>(N.getOperand(0))) {
309 AM.GV = G->getGlobal();
310 AM.Disp += G->getOffset();
317 case ISD::FrameIndex:
318 if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
319 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
320 AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
326 if (!Available && AM.IndexReg.Val == 0 && AM.Scale == 1)
327 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
328 unsigned Val = CN->getValue();
329 if (Val == 1 || Val == 2 || Val == 3) {
331 SDOperand ShVal = N.Val->getOperand(0);
333 // Okay, we know that we have a scale by now. However, if the scaled
334 // value is an add of something and a constant, we can fold the
335 // constant into the disp field here.
336 if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
337 isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
338 AM.IndexReg = ShVal.Val->getOperand(0);
339 ConstantSDNode *AddVal =
340 cast<ConstantSDNode>(ShVal.Val->getOperand(1));
341 AM.Disp += AddVal->getValue() << Val;
351 // X*[3,5,9] -> X+X*[2,4,8]
353 AM.BaseType == X86ISelAddressMode::RegBase &&
354 AM.Base.Reg.Val == 0 &&
355 AM.IndexReg.Val == 0)
356 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
357 if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
358 AM.Scale = unsigned(CN->getValue())-1;
360 SDOperand MulVal = N.Val->getOperand(0);
363 // Okay, we know that we have a scale by now. However, if the scaled
364 // value is an add of something and a constant, we can fold the
365 // constant into the disp field here.
366 if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
367 isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
368 Reg = MulVal.Val->getOperand(0);
369 ConstantSDNode *AddVal =
370 cast<ConstantSDNode>(MulVal.Val->getOperand(1));
371 AM.Disp += AddVal->getValue() * CN->getValue();
373 Reg = N.Val->getOperand(0);
376 AM.IndexReg = AM.Base.Reg = Reg;
383 X86ISelAddressMode Backup = AM;
384 if (!MatchAddress(N.Val->getOperand(0), AM, false) &&
385 !MatchAddress(N.Val->getOperand(1), AM, false))
388 if (!MatchAddress(N.Val->getOperand(1), AM, false) &&
389 !MatchAddress(N.Val->getOperand(0), AM, false))
398 X86ISelAddressMode Backup = AM;
399 // Look for (x << c1) | c2 where (c2 < c1)
400 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(0));
401 if (CN && !MatchAddress(N.Val->getOperand(1), AM, false)) {
402 if (AM.GV == NULL && AM.Disp == 0 && CN->getValue() < AM.Scale) {
403 AM.Disp = CN->getValue();
408 CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1));
409 if (CN && !MatchAddress(N.Val->getOperand(0), AM, false)) {
410 if (AM.GV == NULL && AM.Disp == 0 && CN->getValue() < AM.Scale) {
411 AM.Disp = CN->getValue();
421 // Is the base register already occupied?
422 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
423 // If so, check to see if the scale index register is set.
424 if (AM.IndexReg.Val == 0) {
430 // Otherwise, we cannot select it.
434 // Default, generate it as a register.
435 AM.BaseType = X86ISelAddressMode::RegBase;
440 /// SelectAddr - returns true if it is able pattern match an addressing mode.
441 /// It returns the operands which make up the maximal addressing mode it can
442 /// match by reference.
443 bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
444 SDOperand &Index, SDOperand &Disp) {
445 X86ISelAddressMode AM;
446 if (MatchAddress(N, AM))
449 if (AM.BaseType == X86ISelAddressMode::RegBase) {
450 if (!AM.Base.Reg.Val)
451 AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
454 if (!AM.IndexReg.Val)
455 AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
457 getAddressOperands(AM, Base, Scale, Index, Disp);
462 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
463 /// mode it matches can be cost effectively emitted as an LEA instruction.
464 /// For X86, it always is unless it's just a (Reg + const).
465 bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
467 SDOperand &Index, SDOperand &Disp) {
468 X86ISelAddressMode AM;
469 if (MatchAddress(N, AM))
472 unsigned Complexity = 0;
473 if (AM.BaseType == X86ISelAddressMode::RegBase)
477 AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
478 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
484 AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
488 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg
489 else if (AM.Scale > 1)
492 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
493 // to a LEA. This is determined with some expermentation but is by no means
494 // optimal (especially for code size consideration). LEA is nice because of
495 // its three-address nature. Tweak the cost function again when we can run
496 // convertToThreeAddress() at register allocation time.
500 if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
503 if (Complexity > 2) {
504 getAddressOperands(AM, Base, Scale, Index, Disp);
511 bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
512 SDOperand &Base, SDOperand &Scale,
513 SDOperand &Index, SDOperand &Disp) {
514 if (N.getOpcode() == ISD::LOAD &&
516 !CodeGenMap.count(N.getValue(0)) &&
517 (P.getNumOperands() == 1 || !isNonImmUse(P.Val, N.Val)))
518 return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
522 static bool isRegister0(SDOperand Op) {
523 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
524 return (R->getReg() == 0);
528 /// getGlobalBaseReg - Output the instructions required to put the
529 /// base address to use for accessing globals into a register.
531 SDOperand X86DAGToDAGISel::getGlobalBaseReg() {
532 if (!GlobalBaseReg) {
533 // Insert the set of GlobalBaseReg into the first MBB of the function
534 MachineBasicBlock &FirstMBB = BB->getParent()->front();
535 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
536 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
537 // FIXME: when we get to LP64, we will need to create the appropriate
538 // type of register here.
539 GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
540 BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
541 BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
543 return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
546 static SDNode *FindCallStartFromCall(SDNode *Node) {
547 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
548 assert(Node->getOperand(0).getValueType() == MVT::Other &&
549 "Node doesn't have a token chain argument!");
550 return FindCallStartFromCall(Node->getOperand(0).Val);
553 void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
554 SDNode *Node = N.Val;
555 MVT::ValueType NVT = Node->getValueType(0);
557 unsigned Opcode = Node->getOpcode();
560 DEBUG(std::cerr << std::string(Indent, ' '));
561 DEBUG(std::cerr << "Selecting: ");
562 DEBUG(Node->dump(CurDAG));
563 DEBUG(std::cerr << "\n");
567 if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) {
570 DEBUG(std::cerr << std::string(Indent-2, ' '));
571 DEBUG(std::cerr << "== ");
572 DEBUG(Node->dump(CurDAG));
573 DEBUG(std::cerr << "\n");
576 return; // Already selected.
579 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
580 if (CGMI != CodeGenMap.end()) {
581 Result = CGMI->second;
583 DEBUG(std::cerr << std::string(Indent-2, ' '));
584 DEBUG(std::cerr << "== ");
585 DEBUG(Result.Val->dump(CurDAG));
586 DEBUG(std::cerr << "\n");
594 case X86ISD::GlobalBaseReg:
595 Result = getGlobalBaseReg();
599 // Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
600 // code and is matched first so to prevent it from being turned into
602 SDOperand N0 = N.getOperand(0);
603 SDOperand N1 = N.getOperand(1);
604 if (N.Val->getValueType(0) == MVT::i32 &&
605 N0.getOpcode() == X86ISD::Wrapper &&
606 N1.getOpcode() == ISD::Constant) {
607 unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
609 // TODO: handle ExternalSymbolSDNode.
610 if (GlobalAddressSDNode *G =
611 dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
612 C = CurDAG->getTargetGlobalAddress(G->getGlobal(), MVT::i32,
613 G->getOffset() + Offset);
614 } else if (ConstantPoolSDNode *CP =
615 dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
616 C = CurDAG->getTargetConstantPool(CP->get(), MVT::i32,
618 CP->getOffset()+Offset);
622 if (N.Val->hasOneUse()) {
623 Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
625 SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C);
626 Result = CodeGenMap[N] = SDOperand(ResNode, 0);
632 // Other cases are handled by auto-generated code.
638 if (Opcode == ISD::MULHU)
640 default: assert(0 && "Unsupported VT!");
641 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
642 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
643 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
647 default: assert(0 && "Unsupported VT!");
648 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
649 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
650 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
653 unsigned LoReg, HiReg;
655 default: assert(0 && "Unsupported VT!");
656 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
657 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
658 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
661 SDOperand N0 = Node->getOperand(0);
662 SDOperand N1 = Node->getOperand(1);
664 bool foldedLoad = false;
665 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
666 foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
667 // MULHU and MULHS are commmutative
669 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
671 N0 = Node->getOperand(1);
672 N1 = Node->getOperand(0);
678 Select(Chain, N1.getOperand(0));
680 Chain = CurDAG->getEntryNode();
682 SDOperand InFlag(0, 0);
684 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
686 InFlag = Chain.getValue(1);
694 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
695 Tmp2, Tmp3, Chain, InFlag);
696 Chain = SDOperand(CNode, 0);
697 InFlag = SDOperand(CNode, 1);
701 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
704 Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
705 CodeGenMap[N.getValue(0)] = Result;
707 CodeGenMap[N1.getValue(1)] = Result.getValue(1);
708 AddHandleReplacement(N1.Val, 1, Result.Val, 1);
712 DEBUG(std::cerr << std::string(Indent-2, ' '));
713 DEBUG(std::cerr << "== ");
714 DEBUG(Result.Val->dump(CurDAG));
715 DEBUG(std::cerr << "\n");
725 bool isSigned = Opcode == ISD::SDIV || Opcode == ISD::SREM;
726 bool isDiv = Opcode == ISD::SDIV || Opcode == ISD::UDIV;
729 default: assert(0 && "Unsupported VT!");
730 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
731 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
732 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
736 default: assert(0 && "Unsupported VT!");
737 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
738 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
739 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
742 unsigned LoReg, HiReg;
743 unsigned ClrOpcode, SExtOpcode;
745 default: assert(0 && "Unsupported VT!");
747 LoReg = X86::AL; HiReg = X86::AH;
748 ClrOpcode = X86::MOV8ri;
749 SExtOpcode = X86::CBW;
752 LoReg = X86::AX; HiReg = X86::DX;
753 ClrOpcode = X86::MOV16ri;
754 SExtOpcode = X86::CWD;
757 LoReg = X86::EAX; HiReg = X86::EDX;
758 ClrOpcode = X86::MOV32ri;
759 SExtOpcode = X86::CDQ;
763 SDOperand N0 = Node->getOperand(0);
764 SDOperand N1 = Node->getOperand(1);
766 bool foldedLoad = false;
767 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
768 foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
771 Select(Chain, N1.getOperand(0));
773 Chain = CurDAG->getEntryNode();
775 SDOperand InFlag(0, 0);
777 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
779 InFlag = Chain.getValue(1);
782 // Sign extend the low part into the high part.
784 SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
786 // Zero out the high part, effectively zero extending the input.
788 SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT,
789 CurDAG->getTargetConstant(0, NVT)), 0);
790 Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT),
792 InFlag = Chain.getValue(1);
801 CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
802 Tmp2, Tmp3, Chain, InFlag);
803 Chain = SDOperand(CNode, 0);
804 InFlag = SDOperand(CNode, 1);
808 SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
811 Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
813 CodeGenMap[N.getValue(0)] = Result;
815 CodeGenMap[N1.getValue(1)] = Result.getValue(1);
816 AddHandleReplacement(N1.Val, 1, Result.Val, 1);
820 DEBUG(std::cerr << std::string(Indent-2, ' '));
821 DEBUG(std::cerr << "== ");
822 DEBUG(Result.Val->dump(CurDAG));
823 DEBUG(std::cerr << "\n");
829 case ISD::TRUNCATE: {
830 if (NVT == MVT::i8) {
833 switch (Node->getOperand(0).getValueType()) {
834 default: assert(0 && "Unknown truncate!");
836 Opc = X86::MOV16to16_;
838 Opc2 = X86::TRUNC_GR16_GR8;
841 Opc = X86::MOV32to32_;
843 Opc2 = X86::TRUNC_GR32_GR8;
847 SDOperand Tmp0, Tmp1;
848 Select(Tmp0, Node->getOperand(0));
849 Tmp1 = SDOperand(CurDAG->getTargetNode(Opc, VT, Tmp0), 0);
850 Result = CodeGenMap[N] =
851 SDOperand(CurDAG->getTargetNode(Opc2, NVT, Tmp1), 0);
854 DEBUG(std::cerr << std::string(Indent-2, ' '));
855 DEBUG(std::cerr << "== ");
856 DEBUG(Result.Val->dump(CurDAG));
857 DEBUG(std::cerr << "\n");
867 SelectCode(Result, N);
869 DEBUG(std::cerr << std::string(Indent-2, ' '));
870 DEBUG(std::cerr << "=> ");
871 DEBUG(Result.Val->dump(CurDAG));
872 DEBUG(std::cerr << "\n");
877 /// createX86ISelDag - This pass converts a legalized DAG into a
878 /// X86-specific DAG, ready for instruction scheduling.
880 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM) {
881 return new X86DAGToDAGISel(TM);