1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
18 #include "X86RegisterInfo.h"
19 #include "X86Subtarget.h"
20 #include "X86TargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetMachine.h"
36 #include "llvm/Target/TargetOptions.h"
40 #define DEBUG_TYPE "x86-isel"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
72 unsigned Align; // CP alignment.
73 unsigned char SymbolFlags; // X86II::MO_*
76 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
77 Segment(), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
78 MCSym(nullptr), JT(-1), Align(0), SymbolFlags(X86II::MO_NO_FLAG) {}
80 bool hasSymbolicDisplacement() const {
81 return GV != nullptr || CP != nullptr || ES != nullptr ||
82 MCSym != nullptr || JT != -1 || BlockAddr != nullptr;
85 bool hasBaseOrIndexReg() const {
86 return BaseType == FrameIndexBase ||
87 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr;
90 /// isRIPRelative - Return true if this addressing mode is already RIP
92 bool isRIPRelative() const {
93 if (BaseType != RegBase) return false;
94 if (RegisterSDNode *RegNode =
95 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
96 return RegNode->getReg() == X86::RIP;
100 void setBaseReg(SDValue Reg) {
105 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
107 dbgs() << "X86ISelAddressMode " << this << '\n';
108 dbgs() << "Base_Reg ";
109 if (Base_Reg.getNode())
110 Base_Reg.getNode()->dump();
113 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
114 << " Scale" << Scale << '\n'
116 if (IndexReg.getNode())
117 IndexReg.getNode()->dump();
120 dbgs() << " Disp " << Disp << '\n'
142 dbgs() << " JT" << JT << " Align" << Align << '\n';
149 //===--------------------------------------------------------------------===//
150 /// ISel - X86 specific code to select X86 machine instructions for
151 /// SelectionDAG operations.
153 class X86DAGToDAGISel final : public SelectionDAGISel {
154 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
155 /// make the right decision when generating code for different targets.
156 const X86Subtarget *Subtarget;
158 /// OptForSize - If true, selector should try to optimize for code size
159 /// instead of performance.
163 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
164 : SelectionDAGISel(tm, OptLevel), OptForSize(false) {}
166 const char *getPassName() const override {
167 return "X86 DAG->DAG Instruction Selection";
170 bool runOnMachineFunction(MachineFunction &MF) override {
171 // Reset the subtarget each time through.
172 Subtarget = &MF.getSubtarget<X86Subtarget>();
173 SelectionDAGISel::runOnMachineFunction(MF);
177 void EmitFunctionEntryCode() override;
179 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
181 void PreprocessISelDAG() override;
183 inline bool immSext8(SDNode *N) const {
184 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
187 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
188 // sign extended field.
189 inline bool i64immSExt32(SDNode *N) const {
190 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
191 return (int64_t)v == (int32_t)v;
194 // Include the pieces autogenerated from the target description.
195 #include "X86GenDAGISel.inc"
198 SDNode *Select(SDNode *N) override;
199 SDNode *SelectGather(SDNode *N, unsigned Opc);
200 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
202 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
203 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
204 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
205 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
206 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
208 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
209 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
210 SDValue &Scale, SDValue &Index, SDValue &Disp,
212 bool SelectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
213 SDValue &Scale, SDValue &Index, SDValue &Disp,
215 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
216 bool SelectLEAAddr(SDValue N, SDValue &Base,
217 SDValue &Scale, SDValue &Index, SDValue &Disp,
219 bool SelectLEA64_32Addr(SDValue N, SDValue &Base,
220 SDValue &Scale, SDValue &Index, SDValue &Disp,
222 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
223 SDValue &Scale, SDValue &Index, SDValue &Disp,
225 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
226 SDValue &Base, SDValue &Scale,
227 SDValue &Index, SDValue &Disp,
229 SDValue &NodeWithChain);
231 bool TryFoldLoad(SDNode *P, SDValue N,
232 SDValue &Base, SDValue &Scale,
233 SDValue &Index, SDValue &Disp,
236 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
237 /// inline asm expressions.
238 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
239 unsigned ConstraintID,
240 std::vector<SDValue> &OutOps) override;
242 void EmitSpecialCodeForMain();
244 inline void getAddressOperands(X86ISelAddressMode &AM, SDLoc DL,
245 SDValue &Base, SDValue &Scale,
246 SDValue &Index, SDValue &Disp,
248 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
249 ? CurDAG->getTargetFrameIndex(
251 TLI->getPointerTy(CurDAG->getDataLayout()))
253 Scale = getI8Imm(AM.Scale, DL);
255 // These are 32-bit even in 64-bit mode since RIP relative offset
258 Disp = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(),
262 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
263 AM.Align, AM.Disp, AM.SymbolFlags);
265 assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
266 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
267 } else if (AM.MCSym) {
268 assert(!AM.Disp && "Non-zero displacement is ignored with MCSym.");
269 assert(AM.SymbolFlags == 0 && "oo");
270 Disp = CurDAG->getMCSymbol(AM.MCSym, MVT::i32);
271 } else if (AM.JT != -1) {
272 assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
273 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
274 } else if (AM.BlockAddr)
275 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
278 Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32);
280 if (AM.Segment.getNode())
281 Segment = AM.Segment;
283 Segment = CurDAG->getRegister(0, MVT::i32);
286 /// getI8Imm - Return a target constant with the specified value, of type
288 inline SDValue getI8Imm(unsigned Imm, SDLoc DL) {
289 return CurDAG->getTargetConstant(Imm, DL, MVT::i8);
292 /// getI32Imm - Return a target constant with the specified value, of type
294 inline SDValue getI32Imm(unsigned Imm, SDLoc DL) {
295 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
298 /// getGlobalBaseReg - Return an SDNode that returns the value of
299 /// the global base register. Output instructions required to
300 /// initialize the global base register, if necessary.
302 SDNode *getGlobalBaseReg();
304 /// getTargetMachine - Return a reference to the TargetMachine, casted
305 /// to the target-specific type.
306 const X86TargetMachine &getTargetMachine() const {
307 return static_cast<const X86TargetMachine &>(TM);
310 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
311 /// to the target-specific type.
312 const X86InstrInfo *getInstrInfo() const {
313 return Subtarget->getInstrInfo();
316 /// \brief Address-mode matching performs shift-of-and to and-of-shift
317 /// reassociation in order to expose more scaled addressing
319 bool ComplexPatternFuncMutatesDAG() const override {
327 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
328 if (OptLevel == CodeGenOpt::None) return false;
333 if (N.getOpcode() != ISD::LOAD)
336 // If N is a load, do additional profitability checks.
338 switch (U->getOpcode()) {
351 SDValue Op1 = U->getOperand(1);
353 // If the other operand is a 8-bit immediate we should fold the immediate
354 // instead. This reduces code size.
356 // movl 4(%esp), %eax
360 // addl 4(%esp), %eax
361 // The former is 2 bytes shorter. In case where the increment is 1, then
362 // the saving can be 4 bytes (by using incl %eax).
363 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
364 if (Imm->getAPIntValue().isSignedIntN(8))
367 // If the other operand is a TLS address, we should fold it instead.
370 // leal i@NTPOFF(%eax), %eax
372 // movl $i@NTPOFF, %eax
374 // if the block also has an access to a second TLS address this will save
376 // FIXME: This is probably also true for non-TLS addresses.
377 if (Op1.getOpcode() == X86ISD::Wrapper) {
378 SDValue Val = Op1.getOperand(0);
379 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
389 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
390 /// load's chain operand and move load below the call's chain operand.
391 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
392 SDValue Call, SDValue OrigChain) {
393 SmallVector<SDValue, 8> Ops;
394 SDValue Chain = OrigChain.getOperand(0);
395 if (Chain.getNode() == Load.getNode())
396 Ops.push_back(Load.getOperand(0));
398 assert(Chain.getOpcode() == ISD::TokenFactor &&
399 "Unexpected chain operand");
400 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
401 if (Chain.getOperand(i).getNode() == Load.getNode())
402 Ops.push_back(Load.getOperand(0));
404 Ops.push_back(Chain.getOperand(i));
406 CurDAG->getNode(ISD::TokenFactor, SDLoc(Load), MVT::Other, Ops);
408 Ops.push_back(NewChain);
410 Ops.append(OrigChain->op_begin() + 1, OrigChain->op_end());
411 CurDAG->UpdateNodeOperands(OrigChain.getNode(), Ops);
412 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
413 Load.getOperand(1), Load.getOperand(2));
416 Ops.push_back(SDValue(Load.getNode(), 1));
417 Ops.append(Call->op_begin() + 1, Call->op_end());
418 CurDAG->UpdateNodeOperands(Call.getNode(), Ops);
421 /// isCalleeLoad - Return true if call address is a load and it can be
422 /// moved below CALLSEQ_START and the chains leading up to the call.
423 /// Return the CALLSEQ_START by reference as a second output.
424 /// In the case of a tail call, there isn't a callseq node between the call
425 /// chain and the load.
426 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
427 // The transformation is somewhat dangerous if the call's chain was glued to
428 // the call. After MoveBelowOrigChain the load is moved between the call and
429 // the chain, this can create a cycle if the load is not folded. So it is
430 // *really* important that we are sure the load will be folded.
431 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
433 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
436 LD->getAddressingMode() != ISD::UNINDEXED ||
437 LD->getExtensionType() != ISD::NON_EXTLOAD)
440 // Now let's find the callseq_start.
441 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
442 if (!Chain.hasOneUse())
444 Chain = Chain.getOperand(0);
447 if (!Chain.getNumOperands())
449 // Since we are not checking for AA here, conservatively abort if the chain
450 // writes to memory. It's not safe to move the callee (a load) across a store.
451 if (isa<MemSDNode>(Chain.getNode()) &&
452 cast<MemSDNode>(Chain.getNode())->writeMem())
454 if (Chain.getOperand(0).getNode() == Callee.getNode())
456 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
457 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
458 Callee.getValue(1).hasOneUse())
463 void X86DAGToDAGISel::PreprocessISelDAG() {
464 // OptForSize is used in pattern predicates that isel is matching.
465 OptForSize = MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
467 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
468 E = CurDAG->allnodes_end(); I != E; ) {
469 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
471 if (OptLevel != CodeGenOpt::None &&
472 // Only does this when target favors doesn't favor register indirect
474 ((N->getOpcode() == X86ISD::CALL && !Subtarget->callRegIndirect()) ||
475 (N->getOpcode() == X86ISD::TC_RETURN &&
476 // Only does this if load can be folded into TC_RETURN.
477 (Subtarget->is64Bit() ||
478 getTargetMachine().getRelocationModel() != Reloc::PIC_)))) {
479 /// Also try moving call address load from outside callseq_start to just
480 /// before the call to allow it to be folded.
498 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
499 SDValue Chain = N->getOperand(0);
500 SDValue Load = N->getOperand(1);
501 if (!isCalleeLoad(Load, Chain, HasCallSeq))
503 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
508 // Lower fpround and fpextend nodes that target the FP stack to be store and
509 // load to the stack. This is a gross hack. We would like to simply mark
510 // these as being illegal, but when we do that, legalize produces these when
511 // it expands calls, then expands these in the same legalize pass. We would
512 // like dag combine to be able to hack on these between the call expansion
513 // and the node legalization. As such this pass basically does "really
514 // late" legalization of these inline with the X86 isel pass.
515 // FIXME: This should only happen when not compiled with -O0.
516 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
519 MVT SrcVT = N->getOperand(0).getSimpleValueType();
520 MVT DstVT = N->getSimpleValueType(0);
522 // If any of the sources are vectors, no fp stack involved.
523 if (SrcVT.isVector() || DstVT.isVector())
526 // If the source and destination are SSE registers, then this is a legal
527 // conversion that should not be lowered.
528 const X86TargetLowering *X86Lowering =
529 static_cast<const X86TargetLowering *>(TLI);
530 bool SrcIsSSE = X86Lowering->isScalarFPTypeInSSEReg(SrcVT);
531 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT);
532 if (SrcIsSSE && DstIsSSE)
535 if (!SrcIsSSE && !DstIsSSE) {
536 // If this is an FPStack extension, it is a noop.
537 if (N->getOpcode() == ISD::FP_EXTEND)
539 // If this is a value-preserving FPStack truncation, it is a noop.
540 if (N->getConstantOperandVal(1))
544 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
545 // FPStack has extload and truncstore. SSE can fold direct loads into other
546 // operations. Based on this, decide what we want to do.
548 if (N->getOpcode() == ISD::FP_ROUND)
549 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
551 MemVT = SrcIsSSE ? SrcVT : DstVT;
553 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
556 // FIXME: optimize the case where the src/dest is a load or store?
557 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
559 MemTmp, MachinePointerInfo(), MemVT,
561 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
562 MachinePointerInfo(),
563 MemVT, false, false, false, 0);
565 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
566 // extload we created. This will cause general havok on the dag because
567 // anything below the conversion could be folded into other existing nodes.
568 // To avoid invalidating 'I', back it up to the convert node.
570 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
572 // Now that we did that, the node is dead. Increment the iterator to the
573 // next node to process, then delete N.
575 CurDAG->DeleteNode(N);
580 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
581 /// the main function.
582 void X86DAGToDAGISel::EmitSpecialCodeForMain() {
583 if (Subtarget->isTargetCygMing()) {
584 TargetLowering::ArgListTy Args;
585 auto &DL = CurDAG->getDataLayout();
587 TargetLowering::CallLoweringInfo CLI(*CurDAG);
588 CLI.setChain(CurDAG->getRoot())
589 .setCallee(CallingConv::C, Type::getVoidTy(*CurDAG->getContext()),
590 CurDAG->getExternalSymbol("__main", TLI->getPointerTy(DL)),
592 const TargetLowering &TLI = CurDAG->getTargetLoweringInfo();
593 std::pair<SDValue, SDValue> Result = TLI.LowerCallTo(CLI);
594 CurDAG->setRoot(Result.second);
598 void X86DAGToDAGISel::EmitFunctionEntryCode() {
599 // If this is main, emit special code for main.
600 if (const Function *Fn = MF->getFunction())
601 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
602 EmitSpecialCodeForMain();
605 static bool isDispSafeForFrameIndex(int64_t Val) {
606 // On 64-bit platforms, we can run into an issue where a frame index
607 // includes a displacement that, when added to the explicit displacement,
608 // will overflow the displacement field. Assuming that the frame index
609 // displacement fits into a 31-bit integer (which is only slightly more
610 // aggressive than the current fundamental assumption that it fits into
611 // a 32-bit integer), a 31-bit disp should always be safe.
612 return isInt<31>(Val);
615 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
616 X86ISelAddressMode &AM) {
617 // Cannot combine ExternalSymbol displacements with integer offsets.
618 if (Offset != 0 && (AM.ES || AM.MCSym))
620 int64_t Val = AM.Disp + Offset;
621 CodeModel::Model M = TM.getCodeModel();
622 if (Subtarget->is64Bit()) {
623 if (!X86::isOffsetSuitableForCodeModel(Val, M,
624 AM.hasSymbolicDisplacement()))
626 // In addition to the checks required for a register base, check that
627 // we do not try to use an unsafe Disp with a frame index.
628 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
629 !isDispSafeForFrameIndex(Val))
637 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
638 SDValue Address = N->getOperand(1);
640 // load gs:0 -> GS segment register.
641 // load fs:0 -> FS segment register.
643 // This optimization is valid because the GNU TLS model defines that
644 // gs:0 (or fs:0 on X86-64) contains its own address.
645 // For more information see http://people.redhat.com/drepper/tls.pdf
646 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
647 if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
648 Subtarget->isTargetLinux())
649 switch (N->getPointerInfo().getAddrSpace()) {
651 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
654 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
661 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
662 /// into an addressing mode. These wrap things that will resolve down into a
663 /// symbol reference. If no match is possible, this returns true, otherwise it
665 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
666 // If the addressing mode already has a symbol as the displacement, we can
667 // never match another symbol.
668 if (AM.hasSymbolicDisplacement())
671 SDValue N0 = N.getOperand(0);
672 CodeModel::Model M = TM.getCodeModel();
674 // Handle X86-64 rip-relative addresses. We check this before checking direct
675 // folding because RIP is preferable to non-RIP accesses.
676 if (Subtarget->is64Bit() && N.getOpcode() == X86ISD::WrapperRIP &&
677 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
678 // they cannot be folded into immediate fields.
679 // FIXME: This can be improved for kernel and other models?
680 (M == CodeModel::Small || M == CodeModel::Kernel)) {
681 // Base and index reg must be 0 in order to use %rip as base.
682 if (AM.hasBaseOrIndexReg())
684 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
685 X86ISelAddressMode Backup = AM;
686 AM.GV = G->getGlobal();
687 AM.SymbolFlags = G->getTargetFlags();
688 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
692 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
693 X86ISelAddressMode Backup = AM;
694 AM.CP = CP->getConstVal();
695 AM.Align = CP->getAlignment();
696 AM.SymbolFlags = CP->getTargetFlags();
697 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
701 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
702 AM.ES = S->getSymbol();
703 AM.SymbolFlags = S->getTargetFlags();
704 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) {
705 AM.MCSym = S->getMCSymbol();
706 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
707 AM.JT = J->getIndex();
708 AM.SymbolFlags = J->getTargetFlags();
709 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
710 X86ISelAddressMode Backup = AM;
711 AM.BlockAddr = BA->getBlockAddress();
712 AM.SymbolFlags = BA->getTargetFlags();
713 if (FoldOffsetIntoAddress(BA->getOffset(), AM)) {
718 llvm_unreachable("Unhandled symbol reference node.");
720 if (N.getOpcode() == X86ISD::WrapperRIP)
721 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
725 // Handle the case when globals fit in our immediate field: This is true for
726 // X86-32 always and X86-64 when in -mcmodel=small mode. In 64-bit
727 // mode, this only applies to a non-RIP-relative computation.
728 if (!Subtarget->is64Bit() ||
729 M == CodeModel::Small || M == CodeModel::Kernel) {
730 assert(N.getOpcode() != X86ISD::WrapperRIP &&
731 "RIP-relative addressing already handled");
732 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
733 AM.GV = G->getGlobal();
734 AM.Disp += G->getOffset();
735 AM.SymbolFlags = G->getTargetFlags();
736 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
737 AM.CP = CP->getConstVal();
738 AM.Align = CP->getAlignment();
739 AM.Disp += CP->getOffset();
740 AM.SymbolFlags = CP->getTargetFlags();
741 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
742 AM.ES = S->getSymbol();
743 AM.SymbolFlags = S->getTargetFlags();
744 } else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) {
745 AM.MCSym = S->getMCSymbol();
746 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
747 AM.JT = J->getIndex();
748 AM.SymbolFlags = J->getTargetFlags();
749 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(N0)) {
750 AM.BlockAddr = BA->getBlockAddress();
751 AM.Disp += BA->getOffset();
752 AM.SymbolFlags = BA->getTargetFlags();
754 llvm_unreachable("Unhandled symbol reference node.");
761 /// MatchAddress - Add the specified node to the specified addressing mode,
762 /// returning true if it cannot be done. This just pattern matches for the
764 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
765 if (MatchAddressRecursively(N, AM, 0))
768 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
769 // a smaller encoding and avoids a scaled-index.
771 AM.BaseType == X86ISelAddressMode::RegBase &&
772 AM.Base_Reg.getNode() == nullptr) {
773 AM.Base_Reg = AM.IndexReg;
777 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
778 // because it has a smaller encoding.
779 // TODO: Which other code models can use this?
780 if (TM.getCodeModel() == CodeModel::Small &&
781 Subtarget->is64Bit() &&
783 AM.BaseType == X86ISelAddressMode::RegBase &&
784 AM.Base_Reg.getNode() == nullptr &&
785 AM.IndexReg.getNode() == nullptr &&
786 AM.SymbolFlags == X86II::MO_NO_FLAG &&
787 AM.hasSymbolicDisplacement())
788 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
793 // Insert a node into the DAG at least before the Pos node's position. This
794 // will reposition the node as needed, and will assign it a node ID that is <=
795 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
796 // IDs! The selection DAG must no longer depend on their uniqueness when this
798 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
799 if (N.getNode()->getNodeId() == -1 ||
800 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
801 DAG.RepositionNode(Pos.getNode(), N.getNode());
802 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
806 // Transform "(X >> (8-C1)) & (0xff << C1)" to "((X >> 8) & 0xff) << C1" if
807 // safe. This allows us to convert the shift and and into an h-register
808 // extract and a scaled index. Returns false if the simplification is
810 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
812 SDValue Shift, SDValue X,
813 X86ISelAddressMode &AM) {
814 if (Shift.getOpcode() != ISD::SRL ||
815 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
819 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
820 if (ScaleLog <= 0 || ScaleLog >= 4 ||
821 Mask != (0xffu << ScaleLog))
824 MVT VT = N.getSimpleValueType();
826 SDValue Eight = DAG.getConstant(8, DL, MVT::i8);
827 SDValue NewMask = DAG.getConstant(0xff, DL, VT);
828 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
829 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
830 SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8);
831 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
833 // Insert the new nodes into the topological ordering. We must do this in
834 // a valid topological ordering as nothing is going to go back and re-sort
835 // these nodes. We continually insert before 'N' in sequence as this is
836 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
837 // hierarchy left to express.
838 InsertDAGNode(DAG, N, Eight);
839 InsertDAGNode(DAG, N, Srl);
840 InsertDAGNode(DAG, N, NewMask);
841 InsertDAGNode(DAG, N, And);
842 InsertDAGNode(DAG, N, ShlCount);
843 InsertDAGNode(DAG, N, Shl);
844 DAG.ReplaceAllUsesWith(N, Shl);
846 AM.Scale = (1 << ScaleLog);
850 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
851 // allows us to fold the shift into this addressing mode. Returns false if the
852 // transform succeeded.
853 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
855 SDValue Shift, SDValue X,
856 X86ISelAddressMode &AM) {
857 if (Shift.getOpcode() != ISD::SHL ||
858 !isa<ConstantSDNode>(Shift.getOperand(1)))
861 // Not likely to be profitable if either the AND or SHIFT node has more
862 // than one use (unless all uses are for address computation). Besides,
863 // isel mechanism requires their node ids to be reused.
864 if (!N.hasOneUse() || !Shift.hasOneUse())
867 // Verify that the shift amount is something we can fold.
868 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
869 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
872 MVT VT = N.getSimpleValueType();
874 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);
875 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
876 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
878 // Insert the new nodes into the topological ordering. We must do this in
879 // a valid topological ordering as nothing is going to go back and re-sort
880 // these nodes. We continually insert before 'N' in sequence as this is
881 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
882 // hierarchy left to express.
883 InsertDAGNode(DAG, N, NewMask);
884 InsertDAGNode(DAG, N, NewAnd);
885 InsertDAGNode(DAG, N, NewShift);
886 DAG.ReplaceAllUsesWith(N, NewShift);
888 AM.Scale = 1 << ShiftAmt;
889 AM.IndexReg = NewAnd;
893 // Implement some heroics to detect shifts of masked values where the mask can
894 // be replaced by extending the shift and undoing that in the addressing mode
895 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
896 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
897 // the addressing mode. This results in code such as:
899 // int f(short *y, int *lookup_table) {
901 // return *y + lookup_table[*y >> 11];
905 // movzwl (%rdi), %eax
908 // addl (%rsi,%rcx,4), %eax
911 // movzwl (%rdi), %eax
915 // addl (%rsi,%rcx), %eax
917 // Note that this function assumes the mask is provided as a mask *after* the
918 // value is shifted. The input chain may or may not match that, but computing
919 // such a mask is trivial.
920 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
922 SDValue Shift, SDValue X,
923 X86ISelAddressMode &AM) {
924 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
925 !isa<ConstantSDNode>(Shift.getOperand(1)))
928 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
929 unsigned MaskLZ = countLeadingZeros(Mask);
930 unsigned MaskTZ = countTrailingZeros(Mask);
932 // The amount of shift we're trying to fit into the addressing mode is taken
933 // from the trailing zeros of the mask.
934 unsigned AMShiftAmt = MaskTZ;
936 // There is nothing we can do here unless the mask is removing some bits.
937 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
938 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
940 // We also need to ensure that mask is a continuous run of bits.
941 if (countTrailingOnes(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
943 // Scale the leading zero count down based on the actual size of the value.
944 // Also scale it down based on the size of the shift.
945 MaskLZ -= (64 - X.getSimpleValueType().getSizeInBits()) + ShiftAmt;
947 // The final check is to ensure that any masked out high bits of X are
948 // already known to be zero. Otherwise, the mask has a semantic impact
949 // other than masking out a couple of low bits. Unfortunately, because of
950 // the mask, zero extensions will be removed from operands in some cases.
951 // This code works extra hard to look through extensions because we can
952 // replace them with zero extensions cheaply if necessary.
953 bool ReplacingAnyExtend = false;
954 if (X.getOpcode() == ISD::ANY_EXTEND) {
955 unsigned ExtendBits = X.getSimpleValueType().getSizeInBits() -
956 X.getOperand(0).getSimpleValueType().getSizeInBits();
957 // Assume that we'll replace the any-extend with a zero-extend, and
958 // narrow the search to the extended value.
960 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
961 ReplacingAnyExtend = true;
963 APInt MaskedHighBits =
964 APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
965 APInt KnownZero, KnownOne;
966 DAG.computeKnownBits(X, KnownZero, KnownOne);
967 if (MaskedHighBits != KnownZero) return true;
969 // We've identified a pattern that can be transformed into a single shift
970 // and an addressing mode. Make it so.
971 MVT VT = N.getSimpleValueType();
972 if (ReplacingAnyExtend) {
973 assert(X.getValueType() != VT);
974 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
975 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(X), VT, X);
976 InsertDAGNode(DAG, N, NewX);
980 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);
981 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
982 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8);
983 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
985 // Insert the new nodes into the topological ordering. We must do this in
986 // a valid topological ordering as nothing is going to go back and re-sort
987 // these nodes. We continually insert before 'N' in sequence as this is
988 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
989 // hierarchy left to express.
990 InsertDAGNode(DAG, N, NewSRLAmt);
991 InsertDAGNode(DAG, N, NewSRL);
992 InsertDAGNode(DAG, N, NewSHLAmt);
993 InsertDAGNode(DAG, N, NewSHL);
994 DAG.ReplaceAllUsesWith(N, NewSHL);
996 AM.Scale = 1 << AMShiftAmt;
997 AM.IndexReg = NewSRL;
1001 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
1005 dbgs() << "MatchAddress: ";
1010 return MatchAddressBase(N, AM);
1012 // If this is already a %rip relative address, we can only merge immediates
1013 // into it. Instead of handling this in every case, we handle it here.
1014 // RIP relative addressing: %rip + 32-bit displacement!
1015 if (AM.isRIPRelative()) {
1016 // FIXME: JumpTable and ExternalSymbol address currently don't like
1017 // displacements. It isn't very important, but this should be fixed for
1019 if (!(AM.ES || AM.MCSym) && AM.JT != -1)
1022 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
1023 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
1028 switch (N.getOpcode()) {
1030 case ISD::LOCAL_RECOVER: {
1031 if (!AM.hasSymbolicDisplacement() && AM.Disp == 0)
1032 if (const auto *ESNode = dyn_cast<MCSymbolSDNode>(N.getOperand(0))) {
1033 // Use the symbol and don't prefix it.
1034 AM.MCSym = ESNode->getMCSymbol();
1039 case ISD::Constant: {
1040 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
1041 if (!FoldOffsetIntoAddress(Val, AM))
1046 case X86ISD::Wrapper:
1047 case X86ISD::WrapperRIP:
1048 if (!MatchWrapper(N, AM))
1053 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
1057 case ISD::FrameIndex:
1058 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1059 AM.Base_Reg.getNode() == nullptr &&
1060 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
1061 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
1062 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
1068 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
1072 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
1073 unsigned Val = CN->getZExtValue();
1074 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
1075 // that the base operand remains free for further matching. If
1076 // the base doesn't end up getting used, a post-processing step
1077 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1078 if (Val == 1 || Val == 2 || Val == 3) {
1079 AM.Scale = 1 << Val;
1080 SDValue ShVal = N.getNode()->getOperand(0);
1082 // Okay, we know that we have a scale by now. However, if the scaled
1083 // value is an add of something and a constant, we can fold the
1084 // constant into the disp field here.
1085 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1086 AM.IndexReg = ShVal.getNode()->getOperand(0);
1087 ConstantSDNode *AddVal =
1088 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1089 uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
1090 if (!FoldOffsetIntoAddress(Disp, AM))
1094 AM.IndexReg = ShVal;
1101 // Scale must not be used already.
1102 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1104 SDValue And = N.getOperand(0);
1105 if (And.getOpcode() != ISD::AND) break;
1106 SDValue X = And.getOperand(0);
1108 // We only handle up to 64-bit values here as those are what matter for
1109 // addressing mode optimizations.
1110 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1112 // The mask used for the transform is expected to be post-shift, but we
1113 // found the shift first so just apply the shift to the mask before passing
1115 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1116 !isa<ConstantSDNode>(And.getOperand(1)))
1118 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1120 // Try to fold the mask and shift into the scale, and return false if we
1122 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1127 case ISD::SMUL_LOHI:
1128 case ISD::UMUL_LOHI:
1129 // A mul_lohi where we need the low part can be folded as a plain multiply.
1130 if (N.getResNo() != 0) break;
1133 case X86ISD::MUL_IMM:
1134 // X*[3,5,9] -> X+X*[2,4,8]
1135 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1136 AM.Base_Reg.getNode() == nullptr &&
1137 AM.IndexReg.getNode() == nullptr) {
1139 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1140 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1141 CN->getZExtValue() == 9) {
1142 AM.Scale = unsigned(CN->getZExtValue())-1;
1144 SDValue MulVal = N.getNode()->getOperand(0);
1147 // Okay, we know that we have a scale by now. However, if the scaled
1148 // value is an add of something and a constant, we can fold the
1149 // constant into the disp field here.
1150 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1151 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1152 Reg = MulVal.getNode()->getOperand(0);
1153 ConstantSDNode *AddVal =
1154 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1155 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1156 if (FoldOffsetIntoAddress(Disp, AM))
1157 Reg = N.getNode()->getOperand(0);
1159 Reg = N.getNode()->getOperand(0);
1162 AM.IndexReg = AM.Base_Reg = Reg;
1169 // Given A-B, if A can be completely folded into the address and
1170 // the index field with the index field unused, use -B as the index.
1171 // This is a win if a has multiple parts that can be folded into
1172 // the address. Also, this saves a mov if the base register has
1173 // other uses, since it avoids a two-address sub instruction, however
1174 // it costs an additional mov if the index register has other uses.
1176 // Add an artificial use to this node so that we can keep track of
1177 // it if it gets CSE'd with a different node.
1178 HandleSDNode Handle(N);
1180 // Test if the LHS of the sub can be folded.
1181 X86ISelAddressMode Backup = AM;
1182 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1186 // Test if the index field is free for use.
1187 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1193 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1194 // If the RHS involves a register with multiple uses, this
1195 // transformation incurs an extra mov, due to the neg instruction
1196 // clobbering its operand.
1197 if (!RHS.getNode()->hasOneUse() ||
1198 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1199 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1200 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1201 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1202 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1204 // If the base is a register with multiple uses, this
1205 // transformation may save a mov.
1206 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1207 AM.Base_Reg.getNode() &&
1208 !AM.Base_Reg.getNode()->hasOneUse()) ||
1209 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1211 // If the folded LHS was interesting, this transformation saves
1212 // address arithmetic.
1213 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1214 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1215 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1217 // If it doesn't look like it may be an overall win, don't do it.
1223 // Ok, the transformation is legal and appears profitable. Go for it.
1224 SDValue Zero = CurDAG->getConstant(0, dl, N.getValueType());
1225 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1229 // Insert the new nodes into the topological ordering.
1230 InsertDAGNode(*CurDAG, N, Zero);
1231 InsertDAGNode(*CurDAG, N, Neg);
1236 // Add an artificial use to this node so that we can keep track of
1237 // it if it gets CSE'd with a different node.
1238 HandleSDNode Handle(N);
1240 X86ISelAddressMode Backup = AM;
1241 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1242 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1246 // Try again after commuting the operands.
1247 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1248 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1252 // If we couldn't fold both operands into the address at the same time,
1253 // see if we can just put each operand into a register and fold at least
1255 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1256 !AM.Base_Reg.getNode() &&
1257 !AM.IndexReg.getNode()) {
1258 N = Handle.getValue();
1259 AM.Base_Reg = N.getOperand(0);
1260 AM.IndexReg = N.getOperand(1);
1264 N = Handle.getValue();
1269 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1270 if (CurDAG->isBaseWithConstantOffset(N)) {
1271 X86ISelAddressMode Backup = AM;
1272 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1274 // Start with the LHS as an addr mode.
1275 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1276 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1283 // Perform some heroic transforms on an and of a constant-count shift
1284 // with a constant to enable use of the scaled offset field.
1286 // Scale must not be used already.
1287 if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1) break;
1289 SDValue Shift = N.getOperand(0);
1290 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1291 SDValue X = Shift.getOperand(0);
1293 // We only handle up to 64-bit values here as those are what matter for
1294 // addressing mode optimizations.
1295 if (X.getSimpleValueType().getSizeInBits() > 64) break;
1297 if (!isa<ConstantSDNode>(N.getOperand(1)))
1299 uint64_t Mask = N.getConstantOperandVal(1);
1301 // Try to fold the mask and shift into an extract and scale.
1302 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1305 // Try to fold the mask and shift directly into the scale.
1306 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1309 // Try to swap the mask and shift to place shifts which can be done as
1310 // a scale on the outside of the mask.
1311 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1317 return MatchAddressBase(N, AM);
1320 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1321 /// specified addressing mode without any further recursion.
1322 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1323 // Is the base register already occupied?
1324 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1325 // If so, check to see if the scale index register is set.
1326 if (!AM.IndexReg.getNode()) {
1332 // Otherwise, we cannot select it.
1336 // Default, generate it as a register.
1337 AM.BaseType = X86ISelAddressMode::RegBase;
1342 bool X86DAGToDAGISel::SelectVectorAddr(SDNode *Parent, SDValue N, SDValue &Base,
1343 SDValue &Scale, SDValue &Index,
1344 SDValue &Disp, SDValue &Segment) {
1346 MaskedGatherScatterSDNode *Mgs = dyn_cast<MaskedGatherScatterSDNode>(Parent);
1349 X86ISelAddressMode AM;
1350 unsigned AddrSpace = Mgs->getPointerInfo().getAddrSpace();
1351 // AddrSpace 256 -> GS, 257 -> FS.
1352 if (AddrSpace == 256)
1353 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1354 if (AddrSpace == 257)
1355 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1358 Base = Mgs->getBasePtr();
1359 Index = Mgs->getIndex();
1360 unsigned ScalarSize = Mgs->getValue().getValueType().getScalarSizeInBits();
1361 Scale = getI8Imm(ScalarSize/8, DL);
1363 // If Base is 0, the whole address is in index and the Scale is 1
1364 if (isa<ConstantSDNode>(Base)) {
1365 assert(dyn_cast<ConstantSDNode>(Base)->isNullValue() &&
1366 "Unexpected base in gather/scatter");
1367 Scale = getI8Imm(1, DL);
1368 Base = CurDAG->getRegister(0, MVT::i32);
1370 if (AM.Segment.getNode())
1371 Segment = AM.Segment;
1373 Segment = CurDAG->getRegister(0, MVT::i32);
1374 Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
1378 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1379 /// It returns the operands which make up the maximal addressing mode it can
1380 /// match by reference.
1382 /// Parent is the parent node of the addr operand that is being matched. It
1383 /// is always a load, store, atomic node, or null. It is only null when
1384 /// checking memory operands for inline asm nodes.
1385 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1386 SDValue &Scale, SDValue &Index,
1387 SDValue &Disp, SDValue &Segment) {
1388 X86ISelAddressMode AM;
1391 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1392 // that are not a MemSDNode, and thus don't have proper addrspace info.
1393 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1394 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1395 Parent->getOpcode() != X86ISD::TLSCALL && // Fixme
1396 Parent->getOpcode() != X86ISD::EH_SJLJ_SETJMP && // setjmp
1397 Parent->getOpcode() != X86ISD::EH_SJLJ_LONGJMP) { // longjmp
1398 unsigned AddrSpace =
1399 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1400 // AddrSpace 256 -> GS, 257 -> FS.
1401 if (AddrSpace == 256)
1402 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1403 if (AddrSpace == 257)
1404 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1407 if (MatchAddress(N, AM))
1410 MVT VT = N.getSimpleValueType();
1411 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1412 if (!AM.Base_Reg.getNode())
1413 AM.Base_Reg = CurDAG->getRegister(0, VT);
1416 if (!AM.IndexReg.getNode())
1417 AM.IndexReg = CurDAG->getRegister(0, VT);
1419 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1423 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1424 /// match a load whose top elements are either undef or zeros. The load flavor
1425 /// is derived from the type of N, which is either v4f32 or v2f64.
1428 /// PatternChainNode: this is the matched node that has a chain input and
1430 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1431 SDValue N, SDValue &Base,
1432 SDValue &Scale, SDValue &Index,
1433 SDValue &Disp, SDValue &Segment,
1434 SDValue &PatternNodeWithChain) {
1435 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1436 PatternNodeWithChain = N.getOperand(0);
1437 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1438 PatternNodeWithChain.hasOneUse() &&
1439 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1440 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1441 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1442 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1448 // Also handle the case where we explicitly require zeros in the top
1449 // elements. This is a vector shuffle from the zero vector.
1450 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1451 // Check to see if the top elements are all zeros (or bitcast of zeros).
1452 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1453 N.getOperand(0).getNode()->hasOneUse() &&
1454 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1455 N.getOperand(0).getOperand(0).hasOneUse() &&
1456 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1457 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1458 // Okay, this is a zero extending load. Fold it.
1459 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1460 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1462 PatternNodeWithChain = SDValue(LD, 0);
1469 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) {
1470 if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1471 uint64_t ImmVal = CN->getZExtValue();
1472 if ((uint32_t)ImmVal != (uint64_t)ImmVal)
1475 Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i64);
1479 // In static codegen with small code model, we can get the address of a label
1480 // into a register with 'movl'. TableGen has already made sure we're looking
1481 // at a label of some kind.
1482 assert(N->getOpcode() == X86ISD::Wrapper &&
1483 "Unexpected node type for MOV32ri64");
1484 N = N.getOperand(0);
1486 if (N->getOpcode() != ISD::TargetConstantPool &&
1487 N->getOpcode() != ISD::TargetJumpTable &&
1488 N->getOpcode() != ISD::TargetGlobalAddress &&
1489 N->getOpcode() != ISD::TargetExternalSymbol &&
1490 N->getOpcode() != ISD::MCSymbol &&
1491 N->getOpcode() != ISD::TargetBlockAddress)
1495 return TM.getCodeModel() == CodeModel::Small;
1498 bool X86DAGToDAGISel::SelectLEA64_32Addr(SDValue N, SDValue &Base,
1499 SDValue &Scale, SDValue &Index,
1500 SDValue &Disp, SDValue &Segment) {
1501 if (!SelectLEAAddr(N, Base, Scale, Index, Disp, Segment))
1505 RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Base);
1506 if (RN && RN->getReg() == 0)
1507 Base = CurDAG->getRegister(0, MVT::i64);
1508 else if (Base.getValueType() == MVT::i32 && !dyn_cast<FrameIndexSDNode>(Base)) {
1509 // Base could already be %rip, particularly in the x32 ABI.
1510 Base = SDValue(CurDAG->getMachineNode(
1511 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1512 CurDAG->getTargetConstant(0, DL, MVT::i64),
1514 CurDAG->getTargetConstant(X86::sub_32bit, DL, MVT::i32)),
1518 RN = dyn_cast<RegisterSDNode>(Index);
1519 if (RN && RN->getReg() == 0)
1520 Index = CurDAG->getRegister(0, MVT::i64);
1522 assert(Index.getValueType() == MVT::i32 &&
1523 "Expect to be extending 32-bit registers for use in LEA");
1524 Index = SDValue(CurDAG->getMachineNode(
1525 TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,
1526 CurDAG->getTargetConstant(0, DL, MVT::i64),
1528 CurDAG->getTargetConstant(X86::sub_32bit, DL,
1536 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1537 /// mode it matches can be cost effectively emitted as an LEA instruction.
1538 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1539 SDValue &Base, SDValue &Scale,
1540 SDValue &Index, SDValue &Disp,
1542 X86ISelAddressMode AM;
1544 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1546 SDValue Copy = AM.Segment;
1547 SDValue T = CurDAG->getRegister(0, MVT::i32);
1549 if (MatchAddress(N, AM))
1551 assert (T == AM.Segment);
1554 MVT VT = N.getSimpleValueType();
1555 unsigned Complexity = 0;
1556 if (AM.BaseType == X86ISelAddressMode::RegBase)
1557 if (AM.Base_Reg.getNode())
1560 AM.Base_Reg = CurDAG->getRegister(0, VT);
1561 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1564 if (AM.IndexReg.getNode())
1567 AM.IndexReg = CurDAG->getRegister(0, VT);
1569 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1574 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1575 // to a LEA. This is determined with some expermentation but is by no means
1576 // optimal (especially for code size consideration). LEA is nice because of
1577 // its three-address nature. Tweak the cost function again when we can run
1578 // convertToThreeAddress() at register allocation time.
1579 if (AM.hasSymbolicDisplacement()) {
1580 // For X86-64, we should always use lea to materialize RIP relative
1582 if (Subtarget->is64Bit())
1588 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1591 // If it isn't worth using an LEA, reject it.
1592 if (Complexity <= 2)
1595 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1599 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1600 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1601 SDValue &Scale, SDValue &Index,
1602 SDValue &Disp, SDValue &Segment) {
1603 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1604 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1606 X86ISelAddressMode AM;
1607 AM.GV = GA->getGlobal();
1608 AM.Disp += GA->getOffset();
1609 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1610 AM.SymbolFlags = GA->getTargetFlags();
1612 if (N.getValueType() == MVT::i32) {
1614 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1616 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1619 getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);
1624 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1625 SDValue &Base, SDValue &Scale,
1626 SDValue &Index, SDValue &Disp,
1628 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1629 !IsProfitableToFold(N, P, P) ||
1630 !IsLegalToFold(N, P, P, OptLevel))
1633 return SelectAddr(N.getNode(),
1634 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1637 /// getGlobalBaseReg - Return an SDNode that returns the value of
1638 /// the global base register. Output instructions required to
1639 /// initialize the global base register, if necessary.
1641 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1642 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1643 auto &DL = MF->getDataLayout();
1644 return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy(DL)).getNode();
1647 /// Atomic opcode table
1675 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1686 X86::LOCK_ADD64mi32,
1699 X86::LOCK_SUB64mi32,
1751 X86::LOCK_AND64mi32,
1764 X86::LOCK_XOR64mi32,
1769 // Return the target constant operand for atomic-load-op and do simple
1770 // translations, such as from atomic-load-add to lock-sub. The return value is
1771 // one of the following 3 cases:
1772 // + target-constant, the operand could be supported as a target constant.
1773 // + empty, the operand is not needed any more with the new op selected.
1774 // + non-empty, otherwise.
1775 static SDValue getAtomicLoadArithTargetConstant(SelectionDAG *CurDAG,
1777 enum AtomicOpc &Op, MVT NVT,
1779 const X86Subtarget *Subtarget) {
1780 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val)) {
1781 int64_t CNVal = CN->getSExtValue();
1782 // Quit if not 32-bit imm.
1783 if ((int32_t)CNVal != CNVal)
1785 // Quit if INT32_MIN: it would be negated as it is negative and overflow,
1786 // producing an immediate that does not fit in the 32 bits available for
1787 // an immediate operand to sub. However, it still fits in 32 bits for the
1788 // add (since it is not negated) so we can return target-constant.
1789 if (CNVal == INT32_MIN)
1790 return CurDAG->getTargetConstant(CNVal, dl, NVT);
1791 // For atomic-load-add, we could do some optimizations.
1793 // Translate to INC/DEC if ADD by 1 or -1.
1794 if (((CNVal == 1) || (CNVal == -1)) && !Subtarget->slowIncDec()) {
1795 Op = (CNVal == 1) ? INC : DEC;
1796 // No more constant operand after being translated into INC/DEC.
1799 // Translate to SUB if ADD by negative value.
1805 return CurDAG->getTargetConstant(CNVal, dl, NVT);
1808 // If the value operand is single-used, try to optimize it.
1809 if (Op == ADD && Val.hasOneUse()) {
1810 // Translate (atomic-load-add ptr (sub 0 x)) back to (lock-sub x).
1811 if (Val.getOpcode() == ISD::SUB && X86::isZeroNode(Val.getOperand(0))) {
1813 return Val.getOperand(1);
1815 // A special case for i16, which needs truncating as, in most cases, it's
1816 // promoted to i32. We will translate
1817 // (atomic-load-add (truncate (sub 0 x))) to (lock-sub (EXTRACT_SUBREG x))
1818 if (Val.getOpcode() == ISD::TRUNCATE && NVT == MVT::i16 &&
1819 Val.getOperand(0).getOpcode() == ISD::SUB &&
1820 X86::isZeroNode(Val.getOperand(0).getOperand(0))) {
1822 Val = Val.getOperand(0);
1823 return CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, NVT,
1831 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, MVT NVT) {
1832 if (Node->hasAnyUseOfValue(0))
1837 // Optimize common patterns for __sync_or_and_fetch and similar arith
1838 // operations where the result is not used. This allows us to use the "lock"
1839 // version of the arithmetic instruction.
1840 SDValue Chain = Node->getOperand(0);
1841 SDValue Ptr = Node->getOperand(1);
1842 SDValue Val = Node->getOperand(2);
1843 SDValue Base, Scale, Index, Disp, Segment;
1844 if (!SelectAddr(Node, Ptr, Base, Scale, Index, Disp, Segment))
1847 // Which index into the table.
1849 switch (Node->getOpcode()) {
1852 case ISD::ATOMIC_LOAD_OR:
1855 case ISD::ATOMIC_LOAD_AND:
1858 case ISD::ATOMIC_LOAD_XOR:
1861 case ISD::ATOMIC_LOAD_ADD:
1866 Val = getAtomicLoadArithTargetConstant(CurDAG, dl, Op, NVT, Val, Subtarget);
1867 bool isUnOp = !Val.getNode();
1868 bool isCN = Val.getNode() && (Val.getOpcode() == ISD::TargetConstant);
1871 switch (NVT.SimpleTy) {
1872 default: return nullptr;
1875 Opc = AtomicOpcTbl[Op][ConstantI8];
1877 Opc = AtomicOpcTbl[Op][I8];
1881 if (immSext8(Val.getNode()))
1882 Opc = AtomicOpcTbl[Op][SextConstantI16];
1884 Opc = AtomicOpcTbl[Op][ConstantI16];
1886 Opc = AtomicOpcTbl[Op][I16];
1890 if (immSext8(Val.getNode()))
1891 Opc = AtomicOpcTbl[Op][SextConstantI32];
1893 Opc = AtomicOpcTbl[Op][ConstantI32];
1895 Opc = AtomicOpcTbl[Op][I32];
1899 if (immSext8(Val.getNode()))
1900 Opc = AtomicOpcTbl[Op][SextConstantI64];
1901 else if (i64immSExt32(Val.getNode()))
1902 Opc = AtomicOpcTbl[Op][ConstantI64];
1904 llvm_unreachable("True 64 bits constant in SelectAtomicLoadArith");
1906 Opc = AtomicOpcTbl[Op][I64];
1910 assert(Opc != 0 && "Invalid arith lock transform!");
1912 // Building the new node.
1915 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Chain };
1916 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1918 SDValue Ops[] = { Base, Scale, Index, Disp, Segment, Val, Chain };
1919 Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops), 0);
1922 // Copying the MachineMemOperand.
1923 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1924 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1925 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1927 // We need to have two outputs as that is what the original instruction had.
1928 // So we add a dummy, undefined output. This is safe as we checked first
1929 // that no-one uses our output anyway.
1930 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1932 SDValue RetVals[] = { Undef, Ret };
1933 return CurDAG->getMergeValues(RetVals, dl).getNode();
1936 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1937 /// any uses which require the SF or OF bits to be accurate.
1938 static bool HasNoSignedComparisonUses(SDNode *N) {
1939 // Examine each user of the node.
1940 for (SDNode::use_iterator UI = N->use_begin(),
1941 UE = N->use_end(); UI != UE; ++UI) {
1942 // Only examine CopyToReg uses.
1943 if (UI->getOpcode() != ISD::CopyToReg)
1945 // Only examine CopyToReg uses that copy to EFLAGS.
1946 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1949 // Examine each user of the CopyToReg use.
1950 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1951 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1952 // Only examine the Flag result.
1953 if (FlagUI.getUse().getResNo() != 1) continue;
1954 // Anything unusual: assume conservatively.
1955 if (!FlagUI->isMachineOpcode()) return false;
1956 // Examine the opcode of the user.
1957 switch (FlagUI->getMachineOpcode()) {
1958 // These comparisons don't treat the most significant bit specially.
1959 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1960 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1961 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1962 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1963 case X86::JA_1: case X86::JAE_1: case X86::JB_1: case X86::JBE_1:
1964 case X86::JE_1: case X86::JNE_1: case X86::JP_1: case X86::JNP_1:
1965 case X86::CMOVA16rr: case X86::CMOVA16rm:
1966 case X86::CMOVA32rr: case X86::CMOVA32rm:
1967 case X86::CMOVA64rr: case X86::CMOVA64rm:
1968 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1969 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1970 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1971 case X86::CMOVB16rr: case X86::CMOVB16rm:
1972 case X86::CMOVB32rr: case X86::CMOVB32rm:
1973 case X86::CMOVB64rr: case X86::CMOVB64rm:
1974 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1975 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1976 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1977 case X86::CMOVE16rr: case X86::CMOVE16rm:
1978 case X86::CMOVE32rr: case X86::CMOVE32rm:
1979 case X86::CMOVE64rr: case X86::CMOVE64rm:
1980 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1981 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1982 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1983 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1984 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1985 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1986 case X86::CMOVP16rr: case X86::CMOVP16rm:
1987 case X86::CMOVP32rr: case X86::CMOVP32rm:
1988 case X86::CMOVP64rr: case X86::CMOVP64rm:
1990 // Anything else: assume conservatively.
1991 default: return false;
1998 /// isLoadIncOrDecStore - Check whether or not the chain ending in StoreNode
1999 /// is suitable for doing the {load; increment or decrement; store} to modify
2001 static bool isLoadIncOrDecStore(StoreSDNode *StoreNode, unsigned Opc,
2002 SDValue StoredVal, SelectionDAG *CurDAG,
2003 LoadSDNode* &LoadNode, SDValue &InputChain) {
2005 // is the value stored the result of a DEC or INC?
2006 if (!(Opc == X86ISD::DEC || Opc == X86ISD::INC)) return false;
2008 // is the stored value result 0 of the load?
2009 if (StoredVal.getResNo() != 0) return false;
2011 // are there other uses of the loaded value than the inc or dec?
2012 if (!StoredVal.getNode()->hasNUsesOfValue(1, 0)) return false;
2014 // is the store non-extending and non-indexed?
2015 if (!ISD::isNormalStore(StoreNode) || StoreNode->isNonTemporal())
2018 SDValue Load = StoredVal->getOperand(0);
2019 // Is the stored value a non-extending and non-indexed load?
2020 if (!ISD::isNormalLoad(Load.getNode())) return false;
2022 // Return LoadNode by reference.
2023 LoadNode = cast<LoadSDNode>(Load);
2024 // is the size of the value one that we can handle? (i.e. 64, 32, 16, or 8)
2025 EVT LdVT = LoadNode->getMemoryVT();
2026 if (LdVT != MVT::i64 && LdVT != MVT::i32 && LdVT != MVT::i16 &&
2030 // Is store the only read of the loaded value?
2031 if (!Load.hasOneUse())
2034 // Is the address of the store the same as the load?
2035 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() ||
2036 LoadNode->getOffset() != StoreNode->getOffset())
2039 // Check if the chain is produced by the load or is a TokenFactor with
2040 // the load output chain as an operand. Return InputChain by reference.
2041 SDValue Chain = StoreNode->getChain();
2043 bool ChainCheck = false;
2044 if (Chain == Load.getValue(1)) {
2046 InputChain = LoadNode->getChain();
2047 } else if (Chain.getOpcode() == ISD::TokenFactor) {
2048 SmallVector<SDValue, 4> ChainOps;
2049 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) {
2050 SDValue Op = Chain.getOperand(i);
2051 if (Op == Load.getValue(1)) {
2056 // Make sure using Op as part of the chain would not cause a cycle here.
2057 // In theory, we could check whether the chain node is a predecessor of
2058 // the load. But that can be very expensive. Instead visit the uses and
2059 // make sure they all have smaller node id than the load.
2060 int LoadId = LoadNode->getNodeId();
2061 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
2062 UE = UI->use_end(); UI != UE; ++UI) {
2063 if (UI.getUse().getResNo() != 0)
2065 if (UI->getNodeId() > LoadId)
2069 ChainOps.push_back(Op);
2073 // Make a new TokenFactor with all the other input chains except
2075 InputChain = CurDAG->getNode(ISD::TokenFactor, SDLoc(Chain),
2076 MVT::Other, ChainOps);
2084 /// getFusedLdStOpcode - Get the appropriate X86 opcode for an in memory
2085 /// increment or decrement. Opc should be X86ISD::DEC or X86ISD::INC.
2086 static unsigned getFusedLdStOpcode(EVT &LdVT, unsigned Opc) {
2087 if (Opc == X86ISD::DEC) {
2088 if (LdVT == MVT::i64) return X86::DEC64m;
2089 if (LdVT == MVT::i32) return X86::DEC32m;
2090 if (LdVT == MVT::i16) return X86::DEC16m;
2091 if (LdVT == MVT::i8) return X86::DEC8m;
2093 assert(Opc == X86ISD::INC && "unrecognized opcode");
2094 if (LdVT == MVT::i64) return X86::INC64m;
2095 if (LdVT == MVT::i32) return X86::INC32m;
2096 if (LdVT == MVT::i16) return X86::INC16m;
2097 if (LdVT == MVT::i8) return X86::INC8m;
2099 llvm_unreachable("unrecognized size for LdVT");
2102 /// SelectGather - Customized ISel for GATHER operations.
2104 SDNode *X86DAGToDAGISel::SelectGather(SDNode *Node, unsigned Opc) {
2105 // Operands of Gather: VSrc, Base, VIdx, VMask, Scale
2106 SDValue Chain = Node->getOperand(0);
2107 SDValue VSrc = Node->getOperand(2);
2108 SDValue Base = Node->getOperand(3);
2109 SDValue VIdx = Node->getOperand(4);
2110 SDValue VMask = Node->getOperand(5);
2111 ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
2115 SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),
2120 // Memory Operands: Base, Scale, Index, Disp, Segment
2121 SDValue Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);
2122 SDValue Segment = CurDAG->getRegister(0, MVT::i32);
2123 const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue(), DL), VIdx,
2124 Disp, Segment, VMask, Chain};
2125 SDNode *ResNode = CurDAG->getMachineNode(Opc, DL, VTs, Ops);
2126 // Node has 2 outputs: VDst and MVT::Other.
2127 // ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.
2128 // We replace VDst of Node with VDst of ResNode, and Other of Node with Other
2130 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
2131 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 2));
2135 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
2136 MVT NVT = Node->getSimpleValueType(0);
2138 unsigned Opcode = Node->getOpcode();
2141 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
2143 if (Node->isMachineOpcode()) {
2144 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
2145 Node->setNodeId(-1);
2146 return nullptr; // Already selected.
2151 case ISD::INTRINSIC_W_CHAIN: {
2152 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2155 case Intrinsic::x86_avx2_gather_d_pd:
2156 case Intrinsic::x86_avx2_gather_d_pd_256:
2157 case Intrinsic::x86_avx2_gather_q_pd:
2158 case Intrinsic::x86_avx2_gather_q_pd_256:
2159 case Intrinsic::x86_avx2_gather_d_ps:
2160 case Intrinsic::x86_avx2_gather_d_ps_256:
2161 case Intrinsic::x86_avx2_gather_q_ps:
2162 case Intrinsic::x86_avx2_gather_q_ps_256:
2163 case Intrinsic::x86_avx2_gather_d_q:
2164 case Intrinsic::x86_avx2_gather_d_q_256:
2165 case Intrinsic::x86_avx2_gather_q_q:
2166 case Intrinsic::x86_avx2_gather_q_q_256:
2167 case Intrinsic::x86_avx2_gather_d_d:
2168 case Intrinsic::x86_avx2_gather_d_d_256:
2169 case Intrinsic::x86_avx2_gather_q_d:
2170 case Intrinsic::x86_avx2_gather_q_d_256: {
2171 if (!Subtarget->hasAVX2())
2175 default: llvm_unreachable("Impossible intrinsic");
2176 case Intrinsic::x86_avx2_gather_d_pd: Opc = X86::VGATHERDPDrm; break;
2177 case Intrinsic::x86_avx2_gather_d_pd_256: Opc = X86::VGATHERDPDYrm; break;
2178 case Intrinsic::x86_avx2_gather_q_pd: Opc = X86::VGATHERQPDrm; break;
2179 case Intrinsic::x86_avx2_gather_q_pd_256: Opc = X86::VGATHERQPDYrm; break;
2180 case Intrinsic::x86_avx2_gather_d_ps: Opc = X86::VGATHERDPSrm; break;
2181 case Intrinsic::x86_avx2_gather_d_ps_256: Opc = X86::VGATHERDPSYrm; break;
2182 case Intrinsic::x86_avx2_gather_q_ps: Opc = X86::VGATHERQPSrm; break;
2183 case Intrinsic::x86_avx2_gather_q_ps_256: Opc = X86::VGATHERQPSYrm; break;
2184 case Intrinsic::x86_avx2_gather_d_q: Opc = X86::VPGATHERDQrm; break;
2185 case Intrinsic::x86_avx2_gather_d_q_256: Opc = X86::VPGATHERDQYrm; break;
2186 case Intrinsic::x86_avx2_gather_q_q: Opc = X86::VPGATHERQQrm; break;
2187 case Intrinsic::x86_avx2_gather_q_q_256: Opc = X86::VPGATHERQQYrm; break;
2188 case Intrinsic::x86_avx2_gather_d_d: Opc = X86::VPGATHERDDrm; break;
2189 case Intrinsic::x86_avx2_gather_d_d_256: Opc = X86::VPGATHERDDYrm; break;
2190 case Intrinsic::x86_avx2_gather_q_d: Opc = X86::VPGATHERQDrm; break;
2191 case Intrinsic::x86_avx2_gather_q_d_256: Opc = X86::VPGATHERQDYrm; break;
2193 SDNode *RetVal = SelectGather(Node, Opc);
2195 // We already called ReplaceUses inside SelectGather.
2202 case X86ISD::GlobalBaseReg:
2203 return getGlobalBaseReg();
2205 case X86ISD::SHRUNKBLEND: {
2206 // SHRUNKBLEND selects like a regular VSELECT.
2207 SDValue VSelect = CurDAG->getNode(
2208 ISD::VSELECT, SDLoc(Node), Node->getValueType(0), Node->getOperand(0),
2209 Node->getOperand(1), Node->getOperand(2));
2210 ReplaceUses(SDValue(Node, 0), VSelect);
2211 SelectCode(VSelect.getNode());
2212 // We already called ReplaceUses.
2216 case ISD::ATOMIC_LOAD_XOR:
2217 case ISD::ATOMIC_LOAD_AND:
2218 case ISD::ATOMIC_LOAD_OR:
2219 case ISD::ATOMIC_LOAD_ADD: {
2220 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
2228 // For operations of the form (x << C1) op C2, check if we can use a smaller
2229 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
2230 SDValue N0 = Node->getOperand(0);
2231 SDValue N1 = Node->getOperand(1);
2233 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
2236 // i8 is unshrinkable, i16 should be promoted to i32.
2237 if (NVT != MVT::i32 && NVT != MVT::i64)
2240 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
2241 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
2242 if (!Cst || !ShlCst)
2245 int64_t Val = Cst->getSExtValue();
2246 uint64_t ShlVal = ShlCst->getZExtValue();
2248 // Make sure that we don't change the operation by removing bits.
2249 // This only matters for OR and XOR, AND is unaffected.
2250 uint64_t RemovedBitsMask = (1ULL << ShlVal) - 1;
2251 if (Opcode != ISD::AND && (Val & RemovedBitsMask) != 0)
2254 unsigned ShlOp, AddOp, Op;
2257 // Check the minimum bitwidth for the new constant.
2258 // TODO: AND32ri is the same as AND64ri32 with zext imm.
2259 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
2260 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
2261 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
2263 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
2266 // Bail if there is no smaller encoding.
2270 switch (NVT.SimpleTy) {
2271 default: llvm_unreachable("Unsupported VT!");
2273 assert(CstVT == MVT::i8);
2274 ShlOp = X86::SHL32ri;
2275 AddOp = X86::ADD32rr;
2278 default: llvm_unreachable("Impossible opcode");
2279 case ISD::AND: Op = X86::AND32ri8; break;
2280 case ISD::OR: Op = X86::OR32ri8; break;
2281 case ISD::XOR: Op = X86::XOR32ri8; break;
2285 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
2286 ShlOp = X86::SHL64ri;
2287 AddOp = X86::ADD64rr;
2290 default: llvm_unreachable("Impossible opcode");
2291 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
2292 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
2293 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
2298 // Emit the smaller op and the shift.
2299 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, dl, CstVT);
2300 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
2302 return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),
2304 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
2305 getI8Imm(ShlVal, dl));
2308 case X86ISD::SMUL8: {
2309 SDValue N0 = Node->getOperand(0);
2310 SDValue N1 = Node->getOperand(1);
2312 Opc = (Opcode == X86ISD::SMUL8 ? X86::IMUL8r : X86::MUL8r);
2314 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, X86::AL,
2315 N0, SDValue()).getValue(1);
2317 SDVTList VTs = CurDAG->getVTList(NVT, MVT::i32);
2318 SDValue Ops[] = {N1, InFlag};
2319 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2321 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2322 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2326 case X86ISD::UMUL: {
2327 SDValue N0 = Node->getOperand(0);
2328 SDValue N1 = Node->getOperand(1);
2331 switch (NVT.SimpleTy) {
2332 default: llvm_unreachable("Unsupported VT!");
2333 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
2334 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
2335 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
2336 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
2339 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2340 N0, SDValue()).getValue(1);
2342 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
2343 SDValue Ops[] = {N1, InFlag};
2344 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2346 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
2347 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
2348 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
2352 case ISD::SMUL_LOHI:
2353 case ISD::UMUL_LOHI: {
2354 SDValue N0 = Node->getOperand(0);
2355 SDValue N1 = Node->getOperand(1);
2357 bool isSigned = Opcode == ISD::SMUL_LOHI;
2358 bool hasBMI2 = Subtarget->hasBMI2();
2360 switch (NVT.SimpleTy) {
2361 default: llvm_unreachable("Unsupported VT!");
2362 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2363 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2364 case MVT::i32: Opc = hasBMI2 ? X86::MULX32rr : X86::MUL32r;
2365 MOpc = hasBMI2 ? X86::MULX32rm : X86::MUL32m; break;
2366 case MVT::i64: Opc = hasBMI2 ? X86::MULX64rr : X86::MUL64r;
2367 MOpc = hasBMI2 ? X86::MULX64rm : X86::MUL64m; break;
2370 switch (NVT.SimpleTy) {
2371 default: llvm_unreachable("Unsupported VT!");
2372 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2373 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2374 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2375 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2379 unsigned SrcReg, LoReg, HiReg;
2381 default: llvm_unreachable("Unknown MUL opcode!");
2384 SrcReg = LoReg = X86::AL; HiReg = X86::AH;
2388 SrcReg = LoReg = X86::AX; HiReg = X86::DX;
2392 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX;
2396 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX;
2399 SrcReg = X86::EDX; LoReg = HiReg = 0;
2402 SrcReg = X86::RDX; LoReg = HiReg = 0;
2406 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2407 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2408 // Multiply is commmutative.
2410 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2415 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SrcReg,
2416 N0, SDValue()).getValue(1);
2417 SDValue ResHi, ResLo;
2421 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2423 if (MOpc == X86::MULX32rm || MOpc == X86::MULX64rm) {
2424 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Other, MVT::Glue);
2425 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2426 ResHi = SDValue(CNode, 0);
2427 ResLo = SDValue(CNode, 1);
2428 Chain = SDValue(CNode, 2);
2429 InFlag = SDValue(CNode, 3);
2431 SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
2432 SDNode *CNode = CurDAG->getMachineNode(MOpc, dl, VTs, Ops);
2433 Chain = SDValue(CNode, 0);
2434 InFlag = SDValue(CNode, 1);
2437 // Update the chain.
2438 ReplaceUses(N1.getValue(1), Chain);
2440 SDValue Ops[] = { N1, InFlag };
2441 if (Opc == X86::MULX32rr || Opc == X86::MULX64rr) {
2442 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::Glue);
2443 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2444 ResHi = SDValue(CNode, 0);
2445 ResLo = SDValue(CNode, 1);
2446 InFlag = SDValue(CNode, 2);
2448 SDVTList VTs = CurDAG->getVTList(MVT::Glue);
2449 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops);
2450 InFlag = SDValue(CNode, 0);
2454 // Prevent use of AH in a REX instruction by referencing AX instead.
2455 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2456 !SDValue(Node, 1).use_empty()) {
2457 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2458 X86::AX, MVT::i16, InFlag);
2459 InFlag = Result.getValue(2);
2460 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2462 if (!SDValue(Node, 0).use_empty())
2463 ReplaceUses(SDValue(Node, 1),
2464 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2466 // Shift AX down 8 bits.
2467 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2469 CurDAG->getTargetConstant(8, dl, MVT::i8)),
2471 // Then truncate it down to i8.
2472 ReplaceUses(SDValue(Node, 1),
2473 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2475 // Copy the low half of the result, if it is needed.
2476 if (!SDValue(Node, 0).use_empty()) {
2477 if (!ResLo.getNode()) {
2478 assert(LoReg && "Register for low half is not defined!");
2479 ResLo = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, LoReg, NVT,
2481 InFlag = ResLo.getValue(2);
2483 ReplaceUses(SDValue(Node, 0), ResLo);
2484 DEBUG(dbgs() << "=> "; ResLo.getNode()->dump(CurDAG); dbgs() << '\n');
2486 // Copy the high half of the result, if it is needed.
2487 if (!SDValue(Node, 1).use_empty()) {
2488 if (!ResHi.getNode()) {
2489 assert(HiReg && "Register for high half is not defined!");
2490 ResHi = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT,
2492 InFlag = ResHi.getValue(2);
2494 ReplaceUses(SDValue(Node, 1), ResHi);
2495 DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
2503 case X86ISD::SDIVREM8_SEXT_HREG:
2504 case X86ISD::UDIVREM8_ZEXT_HREG: {
2505 SDValue N0 = Node->getOperand(0);
2506 SDValue N1 = Node->getOperand(1);
2508 bool isSigned = (Opcode == ISD::SDIVREM ||
2509 Opcode == X86ISD::SDIVREM8_SEXT_HREG);
2511 switch (NVT.SimpleTy) {
2512 default: llvm_unreachable("Unsupported VT!");
2513 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2514 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2515 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2516 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2519 switch (NVT.SimpleTy) {
2520 default: llvm_unreachable("Unsupported VT!");
2521 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2522 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2523 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2524 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2528 unsigned LoReg, HiReg, ClrReg;
2529 unsigned SExtOpcode;
2530 switch (NVT.SimpleTy) {
2531 default: llvm_unreachable("Unsupported VT!");
2533 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2534 SExtOpcode = X86::CBW;
2537 LoReg = X86::AX; HiReg = X86::DX;
2539 SExtOpcode = X86::CWD;
2542 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2543 SExtOpcode = X86::CDQ;
2546 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2547 SExtOpcode = X86::CQO;
2551 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2552 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2553 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2556 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2557 // Special case for div8, just use a move with zero extension to AX to
2558 // clear the upper 8 bits (AH).
2559 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2560 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2561 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2563 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2564 MVT::Other, Ops), 0);
2565 Chain = Move.getValue(1);
2566 ReplaceUses(N0.getValue(1), Chain);
2569 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2570 Chain = CurDAG->getEntryNode();
2572 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2573 InFlag = Chain.getValue(1);
2576 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2577 LoReg, N0, SDValue()).getValue(1);
2578 if (isSigned && !signBitIsZero) {
2579 // Sign extend the low part into the high part.
2581 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2583 // Zero out the high part, effectively zero extending the input.
2584 SDValue ClrNode = SDValue(CurDAG->getMachineNode(X86::MOV32r0, dl, NVT), 0);
2585 switch (NVT.SimpleTy) {
2588 SDValue(CurDAG->getMachineNode(
2589 TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,
2590 CurDAG->getTargetConstant(X86::sub_16bit, dl,
2598 SDValue(CurDAG->getMachineNode(
2599 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2600 CurDAG->getTargetConstant(0, dl, MVT::i64), ClrNode,
2601 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2606 llvm_unreachable("Unexpected division source");
2609 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2610 ClrNode, InFlag).getValue(1);
2615 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2618 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops);
2619 InFlag = SDValue(CNode, 1);
2620 // Update the chain.
2621 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2624 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2627 // Prevent use of AH in a REX instruction by explicitly copying it to
2628 // an ABCD_L register.
2630 // The current assumption of the register allocator is that isel
2631 // won't generate explicit references to the GR8_ABCD_H registers. If
2632 // the allocator and/or the backend get enhanced to be more robust in
2633 // that regard, this can be, and should be, removed.
2634 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) {
2635 SDValue AHCopy = CurDAG->getRegister(X86::AH, MVT::i8);
2636 unsigned AHExtOpcode =
2637 isSigned ? X86::MOVSX32_NOREXrr8 : X86::MOVZX32_NOREXrr8;
2639 SDNode *RNode = CurDAG->getMachineNode(AHExtOpcode, dl, MVT::i32,
2640 MVT::Glue, AHCopy, InFlag);
2641 SDValue Result(RNode, 0);
2642 InFlag = SDValue(RNode, 1);
2644 if (Opcode == X86ISD::UDIVREM8_ZEXT_HREG ||
2645 Opcode == X86ISD::SDIVREM8_SEXT_HREG) {
2646 if (Node->getValueType(1) == MVT::i64) {
2647 // It's not possible to directly movsx AH to a 64bit register, because
2648 // the latter needs the REX prefix, but the former can't have it.
2649 assert(Opcode != X86ISD::SDIVREM8_SEXT_HREG &&
2650 "Unexpected i64 sext of h-register");
2652 SDValue(CurDAG->getMachineNode(
2653 TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,
2654 CurDAG->getTargetConstant(0, dl, MVT::i64), Result,
2655 CurDAG->getTargetConstant(X86::sub_32bit, dl,
2661 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result);
2663 ReplaceUses(SDValue(Node, 1), Result);
2664 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2666 // Copy the division (low) result, if it is needed.
2667 if (!SDValue(Node, 0).use_empty()) {
2668 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2669 LoReg, NVT, InFlag);
2670 InFlag = Result.getValue(2);
2671 ReplaceUses(SDValue(Node, 0), Result);
2672 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2674 // Copy the remainder (high) result, if it is needed.
2675 if (!SDValue(Node, 1).use_empty()) {
2676 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2677 HiReg, NVT, InFlag);
2678 InFlag = Result.getValue(2);
2679 ReplaceUses(SDValue(Node, 1), Result);
2680 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2687 // Sometimes a SUB is used to perform comparison.
2688 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0))
2689 // This node is not a CMP.
2691 SDValue N0 = Node->getOperand(0);
2692 SDValue N1 = Node->getOperand(1);
2694 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2695 HasNoSignedComparisonUses(Node))
2696 N0 = N0.getOperand(0);
2698 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2699 // use a smaller encoding.
2700 // Look past the truncate if CMP is the only use of it.
2701 if ((N0.getNode()->getOpcode() == ISD::AND ||
2702 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2703 N0.getNode()->hasOneUse() &&
2704 N0.getValueType() != MVT::i8 &&
2705 X86::isZeroNode(N1)) {
2706 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2709 // For example, convert "testl %eax, $8" to "testb %al, $8"
2710 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2711 (!(C->getZExtValue() & 0x80) ||
2712 HasNoSignedComparisonUses(Node))) {
2713 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, MVT::i8);
2714 SDValue Reg = N0.getNode()->getOperand(0);
2716 // On x86-32, only the ABCD registers have 8-bit subregisters.
2717 if (!Subtarget->is64Bit()) {
2718 const TargetRegisterClass *TRC;
2719 switch (N0.getSimpleValueType().SimpleTy) {
2720 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2721 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2722 default: llvm_unreachable("Unsupported TEST operand type!");
2724 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2725 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2726 Reg.getValueType(), Reg, RC), 0);
2729 // Extract the l-register.
2730 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2734 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32,
2736 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2737 // one, do not call ReplaceAllUsesWith.
2738 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2739 SDValue(NewNode, 0));
2743 // For example, "testl %eax, $2048" to "testb %ah, $8".
2744 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2745 (!(C->getZExtValue() & 0x8000) ||
2746 HasNoSignedComparisonUses(Node))) {
2747 // Shift the immediate right by 8 bits.
2748 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2750 SDValue Reg = N0.getNode()->getOperand(0);
2752 // Put the value in an ABCD register.
2753 const TargetRegisterClass *TRC;
2754 switch (N0.getSimpleValueType().SimpleTy) {
2755 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2756 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2757 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2758 default: llvm_unreachable("Unsupported TEST operand type!");
2760 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);
2761 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2762 Reg.getValueType(), Reg, RC), 0);
2764 // Extract the h-register.
2765 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2768 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2769 // target GR8_NOREX registers, so make sure the register class is
2771 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl,
2772 MVT::i32, Subreg, ShiftedImm);
2773 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2774 // one, do not call ReplaceAllUsesWith.
2775 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2776 SDValue(NewNode, 0));
2780 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2781 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2782 N0.getValueType() != MVT::i16 &&
2783 (!(C->getZExtValue() & 0x8000) ||
2784 HasNoSignedComparisonUses(Node))) {
2785 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2787 SDValue Reg = N0.getNode()->getOperand(0);
2789 // Extract the 16-bit subregister.
2790 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2794 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32,
2796 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2797 // one, do not call ReplaceAllUsesWith.
2798 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2799 SDValue(NewNode, 0));
2803 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2804 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2805 N0.getValueType() == MVT::i64 &&
2806 (!(C->getZExtValue() & 0x80000000) ||
2807 HasNoSignedComparisonUses(Node))) {
2808 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,
2810 SDValue Reg = N0.getNode()->getOperand(0);
2812 // Extract the 32-bit subregister.
2813 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2817 SDNode *NewNode = CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32,
2819 // Replace SUB|CMP with TEST, since SUB has two outputs while TEST has
2820 // one, do not call ReplaceAllUsesWith.
2821 ReplaceUses(SDValue(Node, (Opcode == X86ISD::SUB ? 1 : 0)),
2822 SDValue(NewNode, 0));
2829 // Change a chain of {load; incr or dec; store} of the same value into
2830 // a simple increment or decrement through memory of that value, if the
2831 // uses of the modified value and its address are suitable.
2832 // The DEC64m tablegen pattern is currently not able to match the case where
2833 // the EFLAGS on the original DEC are used. (This also applies to
2834 // {INC,DEC}X{64,32,16,8}.)
2835 // We'll need to improve tablegen to allow flags to be transferred from a
2836 // node in the pattern to the result node. probably with a new keyword
2837 // for example, we have this
2838 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2839 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2840 // (implicit EFLAGS)]>;
2841 // but maybe need something like this
2842 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2843 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2844 // (transferrable EFLAGS)]>;
2846 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2847 SDValue StoredVal = StoreNode->getOperand(1);
2848 unsigned Opc = StoredVal->getOpcode();
2850 LoadSDNode *LoadNode = nullptr;
2852 if (!isLoadIncOrDecStore(StoreNode, Opc, StoredVal, CurDAG,
2853 LoadNode, InputChain))
2856 SDValue Base, Scale, Index, Disp, Segment;
2857 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2858 Base, Scale, Index, Disp, Segment))
2861 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2862 MemOp[0] = StoreNode->getMemOperand();
2863 MemOp[1] = LoadNode->getMemOperand();
2864 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2865 EVT LdVT = LoadNode->getMemoryVT();
2866 unsigned newOpc = getFusedLdStOpcode(LdVT, Opc);
2867 MachineSDNode *Result = CurDAG->getMachineNode(newOpc,
2869 MVT::i32, MVT::Other, Ops);
2870 Result->setMemRefs(MemOp, MemOp + 2);
2872 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2873 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2879 SDNode *ResNode = SelectCode(Node);
2881 DEBUG(dbgs() << "=> ";
2882 if (ResNode == nullptr || ResNode == Node)
2885 ResNode->dump(CurDAG);
2891 bool X86DAGToDAGISel::
2892 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
2893 std::vector<SDValue> &OutOps) {
2894 SDValue Op0, Op1, Op2, Op3, Op4;
2895 switch (ConstraintID) {
2897 llvm_unreachable("Unexpected asm memory constraint");
2898 case InlineAsm::Constraint_i:
2899 // FIXME: It seems strange that 'i' is needed here since it's supposed to
2900 // be an immediate and not a memory constraint.
2902 case InlineAsm::Constraint_o: // offsetable ??
2903 case InlineAsm::Constraint_v: // not offsetable ??
2904 case InlineAsm::Constraint_m: // memory
2905 case InlineAsm::Constraint_X:
2906 if (!SelectAddr(nullptr, Op, Op0, Op1, Op2, Op3, Op4))
2911 OutOps.push_back(Op0);
2912 OutOps.push_back(Op1);
2913 OutOps.push_back(Op2);
2914 OutOps.push_back(Op3);
2915 OutOps.push_back(Op4);
2919 /// createX86ISelDag - This pass converts a legalized DAG into a
2920 /// X86-specific DAG, ready for instruction scheduling.
2922 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2923 CodeGenOpt::Level OptLevel) {
2924 return new X86DAGToDAGISel(TM, OptLevel);