1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a DAG pattern matching instruction selector for X86,
11 // converting from a legalized dag to a X86 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86RegisterInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Instructions.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/FunctionLoweringInfo.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CFG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/Statistic.h"
42 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor");
44 //===----------------------------------------------------------------------===//
45 // Pattern Matcher Implementation
46 //===----------------------------------------------------------------------===//
49 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
50 /// SDValue's instead of register numbers for the leaves of the matched
52 struct X86ISelAddressMode {
58 // This is really a union, discriminated by BaseType!
66 const GlobalValue *GV;
68 const BlockAddress *BlockAddr;
71 unsigned Align; // CP alignment.
72 unsigned char SymbolFlags; // X86II::MO_*
75 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0),
76 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0),
77 SymbolFlags(X86II::MO_NO_FLAG) {
80 bool hasSymbolicDisplacement() const {
81 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0;
84 bool hasBaseOrIndexReg() const {
85 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0;
88 /// isRIPRelative - Return true if this addressing mode is already RIP
90 bool isRIPRelative() const {
91 if (BaseType != RegBase) return false;
92 if (RegisterSDNode *RegNode =
93 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode()))
94 return RegNode->getReg() == X86::RIP;
98 void setBaseReg(SDValue Reg) {
104 dbgs() << "X86ISelAddressMode " << this << '\n';
105 dbgs() << "Base_Reg ";
106 if (Base_Reg.getNode() != 0)
107 Base_Reg.getNode()->dump();
110 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n'
111 << " Scale" << Scale << '\n'
113 if (IndexReg.getNode() != 0)
114 IndexReg.getNode()->dump();
117 dbgs() << " Disp " << Disp << '\n'
134 dbgs() << " JT" << JT << " Align" << Align << '\n';
140 //===--------------------------------------------------------------------===//
141 /// ISel - X86 specific code to select X86 machine instructions for
142 /// SelectionDAG operations.
144 class X86DAGToDAGISel : public SelectionDAGISel {
145 /// X86Lowering - This object fully describes how to lower LLVM code to an
146 /// X86-specific SelectionDAG.
147 const X86TargetLowering &X86Lowering;
149 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
150 /// make the right decision when generating code for different targets.
151 const X86Subtarget *Subtarget;
153 /// OptForSize - If true, selector should try to optimize for code size
154 /// instead of performance.
158 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
159 : SelectionDAGISel(tm, OptLevel),
160 X86Lowering(*tm.getTargetLowering()),
161 Subtarget(&tm.getSubtarget<X86Subtarget>()),
164 virtual const char *getPassName() const {
165 return "X86 DAG->DAG Instruction Selection";
168 virtual void EmitFunctionEntryCode();
170 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
172 virtual void PreprocessISelDAG();
174 inline bool immSext8(SDNode *N) const {
175 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
178 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
179 // sign extended field.
180 inline bool i64immSExt32(SDNode *N) const {
181 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
182 return (int64_t)v == (int32_t)v;
185 // Include the pieces autogenerated from the target description.
186 #include "X86GenDAGISel.inc"
189 SDNode *Select(SDNode *N);
190 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
191 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT);
192 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT);
194 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM);
195 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM);
196 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
197 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
198 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
200 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM);
201 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
202 SDValue &Scale, SDValue &Index, SDValue &Disp,
204 bool SelectLEAAddr(SDValue N, SDValue &Base,
205 SDValue &Scale, SDValue &Index, SDValue &Disp,
207 bool SelectTLSADDRAddr(SDValue N, SDValue &Base,
208 SDValue &Scale, SDValue &Index, SDValue &Disp,
210 bool SelectScalarSSELoad(SDNode *Root, SDValue N,
211 SDValue &Base, SDValue &Scale,
212 SDValue &Index, SDValue &Disp,
214 SDValue &NodeWithChain);
216 bool TryFoldLoad(SDNode *P, SDValue N,
217 SDValue &Base, SDValue &Scale,
218 SDValue &Index, SDValue &Disp,
221 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
222 /// inline asm expressions.
223 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
225 std::vector<SDValue> &OutOps);
227 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
229 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,
230 SDValue &Scale, SDValue &Index,
231 SDValue &Disp, SDValue &Segment) {
232 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
233 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) :
235 Scale = getI8Imm(AM.Scale);
237 // These are 32-bit even in 64-bit mode since RIP relative offset
240 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(),
244 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
245 AM.Align, AM.Disp, AM.SymbolFlags);
247 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
248 else if (AM.JT != -1)
249 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
250 else if (AM.BlockAddr)
251 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
252 true, AM.SymbolFlags);
254 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
256 if (AM.Segment.getNode())
257 Segment = AM.Segment;
259 Segment = CurDAG->getRegister(0, MVT::i32);
262 /// getI8Imm - Return a target constant with the specified value, of type
264 inline SDValue getI8Imm(unsigned Imm) {
265 return CurDAG->getTargetConstant(Imm, MVT::i8);
268 /// getI32Imm - Return a target constant with the specified value, of type
270 inline SDValue getI32Imm(unsigned Imm) {
271 return CurDAG->getTargetConstant(Imm, MVT::i32);
274 /// getGlobalBaseReg - Return an SDNode that returns the value of
275 /// the global base register. Output instructions required to
276 /// initialize the global base register, if necessary.
278 SDNode *getGlobalBaseReg();
280 /// getTargetMachine - Return a reference to the TargetMachine, casted
281 /// to the target-specific type.
282 const X86TargetMachine &getTargetMachine() {
283 return static_cast<const X86TargetMachine &>(TM);
286 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted
287 /// to the target-specific type.
288 const X86InstrInfo *getInstrInfo() {
289 return getTargetMachine().getInstrInfo();
296 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
297 if (OptLevel == CodeGenOpt::None) return false;
302 if (N.getOpcode() != ISD::LOAD)
305 // If N is a load, do additional profitability checks.
307 switch (U->getOpcode()) {
320 SDValue Op1 = U->getOperand(1);
322 // If the other operand is a 8-bit immediate we should fold the immediate
323 // instead. This reduces code size.
325 // movl 4(%esp), %eax
329 // addl 4(%esp), %eax
330 // The former is 2 bytes shorter. In case where the increment is 1, then
331 // the saving can be 4 bytes (by using incl %eax).
332 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
333 if (Imm->getAPIntValue().isSignedIntN(8))
336 // If the other operand is a TLS address, we should fold it instead.
339 // leal i@NTPOFF(%eax), %eax
341 // movl $i@NTPOFF, %eax
343 // if the block also has an access to a second TLS address this will save
345 // FIXME: This is probably also true for non TLS addresses.
346 if (Op1.getOpcode() == X86ISD::Wrapper) {
347 SDValue Val = Op1.getOperand(0);
348 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
358 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with
359 /// load's chain operand and move load below the call's chain operand.
360 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load,
361 SDValue Call, SDValue OrigChain) {
362 SmallVector<SDValue, 8> Ops;
363 SDValue Chain = OrigChain.getOperand(0);
364 if (Chain.getNode() == Load.getNode())
365 Ops.push_back(Load.getOperand(0));
367 assert(Chain.getOpcode() == ISD::TokenFactor &&
368 "Unexpected chain operand");
369 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i)
370 if (Chain.getOperand(i).getNode() == Load.getNode())
371 Ops.push_back(Load.getOperand(0));
373 Ops.push_back(Chain.getOperand(i));
375 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(),
376 MVT::Other, &Ops[0], Ops.size());
378 Ops.push_back(NewChain);
380 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i)
381 Ops.push_back(OrigChain.getOperand(i));
382 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size());
383 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0),
384 Load.getOperand(1), Load.getOperand(2));
386 Ops.push_back(SDValue(Load.getNode(), 1));
387 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i)
388 Ops.push_back(Call.getOperand(i));
389 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size());
392 /// isCalleeLoad - Return true if call address is a load and it can be
393 /// moved below CALLSEQ_START and the chains leading up to the call.
394 /// Return the CALLSEQ_START by reference as a second output.
395 /// In the case of a tail call, there isn't a callseq node between the call
396 /// chain and the load.
397 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) {
398 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse())
400 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode());
403 LD->getAddressingMode() != ISD::UNINDEXED ||
404 LD->getExtensionType() != ISD::NON_EXTLOAD)
407 // Now let's find the callseq_start.
408 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
409 if (!Chain.hasOneUse())
411 Chain = Chain.getOperand(0);
414 if (!Chain.getNumOperands())
416 if (Chain.getOperand(0).getNode() == Callee.getNode())
418 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
419 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) &&
420 Callee.getValue(1).hasOneUse())
425 void X86DAGToDAGISel::PreprocessISelDAG() {
426 // OptForSize is used in pattern predicates that isel is matching.
427 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize);
429 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
430 E = CurDAG->allnodes_end(); I != E; ) {
431 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
433 if (OptLevel != CodeGenOpt::None &&
434 (N->getOpcode() == X86ISD::CALL ||
435 N->getOpcode() == X86ISD::TC_RETURN)) {
436 /// Also try moving call address load from outside callseq_start to just
437 /// before the call to allow it to be folded.
455 bool HasCallSeq = N->getOpcode() == X86ISD::CALL;
456 SDValue Chain = N->getOperand(0);
457 SDValue Load = N->getOperand(1);
458 if (!isCalleeLoad(Load, Chain, HasCallSeq))
460 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain);
465 // Lower fpround and fpextend nodes that target the FP stack to be store and
466 // load to the stack. This is a gross hack. We would like to simply mark
467 // these as being illegal, but when we do that, legalize produces these when
468 // it expands calls, then expands these in the same legalize pass. We would
469 // like dag combine to be able to hack on these between the call expansion
470 // and the node legalization. As such this pass basically does "really
471 // late" legalization of these inline with the X86 isel pass.
472 // FIXME: This should only happen when not compiled with -O0.
473 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
476 EVT SrcVT = N->getOperand(0).getValueType();
477 EVT DstVT = N->getValueType(0);
479 // If any of the sources are vectors, no fp stack involved.
480 if (SrcVT.isVector() || DstVT.isVector())
483 // If the source and destination are SSE registers, then this is a legal
484 // conversion that should not be lowered.
485 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT);
486 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT);
487 if (SrcIsSSE && DstIsSSE)
490 if (!SrcIsSSE && !DstIsSSE) {
491 // If this is an FPStack extension, it is a noop.
492 if (N->getOpcode() == ISD::FP_EXTEND)
494 // If this is a value-preserving FPStack truncation, it is a noop.
495 if (N->getConstantOperandVal(1))
499 // Here we could have an FP stack truncation or an FPStack <-> SSE convert.
500 // FPStack has extload and truncstore. SSE can fold direct loads into other
501 // operations. Based on this, decide what we want to do.
503 if (N->getOpcode() == ISD::FP_ROUND)
504 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'.
506 MemVT = SrcIsSSE ? SrcVT : DstVT;
508 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
509 DebugLoc dl = N->getDebugLoc();
511 // FIXME: optimize the case where the src/dest is a load or store?
512 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl,
514 MemTmp, MachinePointerInfo(), MemVT,
516 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp,
517 MachinePointerInfo(),
518 MemVT, false, false, 0);
520 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
521 // extload we created. This will cause general havok on the dag because
522 // anything below the conversion could be folded into other existing nodes.
523 // To avoid invalidating 'I', back it up to the convert node.
525 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
527 // Now that we did that, the node is dead. Increment the iterator to the
528 // next node to process, then delete N.
530 CurDAG->DeleteNode(N);
535 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
536 /// the main function.
537 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB,
538 MachineFrameInfo *MFI) {
539 const TargetInstrInfo *TII = TM.getInstrInfo();
540 if (Subtarget->isTargetCygMing()) {
542 Subtarget->is64Bit() ? X86::CALL64pcrel32 : X86::CALLpcrel32;
543 BuildMI(BB, DebugLoc(),
544 TII->get(CallOp)).addExternalSymbol("__main");
548 void X86DAGToDAGISel::EmitFunctionEntryCode() {
549 // If this is main, emit special code for main.
550 if (const Function *Fn = MF->getFunction())
551 if (Fn->hasExternalLinkage() && Fn->getName() == "main")
552 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo());
555 static bool isDispSafeForFrameIndex(int64_t Val) {
556 // On 64-bit platforms, we can run into an issue where a frame index
557 // includes a displacement that, when added to the explicit displacement,
558 // will overflow the displacement field. Assuming that the frame index
559 // displacement fits into a 31-bit integer (which is only slightly more
560 // aggressive than the current fundamental assumption that it fits into
561 // a 32-bit integer), a 31-bit disp should always be safe.
562 return isInt<31>(Val);
565 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset,
566 X86ISelAddressMode &AM) {
567 int64_t Val = AM.Disp + Offset;
568 CodeModel::Model M = TM.getCodeModel();
569 if (Subtarget->is64Bit()) {
570 if (!X86::isOffsetSuitableForCodeModel(Val, M,
571 AM.hasSymbolicDisplacement()))
573 // In addition to the checks required for a register base, check that
574 // we do not try to use an unsafe Disp with a frame index.
575 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase &&
576 !isDispSafeForFrameIndex(Val))
584 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){
585 SDValue Address = N->getOperand(1);
587 // load gs:0 -> GS segment register.
588 // load fs:0 -> FS segment register.
590 // This optimization is valid because the GNU TLS model defines that
591 // gs:0 (or fs:0 on X86-64) contains its own address.
592 // For more information see http://people.redhat.com/drepper/tls.pdf
593 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
594 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 &&
595 Subtarget->isTargetELF())
596 switch (N->getPointerInfo().getAddrSpace()) {
598 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
601 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
608 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes
609 /// into an addressing mode. These wrap things that will resolve down into a
610 /// symbol reference. If no match is possible, this returns true, otherwise it
612 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) {
613 // If the addressing mode already has a symbol as the displacement, we can
614 // never match another symbol.
615 if (AM.hasSymbolicDisplacement())
618 SDValue N0 = N.getOperand(0);
619 CodeModel::Model M = TM.getCodeModel();
621 // Handle X86-64 rip-relative addresses. We check this before checking direct
622 // folding because RIP is preferable to non-RIP accesses.
623 if (Subtarget->is64Bit() &&
624 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so
625 // they cannot be folded into immediate fields.
626 // FIXME: This can be improved for kernel and other models?
627 (M == CodeModel::Small || M == CodeModel::Kernel) &&
628 // Base and index reg must be 0 in order to use %rip as base and lowering
630 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) {
631 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
632 X86ISelAddressMode Backup = AM;
633 AM.GV = G->getGlobal();
634 AM.SymbolFlags = G->getTargetFlags();
635 if (FoldOffsetIntoAddress(G->getOffset(), AM)) {
639 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
640 X86ISelAddressMode Backup = AM;
641 AM.CP = CP->getConstVal();
642 AM.Align = CP->getAlignment();
643 AM.SymbolFlags = CP->getTargetFlags();
644 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) {
648 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
649 AM.ES = S->getSymbol();
650 AM.SymbolFlags = S->getTargetFlags();
651 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
652 AM.JT = J->getIndex();
653 AM.SymbolFlags = J->getTargetFlags();
655 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
656 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
659 if (N.getOpcode() == X86ISD::WrapperRIP)
660 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64));
664 // Handle the case when globals fit in our immediate field: This is true for
665 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit
666 // mode, this results in a non-RIP-relative computation.
667 if (!Subtarget->is64Bit() ||
668 ((M == CodeModel::Small || M == CodeModel::Kernel) &&
669 TM.getRelocationModel() == Reloc::Static)) {
670 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) {
671 AM.GV = G->getGlobal();
672 AM.Disp += G->getOffset();
673 AM.SymbolFlags = G->getTargetFlags();
674 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
675 AM.CP = CP->getConstVal();
676 AM.Align = CP->getAlignment();
677 AM.Disp += CP->getOffset();
678 AM.SymbolFlags = CP->getTargetFlags();
679 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
680 AM.ES = S->getSymbol();
681 AM.SymbolFlags = S->getTargetFlags();
682 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) {
683 AM.JT = J->getIndex();
684 AM.SymbolFlags = J->getTargetFlags();
686 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress();
687 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags();
695 /// MatchAddress - Add the specified node to the specified addressing mode,
696 /// returning true if it cannot be done. This just pattern matches for the
698 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) {
699 if (MatchAddressRecursively(N, AM, 0))
702 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
703 // a smaller encoding and avoids a scaled-index.
705 AM.BaseType == X86ISelAddressMode::RegBase &&
706 AM.Base_Reg.getNode() == 0) {
707 AM.Base_Reg = AM.IndexReg;
711 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode,
712 // because it has a smaller encoding.
713 // TODO: Which other code models can use this?
714 if (TM.getCodeModel() == CodeModel::Small &&
715 Subtarget->is64Bit() &&
717 AM.BaseType == X86ISelAddressMode::RegBase &&
718 AM.Base_Reg.getNode() == 0 &&
719 AM.IndexReg.getNode() == 0 &&
720 AM.SymbolFlags == X86II::MO_NO_FLAG &&
721 AM.hasSymbolicDisplacement())
722 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64);
727 // Insert a node into the DAG at least before the Pos node's position. This
728 // will reposition the node as needed, and will assign it a node ID that is <=
729 // the Pos node's ID. Note that this does *not* preserve the uniqueness of node
730 // IDs! The selection DAG must no longer depend on their uniqueness when this
732 static void InsertDAGNode(SelectionDAG &DAG, SDValue Pos, SDValue N) {
733 if (N.getNode()->getNodeId() == -1 ||
734 N.getNode()->getNodeId() > Pos.getNode()->getNodeId()) {
735 DAG.RepositionNode(Pos.getNode(), N.getNode());
736 N.getNode()->setNodeId(Pos.getNode()->getNodeId());
740 // Transform "(X >> (8-C1)) & C2" to "(X >> 8) & 0xff)" if safe. This
741 // allows us to convert the shift and and into an h-register extract and
742 // a scaled index. Returns false if the simplification is performed.
743 static bool FoldMaskAndShiftToExtract(SelectionDAG &DAG, SDValue N,
745 SDValue Shift, SDValue X,
746 X86ISelAddressMode &AM) {
747 if (Shift.getOpcode() != ISD::SRL ||
748 !isa<ConstantSDNode>(Shift.getOperand(1)) ||
752 int ScaleLog = 8 - Shift.getConstantOperandVal(1);
753 if (ScaleLog <= 0 || ScaleLog >= 4 ||
754 Mask != (0xffu << ScaleLog))
757 EVT VT = N.getValueType();
758 DebugLoc DL = N.getDebugLoc();
759 SDValue Eight = DAG.getConstant(8, MVT::i8);
760 SDValue NewMask = DAG.getConstant(0xff, VT);
761 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
762 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
763 SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);
764 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
766 // Insert the new nodes into the topological ordering. We must do this in
767 // a valid topological ordering as nothing is going to go back and re-sort
768 // these nodes. We continually insert before 'N' in sequence as this is
769 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
770 // hierarchy left to express.
771 InsertDAGNode(DAG, N, Eight);
772 InsertDAGNode(DAG, N, Srl);
773 InsertDAGNode(DAG, N, NewMask);
774 InsertDAGNode(DAG, N, And);
775 InsertDAGNode(DAG, N, ShlCount);
776 InsertDAGNode(DAG, N, Shl);
777 DAG.ReplaceAllUsesWith(N, Shl);
779 AM.Scale = (1 << ScaleLog);
783 // Transforms "(X << C1) & C2" to "(X & (C2>>C1)) << C1" if safe and if this
784 // allows us to fold the shift into this addressing mode. Returns false if the
785 // transform succeeded.
786 static bool FoldMaskedShiftToScaledMask(SelectionDAG &DAG, SDValue N,
788 SDValue Shift, SDValue X,
789 X86ISelAddressMode &AM) {
790 if (Shift.getOpcode() != ISD::SHL ||
791 !isa<ConstantSDNode>(Shift.getOperand(1)))
794 // Not likely to be profitable if either the AND or SHIFT node has more
795 // than one use (unless all uses are for address computation). Besides,
796 // isel mechanism requires their node ids to be reused.
797 if (!N.hasOneUse() || !Shift.hasOneUse())
800 // Verify that the shift amount is something we can fold.
801 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
802 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
805 EVT VT = N.getValueType();
806 DebugLoc DL = N.getDebugLoc();
807 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
808 SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);
809 SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));
811 // Insert the new nodes into the topological ordering. We must do this in
812 // a valid topological ordering as nothing is going to go back and re-sort
813 // these nodes. We continually insert before 'N' in sequence as this is
814 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
815 // hierarchy left to express.
816 InsertDAGNode(DAG, N, NewMask);
817 InsertDAGNode(DAG, N, NewAnd);
818 InsertDAGNode(DAG, N, NewShift);
819 DAG.ReplaceAllUsesWith(N, NewShift);
821 AM.Scale = 1 << ShiftAmt;
822 AM.IndexReg = NewAnd;
826 // Implement some heroics to detect shifts of masked values where the mask can
827 // be replaced by extending the shift and undoing that in the addressing mode
828 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
829 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done in
830 // the addressing mode. This results in code such as:
832 // int f(short *y, int *lookup_table) {
834 // return *y + lookup_table[*y >> 11];
838 // movzwl (%rdi), %eax
841 // addl (%rsi,%rcx,4), %eax
844 // movzwl (%rdi), %eax
848 // addl (%rsi,%rcx), %eax
850 // Note that this function assumes the mask is provided as a mask *after* the
851 // value is shifted. The input chain may or may not match that, but computing
852 // such a mask is trivial.
853 static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
855 SDValue Shift, SDValue X,
856 X86ISelAddressMode &AM) {
857 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
858 !isa<ConstantSDNode>(Shift.getOperand(1)))
861 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
862 unsigned MaskLZ = CountLeadingZeros_64(Mask);
863 unsigned MaskTZ = CountTrailingZeros_64(Mask);
865 // The amount of shift we're trying to fit into the addressing mode is taken
866 // from the trailing zeros of the mask.
867 unsigned AMShiftAmt = MaskTZ;
869 // There is nothing we can do here unless the mask is removing some bits.
870 // Also, the addressing mode can only represent shifts of 1, 2, or 3 bits.
871 if (AMShiftAmt <= 0 || AMShiftAmt > 3) return true;
873 // We also need to ensure that mask is a continuous run of bits.
874 if (CountTrailingOnes_64(Mask >> MaskTZ) + MaskTZ + MaskLZ != 64) return true;
876 // Scale the leading zero count down based on the actual size of the value.
877 // Also scale it down based on the size of the shift.
878 MaskLZ -= (64 - X.getValueSizeInBits()) + ShiftAmt;
880 // The final check is to ensure that any masked out high bits of X are
881 // already known to be zero. Otherwise, the mask has a semantic impact
882 // other than masking out a couple of low bits. Unfortunately, because of
883 // the mask, zero extensions will be removed from operands in some cases.
884 // This code works extra hard to look through extensions because we can
885 // replace them with zero extensions cheaply if necessary.
886 bool ReplacingAnyExtend = false;
887 if (X.getOpcode() == ISD::ANY_EXTEND) {
888 unsigned ExtendBits =
889 X.getValueSizeInBits() - X.getOperand(0).getValueSizeInBits();
890 // Assume that we'll replace the any-extend with a zero-extend, and
891 // narrow the search to the extended value.
893 MaskLZ = ExtendBits > MaskLZ ? 0 : MaskLZ - ExtendBits;
894 ReplacingAnyExtend = true;
896 APInt MaskedHighBits = APInt::getHighBitsSet(X.getValueSizeInBits(),
898 APInt KnownZero, KnownOne;
899 DAG.ComputeMaskedBits(X, MaskedHighBits, KnownZero, KnownOne);
900 if (MaskedHighBits != KnownZero) return true;
902 // We've identified a pattern that can be transformed into a single shift
903 // and an addressing mode. Make it so.
904 EVT VT = N.getValueType();
905 if (ReplacingAnyExtend) {
906 assert(X.getValueType() != VT);
907 // We looked through an ANY_EXTEND node, insert a ZERO_EXTEND.
908 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, X.getDebugLoc(), VT, X);
909 InsertDAGNode(DAG, N, NewX);
912 DebugLoc DL = N.getDebugLoc();
913 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);
914 SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);
915 SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);
916 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);
918 // Insert the new nodes into the topological ordering. We must do this in
919 // a valid topological ordering as nothing is going to go back and re-sort
920 // these nodes. We continually insert before 'N' in sequence as this is
921 // essentially a pre-flattened and pre-sorted sequence of nodes. There is no
922 // hierarchy left to express.
923 InsertDAGNode(DAG, N, NewSRLAmt);
924 InsertDAGNode(DAG, N, NewSRL);
925 InsertDAGNode(DAG, N, NewSHLAmt);
926 InsertDAGNode(DAG, N, NewSHL);
927 DAG.ReplaceAllUsesWith(N, NewSHL);
929 AM.Scale = 1 << AMShiftAmt;
930 AM.IndexReg = NewSRL;
934 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
936 DebugLoc dl = N.getDebugLoc();
938 dbgs() << "MatchAddress: ";
943 return MatchAddressBase(N, AM);
945 // If this is already a %rip relative address, we can only merge immediates
946 // into it. Instead of handling this in every case, we handle it here.
947 // RIP relative addressing: %rip + 32-bit displacement!
948 if (AM.isRIPRelative()) {
949 // FIXME: JumpTable and ExternalSymbol address currently don't like
950 // displacements. It isn't very important, but this should be fixed for
952 if (!AM.ES && AM.JT != -1) return true;
954 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
955 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM))
960 switch (N.getOpcode()) {
962 case ISD::Constant: {
963 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
964 if (!FoldOffsetIntoAddress(Val, AM))
969 case X86ISD::Wrapper:
970 case X86ISD::WrapperRIP:
971 if (!MatchWrapper(N, AM))
976 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM))
980 case ISD::FrameIndex:
981 if (AM.BaseType == X86ISelAddressMode::RegBase &&
982 AM.Base_Reg.getNode() == 0 &&
983 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) {
984 AM.BaseType = X86ISelAddressMode::FrameIndexBase;
985 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
991 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1)
995 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
996 unsigned Val = CN->getZExtValue();
997 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
998 // that the base operand remains free for further matching. If
999 // the base doesn't end up getting used, a post-processing step
1000 // in MatchAddress turns (,x,2) into (x,x), which is cheaper.
1001 if (Val == 1 || Val == 2 || Val == 3) {
1002 AM.Scale = 1 << Val;
1003 SDValue ShVal = N.getNode()->getOperand(0);
1005 // Okay, we know that we have a scale by now. However, if the scaled
1006 // value is an add of something and a constant, we can fold the
1007 // constant into the disp field here.
1008 if (CurDAG->isBaseWithConstantOffset(ShVal)) {
1009 AM.IndexReg = ShVal.getNode()->getOperand(0);
1010 ConstantSDNode *AddVal =
1011 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
1012 uint64_t Disp = AddVal->getSExtValue() << Val;
1013 if (!FoldOffsetIntoAddress(Disp, AM))
1017 AM.IndexReg = ShVal;
1024 // Scale must not be used already.
1025 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1027 SDValue And = N.getOperand(0);
1028 if (And.getOpcode() != ISD::AND) break;
1029 SDValue X = And.getOperand(0);
1031 // We only handle up to 64-bit values here as those are what matter for
1032 // addressing mode optimizations.
1033 if (X.getValueSizeInBits() > 64) break;
1035 // The mask used for the transform is expected to be post-shift, but we
1036 // found the shift first so just apply the shift to the mask before passing
1038 if (!isa<ConstantSDNode>(N.getOperand(1)) ||
1039 !isa<ConstantSDNode>(And.getOperand(1)))
1041 uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
1043 // Try to fold the mask and shift into the scale, and return false if we
1045 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, N, X, AM))
1050 case ISD::SMUL_LOHI:
1051 case ISD::UMUL_LOHI:
1052 // A mul_lohi where we need the low part can be folded as a plain multiply.
1053 if (N.getResNo() != 0) break;
1056 case X86ISD::MUL_IMM:
1057 // X*[3,5,9] -> X+X*[2,4,8]
1058 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1059 AM.Base_Reg.getNode() == 0 &&
1060 AM.IndexReg.getNode() == 0) {
1062 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
1063 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
1064 CN->getZExtValue() == 9) {
1065 AM.Scale = unsigned(CN->getZExtValue())-1;
1067 SDValue MulVal = N.getNode()->getOperand(0);
1070 // Okay, we know that we have a scale by now. However, if the scaled
1071 // value is an add of something and a constant, we can fold the
1072 // constant into the disp field here.
1073 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
1074 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
1075 Reg = MulVal.getNode()->getOperand(0);
1076 ConstantSDNode *AddVal =
1077 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
1078 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
1079 if (FoldOffsetIntoAddress(Disp, AM))
1080 Reg = N.getNode()->getOperand(0);
1082 Reg = N.getNode()->getOperand(0);
1085 AM.IndexReg = AM.Base_Reg = Reg;
1092 // Given A-B, if A can be completely folded into the address and
1093 // the index field with the index field unused, use -B as the index.
1094 // This is a win if a has multiple parts that can be folded into
1095 // the address. Also, this saves a mov if the base register has
1096 // other uses, since it avoids a two-address sub instruction, however
1097 // it costs an additional mov if the index register has other uses.
1099 // Add an artificial use to this node so that we can keep track of
1100 // it if it gets CSE'd with a different node.
1101 HandleSDNode Handle(N);
1103 // Test if the LHS of the sub can be folded.
1104 X86ISelAddressMode Backup = AM;
1105 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) {
1109 // Test if the index field is free for use.
1110 if (AM.IndexReg.getNode() || AM.isRIPRelative()) {
1116 SDValue RHS = Handle.getValue().getNode()->getOperand(1);
1117 // If the RHS involves a register with multiple uses, this
1118 // transformation incurs an extra mov, due to the neg instruction
1119 // clobbering its operand.
1120 if (!RHS.getNode()->hasOneUse() ||
1121 RHS.getNode()->getOpcode() == ISD::CopyFromReg ||
1122 RHS.getNode()->getOpcode() == ISD::TRUNCATE ||
1123 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND ||
1124 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND &&
1125 RHS.getNode()->getOperand(0).getValueType() == MVT::i32))
1127 // If the base is a register with multiple uses, this
1128 // transformation may save a mov.
1129 if ((AM.BaseType == X86ISelAddressMode::RegBase &&
1130 AM.Base_Reg.getNode() &&
1131 !AM.Base_Reg.getNode()->hasOneUse()) ||
1132 AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1134 // If the folded LHS was interesting, this transformation saves
1135 // address arithmetic.
1136 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) +
1137 ((AM.Disp != 0) && (Backup.Disp == 0)) +
1138 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2)
1140 // If it doesn't look like it may be an overall win, don't do it.
1146 // Ok, the transformation is legal and appears profitable. Go for it.
1147 SDValue Zero = CurDAG->getConstant(0, N.getValueType());
1148 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);
1152 // Insert the new nodes into the topological ordering.
1153 InsertDAGNode(*CurDAG, N, Zero);
1154 InsertDAGNode(*CurDAG, N, Neg);
1159 // Add an artificial use to this node so that we can keep track of
1160 // it if it gets CSE'd with a different node.
1161 HandleSDNode Handle(N);
1163 X86ISelAddressMode Backup = AM;
1164 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1165 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1))
1169 // Try again after commuting the operands.
1170 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&&
1171 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1))
1175 // If we couldn't fold both operands into the address at the same time,
1176 // see if we can just put each operand into a register and fold at least
1178 if (AM.BaseType == X86ISelAddressMode::RegBase &&
1179 !AM.Base_Reg.getNode() &&
1180 !AM.IndexReg.getNode()) {
1181 N = Handle.getValue();
1182 AM.Base_Reg = N.getOperand(0);
1183 AM.IndexReg = N.getOperand(1);
1187 N = Handle.getValue();
1192 // Handle "X | C" as "X + C" iff X is known to have C bits clear.
1193 if (CurDAG->isBaseWithConstantOffset(N)) {
1194 X86ISelAddressMode Backup = AM;
1195 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1));
1197 // Start with the LHS as an addr mode.
1198 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) &&
1199 !FoldOffsetIntoAddress(CN->getSExtValue(), AM))
1206 // Perform some heroic transforms on an and of a constant-count shift
1207 // with a constant to enable use of the scaled offset field.
1209 // Scale must not be used already.
1210 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break;
1212 SDValue Shift = N.getOperand(0);
1213 if (Shift.getOpcode() != ISD::SRL && Shift.getOpcode() != ISD::SHL) break;
1214 SDValue X = Shift.getOperand(0);
1216 // We only handle up to 64-bit values here as those are what matter for
1217 // addressing mode optimizations.
1218 if (X.getValueSizeInBits() > 64) break;
1220 if (!isa<ConstantSDNode>(N.getOperand(1)))
1222 uint64_t Mask = N.getConstantOperandVal(1);
1224 // Try to fold the mask and shift into an extract and scale.
1225 if (!FoldMaskAndShiftToExtract(*CurDAG, N, Mask, Shift, X, AM))
1228 // Try to fold the mask and shift directly into the scale.
1229 if (!FoldMaskAndShiftToScale(*CurDAG, N, Mask, Shift, X, AM))
1232 // Try to swap the mask and shift to place shifts which can be done as
1233 // a scale on the outside of the mask.
1234 if (!FoldMaskedShiftToScaledMask(*CurDAG, N, Mask, Shift, X, AM))
1240 return MatchAddressBase(N, AM);
1243 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the
1244 /// specified addressing mode without any further recursion.
1245 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) {
1246 // Is the base register already occupied?
1247 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) {
1248 // If so, check to see if the scale index register is set.
1249 if (AM.IndexReg.getNode() == 0) {
1255 // Otherwise, we cannot select it.
1259 // Default, generate it as a register.
1260 AM.BaseType = X86ISelAddressMode::RegBase;
1265 /// SelectAddr - returns true if it is able pattern match an addressing mode.
1266 /// It returns the operands which make up the maximal addressing mode it can
1267 /// match by reference.
1269 /// Parent is the parent node of the addr operand that is being matched. It
1270 /// is always a load, store, atomic node, or null. It is only null when
1271 /// checking memory operands for inline asm nodes.
1272 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base,
1273 SDValue &Scale, SDValue &Index,
1274 SDValue &Disp, SDValue &Segment) {
1275 X86ISelAddressMode AM;
1278 // This list of opcodes are all the nodes that have an "addr:$ptr" operand
1279 // that are not a MemSDNode, and thus don't have proper addrspace info.
1280 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme
1281 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores
1282 Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme
1283 unsigned AddrSpace =
1284 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace();
1285 // AddrSpace 256 -> GS, 257 -> FS.
1286 if (AddrSpace == 256)
1287 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16);
1288 if (AddrSpace == 257)
1289 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16);
1292 if (MatchAddress(N, AM))
1295 EVT VT = N.getValueType();
1296 if (AM.BaseType == X86ISelAddressMode::RegBase) {
1297 if (!AM.Base_Reg.getNode())
1298 AM.Base_Reg = CurDAG->getRegister(0, VT);
1301 if (!AM.IndexReg.getNode())
1302 AM.IndexReg = CurDAG->getRegister(0, VT);
1304 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1308 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to
1309 /// match a load whose top elements are either undef or zeros. The load flavor
1310 /// is derived from the type of N, which is either v4f32 or v2f64.
1313 /// PatternChainNode: this is the matched node that has a chain input and
1315 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root,
1316 SDValue N, SDValue &Base,
1317 SDValue &Scale, SDValue &Index,
1318 SDValue &Disp, SDValue &Segment,
1319 SDValue &PatternNodeWithChain) {
1320 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) {
1321 PatternNodeWithChain = N.getOperand(0);
1322 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) &&
1323 PatternNodeWithChain.hasOneUse() &&
1324 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1325 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1326 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain);
1327 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1333 // Also handle the case where we explicitly require zeros in the top
1334 // elements. This is a vector shuffle from the zero vector.
1335 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() &&
1336 // Check to see if the top elements are all zeros (or bitcast of zeros).
1337 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
1338 N.getOperand(0).getNode()->hasOneUse() &&
1339 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) &&
1340 N.getOperand(0).getOperand(0).hasOneUse() &&
1341 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) &&
1342 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) {
1343 // Okay, this is a zero extending load. Fold it.
1344 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0));
1345 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment))
1347 PatternNodeWithChain = SDValue(LD, 0);
1354 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
1355 /// mode it matches can be cost effectively emitted as an LEA instruction.
1356 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N,
1357 SDValue &Base, SDValue &Scale,
1358 SDValue &Index, SDValue &Disp,
1360 X86ISelAddressMode AM;
1362 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support
1364 SDValue Copy = AM.Segment;
1365 SDValue T = CurDAG->getRegister(0, MVT::i32);
1367 if (MatchAddress(N, AM))
1369 assert (T == AM.Segment);
1372 EVT VT = N.getValueType();
1373 unsigned Complexity = 0;
1374 if (AM.BaseType == X86ISelAddressMode::RegBase)
1375 if (AM.Base_Reg.getNode())
1378 AM.Base_Reg = CurDAG->getRegister(0, VT);
1379 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
1382 if (AM.IndexReg.getNode())
1385 AM.IndexReg = CurDAG->getRegister(0, VT);
1387 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with
1392 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
1393 // to a LEA. This is determined with some expermentation but is by no means
1394 // optimal (especially for code size consideration). LEA is nice because of
1395 // its three-address nature. Tweak the cost function again when we can run
1396 // convertToThreeAddress() at register allocation time.
1397 if (AM.hasSymbolicDisplacement()) {
1398 // For X86-64, we should always use lea to materialize RIP relative
1400 if (Subtarget->is64Bit())
1406 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode()))
1409 // If it isn't worth using an LEA, reject it.
1410 if (Complexity <= 2)
1413 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1417 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes.
1418 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base,
1419 SDValue &Scale, SDValue &Index,
1420 SDValue &Disp, SDValue &Segment) {
1421 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress);
1422 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
1424 X86ISelAddressMode AM;
1425 AM.GV = GA->getGlobal();
1426 AM.Disp += GA->getOffset();
1427 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType());
1428 AM.SymbolFlags = GA->getTargetFlags();
1430 if (N.getValueType() == MVT::i32) {
1432 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32);
1434 AM.IndexReg = CurDAG->getRegister(0, MVT::i64);
1437 getAddressOperands(AM, Base, Scale, Index, Disp, Segment);
1442 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N,
1443 SDValue &Base, SDValue &Scale,
1444 SDValue &Index, SDValue &Disp,
1446 if (!ISD::isNON_EXTLoad(N.getNode()) ||
1447 !IsProfitableToFold(N, P, P) ||
1448 !IsLegalToFold(N, P, P, OptLevel))
1451 return SelectAddr(N.getNode(),
1452 N.getOperand(1), Base, Scale, Index, Disp, Segment);
1455 /// getGlobalBaseReg - Return an SDNode that returns the value of
1456 /// the global base register. Output instructions required to
1457 /// initialize the global base register, if necessary.
1459 SDNode *X86DAGToDAGISel::getGlobalBaseReg() {
1460 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
1461 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
1464 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
1465 SDValue Chain = Node->getOperand(0);
1466 SDValue In1 = Node->getOperand(1);
1467 SDValue In2L = Node->getOperand(2);
1468 SDValue In2H = Node->getOperand(3);
1469 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1470 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1472 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1473 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1474 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1475 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
1476 MVT::i32, MVT::i32, MVT::Other, Ops,
1477 array_lengthof(Ops));
1478 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
1482 // FIXME: Figure out some way to unify this with the 'or' and other code
1484 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
1485 if (Node->hasAnyUseOfValue(0))
1488 // Optimize common patterns for __sync_add_and_fetch and
1489 // __sync_sub_and_fetch where the result is not used. This allows us
1490 // to use "lock" version of add, sub, inc, dec instructions.
1491 // FIXME: Do not use special instructions but instead add the "lock"
1492 // prefix to the target node somehow. The extra information will then be
1493 // transferred to machine instruction and it denotes the prefix.
1494 SDValue Chain = Node->getOperand(0);
1495 SDValue Ptr = Node->getOperand(1);
1496 SDValue Val = Node->getOperand(2);
1497 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1498 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1501 bool isInc = false, isDec = false, isSub = false, isCN = false;
1502 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1503 if (CN && CN->getSExtValue() == (int32_t)CN->getSExtValue()) {
1505 int64_t CNVal = CN->getSExtValue();
1508 else if (CNVal == -1)
1510 else if (CNVal >= 0)
1511 Val = CurDAG->getTargetConstant(CNVal, NVT);
1514 Val = CurDAG->getTargetConstant(-CNVal, NVT);
1516 } else if (Val.hasOneUse() &&
1517 Val.getOpcode() == ISD::SUB &&
1518 X86::isZeroNode(Val.getOperand(0))) {
1520 Val = Val.getOperand(1);
1523 DebugLoc dl = Node->getDebugLoc();
1525 switch (NVT.getSimpleVT().SimpleTy) {
1529 Opc = X86::LOCK_INC8m;
1531 Opc = X86::LOCK_DEC8m;
1534 Opc = X86::LOCK_SUB8mi;
1536 Opc = X86::LOCK_SUB8mr;
1539 Opc = X86::LOCK_ADD8mi;
1541 Opc = X86::LOCK_ADD8mr;
1546 Opc = X86::LOCK_INC16m;
1548 Opc = X86::LOCK_DEC16m;
1551 if (immSext8(Val.getNode()))
1552 Opc = X86::LOCK_SUB16mi8;
1554 Opc = X86::LOCK_SUB16mi;
1556 Opc = X86::LOCK_SUB16mr;
1559 if (immSext8(Val.getNode()))
1560 Opc = X86::LOCK_ADD16mi8;
1562 Opc = X86::LOCK_ADD16mi;
1564 Opc = X86::LOCK_ADD16mr;
1569 Opc = X86::LOCK_INC32m;
1571 Opc = X86::LOCK_DEC32m;
1574 if (immSext8(Val.getNode()))
1575 Opc = X86::LOCK_SUB32mi8;
1577 Opc = X86::LOCK_SUB32mi;
1579 Opc = X86::LOCK_SUB32mr;
1582 if (immSext8(Val.getNode()))
1583 Opc = X86::LOCK_ADD32mi8;
1585 Opc = X86::LOCK_ADD32mi;
1587 Opc = X86::LOCK_ADD32mr;
1592 Opc = X86::LOCK_INC64m;
1594 Opc = X86::LOCK_DEC64m;
1596 Opc = X86::LOCK_SUB64mr;
1598 if (immSext8(Val.getNode()))
1599 Opc = X86::LOCK_SUB64mi8;
1600 else if (i64immSExt32(Val.getNode()))
1601 Opc = X86::LOCK_SUB64mi32;
1604 Opc = X86::LOCK_ADD64mr;
1606 if (immSext8(Val.getNode()))
1607 Opc = X86::LOCK_ADD64mi8;
1608 else if (i64immSExt32(Val.getNode()))
1609 Opc = X86::LOCK_ADD64mi32;
1615 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1617 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1618 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1619 if (isInc || isDec) {
1620 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1621 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0);
1622 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1623 SDValue RetVals[] = { Undef, Ret };
1624 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1626 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1627 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1628 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1629 SDValue RetVals[] = { Undef, Ret };
1630 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1656 static const uint16_t AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = {
1680 X86::LOCK_AND64mi32,
1693 X86::LOCK_XOR64mi32,
1698 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) {
1699 if (Node->hasAnyUseOfValue(0))
1702 // Optimize common patterns for __sync_or_and_fetch and similar arith
1703 // operations where the result is not used. This allows us to use the "lock"
1704 // version of the arithmetic instruction.
1705 // FIXME: Same as for 'add' and 'sub', try to merge those down here.
1706 SDValue Chain = Node->getOperand(0);
1707 SDValue Ptr = Node->getOperand(1);
1708 SDValue Val = Node->getOperand(2);
1709 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
1710 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1713 // Which index into the table.
1715 switch (Node->getOpcode()) {
1716 case ISD::ATOMIC_LOAD_OR:
1719 case ISD::ATOMIC_LOAD_AND:
1722 case ISD::ATOMIC_LOAD_XOR:
1730 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val);
1731 if (CN && (int32_t)CN->getSExtValue() == CN->getSExtValue()) {
1733 Val = CurDAG->getTargetConstant(CN->getSExtValue(), NVT);
1737 switch (NVT.getSimpleVT().SimpleTy) {
1741 Opc = AtomicOpcTbl[Op][ConstantI8];
1743 Opc = AtomicOpcTbl[Op][I8];
1747 if (immSext8(Val.getNode()))
1748 Opc = AtomicOpcTbl[Op][SextConstantI16];
1750 Opc = AtomicOpcTbl[Op][ConstantI16];
1752 Opc = AtomicOpcTbl[Op][I16];
1756 if (immSext8(Val.getNode()))
1757 Opc = AtomicOpcTbl[Op][SextConstantI32];
1759 Opc = AtomicOpcTbl[Op][ConstantI32];
1761 Opc = AtomicOpcTbl[Op][I32];
1764 Opc = AtomicOpcTbl[Op][I64];
1766 if (immSext8(Val.getNode()))
1767 Opc = AtomicOpcTbl[Op][SextConstantI64];
1768 else if (i64immSExt32(Val.getNode()))
1769 Opc = AtomicOpcTbl[Op][ConstantI64];
1774 assert(Opc != 0 && "Invalid arith lock transform!");
1776 DebugLoc dl = Node->getDebugLoc();
1777 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1779 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1780 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
1781 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
1782 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0);
1783 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
1784 SDValue RetVals[] = { Undef, Ret };
1785 return CurDAG->getMergeValues(RetVals, 2, dl).getNode();
1788 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has
1789 /// any uses which require the SF or OF bits to be accurate.
1790 static bool HasNoSignedComparisonUses(SDNode *N) {
1791 // Examine each user of the node.
1792 for (SDNode::use_iterator UI = N->use_begin(),
1793 UE = N->use_end(); UI != UE; ++UI) {
1794 // Only examine CopyToReg uses.
1795 if (UI->getOpcode() != ISD::CopyToReg)
1797 // Only examine CopyToReg uses that copy to EFLAGS.
1798 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() !=
1801 // Examine each user of the CopyToReg use.
1802 for (SDNode::use_iterator FlagUI = UI->use_begin(),
1803 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) {
1804 // Only examine the Flag result.
1805 if (FlagUI.getUse().getResNo() != 1) continue;
1806 // Anything unusual: assume conservatively.
1807 if (!FlagUI->isMachineOpcode()) return false;
1808 // Examine the opcode of the user.
1809 switch (FlagUI->getMachineOpcode()) {
1810 // These comparisons don't treat the most significant bit specially.
1811 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr:
1812 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr:
1813 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm:
1814 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm:
1815 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4:
1816 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4:
1817 case X86::CMOVA16rr: case X86::CMOVA16rm:
1818 case X86::CMOVA32rr: case X86::CMOVA32rm:
1819 case X86::CMOVA64rr: case X86::CMOVA64rm:
1820 case X86::CMOVAE16rr: case X86::CMOVAE16rm:
1821 case X86::CMOVAE32rr: case X86::CMOVAE32rm:
1822 case X86::CMOVAE64rr: case X86::CMOVAE64rm:
1823 case X86::CMOVB16rr: case X86::CMOVB16rm:
1824 case X86::CMOVB32rr: case X86::CMOVB32rm:
1825 case X86::CMOVB64rr: case X86::CMOVB64rm:
1826 case X86::CMOVBE16rr: case X86::CMOVBE16rm:
1827 case X86::CMOVBE32rr: case X86::CMOVBE32rm:
1828 case X86::CMOVBE64rr: case X86::CMOVBE64rm:
1829 case X86::CMOVE16rr: case X86::CMOVE16rm:
1830 case X86::CMOVE32rr: case X86::CMOVE32rm:
1831 case X86::CMOVE64rr: case X86::CMOVE64rm:
1832 case X86::CMOVNE16rr: case X86::CMOVNE16rm:
1833 case X86::CMOVNE32rr: case X86::CMOVNE32rm:
1834 case X86::CMOVNE64rr: case X86::CMOVNE64rm:
1835 case X86::CMOVNP16rr: case X86::CMOVNP16rm:
1836 case X86::CMOVNP32rr: case X86::CMOVNP32rm:
1837 case X86::CMOVNP64rr: case X86::CMOVNP64rm:
1838 case X86::CMOVP16rr: case X86::CMOVP16rm:
1839 case X86::CMOVP32rr: case X86::CMOVP32rm:
1840 case X86::CMOVP64rr: case X86::CMOVP64rm:
1842 // Anything else: assume conservatively.
1843 default: return false;
1850 SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
1851 EVT NVT = Node->getValueType(0);
1853 unsigned Opcode = Node->getOpcode();
1854 DebugLoc dl = Node->getDebugLoc();
1856 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
1858 if (Node->isMachineOpcode()) {
1859 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
1860 return NULL; // Already selected.
1865 case X86ISD::GlobalBaseReg:
1866 return getGlobalBaseReg();
1868 case X86ISD::ATOMOR64_DAG:
1869 return SelectAtomic64(Node, X86::ATOMOR6432);
1870 case X86ISD::ATOMXOR64_DAG:
1871 return SelectAtomic64(Node, X86::ATOMXOR6432);
1872 case X86ISD::ATOMADD64_DAG:
1873 return SelectAtomic64(Node, X86::ATOMADD6432);
1874 case X86ISD::ATOMSUB64_DAG:
1875 return SelectAtomic64(Node, X86::ATOMSUB6432);
1876 case X86ISD::ATOMNAND64_DAG:
1877 return SelectAtomic64(Node, X86::ATOMNAND6432);
1878 case X86ISD::ATOMAND64_DAG:
1879 return SelectAtomic64(Node, X86::ATOMAND6432);
1880 case X86ISD::ATOMSWAP64_DAG:
1881 return SelectAtomic64(Node, X86::ATOMSWAP6432);
1883 case ISD::ATOMIC_LOAD_ADD: {
1884 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT);
1889 case ISD::ATOMIC_LOAD_XOR:
1890 case ISD::ATOMIC_LOAD_AND:
1891 case ISD::ATOMIC_LOAD_OR: {
1892 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT);
1900 // For operations of the form (x << C1) op C2, check if we can use a smaller
1901 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1.
1902 SDValue N0 = Node->getOperand(0);
1903 SDValue N1 = Node->getOperand(1);
1905 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse())
1908 // i8 is unshrinkable, i16 should be promoted to i32.
1909 if (NVT != MVT::i32 && NVT != MVT::i64)
1912 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
1913 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
1914 if (!Cst || !ShlCst)
1917 int64_t Val = Cst->getSExtValue();
1918 uint64_t ShlVal = ShlCst->getZExtValue();
1920 // Make sure that we don't change the operation by removing bits.
1921 // This only matters for OR and XOR, AND is unaffected.
1922 if (Opcode != ISD::AND && ((Val >> ShlVal) << ShlVal) != Val)
1925 unsigned ShlOp, Op = 0;
1928 // Check the minimum bitwidth for the new constant.
1929 // TODO: AND32ri is the same as AND64ri32 with zext imm.
1930 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr
1931 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32.
1932 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal))
1934 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal))
1937 // Bail if there is no smaller encoding.
1941 switch (NVT.getSimpleVT().SimpleTy) {
1942 default: llvm_unreachable("Unsupported VT!");
1944 assert(CstVT == MVT::i8);
1945 ShlOp = X86::SHL32ri;
1948 case ISD::AND: Op = X86::AND32ri8; break;
1949 case ISD::OR: Op = X86::OR32ri8; break;
1950 case ISD::XOR: Op = X86::XOR32ri8; break;
1954 assert(CstVT == MVT::i8 || CstVT == MVT::i32);
1955 ShlOp = X86::SHL64ri;
1958 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break;
1959 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break;
1960 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break;
1965 // Emit the smaller op and the shift.
1966 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);
1967 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);
1968 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),
1971 case X86ISD::UMUL: {
1972 SDValue N0 = Node->getOperand(0);
1973 SDValue N1 = Node->getOperand(1);
1976 switch (NVT.getSimpleVT().SimpleTy) {
1977 default: llvm_unreachable("Unsupported VT!");
1978 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break;
1979 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break;
1980 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break;
1981 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break;
1984 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
1985 N0, SDValue()).getValue(1);
1987 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32);
1988 SDValue Ops[] = {N1, InFlag};
1989 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops, 2);
1991 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0));
1992 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1));
1993 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2));
1997 case ISD::SMUL_LOHI:
1998 case ISD::UMUL_LOHI: {
1999 SDValue N0 = Node->getOperand(0);
2000 SDValue N1 = Node->getOperand(1);
2002 bool isSigned = Opcode == ISD::SMUL_LOHI;
2004 switch (NVT.getSimpleVT().SimpleTy) {
2005 default: llvm_unreachable("Unsupported VT!");
2006 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
2007 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
2008 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
2009 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break;
2012 switch (NVT.getSimpleVT().SimpleTy) {
2013 default: llvm_unreachable("Unsupported VT!");
2014 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
2015 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
2016 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
2017 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break;
2021 unsigned LoReg, HiReg;
2022 switch (NVT.getSimpleVT().SimpleTy) {
2023 default: llvm_unreachable("Unsupported VT!");
2024 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
2025 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
2026 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
2027 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break;
2030 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2031 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2032 // Multiply is commmutative.
2034 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2039 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg,
2040 N0, SDValue()).getValue(1);
2043 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2046 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
2047 array_lengthof(Ops));
2048 InFlag = SDValue(CNode, 1);
2050 // Update the chain.
2051 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2053 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag);
2054 InFlag = SDValue(CNode, 0);
2057 // Prevent use of AH in a REX instruction by referencing AX instead.
2058 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2059 !SDValue(Node, 1).use_empty()) {
2060 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2061 X86::AX, MVT::i16, InFlag);
2062 InFlag = Result.getValue(2);
2063 // Get the low part if needed. Don't use getCopyFromReg for aliasing
2065 if (!SDValue(Node, 0).use_empty())
2066 ReplaceUses(SDValue(Node, 1),
2067 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2069 // Shift AX down 8 bits.
2070 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2072 CurDAG->getTargetConstant(8, MVT::i8)), 0);
2073 // Then truncate it down to i8.
2074 ReplaceUses(SDValue(Node, 1),
2075 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2077 // Copy the low half of the result, if it is needed.
2078 if (!SDValue(Node, 0).use_empty()) {
2079 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2080 LoReg, NVT, InFlag);
2081 InFlag = Result.getValue(2);
2082 ReplaceUses(SDValue(Node, 0), Result);
2083 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2085 // Copy the high half of the result, if it is needed.
2086 if (!SDValue(Node, 1).use_empty()) {
2087 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2088 HiReg, NVT, InFlag);
2089 InFlag = Result.getValue(2);
2090 ReplaceUses(SDValue(Node, 1), Result);
2091 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2098 case ISD::UDIVREM: {
2099 SDValue N0 = Node->getOperand(0);
2100 SDValue N1 = Node->getOperand(1);
2102 bool isSigned = Opcode == ISD::SDIVREM;
2104 switch (NVT.getSimpleVT().SimpleTy) {
2105 default: llvm_unreachable("Unsupported VT!");
2106 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
2107 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
2108 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
2109 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break;
2112 switch (NVT.getSimpleVT().SimpleTy) {
2113 default: llvm_unreachable("Unsupported VT!");
2114 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
2115 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
2116 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
2117 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break;
2121 unsigned LoReg, HiReg, ClrReg;
2122 unsigned ClrOpcode, SExtOpcode;
2123 switch (NVT.getSimpleVT().SimpleTy) {
2124 default: llvm_unreachable("Unsupported VT!");
2126 LoReg = X86::AL; ClrReg = HiReg = X86::AH;
2128 SExtOpcode = X86::CBW;
2131 LoReg = X86::AX; HiReg = X86::DX;
2132 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX;
2133 SExtOpcode = X86::CWD;
2136 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX;
2137 ClrOpcode = X86::MOV32r0;
2138 SExtOpcode = X86::CDQ;
2141 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX;
2142 ClrOpcode = X86::MOV64r0;
2143 SExtOpcode = X86::CQO;
2147 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
2148 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2149 bool signBitIsZero = CurDAG->SignBitIsZero(N0);
2152 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) {
2153 // Special case for div8, just use a move with zero extension to AX to
2154 // clear the upper 8 bits (AH).
2155 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain;
2156 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
2157 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) };
2159 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32,
2161 array_lengthof(Ops)), 0);
2162 Chain = Move.getValue(1);
2163 ReplaceUses(N0.getValue(1), Chain);
2166 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0);
2167 Chain = CurDAG->getEntryNode();
2169 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue());
2170 InFlag = Chain.getValue(1);
2173 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl,
2174 LoReg, N0, SDValue()).getValue(1);
2175 if (isSigned && !signBitIsZero) {
2176 // Sign extend the low part into the high part.
2178 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0);
2180 // Zero out the high part, effectively zero extending the input.
2182 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0);
2183 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg,
2184 ClrNode, InFlag).getValue(1);
2189 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0),
2192 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops,
2193 array_lengthof(Ops));
2194 InFlag = SDValue(CNode, 1);
2195 // Update the chain.
2196 ReplaceUses(N1.getValue(1), SDValue(CNode, 0));
2199 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0);
2202 // Prevent use of AH in a REX instruction by referencing AX instead.
2203 // Shift it down 8 bits.
2204 if (HiReg == X86::AH && Subtarget->is64Bit() &&
2205 !SDValue(Node, 1).use_empty()) {
2206 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2207 X86::AX, MVT::i16, InFlag);
2208 InFlag = Result.getValue(2);
2210 // If we also need AL (the quotient), get it by extracting a subreg from
2211 // Result. The fast register allocator does not like multiple CopyFromReg
2212 // nodes using aliasing registers.
2213 if (!SDValue(Node, 0).use_empty())
2214 ReplaceUses(SDValue(Node, 0),
2215 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2217 // Shift AX right by 8 bits instead of using AH.
2218 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,
2220 CurDAG->getTargetConstant(8, MVT::i8)),
2222 ReplaceUses(SDValue(Node, 1),
2223 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));
2225 // Copy the division (low) result, if it is needed.
2226 if (!SDValue(Node, 0).use_empty()) {
2227 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2228 LoReg, NVT, InFlag);
2229 InFlag = Result.getValue(2);
2230 ReplaceUses(SDValue(Node, 0), Result);
2231 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2233 // Copy the remainder (high) result, if it is needed.
2234 if (!SDValue(Node, 1).use_empty()) {
2235 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2236 HiReg, NVT, InFlag);
2237 InFlag = Result.getValue(2);
2238 ReplaceUses(SDValue(Node, 1), Result);
2239 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n');
2245 SDValue N0 = Node->getOperand(0);
2246 SDValue N1 = Node->getOperand(1);
2248 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to
2249 // use a smaller encoding.
2250 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() &&
2251 HasNoSignedComparisonUses(Node))
2252 // Look past the truncate if CMP is the only use of it.
2253 N0 = N0.getOperand(0);
2254 if ((N0.getNode()->getOpcode() == ISD::AND ||
2255 (N0.getResNo() == 0 && N0.getNode()->getOpcode() == X86ISD::AND)) &&
2256 N0.getNode()->hasOneUse() &&
2257 N0.getValueType() != MVT::i8 &&
2258 X86::isZeroNode(N1)) {
2259 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
2262 // For example, convert "testl %eax, $8" to "testb %al, $8"
2263 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&
2264 (!(C->getZExtValue() & 0x80) ||
2265 HasNoSignedComparisonUses(Node))) {
2266 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);
2267 SDValue Reg = N0.getNode()->getOperand(0);
2269 // On x86-32, only the ABCD registers have 8-bit subregisters.
2270 if (!Subtarget->is64Bit()) {
2271 const TargetRegisterClass *TRC;
2272 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2273 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2274 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2275 default: llvm_unreachable("Unsupported TEST operand type!");
2277 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2278 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2279 Reg.getValueType(), Reg, RC), 0);
2282 // Extract the l-register.
2283 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl,
2287 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm);
2290 // For example, "testl %eax, $2048" to "testb %ah, $8".
2291 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 &&
2292 (!(C->getZExtValue() & 0x8000) ||
2293 HasNoSignedComparisonUses(Node))) {
2294 // Shift the immediate right by 8 bits.
2295 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,
2297 SDValue Reg = N0.getNode()->getOperand(0);
2299 // Put the value in an ABCD register.
2300 const TargetRegisterClass *TRC;
2301 switch (N0.getValueType().getSimpleVT().SimpleTy) {
2302 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break;
2303 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break;
2304 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;
2305 default: llvm_unreachable("Unsupported TEST operand type!");
2307 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
2308 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,
2309 Reg.getValueType(), Reg, RC), 0);
2311 // Extract the h-register.
2312 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl,
2315 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only
2316 // target GR8_NOREX registers, so make sure the register class is
2318 return CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl, MVT::i32,
2319 Subreg, ShiftedImm);
2322 // For example, "testl %eax, $32776" to "testw %ax, $32776".
2323 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 &&
2324 N0.getValueType() != MVT::i16 &&
2325 (!(C->getZExtValue() & 0x8000) ||
2326 HasNoSignedComparisonUses(Node))) {
2327 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);
2328 SDValue Reg = N0.getNode()->getOperand(0);
2330 // Extract the 16-bit subregister.
2331 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl,
2335 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm);
2338 // For example, "testq %rax, $268468232" to "testl %eax, $268468232".
2339 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 &&
2340 N0.getValueType() == MVT::i64 &&
2341 (!(C->getZExtValue() & 0x80000000) ||
2342 HasNoSignedComparisonUses(Node))) {
2343 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
2344 SDValue Reg = N0.getNode()->getOperand(0);
2346 // Extract the 32-bit subregister.
2347 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl,
2351 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm);
2357 // The DEC64m tablegen pattern is currently not able to match the case where
2358 // the EFLAGS on the original DEC are used.
2359 // we'll need to improve tablegen to allow flags to be transferred from a
2360 // node in the pattern to the result node. probably with a new keyword
2361 // for example, we have this
2362 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2363 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2364 // (implicit EFLAGS)]>;
2365 // but maybe need something like this
2366 // def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
2367 // [(store (add (loadi64 addr:$dst), -1), addr:$dst),
2368 // (transferrable EFLAGS)]>;
2369 StoreSDNode *StoreNode = cast<StoreSDNode>(Node);
2370 SDValue Chain = StoreNode->getOperand(0);
2371 SDValue StoredVal = StoreNode->getOperand(1);
2372 SDValue Address = StoreNode->getOperand(2);
2373 SDValue Undef = StoreNode->getOperand(3);
2375 if (StoreNode->getMemOperand()->getSize() != 8 ||
2376 Undef->getOpcode() != ISD::UNDEF ||
2377 Chain->getOpcode() != ISD::LOAD ||
2378 StoredVal->getOpcode() != X86ISD::DEC ||
2379 StoredVal.getResNo() != 0 ||
2380 !StoredVal.getNode()->hasNUsesOfValue(1, 0) ||
2381 !Chain.getNode()->hasNUsesOfValue(1, 0) ||
2382 StoredVal->getOperand(0).getNode() != Chain.getNode())
2385 //OPC_CheckPredicate, 1, // Predicate_nontemporalstore
2386 if (StoreNode->isNonTemporal())
2389 LoadSDNode *LoadNode = cast<LoadSDNode>(Chain.getNode());
2390 if (LoadNode->getOperand(1) != Address ||
2391 LoadNode->getOperand(2) != Undef)
2394 if (!ISD::isNormalLoad(LoadNode))
2397 if (!ISD::isNormalStore(StoreNode))
2400 // check load chain has only one use (from the store)
2401 if (!Chain.hasOneUse())
2404 // Merge the input chains if they are not intra-pattern references.
2405 SDValue InputChain = LoadNode->getOperand(0);
2407 SDValue Base, Scale, Index, Disp, Segment;
2408 if (!SelectAddr(LoadNode, LoadNode->getBasePtr(),
2409 Base, Scale, Index, Disp, Segment))
2412 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(2);
2413 MemOp[0] = StoreNode->getMemOperand();
2414 MemOp[1] = LoadNode->getMemOperand();
2415 const SDValue Ops[] = { Base, Scale, Index, Disp, Segment, InputChain };
2416 MachineSDNode *Result = CurDAG->getMachineNode(X86::DEC64m,
2417 Node->getDebugLoc(),
2418 MVT::i32, MVT::Other, Ops,
2419 array_lengthof(Ops));
2420 Result->setMemRefs(MemOp, MemOp + 2);
2422 ReplaceUses(SDValue(StoreNode, 0), SDValue(Result, 1));
2423 ReplaceUses(SDValue(StoredVal.getNode(), 1), SDValue(Result, 0));
2429 SDNode *ResNode = SelectCode(Node);
2431 DEBUG(dbgs() << "=> ";
2432 if (ResNode == NULL || ResNode == Node)
2435 ResNode->dump(CurDAG);
2441 bool X86DAGToDAGISel::
2442 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2443 std::vector<SDValue> &OutOps) {
2444 SDValue Op0, Op1, Op2, Op3, Op4;
2445 switch (ConstraintCode) {
2446 case 'o': // offsetable ??
2447 case 'v': // not offsetable ??
2448 default: return true;
2450 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4))
2455 OutOps.push_back(Op0);
2456 OutOps.push_back(Op1);
2457 OutOps.push_back(Op2);
2458 OutOps.push_back(Op3);
2459 OutOps.push_back(Op4);
2463 /// createX86ISelDag - This pass converts a legalized DAG into a
2464 /// X86-specific DAG, ready for instruction scheduling.
2466 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
2467 CodeGenOpt::Level OptLevel) {
2468 return new X86DAGToDAGISel(TM, OptLevel);