1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
43 // Forward declarations.
44 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
46 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
47 : TargetLowering(TM) {
48 Subtarget = &TM.getSubtarget<X86Subtarget>();
49 X86ScalarSSEf64 = Subtarget->hasSSE2();
50 X86ScalarSSEf32 = Subtarget->hasSSE1();
51 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
55 RegInfo = TM.getRegisterInfo();
58 // Set up the TargetLowering object.
60 // X86 is weird, it always uses i8 for shift amounts and setcc results.
61 setShiftAmountType(MVT::i8);
62 setSetCCResultContents(ZeroOrOneSetCCResult);
63 setSchedulingPreference(SchedulingForRegPressure);
64 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
65 setStackPointerRegisterToSaveRestore(X86StackPtr);
67 if (Subtarget->isTargetDarwin()) {
68 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(false);
70 setUseUnderscoreLongJmp(false);
71 } else if (Subtarget->isTargetMingw()) {
72 // MS runtime is weird: it exports _setjmp, but longjmp!
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(false);
76 setUseUnderscoreSetJmp(true);
77 setUseUnderscoreLongJmp(true);
80 // Set up the register classes.
81 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
82 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
83 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
84 if (Subtarget->is64Bit())
85 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 // We don't accept any truncstore of integer registers.
90 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
91 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
92 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
93 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
94 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
95 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
97 // SETOEQ and SETUNE require checking two conditions.
98 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
99 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
100 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
101 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
102 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
103 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
105 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
107 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
108 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
109 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
111 if (Subtarget->is64Bit()) {
112 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
116 // If SSE i64 SINT_TO_FP is not available, expand i32 UINT_TO_FP.
117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
119 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
122 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
124 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
125 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
126 // SSE has no i16 to fp conversion, only i32
127 if (X86ScalarSSEf32) {
128 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
129 // f32 and f64 cases are Legal, f80 case is not
130 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
132 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
133 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
136 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
137 // are Legal, f80 is custom lowered.
138 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
139 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
141 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
143 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
144 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
146 if (X86ScalarSSEf32) {
147 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
148 // f32 and f64 cases are Legal, f80 case is not
149 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
151 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
152 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
155 // Handle FP_TO_UINT by promoting the destination to a larger signed
157 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
158 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
159 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
161 if (Subtarget->is64Bit()) {
162 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
163 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
165 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
166 // Expand FP_TO_UINT into a select.
167 // FIXME: We would like to use a Custom expander here eventually to do
168 // the optimal thing for SSE vs. the default expansion in the legalizer.
169 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
171 // With SSE3 we can use fisttpll to convert to a signed i64.
172 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
175 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
176 if (!X86ScalarSSEf64) {
177 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
178 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
181 // Scalar integer divide and remainder are lowered to use operations that
182 // produce two results, to match the available instructions. This exposes
183 // the two-result form to trivial CSE, which is able to combine x/y and x%y
184 // into a single instruction.
186 // Scalar integer multiply-high is also lowered to use two-result
187 // operations, to match the available instructions. However, plain multiply
188 // (low) operations are left as Legal, as there are single-result
189 // instructions for this in x86. Using the two-result multiply instructions
190 // when both high and low results are needed must be arranged by dagcombine.
191 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
192 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
193 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
194 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
195 setOperationAction(ISD::SREM , MVT::i8 , Expand);
196 setOperationAction(ISD::UREM , MVT::i8 , Expand);
197 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
198 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
199 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
200 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
201 setOperationAction(ISD::SREM , MVT::i16 , Expand);
202 setOperationAction(ISD::UREM , MVT::i16 , Expand);
203 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
204 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
205 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
206 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
207 setOperationAction(ISD::SREM , MVT::i32 , Expand);
208 setOperationAction(ISD::UREM , MVT::i32 , Expand);
209 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
210 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
211 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
212 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
213 setOperationAction(ISD::SREM , MVT::i64 , Expand);
214 setOperationAction(ISD::UREM , MVT::i64 , Expand);
216 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
217 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
218 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
219 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
220 if (Subtarget->is64Bit())
221 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
222 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
223 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
224 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
225 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
226 setOperationAction(ISD::FREM , MVT::f32 , Expand);
227 setOperationAction(ISD::FREM , MVT::f64 , Expand);
228 setOperationAction(ISD::FREM , MVT::f80 , Expand);
229 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
231 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
232 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
233 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
234 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
235 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
236 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
237 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
238 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
239 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
240 if (Subtarget->is64Bit()) {
241 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
242 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
243 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
246 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
247 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
249 // These should be promoted to a larger select which is supported.
250 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
251 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
252 // X86 wants to expand cmov itself.
253 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
254 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
255 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
256 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
257 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
258 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
259 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
260 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
261 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
262 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
263 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
264 if (Subtarget->is64Bit()) {
265 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
266 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
268 // X86 ret instruction may pop stack.
269 setOperationAction(ISD::RET , MVT::Other, Custom);
270 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
273 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
274 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
275 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
276 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
277 if (Subtarget->is64Bit())
278 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
279 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
280 if (Subtarget->is64Bit()) {
281 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
282 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
283 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
284 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
286 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
287 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
288 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
289 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
290 if (Subtarget->is64Bit()) {
291 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
292 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
293 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
296 if (Subtarget->hasSSE1())
297 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
299 if (!Subtarget->hasSSE2())
300 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
302 // Expand certain atomics
303 setOperationAction(ISD::ATOMIC_CMP_SWAP_8 , MVT::i8, Custom);
304 setOperationAction(ISD::ATOMIC_CMP_SWAP_16, MVT::i16, Custom);
305 setOperationAction(ISD::ATOMIC_CMP_SWAP_32, MVT::i32, Custom);
306 setOperationAction(ISD::ATOMIC_CMP_SWAP_64, MVT::i64, Custom);
308 setOperationAction(ISD::ATOMIC_LOAD_SUB_8 , MVT::i8, Custom);
309 setOperationAction(ISD::ATOMIC_LOAD_SUB_16, MVT::i16, Custom);
310 setOperationAction(ISD::ATOMIC_LOAD_SUB_32, MVT::i32, Custom);
311 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Custom);
313 if (!Subtarget->is64Bit()) {
314 setOperationAction(ISD::ATOMIC_LOAD_ADD_64, MVT::i64, Custom);
315 setOperationAction(ISD::ATOMIC_LOAD_SUB_64, MVT::i64, Custom);
316 setOperationAction(ISD::ATOMIC_LOAD_AND_64, MVT::i64, Custom);
317 setOperationAction(ISD::ATOMIC_LOAD_OR_64, MVT::i64, Custom);
318 setOperationAction(ISD::ATOMIC_LOAD_XOR_64, MVT::i64, Custom);
319 setOperationAction(ISD::ATOMIC_LOAD_NAND_64, MVT::i64, Custom);
320 setOperationAction(ISD::ATOMIC_SWAP_64, MVT::i64, Custom);
323 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
324 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
325 // FIXME - use subtarget debug flags
326 if (!Subtarget->isTargetDarwin() &&
327 !Subtarget->isTargetELF() &&
328 !Subtarget->isTargetCygMing()) {
329 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
330 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
333 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
334 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
335 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
336 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
337 if (Subtarget->is64Bit()) {
338 setExceptionPointerRegister(X86::RAX);
339 setExceptionSelectorRegister(X86::RDX);
341 setExceptionPointerRegister(X86::EAX);
342 setExceptionSelectorRegister(X86::EDX);
344 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
345 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
347 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
349 setOperationAction(ISD::TRAP, MVT::Other, Legal);
351 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
352 setOperationAction(ISD::VASTART , MVT::Other, Custom);
353 setOperationAction(ISD::VAEND , MVT::Other, Expand);
354 if (Subtarget->is64Bit()) {
355 setOperationAction(ISD::VAARG , MVT::Other, Custom);
356 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
358 setOperationAction(ISD::VAARG , MVT::Other, Expand);
359 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
362 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
363 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
364 if (Subtarget->is64Bit())
365 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
366 if (Subtarget->isTargetCygMing())
367 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
369 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
371 if (X86ScalarSSEf64) {
372 // f32 and f64 use SSE.
373 // Set up the FP register classes.
374 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
375 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
377 // Use ANDPD to simulate FABS.
378 setOperationAction(ISD::FABS , MVT::f64, Custom);
379 setOperationAction(ISD::FABS , MVT::f32, Custom);
381 // Use XORP to simulate FNEG.
382 setOperationAction(ISD::FNEG , MVT::f64, Custom);
383 setOperationAction(ISD::FNEG , MVT::f32, Custom);
385 // Use ANDPD and ORPD to simulate FCOPYSIGN.
386 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
387 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
389 // We don't support sin/cos/fmod
390 setOperationAction(ISD::FSIN , MVT::f64, Expand);
391 setOperationAction(ISD::FCOS , MVT::f64, Expand);
392 setOperationAction(ISD::FSIN , MVT::f32, Expand);
393 setOperationAction(ISD::FCOS , MVT::f32, Expand);
395 // Expand FP immediates into loads from the stack, except for the special
397 addLegalFPImmediate(APFloat(+0.0)); // xorpd
398 addLegalFPImmediate(APFloat(+0.0f)); // xorps
400 // Floating truncations from f80 and extensions to f80 go through memory.
401 // If optimizing, we lie about this though and handle it in
402 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
404 setConvertAction(MVT::f32, MVT::f80, Expand);
405 setConvertAction(MVT::f64, MVT::f80, Expand);
406 setConvertAction(MVT::f80, MVT::f32, Expand);
407 setConvertAction(MVT::f80, MVT::f64, Expand);
409 } else if (X86ScalarSSEf32) {
410 // Use SSE for f32, x87 for f64.
411 // Set up the FP register classes.
412 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
413 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
415 // Use ANDPS to simulate FABS.
416 setOperationAction(ISD::FABS , MVT::f32, Custom);
418 // Use XORP to simulate FNEG.
419 setOperationAction(ISD::FNEG , MVT::f32, Custom);
421 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
423 // Use ANDPS and ORPS to simulate FCOPYSIGN.
424 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
425 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
427 // We don't support sin/cos/fmod
428 setOperationAction(ISD::FSIN , MVT::f32, Expand);
429 setOperationAction(ISD::FCOS , MVT::f32, Expand);
431 // Special cases we handle for FP constants.
432 addLegalFPImmediate(APFloat(+0.0f)); // xorps
433 addLegalFPImmediate(APFloat(+0.0)); // FLD0
434 addLegalFPImmediate(APFloat(+1.0)); // FLD1
435 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
436 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
438 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
439 // this though and handle it in InstructionSelectPreprocess so that
440 // dagcombine2 can hack on these.
442 setConvertAction(MVT::f32, MVT::f64, Expand);
443 setConvertAction(MVT::f32, MVT::f80, Expand);
444 setConvertAction(MVT::f80, MVT::f32, Expand);
445 setConvertAction(MVT::f64, MVT::f32, Expand);
446 // And x87->x87 truncations also.
447 setConvertAction(MVT::f80, MVT::f64, Expand);
451 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
452 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
455 // f32 and f64 in x87.
456 // Set up the FP register classes.
457 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
458 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
460 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
461 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
462 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
463 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
465 // Floating truncations go through memory. If optimizing, we lie about
466 // this though and handle it in InstructionSelectPreprocess so that
467 // dagcombine2 can hack on these.
469 setConvertAction(MVT::f80, MVT::f32, Expand);
470 setConvertAction(MVT::f64, MVT::f32, Expand);
471 setConvertAction(MVT::f80, MVT::f64, Expand);
475 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
476 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
478 addLegalFPImmediate(APFloat(+0.0)); // FLD0
479 addLegalFPImmediate(APFloat(+1.0)); // FLD1
480 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
481 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
482 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
483 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
484 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
485 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
488 // Long double always uses X87.
489 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
490 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
491 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
494 APFloat TmpFlt(+0.0);
495 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
497 addLegalFPImmediate(TmpFlt); // FLD0
499 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
500 APFloat TmpFlt2(+1.0);
501 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
503 addLegalFPImmediate(TmpFlt2); // FLD1
504 TmpFlt2.changeSign();
505 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
509 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
510 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
513 // Always use a library call for pow.
514 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
515 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
516 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
518 setOperationAction(ISD::FLOG, MVT::f80, Expand);
519 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
520 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
521 setOperationAction(ISD::FEXP, MVT::f80, Expand);
522 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
524 // First set operation action for all vector types to expand. Then we
525 // will selectively turn on ones that can be effectively codegen'd.
526 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
527 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
528 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
543 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
573 if (Subtarget->hasMMX()) {
574 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
575 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
576 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
577 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
578 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
580 // FIXME: add MMX packed arithmetics
582 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
583 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
584 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
585 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
587 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
588 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
589 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
590 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
592 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
593 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
595 setOperationAction(ISD::AND, MVT::v8i8, Promote);
596 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
597 setOperationAction(ISD::AND, MVT::v4i16, Promote);
598 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
599 setOperationAction(ISD::AND, MVT::v2i32, Promote);
600 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
601 setOperationAction(ISD::AND, MVT::v1i64, Legal);
603 setOperationAction(ISD::OR, MVT::v8i8, Promote);
604 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
605 setOperationAction(ISD::OR, MVT::v4i16, Promote);
606 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
607 setOperationAction(ISD::OR, MVT::v2i32, Promote);
608 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
609 setOperationAction(ISD::OR, MVT::v1i64, Legal);
611 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
612 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
613 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
614 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
615 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
616 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
617 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
619 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
620 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
621 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
622 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
623 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
624 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
625 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
626 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
627 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
629 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
630 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
631 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
632 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
633 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
635 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
636 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
637 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
638 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
640 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
641 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
642 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
643 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
645 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
648 if (Subtarget->hasSSE1()) {
649 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
651 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
652 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
653 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
654 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
655 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
656 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
657 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
658 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
659 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
660 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
661 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
662 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
665 if (Subtarget->hasSSE2()) {
666 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
667 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
668 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
669 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
670 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
672 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
673 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
674 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
675 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
676 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
677 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
678 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
679 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
680 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
681 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
682 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
683 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
684 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
685 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
686 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
688 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
689 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
690 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
691 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
693 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
694 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
695 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
696 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
697 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
699 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
700 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
701 MVT VT = (MVT::SimpleValueType)i;
702 // Do not attempt to custom lower non-power-of-2 vectors
703 if (!isPowerOf2_32(VT.getVectorNumElements()))
705 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
706 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
707 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
709 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
710 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
711 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
712 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
714 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
715 if (Subtarget->is64Bit()) {
716 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
717 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
720 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
721 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
722 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
723 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
724 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
725 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
726 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
727 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
728 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
729 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
730 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
731 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
734 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
736 // Custom lower v2i64 and v2f64 selects.
737 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
738 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
739 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
740 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
744 if (Subtarget->hasSSE41()) {
745 // FIXME: Do we need to handle scalar-to-vector here?
746 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
747 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
749 // i8 and i16 vectors are custom , because the source register and source
750 // source memory operand types are not the same width. f32 vectors are
751 // custom since the immediate controlling the insert encodes additional
753 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
754 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
755 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
756 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
758 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
759 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
760 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
761 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
763 if (Subtarget->is64Bit()) {
764 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
765 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
769 if (Subtarget->hasSSE42()) {
770 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
773 // We want to custom lower some of our intrinsics.
774 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
776 // We have target-specific dag combine patterns for the following nodes:
777 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
778 setTargetDAGCombine(ISD::BUILD_VECTOR);
779 setTargetDAGCombine(ISD::SELECT);
780 setTargetDAGCombine(ISD::STORE);
782 computeRegisterProperties();
784 // FIXME: These should be based on subtarget info. Plus, the values should
785 // be smaller when we are in optimizing for size mode.
786 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
787 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
788 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
789 allowUnalignedMemoryAccesses = true; // x86 supports it!
790 setPrefLoopAlignment(16);
794 MVT X86TargetLowering::getSetCCResultType(const SDValue &) const {
799 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
800 /// the desired ByVal argument alignment.
801 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
804 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
805 if (VTy->getBitWidth() == 128)
807 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
808 unsigned EltAlign = 0;
809 getMaxByValAlign(ATy->getElementType(), EltAlign);
810 if (EltAlign > MaxAlign)
812 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
813 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
814 unsigned EltAlign = 0;
815 getMaxByValAlign(STy->getElementType(i), EltAlign);
816 if (EltAlign > MaxAlign)
825 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
826 /// function arguments in the caller parameter area. For X86, aggregates
827 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
828 /// are at 4-byte boundaries.
829 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
830 if (Subtarget->is64Bit()) {
831 // Max of 8 and alignment of type.
832 unsigned TyAlign = TD->getABITypeAlignment(Ty);
839 if (Subtarget->hasSSE1())
840 getMaxByValAlign(Ty, Align);
844 /// getOptimalMemOpType - Returns the target specific optimal type for load
845 /// and store operations as a result of memset, memcpy, and memmove
846 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
849 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
850 bool isSrcConst, bool isSrcStr) const {
851 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
853 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
855 if (Subtarget->is64Bit() && Size >= 8)
861 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
863 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
864 SelectionDAG &DAG) const {
865 if (usesGlobalOffsetTable())
866 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
867 if (!Subtarget->isPICStyleRIPRel())
868 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
872 //===----------------------------------------------------------------------===//
873 // Return Value Calling Convention Implementation
874 //===----------------------------------------------------------------------===//
876 #include "X86GenCallingConv.inc"
878 /// LowerRET - Lower an ISD::RET node.
879 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
880 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
882 SmallVector<CCValAssign, 16> RVLocs;
883 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
884 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
885 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
886 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
888 // If this is the first return lowered for this function, add the regs to the
889 // liveout set for the function.
890 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
891 for (unsigned i = 0; i != RVLocs.size(); ++i)
892 if (RVLocs[i].isRegLoc())
893 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
895 SDValue Chain = Op.getOperand(0);
897 // Handle tail call return.
898 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
899 if (Chain.getOpcode() == X86ISD::TAILCALL) {
900 SDValue TailCall = Chain;
901 SDValue TargetAddress = TailCall.getOperand(1);
902 SDValue StackAdjustment = TailCall.getOperand(2);
903 assert(((TargetAddress.getOpcode() == ISD::Register &&
904 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
905 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
906 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
907 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
908 "Expecting an global address, external symbol, or register");
909 assert(StackAdjustment.getOpcode() == ISD::Constant &&
910 "Expecting a const value");
912 SmallVector<SDValue,8> Operands;
913 Operands.push_back(Chain.getOperand(0));
914 Operands.push_back(TargetAddress);
915 Operands.push_back(StackAdjustment);
916 // Copy registers used by the call. Last operand is a flag so it is not
918 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
919 Operands.push_back(Chain.getOperand(i));
921 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
928 SmallVector<SDValue, 6> RetOps;
929 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
930 // Operand #1 = Bytes To Pop
931 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
933 // Copy the result values into the output registers.
934 for (unsigned i = 0; i != RVLocs.size(); ++i) {
935 CCValAssign &VA = RVLocs[i];
936 assert(VA.isRegLoc() && "Can only return in registers!");
937 SDValue ValToCopy = Op.getOperand(i*2+1);
939 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
940 // the RET instruction and handled by the FP Stackifier.
941 if (RVLocs[i].getLocReg() == X86::ST0 ||
942 RVLocs[i].getLocReg() == X86::ST1) {
943 // If this is a copy from an xmm register to ST(0), use an FPExtend to
944 // change the value to the FP stack register class.
945 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
946 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
947 RetOps.push_back(ValToCopy);
948 // Don't emit a copytoreg.
952 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
953 Flag = Chain.getValue(1);
956 // The x86-64 ABI for returning structs by value requires that we copy
957 // the sret argument into %rax for the return. We saved the argument into
958 // a virtual register in the entry block, so now we copy the value out
960 if (Subtarget->is64Bit() &&
961 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
962 MachineFunction &MF = DAG.getMachineFunction();
963 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
964 unsigned Reg = FuncInfo->getSRetReturnReg();
966 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
967 FuncInfo->setSRetReturnReg(Reg);
969 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
971 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
972 Flag = Chain.getValue(1);
975 RetOps[0] = Chain; // Update chain.
977 // Add the flag if we have it.
979 RetOps.push_back(Flag);
981 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
985 /// LowerCallResult - Lower the result values of an ISD::CALL into the
986 /// appropriate copies out of appropriate physical registers. This assumes that
987 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
988 /// being lowered. The returns a SDNode with the same number of values as the
990 SDNode *X86TargetLowering::
991 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
992 unsigned CallingConv, SelectionDAG &DAG) {
994 // Assign locations to each value returned by this call.
995 SmallVector<CCValAssign, 16> RVLocs;
996 bool isVarArg = TheCall->isVarArg();
997 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
998 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1000 SmallVector<SDValue, 8> ResultVals;
1002 // Copy all of the result registers out of their specified physreg.
1003 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1004 MVT CopyVT = RVLocs[i].getValVT();
1006 // If this is a call to a function that returns an fp value on the floating
1007 // point stack, but where we prefer to use the value in xmm registers, copy
1008 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1009 if ((RVLocs[i].getLocReg() == X86::ST0 ||
1010 RVLocs[i].getLocReg() == X86::ST1) &&
1011 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
1015 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
1016 CopyVT, InFlag).getValue(1);
1017 SDValue Val = Chain.getValue(0);
1018 InFlag = Chain.getValue(2);
1020 if (CopyVT != RVLocs[i].getValVT()) {
1021 // Round the F80 the right size, which also moves to the appropriate xmm
1023 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
1024 // This truncation won't change the value.
1025 DAG.getIntPtrConstant(1));
1028 ResultVals.push_back(Val);
1031 // Merge everything together with a MERGE_VALUES node.
1032 ResultVals.push_back(Chain);
1033 return DAG.getMergeValues(TheCall->getVTList(), &ResultVals[0],
1034 ResultVals.size()).getNode();
1038 //===----------------------------------------------------------------------===//
1039 // C & StdCall & Fast Calling Convention implementation
1040 //===----------------------------------------------------------------------===//
1041 // StdCall calling convention seems to be standard for many Windows' API
1042 // routines and around. It differs from C calling convention just a little:
1043 // callee should clean up the stack, not caller. Symbols should be also
1044 // decorated in some fancy way :) It doesn't support any vector arguments.
1045 // For info on fast calling convention see Fast Calling Convention (tail call)
1046 // implementation LowerX86_32FastCCCallTo.
1048 /// AddLiveIn - This helper function adds the specified physical register to the
1049 /// MachineFunction as a live in value. It also creates a corresponding virtual
1050 /// register for it.
1051 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1052 const TargetRegisterClass *RC) {
1053 assert(RC->contains(PReg) && "Not the correct regclass!");
1054 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1055 MF.getRegInfo().addLiveIn(PReg, VReg);
1059 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1061 static bool CallIsStructReturn(CallSDNode *TheCall) {
1062 unsigned NumOps = TheCall->getNumArgs();
1066 return TheCall->getArgFlags(0).isSRet();
1069 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1070 /// return semantics.
1071 static bool ArgsAreStructReturn(SDValue Op) {
1072 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1076 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1079 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1080 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1082 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1086 switch (CallingConv) {
1089 case CallingConv::X86_StdCall:
1090 return !Subtarget->is64Bit();
1091 case CallingConv::X86_FastCall:
1092 return !Subtarget->is64Bit();
1093 case CallingConv::Fast:
1094 return PerformTailCallOpt;
1098 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1099 /// given CallingConvention value.
1100 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1101 if (Subtarget->is64Bit()) {
1102 if (Subtarget->isTargetWin64())
1103 return CC_X86_Win64_C;
1104 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1105 return CC_X86_64_TailCall;
1110 if (CC == CallingConv::X86_FastCall)
1111 return CC_X86_32_FastCall;
1112 else if (CC == CallingConv::Fast)
1113 return CC_X86_32_FastCC;
1118 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1119 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1121 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1122 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1123 if (CC == CallingConv::X86_FastCall)
1125 else if (CC == CallingConv::X86_StdCall)
1131 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1132 /// in a register before calling.
1133 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1134 return !IsTailCall && !Is64Bit &&
1135 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1136 Subtarget->isPICStyleGOT();
1139 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1140 /// address to be loaded in a register.
1142 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1143 return !Is64Bit && IsTailCall &&
1144 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1145 Subtarget->isPICStyleGOT();
1148 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1149 /// by "Src" to address "Dst" with size and alignment information specified by
1150 /// the specific parameter attribute. The copy will be passed as a byval
1151 /// function parameter.
1153 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1154 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1155 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1156 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1157 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1160 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1161 const CCValAssign &VA,
1162 MachineFrameInfo *MFI,
1164 SDValue Root, unsigned i) {
1165 // Create the nodes corresponding to a load from this parameter slot.
1166 ISD::ArgFlagsTy Flags =
1167 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1168 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1169 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1171 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1172 // changed with more analysis.
1173 // In case of tail call optimization mark all arguments mutable. Since they
1174 // could be overwritten by lowering of arguments in case of a tail call.
1175 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1176 VA.getLocMemOffset(), isImmutable);
1177 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1178 if (Flags.isByVal())
1180 return DAG.getLoad(VA.getValVT(), Root, FIN,
1181 PseudoSourceValue::getFixedStack(FI), 0);
1185 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1186 MachineFunction &MF = DAG.getMachineFunction();
1187 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1189 const Function* Fn = MF.getFunction();
1190 if (Fn->hasExternalLinkage() &&
1191 Subtarget->isTargetCygMing() &&
1192 Fn->getName() == "main")
1193 FuncInfo->setForceFramePointer(true);
1195 // Decorate the function name.
1196 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1198 MachineFrameInfo *MFI = MF.getFrameInfo();
1199 SDValue Root = Op.getOperand(0);
1200 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1201 unsigned CC = MF.getFunction()->getCallingConv();
1202 bool Is64Bit = Subtarget->is64Bit();
1203 bool IsWin64 = Subtarget->isTargetWin64();
1205 assert(!(isVarArg && CC == CallingConv::Fast) &&
1206 "Var args not supported with calling convention fastcc");
1208 // Assign locations to all of the incoming arguments.
1209 SmallVector<CCValAssign, 16> ArgLocs;
1210 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1211 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1213 SmallVector<SDValue, 8> ArgValues;
1214 unsigned LastVal = ~0U;
1215 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1216 CCValAssign &VA = ArgLocs[i];
1217 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1219 assert(VA.getValNo() != LastVal &&
1220 "Don't support value assigned to multiple locs yet");
1221 LastVal = VA.getValNo();
1223 if (VA.isRegLoc()) {
1224 MVT RegVT = VA.getLocVT();
1225 TargetRegisterClass *RC;
1226 if (RegVT == MVT::i32)
1227 RC = X86::GR32RegisterClass;
1228 else if (Is64Bit && RegVT == MVT::i64)
1229 RC = X86::GR64RegisterClass;
1230 else if (RegVT == MVT::f32)
1231 RC = X86::FR32RegisterClass;
1232 else if (RegVT == MVT::f64)
1233 RC = X86::FR64RegisterClass;
1234 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1235 RC = X86::VR128RegisterClass;
1236 else if (RegVT.isVector()) {
1237 assert(RegVT.getSizeInBits() == 64);
1239 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1241 // Darwin calling convention passes MMX values in either GPRs or
1242 // XMMs in x86-64. Other targets pass them in memory.
1243 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1244 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1247 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1252 assert(0 && "Unknown argument type!");
1255 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1256 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1258 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1259 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1261 if (VA.getLocInfo() == CCValAssign::SExt)
1262 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1263 DAG.getValueType(VA.getValVT()));
1264 else if (VA.getLocInfo() == CCValAssign::ZExt)
1265 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1266 DAG.getValueType(VA.getValVT()));
1268 if (VA.getLocInfo() != CCValAssign::Full)
1269 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1271 // Handle MMX values passed in GPRs.
1272 if (Is64Bit && RegVT != VA.getLocVT()) {
1273 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1274 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1275 else if (RC == X86::VR128RegisterClass) {
1276 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1277 DAG.getConstant(0, MVT::i64));
1278 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1282 ArgValues.push_back(ArgValue);
1284 assert(VA.isMemLoc());
1285 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1289 // The x86-64 ABI for returning structs by value requires that we copy
1290 // the sret argument into %rax for the return. Save the argument into
1291 // a virtual register so that we can access it from the return points.
1292 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1293 MachineFunction &MF = DAG.getMachineFunction();
1294 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1295 unsigned Reg = FuncInfo->getSRetReturnReg();
1297 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1298 FuncInfo->setSRetReturnReg(Reg);
1300 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1301 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1304 unsigned StackSize = CCInfo.getNextStackOffset();
1305 // align stack specially for tail calls
1306 if (PerformTailCallOpt && CC == CallingConv::Fast)
1307 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1309 // If the function takes variable number of arguments, make a frame index for
1310 // the start of the first vararg value... for expansion of llvm.va_start.
1312 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1313 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1316 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1318 // FIXME: We should really autogenerate these arrays
1319 static const unsigned GPR64ArgRegsWin64[] = {
1320 X86::RCX, X86::RDX, X86::R8, X86::R9
1322 static const unsigned XMMArgRegsWin64[] = {
1323 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1325 static const unsigned GPR64ArgRegs64Bit[] = {
1326 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1328 static const unsigned XMMArgRegs64Bit[] = {
1329 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1330 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1332 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1335 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1336 GPR64ArgRegs = GPR64ArgRegsWin64;
1337 XMMArgRegs = XMMArgRegsWin64;
1339 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1340 GPR64ArgRegs = GPR64ArgRegs64Bit;
1341 XMMArgRegs = XMMArgRegs64Bit;
1343 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1345 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1348 // For X86-64, if there are vararg parameters that are passed via
1349 // registers, then we must store them to their spots on the stack so they
1350 // may be loaded by deferencing the result of va_next.
1351 VarArgsGPOffset = NumIntRegs * 8;
1352 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1353 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1354 TotalNumXMMRegs * 16, 16);
1356 // Store the integer parameter registers.
1357 SmallVector<SDValue, 8> MemOps;
1358 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1359 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1360 DAG.getIntPtrConstant(VarArgsGPOffset));
1361 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1362 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1363 X86::GR64RegisterClass);
1364 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1366 DAG.getStore(Val.getValue(1), Val, FIN,
1367 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1368 MemOps.push_back(Store);
1369 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1370 DAG.getIntPtrConstant(8));
1373 // Now store the XMM (fp + vector) parameter registers.
1374 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1375 DAG.getIntPtrConstant(VarArgsFPOffset));
1376 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1377 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1378 X86::VR128RegisterClass);
1379 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1381 DAG.getStore(Val.getValue(1), Val, FIN,
1382 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1383 MemOps.push_back(Store);
1384 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1385 DAG.getIntPtrConstant(16));
1387 if (!MemOps.empty())
1388 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1389 &MemOps[0], MemOps.size());
1393 ArgValues.push_back(Root);
1395 // Some CCs need callee pop.
1396 if (IsCalleePop(isVarArg, CC)) {
1397 BytesToPopOnReturn = StackSize; // Callee pops everything.
1398 BytesCallerReserves = 0;
1400 BytesToPopOnReturn = 0; // Callee pops nothing.
1401 // If this is an sret function, the return should pop the hidden pointer.
1402 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1403 BytesToPopOnReturn = 4;
1404 BytesCallerReserves = StackSize;
1408 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1409 if (CC == CallingConv::X86_FastCall)
1410 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1413 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1415 // Return the new list of results.
1416 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
1417 ArgValues.size()).getValue(Op.getResNo());
1421 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1422 const SDValue &StackPtr,
1423 const CCValAssign &VA,
1425 SDValue Arg, ISD::ArgFlagsTy Flags) {
1426 unsigned LocMemOffset = VA.getLocMemOffset();
1427 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1428 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1429 if (Flags.isByVal()) {
1430 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1432 return DAG.getStore(Chain, Arg, PtrOff,
1433 PseudoSourceValue::getStack(), LocMemOffset);
1436 /// EmitTailCallLoadRetAddr - Emit a load of return adress if tail call
1437 /// optimization is performed and it is required.
1439 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1440 SDValue &OutRetAddr,
1445 if (!IsTailCall || FPDiff==0) return Chain;
1447 // Adjust the Return address stack slot.
1448 MVT VT = getPointerTy();
1449 OutRetAddr = getReturnAddressFrameIndex(DAG);
1450 // Load the "old" Return address.
1451 OutRetAddr = DAG.getLoad(VT, Chain,OutRetAddr, NULL, 0);
1452 return SDValue(OutRetAddr.getNode(), 1);
1455 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1456 /// optimization is performed and it is required (FPDiff!=0).
1458 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1459 SDValue Chain, SDValue RetAddrFrIdx,
1460 bool Is64Bit, int FPDiff) {
1461 // Store the return address to the appropriate stack slot.
1462 if (!FPDiff) return Chain;
1463 // Calculate the new stack slot for the return address.
1464 int SlotSize = Is64Bit ? 8 : 4;
1465 int NewReturnAddrFI =
1466 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1467 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1468 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1469 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1470 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1474 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1475 MachineFunction &MF = DAG.getMachineFunction();
1476 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1477 SDValue Chain = TheCall->getChain();
1478 unsigned CC = TheCall->getCallingConv();
1479 bool isVarArg = TheCall->isVarArg();
1480 bool IsTailCall = TheCall->isTailCall() &&
1481 CC == CallingConv::Fast && PerformTailCallOpt;
1482 SDValue Callee = TheCall->getCallee();
1483 bool Is64Bit = Subtarget->is64Bit();
1484 bool IsStructRet = CallIsStructReturn(TheCall);
1486 assert(!(isVarArg && CC == CallingConv::Fast) &&
1487 "Var args not supported with calling convention fastcc");
1489 // Analyze operands of the call, assigning locations to each operand.
1490 SmallVector<CCValAssign, 16> ArgLocs;
1491 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1492 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1494 // Get a count of how many bytes are to be pushed on the stack.
1495 unsigned NumBytes = CCInfo.getNextStackOffset();
1496 if (PerformTailCallOpt && CC == CallingConv::Fast)
1497 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1501 // Lower arguments at fp - stackoffset + fpdiff.
1502 unsigned NumBytesCallerPushed =
1503 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1504 FPDiff = NumBytesCallerPushed - NumBytes;
1506 // Set the delta of movement of the returnaddr stackslot.
1507 // But only set if delta is greater than previous delta.
1508 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1509 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1512 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1514 SDValue RetAddrFrIdx;
1515 // Load return adress for tail calls.
1516 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1519 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1520 SmallVector<SDValue, 8> MemOpChains;
1523 // Walk the register/memloc assignments, inserting copies/loads. In the case
1524 // of tail call optimization arguments are handle later.
1525 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1526 CCValAssign &VA = ArgLocs[i];
1527 SDValue Arg = TheCall->getArg(i);
1528 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1529 bool isByVal = Flags.isByVal();
1531 // Promote the value if needed.
1532 switch (VA.getLocInfo()) {
1533 default: assert(0 && "Unknown loc info!");
1534 case CCValAssign::Full: break;
1535 case CCValAssign::SExt:
1536 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1538 case CCValAssign::ZExt:
1539 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1541 case CCValAssign::AExt:
1542 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1546 if (VA.isRegLoc()) {
1548 MVT RegVT = VA.getLocVT();
1549 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1550 switch (VA.getLocReg()) {
1553 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1555 // Special case: passing MMX values in GPR registers.
1556 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1559 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1560 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1561 // Special case: passing MMX values in XMM registers.
1562 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1563 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1564 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1565 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1566 getMOVLMask(2, DAG));
1571 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1573 if (!IsTailCall || (IsTailCall && isByVal)) {
1574 assert(VA.isMemLoc());
1575 if (StackPtr.getNode() == 0)
1576 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1578 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1579 Chain, Arg, Flags));
1584 if (!MemOpChains.empty())
1585 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1586 &MemOpChains[0], MemOpChains.size());
1588 // Build a sequence of copy-to-reg nodes chained together with token chain
1589 // and flag operands which copy the outgoing args into registers.
1591 // Tail call byval lowering might overwrite argument registers so in case of
1592 // tail call optimization the copies to registers are lowered later.
1594 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1595 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1597 InFlag = Chain.getValue(1);
1600 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1602 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1603 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1604 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1606 InFlag = Chain.getValue(1);
1608 // If we are tail calling and generating PIC/GOT style code load the address
1609 // of the callee into ecx. The value in ecx is used as target of the tail
1610 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1611 // calls on PIC/GOT architectures. Normally we would just put the address of
1612 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1613 // restored (since ebx is callee saved) before jumping to the target@PLT.
1614 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1615 // Note: The actual moving to ecx is done further down.
1616 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1617 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1618 !G->getGlobal()->hasProtectedVisibility())
1619 Callee = LowerGlobalAddress(Callee, DAG);
1620 else if (isa<ExternalSymbolSDNode>(Callee))
1621 Callee = LowerExternalSymbol(Callee,DAG);
1624 if (Is64Bit && isVarArg) {
1625 // From AMD64 ABI document:
1626 // For calls that may call functions that use varargs or stdargs
1627 // (prototype-less calls or calls to functions containing ellipsis (...) in
1628 // the declaration) %al is used as hidden argument to specify the number
1629 // of SSE registers used. The contents of %al do not need to match exactly
1630 // the number of registers, but must be an ubound on the number of SSE
1631 // registers used and is in the range 0 - 8 inclusive.
1633 // FIXME: Verify this on Win64
1634 // Count the number of XMM registers allocated.
1635 static const unsigned XMMArgRegs[] = {
1636 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1637 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1639 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1641 Chain = DAG.getCopyToReg(Chain, X86::AL,
1642 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1643 InFlag = Chain.getValue(1);
1647 // For tail calls lower the arguments to the 'real' stack slot.
1649 SmallVector<SDValue, 8> MemOpChains2;
1652 // Do not flag preceeding copytoreg stuff together with the following stuff.
1654 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1655 CCValAssign &VA = ArgLocs[i];
1656 if (!VA.isRegLoc()) {
1657 assert(VA.isMemLoc());
1658 SDValue Arg = TheCall->getArg(i);
1659 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1660 // Create frame index.
1661 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1662 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1663 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1664 FIN = DAG.getFrameIndex(FI, getPointerTy());
1666 if (Flags.isByVal()) {
1667 // Copy relative to framepointer.
1668 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1669 if (StackPtr.getNode() == 0)
1670 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1671 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1673 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1676 // Store relative to framepointer.
1677 MemOpChains2.push_back(
1678 DAG.getStore(Chain, Arg, FIN,
1679 PseudoSourceValue::getFixedStack(FI), 0));
1684 if (!MemOpChains2.empty())
1685 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1686 &MemOpChains2[0], MemOpChains2.size());
1688 // Copy arguments to their registers.
1689 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1690 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1692 InFlag = Chain.getValue(1);
1696 // Store the return address to the appropriate stack slot.
1697 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1701 // If the callee is a GlobalAddress node (quite common, every direct call is)
1702 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1703 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1704 // We should use extra load for direct calls to dllimported functions in
1706 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1707 getTargetMachine(), true))
1708 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1710 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1711 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1712 } else if (IsTailCall) {
1713 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
1715 Chain = DAG.getCopyToReg(Chain,
1716 DAG.getRegister(Opc, getPointerTy()),
1718 Callee = DAG.getRegister(Opc, getPointerTy());
1719 // Add register as live out.
1720 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1723 // Returns a chain & a flag for retval copy to use.
1724 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1725 SmallVector<SDValue, 8> Ops;
1728 Ops.push_back(Chain);
1729 Ops.push_back(DAG.getIntPtrConstant(NumBytes, true));
1730 Ops.push_back(DAG.getIntPtrConstant(0, true));
1731 if (InFlag.getNode())
1732 Ops.push_back(InFlag);
1733 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1734 InFlag = Chain.getValue(1);
1736 // Returns a chain & a flag for retval copy to use.
1737 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1741 Ops.push_back(Chain);
1742 Ops.push_back(Callee);
1745 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1747 // Add argument registers to the end of the list so that they are known live
1749 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1750 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1751 RegsToPass[i].second.getValueType()));
1753 // Add an implicit use GOT pointer in EBX.
1754 if (!IsTailCall && !Is64Bit &&
1755 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1756 Subtarget->isPICStyleGOT())
1757 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1759 // Add an implicit use of AL for x86 vararg functions.
1760 if (Is64Bit && isVarArg)
1761 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1763 if (InFlag.getNode())
1764 Ops.push_back(InFlag);
1767 assert(InFlag.getNode() &&
1768 "Flag must be set. Depend on flag being set in LowerRET");
1769 Chain = DAG.getNode(X86ISD::TAILCALL,
1770 TheCall->getVTList(), &Ops[0], Ops.size());
1772 return SDValue(Chain.getNode(), Op.getResNo());
1775 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1776 InFlag = Chain.getValue(1);
1778 // Create the CALLSEQ_END node.
1779 unsigned NumBytesForCalleeToPush;
1780 if (IsCalleePop(isVarArg, CC))
1781 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1782 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1783 // If this is is a call to a struct-return function, the callee
1784 // pops the hidden struct pointer, so we have to push it back.
1785 // This is common for Darwin/X86, Linux & Mingw32 targets.
1786 NumBytesForCalleeToPush = 4;
1788 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1790 // Returns a flag for retval copy to use.
1791 Chain = DAG.getCALLSEQ_END(Chain,
1792 DAG.getIntPtrConstant(NumBytes, true),
1793 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1796 InFlag = Chain.getValue(1);
1798 // Handle result values, copying them out of physregs into vregs that we
1800 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1805 //===----------------------------------------------------------------------===//
1806 // Fast Calling Convention (tail call) implementation
1807 //===----------------------------------------------------------------------===//
1809 // Like std call, callee cleans arguments, convention except that ECX is
1810 // reserved for storing the tail called function address. Only 2 registers are
1811 // free for argument passing (inreg). Tail call optimization is performed
1813 // * tailcallopt is enabled
1814 // * caller/callee are fastcc
1815 // On X86_64 architecture with GOT-style position independent code only local
1816 // (within module) calls are supported at the moment.
1817 // To keep the stack aligned according to platform abi the function
1818 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1819 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1820 // If a tail called function callee has more arguments than the caller the
1821 // caller needs to make sure that there is room to move the RETADDR to. This is
1822 // achieved by reserving an area the size of the argument delta right after the
1823 // original REtADDR, but before the saved framepointer or the spilled registers
1824 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1836 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1837 /// for a 16 byte align requirement.
1838 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1839 SelectionDAG& DAG) {
1840 MachineFunction &MF = DAG.getMachineFunction();
1841 const TargetMachine &TM = MF.getTarget();
1842 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1843 unsigned StackAlignment = TFI.getStackAlignment();
1844 uint64_t AlignMask = StackAlignment - 1;
1845 int64_t Offset = StackSize;
1846 uint64_t SlotSize = TD->getPointerSize();
1847 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1848 // Number smaller than 12 so just add the difference.
1849 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1851 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1852 Offset = ((~AlignMask) & Offset) + StackAlignment +
1853 (StackAlignment-SlotSize);
1858 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1859 /// following the call is a return. A function is eligible if caller/callee
1860 /// calling conventions match, currently only fastcc supports tail calls, and
1861 /// the function CALL is immediatly followed by a RET.
1862 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1864 SelectionDAG& DAG) const {
1865 if (!PerformTailCallOpt)
1868 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1869 MachineFunction &MF = DAG.getMachineFunction();
1870 unsigned CallerCC = MF.getFunction()->getCallingConv();
1871 unsigned CalleeCC= TheCall->getCallingConv();
1872 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1873 SDValue Callee = TheCall->getCallee();
1874 // On x86/32Bit PIC/GOT tail calls are supported.
1875 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1876 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1879 // Can only do local tail calls (in same module, hidden or protected) on
1880 // x86_64 PIC/GOT at the moment.
1881 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1882 return G->getGlobal()->hasHiddenVisibility()
1883 || G->getGlobal()->hasProtectedVisibility();
1891 X86TargetLowering::createFastISel(MachineFunction &mf,
1892 MachineModuleInfo *mmo,
1893 DenseMap<const Value *, unsigned> &vm,
1894 DenseMap<const BasicBlock *,
1895 MachineBasicBlock *> &bm,
1896 DenseMap<const AllocaInst *, int> &am
1898 , SmallSet<Instruction*, 8> &cil
1901 return X86::createFastISel(mf, mmo, vm, bm, am
1909 //===----------------------------------------------------------------------===//
1910 // Other Lowering Hooks
1911 //===----------------------------------------------------------------------===//
1914 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1915 MachineFunction &MF = DAG.getMachineFunction();
1916 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1917 int ReturnAddrIndex = FuncInfo->getRAIndex();
1918 uint64_t SlotSize = TD->getPointerSize();
1920 if (ReturnAddrIndex == 0) {
1921 // Set up a frame object for the return address.
1922 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
1923 FuncInfo->setRAIndex(ReturnAddrIndex);
1926 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1930 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1931 /// specific condition code. It returns a false if it cannot do a direct
1932 /// translation. X86CC is the translated CondCode. LHS/RHS are modified as
1934 static bool translateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1935 unsigned &X86CC, SDValue &LHS, SDValue &RHS,
1936 SelectionDAG &DAG) {
1937 X86CC = X86::COND_INVALID;
1939 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1940 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1941 // X > -1 -> X == 0, jump !sign.
1942 RHS = DAG.getConstant(0, RHS.getValueType());
1943 X86CC = X86::COND_NS;
1945 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1946 // X < 0 -> X == 0, jump on sign.
1947 X86CC = X86::COND_S;
1949 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1951 RHS = DAG.getConstant(0, RHS.getValueType());
1952 X86CC = X86::COND_LE;
1957 switch (SetCCOpcode) {
1959 case ISD::SETEQ: X86CC = X86::COND_E; break;
1960 case ISD::SETGT: X86CC = X86::COND_G; break;
1961 case ISD::SETGE: X86CC = X86::COND_GE; break;
1962 case ISD::SETLT: X86CC = X86::COND_L; break;
1963 case ISD::SETLE: X86CC = X86::COND_LE; break;
1964 case ISD::SETNE: X86CC = X86::COND_NE; break;
1965 case ISD::SETULT: X86CC = X86::COND_B; break;
1966 case ISD::SETUGT: X86CC = X86::COND_A; break;
1967 case ISD::SETULE: X86CC = X86::COND_BE; break;
1968 case ISD::SETUGE: X86CC = X86::COND_AE; break;
1971 // First determine if it requires or is profitable to flip the operands.
1973 switch (SetCCOpcode) {
1983 // If LHS is a foldable load, but RHS is not, flip the condition.
1985 (ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
1986 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
1987 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
1991 std::swap(LHS, RHS);
1993 // On a floating point condition, the flags are set as follows:
1995 // 0 | 0 | 0 | X > Y
1996 // 0 | 0 | 1 | X < Y
1997 // 1 | 0 | 0 | X == Y
1998 // 1 | 1 | 1 | unordered
1999 switch (SetCCOpcode) {
2003 X86CC = X86::COND_E;
2005 case ISD::SETOLT: // flipped
2008 X86CC = X86::COND_A;
2010 case ISD::SETOLE: // flipped
2013 X86CC = X86::COND_AE;
2015 case ISD::SETUGT: // flipped
2018 X86CC = X86::COND_B;
2020 case ISD::SETUGE: // flipped
2023 X86CC = X86::COND_BE;
2027 X86CC = X86::COND_NE;
2030 X86CC = X86::COND_P;
2033 X86CC = X86::COND_NP;
2038 return X86CC != X86::COND_INVALID;
2041 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2042 /// code. Current x86 isa includes the following FP cmov instructions:
2043 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2044 static bool hasFPCMov(unsigned X86CC) {
2060 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2061 /// true if Op is undef or if its value falls within the specified range (L, H].
2062 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2063 if (Op.getOpcode() == ISD::UNDEF)
2066 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2067 return (Val >= Low && Val < Hi);
2070 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2071 /// true if Op is undef or if its value equal to the specified value.
2072 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2073 if (Op.getOpcode() == ISD::UNDEF)
2075 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2078 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2079 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2080 bool X86::isPSHUFDMask(SDNode *N) {
2081 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2083 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2086 // Check if the value doesn't reference the second vector.
2087 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2088 SDValue Arg = N->getOperand(i);
2089 if (Arg.getOpcode() == ISD::UNDEF) continue;
2090 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2091 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2098 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2099 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2100 bool X86::isPSHUFHWMask(SDNode *N) {
2101 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2103 if (N->getNumOperands() != 8)
2106 // Lower quadword copied in order.
2107 for (unsigned i = 0; i != 4; ++i) {
2108 SDValue Arg = N->getOperand(i);
2109 if (Arg.getOpcode() == ISD::UNDEF) continue;
2110 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2111 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2115 // Upper quadword shuffled.
2116 for (unsigned i = 4; i != 8; ++i) {
2117 SDValue Arg = N->getOperand(i);
2118 if (Arg.getOpcode() == ISD::UNDEF) continue;
2119 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2120 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2121 if (Val < 4 || Val > 7)
2128 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2129 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2130 bool X86::isPSHUFLWMask(SDNode *N) {
2131 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2133 if (N->getNumOperands() != 8)
2136 // Upper quadword copied in order.
2137 for (unsigned i = 4; i != 8; ++i)
2138 if (!isUndefOrEqual(N->getOperand(i), i))
2141 // Lower quadword shuffled.
2142 for (unsigned i = 0; i != 4; ++i)
2143 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2149 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2150 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2151 static bool isSHUFPMask(SDOperandPtr Elems, unsigned NumElems) {
2152 if (NumElems != 2 && NumElems != 4) return false;
2154 unsigned Half = NumElems / 2;
2155 for (unsigned i = 0; i < Half; ++i)
2156 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2158 for (unsigned i = Half; i < NumElems; ++i)
2159 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2165 bool X86::isSHUFPMask(SDNode *N) {
2166 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2167 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2170 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2171 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2172 /// half elements to come from vector 1 (which would equal the dest.) and
2173 /// the upper half to come from vector 2.
2174 static bool isCommutedSHUFP(SDOperandPtr Ops, unsigned NumOps) {
2175 if (NumOps != 2 && NumOps != 4) return false;
2177 unsigned Half = NumOps / 2;
2178 for (unsigned i = 0; i < Half; ++i)
2179 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2181 for (unsigned i = Half; i < NumOps; ++i)
2182 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2187 static bool isCommutedSHUFP(SDNode *N) {
2188 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2189 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2192 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2193 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2194 bool X86::isMOVHLPSMask(SDNode *N) {
2195 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2197 if (N->getNumOperands() != 4)
2200 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2201 return isUndefOrEqual(N->getOperand(0), 6) &&
2202 isUndefOrEqual(N->getOperand(1), 7) &&
2203 isUndefOrEqual(N->getOperand(2), 2) &&
2204 isUndefOrEqual(N->getOperand(3), 3);
2207 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2208 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2210 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2211 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2213 if (N->getNumOperands() != 4)
2216 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2217 return isUndefOrEqual(N->getOperand(0), 2) &&
2218 isUndefOrEqual(N->getOperand(1), 3) &&
2219 isUndefOrEqual(N->getOperand(2), 2) &&
2220 isUndefOrEqual(N->getOperand(3), 3);
2223 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2224 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2225 bool X86::isMOVLPMask(SDNode *N) {
2226 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2228 unsigned NumElems = N->getNumOperands();
2229 if (NumElems != 2 && NumElems != 4)
2232 for (unsigned i = 0; i < NumElems/2; ++i)
2233 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2236 for (unsigned i = NumElems/2; i < NumElems; ++i)
2237 if (!isUndefOrEqual(N->getOperand(i), i))
2243 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2244 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2246 bool X86::isMOVHPMask(SDNode *N) {
2247 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2249 unsigned NumElems = N->getNumOperands();
2250 if (NumElems != 2 && NumElems != 4)
2253 for (unsigned i = 0; i < NumElems/2; ++i)
2254 if (!isUndefOrEqual(N->getOperand(i), i))
2257 for (unsigned i = 0; i < NumElems/2; ++i) {
2258 SDValue Arg = N->getOperand(i + NumElems/2);
2259 if (!isUndefOrEqual(Arg, i + NumElems))
2266 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2267 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2268 bool static isUNPCKLMask(SDOperandPtr Elts, unsigned NumElts,
2269 bool V2IsSplat = false) {
2270 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2273 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2274 SDValue BitI = Elts[i];
2275 SDValue BitI1 = Elts[i+1];
2276 if (!isUndefOrEqual(BitI, j))
2279 if (isUndefOrEqual(BitI1, NumElts))
2282 if (!isUndefOrEqual(BitI1, j + NumElts))
2290 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2291 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2292 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2295 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2296 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2297 bool static isUNPCKHMask(SDOperandPtr Elts, unsigned NumElts,
2298 bool V2IsSplat = false) {
2299 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2302 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2303 SDValue BitI = Elts[i];
2304 SDValue BitI1 = Elts[i+1];
2305 if (!isUndefOrEqual(BitI, j + NumElts/2))
2308 if (isUndefOrEqual(BitI1, NumElts))
2311 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2319 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2320 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2321 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2324 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2325 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2327 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2328 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2330 unsigned NumElems = N->getNumOperands();
2331 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2334 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2335 SDValue BitI = N->getOperand(i);
2336 SDValue BitI1 = N->getOperand(i+1);
2338 if (!isUndefOrEqual(BitI, j))
2340 if (!isUndefOrEqual(BitI1, j))
2347 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2348 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2350 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2351 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2353 unsigned NumElems = N->getNumOperands();
2354 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2357 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2358 SDValue BitI = N->getOperand(i);
2359 SDValue BitI1 = N->getOperand(i + 1);
2361 if (!isUndefOrEqual(BitI, j))
2363 if (!isUndefOrEqual(BitI1, j))
2370 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2371 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2372 /// MOVSD, and MOVD, i.e. setting the lowest element.
2373 static bool isMOVLMask(SDOperandPtr Elts, unsigned NumElts) {
2374 if (NumElts != 2 && NumElts != 4)
2377 if (!isUndefOrEqual(Elts[0], NumElts))
2380 for (unsigned i = 1; i < NumElts; ++i) {
2381 if (!isUndefOrEqual(Elts[i], i))
2388 bool X86::isMOVLMask(SDNode *N) {
2389 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2390 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2393 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2394 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2395 /// element of vector 2 and the other elements to come from vector 1 in order.
2396 static bool isCommutedMOVL(SDOperandPtr Ops, unsigned NumOps,
2397 bool V2IsSplat = false,
2398 bool V2IsUndef = false) {
2399 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2402 if (!isUndefOrEqual(Ops[0], 0))
2405 for (unsigned i = 1; i < NumOps; ++i) {
2406 SDValue Arg = Ops[i];
2407 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2408 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2409 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2416 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2417 bool V2IsUndef = false) {
2418 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2419 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2420 V2IsSplat, V2IsUndef);
2423 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2424 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2425 bool X86::isMOVSHDUPMask(SDNode *N) {
2426 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2428 if (N->getNumOperands() != 4)
2431 // Expect 1, 1, 3, 3
2432 for (unsigned i = 0; i < 2; ++i) {
2433 SDValue Arg = N->getOperand(i);
2434 if (Arg.getOpcode() == ISD::UNDEF) continue;
2435 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2436 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2437 if (Val != 1) return false;
2441 for (unsigned i = 2; i < 4; ++i) {
2442 SDValue Arg = N->getOperand(i);
2443 if (Arg.getOpcode() == ISD::UNDEF) continue;
2444 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2445 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2446 if (Val != 3) return false;
2450 // Don't use movshdup if it can be done with a shufps.
2454 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2455 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2456 bool X86::isMOVSLDUPMask(SDNode *N) {
2457 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2459 if (N->getNumOperands() != 4)
2462 // Expect 0, 0, 2, 2
2463 for (unsigned i = 0; i < 2; ++i) {
2464 SDValue Arg = N->getOperand(i);
2465 if (Arg.getOpcode() == ISD::UNDEF) continue;
2466 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2467 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2468 if (Val != 0) return false;
2472 for (unsigned i = 2; i < 4; ++i) {
2473 SDValue Arg = N->getOperand(i);
2474 if (Arg.getOpcode() == ISD::UNDEF) continue;
2475 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2476 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2477 if (Val != 2) return false;
2481 // Don't use movshdup if it can be done with a shufps.
2485 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2486 /// specifies a identity operation on the LHS or RHS.
2487 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2488 unsigned NumElems = N->getNumOperands();
2489 for (unsigned i = 0; i < NumElems; ++i)
2490 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2495 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2496 /// a splat of a single element.
2497 static bool isSplatMask(SDNode *N) {
2498 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2500 // This is a splat operation if each element of the permute is the same, and
2501 // if the value doesn't reference the second vector.
2502 unsigned NumElems = N->getNumOperands();
2503 SDValue ElementBase;
2505 for (; i != NumElems; ++i) {
2506 SDValue Elt = N->getOperand(i);
2507 if (isa<ConstantSDNode>(Elt)) {
2513 if (!ElementBase.getNode())
2516 for (; i != NumElems; ++i) {
2517 SDValue Arg = N->getOperand(i);
2518 if (Arg.getOpcode() == ISD::UNDEF) continue;
2519 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2520 if (Arg != ElementBase) return false;
2523 // Make sure it is a splat of the first vector operand.
2524 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2527 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2528 /// a splat of a single element and it's a 2 or 4 element mask.
2529 bool X86::isSplatMask(SDNode *N) {
2530 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2532 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2533 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2535 return ::isSplatMask(N);
2538 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2539 /// specifies a splat of zero element.
2540 bool X86::isSplatLoMask(SDNode *N) {
2541 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2543 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2544 if (!isUndefOrEqual(N->getOperand(i), 0))
2549 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2550 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2551 bool X86::isMOVDDUPMask(SDNode *N) {
2552 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2554 unsigned e = N->getNumOperands() / 2;
2555 for (unsigned i = 0; i < e; ++i)
2556 if (!isUndefOrEqual(N->getOperand(i), i))
2558 for (unsigned i = 0; i < e; ++i)
2559 if (!isUndefOrEqual(N->getOperand(e+i), i))
2564 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2565 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2567 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2568 unsigned NumOperands = N->getNumOperands();
2569 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2571 for (unsigned i = 0; i < NumOperands; ++i) {
2573 SDValue Arg = N->getOperand(NumOperands-i-1);
2574 if (Arg.getOpcode() != ISD::UNDEF)
2575 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2576 if (Val >= NumOperands) Val -= NumOperands;
2578 if (i != NumOperands - 1)
2585 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2586 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2588 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2590 // 8 nodes, but we only care about the last 4.
2591 for (unsigned i = 7; i >= 4; --i) {
2593 SDValue Arg = N->getOperand(i);
2594 if (Arg.getOpcode() != ISD::UNDEF)
2595 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2604 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2605 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2607 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2609 // 8 nodes, but we only care about the first 4.
2610 for (int i = 3; i >= 0; --i) {
2612 SDValue Arg = N->getOperand(i);
2613 if (Arg.getOpcode() != ISD::UNDEF)
2614 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2623 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2624 /// specifies a 8 element shuffle that can be broken into a pair of
2625 /// PSHUFHW and PSHUFLW.
2626 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2627 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2629 if (N->getNumOperands() != 8)
2632 // Lower quadword shuffled.
2633 for (unsigned i = 0; i != 4; ++i) {
2634 SDValue Arg = N->getOperand(i);
2635 if (Arg.getOpcode() == ISD::UNDEF) continue;
2636 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2637 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2642 // Upper quadword shuffled.
2643 for (unsigned i = 4; i != 8; ++i) {
2644 SDValue Arg = N->getOperand(i);
2645 if (Arg.getOpcode() == ISD::UNDEF) continue;
2646 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2647 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2648 if (Val < 4 || Val > 7)
2655 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2656 /// values in ther permute mask.
2657 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2658 SDValue &V2, SDValue &Mask,
2659 SelectionDAG &DAG) {
2660 MVT VT = Op.getValueType();
2661 MVT MaskVT = Mask.getValueType();
2662 MVT EltVT = MaskVT.getVectorElementType();
2663 unsigned NumElems = Mask.getNumOperands();
2664 SmallVector<SDValue, 8> MaskVec;
2666 for (unsigned i = 0; i != NumElems; ++i) {
2667 SDValue Arg = Mask.getOperand(i);
2668 if (Arg.getOpcode() == ISD::UNDEF) {
2669 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2672 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2673 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2675 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2677 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2681 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2682 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2685 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2686 /// the two vector operands have swapped position.
2688 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
2689 MVT MaskVT = Mask.getValueType();
2690 MVT EltVT = MaskVT.getVectorElementType();
2691 unsigned NumElems = Mask.getNumOperands();
2692 SmallVector<SDValue, 8> MaskVec;
2693 for (unsigned i = 0; i != NumElems; ++i) {
2694 SDValue Arg = Mask.getOperand(i);
2695 if (Arg.getOpcode() == ISD::UNDEF) {
2696 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2699 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2700 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2702 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2704 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2706 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2710 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2711 /// match movhlps. The lower half elements should come from upper half of
2712 /// V1 (and in order), and the upper half elements should come from the upper
2713 /// half of V2 (and in order).
2714 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2715 unsigned NumElems = Mask->getNumOperands();
2718 for (unsigned i = 0, e = 2; i != e; ++i)
2719 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2721 for (unsigned i = 2; i != 4; ++i)
2722 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2727 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2728 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2730 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2731 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2733 N = N->getOperand(0).getNode();
2734 if (!ISD::isNON_EXTLoad(N))
2737 *LD = cast<LoadSDNode>(N);
2741 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2742 /// match movlp{s|d}. The lower half elements should come from lower half of
2743 /// V1 (and in order), and the upper half elements should come from the upper
2744 /// half of V2 (and in order). And since V1 will become the source of the
2745 /// MOVLP, it must be either a vector load or a scalar load to vector.
2746 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2747 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2749 // Is V2 is a vector load, don't do this transformation. We will try to use
2750 // load folding shufps op.
2751 if (ISD::isNON_EXTLoad(V2))
2754 unsigned NumElems = Mask->getNumOperands();
2755 if (NumElems != 2 && NumElems != 4)
2757 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2758 if (!isUndefOrEqual(Mask->getOperand(i), i))
2760 for (unsigned i = NumElems/2; i != NumElems; ++i)
2761 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2766 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2768 static bool isSplatVector(SDNode *N) {
2769 if (N->getOpcode() != ISD::BUILD_VECTOR)
2772 SDValue SplatValue = N->getOperand(0);
2773 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2774 if (N->getOperand(i) != SplatValue)
2779 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2781 static bool isUndefShuffle(SDNode *N) {
2782 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2785 SDValue V1 = N->getOperand(0);
2786 SDValue V2 = N->getOperand(1);
2787 SDValue Mask = N->getOperand(2);
2788 unsigned NumElems = Mask.getNumOperands();
2789 for (unsigned i = 0; i != NumElems; ++i) {
2790 SDValue Arg = Mask.getOperand(i);
2791 if (Arg.getOpcode() != ISD::UNDEF) {
2792 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2793 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2795 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2802 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2804 static inline bool isZeroNode(SDValue Elt) {
2805 return ((isa<ConstantSDNode>(Elt) &&
2806 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2807 (isa<ConstantFPSDNode>(Elt) &&
2808 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2811 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2812 /// to an zero vector.
2813 static bool isZeroShuffle(SDNode *N) {
2814 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2817 SDValue V1 = N->getOperand(0);
2818 SDValue V2 = N->getOperand(1);
2819 SDValue Mask = N->getOperand(2);
2820 unsigned NumElems = Mask.getNumOperands();
2821 for (unsigned i = 0; i != NumElems; ++i) {
2822 SDValue Arg = Mask.getOperand(i);
2823 if (Arg.getOpcode() == ISD::UNDEF)
2826 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2827 if (Idx < NumElems) {
2828 unsigned Opc = V1.getNode()->getOpcode();
2829 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2831 if (Opc != ISD::BUILD_VECTOR ||
2832 !isZeroNode(V1.getNode()->getOperand(Idx)))
2834 } else if (Idx >= NumElems) {
2835 unsigned Opc = V2.getNode()->getOpcode();
2836 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2838 if (Opc != ISD::BUILD_VECTOR ||
2839 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2846 /// getZeroVector - Returns a vector of specified type with all zero elements.
2848 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2849 assert(VT.isVector() && "Expected a vector type");
2851 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2852 // type. This ensures they get CSE'd.
2854 if (VT.getSizeInBits() == 64) { // MMX
2855 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2856 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2857 } else if (HasSSE2) { // SSE2
2858 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2859 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2861 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2862 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2864 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2867 /// getOnesVector - Returns a vector of specified type with all bits set.
2869 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
2870 assert(VT.isVector() && "Expected a vector type");
2872 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2873 // type. This ensures they get CSE'd.
2874 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2876 if (VT.getSizeInBits() == 64) // MMX
2877 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2879 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2880 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2884 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2885 /// that point to V2 points to its first element.
2886 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2887 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2889 bool Changed = false;
2890 SmallVector<SDValue, 8> MaskVec;
2891 unsigned NumElems = Mask.getNumOperands();
2892 for (unsigned i = 0; i != NumElems; ++i) {
2893 SDValue Arg = Mask.getOperand(i);
2894 if (Arg.getOpcode() != ISD::UNDEF) {
2895 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2896 if (Val > NumElems) {
2897 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2901 MaskVec.push_back(Arg);
2905 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2906 &MaskVec[0], MaskVec.size());
2910 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2911 /// operation of specified width.
2912 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2913 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2914 MVT BaseVT = MaskVT.getVectorElementType();
2916 SmallVector<SDValue, 8> MaskVec;
2917 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2918 for (unsigned i = 1; i != NumElems; ++i)
2919 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2920 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2923 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2924 /// of specified width.
2925 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2926 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2927 MVT BaseVT = MaskVT.getVectorElementType();
2928 SmallVector<SDValue, 8> MaskVec;
2929 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2930 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2931 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2933 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2936 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2937 /// of specified width.
2938 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2939 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2940 MVT BaseVT = MaskVT.getVectorElementType();
2941 unsigned Half = NumElems/2;
2942 SmallVector<SDValue, 8> MaskVec;
2943 for (unsigned i = 0; i != Half; ++i) {
2944 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2945 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2947 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2950 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2951 /// element #0 of a vector with the specified index, leaving the rest of the
2952 /// elements in place.
2953 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2954 SelectionDAG &DAG) {
2955 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2956 MVT BaseVT = MaskVT.getVectorElementType();
2957 SmallVector<SDValue, 8> MaskVec;
2958 // Element #0 of the result gets the elt we are replacing.
2959 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2960 for (unsigned i = 1; i != NumElems; ++i)
2961 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2962 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2965 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2966 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
2967 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
2968 MVT VT = Op.getValueType();
2971 SDValue V1 = Op.getOperand(0);
2972 SDValue Mask = Op.getOperand(2);
2973 unsigned NumElems = Mask.getNumOperands();
2974 // Special handling of v4f32 -> v4i32.
2975 if (VT != MVT::v4f32) {
2976 Mask = getUnpacklMask(NumElems, DAG);
2977 while (NumElems > 4) {
2978 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
2981 Mask = getZeroVector(MVT::v4i32, true, DAG);
2984 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
2985 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
2986 DAG.getNode(ISD::UNDEF, PVT), Mask);
2987 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
2990 /// isVectorLoad - Returns true if the node is a vector load, a scalar
2991 /// load that's promoted to vector, or a load bitcasted.
2992 static bool isVectorLoad(SDValue Op) {
2993 assert(Op.getValueType().isVector() && "Expected a vector type");
2994 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
2995 Op.getOpcode() == ISD::BIT_CONVERT) {
2996 return isa<LoadSDNode>(Op.getOperand(0));
2998 return isa<LoadSDNode>(Op);
3002 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
3004 static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
3005 SelectionDAG &DAG, bool HasSSE3) {
3006 // If we have sse3 and shuffle has more than one use or input is a load, then
3007 // use movddup. Otherwise, use movlhps.
3008 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
3009 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
3010 MVT VT = Op.getValueType();
3013 unsigned NumElems = PVT.getVectorNumElements();
3014 if (NumElems == 2) {
3015 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3016 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
3018 assert(NumElems == 4);
3019 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
3020 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
3021 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1);
3024 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3025 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3026 DAG.getNode(ISD::UNDEF, PVT), Mask);
3027 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3030 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3031 /// vector of zero or undef vector. This produces a shuffle where the low
3032 /// element of V2 is swizzled into the zero/undef vector, landing at element
3033 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3034 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3035 bool isZero, bool HasSSE2,
3036 SelectionDAG &DAG) {
3037 MVT VT = V2.getValueType();
3039 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
3040 unsigned NumElems = V2.getValueType().getVectorNumElements();
3041 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3042 MVT EVT = MaskVT.getVectorElementType();
3043 SmallVector<SDValue, 16> MaskVec;
3044 for (unsigned i = 0; i != NumElems; ++i)
3045 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
3046 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
3048 MaskVec.push_back(DAG.getConstant(i, EVT));
3049 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3050 &MaskVec[0], MaskVec.size());
3051 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3054 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3055 /// a shuffle that is zero.
3057 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
3058 unsigned NumElems, bool Low,
3059 SelectionDAG &DAG) {
3060 unsigned NumZeros = 0;
3061 for (unsigned i = 0; i < NumElems; ++i) {
3062 unsigned Index = Low ? i : NumElems-i-1;
3063 SDValue Idx = Mask.getOperand(Index);
3064 if (Idx.getOpcode() == ISD::UNDEF) {
3068 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3069 if (Elt.getNode() && isZeroNode(Elt))
3077 /// isVectorShift - Returns true if the shuffle can be implemented as a
3078 /// logical left or right shift of a vector.
3079 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3080 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3081 unsigned NumElems = Mask.getNumOperands();
3084 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3087 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3092 bool SeenV1 = false;
3093 bool SeenV2 = false;
3094 for (unsigned i = NumZeros; i < NumElems; ++i) {
3095 unsigned Val = isLeft ? (i - NumZeros) : i;
3096 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3097 if (Idx.getOpcode() == ISD::UNDEF)
3099 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3100 if (Index < NumElems)
3109 if (SeenV1 && SeenV2)
3112 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3118 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3120 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3121 unsigned NumNonZero, unsigned NumZero,
3122 SelectionDAG &DAG, TargetLowering &TLI) {
3128 for (unsigned i = 0; i < 16; ++i) {
3129 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3130 if (ThisIsNonZero && First) {
3132 V = getZeroVector(MVT::v8i16, true, DAG);
3134 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3139 SDValue ThisElt(0, 0), LastElt(0, 0);
3140 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3141 if (LastIsNonZero) {
3142 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3144 if (ThisIsNonZero) {
3145 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3146 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3147 ThisElt, DAG.getConstant(8, MVT::i8));
3149 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3153 if (ThisElt.getNode())
3154 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3155 DAG.getIntPtrConstant(i/2));
3159 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3162 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3164 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3165 unsigned NumNonZero, unsigned NumZero,
3166 SelectionDAG &DAG, TargetLowering &TLI) {
3172 for (unsigned i = 0; i < 8; ++i) {
3173 bool isNonZero = (NonZeros & (1 << i)) != 0;
3177 V = getZeroVector(MVT::v8i16, true, DAG);
3179 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3182 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3183 DAG.getIntPtrConstant(i));
3190 /// getVShift - Return a vector logical shift node.
3192 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3193 unsigned NumBits, SelectionDAG &DAG,
3194 const TargetLowering &TLI) {
3195 bool isMMX = VT.getSizeInBits() == 64;
3196 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3197 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3198 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3199 return DAG.getNode(ISD::BIT_CONVERT, VT,
3200 DAG.getNode(Opc, ShVT, SrcOp,
3201 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3205 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3206 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3207 if (ISD::isBuildVectorAllZeros(Op.getNode())
3208 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3209 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3210 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3211 // eliminated on x86-32 hosts.
3212 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3215 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3216 return getOnesVector(Op.getValueType(), DAG);
3217 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3220 MVT VT = Op.getValueType();
3221 MVT EVT = VT.getVectorElementType();
3222 unsigned EVTBits = EVT.getSizeInBits();
3224 unsigned NumElems = Op.getNumOperands();
3225 unsigned NumZero = 0;
3226 unsigned NumNonZero = 0;
3227 unsigned NonZeros = 0;
3228 bool IsAllConstants = true;
3229 SmallSet<SDValue, 8> Values;
3230 for (unsigned i = 0; i < NumElems; ++i) {
3231 SDValue Elt = Op.getOperand(i);
3232 if (Elt.getOpcode() == ISD::UNDEF)
3235 if (Elt.getOpcode() != ISD::Constant &&
3236 Elt.getOpcode() != ISD::ConstantFP)
3237 IsAllConstants = false;
3238 if (isZeroNode(Elt))
3241 NonZeros |= (1 << i);
3246 if (NumNonZero == 0) {
3247 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3248 return DAG.getNode(ISD::UNDEF, VT);
3251 // Special case for single non-zero, non-undef, element.
3252 if (NumNonZero == 1 && NumElems <= 4) {
3253 unsigned Idx = CountTrailingZeros_32(NonZeros);
3254 SDValue Item = Op.getOperand(Idx);
3256 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3257 // the value are obviously zero, truncate the value to i32 and do the
3258 // insertion that way. Only do this if the value is non-constant or if the
3259 // value is a constant being inserted into element 0. It is cheaper to do
3260 // a constant pool load than it is to do a movd + shuffle.
3261 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3262 (!IsAllConstants || Idx == 0)) {
3263 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3264 // Handle MMX and SSE both.
3265 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3266 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3268 // Truncate the value (which may itself be a constant) to i32, and
3269 // convert it to a vector with movd (S2V+shuffle to zero extend).
3270 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3271 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3272 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3273 Subtarget->hasSSE2(), DAG);
3275 // Now we have our 32-bit value zero extended in the low element of
3276 // a vector. If Idx != 0, swizzle it into place.
3279 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3280 getSwapEltZeroMask(VecElts, Idx, DAG)
3282 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3284 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3288 // If we have a constant or non-constant insertion into the low element of
3289 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3290 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3291 // depending on what the source datatype is. Because we can only get here
3292 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3294 // Don't do this for i64 values on x86-32.
3295 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3296 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3297 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3298 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3299 Subtarget->hasSSE2(), DAG);
3302 // Is it a vector logical left shift?
3303 if (NumElems == 2 && Idx == 1 &&
3304 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3305 unsigned NumBits = VT.getSizeInBits();
3306 return getVShift(true, VT,
3307 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3308 NumBits/2, DAG, *this);
3311 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3314 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3315 // is a non-constant being inserted into an element other than the low one,
3316 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3317 // movd/movss) to move this into the low element, then shuffle it into
3319 if (EVTBits == 32) {
3320 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3322 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3323 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3324 Subtarget->hasSSE2(), DAG);
3325 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3326 MVT MaskEVT = MaskVT.getVectorElementType();
3327 SmallVector<SDValue, 8> MaskVec;
3328 for (unsigned i = 0; i < NumElems; i++)
3329 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3330 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3331 &MaskVec[0], MaskVec.size());
3332 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3333 DAG.getNode(ISD::UNDEF, VT), Mask);
3337 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3338 if (Values.size() == 1)
3341 // A vector full of immediates; various special cases are already
3342 // handled, so this is best done with a single constant-pool load.
3346 // Let legalizer expand 2-wide build_vectors.
3347 if (EVTBits == 64) {
3348 if (NumNonZero == 1) {
3349 // One half is zero or undef.
3350 unsigned Idx = CountTrailingZeros_32(NonZeros);
3351 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3352 Op.getOperand(Idx));
3353 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3354 Subtarget->hasSSE2(), DAG);
3359 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3360 if (EVTBits == 8 && NumElems == 16) {
3361 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3363 if (V.getNode()) return V;
3366 if (EVTBits == 16 && NumElems == 8) {
3367 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3369 if (V.getNode()) return V;
3372 // If element VT is == 32 bits, turn it into a number of shuffles.
3373 SmallVector<SDValue, 8> V;
3375 if (NumElems == 4 && NumZero > 0) {
3376 for (unsigned i = 0; i < 4; ++i) {
3377 bool isZero = !(NonZeros & (1 << i));
3379 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3381 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3384 for (unsigned i = 0; i < 2; ++i) {
3385 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3388 V[i] = V[i*2]; // Must be a zero vector.
3391 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3392 getMOVLMask(NumElems, DAG));
3395 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3396 getMOVLMask(NumElems, DAG));
3399 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3400 getUnpacklMask(NumElems, DAG));
3405 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3406 MVT EVT = MaskVT.getVectorElementType();
3407 SmallVector<SDValue, 8> MaskVec;
3408 bool Reverse = (NonZeros & 0x3) == 2;
3409 for (unsigned i = 0; i < 2; ++i)
3411 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3413 MaskVec.push_back(DAG.getConstant(i, EVT));
3414 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3415 for (unsigned i = 0; i < 2; ++i)
3417 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3419 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3420 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3421 &MaskVec[0], MaskVec.size());
3422 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3425 if (Values.size() > 2) {
3426 // Expand into a number of unpckl*.
3428 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3429 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3430 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3431 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
3432 for (unsigned i = 0; i < NumElems; ++i)
3433 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3435 while (NumElems != 0) {
3436 for (unsigned i = 0; i < NumElems; ++i)
3437 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3448 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3449 SDValue PermMask, SelectionDAG &DAG,
3450 TargetLowering &TLI) {
3452 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3453 MVT MaskEVT = MaskVT.getVectorElementType();
3454 MVT PtrVT = TLI.getPointerTy();
3455 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3456 PermMask.getNode()->op_end());
3458 // First record which half of which vector the low elements come from.
3459 SmallVector<unsigned, 4> LowQuad(4);
3460 for (unsigned i = 0; i < 4; ++i) {
3461 SDValue Elt = MaskElts[i];
3462 if (Elt.getOpcode() == ISD::UNDEF)
3464 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3465 int QuadIdx = EltIdx / 4;
3469 int BestLowQuad = -1;
3470 unsigned MaxQuad = 1;
3471 for (unsigned i = 0; i < 4; ++i) {
3472 if (LowQuad[i] > MaxQuad) {
3474 MaxQuad = LowQuad[i];
3478 // Record which half of which vector the high elements come from.
3479 SmallVector<unsigned, 4> HighQuad(4);
3480 for (unsigned i = 4; i < 8; ++i) {
3481 SDValue Elt = MaskElts[i];
3482 if (Elt.getOpcode() == ISD::UNDEF)
3484 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3485 int QuadIdx = EltIdx / 4;
3486 ++HighQuad[QuadIdx];
3489 int BestHighQuad = -1;
3491 for (unsigned i = 0; i < 4; ++i) {
3492 if (HighQuad[i] > MaxQuad) {
3494 MaxQuad = HighQuad[i];
3498 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3499 if (BestLowQuad != -1 || BestHighQuad != -1) {
3500 // First sort the 4 chunks in order using shufpd.
3501 SmallVector<SDValue, 8> MaskVec;
3503 if (BestLowQuad != -1)
3504 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3506 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3508 if (BestHighQuad != -1)
3509 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3511 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3513 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3514 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3515 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3516 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3517 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3519 // Now sort high and low parts separately.
3520 BitVector InOrder(8);
3521 if (BestLowQuad != -1) {
3522 // Sort lower half in order using PSHUFLW.
3524 bool AnyOutOrder = false;
3526 for (unsigned i = 0; i != 4; ++i) {
3527 SDValue Elt = MaskElts[i];
3528 if (Elt.getOpcode() == ISD::UNDEF) {
3529 MaskVec.push_back(Elt);
3532 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3536 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3538 // If this element is in the right place after this shuffle, then
3540 if ((int)(EltIdx / 4) == BestLowQuad)
3545 for (unsigned i = 4; i != 8; ++i)
3546 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3547 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3548 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3552 if (BestHighQuad != -1) {
3553 // Sort high half in order using PSHUFHW if possible.
3556 for (unsigned i = 0; i != 4; ++i)
3557 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3559 bool AnyOutOrder = false;
3560 for (unsigned i = 4; i != 8; ++i) {
3561 SDValue Elt = MaskElts[i];
3562 if (Elt.getOpcode() == ISD::UNDEF) {
3563 MaskVec.push_back(Elt);
3566 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3570 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3572 // If this element is in the right place after this shuffle, then
3574 if ((int)(EltIdx / 4) == BestHighQuad)
3580 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3581 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3585 // The other elements are put in the right place using pextrw and pinsrw.
3586 for (unsigned i = 0; i != 8; ++i) {
3589 SDValue Elt = MaskElts[i];
3590 if (Elt.getOpcode() == ISD::UNDEF)
3592 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3593 SDValue ExtOp = (EltIdx < 8)
3594 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3595 DAG.getConstant(EltIdx, PtrVT))
3596 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3597 DAG.getConstant(EltIdx - 8, PtrVT));
3598 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3599 DAG.getConstant(i, PtrVT));
3605 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3606 // few as possible. First, let's find out how many elements are already in the
3608 unsigned V1InOrder = 0;
3609 unsigned V1FromV1 = 0;
3610 unsigned V2InOrder = 0;
3611 unsigned V2FromV2 = 0;
3612 SmallVector<SDValue, 8> V1Elts;
3613 SmallVector<SDValue, 8> V2Elts;
3614 for (unsigned i = 0; i < 8; ++i) {
3615 SDValue Elt = MaskElts[i];
3616 if (Elt.getOpcode() == ISD::UNDEF) {
3617 V1Elts.push_back(Elt);
3618 V2Elts.push_back(Elt);
3623 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3625 V1Elts.push_back(Elt);
3626 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3628 } else if (EltIdx == i+8) {
3629 V1Elts.push_back(Elt);
3630 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3632 } else if (EltIdx < 8) {
3633 V1Elts.push_back(Elt);
3636 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3641 if (V2InOrder > V1InOrder) {
3642 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3644 std::swap(V1Elts, V2Elts);
3645 std::swap(V1FromV1, V2FromV2);
3648 if ((V1FromV1 + V1InOrder) != 8) {
3649 // Some elements are from V2.
3651 // If there are elements that are from V1 but out of place,
3652 // then first sort them in place
3653 SmallVector<SDValue, 8> MaskVec;
3654 for (unsigned i = 0; i < 8; ++i) {
3655 SDValue Elt = V1Elts[i];
3656 if (Elt.getOpcode() == ISD::UNDEF) {
3657 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3660 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3662 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3664 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3666 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3667 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3671 for (unsigned i = 0; i < 8; ++i) {
3672 SDValue Elt = V1Elts[i];
3673 if (Elt.getOpcode() == ISD::UNDEF)
3675 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3678 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3679 DAG.getConstant(EltIdx - 8, PtrVT));
3680 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3681 DAG.getConstant(i, PtrVT));
3685 // All elements are from V1.
3687 for (unsigned i = 0; i < 8; ++i) {
3688 SDValue Elt = V1Elts[i];
3689 if (Elt.getOpcode() == ISD::UNDEF)
3691 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3692 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3693 DAG.getConstant(EltIdx, PtrVT));
3694 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3695 DAG.getConstant(i, PtrVT));
3701 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3702 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3703 /// done when every pair / quad of shuffle mask elements point to elements in
3704 /// the right sequence. e.g.
3705 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3707 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3709 SDValue PermMask, SelectionDAG &DAG,
3710 TargetLowering &TLI) {
3711 unsigned NumElems = PermMask.getNumOperands();
3712 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3713 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3714 MVT MaskEltVT = MaskVT.getVectorElementType();
3716 switch (VT.getSimpleVT()) {
3717 default: assert(false && "Unexpected!");
3718 case MVT::v4f32: NewVT = MVT::v2f64; break;
3719 case MVT::v4i32: NewVT = MVT::v2i64; break;
3720 case MVT::v8i16: NewVT = MVT::v4i32; break;
3721 case MVT::v16i8: NewVT = MVT::v4i32; break;
3724 if (NewWidth == 2) {
3730 unsigned Scale = NumElems / NewWidth;
3731 SmallVector<SDValue, 8> MaskVec;
3732 for (unsigned i = 0; i < NumElems; i += Scale) {
3733 unsigned StartIdx = ~0U;
3734 for (unsigned j = 0; j < Scale; ++j) {
3735 SDValue Elt = PermMask.getOperand(i+j);
3736 if (Elt.getOpcode() == ISD::UNDEF)
3738 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3739 if (StartIdx == ~0U)
3740 StartIdx = EltIdx - (EltIdx % Scale);
3741 if (EltIdx != StartIdx + j)
3744 if (StartIdx == ~0U)
3745 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
3747 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3750 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3751 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3752 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3753 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3754 &MaskVec[0], MaskVec.size()));
3757 /// getVZextMovL - Return a zero-extending vector move low node.
3759 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3760 SDValue SrcOp, SelectionDAG &DAG,
3761 const X86Subtarget *Subtarget) {
3762 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3763 LoadSDNode *LD = NULL;
3764 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3765 LD = dyn_cast<LoadSDNode>(SrcOp);
3767 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3769 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3770 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3771 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3772 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3773 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3775 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3776 return DAG.getNode(ISD::BIT_CONVERT, VT,
3777 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3778 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3785 return DAG.getNode(ISD::BIT_CONVERT, VT,
3786 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3787 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3790 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3793 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3794 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
3795 MVT MaskVT = PermMask.getValueType();
3796 MVT MaskEVT = MaskVT.getVectorElementType();
3797 SmallVector<std::pair<int, int>, 8> Locs;
3799 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3802 for (unsigned i = 0; i != 4; ++i) {
3803 SDValue Elt = PermMask.getOperand(i);
3804 if (Elt.getOpcode() == ISD::UNDEF) {
3805 Locs[i] = std::make_pair(-1, -1);
3807 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3808 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3810 Locs[i] = std::make_pair(0, NumLo);
3814 Locs[i] = std::make_pair(1, NumHi);
3816 Mask1[2+NumHi] = Elt;
3822 if (NumLo <= 2 && NumHi <= 2) {
3823 // If no more than two elements come from either vector. This can be
3824 // implemented with two shuffles. First shuffle gather the elements.
3825 // The second shuffle, which takes the first shuffle as both of its
3826 // vector operands, put the elements into the right order.
3827 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3828 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3829 &Mask1[0], Mask1.size()));
3831 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3832 for (unsigned i = 0; i != 4; ++i) {
3833 if (Locs[i].first == -1)
3836 unsigned Idx = (i < 2) ? 0 : 4;
3837 Idx += Locs[i].first * 2 + Locs[i].second;
3838 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3842 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3843 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3844 &Mask2[0], Mask2.size()));
3845 } else if (NumLo == 3 || NumHi == 3) {
3846 // Otherwise, we must have three elements from one vector, call it X, and
3847 // one element from the other, call it Y. First, use a shufps to build an
3848 // intermediate vector with the one element from Y and the element from X
3849 // that will be in the same half in the final destination (the indexes don't
3850 // matter). Then, use a shufps to build the final vector, taking the half
3851 // containing the element from Y from the intermediate, and the other half
3854 // Normalize it so the 3 elements come from V1.
3855 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3859 // Find the element from V2.
3861 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3862 SDValue Elt = PermMask.getOperand(HiIndex);
3863 if (Elt.getOpcode() == ISD::UNDEF)
3865 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3870 Mask1[0] = PermMask.getOperand(HiIndex);
3871 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3872 Mask1[2] = PermMask.getOperand(HiIndex^1);
3873 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3874 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3875 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3878 Mask1[0] = PermMask.getOperand(0);
3879 Mask1[1] = PermMask.getOperand(1);
3880 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3881 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3882 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3883 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3885 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3886 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3887 Mask1[2] = PermMask.getOperand(2);
3888 Mask1[3] = PermMask.getOperand(3);
3889 if (Mask1[2].getOpcode() != ISD::UNDEF)
3891 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
3893 if (Mask1[3].getOpcode() != ISD::UNDEF)
3895 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
3897 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3898 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3902 // Break it into (shuffle shuffle_hi, shuffle_lo).
3904 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3905 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3906 SmallVector<SDValue,8> *MaskPtr = &LoMask;
3907 unsigned MaskIdx = 0;
3910 for (unsigned i = 0; i != 4; ++i) {
3917 SDValue Elt = PermMask.getOperand(i);
3918 if (Elt.getOpcode() == ISD::UNDEF) {
3919 Locs[i] = std::make_pair(-1, -1);
3920 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
3921 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3922 (*MaskPtr)[LoIdx] = Elt;
3925 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3926 (*MaskPtr)[HiIdx] = Elt;
3931 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3932 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3933 &LoMask[0], LoMask.size()));
3934 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3935 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3936 &HiMask[0], HiMask.size()));
3937 SmallVector<SDValue, 8> MaskOps;
3938 for (unsigned i = 0; i != 4; ++i) {
3939 if (Locs[i].first == -1) {
3940 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3942 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3943 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3946 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3947 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3948 &MaskOps[0], MaskOps.size()));
3952 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3953 SDValue V1 = Op.getOperand(0);
3954 SDValue V2 = Op.getOperand(1);
3955 SDValue PermMask = Op.getOperand(2);
3956 MVT VT = Op.getValueType();
3957 unsigned NumElems = PermMask.getNumOperands();
3958 bool isMMX = VT.getSizeInBits() == 64;
3959 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
3960 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
3961 bool V1IsSplat = false;
3962 bool V2IsSplat = false;
3964 if (isUndefShuffle(Op.getNode()))
3965 return DAG.getNode(ISD::UNDEF, VT);
3967 if (isZeroShuffle(Op.getNode()))
3968 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3970 if (isIdentityMask(PermMask.getNode()))
3972 else if (isIdentityMask(PermMask.getNode(), true))
3975 // Canonicalize movddup shuffles.
3976 if (V2IsUndef && Subtarget->hasSSE2() &&
3977 VT.getSizeInBits() == 128 &&
3978 X86::isMOVDDUPMask(PermMask.getNode()))
3979 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
3981 if (isSplatMask(PermMask.getNode())) {
3982 if (isMMX || NumElems < 4) return Op;
3983 // Promote it to a v4{if}32 splat.
3984 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
3987 // If the shuffle can be profitably rewritten as a narrower shuffle, then
3989 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
3990 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
3991 if (NewOp.getNode())
3992 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
3993 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
3994 // FIXME: Figure out a cleaner way to do this.
3995 // Try to make use of movq to zero out the top part.
3996 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
3997 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
3999 if (NewOp.getNode()) {
4000 SDValue NewV1 = NewOp.getOperand(0);
4001 SDValue NewV2 = NewOp.getOperand(1);
4002 SDValue NewMask = NewOp.getOperand(2);
4003 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
4004 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
4005 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
4008 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4009 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4011 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
4012 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4017 // Check if this can be converted into a logical shift.
4018 bool isLeft = false;
4021 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
4022 if (isShift && ShVal.hasOneUse()) {
4023 // If the shifted value has multiple uses, it may be cheaper to use
4024 // v_set0 + movlhps or movhlps, etc.
4025 MVT EVT = VT.getVectorElementType();
4026 ShAmt *= EVT.getSizeInBits();
4027 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4030 if (X86::isMOVLMask(PermMask.getNode())) {
4033 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4034 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
4039 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
4040 X86::isMOVSLDUPMask(PermMask.getNode()) ||
4041 X86::isMOVHLPSMask(PermMask.getNode()) ||
4042 X86::isMOVHPMask(PermMask.getNode()) ||
4043 X86::isMOVLPMask(PermMask.getNode())))
4046 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
4047 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
4048 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4051 // No better options. Use a vshl / vsrl.
4052 MVT EVT = VT.getVectorElementType();
4053 ShAmt *= EVT.getSizeInBits();
4054 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4057 bool Commuted = false;
4058 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4059 // 1,1,1,1 -> v8i16 though.
4060 V1IsSplat = isSplatVector(V1.getNode());
4061 V2IsSplat = isSplatVector(V2.getNode());
4063 // Canonicalize the splat or undef, if present, to be on the RHS.
4064 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4065 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4066 std::swap(V1IsSplat, V2IsSplat);
4067 std::swap(V1IsUndef, V2IsUndef);
4071 // FIXME: Figure out a cleaner way to do this.
4072 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
4073 if (V2IsUndef) return V1;
4074 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4076 // V2 is a splat, so the mask may be malformed. That is, it may point
4077 // to any V2 element. The instruction selectior won't like this. Get
4078 // a corrected mask and commute to form a proper MOVS{S|D}.
4079 SDValue NewMask = getMOVLMask(NumElems, DAG);
4080 if (NewMask.getNode() != PermMask.getNode())
4081 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4086 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4087 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4088 X86::isUNPCKLMask(PermMask.getNode()) ||
4089 X86::isUNPCKHMask(PermMask.getNode()))
4093 // Normalize mask so all entries that point to V2 points to its first
4094 // element then try to match unpck{h|l} again. If match, return a
4095 // new vector_shuffle with the corrected mask.
4096 SDValue NewMask = NormalizeMask(PermMask, DAG);
4097 if (NewMask.getNode() != PermMask.getNode()) {
4098 if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
4099 SDValue NewMask = getUnpacklMask(NumElems, DAG);
4100 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4101 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
4102 SDValue NewMask = getUnpackhMask(NumElems, DAG);
4103 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4108 // Normalize the node to match x86 shuffle ops if needed
4109 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4110 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4113 // Commute is back and try unpck* again.
4114 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4115 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4116 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4117 X86::isUNPCKLMask(PermMask.getNode()) ||
4118 X86::isUNPCKHMask(PermMask.getNode()))
4122 // Try PSHUF* first, then SHUFP*.
4123 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4124 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4125 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4126 if (V2.getOpcode() != ISD::UNDEF)
4127 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
4128 DAG.getNode(ISD::UNDEF, VT), PermMask);
4133 if (Subtarget->hasSSE2() &&
4134 (X86::isPSHUFDMask(PermMask.getNode()) ||
4135 X86::isPSHUFHWMask(PermMask.getNode()) ||
4136 X86::isPSHUFLWMask(PermMask.getNode()))) {
4138 if (VT == MVT::v4f32) {
4140 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4141 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4142 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4143 } else if (V2.getOpcode() != ISD::UNDEF)
4144 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4145 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4147 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
4151 // Binary or unary shufps.
4152 if (X86::isSHUFPMask(PermMask.getNode()) ||
4153 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4157 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4158 if (VT == MVT::v8i16) {
4159 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
4160 if (NewOp.getNode())
4164 // Handle all 4 wide cases with a number of shuffles except for MMX.
4165 if (NumElems == 4 && !isMMX)
4166 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
4172 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4173 SelectionDAG &DAG) {
4174 MVT VT = Op.getValueType();
4175 if (VT.getSizeInBits() == 8) {
4176 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
4177 Op.getOperand(0), Op.getOperand(1));
4178 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4179 DAG.getValueType(VT));
4180 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4181 } else if (VT.getSizeInBits() == 16) {
4182 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
4183 Op.getOperand(0), Op.getOperand(1));
4184 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4185 DAG.getValueType(VT));
4186 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4187 } else if (VT == MVT::f32) {
4188 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4189 // the result back to FR32 register. It's only worth matching if the
4190 // result has a single use which is a store or a bitcast to i32.
4191 if (!Op.hasOneUse())
4193 SDNode *User = *Op.getNode()->use_begin();
4194 if (User->getOpcode() != ISD::STORE &&
4195 (User->getOpcode() != ISD::BIT_CONVERT ||
4196 User->getValueType(0) != MVT::i32))
4198 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4199 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4201 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
4208 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4209 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4212 if (Subtarget->hasSSE41()) {
4213 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4218 MVT VT = Op.getValueType();
4219 // TODO: handle v16i8.
4220 if (VT.getSizeInBits() == 16) {
4221 SDValue Vec = Op.getOperand(0);
4222 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4224 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4225 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4226 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4228 // Transform it so it match pextrw which produces a 32-bit result.
4229 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4230 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4231 Op.getOperand(0), Op.getOperand(1));
4232 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4233 DAG.getValueType(VT));
4234 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4235 } else if (VT.getSizeInBits() == 32) {
4236 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4239 // SHUFPS the element to the lowest double word, then movss.
4240 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4241 SmallVector<SDValue, 8> IdxVec;
4243 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4245 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4247 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4249 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4250 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4251 &IdxVec[0], IdxVec.size());
4252 SDValue Vec = Op.getOperand(0);
4253 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4254 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4255 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4256 DAG.getIntPtrConstant(0));
4257 } else if (VT.getSizeInBits() == 64) {
4258 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4259 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4260 // to match extract_elt for f64.
4261 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4265 // UNPCKHPD the element to the lowest double word, then movsd.
4266 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4267 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4268 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4269 SmallVector<SDValue, 8> IdxVec;
4270 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4272 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4273 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4274 &IdxVec[0], IdxVec.size());
4275 SDValue Vec = Op.getOperand(0);
4276 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4277 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4278 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4279 DAG.getIntPtrConstant(0));
4286 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4287 MVT VT = Op.getValueType();
4288 MVT EVT = VT.getVectorElementType();
4290 SDValue N0 = Op.getOperand(0);
4291 SDValue N1 = Op.getOperand(1);
4292 SDValue N2 = Op.getOperand(2);
4294 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4295 isa<ConstantSDNode>(N2)) {
4296 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4298 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4300 if (N1.getValueType() != MVT::i32)
4301 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4302 if (N2.getValueType() != MVT::i32)
4303 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4304 return DAG.getNode(Opc, VT, N0, N1, N2);
4305 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4306 // Bits [7:6] of the constant are the source select. This will always be
4307 // zero here. The DAG Combiner may combine an extract_elt index into these
4308 // bits. For example (insert (extract, 3), 2) could be matched by putting
4309 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4310 // Bits [5:4] of the constant are the destination select. This is the
4311 // value of the incoming immediate.
4312 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4313 // combine either bitwise AND or insert of float 0.0 to set these bits.
4314 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4315 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4321 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4322 MVT VT = Op.getValueType();
4323 MVT EVT = VT.getVectorElementType();
4325 if (Subtarget->hasSSE41())
4326 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4331 SDValue N0 = Op.getOperand(0);
4332 SDValue N1 = Op.getOperand(1);
4333 SDValue N2 = Op.getOperand(2);
4335 if (EVT.getSizeInBits() == 16) {
4336 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4337 // as its second argument.
4338 if (N1.getValueType() != MVT::i32)
4339 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4340 if (N2.getValueType() != MVT::i32)
4341 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4342 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4348 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4349 if (Op.getValueType() == MVT::v2f32)
4350 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4351 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4352 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4353 Op.getOperand(0))));
4355 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4356 MVT VT = MVT::v2i32;
4357 switch (Op.getValueType().getSimpleVT()) {
4364 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4365 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4368 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4369 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4370 // one of the above mentioned nodes. It has to be wrapped because otherwise
4371 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4372 // be used to form addressing mode. These wrapped nodes will be selected
4375 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4376 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4377 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4379 CP->getAlignment());
4380 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4381 // With PIC, the address is actually $g + Offset.
4382 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4383 !Subtarget->isPICStyleRIPRel()) {
4384 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4385 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4393 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV,
4395 SelectionDAG &DAG) const {
4396 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4397 bool ExtraLoadRequired =
4398 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4400 // Create the TargetGlobalAddress node, folding in the constant
4401 // offset if it is legal.
4403 if (!IsPic && !ExtraLoadRequired) {
4404 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4407 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
4408 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4410 // With PIC, the address is actually $g + Offset.
4411 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4412 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4413 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4417 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4418 // load the value at address GV, not the value of GV itself. This means that
4419 // the GlobalAddress must be in the base or index register of the address, not
4420 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4421 // The same applies for external symbols during PIC codegen
4422 if (ExtraLoadRequired)
4423 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4424 PseudoSourceValue::getGOT(), 0);
4426 // If there was a non-zero offset that we didn't fold, create an explicit
4429 Result = DAG.getNode(ISD::ADD, getPointerTy(), Result,
4430 DAG.getConstant(Offset, getPointerTy()));
4436 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4437 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4438 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4439 return LowerGlobalAddress(GV, Offset, DAG);
4442 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4444 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4447 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4448 DAG.getNode(X86ISD::GlobalBaseReg,
4450 InFlag = Chain.getValue(1);
4452 // emit leal symbol@TLSGD(,%ebx,1), %eax
4453 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4454 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4455 GA->getValueType(0),
4457 SDValue Ops[] = { Chain, TGA, InFlag };
4458 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4459 InFlag = Result.getValue(2);
4460 Chain = Result.getValue(1);
4462 // call ___tls_get_addr. This function receives its argument in
4463 // the register EAX.
4464 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4465 InFlag = Chain.getValue(1);
4467 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4468 SDValue Ops1[] = { Chain,
4469 DAG.getTargetExternalSymbol("___tls_get_addr",
4471 DAG.getRegister(X86::EAX, PtrVT),
4472 DAG.getRegister(X86::EBX, PtrVT),
4474 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4475 InFlag = Chain.getValue(1);
4477 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4480 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4482 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4484 SDValue InFlag, Chain;
4486 // emit leaq symbol@TLSGD(%rip), %rdi
4487 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4488 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4489 GA->getValueType(0),
4491 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4492 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4493 Chain = Result.getValue(1);
4494 InFlag = Result.getValue(2);
4496 // call __tls_get_addr. This function receives its argument in
4497 // the register RDI.
4498 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4499 InFlag = Chain.getValue(1);
4501 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4502 SDValue Ops1[] = { Chain,
4503 DAG.getTargetExternalSymbol("__tls_get_addr",
4505 DAG.getRegister(X86::RDI, PtrVT),
4507 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4508 InFlag = Chain.getValue(1);
4510 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4513 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4514 // "local exec" model.
4515 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4517 // Get the Thread Pointer
4518 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4519 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4521 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4522 GA->getValueType(0),
4524 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4526 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4527 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4528 PseudoSourceValue::getGOT(), 0);
4530 // The address of the thread local variable is the add of the thread
4531 // pointer with the offset of the variable.
4532 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4536 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4537 // TODO: implement the "local dynamic" model
4538 // TODO: implement the "initial exec"model for pic executables
4539 assert(Subtarget->isTargetELF() &&
4540 "TLS not implemented for non-ELF targets");
4541 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4542 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4543 // otherwise use the "Local Exec"TLS Model
4544 if (Subtarget->is64Bit()) {
4545 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4547 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4548 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4550 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4555 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4556 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4557 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4558 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4559 // With PIC, the address is actually $g + Offset.
4560 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4561 !Subtarget->isPICStyleRIPRel()) {
4562 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4563 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4570 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4571 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4572 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4573 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4574 // With PIC, the address is actually $g + Offset.
4575 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4576 !Subtarget->isPICStyleRIPRel()) {
4577 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4578 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4585 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4586 /// take a 2 x i32 value to shift plus a shift amount.
4587 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4588 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4589 MVT VT = Op.getValueType();
4590 unsigned VTBits = VT.getSizeInBits();
4591 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4592 SDValue ShOpLo = Op.getOperand(0);
4593 SDValue ShOpHi = Op.getOperand(1);
4594 SDValue ShAmt = Op.getOperand(2);
4595 SDValue Tmp1 = isSRA ?
4596 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4597 DAG.getConstant(0, VT);
4600 if (Op.getOpcode() == ISD::SHL_PARTS) {
4601 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4602 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4604 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4605 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4608 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4609 DAG.getConstant(VTBits, MVT::i8));
4610 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
4611 AndNode, DAG.getConstant(0, MVT::i8));
4614 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4615 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4616 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4618 if (Op.getOpcode() == ISD::SHL_PARTS) {
4619 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4620 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4622 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4623 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4626 SDValue Ops[2] = { Lo, Hi };
4627 return DAG.getMergeValues(Ops, 2);
4630 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4631 MVT SrcVT = Op.getOperand(0).getValueType();
4632 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4633 "Unknown SINT_TO_FP to lower!");
4635 // These are really Legal; caller falls through into that case.
4636 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4638 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4639 Subtarget->is64Bit())
4642 unsigned Size = SrcVT.getSizeInBits()/8;
4643 MachineFunction &MF = DAG.getMachineFunction();
4644 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4645 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4646 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4648 PseudoSourceValue::getFixedStack(SSFI), 0);
4652 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4654 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4656 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4657 SmallVector<SDValue, 8> Ops;
4658 Ops.push_back(Chain);
4659 Ops.push_back(StackSlot);
4660 Ops.push_back(DAG.getValueType(SrcVT));
4661 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4662 Tys, &Ops[0], Ops.size());
4665 Chain = Result.getValue(1);
4666 SDValue InFlag = Result.getValue(2);
4668 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4669 // shouldn't be necessary except that RFP cannot be live across
4670 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4671 MachineFunction &MF = DAG.getMachineFunction();
4672 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4673 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4674 Tys = DAG.getVTList(MVT::Other);
4675 SmallVector<SDValue, 8> Ops;
4676 Ops.push_back(Chain);
4677 Ops.push_back(Result);
4678 Ops.push_back(StackSlot);
4679 Ops.push_back(DAG.getValueType(Op.getValueType()));
4680 Ops.push_back(InFlag);
4681 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4682 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4683 PseudoSourceValue::getFixedStack(SSFI), 0);
4689 std::pair<SDValue,SDValue> X86TargetLowering::
4690 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
4691 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4692 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4693 "Unknown FP_TO_SINT to lower!");
4695 // These are really Legal.
4696 if (Op.getValueType() == MVT::i32 &&
4697 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4698 return std::make_pair(SDValue(), SDValue());
4699 if (Subtarget->is64Bit() &&
4700 Op.getValueType() == MVT::i64 &&
4701 Op.getOperand(0).getValueType() != MVT::f80)
4702 return std::make_pair(SDValue(), SDValue());
4704 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4706 MachineFunction &MF = DAG.getMachineFunction();
4707 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4708 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4709 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4711 switch (Op.getValueType().getSimpleVT()) {
4712 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4713 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4714 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4715 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4718 SDValue Chain = DAG.getEntryNode();
4719 SDValue Value = Op.getOperand(0);
4720 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4721 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4722 Chain = DAG.getStore(Chain, Value, StackSlot,
4723 PseudoSourceValue::getFixedStack(SSFI), 0);
4724 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4726 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4728 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4729 Chain = Value.getValue(1);
4730 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4731 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4734 // Build the FP_TO_INT*_IN_MEM
4735 SDValue Ops[] = { Chain, Value, StackSlot };
4736 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4738 return std::make_pair(FIST, StackSlot);
4741 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4742 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4743 SDValue FIST = Vals.first, StackSlot = Vals.second;
4744 if (FIST.getNode() == 0) return SDValue();
4747 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4750 SDNode *X86TargetLowering::ExpandFP_TO_SINT(SDNode *N, SelectionDAG &DAG) {
4751 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
4752 SDValue FIST = Vals.first, StackSlot = Vals.second;
4753 if (FIST.getNode() == 0) return 0;
4755 MVT VT = N->getValueType(0);
4757 // Return a load from the stack slot.
4758 SDValue Res = DAG.getLoad(VT, FIST, StackSlot, NULL, 0);
4760 // Use MERGE_VALUES to drop the chain result value and get a node with one
4761 // result. This requires turning off getMergeValues simplification, since
4762 // otherwise it will give us Res back.
4763 return DAG.getMergeValues(&Res, 1, false).getNode();
4766 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
4767 MVT VT = Op.getValueType();
4770 EltVT = VT.getVectorElementType();
4771 std::vector<Constant*> CV;
4772 if (EltVT == MVT::f64) {
4773 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4777 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4783 Constant *C = ConstantVector::get(CV);
4784 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4785 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4786 PseudoSourceValue::getConstantPool(), 0,
4788 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
4791 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
4792 MVT VT = Op.getValueType();
4794 unsigned EltNum = 1;
4795 if (VT.isVector()) {
4796 EltVT = VT.getVectorElementType();
4797 EltNum = VT.getVectorNumElements();
4799 std::vector<Constant*> CV;
4800 if (EltVT == MVT::f64) {
4801 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
4805 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
4811 Constant *C = ConstantVector::get(CV);
4812 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4813 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4814 PseudoSourceValue::getConstantPool(), 0,
4816 if (VT.isVector()) {
4817 return DAG.getNode(ISD::BIT_CONVERT, VT,
4818 DAG.getNode(ISD::XOR, MVT::v2i64,
4819 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
4820 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
4822 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
4826 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
4827 SDValue Op0 = Op.getOperand(0);
4828 SDValue Op1 = Op.getOperand(1);
4829 MVT VT = Op.getValueType();
4830 MVT SrcVT = Op1.getValueType();
4832 // If second operand is smaller, extend it first.
4833 if (SrcVT.bitsLT(VT)) {
4834 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
4837 // And if it is bigger, shrink it first.
4838 if (SrcVT.bitsGT(VT)) {
4839 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
4843 // At this point the operands and the result should have the same
4844 // type, and that won't be f80 since that is not custom lowered.
4846 // First get the sign bit of second operand.
4847 std::vector<Constant*> CV;
4848 if (SrcVT == MVT::f64) {
4849 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
4850 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4852 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
4853 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4854 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4855 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4857 Constant *C = ConstantVector::get(CV);
4858 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4859 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
4860 PseudoSourceValue::getConstantPool(), 0,
4862 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
4864 // Shift sign bit right or left if the two operands have different types.
4865 if (SrcVT.bitsGT(VT)) {
4866 // Op0 is MVT::f32, Op1 is MVT::f64.
4867 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
4868 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
4869 DAG.getConstant(32, MVT::i32));
4870 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
4871 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
4872 DAG.getIntPtrConstant(0));
4875 // Clear first operand sign bit.
4877 if (VT == MVT::f64) {
4878 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
4879 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
4881 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
4882 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4883 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4884 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
4886 C = ConstantVector::get(CV);
4887 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4888 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4889 PseudoSourceValue::getConstantPool(), 0,
4891 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
4893 // Or the value with the sign bit.
4894 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
4897 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
4898 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
4900 SDValue Op0 = Op.getOperand(0);
4901 SDValue Op1 = Op.getOperand(1);
4902 SDValue CC = Op.getOperand(2);
4903 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4906 if (translateX86CC(cast<CondCodeSDNode>(CC)->get(), isFP, X86CC,
4908 Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
4909 return DAG.getNode(X86ISD::SETCC, MVT::i8,
4910 DAG.getConstant(X86CC, MVT::i8), Cond);
4913 assert(0 && "Illegal SetCC!");
4917 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4919 SDValue Op0 = Op.getOperand(0);
4920 SDValue Op1 = Op.getOperand(1);
4921 SDValue CC = Op.getOperand(2);
4922 MVT VT = Op.getValueType();
4923 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4924 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
4928 MVT VT0 = Op0.getValueType();
4929 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
4930 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
4933 switch (SetCCOpcode) {
4936 case ISD::SETEQ: SSECC = 0; break;
4938 case ISD::SETGT: Swap = true; // Fallthrough
4940 case ISD::SETOLT: SSECC = 1; break;
4942 case ISD::SETGE: Swap = true; // Fallthrough
4944 case ISD::SETOLE: SSECC = 2; break;
4945 case ISD::SETUO: SSECC = 3; break;
4947 case ISD::SETNE: SSECC = 4; break;
4948 case ISD::SETULE: Swap = true;
4949 case ISD::SETUGE: SSECC = 5; break;
4950 case ISD::SETULT: Swap = true;
4951 case ISD::SETUGT: SSECC = 6; break;
4952 case ISD::SETO: SSECC = 7; break;
4955 std::swap(Op0, Op1);
4957 // In the two special cases we can't handle, emit two comparisons.
4959 if (SetCCOpcode == ISD::SETUEQ) {
4961 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
4962 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
4963 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
4965 else if (SetCCOpcode == ISD::SETONE) {
4967 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
4968 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
4969 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
4971 assert(0 && "Illegal FP comparison");
4973 // Handle all other FP comparisons here.
4974 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
4977 // We are handling one of the integer comparisons here. Since SSE only has
4978 // GT and EQ comparisons for integer, swapping operands and multiple
4979 // operations may be required for some comparisons.
4980 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
4981 bool Swap = false, Invert = false, FlipSigns = false;
4983 switch (VT.getSimpleVT()) {
4985 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
4986 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
4987 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
4988 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
4991 switch (SetCCOpcode) {
4993 case ISD::SETNE: Invert = true;
4994 case ISD::SETEQ: Opc = EQOpc; break;
4995 case ISD::SETLT: Swap = true;
4996 case ISD::SETGT: Opc = GTOpc; break;
4997 case ISD::SETGE: Swap = true;
4998 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
4999 case ISD::SETULT: Swap = true;
5000 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5001 case ISD::SETUGE: Swap = true;
5002 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5005 std::swap(Op0, Op1);
5007 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5008 // bits of the inputs before performing those operations.
5010 MVT EltVT = VT.getVectorElementType();
5011 SDValue SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
5012 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5013 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
5015 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
5016 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
5019 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
5021 // If the logical-not of the result is required, perform that now.
5023 MVT EltVT = VT.getVectorElementType();
5024 SDValue NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
5025 std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOne);
5026 SDValue NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
5028 Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
5033 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5034 bool addTest = true;
5035 SDValue Cond = Op.getOperand(0);
5038 if (Cond.getOpcode() == ISD::SETCC)
5039 Cond = LowerSETCC(Cond, DAG);
5041 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5042 // setting operand in place of the X86ISD::SETCC.
5043 if (Cond.getOpcode() == X86ISD::SETCC) {
5044 CC = Cond.getOperand(0);
5046 SDValue Cmp = Cond.getOperand(1);
5047 unsigned Opc = Cmp.getOpcode();
5048 MVT VT = Op.getValueType();
5050 bool IllegalFPCMov = false;
5051 if (VT.isFloatingPoint() && !VT.isVector() &&
5052 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5053 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5055 if ((Opc == X86ISD::CMP ||
5056 Opc == X86ISD::COMI ||
5057 Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
5064 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5065 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5068 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
5070 SmallVector<SDValue, 4> Ops;
5071 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5072 // condition is true.
5073 Ops.push_back(Op.getOperand(2));
5074 Ops.push_back(Op.getOperand(1));
5076 Ops.push_back(Cond);
5077 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
5080 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5081 bool addTest = true;
5082 SDValue Chain = Op.getOperand(0);
5083 SDValue Cond = Op.getOperand(1);
5084 SDValue Dest = Op.getOperand(2);
5087 if (Cond.getOpcode() == ISD::SETCC)
5088 Cond = LowerSETCC(Cond, DAG);
5090 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5091 // setting operand in place of the X86ISD::SETCC.
5092 if (Cond.getOpcode() == X86ISD::SETCC) {
5093 CC = Cond.getOperand(0);
5095 SDValue Cmp = Cond.getOperand(1);
5096 unsigned Opc = Cmp.getOpcode();
5097 if (Opc == X86ISD::CMP ||
5098 Opc == X86ISD::COMI ||
5099 Opc == X86ISD::UCOMI) {
5106 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5107 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5109 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5110 Chain, Op.getOperand(2), CC, Cond);
5114 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5115 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5116 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5117 // that the guard pages used by the OS virtual memory manager are allocated in
5118 // correct sequence.
5120 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5121 SelectionDAG &DAG) {
5122 assert(Subtarget->isTargetCygMing() &&
5123 "This should be used only on Cygwin/Mingw targets");
5126 SDValue Chain = Op.getOperand(0);
5127 SDValue Size = Op.getOperand(1);
5128 // FIXME: Ensure alignment here
5132 MVT IntPtr = getPointerTy();
5133 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5135 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5137 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
5138 Flag = Chain.getValue(1);
5140 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5141 SDValue Ops[] = { Chain,
5142 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5143 DAG.getRegister(X86::EAX, IntPtr),
5144 DAG.getRegister(X86StackPtr, SPTy),
5146 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
5147 Flag = Chain.getValue(1);
5149 Chain = DAG.getCALLSEQ_END(Chain,
5150 DAG.getIntPtrConstant(0, true),
5151 DAG.getIntPtrConstant(0, true),
5154 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
5156 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5157 return DAG.getMergeValues(Ops1, 2);
5161 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
5163 SDValue Dst, SDValue Src,
5164 SDValue Size, unsigned Align,
5166 uint64_t DstSVOff) {
5167 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5169 // If not DWORD aligned or size is more than the threshold, call the library.
5170 // The libc version is likely to be faster for these cases. It can use the
5171 // address value and run time information about the CPU.
5172 if ((Align & 3) != 0 ||
5174 ConstantSize->getZExtValue() >
5175 getSubtarget()->getMaxInlineSizeThreshold()) {
5176 SDValue InFlag(0, 0);
5178 // Check to see if there is a specialized entry-point for memory zeroing.
5179 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5181 if (const char *bzeroEntry = V &&
5182 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5183 MVT IntPtr = getPointerTy();
5184 const Type *IntPtrTy = TD->getIntPtrType();
5185 TargetLowering::ArgListTy Args;
5186 TargetLowering::ArgListEntry Entry;
5188 Entry.Ty = IntPtrTy;
5189 Args.push_back(Entry);
5191 Args.push_back(Entry);
5192 std::pair<SDValue,SDValue> CallResult =
5193 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5194 CallingConv::C, false,
5195 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG);
5196 return CallResult.second;
5199 // Otherwise have the target-independent code call memset.
5203 uint64_t SizeVal = ConstantSize->getZExtValue();
5204 SDValue InFlag(0, 0);
5207 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5208 unsigned BytesLeft = 0;
5209 bool TwoRepStos = false;
5212 uint64_t Val = ValC->getZExtValue() & 255;
5214 // If the value is a constant, then we can potentially use larger sets.
5215 switch (Align & 3) {
5216 case 2: // WORD aligned
5219 Val = (Val << 8) | Val;
5221 case 0: // DWORD aligned
5224 Val = (Val << 8) | Val;
5225 Val = (Val << 16) | Val;
5226 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5229 Val = (Val << 32) | Val;
5232 default: // Byte aligned
5235 Count = DAG.getIntPtrConstant(SizeVal);
5239 if (AVT.bitsGT(MVT::i8)) {
5240 unsigned UBytes = AVT.getSizeInBits() / 8;
5241 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5242 BytesLeft = SizeVal % UBytes;
5245 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5247 InFlag = Chain.getValue(1);
5250 Count = DAG.getIntPtrConstant(SizeVal);
5251 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
5252 InFlag = Chain.getValue(1);
5255 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5257 InFlag = Chain.getValue(1);
5258 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5260 InFlag = Chain.getValue(1);
5262 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5263 SmallVector<SDValue, 8> Ops;
5264 Ops.push_back(Chain);
5265 Ops.push_back(DAG.getValueType(AVT));
5266 Ops.push_back(InFlag);
5267 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5270 InFlag = Chain.getValue(1);
5272 MVT CVT = Count.getValueType();
5273 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
5274 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5275 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5277 InFlag = Chain.getValue(1);
5278 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5280 Ops.push_back(Chain);
5281 Ops.push_back(DAG.getValueType(MVT::i8));
5282 Ops.push_back(InFlag);
5283 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5284 } else if (BytesLeft) {
5285 // Handle the last 1 - 7 bytes.
5286 unsigned Offset = SizeVal - BytesLeft;
5287 MVT AddrVT = Dst.getValueType();
5288 MVT SizeVT = Size.getValueType();
5290 Chain = DAG.getMemset(Chain,
5291 DAG.getNode(ISD::ADD, AddrVT, Dst,
5292 DAG.getConstant(Offset, AddrVT)),
5294 DAG.getConstant(BytesLeft, SizeVT),
5295 Align, DstSV, DstSVOff + Offset);
5298 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5303 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
5304 SDValue Chain, SDValue Dst, SDValue Src,
5305 SDValue Size, unsigned Align,
5307 const Value *DstSV, uint64_t DstSVOff,
5308 const Value *SrcSV, uint64_t SrcSVOff) {
5309 // This requires the copy size to be a constant, preferrably
5310 // within a subtarget-specific limit.
5311 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5314 uint64_t SizeVal = ConstantSize->getZExtValue();
5315 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5318 /// If not DWORD aligned, call the library.
5319 if ((Align & 3) != 0)
5324 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5327 unsigned UBytes = AVT.getSizeInBits() / 8;
5328 unsigned CountVal = SizeVal / UBytes;
5329 SDValue Count = DAG.getIntPtrConstant(CountVal);
5330 unsigned BytesLeft = SizeVal % UBytes;
5332 SDValue InFlag(0, 0);
5333 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5335 InFlag = Chain.getValue(1);
5336 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5338 InFlag = Chain.getValue(1);
5339 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5341 InFlag = Chain.getValue(1);
5343 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5344 SmallVector<SDValue, 8> Ops;
5345 Ops.push_back(Chain);
5346 Ops.push_back(DAG.getValueType(AVT));
5347 Ops.push_back(InFlag);
5348 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5350 SmallVector<SDValue, 4> Results;
5351 Results.push_back(RepMovs);
5353 // Handle the last 1 - 7 bytes.
5354 unsigned Offset = SizeVal - BytesLeft;
5355 MVT DstVT = Dst.getValueType();
5356 MVT SrcVT = Src.getValueType();
5357 MVT SizeVT = Size.getValueType();
5358 Results.push_back(DAG.getMemcpy(Chain,
5359 DAG.getNode(ISD::ADD, DstVT, Dst,
5360 DAG.getConstant(Offset, DstVT)),
5361 DAG.getNode(ISD::ADD, SrcVT, Src,
5362 DAG.getConstant(Offset, SrcVT)),
5363 DAG.getConstant(BytesLeft, SizeVT),
5364 Align, AlwaysInline,
5365 DstSV, DstSVOff + Offset,
5366 SrcSV, SrcSVOff + Offset));
5369 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5372 /// Expand the result of: i64,outchain = READCYCLECOUNTER inchain
5373 SDNode *X86TargetLowering::ExpandREADCYCLECOUNTER(SDNode *N, SelectionDAG &DAG){
5374 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5375 SDValue TheChain = N->getOperand(0);
5376 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
5377 if (Subtarget->is64Bit()) {
5378 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
5379 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX,
5380 MVT::i64, rax.getValue(2));
5381 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
5382 DAG.getConstant(32, MVT::i8));
5384 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp), rdx.getValue(1)
5387 return DAG.getMergeValues(Ops, 2).getNode();
5390 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
5391 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX,
5392 MVT::i32, eax.getValue(2));
5393 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
5394 SDValue Ops[] = { eax, edx };
5395 Ops[0] = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2);
5397 // Use a MERGE_VALUES to return the value and chain.
5398 Ops[1] = edx.getValue(1);
5399 return DAG.getMergeValues(Ops, 2).getNode();
5402 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5403 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5405 if (!Subtarget->is64Bit()) {
5406 // vastart just stores the address of the VarArgsFrameIndex slot into the
5407 // memory location argument.
5408 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5409 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5413 // gp_offset (0 - 6 * 8)
5414 // fp_offset (48 - 48 + 8 * 16)
5415 // overflow_arg_area (point to parameters coming in memory).
5417 SmallVector<SDValue, 8> MemOps;
5418 SDValue FIN = Op.getOperand(1);
5420 SDValue Store = DAG.getStore(Op.getOperand(0),
5421 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5423 MemOps.push_back(Store);
5426 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5427 Store = DAG.getStore(Op.getOperand(0),
5428 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5430 MemOps.push_back(Store);
5432 // Store ptr to overflow_arg_area
5433 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5434 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5435 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5436 MemOps.push_back(Store);
5438 // Store ptr to reg_save_area.
5439 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5440 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5441 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5442 MemOps.push_back(Store);
5443 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5446 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5447 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5448 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5449 SDValue Chain = Op.getOperand(0);
5450 SDValue SrcPtr = Op.getOperand(1);
5451 SDValue SrcSV = Op.getOperand(2);
5453 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5458 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5459 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5460 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5461 SDValue Chain = Op.getOperand(0);
5462 SDValue DstPtr = Op.getOperand(1);
5463 SDValue SrcPtr = Op.getOperand(2);
5464 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5465 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5467 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5468 DAG.getIntPtrConstant(24), 8, false,
5469 DstSV, 0, SrcSV, 0);
5473 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5474 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5476 default: return SDValue(); // Don't custom lower most intrinsics.
5477 // Comparison intrinsics.
5478 case Intrinsic::x86_sse_comieq_ss:
5479 case Intrinsic::x86_sse_comilt_ss:
5480 case Intrinsic::x86_sse_comile_ss:
5481 case Intrinsic::x86_sse_comigt_ss:
5482 case Intrinsic::x86_sse_comige_ss:
5483 case Intrinsic::x86_sse_comineq_ss:
5484 case Intrinsic::x86_sse_ucomieq_ss:
5485 case Intrinsic::x86_sse_ucomilt_ss:
5486 case Intrinsic::x86_sse_ucomile_ss:
5487 case Intrinsic::x86_sse_ucomigt_ss:
5488 case Intrinsic::x86_sse_ucomige_ss:
5489 case Intrinsic::x86_sse_ucomineq_ss:
5490 case Intrinsic::x86_sse2_comieq_sd:
5491 case Intrinsic::x86_sse2_comilt_sd:
5492 case Intrinsic::x86_sse2_comile_sd:
5493 case Intrinsic::x86_sse2_comigt_sd:
5494 case Intrinsic::x86_sse2_comige_sd:
5495 case Intrinsic::x86_sse2_comineq_sd:
5496 case Intrinsic::x86_sse2_ucomieq_sd:
5497 case Intrinsic::x86_sse2_ucomilt_sd:
5498 case Intrinsic::x86_sse2_ucomile_sd:
5499 case Intrinsic::x86_sse2_ucomigt_sd:
5500 case Intrinsic::x86_sse2_ucomige_sd:
5501 case Intrinsic::x86_sse2_ucomineq_sd: {
5503 ISD::CondCode CC = ISD::SETCC_INVALID;
5506 case Intrinsic::x86_sse_comieq_ss:
5507 case Intrinsic::x86_sse2_comieq_sd:
5511 case Intrinsic::x86_sse_comilt_ss:
5512 case Intrinsic::x86_sse2_comilt_sd:
5516 case Intrinsic::x86_sse_comile_ss:
5517 case Intrinsic::x86_sse2_comile_sd:
5521 case Intrinsic::x86_sse_comigt_ss:
5522 case Intrinsic::x86_sse2_comigt_sd:
5526 case Intrinsic::x86_sse_comige_ss:
5527 case Intrinsic::x86_sse2_comige_sd:
5531 case Intrinsic::x86_sse_comineq_ss:
5532 case Intrinsic::x86_sse2_comineq_sd:
5536 case Intrinsic::x86_sse_ucomieq_ss:
5537 case Intrinsic::x86_sse2_ucomieq_sd:
5538 Opc = X86ISD::UCOMI;
5541 case Intrinsic::x86_sse_ucomilt_ss:
5542 case Intrinsic::x86_sse2_ucomilt_sd:
5543 Opc = X86ISD::UCOMI;
5546 case Intrinsic::x86_sse_ucomile_ss:
5547 case Intrinsic::x86_sse2_ucomile_sd:
5548 Opc = X86ISD::UCOMI;
5551 case Intrinsic::x86_sse_ucomigt_ss:
5552 case Intrinsic::x86_sse2_ucomigt_sd:
5553 Opc = X86ISD::UCOMI;
5556 case Intrinsic::x86_sse_ucomige_ss:
5557 case Intrinsic::x86_sse2_ucomige_sd:
5558 Opc = X86ISD::UCOMI;
5561 case Intrinsic::x86_sse_ucomineq_ss:
5562 case Intrinsic::x86_sse2_ucomineq_sd:
5563 Opc = X86ISD::UCOMI;
5569 SDValue LHS = Op.getOperand(1);
5570 SDValue RHS = Op.getOperand(2);
5571 translateX86CC(CC, true, X86CC, LHS, RHS, DAG);
5573 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5574 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5575 DAG.getConstant(X86CC, MVT::i8), Cond);
5576 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
5579 // Fix vector shift instructions where the last operand is a non-immediate
5581 case Intrinsic::x86_sse2_pslli_w:
5582 case Intrinsic::x86_sse2_pslli_d:
5583 case Intrinsic::x86_sse2_pslli_q:
5584 case Intrinsic::x86_sse2_psrli_w:
5585 case Intrinsic::x86_sse2_psrli_d:
5586 case Intrinsic::x86_sse2_psrli_q:
5587 case Intrinsic::x86_sse2_psrai_w:
5588 case Intrinsic::x86_sse2_psrai_d:
5589 case Intrinsic::x86_mmx_pslli_w:
5590 case Intrinsic::x86_mmx_pslli_d:
5591 case Intrinsic::x86_mmx_pslli_q:
5592 case Intrinsic::x86_mmx_psrli_w:
5593 case Intrinsic::x86_mmx_psrli_d:
5594 case Intrinsic::x86_mmx_psrli_q:
5595 case Intrinsic::x86_mmx_psrai_w:
5596 case Intrinsic::x86_mmx_psrai_d: {
5597 SDValue ShAmt = Op.getOperand(2);
5598 if (isa<ConstantSDNode>(ShAmt))
5601 unsigned NewIntNo = 0;
5602 MVT ShAmtVT = MVT::v4i32;
5604 case Intrinsic::x86_sse2_pslli_w:
5605 NewIntNo = Intrinsic::x86_sse2_psll_w;
5607 case Intrinsic::x86_sse2_pslli_d:
5608 NewIntNo = Intrinsic::x86_sse2_psll_d;
5610 case Intrinsic::x86_sse2_pslli_q:
5611 NewIntNo = Intrinsic::x86_sse2_psll_q;
5613 case Intrinsic::x86_sse2_psrli_w:
5614 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5616 case Intrinsic::x86_sse2_psrli_d:
5617 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5619 case Intrinsic::x86_sse2_psrli_q:
5620 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5622 case Intrinsic::x86_sse2_psrai_w:
5623 NewIntNo = Intrinsic::x86_sse2_psra_w;
5625 case Intrinsic::x86_sse2_psrai_d:
5626 NewIntNo = Intrinsic::x86_sse2_psra_d;
5629 ShAmtVT = MVT::v2i32;
5631 case Intrinsic::x86_mmx_pslli_w:
5632 NewIntNo = Intrinsic::x86_mmx_psll_w;
5634 case Intrinsic::x86_mmx_pslli_d:
5635 NewIntNo = Intrinsic::x86_mmx_psll_d;
5637 case Intrinsic::x86_mmx_pslli_q:
5638 NewIntNo = Intrinsic::x86_mmx_psll_q;
5640 case Intrinsic::x86_mmx_psrli_w:
5641 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5643 case Intrinsic::x86_mmx_psrli_d:
5644 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5646 case Intrinsic::x86_mmx_psrli_q:
5647 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5649 case Intrinsic::x86_mmx_psrai_w:
5650 NewIntNo = Intrinsic::x86_mmx_psra_w;
5652 case Intrinsic::x86_mmx_psrai_d:
5653 NewIntNo = Intrinsic::x86_mmx_psra_d;
5655 default: abort(); // Can't reach here.
5660 MVT VT = Op.getValueType();
5661 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5662 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5663 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5664 DAG.getConstant(NewIntNo, MVT::i32),
5665 Op.getOperand(1), ShAmt);
5670 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5671 // Depths > 0 not supported yet!
5672 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5675 // Just load the return address
5676 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5677 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
5680 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5681 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5682 MFI->setFrameAddressIsTaken(true);
5683 MVT VT = Op.getValueType();
5684 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5685 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
5686 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT);
5688 FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0);
5692 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
5693 SelectionDAG &DAG) {
5694 return DAG.getIntPtrConstant(2*TD->getPointerSize());
5697 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
5699 MachineFunction &MF = DAG.getMachineFunction();
5700 SDValue Chain = Op.getOperand(0);
5701 SDValue Offset = Op.getOperand(1);
5702 SDValue Handler = Op.getOperand(2);
5704 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
5706 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
5708 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
5709 DAG.getIntPtrConstant(-TD->getPointerSize()));
5710 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
5711 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
5712 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
5713 MF.getRegInfo().addLiveOut(StoreAddrReg);
5715 return DAG.getNode(X86ISD::EH_RETURN,
5717 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
5720 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
5721 SelectionDAG &DAG) {
5722 SDValue Root = Op.getOperand(0);
5723 SDValue Trmp = Op.getOperand(1); // trampoline
5724 SDValue FPtr = Op.getOperand(2); // nested function
5725 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
5727 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5729 const X86InstrInfo *TII =
5730 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
5732 if (Subtarget->is64Bit()) {
5733 SDValue OutChains[6];
5735 // Large code-model.
5737 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
5738 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
5740 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
5741 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
5743 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
5745 // Load the pointer to the nested function into R11.
5746 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
5747 SDValue Addr = Trmp;
5748 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5751 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
5752 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
5754 // Load the 'nest' parameter value into R10.
5755 // R10 is specified in X86CallingConv.td
5756 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
5757 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
5758 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5761 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
5762 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
5764 // Jump to the nested function.
5765 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
5766 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
5767 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
5770 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
5771 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
5772 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
5776 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
5777 return DAG.getMergeValues(Ops, 2);
5779 const Function *Func =
5780 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
5781 unsigned CC = Func->getCallingConv();
5786 assert(0 && "Unsupported calling convention");
5787 case CallingConv::C:
5788 case CallingConv::X86_StdCall: {
5789 // Pass 'nest' parameter in ECX.
5790 // Must be kept in sync with X86CallingConv.td
5793 // Check that ECX wasn't needed by an 'inreg' parameter.
5794 const FunctionType *FTy = Func->getFunctionType();
5795 const AttrListPtr &Attrs = Func->getAttributes();
5797 if (!Attrs.isEmpty() && !Func->isVarArg()) {
5798 unsigned InRegCount = 0;
5801 for (FunctionType::param_iterator I = FTy->param_begin(),
5802 E = FTy->param_end(); I != E; ++I, ++Idx)
5803 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
5804 // FIXME: should only count parameters that are lowered to integers.
5805 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
5807 if (InRegCount > 2) {
5808 cerr << "Nest register in use - reduce number of inreg parameters!\n";
5814 case CallingConv::X86_FastCall:
5815 case CallingConv::Fast:
5816 // Pass 'nest' parameter in EAX.
5817 // Must be kept in sync with X86CallingConv.td
5822 SDValue OutChains[4];
5825 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
5826 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
5828 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
5829 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
5830 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
5833 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
5834 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
5836 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
5837 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
5838 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
5839 TrmpAddr, 5, false, 1);
5841 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
5842 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
5845 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
5846 return DAG.getMergeValues(Ops, 2);
5850 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
5852 The rounding mode is in bits 11:10 of FPSR, and has the following
5859 FLT_ROUNDS, on the other hand, expects the following:
5866 To perform the conversion, we do:
5867 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
5870 MachineFunction &MF = DAG.getMachineFunction();
5871 const TargetMachine &TM = MF.getTarget();
5872 const TargetFrameInfo &TFI = *TM.getFrameInfo();
5873 unsigned StackAlignment = TFI.getStackAlignment();
5874 MVT VT = Op.getValueType();
5876 // Save FP Control Word to stack slot
5877 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
5878 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5880 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
5881 DAG.getEntryNode(), StackSlot);
5883 // Load FP Control Word from stack slot
5884 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
5886 // Transform as necessary
5888 DAG.getNode(ISD::SRL, MVT::i16,
5889 DAG.getNode(ISD::AND, MVT::i16,
5890 CWD, DAG.getConstant(0x800, MVT::i16)),
5891 DAG.getConstant(11, MVT::i8));
5893 DAG.getNode(ISD::SRL, MVT::i16,
5894 DAG.getNode(ISD::AND, MVT::i16,
5895 CWD, DAG.getConstant(0x400, MVT::i16)),
5896 DAG.getConstant(9, MVT::i8));
5899 DAG.getNode(ISD::AND, MVT::i16,
5900 DAG.getNode(ISD::ADD, MVT::i16,
5901 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
5902 DAG.getConstant(1, MVT::i16)),
5903 DAG.getConstant(3, MVT::i16));
5906 return DAG.getNode((VT.getSizeInBits() < 16 ?
5907 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
5910 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
5911 MVT VT = Op.getValueType();
5913 unsigned NumBits = VT.getSizeInBits();
5915 Op = Op.getOperand(0);
5916 if (VT == MVT::i8) {
5917 // Zero extend to i32 since there is not an i8 bsr.
5919 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5922 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
5923 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5924 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
5926 // If src is zero (i.e. bsr sets ZF), returns NumBits.
5927 SmallVector<SDValue, 4> Ops;
5929 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
5930 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5931 Ops.push_back(Op.getValue(1));
5932 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5934 // Finally xor with NumBits-1.
5935 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
5938 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5942 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
5943 MVT VT = Op.getValueType();
5945 unsigned NumBits = VT.getSizeInBits();
5947 Op = Op.getOperand(0);
5948 if (VT == MVT::i8) {
5950 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
5953 // Issue a bsf (scan bits forward) which also sets EFLAGS.
5954 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
5955 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
5957 // If src is zero (i.e. bsf sets ZF), returns NumBits.
5958 SmallVector<SDValue, 4> Ops;
5960 Ops.push_back(DAG.getConstant(NumBits, OpVT));
5961 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
5962 Ops.push_back(Op.getValue(1));
5963 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
5966 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
5970 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
5971 MVT T = Op.getValueType();
5974 switch(T.getSimpleVT()) {
5976 assert(false && "Invalid value type!");
5977 case MVT::i8: Reg = X86::AL; size = 1; break;
5978 case MVT::i16: Reg = X86::AX; size = 2; break;
5979 case MVT::i32: Reg = X86::EAX; size = 4; break;
5981 if (Subtarget->is64Bit()) {
5982 Reg = X86::RAX; size = 8;
5983 } else //Should go away when LegalizeType stuff lands
5984 return SDValue(ExpandATOMIC_CMP_SWAP(Op.getNode(), DAG), 0);
5987 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
5988 Op.getOperand(2), SDValue());
5989 SDValue Ops[] = { cpIn.getValue(0),
5992 DAG.getTargetConstant(size, MVT::i8),
5994 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5995 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
5997 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
6001 SDNode* X86TargetLowering::ExpandATOMIC_CMP_SWAP(SDNode* Op,
6002 SelectionDAG &DAG) {
6003 MVT T = Op->getValueType(0);
6004 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6005 SDValue cpInL, cpInH;
6006 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
6007 DAG.getConstant(0, MVT::i32));
6008 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(2),
6009 DAG.getConstant(1, MVT::i32));
6010 cpInL = DAG.getCopyToReg(Op->getOperand(0), X86::EAX,
6012 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX,
6013 cpInH, cpInL.getValue(1));
6014 SDValue swapInL, swapInH;
6015 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
6016 DAG.getConstant(0, MVT::i32));
6017 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op->getOperand(3),
6018 DAG.getConstant(1, MVT::i32));
6019 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX,
6020 swapInL, cpInH.getValue(1));
6021 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX,
6022 swapInH, swapInL.getValue(1));
6023 SDValue Ops[] = { swapInH.getValue(0),
6025 swapInH.getValue(1) };
6026 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6027 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
6028 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
6029 Result.getValue(1));
6030 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
6031 cpOutL.getValue(2));
6032 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6033 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
6034 SDValue Vals[2] = { ResultVal, cpOutH.getValue(1) };
6035 return DAG.getMergeValues(Vals, 2).getNode();
6038 SDValue X86TargetLowering::LowerATOMIC_BINARY_64(SDValue Op,
6041 SDNode *Node = Op.getNode();
6042 MVT T = Node->getValueType(0);
6043 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6045 SDValue Chain = Node->getOperand(0);
6046 SDValue In1 = Node->getOperand(1);
6047 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6048 Node->getOperand(2), DAG.getIntPtrConstant(0));
6049 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6050 Node->getOperand(2), DAG.getIntPtrConstant(1));
6051 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6052 // have a MemOperand. Pass the info through as a normal operand.
6053 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6054 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6055 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6056 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5);
6057 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6058 SDValue ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2);
6059 SDValue Vals[2] = { ResultVal, Result.getValue(2) };
6060 return SDValue(DAG.getMergeValues(Vals, 2).getNode(), 0);
6063 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6064 SDNode *Node = Op.getNode();
6065 MVT T = Node->getValueType(0);
6066 SDValue negOp = DAG.getNode(ISD::SUB, T,
6067 DAG.getConstant(0, T), Node->getOperand(2));
6068 return DAG.getAtomic((Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_8 ?
6069 ISD::ATOMIC_LOAD_ADD_8 :
6070 Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_16 ?
6071 ISD::ATOMIC_LOAD_ADD_16 :
6072 Op.getOpcode()==ISD::ATOMIC_LOAD_SUB_32 ?
6073 ISD::ATOMIC_LOAD_ADD_32 :
6074 ISD::ATOMIC_LOAD_ADD_64),
6075 Node->getOperand(0),
6076 Node->getOperand(1), negOp,
6077 cast<AtomicSDNode>(Node)->getSrcValue(),
6078 cast<AtomicSDNode>(Node)->getAlignment());
6081 /// LowerOperation - Provide custom lowering hooks for some operations.
6083 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6084 switch (Op.getOpcode()) {
6085 default: assert(0 && "Should not custom lower this!");
6086 case ISD::ATOMIC_CMP_SWAP_8:
6087 case ISD::ATOMIC_CMP_SWAP_16:
6088 case ISD::ATOMIC_CMP_SWAP_32:
6089 case ISD::ATOMIC_CMP_SWAP_64: return LowerCMP_SWAP(Op,DAG);
6090 case ISD::ATOMIC_LOAD_SUB_8:
6091 case ISD::ATOMIC_LOAD_SUB_16:
6092 case ISD::ATOMIC_LOAD_SUB_32: return LowerLOAD_SUB(Op,DAG);
6093 case ISD::ATOMIC_LOAD_SUB_64: return (Subtarget->is64Bit()) ?
6094 LowerLOAD_SUB(Op,DAG) :
6095 LowerATOMIC_BINARY_64(Op,DAG,
6096 X86ISD::ATOMSUB64_DAG);
6097 case ISD::ATOMIC_LOAD_AND_64: return LowerATOMIC_BINARY_64(Op,DAG,
6098 X86ISD::ATOMAND64_DAG);
6099 case ISD::ATOMIC_LOAD_OR_64: return LowerATOMIC_BINARY_64(Op, DAG,
6100 X86ISD::ATOMOR64_DAG);
6101 case ISD::ATOMIC_LOAD_XOR_64: return LowerATOMIC_BINARY_64(Op,DAG,
6102 X86ISD::ATOMXOR64_DAG);
6103 case ISD::ATOMIC_LOAD_NAND_64:return LowerATOMIC_BINARY_64(Op,DAG,
6104 X86ISD::ATOMNAND64_DAG);
6105 case ISD::ATOMIC_LOAD_ADD_64: return LowerATOMIC_BINARY_64(Op,DAG,
6106 X86ISD::ATOMADD64_DAG);
6107 case ISD::ATOMIC_SWAP_64: return LowerATOMIC_BINARY_64(Op,DAG,
6108 X86ISD::ATOMSWAP64_DAG);
6109 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6110 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6111 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6112 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6113 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6114 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6115 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6116 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6117 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6118 case ISD::SHL_PARTS:
6119 case ISD::SRA_PARTS:
6120 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6121 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6122 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6123 case ISD::FABS: return LowerFABS(Op, DAG);
6124 case ISD::FNEG: return LowerFNEG(Op, DAG);
6125 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6126 case ISD::SETCC: return LowerSETCC(Op, DAG);
6127 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6128 case ISD::SELECT: return LowerSELECT(Op, DAG);
6129 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6130 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6131 case ISD::CALL: return LowerCALL(Op, DAG);
6132 case ISD::RET: return LowerRET(Op, DAG);
6133 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6134 case ISD::VASTART: return LowerVASTART(Op, DAG);
6135 case ISD::VAARG: return LowerVAARG(Op, DAG);
6136 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6137 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6138 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6139 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6140 case ISD::FRAME_TO_ARGS_OFFSET:
6141 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6142 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6143 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6144 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6145 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6146 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6147 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6149 // FIXME: REMOVE THIS WHEN LegalizeDAGTypes lands.
6150 case ISD::READCYCLECOUNTER:
6151 return SDValue(ExpandREADCYCLECOUNTER(Op.getNode(), DAG), 0);
6155 /// ReplaceNodeResults - Replace a node with an illegal result type
6156 /// with a new node built out of custom code.
6157 SDNode *X86TargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
6158 switch (N->getOpcode()) {
6160 return X86TargetLowering::LowerOperation(SDValue (N, 0), DAG).getNode();
6161 case ISD::FP_TO_SINT: return ExpandFP_TO_SINT(N, DAG);
6162 case ISD::READCYCLECOUNTER: return ExpandREADCYCLECOUNTER(N, DAG);
6163 case ISD::ATOMIC_CMP_SWAP_64: return ExpandATOMIC_CMP_SWAP(N, DAG);
6167 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6169 default: return NULL;
6170 case X86ISD::BSF: return "X86ISD::BSF";
6171 case X86ISD::BSR: return "X86ISD::BSR";
6172 case X86ISD::SHLD: return "X86ISD::SHLD";
6173 case X86ISD::SHRD: return "X86ISD::SHRD";
6174 case X86ISD::FAND: return "X86ISD::FAND";
6175 case X86ISD::FOR: return "X86ISD::FOR";
6176 case X86ISD::FXOR: return "X86ISD::FXOR";
6177 case X86ISD::FSRL: return "X86ISD::FSRL";
6178 case X86ISD::FILD: return "X86ISD::FILD";
6179 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6180 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6181 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6182 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6183 case X86ISD::FLD: return "X86ISD::FLD";
6184 case X86ISD::FST: return "X86ISD::FST";
6185 case X86ISD::CALL: return "X86ISD::CALL";
6186 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6187 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6188 case X86ISD::CMP: return "X86ISD::CMP";
6189 case X86ISD::COMI: return "X86ISD::COMI";
6190 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6191 case X86ISD::SETCC: return "X86ISD::SETCC";
6192 case X86ISD::CMOV: return "X86ISD::CMOV";
6193 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6194 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6195 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6196 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6197 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6198 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6199 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6200 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6201 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6202 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6203 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6204 case X86ISD::FMAX: return "X86ISD::FMAX";
6205 case X86ISD::FMIN: return "X86ISD::FMIN";
6206 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6207 case X86ISD::FRCP: return "X86ISD::FRCP";
6208 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6209 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6210 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6211 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6212 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6213 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6214 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6215 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
6216 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
6217 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
6218 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
6219 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
6220 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
6221 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6222 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6223 case X86ISD::VSHL: return "X86ISD::VSHL";
6224 case X86ISD::VSRL: return "X86ISD::VSRL";
6225 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6226 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6227 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6228 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6229 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6230 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6231 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6232 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6233 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6234 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6238 // isLegalAddressingMode - Return true if the addressing mode represented
6239 // by AM is legal for this target, for a load/store of the specified type.
6240 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6241 const Type *Ty) const {
6242 // X86 supports extremely general addressing modes.
6244 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6245 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6249 // We can only fold this if we don't need an extra load.
6250 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6253 // X86-64 only supports addr of globals in small code model.
6254 if (Subtarget->is64Bit()) {
6255 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6257 // If lower 4G is not available, then we must use rip-relative addressing.
6258 if (AM.BaseOffs || AM.Scale > 1)
6269 // These scales always work.
6274 // These scales are formed with basereg+scalereg. Only accept if there is
6279 default: // Other stuff never works.
6287 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6288 if (!Ty1->isInteger() || !Ty2->isInteger())
6290 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6291 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6292 if (NumBits1 <= NumBits2)
6294 return Subtarget->is64Bit() || NumBits1 < 64;
6297 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6298 if (!VT1.isInteger() || !VT2.isInteger())
6300 unsigned NumBits1 = VT1.getSizeInBits();
6301 unsigned NumBits2 = VT2.getSizeInBits();
6302 if (NumBits1 <= NumBits2)
6304 return Subtarget->is64Bit() || NumBits1 < 64;
6307 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6308 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6309 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6310 /// are assumed to be legal.
6312 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6313 // Only do shuffles on 128-bit vector types for now.
6314 if (VT.getSizeInBits() == 64) return false;
6315 return (Mask.getNode()->getNumOperands() <= 4 ||
6316 isIdentityMask(Mask.getNode()) ||
6317 isIdentityMask(Mask.getNode(), true) ||
6318 isSplatMask(Mask.getNode()) ||
6319 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6320 X86::isUNPCKLMask(Mask.getNode()) ||
6321 X86::isUNPCKHMask(Mask.getNode()) ||
6322 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6323 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
6327 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6328 MVT EVT, SelectionDAG &DAG) const {
6329 unsigned NumElts = BVOps.size();
6330 // Only do shuffles on 128-bit vector types for now.
6331 if (EVT.getSizeInBits() * NumElts == 64) return false;
6332 if (NumElts == 2) return true;
6334 return (isMOVLMask(&BVOps[0], 4) ||
6335 isCommutedMOVL(&BVOps[0], 4, true) ||
6336 isSHUFPMask(&BVOps[0], 4) ||
6337 isCommutedSHUFP(&BVOps[0], 4));
6342 //===----------------------------------------------------------------------===//
6343 // X86 Scheduler Hooks
6344 //===----------------------------------------------------------------------===//
6346 // private utility function
6348 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6349 MachineBasicBlock *MBB,
6357 TargetRegisterClass *RC,
6359 // For the atomic bitwise operator, we generate
6362 // ld t1 = [bitinstr.addr]
6363 // op t2 = t1, [bitinstr.val]
6365 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6367 // fallthrough -->nextMBB
6368 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6369 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6370 MachineFunction::iterator MBBIter = MBB;
6373 /// First build the CFG
6374 MachineFunction *F = MBB->getParent();
6375 MachineBasicBlock *thisMBB = MBB;
6376 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6377 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6378 F->insert(MBBIter, newMBB);
6379 F->insert(MBBIter, nextMBB);
6381 // Move all successors to thisMBB to nextMBB
6382 nextMBB->transferSuccessors(thisMBB);
6384 // Update thisMBB to fall through to newMBB
6385 thisMBB->addSuccessor(newMBB);
6387 // newMBB jumps to itself and fall through to nextMBB
6388 newMBB->addSuccessor(nextMBB);
6389 newMBB->addSuccessor(newMBB);
6391 // Insert instructions into newMBB based on incoming instruction
6392 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6393 MachineOperand& destOper = bInstr->getOperand(0);
6394 MachineOperand* argOpers[6];
6395 int numArgs = bInstr->getNumOperands() - 1;
6396 for (int i=0; i < numArgs; ++i)
6397 argOpers[i] = &bInstr->getOperand(i+1);
6399 // x86 address has 4 operands: base, index, scale, and displacement
6400 int lastAddrIndx = 3; // [0,3]
6403 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6404 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
6405 for (int i=0; i <= lastAddrIndx; ++i)
6406 (*MIB).addOperand(*argOpers[i]);
6408 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
6410 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
6415 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6416 assert((argOpers[valArgIndx]->isReg() ||
6417 argOpers[valArgIndx]->isImm()) &&
6419 if (argOpers[valArgIndx]->isReg())
6420 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6422 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6424 (*MIB).addOperand(*argOpers[valArgIndx]);
6426 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
6429 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
6430 for (int i=0; i <= lastAddrIndx; ++i)
6431 (*MIB).addOperand(*argOpers[i]);
6433 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6434 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6436 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6440 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6442 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6446 // private utility function: 64 bit atomics on 32 bit host.
6448 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
6449 MachineBasicBlock *MBB,
6455 // For the atomic bitwise operator, we generate
6456 // thisMBB (instructions are in pairs, except cmpxchg8b)
6457 // ld t1,t2 = [bitinstr.addr]
6459 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
6460 // op t5, t6 <- out1, out2, [bitinstr.val]
6461 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
6462 // mov ECX, EBX <- t5, t6
6463 // mov EAX, EDX <- t1, t2
6464 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
6465 // mov t3, t4 <- EAX, EDX
6467 // result in out1, out2
6468 // fallthrough -->nextMBB
6470 const TargetRegisterClass *RC = X86::GR32RegisterClass;
6471 const unsigned LoadOpc = X86::MOV32rm;
6472 const unsigned copyOpc = X86::MOV32rr;
6473 const unsigned NotOpc = X86::NOT32r;
6474 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6475 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6476 MachineFunction::iterator MBBIter = MBB;
6479 /// First build the CFG
6480 MachineFunction *F = MBB->getParent();
6481 MachineBasicBlock *thisMBB = MBB;
6482 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6483 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6484 F->insert(MBBIter, newMBB);
6485 F->insert(MBBIter, nextMBB);
6487 // Move all successors to thisMBB to nextMBB
6488 nextMBB->transferSuccessors(thisMBB);
6490 // Update thisMBB to fall through to newMBB
6491 thisMBB->addSuccessor(newMBB);
6493 // newMBB jumps to itself and fall through to nextMBB
6494 newMBB->addSuccessor(nextMBB);
6495 newMBB->addSuccessor(newMBB);
6497 // Insert instructions into newMBB based on incoming instruction
6498 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
6499 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
6500 MachineOperand& dest1Oper = bInstr->getOperand(0);
6501 MachineOperand& dest2Oper = bInstr->getOperand(1);
6502 MachineOperand* argOpers[6];
6503 for (int i=0; i < 6; ++i)
6504 argOpers[i] = &bInstr->getOperand(i+2);
6506 // x86 address has 4 operands: base, index, scale, and displacement
6507 int lastAddrIndx = 3; // [0,3]
6509 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6510 MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1);
6511 for (int i=0; i <= lastAddrIndx; ++i)
6512 (*MIB).addOperand(*argOpers[i]);
6513 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6514 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2);
6515 // add 4 to displacement.
6516 for (int i=0; i <= lastAddrIndx-1; ++i)
6517 (*MIB).addOperand(*argOpers[i]);
6518 MachineOperand newOp3 = *(argOpers[3]);
6520 newOp3.setImm(newOp3.getImm()+4);
6522 newOp3.setOffset(newOp3.getOffset()+4);
6523 (*MIB).addOperand(newOp3);
6525 // t3/4 are defined later, at the bottom of the loop
6526 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
6527 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
6528 BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg())
6529 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
6530 BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg())
6531 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
6533 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
6534 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
6536 MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1);
6537 MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2);
6543 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
6545 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
6546 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
6547 if (argOpers[4]->isReg())
6548 MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
6550 MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
6551 if (regOpcL != X86::MOV32rr)
6553 (*MIB).addOperand(*argOpers[4]);
6554 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
6555 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
6556 if (argOpers[5]->isReg())
6557 MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
6559 MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
6560 if (regOpcH != X86::MOV32rr)
6562 (*MIB).addOperand(*argOpers[5]);
6564 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX);
6566 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX);
6569 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX);
6571 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX);
6574 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B));
6575 for (int i=0; i <= lastAddrIndx; ++i)
6576 (*MIB).addOperand(*argOpers[i]);
6578 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6579 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6581 MIB = BuildMI(newMBB, TII->get(copyOpc), t3);
6582 MIB.addReg(X86::EAX);
6583 MIB = BuildMI(newMBB, TII->get(copyOpc), t4);
6584 MIB.addReg(X86::EDX);
6587 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6589 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6593 // private utility function
6595 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
6596 MachineBasicBlock *MBB,
6598 // For the atomic min/max operator, we generate
6601 // ld t1 = [min/max.addr]
6602 // mov t2 = [min/max.val]
6604 // cmov[cond] t2 = t1
6606 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6608 // fallthrough -->nextMBB
6610 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6611 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6612 MachineFunction::iterator MBBIter = MBB;
6615 /// First build the CFG
6616 MachineFunction *F = MBB->getParent();
6617 MachineBasicBlock *thisMBB = MBB;
6618 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6619 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6620 F->insert(MBBIter, newMBB);
6621 F->insert(MBBIter, nextMBB);
6623 // Move all successors to thisMBB to nextMBB
6624 nextMBB->transferSuccessors(thisMBB);
6626 // Update thisMBB to fall through to newMBB
6627 thisMBB->addSuccessor(newMBB);
6629 // newMBB jumps to newMBB and fall through to nextMBB
6630 newMBB->addSuccessor(nextMBB);
6631 newMBB->addSuccessor(newMBB);
6633 // Insert instructions into newMBB based on incoming instruction
6634 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
6635 MachineOperand& destOper = mInstr->getOperand(0);
6636 MachineOperand* argOpers[6];
6637 int numArgs = mInstr->getNumOperands() - 1;
6638 for (int i=0; i < numArgs; ++i)
6639 argOpers[i] = &mInstr->getOperand(i+1);
6641 // x86 address has 4 operands: base, index, scale, and displacement
6642 int lastAddrIndx = 3; // [0,3]
6645 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6646 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
6647 for (int i=0; i <= lastAddrIndx; ++i)
6648 (*MIB).addOperand(*argOpers[i]);
6650 // We only support register and immediate values
6651 assert((argOpers[valArgIndx]->isReg() ||
6652 argOpers[valArgIndx]->isImm()) &&
6655 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6656 if (argOpers[valArgIndx]->isReg())
6657 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6659 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
6660 (*MIB).addOperand(*argOpers[valArgIndx]);
6662 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
6665 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
6670 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
6671 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
6675 // Cmp and exchange if none has modified the memory location
6676 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
6677 for (int i=0; i <= lastAddrIndx; ++i)
6678 (*MIB).addOperand(*argOpers[i]);
6680 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6681 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
6683 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
6684 MIB.addReg(X86::EAX);
6687 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6689 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
6695 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6696 MachineBasicBlock *BB) {
6697 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6698 switch (MI->getOpcode()) {
6699 default: assert(false && "Unexpected instr type to insert");
6700 case X86::CMOV_FR32:
6701 case X86::CMOV_FR64:
6702 case X86::CMOV_V4F32:
6703 case X86::CMOV_V2F64:
6704 case X86::CMOV_V2I64: {
6705 // To "insert" a SELECT_CC instruction, we actually have to insert the
6706 // diamond control-flow pattern. The incoming instruction knows the
6707 // destination vreg to set, the condition code register to branch on, the
6708 // true/false values to select between, and a branch opcode to use.
6709 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6710 MachineFunction::iterator It = BB;
6716 // cmpTY ccX, r1, r2
6718 // fallthrough --> copy0MBB
6719 MachineBasicBlock *thisMBB = BB;
6720 MachineFunction *F = BB->getParent();
6721 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6722 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6724 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
6725 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
6726 F->insert(It, copy0MBB);
6727 F->insert(It, sinkMBB);
6728 // Update machine-CFG edges by transferring all successors of the current
6729 // block to the new block which will contain the Phi node for the select.
6730 sinkMBB->transferSuccessors(BB);
6732 // Add the true and fallthrough blocks as its successors.
6733 BB->addSuccessor(copy0MBB);
6734 BB->addSuccessor(sinkMBB);
6737 // %FalseValue = ...
6738 // # fallthrough to sinkMBB
6741 // Update machine-CFG edges
6742 BB->addSuccessor(sinkMBB);
6745 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6748 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
6749 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6750 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6752 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6756 case X86::FP32_TO_INT16_IN_MEM:
6757 case X86::FP32_TO_INT32_IN_MEM:
6758 case X86::FP32_TO_INT64_IN_MEM:
6759 case X86::FP64_TO_INT16_IN_MEM:
6760 case X86::FP64_TO_INT32_IN_MEM:
6761 case X86::FP64_TO_INT64_IN_MEM:
6762 case X86::FP80_TO_INT16_IN_MEM:
6763 case X86::FP80_TO_INT32_IN_MEM:
6764 case X86::FP80_TO_INT64_IN_MEM: {
6765 // Change the floating point control register to use "round towards zero"
6766 // mode when truncating to an integer value.
6767 MachineFunction *F = BB->getParent();
6768 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
6769 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
6771 // Load the old value of the high byte of the control word...
6773 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
6774 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
6776 // Set the high part to be round to zero...
6777 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
6780 // Reload the modified control word now...
6781 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6783 // Restore the memory image of control word to original value
6784 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
6787 // Get the X86 opcode to use.
6789 switch (MI->getOpcode()) {
6790 default: assert(0 && "illegal opcode!");
6791 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
6792 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
6793 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
6794 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
6795 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
6796 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
6797 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
6798 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
6799 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
6803 MachineOperand &Op = MI->getOperand(0);
6805 AM.BaseType = X86AddressMode::RegBase;
6806 AM.Base.Reg = Op.getReg();
6808 AM.BaseType = X86AddressMode::FrameIndexBase;
6809 AM.Base.FrameIndex = Op.getIndex();
6811 Op = MI->getOperand(1);
6813 AM.Scale = Op.getImm();
6814 Op = MI->getOperand(2);
6816 AM.IndexReg = Op.getImm();
6817 Op = MI->getOperand(3);
6818 if (Op.isGlobal()) {
6819 AM.GV = Op.getGlobal();
6821 AM.Disp = Op.getImm();
6823 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
6824 .addReg(MI->getOperand(4).getReg());
6826 // Reload the original control word now.
6827 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
6829 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
6832 case X86::ATOMAND32:
6833 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6834 X86::AND32ri, X86::MOV32rm,
6835 X86::LCMPXCHG32, X86::MOV32rr,
6836 X86::NOT32r, X86::EAX,
6837 X86::GR32RegisterClass);
6839 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
6840 X86::OR32ri, X86::MOV32rm,
6841 X86::LCMPXCHG32, X86::MOV32rr,
6842 X86::NOT32r, X86::EAX,
6843 X86::GR32RegisterClass);
6844 case X86::ATOMXOR32:
6845 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
6846 X86::XOR32ri, X86::MOV32rm,
6847 X86::LCMPXCHG32, X86::MOV32rr,
6848 X86::NOT32r, X86::EAX,
6849 X86::GR32RegisterClass);
6850 case X86::ATOMNAND32:
6851 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
6852 X86::AND32ri, X86::MOV32rm,
6853 X86::LCMPXCHG32, X86::MOV32rr,
6854 X86::NOT32r, X86::EAX,
6855 X86::GR32RegisterClass, true);
6856 case X86::ATOMMIN32:
6857 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
6858 case X86::ATOMMAX32:
6859 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
6860 case X86::ATOMUMIN32:
6861 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
6862 case X86::ATOMUMAX32:
6863 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
6865 case X86::ATOMAND16:
6866 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6867 X86::AND16ri, X86::MOV16rm,
6868 X86::LCMPXCHG16, X86::MOV16rr,
6869 X86::NOT16r, X86::AX,
6870 X86::GR16RegisterClass);
6872 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
6873 X86::OR16ri, X86::MOV16rm,
6874 X86::LCMPXCHG16, X86::MOV16rr,
6875 X86::NOT16r, X86::AX,
6876 X86::GR16RegisterClass);
6877 case X86::ATOMXOR16:
6878 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
6879 X86::XOR16ri, X86::MOV16rm,
6880 X86::LCMPXCHG16, X86::MOV16rr,
6881 X86::NOT16r, X86::AX,
6882 X86::GR16RegisterClass);
6883 case X86::ATOMNAND16:
6884 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
6885 X86::AND16ri, X86::MOV16rm,
6886 X86::LCMPXCHG16, X86::MOV16rr,
6887 X86::NOT16r, X86::AX,
6888 X86::GR16RegisterClass, true);
6889 case X86::ATOMMIN16:
6890 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
6891 case X86::ATOMMAX16:
6892 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
6893 case X86::ATOMUMIN16:
6894 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
6895 case X86::ATOMUMAX16:
6896 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
6899 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6900 X86::AND8ri, X86::MOV8rm,
6901 X86::LCMPXCHG8, X86::MOV8rr,
6902 X86::NOT8r, X86::AL,
6903 X86::GR8RegisterClass);
6905 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
6906 X86::OR8ri, X86::MOV8rm,
6907 X86::LCMPXCHG8, X86::MOV8rr,
6908 X86::NOT8r, X86::AL,
6909 X86::GR8RegisterClass);
6911 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
6912 X86::XOR8ri, X86::MOV8rm,
6913 X86::LCMPXCHG8, X86::MOV8rr,
6914 X86::NOT8r, X86::AL,
6915 X86::GR8RegisterClass);
6916 case X86::ATOMNAND8:
6917 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
6918 X86::AND8ri, X86::MOV8rm,
6919 X86::LCMPXCHG8, X86::MOV8rr,
6920 X86::NOT8r, X86::AL,
6921 X86::GR8RegisterClass, true);
6922 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
6923 // This group is for 64-bit host.
6924 case X86::ATOMAND64:
6925 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6926 X86::AND64ri32, X86::MOV64rm,
6927 X86::LCMPXCHG64, X86::MOV64rr,
6928 X86::NOT64r, X86::RAX,
6929 X86::GR64RegisterClass);
6931 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
6932 X86::OR64ri32, X86::MOV64rm,
6933 X86::LCMPXCHG64, X86::MOV64rr,
6934 X86::NOT64r, X86::RAX,
6935 X86::GR64RegisterClass);
6936 case X86::ATOMXOR64:
6937 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
6938 X86::XOR64ri32, X86::MOV64rm,
6939 X86::LCMPXCHG64, X86::MOV64rr,
6940 X86::NOT64r, X86::RAX,
6941 X86::GR64RegisterClass);
6942 case X86::ATOMNAND64:
6943 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
6944 X86::AND64ri32, X86::MOV64rm,
6945 X86::LCMPXCHG64, X86::MOV64rr,
6946 X86::NOT64r, X86::RAX,
6947 X86::GR64RegisterClass, true);
6948 case X86::ATOMMIN64:
6949 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
6950 case X86::ATOMMAX64:
6951 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
6952 case X86::ATOMUMIN64:
6953 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
6954 case X86::ATOMUMAX64:
6955 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
6957 // This group does 64-bit operations on a 32-bit host.
6958 case X86::ATOMAND6432:
6959 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6960 X86::AND32rr, X86::AND32rr,
6961 X86::AND32ri, X86::AND32ri,
6963 case X86::ATOMOR6432:
6964 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6965 X86::OR32rr, X86::OR32rr,
6966 X86::OR32ri, X86::OR32ri,
6968 case X86::ATOMXOR6432:
6969 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6970 X86::XOR32rr, X86::XOR32rr,
6971 X86::XOR32ri, X86::XOR32ri,
6973 case X86::ATOMNAND6432:
6974 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6975 X86::AND32rr, X86::AND32rr,
6976 X86::AND32ri, X86::AND32ri,
6978 case X86::ATOMADD6432:
6979 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6980 X86::ADD32rr, X86::ADC32rr,
6981 X86::ADD32ri, X86::ADC32ri,
6983 case X86::ATOMSUB6432:
6984 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6985 X86::SUB32rr, X86::SBB32rr,
6986 X86::SUB32ri, X86::SBB32ri,
6988 case X86::ATOMSWAP6432:
6989 return EmitAtomicBit6432WithCustomInserter(MI, BB,
6990 X86::MOV32rr, X86::MOV32rr,
6991 X86::MOV32ri, X86::MOV32ri,
6996 //===----------------------------------------------------------------------===//
6997 // X86 Optimization Hooks
6998 //===----------------------------------------------------------------------===//
7000 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7004 const SelectionDAG &DAG,
7005 unsigned Depth) const {
7006 unsigned Opc = Op.getOpcode();
7007 assert((Opc >= ISD::BUILTIN_OP_END ||
7008 Opc == ISD::INTRINSIC_WO_CHAIN ||
7009 Opc == ISD::INTRINSIC_W_CHAIN ||
7010 Opc == ISD::INTRINSIC_VOID) &&
7011 "Should use MaskedValueIsZero if you don't know whether Op"
7012 " is a target node!");
7014 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7018 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7019 Mask.getBitWidth() - 1);
7024 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7025 /// node is a GlobalAddress + offset.
7026 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7027 GlobalValue* &GA, int64_t &Offset) const{
7028 if (N->getOpcode() == X86ISD::Wrapper) {
7029 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7030 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7031 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7035 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7038 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7039 const TargetLowering &TLI) {
7042 if (TLI.isGAPlusOffset(Base, GV, Offset))
7043 return (GV->getAlignment() >= N && (Offset % N) == 0);
7044 // DAG combine handles the stack object case.
7048 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
7049 unsigned NumElems, MVT EVT,
7051 SelectionDAG &DAG, MachineFrameInfo *MFI,
7052 const TargetLowering &TLI) {
7054 for (unsigned i = 0; i < NumElems; ++i) {
7055 SDValue Idx = PermMask.getOperand(i);
7056 if (Idx.getOpcode() == ISD::UNDEF) {
7062 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7063 if (!Elt.getNode() ||
7064 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7067 Base = Elt.getNode();
7068 if (Base->getOpcode() == ISD::UNDEF)
7072 if (Elt.getOpcode() == ISD::UNDEF)
7075 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
7076 EVT.getSizeInBits()/8, i, MFI))
7082 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7083 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7084 /// if the load addresses are consecutive, non-overlapping, and in the right
7086 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7087 const TargetLowering &TLI) {
7088 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7089 MVT VT = N->getValueType(0);
7090 MVT EVT = VT.getVectorElementType();
7091 SDValue PermMask = N->getOperand(2);
7092 unsigned NumElems = PermMask.getNumOperands();
7093 SDNode *Base = NULL;
7094 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
7098 LoadSDNode *LD = cast<LoadSDNode>(Base);
7099 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
7100 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7101 LD->getSrcValueOffset(), LD->isVolatile());
7102 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7103 LD->getSrcValueOffset(), LD->isVolatile(),
7104 LD->getAlignment());
7107 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
7108 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
7109 const X86Subtarget *Subtarget,
7110 const TargetLowering &TLI) {
7111 unsigned NumOps = N->getNumOperands();
7113 // Ignore single operand BUILD_VECTOR.
7117 MVT VT = N->getValueType(0);
7118 MVT EVT = VT.getVectorElementType();
7119 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
7120 // We are looking for load i64 and zero extend. We want to transform
7121 // it before legalizer has a chance to expand it. Also look for i64
7122 // BUILD_PAIR bit casted to f64.
7124 // This must be an insertion into a zero vector.
7125 SDValue HighElt = N->getOperand(1);
7126 if (!isZeroNode(HighElt))
7129 // Value must be a load.
7130 SDNode *Base = N->getOperand(0).getNode();
7131 if (!isa<LoadSDNode>(Base)) {
7132 if (Base->getOpcode() != ISD::BIT_CONVERT)
7134 Base = Base->getOperand(0).getNode();
7135 if (!isa<LoadSDNode>(Base))
7139 // Transform it into VZEXT_LOAD addr.
7140 LoadSDNode *LD = cast<LoadSDNode>(Base);
7142 // Load must not be an extload.
7143 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
7146 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
7147 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7148 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
7149 DAG.ReplaceAllUsesOfValueWith(SDValue(Base, 1), ResNode.getValue(1));
7153 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7154 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7155 const X86Subtarget *Subtarget) {
7156 SDValue Cond = N->getOperand(0);
7158 // If we have SSE[12] support, try to form min/max nodes.
7159 if (Subtarget->hasSSE2() &&
7160 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
7161 if (Cond.getOpcode() == ISD::SETCC) {
7162 // Get the LHS/RHS of the select.
7163 SDValue LHS = N->getOperand(1);
7164 SDValue RHS = N->getOperand(2);
7165 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
7167 unsigned Opcode = 0;
7168 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7171 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
7174 if (!UnsafeFPMath) break;
7176 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
7178 Opcode = X86ISD::FMIN;
7181 case ISD::SETOGT: // (X > Y) ? X : Y -> max
7184 if (!UnsafeFPMath) break;
7186 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
7188 Opcode = X86ISD::FMAX;
7191 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
7194 case ISD::SETOGT: // (X > Y) ? Y : X -> min
7197 if (!UnsafeFPMath) break;
7199 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
7201 Opcode = X86ISD::FMIN;
7204 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
7207 if (!UnsafeFPMath) break;
7209 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
7211 Opcode = X86ISD::FMAX;
7217 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
7225 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
7226 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
7227 const X86Subtarget *Subtarget) {
7228 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
7229 // the FP state in cases where an emms may be missing.
7230 // A preferable solution to the general problem is to figure out the right
7231 // places to insert EMMS. This qualifies as a quick hack.
7232 StoreSDNode *St = cast<StoreSDNode>(N);
7233 if (St->getValue().getValueType().isVector() &&
7234 St->getValue().getValueType().getSizeInBits() == 64 &&
7235 isa<LoadSDNode>(St->getValue()) &&
7236 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
7237 St->getChain().hasOneUse() && !St->isVolatile()) {
7238 SDNode* LdVal = St->getValue().getNode();
7240 int TokenFactorIndex = -1;
7241 SmallVector<SDValue, 8> Ops;
7242 SDNode* ChainVal = St->getChain().getNode();
7243 // Must be a store of a load. We currently handle two cases: the load
7244 // is a direct child, and it's under an intervening TokenFactor. It is
7245 // possible to dig deeper under nested TokenFactors.
7246 if (ChainVal == LdVal)
7247 Ld = cast<LoadSDNode>(St->getChain());
7248 else if (St->getValue().hasOneUse() &&
7249 ChainVal->getOpcode() == ISD::TokenFactor) {
7250 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
7251 if (ChainVal->getOperand(i).getNode() == LdVal) {
7252 TokenFactorIndex = i;
7253 Ld = cast<LoadSDNode>(St->getValue());
7255 Ops.push_back(ChainVal->getOperand(i));
7259 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
7260 if (Subtarget->is64Bit()) {
7261 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
7262 Ld->getBasePtr(), Ld->getSrcValue(),
7263 Ld->getSrcValueOffset(), Ld->isVolatile(),
7264 Ld->getAlignment());
7265 SDValue NewChain = NewLd.getValue(1);
7266 if (TokenFactorIndex != -1) {
7267 Ops.push_back(NewChain);
7268 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7271 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
7272 St->getSrcValue(), St->getSrcValueOffset(),
7273 St->isVolatile(), St->getAlignment());
7276 // Otherwise, lower to two 32-bit copies.
7277 SDValue LoAddr = Ld->getBasePtr();
7278 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7279 DAG.getConstant(4, MVT::i32));
7281 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
7282 Ld->getSrcValue(), Ld->getSrcValueOffset(),
7283 Ld->isVolatile(), Ld->getAlignment());
7284 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
7285 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
7287 MinAlign(Ld->getAlignment(), 4));
7289 SDValue NewChain = LoLd.getValue(1);
7290 if (TokenFactorIndex != -1) {
7291 Ops.push_back(LoLd);
7292 Ops.push_back(HiLd);
7293 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7297 LoAddr = St->getBasePtr();
7298 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7299 DAG.getConstant(4, MVT::i32));
7301 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
7302 St->getSrcValue(), St->getSrcValueOffset(),
7303 St->isVolatile(), St->getAlignment());
7304 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
7306 St->getSrcValueOffset() + 4,
7308 MinAlign(St->getAlignment(), 4));
7309 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
7315 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
7316 /// X86ISD::FXOR nodes.
7317 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
7318 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
7319 // F[X]OR(0.0, x) -> x
7320 // F[X]OR(x, 0.0) -> x
7321 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7322 if (C->getValueAPF().isPosZero())
7323 return N->getOperand(1);
7324 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7325 if (C->getValueAPF().isPosZero())
7326 return N->getOperand(0);
7330 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
7331 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
7332 // FAND(0.0, x) -> 0.0
7333 // FAND(x, 0.0) -> 0.0
7334 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7335 if (C->getValueAPF().isPosZero())
7336 return N->getOperand(0);
7337 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7338 if (C->getValueAPF().isPosZero())
7339 return N->getOperand(1);
7344 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
7345 DAGCombinerInfo &DCI) const {
7346 SelectionDAG &DAG = DCI.DAG;
7347 switch (N->getOpcode()) {
7349 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
7350 case ISD::BUILD_VECTOR:
7351 return PerformBuildVectorCombine(N, DAG, Subtarget, *this);
7352 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
7353 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
7355 case X86ISD::FOR: return PerformFORCombine(N, DAG);
7356 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
7362 //===----------------------------------------------------------------------===//
7363 // X86 Inline Assembly Support
7364 //===----------------------------------------------------------------------===//
7366 /// getConstraintType - Given a constraint letter, return the type of
7367 /// constraint it is for this target.
7368 X86TargetLowering::ConstraintType
7369 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
7370 if (Constraint.size() == 1) {
7371 switch (Constraint[0]) {
7382 return C_RegisterClass;
7387 return TargetLowering::getConstraintType(Constraint);
7390 /// LowerXConstraint - try to replace an X constraint, which matches anything,
7391 /// with another that has more specific requirements based on the type of the
7392 /// corresponding operand.
7393 const char *X86TargetLowering::
7394 LowerXConstraint(MVT ConstraintVT) const {
7395 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
7396 // 'f' like normal targets.
7397 if (ConstraintVT.isFloatingPoint()) {
7398 if (Subtarget->hasSSE2())
7400 if (Subtarget->hasSSE1())
7404 return TargetLowering::LowerXConstraint(ConstraintVT);
7407 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7408 /// vector. If it is invalid, don't add anything to Ops.
7409 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7412 std::vector<SDValue>&Ops,
7413 SelectionDAG &DAG) const {
7414 SDValue Result(0, 0);
7416 switch (Constraint) {
7419 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7420 if (C->getZExtValue() <= 31) {
7421 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7427 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7428 if (C->getZExtValue() <= 63) {
7429 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7435 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
7436 if (C->getZExtValue() <= 255) {
7437 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
7443 // Literal immediates are always ok.
7444 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
7445 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
7449 // If we are in non-pic codegen mode, we allow the address of a global (with
7450 // an optional displacement) to be used with 'i'.
7451 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
7454 // Match either (GA) or (GA+C)
7456 Offset = GA->getOffset();
7457 } else if (Op.getOpcode() == ISD::ADD) {
7458 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7459 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7461 Offset = GA->getOffset()+C->getZExtValue();
7463 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
7464 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
7466 Offset = GA->getOffset()+C->getZExtValue();
7474 Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG);
7476 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
7482 // Otherwise, not valid for this mode.
7487 if (Result.getNode()) {
7488 Ops.push_back(Result);
7491 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
7495 std::vector<unsigned> X86TargetLowering::
7496 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7498 if (Constraint.size() == 1) {
7499 // FIXME: not handling fp-stack yet!
7500 switch (Constraint[0]) { // GCC X86 Constraint Letters
7501 default: break; // Unknown constraint letter
7502 case 'A': // EAX/EDX
7503 if (VT == MVT::i32 || VT == MVT::i64)
7504 return make_vector<unsigned>(X86::EAX, X86::EDX, 0);
7506 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
7509 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
7510 else if (VT == MVT::i16)
7511 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
7512 else if (VT == MVT::i8)
7513 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
7514 else if (VT == MVT::i64)
7515 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
7520 return std::vector<unsigned>();
7523 std::pair<unsigned, const TargetRegisterClass*>
7524 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7526 // First, see if this is a constraint that directly corresponds to an LLVM
7528 if (Constraint.size() == 1) {
7529 // GCC Constraint Letters
7530 switch (Constraint[0]) {
7532 case 'r': // GENERAL_REGS
7533 case 'R': // LEGACY_REGS
7534 case 'l': // INDEX_REGS
7536 return std::make_pair(0U, X86::GR8RegisterClass);
7538 return std::make_pair(0U, X86::GR16RegisterClass);
7539 if (VT == MVT::i32 || !Subtarget->is64Bit())
7540 return std::make_pair(0U, X86::GR32RegisterClass);
7541 return std::make_pair(0U, X86::GR64RegisterClass);
7542 case 'f': // FP Stack registers.
7543 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
7544 // value to the correct fpstack register class.
7545 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
7546 return std::make_pair(0U, X86::RFP32RegisterClass);
7547 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
7548 return std::make_pair(0U, X86::RFP64RegisterClass);
7549 return std::make_pair(0U, X86::RFP80RegisterClass);
7550 case 'y': // MMX_REGS if MMX allowed.
7551 if (!Subtarget->hasMMX()) break;
7552 return std::make_pair(0U, X86::VR64RegisterClass);
7553 case 'Y': // SSE_REGS if SSE2 allowed
7554 if (!Subtarget->hasSSE2()) break;
7556 case 'x': // SSE_REGS if SSE1 allowed
7557 if (!Subtarget->hasSSE1()) break;
7559 switch (VT.getSimpleVT()) {
7561 // Scalar SSE types.
7564 return std::make_pair(0U, X86::FR32RegisterClass);
7567 return std::make_pair(0U, X86::FR64RegisterClass);
7575 return std::make_pair(0U, X86::VR128RegisterClass);
7581 // Use the default implementation in TargetLowering to convert the register
7582 // constraint into a member of a register class.
7583 std::pair<unsigned, const TargetRegisterClass*> Res;
7584 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7586 // Not found as a standard register?
7587 if (Res.second == 0) {
7588 // GCC calls "st(0)" just plain "st".
7589 if (StringsEqualNoCase("{st}", Constraint)) {
7590 Res.first = X86::ST0;
7591 Res.second = X86::RFP80RegisterClass;
7597 // Otherwise, check to see if this is a register class of the wrong value
7598 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
7599 // turn into {ax},{dx}.
7600 if (Res.second->hasType(VT))
7601 return Res; // Correct type already, nothing to do.
7603 // All of the single-register GCC register classes map their values onto
7604 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
7605 // really want an 8-bit or 32-bit register, map to the appropriate register
7606 // class and return the appropriate register.
7607 if (Res.second == X86::GR16RegisterClass) {
7608 if (VT == MVT::i8) {
7609 unsigned DestReg = 0;
7610 switch (Res.first) {
7612 case X86::AX: DestReg = X86::AL; break;
7613 case X86::DX: DestReg = X86::DL; break;
7614 case X86::CX: DestReg = X86::CL; break;
7615 case X86::BX: DestReg = X86::BL; break;
7618 Res.first = DestReg;
7619 Res.second = Res.second = X86::GR8RegisterClass;
7621 } else if (VT == MVT::i32) {
7622 unsigned DestReg = 0;
7623 switch (Res.first) {
7625 case X86::AX: DestReg = X86::EAX; break;
7626 case X86::DX: DestReg = X86::EDX; break;
7627 case X86::CX: DestReg = X86::ECX; break;
7628 case X86::BX: DestReg = X86::EBX; break;
7629 case X86::SI: DestReg = X86::ESI; break;
7630 case X86::DI: DestReg = X86::EDI; break;
7631 case X86::BP: DestReg = X86::EBP; break;
7632 case X86::SP: DestReg = X86::ESP; break;
7635 Res.first = DestReg;
7636 Res.second = Res.second = X86::GR32RegisterClass;
7638 } else if (VT == MVT::i64) {
7639 unsigned DestReg = 0;
7640 switch (Res.first) {
7642 case X86::AX: DestReg = X86::RAX; break;
7643 case X86::DX: DestReg = X86::RDX; break;
7644 case X86::CX: DestReg = X86::RCX; break;
7645 case X86::BX: DestReg = X86::RBX; break;
7646 case X86::SI: DestReg = X86::RSI; break;
7647 case X86::DI: DestReg = X86::RDI; break;
7648 case X86::BP: DestReg = X86::RBP; break;
7649 case X86::SP: DestReg = X86::RSP; break;
7652 Res.first = DestReg;
7653 Res.second = Res.second = X86::GR64RegisterClass;
7656 } else if (Res.second == X86::FR32RegisterClass ||
7657 Res.second == X86::FR64RegisterClass ||
7658 Res.second == X86::VR128RegisterClass) {
7659 // Handle references to XMM physical registers that got mapped into the
7660 // wrong class. This can happen with constraints like {xmm0} where the
7661 // target independent register mapper will just pick the first match it can
7662 // find, ignoring the required type.
7664 Res.second = X86::FR32RegisterClass;
7665 else if (VT == MVT::f64)
7666 Res.second = X86::FR64RegisterClass;
7667 else if (X86::VR128RegisterClass->hasType(VT))
7668 Res.second = X86::VR128RegisterClass;