1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86ShuffleDecodeConstantPool.h"
22 #include "X86TargetMachine.h"
23 #include "X86TargetObjectFile.h"
24 #include "llvm/ADT/SmallBitVector.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
29 #include "llvm/Analysis/EHPersonalities.h"
30 #include "llvm/CodeGen/IntrinsicLowering.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineModuleInfo.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/WinEHFuncInfo.h"
38 #include "llvm/IR/CallSite.h"
39 #include "llvm/IR/CallingConv.h"
40 #include "llvm/IR/Constants.h"
41 #include "llvm/IR/DerivedTypes.h"
42 #include "llvm/IR/Function.h"
43 #include "llvm/IR/GlobalAlias.h"
44 #include "llvm/IR/GlobalVariable.h"
45 #include "llvm/IR/Instructions.h"
46 #include "llvm/IR/Intrinsics.h"
47 #include "llvm/MC/MCAsmInfo.h"
48 #include "llvm/MC/MCContext.h"
49 #include "llvm/MC/MCExpr.h"
50 #include "llvm/MC/MCSymbol.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Debug.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Support/MathExtras.h"
55 #include "llvm/Target/TargetOptions.h"
56 #include "X86IntrinsicsInfo.h"
62 #define DEBUG_TYPE "x86-isel"
64 STATISTIC(NumTailCalls, "Number of tail calls");
66 static cl::opt<bool> ExperimentalVectorWideningLegalization(
67 "x86-experimental-vector-widening-legalization", cl::init(false),
68 cl::desc("Enable an experimental vector type legalization through widening "
69 "rather than promotion."),
72 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
73 const X86Subtarget &STI)
74 : TargetLowering(TM), Subtarget(&STI) {
75 X86ScalarSSEf64 = Subtarget->hasSSE2();
76 X86ScalarSSEf32 = Subtarget->hasSSE1();
77 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
79 // Set up the TargetLowering object.
81 // X86 is weird. It always uses i8 for shift amounts and setcc results.
82 setBooleanContents(ZeroOrOneBooleanContent);
83 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
84 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
86 // For 64-bit, since we have so many registers, use the ILP scheduler.
87 // For 32-bit, use the register pressure specific scheduling.
88 // For Atom, always use ILP scheduling.
89 if (Subtarget->isAtom())
90 setSchedulingPreference(Sched::ILP);
91 else if (Subtarget->is64Bit())
92 setSchedulingPreference(Sched::ILP);
94 setSchedulingPreference(Sched::RegPressure);
95 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
96 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
98 // Bypass expensive divides on Atom when compiling with O2.
99 if (TM.getOptLevel() >= CodeGenOpt::Default) {
100 if (Subtarget->hasSlowDivide32())
101 addBypassSlowDiv(32, 8);
102 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
103 addBypassSlowDiv(64, 16);
106 if (Subtarget->isTargetKnownWindowsMSVC()) {
107 // Setup Windows compiler runtime calls.
108 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
109 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
110 setLibcallName(RTLIB::SREM_I64, "_allrem");
111 setLibcallName(RTLIB::UREM_I64, "_aullrem");
112 setLibcallName(RTLIB::MUL_I64, "_allmul");
113 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
120 if (Subtarget->isTargetDarwin()) {
121 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
122 setUseUnderscoreSetJmp(false);
123 setUseUnderscoreLongJmp(false);
124 } else if (Subtarget->isTargetWindowsGNU()) {
125 // MS runtime is weird: it exports _setjmp, but longjmp!
126 setUseUnderscoreSetJmp(true);
127 setUseUnderscoreLongJmp(false);
129 setUseUnderscoreSetJmp(true);
130 setUseUnderscoreLongJmp(true);
133 // Set up the register classes.
134 addRegisterClass(MVT::i8, &X86::GR8RegClass);
135 addRegisterClass(MVT::i16, &X86::GR16RegClass);
136 addRegisterClass(MVT::i32, &X86::GR32RegClass);
137 if (Subtarget->is64Bit())
138 addRegisterClass(MVT::i64, &X86::GR64RegClass);
140 for (MVT VT : MVT::integer_valuetypes())
141 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
143 // We don't accept any truncstore of integer registers.
144 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
146 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
147 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
148 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
149 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
151 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
153 // SETOEQ and SETUNE require checking two conditions.
154 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
156 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
159 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
161 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
163 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
165 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
167 if (Subtarget->is64Bit()) {
168 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
169 // f32/f64 are legal, f80 is custom.
170 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
173 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
174 } else if (!Subtarget->useSoftFloat()) {
175 // We have an algorithm for SSE2->double, and we turn this into a
176 // 64-bit FILD followed by conditional FADD for other targets.
177 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
178 // We have an algorithm for SSE2, and we turn this into a 64-bit
179 // FILD or VCVTUSI2SS/SD for other targets.
180 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
183 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
185 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
186 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
188 if (!Subtarget->useSoftFloat()) {
189 // SSE has no i16 to fp conversion, only i32
190 if (X86ScalarSSEf32) {
191 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
192 // f32 and f64 cases are Legal, f80 case is not
193 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
196 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
200 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
203 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
205 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
206 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
208 if (!Subtarget->useSoftFloat()) {
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 if (X86ScalarSSEf32) {
215 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
216 // f32 and f64 cases are Legal, f80 case is not
217 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
220 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
236 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
237 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
238 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
241 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
243 } else if (!Subtarget->useSoftFloat()) {
244 // Since AVX is a superset of SSE3, only check for SSE here.
245 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
246 // Expand FP_TO_UINT into a select.
247 // FIXME: We would like to use a Custom expander here eventually to do
248 // the optimal thing for SSE vs. the default expansion in the legalizer.
249 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
251 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
252 // With SSE3 we can use fisttpll to convert to a signed i64; without
253 // SSE, we're stuck with a fistpll.
254 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
256 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
259 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
260 if (!X86ScalarSSEf64) {
261 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
262 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
263 if (Subtarget->is64Bit()) {
264 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
265 // Without SSE, i64->f64 goes through memory.
266 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
270 // Scalar integer divide and remainder are lowered to use operations that
271 // produce two results, to match the available instructions. This exposes
272 // the two-result form to trivial CSE, which is able to combine x/y and x%y
273 // into a single instruction.
275 // Scalar integer multiply-high is also lowered to use two-result
276 // operations, to match the available instructions. However, plain multiply
277 // (low) operations are left as Legal, as there are single-result
278 // instructions for this in x86. Using the two-result multiply instructions
279 // when both high and low results are needed must be arranged by dagcombine.
280 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
281 setOperationAction(ISD::MULHS, VT, Expand);
282 setOperationAction(ISD::MULHU, VT, Expand);
283 setOperationAction(ISD::SDIV, VT, Expand);
284 setOperationAction(ISD::UDIV, VT, Expand);
285 setOperationAction(ISD::SREM, VT, Expand);
286 setOperationAction(ISD::UREM, VT, Expand);
288 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
289 setOperationAction(ISD::ADDC, VT, Custom);
290 setOperationAction(ISD::ADDE, VT, Custom);
291 setOperationAction(ISD::SUBC, VT, Custom);
292 setOperationAction(ISD::SUBE, VT, Custom);
295 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
296 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
297 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
299 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
300 setOperationAction(ISD::BR_CC , MVT::f128, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
303 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
304 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::f128, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
310 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
311 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
312 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
313 if (Subtarget->is64Bit())
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
315 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
316 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
317 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
318 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
320 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
321 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
322 // is. We should promote the value to 64-bits to solve this.
323 // This is what the CRT headers do - `fmodf` is an inline header
324 // function casting to f64 and calling `fmod`.
325 setOperationAction(ISD::FREM , MVT::f32 , Promote);
327 setOperationAction(ISD::FREM , MVT::f32 , Expand);
330 setOperationAction(ISD::FREM , MVT::f64 , Expand);
331 setOperationAction(ISD::FREM , MVT::f80 , Expand);
332 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
334 // Promote the i8 variants and force them on up to i32 which has a shorter
336 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
337 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
339 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
340 if (Subtarget->hasBMI()) {
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
342 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
343 if (Subtarget->is64Bit())
344 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
346 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
347 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
348 if (Subtarget->is64Bit())
349 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
352 if (Subtarget->hasLZCNT()) {
353 // When promoting the i8 variants, force them to i32 for a shorter
355 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
356 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
358 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
361 if (Subtarget->is64Bit())
362 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
364 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
367 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
368 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
370 if (Subtarget->is64Bit()) {
371 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
372 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
376 // Special handling for half-precision floating point conversions.
377 // If we don't have F16C support, then lower half float conversions
378 // into library calls.
379 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
380 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
381 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
384 // There's never any support for operations beyond MVT::f32.
385 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
386 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
387 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
388 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
390 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
391 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
392 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
393 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
394 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
395 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
397 if (Subtarget->hasPOPCNT()) {
398 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
400 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
401 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
402 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
403 if (Subtarget->is64Bit())
404 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
407 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
409 if (!Subtarget->hasMOVBE())
410 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
412 // These should be promoted to a larger select which is supported.
413 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
414 // X86 wants to expand cmov itself.
415 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
416 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
417 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
418 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
419 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
420 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
421 setOperationAction(ISD::SELECT , MVT::f128 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
423 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
424 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
425 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
426 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
428 setOperationAction(ISD::SETCC , MVT::f128 , Custom);
429 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
431 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
432 if (Subtarget->is64Bit()) {
433 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
434 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
435 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
437 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
438 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
439 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
440 // support continuation, user-level threading, and etc.. As a result, no
441 // other SjLj exception interfaces are implemented and please don't build
442 // your own exception handling based on them.
443 // LLVM/Clang supports zero-cost DWARF exception handling.
444 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
445 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
448 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
449 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
450 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
451 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
452 if (Subtarget->is64Bit())
453 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
454 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
455 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
456 if (Subtarget->is64Bit()) {
457 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
458 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
459 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
460 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
461 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
463 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
464 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
465 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
466 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
467 if (Subtarget->is64Bit()) {
468 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
469 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
470 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
473 if (Subtarget->hasSSE1())
474 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
476 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
478 // Expand certain atomics
479 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
480 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
481 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
482 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
485 if (Subtarget->hasCmpxchg16b()) {
486 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
489 // FIXME - use subtarget debug flags
490 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
491 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
492 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
495 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
496 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
498 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
499 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
501 setOperationAction(ISD::TRAP, MVT::Other, Legal);
502 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
504 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
505 setOperationAction(ISD::VASTART , MVT::Other, Custom);
506 setOperationAction(ISD::VAEND , MVT::Other, Expand);
507 if (Subtarget->is64Bit()) {
508 setOperationAction(ISD::VAARG , MVT::Other, Custom);
509 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
511 // TargetInfo::CharPtrBuiltinVaList
512 setOperationAction(ISD::VAARG , MVT::Other, Expand);
513 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
516 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
517 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
519 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
521 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
522 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
523 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
525 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
526 // f32 and f64 use SSE.
527 // Set up the FP register classes.
528 addRegisterClass(MVT::f32, &X86::FR32RegClass);
529 addRegisterClass(MVT::f64, &X86::FR64RegClass);
531 // Use ANDPD to simulate FABS.
532 setOperationAction(ISD::FABS , MVT::f64, Custom);
533 setOperationAction(ISD::FABS , MVT::f32, Custom);
535 // Use XORP to simulate FNEG.
536 setOperationAction(ISD::FNEG , MVT::f64, Custom);
537 setOperationAction(ISD::FNEG , MVT::f32, Custom);
539 // Use ANDPD and ORPD to simulate FCOPYSIGN.
540 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
541 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
543 // Lower this to FGETSIGNx86 plus an AND.
544 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
545 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
547 // We don't support sin/cos/fmod
548 setOperationAction(ISD::FSIN , MVT::f64, Expand);
549 setOperationAction(ISD::FCOS , MVT::f64, Expand);
550 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
551 setOperationAction(ISD::FSIN , MVT::f32, Expand);
552 setOperationAction(ISD::FCOS , MVT::f32, Expand);
553 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
555 // Expand FP immediates into loads from the stack, except for the special
557 addLegalFPImmediate(APFloat(+0.0)); // xorpd
558 addLegalFPImmediate(APFloat(+0.0f)); // xorps
559 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
560 // Use SSE for f32, x87 for f64.
561 // Set up the FP register classes.
562 addRegisterClass(MVT::f32, &X86::FR32RegClass);
563 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
565 // Use ANDPS to simulate FABS.
566 setOperationAction(ISD::FABS , MVT::f32, Custom);
568 // Use XORP to simulate FNEG.
569 setOperationAction(ISD::FNEG , MVT::f32, Custom);
571 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
573 // Use ANDPS and ORPS to simulate FCOPYSIGN.
574 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
575 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
577 // We don't support sin/cos/fmod
578 setOperationAction(ISD::FSIN , MVT::f32, Expand);
579 setOperationAction(ISD::FCOS , MVT::f32, Expand);
580 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
582 // Special cases we handle for FP constants.
583 addLegalFPImmediate(APFloat(+0.0f)); // xorps
584 addLegalFPImmediate(APFloat(+0.0)); // FLD0
585 addLegalFPImmediate(APFloat(+1.0)); // FLD1
586 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
587 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
589 if (!TM.Options.UnsafeFPMath) {
590 setOperationAction(ISD::FSIN , MVT::f64, Expand);
591 setOperationAction(ISD::FCOS , MVT::f64, Expand);
592 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
594 } else if (!Subtarget->useSoftFloat()) {
595 // f32 and f64 in x87.
596 // Set up the FP register classes.
597 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
598 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
600 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
601 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
602 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
603 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
605 if (!TM.Options.UnsafeFPMath) {
606 setOperationAction(ISD::FSIN , MVT::f64, Expand);
607 setOperationAction(ISD::FSIN , MVT::f32, Expand);
608 setOperationAction(ISD::FCOS , MVT::f64, Expand);
609 setOperationAction(ISD::FCOS , MVT::f32, Expand);
610 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
611 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
613 addLegalFPImmediate(APFloat(+0.0)); // FLD0
614 addLegalFPImmediate(APFloat(+1.0)); // FLD1
615 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
616 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
617 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
618 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
619 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
620 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
623 // We don't support FMA.
624 setOperationAction(ISD::FMA, MVT::f64, Expand);
625 setOperationAction(ISD::FMA, MVT::f32, Expand);
627 // Long double always uses X87, except f128 in MMX.
628 if (!Subtarget->useSoftFloat()) {
629 if (Subtarget->is64Bit() && Subtarget->hasMMX()) {
630 addRegisterClass(MVT::f128, &X86::FR128RegClass);
631 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
632 setOperationAction(ISD::FABS , MVT::f128, Custom);
633 setOperationAction(ISD::FNEG , MVT::f128, Custom);
634 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Custom);
637 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
638 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
639 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
641 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
642 addLegalFPImmediate(TmpFlt); // FLD0
644 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
647 APFloat TmpFlt2(+1.0);
648 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
650 addLegalFPImmediate(TmpFlt2); // FLD1
651 TmpFlt2.changeSign();
652 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
655 if (!TM.Options.UnsafeFPMath) {
656 setOperationAction(ISD::FSIN , MVT::f80, Expand);
657 setOperationAction(ISD::FCOS , MVT::f80, Expand);
658 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
661 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
662 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
663 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
664 setOperationAction(ISD::FRINT, MVT::f80, Expand);
665 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
666 setOperationAction(ISD::FMA, MVT::f80, Expand);
669 // Always use a library call for pow.
670 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
671 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
672 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
674 setOperationAction(ISD::FLOG, MVT::f80, Expand);
675 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
676 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
677 setOperationAction(ISD::FEXP, MVT::f80, Expand);
678 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
679 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
680 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
682 // First set operation action for all vector types to either promote
683 // (for widening) or expand (for scalarization). Then we will selectively
684 // turn on ones that can be effectively codegen'd.
685 for (MVT VT : MVT::vector_valuetypes()) {
686 setOperationAction(ISD::ADD , VT, Expand);
687 setOperationAction(ISD::SUB , VT, Expand);
688 setOperationAction(ISD::FADD, VT, Expand);
689 setOperationAction(ISD::FNEG, VT, Expand);
690 setOperationAction(ISD::FSUB, VT, Expand);
691 setOperationAction(ISD::MUL , VT, Expand);
692 setOperationAction(ISD::FMUL, VT, Expand);
693 setOperationAction(ISD::SDIV, VT, Expand);
694 setOperationAction(ISD::UDIV, VT, Expand);
695 setOperationAction(ISD::FDIV, VT, Expand);
696 setOperationAction(ISD::SREM, VT, Expand);
697 setOperationAction(ISD::UREM, VT, Expand);
698 setOperationAction(ISD::LOAD, VT, Expand);
699 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
700 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
701 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
702 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
703 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
704 setOperationAction(ISD::FABS, VT, Expand);
705 setOperationAction(ISD::FSIN, VT, Expand);
706 setOperationAction(ISD::FSINCOS, VT, Expand);
707 setOperationAction(ISD::FCOS, VT, Expand);
708 setOperationAction(ISD::FSINCOS, VT, Expand);
709 setOperationAction(ISD::FREM, VT, Expand);
710 setOperationAction(ISD::FMA, VT, Expand);
711 setOperationAction(ISD::FPOWI, VT, Expand);
712 setOperationAction(ISD::FSQRT, VT, Expand);
713 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
714 setOperationAction(ISD::FFLOOR, VT, Expand);
715 setOperationAction(ISD::FCEIL, VT, Expand);
716 setOperationAction(ISD::FTRUNC, VT, Expand);
717 setOperationAction(ISD::FRINT, VT, Expand);
718 setOperationAction(ISD::FNEARBYINT, VT, Expand);
719 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
720 setOperationAction(ISD::MULHS, VT, Expand);
721 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
722 setOperationAction(ISD::MULHU, VT, Expand);
723 setOperationAction(ISD::SDIVREM, VT, Expand);
724 setOperationAction(ISD::UDIVREM, VT, Expand);
725 setOperationAction(ISD::FPOW, VT, Expand);
726 setOperationAction(ISD::CTPOP, VT, Expand);
727 setOperationAction(ISD::CTTZ, VT, Expand);
728 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
729 setOperationAction(ISD::CTLZ, VT, Expand);
730 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
731 setOperationAction(ISD::SHL, VT, Expand);
732 setOperationAction(ISD::SRA, VT, Expand);
733 setOperationAction(ISD::SRL, VT, Expand);
734 setOperationAction(ISD::ROTL, VT, Expand);
735 setOperationAction(ISD::ROTR, VT, Expand);
736 setOperationAction(ISD::BSWAP, VT, Expand);
737 setOperationAction(ISD::SETCC, VT, Expand);
738 setOperationAction(ISD::FLOG, VT, Expand);
739 setOperationAction(ISD::FLOG2, VT, Expand);
740 setOperationAction(ISD::FLOG10, VT, Expand);
741 setOperationAction(ISD::FEXP, VT, Expand);
742 setOperationAction(ISD::FEXP2, VT, Expand);
743 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
744 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
745 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
746 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
747 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
748 setOperationAction(ISD::TRUNCATE, VT, Expand);
749 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
750 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
751 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
752 setOperationAction(ISD::VSELECT, VT, Expand);
753 setOperationAction(ISD::SELECT_CC, VT, Expand);
754 for (MVT InnerVT : MVT::vector_valuetypes()) {
755 setTruncStoreAction(InnerVT, VT, Expand);
757 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
758 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
760 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
761 // types, we have to deal with them whether we ask for Expansion or not.
762 // Setting Expand causes its own optimisation problems though, so leave
764 if (VT.getVectorElementType() == MVT::i1)
765 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
767 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
768 // split/scalarized right now.
769 if (VT.getVectorElementType() == MVT::f16)
770 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
774 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
775 // with -msoft-float, disable use of MMX as well.
776 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
777 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
778 // No operations on x86mmx supported, everything uses intrinsics.
781 // MMX-sized vectors (other than x86mmx) are expected to be expanded
782 // into smaller operations.
783 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
784 setOperationAction(ISD::MULHS, MMXTy, Expand);
785 setOperationAction(ISD::AND, MMXTy, Expand);
786 setOperationAction(ISD::OR, MMXTy, Expand);
787 setOperationAction(ISD::XOR, MMXTy, Expand);
788 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
789 setOperationAction(ISD::SELECT, MMXTy, Expand);
790 setOperationAction(ISD::BITCAST, MMXTy, Expand);
792 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
795 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
797 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
798 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
799 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
800 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
801 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
802 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
803 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
804 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
805 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
806 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
807 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
808 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
809 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
810 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
813 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
814 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
816 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
817 // registers cannot be used even for integer operations.
818 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
819 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
820 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
821 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
823 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
824 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
825 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
826 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
827 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
828 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
829 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
830 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
831 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
832 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
833 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
834 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
835 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
836 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
837 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
838 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
839 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
840 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
841 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
842 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
843 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
844 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
845 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
847 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
848 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
849 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
850 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
852 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
853 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
854 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
855 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
857 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
858 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
859 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
861 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
863 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
864 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
865 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
866 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
868 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
869 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
870 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
871 // ISD::CTTZ v2i64 - scalarization is faster.
872 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
873 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
874 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
875 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
877 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
878 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
879 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
880 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
881 setOperationAction(ISD::VSELECT, VT, Custom);
882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
885 // We support custom legalizing of sext and anyext loads for specific
886 // memory vector types which we can load as a scalar (or sequence of
887 // scalars) and extend in-register to a legal 128-bit vector type. For sext
888 // loads these must work with a single scalar load.
889 for (MVT VT : MVT::integer_vector_valuetypes()) {
890 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
891 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
892 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
893 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
894 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
895 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
896 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
897 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
898 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
901 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
902 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
903 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
904 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
905 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
906 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
907 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
908 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
910 if (Subtarget->is64Bit()) {
911 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
912 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
915 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
916 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
917 setOperationAction(ISD::AND, VT, Promote);
918 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
919 setOperationAction(ISD::OR, VT, Promote);
920 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
921 setOperationAction(ISD::XOR, VT, Promote);
922 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
923 setOperationAction(ISD::LOAD, VT, Promote);
924 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
925 setOperationAction(ISD::SELECT, VT, Promote);
926 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
929 // Custom lower v2i64 and v2f64 selects.
930 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
931 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
932 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
933 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
935 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
936 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
938 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
941 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
942 // As there is no 64-bit GPR available, we need build a special custom
943 // sequence to convert from v2i32 to v2f32.
944 if (!Subtarget->is64Bit())
945 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
948 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
950 for (MVT VT : MVT::fp_vector_valuetypes())
951 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
953 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
955 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
958 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
959 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
960 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
961 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
962 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
963 setOperationAction(ISD::FRINT, RoundedTy, Legal);
964 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
967 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
968 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
969 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
970 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
971 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
972 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
973 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
974 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
976 // FIXME: Do we need to handle scalar-to-vector here?
977 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
979 // We directly match byte blends in the backend as they match the VSELECT
981 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
983 // SSE41 brings specific instructions for doing vector sign extend even in
984 // cases where we don't have SRA.
985 for (MVT VT : MVT::integer_vector_valuetypes()) {
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
988 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
991 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
997 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1004 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1006 // i8 and i16 vectors are custom because the source register and source
1007 // source memory operand types are not the same width. f32 vectors are
1008 // custom since the immediate controlling the insert encodes additional
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1013 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1018 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1020 // FIXME: these should be Legal, but that's only for the case where
1021 // the index is constant. For now custom expand to deal with that.
1022 if (Subtarget->is64Bit()) {
1023 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1024 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1028 if (Subtarget->hasSSE2()) {
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1031 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1034 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1036 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1037 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1039 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1040 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1042 // In the customized shift lowering, the legal cases in AVX2 will be
1044 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1045 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1047 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1048 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1050 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1051 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1054 if (Subtarget->hasXOP()) {
1055 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1056 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1057 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1058 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1059 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1060 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1061 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1062 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1065 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1066 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1067 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1068 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1069 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1070 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1071 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1073 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1074 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1075 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1077 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1088 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1090 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1091 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1092 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1093 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1094 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1095 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1096 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1097 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1098 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1099 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1100 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1101 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1103 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1104 // even though v8i16 is a legal type.
1105 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1106 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1107 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1109 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1110 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1111 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1113 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1114 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1116 for (MVT VT : MVT::fp_vector_valuetypes())
1117 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1119 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1120 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1122 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1123 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1125 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1126 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1128 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1129 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1130 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1131 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1133 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1134 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1135 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1137 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1138 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1139 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1140 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1141 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1142 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1143 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1144 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1145 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1146 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1147 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1148 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1150 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1151 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1152 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1153 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1155 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1156 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1157 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1158 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1160 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1161 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1162 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1164 if (Subtarget->hasAnyFMA()) {
1165 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1166 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1167 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1168 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1169 setOperationAction(ISD::FMA, MVT::f32, Legal);
1170 setOperationAction(ISD::FMA, MVT::f64, Legal);
1173 if (Subtarget->hasInt256()) {
1174 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1175 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1176 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1177 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1179 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1180 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1181 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1184 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1185 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1186 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1187 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1189 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1190 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1191 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1192 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1194 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1195 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1196 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1197 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1198 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1199 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1200 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1201 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1202 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1203 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1204 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1205 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1207 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1208 // when we have a 256bit-wide blend with immediate.
1209 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1211 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1212 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1213 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1214 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1215 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1216 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1217 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1220 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1223 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1226 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1227 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1228 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1229 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1231 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1232 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1233 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1234 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1236 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1237 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1238 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1239 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1241 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1242 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1243 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1244 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1245 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1246 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1248 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1249 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1250 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1251 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1252 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1255 // In the customized shift lowering, the legal cases in AVX2 will be
1257 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1258 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1260 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1261 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1263 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1264 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1266 // Custom lower several nodes for 256-bit types.
1267 for (MVT VT : MVT::vector_valuetypes()) {
1268 if (VT.getScalarSizeInBits() >= 32) {
1269 setOperationAction(ISD::MLOAD, VT, Legal);
1270 setOperationAction(ISD::MSTORE, VT, Legal);
1272 // Extract subvector is special because the value type
1273 // (result) is 128-bit but the source is 256-bit wide.
1274 if (VT.is128BitVector()) {
1275 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1277 // Do not attempt to custom lower other non-256-bit vectors
1278 if (!VT.is256BitVector())
1281 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1282 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1283 setOperationAction(ISD::VSELECT, VT, Custom);
1284 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1285 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1286 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1287 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1288 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1291 if (Subtarget->hasInt256())
1292 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1294 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1295 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1296 setOperationAction(ISD::AND, VT, Promote);
1297 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1298 setOperationAction(ISD::OR, VT, Promote);
1299 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1300 setOperationAction(ISD::XOR, VT, Promote);
1301 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1302 setOperationAction(ISD::LOAD, VT, Promote);
1303 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1304 setOperationAction(ISD::SELECT, VT, Promote);
1305 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1309 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1310 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1311 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1312 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1313 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1315 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1316 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1317 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1319 for (MVT VT : MVT::fp_vector_valuetypes())
1320 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1328 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1329 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1330 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1331 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1332 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1333 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1335 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1336 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1337 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1338 setOperationAction(ISD::XOR, MVT::i1, Legal);
1339 setOperationAction(ISD::OR, MVT::i1, Legal);
1340 setOperationAction(ISD::AND, MVT::i1, Legal);
1341 setOperationAction(ISD::SUB, MVT::i1, Custom);
1342 setOperationAction(ISD::ADD, MVT::i1, Custom);
1343 setOperationAction(ISD::MUL, MVT::i1, Custom);
1344 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1345 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1346 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1347 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1348 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1350 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1351 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1355 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1356 setOperationAction(ISD::FABS, MVT::v16f32, Custom);
1358 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1359 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1360 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1361 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1362 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1363 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1364 setOperationAction(ISD::FABS, MVT::v8f64, Custom);
1365 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1366 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1368 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1369 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1370 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1371 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1372 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1373 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1374 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1375 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1376 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1377 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1378 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1379 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1380 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1381 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1382 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1383 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1385 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1386 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1387 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1388 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1389 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1390 if (Subtarget->hasVLX()){
1391 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1392 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1393 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1394 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1395 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1397 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1398 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1399 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1400 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1401 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1403 setOperationAction(ISD::MLOAD, MVT::v8i32, Custom);
1404 setOperationAction(ISD::MLOAD, MVT::v8f32, Custom);
1405 setOperationAction(ISD::MSTORE, MVT::v8i32, Custom);
1406 setOperationAction(ISD::MSTORE, MVT::v8f32, Custom);
1408 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1409 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1410 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1411 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1412 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1413 if (Subtarget->hasDQI()) {
1414 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1415 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1419 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1420 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1421 if (Subtarget->hasVLX()) {
1422 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1423 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1424 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1427 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1428 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1432 if (Subtarget->hasVLX()) {
1433 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1434 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1435 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1436 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1437 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1438 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1439 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1440 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1442 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1443 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1444 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1445 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1446 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1447 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1448 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1450 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1451 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1452 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1453 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1454 if (Subtarget->hasDQI()) {
1455 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1456 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1458 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1459 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1460 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1461 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1462 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1463 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1464 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1465 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1466 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1467 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1470 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1471 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1472 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1473 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1475 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1476 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1478 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1480 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1481 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1482 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v16i1, Custom);
1483 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1484 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1485 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1486 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1487 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1488 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1489 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1490 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1491 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1493 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1494 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1495 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1496 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1497 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1498 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1499 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1500 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1502 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1503 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1505 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1506 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1508 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1510 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1511 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1513 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1514 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1516 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1517 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1519 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1520 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1521 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1522 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1523 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1524 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1526 if (Subtarget->hasCDI()) {
1527 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1528 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Expand);
1530 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Expand);
1532 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1533 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1534 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1535 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Expand);
1537 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Expand);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Expand);
1539 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Expand);
1541 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1542 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1544 if (Subtarget->hasVLX()) {
1545 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1546 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1547 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1548 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1549 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Expand);
1550 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Expand);
1551 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Expand);
1552 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Expand);
1554 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1555 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1556 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1557 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1559 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1560 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1561 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1562 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1563 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Expand);
1564 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Expand);
1565 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Expand);
1566 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Expand);
1568 } // Subtarget->hasCDI()
1570 if (Subtarget->hasDQI()) {
1571 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1572 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1573 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1575 // Custom lower several nodes.
1576 for (MVT VT : MVT::vector_valuetypes()) {
1577 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1579 setOperationAction(ISD::AND, VT, Legal);
1580 setOperationAction(ISD::OR, VT, Legal);
1581 setOperationAction(ISD::XOR, VT, Legal);
1583 if ((VT.is128BitVector() || VT.is256BitVector()) && EltSize >= 32) {
1584 setOperationAction(ISD::MGATHER, VT, Custom);
1585 setOperationAction(ISD::MSCATTER, VT, Custom);
1587 // Extract subvector is special because the value type
1588 // (result) is 256/128-bit but the source is 512-bit wide.
1589 if (VT.is128BitVector() || VT.is256BitVector()) {
1590 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1592 if (VT.getVectorElementType() == MVT::i1)
1593 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1595 // Do not attempt to custom lower other non-512-bit vectors
1596 if (!VT.is512BitVector())
1599 if (EltSize >= 32) {
1600 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1601 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1602 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1603 setOperationAction(ISD::VSELECT, VT, Legal);
1604 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1605 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1606 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1607 setOperationAction(ISD::MLOAD, VT, Legal);
1608 setOperationAction(ISD::MSTORE, VT, Legal);
1609 setOperationAction(ISD::MGATHER, VT, Legal);
1610 setOperationAction(ISD::MSCATTER, VT, Custom);
1613 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1614 setOperationAction(ISD::SELECT, VT, Promote);
1615 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1619 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1620 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1621 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1623 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1624 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1626 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1627 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1628 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1629 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1630 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1631 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1632 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1633 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1634 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1635 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1636 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1637 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1638 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1639 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1640 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1641 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1642 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1643 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1644 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1645 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1646 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1647 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1648 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1649 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1650 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1651 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1652 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1653 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1654 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1655 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1656 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1657 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1658 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1659 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1660 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1661 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1662 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1663 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1664 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1665 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1666 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1667 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1669 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1670 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1671 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1672 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1673 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1674 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1675 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1676 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1678 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1679 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1680 if (Subtarget->hasVLX())
1681 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1683 if (Subtarget->hasCDI()) {
1684 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1685 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1686 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Expand);
1687 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Expand);
1690 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1691 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1692 setOperationAction(ISD::VSELECT, VT, Legal);
1693 setOperationAction(ISD::SRL, VT, Custom);
1694 setOperationAction(ISD::SHL, VT, Custom);
1695 setOperationAction(ISD::SRA, VT, Custom);
1697 setOperationAction(ISD::AND, VT, Promote);
1698 AddPromotedToType (ISD::AND, VT, MVT::v8i64);
1699 setOperationAction(ISD::OR, VT, Promote);
1700 AddPromotedToType (ISD::OR, VT, MVT::v8i64);
1701 setOperationAction(ISD::XOR, VT, Promote);
1702 AddPromotedToType (ISD::XOR, VT, MVT::v8i64);
1706 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1707 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1708 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1710 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1711 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1712 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1713 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1714 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1715 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1716 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1717 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1718 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1719 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1720 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1721 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1723 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1724 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1725 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1726 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1727 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1728 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1729 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1730 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1732 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1733 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1734 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1735 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1736 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1737 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1738 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1739 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1742 // We want to custom lower some of our intrinsics.
1743 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1744 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1745 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1746 if (!Subtarget->is64Bit()) {
1747 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1748 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
1751 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1752 // handle type legalization for these operations here.
1754 // FIXME: We really should do custom legalization for addition and
1755 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1756 // than generic legalization for 64-bit multiplication-with-overflow, though.
1757 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1758 if (VT == MVT::i64 && !Subtarget->is64Bit())
1760 // Add/Sub/Mul with overflow operations are custom lowered.
1761 setOperationAction(ISD::SADDO, VT, Custom);
1762 setOperationAction(ISD::UADDO, VT, Custom);
1763 setOperationAction(ISD::SSUBO, VT, Custom);
1764 setOperationAction(ISD::USUBO, VT, Custom);
1765 setOperationAction(ISD::SMULO, VT, Custom);
1766 setOperationAction(ISD::UMULO, VT, Custom);
1769 if (!Subtarget->is64Bit()) {
1770 // These libcalls are not available in 32-bit.
1771 setLibcallName(RTLIB::SHL_I128, nullptr);
1772 setLibcallName(RTLIB::SRL_I128, nullptr);
1773 setLibcallName(RTLIB::SRA_I128, nullptr);
1776 // Combine sin / cos into one node or libcall if possible.
1777 if (Subtarget->hasSinCos()) {
1778 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1779 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1780 if (Subtarget->isTargetDarwin()) {
1781 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1782 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1783 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1784 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1788 if (Subtarget->isTargetWin64()) {
1789 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1790 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1791 setOperationAction(ISD::SREM, MVT::i128, Custom);
1792 setOperationAction(ISD::UREM, MVT::i128, Custom);
1793 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1794 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1797 // We have target-specific dag combine patterns for the following nodes:
1798 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1799 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1800 setTargetDAGCombine(ISD::BITCAST);
1801 setTargetDAGCombine(ISD::VSELECT);
1802 setTargetDAGCombine(ISD::SELECT);
1803 setTargetDAGCombine(ISD::SHL);
1804 setTargetDAGCombine(ISD::SRA);
1805 setTargetDAGCombine(ISD::SRL);
1806 setTargetDAGCombine(ISD::OR);
1807 setTargetDAGCombine(ISD::AND);
1808 setTargetDAGCombine(ISD::ADD);
1809 setTargetDAGCombine(ISD::FADD);
1810 setTargetDAGCombine(ISD::FSUB);
1811 setTargetDAGCombine(ISD::FNEG);
1812 setTargetDAGCombine(ISD::FMA);
1813 setTargetDAGCombine(ISD::FMINNUM);
1814 setTargetDAGCombine(ISD::FMAXNUM);
1815 setTargetDAGCombine(ISD::SUB);
1816 setTargetDAGCombine(ISD::LOAD);
1817 setTargetDAGCombine(ISD::MLOAD);
1818 setTargetDAGCombine(ISD::STORE);
1819 setTargetDAGCombine(ISD::MSTORE);
1820 setTargetDAGCombine(ISD::TRUNCATE);
1821 setTargetDAGCombine(ISD::ZERO_EXTEND);
1822 setTargetDAGCombine(ISD::ANY_EXTEND);
1823 setTargetDAGCombine(ISD::SIGN_EXTEND);
1824 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1825 setTargetDAGCombine(ISD::SINT_TO_FP);
1826 setTargetDAGCombine(ISD::UINT_TO_FP);
1827 setTargetDAGCombine(ISD::SETCC);
1828 setTargetDAGCombine(ISD::BUILD_VECTOR);
1829 setTargetDAGCombine(ISD::MUL);
1830 setTargetDAGCombine(ISD::XOR);
1831 setTargetDAGCombine(ISD::MSCATTER);
1832 setTargetDAGCombine(ISD::MGATHER);
1834 computeRegisterProperties(Subtarget->getRegisterInfo());
1836 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1837 MaxStoresPerMemsetOptSize = 8;
1838 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1839 MaxStoresPerMemcpyOptSize = 4;
1840 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1841 MaxStoresPerMemmoveOptSize = 4;
1842 setPrefLoopAlignment(4); // 2^4 bytes.
1844 // A predictable cmov does not hurt on an in-order CPU.
1845 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1846 PredictableSelectIsExpensive = !Subtarget->isAtom();
1847 EnableExtLdPromotion = true;
1848 setPrefFunctionAlignment(4); // 2^4 bytes.
1850 verifyIntrinsicTables();
1853 // This has so far only been implemented for 64-bit MachO.
1854 bool X86TargetLowering::useLoadStackGuardNode() const {
1855 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1858 TargetLoweringBase::LegalizeTypeAction
1859 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1860 if (ExperimentalVectorWideningLegalization &&
1861 VT.getVectorNumElements() != 1 &&
1862 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1863 return TypeWidenVector;
1865 return TargetLoweringBase::getPreferredVectorAction(VT);
1868 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1871 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1873 if (VT.isSimple()) {
1874 MVT VVT = VT.getSimpleVT();
1875 const unsigned NumElts = VVT.getVectorNumElements();
1876 const MVT EltVT = VVT.getVectorElementType();
1877 if (VVT.is512BitVector()) {
1878 if (Subtarget->hasAVX512())
1879 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1880 EltVT == MVT::f32 || EltVT == MVT::f64)
1882 case 8: return MVT::v8i1;
1883 case 16: return MVT::v16i1;
1885 if (Subtarget->hasBWI())
1886 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1888 case 32: return MVT::v32i1;
1889 case 64: return MVT::v64i1;
1893 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1894 if (Subtarget->hasVLX())
1895 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1896 EltVT == MVT::f32 || EltVT == MVT::f64)
1898 case 2: return MVT::v2i1;
1899 case 4: return MVT::v4i1;
1900 case 8: return MVT::v8i1;
1902 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1903 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1905 case 8: return MVT::v8i1;
1906 case 16: return MVT::v16i1;
1907 case 32: return MVT::v32i1;
1912 return VT.changeVectorElementTypeToInteger();
1915 /// Helper for getByValTypeAlignment to determine
1916 /// the desired ByVal argument alignment.
1917 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1920 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1921 if (VTy->getBitWidth() == 128)
1923 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1924 unsigned EltAlign = 0;
1925 getMaxByValAlign(ATy->getElementType(), EltAlign);
1926 if (EltAlign > MaxAlign)
1927 MaxAlign = EltAlign;
1928 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1929 for (auto *EltTy : STy->elements()) {
1930 unsigned EltAlign = 0;
1931 getMaxByValAlign(EltTy, EltAlign);
1932 if (EltAlign > MaxAlign)
1933 MaxAlign = EltAlign;
1940 /// Return the desired alignment for ByVal aggregate
1941 /// function arguments in the caller parameter area. For X86, aggregates
1942 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1943 /// are at 4-byte boundaries.
1944 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1945 const DataLayout &DL) const {
1946 if (Subtarget->is64Bit()) {
1947 // Max of 8 and alignment of type.
1948 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1955 if (Subtarget->hasSSE1())
1956 getMaxByValAlign(Ty, Align);
1960 /// Returns the target specific optimal type for load
1961 /// and store operations as a result of memset, memcpy, and memmove
1962 /// lowering. If DstAlign is zero that means it's safe to destination
1963 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1964 /// means there isn't a need to check it against alignment requirement,
1965 /// probably because the source does not need to be loaded. If 'IsMemset' is
1966 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1967 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1968 /// source is constant so it does not need to be loaded.
1969 /// It returns EVT::Other if the type should be determined using generic
1970 /// target-independent logic.
1972 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1973 unsigned DstAlign, unsigned SrcAlign,
1974 bool IsMemset, bool ZeroMemset,
1976 MachineFunction &MF) const {
1977 const Function *F = MF.getFunction();
1978 if ((!IsMemset || ZeroMemset) &&
1979 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1981 (!Subtarget->isUnalignedMem16Slow() ||
1982 ((DstAlign == 0 || DstAlign >= 16) &&
1983 (SrcAlign == 0 || SrcAlign >= 16)))) {
1985 // FIXME: Check if unaligned 32-byte accesses are slow.
1986 if (Subtarget->hasInt256())
1988 if (Subtarget->hasFp256())
1991 if (Subtarget->hasSSE2())
1993 if (Subtarget->hasSSE1())
1995 } else if (!MemcpyStrSrc && Size >= 8 &&
1996 !Subtarget->is64Bit() &&
1997 Subtarget->hasSSE2()) {
1998 // Do not use f64 to lower memcpy if source is string constant. It's
1999 // better to use i32 to avoid the loads.
2003 // This is a compromise. If we reach here, unaligned accesses may be slow on
2004 // this target. However, creating smaller, aligned accesses could be even
2005 // slower and would certainly be a lot more code.
2006 if (Subtarget->is64Bit() && Size >= 8)
2011 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
2013 return X86ScalarSSEf32;
2014 else if (VT == MVT::f64)
2015 return X86ScalarSSEf64;
2020 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
2025 switch (VT.getSizeInBits()) {
2027 // 8-byte and under are always assumed to be fast.
2031 *Fast = !Subtarget->isUnalignedMem16Slow();
2034 *Fast = !Subtarget->isUnalignedMem32Slow();
2036 // TODO: What about AVX-512 (512-bit) accesses?
2039 // Misaligned accesses of any size are always allowed.
2043 /// Return the entry encoding for a jump table in the
2044 /// current function. The returned value is a member of the
2045 /// MachineJumpTableInfo::JTEntryKind enum.
2046 unsigned X86TargetLowering::getJumpTableEncoding() const {
2047 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2049 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2050 Subtarget->isPICStyleGOT())
2051 return MachineJumpTableInfo::EK_Custom32;
2053 // Otherwise, use the normal jump table encoding heuristics.
2054 return TargetLowering::getJumpTableEncoding();
2057 bool X86TargetLowering::useSoftFloat() const {
2058 return Subtarget->useSoftFloat();
2062 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2063 const MachineBasicBlock *MBB,
2064 unsigned uid,MCContext &Ctx) const{
2065 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2066 Subtarget->isPICStyleGOT());
2067 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2069 return MCSymbolRefExpr::create(MBB->getSymbol(),
2070 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2073 /// Returns relocation base for the given PIC jumptable.
2074 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2075 SelectionDAG &DAG) const {
2076 if (!Subtarget->is64Bit())
2077 // This doesn't have SDLoc associated with it, but is not really the
2078 // same as a Register.
2079 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2080 getPointerTy(DAG.getDataLayout()));
2084 /// This returns the relocation base for the given PIC jumptable,
2085 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2086 const MCExpr *X86TargetLowering::
2087 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2088 MCContext &Ctx) const {
2089 // X86-64 uses RIP relative addressing based on the jump table label.
2090 if (Subtarget->isPICStyleRIPRel())
2091 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2093 // Otherwise, the reference is relative to the PIC base.
2094 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2097 std::pair<const TargetRegisterClass *, uint8_t>
2098 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2100 const TargetRegisterClass *RRC = nullptr;
2102 switch (VT.SimpleTy) {
2104 return TargetLowering::findRepresentativeClass(TRI, VT);
2105 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2106 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2109 RRC = &X86::VR64RegClass;
2111 case MVT::f32: case MVT::f64:
2112 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2113 case MVT::v4f32: case MVT::v2f64:
2114 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2116 RRC = &X86::VR128RegClass;
2119 return std::make_pair(RRC, Cost);
2122 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2123 unsigned &Offset) const {
2124 if (!Subtarget->isTargetLinux())
2127 if (Subtarget->is64Bit()) {
2128 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2130 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2142 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2143 if (!Subtarget->isTargetAndroid())
2144 return TargetLowering::getSafeStackPointerLocation(IRB);
2146 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2147 // definition of TLS_SLOT_SAFESTACK in
2148 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2149 unsigned AddressSpace, Offset;
2150 if (Subtarget->is64Bit()) {
2151 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2153 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2163 return ConstantExpr::getIntToPtr(
2164 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2165 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2168 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2169 unsigned DestAS) const {
2170 assert(SrcAS != DestAS && "Expected different address spaces!");
2172 return SrcAS < 256 && DestAS < 256;
2175 //===----------------------------------------------------------------------===//
2176 // Return Value Calling Convention Implementation
2177 //===----------------------------------------------------------------------===//
2179 #include "X86GenCallingConv.inc"
2181 bool X86TargetLowering::CanLowerReturn(
2182 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2183 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2184 SmallVector<CCValAssign, 16> RVLocs;
2185 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2186 return CCInfo.CheckReturn(Outs, RetCC_X86);
2189 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2190 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2195 X86TargetLowering::LowerReturn(SDValue Chain,
2196 CallingConv::ID CallConv, bool isVarArg,
2197 const SmallVectorImpl<ISD::OutputArg> &Outs,
2198 const SmallVectorImpl<SDValue> &OutVals,
2199 SDLoc dl, SelectionDAG &DAG) const {
2200 MachineFunction &MF = DAG.getMachineFunction();
2201 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2203 if (CallConv == CallingConv::X86_INTR && !Outs.empty())
2204 report_fatal_error("X86 interrupts may not return any value");
2206 SmallVector<CCValAssign, 16> RVLocs;
2207 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2208 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2211 SmallVector<SDValue, 6> RetOps;
2212 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2213 // Operand #1 = Bytes To Pop
2214 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2217 // Copy the result values into the output registers.
2218 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2219 CCValAssign &VA = RVLocs[i];
2220 assert(VA.isRegLoc() && "Can only return in registers!");
2221 SDValue ValToCopy = OutVals[i];
2222 EVT ValVT = ValToCopy.getValueType();
2224 // Promote values to the appropriate types.
2225 if (VA.getLocInfo() == CCValAssign::SExt)
2226 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2227 else if (VA.getLocInfo() == CCValAssign::ZExt)
2228 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2229 else if (VA.getLocInfo() == CCValAssign::AExt) {
2230 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2231 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2233 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2235 else if (VA.getLocInfo() == CCValAssign::BCvt)
2236 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2238 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2239 "Unexpected FP-extend for return value.");
2241 // If this is x86-64, and we disabled SSE, we can't return FP values,
2242 // or SSE or MMX vectors.
2243 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2244 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2245 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2246 report_fatal_error("SSE register return with SSE disabled");
2248 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2249 // llvm-gcc has never done it right and no one has noticed, so this
2250 // should be OK for now.
2251 if (ValVT == MVT::f64 &&
2252 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2253 report_fatal_error("SSE2 register return with SSE2 disabled");
2255 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2256 // the RET instruction and handled by the FP Stackifier.
2257 if (VA.getLocReg() == X86::FP0 ||
2258 VA.getLocReg() == X86::FP1) {
2259 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2260 // change the value to the FP stack register class.
2261 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2262 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2263 RetOps.push_back(ValToCopy);
2264 // Don't emit a copytoreg.
2268 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2269 // which is returned in RAX / RDX.
2270 if (Subtarget->is64Bit()) {
2271 if (ValVT == MVT::x86mmx) {
2272 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2273 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2274 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2276 // If we don't have SSE2 available, convert to v4f32 so the generated
2277 // register is legal.
2278 if (!Subtarget->hasSSE2())
2279 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2284 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2285 Flag = Chain.getValue(1);
2286 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2289 // All x86 ABIs require that for returning structs by value we copy
2290 // the sret argument into %rax/%eax (depending on ABI) for the return.
2291 // We saved the argument into a virtual register in the entry block,
2292 // so now we copy the value out and into %rax/%eax.
2294 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2295 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2296 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2297 // either case FuncInfo->setSRetReturnReg() will have been called.
2298 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2299 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2300 getPointerTy(MF.getDataLayout()));
2303 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2304 X86::RAX : X86::EAX;
2305 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2306 Flag = Chain.getValue(1);
2308 // RAX/EAX now acts like a return value.
2310 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2313 RetOps[0] = Chain; // Update chain.
2315 // Add the flag if we have it.
2317 RetOps.push_back(Flag);
2319 X86ISD::NodeType opcode = X86ISD::RET_FLAG;
2320 if (CallConv == CallingConv::X86_INTR)
2321 opcode = X86ISD::IRET;
2322 return DAG.getNode(opcode, dl, MVT::Other, RetOps);
2325 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2326 if (N->getNumValues() != 1)
2328 if (!N->hasNUsesOfValue(1, 0))
2331 SDValue TCChain = Chain;
2332 SDNode *Copy = *N->use_begin();
2333 if (Copy->getOpcode() == ISD::CopyToReg) {
2334 // If the copy has a glue operand, we conservatively assume it isn't safe to
2335 // perform a tail call.
2336 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2338 TCChain = Copy->getOperand(0);
2339 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2342 bool HasRet = false;
2343 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2345 if (UI->getOpcode() != X86ISD::RET_FLAG)
2347 // If we are returning more than one value, we can definitely
2348 // not make a tail call see PR19530
2349 if (UI->getNumOperands() > 4)
2351 if (UI->getNumOperands() == 4 &&
2352 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2365 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2366 ISD::NodeType ExtendKind) const {
2368 // TODO: Is this also valid on 32-bit?
2369 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2370 ReturnMVT = MVT::i8;
2372 ReturnMVT = MVT::i32;
2374 EVT MinVT = getRegisterType(Context, ReturnMVT);
2375 return VT.bitsLT(MinVT) ? MinVT : VT;
2378 /// Lower the result values of a call into the
2379 /// appropriate copies out of appropriate physical registers.
2382 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2383 CallingConv::ID CallConv, bool isVarArg,
2384 const SmallVectorImpl<ISD::InputArg> &Ins,
2385 SDLoc dl, SelectionDAG &DAG,
2386 SmallVectorImpl<SDValue> &InVals) const {
2388 // Assign locations to each value returned by this call.
2389 SmallVector<CCValAssign, 16> RVLocs;
2390 bool Is64Bit = Subtarget->is64Bit();
2391 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2393 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2395 // Copy all of the result registers out of their specified physreg.
2396 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2397 CCValAssign &VA = RVLocs[i];
2398 EVT CopyVT = VA.getLocVT();
2400 // If this is x86-64, and we disabled SSE, we can't return FP values
2401 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64 || CopyVT == MVT::f128) &&
2402 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2403 report_fatal_error("SSE register return with SSE disabled");
2406 // If we prefer to use the value in xmm registers, copy it out as f80 and
2407 // use a truncate to move it from fp stack reg to xmm reg.
2408 bool RoundAfterCopy = false;
2409 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2410 isScalarFPTypeInSSEReg(VA.getValVT())) {
2412 RoundAfterCopy = (CopyVT != VA.getLocVT());
2415 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2416 CopyVT, InFlag).getValue(1);
2417 SDValue Val = Chain.getValue(0);
2420 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2421 // This truncation won't change the value.
2422 DAG.getIntPtrConstant(1, dl));
2424 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2425 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2427 InFlag = Chain.getValue(2);
2428 InVals.push_back(Val);
2434 //===----------------------------------------------------------------------===//
2435 // C & StdCall & Fast Calling Convention implementation
2436 //===----------------------------------------------------------------------===//
2437 // StdCall calling convention seems to be standard for many Windows' API
2438 // routines and around. It differs from C calling convention just a little:
2439 // callee should clean up the stack, not caller. Symbols should be also
2440 // decorated in some fancy way :) It doesn't support any vector arguments.
2441 // For info on fast calling convention see Fast Calling Convention (tail call)
2442 // implementation LowerX86_32FastCCCallTo.
2444 /// CallIsStructReturn - Determines whether a call uses struct return
2446 enum StructReturnType {
2451 static StructReturnType
2452 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsMCU) {
2454 return NotStructReturn;
2456 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2457 if (!Flags.isSRet())
2458 return NotStructReturn;
2459 if (Flags.isInReg() || IsMCU)
2460 return RegStructReturn;
2461 return StackStructReturn;
2464 /// Determines whether a function uses struct return semantics.
2465 static StructReturnType
2466 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsMCU) {
2468 return NotStructReturn;
2470 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2471 if (!Flags.isSRet())
2472 return NotStructReturn;
2473 if (Flags.isInReg() || IsMCU)
2474 return RegStructReturn;
2475 return StackStructReturn;
2478 /// Make a copy of an aggregate at address specified by "Src" to address
2479 /// "Dst" with size and alignment information specified by the specific
2480 /// parameter attribute. The copy will be passed as a byval function parameter.
2482 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2483 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2485 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2487 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2488 /*isVolatile*/false, /*AlwaysInline=*/true,
2489 /*isTailCall*/false,
2490 MachinePointerInfo(), MachinePointerInfo());
2493 /// Return true if the calling convention is one that we can guarantee TCO for.
2494 static bool canGuaranteeTCO(CallingConv::ID CC) {
2495 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2496 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2499 /// Return true if we might ever do TCO for calls with this calling convention.
2500 static bool mayTailCallThisCC(CallingConv::ID CC) {
2502 // C calling conventions:
2503 case CallingConv::C:
2504 case CallingConv::X86_64_Win64:
2505 case CallingConv::X86_64_SysV:
2506 // Callee pop conventions:
2507 case CallingConv::X86_ThisCall:
2508 case CallingConv::X86_StdCall:
2509 case CallingConv::X86_VectorCall:
2510 case CallingConv::X86_FastCall:
2513 return canGuaranteeTCO(CC);
2517 /// Return true if the function is being made into a tailcall target by
2518 /// changing its ABI.
2519 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2520 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2523 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2525 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2526 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2530 CallingConv::ID CalleeCC = CS.getCallingConv();
2531 if (!mayTailCallThisCC(CalleeCC))
2538 X86TargetLowering::LowerMemArgument(SDValue Chain,
2539 CallingConv::ID CallConv,
2540 const SmallVectorImpl<ISD::InputArg> &Ins,
2541 SDLoc dl, SelectionDAG &DAG,
2542 const CCValAssign &VA,
2543 MachineFrameInfo *MFI,
2545 // Create the nodes corresponding to a load from this parameter slot.
2546 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2547 bool AlwaysUseMutable = shouldGuaranteeTCO(
2548 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2549 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2552 // If value is passed by pointer we have address passed instead of the value
2554 bool ExtendedInMem = VA.isExtInLoc() &&
2555 VA.getValVT().getScalarType() == MVT::i1;
2557 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2558 ValVT = VA.getLocVT();
2560 ValVT = VA.getValVT();
2562 // Calculate SP offset of interrupt parameter, re-arrange the slot normally
2563 // taken by a return address.
2565 if (CallConv == CallingConv::X86_INTR) {
2566 const X86Subtarget& Subtarget =
2567 static_cast<const X86Subtarget&>(DAG.getSubtarget());
2568 // X86 interrupts may take one or two arguments.
2569 // On the stack there will be no return address as in regular call.
2570 // Offset of last argument need to be set to -4/-8 bytes.
2571 // Where offset of the first argument out of two, should be set to 0 bytes.
2572 Offset = (Subtarget.is64Bit() ? 8 : 4) * ((i + 1) % Ins.size() - 1);
2575 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2576 // changed with more analysis.
2577 // In case of tail call optimization mark all arguments mutable. Since they
2578 // could be overwritten by lowering of arguments in case of a tail call.
2579 if (Flags.isByVal()) {
2580 unsigned Bytes = Flags.getByValSize();
2581 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2582 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2583 // Adjust SP offset of interrupt parameter.
2584 if (CallConv == CallingConv::X86_INTR) {
2585 MFI->setObjectOffset(FI, Offset);
2587 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2589 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2590 VA.getLocMemOffset(), isImmutable);
2591 // Adjust SP offset of interrupt parameter.
2592 if (CallConv == CallingConv::X86_INTR) {
2593 MFI->setObjectOffset(FI, Offset);
2596 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2597 SDValue Val = DAG.getLoad(
2598 ValVT, dl, Chain, FIN,
2599 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2601 return ExtendedInMem ?
2602 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2606 // FIXME: Get this from tablegen.
2607 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2608 const X86Subtarget *Subtarget) {
2609 assert(Subtarget->is64Bit());
2611 if (Subtarget->isCallingConvWin64(CallConv)) {
2612 static const MCPhysReg GPR64ArgRegsWin64[] = {
2613 X86::RCX, X86::RDX, X86::R8, X86::R9
2615 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2618 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2619 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2621 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2624 // FIXME: Get this from tablegen.
2625 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2626 CallingConv::ID CallConv,
2627 const X86Subtarget *Subtarget) {
2628 assert(Subtarget->is64Bit());
2629 if (Subtarget->isCallingConvWin64(CallConv)) {
2630 // The XMM registers which might contain var arg parameters are shadowed
2631 // in their paired GPR. So we only need to save the GPR to their home
2633 // TODO: __vectorcall will change this.
2637 const Function *Fn = MF.getFunction();
2638 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2639 bool isSoftFloat = Subtarget->useSoftFloat();
2640 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2641 "SSE register cannot be used when SSE is disabled!");
2642 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2643 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2647 static const MCPhysReg XMMArgRegs64Bit[] = {
2648 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2649 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2651 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2654 SDValue X86TargetLowering::LowerFormalArguments(
2655 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2656 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2657 SmallVectorImpl<SDValue> &InVals) const {
2658 MachineFunction &MF = DAG.getMachineFunction();
2659 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2660 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2662 const Function* Fn = MF.getFunction();
2663 if (Fn->hasExternalLinkage() &&
2664 Subtarget->isTargetCygMing() &&
2665 Fn->getName() == "main")
2666 FuncInfo->setForceFramePointer(true);
2668 MachineFrameInfo *MFI = MF.getFrameInfo();
2669 bool Is64Bit = Subtarget->is64Bit();
2670 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2672 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2673 "Var args not supported with calling convention fastcc, ghc or hipe");
2675 if (CallConv == CallingConv::X86_INTR) {
2676 bool isLegal = Ins.size() == 1 ||
2677 (Ins.size() == 2 && ((Is64Bit && Ins[1].VT == MVT::i64) ||
2678 (!Is64Bit && Ins[1].VT == MVT::i32)));
2680 report_fatal_error("X86 interrupts may take one or two arguments");
2683 // Assign locations to all of the incoming arguments.
2684 SmallVector<CCValAssign, 16> ArgLocs;
2685 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2687 // Allocate shadow area for Win64
2689 CCInfo.AllocateStack(32, 8);
2691 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2693 unsigned LastVal = ~0U;
2695 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2696 CCValAssign &VA = ArgLocs[i];
2697 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2699 assert(VA.getValNo() != LastVal &&
2700 "Don't support value assigned to multiple locs yet");
2702 LastVal = VA.getValNo();
2704 if (VA.isRegLoc()) {
2705 EVT RegVT = VA.getLocVT();
2706 const TargetRegisterClass *RC;
2707 if (RegVT == MVT::i32)
2708 RC = &X86::GR32RegClass;
2709 else if (Is64Bit && RegVT == MVT::i64)
2710 RC = &X86::GR64RegClass;
2711 else if (RegVT == MVT::f32)
2712 RC = &X86::FR32RegClass;
2713 else if (RegVT == MVT::f64)
2714 RC = &X86::FR64RegClass;
2715 else if (RegVT == MVT::f128)
2716 RC = &X86::FR128RegClass;
2717 else if (RegVT.is512BitVector())
2718 RC = &X86::VR512RegClass;
2719 else if (RegVT.is256BitVector())
2720 RC = &X86::VR256RegClass;
2721 else if (RegVT.is128BitVector())
2722 RC = &X86::VR128RegClass;
2723 else if (RegVT == MVT::x86mmx)
2724 RC = &X86::VR64RegClass;
2725 else if (RegVT == MVT::i1)
2726 RC = &X86::VK1RegClass;
2727 else if (RegVT == MVT::v8i1)
2728 RC = &X86::VK8RegClass;
2729 else if (RegVT == MVT::v16i1)
2730 RC = &X86::VK16RegClass;
2731 else if (RegVT == MVT::v32i1)
2732 RC = &X86::VK32RegClass;
2733 else if (RegVT == MVT::v64i1)
2734 RC = &X86::VK64RegClass;
2736 llvm_unreachable("Unknown argument type!");
2738 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2739 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2741 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2742 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2744 if (VA.getLocInfo() == CCValAssign::SExt)
2745 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2746 DAG.getValueType(VA.getValVT()));
2747 else if (VA.getLocInfo() == CCValAssign::ZExt)
2748 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2749 DAG.getValueType(VA.getValVT()));
2750 else if (VA.getLocInfo() == CCValAssign::BCvt)
2751 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2753 if (VA.isExtInLoc()) {
2754 // Handle MMX values passed in XMM regs.
2755 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2756 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2758 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2761 assert(VA.isMemLoc());
2762 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2765 // If value is passed via pointer - do a load.
2766 if (VA.getLocInfo() == CCValAssign::Indirect)
2767 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2768 MachinePointerInfo(), false, false, false, 0);
2770 InVals.push_back(ArgValue);
2773 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2774 // All x86 ABIs require that for returning structs by value we copy the
2775 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2776 // the argument into a virtual register so that we can access it from the
2778 if (Ins[i].Flags.isSRet()) {
2779 unsigned Reg = FuncInfo->getSRetReturnReg();
2781 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2782 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2783 FuncInfo->setSRetReturnReg(Reg);
2785 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2786 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2791 unsigned StackSize = CCInfo.getNextStackOffset();
2792 // Align stack specially for tail calls.
2793 if (shouldGuaranteeTCO(CallConv,
2794 MF.getTarget().Options.GuaranteedTailCallOpt))
2795 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2797 // If the function takes variable number of arguments, make a frame index for
2798 // the start of the first vararg value... for expansion of llvm.va_start. We
2799 // can skip this if there are no va_start calls.
2800 if (MFI->hasVAStart() &&
2801 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2802 CallConv != CallingConv::X86_ThisCall))) {
2803 FuncInfo->setVarArgsFrameIndex(
2804 MFI->CreateFixedObject(1, StackSize, true));
2807 // Figure out if XMM registers are in use.
2808 assert(!(Subtarget->useSoftFloat() &&
2809 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2810 "SSE register cannot be used when SSE is disabled!");
2812 // 64-bit calling conventions support varargs and register parameters, so we
2813 // have to do extra work to spill them in the prologue.
2814 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2815 // Find the first unallocated argument registers.
2816 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2817 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2818 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2819 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2820 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2821 "SSE register cannot be used when SSE is disabled!");
2823 // Gather all the live in physical registers.
2824 SmallVector<SDValue, 6> LiveGPRs;
2825 SmallVector<SDValue, 8> LiveXMMRegs;
2827 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2828 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2830 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2832 if (!ArgXMMs.empty()) {
2833 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2834 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2835 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2836 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2837 LiveXMMRegs.push_back(
2838 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2843 // Get to the caller-allocated home save location. Add 8 to account
2844 // for the return address.
2845 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2846 FuncInfo->setRegSaveFrameIndex(
2847 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2848 // Fixup to set vararg frame on shadow area (4 x i64).
2850 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2852 // For X86-64, if there are vararg parameters that are passed via
2853 // registers, then we must store them to their spots on the stack so
2854 // they may be loaded by deferencing the result of va_next.
2855 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2856 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2857 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2858 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2861 // Store the integer parameter registers.
2862 SmallVector<SDValue, 8> MemOps;
2863 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2864 getPointerTy(DAG.getDataLayout()));
2865 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2866 for (SDValue Val : LiveGPRs) {
2867 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2868 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2870 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2871 MachinePointerInfo::getFixedStack(
2872 DAG.getMachineFunction(),
2873 FuncInfo->getRegSaveFrameIndex(), Offset),
2875 MemOps.push_back(Store);
2879 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2880 // Now store the XMM (fp + vector) parameter registers.
2881 SmallVector<SDValue, 12> SaveXMMOps;
2882 SaveXMMOps.push_back(Chain);
2883 SaveXMMOps.push_back(ALVal);
2884 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2885 FuncInfo->getRegSaveFrameIndex(), dl));
2886 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2887 FuncInfo->getVarArgsFPOffset(), dl));
2888 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2890 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2891 MVT::Other, SaveXMMOps));
2894 if (!MemOps.empty())
2895 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2898 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2899 // Find the largest legal vector type.
2900 MVT VecVT = MVT::Other;
2901 // FIXME: Only some x86_32 calling conventions support AVX512.
2902 if (Subtarget->hasAVX512() &&
2903 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2904 CallConv == CallingConv::Intel_OCL_BI)))
2905 VecVT = MVT::v16f32;
2906 else if (Subtarget->hasAVX())
2908 else if (Subtarget->hasSSE2())
2911 // We forward some GPRs and some vector types.
2912 SmallVector<MVT, 2> RegParmTypes;
2913 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2914 RegParmTypes.push_back(IntVT);
2915 if (VecVT != MVT::Other)
2916 RegParmTypes.push_back(VecVT);
2918 // Compute the set of forwarded registers. The rest are scratch.
2919 SmallVectorImpl<ForwardedRegister> &Forwards =
2920 FuncInfo->getForwardedMustTailRegParms();
2921 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2923 // Conservatively forward AL on x86_64, since it might be used for varargs.
2924 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2925 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2926 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2929 // Copy all forwards from physical to virtual registers.
2930 for (ForwardedRegister &F : Forwards) {
2931 // FIXME: Can we use a less constrained schedule?
2932 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2933 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2934 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2938 // Some CCs need callee pop.
2939 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2940 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2941 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2942 } else if (CallConv == CallingConv::X86_INTR && Ins.size() == 2) {
2943 // X86 interrupts must pop the error code if present
2944 FuncInfo->setBytesToPopOnReturn(Is64Bit ? 8 : 4);
2946 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2947 // If this is an sret function, the return should pop the hidden pointer.
2948 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2949 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2950 argsAreStructReturn(Ins, Subtarget->isTargetMCU()) == StackStructReturn)
2951 FuncInfo->setBytesToPopOnReturn(4);
2955 // RegSaveFrameIndex is X86-64 only.
2956 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2957 if (CallConv == CallingConv::X86_FastCall ||
2958 CallConv == CallingConv::X86_ThisCall)
2959 // fastcc functions can't have varargs.
2960 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2963 FuncInfo->setArgumentStackSize(StackSize);
2965 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2966 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2967 if (Personality == EHPersonality::CoreCLR) {
2969 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2970 // that we'd prefer this slot be allocated towards the bottom of the frame
2971 // (i.e. near the stack pointer after allocating the frame). Every
2972 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2973 // offset from the bottom of this and each funclet's frame must be the
2974 // same, so the size of funclets' (mostly empty) frames is dictated by
2975 // how far this slot is from the bottom (since they allocate just enough
2976 // space to accomodate holding this slot at the correct offset).
2977 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2978 EHInfo->PSPSymFrameIdx = PSPSymFI;
2986 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2987 SDValue StackPtr, SDValue Arg,
2988 SDLoc dl, SelectionDAG &DAG,
2989 const CCValAssign &VA,
2990 ISD::ArgFlagsTy Flags) const {
2991 unsigned LocMemOffset = VA.getLocMemOffset();
2992 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2993 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2995 if (Flags.isByVal())
2996 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2998 return DAG.getStore(
2999 Chain, dl, Arg, PtrOff,
3000 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
3004 /// Emit a load of return address if tail call
3005 /// optimization is performed and it is required.
3007 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
3008 SDValue &OutRetAddr, SDValue Chain,
3009 bool IsTailCall, bool Is64Bit,
3010 int FPDiff, SDLoc dl) const {
3011 // Adjust the Return address stack slot.
3012 EVT VT = getPointerTy(DAG.getDataLayout());
3013 OutRetAddr = getReturnAddressFrameIndex(DAG);
3015 // Load the "old" Return address.
3016 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
3017 false, false, false, 0);
3018 return SDValue(OutRetAddr.getNode(), 1);
3021 /// Emit a store of the return address if tail call
3022 /// optimization is performed and it is required (FPDiff!=0).
3023 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
3024 SDValue Chain, SDValue RetAddrFrIdx,
3025 EVT PtrVT, unsigned SlotSize,
3026 int FPDiff, SDLoc dl) {
3027 // Store the return address to the appropriate stack slot.
3028 if (!FPDiff) return Chain;
3029 // Calculate the new stack slot for the return address.
3030 int NewReturnAddrFI =
3031 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
3033 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
3034 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
3035 MachinePointerInfo::getFixedStack(
3036 DAG.getMachineFunction(), NewReturnAddrFI),
3041 /// Returns a vector_shuffle mask for an movs{s|d}, movd
3042 /// operation of specified width.
3043 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
3045 unsigned NumElems = VT.getVectorNumElements();
3046 SmallVector<int, 8> Mask;
3047 Mask.push_back(NumElems);
3048 for (unsigned i = 1; i != NumElems; ++i)
3050 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
3054 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3055 SmallVectorImpl<SDValue> &InVals) const {
3056 SelectionDAG &DAG = CLI.DAG;
3058 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3059 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3060 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3061 SDValue Chain = CLI.Chain;
3062 SDValue Callee = CLI.Callee;
3063 CallingConv::ID CallConv = CLI.CallConv;
3064 bool &isTailCall = CLI.IsTailCall;
3065 bool isVarArg = CLI.IsVarArg;
3067 MachineFunction &MF = DAG.getMachineFunction();
3068 bool Is64Bit = Subtarget->is64Bit();
3069 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
3070 StructReturnType SR = callIsStructReturn(Outs, Subtarget->isTargetMCU());
3071 bool IsSibcall = false;
3072 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3073 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3075 if (CallConv == CallingConv::X86_INTR)
3076 report_fatal_error("X86 interrupts may not be called directly");
3078 if (Attr.getValueAsString() == "true")
3081 if (Subtarget->isPICStyleGOT() &&
3082 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3083 // If we are using a GOT, disable tail calls to external symbols with
3084 // default visibility. Tail calling such a symbol requires using a GOT
3085 // relocation, which forces early binding of the symbol. This breaks code
3086 // that require lazy function symbol resolution. Using musttail or
3087 // GuaranteedTailCallOpt will override this.
3088 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3089 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3090 G->getGlobal()->hasDefaultVisibility()))
3094 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3096 // Force this to be a tail call. The verifier rules are enough to ensure
3097 // that we can lower this successfully without moving the return address
3100 } else if (isTailCall) {
3101 // Check if it's really possible to do a tail call.
3102 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3103 isVarArg, SR != NotStructReturn,
3104 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3105 Outs, OutVals, Ins, DAG);
3107 // Sibcalls are automatically detected tailcalls which do not require
3109 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3116 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3117 "Var args not supported with calling convention fastcc, ghc or hipe");
3119 // Analyze operands of the call, assigning locations to each operand.
3120 SmallVector<CCValAssign, 16> ArgLocs;
3121 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3123 // Allocate shadow area for Win64
3125 CCInfo.AllocateStack(32, 8);
3127 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3129 // Get a count of how many bytes are to be pushed on the stack.
3130 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3132 // This is a sibcall. The memory operands are available in caller's
3133 // own caller's stack.
3135 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3136 canGuaranteeTCO(CallConv))
3137 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3140 if (isTailCall && !IsSibcall && !IsMustTail) {
3141 // Lower arguments at fp - stackoffset + fpdiff.
3142 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3144 FPDiff = NumBytesCallerPushed - NumBytes;
3146 // Set the delta of movement of the returnaddr stackslot.
3147 // But only set if delta is greater than previous delta.
3148 if (FPDiff < X86Info->getTCReturnAddrDelta())
3149 X86Info->setTCReturnAddrDelta(FPDiff);
3152 unsigned NumBytesToPush = NumBytes;
3153 unsigned NumBytesToPop = NumBytes;
3155 // If we have an inalloca argument, all stack space has already been allocated
3156 // for us and be right at the top of the stack. We don't support multiple
3157 // arguments passed in memory when using inalloca.
3158 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3160 if (!ArgLocs.back().isMemLoc())
3161 report_fatal_error("cannot use inalloca attribute on a register "
3163 if (ArgLocs.back().getLocMemOffset() != 0)
3164 report_fatal_error("any parameter with the inalloca attribute must be "
3165 "the only memory argument");
3169 Chain = DAG.getCALLSEQ_START(
3170 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3172 SDValue RetAddrFrIdx;
3173 // Load return address for tail calls.
3174 if (isTailCall && FPDiff)
3175 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3176 Is64Bit, FPDiff, dl);
3178 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3179 SmallVector<SDValue, 8> MemOpChains;
3182 // Walk the register/memloc assignments, inserting copies/loads. In the case
3183 // of tail call optimization arguments are handle later.
3184 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3185 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3186 // Skip inalloca arguments, they have already been written.
3187 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3188 if (Flags.isInAlloca())
3191 CCValAssign &VA = ArgLocs[i];
3192 EVT RegVT = VA.getLocVT();
3193 SDValue Arg = OutVals[i];
3194 bool isByVal = Flags.isByVal();
3196 // Promote the value if needed.
3197 switch (VA.getLocInfo()) {
3198 default: llvm_unreachable("Unknown loc info!");
3199 case CCValAssign::Full: break;
3200 case CCValAssign::SExt:
3201 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3203 case CCValAssign::ZExt:
3204 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3206 case CCValAssign::AExt:
3207 if (Arg.getValueType().isVector() &&
3208 Arg.getValueType().getVectorElementType() == MVT::i1)
3209 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3210 else if (RegVT.is128BitVector()) {
3211 // Special case: passing MMX values in XMM registers.
3212 Arg = DAG.getBitcast(MVT::i64, Arg);
3213 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3214 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3216 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3218 case CCValAssign::BCvt:
3219 Arg = DAG.getBitcast(RegVT, Arg);
3221 case CCValAssign::Indirect: {
3222 // Store the argument.
3223 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3224 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3225 Chain = DAG.getStore(
3226 Chain, dl, Arg, SpillSlot,
3227 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3234 if (VA.isRegLoc()) {
3235 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3236 if (isVarArg && IsWin64) {
3237 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3238 // shadow reg if callee is a varargs function.
3239 unsigned ShadowReg = 0;
3240 switch (VA.getLocReg()) {
3241 case X86::XMM0: ShadowReg = X86::RCX; break;
3242 case X86::XMM1: ShadowReg = X86::RDX; break;
3243 case X86::XMM2: ShadowReg = X86::R8; break;
3244 case X86::XMM3: ShadowReg = X86::R9; break;
3247 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3249 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3250 assert(VA.isMemLoc());
3251 if (!StackPtr.getNode())
3252 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3253 getPointerTy(DAG.getDataLayout()));
3254 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3255 dl, DAG, VA, Flags));
3259 if (!MemOpChains.empty())
3260 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3262 if (Subtarget->isPICStyleGOT()) {
3263 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3266 RegsToPass.push_back(std::make_pair(
3267 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3268 getPointerTy(DAG.getDataLayout()))));
3270 // If we are tail calling and generating PIC/GOT style code load the
3271 // address of the callee into ECX. The value in ecx is used as target of
3272 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3273 // for tail calls on PIC/GOT architectures. Normally we would just put the
3274 // address of GOT into ebx and then call target@PLT. But for tail calls
3275 // ebx would be restored (since ebx is callee saved) before jumping to the
3278 // Note: The actual moving to ECX is done further down.
3279 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3280 if (G && !G->getGlobal()->hasLocalLinkage() &&
3281 G->getGlobal()->hasDefaultVisibility())
3282 Callee = LowerGlobalAddress(Callee, DAG);
3283 else if (isa<ExternalSymbolSDNode>(Callee))
3284 Callee = LowerExternalSymbol(Callee, DAG);
3288 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3289 // From AMD64 ABI document:
3290 // For calls that may call functions that use varargs or stdargs
3291 // (prototype-less calls or calls to functions containing ellipsis (...) in
3292 // the declaration) %al is used as hidden argument to specify the number
3293 // of SSE registers used. The contents of %al do not need to match exactly
3294 // the number of registers, but must be an ubound on the number of SSE
3295 // registers used and is in the range 0 - 8 inclusive.
3297 // Count the number of XMM registers allocated.
3298 static const MCPhysReg XMMArgRegs[] = {
3299 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3300 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3302 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3303 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3304 && "SSE registers cannot be used when SSE is disabled");
3306 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3307 DAG.getConstant(NumXMMRegs, dl,
3311 if (isVarArg && IsMustTail) {
3312 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3313 for (const auto &F : Forwards) {
3314 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3315 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3319 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3320 // don't need this because the eligibility check rejects calls that require
3321 // shuffling arguments passed in memory.
3322 if (!IsSibcall && isTailCall) {
3323 // Force all the incoming stack arguments to be loaded from the stack
3324 // before any new outgoing arguments are stored to the stack, because the
3325 // outgoing stack slots may alias the incoming argument stack slots, and
3326 // the alias isn't otherwise explicit. This is slightly more conservative
3327 // than necessary, because it means that each store effectively depends
3328 // on every argument instead of just those arguments it would clobber.
3329 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3331 SmallVector<SDValue, 8> MemOpChains2;
3334 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3335 CCValAssign &VA = ArgLocs[i];
3338 assert(VA.isMemLoc());
3339 SDValue Arg = OutVals[i];
3340 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3341 // Skip inalloca arguments. They don't require any work.
3342 if (Flags.isInAlloca())
3344 // Create frame index.
3345 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3346 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3347 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3348 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3350 if (Flags.isByVal()) {
3351 // Copy relative to framepointer.
3352 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3353 if (!StackPtr.getNode())
3354 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3355 getPointerTy(DAG.getDataLayout()));
3356 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3359 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3363 // Store relative to framepointer.
3364 MemOpChains2.push_back(DAG.getStore(
3365 ArgChain, dl, Arg, FIN,
3366 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3371 if (!MemOpChains2.empty())
3372 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3374 // Store the return address to the appropriate stack slot.
3375 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3376 getPointerTy(DAG.getDataLayout()),
3377 RegInfo->getSlotSize(), FPDiff, dl);
3380 // Build a sequence of copy-to-reg nodes chained together with token chain
3381 // and flag operands which copy the outgoing args into registers.
3383 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3384 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3385 RegsToPass[i].second, InFlag);
3386 InFlag = Chain.getValue(1);
3389 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3390 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3391 // In the 64-bit large code model, we have to make all calls
3392 // through a register, since the call instruction's 32-bit
3393 // pc-relative offset may not be large enough to hold the whole
3395 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3396 // If the callee is a GlobalAddress node (quite common, every direct call
3397 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3399 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3401 // We should use extra load for direct calls to dllimported functions in
3403 const GlobalValue *GV = G->getGlobal();
3404 if (!GV->hasDLLImportStorageClass()) {
3405 unsigned char OpFlags = 0;
3406 bool ExtraLoad = false;
3407 unsigned WrapperKind = ISD::DELETED_NODE;
3409 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3410 // external symbols most go through the PLT in PIC mode. If the symbol
3411 // has hidden or protected visibility, or if it is static or local, then
3412 // we don't need to use the PLT - we can directly call it.
3413 if (Subtarget->isTargetELF() &&
3414 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3415 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3416 OpFlags = X86II::MO_PLT;
3417 } else if (Subtarget->isPICStyleStubAny() &&
3418 !GV->isStrongDefinitionForLinker() &&
3419 (!Subtarget->getTargetTriple().isMacOSX() ||
3420 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3421 // PC-relative references to external symbols should go through $stub,
3422 // unless we're building with the leopard linker or later, which
3423 // automatically synthesizes these stubs.
3424 OpFlags = X86II::MO_DARWIN_STUB;
3425 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3426 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3427 // If the function is marked as non-lazy, generate an indirect call
3428 // which loads from the GOT directly. This avoids runtime overhead
3429 // at the cost of eager binding (and one extra byte of encoding).
3430 OpFlags = X86II::MO_GOTPCREL;
3431 WrapperKind = X86ISD::WrapperRIP;
3435 Callee = DAG.getTargetGlobalAddress(
3436 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3438 // Add a wrapper if needed.
3439 if (WrapperKind != ISD::DELETED_NODE)
3440 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3441 getPointerTy(DAG.getDataLayout()), Callee);
3442 // Add extra indirection if needed.
3444 Callee = DAG.getLoad(
3445 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3446 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3449 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3450 unsigned char OpFlags = 0;
3452 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3453 // external symbols should go through the PLT.
3454 if (Subtarget->isTargetELF() &&
3455 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3456 OpFlags = X86II::MO_PLT;
3457 } else if (Subtarget->isPICStyleStubAny() &&
3458 (!Subtarget->getTargetTriple().isMacOSX() ||
3459 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3460 // PC-relative references to external symbols should go through $stub,
3461 // unless we're building with the leopard linker or later, which
3462 // automatically synthesizes these stubs.
3463 OpFlags = X86II::MO_DARWIN_STUB;
3466 Callee = DAG.getTargetExternalSymbol(
3467 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3468 } else if (Subtarget->isTarget64BitILP32() &&
3469 Callee->getValueType(0) == MVT::i32) {
3470 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3471 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3474 // Returns a chain & a flag for retval copy to use.
3475 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3476 SmallVector<SDValue, 8> Ops;
3478 if (!IsSibcall && isTailCall) {
3479 Chain = DAG.getCALLSEQ_END(Chain,
3480 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3481 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3482 InFlag = Chain.getValue(1);
3485 Ops.push_back(Chain);
3486 Ops.push_back(Callee);
3489 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3491 // Add argument registers to the end of the list so that they are known live
3493 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3494 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3495 RegsToPass[i].second.getValueType()));
3497 // Add a register mask operand representing the call-preserved registers.
3498 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3499 assert(Mask && "Missing call preserved mask for calling convention");
3501 // If this is an invoke in a 32-bit function using a funclet-based
3502 // personality, assume the function clobbers all registers. If an exception
3503 // is thrown, the runtime will not restore CSRs.
3504 // FIXME: Model this more precisely so that we can register allocate across
3505 // the normal edge and spill and fill across the exceptional edge.
3506 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3507 const Function *CallerFn = MF.getFunction();
3508 EHPersonality Pers =
3509 CallerFn->hasPersonalityFn()
3510 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3511 : EHPersonality::Unknown;
3512 if (isFuncletEHPersonality(Pers))
3513 Mask = RegInfo->getNoPreservedMask();
3516 Ops.push_back(DAG.getRegisterMask(Mask));
3518 if (InFlag.getNode())
3519 Ops.push_back(InFlag);
3523 //// If this is the first return lowered for this function, add the regs
3524 //// to the liveout set for the function.
3525 // This isn't right, although it's probably harmless on x86; liveouts
3526 // should be computed from returns not tail calls. Consider a void
3527 // function making a tail call to a function returning int.
3528 MF.getFrameInfo()->setHasTailCall();
3529 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3532 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3533 InFlag = Chain.getValue(1);
3535 // Create the CALLSEQ_END node.
3536 unsigned NumBytesForCalleeToPop;
3537 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3538 DAG.getTarget().Options.GuaranteedTailCallOpt))
3539 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3540 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3541 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3542 SR == StackStructReturn)
3543 // If this is a call to a struct-return function, the callee
3544 // pops the hidden struct pointer, so we have to push it back.
3545 // This is common for Darwin/X86, Linux & Mingw32 targets.
3546 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3547 NumBytesForCalleeToPop = 4;
3549 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3551 // Returns a flag for retval copy to use.
3553 Chain = DAG.getCALLSEQ_END(Chain,
3554 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3555 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3558 InFlag = Chain.getValue(1);
3561 // Handle result values, copying them out of physregs into vregs that we
3563 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3564 Ins, dl, DAG, InVals);
3567 //===----------------------------------------------------------------------===//
3568 // Fast Calling Convention (tail call) implementation
3569 //===----------------------------------------------------------------------===//
3571 // Like std call, callee cleans arguments, convention except that ECX is
3572 // reserved for storing the tail called function address. Only 2 registers are
3573 // free for argument passing (inreg). Tail call optimization is performed
3575 // * tailcallopt is enabled
3576 // * caller/callee are fastcc
3577 // On X86_64 architecture with GOT-style position independent code only local
3578 // (within module) calls are supported at the moment.
3579 // To keep the stack aligned according to platform abi the function
3580 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3581 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3582 // If a tail called function callee has more arguments than the caller the
3583 // caller needs to make sure that there is room to move the RETADDR to. This is
3584 // achieved by reserving an area the size of the argument delta right after the
3585 // original RETADDR, but before the saved framepointer or the spilled registers
3586 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3598 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3601 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3602 SelectionDAG& DAG) const {
3603 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3604 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3605 unsigned StackAlignment = TFI.getStackAlignment();
3606 uint64_t AlignMask = StackAlignment - 1;
3607 int64_t Offset = StackSize;
3608 unsigned SlotSize = RegInfo->getSlotSize();
3609 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3610 // Number smaller than 12 so just add the difference.
3611 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3613 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3614 Offset = ((~AlignMask) & Offset) + StackAlignment +
3615 (StackAlignment-SlotSize);
3620 /// Return true if the given stack call argument is already available in the
3621 /// same position (relatively) of the caller's incoming argument stack.
3623 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3624 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3625 const X86InstrInfo *TII) {
3626 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3628 if (Arg.getOpcode() == ISD::CopyFromReg) {
3629 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3630 if (!TargetRegisterInfo::isVirtualRegister(VR))
3632 MachineInstr *Def = MRI->getVRegDef(VR);
3635 if (!Flags.isByVal()) {
3636 if (!TII->isLoadFromStackSlot(Def, FI))
3639 unsigned Opcode = Def->getOpcode();
3640 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3641 Opcode == X86::LEA64_32r) &&
3642 Def->getOperand(1).isFI()) {
3643 FI = Def->getOperand(1).getIndex();
3644 Bytes = Flags.getByValSize();
3648 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3649 if (Flags.isByVal())
3650 // ByVal argument is passed in as a pointer but it's now being
3651 // dereferenced. e.g.
3652 // define @foo(%struct.X* %A) {
3653 // tail call @bar(%struct.X* byval %A)
3656 SDValue Ptr = Ld->getBasePtr();
3657 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3660 FI = FINode->getIndex();
3661 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3662 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3663 FI = FINode->getIndex();
3664 Bytes = Flags.getByValSize();
3668 assert(FI != INT_MAX);
3669 if (!MFI->isFixedObjectIndex(FI))
3671 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3674 /// Check whether the call is eligible for tail call optimization. Targets
3675 /// that want to do tail call optimization should implement this function.
3676 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3677 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3678 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3679 const SmallVectorImpl<ISD::OutputArg> &Outs,
3680 const SmallVectorImpl<SDValue> &OutVals,
3681 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3682 if (!mayTailCallThisCC(CalleeCC))
3685 // If -tailcallopt is specified, make fastcc functions tail-callable.
3686 MachineFunction &MF = DAG.getMachineFunction();
3687 const Function *CallerF = MF.getFunction();
3689 // If the function return type is x86_fp80 and the callee return type is not,
3690 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3691 // perform a tailcall optimization here.
3692 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3695 CallingConv::ID CallerCC = CallerF->getCallingConv();
3696 bool CCMatch = CallerCC == CalleeCC;
3697 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3698 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3700 // Win64 functions have extra shadow space for argument homing. Don't do the
3701 // sibcall if the caller and callee have mismatched expectations for this
3703 if (IsCalleeWin64 != IsCallerWin64)
3706 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3707 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3712 // Look for obvious safe cases to perform tail call optimization that do not
3713 // require ABI changes. This is what gcc calls sibcall.
3715 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3716 // emit a special epilogue.
3717 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3718 if (RegInfo->needsStackRealignment(MF))
3721 // Also avoid sibcall optimization if either caller or callee uses struct
3722 // return semantics.
3723 if (isCalleeStructRet || isCallerStructRet)
3726 // Do not sibcall optimize vararg calls unless all arguments are passed via
3728 if (isVarArg && !Outs.empty()) {
3729 // Optimizing for varargs on Win64 is unlikely to be safe without
3730 // additional testing.
3731 if (IsCalleeWin64 || IsCallerWin64)
3734 SmallVector<CCValAssign, 16> ArgLocs;
3735 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3738 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3739 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3740 if (!ArgLocs[i].isRegLoc())
3744 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3745 // stack. Therefore, if it's not used by the call it is not safe to optimize
3746 // this into a sibcall.
3747 bool Unused = false;
3748 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3755 SmallVector<CCValAssign, 16> RVLocs;
3756 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3758 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3759 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3760 CCValAssign &VA = RVLocs[i];
3761 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3766 // If the calling conventions do not match, then we'd better make sure the
3767 // results are returned in the same way as what the caller expects.
3769 SmallVector<CCValAssign, 16> RVLocs1;
3770 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3772 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3774 SmallVector<CCValAssign, 16> RVLocs2;
3775 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3777 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3779 if (RVLocs1.size() != RVLocs2.size())
3781 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3782 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3784 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3786 if (RVLocs1[i].isRegLoc()) {
3787 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3790 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3796 unsigned StackArgsSize = 0;
3798 // If the callee takes no arguments then go on to check the results of the
3800 if (!Outs.empty()) {
3801 // Check if stack adjustment is needed. For now, do not do this if any
3802 // argument is passed on the stack.
3803 SmallVector<CCValAssign, 16> ArgLocs;
3804 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3807 // Allocate shadow area for Win64
3809 CCInfo.AllocateStack(32, 8);
3811 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3812 StackArgsSize = CCInfo.getNextStackOffset();
3814 if (CCInfo.getNextStackOffset()) {
3815 // Check if the arguments are already laid out in the right way as
3816 // the caller's fixed stack objects.
3817 MachineFrameInfo *MFI = MF.getFrameInfo();
3818 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3819 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3820 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3821 CCValAssign &VA = ArgLocs[i];
3822 SDValue Arg = OutVals[i];
3823 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3824 if (VA.getLocInfo() == CCValAssign::Indirect)
3826 if (!VA.isRegLoc()) {
3827 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3834 // If the tailcall address may be in a register, then make sure it's
3835 // possible to register allocate for it. In 32-bit, the call address can
3836 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3837 // callee-saved registers are restored. These happen to be the same
3838 // registers used to pass 'inreg' arguments so watch out for those.
3839 if (!Subtarget->is64Bit() &&
3840 ((!isa<GlobalAddressSDNode>(Callee) &&
3841 !isa<ExternalSymbolSDNode>(Callee)) ||
3842 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3843 unsigned NumInRegs = 0;
3844 // In PIC we need an extra register to formulate the address computation
3846 unsigned MaxInRegs =
3847 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3849 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3850 CCValAssign &VA = ArgLocs[i];
3853 unsigned Reg = VA.getLocReg();
3856 case X86::EAX: case X86::EDX: case X86::ECX:
3857 if (++NumInRegs == MaxInRegs)
3865 bool CalleeWillPop =
3866 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3867 MF.getTarget().Options.GuaranteedTailCallOpt);
3869 if (unsigned BytesToPop =
3870 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3871 // If we have bytes to pop, the callee must pop them.
3872 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3873 if (!CalleePopMatches)
3875 } else if (CalleeWillPop && StackArgsSize > 0) {
3876 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3884 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3885 const TargetLibraryInfo *libInfo) const {
3886 return X86::createFastISel(funcInfo, libInfo);
3889 //===----------------------------------------------------------------------===//
3890 // Other Lowering Hooks
3891 //===----------------------------------------------------------------------===//
3893 static bool MayFoldLoad(SDValue Op) {
3894 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3897 static bool MayFoldIntoStore(SDValue Op) {
3898 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3901 static bool isTargetShuffle(unsigned Opcode) {
3903 default: return false;
3904 case X86ISD::BLENDI:
3905 case X86ISD::PSHUFB:
3906 case X86ISD::PSHUFD:
3907 case X86ISD::PSHUFHW:
3908 case X86ISD::PSHUFLW:
3910 case X86ISD::INSERTPS:
3911 case X86ISD::PALIGNR:
3912 case X86ISD::MOVLHPS:
3913 case X86ISD::MOVLHPD:
3914 case X86ISD::MOVHLPS:
3915 case X86ISD::MOVLPS:
3916 case X86ISD::MOVLPD:
3917 case X86ISD::MOVSHDUP:
3918 case X86ISD::MOVSLDUP:
3919 case X86ISD::MOVDDUP:
3922 case X86ISD::UNPCKL:
3923 case X86ISD::UNPCKH:
3924 case X86ISD::VPERMILPI:
3925 case X86ISD::VPERM2X128:
3926 case X86ISD::VPERMI:
3927 case X86ISD::VPERMV:
3928 case X86ISD::VPERMV3:
3933 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3934 SDValue V1, unsigned TargetMask,
3935 SelectionDAG &DAG) {
3937 default: llvm_unreachable("Unknown x86 shuffle node");
3938 case X86ISD::PSHUFD:
3939 case X86ISD::PSHUFHW:
3940 case X86ISD::PSHUFLW:
3941 case X86ISD::VPERMILPI:
3942 case X86ISD::VPERMI:
3943 return DAG.getNode(Opc, dl, VT, V1,
3944 DAG.getConstant(TargetMask, dl, MVT::i8));
3948 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3949 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3951 default: llvm_unreachable("Unknown x86 shuffle node");
3952 case X86ISD::MOVLHPS:
3953 case X86ISD::MOVLHPD:
3954 case X86ISD::MOVHLPS:
3955 case X86ISD::MOVLPS:
3956 case X86ISD::MOVLPD:
3959 case X86ISD::UNPCKL:
3960 case X86ISD::UNPCKH:
3961 return DAG.getNode(Opc, dl, VT, V1, V2);
3965 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3966 MachineFunction &MF = DAG.getMachineFunction();
3967 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3968 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3969 int ReturnAddrIndex = FuncInfo->getRAIndex();
3971 if (ReturnAddrIndex == 0) {
3972 // Set up a frame object for the return address.
3973 unsigned SlotSize = RegInfo->getSlotSize();
3974 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3977 FuncInfo->setRAIndex(ReturnAddrIndex);
3980 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3983 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3984 bool hasSymbolicDisplacement) {
3985 // Offset should fit into 32 bit immediate field.
3986 if (!isInt<32>(Offset))
3989 // If we don't have a symbolic displacement - we don't have any extra
3991 if (!hasSymbolicDisplacement)
3994 // FIXME: Some tweaks might be needed for medium code model.
3995 if (M != CodeModel::Small && M != CodeModel::Kernel)
3998 // For small code model we assume that latest object is 16MB before end of 31
3999 // bits boundary. We may also accept pretty large negative constants knowing
4000 // that all objects are in the positive half of address space.
4001 if (M == CodeModel::Small && Offset < 16*1024*1024)
4004 // For kernel code model we know that all object resist in the negative half
4005 // of 32bits address space. We may not accept negative offsets, since they may
4006 // be just off and we may accept pretty large positive ones.
4007 if (M == CodeModel::Kernel && Offset >= 0)
4013 /// Determines whether the callee is required to pop its own arguments.
4014 /// Callee pop is necessary to support tail calls.
4015 bool X86::isCalleePop(CallingConv::ID CallingConv,
4016 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
4017 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
4018 // can guarantee TCO.
4019 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
4022 switch (CallingConv) {
4025 case CallingConv::X86_StdCall:
4026 case CallingConv::X86_FastCall:
4027 case CallingConv::X86_ThisCall:
4028 case CallingConv::X86_VectorCall:
4033 /// \brief Return true if the condition is an unsigned comparison operation.
4034 static bool isX86CCUnsigned(unsigned X86CC) {
4036 default: llvm_unreachable("Invalid integer condition!");
4037 case X86::COND_E: return true;
4038 case X86::COND_G: return false;
4039 case X86::COND_GE: return false;
4040 case X86::COND_L: return false;
4041 case X86::COND_LE: return false;
4042 case X86::COND_NE: return true;
4043 case X86::COND_B: return true;
4044 case X86::COND_A: return true;
4045 case X86::COND_BE: return true;
4046 case X86::COND_AE: return true;
4050 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
4051 switch (SetCCOpcode) {
4052 default: llvm_unreachable("Invalid integer condition!");
4053 case ISD::SETEQ: return X86::COND_E;
4054 case ISD::SETGT: return X86::COND_G;
4055 case ISD::SETGE: return X86::COND_GE;
4056 case ISD::SETLT: return X86::COND_L;
4057 case ISD::SETLE: return X86::COND_LE;
4058 case ISD::SETNE: return X86::COND_NE;
4059 case ISD::SETULT: return X86::COND_B;
4060 case ISD::SETUGT: return X86::COND_A;
4061 case ISD::SETULE: return X86::COND_BE;
4062 case ISD::SETUGE: return X86::COND_AE;
4066 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
4067 /// condition code, returning the condition code and the LHS/RHS of the
4068 /// comparison to make.
4069 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
4070 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
4072 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
4073 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
4074 // X > -1 -> X == 0, jump !sign.
4075 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4076 return X86::COND_NS;
4078 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
4079 // X < 0 -> X == 0, jump on sign.
4082 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4084 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4085 return X86::COND_LE;
4089 return TranslateIntegerX86CC(SetCCOpcode);
4092 // First determine if it is required or is profitable to flip the operands.
4094 // If LHS is a foldable load, but RHS is not, flip the condition.
4095 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4096 !ISD::isNON_EXTLoad(RHS.getNode())) {
4097 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4098 std::swap(LHS, RHS);
4101 switch (SetCCOpcode) {
4107 std::swap(LHS, RHS);
4111 // On a floating point condition, the flags are set as follows:
4113 // 0 | 0 | 0 | X > Y
4114 // 0 | 0 | 1 | X < Y
4115 // 1 | 0 | 0 | X == Y
4116 // 1 | 1 | 1 | unordered
4117 switch (SetCCOpcode) {
4118 default: llvm_unreachable("Condcode should be pre-legalized away");
4120 case ISD::SETEQ: return X86::COND_E;
4121 case ISD::SETOLT: // flipped
4123 case ISD::SETGT: return X86::COND_A;
4124 case ISD::SETOLE: // flipped
4126 case ISD::SETGE: return X86::COND_AE;
4127 case ISD::SETUGT: // flipped
4129 case ISD::SETLT: return X86::COND_B;
4130 case ISD::SETUGE: // flipped
4132 case ISD::SETLE: return X86::COND_BE;
4134 case ISD::SETNE: return X86::COND_NE;
4135 case ISD::SETUO: return X86::COND_P;
4136 case ISD::SETO: return X86::COND_NP;
4138 case ISD::SETUNE: return X86::COND_INVALID;
4142 /// Is there a floating point cmov for the specific X86 condition code?
4143 /// Current x86 isa includes the following FP cmov instructions:
4144 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4145 static bool hasFPCMov(unsigned X86CC) {
4161 /// Returns true if the target can instruction select the
4162 /// specified FP immediate natively. If false, the legalizer will
4163 /// materialize the FP immediate as a load from a constant pool.
4164 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4165 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4166 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4172 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4173 ISD::LoadExtType ExtTy,
4175 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4176 // relocation target a movq or addq instruction: don't let the load shrink.
4177 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4178 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4179 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4180 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4184 /// \brief Returns true if it is beneficial to convert a load of a constant
4185 /// to just the constant itself.
4186 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4188 assert(Ty->isIntegerTy());
4190 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4191 if (BitSize == 0 || BitSize > 64)
4196 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4197 unsigned Index) const {
4198 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4201 return (Index == 0 || Index == ResVT.getVectorNumElements());
4204 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4205 // Speculate cttz only if we can directly use TZCNT.
4206 return Subtarget->hasBMI();
4209 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4210 // Speculate ctlz only if we can directly use LZCNT.
4211 return Subtarget->hasLZCNT();
4214 /// Return true if every element in Mask, beginning
4215 /// from position Pos and ending in Pos+Size is undef.
4216 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4217 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4223 /// Return true if Val is undef or if its value falls within the
4224 /// specified range (L, H].
4225 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4226 return (Val < 0) || (Val >= Low && Val < Hi);
4229 /// Val is either less than zero (undef) or equal to the specified value.
4230 static bool isUndefOrEqual(int Val, int CmpVal) {
4231 return (Val < 0 || Val == CmpVal);
4234 /// Return true if every element in Mask, beginning
4235 /// from position Pos and ending in Pos+Size, falls within the specified
4236 /// sequential range (Low, Low+Size]. or is undef.
4237 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4238 unsigned Pos, unsigned Size, int Low) {
4239 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4240 if (!isUndefOrEqual(Mask[i], Low))
4245 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4246 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4247 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4248 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4249 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4252 // The index should be aligned on a vecWidth-bit boundary.
4254 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4256 MVT VT = N->getSimpleValueType(0);
4257 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4258 bool Result = (Index * ElSize) % vecWidth == 0;
4263 /// Return true if the specified INSERT_SUBVECTOR
4264 /// operand specifies a subvector insert that is suitable for input to
4265 /// insertion of 128 or 256-bit subvectors
4266 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4267 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4268 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4270 // The index should be aligned on a vecWidth-bit boundary.
4272 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4274 MVT VT = N->getSimpleValueType(0);
4275 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4276 bool Result = (Index * ElSize) % vecWidth == 0;
4281 bool X86::isVINSERT128Index(SDNode *N) {
4282 return isVINSERTIndex(N, 128);
4285 bool X86::isVINSERT256Index(SDNode *N) {
4286 return isVINSERTIndex(N, 256);
4289 bool X86::isVEXTRACT128Index(SDNode *N) {
4290 return isVEXTRACTIndex(N, 128);
4293 bool X86::isVEXTRACT256Index(SDNode *N) {
4294 return isVEXTRACTIndex(N, 256);
4297 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4298 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4299 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4300 "Illegal extract subvector for VEXTRACT");
4303 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4305 MVT VecVT = N->getOperand(0).getSimpleValueType();
4306 MVT ElVT = VecVT.getVectorElementType();
4308 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4309 return Index / NumElemsPerChunk;
4312 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4313 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4314 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4315 "Illegal insert subvector for VINSERT");
4318 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4320 MVT VecVT = N->getSimpleValueType(0);
4321 MVT ElVT = VecVT.getVectorElementType();
4323 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4324 return Index / NumElemsPerChunk;
4327 /// Return the appropriate immediate to extract the specified
4328 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4329 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4330 return getExtractVEXTRACTImmediate(N, 128);
4333 /// Return the appropriate immediate to extract the specified
4334 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4335 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4336 return getExtractVEXTRACTImmediate(N, 256);
4339 /// Return the appropriate immediate to insert at the specified
4340 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4341 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4342 return getInsertVINSERTImmediate(N, 128);
4345 /// Return the appropriate immediate to insert at the specified
4346 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4347 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4348 return getInsertVINSERTImmediate(N, 256);
4351 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4352 bool X86::isZeroNode(SDValue Elt) {
4353 return isNullConstant(Elt) || isNullFPConstant(Elt);
4356 // Build a vector of constants
4357 // Use an UNDEF node if MaskElt == -1.
4358 // Spilt 64-bit constants in the 32-bit mode.
4359 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4361 SDLoc dl, bool IsMask = false) {
4363 SmallVector<SDValue, 32> Ops;
4366 MVT ConstVecVT = VT;
4367 unsigned NumElts = VT.getVectorNumElements();
4368 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4369 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4370 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4374 MVT EltVT = ConstVecVT.getVectorElementType();
4375 for (unsigned i = 0; i < NumElts; ++i) {
4376 bool IsUndef = Values[i] < 0 && IsMask;
4377 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4378 DAG.getConstant(Values[i], dl, EltVT);
4379 Ops.push_back(OpNode);
4381 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4382 DAG.getConstant(0, dl, EltVT));
4384 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4386 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4390 /// Returns a vector of specified type with all zero elements.
4391 static SDValue getZeroVector(MVT VT, const X86Subtarget *Subtarget,
4392 SelectionDAG &DAG, SDLoc dl) {
4393 assert(VT.isVector() && "Expected a vector type");
4395 // Always build SSE zero vectors as <4 x i32> bitcasted
4396 // to their dest type. This ensures they get CSE'd.
4398 if (VT.is128BitVector()) { // SSE
4399 if (Subtarget->hasSSE2()) { // SSE2
4400 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4401 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4403 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4404 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4406 } else if (VT.is256BitVector()) { // AVX
4407 if (Subtarget->hasInt256()) { // AVX2
4408 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4409 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4410 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4412 // 256-bit logic and arithmetic instructions in AVX are all
4413 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4414 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4415 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4416 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4418 } else if (VT.is512BitVector()) { // AVX-512
4419 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4420 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4421 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4422 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4423 } else if (VT.getVectorElementType() == MVT::i1) {
4425 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4426 && "Unexpected vector type");
4427 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4428 && "Unexpected vector type");
4429 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4430 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4431 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4433 llvm_unreachable("Unexpected vector type");
4435 return DAG.getBitcast(VT, Vec);
4438 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4439 SelectionDAG &DAG, SDLoc dl,
4440 unsigned vectorWidth) {
4441 assert((vectorWidth == 128 || vectorWidth == 256) &&
4442 "Unsupported vector width");
4443 EVT VT = Vec.getValueType();
4444 EVT ElVT = VT.getVectorElementType();
4445 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4446 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4447 VT.getVectorNumElements()/Factor);
4449 // Extract from UNDEF is UNDEF.
4450 if (Vec.getOpcode() == ISD::UNDEF)
4451 return DAG.getUNDEF(ResultVT);
4453 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4454 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4455 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4457 // This is the index of the first element of the vectorWidth-bit chunk
4458 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4459 IdxVal &= ~(ElemsPerChunk - 1);
4461 // If the input is a buildvector just emit a smaller one.
4462 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4463 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4464 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4466 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4467 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4470 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4471 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4472 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4473 /// instructions or a simple subregister reference. Idx is an index in the
4474 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4475 /// lowering EXTRACT_VECTOR_ELT operations easier.
4476 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4477 SelectionDAG &DAG, SDLoc dl) {
4478 assert((Vec.getValueType().is256BitVector() ||
4479 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4480 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4483 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4484 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4485 SelectionDAG &DAG, SDLoc dl) {
4486 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4487 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4490 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4491 unsigned IdxVal, SelectionDAG &DAG,
4492 SDLoc dl, unsigned vectorWidth) {
4493 assert((vectorWidth == 128 || vectorWidth == 256) &&
4494 "Unsupported vector width");
4495 // Inserting UNDEF is Result
4496 if (Vec.getOpcode() == ISD::UNDEF)
4498 EVT VT = Vec.getValueType();
4499 EVT ElVT = VT.getVectorElementType();
4500 EVT ResultVT = Result.getValueType();
4502 // Insert the relevant vectorWidth bits.
4503 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4504 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4506 // This is the index of the first element of the vectorWidth-bit chunk
4507 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4508 IdxVal &= ~(ElemsPerChunk - 1);
4510 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4511 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4514 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4515 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4516 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4517 /// simple superregister reference. Idx is an index in the 128 bits
4518 /// we want. It need not be aligned to a 128-bit boundary. That makes
4519 /// lowering INSERT_VECTOR_ELT operations easier.
4520 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4521 SelectionDAG &DAG, SDLoc dl) {
4522 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4524 // For insertion into the zero index (low half) of a 256-bit vector, it is
4525 // more efficient to generate a blend with immediate instead of an insert*128.
4526 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4527 // extend the subvector to the size of the result vector. Make sure that
4528 // we are not recursing on that node by checking for undef here.
4529 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4530 Result.getOpcode() != ISD::UNDEF) {
4531 EVT ResultVT = Result.getValueType();
4532 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4533 SDValue Undef = DAG.getUNDEF(ResultVT);
4534 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4537 // The blend instruction, and therefore its mask, depend on the data type.
4538 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4539 if (ScalarType.isFloatingPoint()) {
4540 // Choose either vblendps (float) or vblendpd (double).
4541 unsigned ScalarSize = ScalarType.getSizeInBits();
4542 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4543 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4544 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4545 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4548 const X86Subtarget &Subtarget =
4549 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4551 // AVX2 is needed for 256-bit integer blend support.
4552 // Integers must be cast to 32-bit because there is only vpblendd;
4553 // vpblendw can't be used for this because it has a handicapped mask.
4555 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4556 // is still more efficient than using the wrong domain vinsertf128 that
4557 // will be created by InsertSubVector().
4558 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4560 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4561 Result = DAG.getBitcast(CastVT, Result);
4562 Vec256 = DAG.getBitcast(CastVT, Vec256);
4563 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4564 return DAG.getBitcast(ResultVT, Vec256);
4567 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4570 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4571 SelectionDAG &DAG, SDLoc dl) {
4572 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4573 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4576 /// Insert i1-subvector to i1-vector.
4577 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4580 SDValue Vec = Op.getOperand(0);
4581 SDValue SubVec = Op.getOperand(1);
4582 SDValue Idx = Op.getOperand(2);
4584 if (!isa<ConstantSDNode>(Idx))
4587 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4588 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4591 MVT OpVT = Op.getSimpleValueType();
4592 MVT SubVecVT = SubVec.getSimpleValueType();
4593 unsigned NumElems = OpVT.getVectorNumElements();
4594 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4596 assert(IdxVal + SubVecNumElems <= NumElems &&
4597 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4598 "Unexpected index value in INSERT_SUBVECTOR");
4600 // There are 3 possible cases:
4601 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4602 // 2. Subvector should be inserted in the upper part
4603 // (IdxVal + SubVecNumElems == NumElems)
4604 // 3. Subvector should be inserted in the middle (for example v2i1
4605 // to v16i1, index 2)
4607 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4608 SDValue Undef = DAG.getUNDEF(OpVT);
4609 SDValue WideSubVec =
4610 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4612 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4613 DAG.getConstant(IdxVal, dl, MVT::i8));
4615 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4616 unsigned ShiftLeft = NumElems - SubVecNumElems;
4617 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4618 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4619 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4620 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4621 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4625 // Zero lower bits of the Vec
4626 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4627 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4628 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4629 // Merge them together
4630 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4633 // Simple case when we put subvector in the upper part
4634 if (IdxVal + SubVecNumElems == NumElems) {
4635 // Zero upper bits of the Vec
4636 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4637 DAG.getConstant(IdxVal, dl, MVT::i8));
4638 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4639 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4640 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4641 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4643 // Subvector should be inserted in the middle - use shuffle
4644 SmallVector<int, 64> Mask;
4645 for (unsigned i = 0; i < NumElems; ++i)
4646 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4648 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4651 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4652 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4653 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4654 /// large BUILD_VECTORS.
4655 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4656 unsigned NumElems, SelectionDAG &DAG,
4658 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4659 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4662 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4663 unsigned NumElems, SelectionDAG &DAG,
4665 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4666 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4669 /// Returns a vector of specified type with all bits set.
4670 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4671 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4672 /// Then bitcast to their original type, ensuring they get CSE'd.
4673 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4674 SelectionDAG &DAG, SDLoc dl) {
4675 assert(VT.isVector() && "Expected a vector type");
4677 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4679 if (VT.is512BitVector()) {
4680 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4681 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4682 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4683 } else if (VT.is256BitVector()) {
4684 if (Subtarget->hasInt256()) { // AVX2
4685 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4686 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4688 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4689 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4691 } else if (VT.is128BitVector()) {
4692 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4694 llvm_unreachable("Unexpected vector type");
4696 return DAG.getBitcast(VT, Vec);
4699 /// Returns a vector_shuffle node for an unpackl operation.
4700 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4702 unsigned NumElems = VT.getVectorNumElements();
4703 SmallVector<int, 8> Mask;
4704 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4706 Mask.push_back(i + NumElems);
4708 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4711 /// Returns a vector_shuffle node for an unpackh operation.
4712 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4714 unsigned NumElems = VT.getVectorNumElements();
4715 SmallVector<int, 8> Mask;
4716 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4717 Mask.push_back(i + Half);
4718 Mask.push_back(i + NumElems + Half);
4720 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4723 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4724 /// This produces a shuffle where the low element of V2 is swizzled into the
4725 /// zero/undef vector, landing at element Idx.
4726 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4727 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4729 const X86Subtarget *Subtarget,
4730 SelectionDAG &DAG) {
4731 MVT VT = V2.getSimpleValueType();
4733 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4734 unsigned NumElems = VT.getVectorNumElements();
4735 SmallVector<int, 16> MaskVec;
4736 for (unsigned i = 0; i != NumElems; ++i)
4737 // If this is the insertion idx, put the low elt of V2 here.
4738 MaskVec.push_back(i == Idx ? NumElems : i);
4739 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4742 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4743 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4744 /// uses one source. Note that this will set IsUnary for shuffles which use a
4745 /// single input multiple times, and in those cases it will
4746 /// adjust the mask to only have indices within that single input.
4747 static bool getTargetShuffleMask(SDNode *N, MVT VT, bool AllowSentinelZero,
4748 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4749 unsigned NumElems = VT.getVectorNumElements();
4753 bool IsFakeUnary = false;
4754 switch(N->getOpcode()) {
4755 case X86ISD::BLENDI:
4756 ImmN = N->getOperand(N->getNumOperands()-1);
4757 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4760 ImmN = N->getOperand(N->getNumOperands()-1);
4761 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4762 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4764 case X86ISD::INSERTPS:
4765 ImmN = N->getOperand(N->getNumOperands()-1);
4766 DecodeINSERTPSMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4767 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4769 case X86ISD::UNPCKH:
4770 DecodeUNPCKHMask(VT, Mask);
4771 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4773 case X86ISD::UNPCKL:
4774 DecodeUNPCKLMask(VT, Mask);
4775 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4777 case X86ISD::MOVHLPS:
4778 DecodeMOVHLPSMask(NumElems, Mask);
4779 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4781 case X86ISD::MOVLHPS:
4782 DecodeMOVLHPSMask(NumElems, Mask);
4783 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4785 case X86ISD::PALIGNR:
4786 ImmN = N->getOperand(N->getNumOperands()-1);
4787 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4789 case X86ISD::PSHUFD:
4790 case X86ISD::VPERMILPI:
4791 ImmN = N->getOperand(N->getNumOperands()-1);
4792 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4795 case X86ISD::PSHUFHW:
4796 ImmN = N->getOperand(N->getNumOperands()-1);
4797 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4800 case X86ISD::PSHUFLW:
4801 ImmN = N->getOperand(N->getNumOperands()-1);
4802 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4805 case X86ISD::PSHUFB: {
4807 SDValue MaskNode = N->getOperand(1);
4808 while (MaskNode->getOpcode() == ISD::BITCAST)
4809 MaskNode = MaskNode->getOperand(0);
4811 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4812 // If we have a build-vector, then things are easy.
4813 MVT VT = MaskNode.getSimpleValueType();
4814 assert(VT.isVector() &&
4815 "Can't produce a non-vector with a build_vector!");
4816 if (!VT.isInteger())
4819 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4821 SmallVector<uint64_t, 32> RawMask;
4822 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4823 SDValue Op = MaskNode->getOperand(i);
4824 if (Op->getOpcode() == ISD::UNDEF) {
4825 RawMask.push_back((uint64_t)SM_SentinelUndef);
4828 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4831 APInt MaskElement = CN->getAPIntValue();
4833 // We now have to decode the element which could be any integer size and
4834 // extract each byte of it.
4835 for (int j = 0; j < NumBytesPerElement; ++j) {
4836 // Note that this is x86 and so always little endian: the low byte is
4837 // the first byte of the mask.
4838 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4839 MaskElement = MaskElement.lshr(8);
4842 DecodePSHUFBMask(RawMask, Mask);
4846 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4850 SDValue Ptr = MaskLoad->getBasePtr();
4851 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4852 Ptr->getOpcode() == X86ISD::WrapperRIP)
4853 Ptr = Ptr->getOperand(0);
4855 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4856 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4859 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4860 DecodePSHUFBMask(C, Mask);
4866 case X86ISD::VPERMI:
4867 ImmN = N->getOperand(N->getNumOperands()-1);
4868 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4873 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4875 case X86ISD::VPERM2X128:
4876 ImmN = N->getOperand(N->getNumOperands()-1);
4877 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4878 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4880 case X86ISD::MOVSLDUP:
4881 DecodeMOVSLDUPMask(VT, Mask);
4884 case X86ISD::MOVSHDUP:
4885 DecodeMOVSHDUPMask(VT, Mask);
4888 case X86ISD::MOVDDUP:
4889 DecodeMOVDDUPMask(VT, Mask);
4892 case X86ISD::MOVLHPD:
4893 case X86ISD::MOVLPD:
4894 case X86ISD::MOVLPS:
4895 // Not yet implemented
4897 case X86ISD::VPERMV: {
4899 SDValue MaskNode = N->getOperand(0);
4900 while (MaskNode->getOpcode() == ISD::BITCAST)
4901 MaskNode = MaskNode->getOperand(0);
4903 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4904 SmallVector<uint64_t, 32> RawMask;
4905 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4906 // If we have a build-vector, then things are easy.
4907 assert(MaskNode.getSimpleValueType().isInteger() &&
4908 MaskNode.getSimpleValueType().getVectorNumElements() ==
4909 VT.getVectorNumElements());
4911 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4912 SDValue Op = MaskNode->getOperand(i);
4913 if (Op->getOpcode() == ISD::UNDEF)
4914 RawMask.push_back((uint64_t)SM_SentinelUndef);
4915 else if (isa<ConstantSDNode>(Op)) {
4916 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4917 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4921 DecodeVPERMVMask(RawMask, Mask);
4924 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4925 unsigned NumEltsInMask = MaskNode->getNumOperands();
4926 MaskNode = MaskNode->getOperand(0);
4927 if (auto *CN = dyn_cast<ConstantSDNode>(MaskNode)) {
4928 APInt MaskEltValue = CN->getAPIntValue();
4929 for (unsigned i = 0; i < NumEltsInMask; ++i)
4930 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4931 DecodeVPERMVMask(RawMask, Mask);
4934 // It may be a scalar load
4937 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4941 SDValue Ptr = MaskLoad->getBasePtr();
4942 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4943 Ptr->getOpcode() == X86ISD::WrapperRIP)
4944 Ptr = Ptr->getOperand(0);
4946 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4947 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4950 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4951 DecodeVPERMVMask(C, VT, Mask);
4956 case X86ISD::VPERMV3: {
4958 SDValue MaskNode = N->getOperand(1);
4959 while (MaskNode->getOpcode() == ISD::BITCAST)
4960 MaskNode = MaskNode->getOperand(1);
4962 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4963 // If we have a build-vector, then things are easy.
4964 assert(MaskNode.getSimpleValueType().isInteger() &&
4965 MaskNode.getSimpleValueType().getVectorNumElements() ==
4966 VT.getVectorNumElements());
4968 SmallVector<uint64_t, 32> RawMask;
4969 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4971 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4972 SDValue Op = MaskNode->getOperand(i);
4973 if (Op->getOpcode() == ISD::UNDEF)
4974 RawMask.push_back((uint64_t)SM_SentinelUndef);
4976 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4979 APInt MaskElement = CN->getAPIntValue();
4980 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4983 DecodeVPERMV3Mask(RawMask, Mask);
4987 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4991 SDValue Ptr = MaskLoad->getBasePtr();
4992 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4993 Ptr->getOpcode() == X86ISD::WrapperRIP)
4994 Ptr = Ptr->getOperand(0);
4996 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4997 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
5000 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
5001 DecodeVPERMV3Mask(C, VT, Mask);
5006 default: llvm_unreachable("unknown target shuffle node");
5009 // Empty mask indicates the decode failed.
5013 // Check if we're getting a shuffle mask with zero'd elements.
5014 if (!AllowSentinelZero)
5015 if (std::any_of(Mask.begin(), Mask.end(),
5016 [](int M){ return M == SM_SentinelZero; }))
5019 // If we have a fake unary shuffle, the shuffle mask is spread across two
5020 // inputs that are actually the same node. Re-map the mask to always point
5021 // into the first input.
5024 if (M >= (int)Mask.size())
5030 /// Returns the scalar element that will make up the ith
5031 /// element of the result of the vector shuffle.
5032 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
5035 return SDValue(); // Limit search depth.
5037 SDValue V = SDValue(N, 0);
5038 EVT VT = V.getValueType();
5039 unsigned Opcode = V.getOpcode();
5041 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
5042 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
5043 int Elt = SV->getMaskElt(Index);
5046 return DAG.getUNDEF(VT.getVectorElementType());
5048 unsigned NumElems = VT.getVectorNumElements();
5049 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
5050 : SV->getOperand(1);
5051 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
5054 // Recurse into target specific vector shuffles to find scalars.
5055 if (isTargetShuffle(Opcode)) {
5056 MVT ShufVT = V.getSimpleValueType();
5057 int NumElems = (int)ShufVT.getVectorNumElements();
5058 SmallVector<int, 16> ShuffleMask;
5061 if (!getTargetShuffleMask(N, ShufVT, false, ShuffleMask, IsUnary))
5064 int Elt = ShuffleMask[Index];
5065 if (Elt == SM_SentinelUndef)
5066 return DAG.getUNDEF(ShufVT.getVectorElementType());
5068 assert(0 <= Elt && Elt < (2*NumElems) && "Shuffle index out of range");
5069 SDValue NewV = (Elt < NumElems) ? N->getOperand(0) : N->getOperand(1);
5070 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
5074 // Actual nodes that may contain scalar elements
5075 if (Opcode == ISD::BITCAST) {
5076 V = V.getOperand(0);
5077 EVT SrcVT = V.getValueType();
5078 unsigned NumElems = VT.getVectorNumElements();
5080 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5084 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5085 return (Index == 0) ? V.getOperand(0)
5086 : DAG.getUNDEF(VT.getVectorElementType());
5088 if (V.getOpcode() == ISD::BUILD_VECTOR)
5089 return V.getOperand(Index);
5094 /// Custom lower build_vector of v16i8.
5095 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5096 unsigned NumNonZero, unsigned NumZero,
5098 const X86Subtarget* Subtarget,
5099 const TargetLowering &TLI) {
5107 // SSE4.1 - use PINSRB to insert each byte directly.
5108 if (Subtarget->hasSSE41()) {
5109 for (unsigned i = 0; i < 16; ++i) {
5110 bool isNonZero = (NonZeros & (1 << i)) != 0;
5114 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5116 V = DAG.getUNDEF(MVT::v16i8);
5119 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5120 MVT::v16i8, V, Op.getOperand(i),
5121 DAG.getIntPtrConstant(i, dl));
5128 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5129 for (unsigned i = 0; i < 16; ++i) {
5130 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5131 if (ThisIsNonZero && First) {
5133 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5135 V = DAG.getUNDEF(MVT::v8i16);
5140 SDValue ThisElt, LastElt;
5141 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5142 if (LastIsNonZero) {
5143 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5144 MVT::i16, Op.getOperand(i-1));
5146 if (ThisIsNonZero) {
5147 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5148 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5149 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5151 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5155 if (ThisElt.getNode())
5156 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5157 DAG.getIntPtrConstant(i/2, dl));
5161 return DAG.getBitcast(MVT::v16i8, V);
5164 /// Custom lower build_vector of v8i16.
5165 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5166 unsigned NumNonZero, unsigned NumZero,
5168 const X86Subtarget* Subtarget,
5169 const TargetLowering &TLI) {
5176 for (unsigned i = 0; i < 8; ++i) {
5177 bool isNonZero = (NonZeros & (1 << i)) != 0;
5181 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5183 V = DAG.getUNDEF(MVT::v8i16);
5186 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5187 MVT::v8i16, V, Op.getOperand(i),
5188 DAG.getIntPtrConstant(i, dl));
5195 /// Custom lower build_vector of v4i32 or v4f32.
5196 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5197 const X86Subtarget *Subtarget,
5198 const TargetLowering &TLI) {
5199 // Find all zeroable elements.
5200 std::bitset<4> Zeroable;
5201 for (int i=0; i < 4; ++i) {
5202 SDValue Elt = Op->getOperand(i);
5203 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5205 assert(Zeroable.size() - Zeroable.count() > 1 &&
5206 "We expect at least two non-zero elements!");
5208 // We only know how to deal with build_vector nodes where elements are either
5209 // zeroable or extract_vector_elt with constant index.
5210 SDValue FirstNonZero;
5211 unsigned FirstNonZeroIdx;
5212 for (unsigned i=0; i < 4; ++i) {
5215 SDValue Elt = Op->getOperand(i);
5216 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5217 !isa<ConstantSDNode>(Elt.getOperand(1)))
5219 // Make sure that this node is extracting from a 128-bit vector.
5220 MVT VT = Elt.getOperand(0).getSimpleValueType();
5221 if (!VT.is128BitVector())
5223 if (!FirstNonZero.getNode()) {
5225 FirstNonZeroIdx = i;
5229 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5230 SDValue V1 = FirstNonZero.getOperand(0);
5231 MVT VT = V1.getSimpleValueType();
5233 // See if this build_vector can be lowered as a blend with zero.
5235 unsigned EltMaskIdx, EltIdx;
5237 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5238 if (Zeroable[EltIdx]) {
5239 // The zero vector will be on the right hand side.
5240 Mask[EltIdx] = EltIdx+4;
5244 Elt = Op->getOperand(EltIdx);
5245 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5246 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5247 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5249 Mask[EltIdx] = EltIdx;
5253 // Let the shuffle legalizer deal with blend operations.
5254 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5255 if (V1.getSimpleValueType() != VT)
5256 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5257 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5260 // See if we can lower this build_vector to a INSERTPS.
5261 if (!Subtarget->hasSSE41())
5264 SDValue V2 = Elt.getOperand(0);
5265 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5268 bool CanFold = true;
5269 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5273 SDValue Current = Op->getOperand(i);
5274 SDValue SrcVector = Current->getOperand(0);
5277 CanFold = SrcVector == V1 &&
5278 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5284 assert(V1.getNode() && "Expected at least two non-zero elements!");
5285 if (V1.getSimpleValueType() != MVT::v4f32)
5286 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5287 if (V2.getSimpleValueType() != MVT::v4f32)
5288 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5290 // Ok, we can emit an INSERTPS instruction.
5291 unsigned ZMask = Zeroable.to_ulong();
5293 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5294 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5296 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5297 DAG.getIntPtrConstant(InsertPSMask, DL));
5298 return DAG.getBitcast(VT, Result);
5301 /// Return a vector logical shift node.
5302 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5303 unsigned NumBits, SelectionDAG &DAG,
5304 const TargetLowering &TLI, SDLoc dl) {
5305 assert(VT.is128BitVector() && "Unknown type for VShift");
5306 MVT ShVT = MVT::v2i64;
5307 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5308 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5309 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5310 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5311 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5312 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5316 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5318 // Check if the scalar load can be widened into a vector load. And if
5319 // the address is "base + cst" see if the cst can be "absorbed" into
5320 // the shuffle mask.
5321 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5322 SDValue Ptr = LD->getBasePtr();
5323 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5325 EVT PVT = LD->getValueType(0);
5326 if (PVT != MVT::i32 && PVT != MVT::f32)
5331 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5332 FI = FINode->getIndex();
5334 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5335 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5336 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5337 Offset = Ptr.getConstantOperandVal(1);
5338 Ptr = Ptr.getOperand(0);
5343 // FIXME: 256-bit vector instructions don't require a strict alignment,
5344 // improve this code to support it better.
5345 unsigned RequiredAlign = VT.getSizeInBits()/8;
5346 SDValue Chain = LD->getChain();
5347 // Make sure the stack object alignment is at least 16 or 32.
5348 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5349 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5350 if (MFI->isFixedObjectIndex(FI)) {
5351 // Can't change the alignment. FIXME: It's possible to compute
5352 // the exact stack offset and reference FI + adjust offset instead.
5353 // If someone *really* cares about this. That's the way to implement it.
5356 MFI->setObjectAlignment(FI, RequiredAlign);
5360 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5361 // Ptr + (Offset & ~15).
5364 if ((Offset % RequiredAlign) & 3)
5366 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5369 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5370 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5373 int EltNo = (Offset - StartOffset) >> 2;
5374 unsigned NumElems = VT.getVectorNumElements();
5376 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5377 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5378 LD->getPointerInfo().getWithOffset(StartOffset),
5379 false, false, false, 0);
5381 SmallVector<int, 8> Mask(NumElems, EltNo);
5383 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5389 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5390 /// elements can be replaced by a single large load which has the same value as
5391 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5393 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5395 /// FIXME: we'd also like to handle the case where the last elements are zero
5396 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5397 /// There's even a handy isZeroNode for that purpose.
5398 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5399 SDLoc &DL, SelectionDAG &DAG,
5400 bool isAfterLegalize) {
5401 unsigned NumElems = Elts.size();
5403 LoadSDNode *LDBase = nullptr;
5404 unsigned LastLoadedElt = -1U;
5406 // For each element in the initializer, see if we've found a load or an undef.
5407 // If we don't find an initial load element, or later load elements are
5408 // non-consecutive, bail out.
5409 for (unsigned i = 0; i < NumElems; ++i) {
5410 SDValue Elt = Elts[i];
5411 // Look through a bitcast.
5412 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5413 Elt = Elt.getOperand(0);
5414 if (!Elt.getNode() ||
5415 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5418 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5420 LDBase = cast<LoadSDNode>(Elt.getNode());
5424 if (Elt.getOpcode() == ISD::UNDEF)
5427 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5428 EVT LdVT = Elt.getValueType();
5429 // Each loaded element must be the correct fractional portion of the
5430 // requested vector load.
5431 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5433 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5438 // If we have found an entire vector of loads and undefs, then return a large
5439 // load of the entire vector width starting at the base pointer. If we found
5440 // consecutive loads for the low half, generate a vzext_load node.
5441 if (LastLoadedElt == NumElems - 1) {
5442 assert(LDBase && "Did not find base load for merging consecutive loads");
5443 EVT EltVT = LDBase->getValueType(0);
5444 // Ensure that the input vector size for the merged loads matches the
5445 // cumulative size of the input elements.
5446 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5449 if (isAfterLegalize &&
5450 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5453 SDValue NewLd = SDValue();
5455 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5456 LDBase->getPointerInfo(), LDBase->isVolatile(),
5457 LDBase->isNonTemporal(), LDBase->isInvariant(),
5458 LDBase->getAlignment());
5460 if (LDBase->hasAnyUseOfValue(1)) {
5461 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5463 SDValue(NewLd.getNode(), 1));
5464 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5465 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5466 SDValue(NewLd.getNode(), 1));
5472 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5473 //of a v4i32 / v4f32. It's probably worth generalizing.
5474 EVT EltVT = VT.getVectorElementType();
5475 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5476 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5477 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5478 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5480 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5481 LDBase->getPointerInfo(),
5482 LDBase->getAlignment(),
5483 false/*isVolatile*/, true/*ReadMem*/,
5486 // Make sure the newly-created LOAD is in the same position as LDBase in
5487 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5488 // update uses of LDBase's output chain to use the TokenFactor.
5489 if (LDBase->hasAnyUseOfValue(1)) {
5490 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5491 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5492 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5493 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5494 SDValue(ResNode.getNode(), 1));
5497 return DAG.getBitcast(VT, ResNode);
5502 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5503 /// to generate a splat value for the following cases:
5504 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5505 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5506 /// a scalar load, or a constant.
5507 /// The VBROADCAST node is returned when a pattern is found,
5508 /// or SDValue() otherwise.
5509 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5510 SelectionDAG &DAG) {
5511 // VBROADCAST requires AVX.
5512 // TODO: Splats could be generated for non-AVX CPUs using SSE
5513 // instructions, but there's less potential gain for only 128-bit vectors.
5514 if (!Subtarget->hasAVX())
5517 MVT VT = Op.getSimpleValueType();
5520 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5521 "Unsupported vector type for broadcast.");
5526 switch (Op.getOpcode()) {
5528 // Unknown pattern found.
5531 case ISD::BUILD_VECTOR: {
5532 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5533 BitVector UndefElements;
5534 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5536 // We need a splat of a single value to use broadcast, and it doesn't
5537 // make any sense if the value is only in one element of the vector.
5538 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5542 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5543 Ld.getOpcode() == ISD::ConstantFP);
5545 // Make sure that all of the users of a non-constant load are from the
5546 // BUILD_VECTOR node.
5547 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5552 case ISD::VECTOR_SHUFFLE: {
5553 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5555 // Shuffles must have a splat mask where the first element is
5557 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5560 SDValue Sc = Op.getOperand(0);
5561 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5562 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5564 if (!Subtarget->hasInt256())
5567 // Use the register form of the broadcast instruction available on AVX2.
5568 if (VT.getSizeInBits() >= 256)
5569 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5570 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5573 Ld = Sc.getOperand(0);
5574 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5575 Ld.getOpcode() == ISD::ConstantFP);
5577 // The scalar_to_vector node and the suspected
5578 // load node must have exactly one user.
5579 // Constants may have multiple users.
5581 // AVX-512 has register version of the broadcast
5582 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5583 Ld.getValueType().getSizeInBits() >= 32;
5584 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5591 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5592 bool IsGE256 = (VT.getSizeInBits() >= 256);
5594 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5595 // instruction to save 8 or more bytes of constant pool data.
5596 // TODO: If multiple splats are generated to load the same constant,
5597 // it may be detrimental to overall size. There needs to be a way to detect
5598 // that condition to know if this is truly a size win.
5599 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5601 // Handle broadcasting a single constant scalar from the constant pool
5603 // On Sandybridge (no AVX2), it is still better to load a constant vector
5604 // from the constant pool and not to broadcast it from a scalar.
5605 // But override that restriction when optimizing for size.
5606 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5607 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5608 EVT CVT = Ld.getValueType();
5609 assert(!CVT.isVector() && "Must not broadcast a vector type");
5611 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5612 // For size optimization, also splat v2f64 and v2i64, and for size opt
5613 // with AVX2, also splat i8 and i16.
5614 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5615 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5616 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5617 const Constant *C = nullptr;
5618 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5619 C = CI->getConstantIntValue();
5620 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5621 C = CF->getConstantFPValue();
5623 assert(C && "Invalid constant type");
5625 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5627 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5628 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5630 CVT, dl, DAG.getEntryNode(), CP,
5631 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5632 false, false, Alignment);
5634 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5638 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5640 // Handle AVX2 in-register broadcasts.
5641 if (!IsLoad && Subtarget->hasInt256() &&
5642 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5643 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5645 // The scalar source must be a normal load.
5649 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5650 (Subtarget->hasVLX() && ScalarSize == 64))
5651 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5653 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5654 // double since there is no vbroadcastsd xmm
5655 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5656 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5657 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5660 // Unsupported broadcast.
5664 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5665 /// underlying vector and index.
5667 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5669 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5671 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5672 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5675 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5677 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5679 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5680 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5683 // In this case the vector is the extract_subvector expression and the index
5684 // is 2, as specified by the shuffle.
5685 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5686 SDValue ShuffleVec = SVOp->getOperand(0);
5687 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5688 assert(ShuffleVecVT.getVectorElementType() ==
5689 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5691 int ShuffleIdx = SVOp->getMaskElt(Idx);
5692 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5693 ExtractedFromVec = ShuffleVec;
5699 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5700 MVT VT = Op.getSimpleValueType();
5702 // Skip if insert_vec_elt is not supported.
5703 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5704 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5708 unsigned NumElems = Op.getNumOperands();
5712 SmallVector<unsigned, 4> InsertIndices;
5713 SmallVector<int, 8> Mask(NumElems, -1);
5715 for (unsigned i = 0; i != NumElems; ++i) {
5716 unsigned Opc = Op.getOperand(i).getOpcode();
5718 if (Opc == ISD::UNDEF)
5721 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5722 // Quit if more than 1 elements need inserting.
5723 if (InsertIndices.size() > 1)
5726 InsertIndices.push_back(i);
5730 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5731 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5732 // Quit if non-constant index.
5733 if (!isa<ConstantSDNode>(ExtIdx))
5735 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5737 // Quit if extracted from vector of different type.
5738 if (ExtractedFromVec.getValueType() != VT)
5741 if (!VecIn1.getNode())
5742 VecIn1 = ExtractedFromVec;
5743 else if (VecIn1 != ExtractedFromVec) {
5744 if (!VecIn2.getNode())
5745 VecIn2 = ExtractedFromVec;
5746 else if (VecIn2 != ExtractedFromVec)
5747 // Quit if more than 2 vectors to shuffle
5751 if (ExtractedFromVec == VecIn1)
5753 else if (ExtractedFromVec == VecIn2)
5754 Mask[i] = Idx + NumElems;
5757 if (!VecIn1.getNode())
5760 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5761 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5762 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5763 unsigned Idx = InsertIndices[i];
5764 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5765 DAG.getIntPtrConstant(Idx, DL));
5771 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5772 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5773 Op.getScalarValueSizeInBits() == 1 &&
5774 "Can not convert non-constant vector");
5775 uint64_t Immediate = 0;
5776 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5777 SDValue In = Op.getOperand(idx);
5778 if (In.getOpcode() != ISD::UNDEF)
5779 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5783 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5784 return DAG.getConstant(Immediate, dl, VT);
5786 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5788 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5790 MVT VT = Op.getSimpleValueType();
5791 assert((VT.getVectorElementType() == MVT::i1) &&
5792 "Unexpected type in LowerBUILD_VECTORvXi1!");
5795 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5796 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5797 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5798 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5801 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5802 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5803 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5804 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5807 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5808 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5809 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5810 return DAG.getBitcast(VT, Imm);
5811 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5812 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5813 DAG.getIntPtrConstant(0, dl));
5816 // Vector has one or more non-const elements
5817 uint64_t Immediate = 0;
5818 SmallVector<unsigned, 16> NonConstIdx;
5819 bool IsSplat = true;
5820 bool HasConstElts = false;
5822 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5823 SDValue In = Op.getOperand(idx);
5824 if (In.getOpcode() == ISD::UNDEF)
5826 if (!isa<ConstantSDNode>(In))
5827 NonConstIdx.push_back(idx);
5829 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5830 HasConstElts = true;
5834 else if (In != Op.getOperand(SplatIdx))
5838 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5840 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5841 DAG.getConstant(1, dl, VT),
5842 DAG.getConstant(0, dl, VT));
5844 // insert elements one by one
5848 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5849 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5851 else if (HasConstElts)
5852 Imm = DAG.getConstant(0, dl, VT);
5854 Imm = DAG.getUNDEF(VT);
5855 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5856 DstVec = DAG.getBitcast(VT, Imm);
5858 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5859 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5860 DAG.getIntPtrConstant(0, dl));
5863 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5864 unsigned InsertIdx = NonConstIdx[i];
5865 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5866 Op.getOperand(InsertIdx),
5867 DAG.getIntPtrConstant(InsertIdx, dl));
5872 /// \brief Return true if \p N implements a horizontal binop and return the
5873 /// operands for the horizontal binop into V0 and V1.
5875 /// This is a helper function of LowerToHorizontalOp().
5876 /// This function checks that the build_vector \p N in input implements a
5877 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5878 /// operation to match.
5879 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5880 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5881 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5884 /// This function only analyzes elements of \p N whose indices are
5885 /// in range [BaseIdx, LastIdx).
5886 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5888 unsigned BaseIdx, unsigned LastIdx,
5889 SDValue &V0, SDValue &V1) {
5890 EVT VT = N->getValueType(0);
5892 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5893 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5894 "Invalid Vector in input!");
5896 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5897 bool CanFold = true;
5898 unsigned ExpectedVExtractIdx = BaseIdx;
5899 unsigned NumElts = LastIdx - BaseIdx;
5900 V0 = DAG.getUNDEF(VT);
5901 V1 = DAG.getUNDEF(VT);
5903 // Check if N implements a horizontal binop.
5904 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5905 SDValue Op = N->getOperand(i + BaseIdx);
5908 if (Op->getOpcode() == ISD::UNDEF) {
5909 // Update the expected vector extract index.
5910 if (i * 2 == NumElts)
5911 ExpectedVExtractIdx = BaseIdx;
5912 ExpectedVExtractIdx += 2;
5916 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5921 SDValue Op0 = Op.getOperand(0);
5922 SDValue Op1 = Op.getOperand(1);
5924 // Try to match the following pattern:
5925 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5926 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5927 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5928 Op0.getOperand(0) == Op1.getOperand(0) &&
5929 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5930 isa<ConstantSDNode>(Op1.getOperand(1)));
5934 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5935 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5937 if (i * 2 < NumElts) {
5938 if (V0.getOpcode() == ISD::UNDEF) {
5939 V0 = Op0.getOperand(0);
5940 if (V0.getValueType() != VT)
5944 if (V1.getOpcode() == ISD::UNDEF) {
5945 V1 = Op0.getOperand(0);
5946 if (V1.getValueType() != VT)
5949 if (i * 2 == NumElts)
5950 ExpectedVExtractIdx = BaseIdx;
5953 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5954 if (I0 == ExpectedVExtractIdx)
5955 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5956 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5957 // Try to match the following dag sequence:
5958 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5959 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5963 ExpectedVExtractIdx += 2;
5969 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5970 /// a concat_vector.
5972 /// This is a helper function of LowerToHorizontalOp().
5973 /// This function expects two 256-bit vectors called V0 and V1.
5974 /// At first, each vector is split into two separate 128-bit vectors.
5975 /// Then, the resulting 128-bit vectors are used to implement two
5976 /// horizontal binary operations.
5978 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5980 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5981 /// the two new horizontal binop.
5982 /// When Mode is set, the first horizontal binop dag node would take as input
5983 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5984 /// horizontal binop dag node would take as input the lower 128-bit of V1
5985 /// and the upper 128-bit of V1.
5987 /// HADD V0_LO, V0_HI
5988 /// HADD V1_LO, V1_HI
5990 /// Otherwise, the first horizontal binop dag node takes as input the lower
5991 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5992 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5994 /// HADD V0_LO, V1_LO
5995 /// HADD V0_HI, V1_HI
5997 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5998 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5999 /// the upper 128-bits of the result.
6000 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
6001 SDLoc DL, SelectionDAG &DAG,
6002 unsigned X86Opcode, bool Mode,
6003 bool isUndefLO, bool isUndefHI) {
6004 EVT VT = V0.getValueType();
6005 assert(VT.is256BitVector() && VT == V1.getValueType() &&
6006 "Invalid nodes in input!");
6008 unsigned NumElts = VT.getVectorNumElements();
6009 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
6010 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
6011 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
6012 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
6013 EVT NewVT = V0_LO.getValueType();
6015 SDValue LO = DAG.getUNDEF(NewVT);
6016 SDValue HI = DAG.getUNDEF(NewVT);
6019 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6020 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
6021 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
6022 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
6023 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
6025 // Don't emit a horizontal binop if the result is expected to be UNDEF.
6026 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
6027 V1_LO->getOpcode() != ISD::UNDEF))
6028 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
6030 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
6031 V1_HI->getOpcode() != ISD::UNDEF))
6032 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
6035 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
6038 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
6040 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
6041 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6042 MVT VT = BV->getSimpleValueType(0);
6043 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
6044 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
6048 unsigned NumElts = VT.getVectorNumElements();
6049 SDValue InVec0 = DAG.getUNDEF(VT);
6050 SDValue InVec1 = DAG.getUNDEF(VT);
6052 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
6053 VT == MVT::v2f64) && "build_vector with an invalid type found!");
6055 // Odd-numbered elements in the input build vector are obtained from
6056 // adding two integer/float elements.
6057 // Even-numbered elements in the input build vector are obtained from
6058 // subtracting two integer/float elements.
6059 unsigned ExpectedOpcode = ISD::FSUB;
6060 unsigned NextExpectedOpcode = ISD::FADD;
6061 bool AddFound = false;
6062 bool SubFound = false;
6064 for (unsigned i = 0, e = NumElts; i != e; ++i) {
6065 SDValue Op = BV->getOperand(i);
6067 // Skip 'undef' values.
6068 unsigned Opcode = Op.getOpcode();
6069 if (Opcode == ISD::UNDEF) {
6070 std::swap(ExpectedOpcode, NextExpectedOpcode);
6074 // Early exit if we found an unexpected opcode.
6075 if (Opcode != ExpectedOpcode)
6078 SDValue Op0 = Op.getOperand(0);
6079 SDValue Op1 = Op.getOperand(1);
6081 // Try to match the following pattern:
6082 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6083 // Early exit if we cannot match that sequence.
6084 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6085 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6086 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6087 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6088 Op0.getOperand(1) != Op1.getOperand(1))
6091 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6095 // We found a valid add/sub node. Update the information accordingly.
6101 // Update InVec0 and InVec1.
6102 if (InVec0.getOpcode() == ISD::UNDEF) {
6103 InVec0 = Op0.getOperand(0);
6104 if (InVec0.getSimpleValueType() != VT)
6107 if (InVec1.getOpcode() == ISD::UNDEF) {
6108 InVec1 = Op1.getOperand(0);
6109 if (InVec1.getSimpleValueType() != VT)
6113 // Make sure that operands in input to each add/sub node always
6114 // come from a same pair of vectors.
6115 if (InVec0 != Op0.getOperand(0)) {
6116 if (ExpectedOpcode == ISD::FSUB)
6119 // FADD is commutable. Try to commute the operands
6120 // and then test again.
6121 std::swap(Op0, Op1);
6122 if (InVec0 != Op0.getOperand(0))
6126 if (InVec1 != Op1.getOperand(0))
6129 // Update the pair of expected opcodes.
6130 std::swap(ExpectedOpcode, NextExpectedOpcode);
6133 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6134 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6135 InVec1.getOpcode() != ISD::UNDEF)
6136 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6141 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6142 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6143 const X86Subtarget *Subtarget,
6144 SelectionDAG &DAG) {
6145 MVT VT = BV->getSimpleValueType(0);
6146 unsigned NumElts = VT.getVectorNumElements();
6147 unsigned NumUndefsLO = 0;
6148 unsigned NumUndefsHI = 0;
6149 unsigned Half = NumElts/2;
6151 // Count the number of UNDEF operands in the build_vector in input.
6152 for (unsigned i = 0, e = Half; i != e; ++i)
6153 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6156 for (unsigned i = Half, e = NumElts; i != e; ++i)
6157 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6160 // Early exit if this is either a build_vector of all UNDEFs or all the
6161 // operands but one are UNDEF.
6162 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6166 SDValue InVec0, InVec1;
6167 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6168 // Try to match an SSE3 float HADD/HSUB.
6169 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6170 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6172 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6173 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6174 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6175 // Try to match an SSSE3 integer HADD/HSUB.
6176 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6177 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6179 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6180 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6183 if (!Subtarget->hasAVX())
6186 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6187 // Try to match an AVX horizontal add/sub of packed single/double
6188 // precision floating point values from 256-bit vectors.
6189 SDValue InVec2, InVec3;
6190 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6191 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6192 ((InVec0.getOpcode() == ISD::UNDEF ||
6193 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6194 ((InVec1.getOpcode() == ISD::UNDEF ||
6195 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6196 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6198 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6199 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6200 ((InVec0.getOpcode() == ISD::UNDEF ||
6201 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6202 ((InVec1.getOpcode() == ISD::UNDEF ||
6203 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6204 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6205 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6206 // Try to match an AVX2 horizontal add/sub of signed integers.
6207 SDValue InVec2, InVec3;
6209 bool CanFold = true;
6211 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6212 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6213 ((InVec0.getOpcode() == ISD::UNDEF ||
6214 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6215 ((InVec1.getOpcode() == ISD::UNDEF ||
6216 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6217 X86Opcode = X86ISD::HADD;
6218 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6219 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6220 ((InVec0.getOpcode() == ISD::UNDEF ||
6221 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6222 ((InVec1.getOpcode() == ISD::UNDEF ||
6223 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6224 X86Opcode = X86ISD::HSUB;
6229 // Fold this build_vector into a single horizontal add/sub.
6230 // Do this only if the target has AVX2.
6231 if (Subtarget->hasAVX2())
6232 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6234 // Do not try to expand this build_vector into a pair of horizontal
6235 // add/sub if we can emit a pair of scalar add/sub.
6236 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6239 // Convert this build_vector into a pair of horizontal binop followed by
6241 bool isUndefLO = NumUndefsLO == Half;
6242 bool isUndefHI = NumUndefsHI == Half;
6243 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6244 isUndefLO, isUndefHI);
6248 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6249 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6251 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6252 X86Opcode = X86ISD::HADD;
6253 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6254 X86Opcode = X86ISD::HSUB;
6255 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6256 X86Opcode = X86ISD::FHADD;
6257 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6258 X86Opcode = X86ISD::FHSUB;
6262 // Don't try to expand this build_vector into a pair of horizontal add/sub
6263 // if we can simply emit a pair of scalar add/sub.
6264 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6267 // Convert this build_vector into two horizontal add/sub followed by
6269 bool isUndefLO = NumUndefsLO == Half;
6270 bool isUndefHI = NumUndefsHI == Half;
6271 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6272 isUndefLO, isUndefHI);
6279 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6282 MVT VT = Op.getSimpleValueType();
6283 MVT ExtVT = VT.getVectorElementType();
6284 unsigned NumElems = Op.getNumOperands();
6286 // Generate vectors for predicate vectors.
6287 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6288 return LowerBUILD_VECTORvXi1(Op, DAG);
6290 // Vectors containing all zeros can be matched by pxor and xorps later
6291 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6292 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6293 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6294 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6297 return getZeroVector(VT, Subtarget, DAG, dl);
6300 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6301 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6302 // vpcmpeqd on 256-bit vectors.
6303 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6304 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6307 if (!VT.is512BitVector())
6308 return getOnesVector(VT, Subtarget, DAG, dl);
6311 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6312 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6314 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6315 return HorizontalOp;
6316 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6319 unsigned EVTBits = ExtVT.getSizeInBits();
6321 unsigned NumZero = 0;
6322 unsigned NumNonZero = 0;
6323 uint64_t NonZeros = 0;
6324 bool IsAllConstants = true;
6325 SmallSet<SDValue, 8> Values;
6326 for (unsigned i = 0; i < NumElems; ++i) {
6327 SDValue Elt = Op.getOperand(i);
6328 if (Elt.getOpcode() == ISD::UNDEF)
6331 if (Elt.getOpcode() != ISD::Constant &&
6332 Elt.getOpcode() != ISD::ConstantFP)
6333 IsAllConstants = false;
6334 if (X86::isZeroNode(Elt))
6337 assert(i < sizeof(NonZeros) * 8); // Make sure the shift is within range.
6338 NonZeros |= ((uint64_t)1 << i);
6343 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6344 if (NumNonZero == 0)
6345 return DAG.getUNDEF(VT);
6347 // Special case for single non-zero, non-undef, element.
6348 if (NumNonZero == 1) {
6349 unsigned Idx = countTrailingZeros(NonZeros);
6350 SDValue Item = Op.getOperand(Idx);
6352 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6353 // the value are obviously zero, truncate the value to i32 and do the
6354 // insertion that way. Only do this if the value is non-constant or if the
6355 // value is a constant being inserted into element 0. It is cheaper to do
6356 // a constant pool load than it is to do a movd + shuffle.
6357 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6358 (!IsAllConstants || Idx == 0)) {
6359 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6361 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6362 MVT VecVT = MVT::v4i32;
6364 // Truncate the value (which may itself be a constant) to i32, and
6365 // convert it to a vector with movd (S2V+shuffle to zero extend).
6366 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6367 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6368 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6369 Item, Idx * 2, true, Subtarget, DAG));
6373 // If we have a constant or non-constant insertion into the low element of
6374 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6375 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6376 // depending on what the source datatype is.
6379 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6381 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6382 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6383 if (VT.is512BitVector()) {
6384 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6385 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6386 Item, DAG.getIntPtrConstant(0, dl));
6388 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6389 "Expected an SSE value type!");
6390 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6391 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6392 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6395 // We can't directly insert an i8 or i16 into a vector, so zero extend
6397 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6398 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6399 if (VT.is256BitVector()) {
6400 if (Subtarget->hasAVX()) {
6401 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6402 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6404 // Without AVX, we need to extend to a 128-bit vector and then
6405 // insert into the 256-bit vector.
6406 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6407 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6408 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6411 assert(VT.is128BitVector() && "Expected an SSE value type!");
6412 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6413 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6415 return DAG.getBitcast(VT, Item);
6419 // Is it a vector logical left shift?
6420 if (NumElems == 2 && Idx == 1 &&
6421 X86::isZeroNode(Op.getOperand(0)) &&
6422 !X86::isZeroNode(Op.getOperand(1))) {
6423 unsigned NumBits = VT.getSizeInBits();
6424 return getVShift(true, VT,
6425 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6426 VT, Op.getOperand(1)),
6427 NumBits/2, DAG, *this, dl);
6430 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6433 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6434 // is a non-constant being inserted into an element other than the low one,
6435 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6436 // movd/movss) to move this into the low element, then shuffle it into
6438 if (EVTBits == 32) {
6439 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6440 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6444 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6445 if (Values.size() == 1) {
6446 if (EVTBits == 32) {
6447 // Instead of a shuffle like this:
6448 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6449 // Check if it's possible to issue this instead.
6450 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6451 unsigned Idx = countTrailingZeros(NonZeros);
6452 SDValue Item = Op.getOperand(Idx);
6453 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6454 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6459 // A vector full of immediates; various special cases are already
6460 // handled, so this is best done with a single constant-pool load.
6464 // For AVX-length vectors, see if we can use a vector load to get all of the
6465 // elements, otherwise build the individual 128-bit pieces and use
6466 // shuffles to put them in place.
6467 if (VT.is256BitVector() || VT.is512BitVector()) {
6468 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6470 // Check for a build vector of consecutive loads.
6471 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6474 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6476 // Build both the lower and upper subvector.
6477 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6478 makeArrayRef(&V[0], NumElems/2));
6479 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6480 makeArrayRef(&V[NumElems / 2], NumElems/2));
6482 // Recreate the wider vector with the lower and upper part.
6483 if (VT.is256BitVector())
6484 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6485 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6488 // Let legalizer expand 2-wide build_vectors.
6489 if (EVTBits == 64) {
6490 if (NumNonZero == 1) {
6491 // One half is zero or undef.
6492 unsigned Idx = countTrailingZeros(NonZeros);
6493 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6494 Op.getOperand(Idx));
6495 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6500 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6501 if (EVTBits == 8 && NumElems == 16)
6502 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6503 DAG, Subtarget, *this))
6506 if (EVTBits == 16 && NumElems == 8)
6507 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6508 DAG, Subtarget, *this))
6511 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6512 if (EVTBits == 32 && NumElems == 4)
6513 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6516 // If element VT is == 32 bits, turn it into a number of shuffles.
6517 SmallVector<SDValue, 8> V(NumElems);
6518 if (NumElems == 4 && NumZero > 0) {
6519 for (unsigned i = 0; i < 4; ++i) {
6520 bool isZero = !(NonZeros & (1ULL << i));
6522 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6524 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6527 for (unsigned i = 0; i < 2; ++i) {
6528 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6531 V[i] = V[i*2]; // Must be a zero vector.
6534 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6537 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6540 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6545 bool Reverse1 = (NonZeros & 0x3) == 2;
6546 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6550 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6551 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6553 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6556 if (Values.size() > 1 && VT.is128BitVector()) {
6557 // Check for a build vector of consecutive loads.
6558 for (unsigned i = 0; i < NumElems; ++i)
6559 V[i] = Op.getOperand(i);
6561 // Check for elements which are consecutive loads.
6562 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6565 // Check for a build vector from mostly shuffle plus few inserting.
6566 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6569 // For SSE 4.1, use insertps to put the high elements into the low element.
6570 if (Subtarget->hasSSE41()) {
6572 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6573 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6575 Result = DAG.getUNDEF(VT);
6577 for (unsigned i = 1; i < NumElems; ++i) {
6578 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6579 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6580 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6585 // Otherwise, expand into a number of unpckl*, start by extending each of
6586 // our (non-undef) elements to the full vector width with the element in the
6587 // bottom slot of the vector (which generates no code for SSE).
6588 for (unsigned i = 0; i < NumElems; ++i) {
6589 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6590 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6592 V[i] = DAG.getUNDEF(VT);
6595 // Next, we iteratively mix elements, e.g. for v4f32:
6596 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6597 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6598 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6599 unsigned EltStride = NumElems >> 1;
6600 while (EltStride != 0) {
6601 for (unsigned i = 0; i < EltStride; ++i) {
6602 // If V[i+EltStride] is undef and this is the first round of mixing,
6603 // then it is safe to just drop this shuffle: V[i] is already in the
6604 // right place, the one element (since it's the first round) being
6605 // inserted as undef can be dropped. This isn't safe for successive
6606 // rounds because they will permute elements within both vectors.
6607 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6608 EltStride == NumElems/2)
6611 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6620 // 256-bit AVX can use the vinsertf128 instruction
6621 // to create 256-bit vectors from two other 128-bit ones.
6622 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6624 MVT ResVT = Op.getSimpleValueType();
6626 assert((ResVT.is256BitVector() ||
6627 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6629 SDValue V1 = Op.getOperand(0);
6630 SDValue V2 = Op.getOperand(1);
6631 unsigned NumElems = ResVT.getVectorNumElements();
6632 if (ResVT.is256BitVector())
6633 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6635 if (Op.getNumOperands() == 4) {
6636 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6637 ResVT.getVectorNumElements()/2);
6638 SDValue V3 = Op.getOperand(2);
6639 SDValue V4 = Op.getOperand(3);
6640 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6641 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6643 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6646 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6647 const X86Subtarget *Subtarget,
6648 SelectionDAG & DAG) {
6650 MVT ResVT = Op.getSimpleValueType();
6651 unsigned NumOfOperands = Op.getNumOperands();
6653 assert(isPowerOf2_32(NumOfOperands) &&
6654 "Unexpected number of operands in CONCAT_VECTORS");
6656 SDValue Undef = DAG.getUNDEF(ResVT);
6657 if (NumOfOperands > 2) {
6658 // Specialize the cases when all, or all but one, of the operands are undef.
6659 unsigned NumOfDefinedOps = 0;
6661 for (unsigned i = 0; i < NumOfOperands; i++)
6662 if (!Op.getOperand(i).isUndef()) {
6666 if (NumOfDefinedOps == 0)
6668 if (NumOfDefinedOps == 1) {
6669 unsigned SubVecNumElts =
6670 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6671 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6672 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6673 Op.getOperand(OpIdx), IdxVal);
6676 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6677 ResVT.getVectorNumElements()/2);
6678 SmallVector<SDValue, 2> Ops;
6679 for (unsigned i = 0; i < NumOfOperands/2; i++)
6680 Ops.push_back(Op.getOperand(i));
6681 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6683 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6684 Ops.push_back(Op.getOperand(i));
6685 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6686 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6690 SDValue V1 = Op.getOperand(0);
6691 SDValue V2 = Op.getOperand(1);
6692 unsigned NumElems = ResVT.getVectorNumElements();
6693 assert(V1.getValueType() == V2.getValueType() &&
6694 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6695 "Unexpected operands in CONCAT_VECTORS");
6697 if (ResVT.getSizeInBits() >= 16)
6698 return Op; // The operation is legal with KUNPCK
6700 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6701 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6702 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6703 if (IsZeroV1 && IsZeroV2)
6706 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6708 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6710 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6712 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6714 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6717 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6719 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6720 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6723 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6724 const X86Subtarget *Subtarget,
6725 SelectionDAG &DAG) {
6726 MVT VT = Op.getSimpleValueType();
6727 if (VT.getVectorElementType() == MVT::i1)
6728 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6730 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6731 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6732 Op.getNumOperands() == 4)));
6734 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6735 // from two other 128-bit ones.
6737 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6738 return LowerAVXCONCAT_VECTORS(Op, DAG);
6741 //===----------------------------------------------------------------------===//
6742 // Vector shuffle lowering
6744 // This is an experimental code path for lowering vector shuffles on x86. It is
6745 // designed to handle arbitrary vector shuffles and blends, gracefully
6746 // degrading performance as necessary. It works hard to recognize idiomatic
6747 // shuffles and lower them to optimal instruction patterns without leaving
6748 // a framework that allows reasonably efficient handling of all vector shuffle
6750 //===----------------------------------------------------------------------===//
6752 /// \brief Tiny helper function to identify a no-op mask.
6754 /// This is a somewhat boring predicate function. It checks whether the mask
6755 /// array input, which is assumed to be a single-input shuffle mask of the kind
6756 /// used by the X86 shuffle instructions (not a fully general
6757 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6758 /// in-place shuffle are 'no-op's.
6759 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6760 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6761 if (Mask[i] != -1 && Mask[i] != i)
6766 /// \brief Helper function to classify a mask as a single-input mask.
6768 /// This isn't a generic single-input test because in the vector shuffle
6769 /// lowering we canonicalize single inputs to be the first input operand. This
6770 /// means we can more quickly test for a single input by only checking whether
6771 /// an input from the second operand exists. We also assume that the size of
6772 /// mask corresponds to the size of the input vectors which isn't true in the
6773 /// fully general case.
6774 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6776 if (M >= (int)Mask.size())
6781 /// \brief Test whether there are elements crossing 128-bit lanes in this
6784 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6785 /// and we routinely test for these.
6786 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6787 int LaneSize = 128 / VT.getScalarSizeInBits();
6788 int Size = Mask.size();
6789 for (int i = 0; i < Size; ++i)
6790 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6795 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6797 /// This checks a shuffle mask to see if it is performing the same
6798 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6799 /// that it is also not lane-crossing. It may however involve a blend from the
6800 /// same lane of a second vector.
6802 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6803 /// non-trivial to compute in the face of undef lanes. The representation is
6804 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6805 /// entries from both V1 and V2 inputs to the wider mask.
6807 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6808 SmallVectorImpl<int> &RepeatedMask) {
6809 int LaneSize = 128 / VT.getScalarSizeInBits();
6810 RepeatedMask.resize(LaneSize, -1);
6811 int Size = Mask.size();
6812 for (int i = 0; i < Size; ++i) {
6815 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6816 // This entry crosses lanes, so there is no way to model this shuffle.
6819 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6820 if (RepeatedMask[i % LaneSize] == -1)
6821 // This is the first non-undef entry in this slot of a 128-bit lane.
6822 RepeatedMask[i % LaneSize] =
6823 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6824 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6825 // Found a mismatch with the repeated mask.
6831 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6834 /// This is a fast way to test a shuffle mask against a fixed pattern:
6836 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6838 /// It returns true if the mask is exactly as wide as the argument list, and
6839 /// each element of the mask is either -1 (signifying undef) or the value given
6840 /// in the argument.
6841 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6842 ArrayRef<int> ExpectedMask) {
6843 if (Mask.size() != ExpectedMask.size())
6846 int Size = Mask.size();
6848 // If the values are build vectors, we can look through them to find
6849 // equivalent inputs that make the shuffles equivalent.
6850 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6851 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6853 for (int i = 0; i < Size; ++i)
6854 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6855 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6856 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6857 if (!MaskBV || !ExpectedBV ||
6858 MaskBV->getOperand(Mask[i] % Size) !=
6859 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6866 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6868 /// This helper function produces an 8-bit shuffle immediate corresponding to
6869 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6870 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6873 /// NB: We rely heavily on "undef" masks preserving the input lane.
6874 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6875 SelectionDAG &DAG) {
6876 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6877 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6878 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6879 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6880 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6883 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6884 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6885 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6886 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6887 return DAG.getConstant(Imm, DL, MVT::i8);
6890 /// \brief Compute whether each element of a shuffle is zeroable.
6892 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6893 /// Either it is an undef element in the shuffle mask, the element of the input
6894 /// referenced is undef, or the element of the input referenced is known to be
6895 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6896 /// as many lanes with this technique as possible to simplify the remaining
6898 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6899 SDValue V1, SDValue V2) {
6900 SmallBitVector Zeroable(Mask.size(), false);
6902 while (V1.getOpcode() == ISD::BITCAST)
6903 V1 = V1->getOperand(0);
6904 while (V2.getOpcode() == ISD::BITCAST)
6905 V2 = V2->getOperand(0);
6907 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6908 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6910 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6912 // Handle the easy cases.
6913 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6918 // If this is an index into a build_vector node (which has the same number
6919 // of elements), dig out the input value and use it.
6920 SDValue V = M < Size ? V1 : V2;
6921 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6924 SDValue Input = V.getOperand(M % Size);
6925 // The UNDEF opcode check really should be dead code here, but not quite
6926 // worth asserting on (it isn't invalid, just unexpected).
6927 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6934 // X86 has dedicated unpack instructions that can handle specific blend
6935 // operations: UNPCKH and UNPCKL.
6936 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6937 SDValue V1, SDValue V2,
6938 SelectionDAG &DAG) {
6939 int NumElts = VT.getVectorNumElements();
6940 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6941 SmallVector<int, 8> Unpckl;
6942 SmallVector<int, 8> Unpckh;
6944 for (int i = 0; i < NumElts; ++i) {
6945 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6946 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6947 int HiPos = LoPos + NumEltsInLane / 2;
6948 Unpckl.push_back(LoPos);
6949 Unpckh.push_back(HiPos);
6952 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6953 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6954 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6955 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6957 // Commute and try again.
6958 ShuffleVectorSDNode::commuteMask(Unpckl);
6959 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6960 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6962 ShuffleVectorSDNode::commuteMask(Unpckh);
6963 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6964 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6969 /// \brief Try to emit a bitmask instruction for a shuffle.
6971 /// This handles cases where we can model a blend exactly as a bitmask due to
6972 /// one of the inputs being zeroable.
6973 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6974 SDValue V2, ArrayRef<int> Mask,
6975 SelectionDAG &DAG) {
6976 MVT EltVT = VT.getVectorElementType();
6977 int NumEltBits = EltVT.getSizeInBits();
6978 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6979 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6980 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6982 if (EltVT.isFloatingPoint()) {
6983 Zero = DAG.getBitcast(EltVT, Zero);
6984 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6986 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6987 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6989 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6992 if (Mask[i] % Size != i)
6993 return SDValue(); // Not a blend.
6995 V = Mask[i] < Size ? V1 : V2;
6996 else if (V != (Mask[i] < Size ? V1 : V2))
6997 return SDValue(); // Can only let one input through the mask.
6999 VMaskOps[i] = AllOnes;
7002 return SDValue(); // No non-zeroable elements!
7004 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
7005 V = DAG.getNode(VT.isFloatingPoint()
7006 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
7011 /// \brief Try to emit a blend instruction for a shuffle using bit math.
7013 /// This is used as a fallback approach when first class blend instructions are
7014 /// unavailable. Currently it is only suitable for integer vectors, but could
7015 /// be generalized for floating point vectors if desirable.
7016 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
7017 SDValue V2, ArrayRef<int> Mask,
7018 SelectionDAG &DAG) {
7019 assert(VT.isInteger() && "Only supports integer vector types!");
7020 MVT EltVT = VT.getVectorElementType();
7021 int NumEltBits = EltVT.getSizeInBits();
7022 SDValue Zero = DAG.getConstant(0, DL, EltVT);
7023 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
7025 SmallVector<SDValue, 16> MaskOps;
7026 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7027 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
7028 return SDValue(); // Shuffled input!
7029 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
7032 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
7033 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
7034 // We have to cast V2 around.
7035 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
7036 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
7037 DAG.getBitcast(MaskVT, V1Mask),
7038 DAG.getBitcast(MaskVT, V2)));
7039 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
7042 /// \brief Try to emit a blend instruction for a shuffle.
7044 /// This doesn't do any checks for the availability of instructions for blending
7045 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
7046 /// be matched in the backend with the type given. What it does check for is
7047 /// that the shuffle mask is a blend, or convertible into a blend with zero.
7048 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
7049 SDValue V2, ArrayRef<int> Original,
7050 const X86Subtarget *Subtarget,
7051 SelectionDAG &DAG) {
7052 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
7053 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
7054 SmallVector<int, 8> Mask(Original.begin(), Original.end());
7055 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7056 bool ForceV1Zero = false, ForceV2Zero = false;
7058 // Attempt to generate the binary blend mask. If an input is zero then
7059 // we can use any lane.
7060 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
7061 unsigned BlendMask = 0;
7062 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7068 if (M == i + Size) {
7069 BlendMask |= 1u << i;
7080 BlendMask |= 1u << i;
7085 return SDValue(); // Shuffled input!
7088 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7090 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7092 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7094 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7095 unsigned ScaledMask = 0;
7096 for (int i = 0; i != Size; ++i)
7097 if (BlendMask & (1u << i))
7098 for (int j = 0; j != Scale; ++j)
7099 ScaledMask |= 1u << (i * Scale + j);
7103 switch (VT.SimpleTy) {
7108 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7109 DAG.getConstant(BlendMask, DL, MVT::i8));
7113 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7117 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7118 // that instruction.
7119 if (Subtarget->hasAVX2()) {
7120 // Scale the blend by the number of 32-bit dwords per element.
7121 int Scale = VT.getScalarSizeInBits() / 32;
7122 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7123 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7124 V1 = DAG.getBitcast(BlendVT, V1);
7125 V2 = DAG.getBitcast(BlendVT, V2);
7126 return DAG.getBitcast(
7127 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7128 DAG.getConstant(BlendMask, DL, MVT::i8)));
7132 // For integer shuffles we need to expand the mask and cast the inputs to
7133 // v8i16s prior to blending.
7134 int Scale = 8 / VT.getVectorNumElements();
7135 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7136 V1 = DAG.getBitcast(MVT::v8i16, V1);
7137 V2 = DAG.getBitcast(MVT::v8i16, V2);
7138 return DAG.getBitcast(VT,
7139 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7140 DAG.getConstant(BlendMask, DL, MVT::i8)));
7144 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7145 SmallVector<int, 8> RepeatedMask;
7146 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7147 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7148 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7150 for (int i = 0; i < 8; ++i)
7151 if (RepeatedMask[i] >= 16)
7152 BlendMask |= 1u << i;
7153 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7154 DAG.getConstant(BlendMask, DL, MVT::i8));
7160 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7161 "256-bit byte-blends require AVX2 support!");
7163 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7164 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7167 // Scale the blend by the number of bytes per element.
7168 int Scale = VT.getScalarSizeInBits() / 8;
7170 // This form of blend is always done on bytes. Compute the byte vector
7172 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7174 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7175 // mix of LLVM's code generator and the x86 backend. We tell the code
7176 // generator that boolean values in the elements of an x86 vector register
7177 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7178 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7179 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7180 // of the element (the remaining are ignored) and 0 in that high bit would
7181 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7182 // the LLVM model for boolean values in vector elements gets the relevant
7183 // bit set, it is set backwards and over constrained relative to x86's
7185 SmallVector<SDValue, 32> VSELECTMask;
7186 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7187 for (int j = 0; j < Scale; ++j)
7188 VSELECTMask.push_back(
7189 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7190 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7193 V1 = DAG.getBitcast(BlendVT, V1);
7194 V2 = DAG.getBitcast(BlendVT, V2);
7195 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7196 DAG.getNode(ISD::BUILD_VECTOR, DL,
7197 BlendVT, VSELECTMask),
7202 llvm_unreachable("Not a supported integer vector type!");
7206 /// \brief Try to lower as a blend of elements from two inputs followed by
7207 /// a single-input permutation.
7209 /// This matches the pattern where we can blend elements from two inputs and
7210 /// then reduce the shuffle to a single-input permutation.
7211 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7214 SelectionDAG &DAG) {
7215 // We build up the blend mask while checking whether a blend is a viable way
7216 // to reduce the shuffle.
7217 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7218 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7220 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7224 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7226 if (BlendMask[Mask[i] % Size] == -1)
7227 BlendMask[Mask[i] % Size] = Mask[i];
7228 else if (BlendMask[Mask[i] % Size] != Mask[i])
7229 return SDValue(); // Can't blend in the needed input!
7231 PermuteMask[i] = Mask[i] % Size;
7234 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7235 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7238 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7239 /// blends and permutes.
7241 /// This matches the extremely common pattern for handling combined
7242 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7243 /// operations. It will try to pick the best arrangement of shuffles and
7245 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7249 SelectionDAG &DAG) {
7250 // Shuffle the input elements into the desired positions in V1 and V2 and
7251 // blend them together.
7252 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7253 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7254 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7255 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7256 if (Mask[i] >= 0 && Mask[i] < Size) {
7257 V1Mask[i] = Mask[i];
7259 } else if (Mask[i] >= Size) {
7260 V2Mask[i] = Mask[i] - Size;
7261 BlendMask[i] = i + Size;
7264 // Try to lower with the simpler initial blend strategy unless one of the
7265 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7266 // shuffle may be able to fold with a load or other benefit. However, when
7267 // we'll have to do 2x as many shuffles in order to achieve this, blending
7268 // first is a better strategy.
7269 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7270 if (SDValue BlendPerm =
7271 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7274 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7275 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7276 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7279 /// \brief Try to lower a vector shuffle as a byte rotation.
7281 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7282 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7283 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7284 /// try to generically lower a vector shuffle through such an pattern. It
7285 /// does not check for the profitability of lowering either as PALIGNR or
7286 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7287 /// This matches shuffle vectors that look like:
7289 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7291 /// Essentially it concatenates V1 and V2, shifts right by some number of
7292 /// elements, and takes the low elements as the result. Note that while this is
7293 /// specified as a *right shift* because x86 is little-endian, it is a *left
7294 /// rotate* of the vector lanes.
7295 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7298 const X86Subtarget *Subtarget,
7299 SelectionDAG &DAG) {
7300 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7302 int NumElts = Mask.size();
7303 int NumLanes = VT.getSizeInBits() / 128;
7304 int NumLaneElts = NumElts / NumLanes;
7306 // We need to detect various ways of spelling a rotation:
7307 // [11, 12, 13, 14, 15, 0, 1, 2]
7308 // [-1, 12, 13, 14, -1, -1, 1, -1]
7309 // [-1, -1, -1, -1, -1, -1, 1, 2]
7310 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7311 // [-1, 4, 5, 6, -1, -1, 9, -1]
7312 // [-1, 4, 5, 6, -1, -1, -1, -1]
7315 for (int l = 0; l < NumElts; l += NumLaneElts) {
7316 for (int i = 0; i < NumLaneElts; ++i) {
7317 if (Mask[l + i] == -1)
7319 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7321 // Get the mod-Size index and lane correct it.
7322 int LaneIdx = (Mask[l + i] % NumElts) - l;
7323 // Make sure it was in this lane.
7324 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7327 // Determine where a rotated vector would have started.
7328 int StartIdx = i - LaneIdx;
7330 // The identity rotation isn't interesting, stop.
7333 // If we found the tail of a vector the rotation must be the missing
7334 // front. If we found the head of a vector, it must be how much of the
7336 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7339 Rotation = CandidateRotation;
7340 else if (Rotation != CandidateRotation)
7341 // The rotations don't match, so we can't match this mask.
7344 // Compute which value this mask is pointing at.
7345 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7347 // Compute which of the two target values this index should be assigned
7348 // to. This reflects whether the high elements are remaining or the low
7349 // elements are remaining.
7350 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7352 // Either set up this value if we've not encountered it before, or check
7353 // that it remains consistent.
7356 else if (TargetV != MaskV)
7357 // This may be a rotation, but it pulls from the inputs in some
7358 // unsupported interleaving.
7363 // Check that we successfully analyzed the mask, and normalize the results.
7364 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7365 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7371 // The actual rotate instruction rotates bytes, so we need to scale the
7372 // rotation based on how many bytes are in the vector lane.
7373 int Scale = 16 / NumLaneElts;
7375 // SSSE3 targets can use the palignr instruction.
7376 if (Subtarget->hasSSSE3()) {
7377 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7378 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7379 Lo = DAG.getBitcast(AlignVT, Lo);
7380 Hi = DAG.getBitcast(AlignVT, Hi);
7382 return DAG.getBitcast(
7383 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7384 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7387 assert(VT.is128BitVector() &&
7388 "Rotate-based lowering only supports 128-bit lowering!");
7389 assert(Mask.size() <= 16 &&
7390 "Can shuffle at most 16 bytes in a 128-bit vector!");
7392 // Default SSE2 implementation
7393 int LoByteShift = 16 - Rotation * Scale;
7394 int HiByteShift = Rotation * Scale;
7396 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7397 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7398 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7400 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7401 DAG.getConstant(LoByteShift, DL, MVT::i8));
7402 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7403 DAG.getConstant(HiByteShift, DL, MVT::i8));
7404 return DAG.getBitcast(VT,
7405 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7408 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7410 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7411 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7412 /// matches elements from one of the input vectors shuffled to the left or
7413 /// right with zeroable elements 'shifted in'. It handles both the strictly
7414 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7417 /// PSHL : (little-endian) left bit shift.
7418 /// [ zz, 0, zz, 2 ]
7419 /// [ -1, 4, zz, -1 ]
7420 /// PSRL : (little-endian) right bit shift.
7422 /// [ -1, -1, 7, zz]
7423 /// PSLLDQ : (little-endian) left byte shift
7424 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7425 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7426 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7427 /// PSRLDQ : (little-endian) right byte shift
7428 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7429 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7430 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7431 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7432 SDValue V2, ArrayRef<int> Mask,
7433 SelectionDAG &DAG) {
7434 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7436 int Size = Mask.size();
7437 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7439 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7440 for (int i = 0; i < Size; i += Scale)
7441 for (int j = 0; j < Shift; ++j)
7442 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7448 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7449 for (int i = 0; i != Size; i += Scale) {
7450 unsigned Pos = Left ? i + Shift : i;
7451 unsigned Low = Left ? i : i + Shift;
7452 unsigned Len = Scale - Shift;
7453 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7454 Low + (V == V1 ? 0 : Size)))
7458 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7459 bool ByteShift = ShiftEltBits > 64;
7460 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7461 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7462 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7464 // Normalize the scale for byte shifts to still produce an i64 element
7466 Scale = ByteShift ? Scale / 2 : Scale;
7468 // We need to round trip through the appropriate type for the shift.
7469 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7470 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7471 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7472 "Illegal integer vector type");
7473 V = DAG.getBitcast(ShiftVT, V);
7475 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7476 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7477 return DAG.getBitcast(VT, V);
7480 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7481 // keep doubling the size of the integer elements up to that. We can
7482 // then shift the elements of the integer vector by whole multiples of
7483 // their width within the elements of the larger integer vector. Test each
7484 // multiple to see if we can find a match with the moved element indices
7485 // and that the shifted in elements are all zeroable.
7486 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7487 for (int Shift = 1; Shift != Scale; ++Shift)
7488 for (bool Left : {true, false})
7489 if (CheckZeros(Shift, Scale, Left))
7490 for (SDValue V : {V1, V2})
7491 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7498 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7499 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7500 SDValue V2, ArrayRef<int> Mask,
7501 SelectionDAG &DAG) {
7502 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7503 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7505 int Size = Mask.size();
7506 int HalfSize = Size / 2;
7507 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7509 // Upper half must be undefined.
7510 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7513 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7514 // Remainder of lower half result is zero and upper half is all undef.
7515 auto LowerAsEXTRQ = [&]() {
7516 // Determine the extraction length from the part of the
7517 // lower half that isn't zeroable.
7519 for (; Len > 0; --Len)
7520 if (!Zeroable[Len - 1])
7522 assert(Len > 0 && "Zeroable shuffle mask");
7524 // Attempt to match first Len sequential elements from the lower half.
7527 for (int i = 0; i != Len; ++i) {
7531 SDValue &V = (M < Size ? V1 : V2);
7534 // The extracted elements must start at a valid index and all mask
7535 // elements must be in the lower half.
7536 if (i > M || M >= HalfSize)
7539 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7550 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7551 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7552 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7553 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7554 DAG.getConstant(BitLen, DL, MVT::i8),
7555 DAG.getConstant(BitIdx, DL, MVT::i8));
7558 if (SDValue ExtrQ = LowerAsEXTRQ())
7561 // INSERTQ: Extract lowest Len elements from lower half of second source and
7562 // insert over first source, starting at Idx.
7563 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7564 auto LowerAsInsertQ = [&]() {
7565 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7568 // Attempt to match first source from mask before insertion point.
7569 if (isUndefInRange(Mask, 0, Idx)) {
7571 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7573 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7579 // Extend the extraction length looking to match both the insertion of
7580 // the second source and the remaining elements of the first.
7581 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7586 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7588 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7594 // Match the remaining elements of the lower half.
7595 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7597 } else if ((!Base || (Base == V1)) &&
7598 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7600 } else if ((!Base || (Base == V2)) &&
7601 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7608 // We may not have a base (first source) - this can safely be undefined.
7610 Base = DAG.getUNDEF(VT);
7612 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7613 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7614 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7615 DAG.getConstant(BitLen, DL, MVT::i8),
7616 DAG.getConstant(BitIdx, DL, MVT::i8));
7623 if (SDValue InsertQ = LowerAsInsertQ())
7629 /// \brief Lower a vector shuffle as a zero or any extension.
7631 /// Given a specific number of elements, element bit width, and extension
7632 /// stride, produce either a zero or any extension based on the available
7633 /// features of the subtarget. The extended elements are consecutive and
7634 /// begin and can start from an offseted element index in the input; to
7635 /// avoid excess shuffling the offset must either being in the bottom lane
7636 /// or at the start of a higher lane. All extended elements must be from
7638 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7639 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7640 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7641 assert(Scale > 1 && "Need a scale to extend.");
7642 int EltBits = VT.getScalarSizeInBits();
7643 int NumElements = VT.getVectorNumElements();
7644 int NumEltsPerLane = 128 / EltBits;
7645 int OffsetLane = Offset / NumEltsPerLane;
7646 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7647 "Only 8, 16, and 32 bit elements can be extended.");
7648 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7649 assert(0 <= Offset && "Extension offset must be positive.");
7650 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7651 "Extension offset must be in the first lane or start an upper lane.");
7653 // Check that an index is in same lane as the base offset.
7654 auto SafeOffset = [&](int Idx) {
7655 return OffsetLane == (Idx / NumEltsPerLane);
7658 // Shift along an input so that the offset base moves to the first element.
7659 auto ShuffleOffset = [&](SDValue V) {
7663 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7664 for (int i = 0; i * Scale < NumElements; ++i) {
7665 int SrcIdx = i + Offset;
7666 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7668 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7671 // Found a valid zext mask! Try various lowering strategies based on the
7672 // input type and available ISA extensions.
7673 if (Subtarget->hasSSE41()) {
7674 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7675 // PUNPCK will catch this in a later shuffle match.
7676 if (Offset && Scale == 2 && VT.is128BitVector())
7678 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7679 NumElements / Scale);
7680 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7681 return DAG.getBitcast(VT, InputV);
7684 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7686 // For any extends we can cheat for larger element sizes and use shuffle
7687 // instructions that can fold with a load and/or copy.
7688 if (AnyExt && EltBits == 32) {
7689 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7691 return DAG.getBitcast(
7692 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7693 DAG.getBitcast(MVT::v4i32, InputV),
7694 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7696 if (AnyExt && EltBits == 16 && Scale > 2) {
7697 int PSHUFDMask[4] = {Offset / 2, -1,
7698 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7699 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7700 DAG.getBitcast(MVT::v4i32, InputV),
7701 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7702 int PSHUFWMask[4] = {1, -1, -1, -1};
7703 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7704 return DAG.getBitcast(
7705 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7706 DAG.getBitcast(MVT::v8i16, InputV),
7707 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7710 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7712 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7713 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7714 assert(VT.is128BitVector() && "Unexpected vector width!");
7716 int LoIdx = Offset * EltBits;
7717 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7718 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7719 DAG.getConstant(EltBits, DL, MVT::i8),
7720 DAG.getConstant(LoIdx, DL, MVT::i8)));
7722 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7723 !SafeOffset(Offset + 1))
7724 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7726 int HiIdx = (Offset + 1) * EltBits;
7727 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7728 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7729 DAG.getConstant(EltBits, DL, MVT::i8),
7730 DAG.getConstant(HiIdx, DL, MVT::i8)));
7731 return DAG.getNode(ISD::BITCAST, DL, VT,
7732 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7735 // If this would require more than 2 unpack instructions to expand, use
7736 // pshufb when available. We can only use more than 2 unpack instructions
7737 // when zero extending i8 elements which also makes it easier to use pshufb.
7738 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7739 assert(NumElements == 16 && "Unexpected byte vector width!");
7740 SDValue PSHUFBMask[16];
7741 for (int i = 0; i < 16; ++i) {
7742 int Idx = Offset + (i / Scale);
7743 PSHUFBMask[i] = DAG.getConstant(
7744 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7746 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7747 return DAG.getBitcast(VT,
7748 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7749 DAG.getNode(ISD::BUILD_VECTOR, DL,
7750 MVT::v16i8, PSHUFBMask)));
7753 // If we are extending from an offset, ensure we start on a boundary that
7754 // we can unpack from.
7755 int AlignToUnpack = Offset % (NumElements / Scale);
7756 if (AlignToUnpack) {
7757 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7758 for (int i = AlignToUnpack; i < NumElements; ++i)
7759 ShMask[i - AlignToUnpack] = i;
7760 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7761 Offset -= AlignToUnpack;
7764 // Otherwise emit a sequence of unpacks.
7766 unsigned UnpackLoHi = X86ISD::UNPCKL;
7767 if (Offset >= (NumElements / 2)) {
7768 UnpackLoHi = X86ISD::UNPCKH;
7769 Offset -= (NumElements / 2);
7772 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7773 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7774 : getZeroVector(InputVT, Subtarget, DAG, DL);
7775 InputV = DAG.getBitcast(InputVT, InputV);
7776 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7780 } while (Scale > 1);
7781 return DAG.getBitcast(VT, InputV);
7784 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7786 /// This routine will try to do everything in its power to cleverly lower
7787 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7788 /// check for the profitability of this lowering, it tries to aggressively
7789 /// match this pattern. It will use all of the micro-architectural details it
7790 /// can to emit an efficient lowering. It handles both blends with all-zero
7791 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7792 /// masking out later).
7794 /// The reason we have dedicated lowering for zext-style shuffles is that they
7795 /// are both incredibly common and often quite performance sensitive.
7796 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7797 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7798 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7799 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7801 int Bits = VT.getSizeInBits();
7802 int NumLanes = Bits / 128;
7803 int NumElements = VT.getVectorNumElements();
7804 int NumEltsPerLane = NumElements / NumLanes;
7805 assert(VT.getScalarSizeInBits() <= 32 &&
7806 "Exceeds 32-bit integer zero extension limit");
7807 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7809 // Define a helper function to check a particular ext-scale and lower to it if
7811 auto Lower = [&](int Scale) -> SDValue {
7816 for (int i = 0; i < NumElements; ++i) {
7819 continue; // Valid anywhere but doesn't tell us anything.
7820 if (i % Scale != 0) {
7821 // Each of the extended elements need to be zeroable.
7825 // We no longer are in the anyext case.
7830 // Each of the base elements needs to be consecutive indices into the
7831 // same input vector.
7832 SDValue V = M < NumElements ? V1 : V2;
7833 M = M % NumElements;
7836 Offset = M - (i / Scale);
7837 } else if (InputV != V)
7838 return SDValue(); // Flip-flopping inputs.
7840 // Offset must start in the lowest 128-bit lane or at the start of an
7842 // FIXME: Is it ever worth allowing a negative base offset?
7843 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7844 (Offset % NumEltsPerLane) == 0))
7847 // If we are offsetting, all referenced entries must come from the same
7849 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7852 if ((M % NumElements) != (Offset + (i / Scale)))
7853 return SDValue(); // Non-consecutive strided elements.
7857 // If we fail to find an input, we have a zero-shuffle which should always
7858 // have already been handled.
7859 // FIXME: Maybe handle this here in case during blending we end up with one?
7863 // If we are offsetting, don't extend if we only match a single input, we
7864 // can always do better by using a basic PSHUF or PUNPCK.
7865 if (Offset != 0 && Matches < 2)
7868 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7869 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7872 // The widest scale possible for extending is to a 64-bit integer.
7873 assert(Bits % 64 == 0 &&
7874 "The number of bits in a vector must be divisible by 64 on x86!");
7875 int NumExtElements = Bits / 64;
7877 // Each iteration, try extending the elements half as much, but into twice as
7879 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7880 assert(NumElements % NumExtElements == 0 &&
7881 "The input vector size must be divisible by the extended size.");
7882 if (SDValue V = Lower(NumElements / NumExtElements))
7886 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7890 // Returns one of the source operands if the shuffle can be reduced to a
7891 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7892 auto CanZExtLowHalf = [&]() {
7893 for (int i = NumElements / 2; i != NumElements; ++i)
7896 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7898 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7903 if (SDValue V = CanZExtLowHalf()) {
7904 V = DAG.getBitcast(MVT::v2i64, V);
7905 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7906 return DAG.getBitcast(VT, V);
7909 // No viable ext lowering found.
7913 /// \brief Try to get a scalar value for a specific element of a vector.
7915 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7916 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7917 SelectionDAG &DAG) {
7918 MVT VT = V.getSimpleValueType();
7919 MVT EltVT = VT.getVectorElementType();
7920 while (V.getOpcode() == ISD::BITCAST)
7921 V = V.getOperand(0);
7922 // If the bitcasts shift the element size, we can't extract an equivalent
7924 MVT NewVT = V.getSimpleValueType();
7925 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7928 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7929 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7930 // Ensure the scalar operand is the same size as the destination.
7931 // FIXME: Add support for scalar truncation where possible.
7932 SDValue S = V.getOperand(Idx);
7933 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7934 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7940 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7942 /// This is particularly important because the set of instructions varies
7943 /// significantly based on whether the operand is a load or not.
7944 static bool isShuffleFoldableLoad(SDValue V) {
7945 while (V.getOpcode() == ISD::BITCAST)
7946 V = V.getOperand(0);
7948 return ISD::isNON_EXTLoad(V.getNode());
7951 /// \brief Try to lower insertion of a single element into a zero vector.
7953 /// This is a common pattern that we have especially efficient patterns to lower
7954 /// across all subtarget feature sets.
7955 static SDValue lowerVectorShuffleAsElementInsertion(
7956 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7957 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7958 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7960 MVT EltVT = VT.getVectorElementType();
7962 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7963 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7965 bool IsV1Zeroable = true;
7966 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7967 if (i != V2Index && !Zeroable[i]) {
7968 IsV1Zeroable = false;
7972 // Check for a single input from a SCALAR_TO_VECTOR node.
7973 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7974 // all the smarts here sunk into that routine. However, the current
7975 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7976 // vector shuffle lowering is dead.
7977 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7979 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7980 // We need to zext the scalar if it is smaller than an i32.
7981 V2S = DAG.getBitcast(EltVT, V2S);
7982 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7983 // Using zext to expand a narrow element won't work for non-zero
7988 // Zero-extend directly to i32.
7990 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7992 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7993 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7994 EltVT == MVT::i16) {
7995 // Either not inserting from the low element of the input or the input
7996 // element size is too small to use VZEXT_MOVL to clear the high bits.
8000 if (!IsV1Zeroable) {
8001 // If V1 can't be treated as a zero vector we have fewer options to lower
8002 // this. We can't support integer vectors or non-zero targets cheaply, and
8003 // the V1 elements can't be permuted in any way.
8004 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
8005 if (!VT.isFloatingPoint() || V2Index != 0)
8007 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
8008 V1Mask[V2Index] = -1;
8009 if (!isNoopShuffleMask(V1Mask))
8011 // This is essentially a special case blend operation, but if we have
8012 // general purpose blend operations, they are always faster. Bail and let
8013 // the rest of the lowering handle these as blends.
8014 if (Subtarget->hasSSE41())
8017 // Otherwise, use MOVSD or MOVSS.
8018 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
8019 "Only two types of floating point element types to handle!");
8020 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8024 // This lowering only works for the low element with floating point vectors.
8025 if (VT.isFloatingPoint() && V2Index != 0)
8028 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
8030 V2 = DAG.getBitcast(VT, V2);
8033 // If we have 4 or fewer lanes we can cheaply shuffle the element into
8034 // the desired position. Otherwise it is more efficient to do a vector
8035 // shift left. We know that we can do a vector shift left because all
8036 // the inputs are zero.
8037 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
8038 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
8039 V2Shuffle[V2Index] = 0;
8040 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
8042 V2 = DAG.getBitcast(MVT::v2i64, V2);
8044 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
8045 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
8046 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
8047 DAG.getDataLayout(), VT)));
8048 V2 = DAG.getBitcast(VT, V2);
8054 /// \brief Try to lower broadcast of a single - truncated - integer element,
8055 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
8057 /// This assumes we have AVX2.
8058 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
8060 const X86Subtarget *Subtarget,
8061 SelectionDAG &DAG) {
8062 assert(Subtarget->hasAVX2() &&
8063 "We can only lower integer broadcasts with AVX2!");
8065 EVT EltVT = VT.getVectorElementType();
8066 EVT V0VT = V0.getValueType();
8068 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
8069 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
8071 EVT V0EltVT = V0VT.getVectorElementType();
8072 if (!V0EltVT.isInteger())
8075 const unsigned EltSize = EltVT.getSizeInBits();
8076 const unsigned V0EltSize = V0EltVT.getSizeInBits();
8078 // This is only a truncation if the original element type is larger.
8079 if (V0EltSize <= EltSize)
8082 assert(((V0EltSize % EltSize) == 0) &&
8083 "Scalar type sizes must all be powers of 2 on x86!");
8085 const unsigned V0Opc = V0.getOpcode();
8086 const unsigned Scale = V0EltSize / EltSize;
8087 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8089 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8090 V0Opc != ISD::BUILD_VECTOR)
8093 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8095 // If we're extracting non-least-significant bits, shift so we can truncate.
8096 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8097 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8098 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8099 if (const int OffsetIdx = BroadcastIdx % Scale)
8100 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8101 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8103 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8104 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8107 /// \brief Try to lower broadcast of a single element.
8109 /// For convenience, this code also bundles all of the subtarget feature set
8110 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8111 /// a convenient way to factor it out.
8112 /// FIXME: This is very similar to LowerVectorBroadcast - can we merge them?
8113 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8115 const X86Subtarget *Subtarget,
8116 SelectionDAG &DAG) {
8117 if (!Subtarget->hasAVX())
8119 if (VT.isInteger() && !Subtarget->hasAVX2())
8122 // Check that the mask is a broadcast.
8123 int BroadcastIdx = -1;
8125 if (M >= 0 && BroadcastIdx == -1)
8127 else if (M >= 0 && M != BroadcastIdx)
8130 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8131 "a sorted mask where the broadcast "
8134 // Go up the chain of (vector) values to find a scalar load that we can
8135 // combine with the broadcast.
8137 switch (V.getOpcode()) {
8138 case ISD::CONCAT_VECTORS: {
8139 int OperandSize = Mask.size() / V.getNumOperands();
8140 V = V.getOperand(BroadcastIdx / OperandSize);
8141 BroadcastIdx %= OperandSize;
8145 case ISD::INSERT_SUBVECTOR: {
8146 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8147 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8151 int BeginIdx = (int)ConstantIdx->getZExtValue();
8153 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8154 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8155 BroadcastIdx -= BeginIdx;
8166 // Peek through any bitcast (only useful for loads).
8168 while (BC.getOpcode() == ISD::BITCAST)
8169 BC = BC.getOperand(0);
8171 // Check if this is a broadcast of a scalar. We special case lowering
8172 // for scalars so that we can more effectively fold with loads.
8173 // First, look through bitcast: if the original value has a larger element
8174 // type than the shuffle, the broadcast element is in essence truncated.
8175 // Make that explicit to ease folding.
8176 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8177 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8178 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8179 return TruncBroadcast;
8181 // Also check the simpler case, where we can directly reuse the scalar.
8182 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8183 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8184 V = V.getOperand(BroadcastIdx);
8186 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8187 // Only AVX2 has register broadcasts.
8188 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8190 } else if (MayFoldLoad(BC) && !cast<LoadSDNode>(BC)->isVolatile()) {
8191 // If we are broadcasting a load that is only used by the shuffle
8192 // then we can reduce the vector load to the broadcasted scalar load.
8193 LoadSDNode *Ld = cast<LoadSDNode>(BC);
8194 SDValue BaseAddr = Ld->getOperand(1);
8195 EVT AddrVT = BaseAddr.getValueType();
8196 EVT SVT = VT.getScalarType();
8197 unsigned Offset = BroadcastIdx * SVT.getStoreSize();
8198 SDValue NewAddr = DAG.getNode(
8199 ISD::ADD, DL, AddrVT, BaseAddr,
8200 DAG.getConstant(Offset, DL, AddrVT));
8201 V = DAG.getLoad(SVT, DL, Ld->getChain(), NewAddr,
8202 DAG.getMachineFunction().getMachineMemOperand(
8203 Ld->getMemOperand(), Offset, SVT.getStoreSize()));
8204 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8205 // We can't broadcast from a vector register without AVX2, and we can only
8206 // broadcast from the zero-element of a vector register.
8210 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8213 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8214 // INSERTPS when the V1 elements are already in the correct locations
8215 // because otherwise we can just always use two SHUFPS instructions which
8216 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8217 // perform INSERTPS if a single V1 element is out of place and all V2
8218 // elements are zeroable.
8219 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8221 SelectionDAG &DAG) {
8222 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8223 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8224 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8225 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8227 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8230 int V1DstIndex = -1;
8231 int V2DstIndex = -1;
8232 bool V1UsedInPlace = false;
8234 for (int i = 0; i < 4; ++i) {
8235 // Synthesize a zero mask from the zeroable elements (includes undefs).
8241 // Flag if we use any V1 inputs in place.
8243 V1UsedInPlace = true;
8247 // We can only insert a single non-zeroable element.
8248 if (V1DstIndex != -1 || V2DstIndex != -1)
8252 // V1 input out of place for insertion.
8255 // V2 input for insertion.
8260 // Don't bother if we have no (non-zeroable) element for insertion.
8261 if (V1DstIndex == -1 && V2DstIndex == -1)
8264 // Determine element insertion src/dst indices. The src index is from the
8265 // start of the inserted vector, not the start of the concatenated vector.
8266 unsigned V2SrcIndex = 0;
8267 if (V1DstIndex != -1) {
8268 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8269 // and don't use the original V2 at all.
8270 V2SrcIndex = Mask[V1DstIndex];
8271 V2DstIndex = V1DstIndex;
8274 V2SrcIndex = Mask[V2DstIndex] - 4;
8277 // If no V1 inputs are used in place, then the result is created only from
8278 // the zero mask and the V2 insertion - so remove V1 dependency.
8280 V1 = DAG.getUNDEF(MVT::v4f32);
8282 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8283 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8285 // Insert the V2 element into the desired position.
8287 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8288 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8291 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8292 /// UNPCK instruction.
8294 /// This specifically targets cases where we end up with alternating between
8295 /// the two inputs, and so can permute them into something that feeds a single
8296 /// UNPCK instruction. Note that this routine only targets integer vectors
8297 /// because for floating point vectors we have a generalized SHUFPS lowering
8298 /// strategy that handles everything that doesn't *exactly* match an unpack,
8299 /// making this clever lowering unnecessary.
8300 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8301 SDValue V1, SDValue V2,
8303 SelectionDAG &DAG) {
8304 assert(!VT.isFloatingPoint() &&
8305 "This routine only supports integer vectors.");
8306 assert(!isSingleInputShuffleMask(Mask) &&
8307 "This routine should only be used when blending two inputs.");
8308 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8310 int Size = Mask.size();
8312 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8313 return M >= 0 && M % Size < Size / 2;
8315 int NumHiInputs = std::count_if(
8316 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8318 bool UnpackLo = NumLoInputs >= NumHiInputs;
8320 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8321 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8322 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8324 for (int i = 0; i < Size; ++i) {
8328 // Each element of the unpack contains Scale elements from this mask.
8329 int UnpackIdx = i / Scale;
8331 // We only handle the case where V1 feeds the first slots of the unpack.
8332 // We rely on canonicalization to ensure this is the case.
8333 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8336 // Setup the mask for this input. The indexing is tricky as we have to
8337 // handle the unpack stride.
8338 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8339 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8343 // If we will have to shuffle both inputs to use the unpack, check whether
8344 // we can just unpack first and shuffle the result. If so, skip this unpack.
8345 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8346 !isNoopShuffleMask(V2Mask))
8349 // Shuffle the inputs into place.
8350 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8351 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8353 // Cast the inputs to the type we will use to unpack them.
8354 V1 = DAG.getBitcast(UnpackVT, V1);
8355 V2 = DAG.getBitcast(UnpackVT, V2);
8357 // Unpack the inputs and cast the result back to the desired type.
8358 return DAG.getBitcast(
8359 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8363 // We try each unpack from the largest to the smallest to try and find one
8364 // that fits this mask.
8365 int OrigNumElements = VT.getVectorNumElements();
8366 int OrigScalarSize = VT.getScalarSizeInBits();
8367 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8368 int Scale = ScalarSize / OrigScalarSize;
8369 int NumElements = OrigNumElements / Scale;
8370 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8371 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8375 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8377 if (NumLoInputs == 0 || NumHiInputs == 0) {
8378 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8379 "We have to have *some* inputs!");
8380 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8382 // FIXME: We could consider the total complexity of the permute of each
8383 // possible unpacking. Or at the least we should consider how many
8384 // half-crossings are created.
8385 // FIXME: We could consider commuting the unpacks.
8387 SmallVector<int, 32> PermMask;
8388 PermMask.assign(Size, -1);
8389 for (int i = 0; i < Size; ++i) {
8393 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8396 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8398 return DAG.getVectorShuffle(
8399 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8401 DAG.getUNDEF(VT), PermMask);
8407 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8409 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8410 /// support for floating point shuffles but not integer shuffles. These
8411 /// instructions will incur a domain crossing penalty on some chips though so
8412 /// it is better to avoid lowering through this for integer vectors where
8414 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8415 const X86Subtarget *Subtarget,
8416 SelectionDAG &DAG) {
8418 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8419 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8420 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8421 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8422 ArrayRef<int> Mask = SVOp->getMask();
8423 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8425 if (isSingleInputShuffleMask(Mask)) {
8426 // Use low duplicate instructions for masks that match their pattern.
8427 if (Subtarget->hasSSE3())
8428 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8429 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8431 // Straight shuffle of a single input vector. Simulate this by using the
8432 // single input as both of the "inputs" to this instruction..
8433 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8435 if (Subtarget->hasAVX()) {
8436 // If we have AVX, we can use VPERMILPS which will allow folding a load
8437 // into the shuffle.
8438 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8439 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8442 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8443 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8445 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8446 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8448 // If we have a single input, insert that into V1 if we can do so cheaply.
8449 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8450 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8451 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8453 // Try inverting the insertion since for v2 masks it is easy to do and we
8454 // can't reliably sort the mask one way or the other.
8455 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8456 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8457 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8458 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8462 // Try to use one of the special instruction patterns to handle two common
8463 // blend patterns if a zero-blend above didn't work.
8464 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8465 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8466 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8467 // We can either use a special instruction to load over the low double or
8468 // to move just the low double.
8470 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8472 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8474 if (Subtarget->hasSSE41())
8475 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8479 // Use dedicated unpack instructions for masks that match their pattern.
8481 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8484 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8485 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8486 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8489 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8491 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8492 /// the integer unit to minimize domain crossing penalties. However, for blends
8493 /// it falls back to the floating point shuffle operation with appropriate bit
8495 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8496 const X86Subtarget *Subtarget,
8497 SelectionDAG &DAG) {
8499 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8500 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8501 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8502 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8503 ArrayRef<int> Mask = SVOp->getMask();
8504 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8506 if (isSingleInputShuffleMask(Mask)) {
8507 // Check for being able to broadcast a single element.
8508 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8509 Mask, Subtarget, DAG))
8512 // Straight shuffle of a single input vector. For everything from SSE2
8513 // onward this has a single fast instruction with no scary immediates.
8514 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8515 V1 = DAG.getBitcast(MVT::v4i32, V1);
8516 int WidenedMask[4] = {
8517 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8518 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8519 return DAG.getBitcast(
8521 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8522 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8524 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8525 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8526 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8527 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8529 // If we have a blend of two PACKUS operations an the blend aligns with the
8530 // low and half halves, we can just merge the PACKUS operations. This is
8531 // particularly important as it lets us merge shuffles that this routine itself
8533 auto GetPackNode = [](SDValue V) {
8534 while (V.getOpcode() == ISD::BITCAST)
8535 V = V.getOperand(0);
8537 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8539 if (SDValue V1Pack = GetPackNode(V1))
8540 if (SDValue V2Pack = GetPackNode(V2))
8541 return DAG.getBitcast(MVT::v2i64,
8542 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8543 Mask[0] == 0 ? V1Pack.getOperand(0)
8544 : V1Pack.getOperand(1),
8545 Mask[1] == 2 ? V2Pack.getOperand(0)
8546 : V2Pack.getOperand(1)));
8548 // Try to use shift instructions.
8550 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8553 // When loading a scalar and then shuffling it into a vector we can often do
8554 // the insertion cheaply.
8555 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8556 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8558 // Try inverting the insertion since for v2 masks it is easy to do and we
8559 // can't reliably sort the mask one way or the other.
8560 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8561 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8562 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8565 // We have different paths for blend lowering, but they all must use the
8566 // *exact* same predicate.
8567 bool IsBlendSupported = Subtarget->hasSSE41();
8568 if (IsBlendSupported)
8569 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8573 // Use dedicated unpack instructions for masks that match their pattern.
8575 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8578 // Try to use byte rotation instructions.
8579 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8580 if (Subtarget->hasSSSE3())
8581 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8582 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8585 // If we have direct support for blends, we should lower by decomposing into
8586 // a permute. That will be faster than the domain cross.
8587 if (IsBlendSupported)
8588 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8591 // We implement this with SHUFPD which is pretty lame because it will likely
8592 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8593 // However, all the alternatives are still more cycles and newer chips don't
8594 // have this problem. It would be really nice if x86 had better shuffles here.
8595 V1 = DAG.getBitcast(MVT::v2f64, V1);
8596 V2 = DAG.getBitcast(MVT::v2f64, V2);
8597 return DAG.getBitcast(MVT::v2i64,
8598 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8601 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8603 /// This is used to disable more specialized lowerings when the shufps lowering
8604 /// will happen to be efficient.
8605 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8606 // This routine only handles 128-bit shufps.
8607 assert(Mask.size() == 4 && "Unsupported mask size!");
8609 // To lower with a single SHUFPS we need to have the low half and high half
8610 // each requiring a single input.
8611 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8613 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8619 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8621 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8622 /// It makes no assumptions about whether this is the *best* lowering, it simply
8624 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8625 ArrayRef<int> Mask, SDValue V1,
8626 SDValue V2, SelectionDAG &DAG) {
8627 SDValue LowV = V1, HighV = V2;
8628 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8631 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8633 if (NumV2Elements == 1) {
8635 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8638 // Compute the index adjacent to V2Index and in the same half by toggling
8640 int V2AdjIndex = V2Index ^ 1;
8642 if (Mask[V2AdjIndex] == -1) {
8643 // Handles all the cases where we have a single V2 element and an undef.
8644 // This will only ever happen in the high lanes because we commute the
8645 // vector otherwise.
8647 std::swap(LowV, HighV);
8648 NewMask[V2Index] -= 4;
8650 // Handle the case where the V2 element ends up adjacent to a V1 element.
8651 // To make this work, blend them together as the first step.
8652 int V1Index = V2AdjIndex;
8653 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8654 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8655 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8657 // Now proceed to reconstruct the final blend as we have the necessary
8658 // high or low half formed.
8665 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8666 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8668 } else if (NumV2Elements == 2) {
8669 if (Mask[0] < 4 && Mask[1] < 4) {
8670 // Handle the easy case where we have V1 in the low lanes and V2 in the
8674 } else if (Mask[2] < 4 && Mask[3] < 4) {
8675 // We also handle the reversed case because this utility may get called
8676 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8677 // arrange things in the right direction.
8683 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8684 // trying to place elements directly, just blend them and set up the final
8685 // shuffle to place them.
8687 // The first two blend mask elements are for V1, the second two are for
8689 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8690 Mask[2] < 4 ? Mask[2] : Mask[3],
8691 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8692 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8693 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8694 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8696 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8699 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8700 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8701 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8702 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8705 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8706 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8709 /// \brief Lower 4-lane 32-bit floating point shuffles.
8711 /// Uses instructions exclusively from the floating point unit to minimize
8712 /// domain crossing penalties, as these are sufficient to implement all v4f32
8714 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8715 const X86Subtarget *Subtarget,
8716 SelectionDAG &DAG) {
8718 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8719 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8720 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8721 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8722 ArrayRef<int> Mask = SVOp->getMask();
8723 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8726 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8728 if (NumV2Elements == 0) {
8729 // Check for being able to broadcast a single element.
8730 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8731 Mask, Subtarget, DAG))
8734 // Use even/odd duplicate instructions for masks that match their pattern.
8735 if (Subtarget->hasSSE3()) {
8736 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8737 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8738 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8739 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8742 if (Subtarget->hasAVX()) {
8743 // If we have AVX, we can use VPERMILPS which will allow folding a load
8744 // into the shuffle.
8745 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8746 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8749 // Otherwise, use a straight shuffle of a single input vector. We pass the
8750 // input vector to both operands to simulate this with a SHUFPS.
8751 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8752 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8755 // There are special ways we can lower some single-element blends. However, we
8756 // have custom ways we can lower more complex single-element blends below that
8757 // we defer to if both this and BLENDPS fail to match, so restrict this to
8758 // when the V2 input is targeting element 0 of the mask -- that is the fast
8760 if (NumV2Elements == 1 && Mask[0] >= 4)
8761 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8762 Mask, Subtarget, DAG))
8765 if (Subtarget->hasSSE41()) {
8766 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8770 // Use INSERTPS if we can complete the shuffle efficiently.
8771 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8774 if (!isSingleSHUFPSMask(Mask))
8775 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8776 DL, MVT::v4f32, V1, V2, Mask, DAG))
8780 // Use dedicated unpack instructions for masks that match their pattern.
8782 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8785 // Otherwise fall back to a SHUFPS lowering strategy.
8786 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8789 /// \brief Lower 4-lane i32 vector shuffles.
8791 /// We try to handle these with integer-domain shuffles where we can, but for
8792 /// blends we use the floating point domain blend instructions.
8793 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8794 const X86Subtarget *Subtarget,
8795 SelectionDAG &DAG) {
8797 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8798 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8799 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8800 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8801 ArrayRef<int> Mask = SVOp->getMask();
8802 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8804 // Whenever we can lower this as a zext, that instruction is strictly faster
8805 // than any alternative. It also allows us to fold memory operands into the
8806 // shuffle in many cases.
8807 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8808 Mask, Subtarget, DAG))
8812 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8814 if (NumV2Elements == 0) {
8815 // Check for being able to broadcast a single element.
8816 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8817 Mask, Subtarget, DAG))
8820 // Straight shuffle of a single input vector. For everything from SSE2
8821 // onward this has a single fast instruction with no scary immediates.
8822 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8823 // but we aren't actually going to use the UNPCK instruction because doing
8824 // so prevents folding a load into this instruction or making a copy.
8825 const int UnpackLoMask[] = {0, 0, 1, 1};
8826 const int UnpackHiMask[] = {2, 2, 3, 3};
8827 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8828 Mask = UnpackLoMask;
8829 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8830 Mask = UnpackHiMask;
8832 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8833 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8836 // Try to use shift instructions.
8838 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8841 // There are special ways we can lower some single-element blends.
8842 if (NumV2Elements == 1)
8843 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8844 Mask, Subtarget, DAG))
8847 // We have different paths for blend lowering, but they all must use the
8848 // *exact* same predicate.
8849 bool IsBlendSupported = Subtarget->hasSSE41();
8850 if (IsBlendSupported)
8851 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8855 if (SDValue Masked =
8856 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8859 // Use dedicated unpack instructions for masks that match their pattern.
8861 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8864 // Try to use byte rotation instructions.
8865 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8866 if (Subtarget->hasSSSE3())
8867 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8868 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8871 // If we have direct support for blends, we should lower by decomposing into
8872 // a permute. That will be faster than the domain cross.
8873 if (IsBlendSupported)
8874 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8877 // Try to lower by permuting the inputs into an unpack instruction.
8878 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8882 // We implement this with SHUFPS because it can blend from two vectors.
8883 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8884 // up the inputs, bypassing domain shift penalties that we would encur if we
8885 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8887 return DAG.getBitcast(
8889 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8890 DAG.getBitcast(MVT::v4f32, V2), Mask));
8893 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8894 /// shuffle lowering, and the most complex part.
8896 /// The lowering strategy is to try to form pairs of input lanes which are
8897 /// targeted at the same half of the final vector, and then use a dword shuffle
8898 /// to place them onto the right half, and finally unpack the paired lanes into
8899 /// their final position.
8901 /// The exact breakdown of how to form these dword pairs and align them on the
8902 /// correct sides is really tricky. See the comments within the function for
8903 /// more of the details.
8905 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8906 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8907 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8908 /// vector, form the analogous 128-bit 8-element Mask.
8909 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8910 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8911 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8912 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8913 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8915 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8916 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8917 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8919 SmallVector<int, 4> LoInputs;
8920 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8921 [](int M) { return M >= 0; });
8922 std::sort(LoInputs.begin(), LoInputs.end());
8923 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8924 SmallVector<int, 4> HiInputs;
8925 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8926 [](int M) { return M >= 0; });
8927 std::sort(HiInputs.begin(), HiInputs.end());
8928 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8930 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8931 int NumHToL = LoInputs.size() - NumLToL;
8933 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8934 int NumHToH = HiInputs.size() - NumLToH;
8935 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8936 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8937 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8938 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8940 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8941 // such inputs we can swap two of the dwords across the half mark and end up
8942 // with <=2 inputs to each half in each half. Once there, we can fall through
8943 // to the generic code below. For example:
8945 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8946 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8948 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8949 // and an existing 2-into-2 on the other half. In this case we may have to
8950 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8951 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8952 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8953 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8954 // half than the one we target for fixing) will be fixed when we re-enter this
8955 // path. We will also combine away any sequence of PSHUFD instructions that
8956 // result into a single instruction. Here is an example of the tricky case:
8958 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8959 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8961 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8963 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8964 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8966 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8967 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8969 // The result is fine to be handled by the generic logic.
8970 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8971 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8972 int AOffset, int BOffset) {
8973 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8974 "Must call this with A having 3 or 1 inputs from the A half.");
8975 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8976 "Must call this with B having 1 or 3 inputs from the B half.");
8977 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8978 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8980 bool ThreeAInputs = AToAInputs.size() == 3;
8982 // Compute the index of dword with only one word among the three inputs in
8983 // a half by taking the sum of the half with three inputs and subtracting
8984 // the sum of the actual three inputs. The difference is the remaining
8987 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8988 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8989 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8990 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8991 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8992 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8993 int TripleNonInputIdx =
8994 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8995 TripleDWord = TripleNonInputIdx / 2;
8997 // We use xor with one to compute the adjacent DWord to whichever one the
8999 OneInputDWord = (OneInput / 2) ^ 1;
9001 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
9002 // and BToA inputs. If there is also such a problem with the BToB and AToB
9003 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
9004 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
9005 // is essential that we don't *create* a 3<-1 as then we might oscillate.
9006 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
9007 // Compute how many inputs will be flipped by swapping these DWords. We
9009 // to balance this to ensure we don't form a 3-1 shuffle in the other
9011 int NumFlippedAToBInputs =
9012 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
9013 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
9014 int NumFlippedBToBInputs =
9015 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
9016 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
9017 if ((NumFlippedAToBInputs == 1 &&
9018 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
9019 (NumFlippedBToBInputs == 1 &&
9020 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
9021 // We choose whether to fix the A half or B half based on whether that
9022 // half has zero flipped inputs. At zero, we may not be able to fix it
9023 // with that half. We also bias towards fixing the B half because that
9024 // will more commonly be the high half, and we have to bias one way.
9025 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
9026 ArrayRef<int> Inputs) {
9027 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
9028 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
9029 PinnedIdx ^ 1) != Inputs.end();
9030 // Determine whether the free index is in the flipped dword or the
9031 // unflipped dword based on where the pinned index is. We use this bit
9032 // in an xor to conditionally select the adjacent dword.
9033 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
9034 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
9035 FixFreeIdx) != Inputs.end();
9036 if (IsFixIdxInput == IsFixFreeIdxInput)
9038 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
9039 FixFreeIdx) != Inputs.end();
9040 assert(IsFixIdxInput != IsFixFreeIdxInput &&
9041 "We need to be changing the number of flipped inputs!");
9042 int PSHUFHalfMask[] = {0, 1, 2, 3};
9043 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
9044 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
9046 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
9049 if (M != -1 && M == FixIdx)
9051 else if (M != -1 && M == FixFreeIdx)
9054 if (NumFlippedBToBInputs != 0) {
9056 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
9057 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
9059 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
9060 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
9061 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
9066 int PSHUFDMask[] = {0, 1, 2, 3};
9067 PSHUFDMask[ADWord] = BDWord;
9068 PSHUFDMask[BDWord] = ADWord;
9071 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9072 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9074 // Adjust the mask to match the new locations of A and B.
9076 if (M != -1 && M/2 == ADWord)
9077 M = 2 * BDWord + M % 2;
9078 else if (M != -1 && M/2 == BDWord)
9079 M = 2 * ADWord + M % 2;
9081 // Recurse back into this routine to re-compute state now that this isn't
9082 // a 3 and 1 problem.
9083 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
9086 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
9087 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
9088 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
9089 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
9091 // At this point there are at most two inputs to the low and high halves from
9092 // each half. That means the inputs can always be grouped into dwords and
9093 // those dwords can then be moved to the correct half with a dword shuffle.
9094 // We use at most one low and one high word shuffle to collect these paired
9095 // inputs into dwords, and finally a dword shuffle to place them.
9096 int PSHUFLMask[4] = {-1, -1, -1, -1};
9097 int PSHUFHMask[4] = {-1, -1, -1, -1};
9098 int PSHUFDMask[4] = {-1, -1, -1, -1};
9100 // First fix the masks for all the inputs that are staying in their
9101 // original halves. This will then dictate the targets of the cross-half
9103 auto fixInPlaceInputs =
9104 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9105 MutableArrayRef<int> SourceHalfMask,
9106 MutableArrayRef<int> HalfMask, int HalfOffset) {
9107 if (InPlaceInputs.empty())
9109 if (InPlaceInputs.size() == 1) {
9110 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9111 InPlaceInputs[0] - HalfOffset;
9112 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9115 if (IncomingInputs.empty()) {
9116 // Just fix all of the in place inputs.
9117 for (int Input : InPlaceInputs) {
9118 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9119 PSHUFDMask[Input / 2] = Input / 2;
9124 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9125 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9126 InPlaceInputs[0] - HalfOffset;
9127 // Put the second input next to the first so that they are packed into
9128 // a dword. We find the adjacent index by toggling the low bit.
9129 int AdjIndex = InPlaceInputs[0] ^ 1;
9130 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9131 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9132 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9134 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9135 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9137 // Now gather the cross-half inputs and place them into a free dword of
9138 // their target half.
9139 // FIXME: This operation could almost certainly be simplified dramatically to
9140 // look more like the 3-1 fixing operation.
9141 auto moveInputsToRightHalf = [&PSHUFDMask](
9142 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9143 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9144 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9146 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9147 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9149 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9151 int LowWord = Word & ~1;
9152 int HighWord = Word | 1;
9153 return isWordClobbered(SourceHalfMask, LowWord) ||
9154 isWordClobbered(SourceHalfMask, HighWord);
9157 if (IncomingInputs.empty())
9160 if (ExistingInputs.empty()) {
9161 // Map any dwords with inputs from them into the right half.
9162 for (int Input : IncomingInputs) {
9163 // If the source half mask maps over the inputs, turn those into
9164 // swaps and use the swapped lane.
9165 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9166 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9167 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9168 Input - SourceOffset;
9169 // We have to swap the uses in our half mask in one sweep.
9170 for (int &M : HalfMask)
9171 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9173 else if (M == Input)
9174 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9176 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9177 Input - SourceOffset &&
9178 "Previous placement doesn't match!");
9180 // Note that this correctly re-maps both when we do a swap and when
9181 // we observe the other side of the swap above. We rely on that to
9182 // avoid swapping the members of the input list directly.
9183 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9186 // Map the input's dword into the correct half.
9187 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9188 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9190 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9192 "Previous placement doesn't match!");
9195 // And just directly shift any other-half mask elements to be same-half
9196 // as we will have mirrored the dword containing the element into the
9197 // same position within that half.
9198 for (int &M : HalfMask)
9199 if (M >= SourceOffset && M < SourceOffset + 4) {
9200 M = M - SourceOffset + DestOffset;
9201 assert(M >= 0 && "This should never wrap below zero!");
9206 // Ensure we have the input in a viable dword of its current half. This
9207 // is particularly tricky because the original position may be clobbered
9208 // by inputs being moved and *staying* in that half.
9209 if (IncomingInputs.size() == 1) {
9210 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9211 int InputFixed = std::find(std::begin(SourceHalfMask),
9212 std::end(SourceHalfMask), -1) -
9213 std::begin(SourceHalfMask) + SourceOffset;
9214 SourceHalfMask[InputFixed - SourceOffset] =
9215 IncomingInputs[0] - SourceOffset;
9216 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9218 IncomingInputs[0] = InputFixed;
9220 } else if (IncomingInputs.size() == 2) {
9221 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9222 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9223 // We have two non-adjacent or clobbered inputs we need to extract from
9224 // the source half. To do this, we need to map them into some adjacent
9225 // dword slot in the source mask.
9226 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9227 IncomingInputs[1] - SourceOffset};
9229 // If there is a free slot in the source half mask adjacent to one of
9230 // the inputs, place the other input in it. We use (Index XOR 1) to
9231 // compute an adjacent index.
9232 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9233 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9234 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9235 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9236 InputsFixed[1] = InputsFixed[0] ^ 1;
9237 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9238 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9239 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9240 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9241 InputsFixed[0] = InputsFixed[1] ^ 1;
9242 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9243 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9244 // The two inputs are in the same DWord but it is clobbered and the
9245 // adjacent DWord isn't used at all. Move both inputs to the free
9247 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9248 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9249 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9250 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9252 // The only way we hit this point is if there is no clobbering
9253 // (because there are no off-half inputs to this half) and there is no
9254 // free slot adjacent to one of the inputs. In this case, we have to
9255 // swap an input with a non-input.
9256 for (int i = 0; i < 4; ++i)
9257 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9258 "We can't handle any clobbers here!");
9259 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9260 "Cannot have adjacent inputs here!");
9262 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9263 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9265 // We also have to update the final source mask in this case because
9266 // it may need to undo the above swap.
9267 for (int &M : FinalSourceHalfMask)
9268 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9269 M = InputsFixed[1] + SourceOffset;
9270 else if (M == InputsFixed[1] + SourceOffset)
9271 M = (InputsFixed[0] ^ 1) + SourceOffset;
9273 InputsFixed[1] = InputsFixed[0] ^ 1;
9276 // Point everything at the fixed inputs.
9277 for (int &M : HalfMask)
9278 if (M == IncomingInputs[0])
9279 M = InputsFixed[0] + SourceOffset;
9280 else if (M == IncomingInputs[1])
9281 M = InputsFixed[1] + SourceOffset;
9283 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9284 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9287 llvm_unreachable("Unhandled input size!");
9290 // Now hoist the DWord down to the right half.
9291 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9292 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9293 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9294 for (int &M : HalfMask)
9295 for (int Input : IncomingInputs)
9297 M = FreeDWord * 2 + Input % 2;
9299 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9300 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9301 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9302 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9304 // Now enact all the shuffles we've computed to move the inputs into their
9306 if (!isNoopShuffleMask(PSHUFLMask))
9307 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9308 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9309 if (!isNoopShuffleMask(PSHUFHMask))
9310 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9311 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9312 if (!isNoopShuffleMask(PSHUFDMask))
9315 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9316 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9318 // At this point, each half should contain all its inputs, and we can then
9319 // just shuffle them into their final position.
9320 assert(std::count_if(LoMask.begin(), LoMask.end(),
9321 [](int M) { return M >= 4; }) == 0 &&
9322 "Failed to lift all the high half inputs to the low mask!");
9323 assert(std::count_if(HiMask.begin(), HiMask.end(),
9324 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9325 "Failed to lift all the low half inputs to the high mask!");
9327 // Do a half shuffle for the low mask.
9328 if (!isNoopShuffleMask(LoMask))
9329 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9330 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9332 // Do a half shuffle with the high mask after shifting its values down.
9333 for (int &M : HiMask)
9336 if (!isNoopShuffleMask(HiMask))
9337 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9338 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9343 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9344 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9345 SDValue V2, ArrayRef<int> Mask,
9346 SelectionDAG &DAG, bool &V1InUse,
9348 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9354 int Size = Mask.size();
9355 int Scale = 16 / Size;
9356 for (int i = 0; i < 16; ++i) {
9357 if (Mask[i / Scale] == -1) {
9358 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9360 const int ZeroMask = 0x80;
9361 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9363 int V2Idx = Mask[i / Scale] < Size
9365 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9366 if (Zeroable[i / Scale])
9367 V1Idx = V2Idx = ZeroMask;
9368 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9369 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9370 V1InUse |= (ZeroMask != V1Idx);
9371 V2InUse |= (ZeroMask != V2Idx);
9376 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9377 DAG.getBitcast(MVT::v16i8, V1),
9378 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9380 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9381 DAG.getBitcast(MVT::v16i8, V2),
9382 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9384 // If we need shuffled inputs from both, blend the two.
9386 if (V1InUse && V2InUse)
9387 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9389 V = V1InUse ? V1 : V2;
9391 // Cast the result back to the correct type.
9392 return DAG.getBitcast(VT, V);
9395 /// \brief Generic lowering of 8-lane i16 shuffles.
9397 /// This handles both single-input shuffles and combined shuffle/blends with
9398 /// two inputs. The single input shuffles are immediately delegated to
9399 /// a dedicated lowering routine.
9401 /// The blends are lowered in one of three fundamental ways. If there are few
9402 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9403 /// of the input is significantly cheaper when lowered as an interleaving of
9404 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9405 /// halves of the inputs separately (making them have relatively few inputs)
9406 /// and then concatenate them.
9407 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9408 const X86Subtarget *Subtarget,
9409 SelectionDAG &DAG) {
9411 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9412 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9413 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9414 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9415 ArrayRef<int> OrigMask = SVOp->getMask();
9416 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9417 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9418 MutableArrayRef<int> Mask(MaskStorage);
9420 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9422 // Whenever we can lower this as a zext, that instruction is strictly faster
9423 // than any alternative.
9424 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9425 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9428 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9430 auto isV2 = [](int M) { return M >= 8; };
9432 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9434 if (NumV2Inputs == 0) {
9435 // Check for being able to broadcast a single element.
9436 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9437 Mask, Subtarget, DAG))
9440 // Try to use shift instructions.
9442 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9445 // Use dedicated unpack instructions for masks that match their pattern.
9447 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9450 // Try to use byte rotation instructions.
9451 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9452 Mask, Subtarget, DAG))
9455 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9459 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9460 "All single-input shuffles should be canonicalized to be V1-input "
9463 // Try to use shift instructions.
9465 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9468 // See if we can use SSE4A Extraction / Insertion.
9469 if (Subtarget->hasSSE4A())
9470 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9473 // There are special ways we can lower some single-element blends.
9474 if (NumV2Inputs == 1)
9475 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9476 Mask, Subtarget, DAG))
9479 // We have different paths for blend lowering, but they all must use the
9480 // *exact* same predicate.
9481 bool IsBlendSupported = Subtarget->hasSSE41();
9482 if (IsBlendSupported)
9483 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9487 if (SDValue Masked =
9488 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9491 // Use dedicated unpack instructions for masks that match their pattern.
9493 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9496 // Try to use byte rotation instructions.
9497 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9498 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9501 if (SDValue BitBlend =
9502 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9505 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9509 // If we can't directly blend but can use PSHUFB, that will be better as it
9510 // can both shuffle and set up the inefficient blend.
9511 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9512 bool V1InUse, V2InUse;
9513 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9517 // We can always bit-blend if we have to so the fallback strategy is to
9518 // decompose into single-input permutes and blends.
9519 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9523 /// \brief Check whether a compaction lowering can be done by dropping even
9524 /// elements and compute how many times even elements must be dropped.
9526 /// This handles shuffles which take every Nth element where N is a power of
9527 /// two. Example shuffle masks:
9529 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9530 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9531 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9532 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9533 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9534 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9536 /// Any of these lanes can of course be undef.
9538 /// This routine only supports N <= 3.
9539 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9542 /// \returns N above, or the number of times even elements must be dropped if
9543 /// there is such a number. Otherwise returns zero.
9544 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9545 // Figure out whether we're looping over two inputs or just one.
9546 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9548 // The modulus for the shuffle vector entries is based on whether this is
9549 // a single input or not.
9550 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9551 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9552 "We should only be called with masks with a power-of-2 size!");
9554 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9556 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9557 // and 2^3 simultaneously. This is because we may have ambiguity with
9558 // partially undef inputs.
9559 bool ViableForN[3] = {true, true, true};
9561 for (int i = 0, e = Mask.size(); i < e; ++i) {
9562 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9567 bool IsAnyViable = false;
9568 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9569 if (ViableForN[j]) {
9572 // The shuffle mask must be equal to (i * 2^N) % M.
9573 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9576 ViableForN[j] = false;
9578 // Early exit if we exhaust the possible powers of two.
9583 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9587 // Return 0 as there is no viable power of two.
9591 /// \brief Generic lowering of v16i8 shuffles.
9593 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9594 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9595 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9596 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9598 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9599 const X86Subtarget *Subtarget,
9600 SelectionDAG &DAG) {
9602 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9603 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9604 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9605 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9606 ArrayRef<int> Mask = SVOp->getMask();
9607 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9609 // Try to use shift instructions.
9611 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9614 // Try to use byte rotation instructions.
9615 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9616 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9619 // Try to use a zext lowering.
9620 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9621 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9624 // See if we can use SSE4A Extraction / Insertion.
9625 if (Subtarget->hasSSE4A())
9626 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9630 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9632 // For single-input shuffles, there are some nicer lowering tricks we can use.
9633 if (NumV2Elements == 0) {
9634 // Check for being able to broadcast a single element.
9635 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9636 Mask, Subtarget, DAG))
9639 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9640 // Notably, this handles splat and partial-splat shuffles more efficiently.
9641 // However, it only makes sense if the pre-duplication shuffle simplifies
9642 // things significantly. Currently, this means we need to be able to
9643 // express the pre-duplication shuffle as an i16 shuffle.
9645 // FIXME: We should check for other patterns which can be widened into an
9646 // i16 shuffle as well.
9647 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9648 for (int i = 0; i < 16; i += 2)
9649 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9654 auto tryToWidenViaDuplication = [&]() -> SDValue {
9655 if (!canWidenViaDuplication(Mask))
9657 SmallVector<int, 4> LoInputs;
9658 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9659 [](int M) { return M >= 0 && M < 8; });
9660 std::sort(LoInputs.begin(), LoInputs.end());
9661 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9663 SmallVector<int, 4> HiInputs;
9664 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9665 [](int M) { return M >= 8; });
9666 std::sort(HiInputs.begin(), HiInputs.end());
9667 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9670 bool TargetLo = LoInputs.size() >= HiInputs.size();
9671 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9672 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9674 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9675 SmallDenseMap<int, int, 8> LaneMap;
9676 for (int I : InPlaceInputs) {
9677 PreDupI16Shuffle[I/2] = I/2;
9680 int j = TargetLo ? 0 : 4, je = j + 4;
9681 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9682 // Check if j is already a shuffle of this input. This happens when
9683 // there are two adjacent bytes after we move the low one.
9684 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9685 // If we haven't yet mapped the input, search for a slot into which
9687 while (j < je && PreDupI16Shuffle[j] != -1)
9691 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9694 // Map this input with the i16 shuffle.
9695 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9698 // Update the lane map based on the mapping we ended up with.
9699 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9701 V1 = DAG.getBitcast(
9703 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9704 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9706 // Unpack the bytes to form the i16s that will be shuffled into place.
9707 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9708 MVT::v16i8, V1, V1);
9710 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9711 for (int i = 0; i < 16; ++i)
9712 if (Mask[i] != -1) {
9713 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9714 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9715 if (PostDupI16Shuffle[i / 2] == -1)
9716 PostDupI16Shuffle[i / 2] = MappedMask;
9718 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9719 "Conflicting entrties in the original shuffle!");
9721 return DAG.getBitcast(
9723 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9724 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9726 if (SDValue V = tryToWidenViaDuplication())
9730 if (SDValue Masked =
9731 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9734 // Use dedicated unpack instructions for masks that match their pattern.
9736 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9739 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9740 // with PSHUFB. It is important to do this before we attempt to generate any
9741 // blends but after all of the single-input lowerings. If the single input
9742 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9743 // want to preserve that and we can DAG combine any longer sequences into
9744 // a PSHUFB in the end. But once we start blending from multiple inputs,
9745 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9746 // and there are *very* few patterns that would actually be faster than the
9747 // PSHUFB approach because of its ability to zero lanes.
9749 // FIXME: The only exceptions to the above are blends which are exact
9750 // interleavings with direct instructions supporting them. We currently don't
9751 // handle those well here.
9752 if (Subtarget->hasSSSE3()) {
9753 bool V1InUse = false;
9754 bool V2InUse = false;
9756 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9757 DAG, V1InUse, V2InUse);
9759 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9760 // do so. This avoids using them to handle blends-with-zero which is
9761 // important as a single pshufb is significantly faster for that.
9762 if (V1InUse && V2InUse) {
9763 if (Subtarget->hasSSE41())
9764 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9765 Mask, Subtarget, DAG))
9768 // We can use an unpack to do the blending rather than an or in some
9769 // cases. Even though the or may be (very minorly) more efficient, we
9770 // preference this lowering because there are common cases where part of
9771 // the complexity of the shuffles goes away when we do the final blend as
9773 // FIXME: It might be worth trying to detect if the unpack-feeding
9774 // shuffles will both be pshufb, in which case we shouldn't bother with
9776 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9777 DL, MVT::v16i8, V1, V2, Mask, DAG))
9784 // There are special ways we can lower some single-element blends.
9785 if (NumV2Elements == 1)
9786 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9787 Mask, Subtarget, DAG))
9790 if (SDValue BitBlend =
9791 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9794 // Check whether a compaction lowering can be done. This handles shuffles
9795 // which take every Nth element for some even N. See the helper function for
9798 // We special case these as they can be particularly efficiently handled with
9799 // the PACKUSB instruction on x86 and they show up in common patterns of
9800 // rearranging bytes to truncate wide elements.
9801 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9802 // NumEvenDrops is the power of two stride of the elements. Another way of
9803 // thinking about it is that we need to drop the even elements this many
9804 // times to get the original input.
9805 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9807 // First we need to zero all the dropped bytes.
9808 assert(NumEvenDrops <= 3 &&
9809 "No support for dropping even elements more than 3 times.");
9810 // We use the mask type to pick which bytes are preserved based on how many
9811 // elements are dropped.
9812 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9813 SDValue ByteClearMask = DAG.getBitcast(
9814 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9815 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9817 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9819 // Now pack things back together.
9820 V1 = DAG.getBitcast(MVT::v8i16, V1);
9821 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9822 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9823 for (int i = 1; i < NumEvenDrops; ++i) {
9824 Result = DAG.getBitcast(MVT::v8i16, Result);
9825 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9831 // Handle multi-input cases by blending single-input shuffles.
9832 if (NumV2Elements > 0)
9833 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9836 // The fallback path for single-input shuffles widens this into two v8i16
9837 // vectors with unpacks, shuffles those, and then pulls them back together
9841 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9842 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9843 for (int i = 0; i < 16; ++i)
9845 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9847 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9849 SDValue VLoHalf, VHiHalf;
9850 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9851 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9853 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9854 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9855 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9856 [](int M) { return M >= 0 && M % 2 == 1; })) {
9857 // Use a mask to drop the high bytes.
9858 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9859 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9860 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9862 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9863 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9865 // Squash the masks to point directly into VLoHalf.
9866 for (int &M : LoBlendMask)
9869 for (int &M : HiBlendMask)
9873 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9874 // VHiHalf so that we can blend them as i16s.
9875 VLoHalf = DAG.getBitcast(
9876 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9877 VHiHalf = DAG.getBitcast(
9878 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9881 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9882 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9884 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9887 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9889 /// This routine breaks down the specific type of 128-bit shuffle and
9890 /// dispatches to the lowering routines accordingly.
9891 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9892 MVT VT, const X86Subtarget *Subtarget,
9893 SelectionDAG &DAG) {
9894 switch (VT.SimpleTy) {
9896 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9898 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9900 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9902 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9904 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9906 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9909 llvm_unreachable("Unimplemented!");
9913 /// \brief Helper function to test whether a shuffle mask could be
9914 /// simplified by widening the elements being shuffled.
9916 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9917 /// leaves it in an unspecified state.
9919 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9920 /// shuffle masks. The latter have the special property of a '-2' representing
9921 /// a zero-ed lane of a vector.
9922 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9923 SmallVectorImpl<int> &WidenedMask) {
9924 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9925 // If both elements are undef, its trivial.
9926 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9927 WidenedMask.push_back(SM_SentinelUndef);
9931 // Check for an undef mask and a mask value properly aligned to fit with
9932 // a pair of values. If we find such a case, use the non-undef mask's value.
9933 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9934 WidenedMask.push_back(Mask[i + 1] / 2);
9937 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9938 WidenedMask.push_back(Mask[i] / 2);
9942 // When zeroing, we need to spread the zeroing across both lanes to widen.
9943 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9944 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9945 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9946 WidenedMask.push_back(SM_SentinelZero);
9952 // Finally check if the two mask values are adjacent and aligned with
9954 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9955 WidenedMask.push_back(Mask[i] / 2);
9959 // Otherwise we can't safely widen the elements used in this shuffle.
9962 assert(WidenedMask.size() == Mask.size() / 2 &&
9963 "Incorrect size of mask after widening the elements!");
9968 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9970 /// This routine just extracts two subvectors, shuffles them independently, and
9971 /// then concatenates them back together. This should work effectively with all
9972 /// AVX vector shuffle types.
9973 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9974 SDValue V2, ArrayRef<int> Mask,
9975 SelectionDAG &DAG) {
9976 assert(VT.getSizeInBits() >= 256 &&
9977 "Only for 256-bit or wider vector shuffles!");
9978 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9979 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9981 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9982 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9984 int NumElements = VT.getVectorNumElements();
9985 int SplitNumElements = NumElements / 2;
9986 MVT ScalarVT = VT.getVectorElementType();
9987 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9989 // Rather than splitting build-vectors, just build two narrower build
9990 // vectors. This helps shuffling with splats and zeros.
9991 auto SplitVector = [&](SDValue V) {
9992 while (V.getOpcode() == ISD::BITCAST)
9993 V = V->getOperand(0);
9995 MVT OrigVT = V.getSimpleValueType();
9996 int OrigNumElements = OrigVT.getVectorNumElements();
9997 int OrigSplitNumElements = OrigNumElements / 2;
9998 MVT OrigScalarVT = OrigVT.getVectorElementType();
9999 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
10003 auto *BV = dyn_cast<BuildVectorSDNode>(V);
10005 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
10006 DAG.getIntPtrConstant(0, DL));
10007 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
10008 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
10011 SmallVector<SDValue, 16> LoOps, HiOps;
10012 for (int i = 0; i < OrigSplitNumElements; ++i) {
10013 LoOps.push_back(BV->getOperand(i));
10014 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
10016 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
10017 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
10019 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
10020 DAG.getBitcast(SplitVT, HiV));
10023 SDValue LoV1, HiV1, LoV2, HiV2;
10024 std::tie(LoV1, HiV1) = SplitVector(V1);
10025 std::tie(LoV2, HiV2) = SplitVector(V2);
10027 // Now create two 4-way blends of these half-width vectors.
10028 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
10029 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
10030 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
10031 for (int i = 0; i < SplitNumElements; ++i) {
10032 int M = HalfMask[i];
10033 if (M >= NumElements) {
10034 if (M >= NumElements + SplitNumElements)
10038 V2BlendMask.push_back(M - NumElements);
10039 V1BlendMask.push_back(-1);
10040 BlendMask.push_back(SplitNumElements + i);
10041 } else if (M >= 0) {
10042 if (M >= SplitNumElements)
10046 V2BlendMask.push_back(-1);
10047 V1BlendMask.push_back(M);
10048 BlendMask.push_back(i);
10050 V2BlendMask.push_back(-1);
10051 V1BlendMask.push_back(-1);
10052 BlendMask.push_back(-1);
10056 // Because the lowering happens after all combining takes place, we need to
10057 // manually combine these blend masks as much as possible so that we create
10058 // a minimal number of high-level vector shuffle nodes.
10060 // First try just blending the halves of V1 or V2.
10061 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
10062 return DAG.getUNDEF(SplitVT);
10063 if (!UseLoV2 && !UseHiV2)
10064 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
10065 if (!UseLoV1 && !UseHiV1)
10066 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10068 SDValue V1Blend, V2Blend;
10069 if (UseLoV1 && UseHiV1) {
10071 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
10073 // We only use half of V1 so map the usage down into the final blend mask.
10074 V1Blend = UseLoV1 ? LoV1 : HiV1;
10075 for (int i = 0; i < SplitNumElements; ++i)
10076 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
10077 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
10079 if (UseLoV2 && UseHiV2) {
10081 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
10083 // We only use half of V2 so map the usage down into the final blend mask.
10084 V2Blend = UseLoV2 ? LoV2 : HiV2;
10085 for (int i = 0; i < SplitNumElements; ++i)
10086 if (BlendMask[i] >= SplitNumElements)
10087 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
10089 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
10091 SDValue Lo = HalfBlend(LoMask);
10092 SDValue Hi = HalfBlend(HiMask);
10093 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
10096 /// \brief Either split a vector in halves or decompose the shuffles and the
10099 /// This is provided as a good fallback for many lowerings of non-single-input
10100 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10101 /// between splitting the shuffle into 128-bit components and stitching those
10102 /// back together vs. extracting the single-input shuffles and blending those
10104 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10105 SDValue V2, ArrayRef<int> Mask,
10106 SelectionDAG &DAG) {
10107 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10108 "lower single-input shuffles as it "
10109 "could then recurse on itself.");
10110 int Size = Mask.size();
10112 // If this can be modeled as a broadcast of two elements followed by a blend,
10113 // prefer that lowering. This is especially important because broadcasts can
10114 // often fold with memory operands.
10115 auto DoBothBroadcast = [&] {
10116 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10119 if (V2BroadcastIdx == -1)
10120 V2BroadcastIdx = M - Size;
10121 else if (M - Size != V2BroadcastIdx)
10123 } else if (M >= 0) {
10124 if (V1BroadcastIdx == -1)
10125 V1BroadcastIdx = M;
10126 else if (M != V1BroadcastIdx)
10131 if (DoBothBroadcast())
10132 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10135 // If the inputs all stem from a single 128-bit lane of each input, then we
10136 // split them rather than blending because the split will decompose to
10137 // unusually few instructions.
10138 int LaneCount = VT.getSizeInBits() / 128;
10139 int LaneSize = Size / LaneCount;
10140 SmallBitVector LaneInputs[2];
10141 LaneInputs[0].resize(LaneCount, false);
10142 LaneInputs[1].resize(LaneCount, false);
10143 for (int i = 0; i < Size; ++i)
10145 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10146 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10147 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10149 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10150 // that the decomposed single-input shuffles don't end up here.
10151 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10154 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10155 /// a permutation and blend of those lanes.
10157 /// This essentially blends the out-of-lane inputs to each lane into the lane
10158 /// from a permuted copy of the vector. This lowering strategy results in four
10159 /// instructions in the worst case for a single-input cross lane shuffle which
10160 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10161 /// of. Special cases for each particular shuffle pattern should be handled
10162 /// prior to trying this lowering.
10163 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10164 SDValue V1, SDValue V2,
10165 ArrayRef<int> Mask,
10166 SelectionDAG &DAG) {
10167 // FIXME: This should probably be generalized for 512-bit vectors as well.
10168 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10169 int LaneSize = Mask.size() / 2;
10171 // If there are only inputs from one 128-bit lane, splitting will in fact be
10172 // less expensive. The flags track whether the given lane contains an element
10173 // that crosses to another lane.
10174 bool LaneCrossing[2] = {false, false};
10175 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10176 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10177 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10178 if (!LaneCrossing[0] || !LaneCrossing[1])
10179 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10181 if (isSingleInputShuffleMask(Mask)) {
10182 SmallVector<int, 32> FlippedBlendMask;
10183 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10184 FlippedBlendMask.push_back(
10185 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10187 : Mask[i] % LaneSize +
10188 (i / LaneSize) * LaneSize + Size));
10190 // Flip the vector, and blend the results which should now be in-lane. The
10191 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10192 // 5 for the high source. The value 3 selects the high half of source 2 and
10193 // the value 2 selects the low half of source 2. We only use source 2 to
10194 // allow folding it into a memory operand.
10195 unsigned PERMMask = 3 | 2 << 4;
10196 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10197 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10198 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10201 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10202 // will be handled by the above logic and a blend of the results, much like
10203 // other patterns in AVX.
10204 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10207 /// \brief Handle lowering 2-lane 128-bit shuffles.
10208 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10209 SDValue V2, ArrayRef<int> Mask,
10210 const X86Subtarget *Subtarget,
10211 SelectionDAG &DAG) {
10212 // TODO: If minimizing size and one of the inputs is a zero vector and the
10213 // the zero vector has only one use, we could use a VPERM2X128 to save the
10214 // instruction bytes needed to explicitly generate the zero vector.
10216 // Blends are faster and handle all the non-lane-crossing cases.
10217 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10221 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10222 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10224 // If either input operand is a zero vector, use VPERM2X128 because its mask
10225 // allows us to replace the zero input with an implicit zero.
10226 if (!IsV1Zero && !IsV2Zero) {
10227 // Check for patterns which can be matched with a single insert of a 128-bit
10229 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10230 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10231 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10232 VT.getVectorNumElements() / 2);
10233 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10234 DAG.getIntPtrConstant(0, DL));
10235 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10236 OnlyUsesV1 ? V1 : V2,
10237 DAG.getIntPtrConstant(0, DL));
10238 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10242 // Otherwise form a 128-bit permutation. After accounting for undefs,
10243 // convert the 64-bit shuffle mask selection values into 128-bit
10244 // selection bits by dividing the indexes by 2 and shifting into positions
10245 // defined by a vperm2*128 instruction's immediate control byte.
10247 // The immediate permute control byte looks like this:
10248 // [1:0] - select 128 bits from sources for low half of destination
10250 // [3] - zero low half of destination
10251 // [5:4] - select 128 bits from sources for high half of destination
10253 // [7] - zero high half of destination
10255 int MaskLO = Mask[0];
10256 if (MaskLO == SM_SentinelUndef)
10257 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10259 int MaskHI = Mask[2];
10260 if (MaskHI == SM_SentinelUndef)
10261 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10263 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10265 // If either input is a zero vector, replace it with an undef input.
10266 // Shuffle mask values < 4 are selecting elements of V1.
10267 // Shuffle mask values >= 4 are selecting elements of V2.
10268 // Adjust each half of the permute mask by clearing the half that was
10269 // selecting the zero vector and setting the zero mask bit.
10271 V1 = DAG.getUNDEF(VT);
10273 PermMask = (PermMask & 0xf0) | 0x08;
10275 PermMask = (PermMask & 0x0f) | 0x80;
10278 V2 = DAG.getUNDEF(VT);
10280 PermMask = (PermMask & 0xf0) | 0x08;
10282 PermMask = (PermMask & 0x0f) | 0x80;
10285 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10286 DAG.getConstant(PermMask, DL, MVT::i8));
10289 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10290 /// shuffling each lane.
10292 /// This will only succeed when the result of fixing the 128-bit lanes results
10293 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10294 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10295 /// the lane crosses early and then use simpler shuffles within each lane.
10297 /// FIXME: It might be worthwhile at some point to support this without
10298 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10299 /// in x86 only floating point has interesting non-repeating shuffles, and even
10300 /// those are still *marginally* more expensive.
10301 static SDValue lowerVectorShuffleByMerging128BitLanes(
10302 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10303 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10304 assert(!isSingleInputShuffleMask(Mask) &&
10305 "This is only useful with multiple inputs.");
10307 int Size = Mask.size();
10308 int LaneSize = 128 / VT.getScalarSizeInBits();
10309 int NumLanes = Size / LaneSize;
10310 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10312 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10313 // check whether the in-128-bit lane shuffles share a repeating pattern.
10314 SmallVector<int, 4> Lanes;
10315 Lanes.resize(NumLanes, -1);
10316 SmallVector<int, 4> InLaneMask;
10317 InLaneMask.resize(LaneSize, -1);
10318 for (int i = 0; i < Size; ++i) {
10322 int j = i / LaneSize;
10324 if (Lanes[j] < 0) {
10325 // First entry we've seen for this lane.
10326 Lanes[j] = Mask[i] / LaneSize;
10327 } else if (Lanes[j] != Mask[i] / LaneSize) {
10328 // This doesn't match the lane selected previously!
10332 // Check that within each lane we have a consistent shuffle mask.
10333 int k = i % LaneSize;
10334 if (InLaneMask[k] < 0) {
10335 InLaneMask[k] = Mask[i] % LaneSize;
10336 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10337 // This doesn't fit a repeating in-lane mask.
10342 // First shuffle the lanes into place.
10343 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10344 VT.getSizeInBits() / 64);
10345 SmallVector<int, 8> LaneMask;
10346 LaneMask.resize(NumLanes * 2, -1);
10347 for (int i = 0; i < NumLanes; ++i)
10348 if (Lanes[i] >= 0) {
10349 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10350 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10353 V1 = DAG.getBitcast(LaneVT, V1);
10354 V2 = DAG.getBitcast(LaneVT, V2);
10355 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10357 // Cast it back to the type we actually want.
10358 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10360 // Now do a simple shuffle that isn't lane crossing.
10361 SmallVector<int, 8> NewMask;
10362 NewMask.resize(Size, -1);
10363 for (int i = 0; i < Size; ++i)
10365 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10366 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10367 "Must not introduce lane crosses at this point!");
10369 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10372 /// Lower shuffles where an entire half of a 256-bit vector is UNDEF.
10373 /// This allows for fast cases such as subvector extraction/insertion
10374 /// or shuffling smaller vector types which can lower more efficiently.
10375 static SDValue lowerVectorShuffleWithUndefHalf(SDLoc DL, MVT VT, SDValue V1,
10376 SDValue V2, ArrayRef<int> Mask,
10377 const X86Subtarget *Subtarget,
10378 SelectionDAG &DAG) {
10379 assert(VT.getSizeInBits() == 256 && "Expected 256-bit vector");
10381 unsigned NumElts = VT.getVectorNumElements();
10382 unsigned HalfNumElts = NumElts / 2;
10383 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(), HalfNumElts);
10385 bool UndefLower = isUndefInRange(Mask, 0, HalfNumElts);
10386 bool UndefUpper = isUndefInRange(Mask, HalfNumElts, HalfNumElts);
10387 if (!UndefLower && !UndefUpper)
10390 // Upper half is undef and lower half is whole upper subvector.
10391 // e.g. vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
10393 isSequentialOrUndefInRange(Mask, 0, HalfNumElts, HalfNumElts)) {
10394 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1,
10395 DAG.getIntPtrConstant(HalfNumElts, DL));
10396 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
10397 DAG.getIntPtrConstant(0, DL));
10400 // Lower half is undef and upper half is whole lower subvector.
10401 // e.g. vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
10403 isSequentialOrUndefInRange(Mask, HalfNumElts, HalfNumElts, 0)) {
10404 SDValue Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V1,
10405 DAG.getIntPtrConstant(0, DL));
10406 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), Hi,
10407 DAG.getIntPtrConstant(HalfNumElts, DL));
10410 // AVX2 supports efficient immediate 64-bit element cross-lane shuffles.
10411 if (UndefLower && Subtarget->hasAVX2() &&
10412 (VT == MVT::v4f64 || VT == MVT::v4i64))
10415 // If the shuffle only uses the lower halves of the input operands,
10416 // then extract them and perform the 'half' shuffle at half width.
10417 // e.g. vector_shuffle <X, X, X, X, u, u, u, u> or <X, X, u, u>
10418 int HalfIdx1 = -1, HalfIdx2 = -1;
10419 SmallVector<int, 8> HalfMask;
10420 unsigned Offset = UndefLower ? HalfNumElts : 0;
10421 for (unsigned i = 0; i != HalfNumElts; ++i) {
10422 int M = Mask[i + Offset];
10424 HalfMask.push_back(M);
10428 // Determine which of the 4 half vectors this element is from.
10429 // i.e. 0 = Lower V1, 1 = Upper V1, 2 = Lower V2, 3 = Upper V2.
10430 int HalfIdx = M / HalfNumElts;
10432 // Only shuffle using the lower halves of the inputs.
10433 // TODO: Investigate usefulness of shuffling with upper halves.
10434 if (HalfIdx != 0 && HalfIdx != 2)
10437 // Determine the element index into its half vector source.
10438 int HalfElt = M % HalfNumElts;
10440 // We can shuffle with up to 2 half vectors, set the new 'half'
10441 // shuffle mask accordingly.
10442 if (-1 == HalfIdx1 || HalfIdx1 == HalfIdx) {
10443 HalfMask.push_back(HalfElt);
10444 HalfIdx1 = HalfIdx;
10447 if (-1 == HalfIdx2 || HalfIdx2 == HalfIdx) {
10448 HalfMask.push_back(HalfElt + HalfNumElts);
10449 HalfIdx2 = HalfIdx;
10453 // Too many half vectors referenced.
10456 assert(HalfMask.size() == HalfNumElts && "Unexpected shuffle mask length");
10458 auto GetHalfVector = [&](int HalfIdx) {
10460 return DAG.getUNDEF(HalfVT);
10461 SDValue V = (HalfIdx < 2 ? V1 : V2);
10462 HalfIdx = (HalfIdx % 2) * HalfNumElts;
10463 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, V,
10464 DAG.getIntPtrConstant(HalfIdx, DL));
10467 SDValue Half1 = GetHalfVector(HalfIdx1);
10468 SDValue Half2 = GetHalfVector(HalfIdx2);
10469 SDValue V = DAG.getVectorShuffle(HalfVT, DL, Half1, Half2, HalfMask);
10470 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT, DAG.getUNDEF(VT), V,
10471 DAG.getIntPtrConstant(Offset, DL));
10474 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10477 /// This returns true if the elements from a particular input are already in the
10478 /// slot required by the given mask and require no permutation.
10479 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10480 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10481 int Size = Mask.size();
10482 for (int i = 0; i < Size; ++i)
10483 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10489 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10490 ArrayRef<int> Mask, SDValue V1,
10491 SDValue V2, SelectionDAG &DAG) {
10493 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10494 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10495 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10496 int NumElts = VT.getVectorNumElements();
10497 bool ShufpdMask = true;
10498 bool CommutableMask = true;
10499 unsigned Immediate = 0;
10500 for (int i = 0; i < NumElts; ++i) {
10503 int Val = (i & 6) + NumElts * (i & 1);
10504 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10505 if (Mask[i] < Val || Mask[i] > Val + 1)
10506 ShufpdMask = false;
10507 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10508 CommutableMask = false;
10509 Immediate |= (Mask[i] % 2) << i;
10512 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10513 DAG.getConstant(Immediate, DL, MVT::i8));
10514 if (CommutableMask)
10515 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10516 DAG.getConstant(Immediate, DL, MVT::i8));
10520 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10522 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10523 /// isn't available.
10524 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10525 const X86Subtarget *Subtarget,
10526 SelectionDAG &DAG) {
10528 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10529 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10530 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10531 ArrayRef<int> Mask = SVOp->getMask();
10532 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10534 SmallVector<int, 4> WidenedMask;
10535 if (canWidenShuffleElements(Mask, WidenedMask))
10536 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10539 if (isSingleInputShuffleMask(Mask)) {
10540 // Check for being able to broadcast a single element.
10541 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10542 Mask, Subtarget, DAG))
10545 // Use low duplicate instructions for masks that match their pattern.
10546 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10547 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10549 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10550 // Non-half-crossing single input shuffles can be lowerid with an
10551 // interleaved permutation.
10552 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10553 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10554 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10555 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10558 // With AVX2 we have direct support for this permutation.
10559 if (Subtarget->hasAVX2())
10560 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10561 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10563 // Otherwise, fall back.
10564 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10568 // Use dedicated unpack instructions for masks that match their pattern.
10570 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10573 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10577 // Check if the blend happens to exactly fit that of SHUFPD.
10579 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10582 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10583 // shuffle. However, if we have AVX2 and either inputs are already in place,
10584 // we will be able to shuffle even across lanes the other input in a single
10585 // instruction so skip this pattern.
10586 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10587 isShuffleMaskInputInPlace(1, Mask))))
10588 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10589 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10592 // If we have AVX2 then we always want to lower with a blend because an v4 we
10593 // can fully permute the elements.
10594 if (Subtarget->hasAVX2())
10595 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10598 // Otherwise fall back on generic lowering.
10599 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10602 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10604 /// This routine is only called when we have AVX2 and thus a reasonable
10605 /// instruction set for v4i64 shuffling..
10606 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10607 const X86Subtarget *Subtarget,
10608 SelectionDAG &DAG) {
10610 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10611 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10612 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10613 ArrayRef<int> Mask = SVOp->getMask();
10614 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10615 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10617 SmallVector<int, 4> WidenedMask;
10618 if (canWidenShuffleElements(Mask, WidenedMask))
10619 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10622 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10626 // Check for being able to broadcast a single element.
10627 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10628 Mask, Subtarget, DAG))
10631 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10632 // use lower latency instructions that will operate on both 128-bit lanes.
10633 SmallVector<int, 2> RepeatedMask;
10634 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10635 if (isSingleInputShuffleMask(Mask)) {
10636 int PSHUFDMask[] = {-1, -1, -1, -1};
10637 for (int i = 0; i < 2; ++i)
10638 if (RepeatedMask[i] >= 0) {
10639 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10640 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10642 return DAG.getBitcast(
10644 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10645 DAG.getBitcast(MVT::v8i32, V1),
10646 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10650 // AVX2 provides a direct instruction for permuting a single input across
10652 if (isSingleInputShuffleMask(Mask))
10653 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10654 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10656 // Try to use shift instructions.
10657 if (SDValue Shift =
10658 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10661 // Use dedicated unpack instructions for masks that match their pattern.
10663 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10666 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10667 // shuffle. However, if we have AVX2 and either inputs are already in place,
10668 // we will be able to shuffle even across lanes the other input in a single
10669 // instruction so skip this pattern.
10670 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10671 isShuffleMaskInputInPlace(1, Mask))))
10672 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10673 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10676 // Otherwise fall back on generic blend lowering.
10677 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10681 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10683 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10684 /// isn't available.
10685 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10686 const X86Subtarget *Subtarget,
10687 SelectionDAG &DAG) {
10689 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10690 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10691 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10692 ArrayRef<int> Mask = SVOp->getMask();
10693 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10695 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10699 // Check for being able to broadcast a single element.
10700 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10701 Mask, Subtarget, DAG))
10704 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10705 // options to efficiently lower the shuffle.
10706 SmallVector<int, 4> RepeatedMask;
10707 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10708 assert(RepeatedMask.size() == 4 &&
10709 "Repeated masks must be half the mask width!");
10711 // Use even/odd duplicate instructions for masks that match their pattern.
10712 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10713 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10714 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10715 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10717 if (isSingleInputShuffleMask(Mask))
10718 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10719 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10721 // Use dedicated unpack instructions for masks that match their pattern.
10723 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10726 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10727 // have already handled any direct blends. We also need to squash the
10728 // repeated mask into a simulated v4f32 mask.
10729 for (int i = 0; i < 4; ++i)
10730 if (RepeatedMask[i] >= 8)
10731 RepeatedMask[i] -= 4;
10732 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10735 // If we have a single input shuffle with different shuffle patterns in the
10736 // two 128-bit lanes use the variable mask to VPERMILPS.
10737 if (isSingleInputShuffleMask(Mask)) {
10738 SDValue VPermMask[8];
10739 for (int i = 0; i < 8; ++i)
10740 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10741 : DAG.getConstant(Mask[i], DL, MVT::i32);
10742 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10743 return DAG.getNode(
10744 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10745 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10747 if (Subtarget->hasAVX2())
10748 return DAG.getNode(
10749 X86ISD::VPERMV, DL, MVT::v8f32,
10750 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10752 // Otherwise, fall back.
10753 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10757 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10759 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10760 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10763 // If we have AVX2 then we always want to lower with a blend because at v8 we
10764 // can fully permute the elements.
10765 if (Subtarget->hasAVX2())
10766 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10769 // Otherwise fall back on generic lowering.
10770 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10773 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10775 /// This routine is only called when we have AVX2 and thus a reasonable
10776 /// instruction set for v8i32 shuffling..
10777 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10778 const X86Subtarget *Subtarget,
10779 SelectionDAG &DAG) {
10781 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10782 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10783 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10784 ArrayRef<int> Mask = SVOp->getMask();
10785 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10786 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10788 // Whenever we can lower this as a zext, that instruction is strictly faster
10789 // than any alternative. It also allows us to fold memory operands into the
10790 // shuffle in many cases.
10791 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10792 Mask, Subtarget, DAG))
10795 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10799 // Check for being able to broadcast a single element.
10800 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10801 Mask, Subtarget, DAG))
10804 // If the shuffle mask is repeated in each 128-bit lane we can use more
10805 // efficient instructions that mirror the shuffles across the two 128-bit
10807 SmallVector<int, 4> RepeatedMask;
10808 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10809 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10810 if (isSingleInputShuffleMask(Mask))
10811 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10812 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10814 // Use dedicated unpack instructions for masks that match their pattern.
10816 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10820 // Try to use shift instructions.
10821 if (SDValue Shift =
10822 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10825 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10826 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10829 // If the shuffle patterns aren't repeated but it is a single input, directly
10830 // generate a cross-lane VPERMD instruction.
10831 if (isSingleInputShuffleMask(Mask)) {
10832 SDValue VPermMask[8];
10833 for (int i = 0; i < 8; ++i)
10834 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10835 : DAG.getConstant(Mask[i], DL, MVT::i32);
10836 return DAG.getNode(
10837 X86ISD::VPERMV, DL, MVT::v8i32,
10838 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10841 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10843 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10844 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10847 // Otherwise fall back on generic blend lowering.
10848 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10852 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10854 /// This routine is only called when we have AVX2 and thus a reasonable
10855 /// instruction set for v16i16 shuffling..
10856 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10857 const X86Subtarget *Subtarget,
10858 SelectionDAG &DAG) {
10860 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10861 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10862 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10863 ArrayRef<int> Mask = SVOp->getMask();
10864 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10865 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10867 // Whenever we can lower this as a zext, that instruction is strictly faster
10868 // than any alternative. It also allows us to fold memory operands into the
10869 // shuffle in many cases.
10870 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10871 Mask, Subtarget, DAG))
10874 // Check for being able to broadcast a single element.
10875 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10876 Mask, Subtarget, DAG))
10879 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10883 // Use dedicated unpack instructions for masks that match their pattern.
10885 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10888 // Try to use shift instructions.
10889 if (SDValue Shift =
10890 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10893 // Try to use byte rotation instructions.
10894 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10895 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10898 if (isSingleInputShuffleMask(Mask)) {
10899 // There are no generalized cross-lane shuffle operations available on i16
10901 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10902 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10905 SmallVector<int, 8> RepeatedMask;
10906 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10907 // As this is a single-input shuffle, the repeated mask should be
10908 // a strictly valid v8i16 mask that we can pass through to the v8i16
10909 // lowering to handle even the v16 case.
10910 return lowerV8I16GeneralSingleInputVectorShuffle(
10911 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10914 SDValue PSHUFBMask[32];
10915 for (int i = 0; i < 16; ++i) {
10916 if (Mask[i] == -1) {
10917 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10921 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10922 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10923 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10924 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10926 return DAG.getBitcast(MVT::v16i16,
10927 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10928 DAG.getBitcast(MVT::v32i8, V1),
10929 DAG.getNode(ISD::BUILD_VECTOR, DL,
10930 MVT::v32i8, PSHUFBMask)));
10933 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10935 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10936 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10939 // Otherwise fall back on generic lowering.
10940 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10943 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10945 /// This routine is only called when we have AVX2 and thus a reasonable
10946 /// instruction set for v32i8 shuffling..
10947 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10948 const X86Subtarget *Subtarget,
10949 SelectionDAG &DAG) {
10951 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10952 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10953 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10954 ArrayRef<int> Mask = SVOp->getMask();
10955 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10956 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10958 // Whenever we can lower this as a zext, that instruction is strictly faster
10959 // than any alternative. It also allows us to fold memory operands into the
10960 // shuffle in many cases.
10961 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10962 Mask, Subtarget, DAG))
10965 // Check for being able to broadcast a single element.
10966 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10967 Mask, Subtarget, DAG))
10970 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10974 // Use dedicated unpack instructions for masks that match their pattern.
10976 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10979 // Try to use shift instructions.
10980 if (SDValue Shift =
10981 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10984 // Try to use byte rotation instructions.
10985 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10986 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10989 if (isSingleInputShuffleMask(Mask)) {
10990 // There are no generalized cross-lane shuffle operations available on i8
10992 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10993 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10996 SDValue PSHUFBMask[32];
10997 for (int i = 0; i < 32; ++i)
11000 ? DAG.getUNDEF(MVT::i8)
11001 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
11004 return DAG.getNode(
11005 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
11006 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
11009 // Try to simplify this by merging 128-bit lanes to enable a lane-based
11011 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
11012 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
11015 // Otherwise fall back on generic lowering.
11016 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
11019 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
11021 /// This routine either breaks down the specific type of a 256-bit x86 vector
11022 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
11023 /// together based on the available instructions.
11024 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11025 MVT VT, const X86Subtarget *Subtarget,
11026 SelectionDAG &DAG) {
11028 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11029 ArrayRef<int> Mask = SVOp->getMask();
11031 // If we have a single input to the zero element, insert that into V1 if we
11032 // can do so cheaply.
11033 int NumElts = VT.getVectorNumElements();
11034 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
11035 return M >= NumElts;
11038 if (NumV2Elements == 1 && Mask[0] >= NumElts)
11039 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
11040 DL, VT, V1, V2, Mask, Subtarget, DAG))
11043 // Handle special cases where the lower or upper half is UNDEF.
11045 lowerVectorShuffleWithUndefHalf(DL, VT, V1, V2, Mask, Subtarget, DAG))
11048 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
11049 // can check for those subtargets here and avoid much of the subtarget
11050 // querying in the per-vector-type lowering routines. With AVX1 we have
11051 // essentially *zero* ability to manipulate a 256-bit vector with integer
11052 // types. Since we'll use floating point types there eventually, just
11053 // immediately cast everything to a float and operate entirely in that domain.
11054 if (VT.isInteger() && !Subtarget->hasAVX2()) {
11055 int ElementBits = VT.getScalarSizeInBits();
11056 if (ElementBits < 32)
11057 // No floating point type available, decompose into 128-bit vectors.
11058 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11060 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
11061 VT.getVectorNumElements());
11062 V1 = DAG.getBitcast(FpVT, V1);
11063 V2 = DAG.getBitcast(FpVT, V2);
11064 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
11067 switch (VT.SimpleTy) {
11069 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11071 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11073 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11075 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11077 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11079 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11082 llvm_unreachable("Not a valid 256-bit x86 vector type!");
11086 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
11087 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
11088 ArrayRef<int> Mask,
11089 SDValue V1, SDValue V2,
11090 SelectionDAG &DAG) {
11091 assert(VT.getScalarSizeInBits() == 64 &&
11092 "Unexpected element type size for 128bit shuffle.");
11094 // To handle 256 bit vector requires VLX and most probably
11095 // function lowerV2X128VectorShuffle() is better solution.
11096 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
11098 SmallVector<int, 4> WidenedMask;
11099 if (!canWidenShuffleElements(Mask, WidenedMask))
11102 // Form a 128-bit permutation.
11103 // Convert the 64-bit shuffle mask selection values into 128-bit selection
11104 // bits defined by a vshuf64x2 instruction's immediate control byte.
11105 unsigned PermMask = 0, Imm = 0;
11106 unsigned ControlBitsNum = WidenedMask.size() / 2;
11108 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
11109 if (WidenedMask[i] == SM_SentinelZero)
11112 // Use first element in place of undef mask.
11113 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
11114 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
11117 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
11118 DAG.getConstant(PermMask, DL, MVT::i8));
11121 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
11122 ArrayRef<int> Mask, SDValue V1,
11123 SDValue V2, SelectionDAG &DAG) {
11125 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
11127 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
11128 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
11130 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
11131 if (isSingleInputShuffleMask(Mask))
11132 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
11134 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
11137 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
11138 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11139 const X86Subtarget *Subtarget,
11140 SelectionDAG &DAG) {
11142 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
11143 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
11144 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11145 ArrayRef<int> Mask = SVOp->getMask();
11146 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
11148 if (SDValue Shuf128 =
11149 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
11152 if (SDValue Unpck =
11153 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
11156 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
11159 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
11160 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11161 const X86Subtarget *Subtarget,
11162 SelectionDAG &DAG) {
11164 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
11165 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
11166 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11167 ArrayRef<int> Mask = SVOp->getMask();
11168 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11170 if (SDValue Unpck =
11171 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
11174 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
11177 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
11178 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11179 const X86Subtarget *Subtarget,
11180 SelectionDAG &DAG) {
11182 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11183 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11184 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11185 ArrayRef<int> Mask = SVOp->getMask();
11186 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
11188 if (SDValue Shuf128 =
11189 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
11192 if (SDValue Unpck =
11193 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
11196 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
11199 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
11200 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11201 const X86Subtarget *Subtarget,
11202 SelectionDAG &DAG) {
11204 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11205 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11206 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11207 ArrayRef<int> Mask = SVOp->getMask();
11208 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11210 if (SDValue Unpck =
11211 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11214 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11217 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11218 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11219 const X86Subtarget *Subtarget,
11220 SelectionDAG &DAG) {
11222 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11223 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11224 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11225 ArrayRef<int> Mask = SVOp->getMask();
11226 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11227 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11229 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11232 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11233 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11234 const X86Subtarget *Subtarget,
11235 SelectionDAG &DAG) {
11237 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11238 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11239 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11240 ArrayRef<int> Mask = SVOp->getMask();
11241 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11242 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11244 // FIXME: Implement direct support for this type!
11245 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11248 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11250 /// This routine either breaks down the specific type of a 512-bit x86 vector
11251 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11252 /// together based on the available instructions.
11253 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11254 MVT VT, const X86Subtarget *Subtarget,
11255 SelectionDAG &DAG) {
11257 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11258 ArrayRef<int> Mask = SVOp->getMask();
11259 assert(Subtarget->hasAVX512() &&
11260 "Cannot lower 512-bit vectors w/ basic ISA!");
11262 // Check for being able to broadcast a single element.
11263 if (SDValue Broadcast =
11264 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11267 // Dispatch to each element type for lowering. If we don't have supprot for
11268 // specific element type shuffles at 512 bits, immediately split them and
11269 // lower them. Each lowering routine of a given type is allowed to assume that
11270 // the requisite ISA extensions for that element type are available.
11271 switch (VT.SimpleTy) {
11273 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11275 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11277 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11279 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11281 if (Subtarget->hasBWI())
11282 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11285 if (Subtarget->hasBWI())
11286 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11290 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11293 // Otherwise fall back on splitting.
11294 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11297 // Lower vXi1 vector shuffles.
11298 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11299 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11300 // vector, shuffle and then truncate it back.
11301 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11302 MVT VT, const X86Subtarget *Subtarget,
11303 SelectionDAG &DAG) {
11305 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11306 ArrayRef<int> Mask = SVOp->getMask();
11307 assert(Subtarget->hasAVX512() &&
11308 "Cannot lower 512-bit vectors w/o basic ISA!");
11310 switch (VT.SimpleTy) {
11312 llvm_unreachable("Expected a vector of i1 elements");
11314 ExtVT = MVT::v2i64;
11317 ExtVT = MVT::v4i32;
11320 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11323 ExtVT = MVT::v16i32;
11326 ExtVT = MVT::v32i16;
11329 ExtVT = MVT::v64i8;
11333 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11334 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11335 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11336 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11338 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11341 V2 = DAG.getUNDEF(ExtVT);
11342 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11343 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11344 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11345 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11347 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11348 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11349 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11351 /// \brief Top-level lowering for x86 vector shuffles.
11353 /// This handles decomposition, canonicalization, and lowering of all x86
11354 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11355 /// above in helper routines. The canonicalization attempts to widen shuffles
11356 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11357 /// s.t. only one of the two inputs needs to be tested, etc.
11358 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11359 SelectionDAG &DAG) {
11360 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11361 ArrayRef<int> Mask = SVOp->getMask();
11362 SDValue V1 = Op.getOperand(0);
11363 SDValue V2 = Op.getOperand(1);
11364 MVT VT = Op.getSimpleValueType();
11365 int NumElements = VT.getVectorNumElements();
11367 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11369 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11370 "Can't lower MMX shuffles");
11372 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11373 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11374 if (V1IsUndef && V2IsUndef)
11375 return DAG.getUNDEF(VT);
11377 // When we create a shuffle node we put the UNDEF node to second operand,
11378 // but in some cases the first operand may be transformed to UNDEF.
11379 // In this case we should just commute the node.
11381 return DAG.getCommutedVectorShuffle(*SVOp);
11383 // Check for non-undef masks pointing at an undef vector and make the masks
11384 // undef as well. This makes it easier to match the shuffle based solely on
11388 if (M >= NumElements) {
11389 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11390 for (int &M : NewMask)
11391 if (M >= NumElements)
11393 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11396 // We actually see shuffles that are entirely re-arrangements of a set of
11397 // zero inputs. This mostly happens while decomposing complex shuffles into
11398 // simple ones. Directly lower these as a buildvector of zeros.
11399 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11400 if (Zeroable.all())
11401 return getZeroVector(VT, Subtarget, DAG, dl);
11403 // Try to collapse shuffles into using a vector type with fewer elements but
11404 // wider element types. We cap this to not form integers or floating point
11405 // elements wider than 64 bits, but it might be interesting to form i128
11406 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11407 SmallVector<int, 16> WidenedMask;
11408 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11409 canWidenShuffleElements(Mask, WidenedMask)) {
11410 MVT NewEltVT = VT.isFloatingPoint()
11411 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11412 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11413 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11414 // Make sure that the new vector type is legal. For example, v2f64 isn't
11416 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11417 V1 = DAG.getBitcast(NewVT, V1);
11418 V2 = DAG.getBitcast(NewVT, V2);
11419 return DAG.getBitcast(
11420 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11424 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11425 for (int M : SVOp->getMask())
11427 ++NumUndefElements;
11428 else if (M < NumElements)
11433 // Commute the shuffle as needed such that more elements come from V1 than
11434 // V2. This allows us to match the shuffle pattern strictly on how many
11435 // elements come from V1 without handling the symmetric cases.
11436 if (NumV2Elements > NumV1Elements)
11437 return DAG.getCommutedVectorShuffle(*SVOp);
11439 // When the number of V1 and V2 elements are the same, try to minimize the
11440 // number of uses of V2 in the low half of the vector. When that is tied,
11441 // ensure that the sum of indices for V1 is equal to or lower than the sum
11442 // indices for V2. When those are equal, try to ensure that the number of odd
11443 // indices for V1 is lower than the number of odd indices for V2.
11444 if (NumV1Elements == NumV2Elements) {
11445 int LowV1Elements = 0, LowV2Elements = 0;
11446 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11447 if (M >= NumElements)
11451 if (LowV2Elements > LowV1Elements) {
11452 return DAG.getCommutedVectorShuffle(*SVOp);
11453 } else if (LowV2Elements == LowV1Elements) {
11454 int SumV1Indices = 0, SumV2Indices = 0;
11455 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11456 if (SVOp->getMask()[i] >= NumElements)
11458 else if (SVOp->getMask()[i] >= 0)
11460 if (SumV2Indices < SumV1Indices) {
11461 return DAG.getCommutedVectorShuffle(*SVOp);
11462 } else if (SumV2Indices == SumV1Indices) {
11463 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11464 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11465 if (SVOp->getMask()[i] >= NumElements)
11466 NumV2OddIndices += i % 2;
11467 else if (SVOp->getMask()[i] >= 0)
11468 NumV1OddIndices += i % 2;
11469 if (NumV2OddIndices < NumV1OddIndices)
11470 return DAG.getCommutedVectorShuffle(*SVOp);
11475 // For each vector width, delegate to a specialized lowering routine.
11476 if (VT.is128BitVector())
11477 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11479 if (VT.is256BitVector())
11480 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11482 if (VT.is512BitVector())
11483 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11486 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11487 llvm_unreachable("Unimplemented!");
11490 // This function assumes its argument is a BUILD_VECTOR of constants or
11491 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11493 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11494 unsigned &MaskValue) {
11496 unsigned NumElems = BuildVector->getNumOperands();
11498 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11499 // We don't handle the >2 lanes case right now.
11500 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11504 unsigned NumElemsInLane = NumElems / NumLanes;
11506 // Blend for v16i16 should be symmetric for the both lanes.
11507 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11508 SDValue EltCond = BuildVector->getOperand(i);
11509 SDValue SndLaneEltCond =
11510 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11512 int Lane1Cond = -1, Lane2Cond = -1;
11513 if (isa<ConstantSDNode>(EltCond))
11514 Lane1Cond = !isNullConstant(EltCond);
11515 if (isa<ConstantSDNode>(SndLaneEltCond))
11516 Lane2Cond = !isNullConstant(SndLaneEltCond);
11518 unsigned LaneMask = 0;
11519 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11520 // Lane1Cond != 0, means we want the first argument.
11521 // Lane1Cond == 0, means we want the second argument.
11522 // The encoding of this argument is 0 for the first argument, 1
11523 // for the second. Therefore, invert the condition.
11524 LaneMask = !Lane1Cond << i;
11525 else if (Lane1Cond < 0)
11526 LaneMask = !Lane2Cond << i;
11530 MaskValue |= LaneMask;
11532 MaskValue |= LaneMask << NumElemsInLane;
11537 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11538 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11539 const X86Subtarget *Subtarget,
11540 SelectionDAG &DAG) {
11541 SDValue Cond = Op.getOperand(0);
11542 SDValue LHS = Op.getOperand(1);
11543 SDValue RHS = Op.getOperand(2);
11545 MVT VT = Op.getSimpleValueType();
11547 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11549 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11551 // Only non-legal VSELECTs reach this lowering, convert those into generic
11552 // shuffles and re-use the shuffle lowering path for blends.
11553 SmallVector<int, 32> Mask;
11554 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11555 SDValue CondElt = CondBV->getOperand(i);
11557 isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
11560 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11563 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11564 // A vselect where all conditions and data are constants can be optimized into
11565 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11566 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11567 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11568 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11571 // Try to lower this to a blend-style vector shuffle. This can handle all
11572 // constant condition cases.
11573 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11576 // Variable blends are only legal from SSE4.1 onward.
11577 if (!Subtarget->hasSSE41())
11580 // Only some types will be legal on some subtargets. If we can emit a legal
11581 // VSELECT-matching blend, return Op, and but if we need to expand, return
11583 switch (Op.getSimpleValueType().SimpleTy) {
11585 // Most of the vector types have blends past SSE4.1.
11589 // The byte blends for AVX vectors were introduced only in AVX2.
11590 if (Subtarget->hasAVX2())
11597 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11598 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11601 // FIXME: We should custom lower this by fixing the condition and using i8
11607 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11608 MVT VT = Op.getSimpleValueType();
11611 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11614 if (VT.getSizeInBits() == 8) {
11615 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11616 Op.getOperand(0), Op.getOperand(1));
11617 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11618 DAG.getValueType(VT));
11619 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11622 if (VT.getSizeInBits() == 16) {
11623 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11624 if (isNullConstant(Op.getOperand(1)))
11625 return DAG.getNode(
11626 ISD::TRUNCATE, dl, MVT::i16,
11627 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11628 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11629 Op.getOperand(1)));
11630 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11631 Op.getOperand(0), Op.getOperand(1));
11632 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11633 DAG.getValueType(VT));
11634 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11637 if (VT == MVT::f32) {
11638 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11639 // the result back to FR32 register. It's only worth matching if the
11640 // result has a single use which is a store or a bitcast to i32. And in
11641 // the case of a store, it's not worth it if the index is a constant 0,
11642 // because a MOVSSmr can be used instead, which is smaller and faster.
11643 if (!Op.hasOneUse())
11645 SDNode *User = *Op.getNode()->use_begin();
11646 if ((User->getOpcode() != ISD::STORE ||
11647 isNullConstant(Op.getOperand(1))) &&
11648 (User->getOpcode() != ISD::BITCAST ||
11649 User->getValueType(0) != MVT::i32))
11651 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11652 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11654 return DAG.getBitcast(MVT::f32, Extract);
11657 if (VT == MVT::i32 || VT == MVT::i64) {
11658 // ExtractPS/pextrq works with constant index.
11659 if (isa<ConstantSDNode>(Op.getOperand(1)))
11665 /// Extract one bit from mask vector, like v16i1 or v8i1.
11666 /// AVX-512 feature.
11668 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11669 SDValue Vec = Op.getOperand(0);
11671 MVT VecVT = Vec.getSimpleValueType();
11672 SDValue Idx = Op.getOperand(1);
11673 MVT EltVT = Op.getSimpleValueType();
11675 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11676 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11677 "Unexpected vector type in ExtractBitFromMaskVector");
11679 // variable index can't be handled in mask registers,
11680 // extend vector to VR512
11681 if (!isa<ConstantSDNode>(Idx)) {
11682 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11683 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11684 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11685 ExtVT.getVectorElementType(), Ext, Idx);
11686 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11689 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11690 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11691 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11692 rc = getRegClassFor(MVT::v16i1);
11693 unsigned MaxSift = rc->getSize()*8 - 1;
11694 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11695 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11696 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11697 DAG.getConstant(MaxSift, dl, MVT::i8));
11698 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11699 DAG.getIntPtrConstant(0, dl));
11703 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11704 SelectionDAG &DAG) const {
11706 SDValue Vec = Op.getOperand(0);
11707 MVT VecVT = Vec.getSimpleValueType();
11708 SDValue Idx = Op.getOperand(1);
11710 if (Op.getSimpleValueType() == MVT::i1)
11711 return ExtractBitFromMaskVector(Op, DAG);
11713 if (!isa<ConstantSDNode>(Idx)) {
11714 if (VecVT.is512BitVector() ||
11715 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11716 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11719 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11720 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11721 MaskEltVT.getSizeInBits());
11723 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11724 auto PtrVT = getPointerTy(DAG.getDataLayout());
11725 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11726 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11727 DAG.getConstant(0, dl, PtrVT));
11728 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11729 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11730 DAG.getConstant(0, dl, PtrVT));
11735 // If this is a 256-bit vector result, first extract the 128-bit vector and
11736 // then extract the element from the 128-bit vector.
11737 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11739 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11740 // Get the 128-bit vector.
11741 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11742 MVT EltVT = VecVT.getVectorElementType();
11744 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11745 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11747 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11748 // this can be done with a mask.
11749 IdxVal &= ElemsPerChunk - 1;
11750 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11751 DAG.getConstant(IdxVal, dl, MVT::i32));
11754 assert(VecVT.is128BitVector() && "Unexpected vector length");
11756 if (Subtarget->hasSSE41())
11757 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11760 MVT VT = Op.getSimpleValueType();
11761 // TODO: handle v16i8.
11762 if (VT.getSizeInBits() == 16) {
11763 SDValue Vec = Op.getOperand(0);
11764 if (isNullConstant(Op.getOperand(1)))
11765 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11766 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11767 DAG.getBitcast(MVT::v4i32, Vec),
11768 Op.getOperand(1)));
11769 // Transform it so it match pextrw which produces a 32-bit result.
11770 MVT EltVT = MVT::i32;
11771 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11772 Op.getOperand(0), Op.getOperand(1));
11773 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11774 DAG.getValueType(VT));
11775 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11778 if (VT.getSizeInBits() == 32) {
11779 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11783 // SHUFPS the element to the lowest double word, then movss.
11784 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11785 MVT VVT = Op.getOperand(0).getSimpleValueType();
11786 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11787 DAG.getUNDEF(VVT), Mask);
11788 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11789 DAG.getIntPtrConstant(0, dl));
11792 if (VT.getSizeInBits() == 64) {
11793 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11794 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11795 // to match extract_elt for f64.
11796 if (isNullConstant(Op.getOperand(1)))
11799 // UNPCKHPD the element to the lowest double word, then movsd.
11800 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11801 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11802 int Mask[2] = { 1, -1 };
11803 MVT VVT = Op.getOperand(0).getSimpleValueType();
11804 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11805 DAG.getUNDEF(VVT), Mask);
11806 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11807 DAG.getIntPtrConstant(0, dl));
11813 /// Insert one bit to mask vector, like v16i1 or v8i1.
11814 /// AVX-512 feature.
11816 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11818 SDValue Vec = Op.getOperand(0);
11819 SDValue Elt = Op.getOperand(1);
11820 SDValue Idx = Op.getOperand(2);
11821 MVT VecVT = Vec.getSimpleValueType();
11823 if (!isa<ConstantSDNode>(Idx)) {
11824 // Non constant index. Extend source and destination,
11825 // insert element and then truncate the result.
11826 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11827 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11828 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11829 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11830 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11831 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11834 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11835 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11837 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11838 DAG.getConstant(IdxVal, dl, MVT::i8));
11839 if (Vec.getOpcode() == ISD::UNDEF)
11841 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11844 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11845 SelectionDAG &DAG) const {
11846 MVT VT = Op.getSimpleValueType();
11847 MVT EltVT = VT.getVectorElementType();
11849 if (EltVT == MVT::i1)
11850 return InsertBitToMaskVector(Op, DAG);
11853 SDValue N0 = Op.getOperand(0);
11854 SDValue N1 = Op.getOperand(1);
11855 SDValue N2 = Op.getOperand(2);
11856 if (!isa<ConstantSDNode>(N2))
11858 auto *N2C = cast<ConstantSDNode>(N2);
11859 unsigned IdxVal = N2C->getZExtValue();
11861 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11862 // into that, and then insert the subvector back into the result.
11863 if (VT.is256BitVector() || VT.is512BitVector()) {
11864 // With a 256-bit vector, we can insert into the zero element efficiently
11865 // using a blend if we have AVX or AVX2 and the right data type.
11866 if (VT.is256BitVector() && IdxVal == 0) {
11867 // TODO: It is worthwhile to cast integer to floating point and back
11868 // and incur a domain crossing penalty if that's what we'll end up
11869 // doing anyway after extracting to a 128-bit vector.
11870 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11871 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11872 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11873 N2 = DAG.getIntPtrConstant(1, dl);
11874 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11878 // Get the desired 128-bit vector chunk.
11879 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11881 // Insert the element into the desired chunk.
11882 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11883 assert(isPowerOf2_32(NumEltsIn128));
11884 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11885 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11887 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11888 DAG.getConstant(IdxIn128, dl, MVT::i32));
11890 // Insert the changed part back into the bigger vector
11891 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11893 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11895 if (Subtarget->hasSSE41()) {
11896 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11898 if (VT == MVT::v8i16) {
11899 Opc = X86ISD::PINSRW;
11901 assert(VT == MVT::v16i8);
11902 Opc = X86ISD::PINSRB;
11905 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11907 if (N1.getValueType() != MVT::i32)
11908 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11909 if (N2.getValueType() != MVT::i32)
11910 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11911 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11914 if (EltVT == MVT::f32) {
11915 // Bits [7:6] of the constant are the source select. This will always be
11916 // zero here. The DAG Combiner may combine an extract_elt index into
11917 // these bits. For example (insert (extract, 3), 2) could be matched by
11918 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11919 // Bits [5:4] of the constant are the destination select. This is the
11920 // value of the incoming immediate.
11921 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11922 // combine either bitwise AND or insert of float 0.0 to set these bits.
11924 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11925 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11926 // If this is an insertion of 32-bits into the low 32-bits of
11927 // a vector, we prefer to generate a blend with immediate rather
11928 // than an insertps. Blends are simpler operations in hardware and so
11929 // will always have equal or better performance than insertps.
11930 // But if optimizing for size and there's a load folding opportunity,
11931 // generate insertps because blendps does not have a 32-bit memory
11933 N2 = DAG.getIntPtrConstant(1, dl);
11934 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11935 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11937 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11938 // Create this as a scalar to vector..
11939 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11940 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11943 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11944 // PINSR* works with constant index.
11949 if (EltVT == MVT::i8)
11952 if (EltVT.getSizeInBits() == 16) {
11953 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11954 // as its second argument.
11955 if (N1.getValueType() != MVT::i32)
11956 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11957 if (N2.getValueType() != MVT::i32)
11958 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11959 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11964 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11966 MVT OpVT = Op.getSimpleValueType();
11968 // If this is a 256-bit vector result, first insert into a 128-bit
11969 // vector and then insert into the 256-bit vector.
11970 if (!OpVT.is128BitVector()) {
11971 // Insert into a 128-bit vector.
11972 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11973 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11974 OpVT.getVectorNumElements() / SizeFactor);
11976 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11978 // Insert the 128-bit vector.
11979 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11982 if (OpVT == MVT::v1i64 &&
11983 Op.getOperand(0).getValueType() == MVT::i64)
11984 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11986 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11987 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11988 return DAG.getBitcast(
11989 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11992 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11993 // a simple subregister reference or explicit instructions to grab
11994 // upper bits of a vector.
11995 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11996 SelectionDAG &DAG) {
11998 SDValue In = Op.getOperand(0);
11999 SDValue Idx = Op.getOperand(1);
12000 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12001 MVT ResVT = Op.getSimpleValueType();
12002 MVT InVT = In.getSimpleValueType();
12004 if (Subtarget->hasFp256()) {
12005 if (ResVT.is128BitVector() &&
12006 (InVT.is256BitVector() || InVT.is512BitVector()) &&
12007 isa<ConstantSDNode>(Idx)) {
12008 return Extract128BitVector(In, IdxVal, DAG, dl);
12010 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
12011 isa<ConstantSDNode>(Idx)) {
12012 return Extract256BitVector(In, IdxVal, DAG, dl);
12018 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
12019 // simple superregister reference or explicit instructions to insert
12020 // the upper bits of a vector.
12021 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
12022 SelectionDAG &DAG) {
12023 if (!Subtarget->hasAVX())
12027 SDValue Vec = Op.getOperand(0);
12028 SDValue SubVec = Op.getOperand(1);
12029 SDValue Idx = Op.getOperand(2);
12031 if (!isa<ConstantSDNode>(Idx))
12034 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12035 MVT OpVT = Op.getSimpleValueType();
12036 MVT SubVecVT = SubVec.getSimpleValueType();
12038 // Fold two 16-byte subvector loads into one 32-byte load:
12039 // (insert_subvector (insert_subvector undef, (load addr), 0),
12040 // (load addr + 16), Elts/2)
12042 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
12043 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
12044 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
12045 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
12046 if (Idx2 && Idx2->getZExtValue() == 0) {
12047 SDValue SubVec2 = Vec.getOperand(1);
12048 // If needed, look through a bitcast to get to the load.
12049 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
12050 SubVec2 = SubVec2.getOperand(0);
12052 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
12054 unsigned Alignment = FirstLd->getAlignment();
12055 unsigned AS = FirstLd->getAddressSpace();
12056 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
12057 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
12058 OpVT, AS, Alignment, &Fast) && Fast) {
12059 SDValue Ops[] = { SubVec2, SubVec };
12060 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
12067 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
12068 SubVecVT.is128BitVector())
12069 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12071 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
12072 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
12074 if (OpVT.getVectorElementType() == MVT::i1)
12075 return Insert1BitVector(Op, DAG);
12080 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
12081 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
12082 // one of the above mentioned nodes. It has to be wrapped because otherwise
12083 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
12084 // be used to form addressing mode. These wrapped nodes will be selected
12087 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
12088 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
12090 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12091 // global base reg.
12092 unsigned char OpFlag = 0;
12093 unsigned WrapperKind = X86ISD::Wrapper;
12094 CodeModel::Model M = DAG.getTarget().getCodeModel();
12096 if (Subtarget->isPICStyleRIPRel() &&
12097 (M == CodeModel::Small || M == CodeModel::Kernel))
12098 WrapperKind = X86ISD::WrapperRIP;
12099 else if (Subtarget->isPICStyleGOT())
12100 OpFlag = X86II::MO_GOTOFF;
12101 else if (Subtarget->isPICStyleStubPIC())
12102 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12104 auto PtrVT = getPointerTy(DAG.getDataLayout());
12105 SDValue Result = DAG.getTargetConstantPool(
12106 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
12108 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12109 // With PIC, the address is actually $g + Offset.
12112 DAG.getNode(ISD::ADD, DL, PtrVT,
12113 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12119 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
12120 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
12122 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12123 // global base reg.
12124 unsigned char OpFlag = 0;
12125 unsigned WrapperKind = X86ISD::Wrapper;
12126 CodeModel::Model M = DAG.getTarget().getCodeModel();
12128 if (Subtarget->isPICStyleRIPRel() &&
12129 (M == CodeModel::Small || M == CodeModel::Kernel))
12130 WrapperKind = X86ISD::WrapperRIP;
12131 else if (Subtarget->isPICStyleGOT())
12132 OpFlag = X86II::MO_GOTOFF;
12133 else if (Subtarget->isPICStyleStubPIC())
12134 OpFlag = X86II::MO_PIC_BASE_OFFSET;
12136 auto PtrVT = getPointerTy(DAG.getDataLayout());
12137 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
12139 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12141 // With PIC, the address is actually $g + Offset.
12144 DAG.getNode(ISD::ADD, DL, PtrVT,
12145 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12151 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
12152 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
12154 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12155 // global base reg.
12156 unsigned char OpFlag = 0;
12157 unsigned WrapperKind = X86ISD::Wrapper;
12158 CodeModel::Model M = DAG.getTarget().getCodeModel();
12160 if (Subtarget->isPICStyleRIPRel() &&
12161 (M == CodeModel::Small || M == CodeModel::Kernel)) {
12162 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
12163 OpFlag = X86II::MO_GOTPCREL;
12164 WrapperKind = X86ISD::WrapperRIP;
12165 } else if (Subtarget->isPICStyleGOT()) {
12166 OpFlag = X86II::MO_GOT;
12167 } else if (Subtarget->isPICStyleStubPIC()) {
12168 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
12169 } else if (Subtarget->isPICStyleStubNoDynamic()) {
12170 OpFlag = X86II::MO_DARWIN_NONLAZY;
12173 auto PtrVT = getPointerTy(DAG.getDataLayout());
12174 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
12177 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12179 // With PIC, the address is actually $g + Offset.
12180 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
12181 !Subtarget->is64Bit()) {
12183 DAG.getNode(ISD::ADD, DL, PtrVT,
12184 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
12187 // For symbols that require a load from a stub to get the address, emit the
12189 if (isGlobalStubReference(OpFlag))
12190 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
12191 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12192 false, false, false, 0);
12198 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12199 // Create the TargetBlockAddressAddress node.
12200 unsigned char OpFlags =
12201 Subtarget->ClassifyBlockAddressReference();
12202 CodeModel::Model M = DAG.getTarget().getCodeModel();
12203 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12204 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12206 auto PtrVT = getPointerTy(DAG.getDataLayout());
12207 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12209 if (Subtarget->isPICStyleRIPRel() &&
12210 (M == CodeModel::Small || M == CodeModel::Kernel))
12211 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12213 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12215 // With PIC, the address is actually $g + Offset.
12216 if (isGlobalRelativeToPICBase(OpFlags)) {
12217 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12218 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12225 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12226 int64_t Offset, SelectionDAG &DAG) const {
12227 // Create the TargetGlobalAddress node, folding in the constant
12228 // offset if it is legal.
12229 unsigned char OpFlags =
12230 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12231 CodeModel::Model M = DAG.getTarget().getCodeModel();
12232 auto PtrVT = getPointerTy(DAG.getDataLayout());
12234 if (OpFlags == X86II::MO_NO_FLAG &&
12235 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12236 // A direct static reference to a global.
12237 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12240 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12243 if (Subtarget->isPICStyleRIPRel() &&
12244 (M == CodeModel::Small || M == CodeModel::Kernel))
12245 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12247 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12249 // With PIC, the address is actually $g + Offset.
12250 if (isGlobalRelativeToPICBase(OpFlags)) {
12251 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12252 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12255 // For globals that require a load from a stub to get the address, emit the
12257 if (isGlobalStubReference(OpFlags))
12258 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12259 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12260 false, false, false, 0);
12262 // If there was a non-zero offset that we didn't fold, create an explicit
12263 // addition for it.
12265 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12266 DAG.getConstant(Offset, dl, PtrVT));
12272 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12273 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12274 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12275 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12279 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12280 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12281 unsigned char OperandFlags, bool LocalDynamic = false) {
12282 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12283 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12285 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12286 GA->getValueType(0),
12290 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12294 SDValue Ops[] = { Chain, TGA, *InFlag };
12295 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12297 SDValue Ops[] = { Chain, TGA };
12298 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12301 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12302 MFI->setAdjustsStack(true);
12303 MFI->setHasCalls(true);
12305 SDValue Flag = Chain.getValue(1);
12306 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12309 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12311 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12314 SDLoc dl(GA); // ? function entry point might be better
12315 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12316 DAG.getNode(X86ISD::GlobalBaseReg,
12317 SDLoc(), PtrVT), InFlag);
12318 InFlag = Chain.getValue(1);
12320 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12323 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12325 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12327 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12328 X86::RAX, X86II::MO_TLSGD);
12331 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12337 // Get the start address of the TLS block for this module.
12338 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12339 .getInfo<X86MachineFunctionInfo>();
12340 MFI->incNumLocalDynamicTLSAccesses();
12344 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12345 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12348 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12349 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12350 InFlag = Chain.getValue(1);
12351 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12352 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12355 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12359 unsigned char OperandFlags = X86II::MO_DTPOFF;
12360 unsigned WrapperKind = X86ISD::Wrapper;
12361 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12362 GA->getValueType(0),
12363 GA->getOffset(), OperandFlags);
12364 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12366 // Add x@dtpoff with the base.
12367 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12370 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12371 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12372 const EVT PtrVT, TLSModel::Model model,
12373 bool is64Bit, bool isPIC) {
12376 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12377 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12378 is64Bit ? 257 : 256));
12380 SDValue ThreadPointer =
12381 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12382 MachinePointerInfo(Ptr), false, false, false, 0);
12384 unsigned char OperandFlags = 0;
12385 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12387 unsigned WrapperKind = X86ISD::Wrapper;
12388 if (model == TLSModel::LocalExec) {
12389 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12390 } else if (model == TLSModel::InitialExec) {
12392 OperandFlags = X86II::MO_GOTTPOFF;
12393 WrapperKind = X86ISD::WrapperRIP;
12395 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12398 llvm_unreachable("Unexpected model");
12401 // emit "addl x@ntpoff,%eax" (local exec)
12402 // or "addl x@indntpoff,%eax" (initial exec)
12403 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12405 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12406 GA->getOffset(), OperandFlags);
12407 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12409 if (model == TLSModel::InitialExec) {
12410 if (isPIC && !is64Bit) {
12411 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12412 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12416 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12417 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12418 false, false, false, 0);
12421 // The address of the thread local variable is the add of the thread
12422 // pointer with the offset of the variable.
12423 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12427 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12429 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12431 // Cygwin uses emutls.
12432 // FIXME: It may be EmulatedTLS-generic also for X86-Android.
12433 if (Subtarget->isTargetWindowsCygwin())
12434 return LowerToTLSEmulatedModel(GA, DAG);
12436 const GlobalValue *GV = GA->getGlobal();
12437 auto PtrVT = getPointerTy(DAG.getDataLayout());
12439 if (Subtarget->isTargetELF()) {
12440 if (DAG.getTarget().Options.EmulatedTLS)
12441 return LowerToTLSEmulatedModel(GA, DAG);
12442 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12444 case TLSModel::GeneralDynamic:
12445 if (Subtarget->is64Bit())
12446 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12447 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12448 case TLSModel::LocalDynamic:
12449 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12450 Subtarget->is64Bit());
12451 case TLSModel::InitialExec:
12452 case TLSModel::LocalExec:
12453 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12454 DAG.getTarget().getRelocationModel() ==
12457 llvm_unreachable("Unknown TLS model.");
12460 if (Subtarget->isTargetDarwin()) {
12461 // Darwin only has one model of TLS. Lower to that.
12462 unsigned char OpFlag = 0;
12463 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12464 X86ISD::WrapperRIP : X86ISD::Wrapper;
12466 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12467 // global base reg.
12468 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12469 !Subtarget->is64Bit();
12471 OpFlag = X86II::MO_TLVP_PIC_BASE;
12473 OpFlag = X86II::MO_TLVP;
12475 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12476 GA->getValueType(0),
12477 GA->getOffset(), OpFlag);
12478 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12480 // With PIC32, the address is actually $g + Offset.
12482 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12483 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12486 // Lowering the machine isd will make sure everything is in the right
12488 SDValue Chain = DAG.getEntryNode();
12489 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12490 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, DL, true), DL);
12491 SDValue Args[] = { Chain, Offset };
12492 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12494 DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, DL, true),
12495 DAG.getIntPtrConstant(0, DL, true), SDValue(), DL);
12497 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12498 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12499 MFI->setAdjustsStack(true);
12501 // And our return value (tls address) is in the standard call return value
12503 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12504 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12507 if (Subtarget->isTargetKnownWindowsMSVC() ||
12508 Subtarget->isTargetWindowsGNU()) {
12509 // Just use the implicit TLS architecture
12510 // Need to generate someting similar to:
12511 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12513 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12514 // mov rcx, qword [rdx+rcx*8]
12515 // mov eax, .tls$:tlsvar
12516 // [rax+rcx] contains the address
12517 // Windows 64bit: gs:0x58
12518 // Windows 32bit: fs:__tls_array
12521 SDValue Chain = DAG.getEntryNode();
12523 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12524 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12525 // use its literal value of 0x2C.
12526 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12527 ? Type::getInt8PtrTy(*DAG.getContext(),
12529 : Type::getInt32PtrTy(*DAG.getContext(),
12532 SDValue TlsArray = Subtarget->is64Bit()
12533 ? DAG.getIntPtrConstant(0x58, dl)
12534 : (Subtarget->isTargetWindowsGNU()
12535 ? DAG.getIntPtrConstant(0x2C, dl)
12536 : DAG.getExternalSymbol("_tls_array", PtrVT));
12538 SDValue ThreadPointer =
12539 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12543 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12544 res = ThreadPointer;
12546 // Load the _tls_index variable
12547 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12548 if (Subtarget->is64Bit())
12549 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12550 MachinePointerInfo(), MVT::i32, false, false,
12553 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12556 auto &DL = DAG.getDataLayout();
12558 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12559 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12561 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12564 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12567 // Get the offset of start of .tls section
12568 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12569 GA->getValueType(0),
12570 GA->getOffset(), X86II::MO_SECREL);
12571 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12573 // The address of the thread local variable is the add of the thread
12574 // pointer with the offset of the variable.
12575 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12578 llvm_unreachable("TLS not implemented for this target.");
12581 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12582 /// and take a 2 x i32 value to shift plus a shift amount.
12583 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12584 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12585 MVT VT = Op.getSimpleValueType();
12586 unsigned VTBits = VT.getSizeInBits();
12588 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12589 SDValue ShOpLo = Op.getOperand(0);
12590 SDValue ShOpHi = Op.getOperand(1);
12591 SDValue ShAmt = Op.getOperand(2);
12592 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12593 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12595 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12596 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12597 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12598 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12599 : DAG.getConstant(0, dl, VT);
12601 SDValue Tmp2, Tmp3;
12602 if (Op.getOpcode() == ISD::SHL_PARTS) {
12603 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12604 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12606 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12607 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12610 // If the shift amount is larger or equal than the width of a part we can't
12611 // rely on the results of shld/shrd. Insert a test and select the appropriate
12612 // values for large shift amounts.
12613 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12614 DAG.getConstant(VTBits, dl, MVT::i8));
12615 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12616 AndNode, DAG.getConstant(0, dl, MVT::i8));
12619 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12620 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12621 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12623 if (Op.getOpcode() == ISD::SHL_PARTS) {
12624 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12625 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12627 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12628 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12631 SDValue Ops[2] = { Lo, Hi };
12632 return DAG.getMergeValues(Ops, dl);
12635 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12636 SelectionDAG &DAG) const {
12637 SDValue Src = Op.getOperand(0);
12638 MVT SrcVT = Src.getSimpleValueType();
12639 MVT VT = Op.getSimpleValueType();
12642 if (SrcVT.isVector()) {
12643 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12644 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12645 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12646 DAG.getUNDEF(SrcVT)));
12648 if (SrcVT.getVectorElementType() == MVT::i1) {
12649 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12650 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12651 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12656 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12657 "Unknown SINT_TO_FP to lower!");
12659 // These are really Legal; return the operand so the caller accepts it as
12661 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12663 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12664 Subtarget->is64Bit()) {
12668 unsigned Size = SrcVT.getSizeInBits()/8;
12669 MachineFunction &MF = DAG.getMachineFunction();
12670 auto PtrVT = getPointerTy(MF.getDataLayout());
12671 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12672 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12673 SDValue Chain = DAG.getStore(
12674 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12675 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12677 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12680 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12682 SelectionDAG &DAG) const {
12686 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12688 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12690 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12692 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12694 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12695 MachineMemOperand *MMO;
12697 int SSFI = FI->getIndex();
12698 MMO = DAG.getMachineFunction().getMachineMemOperand(
12699 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12700 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12702 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12703 StackSlot = StackSlot.getOperand(1);
12705 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12706 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12708 Tys, Ops, SrcVT, MMO);
12711 Chain = Result.getValue(1);
12712 SDValue InFlag = Result.getValue(2);
12714 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12715 // shouldn't be necessary except that RFP cannot be live across
12716 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12717 MachineFunction &MF = DAG.getMachineFunction();
12718 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12719 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12720 auto PtrVT = getPointerTy(MF.getDataLayout());
12721 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12722 Tys = DAG.getVTList(MVT::Other);
12724 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12726 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12727 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12728 MachineMemOperand::MOStore, SSFISize, SSFISize);
12730 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12731 Ops, Op.getValueType(), MMO);
12732 Result = DAG.getLoad(
12733 Op.getValueType(), DL, Chain, StackSlot,
12734 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12735 false, false, false, 0);
12741 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12742 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12743 SelectionDAG &DAG) const {
12744 // This algorithm is not obvious. Here it is what we're trying to output:
12747 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12748 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12750 haddpd %xmm0, %xmm0
12752 pshufd $0x4e, %xmm0, %xmm1
12758 LLVMContext *Context = DAG.getContext();
12760 // Build some magic constants.
12761 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12762 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12763 auto PtrVT = getPointerTy(DAG.getDataLayout());
12764 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12766 SmallVector<Constant*,2> CV1;
12768 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12769 APInt(64, 0x4330000000000000ULL))));
12771 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12772 APInt(64, 0x4530000000000000ULL))));
12773 Constant *C1 = ConstantVector::get(CV1);
12774 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12776 // Load the 64-bit value into an XMM register.
12777 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12780 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12781 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12782 false, false, false, 16);
12784 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12787 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12788 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12789 false, false, false, 16);
12790 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12791 // TODO: Are there any fast-math-flags to propagate here?
12792 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12795 if (Subtarget->hasSSE3()) {
12796 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12797 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12799 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12800 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12802 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12803 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12806 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12807 DAG.getIntPtrConstant(0, dl));
12810 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12811 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12812 SelectionDAG &DAG) const {
12814 // FP constant to bias correct the final result.
12815 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12818 // Load the 32-bit value into an XMM register.
12819 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12822 // Zero out the upper parts of the register.
12823 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12825 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12826 DAG.getBitcast(MVT::v2f64, Load),
12827 DAG.getIntPtrConstant(0, dl));
12829 // Or the load with the bias.
12830 SDValue Or = DAG.getNode(
12831 ISD::OR, dl, MVT::v2i64,
12832 DAG.getBitcast(MVT::v2i64,
12833 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12834 DAG.getBitcast(MVT::v2i64,
12835 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12837 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12838 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12840 // Subtract the bias.
12841 // TODO: Are there any fast-math-flags to propagate here?
12842 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12844 // Handle final rounding.
12845 MVT DestVT = Op.getSimpleValueType();
12847 if (DestVT.bitsLT(MVT::f64))
12848 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12849 DAG.getIntPtrConstant(0, dl));
12850 if (DestVT.bitsGT(MVT::f64))
12851 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12853 // Handle final rounding.
12857 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12858 const X86Subtarget &Subtarget) {
12859 // The algorithm is the following:
12860 // #ifdef __SSE4_1__
12861 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12862 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12863 // (uint4) 0x53000000, 0xaa);
12865 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12866 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12868 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12869 // return (float4) lo + fhi;
12871 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12872 // reassociate the two FADDs, and if we do that, the algorithm fails
12873 // spectacularly (PR24512).
12874 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12875 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12876 // there's also the MachineCombiner reassociations happening on Machine IR.
12877 if (DAG.getTarget().Options.UnsafeFPMath)
12881 SDValue V = Op->getOperand(0);
12882 MVT VecIntVT = V.getSimpleValueType();
12883 bool Is128 = VecIntVT == MVT::v4i32;
12884 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12885 // If we convert to something else than the supported type, e.g., to v4f64,
12887 if (VecFloatVT != Op->getSimpleValueType(0))
12890 unsigned NumElts = VecIntVT.getVectorNumElements();
12891 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12892 "Unsupported custom type");
12893 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12895 // In the #idef/#else code, we have in common:
12896 // - The vector of constants:
12902 // Create the splat vector for 0x4b000000.
12903 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12904 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12905 CstLow, CstLow, CstLow, CstLow};
12906 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12907 makeArrayRef(&CstLowArray[0], NumElts));
12908 // Create the splat vector for 0x53000000.
12909 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12910 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12911 CstHigh, CstHigh, CstHigh, CstHigh};
12912 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12913 makeArrayRef(&CstHighArray[0], NumElts));
12915 // Create the right shift.
12916 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12917 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12918 CstShift, CstShift, CstShift, CstShift};
12919 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12920 makeArrayRef(&CstShiftArray[0], NumElts));
12921 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12924 if (Subtarget.hasSSE41()) {
12925 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12926 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12927 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12928 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12929 // Low will be bitcasted right away, so do not bother bitcasting back to its
12931 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12932 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12933 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12934 // (uint4) 0x53000000, 0xaa);
12935 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12936 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12937 // High will be bitcasted right away, so do not bother bitcasting back to
12938 // its original type.
12939 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12940 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12942 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12943 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12944 CstMask, CstMask, CstMask);
12945 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12946 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12947 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12949 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12950 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12953 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12954 SDValue CstFAdd = DAG.getConstantFP(
12955 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12956 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12957 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12958 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12959 makeArrayRef(&CstFAddArray[0], NumElts));
12961 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12962 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12963 // TODO: Are there any fast-math-flags to propagate here?
12965 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12966 // return (float4) lo + fhi;
12967 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12968 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12971 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12972 SelectionDAG &DAG) const {
12973 SDValue N0 = Op.getOperand(0);
12974 MVT SVT = N0.getSimpleValueType();
12977 switch (SVT.SimpleTy) {
12979 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12984 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12985 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12986 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12990 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12993 assert(Subtarget->hasAVX512());
12994 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12995 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12999 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
13000 SelectionDAG &DAG) const {
13001 SDValue N0 = Op.getOperand(0);
13003 auto PtrVT = getPointerTy(DAG.getDataLayout());
13005 if (Op.getSimpleValueType().isVector())
13006 return lowerUINT_TO_FP_vec(Op, DAG);
13008 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
13009 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
13010 // the optimization here.
13011 if (DAG.SignBitIsZero(N0))
13012 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
13014 MVT SrcVT = N0.getSimpleValueType();
13015 MVT DstVT = Op.getSimpleValueType();
13017 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
13018 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
13019 // Conversions from unsigned i32 to f32/f64 are legal,
13020 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
13024 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
13025 return LowerUINT_TO_FP_i64(Op, DAG);
13026 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
13027 return LowerUINT_TO_FP_i32(Op, DAG);
13028 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
13031 // Make a 64-bit buffer, and use it to build an FILD.
13032 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
13033 if (SrcVT == MVT::i32) {
13034 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
13035 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
13036 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13037 StackSlot, MachinePointerInfo(),
13039 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
13040 OffsetSlot, MachinePointerInfo(),
13042 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
13046 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
13047 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
13048 StackSlot, MachinePointerInfo(),
13050 // For i64 source, we need to add the appropriate power of 2 if the input
13051 // was negative. This is the same as the optimization in
13052 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
13053 // we must be careful to do the computation in x87 extended precision, not
13054 // in SSE. (The generic code can't know it's OK to do this, or how to.)
13055 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
13056 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
13057 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
13058 MachineMemOperand::MOLoad, 8, 8);
13060 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
13061 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
13062 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
13065 APInt FF(32, 0x5F800000ULL);
13067 // Check whether the sign bit is set.
13068 SDValue SignSet = DAG.getSetCC(
13069 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
13070 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
13072 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
13073 SDValue FudgePtr = DAG.getConstantPool(
13074 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
13076 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
13077 SDValue Zero = DAG.getIntPtrConstant(0, dl);
13078 SDValue Four = DAG.getIntPtrConstant(4, dl);
13079 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
13081 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
13083 // Load the value out, extending it from f32 to f80.
13084 // FIXME: Avoid the extend by constructing the right constant pool?
13085 SDValue Fudge = DAG.getExtLoad(
13086 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
13087 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
13088 false, false, false, 4);
13089 // Extend everything to 80 bits to force it to be done on x87.
13090 // TODO: Are there any fast-math-flags to propagate here?
13091 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
13092 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
13093 DAG.getIntPtrConstant(0, dl));
13096 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
13097 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
13098 // just return an <SDValue(), SDValue()> pair.
13099 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
13100 // to i16, i32 or i64, and we lower it to a legal sequence.
13101 // If lowered to the final integer result we return a <result, SDValue()> pair.
13102 // Otherwise we lower it to a sequence ending with a FIST, return a
13103 // <FIST, StackSlot> pair, and the caller is responsible for loading
13104 // the final integer result from StackSlot.
13105 std::pair<SDValue,SDValue>
13106 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
13107 bool IsSigned, bool IsReplace) const {
13110 EVT DstTy = Op.getValueType();
13111 EVT TheVT = Op.getOperand(0).getValueType();
13112 auto PtrVT = getPointerTy(DAG.getDataLayout());
13114 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
13115 // f16 must be promoted before using the lowering in this routine.
13116 // fp128 does not use this lowering.
13117 return std::make_pair(SDValue(), SDValue());
13120 // If using FIST to compute an unsigned i64, we'll need some fixup
13121 // to handle values above the maximum signed i64. A FIST is always
13122 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
13123 bool UnsignedFixup = !IsSigned &&
13124 DstTy == MVT::i64 &&
13125 (!Subtarget->is64Bit() ||
13126 !isScalarFPTypeInSSEReg(TheVT));
13128 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
13129 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
13130 // The low 32 bits of the fist result will have the correct uint32 result.
13131 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
13135 assert(DstTy.getSimpleVT() <= MVT::i64 &&
13136 DstTy.getSimpleVT() >= MVT::i16 &&
13137 "Unknown FP_TO_INT to lower!");
13139 // These are really Legal.
13140 if (DstTy == MVT::i32 &&
13141 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13142 return std::make_pair(SDValue(), SDValue());
13143 if (Subtarget->is64Bit() &&
13144 DstTy == MVT::i64 &&
13145 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
13146 return std::make_pair(SDValue(), SDValue());
13148 // We lower FP->int64 into FISTP64 followed by a load from a temporary
13150 MachineFunction &MF = DAG.getMachineFunction();
13151 unsigned MemSize = DstTy.getSizeInBits()/8;
13152 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13153 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13156 switch (DstTy.getSimpleVT().SimpleTy) {
13157 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
13158 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
13159 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
13160 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
13163 SDValue Chain = DAG.getEntryNode();
13164 SDValue Value = Op.getOperand(0);
13165 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
13167 if (UnsignedFixup) {
13169 // Conversion to unsigned i64 is implemented with a select,
13170 // depending on whether the source value fits in the range
13171 // of a signed i64. Let Thresh be the FP equivalent of
13172 // 0x8000000000000000ULL.
13174 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
13175 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
13176 // Fist-to-mem64 FistSrc
13177 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
13178 // to XOR'ing the high 32 bits with Adjust.
13180 // Being a power of 2, Thresh is exactly representable in all FP formats.
13181 // For X87 we'd like to use the smallest FP type for this constant, but
13182 // for DAG type consistency we have to match the FP operand type.
13184 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
13185 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
13186 bool LosesInfo = false;
13187 if (TheVT == MVT::f64)
13188 // The rounding mode is irrelevant as the conversion should be exact.
13189 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
13191 else if (TheVT == MVT::f80)
13192 Status = Thresh.convert(APFloat::x87DoubleExtended,
13193 APFloat::rmNearestTiesToEven, &LosesInfo);
13195 assert(Status == APFloat::opOK && !LosesInfo &&
13196 "FP conversion should have been exact");
13198 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
13200 SDValue Cmp = DAG.getSetCC(DL,
13201 getSetCCResultType(DAG.getDataLayout(),
13202 *DAG.getContext(), TheVT),
13203 Value, ThreshVal, ISD::SETLT);
13204 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
13205 DAG.getConstant(0, DL, MVT::i32),
13206 DAG.getConstant(0x80000000, DL, MVT::i32));
13207 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
13208 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
13209 *DAG.getContext(), TheVT),
13210 Value, ThreshVal, ISD::SETLT);
13211 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
13214 // FIXME This causes a redundant load/store if the SSE-class value is already
13215 // in memory, such as if it is on the callstack.
13216 if (isScalarFPTypeInSSEReg(TheVT)) {
13217 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13218 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13219 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13221 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13223 Chain, StackSlot, DAG.getValueType(TheVT)
13226 MachineMemOperand *MMO =
13227 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13228 MachineMemOperand::MOLoad, MemSize, MemSize);
13229 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13230 Chain = Value.getValue(1);
13231 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13232 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13235 MachineMemOperand *MMO =
13236 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13237 MachineMemOperand::MOStore, MemSize, MemSize);
13239 if (UnsignedFixup) {
13241 // Insert the FIST, load its result as two i32's,
13242 // and XOR the high i32 with Adjust.
13244 SDValue FistOps[] = { Chain, Value, StackSlot };
13245 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13246 FistOps, DstTy, MMO);
13248 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13249 MachinePointerInfo(),
13250 false, false, false, 0);
13251 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13252 DAG.getConstant(4, DL, PtrVT));
13254 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13255 MachinePointerInfo(),
13256 false, false, false, 0);
13257 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13259 if (Subtarget->is64Bit()) {
13260 // Join High32 and Low32 into a 64-bit result.
13261 // (High32 << 32) | Low32
13262 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13263 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13264 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13265 DAG.getConstant(32, DL, MVT::i8));
13266 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13267 return std::make_pair(Result, SDValue());
13270 SDValue ResultOps[] = { Low32, High32 };
13272 SDValue pair = IsReplace
13273 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13274 : DAG.getMergeValues(ResultOps, DL);
13275 return std::make_pair(pair, SDValue());
13277 // Build the FP_TO_INT*_IN_MEM
13278 SDValue Ops[] = { Chain, Value, StackSlot };
13279 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13281 return std::make_pair(FIST, StackSlot);
13285 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13286 const X86Subtarget *Subtarget) {
13287 MVT VT = Op->getSimpleValueType(0);
13288 SDValue In = Op->getOperand(0);
13289 MVT InVT = In.getSimpleValueType();
13292 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13293 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13295 // Optimize vectors in AVX mode:
13298 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13299 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13300 // Concat upper and lower parts.
13303 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13304 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13305 // Concat upper and lower parts.
13308 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13309 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13310 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13313 if (Subtarget->hasInt256())
13314 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13316 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13317 SDValue Undef = DAG.getUNDEF(InVT);
13318 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13319 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13320 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13322 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13323 VT.getVectorNumElements()/2);
13325 OpLo = DAG.getBitcast(HVT, OpLo);
13326 OpHi = DAG.getBitcast(HVT, OpHi);
13328 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13331 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13332 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13333 MVT VT = Op->getSimpleValueType(0);
13334 SDValue In = Op->getOperand(0);
13335 MVT InVT = In.getSimpleValueType();
13337 unsigned int NumElts = VT.getVectorNumElements();
13338 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13341 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13342 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13344 assert(InVT.getVectorElementType() == MVT::i1);
13345 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13347 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13349 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13351 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13352 if (VT.is512BitVector())
13354 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13357 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13358 SelectionDAG &DAG) {
13359 if (Subtarget->hasFp256())
13360 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13366 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13367 SelectionDAG &DAG) {
13369 MVT VT = Op.getSimpleValueType();
13370 SDValue In = Op.getOperand(0);
13371 MVT SVT = In.getSimpleValueType();
13373 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13374 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13376 if (Subtarget->hasFp256())
13377 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13380 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13381 VT.getVectorNumElements() != SVT.getVectorNumElements());
13385 static SDValue LowerTruncateVecI1(SDValue Op, SelectionDAG &DAG,
13386 const X86Subtarget *Subtarget) {
13389 MVT VT = Op.getSimpleValueType();
13390 SDValue In = Op.getOperand(0);
13391 MVT InVT = In.getSimpleValueType();
13393 assert(VT.getVectorElementType() == MVT::i1 && "Unexected vector type.");
13395 // Shift LSB to MSB and use VPMOVB2M - SKX.
13396 unsigned ShiftInx = InVT.getScalarSizeInBits() - 1;
13397 if ((InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13398 Subtarget->hasBWI()) || // legal, will go to VPMOVB2M, VPMOVW2M
13399 ((InVT.is256BitVector() || InVT.is128BitVector()) &&
13400 InVT.getScalarSizeInBits() <= 16 && Subtarget->hasBWI() &&
13401 Subtarget->hasVLX())) { // legal, will go to VPMOVB2M, VPMOVW2M
13402 // Shift packed bytes not supported natively, bitcast to dword
13403 MVT ExtVT = MVT::getVectorVT(MVT::i16, InVT.getSizeInBits()/16);
13404 SDValue ShiftNode = DAG.getNode(ISD::SHL, DL, ExtVT,
13405 DAG.getBitcast(ExtVT, In),
13406 DAG.getConstant(ShiftInx, DL, ExtVT));
13407 ShiftNode = DAG.getBitcast(InVT, ShiftNode);
13408 return DAG.getNode(X86ISD::CVT2MASK, DL, VT, ShiftNode);
13410 if ((InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13411 Subtarget->hasDQI()) || // legal, will go to VPMOVD2M, VPMOVQ2M
13412 ((InVT.is256BitVector() || InVT.is128BitVector()) &&
13413 InVT.getScalarSizeInBits() >= 32 && Subtarget->hasDQI() &&
13414 Subtarget->hasVLX())) { // legal, will go to VPMOVD2M, VPMOVQ2M
13416 SDValue ShiftNode = DAG.getNode(ISD::SHL, DL, InVT, In,
13417 DAG.getConstant(ShiftInx, DL, InVT));
13418 return DAG.getNode(X86ISD::CVT2MASK, DL, VT, ShiftNode);
13421 // Shift LSB to MSB, extend if necessary and use TESTM.
13422 unsigned NumElts = InVT.getVectorNumElements();
13423 if (InVT.getSizeInBits() < 512 &&
13424 (InVT.getScalarType() == MVT::i8 || InVT.getScalarType() == MVT::i16 ||
13425 !Subtarget->hasVLX())) {
13426 assert((NumElts == 8 || NumElts == 16) && "Unexected vector type.");
13428 // TESTD/Q should be used (if BW supported we use CVT2MASK above),
13429 // so vector should be extended to packed dword/qword.
13430 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(512/NumElts), NumElts);
13431 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13433 ShiftInx = InVT.getScalarSizeInBits() - 1;
13436 SDValue ShiftNode = DAG.getNode(ISD::SHL, DL, InVT, In,
13437 DAG.getConstant(ShiftInx, DL, InVT));
13438 return DAG.getNode(X86ISD::TESTM, DL, VT, ShiftNode, ShiftNode);
13441 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13443 MVT VT = Op.getSimpleValueType();
13444 SDValue In = Op.getOperand(0);
13445 MVT InVT = In.getSimpleValueType();
13447 if (VT == MVT::i1) {
13448 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13449 "Invalid scalar TRUNCATE operation");
13450 if (InVT.getSizeInBits() >= 32)
13452 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13453 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13455 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13456 "Invalid TRUNCATE operation");
13458 if (VT.getVectorElementType() == MVT::i1)
13459 return LowerTruncateVecI1(Op, DAG, Subtarget);
13461 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13462 if (Subtarget->hasAVX512()) {
13463 // word to byte only under BWI
13464 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13465 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13466 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13467 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13469 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13470 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13471 if (Subtarget->hasInt256()) {
13472 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13473 In = DAG.getBitcast(MVT::v8i32, In);
13474 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13476 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13477 DAG.getIntPtrConstant(0, DL));
13480 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13481 DAG.getIntPtrConstant(0, DL));
13482 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13483 DAG.getIntPtrConstant(2, DL));
13484 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13485 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13486 static const int ShufMask[] = {0, 2, 4, 6};
13487 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13490 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13491 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13492 if (Subtarget->hasInt256()) {
13493 In = DAG.getBitcast(MVT::v32i8, In);
13495 SmallVector<SDValue,32> pshufbMask;
13496 for (unsigned i = 0; i < 2; ++i) {
13497 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13498 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13499 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13500 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13501 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13502 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13503 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13504 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13505 for (unsigned j = 0; j < 8; ++j)
13506 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13508 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13509 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13510 In = DAG.getBitcast(MVT::v4i64, In);
13512 static const int ShufMask[] = {0, 2, -1, -1};
13513 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13515 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13516 DAG.getIntPtrConstant(0, DL));
13517 return DAG.getBitcast(VT, In);
13520 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13521 DAG.getIntPtrConstant(0, DL));
13523 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13524 DAG.getIntPtrConstant(4, DL));
13526 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13527 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13529 // The PSHUFB mask:
13530 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13531 -1, -1, -1, -1, -1, -1, -1, -1};
13533 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13534 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13535 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13537 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13538 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13540 // The MOVLHPS Mask:
13541 static const int ShufMask2[] = {0, 1, 4, 5};
13542 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13543 return DAG.getBitcast(MVT::v8i16, res);
13546 // Handle truncation of V256 to V128 using shuffles.
13547 if (!VT.is128BitVector() || !InVT.is256BitVector())
13550 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13552 unsigned NumElems = VT.getVectorNumElements();
13553 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13555 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13556 // Prepare truncation shuffle mask
13557 for (unsigned i = 0; i != NumElems; ++i)
13558 MaskVec[i] = i * 2;
13559 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13560 DAG.getUNDEF(NVT), &MaskVec[0]);
13561 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13562 DAG.getIntPtrConstant(0, DL));
13565 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13566 SelectionDAG &DAG) const {
13567 assert(!Op.getSimpleValueType().isVector());
13569 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13570 /*IsSigned=*/ true, /*IsReplace=*/ false);
13571 SDValue FIST = Vals.first, StackSlot = Vals.second;
13572 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13573 if (!FIST.getNode())
13576 if (StackSlot.getNode())
13577 // Load the result.
13578 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13579 FIST, StackSlot, MachinePointerInfo(),
13580 false, false, false, 0);
13582 // The node is the result.
13586 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13587 SelectionDAG &DAG) const {
13588 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13589 /*IsSigned=*/ false, /*IsReplace=*/ false);
13590 SDValue FIST = Vals.first, StackSlot = Vals.second;
13591 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13592 if (!FIST.getNode())
13595 if (StackSlot.getNode())
13596 // Load the result.
13597 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13598 FIST, StackSlot, MachinePointerInfo(),
13599 false, false, false, 0);
13601 // The node is the result.
13605 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13607 MVT VT = Op.getSimpleValueType();
13608 SDValue In = Op.getOperand(0);
13609 MVT SVT = In.getSimpleValueType();
13611 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13613 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13614 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13615 In, DAG.getUNDEF(SVT)));
13618 /// The only differences between FABS and FNEG are the mask and the logic op.
13619 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13620 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13621 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13622 "Wrong opcode for lowering FABS or FNEG.");
13624 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13626 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13627 // into an FNABS. We'll lower the FABS after that if it is still in use.
13629 for (SDNode *User : Op->uses())
13630 if (User->getOpcode() == ISD::FNEG)
13634 MVT VT = Op.getSimpleValueType();
13636 bool IsF128 = (VT == MVT::f128);
13638 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13639 // decide if we should generate a 16-byte constant mask when we only need 4 or
13640 // 8 bytes for the scalar case.
13646 if (VT.isVector()) {
13648 EltVT = VT.getVectorElementType();
13649 NumElts = VT.getVectorNumElements();
13650 } else if (IsF128) {
13651 // SSE instructions are used for optimized f128 logical operations.
13652 LogicVT = MVT::f128;
13656 // There are no scalar bitwise logical SSE/AVX instructions, so we
13657 // generate a 16-byte vector constant and logic op even for the scalar case.
13658 // Using a 16-byte mask allows folding the load of the mask with
13659 // the logic op, so it can save (~4 bytes) on code size.
13660 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13662 NumElts = (VT == MVT::f64) ? 2 : 4;
13665 unsigned EltBits = EltVT.getSizeInBits();
13666 LLVMContext *Context = DAG.getContext();
13667 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13669 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13670 Constant *C = ConstantInt::get(*Context, MaskElt);
13671 C = ConstantVector::getSplat(NumElts, C);
13672 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13673 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13674 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13676 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13677 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13678 false, false, false, Alignment);
13680 SDValue Op0 = Op.getOperand(0);
13681 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13683 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13684 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13686 if (VT.isVector() || IsF128)
13687 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13689 // For the scalar case extend to a 128-bit vector, perform the logic op,
13690 // and extract the scalar result back out.
13691 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13692 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13693 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13694 DAG.getIntPtrConstant(0, dl));
13697 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13698 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13699 LLVMContext *Context = DAG.getContext();
13700 SDValue Op0 = Op.getOperand(0);
13701 SDValue Op1 = Op.getOperand(1);
13703 MVT VT = Op.getSimpleValueType();
13704 MVT SrcVT = Op1.getSimpleValueType();
13705 bool IsF128 = (VT == MVT::f128);
13707 // If second operand is smaller, extend it first.
13708 if (SrcVT.bitsLT(VT)) {
13709 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13712 // And if it is bigger, shrink it first.
13713 if (SrcVT.bitsGT(VT)) {
13714 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13718 // At this point the operands and the result should have the same
13719 // type, and that won't be f80 since that is not custom lowered.
13720 assert((VT == MVT::f64 || VT == MVT::f32 || IsF128) &&
13721 "Unexpected type in LowerFCOPYSIGN");
13723 const fltSemantics &Sem =
13724 VT == MVT::f64 ? APFloat::IEEEdouble :
13725 (IsF128 ? APFloat::IEEEquad : APFloat::IEEEsingle);
13726 const unsigned SizeInBits = VT.getSizeInBits();
13728 SmallVector<Constant *, 4> CV(
13729 VT == MVT::f64 ? 2 : (IsF128 ? 1 : 4),
13730 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13732 // First, clear all bits but the sign bit from the second operand (sign).
13733 CV[0] = ConstantFP::get(*Context,
13734 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13735 Constant *C = ConstantVector::get(CV);
13736 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13737 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13739 // Perform all logic operations as 16-byte vectors because there are no
13740 // scalar FP logic instructions in SSE. This allows load folding of the
13741 // constants into the logic instructions.
13742 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : (IsF128 ? MVT::f128 : MVT::v4f32);
13744 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13745 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13746 false, false, false, 16);
13748 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13749 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13751 // Next, clear the sign bit from the first operand (magnitude).
13752 // If it's a constant, we can clear it here.
13753 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13754 APFloat APF = Op0CN->getValueAPF();
13755 // If the magnitude is a positive zero, the sign bit alone is enough.
13756 if (APF.isPosZero())
13757 return IsF128 ? SignBit :
13758 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13759 DAG.getIntPtrConstant(0, dl));
13761 CV[0] = ConstantFP::get(*Context, APF);
13763 CV[0] = ConstantFP::get(
13765 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13767 C = ConstantVector::get(CV);
13768 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13770 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13771 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13772 false, false, false, 16);
13773 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13774 if (!isa<ConstantFPSDNode>(Op0)) {
13776 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13777 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13779 // OR the magnitude value with the sign bit.
13780 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13781 return IsF128 ? Val :
13782 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13783 DAG.getIntPtrConstant(0, dl));
13786 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13787 SDValue N0 = Op.getOperand(0);
13789 MVT VT = Op.getSimpleValueType();
13791 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13792 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13793 DAG.getConstant(1, dl, VT));
13794 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13797 // Check whether an OR'd tree is PTEST-able.
13798 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13799 SelectionDAG &DAG) {
13800 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13802 if (!Subtarget->hasSSE41())
13805 if (!Op->hasOneUse())
13808 SDNode *N = Op.getNode();
13811 SmallVector<SDValue, 8> Opnds;
13812 DenseMap<SDValue, unsigned> VecInMap;
13813 SmallVector<SDValue, 8> VecIns;
13814 EVT VT = MVT::Other;
13816 // Recognize a special case where a vector is casted into wide integer to
13818 Opnds.push_back(N->getOperand(0));
13819 Opnds.push_back(N->getOperand(1));
13821 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13822 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13823 // BFS traverse all OR'd operands.
13824 if (I->getOpcode() == ISD::OR) {
13825 Opnds.push_back(I->getOperand(0));
13826 Opnds.push_back(I->getOperand(1));
13827 // Re-evaluate the number of nodes to be traversed.
13828 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13832 // Quit if a non-EXTRACT_VECTOR_ELT
13833 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13836 // Quit if without a constant index.
13837 SDValue Idx = I->getOperand(1);
13838 if (!isa<ConstantSDNode>(Idx))
13841 SDValue ExtractedFromVec = I->getOperand(0);
13842 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13843 if (M == VecInMap.end()) {
13844 VT = ExtractedFromVec.getValueType();
13845 // Quit if not 128/256-bit vector.
13846 if (!VT.is128BitVector() && !VT.is256BitVector())
13848 // Quit if not the same type.
13849 if (VecInMap.begin() != VecInMap.end() &&
13850 VT != VecInMap.begin()->first.getValueType())
13852 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13853 VecIns.push_back(ExtractedFromVec);
13855 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13858 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13859 "Not extracted from 128-/256-bit vector.");
13861 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13863 for (DenseMap<SDValue, unsigned>::const_iterator
13864 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13865 // Quit if not all elements are used.
13866 if (I->second != FullMask)
13870 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13872 // Cast all vectors into TestVT for PTEST.
13873 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13874 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13876 // If more than one full vectors are evaluated, OR them first before PTEST.
13877 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13878 // Each iteration will OR 2 nodes and append the result until there is only
13879 // 1 node left, i.e. the final OR'd value of all vectors.
13880 SDValue LHS = VecIns[Slot];
13881 SDValue RHS = VecIns[Slot + 1];
13882 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13885 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13886 VecIns.back(), VecIns.back());
13889 /// \brief return true if \c Op has a use that doesn't just read flags.
13890 static bool hasNonFlagsUse(SDValue Op) {
13891 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13893 SDNode *User = *UI;
13894 unsigned UOpNo = UI.getOperandNo();
13895 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13896 // Look pass truncate.
13897 UOpNo = User->use_begin().getOperandNo();
13898 User = *User->use_begin();
13901 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13902 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13908 /// Emit nodes that will be selected as "test Op0,Op0", or something
13910 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13911 SelectionDAG &DAG) const {
13912 if (Op.getValueType() == MVT::i1) {
13913 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13914 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13915 DAG.getConstant(0, dl, MVT::i8));
13917 // CF and OF aren't always set the way we want. Determine which
13918 // of these we need.
13919 bool NeedCF = false;
13920 bool NeedOF = false;
13923 case X86::COND_A: case X86::COND_AE:
13924 case X86::COND_B: case X86::COND_BE:
13927 case X86::COND_G: case X86::COND_GE:
13928 case X86::COND_L: case X86::COND_LE:
13929 case X86::COND_O: case X86::COND_NO: {
13930 // Check if we really need to set the
13931 // Overflow flag. If NoSignedWrap is present
13932 // that is not actually needed.
13933 switch (Op->getOpcode()) {
13938 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13939 if (BinNode->Flags.hasNoSignedWrap())
13949 // See if we can use the EFLAGS value from the operand instead of
13950 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13951 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13952 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13953 // Emit a CMP with 0, which is the TEST pattern.
13954 //if (Op.getValueType() == MVT::i1)
13955 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13956 // DAG.getConstant(0, MVT::i1));
13957 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13958 DAG.getConstant(0, dl, Op.getValueType()));
13960 unsigned Opcode = 0;
13961 unsigned NumOperands = 0;
13963 // Truncate operations may prevent the merge of the SETCC instruction
13964 // and the arithmetic instruction before it. Attempt to truncate the operands
13965 // of the arithmetic instruction and use a reduced bit-width instruction.
13966 bool NeedTruncation = false;
13967 SDValue ArithOp = Op;
13968 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13969 SDValue Arith = Op->getOperand(0);
13970 // Both the trunc and the arithmetic op need to have one user each.
13971 if (Arith->hasOneUse())
13972 switch (Arith.getOpcode()) {
13979 NeedTruncation = true;
13985 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13986 // which may be the result of a CAST. We use the variable 'Op', which is the
13987 // non-casted variable when we check for possible users.
13988 switch (ArithOp.getOpcode()) {
13990 // Due to an isel shortcoming, be conservative if this add is likely to be
13991 // selected as part of a load-modify-store instruction. When the root node
13992 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13993 // uses of other nodes in the match, such as the ADD in this case. This
13994 // leads to the ADD being left around and reselected, with the result being
13995 // two adds in the output. Alas, even if none our users are stores, that
13996 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13997 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13998 // climbing the DAG back to the root, and it doesn't seem to be worth the
14000 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14001 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14002 if (UI->getOpcode() != ISD::CopyToReg &&
14003 UI->getOpcode() != ISD::SETCC &&
14004 UI->getOpcode() != ISD::STORE)
14007 if (ConstantSDNode *C =
14008 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
14009 // An add of one will be selected as an INC.
14010 if (C->isOne() && !Subtarget->slowIncDec()) {
14011 Opcode = X86ISD::INC;
14016 // An add of negative one (subtract of one) will be selected as a DEC.
14017 if (C->isAllOnesValue() && !Subtarget->slowIncDec()) {
14018 Opcode = X86ISD::DEC;
14024 // Otherwise use a regular EFLAGS-setting add.
14025 Opcode = X86ISD::ADD;
14030 // If we have a constant logical shift that's only used in a comparison
14031 // against zero turn it into an equivalent AND. This allows turning it into
14032 // a TEST instruction later.
14033 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
14034 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
14035 EVT VT = Op.getValueType();
14036 unsigned BitWidth = VT.getSizeInBits();
14037 unsigned ShAmt = Op->getConstantOperandVal(1);
14038 if (ShAmt >= BitWidth) // Avoid undefined shifts.
14040 APInt Mask = ArithOp.getOpcode() == ISD::SRL
14041 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
14042 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
14043 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
14045 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
14046 DAG.getConstant(Mask, dl, VT));
14047 DAG.ReplaceAllUsesWith(Op, New);
14053 // If the primary and result isn't used, don't bother using X86ISD::AND,
14054 // because a TEST instruction will be better.
14055 if (!hasNonFlagsUse(Op))
14061 // Due to the ISEL shortcoming noted above, be conservative if this op is
14062 // likely to be selected as part of a load-modify-store instruction.
14063 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
14064 UE = Op.getNode()->use_end(); UI != UE; ++UI)
14065 if (UI->getOpcode() == ISD::STORE)
14068 // Otherwise use a regular EFLAGS-setting instruction.
14069 switch (ArithOp.getOpcode()) {
14070 default: llvm_unreachable("unexpected operator!");
14071 case ISD::SUB: Opcode = X86ISD::SUB; break;
14072 case ISD::XOR: Opcode = X86ISD::XOR; break;
14073 case ISD::AND: Opcode = X86ISD::AND; break;
14075 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
14076 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
14077 if (EFLAGS.getNode())
14080 Opcode = X86ISD::OR;
14094 return SDValue(Op.getNode(), 1);
14100 // If we found that truncation is beneficial, perform the truncation and
14102 if (NeedTruncation) {
14103 EVT VT = Op.getValueType();
14104 SDValue WideVal = Op->getOperand(0);
14105 EVT WideVT = WideVal.getValueType();
14106 unsigned ConvertedOp = 0;
14107 // Use a target machine opcode to prevent further DAGCombine
14108 // optimizations that may separate the arithmetic operations
14109 // from the setcc node.
14110 switch (WideVal.getOpcode()) {
14112 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
14113 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
14114 case ISD::AND: ConvertedOp = X86ISD::AND; break;
14115 case ISD::OR: ConvertedOp = X86ISD::OR; break;
14116 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
14120 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14121 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
14122 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
14123 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
14124 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
14130 // Emit a CMP with 0, which is the TEST pattern.
14131 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
14132 DAG.getConstant(0, dl, Op.getValueType()));
14134 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
14135 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
14137 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
14138 DAG.ReplaceAllUsesWith(Op, New);
14139 return SDValue(New.getNode(), 1);
14142 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
14144 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
14145 SDLoc dl, SelectionDAG &DAG) const {
14146 if (isNullConstant(Op1))
14147 return EmitTest(Op0, X86CC, dl, DAG);
14149 assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
14150 "Unexpected comparison operation for MVT::i1 operands");
14152 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
14153 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
14154 // Do the comparison at i32 if it's smaller, besides the Atom case.
14155 // This avoids subregister aliasing issues. Keep the smaller reference
14156 // if we're optimizing for size, however, as that'll allow better folding
14157 // of memory operations.
14158 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
14159 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
14160 !Subtarget->isAtom()) {
14161 unsigned ExtendOp =
14162 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
14163 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
14164 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
14166 // Use SUB instead of CMP to enable CSE between SUB and CMP.
14167 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
14168 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
14170 return SDValue(Sub.getNode(), 1);
14172 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
14175 /// Convert a comparison if required by the subtarget.
14176 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
14177 SelectionDAG &DAG) const {
14178 // If the subtarget does not support the FUCOMI instruction, floating-point
14179 // comparisons have to be converted.
14180 if (Subtarget->hasCMov() ||
14181 Cmp.getOpcode() != X86ISD::CMP ||
14182 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
14183 !Cmp.getOperand(1).getValueType().isFloatingPoint())
14186 // The instruction selector will select an FUCOM instruction instead of
14187 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
14188 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
14189 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
14191 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
14192 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
14193 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
14194 DAG.getConstant(8, dl, MVT::i8));
14195 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
14197 // Some 64-bit targets lack SAHF support, but they do support FCOMI.
14198 assert(Subtarget->hasLAHFSAHF() && "Target doesn't support SAHF or FCOMI?");
14199 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
14202 /// The minimum architected relative accuracy is 2^-12. We need one
14203 /// Newton-Raphson step to have a good float result (24 bits of precision).
14204 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
14205 DAGCombinerInfo &DCI,
14206 unsigned &RefinementSteps,
14207 bool &UseOneConstNR) const {
14208 EVT VT = Op.getValueType();
14209 const char *RecipOp;
14211 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
14212 // TODO: Add support for AVX512 (v16f32).
14213 // It is likely not profitable to do this for f64 because a double-precision
14214 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
14215 // instructions: convert to single, rsqrtss, convert back to double, refine
14216 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
14217 // along with FMA, this could be a throughput win.
14218 if (VT == MVT::f32 && Subtarget->hasSSE1())
14220 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14221 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14222 RecipOp = "vec-sqrtf";
14226 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14227 if (!Recips.isEnabled(RecipOp))
14230 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14231 UseOneConstNR = false;
14232 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
14235 /// The minimum architected relative accuracy is 2^-12. We need one
14236 /// Newton-Raphson step to have a good float result (24 bits of precision).
14237 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
14238 DAGCombinerInfo &DCI,
14239 unsigned &RefinementSteps) const {
14240 EVT VT = Op.getValueType();
14241 const char *RecipOp;
14243 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
14244 // TODO: Add support for AVX512 (v16f32).
14245 // It is likely not profitable to do this for f64 because a double-precision
14246 // reciprocal estimate with refinement on x86 prior to FMA requires
14247 // 15 instructions: convert to single, rcpss, convert back to double, refine
14248 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
14249 // along with FMA, this could be a throughput win.
14250 if (VT == MVT::f32 && Subtarget->hasSSE1())
14252 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14253 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14254 RecipOp = "vec-divf";
14258 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14259 if (!Recips.isEnabled(RecipOp))
14262 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14263 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14266 /// If we have at least two divisions that use the same divisor, convert to
14267 /// multplication by a reciprocal. This may need to be adjusted for a given
14268 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14269 /// This is because we still need one division to calculate the reciprocal and
14270 /// then we need two multiplies by that reciprocal as replacements for the
14271 /// original divisions.
14272 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14276 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14277 /// if it's possible.
14278 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14279 SDLoc dl, SelectionDAG &DAG) const {
14280 SDValue Op0 = And.getOperand(0);
14281 SDValue Op1 = And.getOperand(1);
14282 if (Op0.getOpcode() == ISD::TRUNCATE)
14283 Op0 = Op0.getOperand(0);
14284 if (Op1.getOpcode() == ISD::TRUNCATE)
14285 Op1 = Op1.getOperand(0);
14288 if (Op1.getOpcode() == ISD::SHL)
14289 std::swap(Op0, Op1);
14290 if (Op0.getOpcode() == ISD::SHL) {
14291 if (isOneConstant(Op0.getOperand(0))) {
14292 // If we looked past a truncate, check that it's only truncating away
14294 unsigned BitWidth = Op0.getValueSizeInBits();
14295 unsigned AndBitWidth = And.getValueSizeInBits();
14296 if (BitWidth > AndBitWidth) {
14298 DAG.computeKnownBits(Op0, Zeros, Ones);
14299 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14303 RHS = Op0.getOperand(1);
14305 } else if (Op1.getOpcode() == ISD::Constant) {
14306 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14307 uint64_t AndRHSVal = AndRHS->getZExtValue();
14308 SDValue AndLHS = Op0;
14310 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14311 LHS = AndLHS.getOperand(0);
14312 RHS = AndLHS.getOperand(1);
14315 // Use BT if the immediate can't be encoded in a TEST instruction.
14316 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14318 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14322 if (LHS.getNode()) {
14323 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14324 // instruction. Since the shift amount is in-range-or-undefined, we know
14325 // that doing a bittest on the i32 value is ok. We extend to i32 because
14326 // the encoding for the i16 version is larger than the i32 version.
14327 // Also promote i16 to i32 for performance / code size reason.
14328 if (LHS.getValueType() == MVT::i8 ||
14329 LHS.getValueType() == MVT::i16)
14330 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14332 // If the operand types disagree, extend the shift amount to match. Since
14333 // BT ignores high bits (like shifts) we can use anyextend.
14334 if (LHS.getValueType() != RHS.getValueType())
14335 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14337 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14338 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14339 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14340 DAG.getConstant(Cond, dl, MVT::i8), BT);
14346 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14348 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14353 // SSE Condition code mapping:
14362 switch (SetCCOpcode) {
14363 default: llvm_unreachable("Unexpected SETCC condition");
14365 case ISD::SETEQ: SSECC = 0; break;
14367 case ISD::SETGT: Swap = true; // Fallthrough
14369 case ISD::SETOLT: SSECC = 1; break;
14371 case ISD::SETGE: Swap = true; // Fallthrough
14373 case ISD::SETOLE: SSECC = 2; break;
14374 case ISD::SETUO: SSECC = 3; break;
14376 case ISD::SETNE: SSECC = 4; break;
14377 case ISD::SETULE: Swap = true; // Fallthrough
14378 case ISD::SETUGE: SSECC = 5; break;
14379 case ISD::SETULT: Swap = true; // Fallthrough
14380 case ISD::SETUGT: SSECC = 6; break;
14381 case ISD::SETO: SSECC = 7; break;
14383 case ISD::SETONE: SSECC = 8; break;
14386 std::swap(Op0, Op1);
14391 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14392 // ones, and then concatenate the result back.
14393 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14394 MVT VT = Op.getSimpleValueType();
14396 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14397 "Unsupported value type for operation");
14399 unsigned NumElems = VT.getVectorNumElements();
14401 SDValue CC = Op.getOperand(2);
14403 // Extract the LHS vectors
14404 SDValue LHS = Op.getOperand(0);
14405 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14406 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14408 // Extract the RHS vectors
14409 SDValue RHS = Op.getOperand(1);
14410 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14411 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14413 // Issue the operation on the smaller types and concatenate the result back
14414 MVT EltVT = VT.getVectorElementType();
14415 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14416 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14417 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14418 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14421 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14422 SDValue Op0 = Op.getOperand(0);
14423 SDValue Op1 = Op.getOperand(1);
14424 SDValue CC = Op.getOperand(2);
14425 MVT VT = Op.getSimpleValueType();
14428 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14429 "Unexpected type for boolean compare operation");
14430 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14431 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14432 DAG.getConstant(-1, dl, VT));
14433 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14434 DAG.getConstant(-1, dl, VT));
14435 switch (SetCCOpcode) {
14436 default: llvm_unreachable("Unexpected SETCC condition");
14438 // (x == y) -> ~(x ^ y)
14439 return DAG.getNode(ISD::XOR, dl, VT,
14440 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14441 DAG.getConstant(-1, dl, VT));
14443 // (x != y) -> (x ^ y)
14444 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14447 // (x > y) -> (x & ~y)
14448 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14451 // (x < y) -> (~x & y)
14452 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14455 // (x <= y) -> (~x | y)
14456 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14459 // (x >=y) -> (x | ~y)
14460 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14464 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14465 const X86Subtarget *Subtarget) {
14466 SDValue Op0 = Op.getOperand(0);
14467 SDValue Op1 = Op.getOperand(1);
14468 SDValue CC = Op.getOperand(2);
14469 MVT VT = Op.getSimpleValueType();
14472 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14473 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14474 "Cannot set masked compare for this operation");
14476 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14478 bool Unsigned = false;
14481 switch (SetCCOpcode) {
14482 default: llvm_unreachable("Unexpected SETCC condition");
14483 case ISD::SETNE: SSECC = 4; break;
14484 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14485 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14486 case ISD::SETLT: Swap = true; //fall-through
14487 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14488 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14489 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14490 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14491 case ISD::SETULE: Unsigned = true; //fall-through
14492 case ISD::SETLE: SSECC = 2; break;
14496 std::swap(Op0, Op1);
14498 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14499 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14500 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14501 DAG.getConstant(SSECC, dl, MVT::i8));
14504 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14505 /// operand \p Op1. If non-trivial (for example because it's not constant)
14506 /// return an empty value.
14507 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14509 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14513 MVT VT = Op1.getSimpleValueType();
14514 MVT EVT = VT.getVectorElementType();
14515 unsigned n = VT.getVectorNumElements();
14516 SmallVector<SDValue, 8> ULTOp1;
14518 for (unsigned i = 0; i < n; ++i) {
14519 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14520 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14523 // Avoid underflow.
14524 APInt Val = Elt->getAPIntValue();
14528 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14531 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14534 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14535 SelectionDAG &DAG) {
14536 SDValue Op0 = Op.getOperand(0);
14537 SDValue Op1 = Op.getOperand(1);
14538 SDValue CC = Op.getOperand(2);
14539 MVT VT = Op.getSimpleValueType();
14540 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14541 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14546 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14547 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14550 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14551 unsigned Opc = X86ISD::CMPP;
14552 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14553 assert(VT.getVectorNumElements() <= 16);
14554 Opc = X86ISD::CMPM;
14556 // In the two special cases we can't handle, emit two comparisons.
14559 unsigned CombineOpc;
14560 if (SetCCOpcode == ISD::SETUEQ) {
14561 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14563 assert(SetCCOpcode == ISD::SETONE);
14564 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14567 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14568 DAG.getConstant(CC0, dl, MVT::i8));
14569 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14570 DAG.getConstant(CC1, dl, MVT::i8));
14571 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14573 // Handle all other FP comparisons here.
14574 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14575 DAG.getConstant(SSECC, dl, MVT::i8));
14578 MVT VTOp0 = Op0.getSimpleValueType();
14579 assert(VTOp0 == Op1.getSimpleValueType() &&
14580 "Expected operands with same type!");
14581 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14582 "Invalid number of packed elements for source and destination!");
14584 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14585 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14586 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14587 // legalizer firstly checks if the first operand in input to the setcc has
14588 // a legal type. If so, then it promotes the return type to that same type.
14589 // Otherwise, the return type is promoted to the 'next legal type' which,
14590 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14592 // We reach this code only if the following two conditions are met:
14593 // 1. Both return type and operand type have been promoted to wider types
14594 // by the type legalizer.
14595 // 2. The original operand type has been promoted to a 256-bit vector.
14597 // Note that condition 2. only applies for AVX targets.
14598 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14599 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14602 // The non-AVX512 code below works under the assumption that source and
14603 // destination types are the same.
14604 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14605 "Value types for source and destination must be the same!");
14607 // Break 256-bit integer vector compare into smaller ones.
14608 if (VT.is256BitVector() && !Subtarget->hasInt256())
14609 return Lower256IntVSETCC(Op, DAG);
14611 MVT OpVT = Op1.getSimpleValueType();
14612 if (OpVT.getVectorElementType() == MVT::i1)
14613 return LowerBoolVSETCC_AVX512(Op, DAG);
14615 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14616 if (Subtarget->hasAVX512()) {
14617 if (Op1.getSimpleValueType().is512BitVector() ||
14618 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14619 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14620 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14622 // In AVX-512 architecture setcc returns mask with i1 elements,
14623 // But there is no compare instruction for i8 and i16 elements in KNL.
14624 // We are not talking about 512-bit operands in this case, these
14625 // types are illegal.
14627 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14628 OpVT.getVectorElementType().getSizeInBits() >= 8))
14629 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14630 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14633 // Lower using XOP integer comparisons.
14634 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14635 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14636 // Translate compare code to XOP PCOM compare mode.
14637 unsigned CmpMode = 0;
14638 switch (SetCCOpcode) {
14639 default: llvm_unreachable("Unexpected SETCC condition");
14641 case ISD::SETLT: CmpMode = 0x00; break;
14643 case ISD::SETLE: CmpMode = 0x01; break;
14645 case ISD::SETGT: CmpMode = 0x02; break;
14647 case ISD::SETGE: CmpMode = 0x03; break;
14648 case ISD::SETEQ: CmpMode = 0x04; break;
14649 case ISD::SETNE: CmpMode = 0x05; break;
14652 // Are we comparing unsigned or signed integers?
14653 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14654 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14656 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14657 DAG.getConstant(CmpMode, dl, MVT::i8));
14660 // We are handling one of the integer comparisons here. Since SSE only has
14661 // GT and EQ comparisons for integer, swapping operands and multiple
14662 // operations may be required for some comparisons.
14664 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14665 bool Subus = false;
14667 switch (SetCCOpcode) {
14668 default: llvm_unreachable("Unexpected SETCC condition");
14669 case ISD::SETNE: Invert = true;
14670 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14671 case ISD::SETLT: Swap = true;
14672 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14673 case ISD::SETGE: Swap = true;
14674 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14675 Invert = true; break;
14676 case ISD::SETULT: Swap = true;
14677 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14678 FlipSigns = true; break;
14679 case ISD::SETUGE: Swap = true;
14680 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14681 FlipSigns = true; Invert = true; break;
14684 // Special case: Use min/max operations for SETULE/SETUGE
14685 MVT VET = VT.getVectorElementType();
14687 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14688 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14691 switch (SetCCOpcode) {
14693 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14694 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14697 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14700 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14701 if (!MinMax && hasSubus) {
14702 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14704 // t = psubus Op0, Op1
14705 // pcmpeq t, <0..0>
14706 switch (SetCCOpcode) {
14708 case ISD::SETULT: {
14709 // If the comparison is against a constant we can turn this into a
14710 // setule. With psubus, setule does not require a swap. This is
14711 // beneficial because the constant in the register is no longer
14712 // destructed as the destination so it can be hoisted out of a loop.
14713 // Only do this pre-AVX since vpcmp* is no longer destructive.
14714 if (Subtarget->hasAVX())
14716 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14717 if (ULEOp1.getNode()) {
14719 Subus = true; Invert = false; Swap = false;
14723 // Psubus is better than flip-sign because it requires no inversion.
14724 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14725 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14729 Opc = X86ISD::SUBUS;
14735 std::swap(Op0, Op1);
14737 // Check that the operation in question is available (most are plain SSE2,
14738 // but PCMPGTQ and PCMPEQQ have different requirements).
14739 if (VT == MVT::v2i64) {
14740 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14741 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14743 // First cast everything to the right type.
14744 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14745 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14747 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14748 // bits of the inputs before performing those operations. The lower
14749 // compare is always unsigned.
14752 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14754 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14755 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14756 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14757 Sign, Zero, Sign, Zero);
14759 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14760 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14762 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14763 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14764 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14766 // Create masks for only the low parts/high parts of the 64 bit integers.
14767 static const int MaskHi[] = { 1, 1, 3, 3 };
14768 static const int MaskLo[] = { 0, 0, 2, 2 };
14769 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14770 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14771 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14773 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14774 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14777 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14779 return DAG.getBitcast(VT, Result);
14782 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14783 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14784 // pcmpeqd + pshufd + pand.
14785 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14787 // First cast everything to the right type.
14788 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14789 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14792 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14794 // Make sure the lower and upper halves are both all-ones.
14795 static const int Mask[] = { 1, 0, 3, 2 };
14796 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14797 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14800 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14802 return DAG.getBitcast(VT, Result);
14806 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14807 // bits of the inputs before performing those operations.
14809 MVT EltVT = VT.getVectorElementType();
14810 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14812 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14813 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14816 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14818 // If the logical-not of the result is required, perform that now.
14820 Result = DAG.getNOT(dl, Result, VT);
14823 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14826 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14827 getZeroVector(VT, Subtarget, DAG, dl));
14832 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14834 MVT VT = Op.getSimpleValueType();
14836 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14838 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14839 && "SetCC type must be 8-bit or 1-bit integer");
14840 SDValue Op0 = Op.getOperand(0);
14841 SDValue Op1 = Op.getOperand(1);
14843 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14845 // Optimize to BT if possible.
14846 // Lower (X & (1 << N)) == 0 to BT(X, N).
14847 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14848 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14849 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14850 isNullConstant(Op1) &&
14851 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14852 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14854 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14859 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14861 if ((isOneConstant(Op1) || isNullConstant(Op1)) &&
14862 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14864 // If the input is a setcc, then reuse the input setcc or use a new one with
14865 // the inverted condition.
14866 if (Op0.getOpcode() == X86ISD::SETCC) {
14867 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14868 bool Invert = (CC == ISD::SETNE) ^ isNullConstant(Op1);
14872 CCode = X86::GetOppositeBranchCondition(CCode);
14873 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14874 DAG.getConstant(CCode, dl, MVT::i8),
14875 Op0.getOperand(1));
14877 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14881 if ((Op0.getValueType() == MVT::i1) && isOneConstant(Op1) &&
14882 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14884 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14885 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14888 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14889 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14890 if (X86CC == X86::COND_INVALID)
14893 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14894 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14895 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14896 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14898 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14902 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14903 SDValue LHS = Op.getOperand(0);
14904 SDValue RHS = Op.getOperand(1);
14905 SDValue Carry = Op.getOperand(2);
14906 SDValue Cond = Op.getOperand(3);
14909 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14910 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14912 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14913 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14914 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14915 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14916 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14919 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14920 static bool isX86LogicalCmp(SDValue Op) {
14921 unsigned Opc = Op.getNode()->getOpcode();
14922 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14923 Opc == X86ISD::SAHF)
14925 if (Op.getResNo() == 1 &&
14926 (Opc == X86ISD::ADD ||
14927 Opc == X86ISD::SUB ||
14928 Opc == X86ISD::ADC ||
14929 Opc == X86ISD::SBB ||
14930 Opc == X86ISD::SMUL ||
14931 Opc == X86ISD::UMUL ||
14932 Opc == X86ISD::INC ||
14933 Opc == X86ISD::DEC ||
14934 Opc == X86ISD::OR ||
14935 Opc == X86ISD::XOR ||
14936 Opc == X86ISD::AND))
14939 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14945 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14946 if (V.getOpcode() != ISD::TRUNCATE)
14949 SDValue VOp0 = V.getOperand(0);
14950 unsigned InBits = VOp0.getValueSizeInBits();
14951 unsigned Bits = V.getValueSizeInBits();
14952 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14955 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14956 bool addTest = true;
14957 SDValue Cond = Op.getOperand(0);
14958 SDValue Op1 = Op.getOperand(1);
14959 SDValue Op2 = Op.getOperand(2);
14961 MVT VT = Op1.getSimpleValueType();
14964 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14965 // are available or VBLENDV if AVX is available.
14966 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14967 if (Cond.getOpcode() == ISD::SETCC &&
14968 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14969 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14970 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14971 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14972 int SSECC = translateX86FSETCC(
14973 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14976 if (Subtarget->hasAVX512()) {
14977 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14978 DAG.getConstant(SSECC, DL, MVT::i8));
14979 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14982 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14983 DAG.getConstant(SSECC, DL, MVT::i8));
14985 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14986 // of 3 logic instructions for size savings and potentially speed.
14987 // Unfortunately, there is no scalar form of VBLENDV.
14989 // If either operand is a constant, don't try this. We can expect to
14990 // optimize away at least one of the logic instructions later in that
14991 // case, so that sequence would be faster than a variable blend.
14993 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14994 // uses XMM0 as the selection register. That may need just as many
14995 // instructions as the AND/ANDN/OR sequence due to register moves, so
14998 if (Subtarget->hasAVX() &&
14999 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
15001 // Convert to vectors, do a VSELECT, and convert back to scalar.
15002 // All of the conversions should be optimized away.
15004 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
15005 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
15006 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
15007 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
15009 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
15010 VCmp = DAG.getBitcast(VCmpVT, VCmp);
15012 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
15014 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
15015 VSel, DAG.getIntPtrConstant(0, DL));
15017 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
15018 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
15019 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
15023 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
15025 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
15026 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
15027 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
15028 Op1Scalar = Op1.getOperand(0);
15030 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
15031 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
15032 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
15033 Op2Scalar = Op2.getOperand(0);
15034 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
15035 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
15036 Op1Scalar.getValueType(),
15037 Cond, Op1Scalar, Op2Scalar);
15038 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
15039 return DAG.getBitcast(VT, newSelect);
15040 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
15041 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
15042 DAG.getIntPtrConstant(0, DL));
15046 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
15047 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
15048 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
15049 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
15050 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
15051 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
15052 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
15054 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
15057 if (Cond.getOpcode() == ISD::SETCC) {
15058 SDValue NewCond = LowerSETCC(Cond, DAG);
15059 if (NewCond.getNode())
15063 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
15064 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
15065 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
15066 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
15067 if (Cond.getOpcode() == X86ISD::SETCC &&
15068 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
15069 isNullConstant(Cond.getOperand(1).getOperand(1))) {
15070 SDValue Cmp = Cond.getOperand(1);
15072 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
15074 if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
15075 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
15076 SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
15078 SDValue CmpOp0 = Cmp.getOperand(0);
15079 // Apply further optimizations for special cases
15080 // (select (x != 0), -1, 0) -> neg & sbb
15081 // (select (x == 0), 0, -1) -> neg & sbb
15082 if (isNullConstant(Y) &&
15083 (isAllOnesConstant(Op1) == (CondCode == X86::COND_NE))) {
15084 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
15085 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
15086 DAG.getConstant(0, DL,
15087 CmpOp0.getValueType()),
15089 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15090 DAG.getConstant(X86::COND_B, DL, MVT::i8),
15091 SDValue(Neg.getNode(), 1));
15095 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
15096 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
15097 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15099 SDValue Res = // Res = 0 or -1.
15100 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15101 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
15103 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_E))
15104 Res = DAG.getNOT(DL, Res, Res.getValueType());
15106 if (!isNullConstant(Op2))
15107 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
15112 // Look past (and (setcc_carry (cmp ...)), 1).
15113 if (Cond.getOpcode() == ISD::AND &&
15114 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15115 isOneConstant(Cond.getOperand(1)))
15116 Cond = Cond.getOperand(0);
15118 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15119 // setting operand in place of the X86ISD::SETCC.
15120 unsigned CondOpcode = Cond.getOpcode();
15121 if (CondOpcode == X86ISD::SETCC ||
15122 CondOpcode == X86ISD::SETCC_CARRY) {
15123 CC = Cond.getOperand(0);
15125 SDValue Cmp = Cond.getOperand(1);
15126 unsigned Opc = Cmp.getOpcode();
15127 MVT VT = Op.getSimpleValueType();
15129 bool IllegalFPCMov = false;
15130 if (VT.isFloatingPoint() && !VT.isVector() &&
15131 !isScalarFPTypeInSSEReg(VT)) // FPStack?
15132 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
15134 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
15135 Opc == X86ISD::BT) { // FIXME
15139 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15140 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15141 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15142 Cond.getOperand(0).getValueType() != MVT::i8)) {
15143 SDValue LHS = Cond.getOperand(0);
15144 SDValue RHS = Cond.getOperand(1);
15145 unsigned X86Opcode;
15148 switch (CondOpcode) {
15149 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15150 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15151 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15152 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15153 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15154 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15155 default: llvm_unreachable("unexpected overflowing operator");
15157 if (CondOpcode == ISD::UMULO)
15158 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15161 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15163 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
15165 if (CondOpcode == ISD::UMULO)
15166 Cond = X86Op.getValue(2);
15168 Cond = X86Op.getValue(1);
15170 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
15175 // Look past the truncate if the high bits are known zero.
15176 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15177 Cond = Cond.getOperand(0);
15179 // We know the result of AND is compared against zero. Try to match
15181 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15182 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
15183 CC = NewSetCC.getOperand(0);
15184 Cond = NewSetCC.getOperand(1);
15191 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
15192 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
15195 // a < b ? -1 : 0 -> RES = ~setcc_carry
15196 // a < b ? 0 : -1 -> RES = setcc_carry
15197 // a >= b ? -1 : 0 -> RES = setcc_carry
15198 // a >= b ? 0 : -1 -> RES = ~setcc_carry
15199 if (Cond.getOpcode() == X86ISD::SUB) {
15200 Cond = ConvertCmpIfNecessary(Cond, DAG);
15201 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
15203 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
15204 (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
15205 (isNullConstant(Op1) || isNullConstant(Op2))) {
15206 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
15207 DAG.getConstant(X86::COND_B, DL, MVT::i8),
15209 if (isAllOnesConstant(Op1) != (CondCode == X86::COND_B))
15210 return DAG.getNOT(DL, Res, Res.getValueType());
15215 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
15216 // widen the cmov and push the truncate through. This avoids introducing a new
15217 // branch during isel and doesn't add any extensions.
15218 if (Op.getValueType() == MVT::i8 &&
15219 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
15220 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
15221 if (T1.getValueType() == T2.getValueType() &&
15222 // Blacklist CopyFromReg to avoid partial register stalls.
15223 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
15224 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
15225 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
15226 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
15230 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
15231 // condition is true.
15232 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
15233 SDValue Ops[] = { Op2, Op1, CC, Cond };
15234 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15237 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
15238 const X86Subtarget *Subtarget,
15239 SelectionDAG &DAG) {
15240 MVT VT = Op->getSimpleValueType(0);
15241 SDValue In = Op->getOperand(0);
15242 MVT InVT = In.getSimpleValueType();
15243 MVT VTElt = VT.getVectorElementType();
15244 MVT InVTElt = InVT.getVectorElementType();
15248 if ((InVTElt == MVT::i1) &&
15249 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15250 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15252 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15253 VTElt.getSizeInBits() <= 16)) ||
15255 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15256 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15258 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15259 VTElt.getSizeInBits() >= 32))))
15260 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15262 unsigned int NumElts = VT.getVectorNumElements();
15264 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15267 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15268 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15269 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15270 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15273 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15274 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15276 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15279 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15281 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15282 if (VT.is512BitVector())
15284 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15287 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15288 const X86Subtarget *Subtarget,
15289 SelectionDAG &DAG) {
15290 SDValue In = Op->getOperand(0);
15291 MVT VT = Op->getSimpleValueType(0);
15292 MVT InVT = In.getSimpleValueType();
15293 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15295 MVT InSVT = InVT.getVectorElementType();
15296 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15298 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15300 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15305 // SSE41 targets can use the pmovsx* instructions directly.
15306 if (Subtarget->hasSSE41())
15307 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15309 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15313 // As SRAI is only available on i16/i32 types, we expand only up to i32
15314 // and handle i64 separately.
15315 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15316 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15317 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15318 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15319 Curr = DAG.getBitcast(CurrVT, Curr);
15322 SDValue SignExt = Curr;
15323 if (CurrVT != InVT) {
15324 unsigned SignExtShift =
15325 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15326 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15327 DAG.getConstant(SignExtShift, dl, MVT::i8));
15333 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15334 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15335 DAG.getConstant(31, dl, MVT::i8));
15336 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15337 return DAG.getBitcast(VT, Ext);
15343 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15344 SelectionDAG &DAG) {
15345 MVT VT = Op->getSimpleValueType(0);
15346 SDValue In = Op->getOperand(0);
15347 MVT InVT = In.getSimpleValueType();
15350 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15351 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15353 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15354 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15355 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15358 if (Subtarget->hasInt256())
15359 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15361 // Optimize vectors in AVX mode
15362 // Sign extend v8i16 to v8i32 and
15365 // Divide input vector into two parts
15366 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15367 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15368 // concat the vectors to original VT
15370 unsigned NumElems = InVT.getVectorNumElements();
15371 SDValue Undef = DAG.getUNDEF(InVT);
15373 SmallVector<int,8> ShufMask1(NumElems, -1);
15374 for (unsigned i = 0; i != NumElems/2; ++i)
15377 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15379 SmallVector<int,8> ShufMask2(NumElems, -1);
15380 for (unsigned i = 0; i != NumElems/2; ++i)
15381 ShufMask2[i] = i + NumElems/2;
15383 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15385 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15386 VT.getVectorNumElements()/2);
15388 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15389 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15391 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15394 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15395 // may emit an illegal shuffle but the expansion is still better than scalar
15396 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15397 // we'll emit a shuffle and a arithmetic shift.
15398 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15399 // TODO: It is possible to support ZExt by zeroing the undef values during
15400 // the shuffle phase or after the shuffle.
15401 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15402 SelectionDAG &DAG) {
15403 MVT RegVT = Op.getSimpleValueType();
15404 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15405 assert(RegVT.isInteger() &&
15406 "We only custom lower integer vector sext loads.");
15408 // Nothing useful we can do without SSE2 shuffles.
15409 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15411 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15413 EVT MemVT = Ld->getMemoryVT();
15414 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15415 unsigned RegSz = RegVT.getSizeInBits();
15417 ISD::LoadExtType Ext = Ld->getExtensionType();
15419 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15420 && "Only anyext and sext are currently implemented.");
15421 assert(MemVT != RegVT && "Cannot extend to the same type");
15422 assert(MemVT.isVector() && "Must load a vector from memory");
15424 unsigned NumElems = RegVT.getVectorNumElements();
15425 unsigned MemSz = MemVT.getSizeInBits();
15426 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15428 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15429 // The only way in which we have a legal 256-bit vector result but not the
15430 // integer 256-bit operations needed to directly lower a sextload is if we
15431 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15432 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15433 // correctly legalized. We do this late to allow the canonical form of
15434 // sextload to persist throughout the rest of the DAG combiner -- it wants
15435 // to fold together any extensions it can, and so will fuse a sign_extend
15436 // of an sextload into a sextload targeting a wider value.
15438 if (MemSz == 128) {
15439 // Just switch this to a normal load.
15440 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15441 "it must be a legal 128-bit vector "
15443 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15444 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15445 Ld->isInvariant(), Ld->getAlignment());
15447 assert(MemSz < 128 &&
15448 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15449 // Do an sext load to a 128-bit vector type. We want to use the same
15450 // number of elements, but elements half as wide. This will end up being
15451 // recursively lowered by this routine, but will succeed as we definitely
15452 // have all the necessary features if we're using AVX1.
15454 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15455 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15457 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15458 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15459 Ld->isNonTemporal(), Ld->isInvariant(),
15460 Ld->getAlignment());
15463 // Replace chain users with the new chain.
15464 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15465 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15467 // Finally, do a normal sign-extend to the desired register.
15468 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15471 // All sizes must be a power of two.
15472 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15473 "Non-power-of-two elements are not custom lowered!");
15475 // Attempt to load the original value using scalar loads.
15476 // Find the largest scalar type that divides the total loaded size.
15477 MVT SclrLoadTy = MVT::i8;
15478 for (MVT Tp : MVT::integer_valuetypes()) {
15479 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15484 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15485 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15487 SclrLoadTy = MVT::f64;
15489 // Calculate the number of scalar loads that we need to perform
15490 // in order to load our vector from memory.
15491 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15493 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15494 "Can only lower sext loads with a single scalar load!");
15496 unsigned loadRegZize = RegSz;
15497 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15500 // Represent our vector as a sequence of elements which are the
15501 // largest scalar that we can load.
15502 EVT LoadUnitVecVT = EVT::getVectorVT(
15503 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15505 // Represent the data using the same element type that is stored in
15506 // memory. In practice, we ''widen'' MemVT.
15508 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15509 loadRegZize / MemVT.getScalarSizeInBits());
15511 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15512 "Invalid vector type");
15514 // We can't shuffle using an illegal type.
15515 assert(TLI.isTypeLegal(WideVecVT) &&
15516 "We only lower types that form legal widened vector types");
15518 SmallVector<SDValue, 8> Chains;
15519 SDValue Ptr = Ld->getBasePtr();
15520 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15521 TLI.getPointerTy(DAG.getDataLayout()));
15522 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15524 for (unsigned i = 0; i < NumLoads; ++i) {
15525 // Perform a single load.
15526 SDValue ScalarLoad =
15527 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15528 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15529 Ld->getAlignment());
15530 Chains.push_back(ScalarLoad.getValue(1));
15531 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15532 // another round of DAGCombining.
15534 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15536 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15537 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15539 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15542 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15544 // Bitcast the loaded value to a vector of the original element type, in
15545 // the size of the target vector type.
15546 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15547 unsigned SizeRatio = RegSz / MemSz;
15549 if (Ext == ISD::SEXTLOAD) {
15550 // If we have SSE4.1, we can directly emit a VSEXT node.
15551 if (Subtarget->hasSSE41()) {
15552 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15553 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15557 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15559 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15560 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15562 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15563 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15567 // Redistribute the loaded elements into the different locations.
15568 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15569 for (unsigned i = 0; i != NumElems; ++i)
15570 ShuffleVec[i * SizeRatio] = i;
15572 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15573 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15575 // Bitcast to the requested type.
15576 Shuff = DAG.getBitcast(RegVT, Shuff);
15577 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15581 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15582 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15583 // from the AND / OR.
15584 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15585 Opc = Op.getOpcode();
15586 if (Opc != ISD::OR && Opc != ISD::AND)
15588 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15589 Op.getOperand(0).hasOneUse() &&
15590 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15591 Op.getOperand(1).hasOneUse());
15594 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15595 // 1 and that the SETCC node has a single use.
15596 static bool isXor1OfSetCC(SDValue Op) {
15597 if (Op.getOpcode() != ISD::XOR)
15599 if (isOneConstant(Op.getOperand(1)))
15600 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15601 Op.getOperand(0).hasOneUse();
15605 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15606 bool addTest = true;
15607 SDValue Chain = Op.getOperand(0);
15608 SDValue Cond = Op.getOperand(1);
15609 SDValue Dest = Op.getOperand(2);
15612 bool Inverted = false;
15614 if (Cond.getOpcode() == ISD::SETCC) {
15615 // Check for setcc([su]{add,sub,mul}o == 0).
15616 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15617 isNullConstant(Cond.getOperand(1)) &&
15618 Cond.getOperand(0).getResNo() == 1 &&
15619 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15620 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15621 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15622 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15623 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15624 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15626 Cond = Cond.getOperand(0);
15628 SDValue NewCond = LowerSETCC(Cond, DAG);
15629 if (NewCond.getNode())
15634 // FIXME: LowerXALUO doesn't handle these!!
15635 else if (Cond.getOpcode() == X86ISD::ADD ||
15636 Cond.getOpcode() == X86ISD::SUB ||
15637 Cond.getOpcode() == X86ISD::SMUL ||
15638 Cond.getOpcode() == X86ISD::UMUL)
15639 Cond = LowerXALUO(Cond, DAG);
15642 // Look pass (and (setcc_carry (cmp ...)), 1).
15643 if (Cond.getOpcode() == ISD::AND &&
15644 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY &&
15645 isOneConstant(Cond.getOperand(1)))
15646 Cond = Cond.getOperand(0);
15648 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15649 // setting operand in place of the X86ISD::SETCC.
15650 unsigned CondOpcode = Cond.getOpcode();
15651 if (CondOpcode == X86ISD::SETCC ||
15652 CondOpcode == X86ISD::SETCC_CARRY) {
15653 CC = Cond.getOperand(0);
15655 SDValue Cmp = Cond.getOperand(1);
15656 unsigned Opc = Cmp.getOpcode();
15657 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15658 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15662 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15666 // These can only come from an arithmetic instruction with overflow,
15667 // e.g. SADDO, UADDO.
15668 Cond = Cond.getNode()->getOperand(1);
15674 CondOpcode = Cond.getOpcode();
15675 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15676 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15677 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15678 Cond.getOperand(0).getValueType() != MVT::i8)) {
15679 SDValue LHS = Cond.getOperand(0);
15680 SDValue RHS = Cond.getOperand(1);
15681 unsigned X86Opcode;
15684 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15685 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15687 switch (CondOpcode) {
15688 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15690 if (isOneConstant(RHS)) {
15691 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15694 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15695 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15697 if (isOneConstant(RHS)) {
15698 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15701 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15702 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15703 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15704 default: llvm_unreachable("unexpected overflowing operator");
15707 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15708 if (CondOpcode == ISD::UMULO)
15709 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15712 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15714 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15716 if (CondOpcode == ISD::UMULO)
15717 Cond = X86Op.getValue(2);
15719 Cond = X86Op.getValue(1);
15721 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15725 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15726 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15727 if (CondOpc == ISD::OR) {
15728 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15729 // two branches instead of an explicit OR instruction with a
15731 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15732 isX86LogicalCmp(Cmp)) {
15733 CC = Cond.getOperand(0).getOperand(0);
15734 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15735 Chain, Dest, CC, Cmp);
15736 CC = Cond.getOperand(1).getOperand(0);
15740 } else { // ISD::AND
15741 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15742 // two branches instead of an explicit AND instruction with a
15743 // separate test. However, we only do this if this block doesn't
15744 // have a fall-through edge, because this requires an explicit
15745 // jmp when the condition is false.
15746 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15747 isX86LogicalCmp(Cmp) &&
15748 Op.getNode()->hasOneUse()) {
15749 X86::CondCode CCode =
15750 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15751 CCode = X86::GetOppositeBranchCondition(CCode);
15752 CC = DAG.getConstant(CCode, dl, MVT::i8);
15753 SDNode *User = *Op.getNode()->use_begin();
15754 // Look for an unconditional branch following this conditional branch.
15755 // We need this because we need to reverse the successors in order
15756 // to implement FCMP_OEQ.
15757 if (User->getOpcode() == ISD::BR) {
15758 SDValue FalseBB = User->getOperand(1);
15760 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15761 assert(NewBR == User);
15765 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15766 Chain, Dest, CC, Cmp);
15767 X86::CondCode CCode =
15768 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15769 CCode = X86::GetOppositeBranchCondition(CCode);
15770 CC = DAG.getConstant(CCode, dl, MVT::i8);
15776 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15777 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15778 // It should be transformed during dag combiner except when the condition
15779 // is set by a arithmetics with overflow node.
15780 X86::CondCode CCode =
15781 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15782 CCode = X86::GetOppositeBranchCondition(CCode);
15783 CC = DAG.getConstant(CCode, dl, MVT::i8);
15784 Cond = Cond.getOperand(0).getOperand(1);
15786 } else if (Cond.getOpcode() == ISD::SETCC &&
15787 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15788 // For FCMP_OEQ, we can emit
15789 // two branches instead of an explicit AND instruction with a
15790 // separate test. However, we only do this if this block doesn't
15791 // have a fall-through edge, because this requires an explicit
15792 // jmp when the condition is false.
15793 if (Op.getNode()->hasOneUse()) {
15794 SDNode *User = *Op.getNode()->use_begin();
15795 // Look for an unconditional branch following this conditional branch.
15796 // We need this because we need to reverse the successors in order
15797 // to implement FCMP_OEQ.
15798 if (User->getOpcode() == ISD::BR) {
15799 SDValue FalseBB = User->getOperand(1);
15801 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15802 assert(NewBR == User);
15806 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15807 Cond.getOperand(0), Cond.getOperand(1));
15808 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15809 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15810 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15811 Chain, Dest, CC, Cmp);
15812 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15817 } else if (Cond.getOpcode() == ISD::SETCC &&
15818 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15819 // For FCMP_UNE, we can emit
15820 // two branches instead of an explicit AND instruction with a
15821 // separate test. However, we only do this if this block doesn't
15822 // have a fall-through edge, because this requires an explicit
15823 // jmp when the condition is false.
15824 if (Op.getNode()->hasOneUse()) {
15825 SDNode *User = *Op.getNode()->use_begin();
15826 // Look for an unconditional branch following this conditional branch.
15827 // We need this because we need to reverse the successors in order
15828 // to implement FCMP_UNE.
15829 if (User->getOpcode() == ISD::BR) {
15830 SDValue FalseBB = User->getOperand(1);
15832 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15833 assert(NewBR == User);
15836 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15837 Cond.getOperand(0), Cond.getOperand(1));
15838 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15839 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15840 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15841 Chain, Dest, CC, Cmp);
15842 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15852 // Look pass the truncate if the high bits are known zero.
15853 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15854 Cond = Cond.getOperand(0);
15856 // We know the result of AND is compared against zero. Try to match
15858 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15859 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15860 CC = NewSetCC.getOperand(0);
15861 Cond = NewSetCC.getOperand(1);
15868 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15869 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15870 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15872 Cond = ConvertCmpIfNecessary(Cond, DAG);
15873 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15874 Chain, Dest, CC, Cond);
15877 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15878 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15879 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15880 // that the guard pages used by the OS virtual memory manager are allocated in
15881 // correct sequence.
15883 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15884 SelectionDAG &DAG) const {
15885 MachineFunction &MF = DAG.getMachineFunction();
15886 bool SplitStack = MF.shouldSplitStack();
15887 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15892 SDNode *Node = Op.getNode();
15893 SDValue Chain = Op.getOperand(0);
15894 SDValue Size = Op.getOperand(1);
15895 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15896 EVT VT = Node->getValueType(0);
15898 // Chain the dynamic stack allocation so that it doesn't modify the stack
15899 // pointer when other instructions are using the stack.
15900 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
15902 bool Is64Bit = Subtarget->is64Bit();
15903 MVT SPTy = getPointerTy(DAG.getDataLayout());
15907 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15908 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15909 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15910 " not tell us which reg is the stack pointer!");
15911 EVT VT = Node->getValueType(0);
15912 SDValue Tmp3 = Node->getOperand(2);
15914 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15915 Chain = SP.getValue(1);
15916 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15917 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15918 unsigned StackAlign = TFI.getStackAlignment();
15919 Result = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15920 if (Align > StackAlign)
15921 Result = DAG.getNode(ISD::AND, dl, VT, Result,
15922 DAG.getConstant(-(uint64_t)Align, dl, VT));
15923 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Result); // Output chain
15924 } else if (SplitStack) {
15925 MachineRegisterInfo &MRI = MF.getRegInfo();
15928 // The 64 bit implementation of segmented stacks needs to clobber both r10
15929 // r11. This makes it impossible to use it along with nested parameters.
15930 const Function *F = MF.getFunction();
15932 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15934 if (I->hasNestAttr())
15935 report_fatal_error("Cannot use segmented stacks with functions that "
15936 "have nested arguments.");
15939 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15940 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15941 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15942 Result = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15943 DAG.getRegister(Vreg, SPTy));
15946 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15948 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15949 Flag = Chain.getValue(1);
15950 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15952 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15954 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15955 unsigned SPReg = RegInfo->getStackRegister();
15956 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15957 Chain = SP.getValue(1);
15960 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15961 DAG.getConstant(-(uint64_t)Align, dl, VT));
15962 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15968 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15969 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
15971 SDValue Ops[2] = {Result, Chain};
15972 return DAG.getMergeValues(Ops, dl);
15975 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15976 MachineFunction &MF = DAG.getMachineFunction();
15977 auto PtrVT = getPointerTy(MF.getDataLayout());
15978 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15980 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15983 if (!Subtarget->is64Bit() ||
15984 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15985 // vastart just stores the address of the VarArgsFrameIndex slot into the
15986 // memory location argument.
15987 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15988 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15989 MachinePointerInfo(SV), false, false, 0);
15993 // gp_offset (0 - 6 * 8)
15994 // fp_offset (48 - 48 + 8 * 16)
15995 // overflow_arg_area (point to parameters coming in memory).
15997 SmallVector<SDValue, 8> MemOps;
15998 SDValue FIN = Op.getOperand(1);
16000 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
16001 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
16003 FIN, MachinePointerInfo(SV), false, false, 0);
16004 MemOps.push_back(Store);
16007 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
16008 Store = DAG.getStore(Op.getOperand(0), DL,
16009 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
16011 FIN, MachinePointerInfo(SV, 4), false, false, 0);
16012 MemOps.push_back(Store);
16014 // Store ptr to overflow_arg_area
16015 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
16016 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
16017 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
16018 MachinePointerInfo(SV, 8),
16020 MemOps.push_back(Store);
16022 // Store ptr to reg_save_area.
16023 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
16024 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
16025 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
16026 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
16027 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
16028 MemOps.push_back(Store);
16029 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
16032 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
16033 assert(Subtarget->is64Bit() &&
16034 "LowerVAARG only handles 64-bit va_arg!");
16035 assert(Op.getNode()->getNumOperands() == 4);
16037 MachineFunction &MF = DAG.getMachineFunction();
16038 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
16039 // The Win64 ABI uses char* instead of a structure.
16040 return DAG.expandVAArg(Op.getNode());
16042 SDValue Chain = Op.getOperand(0);
16043 SDValue SrcPtr = Op.getOperand(1);
16044 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
16045 unsigned Align = Op.getConstantOperandVal(3);
16048 EVT ArgVT = Op.getNode()->getValueType(0);
16049 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16050 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
16053 // Decide which area this value should be read from.
16054 // TODO: Implement the AMD64 ABI in its entirety. This simple
16055 // selection mechanism works only for the basic types.
16056 if (ArgVT == MVT::f80) {
16057 llvm_unreachable("va_arg for f80 not yet implemented");
16058 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
16059 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
16060 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
16061 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
16063 llvm_unreachable("Unhandled argument type in LowerVAARG");
16066 if (ArgMode == 2) {
16067 // Sanity Check: Make sure using fp_offset makes sense.
16068 assert(!Subtarget->useSoftFloat() &&
16069 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
16070 Subtarget->hasSSE1());
16073 // Insert VAARG_64 node into the DAG
16074 // VAARG_64 returns two values: Variable Argument Address, Chain
16075 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
16076 DAG.getConstant(ArgMode, dl, MVT::i8),
16077 DAG.getConstant(Align, dl, MVT::i32)};
16078 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
16079 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
16080 VTs, InstOps, MVT::i64,
16081 MachinePointerInfo(SV),
16083 /*Volatile=*/false,
16085 /*WriteMem=*/true);
16086 Chain = VAARG.getValue(1);
16088 // Load the next argument and return it
16089 return DAG.getLoad(ArgVT, dl,
16092 MachinePointerInfo(),
16093 false, false, false, 0);
16096 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
16097 SelectionDAG &DAG) {
16098 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
16099 // where a va_list is still an i8*.
16100 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
16101 if (Subtarget->isCallingConvWin64(
16102 DAG.getMachineFunction().getFunction()->getCallingConv()))
16103 // Probably a Win64 va_copy.
16104 return DAG.expandVACopy(Op.getNode());
16106 SDValue Chain = Op.getOperand(0);
16107 SDValue DstPtr = Op.getOperand(1);
16108 SDValue SrcPtr = Op.getOperand(2);
16109 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
16110 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16113 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
16114 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
16116 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
16119 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
16120 // amount is a constant. Takes immediate version of shift as input.
16121 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
16122 SDValue SrcOp, uint64_t ShiftAmt,
16123 SelectionDAG &DAG) {
16124 MVT ElementType = VT.getVectorElementType();
16126 // Fold this packed shift into its first operand if ShiftAmt is 0.
16130 // Check for ShiftAmt >= element width
16131 if (ShiftAmt >= ElementType.getSizeInBits()) {
16132 if (Opc == X86ISD::VSRAI)
16133 ShiftAmt = ElementType.getSizeInBits() - 1;
16135 return DAG.getConstant(0, dl, VT);
16138 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
16139 && "Unknown target vector shift-by-constant node");
16141 // Fold this packed vector shift into a build vector if SrcOp is a
16142 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
16143 if (VT == SrcOp.getSimpleValueType() &&
16144 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
16145 SmallVector<SDValue, 8> Elts;
16146 unsigned NumElts = SrcOp->getNumOperands();
16147 ConstantSDNode *ND;
16150 default: llvm_unreachable(nullptr);
16151 case X86ISD::VSHLI:
16152 for (unsigned i=0; i!=NumElts; ++i) {
16153 SDValue CurrentOp = SrcOp->getOperand(i);
16154 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16155 Elts.push_back(CurrentOp);
16158 ND = cast<ConstantSDNode>(CurrentOp);
16159 const APInt &C = ND->getAPIntValue();
16160 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
16163 case X86ISD::VSRLI:
16164 for (unsigned i=0; i!=NumElts; ++i) {
16165 SDValue CurrentOp = SrcOp->getOperand(i);
16166 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16167 Elts.push_back(CurrentOp);
16170 ND = cast<ConstantSDNode>(CurrentOp);
16171 const APInt &C = ND->getAPIntValue();
16172 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
16175 case X86ISD::VSRAI:
16176 for (unsigned i=0; i!=NumElts; ++i) {
16177 SDValue CurrentOp = SrcOp->getOperand(i);
16178 if (CurrentOp->getOpcode() == ISD::UNDEF) {
16179 Elts.push_back(CurrentOp);
16182 ND = cast<ConstantSDNode>(CurrentOp);
16183 const APInt &C = ND->getAPIntValue();
16184 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
16189 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16192 return DAG.getNode(Opc, dl, VT, SrcOp,
16193 DAG.getConstant(ShiftAmt, dl, MVT::i8));
16196 // getTargetVShiftNode - Handle vector element shifts where the shift amount
16197 // may or may not be a constant. Takes immediate version of shift as input.
16198 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
16199 SDValue SrcOp, SDValue ShAmt,
16200 SelectionDAG &DAG) {
16201 MVT SVT = ShAmt.getSimpleValueType();
16202 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
16204 // Catch shift-by-constant.
16205 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
16206 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
16207 CShAmt->getZExtValue(), DAG);
16209 // Change opcode to non-immediate version
16211 default: llvm_unreachable("Unknown target vector shift node");
16212 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
16213 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
16214 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
16217 const X86Subtarget &Subtarget =
16218 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16219 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16220 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16221 // Let the shuffle legalizer expand this shift amount node.
16222 SDValue Op0 = ShAmt.getOperand(0);
16223 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16224 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16226 // Need to build a vector containing shift amount.
16227 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16228 SmallVector<SDValue, 4> ShOps;
16229 ShOps.push_back(ShAmt);
16230 if (SVT == MVT::i32) {
16231 ShOps.push_back(DAG.getConstant(0, dl, SVT));
16232 ShOps.push_back(DAG.getUNDEF(SVT));
16234 ShOps.push_back(DAG.getUNDEF(SVT));
16236 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16237 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16240 // The return type has to be a 128-bit type with the same element
16241 // type as the input type.
16242 MVT EltVT = VT.getVectorElementType();
16243 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16245 ShAmt = DAG.getBitcast(ShVT, ShAmt);
16246 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16249 /// \brief Return Mask with the necessary casting or extending
16250 /// for \p Mask according to \p MaskVT when lowering masking intrinsics
16251 static SDValue getMaskNode(SDValue Mask, MVT MaskVT,
16252 const X86Subtarget *Subtarget,
16253 SelectionDAG &DAG, SDLoc dl) {
16255 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16256 // Mask should be extended
16257 Mask = DAG.getNode(ISD::ANY_EXTEND, dl,
16258 MVT::getIntegerVT(MaskVT.getSizeInBits()), Mask);
16261 if (Mask.getSimpleValueType() == MVT::i64 && Subtarget->is32Bit()) {
16262 if (MaskVT == MVT::v64i1) {
16263 assert(Subtarget->hasBWI() && "Expected AVX512BW target!");
16264 // In case 32bit mode, bitcast i64 is illegal, extend/split it.
16266 Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16267 DAG.getConstant(0, dl, MVT::i32));
16268 Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Mask,
16269 DAG.getConstant(1, dl, MVT::i32));
16271 Lo = DAG.getBitcast(MVT::v32i1, Lo);
16272 Hi = DAG.getBitcast(MVT::v32i1, Hi);
16274 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lo, Hi);
16276 // MaskVT require < 64bit. Truncate mask (should succeed in any case),
16278 MVT TruncVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16279 return DAG.getBitcast(MaskVT,
16280 DAG.getNode(ISD::TRUNCATE, dl, TruncVT, Mask));
16284 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16285 Mask.getSimpleValueType().getSizeInBits());
16286 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16287 // are extracted by EXTRACT_SUBVECTOR.
16288 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16289 DAG.getBitcast(BitcastVT, Mask),
16290 DAG.getIntPtrConstant(0, dl));
16294 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16295 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16296 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16297 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16298 SDValue PreservedSrc,
16299 const X86Subtarget *Subtarget,
16300 SelectionDAG &DAG) {
16301 MVT VT = Op.getSimpleValueType();
16302 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16303 unsigned OpcodeSelect = ISD::VSELECT;
16306 if (isAllOnesConstant(Mask))
16309 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16311 switch (Op.getOpcode()) {
16313 case X86ISD::PCMPEQM:
16314 case X86ISD::PCMPGTM:
16316 case X86ISD::CMPMU:
16317 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16318 case X86ISD::VFPCLASS:
16319 case X86ISD::VFPCLASSS:
16320 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16321 case X86ISD::VTRUNC:
16322 case X86ISD::VTRUNCS:
16323 case X86ISD::VTRUNCUS:
16324 // We can't use ISD::VSELECT here because it is not always "Legal"
16325 // for the destination type. For example vpmovqb require only AVX512
16326 // and vselect that can operate on byte element type require BWI
16327 OpcodeSelect = X86ISD::SELECT;
16330 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16331 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16332 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16335 /// \brief Creates an SDNode for a predicated scalar operation.
16336 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16337 /// The mask is coming as MVT::i8 and it should be truncated
16338 /// to MVT::i1 while lowering masking intrinsics.
16339 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16340 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16341 /// for a scalar instruction.
16342 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16343 SDValue PreservedSrc,
16344 const X86Subtarget *Subtarget,
16345 SelectionDAG &DAG) {
16346 if (isAllOnesConstant(Mask))
16349 MVT VT = Op.getSimpleValueType();
16351 // The mask should be of type MVT::i1
16352 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16354 if (Op.getOpcode() == X86ISD::FSETCC)
16355 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16356 if (Op.getOpcode() == X86ISD::VFPCLASS ||
16357 Op.getOpcode() == X86ISD::VFPCLASSS)
16358 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16360 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16361 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16362 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16365 static int getSEHRegistrationNodeSize(const Function *Fn) {
16366 if (!Fn->hasPersonalityFn())
16367 report_fatal_error(
16368 "querying registration node size for function without personality");
16369 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16370 // WinEHStatePass for the full struct definition.
16371 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16372 case EHPersonality::MSVC_X86SEH: return 24;
16373 case EHPersonality::MSVC_CXX: return 16;
16376 report_fatal_error(
16377 "can only recover FP for 32-bit MSVC EH personality functions");
16380 /// When the MSVC runtime transfers control to us, either to an outlined
16381 /// function or when returning to a parent frame after catching an exception, we
16382 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16383 /// Here's the math:
16384 /// RegNodeBase = EntryEBP - RegNodeSize
16385 /// ParentFP = RegNodeBase - ParentFrameOffset
16386 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16387 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16388 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16389 SDValue EntryEBP) {
16390 MachineFunction &MF = DAG.getMachineFunction();
16393 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16394 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16396 // It's possible that the parent function no longer has a personality function
16397 // if the exceptional code was optimized away, in which case we just return
16398 // the incoming EBP.
16399 if (!Fn->hasPersonalityFn())
16402 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16403 // registration, or the .set_setframe offset.
16404 MCSymbol *OffsetSym =
16405 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16406 GlobalValue::getRealLinkageName(Fn->getName()));
16407 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16408 SDValue ParentFrameOffset =
16409 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16411 // Return EntryEBP + ParentFrameOffset for x64. This adjusts from RSP after
16412 // prologue to RBP in the parent function.
16413 const X86Subtarget &Subtarget =
16414 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16415 if (Subtarget.is64Bit())
16416 return DAG.getNode(ISD::ADD, dl, PtrVT, EntryEBP, ParentFrameOffset);
16418 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16419 // RegNodeBase = EntryEBP - RegNodeSize
16420 // ParentFP = RegNodeBase - ParentFrameOffset
16421 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16422 DAG.getConstant(RegNodeSize, dl, PtrVT));
16423 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, ParentFrameOffset);
16426 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16427 SelectionDAG &DAG) {
16429 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16430 MVT VT = Op.getSimpleValueType();
16431 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16433 switch(IntrData->Type) {
16434 case INTR_TYPE_1OP:
16435 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16436 case INTR_TYPE_2OP:
16437 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16439 case INTR_TYPE_2OP_IMM8:
16440 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16441 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16442 case INTR_TYPE_3OP:
16443 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16444 Op.getOperand(2), Op.getOperand(3));
16445 case INTR_TYPE_4OP:
16446 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16447 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16448 case INTR_TYPE_1OP_MASK_RM: {
16449 SDValue Src = Op.getOperand(1);
16450 SDValue PassThru = Op.getOperand(2);
16451 SDValue Mask = Op.getOperand(3);
16452 SDValue RoundingMode;
16453 // We allways add rounding mode to the Node.
16454 // If the rounding mode is not specified, we add the
16455 // "current direction" mode.
16456 if (Op.getNumOperands() == 4)
16458 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16460 RoundingMode = Op.getOperand(4);
16461 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16462 if (IntrWithRoundingModeOpcode != 0)
16463 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16464 X86::STATIC_ROUNDING::CUR_DIRECTION)
16465 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16466 dl, Op.getValueType(), Src, RoundingMode),
16467 Mask, PassThru, Subtarget, DAG);
16468 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16470 Mask, PassThru, Subtarget, DAG);
16472 case INTR_TYPE_1OP_MASK: {
16473 SDValue Src = Op.getOperand(1);
16474 SDValue PassThru = Op.getOperand(2);
16475 SDValue Mask = Op.getOperand(3);
16476 // We add rounding mode to the Node when
16477 // - RM Opcode is specified and
16478 // - RM is not "current direction".
16479 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16480 if (IntrWithRoundingModeOpcode != 0) {
16481 SDValue Rnd = Op.getOperand(4);
16482 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16483 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16484 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16485 dl, Op.getValueType(),
16487 Mask, PassThru, Subtarget, DAG);
16490 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16491 Mask, PassThru, Subtarget, DAG);
16493 case INTR_TYPE_SCALAR_MASK: {
16494 SDValue Src1 = Op.getOperand(1);
16495 SDValue Src2 = Op.getOperand(2);
16496 SDValue passThru = Op.getOperand(3);
16497 SDValue Mask = Op.getOperand(4);
16498 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16499 Mask, passThru, Subtarget, DAG);
16501 case INTR_TYPE_SCALAR_MASK_RM: {
16502 SDValue Src1 = Op.getOperand(1);
16503 SDValue Src2 = Op.getOperand(2);
16504 SDValue Src0 = Op.getOperand(3);
16505 SDValue Mask = Op.getOperand(4);
16506 // There are 2 kinds of intrinsics in this group:
16507 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16508 // (2) With rounding mode and sae - 7 operands.
16509 if (Op.getNumOperands() == 6) {
16510 SDValue Sae = Op.getOperand(5);
16511 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16512 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16514 Mask, Src0, Subtarget, DAG);
16516 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16517 SDValue RoundingMode = Op.getOperand(5);
16518 SDValue Sae = Op.getOperand(6);
16519 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16520 RoundingMode, Sae),
16521 Mask, Src0, Subtarget, DAG);
16523 case INTR_TYPE_2OP_MASK:
16524 case INTR_TYPE_2OP_IMM8_MASK: {
16525 SDValue Src1 = Op.getOperand(1);
16526 SDValue Src2 = Op.getOperand(2);
16527 SDValue PassThru = Op.getOperand(3);
16528 SDValue Mask = Op.getOperand(4);
16530 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16531 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16533 // We specify 2 possible opcodes for intrinsics with rounding modes.
16534 // First, we check if the intrinsic may have non-default rounding mode,
16535 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16536 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16537 if (IntrWithRoundingModeOpcode != 0) {
16538 SDValue Rnd = Op.getOperand(5);
16539 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16540 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16541 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16542 dl, Op.getValueType(),
16544 Mask, PassThru, Subtarget, DAG);
16547 // TODO: Intrinsics should have fast-math-flags to propagate.
16548 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16549 Mask, PassThru, Subtarget, DAG);
16551 case INTR_TYPE_2OP_MASK_RM: {
16552 SDValue Src1 = Op.getOperand(1);
16553 SDValue Src2 = Op.getOperand(2);
16554 SDValue PassThru = Op.getOperand(3);
16555 SDValue Mask = Op.getOperand(4);
16556 // We specify 2 possible modes for intrinsics, with/without rounding
16558 // First, we check if the intrinsic have rounding mode (6 operands),
16559 // if not, we set rounding mode to "current".
16561 if (Op.getNumOperands() == 6)
16562 Rnd = Op.getOperand(5);
16564 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16565 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16567 Mask, PassThru, Subtarget, DAG);
16569 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16570 SDValue Src1 = Op.getOperand(1);
16571 SDValue Src2 = Op.getOperand(2);
16572 SDValue Src3 = Op.getOperand(3);
16573 SDValue PassThru = Op.getOperand(4);
16574 SDValue Mask = Op.getOperand(5);
16575 SDValue Sae = Op.getOperand(6);
16577 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16579 Mask, PassThru, Subtarget, DAG);
16581 case INTR_TYPE_3OP_MASK_RM: {
16582 SDValue Src1 = Op.getOperand(1);
16583 SDValue Src2 = Op.getOperand(2);
16584 SDValue Imm = Op.getOperand(3);
16585 SDValue PassThru = Op.getOperand(4);
16586 SDValue Mask = Op.getOperand(5);
16587 // We specify 2 possible modes for intrinsics, with/without rounding
16589 // First, we check if the intrinsic have rounding mode (7 operands),
16590 // if not, we set rounding mode to "current".
16592 if (Op.getNumOperands() == 7)
16593 Rnd = Op.getOperand(6);
16595 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16596 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16597 Src1, Src2, Imm, Rnd),
16598 Mask, PassThru, Subtarget, DAG);
16600 case INTR_TYPE_3OP_IMM8_MASK:
16601 case INTR_TYPE_3OP_MASK:
16602 case INSERT_SUBVEC: {
16603 SDValue Src1 = Op.getOperand(1);
16604 SDValue Src2 = Op.getOperand(2);
16605 SDValue Src3 = Op.getOperand(3);
16606 SDValue PassThru = Op.getOperand(4);
16607 SDValue Mask = Op.getOperand(5);
16609 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16610 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16611 else if (IntrData->Type == INSERT_SUBVEC) {
16612 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16613 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16614 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16615 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16616 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16619 // We specify 2 possible opcodes for intrinsics with rounding modes.
16620 // First, we check if the intrinsic may have non-default rounding mode,
16621 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16622 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16623 if (IntrWithRoundingModeOpcode != 0) {
16624 SDValue Rnd = Op.getOperand(6);
16625 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16626 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16627 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16628 dl, Op.getValueType(),
16629 Src1, Src2, Src3, Rnd),
16630 Mask, PassThru, Subtarget, DAG);
16633 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16635 Mask, PassThru, Subtarget, DAG);
16637 case VPERM_3OP_MASKZ:
16638 case VPERM_3OP_MASK:{
16639 // Src2 is the PassThru
16640 SDValue Src1 = Op.getOperand(1);
16641 SDValue Src2 = Op.getOperand(2);
16642 SDValue Src3 = Op.getOperand(3);
16643 SDValue Mask = Op.getOperand(4);
16644 MVT VT = Op.getSimpleValueType();
16645 SDValue PassThru = SDValue();
16647 // set PassThru element
16648 if (IntrData->Type == VPERM_3OP_MASKZ)
16649 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16651 PassThru = DAG.getBitcast(VT, Src2);
16653 // Swap Src1 and Src2 in the node creation
16654 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16655 dl, Op.getValueType(),
16657 Mask, PassThru, Subtarget, DAG);
16661 case FMA_OP_MASK: {
16662 SDValue Src1 = Op.getOperand(1);
16663 SDValue Src2 = Op.getOperand(2);
16664 SDValue Src3 = Op.getOperand(3);
16665 SDValue Mask = Op.getOperand(4);
16666 MVT VT = Op.getSimpleValueType();
16667 SDValue PassThru = SDValue();
16669 // set PassThru element
16670 if (IntrData->Type == FMA_OP_MASKZ)
16671 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16672 else if (IntrData->Type == FMA_OP_MASK3)
16677 // We specify 2 possible opcodes for intrinsics with rounding modes.
16678 // First, we check if the intrinsic may have non-default rounding mode,
16679 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16680 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16681 if (IntrWithRoundingModeOpcode != 0) {
16682 SDValue Rnd = Op.getOperand(5);
16683 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16684 X86::STATIC_ROUNDING::CUR_DIRECTION)
16685 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16686 dl, Op.getValueType(),
16687 Src1, Src2, Src3, Rnd),
16688 Mask, PassThru, Subtarget, DAG);
16690 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16691 dl, Op.getValueType(),
16693 Mask, PassThru, Subtarget, DAG);
16695 case TERLOG_OP_MASK:
16696 case TERLOG_OP_MASKZ: {
16697 SDValue Src1 = Op.getOperand(1);
16698 SDValue Src2 = Op.getOperand(2);
16699 SDValue Src3 = Op.getOperand(3);
16700 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16701 SDValue Mask = Op.getOperand(5);
16702 MVT VT = Op.getSimpleValueType();
16703 SDValue PassThru = Src1;
16704 // Set PassThru element.
16705 if (IntrData->Type == TERLOG_OP_MASKZ)
16706 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16708 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16709 Src1, Src2, Src3, Src4),
16710 Mask, PassThru, Subtarget, DAG);
16713 // FPclass intrinsics with mask
16714 SDValue Src1 = Op.getOperand(1);
16715 MVT VT = Src1.getSimpleValueType();
16716 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16717 SDValue Imm = Op.getOperand(2);
16718 SDValue Mask = Op.getOperand(3);
16719 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16720 Mask.getSimpleValueType().getSizeInBits());
16721 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16722 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16723 DAG.getTargetConstant(0, dl, MaskVT),
16725 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16726 DAG.getUNDEF(BitcastVT), FPclassMask,
16727 DAG.getIntPtrConstant(0, dl));
16728 return DAG.getBitcast(Op.getValueType(), Res);
16731 SDValue Src1 = Op.getOperand(1);
16732 SDValue Imm = Op.getOperand(2);
16733 SDValue Mask = Op.getOperand(3);
16734 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16735 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16736 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16737 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16740 case CMP_MASK_CC: {
16741 // Comparison intrinsics with masks.
16742 // Example of transformation:
16743 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16744 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16746 // (v8i1 (insert_subvector undef,
16747 // (v2i1 (and (PCMPEQM %a, %b),
16748 // (extract_subvector
16749 // (v8i1 (bitcast %mask)), 0))), 0))))
16750 MVT VT = Op.getOperand(1).getSimpleValueType();
16751 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16752 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16753 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16754 Mask.getSimpleValueType().getSizeInBits());
16756 if (IntrData->Type == CMP_MASK_CC) {
16757 SDValue CC = Op.getOperand(3);
16758 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16759 // We specify 2 possible opcodes for intrinsics with rounding modes.
16760 // First, we check if the intrinsic may have non-default rounding mode,
16761 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16762 if (IntrData->Opc1 != 0) {
16763 SDValue Rnd = Op.getOperand(5);
16764 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16765 X86::STATIC_ROUNDING::CUR_DIRECTION)
16766 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16767 Op.getOperand(2), CC, Rnd);
16769 //default rounding mode
16771 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16772 Op.getOperand(2), CC);
16775 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16776 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16779 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16780 DAG.getTargetConstant(0, dl,
16783 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16784 DAG.getUNDEF(BitcastVT), CmpMask,
16785 DAG.getIntPtrConstant(0, dl));
16786 return DAG.getBitcast(Op.getValueType(), Res);
16788 case CMP_MASK_SCALAR_CC: {
16789 SDValue Src1 = Op.getOperand(1);
16790 SDValue Src2 = Op.getOperand(2);
16791 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16792 SDValue Mask = Op.getOperand(4);
16795 if (IntrData->Opc1 != 0) {
16796 SDValue Rnd = Op.getOperand(5);
16797 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16798 X86::STATIC_ROUNDING::CUR_DIRECTION)
16799 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16801 //default rounding mode
16803 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16805 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16806 DAG.getTargetConstant(0, dl,
16810 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16811 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16812 DAG.getValueType(MVT::i1));
16814 case COMI: { // Comparison intrinsics
16815 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16816 SDValue LHS = Op.getOperand(1);
16817 SDValue RHS = Op.getOperand(2);
16818 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16819 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16820 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16821 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16822 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16823 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16825 case COMI_RM: { // Comparison intrinsics with Sae
16826 SDValue LHS = Op.getOperand(1);
16827 SDValue RHS = Op.getOperand(2);
16828 SDValue CC = Op.getOperand(3);
16829 SDValue Sae = Op.getOperand(4);
16830 auto ComiType = TranslateX86ConstCondToX86CC(CC);
16831 // choose between ordered and unordered (comi/ucomi)
16832 unsigned comiOp = std::get<0>(ComiType) ? IntrData->Opc0 : IntrData->Opc1;
16834 if (cast<ConstantSDNode>(Sae)->getZExtValue() !=
16835 X86::STATIC_ROUNDING::CUR_DIRECTION)
16836 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS, Sae);
16838 Cond = DAG.getNode(comiOp, dl, MVT::i32, LHS, RHS);
16839 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16840 DAG.getConstant(std::get<1>(ComiType), dl, MVT::i8), Cond);
16841 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16844 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16845 Op.getOperand(1), Op.getOperand(2), DAG);
16847 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16848 Op.getSimpleValueType(),
16850 Op.getOperand(2), DAG),
16851 Op.getOperand(4), Op.getOperand(3), Subtarget,
16853 case COMPRESS_EXPAND_IN_REG: {
16854 SDValue Mask = Op.getOperand(3);
16855 SDValue DataToCompress = Op.getOperand(1);
16856 SDValue PassThru = Op.getOperand(2);
16857 if (isAllOnesConstant(Mask)) // return data as is
16858 return Op.getOperand(1);
16860 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16862 Mask, PassThru, Subtarget, DAG);
16865 SDValue Mask = Op.getOperand(1);
16866 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16867 Mask.getSimpleValueType().getSizeInBits());
16868 Mask = DAG.getBitcast(MaskVT, Mask);
16869 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16872 SDValue Mask = Op.getOperand(3);
16873 MVT VT = Op.getSimpleValueType();
16874 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16875 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16876 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16880 MVT VT = Op.getSimpleValueType();
16881 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits()/2);
16883 SDValue Src1 = getMaskNode(Op.getOperand(1), MaskVT, Subtarget, DAG, dl);
16884 SDValue Src2 = getMaskNode(Op.getOperand(2), MaskVT, Subtarget, DAG, dl);
16885 // Arguments should be swapped.
16886 SDValue Res = DAG.getNode(IntrData->Opc0, dl,
16887 MVT::getVectorVT(MVT::i1, VT.getSizeInBits()),
16889 return DAG.getBitcast(VT, Res);
16891 case CONVERT_TO_MASK: {
16892 MVT SrcVT = Op.getOperand(1).getSimpleValueType();
16893 MVT MaskVT = MVT::getVectorVT(MVT::i1, SrcVT.getVectorNumElements());
16894 MVT BitcastVT = MVT::getVectorVT(MVT::i1, VT.getSizeInBits());
16896 SDValue CvtMask = DAG.getNode(IntrData->Opc0, dl, MaskVT,
16898 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16899 DAG.getUNDEF(BitcastVT), CvtMask,
16900 DAG.getIntPtrConstant(0, dl));
16901 return DAG.getBitcast(Op.getValueType(), Res);
16903 case CONVERT_MASK_TO_VEC: {
16904 SDValue Mask = Op.getOperand(1);
16905 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16906 SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
16907 return DAG.getNode(IntrData->Opc0, dl, VT, VMask);
16909 case BRCST_SUBVEC_TO_VEC: {
16910 SDValue Src = Op.getOperand(1);
16911 SDValue Passthru = Op.getOperand(2);
16912 SDValue Mask = Op.getOperand(3);
16913 EVT resVT = Passthru.getValueType();
16914 SDValue subVec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, resVT,
16915 DAG.getUNDEF(resVT), Src,
16916 DAG.getIntPtrConstant(0, dl));
16918 if (Src.getSimpleValueType().is256BitVector() && resVT.is512BitVector())
16919 immVal = DAG.getConstant(0x44, dl, MVT::i8);
16921 immVal = DAG.getConstant(0, dl, MVT::i8);
16922 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16923 subVec, subVec, immVal),
16924 Mask, Passthru, Subtarget, DAG);
16932 default: return SDValue(); // Don't custom lower most intrinsics.
16934 case Intrinsic::x86_avx2_permd:
16935 case Intrinsic::x86_avx2_permps:
16936 // Operands intentionally swapped. Mask is last operand to intrinsic,
16937 // but second operand for node/instruction.
16938 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16939 Op.getOperand(2), Op.getOperand(1));
16941 // ptest and testp intrinsics. The intrinsic these come from are designed to
16942 // return an integer value, not just an instruction so lower it to the ptest
16943 // or testp pattern and a setcc for the result.
16944 case Intrinsic::x86_sse41_ptestz:
16945 case Intrinsic::x86_sse41_ptestc:
16946 case Intrinsic::x86_sse41_ptestnzc:
16947 case Intrinsic::x86_avx_ptestz_256:
16948 case Intrinsic::x86_avx_ptestc_256:
16949 case Intrinsic::x86_avx_ptestnzc_256:
16950 case Intrinsic::x86_avx_vtestz_ps:
16951 case Intrinsic::x86_avx_vtestc_ps:
16952 case Intrinsic::x86_avx_vtestnzc_ps:
16953 case Intrinsic::x86_avx_vtestz_pd:
16954 case Intrinsic::x86_avx_vtestc_pd:
16955 case Intrinsic::x86_avx_vtestnzc_pd:
16956 case Intrinsic::x86_avx_vtestz_ps_256:
16957 case Intrinsic::x86_avx_vtestc_ps_256:
16958 case Intrinsic::x86_avx_vtestnzc_ps_256:
16959 case Intrinsic::x86_avx_vtestz_pd_256:
16960 case Intrinsic::x86_avx_vtestc_pd_256:
16961 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16962 bool IsTestPacked = false;
16965 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16966 case Intrinsic::x86_avx_vtestz_ps:
16967 case Intrinsic::x86_avx_vtestz_pd:
16968 case Intrinsic::x86_avx_vtestz_ps_256:
16969 case Intrinsic::x86_avx_vtestz_pd_256:
16970 IsTestPacked = true; // Fallthrough
16971 case Intrinsic::x86_sse41_ptestz:
16972 case Intrinsic::x86_avx_ptestz_256:
16974 X86CC = X86::COND_E;
16976 case Intrinsic::x86_avx_vtestc_ps:
16977 case Intrinsic::x86_avx_vtestc_pd:
16978 case Intrinsic::x86_avx_vtestc_ps_256:
16979 case Intrinsic::x86_avx_vtestc_pd_256:
16980 IsTestPacked = true; // Fallthrough
16981 case Intrinsic::x86_sse41_ptestc:
16982 case Intrinsic::x86_avx_ptestc_256:
16984 X86CC = X86::COND_B;
16986 case Intrinsic::x86_avx_vtestnzc_ps:
16987 case Intrinsic::x86_avx_vtestnzc_pd:
16988 case Intrinsic::x86_avx_vtestnzc_ps_256:
16989 case Intrinsic::x86_avx_vtestnzc_pd_256:
16990 IsTestPacked = true; // Fallthrough
16991 case Intrinsic::x86_sse41_ptestnzc:
16992 case Intrinsic::x86_avx_ptestnzc_256:
16994 X86CC = X86::COND_A;
16998 SDValue LHS = Op.getOperand(1);
16999 SDValue RHS = Op.getOperand(2);
17000 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
17001 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
17002 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
17003 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
17004 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17006 case Intrinsic::x86_avx512_kortestz_w:
17007 case Intrinsic::x86_avx512_kortestc_w: {
17008 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
17009 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
17010 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
17011 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
17012 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
17013 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
17014 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17017 case Intrinsic::x86_sse42_pcmpistria128:
17018 case Intrinsic::x86_sse42_pcmpestria128:
17019 case Intrinsic::x86_sse42_pcmpistric128:
17020 case Intrinsic::x86_sse42_pcmpestric128:
17021 case Intrinsic::x86_sse42_pcmpistrio128:
17022 case Intrinsic::x86_sse42_pcmpestrio128:
17023 case Intrinsic::x86_sse42_pcmpistris128:
17024 case Intrinsic::x86_sse42_pcmpestris128:
17025 case Intrinsic::x86_sse42_pcmpistriz128:
17026 case Intrinsic::x86_sse42_pcmpestriz128: {
17030 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
17031 case Intrinsic::x86_sse42_pcmpistria128:
17032 Opcode = X86ISD::PCMPISTRI;
17033 X86CC = X86::COND_A;
17035 case Intrinsic::x86_sse42_pcmpestria128:
17036 Opcode = X86ISD::PCMPESTRI;
17037 X86CC = X86::COND_A;
17039 case Intrinsic::x86_sse42_pcmpistric128:
17040 Opcode = X86ISD::PCMPISTRI;
17041 X86CC = X86::COND_B;
17043 case Intrinsic::x86_sse42_pcmpestric128:
17044 Opcode = X86ISD::PCMPESTRI;
17045 X86CC = X86::COND_B;
17047 case Intrinsic::x86_sse42_pcmpistrio128:
17048 Opcode = X86ISD::PCMPISTRI;
17049 X86CC = X86::COND_O;
17051 case Intrinsic::x86_sse42_pcmpestrio128:
17052 Opcode = X86ISD::PCMPESTRI;
17053 X86CC = X86::COND_O;
17055 case Intrinsic::x86_sse42_pcmpistris128:
17056 Opcode = X86ISD::PCMPISTRI;
17057 X86CC = X86::COND_S;
17059 case Intrinsic::x86_sse42_pcmpestris128:
17060 Opcode = X86ISD::PCMPESTRI;
17061 X86CC = X86::COND_S;
17063 case Intrinsic::x86_sse42_pcmpistriz128:
17064 Opcode = X86ISD::PCMPISTRI;
17065 X86CC = X86::COND_E;
17067 case Intrinsic::x86_sse42_pcmpestriz128:
17068 Opcode = X86ISD::PCMPESTRI;
17069 X86CC = X86::COND_E;
17072 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17073 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17074 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
17075 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17076 DAG.getConstant(X86CC, dl, MVT::i8),
17077 SDValue(PCMP.getNode(), 1));
17078 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
17081 case Intrinsic::x86_sse42_pcmpistri128:
17082 case Intrinsic::x86_sse42_pcmpestri128: {
17084 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
17085 Opcode = X86ISD::PCMPISTRI;
17087 Opcode = X86ISD::PCMPESTRI;
17089 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
17090 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
17091 return DAG.getNode(Opcode, dl, VTs, NewOps);
17094 case Intrinsic::x86_seh_lsda: {
17095 // Compute the symbol for the LSDA. We know it'll get emitted later.
17096 MachineFunction &MF = DAG.getMachineFunction();
17097 SDValue Op1 = Op.getOperand(1);
17098 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
17099 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
17100 GlobalValue::getRealLinkageName(Fn->getName()));
17102 // Generate a simple absolute symbol reference. This intrinsic is only
17103 // supported on 32-bit Windows, which isn't PIC.
17104 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
17105 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
17108 case Intrinsic::x86_seh_recoverfp: {
17109 SDValue FnOp = Op.getOperand(1);
17110 SDValue IncomingFPOp = Op.getOperand(2);
17111 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
17112 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
17114 report_fatal_error(
17115 "llvm.x86.seh.recoverfp must take a function as the first argument");
17116 return recoverFramePointer(DAG, Fn, IncomingFPOp);
17119 case Intrinsic::localaddress: {
17120 // Returns one of the stack, base, or frame pointer registers, depending on
17121 // which is used to reference local variables.
17122 MachineFunction &MF = DAG.getMachineFunction();
17123 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17125 if (RegInfo->hasBasePointer(MF))
17126 Reg = RegInfo->getBaseRegister();
17127 else // This function handles the SP or FP case.
17128 Reg = RegInfo->getPtrSizedFrameRegister(MF);
17129 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
17134 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17135 SDValue Src, SDValue Mask, SDValue Base,
17136 SDValue Index, SDValue ScaleOp, SDValue Chain,
17137 const X86Subtarget * Subtarget) {
17139 auto *C = cast<ConstantSDNode>(ScaleOp);
17140 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17141 MVT MaskVT = MVT::getVectorVT(MVT::i1,
17142 Index.getSimpleValueType().getVectorNumElements());
17144 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17146 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17148 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17149 Mask.getSimpleValueType().getSizeInBits());
17151 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17152 // are extracted by EXTRACT_SUBVECTOR.
17153 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17154 DAG.getBitcast(BitcastVT, Mask),
17155 DAG.getIntPtrConstant(0, dl));
17157 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
17158 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17159 SDValue Segment = DAG.getRegister(0, MVT::i32);
17160 if (Src.getOpcode() == ISD::UNDEF)
17161 Src = getZeroVector(Op.getSimpleValueType(), Subtarget, DAG, dl);
17162 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17163 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17164 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
17165 return DAG.getMergeValues(RetOps, dl);
17168 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17169 SDValue Src, SDValue Mask, SDValue Base,
17170 SDValue Index, SDValue ScaleOp, SDValue Chain) {
17172 auto *C = cast<ConstantSDNode>(ScaleOp);
17173 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17174 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17175 SDValue Segment = DAG.getRegister(0, MVT::i32);
17176 MVT MaskVT = MVT::getVectorVT(MVT::i1,
17177 Index.getSimpleValueType().getVectorNumElements());
17179 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17181 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17183 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17184 Mask.getSimpleValueType().getSizeInBits());
17186 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17187 // are extracted by EXTRACT_SUBVECTOR.
17188 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17189 DAG.getBitcast(BitcastVT, Mask),
17190 DAG.getIntPtrConstant(0, dl));
17192 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
17193 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
17194 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
17195 return SDValue(Res, 1);
17198 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
17199 SDValue Mask, SDValue Base, SDValue Index,
17200 SDValue ScaleOp, SDValue Chain) {
17202 auto *C = cast<ConstantSDNode>(ScaleOp);
17203 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
17204 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
17205 SDValue Segment = DAG.getRegister(0, MVT::i32);
17207 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
17209 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
17211 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
17213 MaskInReg = DAG.getBitcast(MaskVT, Mask);
17214 //SDVTList VTs = DAG.getVTList(MVT::Other);
17215 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
17216 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
17217 return SDValue(Res, 0);
17220 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
17221 // read performance monitor counters (x86_rdpmc).
17222 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
17223 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17224 SmallVectorImpl<SDValue> &Results) {
17225 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17226 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17229 // The ECX register is used to select the index of the performance counter
17231 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
17233 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
17235 // Reads the content of a 64-bit performance counter and returns it in the
17236 // registers EDX:EAX.
17237 if (Subtarget->is64Bit()) {
17238 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17239 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17242 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17243 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17246 Chain = HI.getValue(1);
17248 if (Subtarget->is64Bit()) {
17249 // The EAX register is loaded with the low-order 32 bits. The EDX register
17250 // is loaded with the supported high-order bits of the counter.
17251 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17252 DAG.getConstant(32, DL, MVT::i8));
17253 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17254 Results.push_back(Chain);
17258 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17259 SDValue Ops[] = { LO, HI };
17260 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17261 Results.push_back(Pair);
17262 Results.push_back(Chain);
17265 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
17266 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
17267 // also used to custom lower READCYCLECOUNTER nodes.
17268 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
17269 SelectionDAG &DAG, const X86Subtarget *Subtarget,
17270 SmallVectorImpl<SDValue> &Results) {
17271 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17272 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
17275 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
17276 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
17277 // and the EAX register is loaded with the low-order 32 bits.
17278 if (Subtarget->is64Bit()) {
17279 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
17280 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
17283 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
17284 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
17287 SDValue Chain = HI.getValue(1);
17289 if (Opcode == X86ISD::RDTSCP_DAG) {
17290 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
17292 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
17293 // the ECX register. Add 'ecx' explicitly to the chain.
17294 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
17296 // Explicitly store the content of ECX at the location passed in input
17297 // to the 'rdtscp' intrinsic.
17298 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
17299 MachinePointerInfo(), false, false, 0);
17302 if (Subtarget->is64Bit()) {
17303 // The EDX register is loaded with the high-order 32 bits of the MSR, and
17304 // the EAX register is loaded with the low-order 32 bits.
17305 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
17306 DAG.getConstant(32, DL, MVT::i8));
17307 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
17308 Results.push_back(Chain);
17312 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
17313 SDValue Ops[] = { LO, HI };
17314 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
17315 Results.push_back(Pair);
17316 Results.push_back(Chain);
17319 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
17320 SelectionDAG &DAG) {
17321 SmallVector<SDValue, 2> Results;
17323 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
17325 return DAG.getMergeValues(Results, DL);
17328 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17329 MachineFunction &MF = DAG.getMachineFunction();
17330 SDValue Chain = Op.getOperand(0);
17331 SDValue RegNode = Op.getOperand(2);
17332 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17334 report_fatal_error("EH registrations only live in functions using WinEH");
17336 // Cast the operand to an alloca, and remember the frame index.
17337 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17339 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17340 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17342 // Return the chain operand without making any DAG nodes.
17346 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17347 /// return truncate Store/MaskedStore Node
17348 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17352 SDValue Mask = Op.getOperand(4);
17353 SDValue DataToTruncate = Op.getOperand(3);
17354 SDValue Addr = Op.getOperand(2);
17355 SDValue Chain = Op.getOperand(0);
17357 MVT VT = DataToTruncate.getSimpleValueType();
17358 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17360 if (isAllOnesConstant(Mask)) // return just a truncate store
17361 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17362 MachinePointerInfo(), SVT, false, false,
17363 SVT.getScalarSizeInBits()/8);
17365 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17366 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17367 Mask.getSimpleValueType().getSizeInBits());
17368 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17369 // are extracted by EXTRACT_SUBVECTOR.
17370 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17371 DAG.getBitcast(BitcastVT, Mask),
17372 DAG.getIntPtrConstant(0, dl));
17374 MachineMemOperand *MMO = DAG.getMachineFunction().
17375 getMachineMemOperand(MachinePointerInfo(),
17376 MachineMemOperand::MOStore, SVT.getStoreSize(),
17377 SVT.getScalarSizeInBits()/8);
17379 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17380 VMask, SVT, MMO, true);
17383 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17384 SelectionDAG &DAG) {
17385 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17387 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17389 if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17390 return MarkEHRegistrationNode(Op, DAG);
17391 if (IntNo == llvm::Intrinsic::x86_flags_read_u32 ||
17392 IntNo == llvm::Intrinsic::x86_flags_read_u64 ||
17393 IntNo == llvm::Intrinsic::x86_flags_write_u32 ||
17394 IntNo == llvm::Intrinsic::x86_flags_write_u64) {
17395 // We need a frame pointer because this will get lowered to a PUSH/POP
17397 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17398 MFI->setHasOpaqueSPAdjustment(true);
17399 // Don't do anything here, we will expand these intrinsics out later
17400 // during ExpandISelPseudos in EmitInstrWithCustomInserter.
17407 switch(IntrData->Type) {
17408 default: llvm_unreachable("Unknown Intrinsic Type");
17411 // Emit the node with the right value type.
17412 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17413 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17415 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17416 // Otherwise return the value from Rand, which is always 0, casted to i32.
17417 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17418 DAG.getConstant(1, dl, Op->getValueType(1)),
17419 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17420 SDValue(Result.getNode(), 1) };
17421 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17422 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17425 // Return { result, isValid, chain }.
17426 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17427 SDValue(Result.getNode(), 2));
17430 //gather(v1, mask, index, base, scale);
17431 SDValue Chain = Op.getOperand(0);
17432 SDValue Src = Op.getOperand(2);
17433 SDValue Base = Op.getOperand(3);
17434 SDValue Index = Op.getOperand(4);
17435 SDValue Mask = Op.getOperand(5);
17436 SDValue Scale = Op.getOperand(6);
17437 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17441 //scatter(base, mask, index, v1, scale);
17442 SDValue Chain = Op.getOperand(0);
17443 SDValue Base = Op.getOperand(2);
17444 SDValue Mask = Op.getOperand(3);
17445 SDValue Index = Op.getOperand(4);
17446 SDValue Src = Op.getOperand(5);
17447 SDValue Scale = Op.getOperand(6);
17448 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17452 SDValue Hint = Op.getOperand(6);
17453 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17454 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17455 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17456 SDValue Chain = Op.getOperand(0);
17457 SDValue Mask = Op.getOperand(2);
17458 SDValue Index = Op.getOperand(3);
17459 SDValue Base = Op.getOperand(4);
17460 SDValue Scale = Op.getOperand(5);
17461 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17463 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17465 SmallVector<SDValue, 2> Results;
17466 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17468 return DAG.getMergeValues(Results, dl);
17470 // Read Performance Monitoring Counters.
17472 SmallVector<SDValue, 2> Results;
17473 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17474 return DAG.getMergeValues(Results, dl);
17476 // XTEST intrinsics.
17478 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17479 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17480 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17481 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17483 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17484 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17485 Ret, SDValue(InTrans.getNode(), 1));
17489 SmallVector<SDValue, 2> Results;
17490 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17491 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17492 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17493 DAG.getConstant(-1, dl, MVT::i8));
17494 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17495 Op.getOperand(4), GenCF.getValue(1));
17496 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17497 Op.getOperand(5), MachinePointerInfo(),
17499 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17500 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17502 Results.push_back(SetCC);
17503 Results.push_back(Store);
17504 return DAG.getMergeValues(Results, dl);
17506 case COMPRESS_TO_MEM: {
17508 SDValue Mask = Op.getOperand(4);
17509 SDValue DataToCompress = Op.getOperand(3);
17510 SDValue Addr = Op.getOperand(2);
17511 SDValue Chain = Op.getOperand(0);
17513 MVT VT = DataToCompress.getSimpleValueType();
17514 if (isAllOnesConstant(Mask)) // return just a store
17515 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17516 MachinePointerInfo(), false, false,
17517 VT.getScalarSizeInBits()/8);
17519 SDValue Compressed =
17520 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17521 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17522 return DAG.getStore(Chain, dl, Compressed, Addr,
17523 MachinePointerInfo(), false, false,
17524 VT.getScalarSizeInBits()/8);
17526 case TRUNCATE_TO_MEM_VI8:
17527 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17528 case TRUNCATE_TO_MEM_VI16:
17529 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17530 case TRUNCATE_TO_MEM_VI32:
17531 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17532 case EXPAND_FROM_MEM: {
17534 SDValue Mask = Op.getOperand(4);
17535 SDValue PassThru = Op.getOperand(3);
17536 SDValue Addr = Op.getOperand(2);
17537 SDValue Chain = Op.getOperand(0);
17538 MVT VT = Op.getSimpleValueType();
17540 if (isAllOnesConstant(Mask)) // return just a load
17541 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17542 false, VT.getScalarSizeInBits()/8);
17544 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17545 false, false, false,
17546 VT.getScalarSizeInBits()/8);
17548 SDValue Results[] = {
17549 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17550 Mask, PassThru, Subtarget, DAG), Chain};
17551 return DAG.getMergeValues(Results, dl);
17556 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17557 SelectionDAG &DAG) const {
17558 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17559 MFI->setReturnAddressIsTaken(true);
17561 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17564 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17566 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17569 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17570 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17571 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17572 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17573 DAG.getNode(ISD::ADD, dl, PtrVT,
17574 FrameAddr, Offset),
17575 MachinePointerInfo(), false, false, false, 0);
17578 // Just load the return address.
17579 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17580 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17581 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17584 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17585 MachineFunction &MF = DAG.getMachineFunction();
17586 MachineFrameInfo *MFI = MF.getFrameInfo();
17587 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17588 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17589 EVT VT = Op.getValueType();
17591 MFI->setFrameAddressIsTaken(true);
17593 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17594 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17595 // is not possible to crawl up the stack without looking at the unwind codes
17597 int FrameAddrIndex = FuncInfo->getFAIndex();
17598 if (!FrameAddrIndex) {
17599 // Set up a frame object for the return address.
17600 unsigned SlotSize = RegInfo->getSlotSize();
17601 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17602 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17603 FuncInfo->setFAIndex(FrameAddrIndex);
17605 return DAG.getFrameIndex(FrameAddrIndex, VT);
17608 unsigned FrameReg =
17609 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17610 SDLoc dl(Op); // FIXME probably not meaningful
17611 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17612 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17613 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17614 "Invalid Frame Register!");
17615 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17617 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17618 MachinePointerInfo(),
17619 false, false, false, 0);
17623 // FIXME? Maybe this could be a TableGen attribute on some registers and
17624 // this table could be generated automatically from RegInfo.
17625 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17626 SelectionDAG &DAG) const {
17627 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17628 const MachineFunction &MF = DAG.getMachineFunction();
17630 unsigned Reg = StringSwitch<unsigned>(RegName)
17631 .Case("esp", X86::ESP)
17632 .Case("rsp", X86::RSP)
17633 .Case("ebp", X86::EBP)
17634 .Case("rbp", X86::RBP)
17637 if (Reg == X86::EBP || Reg == X86::RBP) {
17638 if (!TFI.hasFP(MF))
17639 report_fatal_error("register " + StringRef(RegName) +
17640 " is allocatable: function has no frame pointer");
17643 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17644 unsigned FrameReg =
17645 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17646 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17647 "Invalid Frame Register!");
17655 report_fatal_error("Invalid register name global variable");
17658 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17659 SelectionDAG &DAG) const {
17660 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17661 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17664 unsigned X86TargetLowering::getExceptionPointerRegister(
17665 const Constant *PersonalityFn) const {
17666 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17667 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17669 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17672 unsigned X86TargetLowering::getExceptionSelectorRegister(
17673 const Constant *PersonalityFn) const {
17674 // Funclet personalities don't use selectors (the runtime does the selection).
17675 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17676 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17679 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17680 SDValue Chain = Op.getOperand(0);
17681 SDValue Offset = Op.getOperand(1);
17682 SDValue Handler = Op.getOperand(2);
17685 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17686 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17687 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17688 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17689 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17690 "Invalid Frame Register!");
17691 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17692 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17694 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17695 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17697 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17698 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17700 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17702 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17703 DAG.getRegister(StoreAddrReg, PtrVT));
17706 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17707 SelectionDAG &DAG) const {
17709 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17710 DAG.getVTList(MVT::i32, MVT::Other),
17711 Op.getOperand(0), Op.getOperand(1));
17714 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17715 SelectionDAG &DAG) const {
17717 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17718 Op.getOperand(0), Op.getOperand(1));
17721 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17722 return Op.getOperand(0);
17725 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17726 SelectionDAG &DAG) const {
17727 SDValue Root = Op.getOperand(0);
17728 SDValue Trmp = Op.getOperand(1); // trampoline
17729 SDValue FPtr = Op.getOperand(2); // nested function
17730 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17733 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17734 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17736 if (Subtarget->is64Bit()) {
17737 SDValue OutChains[6];
17739 // Large code-model.
17740 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17741 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17743 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17744 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17746 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17748 // Load the pointer to the nested function into R11.
17749 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17750 SDValue Addr = Trmp;
17751 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17752 Addr, MachinePointerInfo(TrmpAddr),
17755 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17756 DAG.getConstant(2, dl, MVT::i64));
17757 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17758 MachinePointerInfo(TrmpAddr, 2),
17761 // Load the 'nest' parameter value into R10.
17762 // R10 is specified in X86CallingConv.td
17763 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17764 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17765 DAG.getConstant(10, dl, MVT::i64));
17766 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17767 Addr, MachinePointerInfo(TrmpAddr, 10),
17770 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17771 DAG.getConstant(12, dl, MVT::i64));
17772 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17773 MachinePointerInfo(TrmpAddr, 12),
17776 // Jump to the nested function.
17777 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17778 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17779 DAG.getConstant(20, dl, MVT::i64));
17780 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17781 Addr, MachinePointerInfo(TrmpAddr, 20),
17784 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17785 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17786 DAG.getConstant(22, dl, MVT::i64));
17787 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17788 Addr, MachinePointerInfo(TrmpAddr, 22),
17791 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17793 const Function *Func =
17794 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17795 CallingConv::ID CC = Func->getCallingConv();
17800 llvm_unreachable("Unsupported calling convention");
17801 case CallingConv::C:
17802 case CallingConv::X86_StdCall: {
17803 // Pass 'nest' parameter in ECX.
17804 // Must be kept in sync with X86CallingConv.td
17805 NestReg = X86::ECX;
17807 // Check that ECX wasn't needed by an 'inreg' parameter.
17808 FunctionType *FTy = Func->getFunctionType();
17809 const AttributeSet &Attrs = Func->getAttributes();
17811 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17812 unsigned InRegCount = 0;
17815 for (FunctionType::param_iterator I = FTy->param_begin(),
17816 E = FTy->param_end(); I != E; ++I, ++Idx)
17817 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17818 auto &DL = DAG.getDataLayout();
17819 // FIXME: should only count parameters that are lowered to integers.
17820 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17823 if (InRegCount > 2) {
17824 report_fatal_error("Nest register in use - reduce number of inreg"
17830 case CallingConv::X86_FastCall:
17831 case CallingConv::X86_ThisCall:
17832 case CallingConv::Fast:
17833 // Pass 'nest' parameter in EAX.
17834 // Must be kept in sync with X86CallingConv.td
17835 NestReg = X86::EAX;
17839 SDValue OutChains[4];
17840 SDValue Addr, Disp;
17842 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17843 DAG.getConstant(10, dl, MVT::i32));
17844 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17846 // This is storing the opcode for MOV32ri.
17847 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17848 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17849 OutChains[0] = DAG.getStore(Root, dl,
17850 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17851 Trmp, MachinePointerInfo(TrmpAddr),
17854 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17855 DAG.getConstant(1, dl, MVT::i32));
17856 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17857 MachinePointerInfo(TrmpAddr, 1),
17860 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17861 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17862 DAG.getConstant(5, dl, MVT::i32));
17863 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17864 Addr, MachinePointerInfo(TrmpAddr, 5),
17867 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17868 DAG.getConstant(6, dl, MVT::i32));
17869 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17870 MachinePointerInfo(TrmpAddr, 6),
17873 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17877 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17878 SelectionDAG &DAG) const {
17880 The rounding mode is in bits 11:10 of FPSR, and has the following
17882 00 Round to nearest
17887 FLT_ROUNDS, on the other hand, expects the following:
17894 To perform the conversion, we do:
17895 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17898 MachineFunction &MF = DAG.getMachineFunction();
17899 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17900 unsigned StackAlignment = TFI.getStackAlignment();
17901 MVT VT = Op.getSimpleValueType();
17904 // Save FP Control Word to stack slot
17905 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17906 SDValue StackSlot =
17907 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17909 MachineMemOperand *MMO =
17910 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17911 MachineMemOperand::MOStore, 2, 2);
17913 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17914 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17915 DAG.getVTList(MVT::Other),
17916 Ops, MVT::i16, MMO);
17918 // Load FP Control Word from stack slot
17919 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17920 MachinePointerInfo(), false, false, false, 0);
17922 // Transform as necessary
17924 DAG.getNode(ISD::SRL, DL, MVT::i16,
17925 DAG.getNode(ISD::AND, DL, MVT::i16,
17926 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17927 DAG.getConstant(11, DL, MVT::i8));
17929 DAG.getNode(ISD::SRL, DL, MVT::i16,
17930 DAG.getNode(ISD::AND, DL, MVT::i16,
17931 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17932 DAG.getConstant(9, DL, MVT::i8));
17935 DAG.getNode(ISD::AND, DL, MVT::i16,
17936 DAG.getNode(ISD::ADD, DL, MVT::i16,
17937 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17938 DAG.getConstant(1, DL, MVT::i16)),
17939 DAG.getConstant(3, DL, MVT::i16));
17941 return DAG.getNode((VT.getSizeInBits() < 16 ?
17942 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17945 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17947 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17948 // to 512-bit vector.
17949 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17950 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17951 // split the vector, perform operation on it's Lo a Hi part and
17952 // concatenate the results.
17953 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17955 MVT VT = Op.getSimpleValueType();
17956 MVT EltVT = VT.getVectorElementType();
17957 unsigned NumElems = VT.getVectorNumElements();
17959 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17960 // Extend to 512 bit vector.
17961 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17962 "Unsupported value type for operation");
17964 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17965 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17966 DAG.getUNDEF(NewVT),
17968 DAG.getIntPtrConstant(0, dl));
17969 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17971 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17972 DAG.getIntPtrConstant(0, dl));
17975 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17976 "Unsupported element type");
17978 if (16 < NumElems) {
17979 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17981 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17982 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17984 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17985 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17987 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17990 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17992 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17993 "Unsupported value type for operation");
17995 // Use native supported vector instruction vplzcntd.
17996 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17997 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17998 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17999 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
18001 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
18004 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
18005 SelectionDAG &DAG) {
18006 MVT VT = Op.getSimpleValueType();
18008 unsigned NumBits = VT.getSizeInBits();
18011 if (VT.isVector() && Subtarget->hasAVX512())
18012 return LowerVectorCTLZ_AVX512(Op, DAG);
18014 Op = Op.getOperand(0);
18015 if (VT == MVT::i8) {
18016 // Zero extend to i32 since there is not an i8 bsr.
18018 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18021 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
18022 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18023 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18025 // If src is zero (i.e. bsr sets ZF), returns NumBits.
18028 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
18029 DAG.getConstant(X86::COND_E, dl, MVT::i8),
18032 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
18034 // Finally xor with NumBits-1.
18035 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
18036 DAG.getConstant(NumBits - 1, dl, OpVT));
18039 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18043 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
18044 SelectionDAG &DAG) {
18045 MVT VT = Op.getSimpleValueType();
18047 unsigned NumBits = VT.getSizeInBits();
18050 Op = Op.getOperand(0);
18051 if (VT == MVT::i8) {
18052 // Zero extend to i32 since there is not an i8 bsr.
18054 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
18057 // Issue a bsr (scan bits in reverse).
18058 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
18059 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
18061 // And xor with NumBits-1.
18062 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
18063 DAG.getConstant(NumBits - 1, dl, OpVT));
18066 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
18070 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
18071 MVT VT = Op.getSimpleValueType();
18072 unsigned NumBits = VT.getScalarSizeInBits();
18075 if (VT.isVector()) {
18076 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18078 SDValue N0 = Op.getOperand(0);
18079 SDValue Zero = DAG.getConstant(0, dl, VT);
18081 // lsb(x) = (x & -x)
18082 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
18083 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
18085 // cttz_undef(x) = (width - 1) - ctlz(lsb)
18086 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
18087 TLI.isOperationLegal(ISD::CTLZ, VT)) {
18088 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
18089 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
18090 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
18093 // cttz(x) = ctpop(lsb - 1)
18094 SDValue One = DAG.getConstant(1, dl, VT);
18095 return DAG.getNode(ISD::CTPOP, dl, VT,
18096 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
18099 assert(Op.getOpcode() == ISD::CTTZ &&
18100 "Only scalar CTTZ requires custom lowering");
18102 // Issue a bsf (scan bits forward) which also sets EFLAGS.
18103 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18104 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
18106 // If src is zero (i.e. bsf sets ZF), returns NumBits.
18109 DAG.getConstant(NumBits, dl, VT),
18110 DAG.getConstant(X86::COND_E, dl, MVT::i8),
18113 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
18116 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
18117 // ones, and then concatenate the result back.
18118 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
18119 MVT VT = Op.getSimpleValueType();
18121 assert(VT.is256BitVector() && VT.isInteger() &&
18122 "Unsupported value type for operation");
18124 unsigned NumElems = VT.getVectorNumElements();
18127 // Extract the LHS vectors
18128 SDValue LHS = Op.getOperand(0);
18129 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
18130 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
18132 // Extract the RHS vectors
18133 SDValue RHS = Op.getOperand(1);
18134 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
18135 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
18137 MVT EltVT = VT.getVectorElementType();
18138 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18140 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18141 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
18142 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
18145 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
18146 if (Op.getValueType() == MVT::i1)
18147 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
18148 Op.getOperand(0), Op.getOperand(1));
18149 assert(Op.getSimpleValueType().is256BitVector() &&
18150 Op.getSimpleValueType().isInteger() &&
18151 "Only handle AVX 256-bit vector integer operation");
18152 return Lower256IntArith(Op, DAG);
18155 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
18156 if (Op.getValueType() == MVT::i1)
18157 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
18158 Op.getOperand(0), Op.getOperand(1));
18159 assert(Op.getSimpleValueType().is256BitVector() &&
18160 Op.getSimpleValueType().isInteger() &&
18161 "Only handle AVX 256-bit vector integer operation");
18162 return Lower256IntArith(Op, DAG);
18165 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
18166 assert(Op.getSimpleValueType().is256BitVector() &&
18167 Op.getSimpleValueType().isInteger() &&
18168 "Only handle AVX 256-bit vector integer operation");
18169 return Lower256IntArith(Op, DAG);
18172 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
18173 SelectionDAG &DAG) {
18175 MVT VT = Op.getSimpleValueType();
18178 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
18180 // Decompose 256-bit ops into smaller 128-bit ops.
18181 if (VT.is256BitVector() && !Subtarget->hasInt256())
18182 return Lower256IntArith(Op, DAG);
18184 SDValue A = Op.getOperand(0);
18185 SDValue B = Op.getOperand(1);
18187 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
18188 // pairs, multiply and truncate.
18189 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
18190 if (Subtarget->hasInt256()) {
18191 if (VT == MVT::v32i8) {
18192 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
18193 SDValue Lo = DAG.getIntPtrConstant(0, dl);
18194 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
18195 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
18196 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
18197 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
18198 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
18199 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
18200 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
18201 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
18204 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
18205 return DAG.getNode(
18206 ISD::TRUNCATE, dl, VT,
18207 DAG.getNode(ISD::MUL, dl, ExVT,
18208 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
18209 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
18212 assert(VT == MVT::v16i8 &&
18213 "Pre-AVX2 support only supports v16i8 multiplication");
18214 MVT ExVT = MVT::v8i16;
18216 // Extract the lo parts and sign extend to i16
18218 if (Subtarget->hasSSE41()) {
18219 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
18220 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
18222 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
18223 -1, 4, -1, 5, -1, 6, -1, 7};
18224 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18225 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18226 ALo = DAG.getBitcast(ExVT, ALo);
18227 BLo = DAG.getBitcast(ExVT, BLo);
18228 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
18229 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
18232 // Extract the hi parts and sign extend to i16
18234 if (Subtarget->hasSSE41()) {
18235 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
18236 -1, -1, -1, -1, -1, -1, -1, -1};
18237 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18238 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18239 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
18240 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
18242 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
18243 -1, 12, -1, 13, -1, 14, -1, 15};
18244 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
18245 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
18246 AHi = DAG.getBitcast(ExVT, AHi);
18247 BHi = DAG.getBitcast(ExVT, BHi);
18248 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
18249 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
18252 // Multiply, mask the lower 8bits of the lo/hi results and pack
18253 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
18254 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
18255 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
18256 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
18257 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18260 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
18261 if (VT == MVT::v4i32) {
18262 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
18263 "Should not custom lower when pmuldq is available!");
18265 // Extract the odd parts.
18266 static const int UnpackMask[] = { 1, -1, 3, -1 };
18267 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
18268 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
18270 // Multiply the even parts.
18271 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
18272 // Now multiply odd parts.
18273 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
18275 Evens = DAG.getBitcast(VT, Evens);
18276 Odds = DAG.getBitcast(VT, Odds);
18278 // Merge the two vectors back together with a shuffle. This expands into 2
18280 static const int ShufMask[] = { 0, 4, 2, 6 };
18281 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
18284 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18285 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18287 // Ahi = psrlqi(a, 32);
18288 // Bhi = psrlqi(b, 32);
18290 // AloBlo = pmuludq(a, b);
18291 // AloBhi = pmuludq(a, Bhi);
18292 // AhiBlo = pmuludq(Ahi, b);
18294 // AloBhi = psllqi(AloBhi, 32);
18295 // AhiBlo = psllqi(AhiBlo, 32);
18296 // return AloBlo + AloBhi + AhiBlo;
18298 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18299 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18301 SDValue AhiBlo = Ahi;
18302 SDValue AloBhi = Bhi;
18303 // Bit cast to 32-bit vectors for MULUDQ
18304 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18305 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18306 A = DAG.getBitcast(MulVT, A);
18307 B = DAG.getBitcast(MulVT, B);
18308 Ahi = DAG.getBitcast(MulVT, Ahi);
18309 Bhi = DAG.getBitcast(MulVT, Bhi);
18311 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18312 // After shifting right const values the result may be all-zero.
18313 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18314 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18315 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18317 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18318 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18319 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18322 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18323 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18326 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18327 assert(Subtarget->isTargetWin64() && "Unexpected target");
18328 EVT VT = Op.getValueType();
18329 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18330 "Unexpected return type for lowering");
18334 switch (Op->getOpcode()) {
18335 default: llvm_unreachable("Unexpected request for libcall!");
18336 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18337 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18338 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18339 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18340 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18341 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18345 SDValue InChain = DAG.getEntryNode();
18347 TargetLowering::ArgListTy Args;
18348 TargetLowering::ArgListEntry Entry;
18349 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18350 EVT ArgVT = Op->getOperand(i).getValueType();
18351 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18352 "Unexpected argument type for lowering");
18353 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18354 Entry.Node = StackPtr;
18355 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18357 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18358 Entry.Ty = PointerType::get(ArgTy,0);
18359 Entry.isSExt = false;
18360 Entry.isZExt = false;
18361 Args.push_back(Entry);
18364 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18365 getPointerTy(DAG.getDataLayout()));
18367 TargetLowering::CallLoweringInfo CLI(DAG);
18368 CLI.setDebugLoc(dl).setChain(InChain)
18369 .setCallee(getLibcallCallingConv(LC),
18370 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18371 Callee, std::move(Args), 0)
18372 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18374 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18375 return DAG.getBitcast(VT, CallInfo.first);
18378 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18379 SelectionDAG &DAG) {
18380 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18381 MVT VT = Op0.getSimpleValueType();
18384 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18385 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18387 // PMULxD operations multiply each even value (starting at 0) of LHS with
18388 // the related value of RHS and produce a widen result.
18389 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18390 // => <2 x i64> <ae|cg>
18392 // In other word, to have all the results, we need to perform two PMULxD:
18393 // 1. one with the even values.
18394 // 2. one with the odd values.
18395 // To achieve #2, with need to place the odd values at an even position.
18397 // Place the odd value at an even position (basically, shift all values 1
18398 // step to the left):
18399 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18400 // <a|b|c|d> => <b|undef|d|undef>
18401 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18402 // <e|f|g|h> => <f|undef|h|undef>
18403 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18405 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18407 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18408 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18410 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18411 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18412 // => <2 x i64> <ae|cg>
18413 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18414 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18415 // => <2 x i64> <bf|dh>
18416 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18418 // Shuffle it back into the right order.
18419 SDValue Highs, Lows;
18420 if (VT == MVT::v8i32) {
18421 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18422 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18423 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18424 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18426 const int HighMask[] = {1, 5, 3, 7};
18427 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18428 const int LowMask[] = {0, 4, 2, 6};
18429 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18432 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18433 // unsigned multiply.
18434 if (IsSigned && !Subtarget->hasSSE41()) {
18435 SDValue ShAmt = DAG.getConstant(
18437 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18438 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18439 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18440 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18441 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18443 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18444 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18447 // The first result of MUL_LOHI is actually the low value, followed by the
18449 SDValue Ops[] = {Lows, Highs};
18450 return DAG.getMergeValues(Ops, dl);
18453 // Return true if the required (according to Opcode) shift-imm form is natively
18454 // supported by the Subtarget
18455 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18457 if (VT.getScalarSizeInBits() < 16)
18460 if (VT.is512BitVector() &&
18461 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18464 bool LShift = VT.is128BitVector() ||
18465 (VT.is256BitVector() && Subtarget->hasInt256());
18467 bool AShift = LShift && (Subtarget->hasVLX() ||
18468 (VT != MVT::v2i64 && VT != MVT::v4i64));
18469 return (Opcode == ISD::SRA) ? AShift : LShift;
18472 // The shift amount is a variable, but it is the same for all vector lanes.
18473 // These instructions are defined together with shift-immediate.
18475 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18477 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18480 // Return true if the required (according to Opcode) variable-shift form is
18481 // natively supported by the Subtarget
18482 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18485 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18488 // vXi16 supported only on AVX-512, BWI
18489 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18492 if (VT.is512BitVector() || Subtarget->hasVLX())
18495 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18496 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18497 return (Opcode == ISD::SRA) ? AShift : LShift;
18500 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18501 const X86Subtarget *Subtarget) {
18502 MVT VT = Op.getSimpleValueType();
18504 SDValue R = Op.getOperand(0);
18505 SDValue Amt = Op.getOperand(1);
18507 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18508 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18510 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18511 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18512 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18513 SDValue Ex = DAG.getBitcast(ExVT, R);
18515 if (ShiftAmt >= 32) {
18516 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18518 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18519 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18520 ShiftAmt - 32, DAG);
18521 if (VT == MVT::v2i64)
18522 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18523 if (VT == MVT::v4i64)
18524 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18525 {9, 1, 11, 3, 13, 5, 15, 7});
18527 // SRA upper i32, SHL whole i64 and select lower i32.
18528 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18531 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18532 Lower = DAG.getBitcast(ExVT, Lower);
18533 if (VT == MVT::v2i64)
18534 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18535 if (VT == MVT::v4i64)
18536 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18537 {8, 1, 10, 3, 12, 5, 14, 7});
18539 return DAG.getBitcast(VT, Ex);
18542 // Optimize shl/srl/sra with constant shift amount.
18543 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18544 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18545 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18547 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18548 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18550 // i64 SRA needs to be performed as partial shifts.
18551 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18552 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18553 return ArithmeticShiftRight64(ShiftAmt);
18555 if (VT == MVT::v16i8 ||
18556 (Subtarget->hasInt256() && VT == MVT::v32i8) ||
18557 VT == MVT::v64i8) {
18558 unsigned NumElts = VT.getVectorNumElements();
18559 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18561 // Simple i8 add case
18562 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18563 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18565 // ashr(R, 7) === cmp_slt(R, 0)
18566 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18567 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18568 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18571 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18572 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18575 if (Op.getOpcode() == ISD::SHL) {
18576 // Make a large shift.
18577 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18579 SHL = DAG.getBitcast(VT, SHL);
18580 // Zero out the rightmost bits.
18581 return DAG.getNode(ISD::AND, dl, VT, SHL,
18582 DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, VT));
18584 if (Op.getOpcode() == ISD::SRL) {
18585 // Make a large shift.
18586 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18588 SRL = DAG.getBitcast(VT, SRL);
18589 // Zero out the leftmost bits.
18590 return DAG.getNode(ISD::AND, dl, VT, SRL,
18591 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, VT));
18593 if (Op.getOpcode() == ISD::SRA) {
18594 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18595 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18597 SDValue Mask = DAG.getConstant(128 >> ShiftAmt, dl, VT);
18598 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18599 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18602 llvm_unreachable("Unknown shift opcode.");
18607 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18608 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18609 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18611 // Peek through any splat that was introduced for i64 shift vectorization.
18612 int SplatIndex = -1;
18613 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18614 if (SVN->isSplat()) {
18615 SplatIndex = SVN->getSplatIndex();
18616 Amt = Amt.getOperand(0);
18617 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18618 "Splat shuffle referencing second operand");
18621 if (Amt.getOpcode() != ISD::BITCAST ||
18622 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18625 Amt = Amt.getOperand(0);
18626 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18627 VT.getVectorNumElements();
18628 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18629 uint64_t ShiftAmt = 0;
18630 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18631 for (unsigned i = 0; i != Ratio; ++i) {
18632 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18636 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18639 // Check remaining shift amounts (if not a splat).
18640 if (SplatIndex < 0) {
18641 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18642 uint64_t ShAmt = 0;
18643 for (unsigned j = 0; j != Ratio; ++j) {
18644 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18648 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18650 if (ShAmt != ShiftAmt)
18655 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18656 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18658 if (Op.getOpcode() == ISD::SRA)
18659 return ArithmeticShiftRight64(ShiftAmt);
18665 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18666 const X86Subtarget* Subtarget) {
18667 MVT VT = Op.getSimpleValueType();
18669 SDValue R = Op.getOperand(0);
18670 SDValue Amt = Op.getOperand(1);
18672 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18673 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18675 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18676 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18678 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18680 MVT EltVT = VT.getVectorElementType();
18682 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18683 // Check if this build_vector node is doing a splat.
18684 // If so, then set BaseShAmt equal to the splat value.
18685 BaseShAmt = BV->getSplatValue();
18686 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18687 BaseShAmt = SDValue();
18689 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18690 Amt = Amt.getOperand(0);
18692 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18693 if (SVN && SVN->isSplat()) {
18694 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18695 SDValue InVec = Amt.getOperand(0);
18696 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18697 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18698 "Unexpected shuffle index found!");
18699 BaseShAmt = InVec.getOperand(SplatIdx);
18700 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18701 if (ConstantSDNode *C =
18702 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18703 if (C->getZExtValue() == SplatIdx)
18704 BaseShAmt = InVec.getOperand(1);
18709 // Avoid introducing an extract element from a shuffle.
18710 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18711 DAG.getIntPtrConstant(SplatIdx, dl));
18715 if (BaseShAmt.getNode()) {
18716 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18717 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18718 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18719 else if (EltVT.bitsLT(MVT::i32))
18720 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18722 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18726 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18727 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18728 Amt.getOpcode() == ISD::BITCAST &&
18729 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18730 Amt = Amt.getOperand(0);
18731 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18732 VT.getVectorNumElements();
18733 std::vector<SDValue> Vals(Ratio);
18734 for (unsigned i = 0; i != Ratio; ++i)
18735 Vals[i] = Amt.getOperand(i);
18736 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18737 for (unsigned j = 0; j != Ratio; ++j)
18738 if (Vals[j] != Amt.getOperand(i + j))
18742 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18743 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18748 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18749 SelectionDAG &DAG) {
18750 MVT VT = Op.getSimpleValueType();
18752 SDValue R = Op.getOperand(0);
18753 SDValue Amt = Op.getOperand(1);
18755 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18756 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18758 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18761 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18764 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18767 // XOP has 128-bit variable logical/arithmetic shifts.
18768 // +ve/-ve Amt = shift left/right.
18769 if (Subtarget->hasXOP() &&
18770 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18771 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18772 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18773 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18774 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18776 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18777 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18778 if (Op.getOpcode() == ISD::SRA)
18779 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18782 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18783 // shifts per-lane and then shuffle the partial results back together.
18784 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18785 // Splat the shift amounts so the scalar shifts above will catch it.
18786 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18787 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18788 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18789 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18790 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18793 // i64 vector arithmetic shift can be emulated with the transform:
18794 // M = lshr(SIGN_BIT, Amt)
18795 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18796 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18797 Op.getOpcode() == ISD::SRA) {
18798 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18799 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18800 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18801 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18802 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18806 // If possible, lower this packed shift into a vector multiply instead of
18807 // expanding it into a sequence of scalar shifts.
18808 // Do this only if the vector shift count is a constant build_vector.
18809 if (Op.getOpcode() == ISD::SHL &&
18810 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18811 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18812 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18813 SmallVector<SDValue, 8> Elts;
18814 MVT SVT = VT.getVectorElementType();
18815 unsigned SVTBits = SVT.getSizeInBits();
18816 APInt One(SVTBits, 1);
18817 unsigned NumElems = VT.getVectorNumElements();
18819 for (unsigned i=0; i !=NumElems; ++i) {
18820 SDValue Op = Amt->getOperand(i);
18821 if (Op->getOpcode() == ISD::UNDEF) {
18822 Elts.push_back(Op);
18826 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18827 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18828 uint64_t ShAmt = C.getZExtValue();
18829 if (ShAmt >= SVTBits) {
18830 Elts.push_back(DAG.getUNDEF(SVT));
18833 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18835 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18836 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18839 // Lower SHL with variable shift amount.
18840 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18841 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18843 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18844 DAG.getConstant(0x3f800000U, dl, VT));
18845 Op = DAG.getBitcast(MVT::v4f32, Op);
18846 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18847 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18850 // If possible, lower this shift as a sequence of two shifts by
18851 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18853 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18855 // Could be rewritten as:
18856 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18858 // The advantage is that the two shifts from the example would be
18859 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18860 // the vector shift into four scalar shifts plus four pairs of vector
18862 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18863 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18864 unsigned TargetOpcode = X86ISD::MOVSS;
18865 bool CanBeSimplified;
18866 // The splat value for the first packed shift (the 'X' from the example).
18867 SDValue Amt1 = Amt->getOperand(0);
18868 // The splat value for the second packed shift (the 'Y' from the example).
18869 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18870 Amt->getOperand(2);
18872 // See if it is possible to replace this node with a sequence of
18873 // two shifts followed by a MOVSS/MOVSD
18874 if (VT == MVT::v4i32) {
18875 // Check if it is legal to use a MOVSS.
18876 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18877 Amt2 == Amt->getOperand(3);
18878 if (!CanBeSimplified) {
18879 // Otherwise, check if we can still simplify this node using a MOVSD.
18880 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18881 Amt->getOperand(2) == Amt->getOperand(3);
18882 TargetOpcode = X86ISD::MOVSD;
18883 Amt2 = Amt->getOperand(2);
18886 // Do similar checks for the case where the machine value type
18888 CanBeSimplified = Amt1 == Amt->getOperand(1);
18889 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18890 CanBeSimplified = Amt2 == Amt->getOperand(i);
18892 if (!CanBeSimplified) {
18893 TargetOpcode = X86ISD::MOVSD;
18894 CanBeSimplified = true;
18895 Amt2 = Amt->getOperand(4);
18896 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18897 CanBeSimplified = Amt1 == Amt->getOperand(i);
18898 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18899 CanBeSimplified = Amt2 == Amt->getOperand(j);
18903 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18904 isa<ConstantSDNode>(Amt2)) {
18905 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18906 MVT CastVT = MVT::v4i32;
18908 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18909 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18911 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18912 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18913 if (TargetOpcode == X86ISD::MOVSD)
18914 CastVT = MVT::v2i64;
18915 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18916 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18917 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18919 return DAG.getBitcast(VT, Result);
18923 // v4i32 Non Uniform Shifts.
18924 // If the shift amount is constant we can shift each lane using the SSE2
18925 // immediate shifts, else we need to zero-extend each lane to the lower i64
18926 // and shift using the SSE2 variable shifts.
18927 // The separate results can then be blended together.
18928 if (VT == MVT::v4i32) {
18929 unsigned Opc = Op.getOpcode();
18930 SDValue Amt0, Amt1, Amt2, Amt3;
18931 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18932 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18933 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18934 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18935 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18937 // ISD::SHL is handled above but we include it here for completeness.
18940 llvm_unreachable("Unknown target vector shift node");
18942 Opc = X86ISD::VSHL;
18945 Opc = X86ISD::VSRL;
18948 Opc = X86ISD::VSRA;
18951 // The SSE2 shifts use the lower i64 as the same shift amount for
18952 // all lanes and the upper i64 is ignored. These shuffle masks
18953 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18954 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18955 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18956 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18957 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18958 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18961 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18962 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18963 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18964 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18965 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18966 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18967 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18970 if (VT == MVT::v16i8 ||
18971 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18972 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18973 unsigned ShiftOpcode = Op->getOpcode();
18975 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18976 // On SSE41 targets we make use of the fact that VSELECT lowers
18977 // to PBLENDVB which selects bytes based just on the sign bit.
18978 if (Subtarget->hasSSE41()) {
18979 V0 = DAG.getBitcast(VT, V0);
18980 V1 = DAG.getBitcast(VT, V1);
18981 Sel = DAG.getBitcast(VT, Sel);
18982 return DAG.getBitcast(SelVT,
18983 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18985 // On pre-SSE41 targets we test for the sign bit by comparing to
18986 // zero - a negative value will set all bits of the lanes to true
18987 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18988 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18989 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18990 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18993 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18994 // We can safely do this using i16 shifts as we're only interested in
18995 // the 3 lower bits of each byte.
18996 Amt = DAG.getBitcast(ExtVT, Amt);
18997 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18998 Amt = DAG.getBitcast(VT, Amt);
19000 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
19001 // r = VSELECT(r, shift(r, 4), a);
19003 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
19004 R = SignBitSelect(VT, Amt, M, R);
19007 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19009 // r = VSELECT(r, shift(r, 2), a);
19010 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
19011 R = SignBitSelect(VT, Amt, M, R);
19014 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19016 // return VSELECT(r, shift(r, 1), a);
19017 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
19018 R = SignBitSelect(VT, Amt, M, R);
19022 if (Op->getOpcode() == ISD::SRA) {
19023 // For SRA we need to unpack each byte to the higher byte of a i16 vector
19024 // so we can correctly sign extend. We don't care what happens to the
19026 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
19027 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
19028 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
19029 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
19030 ALo = DAG.getBitcast(ExtVT, ALo);
19031 AHi = DAG.getBitcast(ExtVT, AHi);
19032 RLo = DAG.getBitcast(ExtVT, RLo);
19033 RHi = DAG.getBitcast(ExtVT, RHi);
19035 // r = VSELECT(r, shift(r, 4), a);
19036 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
19037 DAG.getConstant(4, dl, ExtVT));
19038 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
19039 DAG.getConstant(4, dl, ExtVT));
19040 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
19041 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
19044 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
19045 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
19047 // r = VSELECT(r, shift(r, 2), a);
19048 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
19049 DAG.getConstant(2, dl, ExtVT));
19050 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
19051 DAG.getConstant(2, dl, ExtVT));
19052 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
19053 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
19056 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
19057 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
19059 // r = VSELECT(r, shift(r, 1), a);
19060 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
19061 DAG.getConstant(1, dl, ExtVT));
19062 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
19063 DAG.getConstant(1, dl, ExtVT));
19064 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
19065 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
19067 // Logical shift the result back to the lower byte, leaving a zero upper
19069 // meaning that we can safely pack with PACKUSWB.
19071 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
19073 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
19074 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
19078 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
19079 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
19080 // solution better.
19081 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
19082 MVT ExtVT = MVT::v8i32;
19084 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
19085 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
19086 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
19087 return DAG.getNode(ISD::TRUNCATE, dl, VT,
19088 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
19091 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
19092 MVT ExtVT = MVT::v8i32;
19093 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
19094 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
19095 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
19096 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
19097 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
19098 ALo = DAG.getBitcast(ExtVT, ALo);
19099 AHi = DAG.getBitcast(ExtVT, AHi);
19100 RLo = DAG.getBitcast(ExtVT, RLo);
19101 RHi = DAG.getBitcast(ExtVT, RHi);
19102 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
19103 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
19104 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
19105 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
19106 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
19109 if (VT == MVT::v8i16) {
19110 unsigned ShiftOpcode = Op->getOpcode();
19112 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
19113 // On SSE41 targets we make use of the fact that VSELECT lowers
19114 // to PBLENDVB which selects bytes based just on the sign bit.
19115 if (Subtarget->hasSSE41()) {
19116 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
19117 V0 = DAG.getBitcast(ExtVT, V0);
19118 V1 = DAG.getBitcast(ExtVT, V1);
19119 Sel = DAG.getBitcast(ExtVT, Sel);
19120 return DAG.getBitcast(
19121 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
19123 // On pre-SSE41 targets we splat the sign bit - a negative value will
19124 // set all bits of the lanes to true and VSELECT uses that in
19125 // its OR(AND(V0,C),AND(V1,~C)) lowering.
19127 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
19128 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
19131 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
19132 if (Subtarget->hasSSE41()) {
19133 // On SSE41 targets we need to replicate the shift mask in both
19134 // bytes for PBLENDVB.
19137 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
19138 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
19140 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
19143 // r = VSELECT(r, shift(r, 8), a);
19144 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
19145 R = SignBitSelect(Amt, M, R);
19148 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19150 // r = VSELECT(r, shift(r, 4), a);
19151 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
19152 R = SignBitSelect(Amt, M, R);
19155 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19157 // r = VSELECT(r, shift(r, 2), a);
19158 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
19159 R = SignBitSelect(Amt, M, R);
19162 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
19164 // return VSELECT(r, shift(r, 1), a);
19165 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
19166 R = SignBitSelect(Amt, M, R);
19170 // Decompose 256-bit shifts into smaller 128-bit shifts.
19171 if (VT.is256BitVector()) {
19172 unsigned NumElems = VT.getVectorNumElements();
19173 MVT EltVT = VT.getVectorElementType();
19174 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
19176 // Extract the two vectors
19177 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
19178 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
19180 // Recreate the shift amount vectors
19181 SDValue Amt1, Amt2;
19182 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
19183 // Constant shift amount
19184 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
19185 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
19186 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
19188 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
19189 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
19191 // Variable shift amount
19192 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
19193 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
19196 // Issue new vector shifts for the smaller types
19197 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
19198 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
19200 // Concatenate the result back
19201 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
19207 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
19208 SelectionDAG &DAG) {
19209 MVT VT = Op.getSimpleValueType();
19211 SDValue R = Op.getOperand(0);
19212 SDValue Amt = Op.getOperand(1);
19214 assert(VT.isVector() && "Custom lowering only for vector rotates!");
19215 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
19216 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
19218 // XOP has 128-bit vector variable + immediate rotates.
19219 // +ve/-ve Amt = rotate left/right.
19221 // Split 256-bit integers.
19222 if (VT.is256BitVector())
19223 return Lower256IntArith(Op, DAG);
19225 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
19227 // Attempt to rotate by immediate.
19228 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
19229 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
19230 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
19231 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
19232 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
19233 DAG.getConstant(RotateAmt, DL, MVT::i8));
19237 // Use general rotate by variable (per-element).
19238 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
19241 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
19242 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
19243 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
19244 // looks for this combo and may remove the "setcc" instruction if the "setcc"
19245 // has only one use.
19246 SDNode *N = Op.getNode();
19247 SDValue LHS = N->getOperand(0);
19248 SDValue RHS = N->getOperand(1);
19249 unsigned BaseOp = 0;
19252 switch (Op.getOpcode()) {
19253 default: llvm_unreachable("Unknown ovf instruction!");
19255 // A subtract of one will be selected as a INC. Note that INC doesn't
19256 // set CF, so we can't do this for UADDO.
19257 if (isOneConstant(RHS)) {
19258 BaseOp = X86ISD::INC;
19259 Cond = X86::COND_O;
19262 BaseOp = X86ISD::ADD;
19263 Cond = X86::COND_O;
19266 BaseOp = X86ISD::ADD;
19267 Cond = X86::COND_B;
19270 // A subtract of one will be selected as a DEC. Note that DEC doesn't
19271 // set CF, so we can't do this for USUBO.
19272 if (isOneConstant(RHS)) {
19273 BaseOp = X86ISD::DEC;
19274 Cond = X86::COND_O;
19277 BaseOp = X86ISD::SUB;
19278 Cond = X86::COND_O;
19281 BaseOp = X86ISD::SUB;
19282 Cond = X86::COND_B;
19285 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19286 Cond = X86::COND_O;
19288 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19289 if (N->getValueType(0) == MVT::i8) {
19290 BaseOp = X86ISD::UMUL8;
19291 Cond = X86::COND_O;
19294 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19296 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19299 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19300 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19301 SDValue(Sum.getNode(), 2));
19303 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19307 // Also sets EFLAGS.
19308 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19309 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19312 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19313 DAG.getConstant(Cond, DL, MVT::i32),
19314 SDValue(Sum.getNode(), 1));
19316 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19319 /// Returns true if the operand type is exactly twice the native width, and
19320 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19321 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19322 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19323 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19324 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19327 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19328 else if (OpWidth == 128)
19329 return Subtarget->hasCmpxchg16b();
19334 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19335 return needsCmpXchgNb(SI->getValueOperand()->getType());
19338 // Note: this turns large loads into lock cmpxchg8b/16b.
19339 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19340 TargetLowering::AtomicExpansionKind
19341 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19342 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19343 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19344 : AtomicExpansionKind::None;
19347 TargetLowering::AtomicExpansionKind
19348 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19349 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19350 Type *MemType = AI->getType();
19352 // If the operand is too big, we must see if cmpxchg8/16b is available
19353 // and default to library calls otherwise.
19354 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19355 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19356 : AtomicExpansionKind::None;
19359 AtomicRMWInst::BinOp Op = AI->getOperation();
19362 llvm_unreachable("Unknown atomic operation");
19363 case AtomicRMWInst::Xchg:
19364 case AtomicRMWInst::Add:
19365 case AtomicRMWInst::Sub:
19366 // It's better to use xadd, xsub or xchg for these in all cases.
19367 return AtomicExpansionKind::None;
19368 case AtomicRMWInst::Or:
19369 case AtomicRMWInst::And:
19370 case AtomicRMWInst::Xor:
19371 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19372 // prefix to a normal instruction for these operations.
19373 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19374 : AtomicExpansionKind::None;
19375 case AtomicRMWInst::Nand:
19376 case AtomicRMWInst::Max:
19377 case AtomicRMWInst::Min:
19378 case AtomicRMWInst::UMax:
19379 case AtomicRMWInst::UMin:
19380 // These always require a non-trivial set of data operations on x86. We must
19381 // use a cmpxchg loop.
19382 return AtomicExpansionKind::CmpXChg;
19386 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19387 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19388 // no-sse2). There isn't any reason to disable it if the target processor
19390 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19394 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19395 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19396 Type *MemType = AI->getType();
19397 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19398 // there is no benefit in turning such RMWs into loads, and it is actually
19399 // harmful as it introduces a mfence.
19400 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19403 auto Builder = IRBuilder<>(AI);
19404 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19405 auto SynchScope = AI->getSynchScope();
19406 // We must restrict the ordering to avoid generating loads with Release or
19407 // ReleaseAcquire orderings.
19408 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19409 auto Ptr = AI->getPointerOperand();
19411 // Before the load we need a fence. Here is an example lifted from
19412 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19415 // x.store(1, relaxed);
19416 // r1 = y.fetch_add(0, release);
19418 // y.fetch_add(42, acquire);
19419 // r2 = x.load(relaxed);
19420 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19421 // lowered to just a load without a fence. A mfence flushes the store buffer,
19422 // making the optimization clearly correct.
19423 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19424 // otherwise, we might be able to be more aggressive on relaxed idempotent
19425 // rmw. In practice, they do not look useful, so we don't try to be
19426 // especially clever.
19427 if (SynchScope == SingleThread)
19428 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19429 // the IR level, so we must wrap it in an intrinsic.
19432 if (!hasMFENCE(*Subtarget))
19433 // FIXME: it might make sense to use a locked operation here but on a
19434 // different cache-line to prevent cache-line bouncing. In practice it
19435 // is probably a small win, and x86 processors without mfence are rare
19436 // enough that we do not bother.
19440 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19441 Builder.CreateCall(MFence, {});
19443 // Finally we can emit the atomic load.
19444 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19445 AI->getType()->getPrimitiveSizeInBits());
19446 Loaded->setAtomic(Order, SynchScope);
19447 AI->replaceAllUsesWith(Loaded);
19448 AI->eraseFromParent();
19452 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19453 SelectionDAG &DAG) {
19455 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19456 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19457 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19458 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19460 // The only fence that needs an instruction is a sequentially-consistent
19461 // cross-thread fence.
19462 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19463 if (hasMFENCE(*Subtarget))
19464 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19466 SDValue Chain = Op.getOperand(0);
19467 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19469 DAG.getRegister(X86::ESP, MVT::i32), // Base
19470 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19471 DAG.getRegister(0, MVT::i32), // Index
19472 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19473 DAG.getRegister(0, MVT::i32), // Segment.
19477 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19478 return SDValue(Res, 0);
19481 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19482 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19485 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19486 SelectionDAG &DAG) {
19487 MVT T = Op.getSimpleValueType();
19491 switch(T.SimpleTy) {
19492 default: llvm_unreachable("Invalid value type!");
19493 case MVT::i8: Reg = X86::AL; size = 1; break;
19494 case MVT::i16: Reg = X86::AX; size = 2; break;
19495 case MVT::i32: Reg = X86::EAX; size = 4; break;
19497 assert(Subtarget->is64Bit() && "Node not type legal!");
19498 Reg = X86::RAX; size = 8;
19501 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19502 Op.getOperand(2), SDValue());
19503 SDValue Ops[] = { cpIn.getValue(0),
19506 DAG.getTargetConstant(size, DL, MVT::i8),
19507 cpIn.getValue(1) };
19508 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19509 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19510 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19514 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19515 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19516 MVT::i32, cpOut.getValue(2));
19517 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19518 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19521 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19522 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19523 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19527 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19528 SelectionDAG &DAG) {
19529 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19530 MVT DstVT = Op.getSimpleValueType();
19532 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19533 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19534 if (DstVT != MVT::f64)
19535 // This conversion needs to be expanded.
19538 SDValue InVec = Op->getOperand(0);
19540 unsigned NumElts = SrcVT.getVectorNumElements();
19541 MVT SVT = SrcVT.getVectorElementType();
19543 // Widen the vector in input in the case of MVT::v2i32.
19544 // Example: from MVT::v2i32 to MVT::v4i32.
19545 SmallVector<SDValue, 16> Elts;
19546 for (unsigned i = 0, e = NumElts; i != e; ++i)
19547 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19548 DAG.getIntPtrConstant(i, dl)));
19550 // Explicitly mark the extra elements as Undef.
19551 Elts.append(NumElts, DAG.getUNDEF(SVT));
19553 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19554 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19555 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19556 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19557 DAG.getIntPtrConstant(0, dl));
19560 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19561 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19562 assert((DstVT == MVT::i64 ||
19563 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19564 "Unexpected custom BITCAST");
19565 // i64 <=> MMX conversions are Legal.
19566 if (SrcVT==MVT::i64 && DstVT.isVector())
19568 if (DstVT==MVT::i64 && SrcVT.isVector())
19570 // MMX <=> MMX conversions are Legal.
19571 if (SrcVT.isVector() && DstVT.isVector())
19573 // All other conversions need to be expanded.
19577 /// Compute the horizontal sum of bytes in V for the elements of VT.
19579 /// Requires V to be a byte vector and VT to be an integer vector type with
19580 /// wider elements than V's type. The width of the elements of VT determines
19581 /// how many bytes of V are summed horizontally to produce each element of the
19583 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19584 const X86Subtarget *Subtarget,
19585 SelectionDAG &DAG) {
19587 MVT ByteVecVT = V.getSimpleValueType();
19588 MVT EltVT = VT.getVectorElementType();
19589 int NumElts = VT.getVectorNumElements();
19590 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19591 "Expected value to have byte element type.");
19592 assert(EltVT != MVT::i8 &&
19593 "Horizontal byte sum only makes sense for wider elements!");
19594 unsigned VecSize = VT.getSizeInBits();
19595 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19597 // PSADBW instruction horizontally add all bytes and leave the result in i64
19598 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19599 if (EltVT == MVT::i64) {
19600 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19601 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19602 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19603 return DAG.getBitcast(VT, V);
19606 if (EltVT == MVT::i32) {
19607 // We unpack the low half and high half into i32s interleaved with zeros so
19608 // that we can use PSADBW to horizontally sum them. The most useful part of
19609 // this is that it lines up the results of two PSADBW instructions to be
19610 // two v2i64 vectors which concatenated are the 4 population counts. We can
19611 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19612 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19613 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19614 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19616 // Do the horizontal sums into two v2i64s.
19617 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19618 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19619 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19620 DAG.getBitcast(ByteVecVT, Low), Zeros);
19621 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19622 DAG.getBitcast(ByteVecVT, High), Zeros);
19624 // Merge them together.
19625 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19626 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19627 DAG.getBitcast(ShortVecVT, Low),
19628 DAG.getBitcast(ShortVecVT, High));
19630 return DAG.getBitcast(VT, V);
19633 // The only element type left is i16.
19634 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19636 // To obtain pop count for each i16 element starting from the pop count for
19637 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19638 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19639 // directly supported.
19640 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19641 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19642 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19643 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19644 DAG.getBitcast(ByteVecVT, V));
19645 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19648 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19649 const X86Subtarget *Subtarget,
19650 SelectionDAG &DAG) {
19651 MVT VT = Op.getSimpleValueType();
19652 MVT EltVT = VT.getVectorElementType();
19653 unsigned VecSize = VT.getSizeInBits();
19655 // Implement a lookup table in register by using an algorithm based on:
19656 // http://wm.ite.pl/articles/sse-popcount.html
19658 // The general idea is that every lower byte nibble in the input vector is an
19659 // index into a in-register pre-computed pop count table. We then split up the
19660 // input vector in two new ones: (1) a vector with only the shifted-right
19661 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19662 // masked out higher ones) for each byte. PSHUB is used separately with both
19663 // to index the in-register table. Next, both are added and the result is a
19664 // i8 vector where each element contains the pop count for input byte.
19666 // To obtain the pop count for elements != i8, we follow up with the same
19667 // approach and use additional tricks as described below.
19669 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19670 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19671 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19672 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19674 int NumByteElts = VecSize / 8;
19675 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19676 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19677 SmallVector<SDValue, 16> LUTVec;
19678 for (int i = 0; i < NumByteElts; ++i)
19679 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19680 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19681 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19682 DAG.getConstant(0x0F, DL, MVT::i8));
19683 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19686 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19687 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19688 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19691 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19693 // The input vector is used as the shuffle mask that index elements into the
19694 // LUT. After counting low and high nibbles, add the vector to obtain the
19695 // final pop count per i8 element.
19696 SDValue HighPopCnt =
19697 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19698 SDValue LowPopCnt =
19699 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19700 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19702 if (EltVT == MVT::i8)
19705 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19708 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19709 const X86Subtarget *Subtarget,
19710 SelectionDAG &DAG) {
19711 MVT VT = Op.getSimpleValueType();
19712 assert(VT.is128BitVector() &&
19713 "Only 128-bit vector bitmath lowering supported.");
19715 int VecSize = VT.getSizeInBits();
19716 MVT EltVT = VT.getVectorElementType();
19717 int Len = EltVT.getSizeInBits();
19719 // This is the vectorized version of the "best" algorithm from
19720 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19721 // with a minor tweak to use a series of adds + shifts instead of vector
19722 // multiplications. Implemented for all integer vector types. We only use
19723 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19724 // much faster, even faster than using native popcnt instructions.
19726 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19727 MVT VT = V.getSimpleValueType();
19728 SmallVector<SDValue, 32> Shifters(
19729 VT.getVectorNumElements(),
19730 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19731 return DAG.getNode(OpCode, DL, VT, V,
19732 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19734 auto GetMask = [&](SDValue V, APInt Mask) {
19735 MVT VT = V.getSimpleValueType();
19736 SmallVector<SDValue, 32> Masks(
19737 VT.getVectorNumElements(),
19738 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19739 return DAG.getNode(ISD::AND, DL, VT, V,
19740 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19743 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19744 // x86, so set the SRL type to have elements at least i16 wide. This is
19745 // correct because all of our SRLs are followed immediately by a mask anyways
19746 // that handles any bits that sneak into the high bits of the byte elements.
19747 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19751 // v = v - ((v >> 1) & 0x55555555...)
19753 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19754 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19755 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19757 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19758 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19759 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19760 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19761 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19763 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19764 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19765 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19766 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19768 // At this point, V contains the byte-wise population count, and we are
19769 // merely doing a horizontal sum if necessary to get the wider element
19771 if (EltVT == MVT::i8)
19774 return LowerHorizontalByteSum(
19775 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19779 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19780 SelectionDAG &DAG) {
19781 MVT VT = Op.getSimpleValueType();
19782 // FIXME: Need to add AVX-512 support here!
19783 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19784 "Unknown CTPOP type to handle");
19785 SDLoc DL(Op.getNode());
19786 SDValue Op0 = Op.getOperand(0);
19788 if (!Subtarget->hasSSSE3()) {
19789 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19790 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19791 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19794 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19795 unsigned NumElems = VT.getVectorNumElements();
19797 // Extract each 128-bit vector, compute pop count and concat the result.
19798 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19799 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19801 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19802 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19803 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19806 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19809 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19810 SelectionDAG &DAG) {
19811 assert(Op.getSimpleValueType().isVector() &&
19812 "We only do custom lowering for vector population count.");
19813 return LowerVectorCTPOP(Op, Subtarget, DAG);
19816 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19817 SDNode *Node = Op.getNode();
19819 EVT T = Node->getValueType(0);
19820 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19821 DAG.getConstant(0, dl, T), Node->getOperand(2));
19822 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19823 cast<AtomicSDNode>(Node)->getMemoryVT(),
19824 Node->getOperand(0),
19825 Node->getOperand(1), negOp,
19826 cast<AtomicSDNode>(Node)->getMemOperand(),
19827 cast<AtomicSDNode>(Node)->getOrdering(),
19828 cast<AtomicSDNode>(Node)->getSynchScope());
19831 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19832 SDNode *Node = Op.getNode();
19834 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19836 // Convert seq_cst store -> xchg
19837 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19838 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19839 // (The only way to get a 16-byte store is cmpxchg16b)
19840 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19841 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19842 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19843 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19844 cast<AtomicSDNode>(Node)->getMemoryVT(),
19845 Node->getOperand(0),
19846 Node->getOperand(1), Node->getOperand(2),
19847 cast<AtomicSDNode>(Node)->getMemOperand(),
19848 cast<AtomicSDNode>(Node)->getOrdering(),
19849 cast<AtomicSDNode>(Node)->getSynchScope());
19850 return Swap.getValue(1);
19852 // Other atomic stores have a simple pattern.
19856 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19857 MVT VT = Op.getNode()->getSimpleValueType(0);
19859 // Let legalize expand this if it isn't a legal type yet.
19860 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19863 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19866 bool ExtraOp = false;
19867 switch (Op.getOpcode()) {
19868 default: llvm_unreachable("Invalid code");
19869 case ISD::ADDC: Opc = X86ISD::ADD; break;
19870 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19871 case ISD::SUBC: Opc = X86ISD::SUB; break;
19872 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19876 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19878 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19879 Op.getOperand(1), Op.getOperand(2));
19882 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19883 SelectionDAG &DAG) {
19884 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19886 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19887 // which returns the values as { float, float } (in XMM0) or
19888 // { double, double } (which is returned in XMM0, XMM1).
19890 SDValue Arg = Op.getOperand(0);
19891 EVT ArgVT = Arg.getValueType();
19892 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19894 TargetLowering::ArgListTy Args;
19895 TargetLowering::ArgListEntry Entry;
19899 Entry.isSExt = false;
19900 Entry.isZExt = false;
19901 Args.push_back(Entry);
19903 bool isF64 = ArgVT == MVT::f64;
19904 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19905 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19906 // the results are returned via SRet in memory.
19907 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19908 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19910 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19912 Type *RetTy = isF64
19913 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19914 : (Type*)VectorType::get(ArgTy, 4);
19916 TargetLowering::CallLoweringInfo CLI(DAG);
19917 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19918 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19920 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19923 // Returned in xmm0 and xmm1.
19924 return CallResult.first;
19926 // Returned in bits 0:31 and 32:64 xmm0.
19927 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19928 CallResult.first, DAG.getIntPtrConstant(0, dl));
19929 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19930 CallResult.first, DAG.getIntPtrConstant(1, dl));
19931 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19932 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19935 /// Widen a vector input to a vector of NVT. The
19936 /// input vector must have the same element type as NVT.
19937 static SDValue ExtendToType(SDValue InOp, MVT NVT, SelectionDAG &DAG,
19938 bool FillWithZeroes = false) {
19939 // Check if InOp already has the right width.
19940 MVT InVT = InOp.getSimpleValueType();
19944 if (InOp.isUndef())
19945 return DAG.getUNDEF(NVT);
19947 assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
19948 "input and widen element type must match");
19950 unsigned InNumElts = InVT.getVectorNumElements();
19951 unsigned WidenNumElts = NVT.getVectorNumElements();
19952 assert(WidenNumElts > InNumElts && WidenNumElts % InNumElts == 0 &&
19953 "Unexpected request for vector widening");
19955 EVT EltVT = NVT.getVectorElementType();
19958 if (InOp.getOpcode() == ISD::CONCAT_VECTORS &&
19959 InOp.getNumOperands() == 2) {
19960 SDValue N1 = InOp.getOperand(1);
19961 if ((ISD::isBuildVectorAllZeros(N1.getNode()) && FillWithZeroes) ||
19963 InOp = InOp.getOperand(0);
19964 InVT = InOp.getSimpleValueType();
19965 InNumElts = InVT.getVectorNumElements();
19968 if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) ||
19969 ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {
19970 SmallVector<SDValue, 16> Ops;
19971 for (unsigned i = 0; i < InNumElts; ++i)
19972 Ops.push_back(InOp.getOperand(i));
19974 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, EltVT) :
19975 DAG.getUNDEF(EltVT);
19976 for (unsigned i = 0; i < WidenNumElts - InNumElts; ++i)
19977 Ops.push_back(FillVal);
19978 return DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Ops);
19980 SDValue FillVal = FillWithZeroes ? DAG.getConstant(0, dl, NVT) :
19982 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NVT, FillVal,
19983 InOp, DAG.getIntPtrConstant(0, dl));
19986 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19987 SelectionDAG &DAG) {
19988 assert(Subtarget->hasAVX512() &&
19989 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19991 // X86 scatter kills mask register, so its type should be added to
19992 // the list of return values.
19993 // If the "scatter" has 2 return values, it is already handled.
19994 if (Op.getNode()->getNumValues() == 2)
19997 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19998 SDValue Src = N->getValue();
19999 MVT VT = Src.getSimpleValueType();
20000 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
20003 SDValue NewScatter;
20004 SDValue Index = N->getIndex();
20005 SDValue Mask = N->getMask();
20006 SDValue Chain = N->getChain();
20007 SDValue BasePtr = N->getBasePtr();
20008 MVT MemVT = N->getMemoryVT().getSimpleVT();
20009 MVT IndexVT = Index.getSimpleValueType();
20010 MVT MaskVT = Mask.getSimpleValueType();
20012 if (MemVT.getScalarSizeInBits() < VT.getScalarSizeInBits()) {
20013 // The v2i32 value was promoted to v2i64.
20014 // Now we "redo" the type legalizer's work and widen the original
20015 // v2i32 value to v4i32. The original v2i32 is retrieved from v2i64
20017 assert((MemVT == MVT::v2i32 && VT == MVT::v2i64) &&
20018 "Unexpected memory type");
20019 int ShuffleMask[] = {0, 2, -1, -1};
20020 Src = DAG.getVectorShuffle(MVT::v4i32, dl, DAG.getBitcast(MVT::v4i32, Src),
20021 DAG.getUNDEF(MVT::v4i32), ShuffleMask);
20022 // Now we have 4 elements instead of 2.
20023 // Expand the index.
20024 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), 4);
20025 Index = ExtendToType(Index, NewIndexVT, DAG);
20027 // Expand the mask with zeroes
20028 // Mask may be <2 x i64> or <2 x i1> at this moment
20029 assert((MaskVT == MVT::v2i1 || MaskVT == MVT::v2i64) &&
20030 "Unexpected mask type");
20031 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), 4);
20032 Mask = ExtendToType(Mask, ExtMaskVT, DAG, true);
20036 unsigned NumElts = VT.getVectorNumElements();
20037 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
20038 !Index.getSimpleValueType().is512BitVector()) {
20039 // AVX512F supports only 512-bit vectors. Or data or index should
20040 // be 512 bit wide. If now the both index and data are 256-bit, but
20041 // the vector contains 8 elements, we just sign-extend the index
20042 if (IndexVT == MVT::v8i32)
20043 // Just extend index
20044 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20046 // The minimal number of elts in scatter is 8
20049 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), NumElts);
20050 // Use original index here, do not modify the index twice
20051 Index = ExtendToType(N->getIndex(), NewIndexVT, DAG);
20052 if (IndexVT.getScalarType() == MVT::i32)
20053 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20056 // At this point we have promoted mask operand
20057 assert(MaskVT.getScalarSizeInBits() >= 32 && "unexpected mask type");
20058 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), NumElts);
20059 // Use the original mask here, do not modify the mask twice
20060 Mask = ExtendToType(N->getMask(), ExtMaskVT, DAG, true);
20062 // The value that should be stored
20063 MVT NewVT = MVT::getVectorVT(VT.getScalarType(), NumElts);
20064 Src = ExtendToType(Src, NewVT, DAG);
20067 // If the mask is "wide" at this point - truncate it to i1 vector
20068 MVT BitMaskVT = MVT::getVectorVT(MVT::i1, NumElts);
20069 Mask = DAG.getNode(ISD::TRUNCATE, dl, BitMaskVT, Mask);
20071 // The mask is killed by scatter, add it to the values
20072 SDVTList VTs = DAG.getVTList(BitMaskVT, MVT::Other);
20073 SDValue Ops[] = {Chain, Src, Mask, BasePtr, Index};
20074 NewScatter = DAG.getMaskedScatter(VTs, N->getMemoryVT(), dl, Ops,
20075 N->getMemOperand());
20076 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
20077 return SDValue(NewScatter.getNode(), 0);
20080 static SDValue LowerMLOAD(SDValue Op, const X86Subtarget *Subtarget,
20081 SelectionDAG &DAG) {
20083 MaskedLoadSDNode *N = cast<MaskedLoadSDNode>(Op.getNode());
20084 MVT VT = Op.getSimpleValueType();
20085 SDValue Mask = N->getMask();
20088 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
20089 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
20090 // This operation is legal for targets with VLX, but without
20091 // VLX the vector should be widened to 512 bit
20092 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
20093 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
20094 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
20095 SDValue Src0 = N->getSrc0();
20096 Src0 = ExtendToType(Src0, WideDataVT, DAG);
20097 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
20098 SDValue NewLoad = DAG.getMaskedLoad(WideDataVT, dl, N->getChain(),
20099 N->getBasePtr(), Mask, Src0,
20100 N->getMemoryVT(), N->getMemOperand(),
20101 N->getExtensionType());
20103 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
20104 NewLoad.getValue(0),
20105 DAG.getIntPtrConstant(0, dl));
20106 SDValue RetOps[] = {Exract, NewLoad.getValue(1)};
20107 return DAG.getMergeValues(RetOps, dl);
20112 static SDValue LowerMSTORE(SDValue Op, const X86Subtarget *Subtarget,
20113 SelectionDAG &DAG) {
20114 MaskedStoreSDNode *N = cast<MaskedStoreSDNode>(Op.getNode());
20115 SDValue DataToStore = N->getValue();
20116 MVT VT = DataToStore.getSimpleValueType();
20117 SDValue Mask = N->getMask();
20120 if (Subtarget->hasAVX512() && !Subtarget->hasVLX() &&
20121 !VT.is512BitVector() && Mask.getValueType() == MVT::v8i1) {
20122 // This operation is legal for targets with VLX, but without
20123 // VLX the vector should be widened to 512 bit
20124 unsigned NumEltsInWideVec = 512/VT.getScalarSizeInBits();
20125 MVT WideDataVT = MVT::getVectorVT(VT.getScalarType(), NumEltsInWideVec);
20126 MVT WideMaskVT = MVT::getVectorVT(MVT::i1, NumEltsInWideVec);
20127 DataToStore = ExtendToType(DataToStore, WideDataVT, DAG);
20128 Mask = ExtendToType(Mask, WideMaskVT, DAG, true);
20129 return DAG.getMaskedStore(N->getChain(), dl, DataToStore, N->getBasePtr(),
20130 Mask, N->getMemoryVT(), N->getMemOperand(),
20131 N->isTruncatingStore());
20136 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
20137 SelectionDAG &DAG) {
20138 assert(Subtarget->hasAVX512() &&
20139 "MGATHER/MSCATTER are supported on AVX-512 arch only");
20141 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
20143 MVT VT = Op.getSimpleValueType();
20144 SDValue Index = N->getIndex();
20145 SDValue Mask = N->getMask();
20146 SDValue Src0 = N->getValue();
20147 MVT IndexVT = Index.getSimpleValueType();
20148 MVT MaskVT = Mask.getSimpleValueType();
20150 unsigned NumElts = VT.getVectorNumElements();
20151 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
20153 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
20154 !Index.getSimpleValueType().is512BitVector()) {
20155 // AVX512F supports only 512-bit vectors. Or data or index should
20156 // be 512 bit wide. If now the both index and data are 256-bit, but
20157 // the vector contains 8 elements, we just sign-extend the index
20158 if (NumElts == 8) {
20159 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20160 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
20161 N->getOperand(3), Index };
20162 DAG.UpdateNodeOperands(N, Ops);
20166 // Minimal number of elements in Gather
20169 MVT NewIndexVT = MVT::getVectorVT(IndexVT.getScalarType(), NumElts);
20170 Index = ExtendToType(Index, NewIndexVT, DAG);
20171 if (IndexVT.getScalarType() == MVT::i32)
20172 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
20175 MVT MaskBitVT = MVT::getVectorVT(MVT::i1, NumElts);
20176 // At this point we have promoted mask operand
20177 assert(MaskVT.getScalarSizeInBits() >= 32 && "unexpected mask type");
20178 MVT ExtMaskVT = MVT::getVectorVT(MaskVT.getScalarType(), NumElts);
20179 Mask = ExtendToType(Mask, ExtMaskVT, DAG, true);
20180 Mask = DAG.getNode(ISD::TRUNCATE, dl, MaskBitVT, Mask);
20182 // The pass-thru value
20183 MVT NewVT = MVT::getVectorVT(VT.getScalarType(), NumElts);
20184 Src0 = ExtendToType(Src0, NewVT, DAG);
20186 SDValue Ops[] = { N->getChain(), Src0, Mask, N->getBasePtr(), Index };
20187 SDValue NewGather = DAG.getMaskedGather(DAG.getVTList(NewVT, MVT::Other),
20188 N->getMemoryVT(), dl, Ops,
20189 N->getMemOperand());
20190 SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
20191 NewGather.getValue(0),
20192 DAG.getIntPtrConstant(0, dl));
20193 SDValue RetOps[] = {Exract, NewGather.getValue(1)};
20194 return DAG.getMergeValues(RetOps, dl);
20199 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
20200 SelectionDAG &DAG) const {
20201 // TODO: Eventually, the lowering of these nodes should be informed by or
20202 // deferred to the GC strategy for the function in which they appear. For
20203 // now, however, they must be lowered to something. Since they are logically
20204 // no-ops in the case of a null GC strategy (or a GC strategy which does not
20205 // require special handling for these nodes), lower them as literal NOOPs for
20207 SmallVector<SDValue, 2> Ops;
20209 Ops.push_back(Op.getOperand(0));
20210 if (Op->getGluedNode())
20211 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
20214 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
20215 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
20220 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
20221 SelectionDAG &DAG) const {
20222 // TODO: Eventually, the lowering of these nodes should be informed by or
20223 // deferred to the GC strategy for the function in which they appear. For
20224 // now, however, they must be lowered to something. Since they are logically
20225 // no-ops in the case of a null GC strategy (or a GC strategy which does not
20226 // require special handling for these nodes), lower them as literal NOOPs for
20228 SmallVector<SDValue, 2> Ops;
20230 Ops.push_back(Op.getOperand(0));
20231 if (Op->getGluedNode())
20232 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
20235 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
20236 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
20241 /// LowerOperation - Provide custom lowering hooks for some operations.
20243 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
20244 switch (Op.getOpcode()) {
20245 default: llvm_unreachable("Should not custom lower this!");
20246 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
20247 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
20248 return LowerCMP_SWAP(Op, Subtarget, DAG);
20249 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
20250 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
20251 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
20252 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
20253 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
20254 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
20255 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
20256 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
20257 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
20258 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
20259 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
20260 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
20261 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
20262 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
20263 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
20264 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
20265 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
20266 case ISD::SHL_PARTS:
20267 case ISD::SRA_PARTS:
20268 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
20269 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
20270 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
20271 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
20272 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
20273 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
20274 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
20275 case ISD::SIGN_EXTEND_VECTOR_INREG:
20276 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
20277 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
20278 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
20279 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
20280 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
20282 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
20283 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
20284 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
20285 case ISD::SETCC: return LowerSETCC(Op, DAG);
20286 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
20287 case ISD::SELECT: return LowerSELECT(Op, DAG);
20288 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
20289 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
20290 case ISD::VASTART: return LowerVASTART(Op, DAG);
20291 case ISD::VAARG: return LowerVAARG(Op, DAG);
20292 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
20293 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
20294 case ISD::INTRINSIC_VOID:
20295 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
20296 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
20297 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
20298 case ISD::FRAME_TO_ARGS_OFFSET:
20299 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
20300 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
20301 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
20302 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
20303 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
20304 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
20305 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
20306 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
20307 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
20308 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
20310 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
20311 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
20312 case ISD::UMUL_LOHI:
20313 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
20314 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
20317 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
20323 case ISD::UMULO: return LowerXALUO(Op, DAG);
20324 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
20325 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
20329 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
20330 case ISD::ADD: return LowerADD(Op, DAG);
20331 case ISD::SUB: return LowerSUB(Op, DAG);
20335 case ISD::UMIN: return LowerMINMAX(Op, DAG);
20336 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
20337 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG);
20338 case ISD::MSTORE: return LowerMSTORE(Op, Subtarget, DAG);
20339 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
20340 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
20341 case ISD::GC_TRANSITION_START:
20342 return LowerGC_TRANSITION_START(Op, DAG);
20343 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
20347 /// ReplaceNodeResults - Replace a node with an illegal result type
20348 /// with a new node built out of custom code.
20349 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
20350 SmallVectorImpl<SDValue>&Results,
20351 SelectionDAG &DAG) const {
20353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
20354 switch (N->getOpcode()) {
20356 llvm_unreachable("Do not know how to custom type legalize this operation!");
20357 case X86ISD::AVG: {
20358 // Legalize types for X86ISD::AVG by expanding vectors.
20359 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20361 auto InVT = N->getValueType(0);
20362 auto InVTSize = InVT.getSizeInBits();
20363 const unsigned RegSize =
20364 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
20365 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
20366 "512-bit vector requires AVX512");
20367 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
20368 "256-bit vector requires AVX2");
20370 auto ElemVT = InVT.getVectorElementType();
20371 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
20372 RegSize / ElemVT.getSizeInBits());
20373 assert(RegSize % InVT.getSizeInBits() == 0);
20374 unsigned NumConcat = RegSize / InVT.getSizeInBits();
20376 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
20377 Ops[0] = N->getOperand(0);
20378 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20379 Ops[0] = N->getOperand(1);
20380 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
20382 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
20383 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
20384 DAG.getIntPtrConstant(0, dl)));
20387 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
20388 case X86ISD::FMINC:
20390 case X86ISD::FMAXC:
20391 case X86ISD::FMAX: {
20392 EVT VT = N->getValueType(0);
20393 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
20394 SDValue UNDEF = DAG.getUNDEF(VT);
20395 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20396 N->getOperand(0), UNDEF);
20397 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
20398 N->getOperand(1), UNDEF);
20399 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
20402 case ISD::SIGN_EXTEND_INREG:
20407 // We don't want to expand or promote these.
20414 case ISD::UDIVREM: {
20415 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
20416 Results.push_back(V);
20419 case ISD::FP_TO_SINT:
20420 case ISD::FP_TO_UINT: {
20421 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
20423 std::pair<SDValue,SDValue> Vals =
20424 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
20425 SDValue FIST = Vals.first, StackSlot = Vals.second;
20426 if (FIST.getNode()) {
20427 EVT VT = N->getValueType(0);
20428 // Return a load from the stack slot.
20429 if (StackSlot.getNode())
20430 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
20431 MachinePointerInfo(),
20432 false, false, false, 0));
20434 Results.push_back(FIST);
20438 case ISD::UINT_TO_FP: {
20439 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20440 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
20441 N->getValueType(0) != MVT::v2f32)
20443 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
20445 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
20447 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
20448 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
20449 DAG.getBitcast(MVT::v2i64, VBias));
20450 Or = DAG.getBitcast(MVT::v2f64, Or);
20451 // TODO: Are there any fast-math-flags to propagate here?
20452 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
20453 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
20456 case ISD::FP_ROUND: {
20457 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
20459 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
20460 Results.push_back(V);
20463 case ISD::FP_EXTEND: {
20464 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
20465 // No other ValueType for FP_EXTEND should reach this point.
20466 assert(N->getValueType(0) == MVT::v2f32 &&
20467 "Do not know how to legalize this Node");
20470 case ISD::INTRINSIC_W_CHAIN: {
20471 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
20473 default : llvm_unreachable("Do not know how to custom type "
20474 "legalize this intrinsic operation!");
20475 case Intrinsic::x86_rdtsc:
20476 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20478 case Intrinsic::x86_rdtscp:
20479 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
20481 case Intrinsic::x86_rdpmc:
20482 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
20485 case ISD::INTRINSIC_WO_CHAIN: {
20486 if (SDValue V = LowerINTRINSIC_WO_CHAIN(SDValue(N, 0), Subtarget, DAG))
20487 Results.push_back(V);
20490 case ISD::READCYCLECOUNTER: {
20491 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
20494 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
20495 EVT T = N->getValueType(0);
20496 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
20497 bool Regs64bit = T == MVT::i128;
20498 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
20499 SDValue cpInL, cpInH;
20500 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20501 DAG.getConstant(0, dl, HalfT));
20502 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20503 DAG.getConstant(1, dl, HalfT));
20504 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20505 Regs64bit ? X86::RAX : X86::EAX,
20507 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20508 Regs64bit ? X86::RDX : X86::EDX,
20509 cpInH, cpInL.getValue(1));
20510 SDValue swapInL, swapInH;
20511 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20512 DAG.getConstant(0, dl, HalfT));
20513 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20514 DAG.getConstant(1, dl, HalfT));
20515 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20516 Regs64bit ? X86::RBX : X86::EBX,
20517 swapInL, cpInH.getValue(1));
20518 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20519 Regs64bit ? X86::RCX : X86::ECX,
20520 swapInH, swapInL.getValue(1));
20521 SDValue Ops[] = { swapInH.getValue(0),
20523 swapInH.getValue(1) };
20524 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20525 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20526 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20527 X86ISD::LCMPXCHG8_DAG;
20528 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20529 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20530 Regs64bit ? X86::RAX : X86::EAX,
20531 HalfT, Result.getValue(1));
20532 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20533 Regs64bit ? X86::RDX : X86::EDX,
20534 HalfT, cpOutL.getValue(2));
20535 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20537 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20538 MVT::i32, cpOutH.getValue(2));
20540 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20541 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20542 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20544 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20545 Results.push_back(Success);
20546 Results.push_back(EFLAGS.getValue(1));
20549 case ISD::ATOMIC_SWAP:
20550 case ISD::ATOMIC_LOAD_ADD:
20551 case ISD::ATOMIC_LOAD_SUB:
20552 case ISD::ATOMIC_LOAD_AND:
20553 case ISD::ATOMIC_LOAD_OR:
20554 case ISD::ATOMIC_LOAD_XOR:
20555 case ISD::ATOMIC_LOAD_NAND:
20556 case ISD::ATOMIC_LOAD_MIN:
20557 case ISD::ATOMIC_LOAD_MAX:
20558 case ISD::ATOMIC_LOAD_UMIN:
20559 case ISD::ATOMIC_LOAD_UMAX:
20560 case ISD::ATOMIC_LOAD: {
20561 // Delegate to generic TypeLegalization. Situations we can really handle
20562 // should have already been dealt with by AtomicExpandPass.cpp.
20565 case ISD::BITCAST: {
20566 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20567 EVT DstVT = N->getValueType(0);
20568 EVT SrcVT = N->getOperand(0)->getValueType(0);
20570 if (SrcVT != MVT::f64 ||
20571 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20574 unsigned NumElts = DstVT.getVectorNumElements();
20575 EVT SVT = DstVT.getVectorElementType();
20576 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20577 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20578 MVT::v2f64, N->getOperand(0));
20579 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20581 if (ExperimentalVectorWideningLegalization) {
20582 // If we are legalizing vectors by widening, we already have the desired
20583 // legal vector type, just return it.
20584 Results.push_back(ToVecInt);
20588 SmallVector<SDValue, 8> Elts;
20589 for (unsigned i = 0, e = NumElts; i != e; ++i)
20590 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20591 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20593 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20598 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20599 switch ((X86ISD::NodeType)Opcode) {
20600 case X86ISD::FIRST_NUMBER: break;
20601 case X86ISD::BSF: return "X86ISD::BSF";
20602 case X86ISD::BSR: return "X86ISD::BSR";
20603 case X86ISD::SHLD: return "X86ISD::SHLD";
20604 case X86ISD::SHRD: return "X86ISD::SHRD";
20605 case X86ISD::FAND: return "X86ISD::FAND";
20606 case X86ISD::FANDN: return "X86ISD::FANDN";
20607 case X86ISD::FOR: return "X86ISD::FOR";
20608 case X86ISD::FXOR: return "X86ISD::FXOR";
20609 case X86ISD::FILD: return "X86ISD::FILD";
20610 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20611 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20612 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20613 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20614 case X86ISD::FLD: return "X86ISD::FLD";
20615 case X86ISD::FST: return "X86ISD::FST";
20616 case X86ISD::CALL: return "X86ISD::CALL";
20617 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20618 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20619 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20620 case X86ISD::BT: return "X86ISD::BT";
20621 case X86ISD::CMP: return "X86ISD::CMP";
20622 case X86ISD::COMI: return "X86ISD::COMI";
20623 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20624 case X86ISD::CMPM: return "X86ISD::CMPM";
20625 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20626 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20627 case X86ISD::SETCC: return "X86ISD::SETCC";
20628 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20629 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20630 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20631 case X86ISD::CMOV: return "X86ISD::CMOV";
20632 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20633 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20634 case X86ISD::IRET: return "X86ISD::IRET";
20635 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20636 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20637 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20638 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20639 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20640 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20641 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20642 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20643 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20644 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20645 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20646 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20647 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20648 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20649 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20650 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20651 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20652 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20653 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20654 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20655 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20656 case X86ISD::HADD: return "X86ISD::HADD";
20657 case X86ISD::HSUB: return "X86ISD::HSUB";
20658 case X86ISD::FHADD: return "X86ISD::FHADD";
20659 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20660 case X86ISD::ABS: return "X86ISD::ABS";
20661 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20662 case X86ISD::FMAX: return "X86ISD::FMAX";
20663 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20664 case X86ISD::FMIN: return "X86ISD::FMIN";
20665 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20666 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20667 case X86ISD::FMINC: return "X86ISD::FMINC";
20668 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20669 case X86ISD::FRCP: return "X86ISD::FRCP";
20670 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20671 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20672 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20673 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20674 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20675 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20676 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20677 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20678 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20679 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20680 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20681 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20682 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20683 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20684 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20685 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20686 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20687 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20688 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20689 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20690 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20691 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20692 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20693 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20694 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20695 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20696 case X86ISD::CVT2MASK: return "X86ISD::CVT2MASK";
20697 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20698 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20699 case X86ISD::VSHL: return "X86ISD::VSHL";
20700 case X86ISD::VSRL: return "X86ISD::VSRL";
20701 case X86ISD::VSRA: return "X86ISD::VSRA";
20702 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20703 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20704 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20705 case X86ISD::CMPP: return "X86ISD::CMPP";
20706 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20707 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20708 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20709 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20710 case X86ISD::ADD: return "X86ISD::ADD";
20711 case X86ISD::SUB: return "X86ISD::SUB";
20712 case X86ISD::ADC: return "X86ISD::ADC";
20713 case X86ISD::SBB: return "X86ISD::SBB";
20714 case X86ISD::SMUL: return "X86ISD::SMUL";
20715 case X86ISD::UMUL: return "X86ISD::UMUL";
20716 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20717 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20718 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20719 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20720 case X86ISD::INC: return "X86ISD::INC";
20721 case X86ISD::DEC: return "X86ISD::DEC";
20722 case X86ISD::OR: return "X86ISD::OR";
20723 case X86ISD::XOR: return "X86ISD::XOR";
20724 case X86ISD::AND: return "X86ISD::AND";
20725 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20726 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20727 case X86ISD::PTEST: return "X86ISD::PTEST";
20728 case X86ISD::TESTP: return "X86ISD::TESTP";
20729 case X86ISD::TESTM: return "X86ISD::TESTM";
20730 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20731 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20732 case X86ISD::KTEST: return "X86ISD::KTEST";
20733 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20734 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20735 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20736 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20737 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20738 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20739 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20740 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20741 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20742 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20743 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20744 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20745 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20746 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20747 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20748 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20749 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20750 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20751 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20752 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20753 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20754 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20755 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20756 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20757 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20758 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20759 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20760 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20761 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20762 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20763 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20764 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20765 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20766 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20767 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20768 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20769 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20770 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20771 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20772 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20773 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20774 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20775 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20776 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20777 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20778 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20779 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20780 case X86ISD::SAHF: return "X86ISD::SAHF";
20781 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20782 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20783 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20784 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20785 case X86ISD::VPROT: return "X86ISD::VPROT";
20786 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20787 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20788 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20789 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20790 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20791 case X86ISD::FMADD: return "X86ISD::FMADD";
20792 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20793 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20794 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20795 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20796 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20797 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20798 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20799 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20800 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20801 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20802 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20803 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20804 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20805 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20806 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20807 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20808 case X86ISD::XTEST: return "X86ISD::XTEST";
20809 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20810 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20811 case X86ISD::SELECT: return "X86ISD::SELECT";
20812 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20813 case X86ISD::RCP28: return "X86ISD::RCP28";
20814 case X86ISD::EXP2: return "X86ISD::EXP2";
20815 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20816 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20817 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20818 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20819 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20820 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20821 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20822 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20823 case X86ISD::ADDS: return "X86ISD::ADDS";
20824 case X86ISD::SUBS: return "X86ISD::SUBS";
20825 case X86ISD::AVG: return "X86ISD::AVG";
20826 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20827 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20828 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20829 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20830 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20831 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20832 case X86ISD::VFPCLASSS: return "X86ISD::VFPCLASSS";
20837 // isLegalAddressingMode - Return true if the addressing mode represented
20838 // by AM is legal for this target, for a load/store of the specified type.
20839 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20840 const AddrMode &AM, Type *Ty,
20841 unsigned AS) const {
20842 // X86 supports extremely general addressing modes.
20843 CodeModel::Model M = getTargetMachine().getCodeModel();
20844 Reloc::Model R = getTargetMachine().getRelocationModel();
20846 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20847 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20852 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20854 // If a reference to this global requires an extra load, we can't fold it.
20855 if (isGlobalStubReference(GVFlags))
20858 // If BaseGV requires a register for the PIC base, we cannot also have a
20859 // BaseReg specified.
20860 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20863 // If lower 4G is not available, then we must use rip-relative addressing.
20864 if ((M != CodeModel::Small || R != Reloc::Static) &&
20865 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20869 switch (AM.Scale) {
20875 // These scales always work.
20880 // These scales are formed with basereg+scalereg. Only accept if there is
20885 default: // Other stuff never works.
20892 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20893 unsigned Bits = Ty->getScalarSizeInBits();
20895 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20896 // particularly cheaper than those without.
20900 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20901 // variable shifts just as cheap as scalar ones.
20902 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20905 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20906 // fully general vector.
20910 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20911 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20913 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20914 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20915 return NumBits1 > NumBits2;
20918 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20919 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20922 if (!isTypeLegal(EVT::getEVT(Ty1)))
20925 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20927 // Assuming the caller doesn't have a zeroext or signext return parameter,
20928 // truncation all the way down to i1 is valid.
20932 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20933 return isInt<32>(Imm);
20936 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20937 // Can also use sub to handle negated immediates.
20938 return isInt<32>(Imm);
20941 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20942 if (!VT1.isInteger() || !VT2.isInteger())
20944 unsigned NumBits1 = VT1.getSizeInBits();
20945 unsigned NumBits2 = VT2.getSizeInBits();
20946 return NumBits1 > NumBits2;
20949 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20950 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20951 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20954 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20955 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20956 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20959 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20960 EVT VT1 = Val.getValueType();
20961 if (isZExtFree(VT1, VT2))
20964 if (Val.getOpcode() != ISD::LOAD)
20967 if (!VT1.isSimple() || !VT1.isInteger() ||
20968 !VT2.isSimple() || !VT2.isInteger())
20971 switch (VT1.getSimpleVT().SimpleTy) {
20976 // X86 has 8, 16, and 32-bit zero-extending loads.
20983 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20986 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20987 if (!Subtarget->hasAnyFMA())
20990 VT = VT.getScalarType();
20992 if (!VT.isSimple())
20995 switch (VT.getSimpleVT().SimpleTy) {
21006 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
21007 // i16 instructions are longer (0x66 prefix) and potentially slower.
21008 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
21011 /// isShuffleMaskLegal - Targets can use this to indicate that they only
21012 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
21013 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
21014 /// are assumed to be legal.
21016 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
21018 if (!VT.isSimple())
21021 // Not for i1 vectors
21022 if (VT.getSimpleVT().getScalarType() == MVT::i1)
21025 // Very little shuffling can be done for 64-bit vectors right now.
21026 if (VT.getSimpleVT().getSizeInBits() == 64)
21029 // We only care that the types being shuffled are legal. The lowering can
21030 // handle any possible shuffle mask that results.
21031 return isTypeLegal(VT.getSimpleVT());
21035 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
21037 // Just delegate to the generic legality, clear masks aren't special.
21038 return isShuffleMaskLegal(Mask, VT);
21041 //===----------------------------------------------------------------------===//
21042 // X86 Scheduler Hooks
21043 //===----------------------------------------------------------------------===//
21045 /// Utility function to emit xbegin specifying the start of an RTM region.
21046 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
21047 const TargetInstrInfo *TII) {
21048 DebugLoc DL = MI->getDebugLoc();
21050 const BasicBlock *BB = MBB->getBasicBlock();
21051 MachineFunction::iterator I = ++MBB->getIterator();
21053 // For the v = xbegin(), we generate
21064 MachineBasicBlock *thisMBB = MBB;
21065 MachineFunction *MF = MBB->getParent();
21066 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21067 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21068 MF->insert(I, mainMBB);
21069 MF->insert(I, sinkMBB);
21071 // Transfer the remainder of BB and its successor edges to sinkMBB.
21072 sinkMBB->splice(sinkMBB->begin(), MBB,
21073 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21074 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21078 // # fallthrough to mainMBB
21079 // # abortion to sinkMBB
21080 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
21081 thisMBB->addSuccessor(mainMBB);
21082 thisMBB->addSuccessor(sinkMBB);
21086 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
21087 mainMBB->addSuccessor(sinkMBB);
21090 // EAX is live into the sinkMBB
21091 sinkMBB->addLiveIn(X86::EAX);
21092 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21093 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21096 MI->eraseFromParent();
21100 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
21101 // or XMM0_V32I8 in AVX all of this code can be replaced with that
21102 // in the .td file.
21103 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
21104 const TargetInstrInfo *TII) {
21106 switch (MI->getOpcode()) {
21107 default: llvm_unreachable("illegal opcode!");
21108 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
21109 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
21110 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
21111 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
21112 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
21113 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
21114 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
21115 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
21118 DebugLoc dl = MI->getDebugLoc();
21119 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
21121 unsigned NumArgs = MI->getNumOperands();
21122 for (unsigned i = 1; i < NumArgs; ++i) {
21123 MachineOperand &Op = MI->getOperand(i);
21124 if (!(Op.isReg() && Op.isImplicit()))
21125 MIB.addOperand(Op);
21127 if (MI->hasOneMemOperand())
21128 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
21130 BuildMI(*BB, MI, dl,
21131 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21132 .addReg(X86::XMM0);
21134 MI->eraseFromParent();
21138 // FIXME: Custom handling because TableGen doesn't support multiple implicit
21139 // defs in an instruction pattern
21140 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
21141 const TargetInstrInfo *TII) {
21143 switch (MI->getOpcode()) {
21144 default: llvm_unreachable("illegal opcode!");
21145 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
21146 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
21147 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
21148 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
21149 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
21150 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
21151 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
21152 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
21155 DebugLoc dl = MI->getDebugLoc();
21156 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
21158 unsigned NumArgs = MI->getNumOperands(); // remove the results
21159 for (unsigned i = 1; i < NumArgs; ++i) {
21160 MachineOperand &Op = MI->getOperand(i);
21161 if (!(Op.isReg() && Op.isImplicit()))
21162 MIB.addOperand(Op);
21164 if (MI->hasOneMemOperand())
21165 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
21167 BuildMI(*BB, MI, dl,
21168 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21171 MI->eraseFromParent();
21175 static MachineBasicBlock *EmitWRPKRU(MachineInstr *MI, MachineBasicBlock *BB,
21176 const X86Subtarget *Subtarget) {
21177 DebugLoc dl = MI->getDebugLoc();
21178 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21180 // insert input VAL into EAX
21181 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
21182 .addReg(MI->getOperand(0).getReg());
21183 // insert zero to ECX
21184 BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::ECX)
21187 // insert zero to EDX
21188 BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::EDX)
21191 // insert WRPKRU instruction
21192 BuildMI(*BB, MI, dl, TII->get(X86::WRPKRUr));
21194 MI->eraseFromParent(); // The pseudo is gone now.
21198 static MachineBasicBlock *EmitRDPKRU(MachineInstr *MI, MachineBasicBlock *BB,
21199 const X86Subtarget *Subtarget) {
21200 DebugLoc dl = MI->getDebugLoc();
21201 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21203 // insert zero to ECX
21204 BuildMI(*BB, MI, dl, TII->get(X86::XOR32rr), X86::ECX)
21207 // insert RDPKRU instruction
21208 BuildMI(*BB, MI, dl, TII->get(X86::RDPKRUr));
21209 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
21212 MI->eraseFromParent(); // The pseudo is gone now.
21216 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
21217 const X86Subtarget *Subtarget) {
21218 DebugLoc dl = MI->getDebugLoc();
21219 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21220 // Address into RAX/EAX, other two args into ECX, EDX.
21221 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
21222 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
21223 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
21224 for (int i = 0; i < X86::AddrNumOperands; ++i)
21225 MIB.addOperand(MI->getOperand(i));
21227 unsigned ValOps = X86::AddrNumOperands;
21228 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
21229 .addReg(MI->getOperand(ValOps).getReg());
21230 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
21231 .addReg(MI->getOperand(ValOps+1).getReg());
21233 // The instruction doesn't actually take any operands though.
21234 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
21236 MI->eraseFromParent(); // The pseudo is gone now.
21240 MachineBasicBlock *
21241 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
21242 MachineBasicBlock *MBB) const {
21243 // Emit va_arg instruction on X86-64.
21245 // Operands to this pseudo-instruction:
21246 // 0 ) Output : destination address (reg)
21247 // 1-5) Input : va_list address (addr, i64mem)
21248 // 6 ) ArgSize : Size (in bytes) of vararg type
21249 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
21250 // 8 ) Align : Alignment of type
21251 // 9 ) EFLAGS (implicit-def)
21253 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
21254 static_assert(X86::AddrNumOperands == 5,
21255 "VAARG_64 assumes 5 address operands");
21257 unsigned DestReg = MI->getOperand(0).getReg();
21258 MachineOperand &Base = MI->getOperand(1);
21259 MachineOperand &Scale = MI->getOperand(2);
21260 MachineOperand &Index = MI->getOperand(3);
21261 MachineOperand &Disp = MI->getOperand(4);
21262 MachineOperand &Segment = MI->getOperand(5);
21263 unsigned ArgSize = MI->getOperand(6).getImm();
21264 unsigned ArgMode = MI->getOperand(7).getImm();
21265 unsigned Align = MI->getOperand(8).getImm();
21267 // Memory Reference
21268 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
21269 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21270 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21272 // Machine Information
21273 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21274 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
21275 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
21276 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
21277 DebugLoc DL = MI->getDebugLoc();
21279 // struct va_list {
21282 // i64 overflow_area (address)
21283 // i64 reg_save_area (address)
21285 // sizeof(va_list) = 24
21286 // alignment(va_list) = 8
21288 unsigned TotalNumIntRegs = 6;
21289 unsigned TotalNumXMMRegs = 8;
21290 bool UseGPOffset = (ArgMode == 1);
21291 bool UseFPOffset = (ArgMode == 2);
21292 unsigned MaxOffset = TotalNumIntRegs * 8 +
21293 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
21295 /* Align ArgSize to a multiple of 8 */
21296 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
21297 bool NeedsAlign = (Align > 8);
21299 MachineBasicBlock *thisMBB = MBB;
21300 MachineBasicBlock *overflowMBB;
21301 MachineBasicBlock *offsetMBB;
21302 MachineBasicBlock *endMBB;
21304 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
21305 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
21306 unsigned OffsetReg = 0;
21308 if (!UseGPOffset && !UseFPOffset) {
21309 // If we only pull from the overflow region, we don't create a branch.
21310 // We don't need to alter control flow.
21311 OffsetDestReg = 0; // unused
21312 OverflowDestReg = DestReg;
21314 offsetMBB = nullptr;
21315 overflowMBB = thisMBB;
21318 // First emit code to check if gp_offset (or fp_offset) is below the bound.
21319 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
21320 // If not, pull from overflow_area. (branch to overflowMBB)
21325 // offsetMBB overflowMBB
21330 // Registers for the PHI in endMBB
21331 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
21332 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
21334 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21335 MachineFunction *MF = MBB->getParent();
21336 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21337 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21338 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21340 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21342 // Insert the new basic blocks
21343 MF->insert(MBBIter, offsetMBB);
21344 MF->insert(MBBIter, overflowMBB);
21345 MF->insert(MBBIter, endMBB);
21347 // Transfer the remainder of MBB and its successor edges to endMBB.
21348 endMBB->splice(endMBB->begin(), thisMBB,
21349 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
21350 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
21352 // Make offsetMBB and overflowMBB successors of thisMBB
21353 thisMBB->addSuccessor(offsetMBB);
21354 thisMBB->addSuccessor(overflowMBB);
21356 // endMBB is a successor of both offsetMBB and overflowMBB
21357 offsetMBB->addSuccessor(endMBB);
21358 overflowMBB->addSuccessor(endMBB);
21360 // Load the offset value into a register
21361 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21362 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
21366 .addDisp(Disp, UseFPOffset ? 4 : 0)
21367 .addOperand(Segment)
21368 .setMemRefs(MMOBegin, MMOEnd);
21370 // Check if there is enough room left to pull this argument.
21371 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
21373 .addImm(MaxOffset + 8 - ArgSizeA8);
21375 // Branch to "overflowMBB" if offset >= max
21376 // Fall through to "offsetMBB" otherwise
21377 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
21378 .addMBB(overflowMBB);
21381 // In offsetMBB, emit code to use the reg_save_area.
21383 assert(OffsetReg != 0);
21385 // Read the reg_save_area address.
21386 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
21387 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
21392 .addOperand(Segment)
21393 .setMemRefs(MMOBegin, MMOEnd);
21395 // Zero-extend the offset
21396 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
21397 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
21400 .addImm(X86::sub_32bit);
21402 // Add the offset to the reg_save_area to get the final address.
21403 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
21404 .addReg(OffsetReg64)
21405 .addReg(RegSaveReg);
21407 // Compute the offset for the next argument
21408 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
21409 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
21411 .addImm(UseFPOffset ? 16 : 8);
21413 // Store it back into the va_list.
21414 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
21418 .addDisp(Disp, UseFPOffset ? 4 : 0)
21419 .addOperand(Segment)
21420 .addReg(NextOffsetReg)
21421 .setMemRefs(MMOBegin, MMOEnd);
21424 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
21429 // Emit code to use overflow area
21432 // Load the overflow_area address into a register.
21433 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
21434 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
21439 .addOperand(Segment)
21440 .setMemRefs(MMOBegin, MMOEnd);
21442 // If we need to align it, do so. Otherwise, just copy the address
21443 // to OverflowDestReg.
21445 // Align the overflow address
21446 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
21447 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
21449 // aligned_addr = (addr + (align-1)) & ~(align-1)
21450 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
21451 .addReg(OverflowAddrReg)
21454 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
21456 .addImm(~(uint64_t)(Align-1));
21458 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
21459 .addReg(OverflowAddrReg);
21462 // Compute the next overflow address after this argument.
21463 // (the overflow address should be kept 8-byte aligned)
21464 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
21465 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
21466 .addReg(OverflowDestReg)
21467 .addImm(ArgSizeA8);
21469 // Store the new overflow address.
21470 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
21475 .addOperand(Segment)
21476 .addReg(NextAddrReg)
21477 .setMemRefs(MMOBegin, MMOEnd);
21479 // If we branched, emit the PHI to the front of endMBB.
21481 BuildMI(*endMBB, endMBB->begin(), DL,
21482 TII->get(X86::PHI), DestReg)
21483 .addReg(OffsetDestReg).addMBB(offsetMBB)
21484 .addReg(OverflowDestReg).addMBB(overflowMBB);
21487 // Erase the pseudo instruction
21488 MI->eraseFromParent();
21493 MachineBasicBlock *
21494 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
21496 MachineBasicBlock *MBB) const {
21497 // Emit code to save XMM registers to the stack. The ABI says that the
21498 // number of registers to save is given in %al, so it's theoretically
21499 // possible to do an indirect jump trick to avoid saving all of them,
21500 // however this code takes a simpler approach and just executes all
21501 // of the stores if %al is non-zero. It's less code, and it's probably
21502 // easier on the hardware branch predictor, and stores aren't all that
21503 // expensive anyway.
21505 // Create the new basic blocks. One block contains all the XMM stores,
21506 // and one block is the final destination regardless of whether any
21507 // stores were performed.
21508 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
21509 MachineFunction *F = MBB->getParent();
21510 MachineFunction::iterator MBBIter = ++MBB->getIterator();
21511 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
21512 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
21513 F->insert(MBBIter, XMMSaveMBB);
21514 F->insert(MBBIter, EndMBB);
21516 // Transfer the remainder of MBB and its successor edges to EndMBB.
21517 EndMBB->splice(EndMBB->begin(), MBB,
21518 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21519 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
21521 // The original block will now fall through to the XMM save block.
21522 MBB->addSuccessor(XMMSaveMBB);
21523 // The XMMSaveMBB will fall through to the end block.
21524 XMMSaveMBB->addSuccessor(EndMBB);
21526 // Now add the instructions.
21527 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21528 DebugLoc DL = MI->getDebugLoc();
21530 unsigned CountReg = MI->getOperand(0).getReg();
21531 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
21532 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
21534 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
21535 // If %al is 0, branch around the XMM save block.
21536 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
21537 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
21538 MBB->addSuccessor(EndMBB);
21541 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
21542 // that was just emitted, but clearly shouldn't be "saved".
21543 assert((MI->getNumOperands() <= 3 ||
21544 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
21545 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
21546 && "Expected last argument to be EFLAGS");
21547 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21548 // In the XMM save block, save all the XMM argument registers.
21549 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21550 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21551 MachineMemOperand *MMO = F->getMachineMemOperand(
21552 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21553 MachineMemOperand::MOStore,
21554 /*Size=*/16, /*Align=*/16);
21555 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21556 .addFrameIndex(RegSaveFrameIndex)
21557 .addImm(/*Scale=*/1)
21558 .addReg(/*IndexReg=*/0)
21559 .addImm(/*Disp=*/Offset)
21560 .addReg(/*Segment=*/0)
21561 .addReg(MI->getOperand(i).getReg())
21562 .addMemOperand(MMO);
21565 MI->eraseFromParent(); // The pseudo instruction is gone now.
21570 // The EFLAGS operand of SelectItr might be missing a kill marker
21571 // because there were multiple uses of EFLAGS, and ISel didn't know
21572 // which to mark. Figure out whether SelectItr should have had a
21573 // kill marker, and set it if it should. Returns the correct kill
21575 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21576 MachineBasicBlock* BB,
21577 const TargetRegisterInfo* TRI) {
21578 // Scan forward through BB for a use/def of EFLAGS.
21579 MachineBasicBlock::iterator miI(std::next(SelectItr));
21580 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21581 const MachineInstr& mi = *miI;
21582 if (mi.readsRegister(X86::EFLAGS))
21584 if (mi.definesRegister(X86::EFLAGS))
21585 break; // Should have kill-flag - update below.
21588 // If we hit the end of the block, check whether EFLAGS is live into a
21590 if (miI == BB->end()) {
21591 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21592 sEnd = BB->succ_end();
21593 sItr != sEnd; ++sItr) {
21594 MachineBasicBlock* succ = *sItr;
21595 if (succ->isLiveIn(X86::EFLAGS))
21600 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21601 // out. SelectMI should have a kill flag on EFLAGS.
21602 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21606 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21607 // together with other CMOV pseudo-opcodes into a single basic-block with
21608 // conditional jump around it.
21609 static bool isCMOVPseudo(MachineInstr *MI) {
21610 switch (MI->getOpcode()) {
21611 case X86::CMOV_FR32:
21612 case X86::CMOV_FR64:
21613 case X86::CMOV_GR8:
21614 case X86::CMOV_GR16:
21615 case X86::CMOV_GR32:
21616 case X86::CMOV_RFP32:
21617 case X86::CMOV_RFP64:
21618 case X86::CMOV_RFP80:
21619 case X86::CMOV_V2F64:
21620 case X86::CMOV_V2I64:
21621 case X86::CMOV_V4F32:
21622 case X86::CMOV_V4F64:
21623 case X86::CMOV_V4I64:
21624 case X86::CMOV_V16F32:
21625 case X86::CMOV_V8F32:
21626 case X86::CMOV_V8F64:
21627 case X86::CMOV_V8I64:
21628 case X86::CMOV_V8I1:
21629 case X86::CMOV_V16I1:
21630 case X86::CMOV_V32I1:
21631 case X86::CMOV_V64I1:
21639 MachineBasicBlock *
21640 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21641 MachineBasicBlock *BB) const {
21642 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21643 DebugLoc DL = MI->getDebugLoc();
21645 // To "insert" a SELECT_CC instruction, we actually have to insert the
21646 // diamond control-flow pattern. The incoming instruction knows the
21647 // destination vreg to set, the condition code register to branch on, the
21648 // true/false values to select between, and a branch opcode to use.
21649 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21650 MachineFunction::iterator It = ++BB->getIterator();
21655 // cmpTY ccX, r1, r2
21657 // fallthrough --> copy0MBB
21658 MachineBasicBlock *thisMBB = BB;
21659 MachineFunction *F = BB->getParent();
21661 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21662 // as described above, by inserting a BB, and then making a PHI at the join
21663 // point to select the true and false operands of the CMOV in the PHI.
21665 // The code also handles two different cases of multiple CMOV opcodes
21669 // In this case, there are multiple CMOVs in a row, all which are based on
21670 // the same condition setting (or the exact opposite condition setting).
21671 // In this case we can lower all the CMOVs using a single inserted BB, and
21672 // then make a number of PHIs at the join point to model the CMOVs. The only
21673 // trickiness here, is that in a case like:
21675 // t2 = CMOV cond1 t1, f1
21676 // t3 = CMOV cond1 t2, f2
21678 // when rewriting this into PHIs, we have to perform some renaming on the
21679 // temps since you cannot have a PHI operand refer to a PHI result earlier
21680 // in the same block. The "simple" but wrong lowering would be:
21682 // t2 = PHI t1(BB1), f1(BB2)
21683 // t3 = PHI t2(BB1), f2(BB2)
21685 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21686 // renaming is to note that on the path through BB1, t2 is really just a
21687 // copy of t1, and do that renaming, properly generating:
21689 // t2 = PHI t1(BB1), f1(BB2)
21690 // t3 = PHI t1(BB1), f2(BB2)
21692 // Case 2, we lower cascaded CMOVs such as
21694 // (CMOV (CMOV F, T, cc1), T, cc2)
21696 // to two successives branches. For that, we look for another CMOV as the
21697 // following instruction.
21699 // Without this, we would add a PHI between the two jumps, which ends up
21700 // creating a few copies all around. For instance, for
21702 // (sitofp (zext (fcmp une)))
21704 // we would generate:
21706 // ucomiss %xmm1, %xmm0
21707 // movss <1.0f>, %xmm0
21708 // movaps %xmm0, %xmm1
21710 // xorps %xmm1, %xmm1
21713 // movaps %xmm1, %xmm0
21717 // because this custom-inserter would have generated:
21729 // A: X = ...; Y = ...
21731 // C: Z = PHI [X, A], [Y, B]
21733 // E: PHI [X, C], [Z, D]
21735 // If we lower both CMOVs in a single step, we can instead generate:
21747 // A: X = ...; Y = ...
21749 // E: PHI [X, A], [X, C], [Y, D]
21751 // Which, in our sitofp/fcmp example, gives us something like:
21753 // ucomiss %xmm1, %xmm0
21754 // movss <1.0f>, %xmm0
21757 // xorps %xmm0, %xmm0
21761 MachineInstr *CascadedCMOV = nullptr;
21762 MachineInstr *LastCMOV = MI;
21763 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21764 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21765 MachineBasicBlock::iterator NextMIIt =
21766 std::next(MachineBasicBlock::iterator(MI));
21768 // Check for case 1, where there are multiple CMOVs with the same condition
21769 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21770 // number of jumps the most.
21772 if (isCMOVPseudo(MI)) {
21773 // See if we have a string of CMOVS with the same condition.
21774 while (NextMIIt != BB->end() &&
21775 isCMOVPseudo(NextMIIt) &&
21776 (NextMIIt->getOperand(3).getImm() == CC ||
21777 NextMIIt->getOperand(3).getImm() == OppCC)) {
21778 LastCMOV = &*NextMIIt;
21783 // This checks for case 2, but only do this if we didn't already find
21784 // case 1, as indicated by LastCMOV == MI.
21785 if (LastCMOV == MI &&
21786 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21787 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21788 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21789 CascadedCMOV = &*NextMIIt;
21792 MachineBasicBlock *jcc1MBB = nullptr;
21794 // If we have a cascaded CMOV, we lower it to two successive branches to
21795 // the same block. EFLAGS is used by both, so mark it as live in the second.
21796 if (CascadedCMOV) {
21797 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21798 F->insert(It, jcc1MBB);
21799 jcc1MBB->addLiveIn(X86::EFLAGS);
21802 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21803 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21804 F->insert(It, copy0MBB);
21805 F->insert(It, sinkMBB);
21807 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21808 // live into the sink and copy blocks.
21809 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21811 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21812 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21813 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21814 copy0MBB->addLiveIn(X86::EFLAGS);
21815 sinkMBB->addLiveIn(X86::EFLAGS);
21818 // Transfer the remainder of BB and its successor edges to sinkMBB.
21819 sinkMBB->splice(sinkMBB->begin(), BB,
21820 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21821 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21823 // Add the true and fallthrough blocks as its successors.
21824 if (CascadedCMOV) {
21825 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21826 BB->addSuccessor(jcc1MBB);
21828 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21829 // jump to the sinkMBB.
21830 jcc1MBB->addSuccessor(copy0MBB);
21831 jcc1MBB->addSuccessor(sinkMBB);
21833 BB->addSuccessor(copy0MBB);
21836 // The true block target of the first (or only) branch is always sinkMBB.
21837 BB->addSuccessor(sinkMBB);
21839 // Create the conditional branch instruction.
21840 unsigned Opc = X86::GetCondBranchFromCond(CC);
21841 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21843 if (CascadedCMOV) {
21844 unsigned Opc2 = X86::GetCondBranchFromCond(
21845 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21846 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21850 // %FalseValue = ...
21851 // # fallthrough to sinkMBB
21852 copy0MBB->addSuccessor(sinkMBB);
21855 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21857 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21858 MachineBasicBlock::iterator MIItEnd =
21859 std::next(MachineBasicBlock::iterator(LastCMOV));
21860 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21861 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21862 MachineInstrBuilder MIB;
21864 // As we are creating the PHIs, we have to be careful if there is more than
21865 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21866 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21867 // That also means that PHI construction must work forward from earlier to
21868 // later, and that the code must maintain a mapping from earlier PHI's
21869 // destination registers, and the registers that went into the PHI.
21871 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21872 unsigned DestReg = MIIt->getOperand(0).getReg();
21873 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21874 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21876 // If this CMOV we are generating is the opposite condition from
21877 // the jump we generated, then we have to swap the operands for the
21878 // PHI that is going to be generated.
21879 if (MIIt->getOperand(3).getImm() == OppCC)
21880 std::swap(Op1Reg, Op2Reg);
21882 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21883 Op1Reg = RegRewriteTable[Op1Reg].first;
21885 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21886 Op2Reg = RegRewriteTable[Op2Reg].second;
21888 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21889 TII->get(X86::PHI), DestReg)
21890 .addReg(Op1Reg).addMBB(copy0MBB)
21891 .addReg(Op2Reg).addMBB(thisMBB);
21893 // Add this PHI to the rewrite table.
21894 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21897 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21898 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21899 if (CascadedCMOV) {
21900 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21901 // Copy the PHI result to the register defined by the second CMOV.
21902 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21903 DL, TII->get(TargetOpcode::COPY),
21904 CascadedCMOV->getOperand(0).getReg())
21905 .addReg(MI->getOperand(0).getReg());
21906 CascadedCMOV->eraseFromParent();
21909 // Now remove the CMOV(s).
21910 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21911 (MIIt++)->eraseFromParent();
21916 MachineBasicBlock *
21917 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21918 MachineBasicBlock *BB) const {
21919 // Combine the following atomic floating-point modification pattern:
21920 // a.store(reg OP a.load(acquire), release)
21921 // Transform them into:
21922 // OPss (%gpr), %xmm
21923 // movss %xmm, (%gpr)
21924 // Or sd equivalent for 64-bit operations.
21926 switch (MI->getOpcode()) {
21927 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21928 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21929 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21931 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21932 DebugLoc DL = MI->getDebugLoc();
21933 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21934 MachineOperand MSrc = MI->getOperand(0);
21935 unsigned VSrc = MI->getOperand(5).getReg();
21936 const MachineOperand &Disp = MI->getOperand(3);
21937 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21938 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21939 if (hasDisp && MSrc.isReg())
21940 MSrc.setIsKill(false);
21941 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21942 .addOperand(/*Base=*/MSrc)
21943 .addImm(/*Scale=*/1)
21944 .addReg(/*Index=*/0)
21945 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21947 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21948 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21950 .addOperand(/*Base=*/MSrc)
21951 .addImm(/*Scale=*/1)
21952 .addReg(/*Index=*/0)
21953 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21954 .addReg(/*Segment=*/0);
21955 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21956 MI->eraseFromParent(); // The pseudo instruction is gone now.
21960 MachineBasicBlock *
21961 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21962 MachineBasicBlock *BB) const {
21963 MachineFunction *MF = BB->getParent();
21964 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21965 DebugLoc DL = MI->getDebugLoc();
21966 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21968 assert(MF->shouldSplitStack());
21970 const bool Is64Bit = Subtarget->is64Bit();
21971 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21973 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21974 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21977 // ... [Till the alloca]
21978 // If stacklet is not large enough, jump to mallocMBB
21981 // Allocate by subtracting from RSP
21982 // Jump to continueMBB
21985 // Allocate by call to runtime
21989 // [rest of original BB]
21992 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21993 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21994 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21996 MachineRegisterInfo &MRI = MF->getRegInfo();
21997 const TargetRegisterClass *AddrRegClass =
21998 getRegClassFor(getPointerTy(MF->getDataLayout()));
22000 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
22001 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
22002 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
22003 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
22004 sizeVReg = MI->getOperand(1).getReg(),
22005 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
22007 MachineFunction::iterator MBBIter = ++BB->getIterator();
22009 MF->insert(MBBIter, bumpMBB);
22010 MF->insert(MBBIter, mallocMBB);
22011 MF->insert(MBBIter, continueMBB);
22013 continueMBB->splice(continueMBB->begin(), BB,
22014 std::next(MachineBasicBlock::iterator(MI)), BB->end());
22015 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
22017 // Add code to the main basic block to check if the stack limit has been hit,
22018 // and if so, jump to mallocMBB otherwise to bumpMBB.
22019 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
22020 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
22021 .addReg(tmpSPVReg).addReg(sizeVReg);
22022 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
22023 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
22024 .addReg(SPLimitVReg);
22025 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
22027 // bumpMBB simply decreases the stack pointer, since we know the current
22028 // stacklet has enough space.
22029 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
22030 .addReg(SPLimitVReg);
22031 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
22032 .addReg(SPLimitVReg);
22033 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
22035 // Calls into a routine in libgcc to allocate more space from the heap.
22036 const uint32_t *RegMask =
22037 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
22039 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
22041 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
22042 .addExternalSymbol("__morestack_allocate_stack_space")
22043 .addRegMask(RegMask)
22044 .addReg(X86::RDI, RegState::Implicit)
22045 .addReg(X86::RAX, RegState::ImplicitDefine);
22046 } else if (Is64Bit) {
22047 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
22049 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
22050 .addExternalSymbol("__morestack_allocate_stack_space")
22051 .addRegMask(RegMask)
22052 .addReg(X86::EDI, RegState::Implicit)
22053 .addReg(X86::EAX, RegState::ImplicitDefine);
22055 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
22057 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
22058 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
22059 .addExternalSymbol("__morestack_allocate_stack_space")
22060 .addRegMask(RegMask)
22061 .addReg(X86::EAX, RegState::ImplicitDefine);
22065 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
22068 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
22069 .addReg(IsLP64 ? X86::RAX : X86::EAX);
22070 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
22072 // Set up the CFG correctly.
22073 BB->addSuccessor(bumpMBB);
22074 BB->addSuccessor(mallocMBB);
22075 mallocMBB->addSuccessor(continueMBB);
22076 bumpMBB->addSuccessor(continueMBB);
22078 // Take care of the PHI nodes.
22079 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
22080 MI->getOperand(0).getReg())
22081 .addReg(mallocPtrVReg).addMBB(mallocMBB)
22082 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
22084 // Delete the original pseudo instruction.
22085 MI->eraseFromParent();
22088 return continueMBB;
22091 MachineBasicBlock *
22092 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
22093 MachineBasicBlock *BB) const {
22094 assert(!Subtarget->isTargetMachO());
22095 DebugLoc DL = MI->getDebugLoc();
22096 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
22097 *BB->getParent(), *BB, MI, DL, false);
22098 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
22099 MI->eraseFromParent(); // The pseudo instruction is gone now.
22103 MachineBasicBlock *
22104 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
22105 MachineBasicBlock *BB) const {
22106 MachineFunction *MF = BB->getParent();
22107 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22108 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
22109 DebugLoc DL = MI->getDebugLoc();
22111 assert(!isAsynchronousEHPersonality(
22112 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
22113 "SEH does not use catchret!");
22115 // Only 32-bit EH needs to worry about manually restoring stack pointers.
22116 if (!Subtarget->is32Bit())
22119 // C++ EH creates a new target block to hold the restore code, and wires up
22120 // the new block to the return destination with a normal JMP_4.
22121 MachineBasicBlock *RestoreMBB =
22122 MF->CreateMachineBasicBlock(BB->getBasicBlock());
22123 assert(BB->succ_size() == 1);
22124 MF->insert(std::next(BB->getIterator()), RestoreMBB);
22125 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
22126 BB->addSuccessor(RestoreMBB);
22127 MI->getOperand(0).setMBB(RestoreMBB);
22129 auto RestoreMBBI = RestoreMBB->begin();
22130 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
22131 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
22135 MachineBasicBlock *
22136 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
22137 MachineBasicBlock *BB) const {
22138 MachineFunction *MF = BB->getParent();
22139 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
22140 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
22141 // Only 32-bit SEH requires special handling for catchpad.
22142 if (IsSEH && Subtarget->is32Bit()) {
22143 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22144 DebugLoc DL = MI->getDebugLoc();
22145 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
22147 MI->eraseFromParent();
22151 MachineBasicBlock *
22152 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
22153 MachineBasicBlock *BB) const {
22154 // This is pretty easy. We're taking the value that we received from
22155 // our load from the relocation, sticking it in either RDI (x86-64)
22156 // or EAX and doing an indirect call. The return value will then
22157 // be in the normal return register.
22158 MachineFunction *F = BB->getParent();
22159 const X86InstrInfo *TII = Subtarget->getInstrInfo();
22160 DebugLoc DL = MI->getDebugLoc();
22162 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
22163 assert(MI->getOperand(3).isGlobal() && "This should be a global");
22165 // Get a register mask for the lowered call.
22166 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
22167 // proper register mask.
22168 const uint32_t *RegMask =
22169 Subtarget->is64Bit() ?
22170 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
22171 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
22172 if (Subtarget->is64Bit()) {
22173 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
22174 TII->get(X86::MOV64rm), X86::RDI)
22176 .addImm(0).addReg(0)
22177 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
22178 MI->getOperand(3).getTargetFlags())
22180 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
22181 addDirectMem(MIB, X86::RDI);
22182 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
22183 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
22184 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
22185 TII->get(X86::MOV32rm), X86::EAX)
22187 .addImm(0).addReg(0)
22188 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
22189 MI->getOperand(3).getTargetFlags())
22191 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
22192 addDirectMem(MIB, X86::EAX);
22193 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
22195 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
22196 TII->get(X86::MOV32rm), X86::EAX)
22197 .addReg(TII->getGlobalBaseReg(F))
22198 .addImm(0).addReg(0)
22199 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
22200 MI->getOperand(3).getTargetFlags())
22202 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
22203 addDirectMem(MIB, X86::EAX);
22204 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
22207 MI->eraseFromParent(); // The pseudo instruction is gone now.
22211 MachineBasicBlock *
22212 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
22213 MachineBasicBlock *MBB) const {
22214 DebugLoc DL = MI->getDebugLoc();
22215 MachineFunction *MF = MBB->getParent();
22216 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22217 MachineRegisterInfo &MRI = MF->getRegInfo();
22219 const BasicBlock *BB = MBB->getBasicBlock();
22220 MachineFunction::iterator I = ++MBB->getIterator();
22222 // Memory Reference
22223 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
22224 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
22227 unsigned MemOpndSlot = 0;
22229 unsigned CurOp = 0;
22231 DstReg = MI->getOperand(CurOp++).getReg();
22232 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
22233 assert(RC->hasType(MVT::i32) && "Invalid destination!");
22234 unsigned mainDstReg = MRI.createVirtualRegister(RC);
22235 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
22237 MemOpndSlot = CurOp;
22239 MVT PVT = getPointerTy(MF->getDataLayout());
22240 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
22241 "Invalid Pointer Size!");
22243 // For v = setjmp(buf), we generate
22246 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
22247 // SjLjSetup restoreMBB
22253 // v = phi(main, restore)
22256 // if base pointer being used, load it from frame
22259 MachineBasicBlock *thisMBB = MBB;
22260 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
22261 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
22262 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
22263 MF->insert(I, mainMBB);
22264 MF->insert(I, sinkMBB);
22265 MF->push_back(restoreMBB);
22266 restoreMBB->setHasAddressTaken();
22268 MachineInstrBuilder MIB;
22270 // Transfer the remainder of BB and its successor edges to sinkMBB.
22271 sinkMBB->splice(sinkMBB->begin(), MBB,
22272 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
22273 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
22276 unsigned PtrStoreOpc = 0;
22277 unsigned LabelReg = 0;
22278 const int64_t LabelOffset = 1 * PVT.getStoreSize();
22279 Reloc::Model RM = MF->getTarget().getRelocationModel();
22280 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
22281 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
22283 // Prepare IP either in reg or imm.
22284 if (!UseImmLabel) {
22285 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
22286 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
22287 LabelReg = MRI.createVirtualRegister(PtrRC);
22288 if (Subtarget->is64Bit()) {
22289 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
22293 .addMBB(restoreMBB)
22296 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
22297 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
22298 .addReg(XII->getGlobalBaseReg(MF))
22301 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
22305 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
22307 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
22308 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22309 if (i == X86::AddrDisp)
22310 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
22312 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
22315 MIB.addReg(LabelReg);
22317 MIB.addMBB(restoreMBB);
22318 MIB.setMemRefs(MMOBegin, MMOEnd);
22320 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
22321 .addMBB(restoreMBB);
22323 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
22324 MIB.addRegMask(RegInfo->getNoPreservedMask());
22325 thisMBB->addSuccessor(mainMBB);
22326 thisMBB->addSuccessor(restoreMBB);
22330 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
22331 mainMBB->addSuccessor(sinkMBB);
22334 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
22335 TII->get(X86::PHI), DstReg)
22336 .addReg(mainDstReg).addMBB(mainMBB)
22337 .addReg(restoreDstReg).addMBB(restoreMBB);
22340 if (RegInfo->hasBasePointer(*MF)) {
22341 const bool Uses64BitFramePtr =
22342 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
22343 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
22344 X86FI->setRestoreBasePointer(MF);
22345 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
22346 unsigned BasePtr = RegInfo->getBaseRegister();
22347 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
22348 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
22349 FramePtr, true, X86FI->getRestoreBasePointerOffset())
22350 .setMIFlag(MachineInstr::FrameSetup);
22352 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
22353 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
22354 restoreMBB->addSuccessor(sinkMBB);
22356 MI->eraseFromParent();
22360 MachineBasicBlock *
22361 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
22362 MachineBasicBlock *MBB) const {
22363 DebugLoc DL = MI->getDebugLoc();
22364 MachineFunction *MF = MBB->getParent();
22365 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22366 MachineRegisterInfo &MRI = MF->getRegInfo();
22368 // Memory Reference
22369 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
22370 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
22372 MVT PVT = getPointerTy(MF->getDataLayout());
22373 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
22374 "Invalid Pointer Size!");
22376 const TargetRegisterClass *RC =
22377 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
22378 unsigned Tmp = MRI.createVirtualRegister(RC);
22379 // Since FP is only updated here but NOT referenced, it's treated as GPR.
22380 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
22381 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
22382 unsigned SP = RegInfo->getStackRegister();
22384 MachineInstrBuilder MIB;
22386 const int64_t LabelOffset = 1 * PVT.getStoreSize();
22387 const int64_t SPOffset = 2 * PVT.getStoreSize();
22389 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
22390 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
22393 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
22394 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
22395 MIB.addOperand(MI->getOperand(i));
22396 MIB.setMemRefs(MMOBegin, MMOEnd);
22398 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
22399 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22400 if (i == X86::AddrDisp)
22401 MIB.addDisp(MI->getOperand(i), LabelOffset);
22403 MIB.addOperand(MI->getOperand(i));
22405 MIB.setMemRefs(MMOBegin, MMOEnd);
22407 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
22408 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
22409 if (i == X86::AddrDisp)
22410 MIB.addDisp(MI->getOperand(i), SPOffset);
22412 MIB.addOperand(MI->getOperand(i));
22414 MIB.setMemRefs(MMOBegin, MMOEnd);
22416 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
22418 MI->eraseFromParent();
22422 // Replace 213-type (isel default) FMA3 instructions with 231-type for
22423 // accumulator loops. Writing back to the accumulator allows the coalescer
22424 // to remove extra copies in the loop.
22425 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
22426 MachineBasicBlock *
22427 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
22428 MachineBasicBlock *MBB) const {
22429 MachineOperand &AddendOp = MI->getOperand(3);
22431 // Bail out early if the addend isn't a register - we can't switch these.
22432 if (!AddendOp.isReg())
22435 MachineFunction &MF = *MBB->getParent();
22436 MachineRegisterInfo &MRI = MF.getRegInfo();
22438 // Check whether the addend is defined by a PHI:
22439 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
22440 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
22441 if (!AddendDef.isPHI())
22444 // Look for the following pattern:
22446 // %addend = phi [%entry, 0], [%loop, %result]
22448 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
22452 // %addend = phi [%entry, 0], [%loop, %result]
22454 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
22456 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
22457 assert(AddendDef.getOperand(i).isReg());
22458 MachineOperand PHISrcOp = AddendDef.getOperand(i);
22459 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
22460 if (&PHISrcInst == MI) {
22461 // Found a matching instruction.
22462 unsigned NewFMAOpc = 0;
22463 switch (MI->getOpcode()) {
22464 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
22465 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
22466 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
22467 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
22468 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
22469 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
22470 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
22471 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
22472 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
22473 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
22474 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
22475 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
22476 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
22477 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
22478 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
22479 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
22480 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
22481 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
22482 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
22483 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
22485 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
22486 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
22487 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
22488 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
22489 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
22490 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
22491 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
22492 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
22493 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
22494 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
22495 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
22496 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
22497 default: llvm_unreachable("Unrecognized FMA variant.");
22500 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
22501 MachineInstrBuilder MIB =
22502 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
22503 .addOperand(MI->getOperand(0))
22504 .addOperand(MI->getOperand(3))
22505 .addOperand(MI->getOperand(2))
22506 .addOperand(MI->getOperand(1));
22507 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
22508 MI->eraseFromParent();
22515 MachineBasicBlock *
22516 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
22517 MachineBasicBlock *BB) const {
22518 switch (MI->getOpcode()) {
22519 default: llvm_unreachable("Unexpected instr type to insert");
22520 case X86::TAILJMPd64:
22521 case X86::TAILJMPr64:
22522 case X86::TAILJMPm64:
22523 case X86::TAILJMPd64_REX:
22524 case X86::TAILJMPr64_REX:
22525 case X86::TAILJMPm64_REX:
22526 llvm_unreachable("TAILJMP64 would not be touched here.");
22527 case X86::TCRETURNdi64:
22528 case X86::TCRETURNri64:
22529 case X86::TCRETURNmi64:
22531 case X86::WIN_ALLOCA:
22532 return EmitLoweredWinAlloca(MI, BB);
22533 case X86::CATCHRET:
22534 return EmitLoweredCatchRet(MI, BB);
22535 case X86::CATCHPAD:
22536 return EmitLoweredCatchPad(MI, BB);
22537 case X86::SEG_ALLOCA_32:
22538 case X86::SEG_ALLOCA_64:
22539 return EmitLoweredSegAlloca(MI, BB);
22540 case X86::TLSCall_32:
22541 case X86::TLSCall_64:
22542 return EmitLoweredTLSCall(MI, BB);
22543 case X86::CMOV_FR32:
22544 case X86::CMOV_FR64:
22545 case X86::CMOV_FR128:
22546 case X86::CMOV_GR8:
22547 case X86::CMOV_GR16:
22548 case X86::CMOV_GR32:
22549 case X86::CMOV_RFP32:
22550 case X86::CMOV_RFP64:
22551 case X86::CMOV_RFP80:
22552 case X86::CMOV_V2F64:
22553 case X86::CMOV_V2I64:
22554 case X86::CMOV_V4F32:
22555 case X86::CMOV_V4F64:
22556 case X86::CMOV_V4I64:
22557 case X86::CMOV_V16F32:
22558 case X86::CMOV_V8F32:
22559 case X86::CMOV_V8F64:
22560 case X86::CMOV_V8I64:
22561 case X86::CMOV_V8I1:
22562 case X86::CMOV_V16I1:
22563 case X86::CMOV_V32I1:
22564 case X86::CMOV_V64I1:
22565 return EmitLoweredSelect(MI, BB);
22567 case X86::RDFLAGS32:
22568 case X86::RDFLAGS64: {
22569 DebugLoc DL = MI->getDebugLoc();
22570 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22572 MI->getOpcode() == X86::RDFLAGS32 ? X86::PUSHF32 : X86::PUSHF64;
22574 MI->getOpcode() == X86::RDFLAGS32 ? X86::POP32r : X86::POP64r;
22575 BuildMI(*BB, MI, DL, TII->get(PushF));
22576 BuildMI(*BB, MI, DL, TII->get(Pop), MI->getOperand(0).getReg());
22578 MI->eraseFromParent(); // The pseudo is gone now.
22582 case X86::WRFLAGS32:
22583 case X86::WRFLAGS64: {
22584 DebugLoc DL = MI->getDebugLoc();
22585 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22587 MI->getOpcode() == X86::WRFLAGS32 ? X86::PUSH32r : X86::PUSH64r;
22589 MI->getOpcode() == X86::WRFLAGS32 ? X86::POPF32 : X86::POPF64;
22590 BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI->getOperand(0).getReg());
22591 BuildMI(*BB, MI, DL, TII->get(PopF));
22593 MI->eraseFromParent(); // The pseudo is gone now.
22597 case X86::RELEASE_FADD32mr:
22598 case X86::RELEASE_FADD64mr:
22599 return EmitLoweredAtomicFP(MI, BB);
22601 case X86::FP32_TO_INT16_IN_MEM:
22602 case X86::FP32_TO_INT32_IN_MEM:
22603 case X86::FP32_TO_INT64_IN_MEM:
22604 case X86::FP64_TO_INT16_IN_MEM:
22605 case X86::FP64_TO_INT32_IN_MEM:
22606 case X86::FP64_TO_INT64_IN_MEM:
22607 case X86::FP80_TO_INT16_IN_MEM:
22608 case X86::FP80_TO_INT32_IN_MEM:
22609 case X86::FP80_TO_INT64_IN_MEM: {
22610 MachineFunction *F = BB->getParent();
22611 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22612 DebugLoc DL = MI->getDebugLoc();
22614 // Change the floating point control register to use "round towards zero"
22615 // mode when truncating to an integer value.
22616 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22617 addFrameReference(BuildMI(*BB, MI, DL,
22618 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22620 // Load the old value of the high byte of the control word...
22622 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22623 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22626 // Set the high part to be round to zero...
22627 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22630 // Reload the modified control word now...
22631 addFrameReference(BuildMI(*BB, MI, DL,
22632 TII->get(X86::FLDCW16m)), CWFrameIdx);
22634 // Restore the memory image of control word to original value
22635 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22638 // Get the X86 opcode to use.
22640 switch (MI->getOpcode()) {
22641 default: llvm_unreachable("illegal opcode!");
22642 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22643 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22644 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22645 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22646 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22647 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22648 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22649 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22650 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22654 MachineOperand &Op = MI->getOperand(0);
22656 AM.BaseType = X86AddressMode::RegBase;
22657 AM.Base.Reg = Op.getReg();
22659 AM.BaseType = X86AddressMode::FrameIndexBase;
22660 AM.Base.FrameIndex = Op.getIndex();
22662 Op = MI->getOperand(1);
22664 AM.Scale = Op.getImm();
22665 Op = MI->getOperand(2);
22667 AM.IndexReg = Op.getImm();
22668 Op = MI->getOperand(3);
22669 if (Op.isGlobal()) {
22670 AM.GV = Op.getGlobal();
22672 AM.Disp = Op.getImm();
22674 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22675 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22677 // Reload the original control word now.
22678 addFrameReference(BuildMI(*BB, MI, DL,
22679 TII->get(X86::FLDCW16m)), CWFrameIdx);
22681 MI->eraseFromParent(); // The pseudo instruction is gone now.
22684 // String/text processing lowering.
22685 case X86::PCMPISTRM128REG:
22686 case X86::VPCMPISTRM128REG:
22687 case X86::PCMPISTRM128MEM:
22688 case X86::VPCMPISTRM128MEM:
22689 case X86::PCMPESTRM128REG:
22690 case X86::VPCMPESTRM128REG:
22691 case X86::PCMPESTRM128MEM:
22692 case X86::VPCMPESTRM128MEM:
22693 assert(Subtarget->hasSSE42() &&
22694 "Target must have SSE4.2 or AVX features enabled");
22695 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22697 // String/text processing lowering.
22698 case X86::PCMPISTRIREG:
22699 case X86::VPCMPISTRIREG:
22700 case X86::PCMPISTRIMEM:
22701 case X86::VPCMPISTRIMEM:
22702 case X86::PCMPESTRIREG:
22703 case X86::VPCMPESTRIREG:
22704 case X86::PCMPESTRIMEM:
22705 case X86::VPCMPESTRIMEM:
22706 assert(Subtarget->hasSSE42() &&
22707 "Target must have SSE4.2 or AVX features enabled");
22708 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22710 // Thread synchronization.
22712 return EmitMonitor(MI, BB, Subtarget);
22715 return EmitWRPKRU(MI, BB, Subtarget);
22717 return EmitRDPKRU(MI, BB, Subtarget);
22720 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22722 case X86::VASTART_SAVE_XMM_REGS:
22723 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22725 case X86::VAARG_64:
22726 return EmitVAARG64WithCustomInserter(MI, BB);
22728 case X86::EH_SjLj_SetJmp32:
22729 case X86::EH_SjLj_SetJmp64:
22730 return emitEHSjLjSetJmp(MI, BB);
22732 case X86::EH_SjLj_LongJmp32:
22733 case X86::EH_SjLj_LongJmp64:
22734 return emitEHSjLjLongJmp(MI, BB);
22736 case TargetOpcode::STATEPOINT:
22737 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22738 // this point in the process. We diverge later.
22739 return emitPatchPoint(MI, BB);
22741 case TargetOpcode::STACKMAP:
22742 case TargetOpcode::PATCHPOINT:
22743 return emitPatchPoint(MI, BB);
22745 case X86::VFMADDPDr213r:
22746 case X86::VFMADDPSr213r:
22747 case X86::VFMADDSDr213r:
22748 case X86::VFMADDSSr213r:
22749 case X86::VFMSUBPDr213r:
22750 case X86::VFMSUBPSr213r:
22751 case X86::VFMSUBSDr213r:
22752 case X86::VFMSUBSSr213r:
22753 case X86::VFNMADDPDr213r:
22754 case X86::VFNMADDPSr213r:
22755 case X86::VFNMADDSDr213r:
22756 case X86::VFNMADDSSr213r:
22757 case X86::VFNMSUBPDr213r:
22758 case X86::VFNMSUBPSr213r:
22759 case X86::VFNMSUBSDr213r:
22760 case X86::VFNMSUBSSr213r:
22761 case X86::VFMADDSUBPDr213r:
22762 case X86::VFMADDSUBPSr213r:
22763 case X86::VFMSUBADDPDr213r:
22764 case X86::VFMSUBADDPSr213r:
22765 case X86::VFMADDPDr213rY:
22766 case X86::VFMADDPSr213rY:
22767 case X86::VFMSUBPDr213rY:
22768 case X86::VFMSUBPSr213rY:
22769 case X86::VFNMADDPDr213rY:
22770 case X86::VFNMADDPSr213rY:
22771 case X86::VFNMSUBPDr213rY:
22772 case X86::VFNMSUBPSr213rY:
22773 case X86::VFMADDSUBPDr213rY:
22774 case X86::VFMADDSUBPSr213rY:
22775 case X86::VFMSUBADDPDr213rY:
22776 case X86::VFMSUBADDPSr213rY:
22777 return emitFMA3Instr(MI, BB);
22781 //===----------------------------------------------------------------------===//
22782 // X86 Optimization Hooks
22783 //===----------------------------------------------------------------------===//
22785 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22788 const SelectionDAG &DAG,
22789 unsigned Depth) const {
22790 unsigned BitWidth = KnownZero.getBitWidth();
22791 unsigned Opc = Op.getOpcode();
22792 assert((Opc >= ISD::BUILTIN_OP_END ||
22793 Opc == ISD::INTRINSIC_WO_CHAIN ||
22794 Opc == ISD::INTRINSIC_W_CHAIN ||
22795 Opc == ISD::INTRINSIC_VOID) &&
22796 "Should use MaskedValueIsZero if you don't know whether Op"
22797 " is a target node!");
22799 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22813 // These nodes' second result is a boolean.
22814 if (Op.getResNo() == 0)
22817 case X86ISD::SETCC:
22818 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22820 case ISD::INTRINSIC_WO_CHAIN: {
22821 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22822 unsigned NumLoBits = 0;
22825 case Intrinsic::x86_sse_movmsk_ps:
22826 case Intrinsic::x86_avx_movmsk_ps_256:
22827 case Intrinsic::x86_sse2_movmsk_pd:
22828 case Intrinsic::x86_avx_movmsk_pd_256:
22829 case Intrinsic::x86_mmx_pmovmskb:
22830 case Intrinsic::x86_sse2_pmovmskb_128:
22831 case Intrinsic::x86_avx2_pmovmskb: {
22832 // High bits of movmskp{s|d}, pmovmskb are known zero.
22834 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22835 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22836 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22837 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22838 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22839 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22840 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22841 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22843 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22852 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22854 const SelectionDAG &,
22855 unsigned Depth) const {
22856 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22857 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22858 return Op.getValueType().getScalarSizeInBits();
22864 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22865 /// node is a GlobalAddress + offset.
22866 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22867 const GlobalValue* &GA,
22868 int64_t &Offset) const {
22869 if (N->getOpcode() == X86ISD::Wrapper) {
22870 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22871 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22872 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22876 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22879 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22880 /// FIXME: This could be expanded to support 512 bit vectors as well.
22881 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22882 TargetLowering::DAGCombinerInfo &DCI,
22883 const X86Subtarget* Subtarget) {
22885 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22886 SDValue V1 = SVOp->getOperand(0);
22887 SDValue V2 = SVOp->getOperand(1);
22888 MVT VT = SVOp->getSimpleValueType(0);
22889 unsigned NumElems = VT.getVectorNumElements();
22891 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22892 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22896 // V UNDEF BUILD_VECTOR UNDEF
22898 // CONCAT_VECTOR CONCAT_VECTOR
22901 // RESULT: V + zero extended
22903 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22904 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22905 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22908 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22911 // To match the shuffle mask, the first half of the mask should
22912 // be exactly the first vector, and all the rest a splat with the
22913 // first element of the second one.
22914 for (unsigned i = 0; i != NumElems/2; ++i)
22915 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22916 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22919 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22920 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22921 if (Ld->hasNUsesOfValue(1, 0)) {
22922 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22923 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22925 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22927 Ld->getPointerInfo(),
22928 Ld->getAlignment(),
22929 false/*isVolatile*/, true/*ReadMem*/,
22930 false/*WriteMem*/);
22932 // Make sure the newly-created LOAD is in the same position as Ld in
22933 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22934 // and update uses of Ld's output chain to use the TokenFactor.
22935 if (Ld->hasAnyUseOfValue(1)) {
22936 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22937 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22938 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22939 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22940 SDValue(ResNode.getNode(), 1));
22943 return DAG.getBitcast(VT, ResNode);
22947 // Emit a zeroed vector and insert the desired subvector on its
22949 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22950 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22951 return DCI.CombineTo(N, InsV);
22957 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22960 /// This is the leaf of the recursive combinine below. When we have found some
22961 /// chain of single-use x86 shuffle instructions and accumulated the combined
22962 /// shuffle mask represented by them, this will try to pattern match that mask
22963 /// into either a single instruction if there is a special purpose instruction
22964 /// for this operation, or into a PSHUFB instruction which is a fully general
22965 /// instruction but should only be used to replace chains over a certain depth.
22966 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22967 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22968 TargetLowering::DAGCombinerInfo &DCI,
22969 const X86Subtarget *Subtarget) {
22970 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22972 // Find the operand that enters the chain. Note that multiple uses are OK
22973 // here, we're not going to remove the operand we find.
22974 SDValue Input = Op.getOperand(0);
22975 while (Input.getOpcode() == ISD::BITCAST)
22976 Input = Input.getOperand(0);
22978 MVT VT = Input.getSimpleValueType();
22979 MVT RootVT = Root.getSimpleValueType();
22982 if (Mask.size() == 1) {
22983 int Index = Mask[0];
22984 assert((Index >= 0 || Index == SM_SentinelUndef ||
22985 Index == SM_SentinelZero) &&
22986 "Invalid shuffle index found!");
22988 // We may end up with an accumulated mask of size 1 as a result of
22989 // widening of shuffle operands (see function canWidenShuffleElements).
22990 // If the only shuffle index is equal to SM_SentinelZero then propagate
22991 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22992 // mask, and therefore the entire chain of shuffles can be folded away.
22993 if (Index == SM_SentinelZero)
22994 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22996 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
23001 // Use the float domain if the operand type is a floating point type.
23002 bool FloatDomain = VT.isFloatingPoint();
23004 // For floating point shuffles, we don't have free copies in the shuffle
23005 // instructions or the ability to load as part of the instruction, so
23006 // canonicalize their shuffles to UNPCK or MOV variants.
23008 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
23009 // vectors because it can have a load folded into it that UNPCK cannot. This
23010 // doesn't preclude something switching to the shorter encoding post-RA.
23012 // FIXME: Should teach these routines about AVX vector widths.
23013 if (FloatDomain && VT.is128BitVector()) {
23014 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
23015 bool Lo = Mask.equals({0, 0});
23018 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
23019 // is no slower than UNPCKLPD but has the option to fold the input operand
23020 // into even an unaligned memory load.
23021 if (Lo && Subtarget->hasSSE3()) {
23022 Shuffle = X86ISD::MOVDDUP;
23023 ShuffleVT = MVT::v2f64;
23025 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
23026 // than the UNPCK variants.
23027 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
23028 ShuffleVT = MVT::v4f32;
23030 if (Depth == 1 && Root->getOpcode() == Shuffle)
23031 return false; // Nothing to do!
23032 Op = DAG.getBitcast(ShuffleVT, Input);
23033 DCI.AddToWorklist(Op.getNode());
23034 if (Shuffle == X86ISD::MOVDDUP)
23035 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
23037 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
23038 DCI.AddToWorklist(Op.getNode());
23039 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23043 if (Subtarget->hasSSE3() &&
23044 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
23045 bool Lo = Mask.equals({0, 0, 2, 2});
23046 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
23047 MVT ShuffleVT = MVT::v4f32;
23048 if (Depth == 1 && Root->getOpcode() == Shuffle)
23049 return false; // Nothing to do!
23050 Op = DAG.getBitcast(ShuffleVT, Input);
23051 DCI.AddToWorklist(Op.getNode());
23052 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
23053 DCI.AddToWorklist(Op.getNode());
23054 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23058 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
23059 bool Lo = Mask.equals({0, 0, 1, 1});
23060 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
23061 MVT ShuffleVT = MVT::v4f32;
23062 if (Depth == 1 && Root->getOpcode() == Shuffle)
23063 return false; // Nothing to do!
23064 Op = DAG.getBitcast(ShuffleVT, Input);
23065 DCI.AddToWorklist(Op.getNode());
23066 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
23067 DCI.AddToWorklist(Op.getNode());
23068 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23074 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
23075 // variants as none of these have single-instruction variants that are
23076 // superior to the UNPCK formulation.
23077 if (!FloatDomain && VT.is128BitVector() &&
23078 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23079 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
23080 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
23082 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
23083 bool Lo = Mask[0] == 0;
23084 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
23085 if (Depth == 1 && Root->getOpcode() == Shuffle)
23086 return false; // Nothing to do!
23088 switch (Mask.size()) {
23090 ShuffleVT = MVT::v8i16;
23093 ShuffleVT = MVT::v16i8;
23096 llvm_unreachable("Impossible mask size!");
23098 Op = DAG.getBitcast(ShuffleVT, Input);
23099 DCI.AddToWorklist(Op.getNode());
23100 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
23101 DCI.AddToWorklist(Op.getNode());
23102 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23107 // Don't try to re-form single instruction chains under any circumstances now
23108 // that we've done encoding canonicalization for them.
23112 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
23113 // can replace them with a single PSHUFB instruction profitably. Intel's
23114 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
23115 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
23116 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
23117 SmallVector<SDValue, 16> PSHUFBMask;
23118 int NumBytes = VT.getSizeInBits() / 8;
23119 int Ratio = NumBytes / Mask.size();
23120 for (int i = 0; i < NumBytes; ++i) {
23121 if (Mask[i / Ratio] == SM_SentinelUndef) {
23122 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
23125 int M = Mask[i / Ratio] != SM_SentinelZero
23126 ? Ratio * Mask[i / Ratio] + i % Ratio
23128 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
23130 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
23131 Op = DAG.getBitcast(ByteVT, Input);
23132 DCI.AddToWorklist(Op.getNode());
23133 SDValue PSHUFBMaskOp =
23134 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
23135 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
23136 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
23137 DCI.AddToWorklist(Op.getNode());
23138 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
23143 // Failed to find any combines.
23147 /// \brief Fully generic combining of x86 shuffle instructions.
23149 /// This should be the last combine run over the x86 shuffle instructions. Once
23150 /// they have been fully optimized, this will recursively consider all chains
23151 /// of single-use shuffle instructions, build a generic model of the cumulative
23152 /// shuffle operation, and check for simpler instructions which implement this
23153 /// operation. We use this primarily for two purposes:
23155 /// 1) Collapse generic shuffles to specialized single instructions when
23156 /// equivalent. In most cases, this is just an encoding size win, but
23157 /// sometimes we will collapse multiple generic shuffles into a single
23158 /// special-purpose shuffle.
23159 /// 2) Look for sequences of shuffle instructions with 3 or more total
23160 /// instructions, and replace them with the slightly more expensive SSSE3
23161 /// PSHUFB instruction if available. We do this as the last combining step
23162 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
23163 /// a suitable short sequence of other instructions. The PHUFB will either
23164 /// use a register or have to read from memory and so is slightly (but only
23165 /// slightly) more expensive than the other shuffle instructions.
23167 /// Because this is inherently a quadratic operation (for each shuffle in
23168 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
23169 /// This should never be an issue in practice as the shuffle lowering doesn't
23170 /// produce sequences of more than 8 instructions.
23172 /// FIXME: We will currently miss some cases where the redundant shuffling
23173 /// would simplify under the threshold for PSHUFB formation because of
23174 /// combine-ordering. To fix this, we should do the redundant instruction
23175 /// combining in this recursive walk.
23176 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
23177 ArrayRef<int> RootMask,
23178 int Depth, bool HasPSHUFB,
23180 TargetLowering::DAGCombinerInfo &DCI,
23181 const X86Subtarget *Subtarget) {
23182 // Bound the depth of our recursive combine because this is ultimately
23183 // quadratic in nature.
23187 // Directly rip through bitcasts to find the underlying operand.
23188 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
23189 Op = Op.getOperand(0);
23191 MVT VT = Op.getSimpleValueType();
23192 if (!VT.isVector())
23193 return false; // Bail if we hit a non-vector.
23195 assert(Root.getSimpleValueType().isVector() &&
23196 "Shuffles operate on vector types!");
23197 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
23198 "Can only combine shuffles of the same vector register size.");
23200 if (!isTargetShuffle(Op.getOpcode()))
23202 SmallVector<int, 16> OpMask;
23204 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, true, OpMask, IsUnary);
23205 // We only can combine unary shuffles which we can decode the mask for.
23206 if (!HaveMask || !IsUnary)
23209 assert(VT.getVectorNumElements() == OpMask.size() &&
23210 "Different mask size from vector size!");
23211 assert(((RootMask.size() > OpMask.size() &&
23212 RootMask.size() % OpMask.size() == 0) ||
23213 (OpMask.size() > RootMask.size() &&
23214 OpMask.size() % RootMask.size() == 0) ||
23215 OpMask.size() == RootMask.size()) &&
23216 "The smaller number of elements must divide the larger.");
23217 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
23218 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
23219 assert(((RootRatio == 1 && OpRatio == 1) ||
23220 (RootRatio == 1) != (OpRatio == 1)) &&
23221 "Must not have a ratio for both incoming and op masks!");
23223 SmallVector<int, 16> Mask;
23224 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
23226 // Merge this shuffle operation's mask into our accumulated mask. Note that
23227 // this shuffle's mask will be the first applied to the input, followed by the
23228 // root mask to get us all the way to the root value arrangement. The reason
23229 // for this order is that we are recursing up the operation chain.
23230 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
23231 int RootIdx = i / RootRatio;
23232 if (RootMask[RootIdx] < 0) {
23233 // This is a zero or undef lane, we're done.
23234 Mask.push_back(RootMask[RootIdx]);
23238 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
23239 int OpIdx = RootMaskedIdx / OpRatio;
23240 if (OpMask[OpIdx] < 0) {
23241 // The incoming lanes are zero or undef, it doesn't matter which ones we
23243 Mask.push_back(OpMask[OpIdx]);
23247 // Ok, we have non-zero lanes, map them through.
23248 Mask.push_back(OpMask[OpIdx] * OpRatio +
23249 RootMaskedIdx % OpRatio);
23252 // See if we can recurse into the operand to combine more things.
23253 switch (Op.getOpcode()) {
23254 case X86ISD::PSHUFB:
23256 case X86ISD::PSHUFD:
23257 case X86ISD::PSHUFHW:
23258 case X86ISD::PSHUFLW:
23259 if (Op.getOperand(0).hasOneUse() &&
23260 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
23261 HasPSHUFB, DAG, DCI, Subtarget))
23265 case X86ISD::UNPCKL:
23266 case X86ISD::UNPCKH:
23267 assert(Op.getOperand(0) == Op.getOperand(1) &&
23268 "We only combine unary shuffles!");
23269 // We can't check for single use, we have to check that this shuffle is the
23271 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
23272 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
23273 HasPSHUFB, DAG, DCI, Subtarget))
23278 // Minor canonicalization of the accumulated shuffle mask to make it easier
23279 // to match below. All this does is detect masks with squential pairs of
23280 // elements, and shrink them to the half-width mask. It does this in a loop
23281 // so it will reduce the size of the mask to the minimal width mask which
23282 // performs an equivalent shuffle.
23283 SmallVector<int, 16> WidenedMask;
23284 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
23285 Mask = std::move(WidenedMask);
23286 WidenedMask.clear();
23289 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
23293 /// \brief Get the PSHUF-style mask from PSHUF node.
23295 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
23296 /// PSHUF-style masks that can be reused with such instructions.
23297 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
23298 MVT VT = N.getSimpleValueType();
23299 SmallVector<int, 4> Mask;
23301 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, false, Mask, IsUnary);
23305 // If we have more than 128-bits, only the low 128-bits of shuffle mask
23306 // matter. Check that the upper masks are repeats and remove them.
23307 if (VT.getSizeInBits() > 128) {
23308 int LaneElts = 128 / VT.getScalarSizeInBits();
23310 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
23311 for (int j = 0; j < LaneElts; ++j)
23312 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
23313 "Mask doesn't repeat in high 128-bit lanes!");
23315 Mask.resize(LaneElts);
23318 switch (N.getOpcode()) {
23319 case X86ISD::PSHUFD:
23321 case X86ISD::PSHUFLW:
23324 case X86ISD::PSHUFHW:
23325 Mask.erase(Mask.begin(), Mask.begin() + 4);
23326 for (int &M : Mask)
23330 llvm_unreachable("No valid shuffle instruction found!");
23334 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
23336 /// We walk up the chain and look for a combinable shuffle, skipping over
23337 /// shuffles that we could hoist this shuffle's transformation past without
23338 /// altering anything.
23340 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
23342 TargetLowering::DAGCombinerInfo &DCI) {
23343 assert(N.getOpcode() == X86ISD::PSHUFD &&
23344 "Called with something other than an x86 128-bit half shuffle!");
23347 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
23348 // of the shuffles in the chain so that we can form a fresh chain to replace
23350 SmallVector<SDValue, 8> Chain;
23351 SDValue V = N.getOperand(0);
23352 for (; V.hasOneUse(); V = V.getOperand(0)) {
23353 switch (V.getOpcode()) {
23355 return SDValue(); // Nothing combined!
23358 // Skip bitcasts as we always know the type for the target specific
23362 case X86ISD::PSHUFD:
23363 // Found another dword shuffle.
23366 case X86ISD::PSHUFLW:
23367 // Check that the low words (being shuffled) are the identity in the
23368 // dword shuffle, and the high words are self-contained.
23369 if (Mask[0] != 0 || Mask[1] != 1 ||
23370 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
23373 Chain.push_back(V);
23376 case X86ISD::PSHUFHW:
23377 // Check that the high words (being shuffled) are the identity in the
23378 // dword shuffle, and the low words are self-contained.
23379 if (Mask[2] != 2 || Mask[3] != 3 ||
23380 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
23383 Chain.push_back(V);
23386 case X86ISD::UNPCKL:
23387 case X86ISD::UNPCKH:
23388 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
23389 // shuffle into a preceding word shuffle.
23390 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
23391 V.getSimpleValueType().getVectorElementType() != MVT::i16)
23394 // Search for a half-shuffle which we can combine with.
23395 unsigned CombineOp =
23396 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
23397 if (V.getOperand(0) != V.getOperand(1) ||
23398 !V->isOnlyUserOf(V.getOperand(0).getNode()))
23400 Chain.push_back(V);
23401 V = V.getOperand(0);
23403 switch (V.getOpcode()) {
23405 return SDValue(); // Nothing to combine.
23407 case X86ISD::PSHUFLW:
23408 case X86ISD::PSHUFHW:
23409 if (V.getOpcode() == CombineOp)
23412 Chain.push_back(V);
23416 V = V.getOperand(0);
23420 } while (V.hasOneUse());
23423 // Break out of the loop if we break out of the switch.
23427 if (!V.hasOneUse())
23428 // We fell out of the loop without finding a viable combining instruction.
23431 // Merge this node's mask and our incoming mask.
23432 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23433 for (int &M : Mask)
23435 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
23436 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23438 // Rebuild the chain around this new shuffle.
23439 while (!Chain.empty()) {
23440 SDValue W = Chain.pop_back_val();
23442 if (V.getValueType() != W.getOperand(0).getValueType())
23443 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
23445 switch (W.getOpcode()) {
23447 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
23449 case X86ISD::UNPCKL:
23450 case X86ISD::UNPCKH:
23451 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
23454 case X86ISD::PSHUFD:
23455 case X86ISD::PSHUFLW:
23456 case X86ISD::PSHUFHW:
23457 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
23461 if (V.getValueType() != N.getValueType())
23462 V = DAG.getBitcast(N.getValueType(), V);
23464 // Return the new chain to replace N.
23468 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
23471 /// We walk up the chain, skipping shuffles of the other half and looking
23472 /// through shuffles which switch halves trying to find a shuffle of the same
23473 /// pair of dwords.
23474 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
23476 TargetLowering::DAGCombinerInfo &DCI) {
23478 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
23479 "Called with something other than an x86 128-bit half shuffle!");
23481 unsigned CombineOpcode = N.getOpcode();
23483 // Walk up a single-use chain looking for a combinable shuffle.
23484 SDValue V = N.getOperand(0);
23485 for (; V.hasOneUse(); V = V.getOperand(0)) {
23486 switch (V.getOpcode()) {
23488 return false; // Nothing combined!
23491 // Skip bitcasts as we always know the type for the target specific
23495 case X86ISD::PSHUFLW:
23496 case X86ISD::PSHUFHW:
23497 if (V.getOpcode() == CombineOpcode)
23500 // Other-half shuffles are no-ops.
23503 // Break out of the loop if we break out of the switch.
23507 if (!V.hasOneUse())
23508 // We fell out of the loop without finding a viable combining instruction.
23511 // Combine away the bottom node as its shuffle will be accumulated into
23512 // a preceding shuffle.
23513 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23515 // Record the old value.
23518 // Merge this node's mask and our incoming mask (adjusted to account for all
23519 // the pshufd instructions encountered).
23520 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23521 for (int &M : Mask)
23523 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
23524 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
23526 // Check that the shuffles didn't cancel each other out. If not, we need to
23527 // combine to the new one.
23529 // Replace the combinable shuffle with the combined one, updating all users
23530 // so that we re-evaluate the chain here.
23531 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23536 /// \brief Try to combine x86 target specific shuffles.
23537 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23538 TargetLowering::DAGCombinerInfo &DCI,
23539 const X86Subtarget *Subtarget) {
23541 MVT VT = N.getSimpleValueType();
23542 SmallVector<int, 4> Mask;
23544 switch (N.getOpcode()) {
23545 case X86ISD::PSHUFD:
23546 case X86ISD::PSHUFLW:
23547 case X86ISD::PSHUFHW:
23548 Mask = getPSHUFShuffleMask(N);
23549 assert(Mask.size() == 4);
23551 case X86ISD::UNPCKL: {
23552 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23553 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23554 // moves upper half elements into the lower half part. For example:
23556 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23558 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23560 // will be combined to:
23562 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23564 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23565 // happen due to advanced instructions.
23566 if (!VT.is128BitVector())
23569 auto Op0 = N.getOperand(0);
23570 auto Op1 = N.getOperand(1);
23571 if (Op0.getOpcode() == ISD::UNDEF &&
23572 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23573 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23575 unsigned NumElts = VT.getVectorNumElements();
23576 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23577 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23580 auto ShufOp = Op1.getOperand(0);
23581 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23582 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23586 case X86ISD::BLENDI: {
23587 SDValue V0 = N->getOperand(0);
23588 SDValue V1 = N->getOperand(1);
23589 assert(VT == V0.getSimpleValueType() && VT == V1.getSimpleValueType() &&
23590 "Unexpected input vector types");
23592 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
23593 // operands and changing the mask to 1. This saves us a bunch of
23594 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
23595 // x86InstrInfo knows how to commute this back after instruction selection
23596 // if it would help register allocation.
23598 // TODO: If optimizing for size or a processor that doesn't suffer from
23599 // partial register update stalls, this should be transformed into a MOVSD
23600 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
23602 if (VT == MVT::v2f64)
23603 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
23604 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
23605 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
23606 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
23615 // Nuke no-op shuffles that show up after combining.
23616 if (isNoopShuffleMask(Mask))
23617 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23619 // Look for simplifications involving one or two shuffle instructions.
23620 SDValue V = N.getOperand(0);
23621 switch (N.getOpcode()) {
23624 case X86ISD::PSHUFLW:
23625 case X86ISD::PSHUFHW:
23626 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23628 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23629 return SDValue(); // We combined away this shuffle, so we're done.
23631 // See if this reduces to a PSHUFD which is no more expensive and can
23632 // combine with more operations. Note that it has to at least flip the
23633 // dwords as otherwise it would have been removed as a no-op.
23634 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23635 int DMask[] = {0, 1, 2, 3};
23636 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23637 DMask[DOffset + 0] = DOffset + 1;
23638 DMask[DOffset + 1] = DOffset + 0;
23639 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23640 V = DAG.getBitcast(DVT, V);
23641 DCI.AddToWorklist(V.getNode());
23642 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23643 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23644 DCI.AddToWorklist(V.getNode());
23645 return DAG.getBitcast(VT, V);
23648 // Look for shuffle patterns which can be implemented as a single unpack.
23649 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23650 // only works when we have a PSHUFD followed by two half-shuffles.
23651 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23652 (V.getOpcode() == X86ISD::PSHUFLW ||
23653 V.getOpcode() == X86ISD::PSHUFHW) &&
23654 V.getOpcode() != N.getOpcode() &&
23656 SDValue D = V.getOperand(0);
23657 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23658 D = D.getOperand(0);
23659 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23660 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23661 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23662 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23663 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23665 for (int i = 0; i < 4; ++i) {
23666 WordMask[i + NOffset] = Mask[i] + NOffset;
23667 WordMask[i + VOffset] = VMask[i] + VOffset;
23669 // Map the word mask through the DWord mask.
23671 for (int i = 0; i < 8; ++i)
23672 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23673 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23674 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23675 // We can replace all three shuffles with an unpack.
23676 V = DAG.getBitcast(VT, D.getOperand(0));
23677 DCI.AddToWorklist(V.getNode());
23678 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23687 case X86ISD::PSHUFD:
23688 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23697 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23699 /// We combine this directly on the abstract vector shuffle nodes so it is
23700 /// easier to generically match. We also insert dummy vector shuffle nodes for
23701 /// the operands which explicitly discard the lanes which are unused by this
23702 /// operation to try to flow through the rest of the combiner the fact that
23703 /// they're unused.
23704 static SDValue combineShuffleToAddSub(SDNode *N, const X86Subtarget *Subtarget,
23705 SelectionDAG &DAG) {
23707 EVT VT = N->getValueType(0);
23708 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
23709 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
23712 // We only handle target-independent shuffles.
23713 // FIXME: It would be easy and harmless to use the target shuffle mask
23714 // extraction tool to support more.
23715 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23718 auto *SVN = cast<ShuffleVectorSDNode>(N);
23719 SmallVector<int, 8> Mask;
23720 for (int M : SVN->getMask())
23723 SDValue V1 = N->getOperand(0);
23724 SDValue V2 = N->getOperand(1);
23726 // We require the first shuffle operand to be the FSUB node, and the second to
23727 // be the FADD node.
23728 if (V1.getOpcode() == ISD::FADD && V2.getOpcode() == ISD::FSUB) {
23729 ShuffleVectorSDNode::commuteMask(Mask);
23731 } else if (V1.getOpcode() != ISD::FSUB || V2.getOpcode() != ISD::FADD)
23734 // If there are other uses of these operations we can't fold them.
23735 if (!V1->hasOneUse() || !V2->hasOneUse())
23738 // Ensure that both operations have the same operands. Note that we can
23739 // commute the FADD operands.
23740 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23741 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23742 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23745 // We're looking for blends between FADD and FSUB nodes. We insist on these
23746 // nodes being lined up in a specific expected pattern.
23747 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23748 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23749 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23752 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23755 /// PerformShuffleCombine - Performs several different shuffle combines.
23756 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23757 TargetLowering::DAGCombinerInfo &DCI,
23758 const X86Subtarget *Subtarget) {
23760 SDValue N0 = N->getOperand(0);
23761 SDValue N1 = N->getOperand(1);
23762 EVT VT = N->getValueType(0);
23764 // Don't create instructions with illegal types after legalize types has run.
23765 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23766 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23769 // If we have legalized the vector types, look for blends of FADD and FSUB
23770 // nodes that we can fuse into an ADDSUB node.
23771 if (TLI.isTypeLegal(VT))
23772 if (SDValue AddSub = combineShuffleToAddSub(N, Subtarget, DAG))
23775 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23776 if (TLI.isTypeLegal(VT) && Subtarget->hasFp256() && VT.is256BitVector() &&
23777 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23778 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23780 // During Type Legalization, when promoting illegal vector types,
23781 // the backend might introduce new shuffle dag nodes and bitcasts.
23783 // This code performs the following transformation:
23784 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23785 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23787 // We do this only if both the bitcast and the BINOP dag nodes have
23788 // one use. Also, perform this transformation only if the new binary
23789 // operation is legal. This is to avoid introducing dag nodes that
23790 // potentially need to be further expanded (or custom lowered) into a
23791 // less optimal sequence of dag nodes.
23792 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23793 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23794 N0.getOpcode() == ISD::BITCAST) {
23795 SDValue BC0 = N0.getOperand(0);
23796 EVT SVT = BC0.getValueType();
23797 unsigned Opcode = BC0.getOpcode();
23798 unsigned NumElts = VT.getVectorNumElements();
23800 if (BC0.hasOneUse() && SVT.isVector() &&
23801 SVT.getVectorNumElements() * 2 == NumElts &&
23802 TLI.isOperationLegal(Opcode, VT)) {
23803 bool CanFold = false;
23815 unsigned SVTNumElts = SVT.getVectorNumElements();
23816 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23817 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23818 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23819 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23820 CanFold = SVOp->getMaskElt(i) < 0;
23823 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23824 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23825 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23826 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23831 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23832 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23833 // consecutive, non-overlapping, and in the right order.
23834 SmallVector<SDValue, 16> Elts;
23835 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23836 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23838 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23841 if (isTargetShuffle(N->getOpcode())) {
23843 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23844 if (Shuffle.getNode())
23847 // Try recursively combining arbitrary sequences of x86 shuffle
23848 // instructions into higher-order shuffles. We do this after combining
23849 // specific PSHUF instruction sequences into their minimal form so that we
23850 // can evaluate how many specialized shuffle instructions are involved in
23851 // a particular chain.
23852 SmallVector<int, 1> NonceMask; // Just a placeholder.
23853 NonceMask.push_back(0);
23854 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23855 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23857 return SDValue(); // This routine will use CombineTo to replace N.
23863 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23864 /// specific shuffle of a load can be folded into a single element load.
23865 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23866 /// shuffles have been custom lowered so we need to handle those here.
23867 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23868 TargetLowering::DAGCombinerInfo &DCI) {
23869 if (DCI.isBeforeLegalizeOps())
23872 SDValue InVec = N->getOperand(0);
23873 SDValue EltNo = N->getOperand(1);
23874 EVT EltVT = N->getValueType(0);
23876 if (!isa<ConstantSDNode>(EltNo))
23879 EVT OriginalVT = InVec.getValueType();
23881 if (InVec.getOpcode() == ISD::BITCAST) {
23882 // Don't duplicate a load with other uses.
23883 if (!InVec.hasOneUse())
23885 EVT BCVT = InVec.getOperand(0).getValueType();
23886 if (!BCVT.isVector() ||
23887 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23889 InVec = InVec.getOperand(0);
23892 EVT CurrentVT = InVec.getValueType();
23894 if (!isTargetShuffle(InVec.getOpcode()))
23897 // Don't duplicate a load with other uses.
23898 if (!InVec.hasOneUse())
23901 SmallVector<int, 16> ShuffleMask;
23903 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(), true,
23904 ShuffleMask, UnaryShuffle))
23907 // Select the input vector, guarding against out of range extract vector.
23908 unsigned NumElems = CurrentVT.getVectorNumElements();
23909 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23910 int Idx = (Elt > (int)NumElems) ? SM_SentinelUndef : ShuffleMask[Elt];
23912 if (Idx == SM_SentinelZero)
23913 return EltVT.isInteger() ? DAG.getConstant(0, SDLoc(N), EltVT)
23914 : DAG.getConstantFP(+0.0, SDLoc(N), EltVT);
23915 if (Idx == SM_SentinelUndef)
23916 return DAG.getUNDEF(EltVT);
23918 assert(0 <= Idx && Idx < (int)(2 * NumElems) && "Shuffle index out of range");
23919 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23920 : InVec.getOperand(1);
23922 // If inputs to shuffle are the same for both ops, then allow 2 uses
23923 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23924 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23926 if (LdNode.getOpcode() == ISD::BITCAST) {
23927 // Don't duplicate a load with other uses.
23928 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23931 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23932 LdNode = LdNode.getOperand(0);
23935 if (!ISD::isNormalLoad(LdNode.getNode()))
23938 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23940 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23943 // If there's a bitcast before the shuffle, check if the load type and
23944 // alignment is valid.
23945 unsigned Align = LN0->getAlignment();
23946 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23947 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23948 EltVT.getTypeForEVT(*DAG.getContext()));
23950 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23953 // All checks match so transform back to vector_shuffle so that DAG combiner
23954 // can finish the job
23957 // Create shuffle node taking into account the case that its a unary shuffle
23958 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23959 : InVec.getOperand(1);
23960 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23961 InVec.getOperand(0), Shuffle,
23963 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23964 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23968 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23969 const X86Subtarget *Subtarget) {
23970 SDValue N0 = N->getOperand(0);
23971 EVT VT = N->getValueType(0);
23973 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23974 // special and don't usually play with other vector types, it's better to
23975 // handle them early to be sure we emit efficient code by avoiding
23976 // store-load conversions.
23977 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23978 N0.getValueType() == MVT::v2i32 &&
23979 isNullConstant(N0.getOperand(1))) {
23980 SDValue N00 = N0->getOperand(0);
23981 if (N00.getValueType() == MVT::i32)
23982 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23985 // Convert a bitcasted integer logic operation that has one bitcasted
23986 // floating-point operand and one constant operand into a floating-point
23987 // logic operation. This may create a load of the constant, but that is
23988 // cheaper than materializing the constant in an integer register and
23989 // transferring it to an SSE register or transferring the SSE operand to
23990 // integer register and back.
23992 switch (N0.getOpcode()) {
23993 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23994 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23995 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23996 default: return SDValue();
23998 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23999 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
24000 isa<ConstantSDNode>(N0.getOperand(1)) &&
24001 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
24002 N0.getOperand(0).getOperand(0).getValueType() == VT) {
24003 SDValue N000 = N0.getOperand(0).getOperand(0);
24004 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
24005 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
24011 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
24012 /// generation and convert it from being a bunch of shuffles and extracts
24013 /// into a somewhat faster sequence. For i686, the best sequence is apparently
24014 /// storing the value and loading scalars back, while for x64 we should
24015 /// use 64-bit extracts and shifts.
24016 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
24017 TargetLowering::DAGCombinerInfo &DCI) {
24018 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
24021 SDValue InputVector = N->getOperand(0);
24022 SDLoc dl(InputVector);
24023 // Detect mmx to i32 conversion through a v2i32 elt extract.
24024 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
24025 N->getValueType(0) == MVT::i32 &&
24026 InputVector.getValueType() == MVT::v2i32) {
24028 // The bitcast source is a direct mmx result.
24029 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
24030 if (MMXSrc.getValueType() == MVT::x86mmx)
24031 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
24032 N->getValueType(0),
24033 InputVector.getNode()->getOperand(0));
24035 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
24036 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
24037 MMXSrc.getValueType() == MVT::i64) {
24038 SDValue MMXSrcOp = MMXSrc.getOperand(0);
24039 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
24040 MMXSrcOp.getValueType() == MVT::v1i64 &&
24041 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
24042 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
24043 N->getValueType(0), MMXSrcOp.getOperand(0));
24047 EVT VT = N->getValueType(0);
24049 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
24050 InputVector.getOpcode() == ISD::BITCAST &&
24051 isa<ConstantSDNode>(InputVector.getOperand(0))) {
24052 uint64_t ExtractedElt =
24053 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
24054 uint64_t InputValue =
24055 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
24056 uint64_t Res = (InputValue >> ExtractedElt) & 1;
24057 return DAG.getConstant(Res, dl, MVT::i1);
24059 // Only operate on vectors of 4 elements, where the alternative shuffling
24060 // gets to be more expensive.
24061 if (InputVector.getValueType() != MVT::v4i32)
24064 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
24065 // single use which is a sign-extend or zero-extend, and all elements are
24067 SmallVector<SDNode *, 4> Uses;
24068 unsigned ExtractedElements = 0;
24069 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
24070 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
24071 if (UI.getUse().getResNo() != InputVector.getResNo())
24074 SDNode *Extract = *UI;
24075 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
24078 if (Extract->getValueType(0) != MVT::i32)
24080 if (!Extract->hasOneUse())
24082 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
24083 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
24085 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
24088 // Record which element was extracted.
24089 ExtractedElements |=
24090 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
24092 Uses.push_back(Extract);
24095 // If not all the elements were used, this may not be worthwhile.
24096 if (ExtractedElements != 15)
24099 // Ok, we've now decided to do the transformation.
24100 // If 64-bit shifts are legal, use the extract-shift sequence,
24101 // otherwise bounce the vector off the cache.
24102 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24105 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
24106 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
24107 auto &DL = DAG.getDataLayout();
24108 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
24109 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
24110 DAG.getConstant(0, dl, VecIdxTy));
24111 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
24112 DAG.getConstant(1, dl, VecIdxTy));
24114 SDValue ShAmt = DAG.getConstant(
24115 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
24116 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
24117 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
24118 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
24119 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
24120 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
24121 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
24123 // Store the value to a temporary stack slot.
24124 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
24125 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
24126 MachinePointerInfo(), false, false, 0);
24128 EVT ElementType = InputVector.getValueType().getVectorElementType();
24129 unsigned EltSize = ElementType.getSizeInBits() / 8;
24131 // Replace each use (extract) with a load of the appropriate element.
24132 for (unsigned i = 0; i < 4; ++i) {
24133 uint64_t Offset = EltSize * i;
24134 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
24135 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
24137 SDValue ScalarAddr =
24138 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
24140 // Load the scalar.
24141 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
24142 ScalarAddr, MachinePointerInfo(),
24143 false, false, false, 0);
24148 // Replace the extracts
24149 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
24150 UE = Uses.end(); UI != UE; ++UI) {
24151 SDNode *Extract = *UI;
24153 SDValue Idx = Extract->getOperand(1);
24154 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
24155 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
24158 // The replacement was made in place; don't return anything.
24163 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
24164 const X86Subtarget *Subtarget) {
24166 SDValue Cond = N->getOperand(0);
24167 SDValue LHS = N->getOperand(1);
24168 SDValue RHS = N->getOperand(2);
24170 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
24171 SDValue CondSrc = Cond->getOperand(0);
24172 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
24173 Cond = CondSrc->getOperand(0);
24176 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
24179 // A vselect where all conditions and data are constants can be optimized into
24180 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
24181 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
24182 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
24185 unsigned MaskValue = 0;
24186 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
24189 MVT VT = N->getSimpleValueType(0);
24190 unsigned NumElems = VT.getVectorNumElements();
24191 SmallVector<int, 8> ShuffleMask(NumElems, -1);
24192 for (unsigned i = 0; i < NumElems; ++i) {
24193 // Be sure we emit undef where we can.
24194 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
24195 ShuffleMask[i] = -1;
24197 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
24200 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24201 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
24203 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
24206 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
24208 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
24209 TargetLowering::DAGCombinerInfo &DCI,
24210 const X86Subtarget *Subtarget) {
24212 SDValue Cond = N->getOperand(0);
24213 // Get the LHS/RHS of the select.
24214 SDValue LHS = N->getOperand(1);
24215 SDValue RHS = N->getOperand(2);
24216 EVT VT = LHS.getValueType();
24217 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24219 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
24220 // instructions match the semantics of the common C idiom x<y?x:y but not
24221 // x<=y?x:y, because of how they handle negative zero (which can be
24222 // ignored in unsafe-math mode).
24223 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
24224 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
24225 VT != MVT::f80 && VT != MVT::f128 &&
24226 (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
24227 (Subtarget->hasSSE2() ||
24228 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
24229 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24231 unsigned Opcode = 0;
24232 // Check for x CC y ? x : y.
24233 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24234 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24238 // Converting this to a min would handle NaNs incorrectly, and swapping
24239 // the operands would cause it to handle comparisons between positive
24240 // and negative zero incorrectly.
24241 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
24242 if (!DAG.getTarget().Options.UnsafeFPMath &&
24243 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
24245 std::swap(LHS, RHS);
24247 Opcode = X86ISD::FMIN;
24250 // Converting this to a min would handle comparisons between positive
24251 // and negative zero incorrectly.
24252 if (!DAG.getTarget().Options.UnsafeFPMath &&
24253 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
24255 Opcode = X86ISD::FMIN;
24258 // Converting this to a min would handle both negative zeros and NaNs
24259 // incorrectly, but we can swap the operands to fix both.
24260 std::swap(LHS, RHS);
24264 Opcode = X86ISD::FMIN;
24268 // Converting this to a max would handle comparisons between positive
24269 // and negative zero incorrectly.
24270 if (!DAG.getTarget().Options.UnsafeFPMath &&
24271 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
24273 Opcode = X86ISD::FMAX;
24276 // Converting this to a max would handle NaNs incorrectly, and swapping
24277 // the operands would cause it to handle comparisons between positive
24278 // and negative zero incorrectly.
24279 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
24280 if (!DAG.getTarget().Options.UnsafeFPMath &&
24281 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
24283 std::swap(LHS, RHS);
24285 Opcode = X86ISD::FMAX;
24288 // Converting this to a max would handle both negative zeros and NaNs
24289 // incorrectly, but we can swap the operands to fix both.
24290 std::swap(LHS, RHS);
24294 Opcode = X86ISD::FMAX;
24297 // Check for x CC y ? y : x -- a min/max with reversed arms.
24298 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
24299 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
24303 // Converting this to a min would handle comparisons between positive
24304 // and negative zero incorrectly, and swapping the operands would
24305 // cause it to handle NaNs incorrectly.
24306 if (!DAG.getTarget().Options.UnsafeFPMath &&
24307 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
24308 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24310 std::swap(LHS, RHS);
24312 Opcode = X86ISD::FMIN;
24315 // Converting this to a min would handle NaNs incorrectly.
24316 if (!DAG.getTarget().Options.UnsafeFPMath &&
24317 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
24319 Opcode = X86ISD::FMIN;
24322 // Converting this to a min would handle both negative zeros and NaNs
24323 // incorrectly, but we can swap the operands to fix both.
24324 std::swap(LHS, RHS);
24328 Opcode = X86ISD::FMIN;
24332 // Converting this to a max would handle NaNs incorrectly.
24333 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24335 Opcode = X86ISD::FMAX;
24338 // Converting this to a max would handle comparisons between positive
24339 // and negative zero incorrectly, and swapping the operands would
24340 // cause it to handle NaNs incorrectly.
24341 if (!DAG.getTarget().Options.UnsafeFPMath &&
24342 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
24343 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
24345 std::swap(LHS, RHS);
24347 Opcode = X86ISD::FMAX;
24350 // Converting this to a max would handle both negative zeros and NaNs
24351 // incorrectly, but we can swap the operands to fix both.
24352 std::swap(LHS, RHS);
24356 Opcode = X86ISD::FMAX;
24362 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
24365 EVT CondVT = Cond.getValueType();
24366 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
24367 CondVT.getVectorElementType() == MVT::i1) {
24368 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
24369 // lowering on KNL. In this case we convert it to
24370 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
24371 // The same situation for all 128 and 256-bit vectors of i8 and i16.
24372 // Since SKX these selects have a proper lowering.
24373 EVT OpVT = LHS.getValueType();
24374 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
24375 (OpVT.getVectorElementType() == MVT::i8 ||
24376 OpVT.getVectorElementType() == MVT::i16) &&
24377 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
24378 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
24379 DCI.AddToWorklist(Cond.getNode());
24380 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
24383 // If this is a select between two integer constants, try to do some
24385 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
24386 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
24387 // Don't do this for crazy integer types.
24388 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
24389 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
24390 // so that TrueC (the true value) is larger than FalseC.
24391 bool NeedsCondInvert = false;
24393 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
24394 // Efficiently invertible.
24395 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
24396 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
24397 isa<ConstantSDNode>(Cond.getOperand(1))))) {
24398 NeedsCondInvert = true;
24399 std::swap(TrueC, FalseC);
24402 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
24403 if (FalseC->getAPIntValue() == 0 &&
24404 TrueC->getAPIntValue().isPowerOf2()) {
24405 if (NeedsCondInvert) // Invert the condition if needed.
24406 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24407 DAG.getConstant(1, DL, Cond.getValueType()));
24409 // Zero extend the condition if needed.
24410 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
24412 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24413 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
24414 DAG.getConstant(ShAmt, DL, MVT::i8));
24417 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
24418 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24419 if (NeedsCondInvert) // Invert the condition if needed.
24420 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24421 DAG.getConstant(1, DL, Cond.getValueType()));
24423 // Zero extend the condition if needed.
24424 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24425 FalseC->getValueType(0), Cond);
24426 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24427 SDValue(FalseC, 0));
24430 // Optimize cases that will turn into an LEA instruction. This requires
24431 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24432 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24433 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24434 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24436 bool isFastMultiplier = false;
24438 switch ((unsigned char)Diff) {
24440 case 1: // result = add base, cond
24441 case 2: // result = lea base( , cond*2)
24442 case 3: // result = lea base(cond, cond*2)
24443 case 4: // result = lea base( , cond*4)
24444 case 5: // result = lea base(cond, cond*4)
24445 case 8: // result = lea base( , cond*8)
24446 case 9: // result = lea base(cond, cond*8)
24447 isFastMultiplier = true;
24452 if (isFastMultiplier) {
24453 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24454 if (NeedsCondInvert) // Invert the condition if needed.
24455 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
24456 DAG.getConstant(1, DL, Cond.getValueType()));
24458 // Zero extend the condition if needed.
24459 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24461 // Scale the condition by the difference.
24463 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24464 DAG.getConstant(Diff, DL,
24465 Cond.getValueType()));
24467 // Add the base if non-zero.
24468 if (FalseC->getAPIntValue() != 0)
24469 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24470 SDValue(FalseC, 0));
24477 // Canonicalize max and min:
24478 // (x > y) ? x : y -> (x >= y) ? x : y
24479 // (x < y) ? x : y -> (x <= y) ? x : y
24480 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
24481 // the need for an extra compare
24482 // against zero. e.g.
24483 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
24485 // testl %edi, %edi
24487 // cmovgl %edi, %eax
24491 // cmovsl %eax, %edi
24492 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
24493 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
24494 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
24495 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24500 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
24501 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
24502 Cond.getOperand(0), Cond.getOperand(1), NewCC);
24503 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
24508 // Early exit check
24509 if (!TLI.isTypeLegal(VT))
24512 // Match VSELECTs into subs with unsigned saturation.
24513 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
24514 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
24515 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
24516 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
24517 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
24519 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
24520 // left side invert the predicate to simplify logic below.
24522 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
24524 CC = ISD::getSetCCInverse(CC, true);
24525 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
24529 if (Other.getNode() && Other->getNumOperands() == 2 &&
24530 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
24531 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
24532 SDValue CondRHS = Cond->getOperand(1);
24534 // Look for a general sub with unsigned saturation first.
24535 // x >= y ? x-y : 0 --> subus x, y
24536 // x > y ? x-y : 0 --> subus x, y
24537 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
24538 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
24539 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
24541 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
24542 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
24543 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
24544 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
24545 // If the RHS is a constant we have to reverse the const
24546 // canonicalization.
24547 // x > C-1 ? x+-C : 0 --> subus x, C
24548 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
24549 CondRHSConst->getAPIntValue() ==
24550 (-OpRHSConst->getAPIntValue() - 1))
24551 return DAG.getNode(
24552 X86ISD::SUBUS, DL, VT, OpLHS,
24553 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
24555 // Another special case: If C was a sign bit, the sub has been
24556 // canonicalized into a xor.
24557 // FIXME: Would it be better to use computeKnownBits to determine
24558 // whether it's safe to decanonicalize the xor?
24559 // x s< 0 ? x^C : 0 --> subus x, C
24560 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
24561 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
24562 OpRHSConst->getAPIntValue().isSignBit())
24563 // Note that we have to rebuild the RHS constant here to ensure we
24564 // don't rely on particular values of undef lanes.
24565 return DAG.getNode(
24566 X86ISD::SUBUS, DL, VT, OpLHS,
24567 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24572 // Simplify vector selection if condition value type matches vselect
24574 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24575 assert(Cond.getValueType().isVector() &&
24576 "vector select expects a vector selector!");
24578 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24579 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24581 // Try invert the condition if true value is not all 1s and false value
24583 if (!TValIsAllOnes && !FValIsAllZeros &&
24584 // Check if the selector will be produced by CMPP*/PCMP*
24585 Cond.getOpcode() == ISD::SETCC &&
24586 // Check if SETCC has already been promoted
24587 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24589 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24590 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24592 if (TValIsAllZeros || FValIsAllOnes) {
24593 SDValue CC = Cond.getOperand(2);
24594 ISD::CondCode NewCC =
24595 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24596 Cond.getOperand(0).getValueType().isInteger());
24597 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24598 std::swap(LHS, RHS);
24599 TValIsAllOnes = FValIsAllOnes;
24600 FValIsAllZeros = TValIsAllZeros;
24604 if (TValIsAllOnes || FValIsAllZeros) {
24607 if (TValIsAllOnes && FValIsAllZeros)
24609 else if (TValIsAllOnes)
24611 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24612 else if (FValIsAllZeros)
24613 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24614 DAG.getBitcast(CondVT, LHS));
24616 return DAG.getBitcast(VT, Ret);
24620 // We should generate an X86ISD::BLENDI from a vselect if its argument
24621 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24622 // constants. This specific pattern gets generated when we split a
24623 // selector for a 512 bit vector in a machine without AVX512 (but with
24624 // 256-bit vectors), during legalization:
24626 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24628 // Iff we find this pattern and the build_vectors are built from
24629 // constants, we translate the vselect into a shuffle_vector that we
24630 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24631 if ((N->getOpcode() == ISD::VSELECT ||
24632 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24633 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24634 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24635 if (Shuffle.getNode())
24639 // If this is a *dynamic* select (non-constant condition) and we can match
24640 // this node with one of the variable blend instructions, restructure the
24641 // condition so that the blends can use the high bit of each element and use
24642 // SimplifyDemandedBits to simplify the condition operand.
24643 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24644 !DCI.isBeforeLegalize() &&
24645 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24646 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24648 // Don't optimize vector selects that map to mask-registers.
24652 // We can only handle the cases where VSELECT is directly legal on the
24653 // subtarget. We custom lower VSELECT nodes with constant conditions and
24654 // this makes it hard to see whether a dynamic VSELECT will correctly
24655 // lower, so we both check the operation's status and explicitly handle the
24656 // cases where a *dynamic* blend will fail even though a constant-condition
24657 // blend could be custom lowered.
24658 // FIXME: We should find a better way to handle this class of problems.
24659 // Potentially, we should combine constant-condition vselect nodes
24660 // pre-legalization into shuffles and not mark as many types as custom
24662 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24664 // FIXME: We don't support i16-element blends currently. We could and
24665 // should support them by making *all* the bits in the condition be set
24666 // rather than just the high bit and using an i8-element blend.
24667 if (VT.getVectorElementType() == MVT::i16)
24669 // Dynamic blending was only available from SSE4.1 onward.
24670 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24672 // Byte blends are only available in AVX2
24673 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24676 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24677 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24679 APInt KnownZero, KnownOne;
24680 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24681 DCI.isBeforeLegalizeOps());
24682 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24683 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24685 // If we changed the computation somewhere in the DAG, this change
24686 // will affect all users of Cond.
24687 // Make sure it is fine and update all the nodes so that we do not
24688 // use the generic VSELECT anymore. Otherwise, we may perform
24689 // wrong optimizations as we messed up with the actual expectation
24690 // for the vector boolean values.
24691 if (Cond != TLO.Old) {
24692 // Check all uses of that condition operand to check whether it will be
24693 // consumed by non-BLEND instructions, which may depend on all bits are
24695 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24697 if (I->getOpcode() != ISD::VSELECT)
24698 // TODO: Add other opcodes eventually lowered into BLEND.
24701 // Update all the users of the condition, before committing the change,
24702 // so that the VSELECT optimizations that expect the correct vector
24703 // boolean value will not be triggered.
24704 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24706 DAG.ReplaceAllUsesOfValueWith(
24708 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24709 Cond, I->getOperand(1), I->getOperand(2)));
24710 DCI.CommitTargetLoweringOpt(TLO);
24713 // At this point, only Cond is changed. Change the condition
24714 // just for N to keep the opportunity to optimize all other
24715 // users their own way.
24716 DAG.ReplaceAllUsesOfValueWith(
24718 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24719 TLO.New, N->getOperand(1), N->getOperand(2)));
24727 // Check whether a boolean test is testing a boolean value generated by
24728 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24731 // Simplify the following patterns:
24732 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24733 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24734 // to (Op EFLAGS Cond)
24736 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24737 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24738 // to (Op EFLAGS !Cond)
24740 // where Op could be BRCOND or CMOV.
24742 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24743 // Quit if not CMP and SUB with its value result used.
24744 if (Cmp.getOpcode() != X86ISD::CMP &&
24745 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24748 // Quit if not used as a boolean value.
24749 if (CC != X86::COND_E && CC != X86::COND_NE)
24752 // Check CMP operands. One of them should be 0 or 1 and the other should be
24753 // an SetCC or extended from it.
24754 SDValue Op1 = Cmp.getOperand(0);
24755 SDValue Op2 = Cmp.getOperand(1);
24758 const ConstantSDNode* C = nullptr;
24759 bool needOppositeCond = (CC == X86::COND_E);
24760 bool checkAgainstTrue = false; // Is it a comparison against 1?
24762 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24764 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24766 else // Quit if all operands are not constants.
24769 if (C->getZExtValue() == 1) {
24770 needOppositeCond = !needOppositeCond;
24771 checkAgainstTrue = true;
24772 } else if (C->getZExtValue() != 0)
24773 // Quit if the constant is neither 0 or 1.
24776 bool truncatedToBoolWithAnd = false;
24777 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24778 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24779 SetCC.getOpcode() == ISD::TRUNCATE ||
24780 SetCC.getOpcode() == ISD::AND) {
24781 if (SetCC.getOpcode() == ISD::AND) {
24783 if (isOneConstant(SetCC.getOperand(0)))
24785 if (isOneConstant(SetCC.getOperand(1)))
24789 SetCC = SetCC.getOperand(OpIdx);
24790 truncatedToBoolWithAnd = true;
24792 SetCC = SetCC.getOperand(0);
24795 switch (SetCC.getOpcode()) {
24796 case X86ISD::SETCC_CARRY:
24797 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24798 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24799 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24800 // truncated to i1 using 'and'.
24801 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24803 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24804 "Invalid use of SETCC_CARRY!");
24806 case X86ISD::SETCC:
24807 // Set the condition code or opposite one if necessary.
24808 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24809 if (needOppositeCond)
24810 CC = X86::GetOppositeBranchCondition(CC);
24811 return SetCC.getOperand(1);
24812 case X86ISD::CMOV: {
24813 // Check whether false/true value has canonical one, i.e. 0 or 1.
24814 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24815 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24816 // Quit if true value is not a constant.
24819 // Quit if false value is not a constant.
24821 SDValue Op = SetCC.getOperand(0);
24822 // Skip 'zext' or 'trunc' node.
24823 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24824 Op.getOpcode() == ISD::TRUNCATE)
24825 Op = Op.getOperand(0);
24826 // A special case for rdrand/rdseed, where 0 is set if false cond is
24828 if ((Op.getOpcode() != X86ISD::RDRAND &&
24829 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24832 // Quit if false value is not the constant 0 or 1.
24833 bool FValIsFalse = true;
24834 if (FVal && FVal->getZExtValue() != 0) {
24835 if (FVal->getZExtValue() != 1)
24837 // If FVal is 1, opposite cond is needed.
24838 needOppositeCond = !needOppositeCond;
24839 FValIsFalse = false;
24841 // Quit if TVal is not the constant opposite of FVal.
24842 if (FValIsFalse && TVal->getZExtValue() != 1)
24844 if (!FValIsFalse && TVal->getZExtValue() != 0)
24846 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24847 if (needOppositeCond)
24848 CC = X86::GetOppositeBranchCondition(CC);
24849 return SetCC.getOperand(3);
24856 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24858 /// (X86or (X86setcc) (X86setcc))
24859 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24860 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24861 X86::CondCode &CC1, SDValue &Flags,
24863 if (Cond->getOpcode() == X86ISD::CMP) {
24864 if (!isNullConstant(Cond->getOperand(1)))
24867 Cond = Cond->getOperand(0);
24872 SDValue SetCC0, SetCC1;
24873 switch (Cond->getOpcode()) {
24874 default: return false;
24881 SetCC0 = Cond->getOperand(0);
24882 SetCC1 = Cond->getOperand(1);
24886 // Make sure we have SETCC nodes, using the same flags value.
24887 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24888 SetCC1.getOpcode() != X86ISD::SETCC ||
24889 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24892 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24893 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24894 Flags = SetCC0->getOperand(1);
24898 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24899 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24900 TargetLowering::DAGCombinerInfo &DCI,
24901 const X86Subtarget *Subtarget) {
24904 // If the flag operand isn't dead, don't touch this CMOV.
24905 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24908 SDValue FalseOp = N->getOperand(0);
24909 SDValue TrueOp = N->getOperand(1);
24910 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24911 SDValue Cond = N->getOperand(3);
24913 if (CC == X86::COND_E || CC == X86::COND_NE) {
24914 switch (Cond.getOpcode()) {
24918 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24919 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24920 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24926 Flags = checkBoolTestSetCCCombine(Cond, CC);
24927 if (Flags.getNode() &&
24928 // Extra check as FCMOV only supports a subset of X86 cond.
24929 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24930 SDValue Ops[] = { FalseOp, TrueOp,
24931 DAG.getConstant(CC, DL, MVT::i8), Flags };
24932 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24935 // If this is a select between two integer constants, try to do some
24936 // optimizations. Note that the operands are ordered the opposite of SELECT
24938 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24939 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24940 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24941 // larger than FalseC (the false value).
24942 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24943 CC = X86::GetOppositeBranchCondition(CC);
24944 std::swap(TrueC, FalseC);
24945 std::swap(TrueOp, FalseOp);
24948 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24949 // This is efficient for any integer data type (including i8/i16) and
24951 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24952 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24953 DAG.getConstant(CC, DL, MVT::i8), Cond);
24955 // Zero extend the condition if needed.
24956 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24958 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24959 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24960 DAG.getConstant(ShAmt, DL, MVT::i8));
24961 if (N->getNumValues() == 2) // Dead flag value?
24962 return DCI.CombineTo(N, Cond, SDValue());
24966 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24967 // for any integer data type, including i8/i16.
24968 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24969 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24970 DAG.getConstant(CC, DL, MVT::i8), Cond);
24972 // Zero extend the condition if needed.
24973 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24974 FalseC->getValueType(0), Cond);
24975 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24976 SDValue(FalseC, 0));
24978 if (N->getNumValues() == 2) // Dead flag value?
24979 return DCI.CombineTo(N, Cond, SDValue());
24983 // Optimize cases that will turn into an LEA instruction. This requires
24984 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24985 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24986 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24987 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24989 bool isFastMultiplier = false;
24991 switch ((unsigned char)Diff) {
24993 case 1: // result = add base, cond
24994 case 2: // result = lea base( , cond*2)
24995 case 3: // result = lea base(cond, cond*2)
24996 case 4: // result = lea base( , cond*4)
24997 case 5: // result = lea base(cond, cond*4)
24998 case 8: // result = lea base( , cond*8)
24999 case 9: // result = lea base(cond, cond*8)
25000 isFastMultiplier = true;
25005 if (isFastMultiplier) {
25006 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
25007 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
25008 DAG.getConstant(CC, DL, MVT::i8), Cond);
25009 // Zero extend the condition if needed.
25010 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
25012 // Scale the condition by the difference.
25014 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
25015 DAG.getConstant(Diff, DL, Cond.getValueType()));
25017 // Add the base if non-zero.
25018 if (FalseC->getAPIntValue() != 0)
25019 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
25020 SDValue(FalseC, 0));
25021 if (N->getNumValues() == 2) // Dead flag value?
25022 return DCI.CombineTo(N, Cond, SDValue());
25029 // Handle these cases:
25030 // (select (x != c), e, c) -> select (x != c), e, x),
25031 // (select (x == c), c, e) -> select (x == c), x, e)
25032 // where the c is an integer constant, and the "select" is the combination
25033 // of CMOV and CMP.
25035 // The rationale for this change is that the conditional-move from a constant
25036 // needs two instructions, however, conditional-move from a register needs
25037 // only one instruction.
25039 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
25040 // some instruction-combining opportunities. This opt needs to be
25041 // postponed as late as possible.
25043 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
25044 // the DCI.xxxx conditions are provided to postpone the optimization as
25045 // late as possible.
25047 ConstantSDNode *CmpAgainst = nullptr;
25048 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
25049 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
25050 !isa<ConstantSDNode>(Cond.getOperand(0))) {
25052 if (CC == X86::COND_NE &&
25053 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
25054 CC = X86::GetOppositeBranchCondition(CC);
25055 std::swap(TrueOp, FalseOp);
25058 if (CC == X86::COND_E &&
25059 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
25060 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
25061 DAG.getConstant(CC, DL, MVT::i8), Cond };
25062 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
25067 // Fold and/or of setcc's to double CMOV:
25068 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
25069 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
25071 // This combine lets us generate:
25072 // cmovcc1 (jcc1 if we don't have CMOV)
25078 // cmovne (jne if we don't have CMOV)
25079 // When we can't use the CMOV instruction, it might increase branch
25081 // When we can use CMOV, or when there is no mispredict, this improves
25082 // throughput and reduces register pressure.
25084 if (CC == X86::COND_NE) {
25086 X86::CondCode CC0, CC1;
25088 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
25090 std::swap(FalseOp, TrueOp);
25091 CC0 = X86::GetOppositeBranchCondition(CC0);
25092 CC1 = X86::GetOppositeBranchCondition(CC1);
25095 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
25097 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
25098 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
25099 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
25100 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
25108 /// PerformMulCombine - Optimize a single multiply with constant into two
25109 /// in order to implement it with two cheaper instructions, e.g.
25110 /// LEA + SHL, LEA + LEA.
25111 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
25112 TargetLowering::DAGCombinerInfo &DCI) {
25113 // An imul is usually smaller than the alternative sequence.
25114 if (DAG.getMachineFunction().getFunction()->optForMinSize())
25117 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
25120 EVT VT = N->getValueType(0);
25121 if (VT != MVT::i64 && VT != MVT::i32)
25124 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
25127 uint64_t MulAmt = C->getZExtValue();
25128 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
25131 uint64_t MulAmt1 = 0;
25132 uint64_t MulAmt2 = 0;
25133 if ((MulAmt % 9) == 0) {
25135 MulAmt2 = MulAmt / 9;
25136 } else if ((MulAmt % 5) == 0) {
25138 MulAmt2 = MulAmt / 5;
25139 } else if ((MulAmt % 3) == 0) {
25141 MulAmt2 = MulAmt / 3;
25147 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
25149 if (isPowerOf2_64(MulAmt2) &&
25150 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
25151 // If second multiplifer is pow2, issue it first. We want the multiply by
25152 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
25154 std::swap(MulAmt1, MulAmt2);
25156 if (isPowerOf2_64(MulAmt1))
25157 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
25158 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
25160 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
25161 DAG.getConstant(MulAmt1, DL, VT));
25163 if (isPowerOf2_64(MulAmt2))
25164 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
25165 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
25167 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
25168 DAG.getConstant(MulAmt2, DL, VT));
25172 assert(MulAmt != 0 && MulAmt != (VT == MVT::i64 ? UINT64_MAX : UINT32_MAX)
25173 && "Both cases that could cause potential overflows should have "
25174 "already been handled.");
25175 if (isPowerOf2_64(MulAmt - 1))
25176 // (mul x, 2^N + 1) => (add (shl x, N), x)
25177 NewMul = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(0),
25178 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
25179 DAG.getConstant(Log2_64(MulAmt - 1), DL,
25182 else if (isPowerOf2_64(MulAmt + 1))
25183 // (mul x, 2^N - 1) => (sub (shl x, N), x)
25184 NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getNode(ISD::SHL, DL, VT,
25186 DAG.getConstant(Log2_64(MulAmt + 1),
25187 DL, MVT::i8)), N->getOperand(0));
25191 // Do not add new nodes to DAG combiner worklist.
25192 DCI.CombineTo(N, NewMul, false);
25197 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
25198 SDValue N0 = N->getOperand(0);
25199 SDValue N1 = N->getOperand(1);
25200 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
25201 EVT VT = N0.getValueType();
25203 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
25204 // since the result of setcc_c is all zero's or all ones.
25205 if (VT.isInteger() && !VT.isVector() &&
25206 N1C && N0.getOpcode() == ISD::AND &&
25207 N0.getOperand(1).getOpcode() == ISD::Constant) {
25208 SDValue N00 = N0.getOperand(0);
25209 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
25210 APInt ShAmt = N1C->getAPIntValue();
25211 Mask = Mask.shl(ShAmt);
25212 bool MaskOK = false;
25213 // We can handle cases concerning bit-widening nodes containing setcc_c if
25214 // we carefully interrogate the mask to make sure we are semantics
25216 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
25217 // of the underlying setcc_c operation if the setcc_c was zero extended.
25218 // Consider the following example:
25219 // zext(setcc_c) -> i32 0x0000FFFF
25220 // c1 -> i32 0x0000FFFF
25221 // c2 -> i32 0x00000001
25222 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
25223 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
25224 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
25226 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
25227 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
25229 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
25230 N00.getOpcode() == ISD::ANY_EXTEND) &&
25231 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
25232 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
25234 if (MaskOK && Mask != 0) {
25236 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
25240 // Hardware support for vector shifts is sparse which makes us scalarize the
25241 // vector operations in many cases. Also, on sandybridge ADD is faster than
25243 // (shl V, 1) -> add V,V
25244 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
25245 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
25246 assert(N0.getValueType().isVector() && "Invalid vector shift type");
25247 // We shift all of the values by one. In many cases we do not have
25248 // hardware support for this operation. This is better expressed as an ADD
25250 if (N1SplatC->getAPIntValue() == 1)
25251 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
25257 static SDValue PerformSRACombine(SDNode *N, SelectionDAG &DAG) {
25258 SDValue N0 = N->getOperand(0);
25259 SDValue N1 = N->getOperand(1);
25260 EVT VT = N0.getValueType();
25261 unsigned Size = VT.getSizeInBits();
25263 // fold (ashr (shl, a, [56,48,32,24,16]), SarConst)
25264 // into (shl, (sext (a), [56,48,32,24,16] - SarConst)) or
25265 // into (lshr, (sext (a), SarConst - [56,48,32,24,16]))
25266 // depending on sign of (SarConst - [56,48,32,24,16])
25268 // sexts in X86 are MOVs. The MOVs have the same code size
25269 // as above SHIFTs (only SHIFT on 1 has lower code size).
25270 // However the MOVs have 2 advantages to a SHIFT:
25271 // 1. MOVs can write to a register that differs from source
25272 // 2. MOVs accept memory operands
25274 if (!VT.isInteger() || VT.isVector() || N1.getOpcode() != ISD::Constant ||
25275 N0.getOpcode() != ISD::SHL || !N0.hasOneUse() ||
25276 N0.getOperand(1).getOpcode() != ISD::Constant)
25279 SDValue N00 = N0.getOperand(0);
25280 SDValue N01 = N0.getOperand(1);
25281 APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue();
25282 APInt SarConst = (cast<ConstantSDNode>(N1))->getAPIntValue();
25283 EVT CVT = N1.getValueType();
25285 if (SarConst.isNegative())
25288 for (MVT SVT : MVT::integer_valuetypes()) {
25289 unsigned ShiftSize = SVT.getSizeInBits();
25290 // skipping types without corresponding sext/zext and
25291 // ShlConst that is not one of [56,48,32,24,16]
25292 if (ShiftSize < 8 || ShiftSize > 64 || ShlConst != Size - ShiftSize)
25296 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N00, DAG.getValueType(SVT));
25297 SarConst = SarConst - (Size - ShiftSize);
25300 else if (SarConst.isNegative())
25301 return DAG.getNode(ISD::SHL, DL, VT, NN,
25302 DAG.getConstant(-SarConst, DL, CVT));
25304 return DAG.getNode(ISD::SRA, DL, VT, NN,
25305 DAG.getConstant(SarConst, DL, CVT));
25310 /// \brief Returns a vector of 0s if the node in input is a vector logical
25311 /// shift by a constant amount which is known to be bigger than or equal
25312 /// to the vector element size in bits.
25313 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
25314 const X86Subtarget *Subtarget) {
25315 EVT VT = N->getValueType(0);
25317 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
25318 (!Subtarget->hasInt256() ||
25319 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
25322 SDValue Amt = N->getOperand(1);
25324 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
25325 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
25326 APInt ShiftAmt = AmtSplat->getAPIntValue();
25327 unsigned MaxAmount =
25328 VT.getSimpleVT().getVectorElementType().getSizeInBits();
25330 // SSE2/AVX2 logical shifts always return a vector of 0s
25331 // if the shift amount is bigger than or equal to
25332 // the element size. The constant shift amount will be
25333 // encoded as a 8-bit immediate.
25334 if (ShiftAmt.trunc(8).uge(MaxAmount))
25335 return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, DL);
25341 /// PerformShiftCombine - Combine shifts.
25342 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
25343 TargetLowering::DAGCombinerInfo &DCI,
25344 const X86Subtarget *Subtarget) {
25345 if (N->getOpcode() == ISD::SHL)
25346 if (SDValue V = PerformSHLCombine(N, DAG))
25349 if (N->getOpcode() == ISD::SRA)
25350 if (SDValue V = PerformSRACombine(N, DAG))
25353 // Try to fold this logical shift into a zero vector.
25354 if (N->getOpcode() != ISD::SRA)
25355 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
25361 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
25362 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
25363 // and friends. Likewise for OR -> CMPNEQSS.
25364 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
25365 TargetLowering::DAGCombinerInfo &DCI,
25366 const X86Subtarget *Subtarget) {
25369 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
25370 // we're requiring SSE2 for both.
25371 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
25372 SDValue N0 = N->getOperand(0);
25373 SDValue N1 = N->getOperand(1);
25374 SDValue CMP0 = N0->getOperand(1);
25375 SDValue CMP1 = N1->getOperand(1);
25378 // The SETCCs should both refer to the same CMP.
25379 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
25382 SDValue CMP00 = CMP0->getOperand(0);
25383 SDValue CMP01 = CMP0->getOperand(1);
25384 EVT VT = CMP00.getValueType();
25386 if (VT == MVT::f32 || VT == MVT::f64) {
25387 bool ExpectingFlags = false;
25388 // Check for any users that want flags:
25389 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
25390 !ExpectingFlags && UI != UE; ++UI)
25391 switch (UI->getOpcode()) {
25396 ExpectingFlags = true;
25398 case ISD::CopyToReg:
25399 case ISD::SIGN_EXTEND:
25400 case ISD::ZERO_EXTEND:
25401 case ISD::ANY_EXTEND:
25405 if (!ExpectingFlags) {
25406 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
25407 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
25409 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
25410 X86::CondCode tmp = cc0;
25415 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
25416 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
25417 // FIXME: need symbolic constants for these magic numbers.
25418 // See X86ATTInstPrinter.cpp:printSSECC().
25419 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
25420 if (Subtarget->hasAVX512()) {
25421 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
25423 DAG.getConstant(x86cc, DL, MVT::i8));
25424 if (N->getValueType(0) != MVT::i1)
25425 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
25429 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
25430 CMP00.getValueType(), CMP00, CMP01,
25431 DAG.getConstant(x86cc, DL,
25434 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
25435 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
25437 if (is64BitFP && !Subtarget->is64Bit()) {
25438 // On a 32-bit target, we cannot bitcast the 64-bit float to a
25439 // 64-bit integer, since that's not a legal type. Since
25440 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
25441 // bits, but can do this little dance to extract the lowest 32 bits
25442 // and work with those going forward.
25443 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
25445 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
25446 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
25447 Vector32, DAG.getIntPtrConstant(0, DL));
25451 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
25452 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
25453 DAG.getConstant(1, DL, IntVT));
25454 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
25456 return OneBitOfTruth;
25464 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
25465 /// so it can be folded inside ANDNP.
25466 static bool CanFoldXORWithAllOnes(const SDNode *N) {
25467 EVT VT = N->getValueType(0);
25469 // Match direct AllOnes for 128 and 256-bit vectors
25470 if (ISD::isBuildVectorAllOnes(N))
25473 // Look through a bit convert.
25474 if (N->getOpcode() == ISD::BITCAST)
25475 N = N->getOperand(0).getNode();
25477 // Sometimes the operand may come from a insert_subvector building a 256-bit
25479 if (VT.is256BitVector() &&
25480 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
25481 SDValue V1 = N->getOperand(0);
25482 SDValue V2 = N->getOperand(1);
25484 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
25485 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
25486 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
25487 ISD::isBuildVectorAllOnes(V2.getNode()))
25494 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
25495 // register. In most cases we actually compare or select YMM-sized registers
25496 // and mixing the two types creates horrible code. This method optimizes
25497 // some of the transition sequences.
25498 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
25499 TargetLowering::DAGCombinerInfo &DCI,
25500 const X86Subtarget *Subtarget) {
25501 EVT VT = N->getValueType(0);
25502 if (!VT.is256BitVector())
25505 assert((N->getOpcode() == ISD::ANY_EXTEND ||
25506 N->getOpcode() == ISD::ZERO_EXTEND ||
25507 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
25509 SDValue Narrow = N->getOperand(0);
25510 EVT NarrowVT = Narrow->getValueType(0);
25511 if (!NarrowVT.is128BitVector())
25514 if (Narrow->getOpcode() != ISD::XOR &&
25515 Narrow->getOpcode() != ISD::AND &&
25516 Narrow->getOpcode() != ISD::OR)
25519 SDValue N0 = Narrow->getOperand(0);
25520 SDValue N1 = Narrow->getOperand(1);
25523 // The Left side has to be a trunc.
25524 if (N0.getOpcode() != ISD::TRUNCATE)
25527 // The type of the truncated inputs.
25528 EVT WideVT = N0->getOperand(0)->getValueType(0);
25532 // The right side has to be a 'trunc' or a constant vector.
25533 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
25534 ConstantSDNode *RHSConstSplat = nullptr;
25535 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
25536 RHSConstSplat = RHSBV->getConstantSplatNode();
25537 if (!RHSTrunc && !RHSConstSplat)
25540 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25542 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
25545 // Set N0 and N1 to hold the inputs to the new wide operation.
25546 N0 = N0->getOperand(0);
25547 if (RHSConstSplat) {
25548 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
25549 SDValue(RHSConstSplat, 0));
25550 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
25551 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
25552 } else if (RHSTrunc) {
25553 N1 = N1->getOperand(0);
25556 // Generate the wide operation.
25557 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
25558 unsigned Opcode = N->getOpcode();
25560 case ISD::ANY_EXTEND:
25562 case ISD::ZERO_EXTEND: {
25563 unsigned InBits = NarrowVT.getScalarSizeInBits();
25564 APInt Mask = APInt::getAllOnesValue(InBits);
25565 Mask = Mask.zext(VT.getScalarSizeInBits());
25566 return DAG.getNode(ISD::AND, DL, VT,
25567 Op, DAG.getConstant(Mask, DL, VT));
25569 case ISD::SIGN_EXTEND:
25570 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
25571 Op, DAG.getValueType(NarrowVT));
25573 llvm_unreachable("Unexpected opcode");
25577 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
25578 TargetLowering::DAGCombinerInfo &DCI,
25579 const X86Subtarget *Subtarget) {
25580 SDValue N0 = N->getOperand(0);
25581 SDValue N1 = N->getOperand(1);
25584 // A vector zext_in_reg may be represented as a shuffle,
25585 // feeding into a bitcast (this represents anyext) feeding into
25586 // an and with a mask.
25587 // We'd like to try to combine that into a shuffle with zero
25588 // plus a bitcast, removing the and.
25589 if (N0.getOpcode() != ISD::BITCAST ||
25590 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
25593 // The other side of the AND should be a splat of 2^C, where C
25594 // is the number of bits in the source type.
25595 if (N1.getOpcode() == ISD::BITCAST)
25596 N1 = N1.getOperand(0);
25597 if (N1.getOpcode() != ISD::BUILD_VECTOR)
25599 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
25601 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
25602 EVT SrcType = Shuffle->getValueType(0);
25604 // We expect a single-source shuffle
25605 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
25608 unsigned SrcSize = SrcType.getScalarSizeInBits();
25610 APInt SplatValue, SplatUndef;
25611 unsigned SplatBitSize;
25613 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
25614 SplatBitSize, HasAnyUndefs))
25617 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
25618 // Make sure the splat matches the mask we expect
25619 if (SplatBitSize > ResSize ||
25620 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
25623 // Make sure the input and output size make sense
25624 if (SrcSize >= ResSize || ResSize % SrcSize)
25627 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
25628 // The number of u's between each two values depends on the ratio between
25629 // the source and dest type.
25630 unsigned ZextRatio = ResSize / SrcSize;
25631 bool IsZext = true;
25632 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
25633 if (i % ZextRatio) {
25634 if (Shuffle->getMaskElt(i) > 0) {
25640 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
25641 // Expected element number
25651 // Ok, perform the transformation - replace the shuffle with
25652 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25653 // (instead of undef) where the k elements come from the zero vector.
25654 SmallVector<int, 8> Mask;
25655 unsigned NumElems = SrcType.getVectorNumElements();
25656 for (unsigned i = 0; i < NumElems; ++i)
25658 Mask.push_back(NumElems);
25660 Mask.push_back(i / ZextRatio);
25662 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25663 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25664 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25667 /// If both input operands of a logic op are being cast from floating point
25668 /// types, try to convert this into a floating point logic node to avoid
25669 /// unnecessary moves from SSE to integer registers.
25670 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25671 const X86Subtarget *Subtarget) {
25672 unsigned FPOpcode = ISD::DELETED_NODE;
25673 if (N->getOpcode() == ISD::AND)
25674 FPOpcode = X86ISD::FAND;
25675 else if (N->getOpcode() == ISD::OR)
25676 FPOpcode = X86ISD::FOR;
25677 else if (N->getOpcode() == ISD::XOR)
25678 FPOpcode = X86ISD::FXOR;
25680 assert(FPOpcode != ISD::DELETED_NODE &&
25681 "Unexpected input node for FP logic conversion");
25683 EVT VT = N->getValueType(0);
25684 SDValue N0 = N->getOperand(0);
25685 SDValue N1 = N->getOperand(1);
25687 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25688 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25689 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25690 SDValue N00 = N0.getOperand(0);
25691 SDValue N10 = N1.getOperand(0);
25692 EVT N00Type = N00.getValueType();
25693 EVT N10Type = N10.getValueType();
25694 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25695 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25696 return DAG.getBitcast(VT, FPLogic);
25702 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25703 TargetLowering::DAGCombinerInfo &DCI,
25704 const X86Subtarget *Subtarget) {
25705 if (DCI.isBeforeLegalizeOps())
25708 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25711 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25714 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25717 EVT VT = N->getValueType(0);
25718 SDValue N0 = N->getOperand(0);
25719 SDValue N1 = N->getOperand(1);
25722 // Create BEXTR instructions
25723 // BEXTR is ((X >> imm) & (2**size-1))
25724 if (VT == MVT::i32 || VT == MVT::i64) {
25725 // Check for BEXTR.
25726 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25727 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25728 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25729 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25730 if (MaskNode && ShiftNode) {
25731 uint64_t Mask = MaskNode->getZExtValue();
25732 uint64_t Shift = ShiftNode->getZExtValue();
25733 if (isMask_64(Mask)) {
25734 uint64_t MaskSize = countPopulation(Mask);
25735 if (Shift + MaskSize <= VT.getSizeInBits())
25736 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25737 DAG.getConstant(Shift | (MaskSize << 8), DL,
25746 // Want to form ANDNP nodes:
25747 // 1) In the hopes of then easily combining them with OR and AND nodes
25748 // to form PBLEND/PSIGN.
25749 // 2) To match ANDN packed intrinsics
25750 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25753 // Check LHS for vnot
25754 if (N0.getOpcode() == ISD::XOR &&
25755 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25756 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25757 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25759 // Check RHS for vnot
25760 if (N1.getOpcode() == ISD::XOR &&
25761 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25762 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25763 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25768 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25769 TargetLowering::DAGCombinerInfo &DCI,
25770 const X86Subtarget *Subtarget) {
25771 if (DCI.isBeforeLegalizeOps())
25774 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25777 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25780 SDValue N0 = N->getOperand(0);
25781 SDValue N1 = N->getOperand(1);
25782 EVT VT = N->getValueType(0);
25784 // look for psign/blend
25785 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25786 if (!Subtarget->hasSSSE3() ||
25787 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25790 // Canonicalize pandn to RHS
25791 if (N0.getOpcode() == X86ISD::ANDNP)
25793 // or (and (m, y), (pandn m, x))
25794 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25795 SDValue Mask = N1.getOperand(0);
25796 SDValue X = N1.getOperand(1);
25798 if (N0.getOperand(0) == Mask)
25799 Y = N0.getOperand(1);
25800 if (N0.getOperand(1) == Mask)
25801 Y = N0.getOperand(0);
25803 // Check to see if the mask appeared in both the AND and ANDNP and
25807 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25808 // Look through mask bitcast.
25809 if (Mask.getOpcode() == ISD::BITCAST)
25810 Mask = Mask.getOperand(0);
25811 if (X.getOpcode() == ISD::BITCAST)
25812 X = X.getOperand(0);
25813 if (Y.getOpcode() == ISD::BITCAST)
25814 Y = Y.getOperand(0);
25816 EVT MaskVT = Mask.getValueType();
25818 // Validate that the Mask operand is a vector sra node.
25819 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25820 // there is no psrai.b
25821 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25822 unsigned SraAmt = ~0;
25823 if (Mask.getOpcode() == ISD::SRA) {
25824 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25825 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25826 SraAmt = AmtConst->getZExtValue();
25827 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25828 SDValue SraC = Mask.getOperand(1);
25829 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25831 if ((SraAmt + 1) != EltBits)
25836 // Now we know we at least have a plendvb with the mask val. See if
25837 // we can form a psignb/w/d.
25838 // psign = x.type == y.type == mask.type && y = sub(0, x);
25839 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25840 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25841 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25842 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25843 "Unsupported VT for PSIGN");
25844 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25845 return DAG.getBitcast(VT, Mask);
25847 // PBLENDVB only available on SSE 4.1
25848 if (!Subtarget->hasSSE41())
25851 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25853 X = DAG.getBitcast(BlendVT, X);
25854 Y = DAG.getBitcast(BlendVT, Y);
25855 Mask = DAG.getBitcast(BlendVT, Mask);
25856 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25857 return DAG.getBitcast(VT, Mask);
25861 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25864 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25865 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25867 // SHLD/SHRD instructions have lower register pressure, but on some
25868 // platforms they have higher latency than the equivalent
25869 // series of shifts/or that would otherwise be generated.
25870 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25871 // have higher latencies and we are not optimizing for size.
25872 if (!OptForSize && Subtarget->isSHLDSlow())
25875 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25877 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25879 if (!N0.hasOneUse() || !N1.hasOneUse())
25882 SDValue ShAmt0 = N0.getOperand(1);
25883 if (ShAmt0.getValueType() != MVT::i8)
25885 SDValue ShAmt1 = N1.getOperand(1);
25886 if (ShAmt1.getValueType() != MVT::i8)
25888 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25889 ShAmt0 = ShAmt0.getOperand(0);
25890 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25891 ShAmt1 = ShAmt1.getOperand(0);
25894 unsigned Opc = X86ISD::SHLD;
25895 SDValue Op0 = N0.getOperand(0);
25896 SDValue Op1 = N1.getOperand(0);
25897 if (ShAmt0.getOpcode() == ISD::SUB) {
25898 Opc = X86ISD::SHRD;
25899 std::swap(Op0, Op1);
25900 std::swap(ShAmt0, ShAmt1);
25903 unsigned Bits = VT.getSizeInBits();
25904 if (ShAmt1.getOpcode() == ISD::SUB) {
25905 SDValue Sum = ShAmt1.getOperand(0);
25906 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25907 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25908 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25909 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25910 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25911 return DAG.getNode(Opc, DL, VT,
25913 DAG.getNode(ISD::TRUNCATE, DL,
25916 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25917 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25919 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25920 return DAG.getNode(Opc, DL, VT,
25921 N0.getOperand(0), N1.getOperand(0),
25922 DAG.getNode(ISD::TRUNCATE, DL,
25929 // Generate NEG and CMOV for integer abs.
25930 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25931 EVT VT = N->getValueType(0);
25933 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25934 // 8-bit integer abs to NEG and CMOV.
25935 if (VT.isInteger() && VT.getSizeInBits() == 8)
25938 SDValue N0 = N->getOperand(0);
25939 SDValue N1 = N->getOperand(1);
25942 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25943 // and change it to SUB and CMOV.
25944 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25945 N0.getOpcode() == ISD::ADD &&
25946 N0.getOperand(1) == N1 &&
25947 N1.getOpcode() == ISD::SRA &&
25948 N1.getOperand(0) == N0.getOperand(0))
25949 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25950 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25951 // Generate SUB & CMOV.
25952 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25953 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25955 SDValue Ops[] = { N0.getOperand(0), Neg,
25956 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25957 SDValue(Neg.getNode(), 1) };
25958 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25963 // Try to turn tests against the signbit in the form of:
25964 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25967 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25968 // This is only worth doing if the output type is i8.
25969 if (N->getValueType(0) != MVT::i8)
25972 SDValue N0 = N->getOperand(0);
25973 SDValue N1 = N->getOperand(1);
25975 // We should be performing an xor against a truncated shift.
25976 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25979 // Make sure we are performing an xor against one.
25980 if (!isOneConstant(N1))
25983 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25984 SDValue Shift = N0.getOperand(0);
25985 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25988 // Make sure we are truncating from one of i16, i32 or i64.
25989 EVT ShiftTy = Shift.getValueType();
25990 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25993 // Make sure the shift amount extracts the sign bit.
25994 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25995 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25998 // Create a greater-than comparison against -1.
25999 // N.B. Using SETGE against 0 works but we want a canonical looking
26000 // comparison, using SETGT matches up with what TranslateX86CC.
26002 SDValue ShiftOp = Shift.getOperand(0);
26003 EVT ShiftOpTy = ShiftOp.getValueType();
26004 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
26005 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
26009 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
26010 TargetLowering::DAGCombinerInfo &DCI,
26011 const X86Subtarget *Subtarget) {
26012 if (DCI.isBeforeLegalizeOps())
26015 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
26018 if (Subtarget->hasCMov())
26019 if (SDValue RV = performIntegerAbsCombine(N, DAG))
26022 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
26028 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
26029 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
26030 /// X86ISD::AVG instruction.
26031 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
26032 const X86Subtarget *Subtarget, SDLoc DL) {
26033 if (!VT.isVector() || !VT.isSimple())
26035 EVT InVT = In.getValueType();
26036 unsigned NumElems = VT.getVectorNumElements();
26038 EVT ScalarVT = VT.getVectorElementType();
26039 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
26040 isPowerOf2_32(NumElems)))
26043 // InScalarVT is the intermediate type in AVG pattern and it should be greater
26044 // than the original input type (i8/i16).
26045 EVT InScalarVT = InVT.getVectorElementType();
26046 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
26049 if (Subtarget->hasAVX512()) {
26050 if (VT.getSizeInBits() > 512)
26052 } else if (Subtarget->hasAVX2()) {
26053 if (VT.getSizeInBits() > 256)
26056 if (VT.getSizeInBits() > 128)
26060 // Detect the following pattern:
26062 // %1 = zext <N x i8> %a to <N x i32>
26063 // %2 = zext <N x i8> %b to <N x i32>
26064 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
26065 // %4 = add nuw nsw <N x i32> %3, %2
26066 // %5 = lshr <N x i32> %N, <i32 1 x N>
26067 // %6 = trunc <N x i32> %5 to <N x i8>
26069 // In AVX512, the last instruction can also be a trunc store.
26071 if (In.getOpcode() != ISD::SRL)
26074 // A lambda checking the given SDValue is a constant vector and each element
26075 // is in the range [Min, Max].
26076 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
26077 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
26078 if (!BV || !BV->isConstant())
26080 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
26081 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
26084 uint64_t Val = C->getZExtValue();
26085 if (Val < Min || Val > Max)
26091 // Check if each element of the vector is left-shifted by one.
26092 auto LHS = In.getOperand(0);
26093 auto RHS = In.getOperand(1);
26094 if (!IsConstVectorInRange(RHS, 1, 1))
26096 if (LHS.getOpcode() != ISD::ADD)
26099 // Detect a pattern of a + b + 1 where the order doesn't matter.
26100 SDValue Operands[3];
26101 Operands[0] = LHS.getOperand(0);
26102 Operands[1] = LHS.getOperand(1);
26104 // Take care of the case when one of the operands is a constant vector whose
26105 // element is in the range [1, 256].
26106 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
26107 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
26108 Operands[0].getOperand(0).getValueType() == VT) {
26109 // The pattern is detected. Subtract one from the constant vector, then
26110 // demote it and emit X86ISD::AVG instruction.
26111 SDValue One = DAG.getConstant(1, DL, InScalarVT);
26112 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
26113 SmallVector<SDValue, 8>(NumElems, One));
26114 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
26115 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
26116 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
26120 if (Operands[0].getOpcode() == ISD::ADD)
26121 std::swap(Operands[0], Operands[1]);
26122 else if (Operands[1].getOpcode() != ISD::ADD)
26124 Operands[2] = Operands[1].getOperand(0);
26125 Operands[1] = Operands[1].getOperand(1);
26127 // Now we have three operands of two additions. Check that one of them is a
26128 // constant vector with ones, and the other two are promoted from i8/i16.
26129 for (int i = 0; i < 3; ++i) {
26130 if (!IsConstVectorInRange(Operands[i], 1, 1))
26132 std::swap(Operands[i], Operands[2]);
26134 // Check if Operands[0] and Operands[1] are results of type promotion.
26135 for (int j = 0; j < 2; ++j)
26136 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
26137 Operands[j].getOperand(0).getValueType() != VT)
26140 // The pattern is detected, emit X86ISD::AVG instruction.
26141 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
26142 Operands[1].getOperand(0));
26148 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
26149 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
26150 TargetLowering::DAGCombinerInfo &DCI,
26151 const X86Subtarget *Subtarget) {
26152 LoadSDNode *Ld = cast<LoadSDNode>(N);
26153 EVT RegVT = Ld->getValueType(0);
26154 EVT MemVT = Ld->getMemoryVT();
26156 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26158 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
26159 // into two 16-byte operations.
26160 ISD::LoadExtType Ext = Ld->getExtensionType();
26162 unsigned AddressSpace = Ld->getAddressSpace();
26163 unsigned Alignment = Ld->getAlignment();
26164 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
26165 Ext == ISD::NON_EXTLOAD &&
26166 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
26167 AddressSpace, Alignment, &Fast) && !Fast) {
26168 unsigned NumElems = RegVT.getVectorNumElements();
26172 SDValue Ptr = Ld->getBasePtr();
26173 SDValue Increment =
26174 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
26176 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
26178 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
26179 Ld->getPointerInfo(), Ld->isVolatile(),
26180 Ld->isNonTemporal(), Ld->isInvariant(),
26182 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
26183 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
26184 Ld->getPointerInfo(), Ld->isVolatile(),
26185 Ld->isNonTemporal(), Ld->isInvariant(),
26186 std::min(16U, Alignment));
26187 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
26189 Load2.getValue(1));
26191 SDValue NewVec = DAG.getUNDEF(RegVT);
26192 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
26193 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
26194 return DCI.CombineTo(N, NewVec, TF, true);
26200 /// PerformMLOADCombine - Resolve extending loads
26201 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
26202 TargetLowering::DAGCombinerInfo &DCI,
26203 const X86Subtarget *Subtarget) {
26204 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
26205 if (Mld->getExtensionType() != ISD::SEXTLOAD)
26208 EVT VT = Mld->getValueType(0);
26209 unsigned NumElems = VT.getVectorNumElements();
26210 EVT LdVT = Mld->getMemoryVT();
26213 assert(LdVT != VT && "Cannot extend to the same type");
26214 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
26215 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
26216 // From, To sizes and ElemCount must be pow of two
26217 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
26218 "Unexpected size for extending masked load");
26220 unsigned SizeRatio = ToSz / FromSz;
26221 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
26223 // Create a type on which we perform the shuffle
26224 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26225 LdVT.getScalarType(), NumElems*SizeRatio);
26226 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26228 // Convert Src0 value
26229 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
26230 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
26231 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26232 for (unsigned i = 0; i != NumElems; ++i)
26233 ShuffleVec[i] = i * SizeRatio;
26235 // Can't shuffle using an illegal type.
26236 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
26237 "WideVecVT should be legal");
26238 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
26239 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
26241 // Prepare the new mask
26243 SDValue Mask = Mld->getMask();
26244 if (Mask.getValueType() == VT) {
26245 // Mask and original value have the same type
26246 NewMask = DAG.getBitcast(WideVecVT, Mask);
26247 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26248 for (unsigned i = 0; i != NumElems; ++i)
26249 ShuffleVec[i] = i * SizeRatio;
26250 for (unsigned i = NumElems; i != NumElems * SizeRatio; ++i)
26251 ShuffleVec[i] = NumElems * SizeRatio;
26252 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
26253 DAG.getConstant(0, dl, WideVecVT),
26257 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
26258 unsigned WidenNumElts = NumElems*SizeRatio;
26259 unsigned MaskNumElts = VT.getVectorNumElements();
26260 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
26263 unsigned NumConcat = WidenNumElts / MaskNumElts;
26264 SmallVector<SDValue, 16> Ops(NumConcat);
26265 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
26267 for (unsigned i = 1; i != NumConcat; ++i)
26270 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
26273 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
26274 Mld->getBasePtr(), NewMask, WideSrc0,
26275 Mld->getMemoryVT(), Mld->getMemOperand(),
26277 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
26278 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
26280 /// PerformMSTORECombine - Resolve truncating stores
26281 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
26282 const X86Subtarget *Subtarget) {
26283 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
26284 if (!Mst->isTruncatingStore())
26287 EVT VT = Mst->getValue().getValueType();
26288 unsigned NumElems = VT.getVectorNumElements();
26289 EVT StVT = Mst->getMemoryVT();
26292 assert(StVT != VT && "Cannot truncate to the same type");
26293 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
26294 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
26296 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26298 // The truncating store is legal in some cases. For example
26299 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
26300 // are designated for truncate store.
26301 // In this case we don't need any further transformations.
26302 if (TLI.isTruncStoreLegal(VT, StVT))
26305 // From, To sizes and ElemCount must be pow of two
26306 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
26307 "Unexpected size for truncating masked store");
26308 // We are going to use the original vector elt for storing.
26309 // Accumulated smaller vector elements must be a multiple of the store size.
26310 assert (((NumElems * FromSz) % ToSz) == 0 &&
26311 "Unexpected ratio for truncating masked store");
26313 unsigned SizeRatio = FromSz / ToSz;
26314 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
26316 // Create a type on which we perform the shuffle
26317 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26318 StVT.getScalarType(), NumElems*SizeRatio);
26320 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26322 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
26323 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
26324 for (unsigned i = 0; i != NumElems; ++i)
26325 ShuffleVec[i] = i * SizeRatio;
26327 // Can't shuffle using an illegal type.
26328 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
26329 "WideVecVT should be legal");
26331 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
26332 DAG.getUNDEF(WideVecVT),
26336 SDValue Mask = Mst->getMask();
26337 if (Mask.getValueType() == VT) {
26338 // Mask and original value have the same type
26339 NewMask = DAG.getBitcast(WideVecVT, Mask);
26340 for (unsigned i = 0; i != NumElems; ++i)
26341 ShuffleVec[i] = i * SizeRatio;
26342 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
26343 ShuffleVec[i] = NumElems*SizeRatio;
26344 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
26345 DAG.getConstant(0, dl, WideVecVT),
26349 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
26350 unsigned WidenNumElts = NumElems*SizeRatio;
26351 unsigned MaskNumElts = VT.getVectorNumElements();
26352 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
26355 unsigned NumConcat = WidenNumElts / MaskNumElts;
26356 SmallVector<SDValue, 16> Ops(NumConcat);
26357 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
26359 for (unsigned i = 1; i != NumConcat; ++i)
26362 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
26365 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal,
26366 Mst->getBasePtr(), NewMask, StVT,
26367 Mst->getMemOperand(), false);
26369 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
26370 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
26371 const X86Subtarget *Subtarget) {
26372 StoreSDNode *St = cast<StoreSDNode>(N);
26373 EVT VT = St->getValue().getValueType();
26374 EVT StVT = St->getMemoryVT();
26376 SDValue StoredVal = St->getOperand(1);
26377 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26379 // If we are saving a concatenation of two XMM registers and 32-byte stores
26380 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
26382 unsigned AddressSpace = St->getAddressSpace();
26383 unsigned Alignment = St->getAlignment();
26384 if (VT.is256BitVector() && StVT == VT &&
26385 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
26386 AddressSpace, Alignment, &Fast) && !Fast) {
26387 unsigned NumElems = VT.getVectorNumElements();
26391 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
26392 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
26395 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
26396 SDValue Ptr0 = St->getBasePtr();
26397 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
26399 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
26400 St->getPointerInfo(), St->isVolatile(),
26401 St->isNonTemporal(), Alignment);
26402 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
26403 St->getPointerInfo(), St->isVolatile(),
26404 St->isNonTemporal(),
26405 std::min(16U, Alignment));
26406 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
26409 // Optimize trunc store (of multiple scalars) to shuffle and store.
26410 // First, pack all of the elements in one place. Next, store to memory
26411 // in fewer chunks.
26412 if (St->isTruncatingStore() && VT.isVector()) {
26413 // Check if we can detect an AVG pattern from the truncation. If yes,
26414 // replace the trunc store by a normal store with the result of X86ISD::AVG
26417 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
26419 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
26420 St->getPointerInfo(), St->isVolatile(),
26421 St->isNonTemporal(), St->getAlignment());
26423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26424 unsigned NumElems = VT.getVectorNumElements();
26425 assert(StVT != VT && "Cannot truncate to the same type");
26426 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
26427 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
26429 // The truncating store is legal in some cases. For example
26430 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
26431 // are designated for truncate store.
26432 // In this case we don't need any further transformations.
26433 if (TLI.isTruncStoreLegal(VT, StVT))
26436 // From, To sizes and ElemCount must be pow of two
26437 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
26438 // We are going to use the original vector elt for storing.
26439 // Accumulated smaller vector elements must be a multiple of the store size.
26440 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
26442 unsigned SizeRatio = FromSz / ToSz;
26444 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
26446 // Create a type on which we perform the shuffle
26447 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
26448 StVT.getScalarType(), NumElems*SizeRatio);
26450 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
26452 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
26453 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
26454 for (unsigned i = 0; i != NumElems; ++i)
26455 ShuffleVec[i] = i * SizeRatio;
26457 // Can't shuffle using an illegal type.
26458 if (!TLI.isTypeLegal(WideVecVT))
26461 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
26462 DAG.getUNDEF(WideVecVT),
26464 // At this point all of the data is stored at the bottom of the
26465 // register. We now need to save it to mem.
26467 // Find the largest store unit
26468 MVT StoreType = MVT::i8;
26469 for (MVT Tp : MVT::integer_valuetypes()) {
26470 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
26474 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
26475 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
26476 (64 <= NumElems * ToSz))
26477 StoreType = MVT::f64;
26479 // Bitcast the original vector into a vector of store-size units
26480 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
26481 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
26482 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
26483 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
26484 SmallVector<SDValue, 8> Chains;
26485 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
26486 TLI.getPointerTy(DAG.getDataLayout()));
26487 SDValue Ptr = St->getBasePtr();
26489 // Perform one or more big stores into memory.
26490 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
26491 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
26492 StoreType, ShuffWide,
26493 DAG.getIntPtrConstant(i, dl));
26494 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
26495 St->getPointerInfo(), St->isVolatile(),
26496 St->isNonTemporal(), St->getAlignment());
26497 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
26498 Chains.push_back(Ch);
26501 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
26504 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
26505 // the FP state in cases where an emms may be missing.
26506 // A preferable solution to the general problem is to figure out the right
26507 // places to insert EMMS. This qualifies as a quick hack.
26509 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
26510 if (VT.getSizeInBits() != 64)
26513 const Function *F = DAG.getMachineFunction().getFunction();
26514 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
26516 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
26517 if ((VT.isVector() ||
26518 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
26519 isa<LoadSDNode>(St->getValue()) &&
26520 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
26521 St->getChain().hasOneUse() && !St->isVolatile()) {
26522 SDNode* LdVal = St->getValue().getNode();
26523 LoadSDNode *Ld = nullptr;
26524 int TokenFactorIndex = -1;
26525 SmallVector<SDValue, 8> Ops;
26526 SDNode* ChainVal = St->getChain().getNode();
26527 // Must be a store of a load. We currently handle two cases: the load
26528 // is a direct child, and it's under an intervening TokenFactor. It is
26529 // possible to dig deeper under nested TokenFactors.
26530 if (ChainVal == LdVal)
26531 Ld = cast<LoadSDNode>(St->getChain());
26532 else if (St->getValue().hasOneUse() &&
26533 ChainVal->getOpcode() == ISD::TokenFactor) {
26534 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
26535 if (ChainVal->getOperand(i).getNode() == LdVal) {
26536 TokenFactorIndex = i;
26537 Ld = cast<LoadSDNode>(St->getValue());
26539 Ops.push_back(ChainVal->getOperand(i));
26543 if (!Ld || !ISD::isNormalLoad(Ld))
26546 // If this is not the MMX case, i.e. we are just turning i64 load/store
26547 // into f64 load/store, avoid the transformation if there are multiple
26548 // uses of the loaded value.
26549 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
26554 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
26555 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
26557 if (Subtarget->is64Bit() || F64IsLegal) {
26558 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
26559 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
26560 Ld->getPointerInfo(), Ld->isVolatile(),
26561 Ld->isNonTemporal(), Ld->isInvariant(),
26562 Ld->getAlignment());
26563 SDValue NewChain = NewLd.getValue(1);
26564 if (TokenFactorIndex != -1) {
26565 Ops.push_back(NewChain);
26566 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26568 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
26569 St->getPointerInfo(),
26570 St->isVolatile(), St->isNonTemporal(),
26571 St->getAlignment());
26574 // Otherwise, lower to two pairs of 32-bit loads / stores.
26575 SDValue LoAddr = Ld->getBasePtr();
26576 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
26577 DAG.getConstant(4, LdDL, MVT::i32));
26579 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
26580 Ld->getPointerInfo(),
26581 Ld->isVolatile(), Ld->isNonTemporal(),
26582 Ld->isInvariant(), Ld->getAlignment());
26583 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
26584 Ld->getPointerInfo().getWithOffset(4),
26585 Ld->isVolatile(), Ld->isNonTemporal(),
26587 MinAlign(Ld->getAlignment(), 4));
26589 SDValue NewChain = LoLd.getValue(1);
26590 if (TokenFactorIndex != -1) {
26591 Ops.push_back(LoLd);
26592 Ops.push_back(HiLd);
26593 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
26596 LoAddr = St->getBasePtr();
26597 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
26598 DAG.getConstant(4, StDL, MVT::i32));
26600 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
26601 St->getPointerInfo(),
26602 St->isVolatile(), St->isNonTemporal(),
26603 St->getAlignment());
26604 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
26605 St->getPointerInfo().getWithOffset(4),
26607 St->isNonTemporal(),
26608 MinAlign(St->getAlignment(), 4));
26609 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
26612 // This is similar to the above case, but here we handle a scalar 64-bit
26613 // integer store that is extracted from a vector on a 32-bit target.
26614 // If we have SSE2, then we can treat it like a floating-point double
26615 // to get past legalization. The execution dependencies fixup pass will
26616 // choose the optimal machine instruction for the store if this really is
26617 // an integer or v2f32 rather than an f64.
26618 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
26619 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
26620 SDValue OldExtract = St->getOperand(1);
26621 SDValue ExtOp0 = OldExtract.getOperand(0);
26622 unsigned VecSize = ExtOp0.getValueSizeInBits();
26623 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
26624 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
26625 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
26626 BitCast, OldExtract.getOperand(1));
26627 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
26628 St->getPointerInfo(), St->isVolatile(),
26629 St->isNonTemporal(), St->getAlignment());
26635 /// Return 'true' if this vector operation is "horizontal"
26636 /// and return the operands for the horizontal operation in LHS and RHS. A
26637 /// horizontal operation performs the binary operation on successive elements
26638 /// of its first operand, then on successive elements of its second operand,
26639 /// returning the resulting values in a vector. For example, if
26640 /// A = < float a0, float a1, float a2, float a3 >
26642 /// B = < float b0, float b1, float b2, float b3 >
26643 /// then the result of doing a horizontal operation on A and B is
26644 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26645 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26646 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26647 /// set to A, RHS to B, and the routine returns 'true'.
26648 /// Note that the binary operation should have the property that if one of the
26649 /// operands is UNDEF then the result is UNDEF.
26650 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26651 // Look for the following pattern: if
26652 // A = < float a0, float a1, float a2, float a3 >
26653 // B = < float b0, float b1, float b2, float b3 >
26655 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26656 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26657 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26658 // which is A horizontal-op B.
26660 // At least one of the operands should be a vector shuffle.
26661 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26662 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26665 MVT VT = LHS.getSimpleValueType();
26667 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26668 "Unsupported vector type for horizontal add/sub");
26670 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26671 // operate independently on 128-bit lanes.
26672 unsigned NumElts = VT.getVectorNumElements();
26673 unsigned NumLanes = VT.getSizeInBits()/128;
26674 unsigned NumLaneElts = NumElts / NumLanes;
26675 assert((NumLaneElts % 2 == 0) &&
26676 "Vector type should have an even number of elements in each lane");
26677 unsigned HalfLaneElts = NumLaneElts/2;
26679 // View LHS in the form
26680 // LHS = VECTOR_SHUFFLE A, B, LMask
26681 // If LHS is not a shuffle then pretend it is the shuffle
26682 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26683 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26686 SmallVector<int, 16> LMask(NumElts);
26687 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26688 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26689 A = LHS.getOperand(0);
26690 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26691 B = LHS.getOperand(1);
26692 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26693 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26695 if (LHS.getOpcode() != ISD::UNDEF)
26697 for (unsigned i = 0; i != NumElts; ++i)
26701 // Likewise, view RHS in the form
26702 // RHS = VECTOR_SHUFFLE C, D, RMask
26704 SmallVector<int, 16> RMask(NumElts);
26705 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26706 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26707 C = RHS.getOperand(0);
26708 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26709 D = RHS.getOperand(1);
26710 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26711 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26713 if (RHS.getOpcode() != ISD::UNDEF)
26715 for (unsigned i = 0; i != NumElts; ++i)
26719 // Check that the shuffles are both shuffling the same vectors.
26720 if (!(A == C && B == D) && !(A == D && B == C))
26723 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26724 if (!A.getNode() && !B.getNode())
26727 // If A and B occur in reverse order in RHS, then "swap" them (which means
26728 // rewriting the mask).
26730 ShuffleVectorSDNode::commuteMask(RMask);
26732 // At this point LHS and RHS are equivalent to
26733 // LHS = VECTOR_SHUFFLE A, B, LMask
26734 // RHS = VECTOR_SHUFFLE A, B, RMask
26735 // Check that the masks correspond to performing a horizontal operation.
26736 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26737 for (unsigned i = 0; i != NumLaneElts; ++i) {
26738 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26740 // Ignore any UNDEF components.
26741 if (LIdx < 0 || RIdx < 0 ||
26742 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26743 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26746 // Check that successive elements are being operated on. If not, this is
26747 // not a horizontal operation.
26748 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26749 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26750 if (!(LIdx == Index && RIdx == Index + 1) &&
26751 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26756 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26757 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26761 /// Do target-specific dag combines on floating point adds.
26762 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26763 const X86Subtarget *Subtarget) {
26764 EVT VT = N->getValueType(0);
26765 SDValue LHS = N->getOperand(0);
26766 SDValue RHS = N->getOperand(1);
26768 // Try to synthesize horizontal adds from adds of shuffles.
26769 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26770 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26771 isHorizontalBinOp(LHS, RHS, true))
26772 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26776 /// Do target-specific dag combines on floating point subs.
26777 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26778 const X86Subtarget *Subtarget) {
26779 EVT VT = N->getValueType(0);
26780 SDValue LHS = N->getOperand(0);
26781 SDValue RHS = N->getOperand(1);
26783 // Try to synthesize horizontal subs from subs of shuffles.
26784 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26785 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26786 isHorizontalBinOp(LHS, RHS, false))
26787 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26791 /// Truncate a group of v4i32 into v16i8/v8i16 using X86ISD::PACKUS.
26793 combineVectorTruncationWithPACKUS(SDNode *N, SelectionDAG &DAG,
26794 SmallVector<SDValue, 8> &Regs) {
26795 assert(Regs.size() > 0 && (Regs[0].getValueType() == MVT::v4i32 ||
26796 Regs[0].getValueType() == MVT::v2i64));
26797 EVT OutVT = N->getValueType(0);
26798 EVT OutSVT = OutVT.getVectorElementType();
26799 EVT InVT = Regs[0].getValueType();
26800 EVT InSVT = InVT.getVectorElementType();
26803 // First, use mask to unset all bits that won't appear in the result.
26804 assert((OutSVT == MVT::i8 || OutSVT == MVT::i16) &&
26805 "OutSVT can only be either i8 or i16.");
26807 DAG.getConstant(OutSVT == MVT::i8 ? 0xFF : 0xFFFF, DL, InSVT);
26808 SDValue MaskVec = DAG.getNode(
26809 ISD::BUILD_VECTOR, DL, InVT,
26810 SmallVector<SDValue, 8>(InVT.getVectorNumElements(), MaskVal));
26811 for (auto &Reg : Regs)
26812 Reg = DAG.getNode(ISD::AND, DL, InVT, MaskVec, Reg);
26814 MVT UnpackedVT, PackedVT;
26815 if (OutSVT == MVT::i8) {
26816 UnpackedVT = MVT::v8i16;
26817 PackedVT = MVT::v16i8;
26819 UnpackedVT = MVT::v4i32;
26820 PackedVT = MVT::v8i16;
26823 // In each iteration, truncate the type by a half size.
26824 auto RegNum = Regs.size();
26825 for (unsigned j = 1, e = InSVT.getSizeInBits() / OutSVT.getSizeInBits();
26826 j < e; j *= 2, RegNum /= 2) {
26827 for (unsigned i = 0; i < RegNum; i++)
26828 Regs[i] = DAG.getNode(ISD::BITCAST, DL, UnpackedVT, Regs[i]);
26829 for (unsigned i = 0; i < RegNum / 2; i++)
26830 Regs[i] = DAG.getNode(X86ISD::PACKUS, DL, PackedVT, Regs[i * 2],
26834 // If the type of the result is v8i8, we need do one more X86ISD::PACKUS, and
26835 // then extract a subvector as the result since v8i8 is not a legal type.
26836 if (OutVT == MVT::v8i8) {
26837 Regs[0] = DAG.getNode(X86ISD::PACKUS, DL, PackedVT, Regs[0], Regs[0]);
26838 Regs[0] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OutVT, Regs[0],
26839 DAG.getIntPtrConstant(0, DL));
26841 } else if (RegNum > 1) {
26842 Regs.resize(RegNum);
26843 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Regs);
26848 /// Truncate a group of v4i32 into v8i16 using X86ISD::PACKSS.
26850 combineVectorTruncationWithPACKSS(SDNode *N, SelectionDAG &DAG,
26851 SmallVector<SDValue, 8> &Regs) {
26852 assert(Regs.size() > 0 && Regs[0].getValueType() == MVT::v4i32);
26853 EVT OutVT = N->getValueType(0);
26856 // Shift left by 16 bits, then arithmetic-shift right by 16 bits.
26857 SDValue ShAmt = DAG.getConstant(16, DL, MVT::i32);
26858 for (auto &Reg : Regs) {
26859 Reg = getTargetVShiftNode(X86ISD::VSHLI, DL, MVT::v4i32, Reg, ShAmt, DAG);
26860 Reg = getTargetVShiftNode(X86ISD::VSRAI, DL, MVT::v4i32, Reg, ShAmt, DAG);
26863 for (unsigned i = 0, e = Regs.size() / 2; i < e; i++)
26864 Regs[i] = DAG.getNode(X86ISD::PACKSS, DL, MVT::v8i16, Regs[i * 2],
26867 if (Regs.size() > 2) {
26868 Regs.resize(Regs.size() / 2);
26869 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Regs);
26874 /// This function transforms truncation from vXi32/vXi64 to vXi8/vXi16 into
26875 /// X86ISD::PACKUS/X86ISD::PACKSS operations. We do it here because after type
26876 /// legalization the truncation will be translated into a BUILD_VECTOR with each
26877 /// element that is extracted from a vector and then truncated, and it is
26878 /// diffcult to do this optimization based on them.
26879 static SDValue combineVectorTruncation(SDNode *N, SelectionDAG &DAG,
26880 const X86Subtarget *Subtarget) {
26881 EVT OutVT = N->getValueType(0);
26882 if (!OutVT.isVector())
26885 SDValue In = N->getOperand(0);
26886 if (!In.getValueType().isSimple())
26889 EVT InVT = In.getValueType();
26890 unsigned NumElems = OutVT.getVectorNumElements();
26892 // TODO: On AVX2, the behavior of X86ISD::PACKUS is different from that on
26893 // SSE2, and we need to take care of it specially.
26894 // AVX512 provides vpmovdb.
26895 if (!Subtarget->hasSSE2() || Subtarget->hasAVX2())
26898 EVT OutSVT = OutVT.getVectorElementType();
26899 EVT InSVT = InVT.getVectorElementType();
26900 if (!((InSVT == MVT::i32 || InSVT == MVT::i64) &&
26901 (OutSVT == MVT::i8 || OutSVT == MVT::i16) && isPowerOf2_32(NumElems) &&
26905 // SSSE3's pshufb results in less instructions in the cases below.
26906 if (Subtarget->hasSSSE3() && NumElems == 8 &&
26907 ((OutSVT == MVT::i8 && InSVT != MVT::i64) ||
26908 (InSVT == MVT::i32 && OutSVT == MVT::i16)))
26913 // Split a long vector into vectors of legal type.
26914 unsigned RegNum = InVT.getSizeInBits() / 128;
26915 SmallVector<SDValue, 8> SubVec(RegNum);
26916 if (InSVT == MVT::i32) {
26917 for (unsigned i = 0; i < RegNum; i++)
26918 SubVec[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
26919 DAG.getIntPtrConstant(i * 4, DL));
26921 for (unsigned i = 0; i < RegNum; i++)
26922 SubVec[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
26923 DAG.getIntPtrConstant(i * 2, DL));
26926 // SSE2 provides PACKUS for only 2 x v8i16 -> v16i8 and SSE4.1 provides PAKCUS
26927 // for 2 x v4i32 -> v8i16. For SSSE3 and below, we need to use PACKSS to
26928 // truncate 2 x v4i32 to v8i16.
26929 if (Subtarget->hasSSE41() || OutSVT == MVT::i8)
26930 return combineVectorTruncationWithPACKUS(N, DAG, SubVec);
26931 else if (InSVT == MVT::i32)
26932 return combineVectorTruncationWithPACKSS(N, DAG, SubVec);
26937 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
26938 const X86Subtarget *Subtarget) {
26939 // Try to detect AVG pattern first.
26940 SDValue Avg = detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG,
26941 Subtarget, SDLoc(N));
26945 return combineVectorTruncation(N, DAG, Subtarget);
26948 /// Do target-specific dag combines on floating point negations.
26949 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26950 const X86Subtarget *Subtarget) {
26951 EVT VT = N->getValueType(0);
26952 EVT SVT = VT.getScalarType();
26953 SDValue Arg = N->getOperand(0);
26956 // Let legalize expand this if it isn't a legal type yet.
26957 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26960 // If we're negating a FMUL node on a target with FMA, then we can avoid the
26961 // use of a constant by performing (-0 - A*B) instead.
26962 // FIXME: Check rounding control flags as well once it becomes available.
26963 if (Arg.getOpcode() == ISD::FMUL && (SVT == MVT::f32 || SVT == MVT::f64) &&
26964 Arg->getFlags()->hasNoSignedZeros() && Subtarget->hasAnyFMA()) {
26965 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
26966 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26967 Arg.getOperand(1), Zero);
26970 // If we're negating a FMA node, then we can adjust the
26971 // instruction to include the extra negation.
26972 if (Arg.hasOneUse()) {
26973 switch (Arg.getOpcode()) {
26974 case X86ISD::FMADD:
26975 return DAG.getNode(X86ISD::FNMSUB, DL, VT, Arg.getOperand(0),
26976 Arg.getOperand(1), Arg.getOperand(2));
26977 case X86ISD::FMSUB:
26978 return DAG.getNode(X86ISD::FNMADD, DL, VT, Arg.getOperand(0),
26979 Arg.getOperand(1), Arg.getOperand(2));
26980 case X86ISD::FNMADD:
26981 return DAG.getNode(X86ISD::FMSUB, DL, VT, Arg.getOperand(0),
26982 Arg.getOperand(1), Arg.getOperand(2));
26983 case X86ISD::FNMSUB:
26984 return DAG.getNode(X86ISD::FMADD, DL, VT, Arg.getOperand(0),
26985 Arg.getOperand(1), Arg.getOperand(2));
26991 static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
26992 const X86Subtarget *Subtarget) {
26993 EVT VT = N->getValueType(0);
26994 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26995 // VXORPS, VORPS, VANDPS, VANDNPS are supported only under DQ extention.
26996 // These logic operations may be executed in the integer domain.
26998 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26999 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
27001 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
27002 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
27003 unsigned IntOpcode = 0;
27004 switch (N->getOpcode()) {
27005 default: llvm_unreachable("Unexpected FP logic op");
27006 case X86ISD::FOR: IntOpcode = ISD::OR; break;
27007 case X86ISD::FXOR: IntOpcode = ISD::XOR; break;
27008 case X86ISD::FAND: IntOpcode = ISD::AND; break;
27009 case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;
27011 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
27012 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
27016 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
27017 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
27018 const X86Subtarget *Subtarget) {
27019 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
27021 // F[X]OR(0.0, x) -> x
27022 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
27023 if (C->getValueAPF().isPosZero())
27024 return N->getOperand(1);
27026 // F[X]OR(x, 0.0) -> x
27027 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
27028 if (C->getValueAPF().isPosZero())
27029 return N->getOperand(0);
27031 return lowerX86FPLogicOp(N, DAG, Subtarget);
27034 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
27035 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
27036 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
27038 // Only perform optimizations if UnsafeMath is used.
27039 if (!DAG.getTarget().Options.UnsafeFPMath)
27042 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
27043 // into FMINC and FMAXC, which are Commutative operations.
27044 unsigned NewOp = 0;
27045 switch (N->getOpcode()) {
27046 default: llvm_unreachable("unknown opcode");
27047 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
27048 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
27051 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
27052 N->getOperand(0), N->getOperand(1));
27055 static SDValue performFMinNumFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
27056 const X86Subtarget *Subtarget) {
27057 if (Subtarget->useSoftFloat())
27060 // TODO: Check for global or instruction-level "nnan". In that case, we
27061 // should be able to lower to FMAX/FMIN alone.
27062 // TODO: If an operand is already known to be a NaN or not a NaN, this
27063 // should be an optional swap and FMAX/FMIN.
27065 EVT VT = N->getValueType(0);
27066 if (!((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
27067 (Subtarget->hasSSE2() && (VT == MVT::f64 || VT == MVT::v2f64)) ||
27068 (Subtarget->hasAVX() && (VT == MVT::v8f32 || VT == MVT::v4f64))))
27071 // This takes at least 3 instructions, so favor a library call when operating
27072 // on a scalar and minimizing code size.
27073 if (!VT.isVector() && DAG.getMachineFunction().getFunction()->optForMinSize())
27076 SDValue Op0 = N->getOperand(0);
27077 SDValue Op1 = N->getOperand(1);
27079 EVT SetCCType = DAG.getTargetLoweringInfo().getSetCCResultType(
27080 DAG.getDataLayout(), *DAG.getContext(), VT);
27082 // There are 4 possibilities involving NaN inputs, and these are the required
27086 // ----------------
27087 // Num | Max | Op0 |
27088 // Op0 ----------------
27089 // NaN | Op1 | NaN |
27090 // ----------------
27092 // The SSE FP max/min instructions were not designed for this case, but rather
27094 // Min = Op1 < Op0 ? Op1 : Op0
27095 // Max = Op1 > Op0 ? Op1 : Op0
27097 // So they always return Op0 if either input is a NaN. However, we can still
27098 // use those instructions for fmaxnum by selecting away a NaN input.
27100 // If either operand is NaN, the 2nd source operand (Op0) is passed through.
27101 auto MinMaxOp = N->getOpcode() == ISD::FMAXNUM ? X86ISD::FMAX : X86ISD::FMIN;
27102 SDValue MinOrMax = DAG.getNode(MinMaxOp, DL, VT, Op1, Op0);
27103 SDValue IsOp0Nan = DAG.getSetCC(DL, SetCCType , Op0, Op0, ISD::SETUO);
27105 // If Op0 is a NaN, select Op1. Otherwise, select the max. If both operands
27106 // are NaN, the NaN value of Op1 is the result.
27107 auto SelectOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT;
27108 return DAG.getNode(SelectOpcode, DL, VT, IsOp0Nan, Op1, MinOrMax);
27111 /// Do target-specific dag combines on X86ISD::FAND nodes.
27112 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG,
27113 const X86Subtarget *Subtarget) {
27114 // FAND(0.0, x) -> 0.0
27115 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
27116 if (C->getValueAPF().isPosZero())
27117 return N->getOperand(0);
27119 // FAND(x, 0.0) -> 0.0
27120 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
27121 if (C->getValueAPF().isPosZero())
27122 return N->getOperand(1);
27124 return lowerX86FPLogicOp(N, DAG, Subtarget);
27127 /// Do target-specific dag combines on X86ISD::FANDN nodes
27128 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG,
27129 const X86Subtarget *Subtarget) {
27130 // FANDN(0.0, x) -> x
27131 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
27132 if (C->getValueAPF().isPosZero())
27133 return N->getOperand(1);
27135 // FANDN(x, 0.0) -> 0.0
27136 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
27137 if (C->getValueAPF().isPosZero())
27138 return N->getOperand(1);
27140 return lowerX86FPLogicOp(N, DAG, Subtarget);
27143 static SDValue PerformBTCombine(SDNode *N,
27145 TargetLowering::DAGCombinerInfo &DCI) {
27146 // BT ignores high bits in the bit index operand.
27147 SDValue Op1 = N->getOperand(1);
27148 if (Op1.hasOneUse()) {
27149 unsigned BitWidth = Op1.getValueSizeInBits();
27150 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
27151 APInt KnownZero, KnownOne;
27152 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
27153 !DCI.isBeforeLegalizeOps());
27154 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
27155 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
27156 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
27157 DCI.CommitTargetLoweringOpt(TLO);
27162 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
27163 SDValue Op = N->getOperand(0);
27164 if (Op.getOpcode() == ISD::BITCAST)
27165 Op = Op.getOperand(0);
27166 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
27167 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
27168 VT.getVectorElementType().getSizeInBits() ==
27169 OpVT.getVectorElementType().getSizeInBits()) {
27170 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
27175 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
27176 const X86Subtarget *Subtarget) {
27177 EVT VT = N->getValueType(0);
27178 if (!VT.isVector())
27181 SDValue N0 = N->getOperand(0);
27182 SDValue N1 = N->getOperand(1);
27183 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
27186 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
27187 // both SSE and AVX2 since there is no sign-extended shift right
27188 // operation on a vector with 64-bit elements.
27189 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
27190 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
27191 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
27192 N0.getOpcode() == ISD::SIGN_EXTEND)) {
27193 SDValue N00 = N0.getOperand(0);
27195 // EXTLOAD has a better solution on AVX2,
27196 // it may be replaced with X86ISD::VSEXT node.
27197 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
27198 if (!ISD::isNormalLoad(N00.getNode()))
27201 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
27202 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
27204 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
27210 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
27211 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
27212 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
27213 /// eliminate extend, add, and shift instructions.
27214 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
27215 const X86Subtarget *Subtarget) {
27216 // TODO: This should be valid for other integer types.
27217 EVT VT = Sext->getValueType(0);
27218 if (VT != MVT::i64)
27221 // We need an 'add nsw' feeding into the 'sext'.
27222 SDValue Add = Sext->getOperand(0);
27223 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
27226 // Having a constant operand to the 'add' ensures that we are not increasing
27227 // the instruction count because the constant is extended for free below.
27228 // A constant operand can also become the displacement field of an LEA.
27229 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
27233 // Don't make the 'add' bigger if there's no hope of combining it with some
27234 // other 'add' or 'shl' instruction.
27235 // TODO: It may be profitable to generate simpler LEA instructions in place
27236 // of single 'add' instructions, but the cost model for selecting an LEA
27237 // currently has a high threshold.
27238 bool HasLEAPotential = false;
27239 for (auto *User : Sext->uses()) {
27240 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
27241 HasLEAPotential = true;
27245 if (!HasLEAPotential)
27248 // Everything looks good, so pull the 'sext' ahead of the 'add'.
27249 int64_t AddConstant = AddOp1->getSExtValue();
27250 SDValue AddOp0 = Add.getOperand(0);
27251 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
27252 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
27254 // The wider add is guaranteed to not wrap because both operands are
27257 Flags.setNoSignedWrap(true);
27258 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
27261 /// (i8,i32 {s/z}ext ({s/u}divrem (i8 x, i8 y)) ->
27262 /// (i8,i32 ({s/u}divrem_sext_hreg (i8 x, i8 y)
27263 /// This exposes the {s/z}ext to the sdivrem lowering, so that it directly
27264 /// extends from AH (which we otherwise need to do contortions to access).
27265 static SDValue getDivRem8(SDNode *N, SelectionDAG &DAG) {
27266 SDValue N0 = N->getOperand(0);
27267 auto OpcodeN = N->getOpcode();
27268 auto OpcodeN0 = N0.getOpcode();
27269 if (!((OpcodeN == ISD::SIGN_EXTEND && OpcodeN0 == ISD::SDIVREM) ||
27270 (OpcodeN == ISD::ZERO_EXTEND && OpcodeN0 == ISD::UDIVREM)))
27273 EVT VT = N->getValueType(0);
27274 EVT InVT = N0.getValueType();
27275 if (N0.getResNo() != 1 || InVT != MVT::i8 || VT != MVT::i32)
27278 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
27279 auto DivRemOpcode = OpcodeN0 == ISD::SDIVREM ? X86ISD::SDIVREM8_SEXT_HREG
27280 : X86ISD::UDIVREM8_ZEXT_HREG;
27281 SDValue R = DAG.getNode(DivRemOpcode, SDLoc(N), NodeTys, N0.getOperand(0),
27283 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
27284 return R.getValue(1);
27287 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
27288 TargetLowering::DAGCombinerInfo &DCI,
27289 const X86Subtarget *Subtarget) {
27290 SDValue N0 = N->getOperand(0);
27291 EVT VT = N->getValueType(0);
27292 EVT SVT = VT.getScalarType();
27293 EVT InVT = N0.getValueType();
27294 EVT InSVT = InVT.getScalarType();
27297 if (SDValue DivRem8 = getDivRem8(N, DAG))
27300 if (!DCI.isBeforeLegalizeOps()) {
27301 if (InVT == MVT::i1) {
27302 SDValue Zero = DAG.getConstant(0, DL, VT);
27304 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
27305 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
27310 if (VT.isVector() && Subtarget->hasSSE2()) {
27311 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
27312 EVT InVT = N.getValueType();
27313 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
27314 Size / InVT.getScalarSizeInBits());
27315 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
27316 DAG.getUNDEF(InVT));
27318 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
27321 // If target-size is less than 128-bits, extend to a type that would extend
27322 // to 128 bits, extend that and extract the original target vector.
27323 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
27324 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
27325 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
27326 unsigned Scale = 128 / VT.getSizeInBits();
27328 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
27329 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
27330 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
27331 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
27332 DAG.getIntPtrConstant(0, DL));
27335 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
27336 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
27337 if (VT.getSizeInBits() == 128 &&
27338 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
27339 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
27340 SDValue ExOp = ExtendVecSize(DL, N0, 128);
27341 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
27344 // On pre-AVX2 targets, split into 128-bit nodes of
27345 // ISD::SIGN_EXTEND_VECTOR_INREG.
27346 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
27347 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
27348 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
27349 unsigned NumVecs = VT.getSizeInBits() / 128;
27350 unsigned NumSubElts = 128 / SVT.getSizeInBits();
27351 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
27352 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
27354 SmallVector<SDValue, 8> Opnds;
27355 for (unsigned i = 0, Offset = 0; i != NumVecs;
27356 ++i, Offset += NumSubElts) {
27357 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
27358 DAG.getIntPtrConstant(Offset, DL));
27359 SrcVec = ExtendVecSize(DL, SrcVec, 128);
27360 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
27361 Opnds.push_back(SrcVec);
27363 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
27367 if (Subtarget->hasAVX() && VT.is256BitVector())
27368 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
27371 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
27377 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
27378 const X86Subtarget* Subtarget) {
27380 EVT VT = N->getValueType(0);
27382 // Let legalize expand this if it isn't a legal type yet.
27383 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
27386 EVT ScalarVT = VT.getScalarType();
27387 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) || !Subtarget->hasAnyFMA())
27390 SDValue A = N->getOperand(0);
27391 SDValue B = N->getOperand(1);
27392 SDValue C = N->getOperand(2);
27394 bool NegA = (A.getOpcode() == ISD::FNEG);
27395 bool NegB = (B.getOpcode() == ISD::FNEG);
27396 bool NegC = (C.getOpcode() == ISD::FNEG);
27398 // Negative multiplication when NegA xor NegB
27399 bool NegMul = (NegA != NegB);
27401 A = A.getOperand(0);
27403 B = B.getOperand(0);
27405 C = C.getOperand(0);
27409 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
27411 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
27413 return DAG.getNode(Opcode, dl, VT, A, B, C);
27416 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
27417 TargetLowering::DAGCombinerInfo &DCI,
27418 const X86Subtarget *Subtarget) {
27419 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
27420 // (and (i32 x86isd::setcc_carry), 1)
27421 // This eliminates the zext. This transformation is necessary because
27422 // ISD::SETCC is always legalized to i8.
27424 SDValue N0 = N->getOperand(0);
27425 EVT VT = N->getValueType(0);
27427 if (N0.getOpcode() == ISD::AND &&
27429 N0.getOperand(0).hasOneUse()) {
27430 SDValue N00 = N0.getOperand(0);
27431 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27432 if (!isOneConstant(N0.getOperand(1)))
27434 return DAG.getNode(ISD::AND, dl, VT,
27435 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
27436 N00.getOperand(0), N00.getOperand(1)),
27437 DAG.getConstant(1, dl, VT));
27441 if (N0.getOpcode() == ISD::TRUNCATE &&
27443 N0.getOperand(0).hasOneUse()) {
27444 SDValue N00 = N0.getOperand(0);
27445 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
27446 return DAG.getNode(ISD::AND, dl, VT,
27447 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
27448 N00.getOperand(0), N00.getOperand(1)),
27449 DAG.getConstant(1, dl, VT));
27453 if (VT.is256BitVector())
27454 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
27457 if (SDValue DivRem8 = getDivRem8(N, DAG))
27463 // Optimize x == -y --> x+y == 0
27464 // x != -y --> x+y != 0
27465 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
27466 const X86Subtarget* Subtarget) {
27467 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
27468 SDValue LHS = N->getOperand(0);
27469 SDValue RHS = N->getOperand(1);
27470 EVT VT = N->getValueType(0);
27473 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
27474 if (isNullConstant(LHS.getOperand(0)) && LHS.hasOneUse()) {
27475 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
27476 LHS.getOperand(1));
27477 return DAG.getSetCC(DL, N->getValueType(0), addV,
27478 DAG.getConstant(0, DL, addV.getValueType()), CC);
27480 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
27481 if (isNullConstant(RHS.getOperand(0)) && RHS.hasOneUse()) {
27482 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
27483 RHS.getOperand(1));
27484 return DAG.getSetCC(DL, N->getValueType(0), addV,
27485 DAG.getConstant(0, DL, addV.getValueType()), CC);
27488 if (VT.getScalarType() == MVT::i1 &&
27489 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
27491 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27492 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
27493 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
27495 if (!IsSEXT0 || !IsVZero1) {
27496 // Swap the operands and update the condition code.
27497 std::swap(LHS, RHS);
27498 CC = ISD::getSetCCSwappedOperands(CC);
27500 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
27501 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
27502 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
27505 if (IsSEXT0 && IsVZero1) {
27506 assert(VT == LHS.getOperand(0).getValueType() &&
27507 "Uexpected operand type");
27508 if (CC == ISD::SETGT)
27509 return DAG.getConstant(0, DL, VT);
27510 if (CC == ISD::SETLE)
27511 return DAG.getConstant(1, DL, VT);
27512 if (CC == ISD::SETEQ || CC == ISD::SETGE)
27513 return DAG.getNOT(DL, LHS.getOperand(0), VT);
27515 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
27516 "Unexpected condition code!");
27517 return LHS.getOperand(0);
27524 static SDValue PerformGatherScatterCombine(SDNode *N, SelectionDAG &DAG) {
27526 // Gather and Scatter instructions use k-registers for masks. The type of
27527 // the masks is v*i1. So the mask will be truncated anyway.
27528 // The SIGN_EXTEND_INREG my be dropped.
27529 SDValue Mask = N->getOperand(2);
27530 if (Mask.getOpcode() == ISD::SIGN_EXTEND_INREG) {
27531 SmallVector<SDValue, 5> NewOps(N->op_begin(), N->op_end());
27532 NewOps[2] = Mask.getOperand(0);
27533 DAG.UpdateNodeOperands(N, NewOps);
27538 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
27539 // as "sbb reg,reg", since it can be extended without zext and produces
27540 // an all-ones bit which is more useful than 0/1 in some cases.
27541 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
27544 return DAG.getNode(ISD::AND, DL, VT,
27545 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
27546 DAG.getConstant(X86::COND_B, DL, MVT::i8),
27548 DAG.getConstant(1, DL, VT));
27549 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
27550 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
27551 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
27552 DAG.getConstant(X86::COND_B, DL, MVT::i8),
27556 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
27557 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
27558 TargetLowering::DAGCombinerInfo &DCI,
27559 const X86Subtarget *Subtarget) {
27561 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
27562 SDValue EFLAGS = N->getOperand(1);
27564 if (CC == X86::COND_A) {
27565 // Try to convert COND_A into COND_B in an attempt to facilitate
27566 // materializing "setb reg".
27568 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
27569 // cannot take an immediate as its first operand.
27571 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
27572 EFLAGS.getValueType().isInteger() &&
27573 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
27574 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
27575 EFLAGS.getNode()->getVTList(),
27576 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
27577 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
27578 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
27582 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
27583 // a zext and produces an all-ones bit which is more useful than 0/1 in some
27585 if (CC == X86::COND_B)
27586 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
27588 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
27589 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
27590 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
27596 // Optimize branch condition evaluation.
27598 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
27599 TargetLowering::DAGCombinerInfo &DCI,
27600 const X86Subtarget *Subtarget) {
27602 SDValue Chain = N->getOperand(0);
27603 SDValue Dest = N->getOperand(1);
27604 SDValue EFLAGS = N->getOperand(3);
27605 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
27607 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
27608 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
27609 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
27616 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
27617 SelectionDAG &DAG) {
27618 // Take advantage of vector comparisons producing 0 or -1 in each lane to
27619 // optimize away operation when it's from a constant.
27621 // The general transformation is:
27622 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
27623 // AND(VECTOR_CMP(x,y), constant2)
27624 // constant2 = UNARYOP(constant)
27626 // Early exit if this isn't a vector operation, the operand of the
27627 // unary operation isn't a bitwise AND, or if the sizes of the operations
27628 // aren't the same.
27629 EVT VT = N->getValueType(0);
27630 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
27631 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
27632 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
27635 // Now check that the other operand of the AND is a constant. We could
27636 // make the transformation for non-constant splats as well, but it's unclear
27637 // that would be a benefit as it would not eliminate any operations, just
27638 // perform one more step in scalar code before moving to the vector unit.
27639 if (BuildVectorSDNode *BV =
27640 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
27641 // Bail out if the vector isn't a constant.
27642 if (!BV->isConstant())
27645 // Everything checks out. Build up the new and improved node.
27647 EVT IntVT = BV->getValueType(0);
27648 // Create a new constant of the appropriate type for the transformed
27650 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
27651 // The AND node needs bitcasts to/from an integer vector type around it.
27652 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
27653 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
27654 N->getOperand(0)->getOperand(0), MaskConst);
27655 SDValue Res = DAG.getBitcast(VT, NewAnd);
27662 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27663 const X86Subtarget *Subtarget) {
27664 SDValue Op0 = N->getOperand(0);
27665 EVT VT = N->getValueType(0);
27666 EVT InVT = Op0.getValueType();
27667 EVT InSVT = InVT.getScalarType();
27668 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
27670 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
27671 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
27672 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27674 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27675 InVT.getVectorNumElements());
27676 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
27678 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
27679 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
27681 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27687 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
27688 const X86Subtarget *Subtarget) {
27689 // First try to optimize away the conversion entirely when it's
27690 // conditionally from a constant. Vectors only.
27691 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
27694 // Now move on to more general possibilities.
27695 SDValue Op0 = N->getOperand(0);
27696 EVT VT = N->getValueType(0);
27697 EVT InVT = Op0.getValueType();
27698 EVT InSVT = InVT.getScalarType();
27700 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
27701 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
27702 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
27704 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
27705 InVT.getVectorNumElements());
27706 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
27707 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
27710 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
27711 // a 32-bit target where SSE doesn't support i64->FP operations.
27712 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
27713 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
27714 EVT LdVT = Ld->getValueType(0);
27716 // This transformation is not supported if the result type is f16
27717 if (VT == MVT::f16)
27720 if (!Ld->isVolatile() && !VT.isVector() &&
27721 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
27722 !Subtarget->is64Bit() && LdVT == MVT::i64) {
27723 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
27724 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
27725 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
27732 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
27733 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
27734 X86TargetLowering::DAGCombinerInfo &DCI) {
27735 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
27736 // the result is either zero or one (depending on the input carry bit).
27737 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
27738 if (X86::isZeroNode(N->getOperand(0)) &&
27739 X86::isZeroNode(N->getOperand(1)) &&
27740 // We don't have a good way to replace an EFLAGS use, so only do this when
27742 SDValue(N, 1).use_empty()) {
27744 EVT VT = N->getValueType(0);
27745 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
27746 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
27747 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
27748 DAG.getConstant(X86::COND_B, DL,
27751 DAG.getConstant(1, DL, VT));
27752 return DCI.CombineTo(N, Res1, CarryOut);
27758 // fold (add Y, (sete X, 0)) -> adc 0, Y
27759 // (add Y, (setne X, 0)) -> sbb -1, Y
27760 // (sub (sete X, 0), Y) -> sbb 0, Y
27761 // (sub (setne X, 0), Y) -> adc -1, Y
27762 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
27765 // Look through ZExts.
27766 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
27767 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
27770 SDValue SetCC = Ext.getOperand(0);
27771 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
27774 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
27775 if (CC != X86::COND_E && CC != X86::COND_NE)
27778 SDValue Cmp = SetCC.getOperand(1);
27779 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
27780 !X86::isZeroNode(Cmp.getOperand(1)) ||
27781 !Cmp.getOperand(0).getValueType().isInteger())
27784 SDValue CmpOp0 = Cmp.getOperand(0);
27785 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
27786 DAG.getConstant(1, DL, CmpOp0.getValueType()));
27788 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
27789 if (CC == X86::COND_NE)
27790 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
27791 DL, OtherVal.getValueType(), OtherVal,
27792 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
27794 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
27795 DL, OtherVal.getValueType(), OtherVal,
27796 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
27799 /// PerformADDCombine - Do target-specific dag combines on integer adds.
27800 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
27801 const X86Subtarget *Subtarget) {
27802 EVT VT = N->getValueType(0);
27803 SDValue Op0 = N->getOperand(0);
27804 SDValue Op1 = N->getOperand(1);
27806 // Try to synthesize horizontal adds from adds of shuffles.
27807 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27808 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27809 isHorizontalBinOp(Op0, Op1, true))
27810 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
27812 return OptimizeConditionalInDecrement(N, DAG);
27815 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
27816 const X86Subtarget *Subtarget) {
27817 SDValue Op0 = N->getOperand(0);
27818 SDValue Op1 = N->getOperand(1);
27820 // X86 can't encode an immediate LHS of a sub. See if we can push the
27821 // negation into a preceding instruction.
27822 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
27823 // If the RHS of the sub is a XOR with one use and a constant, invert the
27824 // immediate. Then add one to the LHS of the sub so we can turn
27825 // X-Y -> X+~Y+1, saving one register.
27826 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
27827 isa<ConstantSDNode>(Op1.getOperand(1))) {
27828 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
27829 EVT VT = Op0.getValueType();
27830 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
27832 DAG.getConstant(~XorC, SDLoc(Op1), VT));
27833 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
27834 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
27838 // Try to synthesize horizontal adds from adds of shuffles.
27839 EVT VT = N->getValueType(0);
27840 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
27841 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
27842 isHorizontalBinOp(Op0, Op1, true))
27843 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
27845 return OptimizeConditionalInDecrement(N, DAG);
27848 /// performVZEXTCombine - Performs build vector combines
27849 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
27850 TargetLowering::DAGCombinerInfo &DCI,
27851 const X86Subtarget *Subtarget) {
27853 MVT VT = N->getSimpleValueType(0);
27854 SDValue Op = N->getOperand(0);
27855 MVT OpVT = Op.getSimpleValueType();
27856 MVT OpEltVT = OpVT.getVectorElementType();
27857 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
27859 // (vzext (bitcast (vzext (x)) -> (vzext x)
27861 while (V.getOpcode() == ISD::BITCAST)
27862 V = V.getOperand(0);
27864 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
27865 MVT InnerVT = V.getSimpleValueType();
27866 MVT InnerEltVT = InnerVT.getVectorElementType();
27868 // If the element sizes match exactly, we can just do one larger vzext. This
27869 // is always an exact type match as vzext operates on integer types.
27870 if (OpEltVT == InnerEltVT) {
27871 assert(OpVT == InnerVT && "Types must match for vzext!");
27872 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
27875 // The only other way we can combine them is if only a single element of the
27876 // inner vzext is used in the input to the outer vzext.
27877 if (InnerEltVT.getSizeInBits() < InputBits)
27880 // In this case, the inner vzext is completely dead because we're going to
27881 // only look at bits inside of the low element. Just do the outer vzext on
27882 // a bitcast of the input to the inner.
27883 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
27886 // Check if we can bypass extracting and re-inserting an element of an input
27887 // vector. Essentially:
27888 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27889 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27890 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27891 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27892 SDValue ExtractedV = V.getOperand(0);
27893 SDValue OrigV = ExtractedV.getOperand(0);
27894 if (isNullConstant(ExtractedV.getOperand(1))) {
27895 MVT OrigVT = OrigV.getSimpleValueType();
27896 // Extract a subvector if necessary...
27897 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27898 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27899 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27900 OrigVT.getVectorNumElements() / Ratio);
27901 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27902 DAG.getIntPtrConstant(0, DL));
27904 Op = DAG.getBitcast(OpVT, OrigV);
27905 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27912 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27913 DAGCombinerInfo &DCI) const {
27914 SelectionDAG &DAG = DCI.DAG;
27915 switch (N->getOpcode()) {
27917 case ISD::EXTRACT_VECTOR_ELT:
27918 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27921 case X86ISD::SHRUNKBLEND:
27922 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27923 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27924 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27925 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27926 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27927 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27928 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27931 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27932 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27933 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27934 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27935 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27936 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27937 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27938 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27939 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27940 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27941 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27942 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27943 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27944 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27946 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27948 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27950 case ISD::FMAXNUM: return performFMinNumFMaxNumCombine(N, DAG,
27952 case X86ISD::FAND: return PerformFANDCombine(N, DAG, Subtarget);
27953 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG, Subtarget);
27954 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27955 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27956 case ISD::ANY_EXTEND:
27957 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27958 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27959 case ISD::SIGN_EXTEND_INREG:
27960 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27961 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27962 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27963 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27964 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27965 case X86ISD::SHUFP: // Handle all target specific shuffles
27966 case X86ISD::PALIGNR:
27967 case X86ISD::BLENDI:
27968 case X86ISD::UNPCKH:
27969 case X86ISD::UNPCKL:
27970 case X86ISD::MOVHLPS:
27971 case X86ISD::MOVLHPS:
27972 case X86ISD::PSHUFB:
27973 case X86ISD::PSHUFD:
27974 case X86ISD::PSHUFHW:
27975 case X86ISD::PSHUFLW:
27976 case X86ISD::MOVSS:
27977 case X86ISD::MOVSD:
27978 case X86ISD::VPERMILPI:
27979 case X86ISD::VPERM2X128:
27980 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27981 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27983 case ISD::MSCATTER: return PerformGatherScatterCombine(N, DAG);
27989 /// isTypeDesirableForOp - Return true if the target has native support for
27990 /// the specified value type and it is 'desirable' to use the type for the
27991 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27992 /// instruction encodings are longer and some i16 instructions are slow.
27993 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27994 if (!isTypeLegal(VT))
27996 if (VT != MVT::i16)
28003 case ISD::SIGN_EXTEND:
28004 case ISD::ZERO_EXTEND:
28005 case ISD::ANY_EXTEND:
28018 /// This function checks if any of the users of EFLAGS copies the EFLAGS. We
28019 /// know that the code that lowers COPY of EFLAGS has to use the stack, and if
28020 /// we don't adjust the stack we clobber the first frame index.
28021 /// See X86InstrInfo::copyPhysReg.
28022 bool X86TargetLowering::hasCopyImplyingStackAdjustment(
28023 MachineFunction *MF) const {
28024 const MachineRegisterInfo &MRI = MF->getRegInfo();
28026 return any_of(MRI.reg_instructions(X86::EFLAGS),
28027 [](const MachineInstr &RI) { return RI.isCopy(); });
28030 /// IsDesirableToPromoteOp - This method query the target whether it is
28031 /// beneficial for dag combiner to promote the specified node. If true, it
28032 /// should return the desired promotion type by reference.
28033 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
28034 EVT VT = Op.getValueType();
28035 if (VT != MVT::i16)
28038 bool Promote = false;
28039 bool Commute = false;
28040 switch (Op.getOpcode()) {
28043 LoadSDNode *LD = cast<LoadSDNode>(Op);
28044 // If the non-extending load has a single use and it's not live out, then it
28045 // might be folded.
28046 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
28047 Op.hasOneUse()*/) {
28048 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
28049 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
28050 // The only case where we'd want to promote LOAD (rather then it being
28051 // promoted as an operand is when it's only use is liveout.
28052 if (UI->getOpcode() != ISD::CopyToReg)
28059 case ISD::SIGN_EXTEND:
28060 case ISD::ZERO_EXTEND:
28061 case ISD::ANY_EXTEND:
28066 SDValue N0 = Op.getOperand(0);
28067 // Look out for (store (shl (load), x)).
28068 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
28081 SDValue N0 = Op.getOperand(0);
28082 SDValue N1 = Op.getOperand(1);
28083 if (!Commute && MayFoldLoad(N1))
28085 // Avoid disabling potential load folding opportunities.
28086 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
28088 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
28098 //===----------------------------------------------------------------------===//
28099 // X86 Inline Assembly Support
28100 //===----------------------------------------------------------------------===//
28102 // Helper to match a string separated by whitespace.
28103 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
28104 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
28106 for (StringRef Piece : Pieces) {
28107 if (!S.startswith(Piece)) // Check if the piece matches.
28110 S = S.substr(Piece.size());
28111 StringRef::size_type Pos = S.find_first_not_of(" \t");
28112 if (Pos == 0) // We matched a prefix.
28121 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
28123 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
28124 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
28125 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
28126 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
28128 if (AsmPieces.size() == 3)
28130 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
28137 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
28138 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
28140 std::string AsmStr = IA->getAsmString();
28142 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
28143 if (!Ty || Ty->getBitWidth() % 16 != 0)
28146 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
28147 SmallVector<StringRef, 4> AsmPieces;
28148 SplitString(AsmStr, AsmPieces, ";\n");
28150 switch (AsmPieces.size()) {
28151 default: return false;
28153 // FIXME: this should verify that we are targeting a 486 or better. If not,
28154 // we will turn this bswap into something that will be lowered to logical
28155 // ops instead of emitting the bswap asm. For now, we don't support 486 or
28156 // lower so don't worry about this.
28158 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
28159 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
28160 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
28161 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
28162 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
28163 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
28164 // No need to check constraints, nothing other than the equivalent of
28165 // "=r,0" would be valid here.
28166 return IntrinsicLowering::LowerToByteSwap(CI);
28169 // rorw $$8, ${0:w} --> llvm.bswap.i16
28170 if (CI->getType()->isIntegerTy(16) &&
28171 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
28172 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
28173 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
28175 StringRef ConstraintsStr = IA->getConstraintString();
28176 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
28177 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
28178 if (clobbersFlagRegisters(AsmPieces))
28179 return IntrinsicLowering::LowerToByteSwap(CI);
28183 if (CI->getType()->isIntegerTy(32) &&
28184 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
28185 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
28186 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
28187 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
28189 StringRef ConstraintsStr = IA->getConstraintString();
28190 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
28191 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
28192 if (clobbersFlagRegisters(AsmPieces))
28193 return IntrinsicLowering::LowerToByteSwap(CI);
28196 if (CI->getType()->isIntegerTy(64)) {
28197 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
28198 if (Constraints.size() >= 2 &&
28199 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
28200 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
28201 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
28202 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
28203 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
28204 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
28205 return IntrinsicLowering::LowerToByteSwap(CI);
28213 /// getConstraintType - Given a constraint letter, return the type of
28214 /// constraint it is for this target.
28215 X86TargetLowering::ConstraintType
28216 X86TargetLowering::getConstraintType(StringRef Constraint) const {
28217 if (Constraint.size() == 1) {
28218 switch (Constraint[0]) {
28229 return C_RegisterClass;
28253 return TargetLowering::getConstraintType(Constraint);
28256 /// Examine constraint type and operand type and determine a weight value.
28257 /// This object must already have been set up with the operand type
28258 /// and the current alternative constraint selected.
28259 TargetLowering::ConstraintWeight
28260 X86TargetLowering::getSingleConstraintMatchWeight(
28261 AsmOperandInfo &info, const char *constraint) const {
28262 ConstraintWeight weight = CW_Invalid;
28263 Value *CallOperandVal = info.CallOperandVal;
28264 // If we don't have a value, we can't do a match,
28265 // but allow it at the lowest weight.
28266 if (!CallOperandVal)
28268 Type *type = CallOperandVal->getType();
28269 // Look at the constraint type.
28270 switch (*constraint) {
28272 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
28283 if (CallOperandVal->getType()->isIntegerTy())
28284 weight = CW_SpecificReg;
28289 if (type->isFloatingPointTy())
28290 weight = CW_SpecificReg;
28293 if (type->isX86_MMXTy() && Subtarget->hasMMX())
28294 weight = CW_SpecificReg;
28298 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
28299 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
28300 weight = CW_Register;
28303 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
28304 if (C->getZExtValue() <= 31)
28305 weight = CW_Constant;
28309 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28310 if (C->getZExtValue() <= 63)
28311 weight = CW_Constant;
28315 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28316 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
28317 weight = CW_Constant;
28321 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28322 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
28323 weight = CW_Constant;
28327 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28328 if (C->getZExtValue() <= 3)
28329 weight = CW_Constant;
28333 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28334 if (C->getZExtValue() <= 0xff)
28335 weight = CW_Constant;
28340 if (isa<ConstantFP>(CallOperandVal)) {
28341 weight = CW_Constant;
28345 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28346 if ((C->getSExtValue() >= -0x80000000LL) &&
28347 (C->getSExtValue() <= 0x7fffffffLL))
28348 weight = CW_Constant;
28352 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
28353 if (C->getZExtValue() <= 0xffffffff)
28354 weight = CW_Constant;
28361 /// LowerXConstraint - try to replace an X constraint, which matches anything,
28362 /// with another that has more specific requirements based on the type of the
28363 /// corresponding operand.
28364 const char *X86TargetLowering::
28365 LowerXConstraint(EVT ConstraintVT) const {
28366 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
28367 // 'f' like normal targets.
28368 if (ConstraintVT.isFloatingPoint()) {
28369 if (Subtarget->hasSSE2())
28371 if (Subtarget->hasSSE1())
28375 return TargetLowering::LowerXConstraint(ConstraintVT);
28378 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
28379 /// vector. If it is invalid, don't add anything to Ops.
28380 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
28381 std::string &Constraint,
28382 std::vector<SDValue>&Ops,
28383 SelectionDAG &DAG) const {
28386 // Only support length 1 constraints for now.
28387 if (Constraint.length() > 1) return;
28389 char ConstraintLetter = Constraint[0];
28390 switch (ConstraintLetter) {
28393 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28394 if (C->getZExtValue() <= 31) {
28395 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28396 Op.getValueType());
28402 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28403 if (C->getZExtValue() <= 63) {
28404 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28405 Op.getValueType());
28411 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28412 if (isInt<8>(C->getSExtValue())) {
28413 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28414 Op.getValueType());
28420 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28421 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
28422 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
28423 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
28424 Op.getValueType());
28430 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28431 if (C->getZExtValue() <= 3) {
28432 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28433 Op.getValueType());
28439 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28440 if (C->getZExtValue() <= 255) {
28441 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28442 Op.getValueType());
28448 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28449 if (C->getZExtValue() <= 127) {
28450 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28451 Op.getValueType());
28457 // 32-bit signed value
28458 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28459 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
28460 C->getSExtValue())) {
28461 // Widen to 64 bits here to get it sign extended.
28462 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
28465 // FIXME gcc accepts some relocatable values here too, but only in certain
28466 // memory models; it's complicated.
28471 // 32-bit unsigned value
28472 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
28473 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
28474 C->getZExtValue())) {
28475 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
28476 Op.getValueType());
28480 // FIXME gcc accepts some relocatable values here too, but only in certain
28481 // memory models; it's complicated.
28485 // Literal immediates are always ok.
28486 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
28487 // Widen to 64 bits here to get it sign extended.
28488 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
28492 // In any sort of PIC mode addresses need to be computed at runtime by
28493 // adding in a register or some sort of table lookup. These can't
28494 // be used as immediates.
28495 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
28498 // If we are in non-pic codegen mode, we allow the address of a global (with
28499 // an optional displacement) to be used with 'i'.
28500 GlobalAddressSDNode *GA = nullptr;
28501 int64_t Offset = 0;
28503 // Match either (GA), (GA+C), (GA+C1+C2), etc.
28505 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
28506 Offset += GA->getOffset();
28508 } else if (Op.getOpcode() == ISD::ADD) {
28509 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
28510 Offset += C->getZExtValue();
28511 Op = Op.getOperand(0);
28514 } else if (Op.getOpcode() == ISD::SUB) {
28515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
28516 Offset += -C->getZExtValue();
28517 Op = Op.getOperand(0);
28522 // Otherwise, this isn't something we can handle, reject it.
28526 const GlobalValue *GV = GA->getGlobal();
28527 // If we require an extra load to get this address, as in PIC mode, we
28528 // can't accept it.
28529 if (isGlobalStubReference(
28530 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
28533 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
28534 GA->getValueType(0), Offset);
28539 if (Result.getNode()) {
28540 Ops.push_back(Result);
28543 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
28546 std::pair<unsigned, const TargetRegisterClass *>
28547 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
28548 StringRef Constraint,
28550 // First, see if this is a constraint that directly corresponds to an LLVM
28552 if (Constraint.size() == 1) {
28553 // GCC Constraint Letters
28554 switch (Constraint[0]) {
28556 // TODO: Slight differences here in allocation order and leaving
28557 // RIP in the class. Do they matter any more here than they do
28558 // in the normal allocation?
28559 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
28560 if (Subtarget->is64Bit()) {
28561 if (VT == MVT::i32 || VT == MVT::f32)
28562 return std::make_pair(0U, &X86::GR32RegClass);
28563 if (VT == MVT::i16)
28564 return std::make_pair(0U, &X86::GR16RegClass);
28565 if (VT == MVT::i8 || VT == MVT::i1)
28566 return std::make_pair(0U, &X86::GR8RegClass);
28567 if (VT == MVT::i64 || VT == MVT::f64)
28568 return std::make_pair(0U, &X86::GR64RegClass);
28571 // 32-bit fallthrough
28572 case 'Q': // Q_REGS
28573 if (VT == MVT::i32 || VT == MVT::f32)
28574 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
28575 if (VT == MVT::i16)
28576 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
28577 if (VT == MVT::i8 || VT == MVT::i1)
28578 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
28579 if (VT == MVT::i64)
28580 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
28582 case 'r': // GENERAL_REGS
28583 case 'l': // INDEX_REGS
28584 if (VT == MVT::i8 || VT == MVT::i1)
28585 return std::make_pair(0U, &X86::GR8RegClass);
28586 if (VT == MVT::i16)
28587 return std::make_pair(0U, &X86::GR16RegClass);
28588 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
28589 return std::make_pair(0U, &X86::GR32RegClass);
28590 return std::make_pair(0U, &X86::GR64RegClass);
28591 case 'R': // LEGACY_REGS
28592 if (VT == MVT::i8 || VT == MVT::i1)
28593 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
28594 if (VT == MVT::i16)
28595 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
28596 if (VT == MVT::i32 || !Subtarget->is64Bit())
28597 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
28598 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
28599 case 'f': // FP Stack registers.
28600 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
28601 // value to the correct fpstack register class.
28602 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
28603 return std::make_pair(0U, &X86::RFP32RegClass);
28604 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
28605 return std::make_pair(0U, &X86::RFP64RegClass);
28606 return std::make_pair(0U, &X86::RFP80RegClass);
28607 case 'y': // MMX_REGS if MMX allowed.
28608 if (!Subtarget->hasMMX()) break;
28609 return std::make_pair(0U, &X86::VR64RegClass);
28610 case 'Y': // SSE_REGS if SSE2 allowed
28611 if (!Subtarget->hasSSE2()) break;
28613 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
28614 if (!Subtarget->hasSSE1()) break;
28616 switch (VT.SimpleTy) {
28618 // Scalar SSE types.
28621 return std::make_pair(0U, &X86::FR32RegClass);
28624 return std::make_pair(0U, &X86::FR64RegClass);
28625 // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
28633 return std::make_pair(0U, &X86::VR128RegClass);
28641 return std::make_pair(0U, &X86::VR256RegClass);
28646 return std::make_pair(0U, &X86::VR512RegClass);
28652 // Use the default implementation in TargetLowering to convert the register
28653 // constraint into a member of a register class.
28654 std::pair<unsigned, const TargetRegisterClass*> Res;
28655 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
28657 // Not found as a standard register?
28659 // Map st(0) -> st(7) -> ST0
28660 if (Constraint.size() == 7 && Constraint[0] == '{' &&
28661 tolower(Constraint[1]) == 's' &&
28662 tolower(Constraint[2]) == 't' &&
28663 Constraint[3] == '(' &&
28664 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
28665 Constraint[5] == ')' &&
28666 Constraint[6] == '}') {
28668 Res.first = X86::FP0+Constraint[4]-'0';
28669 Res.second = &X86::RFP80RegClass;
28673 // GCC allows "st(0)" to be called just plain "st".
28674 if (StringRef("{st}").equals_lower(Constraint)) {
28675 Res.first = X86::FP0;
28676 Res.second = &X86::RFP80RegClass;
28681 if (StringRef("{flags}").equals_lower(Constraint)) {
28682 Res.first = X86::EFLAGS;
28683 Res.second = &X86::CCRRegClass;
28687 // 'A' means EAX + EDX.
28688 if (Constraint == "A") {
28689 Res.first = X86::EAX;
28690 Res.second = &X86::GR32_ADRegClass;
28696 // Otherwise, check to see if this is a register class of the wrong value
28697 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
28698 // turn into {ax},{dx}.
28699 // MVT::Other is used to specify clobber names.
28700 if (Res.second->hasType(VT) || VT == MVT::Other)
28701 return Res; // Correct type already, nothing to do.
28703 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
28704 // return "eax". This should even work for things like getting 64bit integer
28705 // registers when given an f64 type.
28706 const TargetRegisterClass *Class = Res.second;
28707 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
28708 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
28709 unsigned Size = VT.getSizeInBits();
28710 if (Size == 1) Size = 8;
28711 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, Size);
28713 Res.first = DestReg;
28714 Res.second = Size == 8 ? &X86::GR8RegClass
28715 : Size == 16 ? &X86::GR16RegClass
28716 : Size == 32 ? &X86::GR32RegClass
28717 : &X86::GR64RegClass;
28718 assert(Res.second->contains(Res.first) && "Register in register class");
28720 // No register found/type mismatch.
28722 Res.second = nullptr;
28724 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
28725 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
28726 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
28727 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
28728 Class == &X86::VR512RegClass) {
28729 // Handle references to XMM physical registers that got mapped into the
28730 // wrong class. This can happen with constraints like {xmm0} where the
28731 // target independent register mapper will just pick the first match it can
28732 // find, ignoring the required type.
28734 // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
28735 if (VT == MVT::f32 || VT == MVT::i32)
28736 Res.second = &X86::FR32RegClass;
28737 else if (VT == MVT::f64 || VT == MVT::i64)
28738 Res.second = &X86::FR64RegClass;
28739 else if (X86::VR128RegClass.hasType(VT))
28740 Res.second = &X86::VR128RegClass;
28741 else if (X86::VR256RegClass.hasType(VT))
28742 Res.second = &X86::VR256RegClass;
28743 else if (X86::VR512RegClass.hasType(VT))
28744 Res.second = &X86::VR512RegClass;
28746 // Type mismatch and not a clobber: Return an error;
28748 Res.second = nullptr;
28755 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
28756 const AddrMode &AM, Type *Ty,
28757 unsigned AS) const {
28758 // Scaling factors are not free at all.
28759 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
28760 // will take 2 allocations in the out of order engine instead of 1
28761 // for plain addressing mode, i.e. inst (reg1).
28763 // vaddps (%rsi,%drx), %ymm0, %ymm1
28764 // Requires two allocations (one for the load, one for the computation)
28766 // vaddps (%rsi), %ymm0, %ymm1
28767 // Requires just 1 allocation, i.e., freeing allocations for other operations
28768 // and having less micro operations to execute.
28770 // For some X86 architectures, this is even worse because for instance for
28771 // stores, the complex addressing mode forces the instruction to use the
28772 // "load" ports instead of the dedicated "store" port.
28773 // E.g., on Haswell:
28774 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
28775 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
28776 if (isLegalAddressingMode(DL, AM, Ty, AS))
28777 // Scale represents reg2 * scale, thus account for 1
28778 // as soon as we use a second register.
28779 return AM.Scale != 0;
28783 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
28784 // Integer division on x86 is expensive. However, when aggressively optimizing
28785 // for code size, we prefer to use a div instruction, as it is usually smaller
28786 // than the alternative sequence.
28787 // The exception to this is vector division. Since x86 doesn't have vector
28788 // integer division, leaving the division as-is is a loss even in terms of
28789 // size, because it will have to be scalarized, while the alternative code
28790 // sequence can be performed in vector form.
28791 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
28792 Attribute::MinSize);
28793 return OptSize && !VT.isVector();