1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
17 #include "X86InstrBuilder.h"
18 #include "X86ISelLowering.h"
19 #include "X86TargetMachine.h"
20 #include "X86TargetObjectFile.h"
21 #include "Utils/X86ShuffleDecode.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instructions.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/LLVMContext.h"
31 #include "llvm/CodeGen/IntrinsicLowering.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineJumpTableInfo.h"
36 #include "llvm/CodeGen/MachineModuleInfo.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/MC/MCAsmInfo.h"
40 #include "llvm/MC/MCContext.h"
41 #include "llvm/MC/MCExpr.h"
42 #include "llvm/MC/MCSymbol.h"
43 #include "llvm/ADT/BitVector.h"
44 #include "llvm/ADT/SmallSet.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/Support/CallSite.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/Dwarf.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
54 #include "llvm/Target/TargetOptions.h"
56 using namespace dwarf;
58 STATISTIC(NumTailCalls, "Number of tail calls");
60 // Forward declarations.
61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
64 static SDValue Insert128BitVector(SDValue Result,
70 static SDValue Extract128BitVector(SDValue Vec,
75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
76 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
77 /// simple subregister reference. Idx is an index in the 128 bits we
78 /// want. It need not be aligned to a 128-bit bounday. That makes
79 /// lowering EXTRACT_VECTOR_ELT operations easier.
80 static SDValue Extract128BitVector(SDValue Vec,
84 EVT VT = Vec.getValueType();
85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!");
86 EVT ElVT = VT.getVectorElementType();
87 int Factor = VT.getSizeInBits()/128;
88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
89 VT.getVectorNumElements()/Factor);
91 // Extract from UNDEF is UNDEF.
92 if (Vec.getOpcode() == ISD::UNDEF)
93 return DAG.getNode(ISD::UNDEF, dl, ResultVT);
95 if (isa<ConstantSDNode>(Idx)) {
96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
99 // we can match to VEXTRACTF128.
100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
102 // This is the index of the first element of the 128-bit chunk
104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
117 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
118 /// sets things up to match to an AVX VINSERTF128 instruction or a
119 /// simple superregister reference. Idx is an index in the 128 bits
120 /// we want. It need not be aligned to a 128-bit bounday. That makes
121 /// lowering INSERT_VECTOR_ELT operations easier.
122 static SDValue Insert128BitVector(SDValue Result,
127 if (isa<ConstantSDNode>(Idx)) {
128 EVT VT = Vec.getValueType();
129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!");
131 EVT ElVT = VT.getVectorElementType();
132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
133 EVT ResultVT = Result.getValueType();
135 // Insert the relevant 128 bits.
136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
138 // This is the index of the first element of the 128-bit chunk
140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
152 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
154 bool is64Bit = Subtarget->is64Bit();
156 if (Subtarget->isTargetEnvMacho()) {
158 return new X8664_MachoTargetObjectFile();
159 return new TargetLoweringObjectFileMachO();
162 if (Subtarget->isTargetELF())
163 return new TargetLoweringObjectFileELF();
164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
165 return new TargetLoweringObjectFileCOFF();
166 llvm_unreachable("unknown subtarget type");
169 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<X86Subtarget>();
172 X86ScalarSSEf64 = Subtarget->hasXMMInt() || Subtarget->hasAVX();
173 X86ScalarSSEf32 = Subtarget->hasXMM() || Subtarget->hasAVX();
174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
176 RegInfo = TM.getRegisterInfo();
177 TD = getTargetData();
179 // Set up the TargetLowering object.
180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
183 setBooleanContents(ZeroOrOneBooleanContent);
184 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
187 // For 64-bit since we have so many registers use the ILP scheduler, for
188 // 32-bit code use the register pressure specific scheduling.
189 if (Subtarget->is64Bit())
190 setSchedulingPreference(Sched::ILP);
192 setSchedulingPreference(Sched::RegPressure);
193 setStackPointerRegisterToSaveRestore(X86StackPtr);
195 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
196 // Setup Windows compiler runtime calls.
197 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
198 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
199 setLibcallName(RTLIB::SREM_I64, "_allrem");
200 setLibcallName(RTLIB::UREM_I64, "_aullrem");
201 setLibcallName(RTLIB::MUL_I64, "_allmul");
202 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2");
203 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2");
204 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
205 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
206 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
207 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
208 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
209 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C);
210 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C);
213 if (Subtarget->isTargetDarwin()) {
214 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
215 setUseUnderscoreSetJmp(false);
216 setUseUnderscoreLongJmp(false);
217 } else if (Subtarget->isTargetMingw()) {
218 // MS runtime is weird: it exports _setjmp, but longjmp!
219 setUseUnderscoreSetJmp(true);
220 setUseUnderscoreLongJmp(false);
222 setUseUnderscoreSetJmp(true);
223 setUseUnderscoreLongJmp(true);
226 // Set up the register classes.
227 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
228 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
229 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
230 if (Subtarget->is64Bit())
231 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
235 // We don't accept any truncstore of integer registers.
236 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
237 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
239 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
241 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
243 // SETOEQ and SETUNE require checking two conditions.
244 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
247 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
248 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
249 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
253 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
257 if (Subtarget->is64Bit()) {
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
260 } else if (!UseSoftFloat) {
261 // We have an algorithm for SSE2->double, and we turn this into a
262 // 64-bit FILD followed by conditional FADD for other targets.
263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
264 // We have an algorithm for SSE2, and we turn this into a 64-bit
265 // FILD for other targets.
266 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
275 // SSE has no i16 to fp conversion, only i32
276 if (X86ScalarSSEf32) {
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
278 // f32 and f64 cases are Legal, f80 case is not
279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
289 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
290 // are Legal, f80 is custom lowered.
291 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
292 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
294 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
296 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
297 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
299 if (X86ScalarSSEf32) {
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
301 // f32 and f64 cases are Legal, f80 case is not
302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
308 // Handle FP_TO_UINT by promoting the destination to a larger signed
310 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
311 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
314 if (Subtarget->is64Bit()) {
315 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
317 } else if (!UseSoftFloat) {
318 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
319 // Expand FP_TO_UINT into a select.
320 // FIXME: We would like to use a Custom expander here eventually to do
321 // the optimal thing for SSE vs. the default expansion in the legalizer.
322 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
324 // With SSE3 we can use fisttpll to convert to a signed i64; without
325 // SSE, we're stuck with a fistpll.
326 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
329 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
330 if (!X86ScalarSSEf64) {
331 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
332 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
333 if (Subtarget->is64Bit()) {
334 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
335 // Without SSE, i64->f64 goes through memory.
336 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
340 // Scalar integer divide and remainder are lowered to use operations that
341 // produce two results, to match the available instructions. This exposes
342 // the two-result form to trivial CSE, which is able to combine x/y and x%y
343 // into a single instruction.
345 // Scalar integer multiply-high is also lowered to use two-result
346 // operations, to match the available instructions. However, plain multiply
347 // (low) operations are left as Legal, as there are single-result
348 // instructions for this in x86. Using the two-result multiply instructions
349 // when both high and low results are needed must be arranged by dagcombine.
350 for (unsigned i = 0, e = 4; i != e; ++i) {
352 setOperationAction(ISD::MULHS, VT, Expand);
353 setOperationAction(ISD::MULHU, VT, Expand);
354 setOperationAction(ISD::SDIV, VT, Expand);
355 setOperationAction(ISD::UDIV, VT, Expand);
356 setOperationAction(ISD::SREM, VT, Expand);
357 setOperationAction(ISD::UREM, VT, Expand);
359 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
360 setOperationAction(ISD::ADDC, VT, Custom);
361 setOperationAction(ISD::ADDE, VT, Custom);
362 setOperationAction(ISD::SUBC, VT, Custom);
363 setOperationAction(ISD::SUBE, VT, Custom);
366 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
367 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
368 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
369 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
370 if (Subtarget->is64Bit())
371 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
375 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
376 setOperationAction(ISD::FREM , MVT::f32 , Expand);
377 setOperationAction(ISD::FREM , MVT::f64 , Expand);
378 setOperationAction(ISD::FREM , MVT::f80 , Expand);
379 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
381 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
382 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
383 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
384 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
385 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
386 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
387 if (Subtarget->is64Bit()) {
388 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
389 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
392 if (Subtarget->hasPOPCNT()) {
393 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
395 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
396 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
397 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
398 if (Subtarget->is64Bit())
399 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
402 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
403 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
405 // These should be promoted to a larger select which is supported.
406 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
407 // X86 wants to expand cmov itself.
408 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
410 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
413 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
416 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
419 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
424 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
427 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
428 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
429 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
431 if (Subtarget->is64Bit())
432 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
433 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
434 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
435 if (Subtarget->is64Bit()) {
436 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
437 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
438 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
439 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
440 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
442 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
443 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
444 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
446 if (Subtarget->is64Bit()) {
447 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
448 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
452 if (Subtarget->hasXMM())
453 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
455 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // On X86 and X86-64, atomic operations are lowered to locked instructions.
459 // Locked instructions, in turn, have implicit fence semantics (all memory
460 // operations are flushed before issuing the locked instruction, and they
461 // are not buffered), so we can fold away the common pattern of
462 // fence-atomic-fence.
463 setShouldFoldAtomicFences(true);
465 // Expand certain atomics
466 for (unsigned i = 0, e = 4; i != e; ++i) {
468 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
469 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
470 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
473 if (!Subtarget->is64Bit()) {
474 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
475 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
477 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
478 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
479 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
480 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
481 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
484 if (Subtarget->hasCmpxchg16b()) {
485 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
488 // FIXME - use subtarget debug flags
489 if (!Subtarget->isTargetDarwin() &&
490 !Subtarget->isTargetELF() &&
491 !Subtarget->isTargetCygMing()) {
492 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
495 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
496 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
497 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
498 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
499 if (Subtarget->is64Bit()) {
500 setExceptionPointerRegister(X86::RAX);
501 setExceptionSelectorRegister(X86::RDX);
503 setExceptionPointerRegister(X86::EAX);
504 setExceptionSelectorRegister(X86::EDX);
506 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
507 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
509 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
510 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
512 setOperationAction(ISD::TRAP, MVT::Other, Legal);
514 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
515 setOperationAction(ISD::VASTART , MVT::Other, Custom);
516 setOperationAction(ISD::VAEND , MVT::Other, Expand);
517 if (Subtarget->is64Bit()) {
518 setOperationAction(ISD::VAARG , MVT::Other, Custom);
519 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
521 setOperationAction(ISD::VAARG , MVT::Other, Expand);
522 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
525 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
526 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
528 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
529 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
530 MVT::i64 : MVT::i32, Custom);
531 else if (EnableSegmentedStacks)
532 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
533 MVT::i64 : MVT::i32, Custom);
535 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
536 MVT::i64 : MVT::i32, Expand);
538 if (!UseSoftFloat && X86ScalarSSEf64) {
539 // f32 and f64 use SSE.
540 // Set up the FP register classes.
541 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
542 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
544 // Use ANDPD to simulate FABS.
545 setOperationAction(ISD::FABS , MVT::f64, Custom);
546 setOperationAction(ISD::FABS , MVT::f32, Custom);
548 // Use XORP to simulate FNEG.
549 setOperationAction(ISD::FNEG , MVT::f64, Custom);
550 setOperationAction(ISD::FNEG , MVT::f32, Custom);
552 // Use ANDPD and ORPD to simulate FCOPYSIGN.
553 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
554 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
556 // Lower this to FGETSIGNx86 plus an AND.
557 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
558 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
560 // We don't support sin/cos/fmod
561 setOperationAction(ISD::FSIN , MVT::f64, Expand);
562 setOperationAction(ISD::FCOS , MVT::f64, Expand);
563 setOperationAction(ISD::FSIN , MVT::f32, Expand);
564 setOperationAction(ISD::FCOS , MVT::f32, Expand);
566 // Expand FP immediates into loads from the stack, except for the special
568 addLegalFPImmediate(APFloat(+0.0)); // xorpd
569 addLegalFPImmediate(APFloat(+0.0f)); // xorps
570 } else if (!UseSoftFloat && X86ScalarSSEf32) {
571 // Use SSE for f32, x87 for f64.
572 // Set up the FP register classes.
573 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
574 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
576 // Use ANDPS to simulate FABS.
577 setOperationAction(ISD::FABS , MVT::f32, Custom);
579 // Use XORP to simulate FNEG.
580 setOperationAction(ISD::FNEG , MVT::f32, Custom);
582 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
584 // Use ANDPS and ORPS to simulate FCOPYSIGN.
585 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
586 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
588 // We don't support sin/cos/fmod
589 setOperationAction(ISD::FSIN , MVT::f32, Expand);
590 setOperationAction(ISD::FCOS , MVT::f32, Expand);
592 // Special cases we handle for FP constants.
593 addLegalFPImmediate(APFloat(+0.0f)); // xorps
594 addLegalFPImmediate(APFloat(+0.0)); // FLD0
595 addLegalFPImmediate(APFloat(+1.0)); // FLD1
596 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
597 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
600 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
601 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
603 } else if (!UseSoftFloat) {
604 // f32 and f64 in x87.
605 // Set up the FP register classes.
606 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
607 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
609 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
610 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
611 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
612 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
615 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
616 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
618 addLegalFPImmediate(APFloat(+0.0)); // FLD0
619 addLegalFPImmediate(APFloat(+1.0)); // FLD1
620 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
621 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
622 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
623 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
624 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
625 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
628 // We don't support FMA.
629 setOperationAction(ISD::FMA, MVT::f64, Expand);
630 setOperationAction(ISD::FMA, MVT::f32, Expand);
632 // Long double always uses X87.
634 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
635 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
636 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
638 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
639 addLegalFPImmediate(TmpFlt); // FLD0
641 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
644 APFloat TmpFlt2(+1.0);
645 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
647 addLegalFPImmediate(TmpFlt2); // FLD1
648 TmpFlt2.changeSign();
649 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
653 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
654 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
657 setOperationAction(ISD::FMA, MVT::f80, Expand);
660 // Always use a library call for pow.
661 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
662 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
663 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
665 setOperationAction(ISD::FLOG, MVT::f80, Expand);
666 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
667 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
668 setOperationAction(ISD::FEXP, MVT::f80, Expand);
669 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
671 // First set operation action for all vector types to either promote
672 // (for widening) or expand (for scalarization). Then we will selectively
673 // turn on ones that can be effectively codegen'd.
674 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
675 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
676 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
677 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
678 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
679 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
680 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
681 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
682 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
683 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
684 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
685 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
686 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
687 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
688 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
689 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
690 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
691 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
692 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
693 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
694 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
695 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
696 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
697 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
698 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
699 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
701 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
703 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
704 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
705 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
706 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
707 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
708 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
709 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
710 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
711 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
712 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
713 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
714 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
715 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand);
716 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
717 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
718 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
719 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
720 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
721 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
722 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
723 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
724 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
725 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand);
726 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand);
727 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand);
728 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand);
729 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand);
730 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand);
731 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
732 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
733 setTruncStoreAction((MVT::SimpleValueType)VT,
734 (MVT::SimpleValueType)InnerVT, Expand);
735 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
736 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
737 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
740 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
741 // with -msoft-float, disable use of MMX as well.
742 if (!UseSoftFloat && Subtarget->hasMMX()) {
743 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass);
744 // No operations on x86mmx supported, everything uses intrinsics.
747 // MMX-sized vectors (other than x86mmx) are expected to be expanded
748 // into smaller operations.
749 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
750 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
751 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
752 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
753 setOperationAction(ISD::AND, MVT::v8i8, Expand);
754 setOperationAction(ISD::AND, MVT::v4i16, Expand);
755 setOperationAction(ISD::AND, MVT::v2i32, Expand);
756 setOperationAction(ISD::AND, MVT::v1i64, Expand);
757 setOperationAction(ISD::OR, MVT::v8i8, Expand);
758 setOperationAction(ISD::OR, MVT::v4i16, Expand);
759 setOperationAction(ISD::OR, MVT::v2i32, Expand);
760 setOperationAction(ISD::OR, MVT::v1i64, Expand);
761 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
762 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
763 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
764 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
765 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
766 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
767 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
768 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
770 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
771 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
772 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
773 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
774 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
775 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
776 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
777 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
779 if (!UseSoftFloat && Subtarget->hasXMM()) {
780 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
782 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
783 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
784 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
785 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
786 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
787 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
788 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
789 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
790 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
791 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
792 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
793 setOperationAction(ISD::SETCC, MVT::v4f32, Custom);
796 if (!UseSoftFloat && Subtarget->hasXMMInt()) {
797 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
799 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
800 // registers cannot be used even for integer operations.
801 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
802 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
803 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
804 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
806 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
807 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
808 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
809 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
812 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
813 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
814 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
815 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
816 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
817 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
818 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
819 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
820 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
821 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
823 setOperationAction(ISD::SETCC, MVT::v2f64, Custom);
824 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
825 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
826 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
828 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
830 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
831 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
834 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom);
835 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom);
836 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
837 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
838 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
840 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
841 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
842 EVT VT = (MVT::SimpleValueType)i;
843 // Do not attempt to custom lower non-power-of-2 vectors
844 if (!isPowerOf2_32(VT.getVectorNumElements()))
846 // Do not attempt to custom lower non-128-bit vectors
847 if (!VT.is128BitVector())
849 setOperationAction(ISD::BUILD_VECTOR,
850 VT.getSimpleVT().SimpleTy, Custom);
851 setOperationAction(ISD::VECTOR_SHUFFLE,
852 VT.getSimpleVT().SimpleTy, Custom);
853 setOperationAction(ISD::EXTRACT_VECTOR_ELT,
854 VT.getSimpleVT().SimpleTy, Custom);
857 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
858 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
859 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
860 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
861 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
862 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
864 if (Subtarget->is64Bit()) {
865 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
866 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
869 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
870 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
871 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
874 // Do not attempt to promote non-128-bit vectors
875 if (!VT.is128BitVector())
878 setOperationAction(ISD::AND, SVT, Promote);
879 AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
880 setOperationAction(ISD::OR, SVT, Promote);
881 AddPromotedToType (ISD::OR, SVT, MVT::v2i64);
882 setOperationAction(ISD::XOR, SVT, Promote);
883 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64);
884 setOperationAction(ISD::LOAD, SVT, Promote);
885 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64);
886 setOperationAction(ISD::SELECT, SVT, Promote);
887 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64);
890 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
892 // Custom lower v2i64 and v2f64 selects.
893 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
894 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
895 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
896 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
898 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
899 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
902 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
903 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
904 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
905 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
906 setOperationAction(ISD::FRINT, MVT::f32, Legal);
907 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
908 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
909 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
910 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
911 setOperationAction(ISD::FRINT, MVT::f64, Legal);
912 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
914 // FIXME: Do we need to handle scalar-to-vector here?
915 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
917 // Can turn SHL into an integer multiply.
918 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
919 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
921 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
922 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
923 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
924 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
925 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
927 // i8 and i16 vectors are custom , because the source register and source
928 // source memory operand types are not the same width. f32 vectors are
929 // custom since the immediate controlling the insert encodes additional
931 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
932 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
933 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
934 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
936 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
937 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
938 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
939 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
941 if (Subtarget->is64Bit()) {
942 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
947 if (Subtarget->hasSSE2() || Subtarget->hasAVX()) {
948 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
949 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
950 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
951 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
953 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
954 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
955 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
957 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
958 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
961 if (Subtarget->hasSSE42() || Subtarget->hasAVX())
962 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
964 if (!UseSoftFloat && Subtarget->hasAVX()) {
965 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass);
966 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass);
967 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
968 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
969 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
970 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
972 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
973 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
974 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
976 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
977 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
978 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
979 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
980 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
981 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
983 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
984 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
985 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
986 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
987 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
988 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
990 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
991 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
992 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
994 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom);
995 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom);
996 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
997 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
998 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom);
999 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom);
1001 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1002 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1003 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1004 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1006 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1007 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1008 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1009 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1011 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1012 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1014 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1015 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1016 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1017 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1019 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1020 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1021 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1023 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1024 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1025 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1026 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1028 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1029 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1030 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1031 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1033 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1034 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1035 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1036 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1038 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1039 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1040 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1041 // Don't lower v32i8 because there is no 128-bit byte mul
1043 // Custom lower several nodes for 256-bit types.
1044 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1045 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
1046 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1049 // Extract subvector is special because the value type
1050 // (result) is 128-bit but the source is 256-bit wide.
1051 if (VT.is128BitVector())
1052 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom);
1054 // Do not attempt to custom lower other non-256-bit vectors
1055 if (!VT.is256BitVector())
1058 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom);
1059 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom);
1060 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom);
1061 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom);
1062 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom);
1063 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom);
1066 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1067 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) {
1068 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i;
1071 // Do not attempt to promote non-256-bit vectors
1072 if (!VT.is256BitVector())
1075 setOperationAction(ISD::AND, SVT, Promote);
1076 AddPromotedToType (ISD::AND, SVT, MVT::v4i64);
1077 setOperationAction(ISD::OR, SVT, Promote);
1078 AddPromotedToType (ISD::OR, SVT, MVT::v4i64);
1079 setOperationAction(ISD::XOR, SVT, Promote);
1080 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64);
1081 setOperationAction(ISD::LOAD, SVT, Promote);
1082 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64);
1083 setOperationAction(ISD::SELECT, SVT, Promote);
1084 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64);
1088 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1089 // of this type with custom code.
1090 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
1091 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) {
1092 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom);
1095 // We want to custom lower some of our intrinsics.
1096 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1099 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1100 // handle type legalization for these operations here.
1102 // FIXME: We really should do custom legalization for addition and
1103 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1104 // than generic legalization for 64-bit multiplication-with-overflow, though.
1105 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1106 // Add/Sub/Mul with overflow operations are custom lowered.
1108 setOperationAction(ISD::SADDO, VT, Custom);
1109 setOperationAction(ISD::UADDO, VT, Custom);
1110 setOperationAction(ISD::SSUBO, VT, Custom);
1111 setOperationAction(ISD::USUBO, VT, Custom);
1112 setOperationAction(ISD::SMULO, VT, Custom);
1113 setOperationAction(ISD::UMULO, VT, Custom);
1116 // There are no 8-bit 3-address imul/mul instructions
1117 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1118 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1120 if (!Subtarget->is64Bit()) {
1121 // These libcalls are not available in 32-bit.
1122 setLibcallName(RTLIB::SHL_I128, 0);
1123 setLibcallName(RTLIB::SRL_I128, 0);
1124 setLibcallName(RTLIB::SRA_I128, 0);
1127 // We have target-specific dag combine patterns for the following nodes:
1128 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1129 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1130 setTargetDAGCombine(ISD::BUILD_VECTOR);
1131 setTargetDAGCombine(ISD::SELECT);
1132 setTargetDAGCombine(ISD::SHL);
1133 setTargetDAGCombine(ISD::SRA);
1134 setTargetDAGCombine(ISD::SRL);
1135 setTargetDAGCombine(ISD::OR);
1136 setTargetDAGCombine(ISD::AND);
1137 setTargetDAGCombine(ISD::ADD);
1138 setTargetDAGCombine(ISD::SUB);
1139 setTargetDAGCombine(ISD::STORE);
1140 setTargetDAGCombine(ISD::ZERO_EXTEND);
1141 setTargetDAGCombine(ISD::SINT_TO_FP);
1142 if (Subtarget->is64Bit())
1143 setTargetDAGCombine(ISD::MUL);
1145 computeRegisterProperties();
1147 // On Darwin, -Os means optimize for size without hurting performance,
1148 // do not reduce the limit.
1149 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1150 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1151 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1152 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1153 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1154 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1155 setPrefLoopAlignment(16);
1156 benefitFromCodePlacementOpt = true;
1158 setPrefFunctionAlignment(4);
1162 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1163 if (!VT.isVector()) return MVT::i8;
1164 return VT.changeVectorElementTypeToInteger();
1168 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1169 /// the desired ByVal argument alignment.
1170 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1173 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1174 if (VTy->getBitWidth() == 128)
1176 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1177 unsigned EltAlign = 0;
1178 getMaxByValAlign(ATy->getElementType(), EltAlign);
1179 if (EltAlign > MaxAlign)
1180 MaxAlign = EltAlign;
1181 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1182 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1183 unsigned EltAlign = 0;
1184 getMaxByValAlign(STy->getElementType(i), EltAlign);
1185 if (EltAlign > MaxAlign)
1186 MaxAlign = EltAlign;
1194 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1195 /// function arguments in the caller parameter area. For X86, aggregates
1196 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1197 /// are at 4-byte boundaries.
1198 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1199 if (Subtarget->is64Bit()) {
1200 // Max of 8 and alignment of type.
1201 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1208 if (Subtarget->hasXMM())
1209 getMaxByValAlign(Ty, Align);
1213 /// getOptimalMemOpType - Returns the target specific optimal type for load
1214 /// and store operations as a result of memset, memcpy, and memmove
1215 /// lowering. If DstAlign is zero that means it's safe to destination
1216 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1217 /// means there isn't a need to check it against alignment requirement,
1218 /// probably because the source does not need to be loaded. If
1219 /// 'NonScalarIntSafe' is true, that means it's safe to return a
1220 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
1221 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
1222 /// constant so it does not need to be loaded.
1223 /// It returns EVT::Other if the type should be determined using generic
1224 /// target-independent logic.
1226 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1227 unsigned DstAlign, unsigned SrcAlign,
1228 bool NonScalarIntSafe,
1230 MachineFunction &MF) const {
1231 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1232 // linux. This is because the stack realignment code can't handle certain
1233 // cases like PR2962. This should be removed when PR2962 is fixed.
1234 const Function *F = MF.getFunction();
1235 if (NonScalarIntSafe &&
1236 !F->hasFnAttr(Attribute::NoImplicitFloat)) {
1238 (Subtarget->isUnalignedMemAccessFast() ||
1239 ((DstAlign == 0 || DstAlign >= 16) &&
1240 (SrcAlign == 0 || SrcAlign >= 16))) &&
1241 Subtarget->getStackAlignment() >= 16) {
1242 if (Subtarget->hasSSE2())
1244 if (Subtarget->hasSSE1())
1246 } else if (!MemcpyStrSrc && Size >= 8 &&
1247 !Subtarget->is64Bit() &&
1248 Subtarget->getStackAlignment() >= 8 &&
1249 Subtarget->hasXMMInt()) {
1250 // Do not use f64 to lower memcpy if source is string constant. It's
1251 // better to use i32 to avoid the loads.
1255 if (Subtarget->is64Bit() && Size >= 8)
1260 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1261 /// current function. The returned value is a member of the
1262 /// MachineJumpTableInfo::JTEntryKind enum.
1263 unsigned X86TargetLowering::getJumpTableEncoding() const {
1264 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1266 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1267 Subtarget->isPICStyleGOT())
1268 return MachineJumpTableInfo::EK_Custom32;
1270 // Otherwise, use the normal jump table encoding heuristics.
1271 return TargetLowering::getJumpTableEncoding();
1275 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1276 const MachineBasicBlock *MBB,
1277 unsigned uid,MCContext &Ctx) const{
1278 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1279 Subtarget->isPICStyleGOT());
1280 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1282 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1283 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1286 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1288 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1289 SelectionDAG &DAG) const {
1290 if (!Subtarget->is64Bit())
1291 // This doesn't have DebugLoc associated with it, but is not really the
1292 // same as a Register.
1293 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1297 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1298 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1300 const MCExpr *X86TargetLowering::
1301 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1302 MCContext &Ctx) const {
1303 // X86-64 uses RIP relative addressing based on the jump table label.
1304 if (Subtarget->isPICStyleRIPRel())
1305 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1307 // Otherwise, the reference is relative to the PIC base.
1308 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1311 // FIXME: Why this routine is here? Move to RegInfo!
1312 std::pair<const TargetRegisterClass*, uint8_t>
1313 X86TargetLowering::findRepresentativeClass(EVT VT) const{
1314 const TargetRegisterClass *RRC = 0;
1316 switch (VT.getSimpleVT().SimpleTy) {
1318 return TargetLowering::findRepresentativeClass(VT);
1319 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1320 RRC = (Subtarget->is64Bit()
1321 ? X86::GR64RegisterClass : X86::GR32RegisterClass);
1324 RRC = X86::VR64RegisterClass;
1326 case MVT::f32: case MVT::f64:
1327 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1328 case MVT::v4f32: case MVT::v2f64:
1329 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1331 RRC = X86::VR128RegisterClass;
1334 return std::make_pair(RRC, Cost);
1337 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1338 unsigned &Offset) const {
1339 if (!Subtarget->isTargetLinux())
1342 if (Subtarget->is64Bit()) {
1343 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1345 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1358 //===----------------------------------------------------------------------===//
1359 // Return Value Calling Convention Implementation
1360 //===----------------------------------------------------------------------===//
1362 #include "X86GenCallingConv.inc"
1365 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1366 MachineFunction &MF, bool isVarArg,
1367 const SmallVectorImpl<ISD::OutputArg> &Outs,
1368 LLVMContext &Context) const {
1369 SmallVector<CCValAssign, 16> RVLocs;
1370 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1372 return CCInfo.CheckReturn(Outs, RetCC_X86);
1376 X86TargetLowering::LowerReturn(SDValue Chain,
1377 CallingConv::ID CallConv, bool isVarArg,
1378 const SmallVectorImpl<ISD::OutputArg> &Outs,
1379 const SmallVectorImpl<SDValue> &OutVals,
1380 DebugLoc dl, SelectionDAG &DAG) const {
1381 MachineFunction &MF = DAG.getMachineFunction();
1382 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1384 SmallVector<CCValAssign, 16> RVLocs;
1385 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1386 RVLocs, *DAG.getContext());
1387 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1389 // Add the regs to the liveout set for the function.
1390 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1391 for (unsigned i = 0; i != RVLocs.size(); ++i)
1392 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1393 MRI.addLiveOut(RVLocs[i].getLocReg());
1397 SmallVector<SDValue, 6> RetOps;
1398 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1399 // Operand #1 = Bytes To Pop
1400 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1403 // Copy the result values into the output registers.
1404 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1405 CCValAssign &VA = RVLocs[i];
1406 assert(VA.isRegLoc() && "Can only return in registers!");
1407 SDValue ValToCopy = OutVals[i];
1408 EVT ValVT = ValToCopy.getValueType();
1410 // If this is x86-64, and we disabled SSE, we can't return FP values,
1411 // or SSE or MMX vectors.
1412 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1413 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1414 (Subtarget->is64Bit() && !Subtarget->hasXMM())) {
1415 report_fatal_error("SSE register return with SSE disabled");
1417 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1418 // llvm-gcc has never done it right and no one has noticed, so this
1419 // should be OK for now.
1420 if (ValVT == MVT::f64 &&
1421 (Subtarget->is64Bit() && !Subtarget->hasXMMInt()))
1422 report_fatal_error("SSE2 register return with SSE2 disabled");
1424 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1425 // the RET instruction and handled by the FP Stackifier.
1426 if (VA.getLocReg() == X86::ST0 ||
1427 VA.getLocReg() == X86::ST1) {
1428 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1429 // change the value to the FP stack register class.
1430 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1431 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1432 RetOps.push_back(ValToCopy);
1433 // Don't emit a copytoreg.
1437 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1438 // which is returned in RAX / RDX.
1439 if (Subtarget->is64Bit()) {
1440 if (ValVT == MVT::x86mmx) {
1441 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1442 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1443 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1445 // If we don't have SSE2 available, convert to v4f32 so the generated
1446 // register is legal.
1447 if (!Subtarget->hasSSE2())
1448 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1453 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1454 Flag = Chain.getValue(1);
1457 // The x86-64 ABI for returning structs by value requires that we copy
1458 // the sret argument into %rax for the return. We saved the argument into
1459 // a virtual register in the entry block, so now we copy the value out
1461 if (Subtarget->is64Bit() &&
1462 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1463 MachineFunction &MF = DAG.getMachineFunction();
1464 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1465 unsigned Reg = FuncInfo->getSRetReturnReg();
1467 "SRetReturnReg should have been set in LowerFormalArguments().");
1468 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1470 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1471 Flag = Chain.getValue(1);
1473 // RAX now acts like a return value.
1474 MRI.addLiveOut(X86::RAX);
1477 RetOps[0] = Chain; // Update chain.
1479 // Add the flag if we have it.
1481 RetOps.push_back(Flag);
1483 return DAG.getNode(X86ISD::RET_FLAG, dl,
1484 MVT::Other, &RetOps[0], RetOps.size());
1487 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const {
1488 if (N->getNumValues() != 1)
1490 if (!N->hasNUsesOfValue(1, 0))
1493 SDNode *Copy = *N->use_begin();
1494 if (Copy->getOpcode() != ISD::CopyToReg &&
1495 Copy->getOpcode() != ISD::FP_EXTEND)
1498 bool HasRet = false;
1499 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1501 if (UI->getOpcode() != X86ISD::RET_FLAG)
1510 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
1511 ISD::NodeType ExtendKind) const {
1513 // TODO: Is this also valid on 32-bit?
1514 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1515 ReturnMVT = MVT::i8;
1517 ReturnMVT = MVT::i32;
1519 EVT MinVT = getRegisterType(Context, ReturnMVT);
1520 return VT.bitsLT(MinVT) ? MinVT : VT;
1523 /// LowerCallResult - Lower the result values of a call into the
1524 /// appropriate copies out of appropriate physical registers.
1527 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1528 CallingConv::ID CallConv, bool isVarArg,
1529 const SmallVectorImpl<ISD::InputArg> &Ins,
1530 DebugLoc dl, SelectionDAG &DAG,
1531 SmallVectorImpl<SDValue> &InVals) const {
1533 // Assign locations to each value returned by this call.
1534 SmallVector<CCValAssign, 16> RVLocs;
1535 bool Is64Bit = Subtarget->is64Bit();
1536 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1537 getTargetMachine(), RVLocs, *DAG.getContext());
1538 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1540 // Copy all of the result registers out of their specified physreg.
1541 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1542 CCValAssign &VA = RVLocs[i];
1543 EVT CopyVT = VA.getValVT();
1545 // If this is x86-64, and we disabled SSE, we can't return FP values
1546 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1547 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1548 report_fatal_error("SSE register return with SSE disabled");
1553 // If this is a call to a function that returns an fp value on the floating
1554 // point stack, we must guarantee the the value is popped from the stack, so
1555 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1556 // if the return value is not used. We use the FpPOP_RETVAL instruction
1558 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1559 // If we prefer to use the value in xmm registers, copy it out as f80 and
1560 // use a truncate to move it from fp stack reg to xmm reg.
1561 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1562 SDValue Ops[] = { Chain, InFlag };
1563 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1564 MVT::Other, MVT::Glue, Ops, 2), 1);
1565 Val = Chain.getValue(0);
1567 // Round the f80 to the right size, which also moves it to the appropriate
1569 if (CopyVT != VA.getValVT())
1570 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1571 // This truncation won't change the value.
1572 DAG.getIntPtrConstant(1));
1574 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1575 CopyVT, InFlag).getValue(1);
1576 Val = Chain.getValue(0);
1578 InFlag = Chain.getValue(2);
1579 InVals.push_back(Val);
1586 //===----------------------------------------------------------------------===//
1587 // C & StdCall & Fast Calling Convention implementation
1588 //===----------------------------------------------------------------------===//
1589 // StdCall calling convention seems to be standard for many Windows' API
1590 // routines and around. It differs from C calling convention just a little:
1591 // callee should clean up the stack, not caller. Symbols should be also
1592 // decorated in some fancy way :) It doesn't support any vector arguments.
1593 // For info on fast calling convention see Fast Calling Convention (tail call)
1594 // implementation LowerX86_32FastCCCallTo.
1596 /// CallIsStructReturn - Determines whether a call uses struct return
1598 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1602 return Outs[0].Flags.isSRet();
1605 /// ArgsAreStructReturn - Determines whether a function uses struct
1606 /// return semantics.
1608 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1612 return Ins[0].Flags.isSRet();
1615 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1616 /// by "Src" to address "Dst" with size and alignment information specified by
1617 /// the specific parameter attribute. The copy will be passed as a byval
1618 /// function parameter.
1620 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1621 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1623 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1625 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1626 /*isVolatile*/false, /*AlwaysInline=*/true,
1627 MachinePointerInfo(), MachinePointerInfo());
1630 /// IsTailCallConvention - Return true if the calling convention is one that
1631 /// supports tail call optimization.
1632 static bool IsTailCallConvention(CallingConv::ID CC) {
1633 return (CC == CallingConv::Fast || CC == CallingConv::GHC);
1636 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1637 if (!CI->isTailCall())
1641 CallingConv::ID CalleeCC = CS.getCallingConv();
1642 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1648 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1649 /// a tailcall target by changing its ABI.
1650 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) {
1651 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1655 X86TargetLowering::LowerMemArgument(SDValue Chain,
1656 CallingConv::ID CallConv,
1657 const SmallVectorImpl<ISD::InputArg> &Ins,
1658 DebugLoc dl, SelectionDAG &DAG,
1659 const CCValAssign &VA,
1660 MachineFrameInfo *MFI,
1662 // Create the nodes corresponding to a load from this parameter slot.
1663 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1664 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv);
1665 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1668 // If value is passed by pointer we have address passed instead of the value
1670 if (VA.getLocInfo() == CCValAssign::Indirect)
1671 ValVT = VA.getLocVT();
1673 ValVT = VA.getValVT();
1675 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1676 // changed with more analysis.
1677 // In case of tail call optimization mark all arguments mutable. Since they
1678 // could be overwritten by lowering of arguments in case of a tail call.
1679 if (Flags.isByVal()) {
1680 unsigned Bytes = Flags.getByValSize();
1681 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1682 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1683 return DAG.getFrameIndex(FI, getPointerTy());
1685 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1686 VA.getLocMemOffset(), isImmutable);
1687 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1688 return DAG.getLoad(ValVT, dl, Chain, FIN,
1689 MachinePointerInfo::getFixedStack(FI),
1695 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1696 CallingConv::ID CallConv,
1698 const SmallVectorImpl<ISD::InputArg> &Ins,
1701 SmallVectorImpl<SDValue> &InVals)
1703 MachineFunction &MF = DAG.getMachineFunction();
1704 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1706 const Function* Fn = MF.getFunction();
1707 if (Fn->hasExternalLinkage() &&
1708 Subtarget->isTargetCygMing() &&
1709 Fn->getName() == "main")
1710 FuncInfo->setForceFramePointer(true);
1712 MachineFrameInfo *MFI = MF.getFrameInfo();
1713 bool Is64Bit = Subtarget->is64Bit();
1714 bool IsWin64 = Subtarget->isTargetWin64();
1716 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1717 "Var args not supported with calling convention fastcc or ghc");
1719 // Assign locations to all of the incoming arguments.
1720 SmallVector<CCValAssign, 16> ArgLocs;
1721 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1722 ArgLocs, *DAG.getContext());
1724 // Allocate shadow area for Win64
1726 CCInfo.AllocateStack(32, 8);
1729 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1731 unsigned LastVal = ~0U;
1733 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1734 CCValAssign &VA = ArgLocs[i];
1735 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1737 assert(VA.getValNo() != LastVal &&
1738 "Don't support value assigned to multiple locs yet");
1739 LastVal = VA.getValNo();
1741 if (VA.isRegLoc()) {
1742 EVT RegVT = VA.getLocVT();
1743 TargetRegisterClass *RC = NULL;
1744 if (RegVT == MVT::i32)
1745 RC = X86::GR32RegisterClass;
1746 else if (Is64Bit && RegVT == MVT::i64)
1747 RC = X86::GR64RegisterClass;
1748 else if (RegVT == MVT::f32)
1749 RC = X86::FR32RegisterClass;
1750 else if (RegVT == MVT::f64)
1751 RC = X86::FR64RegisterClass;
1752 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256)
1753 RC = X86::VR256RegisterClass;
1754 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1755 RC = X86::VR128RegisterClass;
1756 else if (RegVT == MVT::x86mmx)
1757 RC = X86::VR64RegisterClass;
1759 llvm_unreachable("Unknown argument type!");
1761 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1762 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1764 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1765 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1767 if (VA.getLocInfo() == CCValAssign::SExt)
1768 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1769 DAG.getValueType(VA.getValVT()));
1770 else if (VA.getLocInfo() == CCValAssign::ZExt)
1771 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1772 DAG.getValueType(VA.getValVT()));
1773 else if (VA.getLocInfo() == CCValAssign::BCvt)
1774 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1776 if (VA.isExtInLoc()) {
1777 // Handle MMX values passed in XMM regs.
1778 if (RegVT.isVector()) {
1779 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(),
1782 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1785 assert(VA.isMemLoc());
1786 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1789 // If value is passed via pointer - do a load.
1790 if (VA.getLocInfo() == CCValAssign::Indirect)
1791 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
1792 MachinePointerInfo(), false, false, 0);
1794 InVals.push_back(ArgValue);
1797 // The x86-64 ABI for returning structs by value requires that we copy
1798 // the sret argument into %rax for the return. Save the argument into
1799 // a virtual register so that we can access it from the return points.
1800 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1801 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1802 unsigned Reg = FuncInfo->getSRetReturnReg();
1804 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1805 FuncInfo->setSRetReturnReg(Reg);
1807 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1808 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1811 unsigned StackSize = CCInfo.getNextStackOffset();
1812 // Align stack specially for tail calls.
1813 if (FuncIsMadeTailCallSafe(CallConv))
1814 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1816 // If the function takes variable number of arguments, make a frame index for
1817 // the start of the first vararg value... for expansion of llvm.va_start.
1819 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
1820 CallConv != CallingConv::X86_ThisCall)) {
1821 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
1824 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1826 // FIXME: We should really autogenerate these arrays
1827 static const unsigned GPR64ArgRegsWin64[] = {
1828 X86::RCX, X86::RDX, X86::R8, X86::R9
1830 static const unsigned GPR64ArgRegs64Bit[] = {
1831 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1833 static const unsigned XMMArgRegs64Bit[] = {
1834 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1835 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1837 const unsigned *GPR64ArgRegs;
1838 unsigned NumXMMRegs = 0;
1841 // The XMM registers which might contain var arg parameters are shadowed
1842 // in their paired GPR. So we only need to save the GPR to their home
1844 TotalNumIntRegs = 4;
1845 GPR64ArgRegs = GPR64ArgRegsWin64;
1847 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1848 GPR64ArgRegs = GPR64ArgRegs64Bit;
1850 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs);
1852 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1855 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1856 assert(!(NumXMMRegs && !Subtarget->hasXMM()) &&
1857 "SSE register cannot be used when SSE is disabled!");
1858 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1859 "SSE register cannot be used when SSE is disabled!");
1860 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM())
1861 // Kernel mode asks for SSE to be disabled, so don't push them
1863 TotalNumXMMRegs = 0;
1866 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
1867 // Get to the caller-allocated home save location. Add 8 to account
1868 // for the return address.
1869 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
1870 FuncInfo->setRegSaveFrameIndex(
1871 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
1872 // Fixup to set vararg frame on shadow area (4 x i64).
1874 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
1876 // For X86-64, if there are vararg parameters that are passed via
1877 // registers, then we must store them to their spots on the stack so they
1878 // may be loaded by deferencing the result of va_next.
1879 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
1880 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
1881 FuncInfo->setRegSaveFrameIndex(
1882 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
1886 // Store the integer parameter registers.
1887 SmallVector<SDValue, 8> MemOps;
1888 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
1890 unsigned Offset = FuncInfo->getVarArgsGPOffset();
1891 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1892 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1893 DAG.getIntPtrConstant(Offset));
1894 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1895 X86::GR64RegisterClass);
1896 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1898 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1899 MachinePointerInfo::getFixedStack(
1900 FuncInfo->getRegSaveFrameIndex(), Offset),
1902 MemOps.push_back(Store);
1906 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
1907 // Now store the XMM (fp + vector) parameter registers.
1908 SmallVector<SDValue, 11> SaveXMMOps;
1909 SaveXMMOps.push_back(Chain);
1911 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
1912 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
1913 SaveXMMOps.push_back(ALVal);
1915 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1916 FuncInfo->getRegSaveFrameIndex()));
1917 SaveXMMOps.push_back(DAG.getIntPtrConstant(
1918 FuncInfo->getVarArgsFPOffset()));
1920 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1921 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
1922 X86::VR128RegisterClass);
1923 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1924 SaveXMMOps.push_back(Val);
1926 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
1928 &SaveXMMOps[0], SaveXMMOps.size()));
1931 if (!MemOps.empty())
1932 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1933 &MemOps[0], MemOps.size());
1937 // Some CCs need callee pop.
1938 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
1939 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
1941 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
1942 // If this is an sret function, the return should pop the hidden pointer.
1943 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins))
1944 FuncInfo->setBytesToPopOnReturn(4);
1948 // RegSaveFrameIndex is X86-64 only.
1949 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
1950 if (CallConv == CallingConv::X86_FastCall ||
1951 CallConv == CallingConv::X86_ThisCall)
1952 // fastcc functions can't have varargs.
1953 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
1956 FuncInfo->setArgumentStackSize(StackSize);
1962 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1963 SDValue StackPtr, SDValue Arg,
1964 DebugLoc dl, SelectionDAG &DAG,
1965 const CCValAssign &VA,
1966 ISD::ArgFlagsTy Flags) const {
1967 unsigned LocMemOffset = VA.getLocMemOffset();
1968 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1969 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1970 if (Flags.isByVal())
1971 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1973 return DAG.getStore(Chain, dl, Arg, PtrOff,
1974 MachinePointerInfo::getStack(LocMemOffset),
1978 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1979 /// optimization is performed and it is required.
1981 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1982 SDValue &OutRetAddr, SDValue Chain,
1983 bool IsTailCall, bool Is64Bit,
1984 int FPDiff, DebugLoc dl) const {
1985 // Adjust the Return address stack slot.
1986 EVT VT = getPointerTy();
1987 OutRetAddr = getReturnAddressFrameIndex(DAG);
1989 // Load the "old" Return address.
1990 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
1992 return SDValue(OutRetAddr.getNode(), 1);
1995 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
1996 /// optimization is performed and it is required (FPDiff!=0).
1998 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1999 SDValue Chain, SDValue RetAddrFrIdx,
2000 bool Is64Bit, int FPDiff, DebugLoc dl) {
2001 // Store the return address to the appropriate stack slot.
2002 if (!FPDiff) return Chain;
2003 // Calculate the new stack slot for the return address.
2004 int SlotSize = Is64Bit ? 8 : 4;
2005 int NewReturnAddrFI =
2006 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2007 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2008 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
2009 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2010 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2016 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2017 CallingConv::ID CallConv, bool isVarArg,
2019 const SmallVectorImpl<ISD::OutputArg> &Outs,
2020 const SmallVectorImpl<SDValue> &OutVals,
2021 const SmallVectorImpl<ISD::InputArg> &Ins,
2022 DebugLoc dl, SelectionDAG &DAG,
2023 SmallVectorImpl<SDValue> &InVals) const {
2024 MachineFunction &MF = DAG.getMachineFunction();
2025 bool Is64Bit = Subtarget->is64Bit();
2026 bool IsWin64 = Subtarget->isTargetWin64();
2027 bool IsStructRet = CallIsStructReturn(Outs);
2028 bool IsSibcall = false;
2031 // Check if it's really possible to do a tail call.
2032 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2033 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
2034 Outs, OutVals, Ins, DAG);
2036 // Sibcalls are automatically detected tailcalls which do not require
2038 if (!GuaranteedTailCallOpt && isTailCall)
2045 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2046 "Var args not supported with calling convention fastcc or ghc");
2048 // Analyze operands of the call, assigning locations to each operand.
2049 SmallVector<CCValAssign, 16> ArgLocs;
2050 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2051 ArgLocs, *DAG.getContext());
2053 // Allocate shadow area for Win64
2055 CCInfo.AllocateStack(32, 8);
2058 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2060 // Get a count of how many bytes are to be pushed on the stack.
2061 unsigned NumBytes = CCInfo.getNextStackOffset();
2063 // This is a sibcall. The memory operands are available in caller's
2064 // own caller's stack.
2066 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv))
2067 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2070 if (isTailCall && !IsSibcall) {
2071 // Lower arguments at fp - stackoffset + fpdiff.
2072 unsigned NumBytesCallerPushed =
2073 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
2074 FPDiff = NumBytesCallerPushed - NumBytes;
2076 // Set the delta of movement of the returnaddr stackslot.
2077 // But only set if delta is greater than previous delta.
2078 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
2079 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
2083 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2085 SDValue RetAddrFrIdx;
2086 // Load return address for tail calls.
2087 if (isTailCall && FPDiff)
2088 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2089 Is64Bit, FPDiff, dl);
2091 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2092 SmallVector<SDValue, 8> MemOpChains;
2095 // Walk the register/memloc assignments, inserting copies/loads. In the case
2096 // of tail call optimization arguments are handle later.
2097 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2098 CCValAssign &VA = ArgLocs[i];
2099 EVT RegVT = VA.getLocVT();
2100 SDValue Arg = OutVals[i];
2101 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2102 bool isByVal = Flags.isByVal();
2104 // Promote the value if needed.
2105 switch (VA.getLocInfo()) {
2106 default: llvm_unreachable("Unknown loc info!");
2107 case CCValAssign::Full: break;
2108 case CCValAssign::SExt:
2109 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2111 case CCValAssign::ZExt:
2112 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2114 case CCValAssign::AExt:
2115 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
2116 // Special case: passing MMX values in XMM registers.
2117 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2118 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2119 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2121 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2123 case CCValAssign::BCvt:
2124 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2126 case CCValAssign::Indirect: {
2127 // Store the argument.
2128 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2129 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2130 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2131 MachinePointerInfo::getFixedStack(FI),
2138 if (VA.isRegLoc()) {
2139 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2140 if (isVarArg && IsWin64) {
2141 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2142 // shadow reg if callee is a varargs function.
2143 unsigned ShadowReg = 0;
2144 switch (VA.getLocReg()) {
2145 case X86::XMM0: ShadowReg = X86::RCX; break;
2146 case X86::XMM1: ShadowReg = X86::RDX; break;
2147 case X86::XMM2: ShadowReg = X86::R8; break;
2148 case X86::XMM3: ShadowReg = X86::R9; break;
2151 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2153 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2154 assert(VA.isMemLoc());
2155 if (StackPtr.getNode() == 0)
2156 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
2157 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2158 dl, DAG, VA, Flags));
2162 if (!MemOpChains.empty())
2163 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2164 &MemOpChains[0], MemOpChains.size());
2166 // Build a sequence of copy-to-reg nodes chained together with token chain
2167 // and flag operands which copy the outgoing args into registers.
2169 // Tail call byval lowering might overwrite argument registers so in case of
2170 // tail call optimization the copies to registers are lowered later.
2172 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2173 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2174 RegsToPass[i].second, InFlag);
2175 InFlag = Chain.getValue(1);
2178 if (Subtarget->isPICStyleGOT()) {
2179 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2182 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
2183 DAG.getNode(X86ISD::GlobalBaseReg,
2184 DebugLoc(), getPointerTy()),
2186 InFlag = Chain.getValue(1);
2188 // If we are tail calling and generating PIC/GOT style code load the
2189 // address of the callee into ECX. The value in ecx is used as target of
2190 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2191 // for tail calls on PIC/GOT architectures. Normally we would just put the
2192 // address of GOT into ebx and then call target@PLT. But for tail calls
2193 // ebx would be restored (since ebx is callee saved) before jumping to the
2196 // Note: The actual moving to ECX is done further down.
2197 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2198 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2199 !G->getGlobal()->hasProtectedVisibility())
2200 Callee = LowerGlobalAddress(Callee, DAG);
2201 else if (isa<ExternalSymbolSDNode>(Callee))
2202 Callee = LowerExternalSymbol(Callee, DAG);
2206 if (Is64Bit && isVarArg && !IsWin64) {
2207 // From AMD64 ABI document:
2208 // For calls that may call functions that use varargs or stdargs
2209 // (prototype-less calls or calls to functions containing ellipsis (...) in
2210 // the declaration) %al is used as hidden argument to specify the number
2211 // of SSE registers used. The contents of %al do not need to match exactly
2212 // the number of registers, but must be an ubound on the number of SSE
2213 // registers used and is in the range 0 - 8 inclusive.
2215 // Count the number of XMM registers allocated.
2216 static const unsigned XMMArgRegs[] = {
2217 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2218 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2220 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2221 assert((Subtarget->hasXMM() || !NumXMMRegs)
2222 && "SSE registers cannot be used when SSE is disabled");
2224 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
2225 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
2226 InFlag = Chain.getValue(1);
2230 // For tail calls lower the arguments to the 'real' stack slot.
2232 // Force all the incoming stack arguments to be loaded from the stack
2233 // before any new outgoing arguments are stored to the stack, because the
2234 // outgoing stack slots may alias the incoming argument stack slots, and
2235 // the alias isn't otherwise explicit. This is slightly more conservative
2236 // than necessary, because it means that each store effectively depends
2237 // on every argument instead of just those arguments it would clobber.
2238 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2240 SmallVector<SDValue, 8> MemOpChains2;
2243 // Do not flag preceding copytoreg stuff together with the following stuff.
2245 if (GuaranteedTailCallOpt) {
2246 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2247 CCValAssign &VA = ArgLocs[i];
2250 assert(VA.isMemLoc());
2251 SDValue Arg = OutVals[i];
2252 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2253 // Create frame index.
2254 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2255 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2256 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2257 FIN = DAG.getFrameIndex(FI, getPointerTy());
2259 if (Flags.isByVal()) {
2260 // Copy relative to framepointer.
2261 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2262 if (StackPtr.getNode() == 0)
2263 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
2265 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2267 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2271 // Store relative to framepointer.
2272 MemOpChains2.push_back(
2273 DAG.getStore(ArgChain, dl, Arg, FIN,
2274 MachinePointerInfo::getFixedStack(FI),
2280 if (!MemOpChains2.empty())
2281 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2282 &MemOpChains2[0], MemOpChains2.size());
2284 // Copy arguments to their registers.
2285 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2286 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2287 RegsToPass[i].second, InFlag);
2288 InFlag = Chain.getValue(1);
2292 // Store the return address to the appropriate stack slot.
2293 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
2297 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2298 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2299 // In the 64-bit large code model, we have to make all calls
2300 // through a register, since the call instruction's 32-bit
2301 // pc-relative offset may not be large enough to hold the whole
2303 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2304 // If the callee is a GlobalAddress node (quite common, every direct call
2305 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2308 // We should use extra load for direct calls to dllimported functions in
2310 const GlobalValue *GV = G->getGlobal();
2311 if (!GV->hasDLLImportLinkage()) {
2312 unsigned char OpFlags = 0;
2313 bool ExtraLoad = false;
2314 unsigned WrapperKind = ISD::DELETED_NODE;
2316 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2317 // external symbols most go through the PLT in PIC mode. If the symbol
2318 // has hidden or protected visibility, or if it is static or local, then
2319 // we don't need to use the PLT - we can directly call it.
2320 if (Subtarget->isTargetELF() &&
2321 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2322 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2323 OpFlags = X86II::MO_PLT;
2324 } else if (Subtarget->isPICStyleStubAny() &&
2325 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2326 (!Subtarget->getTargetTriple().isMacOSX() ||
2327 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2328 // PC-relative references to external symbols should go through $stub,
2329 // unless we're building with the leopard linker or later, which
2330 // automatically synthesizes these stubs.
2331 OpFlags = X86II::MO_DARWIN_STUB;
2332 } else if (Subtarget->isPICStyleRIPRel() &&
2333 isa<Function>(GV) &&
2334 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) {
2335 // If the function is marked as non-lazy, generate an indirect call
2336 // which loads from the GOT directly. This avoids runtime overhead
2337 // at the cost of eager binding (and one extra byte of encoding).
2338 OpFlags = X86II::MO_GOTPCREL;
2339 WrapperKind = X86ISD::WrapperRIP;
2343 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2344 G->getOffset(), OpFlags);
2346 // Add a wrapper if needed.
2347 if (WrapperKind != ISD::DELETED_NODE)
2348 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2349 // Add extra indirection if needed.
2351 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2352 MachinePointerInfo::getGOT(),
2355 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2356 unsigned char OpFlags = 0;
2358 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2359 // external symbols should go through the PLT.
2360 if (Subtarget->isTargetELF() &&
2361 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2362 OpFlags = X86II::MO_PLT;
2363 } else if (Subtarget->isPICStyleStubAny() &&
2364 (!Subtarget->getTargetTriple().isMacOSX() ||
2365 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2366 // PC-relative references to external symbols should go through $stub,
2367 // unless we're building with the leopard linker or later, which
2368 // automatically synthesizes these stubs.
2369 OpFlags = X86II::MO_DARWIN_STUB;
2372 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2376 // Returns a chain & a flag for retval copy to use.
2377 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2378 SmallVector<SDValue, 8> Ops;
2380 if (!IsSibcall && isTailCall) {
2381 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2382 DAG.getIntPtrConstant(0, true), InFlag);
2383 InFlag = Chain.getValue(1);
2386 Ops.push_back(Chain);
2387 Ops.push_back(Callee);
2390 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2392 // Add argument registers to the end of the list so that they are known live
2394 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2395 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2396 RegsToPass[i].second.getValueType()));
2398 // Add an implicit use GOT pointer in EBX.
2399 if (!isTailCall && Subtarget->isPICStyleGOT())
2400 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
2402 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions.
2403 if (Is64Bit && isVarArg && !IsWin64)
2404 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
2406 if (InFlag.getNode())
2407 Ops.push_back(InFlag);
2411 //// If this is the first return lowered for this function, add the regs
2412 //// to the liveout set for the function.
2413 // This isn't right, although it's probably harmless on x86; liveouts
2414 // should be computed from returns not tail calls. Consider a void
2415 // function making a tail call to a function returning int.
2416 return DAG.getNode(X86ISD::TC_RETURN, dl,
2417 NodeTys, &Ops[0], Ops.size());
2420 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2421 InFlag = Chain.getValue(1);
2423 // Create the CALLSEQ_END node.
2424 unsigned NumBytesForCalleeToPush;
2425 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
2426 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2427 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
2428 // If this is a call to a struct-return function, the callee
2429 // pops the hidden struct pointer, so we have to push it back.
2430 // This is common for Darwin/X86, Linux & Mingw32 targets.
2431 NumBytesForCalleeToPush = 4;
2433 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2435 // Returns a flag for retval copy to use.
2437 Chain = DAG.getCALLSEQ_END(Chain,
2438 DAG.getIntPtrConstant(NumBytes, true),
2439 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2442 InFlag = Chain.getValue(1);
2445 // Handle result values, copying them out of physregs into vregs that we
2447 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2448 Ins, dl, DAG, InVals);
2452 //===----------------------------------------------------------------------===//
2453 // Fast Calling Convention (tail call) implementation
2454 //===----------------------------------------------------------------------===//
2456 // Like std call, callee cleans arguments, convention except that ECX is
2457 // reserved for storing the tail called function address. Only 2 registers are
2458 // free for argument passing (inreg). Tail call optimization is performed
2460 // * tailcallopt is enabled
2461 // * caller/callee are fastcc
2462 // On X86_64 architecture with GOT-style position independent code only local
2463 // (within module) calls are supported at the moment.
2464 // To keep the stack aligned according to platform abi the function
2465 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2466 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2467 // If a tail called function callee has more arguments than the caller the
2468 // caller needs to make sure that there is room to move the RETADDR to. This is
2469 // achieved by reserving an area the size of the argument delta right after the
2470 // original REtADDR, but before the saved framepointer or the spilled registers
2471 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2483 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2484 /// for a 16 byte align requirement.
2486 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2487 SelectionDAG& DAG) const {
2488 MachineFunction &MF = DAG.getMachineFunction();
2489 const TargetMachine &TM = MF.getTarget();
2490 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2491 unsigned StackAlignment = TFI.getStackAlignment();
2492 uint64_t AlignMask = StackAlignment - 1;
2493 int64_t Offset = StackSize;
2494 uint64_t SlotSize = TD->getPointerSize();
2495 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2496 // Number smaller than 12 so just add the difference.
2497 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2499 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2500 Offset = ((~AlignMask) & Offset) + StackAlignment +
2501 (StackAlignment-SlotSize);
2506 /// MatchingStackOffset - Return true if the given stack call argument is
2507 /// already available in the same position (relatively) of the caller's
2508 /// incoming argument stack.
2510 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2511 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2512 const X86InstrInfo *TII) {
2513 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2515 if (Arg.getOpcode() == ISD::CopyFromReg) {
2516 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2517 if (!TargetRegisterInfo::isVirtualRegister(VR))
2519 MachineInstr *Def = MRI->getVRegDef(VR);
2522 if (!Flags.isByVal()) {
2523 if (!TII->isLoadFromStackSlot(Def, FI))
2526 unsigned Opcode = Def->getOpcode();
2527 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2528 Def->getOperand(1).isFI()) {
2529 FI = Def->getOperand(1).getIndex();
2530 Bytes = Flags.getByValSize();
2534 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2535 if (Flags.isByVal())
2536 // ByVal argument is passed in as a pointer but it's now being
2537 // dereferenced. e.g.
2538 // define @foo(%struct.X* %A) {
2539 // tail call @bar(%struct.X* byval %A)
2542 SDValue Ptr = Ld->getBasePtr();
2543 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2546 FI = FINode->getIndex();
2547 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2548 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2549 FI = FINode->getIndex();
2550 Bytes = Flags.getByValSize();
2554 assert(FI != INT_MAX);
2555 if (!MFI->isFixedObjectIndex(FI))
2557 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2560 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2561 /// for tail call optimization. Targets which want to do tail call
2562 /// optimization should implement this function.
2564 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2565 CallingConv::ID CalleeCC,
2567 bool isCalleeStructRet,
2568 bool isCallerStructRet,
2569 const SmallVectorImpl<ISD::OutputArg> &Outs,
2570 const SmallVectorImpl<SDValue> &OutVals,
2571 const SmallVectorImpl<ISD::InputArg> &Ins,
2572 SelectionDAG& DAG) const {
2573 if (!IsTailCallConvention(CalleeCC) &&
2574 CalleeCC != CallingConv::C)
2577 // If -tailcallopt is specified, make fastcc functions tail-callable.
2578 const MachineFunction &MF = DAG.getMachineFunction();
2579 const Function *CallerF = DAG.getMachineFunction().getFunction();
2580 CallingConv::ID CallerCC = CallerF->getCallingConv();
2581 bool CCMatch = CallerCC == CalleeCC;
2583 if (GuaranteedTailCallOpt) {
2584 if (IsTailCallConvention(CalleeCC) && CCMatch)
2589 // Look for obvious safe cases to perform tail call optimization that do not
2590 // require ABI changes. This is what gcc calls sibcall.
2592 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2593 // emit a special epilogue.
2594 if (RegInfo->needsStackRealignment(MF))
2597 // Also avoid sibcall optimization if either caller or callee uses struct
2598 // return semantics.
2599 if (isCalleeStructRet || isCallerStructRet)
2602 // An stdcall caller is expected to clean up its arguments; the callee
2603 // isn't going to do that.
2604 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2607 // Do not sibcall optimize vararg calls unless all arguments are passed via
2609 if (isVarArg && !Outs.empty()) {
2611 // Optimizing for varargs on Win64 is unlikely to be safe without
2612 // additional testing.
2613 if (Subtarget->isTargetWin64())
2616 SmallVector<CCValAssign, 16> ArgLocs;
2617 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2618 getTargetMachine(), ArgLocs, *DAG.getContext());
2620 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2621 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2622 if (!ArgLocs[i].isRegLoc())
2626 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack.
2627 // Therefore if it's not used by the call it is not safe to optimize this into
2629 bool Unused = false;
2630 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2637 SmallVector<CCValAssign, 16> RVLocs;
2638 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2639 getTargetMachine(), RVLocs, *DAG.getContext());
2640 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2641 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2642 CCValAssign &VA = RVLocs[i];
2643 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2648 // If the calling conventions do not match, then we'd better make sure the
2649 // results are returned in the same way as what the caller expects.
2651 SmallVector<CCValAssign, 16> RVLocs1;
2652 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2653 getTargetMachine(), RVLocs1, *DAG.getContext());
2654 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2656 SmallVector<CCValAssign, 16> RVLocs2;
2657 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2658 getTargetMachine(), RVLocs2, *DAG.getContext());
2659 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2661 if (RVLocs1.size() != RVLocs2.size())
2663 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2664 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2666 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2668 if (RVLocs1[i].isRegLoc()) {
2669 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2672 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2678 // If the callee takes no arguments then go on to check the results of the
2680 if (!Outs.empty()) {
2681 // Check if stack adjustment is needed. For now, do not do this if any
2682 // argument is passed on the stack.
2683 SmallVector<CCValAssign, 16> ArgLocs;
2684 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2685 getTargetMachine(), ArgLocs, *DAG.getContext());
2687 // Allocate shadow area for Win64
2688 if (Subtarget->isTargetWin64()) {
2689 CCInfo.AllocateStack(32, 8);
2692 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2693 if (CCInfo.getNextStackOffset()) {
2694 MachineFunction &MF = DAG.getMachineFunction();
2695 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2698 // Check if the arguments are already laid out in the right way as
2699 // the caller's fixed stack objects.
2700 MachineFrameInfo *MFI = MF.getFrameInfo();
2701 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2702 const X86InstrInfo *TII =
2703 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
2704 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2705 CCValAssign &VA = ArgLocs[i];
2706 SDValue Arg = OutVals[i];
2707 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2708 if (VA.getLocInfo() == CCValAssign::Indirect)
2710 if (!VA.isRegLoc()) {
2711 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2718 // If the tailcall address may be in a register, then make sure it's
2719 // possible to register allocate for it. In 32-bit, the call address can
2720 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2721 // callee-saved registers are restored. These happen to be the same
2722 // registers used to pass 'inreg' arguments so watch out for those.
2723 if (!Subtarget->is64Bit() &&
2724 !isa<GlobalAddressSDNode>(Callee) &&
2725 !isa<ExternalSymbolSDNode>(Callee)) {
2726 unsigned NumInRegs = 0;
2727 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2728 CCValAssign &VA = ArgLocs[i];
2731 unsigned Reg = VA.getLocReg();
2734 case X86::EAX: case X86::EDX: case X86::ECX:
2735 if (++NumInRegs == 3)
2747 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
2748 return X86::createFastISel(funcInfo);
2752 //===----------------------------------------------------------------------===//
2753 // Other Lowering Hooks
2754 //===----------------------------------------------------------------------===//
2756 static bool MayFoldLoad(SDValue Op) {
2757 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2760 static bool MayFoldIntoStore(SDValue Op) {
2761 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2764 static bool isTargetShuffle(unsigned Opcode) {
2766 default: return false;
2767 case X86ISD::PSHUFD:
2768 case X86ISD::PSHUFHW:
2769 case X86ISD::PSHUFLW:
2770 case X86ISD::SHUFPD:
2771 case X86ISD::PALIGN:
2772 case X86ISD::SHUFPS:
2773 case X86ISD::MOVLHPS:
2774 case X86ISD::MOVLHPD:
2775 case X86ISD::MOVHLPS:
2776 case X86ISD::MOVLPS:
2777 case X86ISD::MOVLPD:
2778 case X86ISD::MOVSHDUP:
2779 case X86ISD::MOVSLDUP:
2780 case X86ISD::MOVDDUP:
2783 case X86ISD::UNPCKLPS:
2784 case X86ISD::UNPCKLPD:
2785 case X86ISD::VUNPCKLPSY:
2786 case X86ISD::VUNPCKLPDY:
2787 case X86ISD::PUNPCKLWD:
2788 case X86ISD::PUNPCKLBW:
2789 case X86ISD::PUNPCKLDQ:
2790 case X86ISD::PUNPCKLQDQ:
2791 case X86ISD::UNPCKHPS:
2792 case X86ISD::UNPCKHPD:
2793 case X86ISD::VUNPCKHPSY:
2794 case X86ISD::VUNPCKHPDY:
2795 case X86ISD::PUNPCKHWD:
2796 case X86ISD::PUNPCKHBW:
2797 case X86ISD::PUNPCKHDQ:
2798 case X86ISD::PUNPCKHQDQ:
2799 case X86ISD::VPERMILPS:
2800 case X86ISD::VPERMILPSY:
2801 case X86ISD::VPERMILPD:
2802 case X86ISD::VPERMILPDY:
2803 case X86ISD::VPERM2F128:
2809 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2810 SDValue V1, SelectionDAG &DAG) {
2812 default: llvm_unreachable("Unknown x86 shuffle node");
2813 case X86ISD::MOVSHDUP:
2814 case X86ISD::MOVSLDUP:
2815 case X86ISD::MOVDDUP:
2816 return DAG.getNode(Opc, dl, VT, V1);
2822 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2823 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) {
2825 default: llvm_unreachable("Unknown x86 shuffle node");
2826 case X86ISD::PSHUFD:
2827 case X86ISD::PSHUFHW:
2828 case X86ISD::PSHUFLW:
2829 case X86ISD::VPERMILPS:
2830 case X86ISD::VPERMILPSY:
2831 case X86ISD::VPERMILPD:
2832 case X86ISD::VPERMILPDY:
2833 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
2839 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2840 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) {
2842 default: llvm_unreachable("Unknown x86 shuffle node");
2843 case X86ISD::PALIGN:
2844 case X86ISD::SHUFPD:
2845 case X86ISD::SHUFPS:
2846 case X86ISD::VPERM2F128:
2847 return DAG.getNode(Opc, dl, VT, V1, V2,
2848 DAG.getConstant(TargetMask, MVT::i8));
2853 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
2854 SDValue V1, SDValue V2, SelectionDAG &DAG) {
2856 default: llvm_unreachable("Unknown x86 shuffle node");
2857 case X86ISD::MOVLHPS:
2858 case X86ISD::MOVLHPD:
2859 case X86ISD::MOVHLPS:
2860 case X86ISD::MOVLPS:
2861 case X86ISD::MOVLPD:
2864 case X86ISD::UNPCKLPS:
2865 case X86ISD::UNPCKLPD:
2866 case X86ISD::VUNPCKLPSY:
2867 case X86ISD::VUNPCKLPDY:
2868 case X86ISD::PUNPCKLWD:
2869 case X86ISD::PUNPCKLBW:
2870 case X86ISD::PUNPCKLDQ:
2871 case X86ISD::PUNPCKLQDQ:
2872 case X86ISD::UNPCKHPS:
2873 case X86ISD::UNPCKHPD:
2874 case X86ISD::VUNPCKHPSY:
2875 case X86ISD::VUNPCKHPDY:
2876 case X86ISD::PUNPCKHWD:
2877 case X86ISD::PUNPCKHBW:
2878 case X86ISD::PUNPCKHDQ:
2879 case X86ISD::PUNPCKHQDQ:
2880 return DAG.getNode(Opc, dl, VT, V1, V2);
2885 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
2886 MachineFunction &MF = DAG.getMachineFunction();
2887 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2888 int ReturnAddrIndex = FuncInfo->getRAIndex();
2890 if (ReturnAddrIndex == 0) {
2891 // Set up a frame object for the return address.
2892 uint64_t SlotSize = TD->getPointerSize();
2893 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
2895 FuncInfo->setRAIndex(ReturnAddrIndex);
2898 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2902 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2903 bool hasSymbolicDisplacement) {
2904 // Offset should fit into 32 bit immediate field.
2905 if (!isInt<32>(Offset))
2908 // If we don't have a symbolic displacement - we don't have any extra
2910 if (!hasSymbolicDisplacement)
2913 // FIXME: Some tweaks might be needed for medium code model.
2914 if (M != CodeModel::Small && M != CodeModel::Kernel)
2917 // For small code model we assume that latest object is 16MB before end of 31
2918 // bits boundary. We may also accept pretty large negative constants knowing
2919 // that all objects are in the positive half of address space.
2920 if (M == CodeModel::Small && Offset < 16*1024*1024)
2923 // For kernel code model we know that all object resist in the negative half
2924 // of 32bits address space. We may not accept negative offsets, since they may
2925 // be just off and we may accept pretty large positive ones.
2926 if (M == CodeModel::Kernel && Offset > 0)
2932 /// isCalleePop - Determines whether the callee is required to pop its
2933 /// own arguments. Callee pop is necessary to support tail calls.
2934 bool X86::isCalleePop(CallingConv::ID CallingConv,
2935 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
2939 switch (CallingConv) {
2942 case CallingConv::X86_StdCall:
2944 case CallingConv::X86_FastCall:
2946 case CallingConv::X86_ThisCall:
2948 case CallingConv::Fast:
2950 case CallingConv::GHC:
2955 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2956 /// specific condition code, returning the condition code and the LHS/RHS of the
2957 /// comparison to make.
2958 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2959 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2961 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2962 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2963 // X > -1 -> X == 0, jump !sign.
2964 RHS = DAG.getConstant(0, RHS.getValueType());
2965 return X86::COND_NS;
2966 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2967 // X < 0 -> X == 0, jump on sign.
2969 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2971 RHS = DAG.getConstant(0, RHS.getValueType());
2972 return X86::COND_LE;
2976 switch (SetCCOpcode) {
2977 default: llvm_unreachable("Invalid integer condition!");
2978 case ISD::SETEQ: return X86::COND_E;
2979 case ISD::SETGT: return X86::COND_G;
2980 case ISD::SETGE: return X86::COND_GE;
2981 case ISD::SETLT: return X86::COND_L;
2982 case ISD::SETLE: return X86::COND_LE;
2983 case ISD::SETNE: return X86::COND_NE;
2984 case ISD::SETULT: return X86::COND_B;
2985 case ISD::SETUGT: return X86::COND_A;
2986 case ISD::SETULE: return X86::COND_BE;
2987 case ISD::SETUGE: return X86::COND_AE;
2991 // First determine if it is required or is profitable to flip the operands.
2993 // If LHS is a foldable load, but RHS is not, flip the condition.
2994 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
2995 !ISD::isNON_EXTLoad(RHS.getNode())) {
2996 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2997 std::swap(LHS, RHS);
3000 switch (SetCCOpcode) {
3006 std::swap(LHS, RHS);
3010 // On a floating point condition, the flags are set as follows:
3012 // 0 | 0 | 0 | X > Y
3013 // 0 | 0 | 1 | X < Y
3014 // 1 | 0 | 0 | X == Y
3015 // 1 | 1 | 1 | unordered
3016 switch (SetCCOpcode) {
3017 default: llvm_unreachable("Condcode should be pre-legalized away");
3019 case ISD::SETEQ: return X86::COND_E;
3020 case ISD::SETOLT: // flipped
3022 case ISD::SETGT: return X86::COND_A;
3023 case ISD::SETOLE: // flipped
3025 case ISD::SETGE: return X86::COND_AE;
3026 case ISD::SETUGT: // flipped
3028 case ISD::SETLT: return X86::COND_B;
3029 case ISD::SETUGE: // flipped
3031 case ISD::SETLE: return X86::COND_BE;
3033 case ISD::SETNE: return X86::COND_NE;
3034 case ISD::SETUO: return X86::COND_P;
3035 case ISD::SETO: return X86::COND_NP;
3037 case ISD::SETUNE: return X86::COND_INVALID;
3041 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3042 /// code. Current x86 isa includes the following FP cmov instructions:
3043 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3044 static bool hasFPCMov(unsigned X86CC) {
3060 /// isFPImmLegal - Returns true if the target can instruction select the
3061 /// specified FP immediate natively. If false, the legalizer will
3062 /// materialize the FP immediate as a load from a constant pool.
3063 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3064 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3065 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3071 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3072 /// the specified range (L, H].
3073 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3074 return (Val < 0) || (Val >= Low && Val < Hi);
3077 /// isUndefOrInRange - Return true if every element in Mask, begining
3078 /// from position Pos and ending in Pos+Size, falls within the specified
3079 /// range (L, L+Pos]. or is undef.
3080 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask,
3081 int Pos, int Size, int Low, int Hi) {
3082 for (int i = Pos, e = Pos+Size; i != e; ++i)
3083 if (!isUndefOrInRange(Mask[i], Low, Hi))
3088 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3089 /// specified value.
3090 static bool isUndefOrEqual(int Val, int CmpVal) {
3091 if (Val < 0 || Val == CmpVal)
3096 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3097 /// from position Pos and ending in Pos+Size, falls within the specified
3098 /// sequential range (L, L+Pos]. or is undef.
3099 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask,
3100 int Pos, int Size, int Low) {
3101 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3102 if (!isUndefOrEqual(Mask[i], Low))
3107 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3108 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3109 /// the second operand.
3110 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3111 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3112 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3113 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3114 return (Mask[0] < 2 && Mask[1] < 2);
3118 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
3119 SmallVector<int, 8> M;
3121 return ::isPSHUFDMask(M, N->getValueType(0));
3124 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3125 /// is suitable for input to PSHUFHW.
3126 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3127 if (VT != MVT::v8i16)
3130 // Lower quadword copied in order or undef.
3131 for (int i = 0; i != 4; ++i)
3132 if (Mask[i] >= 0 && Mask[i] != i)
3135 // Upper quadword shuffled.
3136 for (int i = 4; i != 8; ++i)
3137 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
3143 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
3144 SmallVector<int, 8> M;
3146 return ::isPSHUFHWMask(M, N->getValueType(0));
3149 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3150 /// is suitable for input to PSHUFLW.
3151 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3152 if (VT != MVT::v8i16)
3155 // Upper quadword copied in order.
3156 for (int i = 4; i != 8; ++i)
3157 if (Mask[i] >= 0 && Mask[i] != i)
3160 // Lower quadword shuffled.
3161 for (int i = 0; i != 4; ++i)
3168 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
3169 SmallVector<int, 8> M;
3171 return ::isPSHUFLWMask(M, N->getValueType(0));
3174 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3175 /// is suitable for input to PALIGNR.
3176 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
3178 int i, e = VT.getVectorNumElements();
3179 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64)
3182 // Do not handle v2i64 / v2f64 shuffles with palignr.
3183 if (e < 4 || !hasSSSE3)
3186 for (i = 0; i != e; ++i)
3190 // All undef, not a palignr.
3194 // Make sure we're shifting in the right direction.
3198 int s = Mask[i] - i;
3200 // Check the rest of the elements to see if they are consecutive.
3201 for (++i; i != e; ++i) {
3203 if (m >= 0 && m != s+i)
3209 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand
3210 /// specifies a shuffle of elements that is suitable for input to 256-bit
3212 static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3213 const X86Subtarget *Subtarget) {
3214 int NumElems = VT.getVectorNumElements();
3216 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3222 // VSHUFPSY divides the resulting vector into 4 chunks.
3223 // The sources are also splitted into 4 chunks, and each destination
3224 // chunk must come from a different source chunk.
3226 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3227 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3229 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3230 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3232 int QuarterSize = NumElems/4;
3233 int HalfSize = QuarterSize*2;
3234 for (int i = 0; i < QuarterSize; ++i)
3235 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3237 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3238 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3241 // The mask of the second half must be the same as the first but with
3242 // the appropriate offsets. This works in the same way as VPERMILPS
3243 // works with masks.
3244 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) {
3245 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3247 int FstHalfIdx = i-HalfSize;
3248 if (Mask[FstHalfIdx] < 0)
3250 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3253 for (int i = QuarterSize*3; i < NumElems; ++i) {
3254 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3256 int FstHalfIdx = i-HalfSize;
3257 if (Mask[FstHalfIdx] < 0)
3259 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize))
3267 /// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle
3268 /// the specified VECTOR_MASK mask with VSHUFPSY instruction.
3269 static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) {
3270 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3271 EVT VT = SVOp->getValueType(0);
3272 int NumElems = VT.getVectorNumElements();
3274 assert(NumElems == 8 && VT.getSizeInBits() == 256 &&
3275 "Only supports v8i32 and v8f32 types");
3277 int HalfSize = NumElems/2;
3279 for (int i = 0; i != NumElems ; ++i) {
3280 if (SVOp->getMaskElt(i) < 0)
3282 // The mask of the first half must be equal to the second one.
3283 unsigned Shamt = (i%HalfSize)*2;
3284 unsigned Elt = SVOp->getMaskElt(i) % HalfSize;
3285 Mask |= Elt << Shamt;
3291 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand
3292 /// specifies a shuffle of elements that is suitable for input to 256-bit
3293 /// VSHUFPDY. This shuffle doesn't have the same restriction as the PS
3294 /// version and the mask of the second half isn't binded with the first
3296 static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT,
3297 const X86Subtarget *Subtarget) {
3298 int NumElems = VT.getVectorNumElements();
3300 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3306 // VSHUFPSY divides the resulting vector into 4 chunks.
3307 // The sources are also splitted into 4 chunks, and each destination
3308 // chunk must come from a different source chunk.
3310 // SRC1 => X3 X2 X1 X0
3311 // SRC2 => Y3 Y2 Y1 Y0
3313 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0
3315 int QuarterSize = NumElems/4;
3316 int HalfSize = QuarterSize*2;
3317 for (int i = 0; i < QuarterSize; ++i)
3318 if (!isUndefOrInRange(Mask[i], 0, HalfSize))
3320 for (int i = QuarterSize; i < QuarterSize*2; ++i)
3321 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize))
3323 for (int i = QuarterSize*2; i < QuarterSize*3; ++i)
3324 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems))
3326 for (int i = QuarterSize*3; i < NumElems; ++i)
3327 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2))
3333 /// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle
3334 /// the specified VECTOR_MASK mask with VSHUFPDY instruction.
3335 static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) {
3336 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3337 EVT VT = SVOp->getValueType(0);
3338 int NumElems = VT.getVectorNumElements();
3340 assert(NumElems == 4 && VT.getSizeInBits() == 256 &&
3341 "Only supports v4i64 and v4f64 types");
3343 int HalfSize = NumElems/2;
3345 for (int i = 0; i != NumElems ; ++i) {
3346 if (SVOp->getMaskElt(i) < 0)
3348 int Elt = SVOp->getMaskElt(i) % HalfSize;
3355 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3356 /// specifies a shuffle of elements that is suitable for input to 128-bit
3357 /// SHUFPS and SHUFPD.
3358 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3359 int NumElems = VT.getVectorNumElements();
3361 if (VT.getSizeInBits() != 128)
3364 if (NumElems != 2 && NumElems != 4)
3367 int Half = NumElems / 2;
3368 for (int i = 0; i < Half; ++i)
3369 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3371 for (int i = Half; i < NumElems; ++i)
3372 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3378 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
3379 SmallVector<int, 8> M;
3381 return ::isSHUFPMask(M, N->getValueType(0));
3384 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
3385 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
3386 /// half elements to come from vector 1 (which would equal the dest.) and
3387 /// the upper half to come from vector 2.
3388 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3389 int NumElems = VT.getVectorNumElements();
3391 if (NumElems != 2 && NumElems != 4)
3394 int Half = NumElems / 2;
3395 for (int i = 0; i < Half; ++i)
3396 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
3398 for (int i = Half; i < NumElems; ++i)
3399 if (!isUndefOrInRange(Mask[i], 0, NumElems))
3404 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
3405 SmallVector<int, 8> M;
3407 return isCommutedSHUFPMask(M, N->getValueType(0));
3410 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3411 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3412 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
3413 EVT VT = N->getValueType(0);
3414 unsigned NumElems = VT.getVectorNumElements();
3416 if (VT.getSizeInBits() != 128)
3422 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3423 return isUndefOrEqual(N->getMaskElt(0), 6) &&
3424 isUndefOrEqual(N->getMaskElt(1), 7) &&
3425 isUndefOrEqual(N->getMaskElt(2), 2) &&
3426 isUndefOrEqual(N->getMaskElt(3), 3);
3429 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3430 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3432 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
3433 EVT VT = N->getValueType(0);
3434 unsigned NumElems = VT.getVectorNumElements();
3436 if (VT.getSizeInBits() != 128)
3442 return isUndefOrEqual(N->getMaskElt(0), 2) &&
3443 isUndefOrEqual(N->getMaskElt(1), 3) &&
3444 isUndefOrEqual(N->getMaskElt(2), 2) &&
3445 isUndefOrEqual(N->getMaskElt(3), 3);
3448 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3449 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3450 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
3451 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3453 if (NumElems != 2 && NumElems != 4)
3456 for (unsigned i = 0; i < NumElems/2; ++i)
3457 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
3460 for (unsigned i = NumElems/2; i < NumElems; ++i)
3461 if (!isUndefOrEqual(N->getMaskElt(i), i))
3467 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3468 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3469 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
3470 unsigned NumElems = N->getValueType(0).getVectorNumElements();
3472 if ((NumElems != 2 && NumElems != 4)
3473 || N->getValueType(0).getSizeInBits() > 128)
3476 for (unsigned i = 0; i < NumElems/2; ++i)
3477 if (!isUndefOrEqual(N->getMaskElt(i), i))
3480 for (unsigned i = 0; i < NumElems/2; ++i)
3481 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
3487 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3488 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3489 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3490 bool V2IsSplat = false) {
3491 int NumElts = VT.getVectorNumElements();
3493 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3494 "Unsupported vector type for unpckh");
3496 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3499 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3500 // independently on 128-bit lanes.
3501 unsigned NumLanes = VT.getSizeInBits()/128;
3502 unsigned NumLaneElts = NumElts/NumLanes;
3505 unsigned End = NumLaneElts;
3506 for (unsigned s = 0; s < NumLanes; ++s) {
3507 for (unsigned i = Start, j = s * NumLaneElts;
3511 int BitI1 = Mask[i+1];
3512 if (!isUndefOrEqual(BitI, j))
3515 if (!isUndefOrEqual(BitI1, NumElts))
3518 if (!isUndefOrEqual(BitI1, j + NumElts))
3522 // Process the next 128 bits.
3523 Start += NumLaneElts;
3530 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3531 SmallVector<int, 8> M;
3533 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
3536 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3537 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3538 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
3539 bool V2IsSplat = false) {
3540 int NumElts = VT.getVectorNumElements();
3542 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3543 "Unsupported vector type for unpckh");
3545 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
3548 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3549 // independently on 128-bit lanes.
3550 unsigned NumLanes = VT.getSizeInBits()/128;
3551 unsigned NumLaneElts = NumElts/NumLanes;
3554 unsigned End = NumLaneElts;
3555 for (unsigned l = 0; l != NumLanes; ++l) {
3556 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
3557 i != End; i += 2, ++j) {
3559 int BitI1 = Mask[i+1];
3560 if (!isUndefOrEqual(BitI, j))
3563 if (isUndefOrEqual(BitI1, NumElts))
3566 if (!isUndefOrEqual(BitI1, j+NumElts))
3570 // Process the next 128 bits.
3571 Start += NumLaneElts;
3577 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
3578 SmallVector<int, 8> M;
3580 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
3583 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3584 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3586 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3587 int NumElems = VT.getVectorNumElements();
3588 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3591 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3592 // FIXME: Need a better way to get rid of this, there's no latency difference
3593 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3594 // the former later. We should also remove the "_undef" special mask.
3595 if (NumElems == 4 && VT.getSizeInBits() == 256)
3598 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3599 // independently on 128-bit lanes.
3600 unsigned NumLanes = VT.getSizeInBits() / 128;
3601 unsigned NumLaneElts = NumElems / NumLanes;
3603 for (unsigned s = 0; s < NumLanes; ++s) {
3604 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
3605 i != NumLaneElts * (s + 1);
3608 int BitI1 = Mask[i+1];
3610 if (!isUndefOrEqual(BitI, j))
3612 if (!isUndefOrEqual(BitI1, j))
3620 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
3621 SmallVector<int, 8> M;
3623 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
3626 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3627 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3629 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
3630 int NumElems = VT.getVectorNumElements();
3631 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
3634 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
3636 int BitI1 = Mask[i+1];
3637 if (!isUndefOrEqual(BitI, j))
3639 if (!isUndefOrEqual(BitI1, j))
3645 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
3646 SmallVector<int, 8> M;
3648 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
3651 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3652 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3653 /// MOVSD, and MOVD, i.e. setting the lowest element.
3654 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) {
3655 if (VT.getVectorElementType().getSizeInBits() < 32)
3658 int NumElts = VT.getVectorNumElements();
3660 if (!isUndefOrEqual(Mask[0], NumElts))
3663 for (int i = 1; i < NumElts; ++i)
3664 if (!isUndefOrEqual(Mask[i], i))
3670 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
3671 SmallVector<int, 8> M;
3673 return ::isMOVLMask(M, N->getValueType(0));
3676 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered
3677 /// as permutations between 128-bit chunks or halves. As an example: this
3679 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3680 /// The first half comes from the second half of V1 and the second half from the
3681 /// the second half of V2.
3682 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT,
3683 const X86Subtarget *Subtarget) {
3684 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256)
3687 // The shuffle result is divided into half A and half B. In total the two
3688 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3689 // B must come from C, D, E or F.
3690 int HalfSize = VT.getVectorNumElements()/2;
3691 bool MatchA = false, MatchB = false;
3693 // Check if A comes from one of C, D, E, F.
3694 for (int Half = 0; Half < 4; ++Half) {
3695 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3701 // Check if B comes from one of C, D, E, F.
3702 for (int Half = 0; Half < 4; ++Half) {
3703 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3709 return MatchA && MatchB;
3712 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle
3713 /// the specified VECTOR_MASK mask with VPERM2F128 instructions.
3714 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) {
3715 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3716 EVT VT = SVOp->getValueType(0);
3718 int HalfSize = VT.getVectorNumElements()/2;
3720 int FstHalf = 0, SndHalf = 0;
3721 for (int i = 0; i < HalfSize; ++i) {
3722 if (SVOp->getMaskElt(i) > 0) {
3723 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3727 for (int i = HalfSize; i < HalfSize*2; ++i) {
3728 if (SVOp->getMaskElt(i) > 0) {
3729 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3734 return (FstHalf | (SndHalf << 4));
3737 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand
3738 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3739 /// Note that VPERMIL mask matching is different depending whether theunderlying
3740 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3741 /// to the same elements of the low, but to the higher half of the source.
3742 /// In VPERMILPD the two lanes could be shuffled independently of each other
3743 /// with the same restriction that lanes can't be crossed.
3744 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
3745 const X86Subtarget *Subtarget) {
3746 int NumElts = VT.getVectorNumElements();
3747 int NumLanes = VT.getSizeInBits()/128;
3749 if (!Subtarget->hasAVX())
3752 // Match any permutation of 128-bit vector with 64-bit types
3753 if (NumLanes == 1 && NumElts != 2)
3756 // Only match 256-bit with 32 types
3757 if (VT.getSizeInBits() == 256 && NumElts != 4)
3760 // The mask on the high lane is independent of the low. Both can match
3761 // any element in inside its own lane, but can't cross.
3762 int LaneSize = NumElts/NumLanes;
3763 for (int l = 0; l < NumLanes; ++l)
3764 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3765 int LaneStart = l*LaneSize;
3766 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize))
3773 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand
3774 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*.
3775 /// Note that VPERMIL mask matching is different depending whether theunderlying
3776 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3777 /// to the same elements of the low, but to the higher half of the source.
3778 /// In VPERMILPD the two lanes could be shuffled independently of each other
3779 /// with the same restriction that lanes can't be crossed.
3780 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
3781 const X86Subtarget *Subtarget) {
3782 unsigned NumElts = VT.getVectorNumElements();
3783 unsigned NumLanes = VT.getSizeInBits()/128;
3785 if (!Subtarget->hasAVX())
3788 // Match any permutation of 128-bit vector with 32-bit types
3789 if (NumLanes == 1 && NumElts != 4)
3792 // Only match 256-bit with 32 types
3793 if (VT.getSizeInBits() == 256 && NumElts != 8)
3796 // The mask on the high lane should be the same as the low. Actually,
3797 // they can differ if any of the corresponding index in a lane is undef
3798 // and the other stays in range.
3799 int LaneSize = NumElts/NumLanes;
3800 for (int i = 0; i < LaneSize; ++i) {
3801 int HighElt = i+LaneSize;
3802 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts);
3803 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize);
3805 if (!HighValid || !LowValid)
3807 if (Mask[i] < 0 || Mask[HighElt] < 0)
3809 if (Mask[HighElt]-Mask[i] != LaneSize)
3816 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle
3817 /// the specified VECTOR_MASK mask with VPERMILPS* instructions.
3818 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) {
3819 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3820 EVT VT = SVOp->getValueType(0);
3822 int NumElts = VT.getVectorNumElements();
3823 int NumLanes = VT.getSizeInBits()/128;
3824 int LaneSize = NumElts/NumLanes;
3826 // Although the mask is equal for both lanes do it twice to get the cases
3827 // where a mask will match because the same mask element is undef on the
3828 // first half but valid on the second. This would get pathological cases
3829 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid.
3831 for (int l = 0; l < NumLanes; ++l) {
3832 for (int i = 0; i < LaneSize; ++i) {
3833 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize));
3836 if (MaskElt >= LaneSize)
3837 MaskElt -= LaneSize;
3838 Mask |= MaskElt << (i*2);
3845 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle
3846 /// the specified VECTOR_MASK mask with VPERMILPD* instructions.
3847 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) {
3848 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
3849 EVT VT = SVOp->getValueType(0);
3851 int NumElts = VT.getVectorNumElements();
3852 int NumLanes = VT.getSizeInBits()/128;
3855 int LaneSize = NumElts/NumLanes;
3856 for (int l = 0; l < NumLanes; ++l)
3857 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) {
3858 int MaskElt = SVOp->getMaskElt(i);
3861 Mask |= (MaskElt-l*LaneSize) << i;
3867 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
3868 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3869 /// element of vector 2 and the other elements to come from vector 1 in order.
3870 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT,
3871 bool V2IsSplat = false, bool V2IsUndef = false) {
3872 int NumOps = VT.getVectorNumElements();
3873 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3876 if (!isUndefOrEqual(Mask[0], 0))
3879 for (int i = 1; i < NumOps; ++i)
3880 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3881 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3882 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3888 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
3889 bool V2IsUndef = false) {
3890 SmallVector<int, 8> M;
3892 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
3895 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3896 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3897 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3898 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N,
3899 const X86Subtarget *Subtarget) {
3900 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3903 // The second vector must be undef
3904 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3907 EVT VT = N->getValueType(0);
3908 unsigned NumElems = VT.getVectorNumElements();
3910 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3911 (VT.getSizeInBits() == 256 && NumElems != 8))
3914 // "i+1" is the value the indexed mask element must have
3915 for (unsigned i = 0; i < NumElems; i += 2)
3916 if (!isUndefOrEqual(N->getMaskElt(i), i+1) ||
3917 !isUndefOrEqual(N->getMaskElt(i+1), i+1))
3923 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3924 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3925 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3926 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N,
3927 const X86Subtarget *Subtarget) {
3928 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX())
3931 // The second vector must be undef
3932 if (N->getOperand(1).getOpcode() != ISD::UNDEF)
3935 EVT VT = N->getValueType(0);
3936 unsigned NumElems = VT.getVectorNumElements();
3938 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3939 (VT.getSizeInBits() == 256 && NumElems != 8))
3942 // "i" is the value the indexed mask element must have
3943 for (unsigned i = 0; i < NumElems; i += 2)
3944 if (!isUndefOrEqual(N->getMaskElt(i), i) ||
3945 !isUndefOrEqual(N->getMaskElt(i+1), i))
3951 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3952 /// specifies a shuffle of elements that is suitable for input to 256-bit
3953 /// version of MOVDDUP.
3954 static bool isMOVDDUPYMask(ShuffleVectorSDNode *N,
3955 const X86Subtarget *Subtarget) {
3956 EVT VT = N->getValueType(0);
3957 int NumElts = VT.getVectorNumElements();
3958 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF;
3960 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 ||
3961 !V2IsUndef || NumElts != 4)
3964 for (int i = 0; i != NumElts/2; ++i)
3965 if (!isUndefOrEqual(N->getMaskElt(i), 0))
3967 for (int i = NumElts/2; i != NumElts; ++i)
3968 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2))
3973 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3974 /// specifies a shuffle of elements that is suitable for input to 128-bit
3975 /// version of MOVDDUP.
3976 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
3977 EVT VT = N->getValueType(0);
3979 if (VT.getSizeInBits() != 128)
3982 int e = VT.getVectorNumElements() / 2;
3983 for (int i = 0; i < e; ++i)
3984 if (!isUndefOrEqual(N->getMaskElt(i), i))
3986 for (int i = 0; i < e; ++i)
3987 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
3992 /// isVEXTRACTF128Index - Return true if the specified
3993 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3994 /// suitable for input to VEXTRACTF128.
3995 bool X86::isVEXTRACTF128Index(SDNode *N) {
3996 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3999 // The index should be aligned on a 128-bit boundary.
4001 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4003 unsigned VL = N->getValueType(0).getVectorNumElements();
4004 unsigned VBits = N->getValueType(0).getSizeInBits();
4005 unsigned ElSize = VBits / VL;
4006 bool Result = (Index * ElSize) % 128 == 0;
4011 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4012 /// operand specifies a subvector insert that is suitable for input to
4014 bool X86::isVINSERTF128Index(SDNode *N) {
4015 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4018 // The index should be aligned on a 128-bit boundary.
4020 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4022 unsigned VL = N->getValueType(0).getVectorNumElements();
4023 unsigned VBits = N->getValueType(0).getSizeInBits();
4024 unsigned ElSize = VBits / VL;
4025 bool Result = (Index * ElSize) % 128 == 0;
4030 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4031 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4032 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
4033 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4034 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
4036 unsigned Shift = (NumOperands == 4) ? 2 : 1;
4038 for (int i = 0; i < NumOperands; ++i) {
4039 int Val = SVOp->getMaskElt(NumOperands-i-1);
4040 if (Val < 0) Val = 0;
4041 if (Val >= NumOperands) Val -= NumOperands;
4043 if (i != NumOperands - 1)
4049 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4050 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4051 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
4052 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4054 // 8 nodes, but we only care about the last 4.
4055 for (unsigned i = 7; i >= 4; --i) {
4056 int Val = SVOp->getMaskElt(i);
4065 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4066 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4067 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
4068 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4070 // 8 nodes, but we only care about the first 4.
4071 for (int i = 3; i >= 0; --i) {
4072 int Val = SVOp->getMaskElt(i);
4081 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4082 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4083 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) {
4084 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
4085 EVT VVT = N->getValueType(0);
4086 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3;
4090 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) {
4091 Val = SVOp->getMaskElt(i);
4095 assert(Val - i > 0 && "PALIGNR imm should be positive");
4096 return (Val - i) * EltSize;
4099 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4100 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4102 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4103 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4104 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4107 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4109 EVT VecVT = N->getOperand(0).getValueType();
4110 EVT ElVT = VecVT.getVectorElementType();
4112 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4113 return Index / NumElemsPerChunk;
4116 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4117 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4119 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4120 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4121 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4124 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4126 EVT VecVT = N->getValueType(0);
4127 EVT ElVT = VecVT.getVectorElementType();
4129 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4130 return Index / NumElemsPerChunk;
4133 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4135 bool X86::isZeroNode(SDValue Elt) {
4136 return ((isa<ConstantSDNode>(Elt) &&
4137 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4138 (isa<ConstantFPSDNode>(Elt) &&
4139 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4142 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4143 /// their permute mask.
4144 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4145 SelectionDAG &DAG) {
4146 EVT VT = SVOp->getValueType(0);
4147 unsigned NumElems = VT.getVectorNumElements();
4148 SmallVector<int, 8> MaskVec;
4150 for (unsigned i = 0; i != NumElems; ++i) {
4151 int idx = SVOp->getMaskElt(i);
4153 MaskVec.push_back(idx);
4154 else if (idx < (int)NumElems)
4155 MaskVec.push_back(idx + NumElems);
4157 MaskVec.push_back(idx - NumElems);
4159 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4160 SVOp->getOperand(0), &MaskVec[0]);
4163 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
4164 /// the two vector operands have swapped position.
4165 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) {
4166 unsigned NumElems = VT.getVectorNumElements();
4167 for (unsigned i = 0; i != NumElems; ++i) {
4171 else if (idx < (int)NumElems)
4172 Mask[i] = idx + NumElems;
4174 Mask[i] = idx - NumElems;
4178 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4179 /// match movhlps. The lower half elements should come from upper half of
4180 /// V1 (and in order), and the upper half elements should come from the upper
4181 /// half of V2 (and in order).
4182 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
4183 EVT VT = Op->getValueType(0);
4184 if (VT.getSizeInBits() != 128)
4186 if (VT.getVectorNumElements() != 4)
4188 for (unsigned i = 0, e = 2; i != e; ++i)
4189 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
4191 for (unsigned i = 2; i != 4; ++i)
4192 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
4197 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4198 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4200 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4201 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4203 N = N->getOperand(0).getNode();
4204 if (!ISD::isNON_EXTLoad(N))
4207 *LD = cast<LoadSDNode>(N);
4211 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4212 /// match movlp{s|d}. The lower half elements should come from lower half of
4213 /// V1 (and in order), and the upper half elements should come from the upper
4214 /// half of V2 (and in order). And since V1 will become the source of the
4215 /// MOVLP, it must be either a vector load or a scalar load to vector.
4216 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4217 ShuffleVectorSDNode *Op) {
4218 EVT VT = Op->getValueType(0);
4219 if (VT.getSizeInBits() != 128)
4222 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4224 // Is V2 is a vector load, don't do this transformation. We will try to use
4225 // load folding shufps op.
4226 if (ISD::isNON_EXTLoad(V2))
4229 unsigned NumElems = VT.getVectorNumElements();
4231 if (NumElems != 2 && NumElems != 4)
4233 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4234 if (!isUndefOrEqual(Op->getMaskElt(i), i))
4236 for (unsigned i = NumElems/2; i != NumElems; ++i)
4237 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
4242 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4244 static bool isSplatVector(SDNode *N) {
4245 if (N->getOpcode() != ISD::BUILD_VECTOR)
4248 SDValue SplatValue = N->getOperand(0);
4249 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4250 if (N->getOperand(i) != SplatValue)
4255 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4256 /// to an zero vector.
4257 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4258 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4259 SDValue V1 = N->getOperand(0);
4260 SDValue V2 = N->getOperand(1);
4261 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4262 for (unsigned i = 0; i != NumElems; ++i) {
4263 int Idx = N->getMaskElt(i);
4264 if (Idx >= (int)NumElems) {
4265 unsigned Opc = V2.getOpcode();
4266 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4268 if (Opc != ISD::BUILD_VECTOR ||
4269 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4271 } else if (Idx >= 0) {
4272 unsigned Opc = V1.getOpcode();
4273 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4275 if (Opc != ISD::BUILD_VECTOR ||
4276 !X86::isZeroNode(V1.getOperand(Idx)))
4283 /// getZeroVector - Returns a vector of specified type with all zero elements.
4285 static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG,
4287 assert(VT.isVector() && "Expected a vector type");
4289 // Always build SSE zero vectors as <4 x i32> bitcasted
4290 // to their dest type. This ensures they get CSE'd.
4292 if (VT.getSizeInBits() == 128) { // SSE
4293 if (HasSSE2) { // SSE2
4294 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4295 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4297 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4298 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4300 } else if (VT.getSizeInBits() == 256) { // AVX
4301 // 256-bit logic and arithmetic instructions in AVX are
4302 // all floating-point, no support for integer ops. Default
4303 // to emitting fp zeroed vectors then.
4304 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4305 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4306 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4308 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4311 /// getOnesVector - Returns a vector of specified type with all bits set.
4312 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two
4313 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their
4314 /// original type, ensuring they get CSE'd.
4315 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4316 assert(VT.isVector() && "Expected a vector type");
4317 assert((VT.is128BitVector() || VT.is256BitVector())
4318 && "Expected a 128-bit or 256-bit vector type");
4320 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4321 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
4322 Cst, Cst, Cst, Cst);
4324 if (VT.is256BitVector()) {
4325 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32),
4326 Vec, DAG.getConstant(0, MVT::i32), DAG, dl);
4327 Vec = Insert128BitVector(InsV, Vec,
4328 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl);
4331 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4334 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4335 /// that point to V2 points to its first element.
4336 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
4337 EVT VT = SVOp->getValueType(0);
4338 unsigned NumElems = VT.getVectorNumElements();
4340 bool Changed = false;
4341 SmallVector<int, 8> MaskVec;
4342 SVOp->getMask(MaskVec);
4344 for (unsigned i = 0; i != NumElems; ++i) {
4345 if (MaskVec[i] > (int)NumElems) {
4346 MaskVec[i] = NumElems;
4351 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
4352 SVOp->getOperand(1), &MaskVec[0]);
4353 return SDValue(SVOp, 0);
4356 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4357 /// operation of specified width.
4358 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4360 unsigned NumElems = VT.getVectorNumElements();
4361 SmallVector<int, 8> Mask;
4362 Mask.push_back(NumElems);
4363 for (unsigned i = 1; i != NumElems; ++i)
4365 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4368 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4369 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4371 unsigned NumElems = VT.getVectorNumElements();
4372 SmallVector<int, 8> Mask;
4373 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4375 Mask.push_back(i + NumElems);
4377 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4380 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4381 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4383 unsigned NumElems = VT.getVectorNumElements();
4384 unsigned Half = NumElems/2;
4385 SmallVector<int, 8> Mask;
4386 for (unsigned i = 0; i != Half; ++i) {
4387 Mask.push_back(i + Half);
4388 Mask.push_back(i + NumElems + Half);
4390 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4393 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4394 // a generic shuffle instruction because the target has no such instructions.
4395 // Generate shuffles which repeat i16 and i8 several times until they can be
4396 // represented by v4f32 and then be manipulated by target suported shuffles.
4397 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4398 EVT VT = V.getValueType();
4399 int NumElems = VT.getVectorNumElements();
4400 DebugLoc dl = V.getDebugLoc();
4402 while (NumElems > 4) {
4403 if (EltNo < NumElems/2) {
4404 V = getUnpackl(DAG, dl, VT, V, V);
4406 V = getUnpackh(DAG, dl, VT, V, V);
4407 EltNo -= NumElems/2;
4414 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4415 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4416 EVT VT = V.getValueType();
4417 DebugLoc dl = V.getDebugLoc();
4418 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256)
4419 && "Vector size not supported");
4421 if (VT.getSizeInBits() == 128) {
4422 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4423 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4424 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4427 // To use VPERMILPS to splat scalars, the second half of indicies must
4428 // refer to the higher part, which is a duplication of the lower one,
4429 // because VPERMILPS can only handle in-lane permutations.
4430 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4431 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4433 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4434 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4438 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4441 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4442 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4443 EVT SrcVT = SV->getValueType(0);
4444 SDValue V1 = SV->getOperand(0);
4445 DebugLoc dl = SV->getDebugLoc();
4447 int EltNo = SV->getSplatIndex();
4448 int NumElems = SrcVT.getVectorNumElements();
4449 unsigned Size = SrcVT.getSizeInBits();
4451 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4452 "Unknown how to promote splat for type");
4454 // Extract the 128-bit part containing the splat element and update
4455 // the splat element index when it refers to the higher register.
4457 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0;
4458 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl);
4460 EltNo -= NumElems/2;
4463 // All i16 and i8 vector types can't be used directly by a generic shuffle
4464 // instruction because the target has no such instruction. Generate shuffles
4465 // which repeat i16 and i8 several times until they fit in i32, and then can
4466 // be manipulated by target suported shuffles.
4467 EVT EltVT = SrcVT.getVectorElementType();
4468 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4469 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4471 // Recreate the 256-bit vector and place the same 128-bit vector
4472 // into the low and high part. This is necessary because we want
4473 // to use VPERM* to shuffle the vectors
4475 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1,
4476 DAG.getConstant(0, MVT::i32), DAG, dl);
4477 V1 = Insert128BitVector(InsV, V1,
4478 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
4481 return getLegalSplat(DAG, V1, EltNo);
4484 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4485 /// vector of zero or undef vector. This produces a shuffle where the low
4486 /// element of V2 is swizzled into the zero/undef vector, landing at element
4487 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4488 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4489 bool isZero, bool HasSSE2,
4490 SelectionDAG &DAG) {
4491 EVT VT = V2.getValueType();
4493 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4494 unsigned NumElems = VT.getVectorNumElements();
4495 SmallVector<int, 16> MaskVec;
4496 for (unsigned i = 0; i != NumElems; ++i)
4497 // If this is the insertion idx, put the low elt of V2 here.
4498 MaskVec.push_back(i == Idx ? NumElems : i);
4499 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4502 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4503 /// element of the result of the vector shuffle.
4504 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
4507 return SDValue(); // Limit search depth.
4509 SDValue V = SDValue(N, 0);
4510 EVT VT = V.getValueType();
4511 unsigned Opcode = V.getOpcode();
4513 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4514 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4515 Index = SV->getMaskElt(Index);
4518 return DAG.getUNDEF(VT.getVectorElementType());
4520 int NumElems = VT.getVectorNumElements();
4521 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1);
4522 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1);
4525 // Recurse into target specific vector shuffles to find scalars.
4526 if (isTargetShuffle(Opcode)) {
4527 int NumElems = VT.getVectorNumElements();
4528 SmallVector<unsigned, 16> ShuffleMask;
4532 case X86ISD::SHUFPS:
4533 case X86ISD::SHUFPD:
4534 ImmN = N->getOperand(N->getNumOperands()-1);
4535 DecodeSHUFPSMask(NumElems,
4536 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4539 case X86ISD::PUNPCKHBW:
4540 case X86ISD::PUNPCKHWD:
4541 case X86ISD::PUNPCKHDQ:
4542 case X86ISD::PUNPCKHQDQ:
4543 DecodePUNPCKHMask(NumElems, ShuffleMask);
4545 case X86ISD::UNPCKHPS:
4546 case X86ISD::UNPCKHPD:
4547 case X86ISD::VUNPCKHPSY:
4548 case X86ISD::VUNPCKHPDY:
4549 DecodeUNPCKHPMask(NumElems, ShuffleMask);
4551 case X86ISD::PUNPCKLBW:
4552 case X86ISD::PUNPCKLWD:
4553 case X86ISD::PUNPCKLDQ:
4554 case X86ISD::PUNPCKLQDQ:
4555 DecodePUNPCKLMask(VT, ShuffleMask);
4557 case X86ISD::UNPCKLPS:
4558 case X86ISD::UNPCKLPD:
4559 case X86ISD::VUNPCKLPSY:
4560 case X86ISD::VUNPCKLPDY:
4561 DecodeUNPCKLPMask(VT, ShuffleMask);
4563 case X86ISD::MOVHLPS:
4564 DecodeMOVHLPSMask(NumElems, ShuffleMask);
4566 case X86ISD::MOVLHPS:
4567 DecodeMOVLHPSMask(NumElems, ShuffleMask);
4569 case X86ISD::PSHUFD:
4570 ImmN = N->getOperand(N->getNumOperands()-1);
4571 DecodePSHUFMask(NumElems,
4572 cast<ConstantSDNode>(ImmN)->getZExtValue(),
4575 case X86ISD::PSHUFHW:
4576 ImmN = N->getOperand(N->getNumOperands()-1);
4577 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4580 case X86ISD::PSHUFLW:
4581 ImmN = N->getOperand(N->getNumOperands()-1);
4582 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(),
4586 case X86ISD::MOVSD: {
4587 // The index 0 always comes from the first element of the second source,
4588 // this is why MOVSS and MOVSD are used in the first place. The other
4589 // elements come from the other positions of the first source vector.
4590 unsigned OpNum = (Index == 0) ? 1 : 0;
4591 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4594 case X86ISD::VPERMILPS:
4595 ImmN = N->getOperand(N->getNumOperands()-1);
4596 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4599 case X86ISD::VPERMILPSY:
4600 ImmN = N->getOperand(N->getNumOperands()-1);
4601 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4604 case X86ISD::VPERMILPD:
4605 ImmN = N->getOperand(N->getNumOperands()-1);
4606 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4609 case X86ISD::VPERMILPDY:
4610 ImmN = N->getOperand(N->getNumOperands()-1);
4611 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4614 case X86ISD::VPERM2F128:
4615 ImmN = N->getOperand(N->getNumOperands()-1);
4616 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(),
4619 case X86ISD::MOVDDUP:
4620 case X86ISD::MOVLHPD:
4621 case X86ISD::MOVLPD:
4622 case X86ISD::MOVLPS:
4623 case X86ISD::MOVSHDUP:
4624 case X86ISD::MOVSLDUP:
4625 case X86ISD::PALIGN:
4626 return SDValue(); // Not yet implemented.
4628 assert(0 && "unknown target shuffle node");
4632 Index = ShuffleMask[Index];
4634 return DAG.getUNDEF(VT.getVectorElementType());
4636 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1);
4637 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG,
4641 // Actual nodes that may contain scalar elements
4642 if (Opcode == ISD::BITCAST) {
4643 V = V.getOperand(0);
4644 EVT SrcVT = V.getValueType();
4645 unsigned NumElems = VT.getVectorNumElements();
4647 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4651 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4652 return (Index == 0) ? V.getOperand(0)
4653 : DAG.getUNDEF(VT.getVectorElementType());
4655 if (V.getOpcode() == ISD::BUILD_VECTOR)
4656 return V.getOperand(Index);
4661 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4662 /// shuffle operation which come from a consecutively from a zero. The
4663 /// search can start in two different directions, from left or right.
4665 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems,
4666 bool ZerosFromLeft, SelectionDAG &DAG) {
4669 while (i < NumElems) {
4670 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4671 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0);
4672 if (!(Elt.getNode() &&
4673 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4681 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to
4682 /// MaskE correspond consecutively to elements from one of the vector operands,
4683 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4685 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE,
4686 int OpIdx, int NumElems, unsigned &OpNum) {
4687 bool SeenV1 = false;
4688 bool SeenV2 = false;
4690 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4691 int Idx = SVOp->getMaskElt(i);
4692 // Ignore undef indicies
4701 // Only accept consecutive elements from the same vector
4702 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4706 OpNum = SeenV1 ? 0 : 1;
4710 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4711 /// logical left shift of a vector.
4712 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4713 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4714 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4715 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4716 false /* check zeros from right */, DAG);
4722 // Considering the elements in the mask that are not consecutive zeros,
4723 // check if they consecutively come from only one of the source vectors.
4725 // V1 = {X, A, B, C} 0
4727 // vector_shuffle V1, V2 <1, 2, 3, X>
4729 if (!isShuffleMaskConsecutive(SVOp,
4730 0, // Mask Start Index
4731 NumElems-NumZeros-1, // Mask End Index
4732 NumZeros, // Where to start looking in the src vector
4733 NumElems, // Number of elements in vector
4734 OpSrc)) // Which source operand ?
4739 ShVal = SVOp->getOperand(OpSrc);
4743 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4744 /// logical left shift of a vector.
4745 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4746 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4747 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4748 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4749 true /* check zeros from left */, DAG);
4755 // Considering the elements in the mask that are not consecutive zeros,
4756 // check if they consecutively come from only one of the source vectors.
4758 // 0 { A, B, X, X } = V2
4760 // vector_shuffle V1, V2 <X, X, 4, 5>
4762 if (!isShuffleMaskConsecutive(SVOp,
4763 NumZeros, // Mask Start Index
4764 NumElems-1, // Mask End Index
4765 0, // Where to start looking in the src vector
4766 NumElems, // Number of elements in vector
4767 OpSrc)) // Which source operand ?
4772 ShVal = SVOp->getOperand(OpSrc);
4776 /// isVectorShift - Returns true if the shuffle can be implemented as a
4777 /// logical left or right shift of a vector.
4778 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4779 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4780 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4781 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4787 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4789 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4790 unsigned NumNonZero, unsigned NumZero,
4792 const TargetLowering &TLI) {
4796 DebugLoc dl = Op.getDebugLoc();
4799 for (unsigned i = 0; i < 16; ++i) {
4800 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4801 if (ThisIsNonZero && First) {
4803 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4805 V = DAG.getUNDEF(MVT::v8i16);
4810 SDValue ThisElt(0, 0), LastElt(0, 0);
4811 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4812 if (LastIsNonZero) {
4813 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4814 MVT::i16, Op.getOperand(i-1));
4816 if (ThisIsNonZero) {
4817 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4818 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4819 ThisElt, DAG.getConstant(8, MVT::i8));
4821 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4825 if (ThisElt.getNode())
4826 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4827 DAG.getIntPtrConstant(i/2));
4831 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4834 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4836 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4837 unsigned NumNonZero, unsigned NumZero,
4839 const TargetLowering &TLI) {
4843 DebugLoc dl = Op.getDebugLoc();
4846 for (unsigned i = 0; i < 8; ++i) {
4847 bool isNonZero = (NonZeros & (1 << i)) != 0;
4851 V = getZeroVector(MVT::v8i16, true, DAG, dl);
4853 V = DAG.getUNDEF(MVT::v8i16);
4856 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4857 MVT::v8i16, V, Op.getOperand(i),
4858 DAG.getIntPtrConstant(i));
4865 /// getVShift - Return a vector logical shift node.
4867 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4868 unsigned NumBits, SelectionDAG &DAG,
4869 const TargetLowering &TLI, DebugLoc dl) {
4870 EVT ShVT = MVT::v2i64;
4871 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
4872 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4873 return DAG.getNode(ISD::BITCAST, dl, VT,
4874 DAG.getNode(Opc, dl, ShVT, SrcOp,
4875 DAG.getConstant(NumBits,
4876 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4880 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4881 SelectionDAG &DAG) const {
4883 // Check if the scalar load can be widened into a vector load. And if
4884 // the address is "base + cst" see if the cst can be "absorbed" into
4885 // the shuffle mask.
4886 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4887 SDValue Ptr = LD->getBasePtr();
4888 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4890 EVT PVT = LD->getValueType(0);
4891 if (PVT != MVT::i32 && PVT != MVT::f32)
4896 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4897 FI = FINode->getIndex();
4899 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4900 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4901 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4902 Offset = Ptr.getConstantOperandVal(1);
4903 Ptr = Ptr.getOperand(0);
4908 // FIXME: 256-bit vector instructions don't require a strict alignment,
4909 // improve this code to support it better.
4910 unsigned RequiredAlign = VT.getSizeInBits()/8;
4911 SDValue Chain = LD->getChain();
4912 // Make sure the stack object alignment is at least 16 or 32.
4913 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4914 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4915 if (MFI->isFixedObjectIndex(FI)) {
4916 // Can't change the alignment. FIXME: It's possible to compute
4917 // the exact stack offset and reference FI + adjust offset instead.
4918 // If someone *really* cares about this. That's the way to implement it.
4921 MFI->setObjectAlignment(FI, RequiredAlign);
4925 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4926 // Ptr + (Offset & ~15).
4929 if ((Offset % RequiredAlign) & 3)
4931 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4933 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4934 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4936 int EltNo = (Offset - StartOffset) >> 2;
4937 int NumElems = VT.getVectorNumElements();
4939 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32;
4940 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4941 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4942 LD->getPointerInfo().getWithOffset(StartOffset),
4945 // Canonicalize it to a v4i32 or v8i32 shuffle.
4946 SmallVector<int, 8> Mask;
4947 for (int i = 0; i < NumElems; ++i)
4948 Mask.push_back(EltNo);
4950 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1);
4951 return DAG.getNode(ISD::BITCAST, dl, NVT,
4952 DAG.getVectorShuffle(CanonVT, dl, V1,
4953 DAG.getUNDEF(CanonVT),&Mask[0]));
4959 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
4960 /// vector of type 'VT', see if the elements can be replaced by a single large
4961 /// load which has the same value as a build_vector whose operands are 'elts'.
4963 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4965 /// FIXME: we'd also like to handle the case where the last elements are zero
4966 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4967 /// There's even a handy isZeroNode for that purpose.
4968 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
4969 DebugLoc &DL, SelectionDAG &DAG) {
4970 EVT EltVT = VT.getVectorElementType();
4971 unsigned NumElems = Elts.size();
4973 LoadSDNode *LDBase = NULL;
4974 unsigned LastLoadedElt = -1U;
4976 // For each element in the initializer, see if we've found a load or an undef.
4977 // If we don't find an initial load element, or later load elements are
4978 // non-consecutive, bail out.
4979 for (unsigned i = 0; i < NumElems; ++i) {
4980 SDValue Elt = Elts[i];
4982 if (!Elt.getNode() ||
4983 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4986 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4988 LDBase = cast<LoadSDNode>(Elt.getNode());
4992 if (Elt.getOpcode() == ISD::UNDEF)
4995 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4996 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5001 // If we have found an entire vector of loads and undefs, then return a large
5002 // load of the entire vector width starting at the base pointer. If we found
5003 // consecutive loads for the low half, generate a vzext_load node.
5004 if (LastLoadedElt == NumElems - 1) {
5005 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5006 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5007 LDBase->getPointerInfo(),
5008 LDBase->isVolatile(), LDBase->isNonTemporal(), 0);
5009 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5010 LDBase->getPointerInfo(),
5011 LDBase->isVolatile(), LDBase->isNonTemporal(),
5012 LDBase->getAlignment());
5013 } else if (NumElems == 4 && LastLoadedElt == 1 &&
5014 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5015 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5016 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5017 SDValue ResNode = DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys,
5019 LDBase->getMemOperand());
5020 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5026 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5027 DebugLoc dl = Op.getDebugLoc();
5029 EVT VT = Op.getValueType();
5030 EVT ExtVT = VT.getVectorElementType();
5031 unsigned NumElems = Op.getNumOperands();
5033 // Vectors containing all zeros can be matched by pxor and xorps later
5034 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5035 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5036 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5037 if (Op.getValueType() == MVT::v4i32 ||
5038 Op.getValueType() == MVT::v8i32)
5041 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
5044 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5045 // vectors or broken into v4i32 operations on 256-bit vectors.
5046 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5047 if (Op.getValueType() == MVT::v4i32)
5050 return getOnesVector(Op.getValueType(), DAG, dl);
5053 unsigned EVTBits = ExtVT.getSizeInBits();
5055 unsigned NumZero = 0;
5056 unsigned NumNonZero = 0;
5057 unsigned NonZeros = 0;
5058 bool IsAllConstants = true;
5059 SmallSet<SDValue, 8> Values;
5060 for (unsigned i = 0; i < NumElems; ++i) {
5061 SDValue Elt = Op.getOperand(i);
5062 if (Elt.getOpcode() == ISD::UNDEF)
5065 if (Elt.getOpcode() != ISD::Constant &&
5066 Elt.getOpcode() != ISD::ConstantFP)
5067 IsAllConstants = false;
5068 if (X86::isZeroNode(Elt))
5071 NonZeros |= (1 << i);
5076 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5077 if (NumNonZero == 0)
5078 return DAG.getUNDEF(VT);
5080 // Special case for single non-zero, non-undef, element.
5081 if (NumNonZero == 1) {
5082 unsigned Idx = CountTrailingZeros_32(NonZeros);
5083 SDValue Item = Op.getOperand(Idx);
5085 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5086 // the value are obviously zero, truncate the value to i32 and do the
5087 // insertion that way. Only do this if the value is non-constant or if the
5088 // value is a constant being inserted into element 0. It is cheaper to do
5089 // a constant pool load than it is to do a movd + shuffle.
5090 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5091 (!IsAllConstants || Idx == 0)) {
5092 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5094 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5095 EVT VecVT = MVT::v4i32;
5096 unsigned VecElts = 4;
5098 // Truncate the value (which may itself be a constant) to i32, and
5099 // convert it to a vector with movd (S2V+shuffle to zero extend).
5100 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5101 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5102 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5103 Subtarget->hasSSE2(), DAG);
5105 // Now we have our 32-bit value zero extended in the low element of
5106 // a vector. If Idx != 0, swizzle it into place.
5108 SmallVector<int, 4> Mask;
5109 Mask.push_back(Idx);
5110 for (unsigned i = 1; i != VecElts; ++i)
5112 Item = DAG.getVectorShuffle(VecVT, dl, Item,
5113 DAG.getUNDEF(Item.getValueType()),
5116 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item);
5120 // If we have a constant or non-constant insertion into the low element of
5121 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5122 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5123 // depending on what the source datatype is.
5126 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5127 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5128 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5129 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5130 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5131 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
5133 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5134 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5135 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!");
5136 EVT MiddleVT = MVT::v4i32;
5137 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
5138 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
5139 Subtarget->hasSSE2(), DAG);
5140 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5144 // Is it a vector logical left shift?
5145 if (NumElems == 2 && Idx == 1 &&
5146 X86::isZeroNode(Op.getOperand(0)) &&
5147 !X86::isZeroNode(Op.getOperand(1))) {
5148 unsigned NumBits = VT.getSizeInBits();
5149 return getVShift(true, VT,
5150 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5151 VT, Op.getOperand(1)),
5152 NumBits/2, DAG, *this, dl);
5155 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5158 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5159 // is a non-constant being inserted into an element other than the low one,
5160 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5161 // movd/movss) to move this into the low element, then shuffle it into
5163 if (EVTBits == 32) {
5164 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5166 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5167 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
5168 Subtarget->hasSSE2(), DAG);
5169 SmallVector<int, 8> MaskVec;
5170 for (unsigned i = 0; i < NumElems; i++)
5171 MaskVec.push_back(i == Idx ? 0 : 1);
5172 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5176 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5177 if (Values.size() == 1) {
5178 if (EVTBits == 32) {
5179 // Instead of a shuffle like this:
5180 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5181 // Check if it's possible to issue this instead.
5182 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5183 unsigned Idx = CountTrailingZeros_32(NonZeros);
5184 SDValue Item = Op.getOperand(Idx);
5185 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5186 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5191 // A vector full of immediates; various special cases are already
5192 // handled, so this is best done with a single constant-pool load.
5196 // For AVX-length vectors, build the individual 128-bit pieces and use
5197 // shuffles to put them in place.
5198 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) {
5199 SmallVector<SDValue, 32> V;
5200 for (unsigned i = 0; i < NumElems; ++i)
5201 V.push_back(Op.getOperand(i));
5203 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5205 // Build both the lower and upper subvector.
5206 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5207 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5210 // Recreate the wider vector with the lower and upper part.
5211 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower,
5212 DAG.getConstant(0, MVT::i32), DAG, dl);
5213 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32),
5217 // Let legalizer expand 2-wide build_vectors.
5218 if (EVTBits == 64) {
5219 if (NumNonZero == 1) {
5220 // One half is zero or undef.
5221 unsigned Idx = CountTrailingZeros_32(NonZeros);
5222 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5223 Op.getOperand(Idx));
5224 return getShuffleVectorZeroOrUndef(V2, Idx, true,
5225 Subtarget->hasSSE2(), DAG);
5230 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5231 if (EVTBits == 8 && NumElems == 16) {
5232 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5234 if (V.getNode()) return V;
5237 if (EVTBits == 16 && NumElems == 8) {
5238 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5240 if (V.getNode()) return V;
5243 // If element VT is == 32 bits, turn it into a number of shuffles.
5244 SmallVector<SDValue, 8> V;
5246 if (NumElems == 4 && NumZero > 0) {
5247 for (unsigned i = 0; i < 4; ++i) {
5248 bool isZero = !(NonZeros & (1 << i));
5250 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
5252 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5255 for (unsigned i = 0; i < 2; ++i) {
5256 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5259 V[i] = V[i*2]; // Must be a zero vector.
5262 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5265 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5268 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5273 SmallVector<int, 8> MaskVec;
5274 bool Reverse = (NonZeros & 0x3) == 2;
5275 for (unsigned i = 0; i < 2; ++i)
5276 MaskVec.push_back(Reverse ? 1-i : i);
5277 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5278 for (unsigned i = 0; i < 2; ++i)
5279 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
5280 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5283 if (Values.size() > 1 && VT.getSizeInBits() == 128) {
5284 // Check for a build vector of consecutive loads.
5285 for (unsigned i = 0; i < NumElems; ++i)
5286 V[i] = Op.getOperand(i);
5288 // Check for elements which are consecutive loads.
5289 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5293 // For SSE 4.1, use insertps to put the high elements into the low element.
5294 if (getSubtarget()->hasSSE41()) {
5296 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5297 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5299 Result = DAG.getUNDEF(VT);
5301 for (unsigned i = 1; i < NumElems; ++i) {
5302 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5303 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5304 Op.getOperand(i), DAG.getIntPtrConstant(i));
5309 // Otherwise, expand into a number of unpckl*, start by extending each of
5310 // our (non-undef) elements to the full vector width with the element in the
5311 // bottom slot of the vector (which generates no code for SSE).
5312 for (unsigned i = 0; i < NumElems; ++i) {
5313 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5314 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5316 V[i] = DAG.getUNDEF(VT);
5319 // Next, we iteratively mix elements, e.g. for v4f32:
5320 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5321 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5322 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5323 unsigned EltStride = NumElems >> 1;
5324 while (EltStride != 0) {
5325 for (unsigned i = 0; i < EltStride; ++i) {
5326 // If V[i+EltStride] is undef and this is the first round of mixing,
5327 // then it is safe to just drop this shuffle: V[i] is already in the
5328 // right place, the one element (since it's the first round) being
5329 // inserted as undef can be dropped. This isn't safe for successive
5330 // rounds because they will permute elements within both vectors.
5331 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5332 EltStride == NumElems/2)
5335 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5344 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place
5345 // them in a MMX register. This is better than doing a stack convert.
5346 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5347 DebugLoc dl = Op.getDebugLoc();
5348 EVT ResVT = Op.getValueType();
5350 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 ||
5351 ResVT == MVT::v8i16 || ResVT == MVT::v16i8);
5353 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0));
5354 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5355 InVec = Op.getOperand(1);
5356 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5357 unsigned NumElts = ResVT.getVectorNumElements();
5358 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5359 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp,
5360 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1));
5362 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec);
5363 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec);
5364 Mask[0] = 0; Mask[1] = 2;
5365 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask);
5367 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp);
5370 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5371 // to create 256-bit vectors from two other 128-bit ones.
5372 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5373 DebugLoc dl = Op.getDebugLoc();
5374 EVT ResVT = Op.getValueType();
5376 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide");
5378 SDValue V1 = Op.getOperand(0);
5379 SDValue V2 = Op.getOperand(1);
5380 unsigned NumElems = ResVT.getVectorNumElements();
5382 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1,
5383 DAG.getConstant(0, MVT::i32), DAG, dl);
5384 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5389 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
5390 EVT ResVT = Op.getValueType();
5392 assert(Op.getNumOperands() == 2);
5393 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) &&
5394 "Unsupported CONCAT_VECTORS for value type");
5396 // We support concatenate two MMX registers and place them in a MMX register.
5397 // This is better than doing a stack convert.
5398 if (ResVT.is128BitVector())
5399 return LowerMMXCONCAT_VECTORS(Op, DAG);
5401 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5402 // from two other 128-bit ones.
5403 return LowerAVXCONCAT_VECTORS(Op, DAG);
5406 // v8i16 shuffles - Prefer shuffles in the following order:
5407 // 1. [all] pshuflw, pshufhw, optional move
5408 // 2. [ssse3] 1 x pshufb
5409 // 3. [ssse3] 2 x pshufb + 1 x por
5410 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5412 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op,
5413 SelectionDAG &DAG) const {
5414 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5415 SDValue V1 = SVOp->getOperand(0);
5416 SDValue V2 = SVOp->getOperand(1);
5417 DebugLoc dl = SVOp->getDebugLoc();
5418 SmallVector<int, 8> MaskVals;
5420 // Determine if more than 1 of the words in each of the low and high quadwords
5421 // of the result come from the same quadword of one of the two inputs. Undef
5422 // mask values count as coming from any quadword, for better codegen.
5423 SmallVector<unsigned, 4> LoQuad(4);
5424 SmallVector<unsigned, 4> HiQuad(4);
5425 BitVector InputQuads(4);
5426 for (unsigned i = 0; i < 8; ++i) {
5427 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
5428 int EltIdx = SVOp->getMaskElt(i);
5429 MaskVals.push_back(EltIdx);
5438 InputQuads.set(EltIdx / 4);
5441 int BestLoQuad = -1;
5442 unsigned MaxQuad = 1;
5443 for (unsigned i = 0; i < 4; ++i) {
5444 if (LoQuad[i] > MaxQuad) {
5446 MaxQuad = LoQuad[i];
5450 int BestHiQuad = -1;
5452 for (unsigned i = 0; i < 4; ++i) {
5453 if (HiQuad[i] > MaxQuad) {
5455 MaxQuad = HiQuad[i];
5459 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5460 // of the two input vectors, shuffle them into one input vector so only a
5461 // single pshufb instruction is necessary. If There are more than 2 input
5462 // quads, disable the next transformation since it does not help SSSE3.
5463 bool V1Used = InputQuads[0] || InputQuads[1];
5464 bool V2Used = InputQuads[2] || InputQuads[3];
5465 if (Subtarget->hasSSSE3()) {
5466 if (InputQuads.count() == 2 && V1Used && V2Used) {
5467 BestLoQuad = InputQuads.find_first();
5468 BestHiQuad = InputQuads.find_next(BestLoQuad);
5470 if (InputQuads.count() > 2) {
5476 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5477 // the shuffle mask. If a quad is scored as -1, that means that it contains
5478 // words from all 4 input quadwords.
5480 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5481 SmallVector<int, 8> MaskV;
5482 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
5483 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
5484 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5485 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5486 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5487 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5489 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5490 // source words for the shuffle, to aid later transformations.
5491 bool AllWordsInNewV = true;
5492 bool InOrder[2] = { true, true };
5493 for (unsigned i = 0; i != 8; ++i) {
5494 int idx = MaskVals[i];
5496 InOrder[i/4] = false;
5497 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5499 AllWordsInNewV = false;
5503 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5504 if (AllWordsInNewV) {
5505 for (int i = 0; i != 8; ++i) {
5506 int idx = MaskVals[i];
5509 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5510 if ((idx != i) && idx < 4)
5512 if ((idx != i) && idx > 3)
5521 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5522 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5523 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5524 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5525 unsigned TargetMask = 0;
5526 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5527 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5528 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()):
5529 X86::getShufflePSHUFLWImmediate(NewV.getNode());
5530 V1 = NewV.getOperand(0);
5531 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5535 // If we have SSSE3, and all words of the result are from 1 input vector,
5536 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5537 // is present, fall back to case 4.
5538 if (Subtarget->hasSSSE3()) {
5539 SmallVector<SDValue,16> pshufbMask;
5541 // If we have elements from both input vectors, set the high bit of the
5542 // shuffle mask element to zero out elements that come from V2 in the V1
5543 // mask, and elements that come from V1 in the V2 mask, so that the two
5544 // results can be OR'd together.
5545 bool TwoInputs = V1Used && V2Used;
5546 for (unsigned i = 0; i != 8; ++i) {
5547 int EltIdx = MaskVals[i] * 2;
5548 if (TwoInputs && (EltIdx >= 16)) {
5549 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5550 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5553 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5554 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
5556 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5557 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5558 DAG.getNode(ISD::BUILD_VECTOR, dl,
5559 MVT::v16i8, &pshufbMask[0], 16));
5561 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5563 // Calculate the shuffle mask for the second input, shuffle it, and
5564 // OR it with the first shuffled input.
5566 for (unsigned i = 0; i != 8; ++i) {
5567 int EltIdx = MaskVals[i] * 2;
5569 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5570 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5573 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5574 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
5576 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5577 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5578 DAG.getNode(ISD::BUILD_VECTOR, dl,
5579 MVT::v16i8, &pshufbMask[0], 16));
5580 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5581 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5584 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5585 // and update MaskVals with new element order.
5586 BitVector InOrder(8);
5587 if (BestLoQuad >= 0) {
5588 SmallVector<int, 8> MaskV;
5589 for (int i = 0; i != 4; ++i) {
5590 int idx = MaskVals[i];
5592 MaskV.push_back(-1);
5594 } else if ((idx / 4) == BestLoQuad) {
5595 MaskV.push_back(idx & 3);
5598 MaskV.push_back(-1);
5601 for (unsigned i = 4; i != 8; ++i)
5603 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5606 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5607 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5609 X86::getShufflePSHUFLWImmediate(NewV.getNode()),
5613 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5614 // and update MaskVals with the new element order.
5615 if (BestHiQuad >= 0) {
5616 SmallVector<int, 8> MaskV;
5617 for (unsigned i = 0; i != 4; ++i)
5619 for (unsigned i = 4; i != 8; ++i) {
5620 int idx = MaskVals[i];
5622 MaskV.push_back(-1);
5624 } else if ((idx / 4) == BestHiQuad) {
5625 MaskV.push_back((idx & 3) + 4);
5628 MaskV.push_back(-1);
5631 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5634 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3())
5635 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5637 X86::getShufflePSHUFHWImmediate(NewV.getNode()),
5641 // In case BestHi & BestLo were both -1, which means each quadword has a word
5642 // from each of the four input quadwords, calculate the InOrder bitvector now
5643 // before falling through to the insert/extract cleanup.
5644 if (BestLoQuad == -1 && BestHiQuad == -1) {
5646 for (int i = 0; i != 8; ++i)
5647 if (MaskVals[i] < 0 || MaskVals[i] == i)
5651 // The other elements are put in the right place using pextrw and pinsrw.
5652 for (unsigned i = 0; i != 8; ++i) {
5655 int EltIdx = MaskVals[i];
5658 SDValue ExtOp = (EltIdx < 8)
5659 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5660 DAG.getIntPtrConstant(EltIdx))
5661 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5662 DAG.getIntPtrConstant(EltIdx - 8));
5663 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5664 DAG.getIntPtrConstant(i));
5669 // v16i8 shuffles - Prefer shuffles in the following order:
5670 // 1. [ssse3] 1 x pshufb
5671 // 2. [ssse3] 2 x pshufb + 1 x por
5672 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5674 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5676 const X86TargetLowering &TLI) {
5677 SDValue V1 = SVOp->getOperand(0);
5678 SDValue V2 = SVOp->getOperand(1);
5679 DebugLoc dl = SVOp->getDebugLoc();
5680 SmallVector<int, 16> MaskVals;
5681 SVOp->getMask(MaskVals);
5683 // If we have SSSE3, case 1 is generated when all result bytes come from
5684 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5685 // present, fall back to case 3.
5686 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
5689 for (unsigned i = 0; i < 16; ++i) {
5690 int EltIdx = MaskVals[i];
5699 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5700 if (TLI.getSubtarget()->hasSSSE3()) {
5701 SmallVector<SDValue,16> pshufbMask;
5703 // If all result elements are from one input vector, then only translate
5704 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5706 // Otherwise, we have elements from both input vectors, and must zero out
5707 // elements that come from V2 in the first mask, and V1 in the second mask
5708 // so that we can OR them together.
5709 bool TwoInputs = !(V1Only || V2Only);
5710 for (unsigned i = 0; i != 16; ++i) {
5711 int EltIdx = MaskVals[i];
5712 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
5713 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5716 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5718 // If all the elements are from V2, assign it to V1 and return after
5719 // building the first pshufb.
5722 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5723 DAG.getNode(ISD::BUILD_VECTOR, dl,
5724 MVT::v16i8, &pshufbMask[0], 16));
5728 // Calculate the shuffle mask for the second input, shuffle it, and
5729 // OR it with the first shuffled input.
5731 for (unsigned i = 0; i != 16; ++i) {
5732 int EltIdx = MaskVals[i];
5734 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
5737 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
5739 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5740 DAG.getNode(ISD::BUILD_VECTOR, dl,
5741 MVT::v16i8, &pshufbMask[0], 16));
5742 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5745 // No SSSE3 - Calculate in place words and then fix all out of place words
5746 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
5747 // the 16 different words that comprise the two doublequadword input vectors.
5748 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5749 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
5750 SDValue NewV = V2Only ? V2 : V1;
5751 for (int i = 0; i != 8; ++i) {
5752 int Elt0 = MaskVals[i*2];
5753 int Elt1 = MaskVals[i*2+1];
5755 // This word of the result is all undef, skip it.
5756 if (Elt0 < 0 && Elt1 < 0)
5759 // This word of the result is already in the correct place, skip it.
5760 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
5762 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
5765 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
5766 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
5769 // If Elt0 and Elt1 are defined, are consecutive, and can be load
5770 // using a single extract together, load it and store it.
5771 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
5772 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5773 DAG.getIntPtrConstant(Elt1 / 2));
5774 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5775 DAG.getIntPtrConstant(i));
5779 // If Elt1 is defined, extract it from the appropriate source. If the
5780 // source byte is not also odd, shift the extracted word left 8 bits
5781 // otherwise clear the bottom 8 bits if we need to do an or.
5783 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
5784 DAG.getIntPtrConstant(Elt1 / 2));
5785 if ((Elt1 & 1) == 0)
5786 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
5788 TLI.getShiftAmountTy(InsElt.getValueType())));
5790 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
5791 DAG.getConstant(0xFF00, MVT::i16));
5793 // If Elt0 is defined, extract it from the appropriate source. If the
5794 // source byte is not also even, shift the extracted word right 8 bits. If
5795 // Elt1 was also defined, OR the extracted values together before
5796 // inserting them in the result.
5798 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
5799 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
5800 if ((Elt0 & 1) != 0)
5801 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
5803 TLI.getShiftAmountTy(InsElt0.getValueType())));
5805 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
5806 DAG.getConstant(0x00FF, MVT::i16));
5807 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
5810 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
5811 DAG.getIntPtrConstant(i));
5813 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
5816 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
5817 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
5818 /// done when every pair / quad of shuffle mask elements point to elements in
5819 /// the right sequence. e.g.
5820 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
5822 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
5823 SelectionDAG &DAG, DebugLoc dl) {
5824 EVT VT = SVOp->getValueType(0);
5825 SDValue V1 = SVOp->getOperand(0);
5826 SDValue V2 = SVOp->getOperand(1);
5827 unsigned NumElems = VT.getVectorNumElements();
5828 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
5830 switch (VT.getSimpleVT().SimpleTy) {
5831 default: assert(false && "Unexpected!");
5832 case MVT::v4f32: NewVT = MVT::v2f64; break;
5833 case MVT::v4i32: NewVT = MVT::v2i64; break;
5834 case MVT::v8i16: NewVT = MVT::v4i32; break;
5835 case MVT::v16i8: NewVT = MVT::v4i32; break;
5838 int Scale = NumElems / NewWidth;
5839 SmallVector<int, 8> MaskVec;
5840 for (unsigned i = 0; i < NumElems; i += Scale) {
5842 for (int j = 0; j < Scale; ++j) {
5843 int EltIdx = SVOp->getMaskElt(i+j);
5847 StartIdx = EltIdx - (EltIdx % Scale);
5848 if (EltIdx != StartIdx + j)
5852 MaskVec.push_back(-1);
5854 MaskVec.push_back(StartIdx / Scale);
5857 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1);
5858 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2);
5859 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
5862 /// getVZextMovL - Return a zero-extending vector move low node.
5864 static SDValue getVZextMovL(EVT VT, EVT OpVT,
5865 SDValue SrcOp, SelectionDAG &DAG,
5866 const X86Subtarget *Subtarget, DebugLoc dl) {
5867 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
5868 LoadSDNode *LD = NULL;
5869 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
5870 LD = dyn_cast<LoadSDNode>(SrcOp);
5872 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
5874 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
5875 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
5876 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5877 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
5878 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
5880 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
5881 return DAG.getNode(ISD::BITCAST, dl, VT,
5882 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5883 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5891 return DAG.getNode(ISD::BITCAST, dl, VT,
5892 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
5893 DAG.getNode(ISD::BITCAST, dl,
5897 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector
5898 /// shuffle node referes to only one lane in the sources.
5899 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) {
5900 EVT VT = SVOp->getValueType(0);
5901 int NumElems = VT.getVectorNumElements();
5902 int HalfSize = NumElems/2;
5903 SmallVector<int, 16> M;
5905 bool MatchA = false, MatchB = false;
5907 for (int l = 0; l < NumElems*2; l += HalfSize) {
5908 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) {
5914 for (int l = 0; l < NumElems*2; l += HalfSize) {
5915 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) {
5921 return MatchA && MatchB;
5924 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
5925 /// which could not be matched by any known target speficic shuffle
5927 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5928 if (areShuffleHalvesWithinDisjointLanes(SVOp)) {
5929 // If each half of a vector shuffle node referes to only one lane in the
5930 // source vectors, extract each used 128-bit lane and shuffle them using
5931 // 128-bit shuffles. Then, concatenate the results. Otherwise leave
5932 // the work to the legalizer.
5933 DebugLoc dl = SVOp->getDebugLoc();
5934 EVT VT = SVOp->getValueType(0);
5935 int NumElems = VT.getVectorNumElements();
5936 int HalfSize = NumElems/2;
5938 // Extract the reference for each half
5939 int FstVecExtractIdx = 0, SndVecExtractIdx = 0;
5940 int FstVecOpNum = 0, SndVecOpNum = 0;
5941 for (int i = 0; i < HalfSize; ++i) {
5942 int Elt = SVOp->getMaskElt(i);
5943 if (SVOp->getMaskElt(i) < 0)
5945 FstVecOpNum = Elt/NumElems;
5946 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5949 for (int i = HalfSize; i < NumElems; ++i) {
5950 int Elt = SVOp->getMaskElt(i);
5951 if (SVOp->getMaskElt(i) < 0)
5953 SndVecOpNum = Elt/NumElems;
5954 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize;
5958 // Extract the subvectors
5959 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum),
5960 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl);
5961 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum),
5962 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl);
5964 // Generate 128-bit shuffles
5965 SmallVector<int, 16> MaskV1, MaskV2;
5966 for (int i = 0; i < HalfSize; ++i) {
5967 int Elt = SVOp->getMaskElt(i);
5968 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5970 for (int i = HalfSize; i < NumElems; ++i) {
5971 int Elt = SVOp->getMaskElt(i);
5972 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize);
5975 EVT NVT = V1.getValueType();
5976 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]);
5977 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]);
5979 // Concatenate the result back
5980 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1,
5981 DAG.getConstant(0, MVT::i32), DAG, dl);
5982 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32),
5989 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
5990 /// 4 elements, and match them with several different shuffle types.
5992 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
5993 SDValue V1 = SVOp->getOperand(0);
5994 SDValue V2 = SVOp->getOperand(1);
5995 DebugLoc dl = SVOp->getDebugLoc();
5996 EVT VT = SVOp->getValueType(0);
5998 assert(VT.getSizeInBits() == 128 && "Unsupported vector size");
6000 SmallVector<std::pair<int, int>, 8> Locs;
6002 SmallVector<int, 8> Mask1(4U, -1);
6003 SmallVector<int, 8> PermMask;
6004 SVOp->getMask(PermMask);
6008 for (unsigned i = 0; i != 4; ++i) {
6009 int Idx = PermMask[i];
6011 Locs[i] = std::make_pair(-1, -1);
6013 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6015 Locs[i] = std::make_pair(0, NumLo);
6019 Locs[i] = std::make_pair(1, NumHi);
6021 Mask1[2+NumHi] = Idx;
6027 if (NumLo <= 2 && NumHi <= 2) {
6028 // If no more than two elements come from either vector. This can be
6029 // implemented with two shuffles. First shuffle gather the elements.
6030 // The second shuffle, which takes the first shuffle as both of its
6031 // vector operands, put the elements into the right order.
6032 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6034 SmallVector<int, 8> Mask2(4U, -1);
6036 for (unsigned i = 0; i != 4; ++i) {
6037 if (Locs[i].first == -1)
6040 unsigned Idx = (i < 2) ? 0 : 4;
6041 Idx += Locs[i].first * 2 + Locs[i].second;
6046 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6047 } else if (NumLo == 3 || NumHi == 3) {
6048 // Otherwise, we must have three elements from one vector, call it X, and
6049 // one element from the other, call it Y. First, use a shufps to build an
6050 // intermediate vector with the one element from Y and the element from X
6051 // that will be in the same half in the final destination (the indexes don't
6052 // matter). Then, use a shufps to build the final vector, taking the half
6053 // containing the element from Y from the intermediate, and the other half
6056 // Normalize it so the 3 elements come from V1.
6057 CommuteVectorShuffleMask(PermMask, VT);
6061 // Find the element from V2.
6063 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6064 int Val = PermMask[HiIndex];
6071 Mask1[0] = PermMask[HiIndex];
6073 Mask1[2] = PermMask[HiIndex^1];
6075 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6078 Mask1[0] = PermMask[0];
6079 Mask1[1] = PermMask[1];
6080 Mask1[2] = HiIndex & 1 ? 6 : 4;
6081 Mask1[3] = HiIndex & 1 ? 4 : 6;
6082 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6084 Mask1[0] = HiIndex & 1 ? 2 : 0;
6085 Mask1[1] = HiIndex & 1 ? 0 : 2;
6086 Mask1[2] = PermMask[2];
6087 Mask1[3] = PermMask[3];
6092 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6096 // Break it into (shuffle shuffle_hi, shuffle_lo).
6099 SmallVector<int,8> LoMask(4U, -1);
6100 SmallVector<int,8> HiMask(4U, -1);
6102 SmallVector<int,8> *MaskPtr = &LoMask;
6103 unsigned MaskIdx = 0;
6106 for (unsigned i = 0; i != 4; ++i) {
6113 int Idx = PermMask[i];
6115 Locs[i] = std::make_pair(-1, -1);
6116 } else if (Idx < 4) {
6117 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6118 (*MaskPtr)[LoIdx] = Idx;
6121 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6122 (*MaskPtr)[HiIdx] = Idx;
6127 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6128 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6129 SmallVector<int, 8> MaskOps;
6130 for (unsigned i = 0; i != 4; ++i) {
6131 if (Locs[i].first == -1) {
6132 MaskOps.push_back(-1);
6134 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
6135 MaskOps.push_back(Idx);
6138 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6141 static bool MayFoldVectorLoad(SDValue V) {
6142 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6143 V = V.getOperand(0);
6144 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6145 V = V.getOperand(0);
6151 // FIXME: the version above should always be used. Since there's
6152 // a bug where several vector shuffles can't be folded because the
6153 // DAG is not updated during lowering and a node claims to have two
6154 // uses while it only has one, use this version, and let isel match
6155 // another instruction if the load really happens to have more than
6156 // one use. Remove this version after this bug get fixed.
6157 // rdar://8434668, PR8156
6158 static bool RelaxedMayFoldVectorLoad(SDValue V) {
6159 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6160 V = V.getOperand(0);
6161 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6162 V = V.getOperand(0);
6163 if (ISD::isNormalLoad(V.getNode()))
6168 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by
6169 /// a vector extract, and if both can be later optimized into a single load.
6170 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked
6171 /// here because otherwise a target specific shuffle node is going to be
6172 /// emitted for this shuffle, and the optimization not done.
6173 /// FIXME: This is probably not the best approach, but fix the problem
6174 /// until the right path is decided.
6176 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG,
6177 const TargetLowering &TLI) {
6178 EVT VT = V.getValueType();
6179 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V);
6181 // Be sure that the vector shuffle is present in a pattern like this:
6182 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr)
6186 SDNode *N = *V.getNode()->use_begin();
6187 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6190 SDValue EltNo = N->getOperand(1);
6191 if (!isa<ConstantSDNode>(EltNo))
6194 // If the bit convert changed the number of elements, it is unsafe
6195 // to examine the mask.
6196 bool HasShuffleIntoBitcast = false;
6197 if (V.getOpcode() == ISD::BITCAST) {
6198 EVT SrcVT = V.getOperand(0).getValueType();
6199 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements())
6201 V = V.getOperand(0);
6202 HasShuffleIntoBitcast = true;
6205 // Select the input vector, guarding against out of range extract vector.
6206 unsigned NumElems = VT.getVectorNumElements();
6207 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6208 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt);
6209 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1);
6211 // Skip one more bit_convert if necessary
6212 if (V.getOpcode() == ISD::BITCAST)
6213 V = V.getOperand(0);
6215 if (ISD::isNormalLoad(V.getNode())) {
6216 // Is the original load suitable?
6217 LoadSDNode *LN0 = cast<LoadSDNode>(V);
6219 // FIXME: avoid the multi-use bug that is preventing lots of
6220 // of foldings to be detected, this is still wrong of course, but
6221 // give the temporary desired behavior, and if it happens that
6222 // the load has real more uses, during isel it will not fold, and
6223 // will generate poor code.
6224 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse()
6227 if (!HasShuffleIntoBitcast)
6230 // If there's a bitcast before the shuffle, check if the load type and
6231 // alignment is valid.
6232 unsigned Align = LN0->getAlignment();
6234 TLI.getTargetData()->getABITypeAlignment(
6235 VT.getTypeForEVT(*DAG.getContext()));
6237 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
6245 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6246 EVT VT = Op.getValueType();
6248 // Canonizalize to v2f64.
6249 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6250 return DAG.getNode(ISD::BITCAST, dl, VT,
6251 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6256 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6258 SDValue V1 = Op.getOperand(0);
6259 SDValue V2 = Op.getOperand(1);
6260 EVT VT = Op.getValueType();
6262 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6264 if (HasSSE2 && VT == MVT::v2f64)
6265 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6267 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6268 return DAG.getNode(ISD::BITCAST, dl, VT,
6269 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6270 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6271 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6275 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6276 SDValue V1 = Op.getOperand(0);
6277 SDValue V2 = Op.getOperand(1);
6278 EVT VT = Op.getValueType();
6280 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6281 "unsupported shuffle type");
6283 if (V2.getOpcode() == ISD::UNDEF)
6287 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6290 static inline unsigned getSHUFPOpcode(EVT VT) {
6291 switch(VT.getSimpleVT().SimpleTy) {
6292 case MVT::v8i32: // Use fp unit for int unpack.
6294 case MVT::v4i32: // Use fp unit for int unpack.
6295 case MVT::v4f32: return X86ISD::SHUFPS;
6296 case MVT::v4i64: // Use fp unit for int unpack.
6298 case MVT::v2i64: // Use fp unit for int unpack.
6299 case MVT::v2f64: return X86ISD::SHUFPD;
6301 llvm_unreachable("Unknown type for shufp*");
6307 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6308 SDValue V1 = Op.getOperand(0);
6309 SDValue V2 = Op.getOperand(1);
6310 EVT VT = Op.getValueType();
6311 unsigned NumElems = VT.getVectorNumElements();
6313 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6314 // operand of these instructions is only memory, so check if there's a
6315 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6317 bool CanFoldLoad = false;
6319 // Trivial case, when V2 comes from a load.
6320 if (MayFoldVectorLoad(V2))
6323 // When V1 is a load, it can be folded later into a store in isel, example:
6324 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6326 // (MOVLPSmr addr:$src1, VR128:$src2)
6327 // So, recognize this potential and also use MOVLPS or MOVLPD
6328 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6331 // Both of them can't be memory operations though.
6332 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2))
6333 CanFoldLoad = false;
6336 if (HasSSE2 && NumElems == 2)
6337 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6340 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6343 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6344 // movl and movlp will both match v2i64, but v2i64 is never matched by
6345 // movl earlier because we make it strict to avoid messing with the movlp load
6346 // folding logic (see the code above getMOVLP call). Match it here then,
6347 // this is horrible, but will stay like this until we move all shuffle
6348 // matching to x86 specific nodes. Note that for the 1st condition all
6349 // types are matched with movsd.
6351 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6352 // as to remove this logic from here, as much as possible
6353 if (NumElems == 2 || !X86::isMOVLMask(SVOp))
6354 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6355 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6358 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6360 // Invert the operand order and use SHUFPS to match it.
6361 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1,
6362 X86::getShuffleSHUFImmediate(SVOp), DAG);
6365 static inline unsigned getUNPCKLOpcode(EVT VT) {
6366 switch(VT.getSimpleVT().SimpleTy) {
6367 case MVT::v4i32: return X86ISD::PUNPCKLDQ;
6368 case MVT::v2i64: return X86ISD::PUNPCKLQDQ;
6369 case MVT::v4f32: return X86ISD::UNPCKLPS;
6370 case MVT::v2f64: return X86ISD::UNPCKLPD;
6371 case MVT::v8i32: // Use fp unit for int unpack.
6372 case MVT::v8f32: return X86ISD::VUNPCKLPSY;
6373 case MVT::v4i64: // Use fp unit for int unpack.
6374 case MVT::v4f64: return X86ISD::VUNPCKLPDY;
6375 case MVT::v16i8: return X86ISD::PUNPCKLBW;
6376 case MVT::v8i16: return X86ISD::PUNPCKLWD;
6378 llvm_unreachable("Unknown type for unpckl");
6383 static inline unsigned getUNPCKHOpcode(EVT VT) {
6384 switch(VT.getSimpleVT().SimpleTy) {
6385 case MVT::v4i32: return X86ISD::PUNPCKHDQ;
6386 case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
6387 case MVT::v4f32: return X86ISD::UNPCKHPS;
6388 case MVT::v2f64: return X86ISD::UNPCKHPD;
6389 case MVT::v8i32: // Use fp unit for int unpack.
6390 case MVT::v8f32: return X86ISD::VUNPCKHPSY;
6391 case MVT::v4i64: // Use fp unit for int unpack.
6392 case MVT::v4f64: return X86ISD::VUNPCKHPDY;
6393 case MVT::v16i8: return X86ISD::PUNPCKHBW;
6394 case MVT::v8i16: return X86ISD::PUNPCKHWD;
6396 llvm_unreachable("Unknown type for unpckh");
6401 static inline unsigned getVPERMILOpcode(EVT VT) {
6402 switch(VT.getSimpleVT().SimpleTy) {
6404 case MVT::v4f32: return X86ISD::VPERMILPS;
6406 case MVT::v2f64: return X86ISD::VPERMILPD;
6408 case MVT::v8f32: return X86ISD::VPERMILPSY;
6410 case MVT::v4f64: return X86ISD::VPERMILPDY;
6412 llvm_unreachable("Unknown type for vpermil");
6417 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to
6418 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming
6419 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded.
6420 static bool isVectorBroadcast(SDValue &Op) {
6421 EVT VT = Op.getValueType();
6422 bool Is256 = VT.getSizeInBits() == 256;
6424 assert((VT.getSizeInBits() == 128 || Is256) &&
6425 "Unsupported type for vbroadcast node");
6428 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6429 V = V.getOperand(0);
6431 if (Is256 && !(V.hasOneUse() &&
6432 V.getOpcode() == ISD::INSERT_SUBVECTOR &&
6433 V.getOperand(0).getOpcode() == ISD::UNDEF))
6437 V = V.getOperand(1);
6442 // Check the source scalar_to_vector type. 256-bit broadcasts are
6443 // supported for 32/64-bit sizes, while 128-bit ones are only supported
6444 // for 32-bit scalars.
6445 if (V.getOpcode() != ISD::SCALAR_TO_VECTOR)
6448 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits();
6449 if (ScalarSize != 32 && ScalarSize != 64)
6451 if (!Is256 && ScalarSize == 64)
6454 V = V.getOperand(0);
6455 if (!MayFoldLoad(V))
6458 // Return the load node
6464 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
6465 const TargetLowering &TLI,
6466 const X86Subtarget *Subtarget) {
6467 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6468 EVT VT = Op.getValueType();
6469 DebugLoc dl = Op.getDebugLoc();
6470 SDValue V1 = Op.getOperand(0);
6471 SDValue V2 = Op.getOperand(1);
6473 if (isZeroShuffle(SVOp))
6474 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
6476 // Handle splat operations
6477 if (SVOp->isSplat()) {
6478 unsigned NumElem = VT.getVectorNumElements();
6479 int Size = VT.getSizeInBits();
6480 // Special case, this is the only place now where it's allowed to return
6481 // a vector_shuffle operation without using a target specific node, because
6482 // *hopefully* it will be optimized away by the dag combiner. FIXME: should
6483 // this be moved to DAGCombine instead?
6484 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
6487 // Use vbroadcast whenever the splat comes from a foldable load
6488 if (Subtarget->hasAVX() && isVectorBroadcast(V1))
6489 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1);
6491 // Handle splats by matching through known shuffle masks
6492 if ((Size == 128 && NumElem <= 4) ||
6493 (Size == 256 && NumElem < 8))
6496 // All remaning splats are promoted to target supported vector shuffles.
6497 return PromoteSplat(SVOp, DAG);
6500 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6502 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
6503 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6504 if (NewOp.getNode())
6505 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6506 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6507 // FIXME: Figure out a cleaner way to do this.
6508 // Try to make use of movq to zero out the top part.
6509 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6510 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6511 if (NewOp.getNode()) {
6512 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
6513 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
6514 DAG, Subtarget, dl);
6516 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6517 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6518 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
6519 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
6520 DAG, Subtarget, dl);
6527 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6528 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6529 SDValue V1 = Op.getOperand(0);
6530 SDValue V2 = Op.getOperand(1);
6531 EVT VT = Op.getValueType();
6532 DebugLoc dl = Op.getDebugLoc();
6533 unsigned NumElems = VT.getVectorNumElements();
6534 bool isMMX = VT.getSizeInBits() == 64;
6535 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6536 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6537 bool V1IsSplat = false;
6538 bool V2IsSplat = false;
6539 bool HasSSE2 = Subtarget->hasSSE2() || Subtarget->hasAVX();
6540 bool HasSSE3 = Subtarget->hasSSE3() || Subtarget->hasAVX();
6541 bool HasSSSE3 = Subtarget->hasSSSE3() || Subtarget->hasAVX();
6542 MachineFunction &MF = DAG.getMachineFunction();
6543 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize);
6545 // Shuffle operations on MMX not supported.
6549 // Vector shuffle lowering takes 3 steps:
6551 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6552 // narrowing and commutation of operands should be handled.
6553 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6555 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6556 // so the shuffle can be broken into other shuffles and the legalizer can
6557 // try the lowering again.
6559 // The general ideia is that no vector_shuffle operation should be left to
6560 // be matched during isel, all of them must be converted to a target specific
6563 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6564 // narrowing and commutation of operands should be handled. The actual code
6565 // doesn't include all of those, work in progress...
6566 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget);
6567 if (NewOp.getNode())
6570 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6571 // unpckh_undef). Only use pshufd if speed is more important than size.
6572 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp))
6573 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6574 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp))
6575 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6577 if (X86::isMOVDDUPMask(SVOp) && HasSSE3 && V2IsUndef &&
6578 RelaxedMayFoldVectorLoad(V1))
6579 return getMOVDDup(Op, dl, V1, DAG);
6581 if (X86::isMOVHLPS_v_undef_Mask(SVOp))
6582 return getMOVHighToLow(Op, dl, DAG);
6584 // Use to match splats
6585 if (HasSSE2 && X86::isUNPCKHMask(SVOp) && V2IsUndef &&
6586 (VT == MVT::v2f64 || VT == MVT::v2i64))
6587 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6589 if (X86::isPSHUFDMask(SVOp)) {
6590 // The actual implementation will match the mask in the if above and then
6591 // during isel it can match several different instructions, not only pshufd
6592 // as its name says, sad but true, emulate the behavior for now...
6593 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6594 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6596 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp);
6598 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6599 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6601 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1,
6605 // Check if this can be converted into a logical shift.
6606 bool isLeft = false;
6609 bool isShift = getSubtarget()->hasSSE2() &&
6610 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6611 if (isShift && ShVal.hasOneUse()) {
6612 // If the shifted value has multiple uses, it may be cheaper to use
6613 // v_set0 + movlhps or movhlps, etc.
6614 EVT EltVT = VT.getVectorElementType();
6615 ShAmt *= EltVT.getSizeInBits();
6616 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6619 if (X86::isMOVLMask(SVOp)) {
6622 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6623 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6624 if (!X86::isMOVLPMask(SVOp)) {
6625 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6626 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6628 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6629 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6633 // FIXME: fold these into legal mask.
6634 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp))
6635 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6637 if (X86::isMOVHLPSMask(SVOp))
6638 return getMOVHighToLow(Op, dl, DAG);
6640 if (X86::isMOVSHDUPMask(SVOp, Subtarget))
6641 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6643 if (X86::isMOVSLDUPMask(SVOp, Subtarget))
6644 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6646 if (X86::isMOVLPMask(SVOp))
6647 return getMOVLP(Op, dl, DAG, HasSSE2);
6649 if (ShouldXformToMOVHLPS(SVOp) ||
6650 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
6651 return CommuteVectorShuffle(SVOp, DAG);
6654 // No better options. Use a vshl / vsrl.
6655 EVT EltVT = VT.getVectorElementType();
6656 ShAmt *= EltVT.getSizeInBits();
6657 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6660 bool Commuted = false;
6661 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6662 // 1,1,1,1 -> v8i16 though.
6663 V1IsSplat = isSplatVector(V1.getNode());
6664 V2IsSplat = isSplatVector(V2.getNode());
6666 // Canonicalize the splat or undef, if present, to be on the RHS.
6667 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
6668 Op = CommuteVectorShuffle(SVOp, DAG);
6669 SVOp = cast<ShuffleVectorSDNode>(Op);
6670 V1 = SVOp->getOperand(0);
6671 V2 = SVOp->getOperand(1);
6672 std::swap(V1IsSplat, V2IsSplat);
6673 std::swap(V1IsUndef, V2IsUndef);
6677 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
6678 // Shuffling low element of v1 into undef, just return v1.
6681 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6682 // the instruction selector will not match, so get a canonical MOVL with
6683 // swapped operands to undo the commute.
6684 return getMOVL(DAG, dl, VT, V2, V1);
6687 if (X86::isUNPCKLMask(SVOp))
6688 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG);
6690 if (X86::isUNPCKHMask(SVOp))
6691 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG);
6694 // Normalize mask so all entries that point to V2 points to its first
6695 // element then try to match unpck{h|l} again. If match, return a
6696 // new vector_shuffle with the corrected mask.
6697 SDValue NewMask = NormalizeMask(SVOp, DAG);
6698 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
6699 if (NSVOp != SVOp) {
6700 if (X86::isUNPCKLMask(NSVOp, true)) {
6702 } else if (X86::isUNPCKHMask(NSVOp, true)) {
6709 // Commute is back and try unpck* again.
6710 // FIXME: this seems wrong.
6711 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
6712 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
6714 if (X86::isUNPCKLMask(NewSVOp))
6715 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG);
6717 if (X86::isUNPCKHMask(NewSVOp))
6718 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG);
6721 // Normalize the node to match x86 shuffle ops if needed
6722 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
6723 return CommuteVectorShuffle(SVOp, DAG);
6725 // The checks below are all present in isShuffleMaskLegal, but they are
6726 // inlined here right now to enable us to directly emit target specific
6727 // nodes, and remove one by one until they don't return Op anymore.
6728 SmallVector<int, 16> M;
6731 if (isPALIGNRMask(M, VT, HasSSSE3))
6732 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6733 X86::getShufflePALIGNRImmediate(SVOp),
6736 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6737 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6738 if (VT == MVT::v2f64)
6739 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG);
6740 if (VT == MVT::v2i64)
6741 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG);
6744 if (isPSHUFHWMask(M, VT))
6745 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6746 X86::getShufflePSHUFHWImmediate(SVOp),
6749 if (isPSHUFLWMask(M, VT))
6750 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6751 X86::getShufflePSHUFLWImmediate(SVOp),
6754 if (isSHUFPMask(M, VT))
6755 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6756 X86::getShuffleSHUFImmediate(SVOp), DAG);
6758 if (X86::isUNPCKL_v_undef_Mask(SVOp))
6759 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG);
6760 if (X86::isUNPCKH_v_undef_Mask(SVOp))
6761 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG);
6763 //===--------------------------------------------------------------------===//
6764 // Generate target specific nodes for 128 or 256-bit shuffles only
6765 // supported in the AVX instruction set.
6768 // Handle VMOVDDUPY permutations
6769 if (isMOVDDUPYMask(SVOp, Subtarget))
6770 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6772 // Handle VPERMILPS* permutations
6773 if (isVPERMILPSMask(M, VT, Subtarget))
6774 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6775 getShuffleVPERMILPSImmediate(SVOp), DAG);
6777 // Handle VPERMILPD* permutations
6778 if (isVPERMILPDMask(M, VT, Subtarget))
6779 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1,
6780 getShuffleVPERMILPDImmediate(SVOp), DAG);
6782 // Handle VPERM2F128 permutations
6783 if (isVPERM2F128Mask(M, VT, Subtarget))
6784 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2,
6785 getShuffleVPERM2F128Immediate(SVOp), DAG);
6787 // Handle VSHUFPSY permutations
6788 if (isVSHUFPSYMask(M, VT, Subtarget))
6789 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6790 getShuffleVSHUFPSYImmediate(SVOp), DAG);
6792 // Handle VSHUFPDY permutations
6793 if (isVSHUFPDYMask(M, VT, Subtarget))
6794 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2,
6795 getShuffleVSHUFPDYImmediate(SVOp), DAG);
6797 //===--------------------------------------------------------------------===//
6798 // Since no target specific shuffle was selected for this generic one,
6799 // lower it into other known shuffles. FIXME: this isn't true yet, but
6800 // this is the plan.
6803 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
6804 if (VT == MVT::v8i16) {
6805 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG);
6806 if (NewOp.getNode())
6810 if (VT == MVT::v16i8) {
6811 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
6812 if (NewOp.getNode())
6816 // Handle all 128-bit wide vectors with 4 elements, and match them with
6817 // several different shuffle types.
6818 if (NumElems == 4 && VT.getSizeInBits() == 128)
6819 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
6821 // Handle general 256-bit shuffles
6822 if (VT.is256BitVector())
6823 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
6829 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
6830 SelectionDAG &DAG) const {
6831 EVT VT = Op.getValueType();
6832 DebugLoc dl = Op.getDebugLoc();
6834 if (Op.getOperand(0).getValueType().getSizeInBits() != 128)
6837 if (VT.getSizeInBits() == 8) {
6838 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
6839 Op.getOperand(0), Op.getOperand(1));
6840 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6841 DAG.getValueType(VT));
6842 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6843 } else if (VT.getSizeInBits() == 16) {
6844 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6845 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
6847 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6848 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6849 DAG.getNode(ISD::BITCAST, dl,
6853 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
6854 Op.getOperand(0), Op.getOperand(1));
6855 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
6856 DAG.getValueType(VT));
6857 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6858 } else if (VT == MVT::f32) {
6859 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
6860 // the result back to FR32 register. It's only worth matching if the
6861 // result has a single use which is a store or a bitcast to i32. And in
6862 // the case of a store, it's not worth it if the index is a constant 0,
6863 // because a MOVSSmr can be used instead, which is smaller and faster.
6864 if (!Op.hasOneUse())
6866 SDNode *User = *Op.getNode()->use_begin();
6867 if ((User->getOpcode() != ISD::STORE ||
6868 (isa<ConstantSDNode>(Op.getOperand(1)) &&
6869 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
6870 (User->getOpcode() != ISD::BITCAST ||
6871 User->getValueType(0) != MVT::i32))
6873 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6874 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
6877 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
6878 } else if (VT == MVT::i32) {
6879 // ExtractPS works with constant index.
6880 if (isa<ConstantSDNode>(Op.getOperand(1)))
6888 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6889 SelectionDAG &DAG) const {
6890 if (!isa<ConstantSDNode>(Op.getOperand(1)))
6893 SDValue Vec = Op.getOperand(0);
6894 EVT VecVT = Vec.getValueType();
6896 // If this is a 256-bit vector result, first extract the 128-bit vector and
6897 // then extract the element from the 128-bit vector.
6898 if (VecVT.getSizeInBits() == 256) {
6899 DebugLoc dl = Op.getNode()->getDebugLoc();
6900 unsigned NumElems = VecVT.getVectorNumElements();
6901 SDValue Idx = Op.getOperand(1);
6902 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
6904 // Get the 128-bit vector.
6905 bool Upper = IdxVal >= NumElems/2;
6906 Vec = Extract128BitVector(Vec,
6907 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl);
6909 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
6910 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx);
6913 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length");
6915 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) {
6916 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
6921 EVT VT = Op.getValueType();
6922 DebugLoc dl = Op.getDebugLoc();
6923 // TODO: handle v16i8.
6924 if (VT.getSizeInBits() == 16) {
6925 SDValue Vec = Op.getOperand(0);
6926 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6928 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
6929 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
6930 DAG.getNode(ISD::BITCAST, dl,
6933 // Transform it so it match pextrw which produces a 32-bit result.
6934 EVT EltVT = MVT::i32;
6935 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
6936 Op.getOperand(0), Op.getOperand(1));
6937 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
6938 DAG.getValueType(VT));
6939 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
6940 } else if (VT.getSizeInBits() == 32) {
6941 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6945 // SHUFPS the element to the lowest double word, then movss.
6946 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
6947 EVT VVT = Op.getOperand(0).getValueType();
6948 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6949 DAG.getUNDEF(VVT), Mask);
6950 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6951 DAG.getIntPtrConstant(0));
6952 } else if (VT.getSizeInBits() == 64) {
6953 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
6954 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
6955 // to match extract_elt for f64.
6956 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
6960 // UNPCKHPD the element to the lowest double word, then movsd.
6961 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
6962 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
6963 int Mask[2] = { 1, -1 };
6964 EVT VVT = Op.getOperand(0).getValueType();
6965 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
6966 DAG.getUNDEF(VVT), Mask);
6967 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
6968 DAG.getIntPtrConstant(0));
6975 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
6976 SelectionDAG &DAG) const {
6977 EVT VT = Op.getValueType();
6978 EVT EltVT = VT.getVectorElementType();
6979 DebugLoc dl = Op.getDebugLoc();
6981 SDValue N0 = Op.getOperand(0);
6982 SDValue N1 = Op.getOperand(1);
6983 SDValue N2 = Op.getOperand(2);
6985 if (VT.getSizeInBits() == 256)
6988 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
6989 isa<ConstantSDNode>(N2)) {
6991 if (VT == MVT::v8i16)
6992 Opc = X86ISD::PINSRW;
6993 else if (VT == MVT::v16i8)
6994 Opc = X86ISD::PINSRB;
6996 Opc = X86ISD::PINSRB;
6998 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7000 if (N1.getValueType() != MVT::i32)
7001 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7002 if (N2.getValueType() != MVT::i32)
7003 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7004 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7005 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7006 // Bits [7:6] of the constant are the source select. This will always be
7007 // zero here. The DAG Combiner may combine an extract_elt index into these
7008 // bits. For example (insert (extract, 3), 2) could be matched by putting
7009 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7010 // Bits [5:4] of the constant are the destination select. This is the
7011 // value of the incoming immediate.
7012 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7013 // combine either bitwise AND or insert of float 0.0 to set these bits.
7014 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7015 // Create this as a scalar to vector..
7016 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7017 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7018 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
7019 // PINSR* works with constant index.
7026 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7027 EVT VT = Op.getValueType();
7028 EVT EltVT = VT.getVectorElementType();
7030 DebugLoc dl = Op.getDebugLoc();
7031 SDValue N0 = Op.getOperand(0);
7032 SDValue N1 = Op.getOperand(1);
7033 SDValue N2 = Op.getOperand(2);
7035 // If this is a 256-bit vector result, first extract the 128-bit vector,
7036 // insert the element into the extracted half and then place it back.
7037 if (VT.getSizeInBits() == 256) {
7038 if (!isa<ConstantSDNode>(N2))
7041 // Get the desired 128-bit vector half.
7042 unsigned NumElems = VT.getVectorNumElements();
7043 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7044 bool Upper = IdxVal >= NumElems/2;
7045 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32);
7046 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl);
7048 // Insert the element into the desired half.
7049 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V,
7050 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2);
7052 // Insert the changed part back to the 256-bit vector
7053 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl);
7056 if (Subtarget->hasSSE41() || Subtarget->hasAVX())
7057 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7059 if (EltVT == MVT::i8)
7062 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7063 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7064 // as its second argument.
7065 if (N1.getValueType() != MVT::i32)
7066 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7067 if (N2.getValueType() != MVT::i32)
7068 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7069 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7075 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
7076 LLVMContext *Context = DAG.getContext();
7077 DebugLoc dl = Op.getDebugLoc();
7078 EVT OpVT = Op.getValueType();
7080 // If this is a 256-bit vector result, first insert into a 128-bit
7081 // vector and then insert into the 256-bit vector.
7082 if (OpVT.getSizeInBits() > 128) {
7083 // Insert into a 128-bit vector.
7084 EVT VT128 = EVT::getVectorVT(*Context,
7085 OpVT.getVectorElementType(),
7086 OpVT.getVectorNumElements() / 2);
7088 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7090 // Insert the 128-bit vector.
7091 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op,
7092 DAG.getConstant(0, MVT::i32),
7096 if (Op.getValueType() == MVT::v1i64 &&
7097 Op.getOperand(0).getValueType() == MVT::i64)
7098 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7100 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7101 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 &&
7102 "Expected an SSE type!");
7103 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(),
7104 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7107 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7108 // a simple subregister reference or explicit instructions to grab
7109 // upper bits of a vector.
7111 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7112 if (Subtarget->hasAVX()) {
7113 DebugLoc dl = Op.getNode()->getDebugLoc();
7114 SDValue Vec = Op.getNode()->getOperand(0);
7115 SDValue Idx = Op.getNode()->getOperand(1);
7117 if (Op.getNode()->getValueType(0).getSizeInBits() == 128
7118 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) {
7119 return Extract128BitVector(Vec, Idx, DAG, dl);
7125 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7126 // simple superregister reference or explicit instructions to insert
7127 // the upper bits of a vector.
7129 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const {
7130 if (Subtarget->hasAVX()) {
7131 DebugLoc dl = Op.getNode()->getDebugLoc();
7132 SDValue Vec = Op.getNode()->getOperand(0);
7133 SDValue SubVec = Op.getNode()->getOperand(1);
7134 SDValue Idx = Op.getNode()->getOperand(2);
7136 if (Op.getNode()->getValueType(0).getSizeInBits() == 256
7137 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) {
7138 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl);
7144 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7145 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7146 // one of the above mentioned nodes. It has to be wrapped because otherwise
7147 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7148 // be used to form addressing mode. These wrapped nodes will be selected
7151 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7152 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7154 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7156 unsigned char OpFlag = 0;
7157 unsigned WrapperKind = X86ISD::Wrapper;
7158 CodeModel::Model M = getTargetMachine().getCodeModel();
7160 if (Subtarget->isPICStyleRIPRel() &&
7161 (M == CodeModel::Small || M == CodeModel::Kernel))
7162 WrapperKind = X86ISD::WrapperRIP;
7163 else if (Subtarget->isPICStyleGOT())
7164 OpFlag = X86II::MO_GOTOFF;
7165 else if (Subtarget->isPICStyleStubPIC())
7166 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7168 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7170 CP->getOffset(), OpFlag);
7171 DebugLoc DL = CP->getDebugLoc();
7172 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7173 // With PIC, the address is actually $g + Offset.
7175 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7176 DAG.getNode(X86ISD::GlobalBaseReg,
7177 DebugLoc(), getPointerTy()),
7184 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7185 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7187 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7189 unsigned char OpFlag = 0;
7190 unsigned WrapperKind = X86ISD::Wrapper;
7191 CodeModel::Model M = getTargetMachine().getCodeModel();
7193 if (Subtarget->isPICStyleRIPRel() &&
7194 (M == CodeModel::Small || M == CodeModel::Kernel))
7195 WrapperKind = X86ISD::WrapperRIP;
7196 else if (Subtarget->isPICStyleGOT())
7197 OpFlag = X86II::MO_GOTOFF;
7198 else if (Subtarget->isPICStyleStubPIC())
7199 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7201 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7203 DebugLoc DL = JT->getDebugLoc();
7204 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7206 // With PIC, the address is actually $g + Offset.
7208 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7209 DAG.getNode(X86ISD::GlobalBaseReg,
7210 DebugLoc(), getPointerTy()),
7217 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7218 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7220 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7222 unsigned char OpFlag = 0;
7223 unsigned WrapperKind = X86ISD::Wrapper;
7224 CodeModel::Model M = getTargetMachine().getCodeModel();
7226 if (Subtarget->isPICStyleRIPRel() &&
7227 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7228 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7229 OpFlag = X86II::MO_GOTPCREL;
7230 WrapperKind = X86ISD::WrapperRIP;
7231 } else if (Subtarget->isPICStyleGOT()) {
7232 OpFlag = X86II::MO_GOT;
7233 } else if (Subtarget->isPICStyleStubPIC()) {
7234 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7235 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7236 OpFlag = X86II::MO_DARWIN_NONLAZY;
7239 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7241 DebugLoc DL = Op.getDebugLoc();
7242 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7245 // With PIC, the address is actually $g + Offset.
7246 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7247 !Subtarget->is64Bit()) {
7248 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7249 DAG.getNode(X86ISD::GlobalBaseReg,
7250 DebugLoc(), getPointerTy()),
7254 // For symbols that require a load from a stub to get the address, emit the
7256 if (isGlobalStubReference(OpFlag))
7257 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7258 MachinePointerInfo::getGOT(), false, false, 0);
7264 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7265 // Create the TargetBlockAddressAddress node.
7266 unsigned char OpFlags =
7267 Subtarget->ClassifyBlockAddressReference();
7268 CodeModel::Model M = getTargetMachine().getCodeModel();
7269 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7270 DebugLoc dl = Op.getDebugLoc();
7271 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(),
7272 /*isTarget=*/true, OpFlags);
7274 if (Subtarget->isPICStyleRIPRel() &&
7275 (M == CodeModel::Small || M == CodeModel::Kernel))
7276 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7278 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7280 // With PIC, the address is actually $g + Offset.
7281 if (isGlobalRelativeToPICBase(OpFlags)) {
7282 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7283 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7291 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7293 SelectionDAG &DAG) const {
7294 // Create the TargetGlobalAddress node, folding in the constant
7295 // offset if it is legal.
7296 unsigned char OpFlags =
7297 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7298 CodeModel::Model M = getTargetMachine().getCodeModel();
7300 if (OpFlags == X86II::MO_NO_FLAG &&
7301 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7302 // A direct static reference to a global.
7303 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7306 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7309 if (Subtarget->isPICStyleRIPRel() &&
7310 (M == CodeModel::Small || M == CodeModel::Kernel))
7311 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7313 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7315 // With PIC, the address is actually $g + Offset.
7316 if (isGlobalRelativeToPICBase(OpFlags)) {
7317 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7318 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7322 // For globals that require a load from a stub to get the address, emit the
7324 if (isGlobalStubReference(OpFlags))
7325 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7326 MachinePointerInfo::getGOT(), false, false, 0);
7328 // If there was a non-zero offset that we didn't fold, create an explicit
7331 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7332 DAG.getConstant(Offset, getPointerTy()));
7338 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7339 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7340 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7341 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7345 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7346 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7347 unsigned char OperandFlags) {
7348 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7349 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7350 DebugLoc dl = GA->getDebugLoc();
7351 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7352 GA->getValueType(0),
7356 SDValue Ops[] = { Chain, TGA, *InFlag };
7357 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
7359 SDValue Ops[] = { Chain, TGA };
7360 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
7363 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7364 MFI->setAdjustsStack(true);
7366 SDValue Flag = Chain.getValue(1);
7367 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7370 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7372 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7375 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7376 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7377 DAG.getNode(X86ISD::GlobalBaseReg,
7378 DebugLoc(), PtrVT), InFlag);
7379 InFlag = Chain.getValue(1);
7381 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7384 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7386 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7388 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7389 X86::RAX, X86II::MO_TLSGD);
7392 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
7393 // "local exec" model.
7394 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7395 const EVT PtrVT, TLSModel::Model model,
7397 DebugLoc dl = GA->getDebugLoc();
7399 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7400 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7401 is64Bit ? 257 : 256));
7403 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7404 DAG.getIntPtrConstant(0),
7405 MachinePointerInfo(Ptr), false, false, 0);
7407 unsigned char OperandFlags = 0;
7408 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7410 unsigned WrapperKind = X86ISD::Wrapper;
7411 if (model == TLSModel::LocalExec) {
7412 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7413 } else if (is64Bit) {
7414 assert(model == TLSModel::InitialExec);
7415 OperandFlags = X86II::MO_GOTTPOFF;
7416 WrapperKind = X86ISD::WrapperRIP;
7418 assert(model == TLSModel::InitialExec);
7419 OperandFlags = X86II::MO_INDNTPOFF;
7422 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
7424 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7425 GA->getValueType(0),
7426 GA->getOffset(), OperandFlags);
7427 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7429 if (model == TLSModel::InitialExec)
7430 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7431 MachinePointerInfo::getGOT(), false, false, 0);
7433 // The address of the thread local variable is the add of the thread
7434 // pointer with the offset of the variable.
7435 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7439 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7441 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7442 const GlobalValue *GV = GA->getGlobal();
7444 if (Subtarget->isTargetELF()) {
7445 // TODO: implement the "local dynamic" model
7446 // TODO: implement the "initial exec"model for pic executables
7448 // If GV is an alias then use the aliasee for determining
7449 // thread-localness.
7450 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7451 GV = GA->resolveAliasedGlobal(false);
7453 TLSModel::Model model
7454 = getTLSModel(GV, getTargetMachine().getRelocationModel());
7457 case TLSModel::GeneralDynamic:
7458 case TLSModel::LocalDynamic: // not implemented
7459 if (Subtarget->is64Bit())
7460 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7461 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7463 case TLSModel::InitialExec:
7464 case TLSModel::LocalExec:
7465 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7466 Subtarget->is64Bit());
7468 } else if (Subtarget->isTargetDarwin()) {
7469 // Darwin only has one model of TLS. Lower to that.
7470 unsigned char OpFlag = 0;
7471 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7472 X86ISD::WrapperRIP : X86ISD::Wrapper;
7474 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7476 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7477 !Subtarget->is64Bit();
7479 OpFlag = X86II::MO_TLVP_PIC_BASE;
7481 OpFlag = X86II::MO_TLVP;
7482 DebugLoc DL = Op.getDebugLoc();
7483 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7484 GA->getValueType(0),
7485 GA->getOffset(), OpFlag);
7486 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7488 // With PIC32, the address is actually $g + Offset.
7490 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7491 DAG.getNode(X86ISD::GlobalBaseReg,
7492 DebugLoc(), getPointerTy()),
7495 // Lowering the machine isd will make sure everything is in the right
7497 SDValue Chain = DAG.getEntryNode();
7498 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7499 SDValue Args[] = { Chain, Offset };
7500 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7502 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7503 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7504 MFI->setAdjustsStack(true);
7506 // And our return value (tls address) is in the standard call return value
7508 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7509 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
7513 "TLS not implemented for this target.");
7515 llvm_unreachable("Unreachable");
7520 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and
7521 /// take a 2 x i32 value to shift plus a shift amount.
7522 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const {
7523 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7524 EVT VT = Op.getValueType();
7525 unsigned VTBits = VT.getSizeInBits();
7526 DebugLoc dl = Op.getDebugLoc();
7527 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7528 SDValue ShOpLo = Op.getOperand(0);
7529 SDValue ShOpHi = Op.getOperand(1);
7530 SDValue ShAmt = Op.getOperand(2);
7531 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7532 DAG.getConstant(VTBits - 1, MVT::i8))
7533 : DAG.getConstant(0, VT);
7536 if (Op.getOpcode() == ISD::SHL_PARTS) {
7537 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7538 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7540 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7541 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7544 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7545 DAG.getConstant(VTBits, MVT::i8));
7546 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7547 AndNode, DAG.getConstant(0, MVT::i8));
7550 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7551 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7552 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7554 if (Op.getOpcode() == ISD::SHL_PARTS) {
7555 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7556 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7558 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7559 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7562 SDValue Ops[2] = { Lo, Hi };
7563 return DAG.getMergeValues(Ops, 2, dl);
7566 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7567 SelectionDAG &DAG) const {
7568 EVT SrcVT = Op.getOperand(0).getValueType();
7570 if (SrcVT.isVector())
7573 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7574 "Unknown SINT_TO_FP to lower!");
7576 // These are really Legal; return the operand so the caller accepts it as
7578 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7580 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7581 Subtarget->is64Bit()) {
7585 DebugLoc dl = Op.getDebugLoc();
7586 unsigned Size = SrcVT.getSizeInBits()/8;
7587 MachineFunction &MF = DAG.getMachineFunction();
7588 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7589 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7590 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7592 MachinePointerInfo::getFixedStack(SSFI),
7594 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7597 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7599 SelectionDAG &DAG) const {
7601 DebugLoc DL = Op.getDebugLoc();
7603 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7605 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7607 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7609 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7611 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7612 MachineMemOperand *MMO;
7614 int SSFI = FI->getIndex();
7616 DAG.getMachineFunction()
7617 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7618 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7620 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7621 StackSlot = StackSlot.getOperand(1);
7623 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7624 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7626 Tys, Ops, array_lengthof(Ops),
7630 Chain = Result.getValue(1);
7631 SDValue InFlag = Result.getValue(2);
7633 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7634 // shouldn't be necessary except that RFP cannot be live across
7635 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7636 MachineFunction &MF = DAG.getMachineFunction();
7637 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7638 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7639 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7640 Tys = DAG.getVTList(MVT::Other);
7642 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7644 MachineMemOperand *MMO =
7645 DAG.getMachineFunction()
7646 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7647 MachineMemOperand::MOStore, SSFISize, SSFISize);
7649 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7650 Ops, array_lengthof(Ops),
7651 Op.getValueType(), MMO);
7652 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7653 MachinePointerInfo::getFixedStack(SSFI),
7660 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7661 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7662 SelectionDAG &DAG) const {
7663 // This algorithm is not obvious. Here it is in C code, more or less:
7665 double uint64_to_double( uint32_t hi, uint32_t lo ) {
7666 static const __m128i exp = { 0x4330000045300000ULL, 0 };
7667 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
7669 // Copy ints to xmm registers.
7670 __m128i xh = _mm_cvtsi32_si128( hi );
7671 __m128i xl = _mm_cvtsi32_si128( lo );
7673 // Combine into low half of a single xmm register.
7674 __m128i x = _mm_unpacklo_epi32( xh, xl );
7678 // Merge in appropriate exponents to give the integer bits the right
7680 x = _mm_unpacklo_epi32( x, exp );
7682 // Subtract away the biases to deal with the IEEE-754 double precision
7684 d = _mm_sub_pd( (__m128d) x, bias );
7686 // All conversions up to here are exact. The correctly rounded result is
7687 // calculated using the current rounding mode using the following
7689 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
7690 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
7691 // store doesn't really need to be here (except
7692 // maybe to zero the other double)
7697 DebugLoc dl = Op.getDebugLoc();
7698 LLVMContext *Context = DAG.getContext();
7700 // Build some magic constants.
7701 std::vector<Constant*> CV0;
7702 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
7703 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
7704 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7705 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
7706 Constant *C0 = ConstantVector::get(CV0);
7707 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
7709 std::vector<Constant*> CV1;
7711 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
7713 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
7714 Constant *C1 = ConstantVector::get(CV1);
7715 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
7717 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7718 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7720 DAG.getIntPtrConstant(1)));
7721 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7722 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
7724 DAG.getIntPtrConstant(0)));
7725 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
7726 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
7727 MachinePointerInfo::getConstantPool(),
7729 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
7730 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2);
7731 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
7732 MachinePointerInfo::getConstantPool(),
7734 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
7736 // Add the halves; easiest way is to swap them into another reg first.
7737 int ShufMask[2] = { 1, -1 };
7738 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
7739 DAG.getUNDEF(MVT::v2f64), ShufMask);
7740 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
7741 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
7742 DAG.getIntPtrConstant(0));
7745 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
7746 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
7747 SelectionDAG &DAG) const {
7748 DebugLoc dl = Op.getDebugLoc();
7749 // FP constant to bias correct the final result.
7750 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
7753 // Load the 32-bit value into an XMM register.
7754 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
7757 // Zero out the upper parts of the register.
7758 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasSSE2(), DAG);
7760 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7761 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
7762 DAG.getIntPtrConstant(0));
7764 // Or the load with the bias.
7765 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
7766 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7767 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7769 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
7770 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
7771 MVT::v2f64, Bias)));
7772 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7773 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
7774 DAG.getIntPtrConstant(0));
7776 // Subtract the bias.
7777 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
7779 // Handle final rounding.
7780 EVT DestVT = Op.getValueType();
7782 if (DestVT.bitsLT(MVT::f64)) {
7783 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
7784 DAG.getIntPtrConstant(0));
7785 } else if (DestVT.bitsGT(MVT::f64)) {
7786 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
7789 // Handle final rounding.
7793 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
7794 SelectionDAG &DAG) const {
7795 SDValue N0 = Op.getOperand(0);
7796 DebugLoc dl = Op.getDebugLoc();
7798 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
7799 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
7800 // the optimization here.
7801 if (DAG.SignBitIsZero(N0))
7802 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
7804 EVT SrcVT = N0.getValueType();
7805 EVT DstVT = Op.getValueType();
7806 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
7807 return LowerUINT_TO_FP_i64(Op, DAG);
7808 else if (SrcVT == MVT::i32 && X86ScalarSSEf64)
7809 return LowerUINT_TO_FP_i32(Op, DAG);
7811 // Make a 64-bit buffer, and use it to build an FILD.
7812 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
7813 if (SrcVT == MVT::i32) {
7814 SDValue WordOff = DAG.getConstant(4, getPointerTy());
7815 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
7816 getPointerTy(), StackSlot, WordOff);
7817 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7818 StackSlot, MachinePointerInfo(),
7820 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
7821 OffsetSlot, MachinePointerInfo(),
7823 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
7827 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
7828 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7829 StackSlot, MachinePointerInfo(),
7831 // For i64 source, we need to add the appropriate power of 2 if the input
7832 // was negative. This is the same as the optimization in
7833 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
7834 // we must be careful to do the computation in x87 extended precision, not
7835 // in SSE. (The generic code can't know it's OK to do this, or how to.)
7836 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
7837 MachineMemOperand *MMO =
7838 DAG.getMachineFunction()
7839 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7840 MachineMemOperand::MOLoad, 8, 8);
7842 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
7843 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
7844 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
7847 APInt FF(32, 0x5F800000ULL);
7849 // Check whether the sign bit is set.
7850 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
7851 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
7854 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
7855 SDValue FudgePtr = DAG.getConstantPool(
7856 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
7859 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
7860 SDValue Zero = DAG.getIntPtrConstant(0);
7861 SDValue Four = DAG.getIntPtrConstant(4);
7862 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
7864 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
7866 // Load the value out, extending it from f32 to f80.
7867 // FIXME: Avoid the extend by constructing the right constant pool?
7868 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
7869 FudgePtr, MachinePointerInfo::getConstantPool(),
7870 MVT::f32, false, false, 4);
7871 // Extend everything to 80 bits to force it to be done on x87.
7872 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
7873 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
7876 std::pair<SDValue,SDValue> X86TargetLowering::
7877 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
7878 DebugLoc DL = Op.getDebugLoc();
7880 EVT DstTy = Op.getValueType();
7883 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
7887 assert(DstTy.getSimpleVT() <= MVT::i64 &&
7888 DstTy.getSimpleVT() >= MVT::i16 &&
7889 "Unknown FP_TO_SINT to lower!");
7891 // These are really Legal.
7892 if (DstTy == MVT::i32 &&
7893 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7894 return std::make_pair(SDValue(), SDValue());
7895 if (Subtarget->is64Bit() &&
7896 DstTy == MVT::i64 &&
7897 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
7898 return std::make_pair(SDValue(), SDValue());
7900 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
7902 MachineFunction &MF = DAG.getMachineFunction();
7903 unsigned MemSize = DstTy.getSizeInBits()/8;
7904 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7905 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7910 switch (DstTy.getSimpleVT().SimpleTy) {
7911 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
7912 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
7913 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
7914 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
7917 SDValue Chain = DAG.getEntryNode();
7918 SDValue Value = Op.getOperand(0);
7919 EVT TheVT = Op.getOperand(0).getValueType();
7920 if (isScalarFPTypeInSSEReg(TheVT)) {
7921 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
7922 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
7923 MachinePointerInfo::getFixedStack(SSFI),
7925 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
7927 Chain, StackSlot, DAG.getValueType(TheVT)
7930 MachineMemOperand *MMO =
7931 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7932 MachineMemOperand::MOLoad, MemSize, MemSize);
7933 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
7935 Chain = Value.getValue(1);
7936 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
7937 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7940 MachineMemOperand *MMO =
7941 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7942 MachineMemOperand::MOStore, MemSize, MemSize);
7944 // Build the FP_TO_INT*_IN_MEM
7945 SDValue Ops[] = { Chain, Value, StackSlot };
7946 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
7947 Ops, 3, DstTy, MMO);
7949 return std::make_pair(FIST, StackSlot);
7952 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
7953 SelectionDAG &DAG) const {
7954 if (Op.getValueType().isVector())
7957 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
7958 SDValue FIST = Vals.first, StackSlot = Vals.second;
7959 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
7960 if (FIST.getNode() == 0) return Op;
7963 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7964 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7967 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
7968 SelectionDAG &DAG) const {
7969 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
7970 SDValue FIST = Vals.first, StackSlot = Vals.second;
7971 assert(FIST.getNode() && "Unexpected failure");
7974 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
7975 FIST, StackSlot, MachinePointerInfo(), false, false, 0);
7978 SDValue X86TargetLowering::LowerFABS(SDValue Op,
7979 SelectionDAG &DAG) const {
7980 LLVMContext *Context = DAG.getContext();
7981 DebugLoc dl = Op.getDebugLoc();
7982 EVT VT = Op.getValueType();
7985 EltVT = VT.getVectorElementType();
7986 std::vector<Constant*> CV;
7987 if (EltVT == MVT::f64) {
7988 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
7992 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
7998 Constant *C = ConstantVector::get(CV);
7999 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8000 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8001 MachinePointerInfo::getConstantPool(),
8003 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8006 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8007 LLVMContext *Context = DAG.getContext();
8008 DebugLoc dl = Op.getDebugLoc();
8009 EVT VT = Op.getValueType();
8012 EltVT = VT.getVectorElementType();
8013 std::vector<Constant*> CV;
8014 if (EltVT == MVT::f64) {
8015 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8019 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8025 Constant *C = ConstantVector::get(CV);
8026 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8027 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8028 MachinePointerInfo::getConstantPool(),
8030 if (VT.isVector()) {
8031 return DAG.getNode(ISD::BITCAST, dl, VT,
8032 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
8033 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8035 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask)));
8037 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8041 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8042 LLVMContext *Context = DAG.getContext();
8043 SDValue Op0 = Op.getOperand(0);
8044 SDValue Op1 = Op.getOperand(1);
8045 DebugLoc dl = Op.getDebugLoc();
8046 EVT VT = Op.getValueType();
8047 EVT SrcVT = Op1.getValueType();
8049 // If second operand is smaller, extend it first.
8050 if (SrcVT.bitsLT(VT)) {
8051 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8054 // And if it is bigger, shrink it first.
8055 if (SrcVT.bitsGT(VT)) {
8056 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8060 // At this point the operands and the result should have the same
8061 // type, and that won't be f80 since that is not custom lowered.
8063 // First get the sign bit of second operand.
8064 std::vector<Constant*> CV;
8065 if (SrcVT == MVT::f64) {
8066 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8067 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8069 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8070 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8071 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8072 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8074 Constant *C = ConstantVector::get(CV);
8075 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8076 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8077 MachinePointerInfo::getConstantPool(),
8079 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8081 // Shift sign bit right or left if the two operands have different types.
8082 if (SrcVT.bitsGT(VT)) {
8083 // Op0 is MVT::f32, Op1 is MVT::f64.
8084 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8085 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8086 DAG.getConstant(32, MVT::i32));
8087 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8088 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8089 DAG.getIntPtrConstant(0));
8092 // Clear first operand sign bit.
8094 if (VT == MVT::f64) {
8095 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8096 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8098 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8099 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8100 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8101 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8103 C = ConstantVector::get(CV);
8104 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8105 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8106 MachinePointerInfo::getConstantPool(),
8108 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8110 // Or the value with the sign bit.
8111 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8114 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const {
8115 SDValue N0 = Op.getOperand(0);
8116 DebugLoc dl = Op.getDebugLoc();
8117 EVT VT = Op.getValueType();
8119 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8120 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8121 DAG.getConstant(1, VT));
8122 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8125 /// Emit nodes that will be selected as "test Op0,Op0", or something
8127 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8128 SelectionDAG &DAG) const {
8129 DebugLoc dl = Op.getDebugLoc();
8131 // CF and OF aren't always set the way we want. Determine which
8132 // of these we need.
8133 bool NeedCF = false;
8134 bool NeedOF = false;
8137 case X86::COND_A: case X86::COND_AE:
8138 case X86::COND_B: case X86::COND_BE:
8141 case X86::COND_G: case X86::COND_GE:
8142 case X86::COND_L: case X86::COND_LE:
8143 case X86::COND_O: case X86::COND_NO:
8148 // See if we can use the EFLAGS value from the operand instead of
8149 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8150 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8151 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8152 // Emit a CMP with 0, which is the TEST pattern.
8153 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8154 DAG.getConstant(0, Op.getValueType()));
8156 unsigned Opcode = 0;
8157 unsigned NumOperands = 0;
8158 switch (Op.getNode()->getOpcode()) {
8160 // Due to an isel shortcoming, be conservative if this add is likely to be
8161 // selected as part of a load-modify-store instruction. When the root node
8162 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8163 // uses of other nodes in the match, such as the ADD in this case. This
8164 // leads to the ADD being left around and reselected, with the result being
8165 // two adds in the output. Alas, even if none our users are stores, that
8166 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8167 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8168 // climbing the DAG back to the root, and it doesn't seem to be worth the
8170 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8171 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8172 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC)
8175 if (ConstantSDNode *C =
8176 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
8177 // An add of one will be selected as an INC.
8178 if (C->getAPIntValue() == 1) {
8179 Opcode = X86ISD::INC;
8184 // An add of negative one (subtract of one) will be selected as a DEC.
8185 if (C->getAPIntValue().isAllOnesValue()) {
8186 Opcode = X86ISD::DEC;
8192 // Otherwise use a regular EFLAGS-setting add.
8193 Opcode = X86ISD::ADD;
8197 // If the primary and result isn't used, don't bother using X86ISD::AND,
8198 // because a TEST instruction will be better.
8199 bool NonFlagUse = false;
8200 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8201 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8203 unsigned UOpNo = UI.getOperandNo();
8204 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8205 // Look pass truncate.
8206 UOpNo = User->use_begin().getOperandNo();
8207 User = *User->use_begin();
8210 if (User->getOpcode() != ISD::BRCOND &&
8211 User->getOpcode() != ISD::SETCC &&
8212 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) {
8225 // Due to the ISEL shortcoming noted above, be conservative if this op is
8226 // likely to be selected as part of a load-modify-store instruction.
8227 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8228 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8229 if (UI->getOpcode() == ISD::STORE)
8232 // Otherwise use a regular EFLAGS-setting instruction.
8233 switch (Op.getNode()->getOpcode()) {
8234 default: llvm_unreachable("unexpected operator!");
8235 case ISD::SUB: Opcode = X86ISD::SUB; break;
8236 case ISD::OR: Opcode = X86ISD::OR; break;
8237 case ISD::XOR: Opcode = X86ISD::XOR; break;
8238 case ISD::AND: Opcode = X86ISD::AND; break;
8250 return SDValue(Op.getNode(), 1);
8257 // Emit a CMP with 0, which is the TEST pattern.
8258 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8259 DAG.getConstant(0, Op.getValueType()));
8261 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
8262 SmallVector<SDValue, 4> Ops;
8263 for (unsigned i = 0; i != NumOperands; ++i)
8264 Ops.push_back(Op.getOperand(i));
8266 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
8267 DAG.ReplaceAllUsesWith(Op, New);
8268 return SDValue(New.getNode(), 1);
8271 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
8273 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
8274 SelectionDAG &DAG) const {
8275 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
8276 if (C->getAPIntValue() == 0)
8277 return EmitTest(Op0, X86CC, DAG);
8279 DebugLoc dl = Op0.getDebugLoc();
8280 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
8283 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
8284 /// if it's possible.
8285 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
8286 DebugLoc dl, SelectionDAG &DAG) const {
8287 SDValue Op0 = And.getOperand(0);
8288 SDValue Op1 = And.getOperand(1);
8289 if (Op0.getOpcode() == ISD::TRUNCATE)
8290 Op0 = Op0.getOperand(0);
8291 if (Op1.getOpcode() == ISD::TRUNCATE)
8292 Op1 = Op1.getOperand(0);
8295 if (Op1.getOpcode() == ISD::SHL)
8296 std::swap(Op0, Op1);
8297 if (Op0.getOpcode() == ISD::SHL) {
8298 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
8299 if (And00C->getZExtValue() == 1) {
8300 // If we looked past a truncate, check that it's only truncating away
8302 unsigned BitWidth = Op0.getValueSizeInBits();
8303 unsigned AndBitWidth = And.getValueSizeInBits();
8304 if (BitWidth > AndBitWidth) {
8305 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones;
8306 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones);
8307 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
8311 RHS = Op0.getOperand(1);
8313 } else if (Op1.getOpcode() == ISD::Constant) {
8314 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
8315 SDValue AndLHS = Op0;
8316 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
8317 LHS = AndLHS.getOperand(0);
8318 RHS = AndLHS.getOperand(1);
8322 if (LHS.getNode()) {
8323 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
8324 // instruction. Since the shift amount is in-range-or-undefined, we know
8325 // that doing a bittest on the i32 value is ok. We extend to i32 because
8326 // the encoding for the i16 version is larger than the i32 version.
8327 // Also promote i16 to i32 for performance / code size reason.
8328 if (LHS.getValueType() == MVT::i8 ||
8329 LHS.getValueType() == MVT::i16)
8330 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
8332 // If the operand types disagree, extend the shift amount to match. Since
8333 // BT ignores high bits (like shifts) we can use anyextend.
8334 if (LHS.getValueType() != RHS.getValueType())
8335 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
8337 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
8338 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
8339 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8340 DAG.getConstant(Cond, MVT::i8), BT);
8346 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
8348 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
8350 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
8351 SDValue Op0 = Op.getOperand(0);
8352 SDValue Op1 = Op.getOperand(1);
8353 DebugLoc dl = Op.getDebugLoc();
8354 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
8356 // Optimize to BT if possible.
8357 // Lower (X & (1 << N)) == 0 to BT(X, N).
8358 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
8359 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
8360 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
8361 Op1.getOpcode() == ISD::Constant &&
8362 cast<ConstantSDNode>(Op1)->isNullValue() &&
8363 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8364 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
8365 if (NewSetCC.getNode())
8369 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
8371 if (Op1.getOpcode() == ISD::Constant &&
8372 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
8373 cast<ConstantSDNode>(Op1)->isNullValue()) &&
8374 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
8376 // If the input is a setcc, then reuse the input setcc or use a new one with
8377 // the inverted condition.
8378 if (Op0.getOpcode() == X86ISD::SETCC) {
8379 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
8380 bool Invert = (CC == ISD::SETNE) ^
8381 cast<ConstantSDNode>(Op1)->isNullValue();
8382 if (!Invert) return Op0;
8384 CCode = X86::GetOppositeBranchCondition(CCode);
8385 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8386 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
8390 bool isFP = Op1.getValueType().isFloatingPoint();
8391 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
8392 if (X86CC == X86::COND_INVALID)
8395 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
8396 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
8397 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
8400 // Lower256IntVETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
8401 // ones, and then concatenate the result back.
8402 static SDValue Lower256IntVETCC(SDValue Op, SelectionDAG &DAG) {
8403 EVT VT = Op.getValueType();
8405 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC &&
8406 "Unsupported value type for operation");
8408 int NumElems = VT.getVectorNumElements();
8409 DebugLoc dl = Op.getDebugLoc();
8410 SDValue CC = Op.getOperand(2);
8411 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
8412 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
8414 // Extract the LHS vectors
8415 SDValue LHS = Op.getOperand(0);
8416 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
8417 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
8419 // Extract the RHS vectors
8420 SDValue RHS = Op.getOperand(1);
8421 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
8422 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
8424 // Issue the operation on the smaller types and concatenate the result back
8425 MVT EltVT = VT.getVectorElementType().getSimpleVT();
8426 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
8427 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
8428 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
8429 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
8433 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
8435 SDValue Op0 = Op.getOperand(0);
8436 SDValue Op1 = Op.getOperand(1);
8437 SDValue CC = Op.getOperand(2);
8438 EVT VT = Op.getValueType();
8439 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
8440 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
8441 DebugLoc dl = Op.getDebugLoc();
8445 EVT EltVT = Op0.getValueType().getVectorElementType();
8446 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
8448 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
8451 // SSE Condition code mapping:
8460 switch (SetCCOpcode) {
8463 case ISD::SETEQ: SSECC = 0; break;
8465 case ISD::SETGT: Swap = true; // Fallthrough
8467 case ISD::SETOLT: SSECC = 1; break;
8469 case ISD::SETGE: Swap = true; // Fallthrough
8471 case ISD::SETOLE: SSECC = 2; break;
8472 case ISD::SETUO: SSECC = 3; break;
8474 case ISD::SETNE: SSECC = 4; break;
8475 case ISD::SETULE: Swap = true;
8476 case ISD::SETUGE: SSECC = 5; break;
8477 case ISD::SETULT: Swap = true;
8478 case ISD::SETUGT: SSECC = 6; break;
8479 case ISD::SETO: SSECC = 7; break;
8482 std::swap(Op0, Op1);
8484 // In the two special cases we can't handle, emit two comparisons.
8486 if (SetCCOpcode == ISD::SETUEQ) {
8488 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
8489 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
8490 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
8492 else if (SetCCOpcode == ISD::SETONE) {
8494 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
8495 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
8496 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
8498 llvm_unreachable("Illegal FP comparison");
8500 // Handle all other FP comparisons here.
8501 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
8504 // Break 256-bit integer vector compare into smaller ones.
8505 if (!isFP && VT.getSizeInBits() == 256)
8506 return Lower256IntVETCC(Op, DAG);
8508 // We are handling one of the integer comparisons here. Since SSE only has
8509 // GT and EQ comparisons for integer, swapping operands and multiple
8510 // operations may be required for some comparisons.
8511 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
8512 bool Swap = false, Invert = false, FlipSigns = false;
8514 switch (VT.getSimpleVT().SimpleTy) {
8516 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
8517 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
8518 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
8519 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
8522 switch (SetCCOpcode) {
8524 case ISD::SETNE: Invert = true;
8525 case ISD::SETEQ: Opc = EQOpc; break;
8526 case ISD::SETLT: Swap = true;
8527 case ISD::SETGT: Opc = GTOpc; break;
8528 case ISD::SETGE: Swap = true;
8529 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
8530 case ISD::SETULT: Swap = true;
8531 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
8532 case ISD::SETUGE: Swap = true;
8533 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
8536 std::swap(Op0, Op1);
8538 // Since SSE has no unsigned integer comparisons, we need to flip the sign
8539 // bits of the inputs before performing those operations.
8541 EVT EltVT = VT.getVectorElementType();
8542 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
8544 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
8545 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
8547 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
8548 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
8551 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
8553 // If the logical-not of the result is required, perform that now.
8555 Result = DAG.getNOT(dl, Result, VT);
8560 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
8561 static bool isX86LogicalCmp(SDValue Op) {
8562 unsigned Opc = Op.getNode()->getOpcode();
8563 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
8565 if (Op.getResNo() == 1 &&
8566 (Opc == X86ISD::ADD ||
8567 Opc == X86ISD::SUB ||
8568 Opc == X86ISD::ADC ||
8569 Opc == X86ISD::SBB ||
8570 Opc == X86ISD::SMUL ||
8571 Opc == X86ISD::UMUL ||
8572 Opc == X86ISD::INC ||
8573 Opc == X86ISD::DEC ||
8574 Opc == X86ISD::OR ||
8575 Opc == X86ISD::XOR ||
8576 Opc == X86ISD::AND))
8579 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
8585 static bool isZero(SDValue V) {
8586 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8587 return C && C->isNullValue();
8590 static bool isAllOnes(SDValue V) {
8591 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
8592 return C && C->isAllOnesValue();
8595 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
8596 bool addTest = true;
8597 SDValue Cond = Op.getOperand(0);
8598 SDValue Op1 = Op.getOperand(1);
8599 SDValue Op2 = Op.getOperand(2);
8600 DebugLoc DL = Op.getDebugLoc();
8603 if (Cond.getOpcode() == ISD::SETCC) {
8604 SDValue NewCond = LowerSETCC(Cond, DAG);
8605 if (NewCond.getNode())
8609 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
8610 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
8611 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
8612 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
8613 if (Cond.getOpcode() == X86ISD::SETCC &&
8614 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
8615 isZero(Cond.getOperand(1).getOperand(1))) {
8616 SDValue Cmp = Cond.getOperand(1);
8618 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
8620 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
8621 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
8622 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
8624 SDValue CmpOp0 = Cmp.getOperand(0);
8625 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
8626 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
8628 SDValue Res = // Res = 0 or -1.
8629 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8630 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
8632 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
8633 Res = DAG.getNOT(DL, Res, Res.getValueType());
8635 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
8636 if (N2C == 0 || !N2C->isNullValue())
8637 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
8642 // Look past (and (setcc_carry (cmp ...)), 1).
8643 if (Cond.getOpcode() == ISD::AND &&
8644 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8645 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8646 if (C && C->getAPIntValue() == 1)
8647 Cond = Cond.getOperand(0);
8650 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8651 // setting operand in place of the X86ISD::SETCC.
8652 if (Cond.getOpcode() == X86ISD::SETCC ||
8653 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8654 CC = Cond.getOperand(0);
8656 SDValue Cmp = Cond.getOperand(1);
8657 unsigned Opc = Cmp.getOpcode();
8658 EVT VT = Op.getValueType();
8660 bool IllegalFPCMov = false;
8661 if (VT.isFloatingPoint() && !VT.isVector() &&
8662 !isScalarFPTypeInSSEReg(VT)) // FPStack?
8663 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
8665 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
8666 Opc == X86ISD::BT) { // FIXME
8673 // Look pass the truncate.
8674 if (Cond.getOpcode() == ISD::TRUNCATE)
8675 Cond = Cond.getOperand(0);
8677 // We know the result of AND is compared against zero. Try to match
8679 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8680 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
8681 if (NewSetCC.getNode()) {
8682 CC = NewSetCC.getOperand(0);
8683 Cond = NewSetCC.getOperand(1);
8690 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8691 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8694 // a < b ? -1 : 0 -> RES = ~setcc_carry
8695 // a < b ? 0 : -1 -> RES = setcc_carry
8696 // a >= b ? -1 : 0 -> RES = setcc_carry
8697 // a >= b ? 0 : -1 -> RES = ~setcc_carry
8698 if (Cond.getOpcode() == X86ISD::CMP) {
8699 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
8701 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
8702 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
8703 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
8704 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
8705 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
8706 return DAG.getNOT(DL, Res, Res.getValueType());
8711 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
8712 // condition is true.
8713 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
8714 SDValue Ops[] = { Op2, Op1, CC, Cond };
8715 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
8718 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
8719 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
8720 // from the AND / OR.
8721 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
8722 Opc = Op.getOpcode();
8723 if (Opc != ISD::OR && Opc != ISD::AND)
8725 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8726 Op.getOperand(0).hasOneUse() &&
8727 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
8728 Op.getOperand(1).hasOneUse());
8731 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
8732 // 1 and that the SETCC node has a single use.
8733 static bool isXor1OfSetCC(SDValue Op) {
8734 if (Op.getOpcode() != ISD::XOR)
8736 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8737 if (N1C && N1C->getAPIntValue() == 1) {
8738 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
8739 Op.getOperand(0).hasOneUse();
8744 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
8745 bool addTest = true;
8746 SDValue Chain = Op.getOperand(0);
8747 SDValue Cond = Op.getOperand(1);
8748 SDValue Dest = Op.getOperand(2);
8749 DebugLoc dl = Op.getDebugLoc();
8752 if (Cond.getOpcode() == ISD::SETCC) {
8753 SDValue NewCond = LowerSETCC(Cond, DAG);
8754 if (NewCond.getNode())
8758 // FIXME: LowerXALUO doesn't handle these!!
8759 else if (Cond.getOpcode() == X86ISD::ADD ||
8760 Cond.getOpcode() == X86ISD::SUB ||
8761 Cond.getOpcode() == X86ISD::SMUL ||
8762 Cond.getOpcode() == X86ISD::UMUL)
8763 Cond = LowerXALUO(Cond, DAG);
8766 // Look pass (and (setcc_carry (cmp ...)), 1).
8767 if (Cond.getOpcode() == ISD::AND &&
8768 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
8769 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
8770 if (C && C->getAPIntValue() == 1)
8771 Cond = Cond.getOperand(0);
8774 // If condition flag is set by a X86ISD::CMP, then use it as the condition
8775 // setting operand in place of the X86ISD::SETCC.
8776 if (Cond.getOpcode() == X86ISD::SETCC ||
8777 Cond.getOpcode() == X86ISD::SETCC_CARRY) {
8778 CC = Cond.getOperand(0);
8780 SDValue Cmp = Cond.getOperand(1);
8781 unsigned Opc = Cmp.getOpcode();
8782 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
8783 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
8787 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
8791 // These can only come from an arithmetic instruction with overflow,
8792 // e.g. SADDO, UADDO.
8793 Cond = Cond.getNode()->getOperand(1);
8800 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
8801 SDValue Cmp = Cond.getOperand(0).getOperand(1);
8802 if (CondOpc == ISD::OR) {
8803 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
8804 // two branches instead of an explicit OR instruction with a
8806 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8807 isX86LogicalCmp(Cmp)) {
8808 CC = Cond.getOperand(0).getOperand(0);
8809 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8810 Chain, Dest, CC, Cmp);
8811 CC = Cond.getOperand(1).getOperand(0);
8815 } else { // ISD::AND
8816 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
8817 // two branches instead of an explicit AND instruction with a
8818 // separate test. However, we only do this if this block doesn't
8819 // have a fall-through edge, because this requires an explicit
8820 // jmp when the condition is false.
8821 if (Cmp == Cond.getOperand(1).getOperand(1) &&
8822 isX86LogicalCmp(Cmp) &&
8823 Op.getNode()->hasOneUse()) {
8824 X86::CondCode CCode =
8825 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8826 CCode = X86::GetOppositeBranchCondition(CCode);
8827 CC = DAG.getConstant(CCode, MVT::i8);
8828 SDNode *User = *Op.getNode()->use_begin();
8829 // Look for an unconditional branch following this conditional branch.
8830 // We need this because we need to reverse the successors in order
8831 // to implement FCMP_OEQ.
8832 if (User->getOpcode() == ISD::BR) {
8833 SDValue FalseBB = User->getOperand(1);
8835 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
8836 assert(NewBR == User);
8840 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8841 Chain, Dest, CC, Cmp);
8842 X86::CondCode CCode =
8843 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
8844 CCode = X86::GetOppositeBranchCondition(CCode);
8845 CC = DAG.getConstant(CCode, MVT::i8);
8851 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
8852 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
8853 // It should be transformed during dag combiner except when the condition
8854 // is set by a arithmetics with overflow node.
8855 X86::CondCode CCode =
8856 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
8857 CCode = X86::GetOppositeBranchCondition(CCode);
8858 CC = DAG.getConstant(CCode, MVT::i8);
8859 Cond = Cond.getOperand(0).getOperand(1);
8865 // Look pass the truncate.
8866 if (Cond.getOpcode() == ISD::TRUNCATE)
8867 Cond = Cond.getOperand(0);
8869 // We know the result of AND is compared against zero. Try to match
8871 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
8872 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
8873 if (NewSetCC.getNode()) {
8874 CC = NewSetCC.getOperand(0);
8875 Cond = NewSetCC.getOperand(1);
8882 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
8883 Cond = EmitTest(Cond, X86::COND_NE, DAG);
8885 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
8886 Chain, Dest, CC, Cond);
8890 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
8891 // Calls to _alloca is needed to probe the stack when allocating more than 4k
8892 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
8893 // that the guard pages used by the OS virtual memory manager are allocated in
8894 // correct sequence.
8896 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
8897 SelectionDAG &DAG) const {
8898 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
8899 EnableSegmentedStacks) &&
8900 "This should be used only on Windows targets or when segmented stacks "
8902 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
8903 DebugLoc dl = Op.getDebugLoc();
8906 SDValue Chain = Op.getOperand(0);
8907 SDValue Size = Op.getOperand(1);
8908 // FIXME: Ensure alignment here
8910 bool Is64Bit = Subtarget->is64Bit();
8911 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
8913 if (EnableSegmentedStacks) {
8914 MachineFunction &MF = DAG.getMachineFunction();
8915 MachineRegisterInfo &MRI = MF.getRegInfo();
8918 // The 64 bit implementation of segmented stacks needs to clobber both r10
8919 // r11. This makes it impossible to use it along with nested parameters.
8920 const Function *F = MF.getFunction();
8922 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
8924 if (I->hasNestAttr())
8925 report_fatal_error("Cannot use segmented stacks with functions that "
8926 "have nested arguments.");
8929 const TargetRegisterClass *AddrRegClass =
8930 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
8931 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
8932 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
8933 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
8934 DAG.getRegister(Vreg, SPTy));
8935 SDValue Ops1[2] = { Value, Chain };
8936 return DAG.getMergeValues(Ops1, 2, dl);
8939 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
8941 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
8942 Flag = Chain.getValue(1);
8943 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
8945 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
8946 Flag = Chain.getValue(1);
8948 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
8950 SDValue Ops1[2] = { Chain.getValue(0), Chain };
8951 return DAG.getMergeValues(Ops1, 2, dl);
8955 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
8956 MachineFunction &MF = DAG.getMachineFunction();
8957 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
8959 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
8960 DebugLoc DL = Op.getDebugLoc();
8962 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
8963 // vastart just stores the address of the VarArgsFrameIndex slot into the
8964 // memory location argument.
8965 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8967 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
8968 MachinePointerInfo(SV), false, false, 0);
8972 // gp_offset (0 - 6 * 8)
8973 // fp_offset (48 - 48 + 8 * 16)
8974 // overflow_arg_area (point to parameters coming in memory).
8976 SmallVector<SDValue, 8> MemOps;
8977 SDValue FIN = Op.getOperand(1);
8979 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
8980 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
8982 FIN, MachinePointerInfo(SV), false, false, 0);
8983 MemOps.push_back(Store);
8986 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8987 FIN, DAG.getIntPtrConstant(4));
8988 Store = DAG.getStore(Op.getOperand(0), DL,
8989 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
8991 FIN, MachinePointerInfo(SV, 4), false, false, 0);
8992 MemOps.push_back(Store);
8994 // Store ptr to overflow_arg_area
8995 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
8996 FIN, DAG.getIntPtrConstant(4));
8997 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
8999 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
9000 MachinePointerInfo(SV, 8),
9002 MemOps.push_back(Store);
9004 // Store ptr to reg_save_area.
9005 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
9006 FIN, DAG.getIntPtrConstant(8));
9007 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
9009 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
9010 MachinePointerInfo(SV, 16), false, false, 0);
9011 MemOps.push_back(Store);
9012 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
9013 &MemOps[0], MemOps.size());
9016 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
9017 assert(Subtarget->is64Bit() &&
9018 "LowerVAARG only handles 64-bit va_arg!");
9019 assert((Subtarget->isTargetLinux() ||
9020 Subtarget->isTargetDarwin()) &&
9021 "Unhandled target in LowerVAARG");
9022 assert(Op.getNode()->getNumOperands() == 4);
9023 SDValue Chain = Op.getOperand(0);
9024 SDValue SrcPtr = Op.getOperand(1);
9025 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
9026 unsigned Align = Op.getConstantOperandVal(3);
9027 DebugLoc dl = Op.getDebugLoc();
9029 EVT ArgVT = Op.getNode()->getValueType(0);
9030 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
9031 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy);
9034 // Decide which area this value should be read from.
9035 // TODO: Implement the AMD64 ABI in its entirety. This simple
9036 // selection mechanism works only for the basic types.
9037 if (ArgVT == MVT::f80) {
9038 llvm_unreachable("va_arg for f80 not yet implemented");
9039 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
9040 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
9041 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
9042 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
9044 llvm_unreachable("Unhandled argument type in LowerVAARG");
9048 // Sanity Check: Make sure using fp_offset makes sense.
9049 assert(!UseSoftFloat &&
9050 !(DAG.getMachineFunction()
9051 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) &&
9052 Subtarget->hasXMM());
9055 // Insert VAARG_64 node into the DAG
9056 // VAARG_64 returns two values: Variable Argument Address, Chain
9057 SmallVector<SDValue, 11> InstOps;
9058 InstOps.push_back(Chain);
9059 InstOps.push_back(SrcPtr);
9060 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
9061 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
9062 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
9063 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
9064 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
9065 VTs, &InstOps[0], InstOps.size(),
9067 MachinePointerInfo(SV),
9072 Chain = VAARG.getValue(1);
9074 // Load the next argument and return it
9075 return DAG.getLoad(ArgVT, dl,
9078 MachinePointerInfo(),
9082 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
9083 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
9084 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
9085 SDValue Chain = Op.getOperand(0);
9086 SDValue DstPtr = Op.getOperand(1);
9087 SDValue SrcPtr = Op.getOperand(2);
9088 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
9089 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9090 DebugLoc DL = Op.getDebugLoc();
9092 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
9093 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
9095 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
9099 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
9100 DebugLoc dl = Op.getDebugLoc();
9101 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9103 default: return SDValue(); // Don't custom lower most intrinsics.
9104 // Comparison intrinsics.
9105 case Intrinsic::x86_sse_comieq_ss:
9106 case Intrinsic::x86_sse_comilt_ss:
9107 case Intrinsic::x86_sse_comile_ss:
9108 case Intrinsic::x86_sse_comigt_ss:
9109 case Intrinsic::x86_sse_comige_ss:
9110 case Intrinsic::x86_sse_comineq_ss:
9111 case Intrinsic::x86_sse_ucomieq_ss:
9112 case Intrinsic::x86_sse_ucomilt_ss:
9113 case Intrinsic::x86_sse_ucomile_ss:
9114 case Intrinsic::x86_sse_ucomigt_ss:
9115 case Intrinsic::x86_sse_ucomige_ss:
9116 case Intrinsic::x86_sse_ucomineq_ss:
9117 case Intrinsic::x86_sse2_comieq_sd:
9118 case Intrinsic::x86_sse2_comilt_sd:
9119 case Intrinsic::x86_sse2_comile_sd:
9120 case Intrinsic::x86_sse2_comigt_sd:
9121 case Intrinsic::x86_sse2_comige_sd:
9122 case Intrinsic::x86_sse2_comineq_sd:
9123 case Intrinsic::x86_sse2_ucomieq_sd:
9124 case Intrinsic::x86_sse2_ucomilt_sd:
9125 case Intrinsic::x86_sse2_ucomile_sd:
9126 case Intrinsic::x86_sse2_ucomigt_sd:
9127 case Intrinsic::x86_sse2_ucomige_sd:
9128 case Intrinsic::x86_sse2_ucomineq_sd: {
9130 ISD::CondCode CC = ISD::SETCC_INVALID;
9133 case Intrinsic::x86_sse_comieq_ss:
9134 case Intrinsic::x86_sse2_comieq_sd:
9138 case Intrinsic::x86_sse_comilt_ss:
9139 case Intrinsic::x86_sse2_comilt_sd:
9143 case Intrinsic::x86_sse_comile_ss:
9144 case Intrinsic::x86_sse2_comile_sd:
9148 case Intrinsic::x86_sse_comigt_ss:
9149 case Intrinsic::x86_sse2_comigt_sd:
9153 case Intrinsic::x86_sse_comige_ss:
9154 case Intrinsic::x86_sse2_comige_sd:
9158 case Intrinsic::x86_sse_comineq_ss:
9159 case Intrinsic::x86_sse2_comineq_sd:
9163 case Intrinsic::x86_sse_ucomieq_ss:
9164 case Intrinsic::x86_sse2_ucomieq_sd:
9165 Opc = X86ISD::UCOMI;
9168 case Intrinsic::x86_sse_ucomilt_ss:
9169 case Intrinsic::x86_sse2_ucomilt_sd:
9170 Opc = X86ISD::UCOMI;
9173 case Intrinsic::x86_sse_ucomile_ss:
9174 case Intrinsic::x86_sse2_ucomile_sd:
9175 Opc = X86ISD::UCOMI;
9178 case Intrinsic::x86_sse_ucomigt_ss:
9179 case Intrinsic::x86_sse2_ucomigt_sd:
9180 Opc = X86ISD::UCOMI;
9183 case Intrinsic::x86_sse_ucomige_ss:
9184 case Intrinsic::x86_sse2_ucomige_sd:
9185 Opc = X86ISD::UCOMI;
9188 case Intrinsic::x86_sse_ucomineq_ss:
9189 case Intrinsic::x86_sse2_ucomineq_sd:
9190 Opc = X86ISD::UCOMI;
9195 SDValue LHS = Op.getOperand(1);
9196 SDValue RHS = Op.getOperand(2);
9197 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
9198 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
9199 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
9200 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9201 DAG.getConstant(X86CC, MVT::i8), Cond);
9202 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9204 // ptest and testp intrinsics. The intrinsic these come from are designed to
9205 // return an integer value, not just an instruction so lower it to the ptest
9206 // or testp pattern and a setcc for the result.
9207 case Intrinsic::x86_sse41_ptestz:
9208 case Intrinsic::x86_sse41_ptestc:
9209 case Intrinsic::x86_sse41_ptestnzc:
9210 case Intrinsic::x86_avx_ptestz_256:
9211 case Intrinsic::x86_avx_ptestc_256:
9212 case Intrinsic::x86_avx_ptestnzc_256:
9213 case Intrinsic::x86_avx_vtestz_ps:
9214 case Intrinsic::x86_avx_vtestc_ps:
9215 case Intrinsic::x86_avx_vtestnzc_ps:
9216 case Intrinsic::x86_avx_vtestz_pd:
9217 case Intrinsic::x86_avx_vtestc_pd:
9218 case Intrinsic::x86_avx_vtestnzc_pd:
9219 case Intrinsic::x86_avx_vtestz_ps_256:
9220 case Intrinsic::x86_avx_vtestc_ps_256:
9221 case Intrinsic::x86_avx_vtestnzc_ps_256:
9222 case Intrinsic::x86_avx_vtestz_pd_256:
9223 case Intrinsic::x86_avx_vtestc_pd_256:
9224 case Intrinsic::x86_avx_vtestnzc_pd_256: {
9225 bool IsTestPacked = false;
9228 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
9229 case Intrinsic::x86_avx_vtestz_ps:
9230 case Intrinsic::x86_avx_vtestz_pd:
9231 case Intrinsic::x86_avx_vtestz_ps_256:
9232 case Intrinsic::x86_avx_vtestz_pd_256:
9233 IsTestPacked = true; // Fallthrough
9234 case Intrinsic::x86_sse41_ptestz:
9235 case Intrinsic::x86_avx_ptestz_256:
9237 X86CC = X86::COND_E;
9239 case Intrinsic::x86_avx_vtestc_ps:
9240 case Intrinsic::x86_avx_vtestc_pd:
9241 case Intrinsic::x86_avx_vtestc_ps_256:
9242 case Intrinsic::x86_avx_vtestc_pd_256:
9243 IsTestPacked = true; // Fallthrough
9244 case Intrinsic::x86_sse41_ptestc:
9245 case Intrinsic::x86_avx_ptestc_256:
9247 X86CC = X86::COND_B;
9249 case Intrinsic::x86_avx_vtestnzc_ps:
9250 case Intrinsic::x86_avx_vtestnzc_pd:
9251 case Intrinsic::x86_avx_vtestnzc_ps_256:
9252 case Intrinsic::x86_avx_vtestnzc_pd_256:
9253 IsTestPacked = true; // Fallthrough
9254 case Intrinsic::x86_sse41_ptestnzc:
9255 case Intrinsic::x86_avx_ptestnzc_256:
9257 X86CC = X86::COND_A;
9261 SDValue LHS = Op.getOperand(1);
9262 SDValue RHS = Op.getOperand(2);
9263 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
9264 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
9265 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
9266 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
9267 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
9270 // Fix vector shift instructions where the last operand is a non-immediate
9272 case Intrinsic::x86_sse2_pslli_w:
9273 case Intrinsic::x86_sse2_pslli_d:
9274 case Intrinsic::x86_sse2_pslli_q:
9275 case Intrinsic::x86_sse2_psrli_w:
9276 case Intrinsic::x86_sse2_psrli_d:
9277 case Intrinsic::x86_sse2_psrli_q:
9278 case Intrinsic::x86_sse2_psrai_w:
9279 case Intrinsic::x86_sse2_psrai_d:
9280 case Intrinsic::x86_mmx_pslli_w:
9281 case Intrinsic::x86_mmx_pslli_d:
9282 case Intrinsic::x86_mmx_pslli_q:
9283 case Intrinsic::x86_mmx_psrli_w:
9284 case Intrinsic::x86_mmx_psrli_d:
9285 case Intrinsic::x86_mmx_psrli_q:
9286 case Intrinsic::x86_mmx_psrai_w:
9287 case Intrinsic::x86_mmx_psrai_d: {
9288 SDValue ShAmt = Op.getOperand(2);
9289 if (isa<ConstantSDNode>(ShAmt))
9292 unsigned NewIntNo = 0;
9293 EVT ShAmtVT = MVT::v4i32;
9295 case Intrinsic::x86_sse2_pslli_w:
9296 NewIntNo = Intrinsic::x86_sse2_psll_w;
9298 case Intrinsic::x86_sse2_pslli_d:
9299 NewIntNo = Intrinsic::x86_sse2_psll_d;
9301 case Intrinsic::x86_sse2_pslli_q:
9302 NewIntNo = Intrinsic::x86_sse2_psll_q;
9304 case Intrinsic::x86_sse2_psrli_w:
9305 NewIntNo = Intrinsic::x86_sse2_psrl_w;
9307 case Intrinsic::x86_sse2_psrli_d:
9308 NewIntNo = Intrinsic::x86_sse2_psrl_d;
9310 case Intrinsic::x86_sse2_psrli_q:
9311 NewIntNo = Intrinsic::x86_sse2_psrl_q;
9313 case Intrinsic::x86_sse2_psrai_w:
9314 NewIntNo = Intrinsic::x86_sse2_psra_w;
9316 case Intrinsic::x86_sse2_psrai_d:
9317 NewIntNo = Intrinsic::x86_sse2_psra_d;
9320 ShAmtVT = MVT::v2i32;
9322 case Intrinsic::x86_mmx_pslli_w:
9323 NewIntNo = Intrinsic::x86_mmx_psll_w;
9325 case Intrinsic::x86_mmx_pslli_d:
9326 NewIntNo = Intrinsic::x86_mmx_psll_d;
9328 case Intrinsic::x86_mmx_pslli_q:
9329 NewIntNo = Intrinsic::x86_mmx_psll_q;
9331 case Intrinsic::x86_mmx_psrli_w:
9332 NewIntNo = Intrinsic::x86_mmx_psrl_w;
9334 case Intrinsic::x86_mmx_psrli_d:
9335 NewIntNo = Intrinsic::x86_mmx_psrl_d;
9337 case Intrinsic::x86_mmx_psrli_q:
9338 NewIntNo = Intrinsic::x86_mmx_psrl_q;
9340 case Intrinsic::x86_mmx_psrai_w:
9341 NewIntNo = Intrinsic::x86_mmx_psra_w;
9343 case Intrinsic::x86_mmx_psrai_d:
9344 NewIntNo = Intrinsic::x86_mmx_psra_d;
9346 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
9352 // The vector shift intrinsics with scalars uses 32b shift amounts but
9353 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
9357 ShOps[1] = DAG.getConstant(0, MVT::i32);
9358 if (ShAmtVT == MVT::v4i32) {
9359 ShOps[2] = DAG.getUNDEF(MVT::i32);
9360 ShOps[3] = DAG.getUNDEF(MVT::i32);
9361 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
9363 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
9364 // FIXME this must be lowered to get rid of the invalid type.
9367 EVT VT = Op.getValueType();
9368 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt);
9369 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9370 DAG.getConstant(NewIntNo, MVT::i32),
9371 Op.getOperand(1), ShAmt);
9376 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
9377 SelectionDAG &DAG) const {
9378 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9379 MFI->setReturnAddressIsTaken(true);
9381 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9382 DebugLoc dl = Op.getDebugLoc();
9385 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9387 DAG.getConstant(TD->getPointerSize(),
9388 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
9389 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9390 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9392 MachinePointerInfo(), false, false, 0);
9395 // Just load the return address.
9396 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
9397 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9398 RetAddrFI, MachinePointerInfo(), false, false, 0);
9401 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
9402 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9403 MFI->setFrameAddressIsTaken(true);
9405 EVT VT = Op.getValueType();
9406 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
9407 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9408 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
9409 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
9411 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
9412 MachinePointerInfo(),
9417 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
9418 SelectionDAG &DAG) const {
9419 return DAG.getIntPtrConstant(2*TD->getPointerSize());
9422 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
9423 MachineFunction &MF = DAG.getMachineFunction();
9424 SDValue Chain = Op.getOperand(0);
9425 SDValue Offset = Op.getOperand(1);
9426 SDValue Handler = Op.getOperand(2);
9427 DebugLoc dl = Op.getDebugLoc();
9429 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
9430 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
9432 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
9434 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
9435 DAG.getIntPtrConstant(TD->getPointerSize()));
9436 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
9437 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
9439 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
9440 MF.getRegInfo().addLiveOut(StoreAddrReg);
9442 return DAG.getNode(X86ISD::EH_RETURN, dl,
9444 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
9447 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
9448 SelectionDAG &DAG) const {
9449 return Op.getOperand(0);
9452 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
9453 SelectionDAG &DAG) const {
9454 SDValue Root = Op.getOperand(0);
9455 SDValue Trmp = Op.getOperand(1); // trampoline
9456 SDValue FPtr = Op.getOperand(2); // nested function
9457 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
9458 DebugLoc dl = Op.getDebugLoc();
9460 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
9462 if (Subtarget->is64Bit()) {
9463 SDValue OutChains[6];
9465 // Large code-model.
9466 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
9467 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
9469 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10);
9470 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11);
9472 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
9474 // Load the pointer to the nested function into R11.
9475 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
9476 SDValue Addr = Trmp;
9477 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9478 Addr, MachinePointerInfo(TrmpAddr),
9481 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9482 DAG.getConstant(2, MVT::i64));
9483 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
9484 MachinePointerInfo(TrmpAddr, 2),
9487 // Load the 'nest' parameter value into R10.
9488 // R10 is specified in X86CallingConv.td
9489 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
9490 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9491 DAG.getConstant(10, MVT::i64));
9492 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9493 Addr, MachinePointerInfo(TrmpAddr, 10),
9496 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9497 DAG.getConstant(12, MVT::i64));
9498 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
9499 MachinePointerInfo(TrmpAddr, 12),
9502 // Jump to the nested function.
9503 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
9504 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9505 DAG.getConstant(20, MVT::i64));
9506 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
9507 Addr, MachinePointerInfo(TrmpAddr, 20),
9510 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
9511 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
9512 DAG.getConstant(22, MVT::i64));
9513 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
9514 MachinePointerInfo(TrmpAddr, 22),
9517 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
9519 const Function *Func =
9520 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
9521 CallingConv::ID CC = Func->getCallingConv();
9526 llvm_unreachable("Unsupported calling convention");
9527 case CallingConv::C:
9528 case CallingConv::X86_StdCall: {
9529 // Pass 'nest' parameter in ECX.
9530 // Must be kept in sync with X86CallingConv.td
9533 // Check that ECX wasn't needed by an 'inreg' parameter.
9534 FunctionType *FTy = Func->getFunctionType();
9535 const AttrListPtr &Attrs = Func->getAttributes();
9537 if (!Attrs.isEmpty() && !Func->isVarArg()) {
9538 unsigned InRegCount = 0;
9541 for (FunctionType::param_iterator I = FTy->param_begin(),
9542 E = FTy->param_end(); I != E; ++I, ++Idx)
9543 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
9544 // FIXME: should only count parameters that are lowered to integers.
9545 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
9547 if (InRegCount > 2) {
9548 report_fatal_error("Nest register in use - reduce number of inreg"
9554 case CallingConv::X86_FastCall:
9555 case CallingConv::X86_ThisCall:
9556 case CallingConv::Fast:
9557 // Pass 'nest' parameter in EAX.
9558 // Must be kept in sync with X86CallingConv.td
9563 SDValue OutChains[4];
9566 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9567 DAG.getConstant(10, MVT::i32));
9568 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
9570 // This is storing the opcode for MOV32ri.
9571 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
9572 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg);
9573 OutChains[0] = DAG.getStore(Root, dl,
9574 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
9575 Trmp, MachinePointerInfo(TrmpAddr),
9578 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9579 DAG.getConstant(1, MVT::i32));
9580 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
9581 MachinePointerInfo(TrmpAddr, 1),
9584 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
9585 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9586 DAG.getConstant(5, MVT::i32));
9587 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
9588 MachinePointerInfo(TrmpAddr, 5),
9591 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
9592 DAG.getConstant(6, MVT::i32));
9593 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
9594 MachinePointerInfo(TrmpAddr, 6),
9597 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
9601 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
9602 SelectionDAG &DAG) const {
9604 The rounding mode is in bits 11:10 of FPSR, and has the following
9611 FLT_ROUNDS, on the other hand, expects the following:
9618 To perform the conversion, we do:
9619 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
9622 MachineFunction &MF = DAG.getMachineFunction();
9623 const TargetMachine &TM = MF.getTarget();
9624 const TargetFrameLowering &TFI = *TM.getFrameLowering();
9625 unsigned StackAlignment = TFI.getStackAlignment();
9626 EVT VT = Op.getValueType();
9627 DebugLoc DL = Op.getDebugLoc();
9629 // Save FP Control Word to stack slot
9630 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
9631 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
9634 MachineMemOperand *MMO =
9635 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
9636 MachineMemOperand::MOStore, 2, 2);
9638 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
9639 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
9640 DAG.getVTList(MVT::Other),
9641 Ops, 2, MVT::i16, MMO);
9643 // Load FP Control Word from stack slot
9644 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
9645 MachinePointerInfo(), false, false, 0);
9647 // Transform as necessary
9649 DAG.getNode(ISD::SRL, DL, MVT::i16,
9650 DAG.getNode(ISD::AND, DL, MVT::i16,
9651 CWD, DAG.getConstant(0x800, MVT::i16)),
9652 DAG.getConstant(11, MVT::i8));
9654 DAG.getNode(ISD::SRL, DL, MVT::i16,
9655 DAG.getNode(ISD::AND, DL, MVT::i16,
9656 CWD, DAG.getConstant(0x400, MVT::i16)),
9657 DAG.getConstant(9, MVT::i8));
9660 DAG.getNode(ISD::AND, DL, MVT::i16,
9661 DAG.getNode(ISD::ADD, DL, MVT::i16,
9662 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
9663 DAG.getConstant(1, MVT::i16)),
9664 DAG.getConstant(3, MVT::i16));
9667 return DAG.getNode((VT.getSizeInBits() < 16 ?
9668 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
9671 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
9672 EVT VT = Op.getValueType();
9674 unsigned NumBits = VT.getSizeInBits();
9675 DebugLoc dl = Op.getDebugLoc();
9677 Op = Op.getOperand(0);
9678 if (VT == MVT::i8) {
9679 // Zero extend to i32 since there is not an i8 bsr.
9681 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9684 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
9685 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9686 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
9688 // If src is zero (i.e. bsr sets ZF), returns NumBits.
9691 DAG.getConstant(NumBits+NumBits-1, OpVT),
9692 DAG.getConstant(X86::COND_E, MVT::i8),
9695 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9697 // Finally xor with NumBits-1.
9698 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
9701 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9705 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const {
9706 EVT VT = Op.getValueType();
9708 unsigned NumBits = VT.getSizeInBits();
9709 DebugLoc dl = Op.getDebugLoc();
9711 Op = Op.getOperand(0);
9712 if (VT == MVT::i8) {
9714 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
9717 // Issue a bsf (scan bits forward) which also sets EFLAGS.
9718 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
9719 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
9721 // If src is zero (i.e. bsf sets ZF), returns NumBits.
9724 DAG.getConstant(NumBits, OpVT),
9725 DAG.getConstant(X86::COND_E, MVT::i8),
9728 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
9731 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
9735 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
9736 // ones, and then concatenate the result back.
9737 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
9738 EVT VT = Op.getValueType();
9740 assert(VT.getSizeInBits() == 256 && VT.isInteger() &&
9741 "Unsupported value type for operation");
9743 int NumElems = VT.getVectorNumElements();
9744 DebugLoc dl = Op.getDebugLoc();
9745 SDValue Idx0 = DAG.getConstant(0, MVT::i32);
9746 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32);
9748 // Extract the LHS vectors
9749 SDValue LHS = Op.getOperand(0);
9750 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl);
9751 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl);
9753 // Extract the RHS vectors
9754 SDValue RHS = Op.getOperand(1);
9755 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl);
9756 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl);
9758 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9759 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9761 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9762 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
9763 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
9766 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const {
9767 assert(Op.getValueType().getSizeInBits() == 256 &&
9768 Op.getValueType().isInteger() &&
9769 "Only handle AVX 256-bit vector integer operation");
9770 return Lower256IntArith(Op, DAG);
9773 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const {
9774 assert(Op.getValueType().getSizeInBits() == 256 &&
9775 Op.getValueType().isInteger() &&
9776 "Only handle AVX 256-bit vector integer operation");
9777 return Lower256IntArith(Op, DAG);
9780 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
9781 EVT VT = Op.getValueType();
9783 // Decompose 256-bit ops into smaller 128-bit ops.
9784 if (VT.getSizeInBits() == 256)
9785 return Lower256IntArith(Op, DAG);
9787 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
9788 DebugLoc dl = Op.getDebugLoc();
9790 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
9791 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
9792 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
9793 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
9794 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
9796 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
9797 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
9798 // return AloBlo + AloBhi + AhiBlo;
9800 SDValue A = Op.getOperand(0);
9801 SDValue B = Op.getOperand(1);
9803 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9804 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9805 A, DAG.getConstant(32, MVT::i32));
9806 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9807 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9808 B, DAG.getConstant(32, MVT::i32));
9809 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9810 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9812 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9813 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9815 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9816 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
9818 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9819 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9820 AloBhi, DAG.getConstant(32, MVT::i32));
9821 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9822 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9823 AhiBlo, DAG.getConstant(32, MVT::i32));
9824 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
9825 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
9829 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
9831 EVT VT = Op.getValueType();
9832 DebugLoc dl = Op.getDebugLoc();
9833 SDValue R = Op.getOperand(0);
9834 SDValue Amt = Op.getOperand(1);
9835 LLVMContext *Context = DAG.getContext();
9837 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
9840 // Decompose 256-bit shifts into smaller 128-bit shifts.
9841 if (VT.getSizeInBits() == 256) {
9842 int NumElems = VT.getVectorNumElements();
9843 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9844 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9846 // Extract the two vectors
9847 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl);
9848 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32),
9851 // Recreate the shift amount vectors
9853 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
9854 // Constant shift amount
9855 SmallVector<SDValue, 4> Amt1Csts;
9856 SmallVector<SDValue, 4> Amt2Csts;
9857 for (int i = 0; i < NumElems/2; ++i)
9858 Amt1Csts.push_back(Amt->getOperand(i));
9859 for (int i = NumElems/2; i < NumElems; ++i)
9860 Amt2Csts.push_back(Amt->getOperand(i));
9862 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9863 &Amt1Csts[0], NumElems/2);
9864 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
9865 &Amt2Csts[0], NumElems/2);
9867 // Variable shift amount
9868 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl);
9869 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32),
9873 // Issue new vector shifts for the smaller types
9874 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
9875 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
9877 // Concatenate the result back
9878 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
9881 // Optimize shl/srl/sra with constant shift amount.
9882 if (isSplatVector(Amt.getNode())) {
9883 SDValue SclrAmt = Amt->getOperand(0);
9884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
9885 uint64_t ShiftAmt = C->getZExtValue();
9887 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL)
9888 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9889 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9890 R, DAG.getConstant(ShiftAmt, MVT::i32));
9892 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL)
9893 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9894 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9895 R, DAG.getConstant(ShiftAmt, MVT::i32));
9897 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL)
9898 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9899 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9900 R, DAG.getConstant(ShiftAmt, MVT::i32));
9902 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL)
9903 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9904 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9905 R, DAG.getConstant(ShiftAmt, MVT::i32));
9907 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL)
9908 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9909 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
9910 R, DAG.getConstant(ShiftAmt, MVT::i32));
9912 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL)
9913 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9914 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
9915 R, DAG.getConstant(ShiftAmt, MVT::i32));
9917 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA)
9918 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9919 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
9920 R, DAG.getConstant(ShiftAmt, MVT::i32));
9922 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA)
9923 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9924 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
9925 R, DAG.getConstant(ShiftAmt, MVT::i32));
9929 // Lower SHL with variable shift amount.
9930 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
9931 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9932 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
9933 Op.getOperand(1), DAG.getConstant(23, MVT::i32));
9935 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
9937 std::vector<Constant*> CV(4, CI);
9938 Constant *C = ConstantVector::get(CV);
9939 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9940 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9941 MachinePointerInfo::getConstantPool(),
9944 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
9945 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
9946 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
9947 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
9949 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
9951 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9952 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
9953 Op.getOperand(1), DAG.getConstant(5, MVT::i32));
9955 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15));
9956 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63));
9958 std::vector<Constant*> CVM1(16, CM1);
9959 std::vector<Constant*> CVM2(16, CM2);
9960 Constant *C = ConstantVector::get(CVM1);
9961 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9962 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9963 MachinePointerInfo::getConstantPool(),
9966 // r = pblendv(r, psllw(r & (char16)15, 4), a);
9967 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9968 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9969 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9970 DAG.getConstant(4, MVT::i32));
9971 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
9973 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9975 C = ConstantVector::get(CVM2);
9976 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
9977 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
9978 MachinePointerInfo::getConstantPool(),
9981 // r = pblendv(r, psllw(r & (char16)63, 2), a);
9982 M = DAG.getNode(ISD::AND, dl, VT, R, M);
9983 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9984 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
9985 DAG.getConstant(2, MVT::i32));
9986 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
9988 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
9990 // return pblendv(r, r+r, a);
9991 R = DAG.getNode(ISD::VSELECT, dl, VT, Op,
9992 R, DAG.getNode(ISD::ADD, dl, VT, R, R));
9998 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
9999 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
10000 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
10001 // looks for this combo and may remove the "setcc" instruction if the "setcc"
10002 // has only one use.
10003 SDNode *N = Op.getNode();
10004 SDValue LHS = N->getOperand(0);
10005 SDValue RHS = N->getOperand(1);
10006 unsigned BaseOp = 0;
10008 DebugLoc DL = Op.getDebugLoc();
10009 switch (Op.getOpcode()) {
10010 default: llvm_unreachable("Unknown ovf instruction!");
10012 // A subtract of one will be selected as a INC. Note that INC doesn't
10013 // set CF, so we can't do this for UADDO.
10014 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10016 BaseOp = X86ISD::INC;
10017 Cond = X86::COND_O;
10020 BaseOp = X86ISD::ADD;
10021 Cond = X86::COND_O;
10024 BaseOp = X86ISD::ADD;
10025 Cond = X86::COND_B;
10028 // A subtract of one will be selected as a DEC. Note that DEC doesn't
10029 // set CF, so we can't do this for USUBO.
10030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
10032 BaseOp = X86ISD::DEC;
10033 Cond = X86::COND_O;
10036 BaseOp = X86ISD::SUB;
10037 Cond = X86::COND_O;
10040 BaseOp = X86ISD::SUB;
10041 Cond = X86::COND_B;
10044 BaseOp = X86ISD::SMUL;
10045 Cond = X86::COND_O;
10047 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
10048 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
10050 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
10053 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
10054 DAG.getConstant(X86::COND_O, MVT::i32),
10055 SDValue(Sum.getNode(), 2));
10057 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10061 // Also sets EFLAGS.
10062 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
10063 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
10066 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
10067 DAG.getConstant(Cond, MVT::i32),
10068 SDValue(Sum.getNode(), 1));
10070 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
10073 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{
10074 DebugLoc dl = Op.getDebugLoc();
10075 SDNode* Node = Op.getNode();
10076 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
10077 EVT VT = Node->getValueType(0);
10078 if (Subtarget->hasSSE2() && VT.isVector()) {
10079 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
10080 ExtraVT.getScalarType().getSizeInBits();
10081 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
10083 unsigned SHLIntrinsicsID = 0;
10084 unsigned SRAIntrinsicsID = 0;
10085 switch (VT.getSimpleVT().SimpleTy) {
10089 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_q;
10090 SRAIntrinsicsID = 0;
10094 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d;
10095 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d;
10099 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w;
10100 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w;
10105 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10106 DAG.getConstant(SHLIntrinsicsID, MVT::i32),
10107 Node->getOperand(0), ShAmt);
10109 // In case of 1 bit sext, no need to shr
10110 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1;
10112 if (SRAIntrinsicsID) {
10113 Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
10114 DAG.getConstant(SRAIntrinsicsID, MVT::i32),
10124 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
10125 DebugLoc dl = Op.getDebugLoc();
10127 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
10128 // There isn't any reason to disable it if the target processor supports it.
10129 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
10130 SDValue Chain = Op.getOperand(0);
10131 SDValue Zero = DAG.getConstant(0, MVT::i32);
10133 DAG.getRegister(X86::ESP, MVT::i32), // Base
10134 DAG.getTargetConstant(1, MVT::i8), // Scale
10135 DAG.getRegister(0, MVT::i32), // Index
10136 DAG.getTargetConstant(0, MVT::i32), // Disp
10137 DAG.getRegister(0, MVT::i32), // Segment.
10142 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10143 array_lengthof(Ops));
10144 return SDValue(Res, 0);
10147 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
10149 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10151 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10152 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
10153 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
10154 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
10156 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
10157 if (!Op1 && !Op2 && !Op3 && Op4)
10158 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
10160 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
10161 if (Op1 && !Op2 && !Op3 && !Op4)
10162 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
10164 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
10166 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10169 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op,
10170 SelectionDAG &DAG) const {
10171 DebugLoc dl = Op.getDebugLoc();
10172 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
10173 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
10174 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
10175 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
10177 // The only fence that needs an instruction is a sequentially-consistent
10178 // cross-thread fence.
10179 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
10180 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
10181 // no-sse2). There isn't any reason to disable it if the target processor
10183 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
10184 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
10186 SDValue Chain = Op.getOperand(0);
10187 SDValue Zero = DAG.getConstant(0, MVT::i32);
10189 DAG.getRegister(X86::ESP, MVT::i32), // Base
10190 DAG.getTargetConstant(1, MVT::i8), // Scale
10191 DAG.getRegister(0, MVT::i32), // Index
10192 DAG.getTargetConstant(0, MVT::i32), // Disp
10193 DAG.getRegister(0, MVT::i32), // Segment.
10198 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
10199 array_lengthof(Ops));
10200 return SDValue(Res, 0);
10203 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
10204 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
10208 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
10209 EVT T = Op.getValueType();
10210 DebugLoc DL = Op.getDebugLoc();
10213 switch(T.getSimpleVT().SimpleTy) {
10215 assert(false && "Invalid value type!");
10216 case MVT::i8: Reg = X86::AL; size = 1; break;
10217 case MVT::i16: Reg = X86::AX; size = 2; break;
10218 case MVT::i32: Reg = X86::EAX; size = 4; break;
10220 assert(Subtarget->is64Bit() && "Node not type legal!");
10221 Reg = X86::RAX; size = 8;
10224 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
10225 Op.getOperand(2), SDValue());
10226 SDValue Ops[] = { cpIn.getValue(0),
10229 DAG.getTargetConstant(size, MVT::i8),
10230 cpIn.getValue(1) };
10231 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10232 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
10233 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
10236 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
10240 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
10241 SelectionDAG &DAG) const {
10242 assert(Subtarget->is64Bit() && "Result not type legalized?");
10243 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10244 SDValue TheChain = Op.getOperand(0);
10245 DebugLoc dl = Op.getDebugLoc();
10246 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10247 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
10248 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
10250 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
10251 DAG.getConstant(32, MVT::i8));
10253 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
10256 return DAG.getMergeValues(Ops, 2, dl);
10259 SDValue X86TargetLowering::LowerBITCAST(SDValue Op,
10260 SelectionDAG &DAG) const {
10261 EVT SrcVT = Op.getOperand(0).getValueType();
10262 EVT DstVT = Op.getValueType();
10263 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
10264 Subtarget->hasMMX() && "Unexpected custom BITCAST");
10265 assert((DstVT == MVT::i64 ||
10266 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
10267 "Unexpected custom BITCAST");
10268 // i64 <=> MMX conversions are Legal.
10269 if (SrcVT==MVT::i64 && DstVT.isVector())
10271 if (DstVT==MVT::i64 && SrcVT.isVector())
10273 // MMX <=> MMX conversions are Legal.
10274 if (SrcVT.isVector() && DstVT.isVector())
10276 // All other conversions need to be expanded.
10280 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const {
10281 SDNode *Node = Op.getNode();
10282 DebugLoc dl = Node->getDebugLoc();
10283 EVT T = Node->getValueType(0);
10284 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
10285 DAG.getConstant(0, T), Node->getOperand(2));
10286 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
10287 cast<AtomicSDNode>(Node)->getMemoryVT(),
10288 Node->getOperand(0),
10289 Node->getOperand(1), negOp,
10290 cast<AtomicSDNode>(Node)->getSrcValue(),
10291 cast<AtomicSDNode>(Node)->getAlignment(),
10292 cast<AtomicSDNode>(Node)->getOrdering(),
10293 cast<AtomicSDNode>(Node)->getSynchScope());
10296 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
10297 SDNode *Node = Op.getNode();
10298 DebugLoc dl = Node->getDebugLoc();
10299 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10301 // Convert seq_cst store -> xchg
10302 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
10303 // FIXME: On 32-bit, store -> fist or movq would be more efficient
10304 // (The only way to get a 16-byte store is cmpxchg16b)
10305 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
10306 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
10307 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
10308 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
10309 cast<AtomicSDNode>(Node)->getMemoryVT(),
10310 Node->getOperand(0),
10311 Node->getOperand(1), Node->getOperand(2),
10312 cast<AtomicSDNode>(Node)->getMemOperand(),
10313 cast<AtomicSDNode>(Node)->getOrdering(),
10314 cast<AtomicSDNode>(Node)->getSynchScope());
10315 return Swap.getValue(1);
10317 // Other atomic stores have a simple pattern.
10321 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
10322 EVT VT = Op.getNode()->getValueType(0);
10324 // Let legalize expand this if it isn't a legal type yet.
10325 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
10328 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
10331 bool ExtraOp = false;
10332 switch (Op.getOpcode()) {
10333 default: assert(0 && "Invalid code");
10334 case ISD::ADDC: Opc = X86ISD::ADD; break;
10335 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
10336 case ISD::SUBC: Opc = X86ISD::SUB; break;
10337 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
10341 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10343 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
10344 Op.getOperand(1), Op.getOperand(2));
10347 /// LowerOperation - Provide custom lowering hooks for some operations.
10349 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
10350 switch (Op.getOpcode()) {
10351 default: llvm_unreachable("Should not custom lower this!");
10352 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
10353 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG);
10354 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG);
10355 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
10356 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
10357 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
10358 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
10359 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
10360 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
10361 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
10362 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
10363 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
10364 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG);
10365 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
10366 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
10367 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
10368 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
10369 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
10370 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
10371 case ISD::SHL_PARTS:
10372 case ISD::SRA_PARTS:
10373 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
10374 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
10375 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
10376 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
10377 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
10378 case ISD::FABS: return LowerFABS(Op, DAG);
10379 case ISD::FNEG: return LowerFNEG(Op, DAG);
10380 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
10381 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
10382 case ISD::SETCC: return LowerSETCC(Op, DAG);
10383 case ISD::SELECT: return LowerSELECT(Op, DAG);
10384 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
10385 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
10386 case ISD::VASTART: return LowerVASTART(Op, DAG);
10387 case ISD::VAARG: return LowerVAARG(Op, DAG);
10388 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
10389 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
10390 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
10391 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
10392 case ISD::FRAME_TO_ARGS_OFFSET:
10393 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
10394 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
10395 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
10396 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
10397 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
10398 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
10399 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
10400 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
10401 case ISD::MUL: return LowerMUL(Op, DAG);
10404 case ISD::SHL: return LowerShift(Op, DAG);
10410 case ISD::UMULO: return LowerXALUO(Op, DAG);
10411 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
10412 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
10416 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10417 case ISD::ADD: return LowerADD(Op, DAG);
10418 case ISD::SUB: return LowerSUB(Op, DAG);
10422 static void ReplaceATOMIC_LOAD(SDNode *Node,
10423 SmallVectorImpl<SDValue> &Results,
10424 SelectionDAG &DAG) {
10425 DebugLoc dl = Node->getDebugLoc();
10426 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
10428 // Convert wide load -> cmpxchg8b/cmpxchg16b
10429 // FIXME: On 32-bit, load -> fild or movq would be more efficient
10430 // (The only way to get a 16-byte load is cmpxchg16b)
10431 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
10432 SDValue Zero = DAG.getConstant(0, VT);
10433 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
10434 Node->getOperand(0),
10435 Node->getOperand(1), Zero, Zero,
10436 cast<AtomicSDNode>(Node)->getMemOperand(),
10437 cast<AtomicSDNode>(Node)->getOrdering(),
10438 cast<AtomicSDNode>(Node)->getSynchScope());
10439 Results.push_back(Swap.getValue(0));
10440 Results.push_back(Swap.getValue(1));
10443 void X86TargetLowering::
10444 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
10445 SelectionDAG &DAG, unsigned NewOp) const {
10446 EVT T = Node->getValueType(0);
10447 DebugLoc dl = Node->getDebugLoc();
10448 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
10450 SDValue Chain = Node->getOperand(0);
10451 SDValue In1 = Node->getOperand(1);
10452 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10453 Node->getOperand(2), DAG.getIntPtrConstant(0));
10454 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
10455 Node->getOperand(2), DAG.getIntPtrConstant(1));
10456 SDValue Ops[] = { Chain, In1, In2L, In2H };
10457 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
10459 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
10460 cast<MemSDNode>(Node)->getMemOperand());
10461 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
10462 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
10463 Results.push_back(Result.getValue(2));
10466 /// ReplaceNodeResults - Replace a node with an illegal result type
10467 /// with a new node built out of custom code.
10468 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
10469 SmallVectorImpl<SDValue>&Results,
10470 SelectionDAG &DAG) const {
10471 DebugLoc dl = N->getDebugLoc();
10472 switch (N->getOpcode()) {
10474 assert(false && "Do not know how to custom type legalize this operation!");
10476 case ISD::SIGN_EXTEND_INREG:
10481 // We don't want to expand or promote these.
10483 case ISD::FP_TO_SINT: {
10484 std::pair<SDValue,SDValue> Vals =
10485 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
10486 SDValue FIST = Vals.first, StackSlot = Vals.second;
10487 if (FIST.getNode() != 0) {
10488 EVT VT = N->getValueType(0);
10489 // Return a load from the stack slot.
10490 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
10491 MachinePointerInfo(), false, false, 0));
10495 case ISD::READCYCLECOUNTER: {
10496 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10497 SDValue TheChain = N->getOperand(0);
10498 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
10499 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
10501 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
10503 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
10504 SDValue Ops[] = { eax, edx };
10505 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
10506 Results.push_back(edx.getValue(1));
10509 case ISD::ATOMIC_CMP_SWAP: {
10510 EVT T = N->getValueType(0);
10511 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
10512 bool Regs64bit = T == MVT::i128;
10513 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
10514 SDValue cpInL, cpInH;
10515 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10516 DAG.getConstant(0, HalfT));
10517 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
10518 DAG.getConstant(1, HalfT));
10519 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
10520 Regs64bit ? X86::RAX : X86::EAX,
10522 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
10523 Regs64bit ? X86::RDX : X86::EDX,
10524 cpInH, cpInL.getValue(1));
10525 SDValue swapInL, swapInH;
10526 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10527 DAG.getConstant(0, HalfT));
10528 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
10529 DAG.getConstant(1, HalfT));
10530 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
10531 Regs64bit ? X86::RBX : X86::EBX,
10532 swapInL, cpInH.getValue(1));
10533 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
10534 Regs64bit ? X86::RCX : X86::ECX,
10535 swapInH, swapInL.getValue(1));
10536 SDValue Ops[] = { swapInH.getValue(0),
10538 swapInH.getValue(1) };
10539 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
10540 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
10541 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
10542 X86ISD::LCMPXCHG8_DAG;
10543 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
10545 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
10546 Regs64bit ? X86::RAX : X86::EAX,
10547 HalfT, Result.getValue(1));
10548 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
10549 Regs64bit ? X86::RDX : X86::EDX,
10550 HalfT, cpOutL.getValue(2));
10551 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
10552 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
10553 Results.push_back(cpOutH.getValue(1));
10556 case ISD::ATOMIC_LOAD_ADD:
10557 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
10559 case ISD::ATOMIC_LOAD_AND:
10560 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
10562 case ISD::ATOMIC_LOAD_NAND:
10563 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
10565 case ISD::ATOMIC_LOAD_OR:
10566 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
10568 case ISD::ATOMIC_LOAD_SUB:
10569 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
10571 case ISD::ATOMIC_LOAD_XOR:
10572 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
10574 case ISD::ATOMIC_SWAP:
10575 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
10577 case ISD::ATOMIC_LOAD:
10578 ReplaceATOMIC_LOAD(N, Results, DAG);
10582 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
10584 default: return NULL;
10585 case X86ISD::BSF: return "X86ISD::BSF";
10586 case X86ISD::BSR: return "X86ISD::BSR";
10587 case X86ISD::SHLD: return "X86ISD::SHLD";
10588 case X86ISD::SHRD: return "X86ISD::SHRD";
10589 case X86ISD::FAND: return "X86ISD::FAND";
10590 case X86ISD::FOR: return "X86ISD::FOR";
10591 case X86ISD::FXOR: return "X86ISD::FXOR";
10592 case X86ISD::FSRL: return "X86ISD::FSRL";
10593 case X86ISD::FILD: return "X86ISD::FILD";
10594 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
10595 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
10596 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
10597 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
10598 case X86ISD::FLD: return "X86ISD::FLD";
10599 case X86ISD::FST: return "X86ISD::FST";
10600 case X86ISD::CALL: return "X86ISD::CALL";
10601 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
10602 case X86ISD::BT: return "X86ISD::BT";
10603 case X86ISD::CMP: return "X86ISD::CMP";
10604 case X86ISD::COMI: return "X86ISD::COMI";
10605 case X86ISD::UCOMI: return "X86ISD::UCOMI";
10606 case X86ISD::SETCC: return "X86ISD::SETCC";
10607 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
10608 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
10609 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
10610 case X86ISD::CMOV: return "X86ISD::CMOV";
10611 case X86ISD::BRCOND: return "X86ISD::BRCOND";
10612 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
10613 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
10614 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
10615 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
10616 case X86ISD::Wrapper: return "X86ISD::Wrapper";
10617 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
10618 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
10619 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
10620 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
10621 case X86ISD::PINSRB: return "X86ISD::PINSRB";
10622 case X86ISD::PINSRW: return "X86ISD::PINSRW";
10623 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
10624 case X86ISD::ANDNP: return "X86ISD::ANDNP";
10625 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
10626 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
10627 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10628 case X86ISD::FMAX: return "X86ISD::FMAX";
10629 case X86ISD::FMIN: return "X86ISD::FMIN";
10630 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
10631 case X86ISD::FRCP: return "X86ISD::FRCP";
10632 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
10633 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
10634 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
10635 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
10636 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
10637 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
10638 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
10639 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
10640 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
10641 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
10642 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
10643 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
10644 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
10645 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
10646 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
10647 case X86ISD::VSHL: return "X86ISD::VSHL";
10648 case X86ISD::VSRL: return "X86ISD::VSRL";
10649 case X86ISD::CMPPD: return "X86ISD::CMPPD";
10650 case X86ISD::CMPPS: return "X86ISD::CMPPS";
10651 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
10652 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
10653 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
10654 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
10655 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
10656 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
10657 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
10658 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
10659 case X86ISD::ADD: return "X86ISD::ADD";
10660 case X86ISD::SUB: return "X86ISD::SUB";
10661 case X86ISD::ADC: return "X86ISD::ADC";
10662 case X86ISD::SBB: return "X86ISD::SBB";
10663 case X86ISD::SMUL: return "X86ISD::SMUL";
10664 case X86ISD::UMUL: return "X86ISD::UMUL";
10665 case X86ISD::INC: return "X86ISD::INC";
10666 case X86ISD::DEC: return "X86ISD::DEC";
10667 case X86ISD::OR: return "X86ISD::OR";
10668 case X86ISD::XOR: return "X86ISD::XOR";
10669 case X86ISD::AND: return "X86ISD::AND";
10670 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
10671 case X86ISD::PTEST: return "X86ISD::PTEST";
10672 case X86ISD::TESTP: return "X86ISD::TESTP";
10673 case X86ISD::PALIGN: return "X86ISD::PALIGN";
10674 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
10675 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
10676 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD";
10677 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
10678 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD";
10679 case X86ISD::SHUFPS: return "X86ISD::SHUFPS";
10680 case X86ISD::SHUFPD: return "X86ISD::SHUFPD";
10681 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
10682 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
10683 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
10684 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD";
10685 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
10686 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
10687 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
10688 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
10689 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
10690 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD";
10691 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD";
10692 case X86ISD::MOVSD: return "X86ISD::MOVSD";
10693 case X86ISD::MOVSS: return "X86ISD::MOVSS";
10694 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS";
10695 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD";
10696 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY";
10697 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS";
10698 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD";
10699 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW";
10700 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD";
10701 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ";
10702 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ";
10703 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW";
10704 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD";
10705 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ";
10706 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ";
10707 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
10708 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS";
10709 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY";
10710 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD";
10711 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY";
10712 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128";
10713 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
10714 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
10715 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
10716 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
10717 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
10721 // isLegalAddressingMode - Return true if the addressing mode represented
10722 // by AM is legal for this target, for a load/store of the specified type.
10723 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
10725 // X86 supports extremely general addressing modes.
10726 CodeModel::Model M = getTargetMachine().getCodeModel();
10727 Reloc::Model R = getTargetMachine().getRelocationModel();
10729 // X86 allows a sign-extended 32-bit immediate field as a displacement.
10730 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
10735 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
10737 // If a reference to this global requires an extra load, we can't fold it.
10738 if (isGlobalStubReference(GVFlags))
10741 // If BaseGV requires a register for the PIC base, we cannot also have a
10742 // BaseReg specified.
10743 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
10746 // If lower 4G is not available, then we must use rip-relative addressing.
10747 if ((M != CodeModel::Small || R != Reloc::Static) &&
10748 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
10752 switch (AM.Scale) {
10758 // These scales always work.
10763 // These scales are formed with basereg+scalereg. Only accept if there is
10768 default: // Other stuff never works.
10776 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10777 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10779 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10780 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10781 if (NumBits1 <= NumBits2)
10786 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10787 if (!VT1.isInteger() || !VT2.isInteger())
10789 unsigned NumBits1 = VT1.getSizeInBits();
10790 unsigned NumBits2 = VT2.getSizeInBits();
10791 if (NumBits1 <= NumBits2)
10796 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
10797 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10798 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
10801 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
10802 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
10803 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
10806 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
10807 // i16 instructions are longer (0x66 prefix) and potentially slower.
10808 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
10811 /// isShuffleMaskLegal - Targets can use this to indicate that they only
10812 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
10813 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
10814 /// are assumed to be legal.
10816 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
10818 // Very little shuffling can be done for 64-bit vectors right now.
10819 if (VT.getSizeInBits() == 64)
10820 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3());
10822 // FIXME: pshufb, blends, shifts.
10823 return (VT.getVectorNumElements() == 2 ||
10824 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
10825 isMOVLMask(M, VT) ||
10826 isSHUFPMask(M, VT) ||
10827 isPSHUFDMask(M, VT) ||
10828 isPSHUFHWMask(M, VT) ||
10829 isPSHUFLWMask(M, VT) ||
10830 isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
10831 isUNPCKLMask(M, VT) ||
10832 isUNPCKHMask(M, VT) ||
10833 isUNPCKL_v_undef_Mask(M, VT) ||
10834 isUNPCKH_v_undef_Mask(M, VT));
10838 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
10840 unsigned NumElts = VT.getVectorNumElements();
10841 // FIXME: This collection of masks seems suspect.
10844 if (NumElts == 4 && VT.getSizeInBits() == 128) {
10845 return (isMOVLMask(Mask, VT) ||
10846 isCommutedMOVLMask(Mask, VT, true) ||
10847 isSHUFPMask(Mask, VT) ||
10848 isCommutedSHUFPMask(Mask, VT));
10853 //===----------------------------------------------------------------------===//
10854 // X86 Scheduler Hooks
10855 //===----------------------------------------------------------------------===//
10857 // private utility function
10858 MachineBasicBlock *
10859 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
10860 MachineBasicBlock *MBB,
10867 TargetRegisterClass *RC,
10868 bool invSrc) const {
10869 // For the atomic bitwise operator, we generate
10872 // ld t1 = [bitinstr.addr]
10873 // op t2 = t1, [bitinstr.val]
10875 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
10877 // fallthrough -->nextMBB
10878 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10879 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10880 MachineFunction::iterator MBBIter = MBB;
10883 /// First build the CFG
10884 MachineFunction *F = MBB->getParent();
10885 MachineBasicBlock *thisMBB = MBB;
10886 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10887 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10888 F->insert(MBBIter, newMBB);
10889 F->insert(MBBIter, nextMBB);
10891 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
10892 nextMBB->splice(nextMBB->begin(), thisMBB,
10893 llvm::next(MachineBasicBlock::iterator(bInstr)),
10895 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
10897 // Update thisMBB to fall through to newMBB
10898 thisMBB->addSuccessor(newMBB);
10900 // newMBB jumps to itself and fall through to nextMBB
10901 newMBB->addSuccessor(nextMBB);
10902 newMBB->addSuccessor(newMBB);
10904 // Insert instructions into newMBB based on incoming instruction
10905 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
10906 "unexpected number of operands");
10907 DebugLoc dl = bInstr->getDebugLoc();
10908 MachineOperand& destOper = bInstr->getOperand(0);
10909 MachineOperand* argOpers[2 + X86::AddrNumOperands];
10910 int numArgs = bInstr->getNumOperands() - 1;
10911 for (int i=0; i < numArgs; ++i)
10912 argOpers[i] = &bInstr->getOperand(i+1);
10914 // x86 address has 4 operands: base, index, scale, and displacement
10915 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
10916 int valArgIndx = lastAddrIndx + 1;
10918 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
10919 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
10920 for (int i=0; i <= lastAddrIndx; ++i)
10921 (*MIB).addOperand(*argOpers[i]);
10923 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
10925 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
10930 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
10931 assert((argOpers[valArgIndx]->isReg() ||
10932 argOpers[valArgIndx]->isImm()) &&
10933 "invalid operand");
10934 if (argOpers[valArgIndx]->isReg())
10935 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
10937 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
10939 (*MIB).addOperand(*argOpers[valArgIndx]);
10941 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
10944 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
10945 for (int i=0; i <= lastAddrIndx; ++i)
10946 (*MIB).addOperand(*argOpers[i]);
10948 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
10949 (*MIB).setMemRefs(bInstr->memoperands_begin(),
10950 bInstr->memoperands_end());
10952 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
10953 MIB.addReg(EAXreg);
10956 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
10958 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
10962 // private utility function: 64 bit atomics on 32 bit host.
10963 MachineBasicBlock *
10964 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
10965 MachineBasicBlock *MBB,
10970 bool invSrc) const {
10971 // For the atomic bitwise operator, we generate
10972 // thisMBB (instructions are in pairs, except cmpxchg8b)
10973 // ld t1,t2 = [bitinstr.addr]
10975 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
10976 // op t5, t6 <- out1, out2, [bitinstr.val]
10977 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
10978 // mov ECX, EBX <- t5, t6
10979 // mov EAX, EDX <- t1, t2
10980 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
10981 // mov t3, t4 <- EAX, EDX
10983 // result in out1, out2
10984 // fallthrough -->nextMBB
10986 const TargetRegisterClass *RC = X86::GR32RegisterClass;
10987 const unsigned LoadOpc = X86::MOV32rm;
10988 const unsigned NotOpc = X86::NOT32r;
10989 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
10990 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
10991 MachineFunction::iterator MBBIter = MBB;
10994 /// First build the CFG
10995 MachineFunction *F = MBB->getParent();
10996 MachineBasicBlock *thisMBB = MBB;
10997 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
10998 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
10999 F->insert(MBBIter, newMBB);
11000 F->insert(MBBIter, nextMBB);
11002 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11003 nextMBB->splice(nextMBB->begin(), thisMBB,
11004 llvm::next(MachineBasicBlock::iterator(bInstr)),
11006 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11008 // Update thisMBB to fall through to newMBB
11009 thisMBB->addSuccessor(newMBB);
11011 // newMBB jumps to itself and fall through to nextMBB
11012 newMBB->addSuccessor(nextMBB);
11013 newMBB->addSuccessor(newMBB);
11015 DebugLoc dl = bInstr->getDebugLoc();
11016 // Insert instructions into newMBB based on incoming instruction
11017 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
11018 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 &&
11019 "unexpected number of operands");
11020 MachineOperand& dest1Oper = bInstr->getOperand(0);
11021 MachineOperand& dest2Oper = bInstr->getOperand(1);
11022 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11023 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) {
11024 argOpers[i] = &bInstr->getOperand(i+2);
11026 // We use some of the operands multiple times, so conservatively just
11027 // clear any kill flags that might be present.
11028 if (argOpers[i]->isReg() && argOpers[i]->isUse())
11029 argOpers[i]->setIsKill(false);
11032 // x86 address has 5 operands: base, index, scale, displacement, and segment.
11033 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11035 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
11036 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
11037 for (int i=0; i <= lastAddrIndx; ++i)
11038 (*MIB).addOperand(*argOpers[i]);
11039 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
11040 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
11041 // add 4 to displacement.
11042 for (int i=0; i <= lastAddrIndx-2; ++i)
11043 (*MIB).addOperand(*argOpers[i]);
11044 MachineOperand newOp3 = *(argOpers[3]);
11045 if (newOp3.isImm())
11046 newOp3.setImm(newOp3.getImm()+4);
11048 newOp3.setOffset(newOp3.getOffset()+4);
11049 (*MIB).addOperand(newOp3);
11050 (*MIB).addOperand(*argOpers[lastAddrIndx]);
11052 // t3/4 are defined later, at the bottom of the loop
11053 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
11054 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
11055 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
11056 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
11057 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
11058 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
11060 // The subsequent operations should be using the destination registers of
11061 //the PHI instructions.
11063 t1 = F->getRegInfo().createVirtualRegister(RC);
11064 t2 = F->getRegInfo().createVirtualRegister(RC);
11065 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
11066 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
11068 t1 = dest1Oper.getReg();
11069 t2 = dest2Oper.getReg();
11072 int valArgIndx = lastAddrIndx + 1;
11073 assert((argOpers[valArgIndx]->isReg() ||
11074 argOpers[valArgIndx]->isImm()) &&
11075 "invalid operand");
11076 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
11077 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
11078 if (argOpers[valArgIndx]->isReg())
11079 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
11081 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
11082 if (regOpcL != X86::MOV32rr)
11084 (*MIB).addOperand(*argOpers[valArgIndx]);
11085 assert(argOpers[valArgIndx + 1]->isReg() ==
11086 argOpers[valArgIndx]->isReg());
11087 assert(argOpers[valArgIndx + 1]->isImm() ==
11088 argOpers[valArgIndx]->isImm());
11089 if (argOpers[valArgIndx + 1]->isReg())
11090 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
11092 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
11093 if (regOpcH != X86::MOV32rr)
11095 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
11097 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11099 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
11102 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
11104 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
11107 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
11108 for (int i=0; i <= lastAddrIndx; ++i)
11109 (*MIB).addOperand(*argOpers[i]);
11111 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11112 (*MIB).setMemRefs(bInstr->memoperands_begin(),
11113 bInstr->memoperands_end());
11115 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3);
11116 MIB.addReg(X86::EAX);
11117 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4);
11118 MIB.addReg(X86::EDX);
11121 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11123 bInstr->eraseFromParent(); // The pseudo instruction is gone now.
11127 // private utility function
11128 MachineBasicBlock *
11129 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
11130 MachineBasicBlock *MBB,
11131 unsigned cmovOpc) const {
11132 // For the atomic min/max operator, we generate
11135 // ld t1 = [min/max.addr]
11136 // mov t2 = [min/max.val]
11138 // cmov[cond] t2 = t1
11140 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
11142 // fallthrough -->nextMBB
11144 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11145 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11146 MachineFunction::iterator MBBIter = MBB;
11149 /// First build the CFG
11150 MachineFunction *F = MBB->getParent();
11151 MachineBasicBlock *thisMBB = MBB;
11152 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
11153 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
11154 F->insert(MBBIter, newMBB);
11155 F->insert(MBBIter, nextMBB);
11157 // Transfer the remainder of thisMBB and its successor edges to nextMBB.
11158 nextMBB->splice(nextMBB->begin(), thisMBB,
11159 llvm::next(MachineBasicBlock::iterator(mInstr)),
11161 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11163 // Update thisMBB to fall through to newMBB
11164 thisMBB->addSuccessor(newMBB);
11166 // newMBB jumps to newMBB and fall through to nextMBB
11167 newMBB->addSuccessor(nextMBB);
11168 newMBB->addSuccessor(newMBB);
11170 DebugLoc dl = mInstr->getDebugLoc();
11171 // Insert instructions into newMBB based on incoming instruction
11172 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 &&
11173 "unexpected number of operands");
11174 MachineOperand& destOper = mInstr->getOperand(0);
11175 MachineOperand* argOpers[2 + X86::AddrNumOperands];
11176 int numArgs = mInstr->getNumOperands() - 1;
11177 for (int i=0; i < numArgs; ++i)
11178 argOpers[i] = &mInstr->getOperand(i+1);
11180 // x86 address has 4 operands: base, index, scale, and displacement
11181 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3]
11182 int valArgIndx = lastAddrIndx + 1;
11184 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11185 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
11186 for (int i=0; i <= lastAddrIndx; ++i)
11187 (*MIB).addOperand(*argOpers[i]);
11189 // We only support register and immediate values
11190 assert((argOpers[valArgIndx]->isReg() ||
11191 argOpers[valArgIndx]->isImm()) &&
11192 "invalid operand");
11194 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11195 if (argOpers[valArgIndx]->isReg())
11196 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2);
11198 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
11199 (*MIB).addOperand(*argOpers[valArgIndx]);
11201 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
11204 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
11209 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
11210 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
11214 // Cmp and exchange if none has modified the memory location
11215 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
11216 for (int i=0; i <= lastAddrIndx; ++i)
11217 (*MIB).addOperand(*argOpers[i]);
11219 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
11220 (*MIB).setMemRefs(mInstr->memoperands_begin(),
11221 mInstr->memoperands_end());
11223 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg());
11224 MIB.addReg(X86::EAX);
11227 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB);
11229 mInstr->eraseFromParent(); // The pseudo instruction is gone now.
11233 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
11234 // or XMM0_V32I8 in AVX all of this code can be replaced with that
11235 // in the .td file.
11236 MachineBasicBlock *
11237 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB,
11238 unsigned numArgs, bool memArg) const {
11239 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) &&
11240 "Target must have SSE4.2 or AVX features enabled");
11242 DebugLoc dl = MI->getDebugLoc();
11243 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11245 if (!Subtarget->hasAVX()) {
11247 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm;
11249 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr;
11252 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm;
11254 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr;
11257 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
11258 for (unsigned i = 0; i < numArgs; ++i) {
11259 MachineOperand &Op = MI->getOperand(i+1);
11260 if (!(Op.isReg() && Op.isImplicit()))
11261 MIB.addOperand(Op);
11263 BuildMI(*BB, MI, dl,
11264 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr),
11265 MI->getOperand(0).getReg())
11266 .addReg(X86::XMM0);
11268 MI->eraseFromParent();
11272 MachineBasicBlock *
11273 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
11274 DebugLoc dl = MI->getDebugLoc();
11275 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11277 // Address into RAX/EAX, other two args into ECX, EDX.
11278 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
11279 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11280 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
11281 for (int i = 0; i < X86::AddrNumOperands; ++i)
11282 MIB.addOperand(MI->getOperand(i));
11284 unsigned ValOps = X86::AddrNumOperands;
11285 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11286 .addReg(MI->getOperand(ValOps).getReg());
11287 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
11288 .addReg(MI->getOperand(ValOps+1).getReg());
11290 // The instruction doesn't actually take any operands though.
11291 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
11293 MI->eraseFromParent(); // The pseudo is gone now.
11297 MachineBasicBlock *
11298 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
11299 DebugLoc dl = MI->getDebugLoc();
11300 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11302 // First arg in ECX, the second in EAX.
11303 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
11304 .addReg(MI->getOperand(0).getReg());
11305 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX)
11306 .addReg(MI->getOperand(1).getReg());
11308 // The instruction doesn't actually take any operands though.
11309 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr));
11311 MI->eraseFromParent(); // The pseudo is gone now.
11315 MachineBasicBlock *
11316 X86TargetLowering::EmitVAARG64WithCustomInserter(
11318 MachineBasicBlock *MBB) const {
11319 // Emit va_arg instruction on X86-64.
11321 // Operands to this pseudo-instruction:
11322 // 0 ) Output : destination address (reg)
11323 // 1-5) Input : va_list address (addr, i64mem)
11324 // 6 ) ArgSize : Size (in bytes) of vararg type
11325 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
11326 // 8 ) Align : Alignment of type
11327 // 9 ) EFLAGS (implicit-def)
11329 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
11330 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
11332 unsigned DestReg = MI->getOperand(0).getReg();
11333 MachineOperand &Base = MI->getOperand(1);
11334 MachineOperand &Scale = MI->getOperand(2);
11335 MachineOperand &Index = MI->getOperand(3);
11336 MachineOperand &Disp = MI->getOperand(4);
11337 MachineOperand &Segment = MI->getOperand(5);
11338 unsigned ArgSize = MI->getOperand(6).getImm();
11339 unsigned ArgMode = MI->getOperand(7).getImm();
11340 unsigned Align = MI->getOperand(8).getImm();
11342 // Memory Reference
11343 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
11344 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
11345 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
11347 // Machine Information
11348 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11349 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
11350 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
11351 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
11352 DebugLoc DL = MI->getDebugLoc();
11354 // struct va_list {
11357 // i64 overflow_area (address)
11358 // i64 reg_save_area (address)
11360 // sizeof(va_list) = 24
11361 // alignment(va_list) = 8
11363 unsigned TotalNumIntRegs = 6;
11364 unsigned TotalNumXMMRegs = 8;
11365 bool UseGPOffset = (ArgMode == 1);
11366 bool UseFPOffset = (ArgMode == 2);
11367 unsigned MaxOffset = TotalNumIntRegs * 8 +
11368 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
11370 /* Align ArgSize to a multiple of 8 */
11371 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
11372 bool NeedsAlign = (Align > 8);
11374 MachineBasicBlock *thisMBB = MBB;
11375 MachineBasicBlock *overflowMBB;
11376 MachineBasicBlock *offsetMBB;
11377 MachineBasicBlock *endMBB;
11379 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
11380 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
11381 unsigned OffsetReg = 0;
11383 if (!UseGPOffset && !UseFPOffset) {
11384 // If we only pull from the overflow region, we don't create a branch.
11385 // We don't need to alter control flow.
11386 OffsetDestReg = 0; // unused
11387 OverflowDestReg = DestReg;
11390 overflowMBB = thisMBB;
11393 // First emit code to check if gp_offset (or fp_offset) is below the bound.
11394 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
11395 // If not, pull from overflow_area. (branch to overflowMBB)
11400 // offsetMBB overflowMBB
11405 // Registers for the PHI in endMBB
11406 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
11407 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
11409 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11410 MachineFunction *MF = MBB->getParent();
11411 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11412 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11413 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11415 MachineFunction::iterator MBBIter = MBB;
11418 // Insert the new basic blocks
11419 MF->insert(MBBIter, offsetMBB);
11420 MF->insert(MBBIter, overflowMBB);
11421 MF->insert(MBBIter, endMBB);
11423 // Transfer the remainder of MBB and its successor edges to endMBB.
11424 endMBB->splice(endMBB->begin(), thisMBB,
11425 llvm::next(MachineBasicBlock::iterator(MI)),
11427 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
11429 // Make offsetMBB and overflowMBB successors of thisMBB
11430 thisMBB->addSuccessor(offsetMBB);
11431 thisMBB->addSuccessor(overflowMBB);
11433 // endMBB is a successor of both offsetMBB and overflowMBB
11434 offsetMBB->addSuccessor(endMBB);
11435 overflowMBB->addSuccessor(endMBB);
11437 // Load the offset value into a register
11438 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11439 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
11443 .addDisp(Disp, UseFPOffset ? 4 : 0)
11444 .addOperand(Segment)
11445 .setMemRefs(MMOBegin, MMOEnd);
11447 // Check if there is enough room left to pull this argument.
11448 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
11450 .addImm(MaxOffset + 8 - ArgSizeA8);
11452 // Branch to "overflowMBB" if offset >= max
11453 // Fall through to "offsetMBB" otherwise
11454 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
11455 .addMBB(overflowMBB);
11458 // In offsetMBB, emit code to use the reg_save_area.
11460 assert(OffsetReg != 0);
11462 // Read the reg_save_area address.
11463 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
11464 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
11469 .addOperand(Segment)
11470 .setMemRefs(MMOBegin, MMOEnd);
11472 // Zero-extend the offset
11473 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
11474 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
11477 .addImm(X86::sub_32bit);
11479 // Add the offset to the reg_save_area to get the final address.
11480 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
11481 .addReg(OffsetReg64)
11482 .addReg(RegSaveReg);
11484 // Compute the offset for the next argument
11485 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
11486 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
11488 .addImm(UseFPOffset ? 16 : 8);
11490 // Store it back into the va_list.
11491 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
11495 .addDisp(Disp, UseFPOffset ? 4 : 0)
11496 .addOperand(Segment)
11497 .addReg(NextOffsetReg)
11498 .setMemRefs(MMOBegin, MMOEnd);
11501 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
11506 // Emit code to use overflow area
11509 // Load the overflow_area address into a register.
11510 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
11511 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
11516 .addOperand(Segment)
11517 .setMemRefs(MMOBegin, MMOEnd);
11519 // If we need to align it, do so. Otherwise, just copy the address
11520 // to OverflowDestReg.
11522 // Align the overflow address
11523 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
11524 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
11526 // aligned_addr = (addr + (align-1)) & ~(align-1)
11527 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
11528 .addReg(OverflowAddrReg)
11531 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
11533 .addImm(~(uint64_t)(Align-1));
11535 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
11536 .addReg(OverflowAddrReg);
11539 // Compute the next overflow address after this argument.
11540 // (the overflow address should be kept 8-byte aligned)
11541 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
11542 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
11543 .addReg(OverflowDestReg)
11544 .addImm(ArgSizeA8);
11546 // Store the new overflow address.
11547 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
11552 .addOperand(Segment)
11553 .addReg(NextAddrReg)
11554 .setMemRefs(MMOBegin, MMOEnd);
11556 // If we branched, emit the PHI to the front of endMBB.
11558 BuildMI(*endMBB, endMBB->begin(), DL,
11559 TII->get(X86::PHI), DestReg)
11560 .addReg(OffsetDestReg).addMBB(offsetMBB)
11561 .addReg(OverflowDestReg).addMBB(overflowMBB);
11564 // Erase the pseudo instruction
11565 MI->eraseFromParent();
11570 MachineBasicBlock *
11571 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
11573 MachineBasicBlock *MBB) const {
11574 // Emit code to save XMM registers to the stack. The ABI says that the
11575 // number of registers to save is given in %al, so it's theoretically
11576 // possible to do an indirect jump trick to avoid saving all of them,
11577 // however this code takes a simpler approach and just executes all
11578 // of the stores if %al is non-zero. It's less code, and it's probably
11579 // easier on the hardware branch predictor, and stores aren't all that
11580 // expensive anyway.
11582 // Create the new basic blocks. One block contains all the XMM stores,
11583 // and one block is the final destination regardless of whether any
11584 // stores were performed.
11585 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
11586 MachineFunction *F = MBB->getParent();
11587 MachineFunction::iterator MBBIter = MBB;
11589 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
11590 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
11591 F->insert(MBBIter, XMMSaveMBB);
11592 F->insert(MBBIter, EndMBB);
11594 // Transfer the remainder of MBB and its successor edges to EndMBB.
11595 EndMBB->splice(EndMBB->begin(), MBB,
11596 llvm::next(MachineBasicBlock::iterator(MI)),
11598 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
11600 // The original block will now fall through to the XMM save block.
11601 MBB->addSuccessor(XMMSaveMBB);
11602 // The XMMSaveMBB will fall through to the end block.
11603 XMMSaveMBB->addSuccessor(EndMBB);
11605 // Now add the instructions.
11606 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11607 DebugLoc DL = MI->getDebugLoc();
11609 unsigned CountReg = MI->getOperand(0).getReg();
11610 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
11611 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
11613 if (!Subtarget->isTargetWin64()) {
11614 // If %al is 0, branch around the XMM save block.
11615 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
11616 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
11617 MBB->addSuccessor(EndMBB);
11620 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr;
11621 // In the XMM save block, save all the XMM argument registers.
11622 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
11623 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
11624 MachineMemOperand *MMO =
11625 F->getMachineMemOperand(
11626 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
11627 MachineMemOperand::MOStore,
11628 /*Size=*/16, /*Align=*/16);
11629 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
11630 .addFrameIndex(RegSaveFrameIndex)
11631 .addImm(/*Scale=*/1)
11632 .addReg(/*IndexReg=*/0)
11633 .addImm(/*Disp=*/Offset)
11634 .addReg(/*Segment=*/0)
11635 .addReg(MI->getOperand(i).getReg())
11636 .addMemOperand(MMO);
11639 MI->eraseFromParent(); // The pseudo instruction is gone now.
11644 MachineBasicBlock *
11645 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
11646 MachineBasicBlock *BB) const {
11647 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11648 DebugLoc DL = MI->getDebugLoc();
11650 // To "insert" a SELECT_CC instruction, we actually have to insert the
11651 // diamond control-flow pattern. The incoming instruction knows the
11652 // destination vreg to set, the condition code register to branch on, the
11653 // true/false values to select between, and a branch opcode to use.
11654 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11655 MachineFunction::iterator It = BB;
11661 // cmpTY ccX, r1, r2
11663 // fallthrough --> copy0MBB
11664 MachineBasicBlock *thisMBB = BB;
11665 MachineFunction *F = BB->getParent();
11666 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
11667 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
11668 F->insert(It, copy0MBB);
11669 F->insert(It, sinkMBB);
11671 // If the EFLAGS register isn't dead in the terminator, then claim that it's
11672 // live into the sink and copy blocks.
11673 if (!MI->killsRegister(X86::EFLAGS)) {
11674 copy0MBB->addLiveIn(X86::EFLAGS);
11675 sinkMBB->addLiveIn(X86::EFLAGS);
11678 // Transfer the remainder of BB and its successor edges to sinkMBB.
11679 sinkMBB->splice(sinkMBB->begin(), BB,
11680 llvm::next(MachineBasicBlock::iterator(MI)),
11682 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
11684 // Add the true and fallthrough blocks as its successors.
11685 BB->addSuccessor(copy0MBB);
11686 BB->addSuccessor(sinkMBB);
11688 // Create the conditional branch instruction.
11690 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
11691 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
11694 // %FalseValue = ...
11695 // # fallthrough to sinkMBB
11696 copy0MBB->addSuccessor(sinkMBB);
11699 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
11701 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
11702 TII->get(X86::PHI), MI->getOperand(0).getReg())
11703 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
11704 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
11706 MI->eraseFromParent(); // The pseudo instruction is gone now.
11710 MachineBasicBlock *
11711 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
11712 bool Is64Bit) const {
11713 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11714 DebugLoc DL = MI->getDebugLoc();
11715 MachineFunction *MF = BB->getParent();
11716 const BasicBlock *LLVM_BB = BB->getBasicBlock();
11718 assert(EnableSegmentedStacks);
11720 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
11721 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
11724 // ... [Till the alloca]
11725 // If stacklet is not large enough, jump to mallocMBB
11728 // Allocate by subtracting from RSP
11729 // Jump to continueMBB
11732 // Allocate by call to runtime
11736 // [rest of original BB]
11739 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11740 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11741 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
11743 MachineRegisterInfo &MRI = MF->getRegInfo();
11744 const TargetRegisterClass *AddrRegClass =
11745 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
11747 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11748 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
11749 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
11750 sizeVReg = MI->getOperand(1).getReg(),
11751 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
11753 MachineFunction::iterator MBBIter = BB;
11756 MF->insert(MBBIter, bumpMBB);
11757 MF->insert(MBBIter, mallocMBB);
11758 MF->insert(MBBIter, continueMBB);
11760 continueMBB->splice(continueMBB->begin(), BB, llvm::next
11761 (MachineBasicBlock::iterator(MI)), BB->end());
11762 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
11764 // Add code to the main basic block to check if the stack limit has been hit,
11765 // and if so, jump to mallocMBB otherwise to bumpMBB.
11766 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
11767 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg)
11768 .addReg(tmpSPVReg).addReg(sizeVReg);
11769 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
11770 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg)
11771 .addReg(tmpSPVReg);
11772 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
11774 // bumpMBB simply decreases the stack pointer, since we know the current
11775 // stacklet has enough space.
11776 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
11777 .addReg(tmpSPVReg);
11778 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
11779 .addReg(tmpSPVReg);
11780 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11782 // Calls into a routine in libgcc to allocate more space from the heap.
11784 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
11786 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
11787 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI);
11789 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
11791 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
11792 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
11793 .addExternalSymbol("__morestack_allocate_stack_space");
11797 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
11800 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
11801 .addReg(Is64Bit ? X86::RAX : X86::EAX);
11802 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
11804 // Set up the CFG correctly.
11805 BB->addSuccessor(bumpMBB);
11806 BB->addSuccessor(mallocMBB);
11807 mallocMBB->addSuccessor(continueMBB);
11808 bumpMBB->addSuccessor(continueMBB);
11810 // Take care of the PHI nodes.
11811 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
11812 MI->getOperand(0).getReg())
11813 .addReg(mallocPtrVReg).addMBB(mallocMBB)
11814 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
11816 // Delete the original pseudo instruction.
11817 MI->eraseFromParent();
11820 return continueMBB;
11823 MachineBasicBlock *
11824 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
11825 MachineBasicBlock *BB) const {
11826 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11827 DebugLoc DL = MI->getDebugLoc();
11829 assert(!Subtarget->isTargetEnvMacho());
11831 // The lowering is pretty easy: we're just emitting the call to _alloca. The
11832 // non-trivial part is impdef of ESP.
11834 if (Subtarget->isTargetWin64()) {
11835 if (Subtarget->isTargetCygMing()) {
11836 // ___chkstk(Mingw64):
11837 // Clobbers R10, R11, RAX and EFLAGS.
11839 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11840 .addExternalSymbol("___chkstk")
11841 .addReg(X86::RAX, RegState::Implicit)
11842 .addReg(X86::RSP, RegState::Implicit)
11843 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
11844 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
11845 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11847 // __chkstk(MSVCRT): does not update stack pointer.
11848 // Clobbers R10, R11 and EFLAGS.
11849 // FIXME: RAX(allocated size) might be reused and not killed.
11850 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
11851 .addExternalSymbol("__chkstk")
11852 .addReg(X86::RAX, RegState::Implicit)
11853 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11854 // RAX has the offset to subtracted from RSP.
11855 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
11860 const char *StackProbeSymbol =
11861 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
11863 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
11864 .addExternalSymbol(StackProbeSymbol)
11865 .addReg(X86::EAX, RegState::Implicit)
11866 .addReg(X86::ESP, RegState::Implicit)
11867 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
11868 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
11869 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
11872 MI->eraseFromParent(); // The pseudo instruction is gone now.
11876 MachineBasicBlock *
11877 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
11878 MachineBasicBlock *BB) const {
11879 // This is pretty easy. We're taking the value that we received from
11880 // our load from the relocation, sticking it in either RDI (x86-64)
11881 // or EAX and doing an indirect call. The return value will then
11882 // be in the normal return register.
11883 const X86InstrInfo *TII
11884 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
11885 DebugLoc DL = MI->getDebugLoc();
11886 MachineFunction *F = BB->getParent();
11888 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
11889 assert(MI->getOperand(3).isGlobal() && "This should be a global");
11891 if (Subtarget->is64Bit()) {
11892 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11893 TII->get(X86::MOV64rm), X86::RDI)
11895 .addImm(0).addReg(0)
11896 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11897 MI->getOperand(3).getTargetFlags())
11899 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
11900 addDirectMem(MIB, X86::RDI);
11901 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
11902 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11903 TII->get(X86::MOV32rm), X86::EAX)
11905 .addImm(0).addReg(0)
11906 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11907 MI->getOperand(3).getTargetFlags())
11909 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11910 addDirectMem(MIB, X86::EAX);
11912 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
11913 TII->get(X86::MOV32rm), X86::EAX)
11914 .addReg(TII->getGlobalBaseReg(F))
11915 .addImm(0).addReg(0)
11916 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
11917 MI->getOperand(3).getTargetFlags())
11919 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
11920 addDirectMem(MIB, X86::EAX);
11923 MI->eraseFromParent(); // The pseudo instruction is gone now.
11927 MachineBasicBlock *
11928 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
11929 MachineBasicBlock *BB) const {
11930 switch (MI->getOpcode()) {
11931 default: assert(false && "Unexpected instr type to insert");
11932 case X86::TAILJMPd64:
11933 case X86::TAILJMPr64:
11934 case X86::TAILJMPm64:
11935 assert(!"TAILJMP64 would not be touched here.");
11936 case X86::TCRETURNdi64:
11937 case X86::TCRETURNri64:
11938 case X86::TCRETURNmi64:
11939 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset.
11940 // On AMD64, additional defs should be added before register allocation.
11941 if (!Subtarget->isTargetWin64()) {
11942 MI->addRegisterDefined(X86::RSI);
11943 MI->addRegisterDefined(X86::RDI);
11944 MI->addRegisterDefined(X86::XMM6);
11945 MI->addRegisterDefined(X86::XMM7);
11946 MI->addRegisterDefined(X86::XMM8);
11947 MI->addRegisterDefined(X86::XMM9);
11948 MI->addRegisterDefined(X86::XMM10);
11949 MI->addRegisterDefined(X86::XMM11);
11950 MI->addRegisterDefined(X86::XMM12);
11951 MI->addRegisterDefined(X86::XMM13);
11952 MI->addRegisterDefined(X86::XMM14);
11953 MI->addRegisterDefined(X86::XMM15);
11956 case X86::WIN_ALLOCA:
11957 return EmitLoweredWinAlloca(MI, BB);
11958 case X86::SEG_ALLOCA_32:
11959 return EmitLoweredSegAlloca(MI, BB, false);
11960 case X86::SEG_ALLOCA_64:
11961 return EmitLoweredSegAlloca(MI, BB, true);
11962 case X86::TLSCall_32:
11963 case X86::TLSCall_64:
11964 return EmitLoweredTLSCall(MI, BB);
11965 case X86::CMOV_GR8:
11966 case X86::CMOV_FR32:
11967 case X86::CMOV_FR64:
11968 case X86::CMOV_V4F32:
11969 case X86::CMOV_V2F64:
11970 case X86::CMOV_V2I64:
11971 case X86::CMOV_V8F32:
11972 case X86::CMOV_V4F64:
11973 case X86::CMOV_V4I64:
11974 case X86::CMOV_GR16:
11975 case X86::CMOV_GR32:
11976 case X86::CMOV_RFP32:
11977 case X86::CMOV_RFP64:
11978 case X86::CMOV_RFP80:
11979 return EmitLoweredSelect(MI, BB);
11981 case X86::FP32_TO_INT16_IN_MEM:
11982 case X86::FP32_TO_INT32_IN_MEM:
11983 case X86::FP32_TO_INT64_IN_MEM:
11984 case X86::FP64_TO_INT16_IN_MEM:
11985 case X86::FP64_TO_INT32_IN_MEM:
11986 case X86::FP64_TO_INT64_IN_MEM:
11987 case X86::FP80_TO_INT16_IN_MEM:
11988 case X86::FP80_TO_INT32_IN_MEM:
11989 case X86::FP80_TO_INT64_IN_MEM: {
11990 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
11991 DebugLoc DL = MI->getDebugLoc();
11993 // Change the floating point control register to use "round towards zero"
11994 // mode when truncating to an integer value.
11995 MachineFunction *F = BB->getParent();
11996 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
11997 addFrameReference(BuildMI(*BB, MI, DL,
11998 TII->get(X86::FNSTCW16m)), CWFrameIdx);
12000 // Load the old value of the high byte of the control word...
12002 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
12003 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
12006 // Set the high part to be round to zero...
12007 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
12010 // Reload the modified control word now...
12011 addFrameReference(BuildMI(*BB, MI, DL,
12012 TII->get(X86::FLDCW16m)), CWFrameIdx);
12014 // Restore the memory image of control word to original value
12015 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
12018 // Get the X86 opcode to use.
12020 switch (MI->getOpcode()) {
12021 default: llvm_unreachable("illegal opcode!");
12022 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
12023 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
12024 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
12025 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
12026 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
12027 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
12028 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
12029 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
12030 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
12034 MachineOperand &Op = MI->getOperand(0);
12036 AM.BaseType = X86AddressMode::RegBase;
12037 AM.Base.Reg = Op.getReg();
12039 AM.BaseType = X86AddressMode::FrameIndexBase;
12040 AM.Base.FrameIndex = Op.getIndex();
12042 Op = MI->getOperand(1);
12044 AM.Scale = Op.getImm();
12045 Op = MI->getOperand(2);
12047 AM.IndexReg = Op.getImm();
12048 Op = MI->getOperand(3);
12049 if (Op.isGlobal()) {
12050 AM.GV = Op.getGlobal();
12052 AM.Disp = Op.getImm();
12054 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
12055 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
12057 // Reload the original control word now.
12058 addFrameReference(BuildMI(*BB, MI, DL,
12059 TII->get(X86::FLDCW16m)), CWFrameIdx);
12061 MI->eraseFromParent(); // The pseudo instruction is gone now.
12064 // String/text processing lowering.
12065 case X86::PCMPISTRM128REG:
12066 case X86::VPCMPISTRM128REG:
12067 return EmitPCMP(MI, BB, 3, false /* in-mem */);
12068 case X86::PCMPISTRM128MEM:
12069 case X86::VPCMPISTRM128MEM:
12070 return EmitPCMP(MI, BB, 3, true /* in-mem */);
12071 case X86::PCMPESTRM128REG:
12072 case X86::VPCMPESTRM128REG:
12073 return EmitPCMP(MI, BB, 5, false /* in mem */);
12074 case X86::PCMPESTRM128MEM:
12075 case X86::VPCMPESTRM128MEM:
12076 return EmitPCMP(MI, BB, 5, true /* in mem */);
12078 // Thread synchronization.
12080 return EmitMonitor(MI, BB);
12082 return EmitMwait(MI, BB);
12084 // Atomic Lowering.
12085 case X86::ATOMAND32:
12086 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12087 X86::AND32ri, X86::MOV32rm,
12089 X86::NOT32r, X86::EAX,
12090 X86::GR32RegisterClass);
12091 case X86::ATOMOR32:
12092 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
12093 X86::OR32ri, X86::MOV32rm,
12095 X86::NOT32r, X86::EAX,
12096 X86::GR32RegisterClass);
12097 case X86::ATOMXOR32:
12098 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
12099 X86::XOR32ri, X86::MOV32rm,
12101 X86::NOT32r, X86::EAX,
12102 X86::GR32RegisterClass);
12103 case X86::ATOMNAND32:
12104 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
12105 X86::AND32ri, X86::MOV32rm,
12107 X86::NOT32r, X86::EAX,
12108 X86::GR32RegisterClass, true);
12109 case X86::ATOMMIN32:
12110 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
12111 case X86::ATOMMAX32:
12112 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
12113 case X86::ATOMUMIN32:
12114 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
12115 case X86::ATOMUMAX32:
12116 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
12118 case X86::ATOMAND16:
12119 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12120 X86::AND16ri, X86::MOV16rm,
12122 X86::NOT16r, X86::AX,
12123 X86::GR16RegisterClass);
12124 case X86::ATOMOR16:
12125 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
12126 X86::OR16ri, X86::MOV16rm,
12128 X86::NOT16r, X86::AX,
12129 X86::GR16RegisterClass);
12130 case X86::ATOMXOR16:
12131 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
12132 X86::XOR16ri, X86::MOV16rm,
12134 X86::NOT16r, X86::AX,
12135 X86::GR16RegisterClass);
12136 case X86::ATOMNAND16:
12137 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
12138 X86::AND16ri, X86::MOV16rm,
12140 X86::NOT16r, X86::AX,
12141 X86::GR16RegisterClass, true);
12142 case X86::ATOMMIN16:
12143 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
12144 case X86::ATOMMAX16:
12145 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
12146 case X86::ATOMUMIN16:
12147 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
12148 case X86::ATOMUMAX16:
12149 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
12151 case X86::ATOMAND8:
12152 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12153 X86::AND8ri, X86::MOV8rm,
12155 X86::NOT8r, X86::AL,
12156 X86::GR8RegisterClass);
12158 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
12159 X86::OR8ri, X86::MOV8rm,
12161 X86::NOT8r, X86::AL,
12162 X86::GR8RegisterClass);
12163 case X86::ATOMXOR8:
12164 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
12165 X86::XOR8ri, X86::MOV8rm,
12167 X86::NOT8r, X86::AL,
12168 X86::GR8RegisterClass);
12169 case X86::ATOMNAND8:
12170 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
12171 X86::AND8ri, X86::MOV8rm,
12173 X86::NOT8r, X86::AL,
12174 X86::GR8RegisterClass, true);
12175 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
12176 // This group is for 64-bit host.
12177 case X86::ATOMAND64:
12178 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12179 X86::AND64ri32, X86::MOV64rm,
12181 X86::NOT64r, X86::RAX,
12182 X86::GR64RegisterClass);
12183 case X86::ATOMOR64:
12184 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
12185 X86::OR64ri32, X86::MOV64rm,
12187 X86::NOT64r, X86::RAX,
12188 X86::GR64RegisterClass);
12189 case X86::ATOMXOR64:
12190 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
12191 X86::XOR64ri32, X86::MOV64rm,
12193 X86::NOT64r, X86::RAX,
12194 X86::GR64RegisterClass);
12195 case X86::ATOMNAND64:
12196 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
12197 X86::AND64ri32, X86::MOV64rm,
12199 X86::NOT64r, X86::RAX,
12200 X86::GR64RegisterClass, true);
12201 case X86::ATOMMIN64:
12202 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
12203 case X86::ATOMMAX64:
12204 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
12205 case X86::ATOMUMIN64:
12206 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
12207 case X86::ATOMUMAX64:
12208 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
12210 // This group does 64-bit operations on a 32-bit host.
12211 case X86::ATOMAND6432:
12212 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12213 X86::AND32rr, X86::AND32rr,
12214 X86::AND32ri, X86::AND32ri,
12216 case X86::ATOMOR6432:
12217 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12218 X86::OR32rr, X86::OR32rr,
12219 X86::OR32ri, X86::OR32ri,
12221 case X86::ATOMXOR6432:
12222 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12223 X86::XOR32rr, X86::XOR32rr,
12224 X86::XOR32ri, X86::XOR32ri,
12226 case X86::ATOMNAND6432:
12227 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12228 X86::AND32rr, X86::AND32rr,
12229 X86::AND32ri, X86::AND32ri,
12231 case X86::ATOMADD6432:
12232 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12233 X86::ADD32rr, X86::ADC32rr,
12234 X86::ADD32ri, X86::ADC32ri,
12236 case X86::ATOMSUB6432:
12237 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12238 X86::SUB32rr, X86::SBB32rr,
12239 X86::SUB32ri, X86::SBB32ri,
12241 case X86::ATOMSWAP6432:
12242 return EmitAtomicBit6432WithCustomInserter(MI, BB,
12243 X86::MOV32rr, X86::MOV32rr,
12244 X86::MOV32ri, X86::MOV32ri,
12246 case X86::VASTART_SAVE_XMM_REGS:
12247 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
12249 case X86::VAARG_64:
12250 return EmitVAARG64WithCustomInserter(MI, BB);
12254 //===----------------------------------------------------------------------===//
12255 // X86 Optimization Hooks
12256 //===----------------------------------------------------------------------===//
12258 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
12262 const SelectionDAG &DAG,
12263 unsigned Depth) const {
12264 unsigned Opc = Op.getOpcode();
12265 assert((Opc >= ISD::BUILTIN_OP_END ||
12266 Opc == ISD::INTRINSIC_WO_CHAIN ||
12267 Opc == ISD::INTRINSIC_W_CHAIN ||
12268 Opc == ISD::INTRINSIC_VOID) &&
12269 "Should use MaskedValueIsZero if you don't know whether Op"
12270 " is a target node!");
12272 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
12286 // These nodes' second result is a boolean.
12287 if (Op.getResNo() == 0)
12290 case X86ISD::SETCC:
12291 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
12292 Mask.getBitWidth() - 1);
12297 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
12298 unsigned Depth) const {
12299 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
12300 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
12301 return Op.getValueType().getScalarType().getSizeInBits();
12307 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
12308 /// node is a GlobalAddress + offset.
12309 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
12310 const GlobalValue* &GA,
12311 int64_t &Offset) const {
12312 if (N->getOpcode() == X86ISD::Wrapper) {
12313 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
12314 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
12315 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
12319 return TargetLowering::isGAPlusOffset(N, GA, Offset);
12322 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
12323 /// same as extracting the high 128-bit part of 256-bit vector and then
12324 /// inserting the result into the low part of a new 256-bit vector
12325 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
12326 EVT VT = SVOp->getValueType(0);
12327 int NumElems = VT.getVectorNumElements();
12329 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12330 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j)
12331 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12332 SVOp->getMaskElt(j) >= 0)
12338 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
12339 /// same as extracting the low 128-bit part of 256-bit vector and then
12340 /// inserting the result into the high part of a new 256-bit vector
12341 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
12342 EVT VT = SVOp->getValueType(0);
12343 int NumElems = VT.getVectorNumElements();
12345 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12346 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j)
12347 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
12348 SVOp->getMaskElt(j) >= 0)
12354 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
12355 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
12356 TargetLowering::DAGCombinerInfo &DCI) {
12357 DebugLoc dl = N->getDebugLoc();
12358 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
12359 SDValue V1 = SVOp->getOperand(0);
12360 SDValue V2 = SVOp->getOperand(1);
12361 EVT VT = SVOp->getValueType(0);
12362 int NumElems = VT.getVectorNumElements();
12364 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
12365 V2.getOpcode() == ISD::CONCAT_VECTORS) {
12369 // V UNDEF BUILD_VECTOR UNDEF
12371 // CONCAT_VECTOR CONCAT_VECTOR
12374 // RESULT: V + zero extended
12376 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
12377 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
12378 V1.getOperand(1).getOpcode() != ISD::UNDEF)
12381 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
12384 // To match the shuffle mask, the first half of the mask should
12385 // be exactly the first vector, and all the rest a splat with the
12386 // first element of the second one.
12387 for (int i = 0; i < NumElems/2; ++i)
12388 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
12389 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
12392 // Emit a zeroed vector and insert the desired subvector on its
12394 SDValue Zeros = getZeroVector(VT, true /* HasSSE2 */, DAG, dl);
12395 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0),
12396 DAG.getConstant(0, MVT::i32), DAG, dl);
12397 return DCI.CombineTo(N, InsV);
12400 //===--------------------------------------------------------------------===//
12401 // Combine some shuffles into subvector extracts and inserts:
12404 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
12405 if (isShuffleHigh128VectorInsertLow(SVOp)) {
12406 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32),
12408 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12409 V, DAG.getConstant(0, MVT::i32), DAG, dl);
12410 return DCI.CombineTo(N, InsV);
12413 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
12414 if (isShuffleLow128VectorInsertHigh(SVOp)) {
12415 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl);
12416 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT),
12417 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
12418 return DCI.CombineTo(N, InsV);
12424 /// PerformShuffleCombine - Performs several different shuffle combines.
12425 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
12426 TargetLowering::DAGCombinerInfo &DCI,
12427 const X86Subtarget *Subtarget) {
12428 DebugLoc dl = N->getDebugLoc();
12429 EVT VT = N->getValueType(0);
12431 // Don't create instructions with illegal types after legalize types has run.
12432 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12433 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
12436 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
12437 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 &&
12438 N->getOpcode() == ISD::VECTOR_SHUFFLE)
12439 return PerformShuffleCombine256(N, DAG, DCI);
12441 // Only handle 128 wide vector from here on.
12442 if (VT.getSizeInBits() != 128)
12445 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
12446 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
12447 // consecutive, non-overlapping, and in the right order.
12448 SmallVector<SDValue, 16> Elts;
12449 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
12450 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
12452 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
12455 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
12456 /// generation and convert it from being a bunch of shuffles and extracts
12457 /// to a simple store and scalar loads to extract the elements.
12458 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
12459 const TargetLowering &TLI) {
12460 SDValue InputVector = N->getOperand(0);
12462 // Only operate on vectors of 4 elements, where the alternative shuffling
12463 // gets to be more expensive.
12464 if (InputVector.getValueType() != MVT::v4i32)
12467 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
12468 // single use which is a sign-extend or zero-extend, and all elements are
12470 SmallVector<SDNode *, 4> Uses;
12471 unsigned ExtractedElements = 0;
12472 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
12473 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
12474 if (UI.getUse().getResNo() != InputVector.getResNo())
12477 SDNode *Extract = *UI;
12478 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12481 if (Extract->getValueType(0) != MVT::i32)
12483 if (!Extract->hasOneUse())
12485 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
12486 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
12488 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
12491 // Record which element was extracted.
12492 ExtractedElements |=
12493 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
12495 Uses.push_back(Extract);
12498 // If not all the elements were used, this may not be worthwhile.
12499 if (ExtractedElements != 15)
12502 // Ok, we've now decided to do the transformation.
12503 DebugLoc dl = InputVector.getDebugLoc();
12505 // Store the value to a temporary stack slot.
12506 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
12507 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
12508 MachinePointerInfo(), false, false, 0);
12510 // Replace each use (extract) with a load of the appropriate element.
12511 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
12512 UE = Uses.end(); UI != UE; ++UI) {
12513 SDNode *Extract = *UI;
12515 // cOMpute the element's address.
12516 SDValue Idx = Extract->getOperand(1);
12518 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
12519 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
12520 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
12522 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
12523 StackPtr, OffsetVal);
12525 // Load the scalar.
12526 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
12527 ScalarAddr, MachinePointerInfo(),
12530 // Replace the exact with the load.
12531 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
12534 // The replacement was made in place; don't return anything.
12538 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
12539 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
12540 const X86Subtarget *Subtarget) {
12541 DebugLoc DL = N->getDebugLoc();
12542 SDValue Cond = N->getOperand(0);
12543 // Get the LHS/RHS of the select.
12544 SDValue LHS = N->getOperand(1);
12545 SDValue RHS = N->getOperand(2);
12547 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
12548 // instructions match the semantics of the common C idiom x<y?x:y but not
12549 // x<=y?x:y, because of how they handle negative zero (which can be
12550 // ignored in unsafe-math mode).
12551 if (Subtarget->hasSSE2() &&
12552 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
12553 Cond.getOpcode() == ISD::SETCC) {
12554 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
12556 unsigned Opcode = 0;
12557 // Check for x CC y ? x : y.
12558 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
12559 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
12563 // Converting this to a min would handle NaNs incorrectly, and swapping
12564 // the operands would cause it to handle comparisons between positive
12565 // and negative zero incorrectly.
12566 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12567 if (!UnsafeFPMath &&
12568 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12570 std::swap(LHS, RHS);
12572 Opcode = X86ISD::FMIN;
12575 // Converting this to a min would handle comparisons between positive
12576 // and negative zero incorrectly.
12577 if (!UnsafeFPMath &&
12578 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12580 Opcode = X86ISD::FMIN;
12583 // Converting this to a min would handle both negative zeros and NaNs
12584 // incorrectly, but we can swap the operands to fix both.
12585 std::swap(LHS, RHS);
12589 Opcode = X86ISD::FMIN;
12593 // Converting this to a max would handle comparisons between positive
12594 // and negative zero incorrectly.
12595 if (!UnsafeFPMath &&
12596 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
12598 Opcode = X86ISD::FMAX;
12601 // Converting this to a max would handle NaNs incorrectly, and swapping
12602 // the operands would cause it to handle comparisons between positive
12603 // and negative zero incorrectly.
12604 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
12605 if (!UnsafeFPMath &&
12606 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
12608 std::swap(LHS, RHS);
12610 Opcode = X86ISD::FMAX;
12613 // Converting this to a max would handle both negative zeros and NaNs
12614 // incorrectly, but we can swap the operands to fix both.
12615 std::swap(LHS, RHS);
12619 Opcode = X86ISD::FMAX;
12622 // Check for x CC y ? y : x -- a min/max with reversed arms.
12623 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
12624 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
12628 // Converting this to a min would handle comparisons between positive
12629 // and negative zero incorrectly, and swapping the operands would
12630 // cause it to handle NaNs incorrectly.
12631 if (!UnsafeFPMath &&
12632 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
12633 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12635 std::swap(LHS, RHS);
12637 Opcode = X86ISD::FMIN;
12640 // Converting this to a min would handle NaNs incorrectly.
12641 if (!UnsafeFPMath &&
12642 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
12644 Opcode = X86ISD::FMIN;
12647 // Converting this to a min would handle both negative zeros and NaNs
12648 // incorrectly, but we can swap the operands to fix both.
12649 std::swap(LHS, RHS);
12653 Opcode = X86ISD::FMIN;
12657 // Converting this to a max would handle NaNs incorrectly.
12658 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12660 Opcode = X86ISD::FMAX;
12663 // Converting this to a max would handle comparisons between positive
12664 // and negative zero incorrectly, and swapping the operands would
12665 // cause it to handle NaNs incorrectly.
12666 if (!UnsafeFPMath &&
12667 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
12668 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
12670 std::swap(LHS, RHS);
12672 Opcode = X86ISD::FMAX;
12675 // Converting this to a max would handle both negative zeros and NaNs
12676 // incorrectly, but we can swap the operands to fix both.
12677 std::swap(LHS, RHS);
12681 Opcode = X86ISD::FMAX;
12687 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
12690 // If this is a select between two integer constants, try to do some
12692 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
12693 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
12694 // Don't do this for crazy integer types.
12695 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
12696 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
12697 // so that TrueC (the true value) is larger than FalseC.
12698 bool NeedsCondInvert = false;
12700 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
12701 // Efficiently invertible.
12702 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
12703 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
12704 isa<ConstantSDNode>(Cond.getOperand(1))))) {
12705 NeedsCondInvert = true;
12706 std::swap(TrueC, FalseC);
12709 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
12710 if (FalseC->getAPIntValue() == 0 &&
12711 TrueC->getAPIntValue().isPowerOf2()) {
12712 if (NeedsCondInvert) // Invert the condition if needed.
12713 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12714 DAG.getConstant(1, Cond.getValueType()));
12716 // Zero extend the condition if needed.
12717 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
12719 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12720 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
12721 DAG.getConstant(ShAmt, MVT::i8));
12724 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
12725 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12726 if (NeedsCondInvert) // Invert the condition if needed.
12727 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12728 DAG.getConstant(1, Cond.getValueType()));
12730 // Zero extend the condition if needed.
12731 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12732 FalseC->getValueType(0), Cond);
12733 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12734 SDValue(FalseC, 0));
12737 // Optimize cases that will turn into an LEA instruction. This requires
12738 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12739 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12740 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12741 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12743 bool isFastMultiplier = false;
12745 switch ((unsigned char)Diff) {
12747 case 1: // result = add base, cond
12748 case 2: // result = lea base( , cond*2)
12749 case 3: // result = lea base(cond, cond*2)
12750 case 4: // result = lea base( , cond*4)
12751 case 5: // result = lea base(cond, cond*4)
12752 case 8: // result = lea base( , cond*8)
12753 case 9: // result = lea base(cond, cond*8)
12754 isFastMultiplier = true;
12759 if (isFastMultiplier) {
12760 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12761 if (NeedsCondInvert) // Invert the condition if needed.
12762 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
12763 DAG.getConstant(1, Cond.getValueType()));
12765 // Zero extend the condition if needed.
12766 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12768 // Scale the condition by the difference.
12770 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12771 DAG.getConstant(Diff, Cond.getValueType()));
12773 // Add the base if non-zero.
12774 if (FalseC->getAPIntValue() != 0)
12775 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12776 SDValue(FalseC, 0));
12786 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
12787 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
12788 TargetLowering::DAGCombinerInfo &DCI) {
12789 DebugLoc DL = N->getDebugLoc();
12791 // If the flag operand isn't dead, don't touch this CMOV.
12792 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
12795 SDValue FalseOp = N->getOperand(0);
12796 SDValue TrueOp = N->getOperand(1);
12797 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
12798 SDValue Cond = N->getOperand(3);
12799 if (CC == X86::COND_E || CC == X86::COND_NE) {
12800 switch (Cond.getOpcode()) {
12804 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
12805 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
12806 return (CC == X86::COND_E) ? FalseOp : TrueOp;
12810 // If this is a select between two integer constants, try to do some
12811 // optimizations. Note that the operands are ordered the opposite of SELECT
12813 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
12814 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
12815 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
12816 // larger than FalseC (the false value).
12817 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
12818 CC = X86::GetOppositeBranchCondition(CC);
12819 std::swap(TrueC, FalseC);
12822 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
12823 // This is efficient for any integer data type (including i8/i16) and
12825 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
12826 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12827 DAG.getConstant(CC, MVT::i8), Cond);
12829 // Zero extend the condition if needed.
12830 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
12832 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
12833 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
12834 DAG.getConstant(ShAmt, MVT::i8));
12835 if (N->getNumValues() == 2) // Dead flag value?
12836 return DCI.CombineTo(N, Cond, SDValue());
12840 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
12841 // for any integer data type, including i8/i16.
12842 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
12843 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12844 DAG.getConstant(CC, MVT::i8), Cond);
12846 // Zero extend the condition if needed.
12847 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
12848 FalseC->getValueType(0), Cond);
12849 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12850 SDValue(FalseC, 0));
12852 if (N->getNumValues() == 2) // Dead flag value?
12853 return DCI.CombineTo(N, Cond, SDValue());
12857 // Optimize cases that will turn into an LEA instruction. This requires
12858 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
12859 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
12860 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
12861 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
12863 bool isFastMultiplier = false;
12865 switch ((unsigned char)Diff) {
12867 case 1: // result = add base, cond
12868 case 2: // result = lea base( , cond*2)
12869 case 3: // result = lea base(cond, cond*2)
12870 case 4: // result = lea base( , cond*4)
12871 case 5: // result = lea base(cond, cond*4)
12872 case 8: // result = lea base( , cond*8)
12873 case 9: // result = lea base(cond, cond*8)
12874 isFastMultiplier = true;
12879 if (isFastMultiplier) {
12880 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
12881 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12882 DAG.getConstant(CC, MVT::i8), Cond);
12883 // Zero extend the condition if needed.
12884 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
12886 // Scale the condition by the difference.
12888 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
12889 DAG.getConstant(Diff, Cond.getValueType()));
12891 // Add the base if non-zero.
12892 if (FalseC->getAPIntValue() != 0)
12893 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
12894 SDValue(FalseC, 0));
12895 if (N->getNumValues() == 2) // Dead flag value?
12896 return DCI.CombineTo(N, Cond, SDValue());
12906 /// PerformMulCombine - Optimize a single multiply with constant into two
12907 /// in order to implement it with two cheaper instructions, e.g.
12908 /// LEA + SHL, LEA + LEA.
12909 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
12910 TargetLowering::DAGCombinerInfo &DCI) {
12911 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
12914 EVT VT = N->getValueType(0);
12915 if (VT != MVT::i64)
12918 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
12921 uint64_t MulAmt = C->getZExtValue();
12922 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
12925 uint64_t MulAmt1 = 0;
12926 uint64_t MulAmt2 = 0;
12927 if ((MulAmt % 9) == 0) {
12929 MulAmt2 = MulAmt / 9;
12930 } else if ((MulAmt % 5) == 0) {
12932 MulAmt2 = MulAmt / 5;
12933 } else if ((MulAmt % 3) == 0) {
12935 MulAmt2 = MulAmt / 3;
12938 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
12939 DebugLoc DL = N->getDebugLoc();
12941 if (isPowerOf2_64(MulAmt2) &&
12942 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
12943 // If second multiplifer is pow2, issue it first. We want the multiply by
12944 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
12946 std::swap(MulAmt1, MulAmt2);
12949 if (isPowerOf2_64(MulAmt1))
12950 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
12951 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
12953 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
12954 DAG.getConstant(MulAmt1, VT));
12956 if (isPowerOf2_64(MulAmt2))
12957 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
12958 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
12960 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
12961 DAG.getConstant(MulAmt2, VT));
12963 // Do not add new nodes to DAG combiner worklist.
12964 DCI.CombineTo(N, NewMul, false);
12969 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
12970 SDValue N0 = N->getOperand(0);
12971 SDValue N1 = N->getOperand(1);
12972 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
12973 EVT VT = N0.getValueType();
12975 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
12976 // since the result of setcc_c is all zero's or all ones.
12977 if (N1C && N0.getOpcode() == ISD::AND &&
12978 N0.getOperand(1).getOpcode() == ISD::Constant) {
12979 SDValue N00 = N0.getOperand(0);
12980 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
12981 ((N00.getOpcode() == ISD::ANY_EXTEND ||
12982 N00.getOpcode() == ISD::ZERO_EXTEND) &&
12983 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
12984 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
12985 APInt ShAmt = N1C->getAPIntValue();
12986 Mask = Mask.shl(ShAmt);
12988 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
12989 N00, DAG.getConstant(Mask, VT));
12996 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
12998 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
12999 const X86Subtarget *Subtarget) {
13000 EVT VT = N->getValueType(0);
13001 if (!VT.isVector() && VT.isInteger() &&
13002 N->getOpcode() == ISD::SHL)
13003 return PerformSHLCombine(N, DAG);
13005 // On X86 with SSE2 support, we can transform this to a vector shift if
13006 // all elements are shifted by the same amount. We can't do this in legalize
13007 // because the a constant vector is typically transformed to a constant pool
13008 // so we have no knowledge of the shift amount.
13009 if (!(Subtarget->hasSSE2() || Subtarget->hasAVX()))
13012 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
13015 SDValue ShAmtOp = N->getOperand(1);
13016 EVT EltVT = VT.getVectorElementType();
13017 DebugLoc DL = N->getDebugLoc();
13018 SDValue BaseShAmt = SDValue();
13019 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
13020 unsigned NumElts = VT.getVectorNumElements();
13022 for (; i != NumElts; ++i) {
13023 SDValue Arg = ShAmtOp.getOperand(i);
13024 if (Arg.getOpcode() == ISD::UNDEF) continue;
13028 for (; i != NumElts; ++i) {
13029 SDValue Arg = ShAmtOp.getOperand(i);
13030 if (Arg.getOpcode() == ISD::UNDEF) continue;
13031 if (Arg != BaseShAmt) {
13035 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
13036 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
13037 SDValue InVec = ShAmtOp.getOperand(0);
13038 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
13039 unsigned NumElts = InVec.getValueType().getVectorNumElements();
13041 for (; i != NumElts; ++i) {
13042 SDValue Arg = InVec.getOperand(i);
13043 if (Arg.getOpcode() == ISD::UNDEF) continue;
13047 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
13048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
13049 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
13050 if (C->getZExtValue() == SplatIdx)
13051 BaseShAmt = InVec.getOperand(1);
13054 if (BaseShAmt.getNode() == 0)
13055 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
13056 DAG.getIntPtrConstant(0));
13060 // The shift amount is an i32.
13061 if (EltVT.bitsGT(MVT::i32))
13062 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
13063 else if (EltVT.bitsLT(MVT::i32))
13064 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
13066 // The shift amount is identical so we can do a vector shift.
13067 SDValue ValOp = N->getOperand(0);
13068 switch (N->getOpcode()) {
13070 llvm_unreachable("Unknown shift opcode!");
13073 if (VT == MVT::v2i64)
13074 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13075 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
13077 if (VT == MVT::v4i32)
13078 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13079 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
13081 if (VT == MVT::v8i16)
13082 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13083 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
13087 if (VT == MVT::v4i32)
13088 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13089 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
13091 if (VT == MVT::v8i16)
13092 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13093 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
13097 if (VT == MVT::v2i64)
13098 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13099 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
13101 if (VT == MVT::v4i32)
13102 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13103 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
13105 if (VT == MVT::v8i16)
13106 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
13107 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
13115 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
13116 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
13117 // and friends. Likewise for OR -> CMPNEQSS.
13118 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
13119 TargetLowering::DAGCombinerInfo &DCI,
13120 const X86Subtarget *Subtarget) {
13123 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
13124 // we're requiring SSE2 for both.
13125 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
13126 SDValue N0 = N->getOperand(0);
13127 SDValue N1 = N->getOperand(1);
13128 SDValue CMP0 = N0->getOperand(1);
13129 SDValue CMP1 = N1->getOperand(1);
13130 DebugLoc DL = N->getDebugLoc();
13132 // The SETCCs should both refer to the same CMP.
13133 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
13136 SDValue CMP00 = CMP0->getOperand(0);
13137 SDValue CMP01 = CMP0->getOperand(1);
13138 EVT VT = CMP00.getValueType();
13140 if (VT == MVT::f32 || VT == MVT::f64) {
13141 bool ExpectingFlags = false;
13142 // Check for any users that want flags:
13143 for (SDNode::use_iterator UI = N->use_begin(),
13145 !ExpectingFlags && UI != UE; ++UI)
13146 switch (UI->getOpcode()) {
13151 ExpectingFlags = true;
13153 case ISD::CopyToReg:
13154 case ISD::SIGN_EXTEND:
13155 case ISD::ZERO_EXTEND:
13156 case ISD::ANY_EXTEND:
13160 if (!ExpectingFlags) {
13161 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
13162 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
13164 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
13165 X86::CondCode tmp = cc0;
13170 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
13171 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
13172 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
13173 X86ISD::NodeType NTOperator = is64BitFP ?
13174 X86ISD::FSETCCsd : X86ISD::FSETCCss;
13175 // FIXME: need symbolic constants for these magic numbers.
13176 // See X86ATTInstPrinter.cpp:printSSECC().
13177 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
13178 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
13179 DAG.getConstant(x86cc, MVT::i8));
13180 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
13182 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
13183 DAG.getConstant(1, MVT::i32));
13184 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
13185 return OneBitOfTruth;
13193 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
13194 /// so it can be folded inside ANDNP.
13195 static bool CanFoldXORWithAllOnes(const SDNode *N) {
13196 EVT VT = N->getValueType(0);
13198 // Match direct AllOnes for 128 and 256-bit vectors
13199 if (ISD::isBuildVectorAllOnes(N))
13202 // Look through a bit convert.
13203 if (N->getOpcode() == ISD::BITCAST)
13204 N = N->getOperand(0).getNode();
13206 // Sometimes the operand may come from a insert_subvector building a 256-bit
13208 if (VT.getSizeInBits() == 256 &&
13209 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
13210 SDValue V1 = N->getOperand(0);
13211 SDValue V2 = N->getOperand(1);
13213 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
13214 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
13215 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
13216 ISD::isBuildVectorAllOnes(V2.getNode()))
13223 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
13224 TargetLowering::DAGCombinerInfo &DCI,
13225 const X86Subtarget *Subtarget) {
13226 if (DCI.isBeforeLegalizeOps())
13229 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13233 // Want to form ANDNP nodes:
13234 // 1) In the hopes of then easily combining them with OR and AND nodes
13235 // to form PBLEND/PSIGN.
13236 // 2) To match ANDN packed intrinsics
13237 EVT VT = N->getValueType(0);
13238 if (VT != MVT::v2i64 && VT != MVT::v4i64)
13241 SDValue N0 = N->getOperand(0);
13242 SDValue N1 = N->getOperand(1);
13243 DebugLoc DL = N->getDebugLoc();
13245 // Check LHS for vnot
13246 if (N0.getOpcode() == ISD::XOR &&
13247 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
13248 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
13249 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
13251 // Check RHS for vnot
13252 if (N1.getOpcode() == ISD::XOR &&
13253 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
13254 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
13255 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
13260 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
13261 TargetLowering::DAGCombinerInfo &DCI,
13262 const X86Subtarget *Subtarget) {
13263 if (DCI.isBeforeLegalizeOps())
13266 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
13270 EVT VT = N->getValueType(0);
13271 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64)
13274 SDValue N0 = N->getOperand(0);
13275 SDValue N1 = N->getOperand(1);
13277 // look for psign/blend
13278 if (Subtarget->hasSSSE3()) {
13279 if (VT == MVT::v2i64) {
13280 // Canonicalize pandn to RHS
13281 if (N0.getOpcode() == X86ISD::ANDNP)
13283 // or (and (m, x), (pandn m, y))
13284 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
13285 SDValue Mask = N1.getOperand(0);
13286 SDValue X = N1.getOperand(1);
13288 if (N0.getOperand(0) == Mask)
13289 Y = N0.getOperand(1);
13290 if (N0.getOperand(1) == Mask)
13291 Y = N0.getOperand(0);
13293 // Check to see if the mask appeared in both the AND and ANDNP and
13297 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
13298 if (Mask.getOpcode() != ISD::BITCAST ||
13299 X.getOpcode() != ISD::BITCAST ||
13300 Y.getOpcode() != ISD::BITCAST)
13303 // Look through mask bitcast.
13304 Mask = Mask.getOperand(0);
13305 EVT MaskVT = Mask.getValueType();
13307 // Validate that the Mask operand is a vector sra node. The sra node
13308 // will be an intrinsic.
13309 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN)
13312 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
13313 // there is no psrai.b
13314 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) {
13315 case Intrinsic::x86_sse2_psrai_w:
13316 case Intrinsic::x86_sse2_psrai_d:
13318 default: return SDValue();
13321 // Check that the SRA is all signbits.
13322 SDValue SraC = Mask.getOperand(2);
13323 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
13324 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
13325 if ((SraAmt + 1) != EltBits)
13328 DebugLoc DL = N->getDebugLoc();
13330 // Now we know we at least have a plendvb with the mask val. See if
13331 // we can form a psignb/w/d.
13332 // psign = x.type == y.type == mask.type && y = sub(0, x);
13333 X = X.getOperand(0);
13334 Y = Y.getOperand(0);
13335 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
13336 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
13337 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){
13340 case 8: Opc = X86ISD::PSIGNB; break;
13341 case 16: Opc = X86ISD::PSIGNW; break;
13342 case 32: Opc = X86ISD::PSIGND; break;
13346 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1));
13347 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign);
13350 // PBLENDVB only available on SSE 4.1
13351 if (!Subtarget->hasSSE41())
13354 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
13355 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
13356 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
13357 Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y);
13358 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
13363 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
13364 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
13366 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
13368 if (!N0.hasOneUse() || !N1.hasOneUse())
13371 SDValue ShAmt0 = N0.getOperand(1);
13372 if (ShAmt0.getValueType() != MVT::i8)
13374 SDValue ShAmt1 = N1.getOperand(1);
13375 if (ShAmt1.getValueType() != MVT::i8)
13377 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
13378 ShAmt0 = ShAmt0.getOperand(0);
13379 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
13380 ShAmt1 = ShAmt1.getOperand(0);
13382 DebugLoc DL = N->getDebugLoc();
13383 unsigned Opc = X86ISD::SHLD;
13384 SDValue Op0 = N0.getOperand(0);
13385 SDValue Op1 = N1.getOperand(0);
13386 if (ShAmt0.getOpcode() == ISD::SUB) {
13387 Opc = X86ISD::SHRD;
13388 std::swap(Op0, Op1);
13389 std::swap(ShAmt0, ShAmt1);
13392 unsigned Bits = VT.getSizeInBits();
13393 if (ShAmt1.getOpcode() == ISD::SUB) {
13394 SDValue Sum = ShAmt1.getOperand(0);
13395 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
13396 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
13397 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
13398 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
13399 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
13400 return DAG.getNode(Opc, DL, VT,
13402 DAG.getNode(ISD::TRUNCATE, DL,
13405 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
13406 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
13408 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
13409 return DAG.getNode(Opc, DL, VT,
13410 N0.getOperand(0), N1.getOperand(0),
13411 DAG.getNode(ISD::TRUNCATE, DL,
13418 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
13419 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
13420 const X86Subtarget *Subtarget) {
13421 StoreSDNode *St = cast<StoreSDNode>(N);
13422 EVT VT = St->getValue().getValueType();
13423 EVT StVT = St->getMemoryVT();
13424 DebugLoc dl = St->getDebugLoc();
13425 SDValue StoredVal = St->getOperand(1);
13426 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13428 // If we are saving a concatination of two XMM registers, perform two stores.
13429 // This is better in Sandy Bridge cause one 256-bit mem op is done via two
13430 // 128-bit ones. If in the future the cost becomes only one memory access the
13431 // first version would be better.
13432 if (VT.getSizeInBits() == 256 &&
13433 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
13434 StoredVal.getNumOperands() == 2) {
13436 SDValue Value0 = StoredVal.getOperand(0);
13437 SDValue Value1 = StoredVal.getOperand(1);
13439 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
13440 SDValue Ptr0 = St->getBasePtr();
13441 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
13443 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
13444 St->getPointerInfo(), St->isVolatile(),
13445 St->isNonTemporal(), St->getAlignment());
13446 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
13447 St->getPointerInfo(), St->isVolatile(),
13448 St->isNonTemporal(), St->getAlignment());
13449 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
13452 // Optimize trunc store (of multiple scalars) to shuffle and store.
13453 // First, pack all of the elements in one place. Next, store to memory
13454 // in fewer chunks.
13455 if (St->isTruncatingStore() && VT.isVector()) {
13456 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13457 unsigned NumElems = VT.getVectorNumElements();
13458 assert(StVT != VT && "Cannot truncate to the same type");
13459 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
13460 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
13462 // From, To sizes and ElemCount must be pow of two
13463 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
13464 // We are going to use the original vector elt for storing.
13465 // accumulated smaller vector elements must be a multiple of bigger size.
13466 if (0 != (NumElems * ToSz) % FromSz) return SDValue();
13467 unsigned SizeRatio = FromSz / ToSz;
13469 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
13471 // Create a type on which we perform the shuffle
13472 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
13473 StVT.getScalarType(), NumElems*SizeRatio);
13475 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
13477 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
13478 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
13479 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio;
13481 // Can't shuffle using an illegal type
13482 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
13484 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
13485 DAG.getUNDEF(WideVec.getValueType()),
13486 ShuffleVec.data());
13487 // At this point all of the data is stored at the bottom of the
13488 // register. We now need to save it to mem.
13490 // Find the largest store unit
13491 MVT StoreType = MVT::i8;
13492 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
13493 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
13494 MVT Tp = (MVT::SimpleValueType)tp;
13495 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
13499 // Bitcast the original vector into a vector of store-size units
13500 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
13501 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
13502 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
13503 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
13504 SmallVector<SDValue, 8> Chains;
13505 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
13506 TLI.getPointerTy());
13507 SDValue Ptr = St->getBasePtr();
13509 // Perform one or more big stores into memory.
13510 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) {
13511 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
13512 StoreType, ShuffWide,
13513 DAG.getIntPtrConstant(i));
13514 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
13515 St->getPointerInfo(), St->isVolatile(),
13516 St->isNonTemporal(), St->getAlignment());
13517 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
13518 Chains.push_back(Ch);
13521 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
13526 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
13527 // the FP state in cases where an emms may be missing.
13528 // A preferable solution to the general problem is to figure out the right
13529 // places to insert EMMS. This qualifies as a quick hack.
13531 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
13532 if (VT.getSizeInBits() != 64)
13535 const Function *F = DAG.getMachineFunction().getFunction();
13536 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
13537 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
13538 && Subtarget->hasSSE2();
13539 if ((VT.isVector() ||
13540 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
13541 isa<LoadSDNode>(St->getValue()) &&
13542 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
13543 St->getChain().hasOneUse() && !St->isVolatile()) {
13544 SDNode* LdVal = St->getValue().getNode();
13545 LoadSDNode *Ld = 0;
13546 int TokenFactorIndex = -1;
13547 SmallVector<SDValue, 8> Ops;
13548 SDNode* ChainVal = St->getChain().getNode();
13549 // Must be a store of a load. We currently handle two cases: the load
13550 // is a direct child, and it's under an intervening TokenFactor. It is
13551 // possible to dig deeper under nested TokenFactors.
13552 if (ChainVal == LdVal)
13553 Ld = cast<LoadSDNode>(St->getChain());
13554 else if (St->getValue().hasOneUse() &&
13555 ChainVal->getOpcode() == ISD::TokenFactor) {
13556 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
13557 if (ChainVal->getOperand(i).getNode() == LdVal) {
13558 TokenFactorIndex = i;
13559 Ld = cast<LoadSDNode>(St->getValue());
13561 Ops.push_back(ChainVal->getOperand(i));
13565 if (!Ld || !ISD::isNormalLoad(Ld))
13568 // If this is not the MMX case, i.e. we are just turning i64 load/store
13569 // into f64 load/store, avoid the transformation if there are multiple
13570 // uses of the loaded value.
13571 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
13574 DebugLoc LdDL = Ld->getDebugLoc();
13575 DebugLoc StDL = N->getDebugLoc();
13576 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
13577 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
13579 if (Subtarget->is64Bit() || F64IsLegal) {
13580 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
13581 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
13582 Ld->getPointerInfo(), Ld->isVolatile(),
13583 Ld->isNonTemporal(), Ld->getAlignment());
13584 SDValue NewChain = NewLd.getValue(1);
13585 if (TokenFactorIndex != -1) {
13586 Ops.push_back(NewChain);
13587 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13590 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
13591 St->getPointerInfo(),
13592 St->isVolatile(), St->isNonTemporal(),
13593 St->getAlignment());
13596 // Otherwise, lower to two pairs of 32-bit loads / stores.
13597 SDValue LoAddr = Ld->getBasePtr();
13598 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
13599 DAG.getConstant(4, MVT::i32));
13601 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
13602 Ld->getPointerInfo(),
13603 Ld->isVolatile(), Ld->isNonTemporal(),
13604 Ld->getAlignment());
13605 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
13606 Ld->getPointerInfo().getWithOffset(4),
13607 Ld->isVolatile(), Ld->isNonTemporal(),
13608 MinAlign(Ld->getAlignment(), 4));
13610 SDValue NewChain = LoLd.getValue(1);
13611 if (TokenFactorIndex != -1) {
13612 Ops.push_back(LoLd);
13613 Ops.push_back(HiLd);
13614 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
13618 LoAddr = St->getBasePtr();
13619 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
13620 DAG.getConstant(4, MVT::i32));
13622 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
13623 St->getPointerInfo(),
13624 St->isVolatile(), St->isNonTemporal(),
13625 St->getAlignment());
13626 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
13627 St->getPointerInfo().getWithOffset(4),
13629 St->isNonTemporal(),
13630 MinAlign(St->getAlignment(), 4));
13631 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
13636 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
13637 /// X86ISD::FXOR nodes.
13638 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
13639 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
13640 // F[X]OR(0.0, x) -> x
13641 // F[X]OR(x, 0.0) -> x
13642 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13643 if (C->getValueAPF().isPosZero())
13644 return N->getOperand(1);
13645 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13646 if (C->getValueAPF().isPosZero())
13647 return N->getOperand(0);
13651 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
13652 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
13653 // FAND(0.0, x) -> 0.0
13654 // FAND(x, 0.0) -> 0.0
13655 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
13656 if (C->getValueAPF().isPosZero())
13657 return N->getOperand(0);
13658 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
13659 if (C->getValueAPF().isPosZero())
13660 return N->getOperand(1);
13664 static SDValue PerformBTCombine(SDNode *N,
13666 TargetLowering::DAGCombinerInfo &DCI) {
13667 // BT ignores high bits in the bit index operand.
13668 SDValue Op1 = N->getOperand(1);
13669 if (Op1.hasOneUse()) {
13670 unsigned BitWidth = Op1.getValueSizeInBits();
13671 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
13672 APInt KnownZero, KnownOne;
13673 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
13674 !DCI.isBeforeLegalizeOps());
13675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13676 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
13677 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
13678 DCI.CommitTargetLoweringOpt(TLO);
13683 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
13684 SDValue Op = N->getOperand(0);
13685 if (Op.getOpcode() == ISD::BITCAST)
13686 Op = Op.getOperand(0);
13687 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
13688 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
13689 VT.getVectorElementType().getSizeInBits() ==
13690 OpVT.getVectorElementType().getSizeInBits()) {
13691 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
13696 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
13697 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
13698 // (and (i32 x86isd::setcc_carry), 1)
13699 // This eliminates the zext. This transformation is necessary because
13700 // ISD::SETCC is always legalized to i8.
13701 DebugLoc dl = N->getDebugLoc();
13702 SDValue N0 = N->getOperand(0);
13703 EVT VT = N->getValueType(0);
13704 if (N0.getOpcode() == ISD::AND &&
13706 N0.getOperand(0).hasOneUse()) {
13707 SDValue N00 = N0.getOperand(0);
13708 if (N00.getOpcode() != X86ISD::SETCC_CARRY)
13710 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
13711 if (!C || C->getZExtValue() != 1)
13713 return DAG.getNode(ISD::AND, dl, VT,
13714 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
13715 N00.getOperand(0), N00.getOperand(1)),
13716 DAG.getConstant(1, VT));
13722 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
13723 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
13724 unsigned X86CC = N->getConstantOperandVal(0);
13725 SDValue EFLAG = N->getOperand(1);
13726 DebugLoc DL = N->getDebugLoc();
13728 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
13729 // a zext and produces an all-ones bit which is more useful than 0/1 in some
13731 if (X86CC == X86::COND_B)
13732 return DAG.getNode(ISD::AND, DL, MVT::i8,
13733 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
13734 DAG.getConstant(X86CC, MVT::i8), EFLAG),
13735 DAG.getConstant(1, MVT::i8));
13740 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
13741 const X86TargetLowering *XTLI) {
13742 SDValue Op0 = N->getOperand(0);
13743 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
13744 // a 32-bit target where SSE doesn't support i64->FP operations.
13745 if (Op0.getOpcode() == ISD::LOAD) {
13746 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
13747 EVT VT = Ld->getValueType(0);
13748 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
13749 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
13750 !XTLI->getSubtarget()->is64Bit() &&
13751 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
13752 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
13753 Ld->getChain(), Op0, DAG);
13754 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
13761 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
13762 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
13763 X86TargetLowering::DAGCombinerInfo &DCI) {
13764 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
13765 // the result is either zero or one (depending on the input carry bit).
13766 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
13767 if (X86::isZeroNode(N->getOperand(0)) &&
13768 X86::isZeroNode(N->getOperand(1)) &&
13769 // We don't have a good way to replace an EFLAGS use, so only do this when
13771 SDValue(N, 1).use_empty()) {
13772 DebugLoc DL = N->getDebugLoc();
13773 EVT VT = N->getValueType(0);
13774 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
13775 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
13776 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
13777 DAG.getConstant(X86::COND_B,MVT::i8),
13779 DAG.getConstant(1, VT));
13780 return DCI.CombineTo(N, Res1, CarryOut);
13786 // fold (add Y, (sete X, 0)) -> adc 0, Y
13787 // (add Y, (setne X, 0)) -> sbb -1, Y
13788 // (sub (sete X, 0), Y) -> sbb 0, Y
13789 // (sub (setne X, 0), Y) -> adc -1, Y
13790 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
13791 DebugLoc DL = N->getDebugLoc();
13793 // Look through ZExts.
13794 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
13795 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
13798 SDValue SetCC = Ext.getOperand(0);
13799 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
13802 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
13803 if (CC != X86::COND_E && CC != X86::COND_NE)
13806 SDValue Cmp = SetCC.getOperand(1);
13807 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
13808 !X86::isZeroNode(Cmp.getOperand(1)) ||
13809 !Cmp.getOperand(0).getValueType().isInteger())
13812 SDValue CmpOp0 = Cmp.getOperand(0);
13813 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
13814 DAG.getConstant(1, CmpOp0.getValueType()));
13816 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
13817 if (CC == X86::COND_NE)
13818 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
13819 DL, OtherVal.getValueType(), OtherVal,
13820 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
13821 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
13822 DL, OtherVal.getValueType(), OtherVal,
13823 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
13826 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) {
13827 SDValue Op0 = N->getOperand(0);
13828 SDValue Op1 = N->getOperand(1);
13830 // X86 can't encode an immediate LHS of a sub. See if we can push the
13831 // negation into a preceding instruction.
13832 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
13833 // If the RHS of the sub is a XOR with one use and a constant, invert the
13834 // immediate. Then add one to the LHS of the sub so we can turn
13835 // X-Y -> X+~Y+1, saving one register.
13836 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
13837 isa<ConstantSDNode>(Op1.getOperand(1))) {
13838 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
13839 EVT VT = Op0.getValueType();
13840 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
13842 DAG.getConstant(~XorC, VT));
13843 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
13844 DAG.getConstant(C->getAPIntValue()+1, VT));
13848 return OptimizeConditionalInDecrement(N, DAG);
13851 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
13852 DAGCombinerInfo &DCI) const {
13853 SelectionDAG &DAG = DCI.DAG;
13854 switch (N->getOpcode()) {
13856 case ISD::EXTRACT_VECTOR_ELT:
13857 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this);
13858 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
13859 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
13860 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG);
13861 case ISD::SUB: return PerformSubCombine(N, DAG);
13862 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
13863 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
13866 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
13867 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
13868 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
13869 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
13870 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
13872 case X86ISD::FOR: return PerformFORCombine(N, DAG);
13873 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
13874 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
13875 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
13876 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
13877 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG);
13878 case X86ISD::SHUFPS: // Handle all target specific shuffles
13879 case X86ISD::SHUFPD:
13880 case X86ISD::PALIGN:
13881 case X86ISD::PUNPCKHBW:
13882 case X86ISD::PUNPCKHWD:
13883 case X86ISD::PUNPCKHDQ:
13884 case X86ISD::PUNPCKHQDQ:
13885 case X86ISD::UNPCKHPS:
13886 case X86ISD::UNPCKHPD:
13887 case X86ISD::VUNPCKHPSY:
13888 case X86ISD::VUNPCKHPDY:
13889 case X86ISD::PUNPCKLBW:
13890 case X86ISD::PUNPCKLWD:
13891 case X86ISD::PUNPCKLDQ:
13892 case X86ISD::PUNPCKLQDQ:
13893 case X86ISD::UNPCKLPS:
13894 case X86ISD::UNPCKLPD:
13895 case X86ISD::VUNPCKLPSY:
13896 case X86ISD::VUNPCKLPDY:
13897 case X86ISD::MOVHLPS:
13898 case X86ISD::MOVLHPS:
13899 case X86ISD::PSHUFD:
13900 case X86ISD::PSHUFHW:
13901 case X86ISD::PSHUFLW:
13902 case X86ISD::MOVSS:
13903 case X86ISD::MOVSD:
13904 case X86ISD::VPERMILPS:
13905 case X86ISD::VPERMILPSY:
13906 case X86ISD::VPERMILPD:
13907 case X86ISD::VPERMILPDY:
13908 case X86ISD::VPERM2F128:
13909 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
13915 /// isTypeDesirableForOp - Return true if the target has native support for
13916 /// the specified value type and it is 'desirable' to use the type for the
13917 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
13918 /// instruction encodings are longer and some i16 instructions are slow.
13919 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
13920 if (!isTypeLegal(VT))
13922 if (VT != MVT::i16)
13929 case ISD::SIGN_EXTEND:
13930 case ISD::ZERO_EXTEND:
13931 case ISD::ANY_EXTEND:
13944 /// IsDesirableToPromoteOp - This method query the target whether it is
13945 /// beneficial for dag combiner to promote the specified node. If true, it
13946 /// should return the desired promotion type by reference.
13947 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
13948 EVT VT = Op.getValueType();
13949 if (VT != MVT::i16)
13952 bool Promote = false;
13953 bool Commute = false;
13954 switch (Op.getOpcode()) {
13957 LoadSDNode *LD = cast<LoadSDNode>(Op);
13958 // If the non-extending load has a single use and it's not live out, then it
13959 // might be folded.
13960 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
13961 Op.hasOneUse()*/) {
13962 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13963 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
13964 // The only case where we'd want to promote LOAD (rather then it being
13965 // promoted as an operand is when it's only use is liveout.
13966 if (UI->getOpcode() != ISD::CopyToReg)
13973 case ISD::SIGN_EXTEND:
13974 case ISD::ZERO_EXTEND:
13975 case ISD::ANY_EXTEND:
13980 SDValue N0 = Op.getOperand(0);
13981 // Look out for (store (shl (load), x)).
13982 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
13995 SDValue N0 = Op.getOperand(0);
13996 SDValue N1 = Op.getOperand(1);
13997 if (!Commute && MayFoldLoad(N1))
13999 // Avoid disabling potential load folding opportunities.
14000 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
14002 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
14012 //===----------------------------------------------------------------------===//
14013 // X86 Inline Assembly Support
14014 //===----------------------------------------------------------------------===//
14016 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
14017 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
14019 std::string AsmStr = IA->getAsmString();
14021 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
14022 SmallVector<StringRef, 4> AsmPieces;
14023 SplitString(AsmStr, AsmPieces, ";\n");
14025 switch (AsmPieces.size()) {
14026 default: return false;
14028 AsmStr = AsmPieces[0];
14030 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
14032 // FIXME: this should verify that we are targeting a 486 or better. If not,
14033 // we will turn this bswap into something that will be lowered to logical ops
14034 // instead of emitting the bswap asm. For now, we don't support 486 or lower
14035 // so don't worry about this.
14037 if (AsmPieces.size() == 2 &&
14038 (AsmPieces[0] == "bswap" ||
14039 AsmPieces[0] == "bswapq" ||
14040 AsmPieces[0] == "bswapl") &&
14041 (AsmPieces[1] == "$0" ||
14042 AsmPieces[1] == "${0:q}")) {
14043 // No need to check constraints, nothing other than the equivalent of
14044 // "=r,0" would be valid here.
14045 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14046 if (!Ty || Ty->getBitWidth() % 16 != 0)
14048 return IntrinsicLowering::LowerToByteSwap(CI);
14050 // rorw $$8, ${0:w} --> llvm.bswap.i16
14051 if (CI->getType()->isIntegerTy(16) &&
14052 AsmPieces.size() == 3 &&
14053 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") &&
14054 AsmPieces[1] == "$$8," &&
14055 AsmPieces[2] == "${0:w}" &&
14056 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14058 const std::string &ConstraintsStr = IA->getConstraintString();
14059 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14060 std::sort(AsmPieces.begin(), AsmPieces.end());
14061 if (AsmPieces.size() == 4 &&
14062 AsmPieces[0] == "~{cc}" &&
14063 AsmPieces[1] == "~{dirflag}" &&
14064 AsmPieces[2] == "~{flags}" &&
14065 AsmPieces[3] == "~{fpsr}") {
14066 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14067 if (!Ty || Ty->getBitWidth() % 16 != 0)
14069 return IntrinsicLowering::LowerToByteSwap(CI);
14074 if (CI->getType()->isIntegerTy(32) &&
14075 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) {
14076 SmallVector<StringRef, 4> Words;
14077 SplitString(AsmPieces[0], Words, " \t,");
14078 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14079 Words[2] == "${0:w}") {
14081 SplitString(AsmPieces[1], Words, " \t,");
14082 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" &&
14083 Words[2] == "$0") {
14085 SplitString(AsmPieces[2], Words, " \t,");
14086 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" &&
14087 Words[2] == "${0:w}") {
14089 const std::string &ConstraintsStr = IA->getConstraintString();
14090 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
14091 std::sort(AsmPieces.begin(), AsmPieces.end());
14092 if (AsmPieces.size() == 4 &&
14093 AsmPieces[0] == "~{cc}" &&
14094 AsmPieces[1] == "~{dirflag}" &&
14095 AsmPieces[2] == "~{flags}" &&
14096 AsmPieces[3] == "~{fpsr}") {
14097 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14098 if (!Ty || Ty->getBitWidth() % 16 != 0)
14100 return IntrinsicLowering::LowerToByteSwap(CI);
14107 if (CI->getType()->isIntegerTy(64)) {
14108 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
14109 if (Constraints.size() >= 2 &&
14110 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
14111 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
14112 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
14113 SmallVector<StringRef, 4> Words;
14114 SplitString(AsmPieces[0], Words, " \t");
14115 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
14117 SplitString(AsmPieces[1], Words, " \t");
14118 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
14120 SplitString(AsmPieces[2], Words, " \t,");
14121 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
14122 Words[2] == "%edx") {
14123 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
14124 if (!Ty || Ty->getBitWidth() % 16 != 0)
14126 return IntrinsicLowering::LowerToByteSwap(CI);
14139 /// getConstraintType - Given a constraint letter, return the type of
14140 /// constraint it is for this target.
14141 X86TargetLowering::ConstraintType
14142 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
14143 if (Constraint.size() == 1) {
14144 switch (Constraint[0]) {
14155 return C_RegisterClass;
14179 return TargetLowering::getConstraintType(Constraint);
14182 /// Examine constraint type and operand type and determine a weight value.
14183 /// This object must already have been set up with the operand type
14184 /// and the current alternative constraint selected.
14185 TargetLowering::ConstraintWeight
14186 X86TargetLowering::getSingleConstraintMatchWeight(
14187 AsmOperandInfo &info, const char *constraint) const {
14188 ConstraintWeight weight = CW_Invalid;
14189 Value *CallOperandVal = info.CallOperandVal;
14190 // If we don't have a value, we can't do a match,
14191 // but allow it at the lowest weight.
14192 if (CallOperandVal == NULL)
14194 Type *type = CallOperandVal->getType();
14195 // Look at the constraint type.
14196 switch (*constraint) {
14198 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
14209 if (CallOperandVal->getType()->isIntegerTy())
14210 weight = CW_SpecificReg;
14215 if (type->isFloatingPointTy())
14216 weight = CW_SpecificReg;
14219 if (type->isX86_MMXTy() && Subtarget->hasMMX())
14220 weight = CW_SpecificReg;
14224 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM())
14225 weight = CW_Register;
14228 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
14229 if (C->getZExtValue() <= 31)
14230 weight = CW_Constant;
14234 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14235 if (C->getZExtValue() <= 63)
14236 weight = CW_Constant;
14240 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14241 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
14242 weight = CW_Constant;
14246 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14247 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
14248 weight = CW_Constant;
14252 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14253 if (C->getZExtValue() <= 3)
14254 weight = CW_Constant;
14258 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14259 if (C->getZExtValue() <= 0xff)
14260 weight = CW_Constant;
14265 if (dyn_cast<ConstantFP>(CallOperandVal)) {
14266 weight = CW_Constant;
14270 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14271 if ((C->getSExtValue() >= -0x80000000LL) &&
14272 (C->getSExtValue() <= 0x7fffffffLL))
14273 weight = CW_Constant;
14277 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
14278 if (C->getZExtValue() <= 0xffffffff)
14279 weight = CW_Constant;
14286 /// LowerXConstraint - try to replace an X constraint, which matches anything,
14287 /// with another that has more specific requirements based on the type of the
14288 /// corresponding operand.
14289 const char *X86TargetLowering::
14290 LowerXConstraint(EVT ConstraintVT) const {
14291 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
14292 // 'f' like normal targets.
14293 if (ConstraintVT.isFloatingPoint()) {
14294 if (Subtarget->hasXMMInt())
14296 if (Subtarget->hasXMM())
14300 return TargetLowering::LowerXConstraint(ConstraintVT);
14303 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
14304 /// vector. If it is invalid, don't add anything to Ops.
14305 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
14306 std::string &Constraint,
14307 std::vector<SDValue>&Ops,
14308 SelectionDAG &DAG) const {
14309 SDValue Result(0, 0);
14311 // Only support length 1 constraints for now.
14312 if (Constraint.length() > 1) return;
14314 char ConstraintLetter = Constraint[0];
14315 switch (ConstraintLetter) {
14318 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14319 if (C->getZExtValue() <= 31) {
14320 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14326 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14327 if (C->getZExtValue() <= 63) {
14328 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14334 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14335 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
14336 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14343 if (C->getZExtValue() <= 255) {
14344 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14350 // 32-bit signed value
14351 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14352 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14353 C->getSExtValue())) {
14354 // Widen to 64 bits here to get it sign extended.
14355 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
14358 // FIXME gcc accepts some relocatable values here too, but only in certain
14359 // memory models; it's complicated.
14364 // 32-bit unsigned value
14365 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
14366 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
14367 C->getZExtValue())) {
14368 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
14372 // FIXME gcc accepts some relocatable values here too, but only in certain
14373 // memory models; it's complicated.
14377 // Literal immediates are always ok.
14378 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
14379 // Widen to 64 bits here to get it sign extended.
14380 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
14384 // In any sort of PIC mode addresses need to be computed at runtime by
14385 // adding in a register or some sort of table lookup. These can't
14386 // be used as immediates.
14387 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
14390 // If we are in non-pic codegen mode, we allow the address of a global (with
14391 // an optional displacement) to be used with 'i'.
14392 GlobalAddressSDNode *GA = 0;
14393 int64_t Offset = 0;
14395 // Match either (GA), (GA+C), (GA+C1+C2), etc.
14397 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
14398 Offset += GA->getOffset();
14400 } else if (Op.getOpcode() == ISD::ADD) {
14401 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14402 Offset += C->getZExtValue();
14403 Op = Op.getOperand(0);
14406 } else if (Op.getOpcode() == ISD::SUB) {
14407 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
14408 Offset += -C->getZExtValue();
14409 Op = Op.getOperand(0);
14414 // Otherwise, this isn't something we can handle, reject it.
14418 const GlobalValue *GV = GA->getGlobal();
14419 // If we require an extra load to get this address, as in PIC mode, we
14420 // can't accept it.
14421 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
14422 getTargetMachine())))
14425 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
14426 GA->getValueType(0), Offset);
14431 if (Result.getNode()) {
14432 Ops.push_back(Result);
14435 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
14438 std::pair<unsigned, const TargetRegisterClass*>
14439 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
14441 // First, see if this is a constraint that directly corresponds to an LLVM
14443 if (Constraint.size() == 1) {
14444 // GCC Constraint Letters
14445 switch (Constraint[0]) {
14447 // TODO: Slight differences here in allocation order and leaving
14448 // RIP in the class. Do they matter any more here than they do
14449 // in the normal allocation?
14450 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
14451 if (Subtarget->is64Bit()) {
14452 if (VT == MVT::i32 || VT == MVT::f32)
14453 return std::make_pair(0U, X86::GR32RegisterClass);
14454 else if (VT == MVT::i16)
14455 return std::make_pair(0U, X86::GR16RegisterClass);
14456 else if (VT == MVT::i8 || VT == MVT::i1)
14457 return std::make_pair(0U, X86::GR8RegisterClass);
14458 else if (VT == MVT::i64 || VT == MVT::f64)
14459 return std::make_pair(0U, X86::GR64RegisterClass);
14462 // 32-bit fallthrough
14463 case 'Q': // Q_REGS
14464 if (VT == MVT::i32 || VT == MVT::f32)
14465 return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
14466 else if (VT == MVT::i16)
14467 return std::make_pair(0U, X86::GR16_ABCDRegisterClass);
14468 else if (VT == MVT::i8 || VT == MVT::i1)
14469 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass);
14470 else if (VT == MVT::i64)
14471 return std::make_pair(0U, X86::GR64_ABCDRegisterClass);
14473 case 'r': // GENERAL_REGS
14474 case 'l': // INDEX_REGS
14475 if (VT == MVT::i8 || VT == MVT::i1)
14476 return std::make_pair(0U, X86::GR8RegisterClass);
14477 if (VT == MVT::i16)
14478 return std::make_pair(0U, X86::GR16RegisterClass);
14479 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
14480 return std::make_pair(0U, X86::GR32RegisterClass);
14481 return std::make_pair(0U, X86::GR64RegisterClass);
14482 case 'R': // LEGACY_REGS
14483 if (VT == MVT::i8 || VT == MVT::i1)
14484 return std::make_pair(0U, X86::GR8_NOREXRegisterClass);
14485 if (VT == MVT::i16)
14486 return std::make_pair(0U, X86::GR16_NOREXRegisterClass);
14487 if (VT == MVT::i32 || !Subtarget->is64Bit())
14488 return std::make_pair(0U, X86::GR32_NOREXRegisterClass);
14489 return std::make_pair(0U, X86::GR64_NOREXRegisterClass);
14490 case 'f': // FP Stack registers.
14491 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
14492 // value to the correct fpstack register class.
14493 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
14494 return std::make_pair(0U, X86::RFP32RegisterClass);
14495 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
14496 return std::make_pair(0U, X86::RFP64RegisterClass);
14497 return std::make_pair(0U, X86::RFP80RegisterClass);
14498 case 'y': // MMX_REGS if MMX allowed.
14499 if (!Subtarget->hasMMX()) break;
14500 return std::make_pair(0U, X86::VR64RegisterClass);
14501 case 'Y': // SSE_REGS if SSE2 allowed
14502 if (!Subtarget->hasXMMInt()) break;
14504 case 'x': // SSE_REGS if SSE1 allowed
14505 if (!Subtarget->hasXMM()) break;
14507 switch (VT.getSimpleVT().SimpleTy) {
14509 // Scalar SSE types.
14512 return std::make_pair(0U, X86::FR32RegisterClass);
14515 return std::make_pair(0U, X86::FR64RegisterClass);
14523 return std::make_pair(0U, X86::VR128RegisterClass);
14529 // Use the default implementation in TargetLowering to convert the register
14530 // constraint into a member of a register class.
14531 std::pair<unsigned, const TargetRegisterClass*> Res;
14532 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
14534 // Not found as a standard register?
14535 if (Res.second == 0) {
14536 // Map st(0) -> st(7) -> ST0
14537 if (Constraint.size() == 7 && Constraint[0] == '{' &&
14538 tolower(Constraint[1]) == 's' &&
14539 tolower(Constraint[2]) == 't' &&
14540 Constraint[3] == '(' &&
14541 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
14542 Constraint[5] == ')' &&
14543 Constraint[6] == '}') {
14545 Res.first = X86::ST0+Constraint[4]-'0';
14546 Res.second = X86::RFP80RegisterClass;
14550 // GCC allows "st(0)" to be called just plain "st".
14551 if (StringRef("{st}").equals_lower(Constraint)) {
14552 Res.first = X86::ST0;
14553 Res.second = X86::RFP80RegisterClass;
14558 if (StringRef("{flags}").equals_lower(Constraint)) {
14559 Res.first = X86::EFLAGS;
14560 Res.second = X86::CCRRegisterClass;
14564 // 'A' means EAX + EDX.
14565 if (Constraint == "A") {
14566 Res.first = X86::EAX;
14567 Res.second = X86::GR32_ADRegisterClass;
14573 // Otherwise, check to see if this is a register class of the wrong value
14574 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
14575 // turn into {ax},{dx}.
14576 if (Res.second->hasType(VT))
14577 return Res; // Correct type already, nothing to do.
14579 // All of the single-register GCC register classes map their values onto
14580 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
14581 // really want an 8-bit or 32-bit register, map to the appropriate register
14582 // class and return the appropriate register.
14583 if (Res.second == X86::GR16RegisterClass) {
14584 if (VT == MVT::i8) {
14585 unsigned DestReg = 0;
14586 switch (Res.first) {
14588 case X86::AX: DestReg = X86::AL; break;
14589 case X86::DX: DestReg = X86::DL; break;
14590 case X86::CX: DestReg = X86::CL; break;
14591 case X86::BX: DestReg = X86::BL; break;
14594 Res.first = DestReg;
14595 Res.second = X86::GR8RegisterClass;
14597 } else if (VT == MVT::i32) {
14598 unsigned DestReg = 0;
14599 switch (Res.first) {
14601 case X86::AX: DestReg = X86::EAX; break;
14602 case X86::DX: DestReg = X86::EDX; break;
14603 case X86::CX: DestReg = X86::ECX; break;
14604 case X86::BX: DestReg = X86::EBX; break;
14605 case X86::SI: DestReg = X86::ESI; break;
14606 case X86::DI: DestReg = X86::EDI; break;
14607 case X86::BP: DestReg = X86::EBP; break;
14608 case X86::SP: DestReg = X86::ESP; break;
14611 Res.first = DestReg;
14612 Res.second = X86::GR32RegisterClass;
14614 } else if (VT == MVT::i64) {
14615 unsigned DestReg = 0;
14616 switch (Res.first) {
14618 case X86::AX: DestReg = X86::RAX; break;
14619 case X86::DX: DestReg = X86::RDX; break;
14620 case X86::CX: DestReg = X86::RCX; break;
14621 case X86::BX: DestReg = X86::RBX; break;
14622 case X86::SI: DestReg = X86::RSI; break;
14623 case X86::DI: DestReg = X86::RDI; break;
14624 case X86::BP: DestReg = X86::RBP; break;
14625 case X86::SP: DestReg = X86::RSP; break;
14628 Res.first = DestReg;
14629 Res.second = X86::GR64RegisterClass;
14632 } else if (Res.second == X86::FR32RegisterClass ||
14633 Res.second == X86::FR64RegisterClass ||
14634 Res.second == X86::VR128RegisterClass) {
14635 // Handle references to XMM physical registers that got mapped into the
14636 // wrong class. This can happen with constraints like {xmm0} where the
14637 // target independent register mapper will just pick the first match it can
14638 // find, ignoring the required type.
14639 if (VT == MVT::f32)
14640 Res.second = X86::FR32RegisterClass;
14641 else if (VT == MVT::f64)
14642 Res.second = X86::FR64RegisterClass;
14643 else if (X86::VR128RegisterClass->hasType(VT))
14644 Res.second = X86::VR128RegisterClass;