1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/CodeGen/IntrinsicLowering.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/Constants.h"
35 #include "llvm/DerivedTypes.h"
36 #include "llvm/Function.h"
37 #include "llvm/GlobalAlias.h"
38 #include "llvm/GlobalVariable.h"
39 #include "llvm/Instructions.h"
40 #include "llvm/Intrinsics.h"
41 #include "llvm/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
89 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
95 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
96 /// sets things up to match to an AVX VINSERTF128 instruction or a
97 /// simple superregister reference. Idx is an index in the 128 bits
98 /// we want. It need not be aligned to a 128-bit bounday. That makes
99 /// lowering INSERT_VECTOR_ELT operations easier.
100 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
101 unsigned IdxVal, SelectionDAG &DAG,
103 // Inserting UNDEF is Result
104 if (Vec.getOpcode() == ISD::UNDEF)
107 EVT VT = Vec.getValueType();
108 assert(VT.is128BitVector() && "Unexpected vector size!");
110 EVT ElVT = VT.getVectorElementType();
111 EVT ResultVT = Result.getValueType();
113 // Insert the relevant 128 bits.
114 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
116 // This is the index of the first element of the 128-bit chunk
118 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
121 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
122 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
126 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
127 /// instructions. This is used because creating CONCAT_VECTOR nodes of
128 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
129 /// large BUILD_VECTORS.
130 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
131 unsigned NumElems, SelectionDAG &DAG,
133 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
134 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
137 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
138 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
139 bool is64Bit = Subtarget->is64Bit();
141 if (Subtarget->isTargetEnvMacho()) {
143 return new X86_64MachoTargetObjectFile();
144 return new TargetLoweringObjectFileMachO();
147 if (Subtarget->isTargetLinux())
148 return new X86LinuxTargetObjectFile();
149 if (Subtarget->isTargetELF())
150 return new TargetLoweringObjectFileELF();
151 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
152 return new TargetLoweringObjectFileCOFF();
153 llvm_unreachable("unknown subtarget type");
156 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<X86Subtarget>();
159 X86ScalarSSEf64 = Subtarget->hasSSE2();
160 X86ScalarSSEf32 = Subtarget->hasSSE1();
162 RegInfo = TM.getRegisterInfo();
163 TD = getDataLayout();
165 // Set up the TargetLowering object.
166 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
168 // X86 is weird, it always uses i8 for shift amounts and setcc results.
169 setBooleanContents(ZeroOrOneBooleanContent);
170 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
171 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
173 // For 64-bit since we have so many registers use the ILP scheduler, for
174 // 32-bit code use the register pressure specific scheduling.
175 // For Atom, always use ILP scheduling.
176 if (Subtarget->isAtom())
177 setSchedulingPreference(Sched::ILP);
178 else if (Subtarget->is64Bit())
179 setSchedulingPreference(Sched::ILP);
181 setSchedulingPreference(Sched::RegPressure);
182 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
184 // Bypass i32 with i8 on Atom when compiling with O2
185 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default)
186 addBypassSlowDiv(32, 8);
188 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
189 // Setup Windows compiler runtime calls.
190 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
191 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
192 setLibcallName(RTLIB::SREM_I64, "_allrem");
193 setLibcallName(RTLIB::UREM_I64, "_aullrem");
194 setLibcallName(RTLIB::MUL_I64, "_allmul");
195 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
196 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
197 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
198 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
199 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
201 // The _ftol2 runtime function has an unusual calling conv, which
202 // is modeled by a special pseudo-instruction.
203 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
204 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
205 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
206 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
209 if (Subtarget->isTargetDarwin()) {
210 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
211 setUseUnderscoreSetJmp(false);
212 setUseUnderscoreLongJmp(false);
213 } else if (Subtarget->isTargetMingw()) {
214 // MS runtime is weird: it exports _setjmp, but longjmp!
215 setUseUnderscoreSetJmp(true);
216 setUseUnderscoreLongJmp(false);
218 setUseUnderscoreSetJmp(true);
219 setUseUnderscoreLongJmp(true);
222 // Set up the register classes.
223 addRegisterClass(MVT::i8, &X86::GR8RegClass);
224 addRegisterClass(MVT::i16, &X86::GR16RegClass);
225 addRegisterClass(MVT::i32, &X86::GR32RegClass);
226 if (Subtarget->is64Bit())
227 addRegisterClass(MVT::i64, &X86::GR64RegClass);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
231 // We don't accept any truncstore of integer registers.
232 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
233 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
234 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
235 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
236 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
237 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
239 // SETOEQ and SETUNE require checking two conditions.
240 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
243 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
244 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
245 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
247 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
249 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
251 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
253 if (Subtarget->is64Bit()) {
254 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
255 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
256 } else if (!TM.Options.UseSoftFloat) {
257 // We have an algorithm for SSE2->double, and we turn this into a
258 // 64-bit FILD followed by conditional FADD for other targets.
259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
260 // We have an algorithm for SSE2, and we turn this into a 64-bit
261 // FILD for other targets.
262 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
265 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
267 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
268 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
270 if (!TM.Options.UseSoftFloat) {
271 // SSE has no i16 to fp conversion, only i32
272 if (X86ScalarSSEf32) {
273 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
274 // f32 and f64 cases are Legal, f80 case is not
275 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
278 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
285 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
286 // are Legal, f80 is custom lowered.
287 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
288 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
290 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
292 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
293 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
295 if (X86ScalarSSEf32) {
296 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
297 // f32 and f64 cases are Legal, f80 case is not
298 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
301 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
304 // Handle FP_TO_UINT by promoting the destination to a larger signed
306 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
308 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
310 if (Subtarget->is64Bit()) {
311 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
312 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
313 } else if (!TM.Options.UseSoftFloat) {
314 // Since AVX is a superset of SSE3, only check for SSE here.
315 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
316 // Expand FP_TO_UINT into a select.
317 // FIXME: We would like to use a Custom expander here eventually to do
318 // the optimal thing for SSE vs. the default expansion in the legalizer.
319 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
321 // With SSE3 we can use fisttpll to convert to a signed i64; without
322 // SSE, we're stuck with a fistpll.
323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
326 if (isTargetFTOL()) {
327 // Use the _ftol2 runtime function, which has a pseudo-instruction
328 // to handle its weird calling convention.
329 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
332 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
333 if (!X86ScalarSSEf64) {
334 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
335 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
338 // Without SSE, i64->f64 goes through memory.
339 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
343 // Scalar integer divide and remainder are lowered to use operations that
344 // produce two results, to match the available instructions. This exposes
345 // the two-result form to trivial CSE, which is able to combine x/y and x%y
346 // into a single instruction.
348 // Scalar integer multiply-high is also lowered to use two-result
349 // operations, to match the available instructions. However, plain multiply
350 // (low) operations are left as Legal, as there are single-result
351 // instructions for this in x86. Using the two-result multiply instructions
352 // when both high and low results are needed must be arranged by dagcombine.
353 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
355 setOperationAction(ISD::MULHS, VT, Expand);
356 setOperationAction(ISD::MULHU, VT, Expand);
357 setOperationAction(ISD::SDIV, VT, Expand);
358 setOperationAction(ISD::UDIV, VT, Expand);
359 setOperationAction(ISD::SREM, VT, Expand);
360 setOperationAction(ISD::UREM, VT, Expand);
362 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
363 setOperationAction(ISD::ADDC, VT, Custom);
364 setOperationAction(ISD::ADDE, VT, Custom);
365 setOperationAction(ISD::SUBC, VT, Custom);
366 setOperationAction(ISD::SUBE, VT, Custom);
369 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
370 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
371 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
372 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
373 if (Subtarget->is64Bit())
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
376 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
377 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
378 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
379 setOperationAction(ISD::FREM , MVT::f32 , Expand);
380 setOperationAction(ISD::FREM , MVT::f64 , Expand);
381 setOperationAction(ISD::FREM , MVT::f80 , Expand);
382 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
384 // Promote the i8 variants and force them on up to i32 which has a shorter
386 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
387 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
388 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
389 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
390 if (Subtarget->hasBMI()) {
391 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
393 if (Subtarget->is64Bit())
394 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
396 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
397 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
398 if (Subtarget->is64Bit())
399 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
402 if (Subtarget->hasLZCNT()) {
403 // When promoting the i8 variants, force them to i32 for a shorter
405 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
406 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
407 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
408 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
409 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
410 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
411 if (Subtarget->is64Bit())
412 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
414 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
415 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
416 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
417 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
418 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
419 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
420 if (Subtarget->is64Bit()) {
421 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
422 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
426 if (Subtarget->hasPOPCNT()) {
427 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
429 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
430 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
431 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
436 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
437 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
439 // These should be promoted to a larger select which is supported.
440 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
441 // X86 wants to expand cmov itself.
442 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
443 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
444 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
445 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
446 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
447 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
448 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
449 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
450 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
451 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
452 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
453 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
454 if (Subtarget->is64Bit()) {
455 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
456 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
458 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
459 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intened to support
460 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
461 // support continuation, user-level threading, and etc.. As a result, no
462 // other SjLj exception interfaces are implemented and please don't build
463 // your own exception handling based on them.
464 // LLVM/Clang supports zero-cost DWARF exception handling.
465 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
466 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
469 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
470 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
471 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
472 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
473 if (Subtarget->is64Bit())
474 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
475 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
476 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
477 if (Subtarget->is64Bit()) {
478 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
479 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
480 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
481 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
482 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
484 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
485 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
486 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
487 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
488 if (Subtarget->is64Bit()) {
489 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
490 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
491 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
494 if (Subtarget->hasSSE1())
495 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
497 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
498 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
500 // On X86 and X86-64, atomic operations are lowered to locked instructions.
501 // Locked instructions, in turn, have implicit fence semantics (all memory
502 // operations are flushed before issuing the locked instruction, and they
503 // are not buffered), so we can fold away the common pattern of
504 // fence-atomic-fence.
505 setShouldFoldAtomicFences(true);
507 // Expand certain atomics
508 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
510 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
511 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
512 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
515 if (!Subtarget->is64Bit()) {
516 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
517 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
518 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
519 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
520 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
521 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
522 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
523 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
524 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
525 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
526 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
527 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
530 if (Subtarget->hasCmpxchg16b()) {
531 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
534 // FIXME - use subtarget debug flags
535 if (!Subtarget->isTargetDarwin() &&
536 !Subtarget->isTargetELF() &&
537 !Subtarget->isTargetCygMing()) {
538 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
541 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
542 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
543 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
544 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
545 if (Subtarget->is64Bit()) {
546 setExceptionPointerRegister(X86::RAX);
547 setExceptionSelectorRegister(X86::RDX);
549 setExceptionPointerRegister(X86::EAX);
550 setExceptionSelectorRegister(X86::EDX);
552 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
553 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
555 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
556 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
558 setOperationAction(ISD::TRAP, MVT::Other, Legal);
559 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
561 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
562 setOperationAction(ISD::VASTART , MVT::Other, Custom);
563 setOperationAction(ISD::VAEND , MVT::Other, Expand);
564 if (Subtarget->is64Bit()) {
565 setOperationAction(ISD::VAARG , MVT::Other, Custom);
566 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
568 setOperationAction(ISD::VAARG , MVT::Other, Expand);
569 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
572 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
573 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
575 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
576 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
577 MVT::i64 : MVT::i32, Custom);
578 else if (TM.Options.EnableSegmentedStacks)
579 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
580 MVT::i64 : MVT::i32, Custom);
582 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
583 MVT::i64 : MVT::i32, Expand);
585 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
586 // f32 and f64 use SSE.
587 // Set up the FP register classes.
588 addRegisterClass(MVT::f32, &X86::FR32RegClass);
589 addRegisterClass(MVT::f64, &X86::FR64RegClass);
591 // Use ANDPD to simulate FABS.
592 setOperationAction(ISD::FABS , MVT::f64, Custom);
593 setOperationAction(ISD::FABS , MVT::f32, Custom);
595 // Use XORP to simulate FNEG.
596 setOperationAction(ISD::FNEG , MVT::f64, Custom);
597 setOperationAction(ISD::FNEG , MVT::f32, Custom);
599 // Use ANDPD and ORPD to simulate FCOPYSIGN.
600 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
601 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
603 // Lower this to FGETSIGNx86 plus an AND.
604 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
605 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
607 // We don't support sin/cos/fmod
608 setOperationAction(ISD::FSIN , MVT::f64, Expand);
609 setOperationAction(ISD::FCOS , MVT::f64, Expand);
610 setOperationAction(ISD::FSIN , MVT::f32, Expand);
611 setOperationAction(ISD::FCOS , MVT::f32, Expand);
613 // Expand FP immediates into loads from the stack, except for the special
615 addLegalFPImmediate(APFloat(+0.0)); // xorpd
616 addLegalFPImmediate(APFloat(+0.0f)); // xorps
617 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
618 // Use SSE for f32, x87 for f64.
619 // Set up the FP register classes.
620 addRegisterClass(MVT::f32, &X86::FR32RegClass);
621 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
623 // Use ANDPS to simulate FABS.
624 setOperationAction(ISD::FABS , MVT::f32, Custom);
626 // Use XORP to simulate FNEG.
627 setOperationAction(ISD::FNEG , MVT::f32, Custom);
629 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
631 // Use ANDPS and ORPS to simulate FCOPYSIGN.
632 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
633 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
635 // We don't support sin/cos/fmod
636 setOperationAction(ISD::FSIN , MVT::f32, Expand);
637 setOperationAction(ISD::FCOS , MVT::f32, Expand);
639 // Special cases we handle for FP constants.
640 addLegalFPImmediate(APFloat(+0.0f)); // xorps
641 addLegalFPImmediate(APFloat(+0.0)); // FLD0
642 addLegalFPImmediate(APFloat(+1.0)); // FLD1
643 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
644 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
646 if (!TM.Options.UnsafeFPMath) {
647 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
648 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
650 } else if (!TM.Options.UseSoftFloat) {
651 // f32 and f64 in x87.
652 // Set up the FP register classes.
653 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
654 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
656 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
657 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
658 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
659 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
661 if (!TM.Options.UnsafeFPMath) {
662 setOperationAction(ISD::FSIN , MVT::f32 , Expand);
663 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
664 setOperationAction(ISD::FCOS , MVT::f32 , Expand);
665 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
667 addLegalFPImmediate(APFloat(+0.0)); // FLD0
668 addLegalFPImmediate(APFloat(+1.0)); // FLD1
669 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
670 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
671 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
672 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
673 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
674 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
677 // We don't support FMA.
678 setOperationAction(ISD::FMA, MVT::f64, Expand);
679 setOperationAction(ISD::FMA, MVT::f32, Expand);
681 // Long double always uses X87.
682 if (!TM.Options.UseSoftFloat) {
683 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
684 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
685 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
687 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
688 addLegalFPImmediate(TmpFlt); // FLD0
690 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
693 APFloat TmpFlt2(+1.0);
694 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
696 addLegalFPImmediate(TmpFlt2); // FLD1
697 TmpFlt2.changeSign();
698 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
701 if (!TM.Options.UnsafeFPMath) {
702 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
703 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
706 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
707 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
708 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
709 setOperationAction(ISD::FRINT, MVT::f80, Expand);
710 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
711 setOperationAction(ISD::FMA, MVT::f80, Expand);
714 // Always use a library call for pow.
715 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
716 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
717 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
719 setOperationAction(ISD::FLOG, MVT::f80, Expand);
720 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
721 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
722 setOperationAction(ISD::FEXP, MVT::f80, Expand);
723 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
725 // First set operation action for all vector types to either promote
726 // (for widening) or expand (for scalarization). Then we will selectively
727 // turn on ones that can be effectively codegen'd.
728 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
729 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
730 MVT VT = (MVT::SimpleValueType)i;
731 setOperationAction(ISD::ADD , VT, Expand);
732 setOperationAction(ISD::SUB , VT, Expand);
733 setOperationAction(ISD::FADD, VT, Expand);
734 setOperationAction(ISD::FNEG, VT, Expand);
735 setOperationAction(ISD::FSUB, VT, Expand);
736 setOperationAction(ISD::MUL , VT, Expand);
737 setOperationAction(ISD::FMUL, VT, Expand);
738 setOperationAction(ISD::SDIV, VT, Expand);
739 setOperationAction(ISD::UDIV, VT, Expand);
740 setOperationAction(ISD::FDIV, VT, Expand);
741 setOperationAction(ISD::SREM, VT, Expand);
742 setOperationAction(ISD::UREM, VT, Expand);
743 setOperationAction(ISD::LOAD, VT, Expand);
744 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
745 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
746 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
747 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
748 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
749 setOperationAction(ISD::FABS, VT, Expand);
750 setOperationAction(ISD::FSIN, VT, Expand);
751 setOperationAction(ISD::FCOS, VT, Expand);
752 setOperationAction(ISD::FREM, VT, Expand);
753 setOperationAction(ISD::FMA, VT, Expand);
754 setOperationAction(ISD::FPOWI, VT, Expand);
755 setOperationAction(ISD::FSQRT, VT, Expand);
756 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
757 setOperationAction(ISD::FFLOOR, VT, Expand);
758 setOperationAction(ISD::FCEIL, VT, Expand);
759 setOperationAction(ISD::FTRUNC, VT, Expand);
760 setOperationAction(ISD::FRINT, VT, Expand);
761 setOperationAction(ISD::FNEARBYINT, VT, Expand);
762 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
763 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
764 setOperationAction(ISD::SDIVREM, VT, Expand);
765 setOperationAction(ISD::UDIVREM, VT, Expand);
766 setOperationAction(ISD::FPOW, VT, Expand);
767 setOperationAction(ISD::CTPOP, VT, Expand);
768 setOperationAction(ISD::CTTZ, VT, Expand);
769 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
770 setOperationAction(ISD::CTLZ, VT, Expand);
771 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
772 setOperationAction(ISD::SHL, VT, Expand);
773 setOperationAction(ISD::SRA, VT, Expand);
774 setOperationAction(ISD::SRL, VT, Expand);
775 setOperationAction(ISD::ROTL, VT, Expand);
776 setOperationAction(ISD::ROTR, VT, Expand);
777 setOperationAction(ISD::BSWAP, VT, Expand);
778 setOperationAction(ISD::SETCC, VT, Expand);
779 setOperationAction(ISD::FLOG, VT, Expand);
780 setOperationAction(ISD::FLOG2, VT, Expand);
781 setOperationAction(ISD::FLOG10, VT, Expand);
782 setOperationAction(ISD::FEXP, VT, Expand);
783 setOperationAction(ISD::FEXP2, VT, Expand);
784 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
785 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
786 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
787 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
788 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
789 setOperationAction(ISD::TRUNCATE, VT, Expand);
790 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
791 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
792 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
793 setOperationAction(ISD::VSELECT, VT, Expand);
794 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
795 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
796 setTruncStoreAction(VT,
797 (MVT::SimpleValueType)InnerVT, Expand);
798 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
799 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
800 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
803 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
804 // with -msoft-float, disable use of MMX as well.
805 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
806 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
807 // No operations on x86mmx supported, everything uses intrinsics.
810 // MMX-sized vectors (other than x86mmx) are expected to be expanded
811 // into smaller operations.
812 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
813 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
814 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
815 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
816 setOperationAction(ISD::AND, MVT::v8i8, Expand);
817 setOperationAction(ISD::AND, MVT::v4i16, Expand);
818 setOperationAction(ISD::AND, MVT::v2i32, Expand);
819 setOperationAction(ISD::AND, MVT::v1i64, Expand);
820 setOperationAction(ISD::OR, MVT::v8i8, Expand);
821 setOperationAction(ISD::OR, MVT::v4i16, Expand);
822 setOperationAction(ISD::OR, MVT::v2i32, Expand);
823 setOperationAction(ISD::OR, MVT::v1i64, Expand);
824 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
825 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
826 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
827 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
828 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
829 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
830 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
831 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
832 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
833 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
834 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
835 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
836 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
837 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
838 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
839 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
840 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
842 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
843 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
845 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
846 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
847 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
848 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
849 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
850 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
851 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
852 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
853 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
855 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
856 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
859 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
860 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
862 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
863 // registers cannot be used even for integer operations.
864 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
865 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
866 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
867 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
869 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
870 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
871 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
872 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
873 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
874 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
875 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
876 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
877 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
878 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
879 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
880 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
881 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
882 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
883 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
884 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
885 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
886 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
888 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
889 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
890 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
891 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
893 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
894 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
895 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
896 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
897 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
899 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
900 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
901 MVT VT = (MVT::SimpleValueType)i;
902 // Do not attempt to custom lower non-power-of-2 vectors
903 if (!isPowerOf2_32(VT.getVectorNumElements()))
905 // Do not attempt to custom lower non-128-bit vectors
906 if (!VT.is128BitVector())
908 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
909 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
910 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
913 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
914 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
915 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
916 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
917 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
918 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
920 if (Subtarget->is64Bit()) {
921 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
922 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
925 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
926 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
927 MVT VT = (MVT::SimpleValueType)i;
929 // Do not attempt to promote non-128-bit vectors
930 if (!VT.is128BitVector())
933 setOperationAction(ISD::AND, VT, Promote);
934 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
935 setOperationAction(ISD::OR, VT, Promote);
936 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
937 setOperationAction(ISD::XOR, VT, Promote);
938 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
939 setOperationAction(ISD::LOAD, VT, Promote);
940 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
941 setOperationAction(ISD::SELECT, VT, Promote);
942 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
945 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
947 // Custom lower v2i64 and v2f64 selects.
948 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
949 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
950 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
951 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
953 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
954 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
956 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
957 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
958 // As there is no 64-bit GPR available, we need build a special custom
959 // sequence to convert from v2i32 to v2f32.
960 if (!Subtarget->is64Bit())
961 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
963 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
964 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
966 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
969 if (Subtarget->hasSSE41()) {
970 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
971 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
972 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
973 setOperationAction(ISD::FRINT, MVT::f32, Legal);
974 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
975 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
976 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
977 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
978 setOperationAction(ISD::FRINT, MVT::f64, Legal);
979 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
981 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
982 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
983 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
984 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
985 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
986 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
987 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
988 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
989 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
990 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
992 // FIXME: Do we need to handle scalar-to-vector here?
993 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
995 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
996 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
997 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
998 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
999 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1001 // i8 and i16 vectors are custom , because the source register and source
1002 // source memory operand types are not the same width. f32 vectors are
1003 // custom since the immediate controlling the insert encodes additional
1005 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1006 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1007 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1008 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1010 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1012 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1013 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1015 // FIXME: these should be Legal but thats only for the case where
1016 // the index is constant. For now custom expand to deal with that.
1017 if (Subtarget->is64Bit()) {
1018 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1019 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1023 if (Subtarget->hasSSE2()) {
1024 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1025 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1027 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1028 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1030 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1031 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1033 if (Subtarget->hasInt256()) {
1034 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
1035 setOperationAction(ISD::SRL, MVT::v4i32, Legal);
1037 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1038 setOperationAction(ISD::SHL, MVT::v4i32, Legal);
1040 setOperationAction(ISD::SRA, MVT::v4i32, Legal);
1042 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1043 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1048 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1052 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1053 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1060 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1064 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1075 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1088 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1090 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1091 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1097 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1099 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1103 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1105 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1106 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1108 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1109 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1111 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1112 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1114 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1119 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1120 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1123 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1124 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1125 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1126 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1128 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1131 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1135 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1136 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1137 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1138 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1139 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1140 setOperationAction(ISD::FMA, MVT::f32, Legal);
1141 setOperationAction(ISD::FMA, MVT::f64, Legal);
1144 if (Subtarget->hasInt256()) {
1145 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1146 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1147 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1148 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1150 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1151 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1152 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1153 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1155 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1156 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1157 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1158 // Don't lower v32i8 because there is no 128-bit byte mul
1160 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1162 setOperationAction(ISD::SRL, MVT::v4i64, Legal);
1163 setOperationAction(ISD::SRL, MVT::v8i32, Legal);
1165 setOperationAction(ISD::SHL, MVT::v4i64, Legal);
1166 setOperationAction(ISD::SHL, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SRA, MVT::v8i32, Legal);
1170 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1171 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1172 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1173 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1175 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1176 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1177 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1178 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1180 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1181 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1182 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1183 // Don't lower v32i8 because there is no 128-bit byte mul
1185 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1186 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1188 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1189 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1191 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1194 // Custom lower several nodes for 256-bit types.
1195 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1196 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1197 MVT VT = (MVT::SimpleValueType)i;
1199 // Extract subvector is special because the value type
1200 // (result) is 128-bit but the source is 256-bit wide.
1201 if (VT.is128BitVector())
1202 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1204 // Do not attempt to custom lower other non-256-bit vectors
1205 if (!VT.is256BitVector())
1208 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1209 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1210 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1211 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1212 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1213 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1214 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1217 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1218 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1219 MVT VT = (MVT::SimpleValueType)i;
1221 // Do not attempt to promote non-256-bit vectors
1222 if (!VT.is256BitVector())
1225 setOperationAction(ISD::AND, VT, Promote);
1226 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1227 setOperationAction(ISD::OR, VT, Promote);
1228 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1229 setOperationAction(ISD::XOR, VT, Promote);
1230 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1231 setOperationAction(ISD::LOAD, VT, Promote);
1232 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1233 setOperationAction(ISD::SELECT, VT, Promote);
1234 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1238 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1239 // of this type with custom code.
1240 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1241 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1242 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1246 // We want to custom lower some of our intrinsics.
1247 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1248 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1250 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1251 // handle type legalization for these operations here.
1253 // FIXME: We really should do custom legalization for addition and
1254 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1255 // than generic legalization for 64-bit multiplication-with-overflow, though.
1256 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1257 // Add/Sub/Mul with overflow operations are custom lowered.
1259 setOperationAction(ISD::SADDO, VT, Custom);
1260 setOperationAction(ISD::UADDO, VT, Custom);
1261 setOperationAction(ISD::SSUBO, VT, Custom);
1262 setOperationAction(ISD::USUBO, VT, Custom);
1263 setOperationAction(ISD::SMULO, VT, Custom);
1264 setOperationAction(ISD::UMULO, VT, Custom);
1267 // There are no 8-bit 3-address imul/mul instructions
1268 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1269 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1271 if (!Subtarget->is64Bit()) {
1272 // These libcalls are not available in 32-bit.
1273 setLibcallName(RTLIB::SHL_I128, 0);
1274 setLibcallName(RTLIB::SRL_I128, 0);
1275 setLibcallName(RTLIB::SRA_I128, 0);
1278 // We have target-specific dag combine patterns for the following nodes:
1279 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1280 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1281 setTargetDAGCombine(ISD::VSELECT);
1282 setTargetDAGCombine(ISD::SELECT);
1283 setTargetDAGCombine(ISD::SHL);
1284 setTargetDAGCombine(ISD::SRA);
1285 setTargetDAGCombine(ISD::SRL);
1286 setTargetDAGCombine(ISD::OR);
1287 setTargetDAGCombine(ISD::AND);
1288 setTargetDAGCombine(ISD::ADD);
1289 setTargetDAGCombine(ISD::FADD);
1290 setTargetDAGCombine(ISD::FSUB);
1291 setTargetDAGCombine(ISD::FMA);
1292 setTargetDAGCombine(ISD::SUB);
1293 setTargetDAGCombine(ISD::LOAD);
1294 setTargetDAGCombine(ISD::STORE);
1295 setTargetDAGCombine(ISD::ZERO_EXTEND);
1296 setTargetDAGCombine(ISD::ANY_EXTEND);
1297 setTargetDAGCombine(ISD::SIGN_EXTEND);
1298 setTargetDAGCombine(ISD::TRUNCATE);
1299 setTargetDAGCombine(ISD::SINT_TO_FP);
1300 setTargetDAGCombine(ISD::SETCC);
1301 if (Subtarget->is64Bit())
1302 setTargetDAGCombine(ISD::MUL);
1303 setTargetDAGCombine(ISD::XOR);
1305 computeRegisterProperties();
1307 // On Darwin, -Os means optimize for size without hurting performance,
1308 // do not reduce the limit.
1309 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1310 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1311 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1312 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1313 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1314 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1315 setPrefLoopAlignment(4); // 2^4 bytes.
1316 benefitFromCodePlacementOpt = true;
1318 // Predictable cmov don't hurt on atom because it's in-order.
1319 predictableSelectIsExpensive = !Subtarget->isAtom();
1321 setPrefFunctionAlignment(4); // 2^4 bytes.
1324 EVT X86TargetLowering::getSetCCResultType(EVT VT) const {
1325 if (!VT.isVector()) return MVT::i8;
1326 return VT.changeVectorElementTypeToInteger();
1329 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1330 /// the desired ByVal argument alignment.
1331 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1334 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1335 if (VTy->getBitWidth() == 128)
1337 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1338 unsigned EltAlign = 0;
1339 getMaxByValAlign(ATy->getElementType(), EltAlign);
1340 if (EltAlign > MaxAlign)
1341 MaxAlign = EltAlign;
1342 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1343 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1344 unsigned EltAlign = 0;
1345 getMaxByValAlign(STy->getElementType(i), EltAlign);
1346 if (EltAlign > MaxAlign)
1347 MaxAlign = EltAlign;
1354 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1355 /// function arguments in the caller parameter area. For X86, aggregates
1356 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1357 /// are at 4-byte boundaries.
1358 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1359 if (Subtarget->is64Bit()) {
1360 // Max of 8 and alignment of type.
1361 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1368 if (Subtarget->hasSSE1())
1369 getMaxByValAlign(Ty, Align);
1373 /// getOptimalMemOpType - Returns the target specific optimal type for load
1374 /// and store operations as a result of memset, memcpy, and memmove
1375 /// lowering. If DstAlign is zero that means it's safe to destination
1376 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1377 /// means there isn't a need to check it against alignment requirement,
1378 /// probably because the source does not need to be loaded. If 'IsMemset' is
1379 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1380 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1381 /// source is constant so it does not need to be loaded.
1382 /// It returns EVT::Other if the type should be determined using generic
1383 /// target-independent logic.
1385 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1386 unsigned DstAlign, unsigned SrcAlign,
1387 bool IsMemset, bool ZeroMemset,
1389 MachineFunction &MF) const {
1390 const Function *F = MF.getFunction();
1391 if ((!IsMemset || ZeroMemset) &&
1392 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1393 Attribute::NoImplicitFloat)) {
1395 (Subtarget->isUnalignedMemAccessFast() ||
1396 ((DstAlign == 0 || DstAlign >= 16) &&
1397 (SrcAlign == 0 || SrcAlign >= 16)))) {
1399 if (Subtarget->hasInt256())
1401 if (Subtarget->hasFp256())
1404 if (Subtarget->hasSSE2())
1406 if (Subtarget->hasSSE1())
1408 } else if (!MemcpyStrSrc && Size >= 8 &&
1409 !Subtarget->is64Bit() &&
1410 Subtarget->hasSSE2()) {
1411 // Do not use f64 to lower memcpy if source is string constant. It's
1412 // better to use i32 to avoid the loads.
1416 if (Subtarget->is64Bit() && Size >= 8)
1421 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1423 return X86ScalarSSEf32;
1424 else if (VT == MVT::f64)
1425 return X86ScalarSSEf64;
1430 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1432 *Fast = Subtarget->isUnalignedMemAccessFast();
1436 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1437 /// current function. The returned value is a member of the
1438 /// MachineJumpTableInfo::JTEntryKind enum.
1439 unsigned X86TargetLowering::getJumpTableEncoding() const {
1440 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1442 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1443 Subtarget->isPICStyleGOT())
1444 return MachineJumpTableInfo::EK_Custom32;
1446 // Otherwise, use the normal jump table encoding heuristics.
1447 return TargetLowering::getJumpTableEncoding();
1451 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1452 const MachineBasicBlock *MBB,
1453 unsigned uid,MCContext &Ctx) const{
1454 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1455 Subtarget->isPICStyleGOT());
1456 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1458 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1459 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1462 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1464 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1465 SelectionDAG &DAG) const {
1466 if (!Subtarget->is64Bit())
1467 // This doesn't have DebugLoc associated with it, but is not really the
1468 // same as a Register.
1469 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1473 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1474 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1476 const MCExpr *X86TargetLowering::
1477 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1478 MCContext &Ctx) const {
1479 // X86-64 uses RIP relative addressing based on the jump table label.
1480 if (Subtarget->isPICStyleRIPRel())
1481 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1483 // Otherwise, the reference is relative to the PIC base.
1484 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1487 // FIXME: Why this routine is here? Move to RegInfo!
1488 std::pair<const TargetRegisterClass*, uint8_t>
1489 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1490 const TargetRegisterClass *RRC = 0;
1492 switch (VT.SimpleTy) {
1494 return TargetLowering::findRepresentativeClass(VT);
1495 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1496 RRC = Subtarget->is64Bit() ?
1497 (const TargetRegisterClass*)&X86::GR64RegClass :
1498 (const TargetRegisterClass*)&X86::GR32RegClass;
1501 RRC = &X86::VR64RegClass;
1503 case MVT::f32: case MVT::f64:
1504 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1505 case MVT::v4f32: case MVT::v2f64:
1506 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1508 RRC = &X86::VR128RegClass;
1511 return std::make_pair(RRC, Cost);
1514 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1515 unsigned &Offset) const {
1516 if (!Subtarget->isTargetLinux())
1519 if (Subtarget->is64Bit()) {
1520 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1522 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1534 //===----------------------------------------------------------------------===//
1535 // Return Value Calling Convention Implementation
1536 //===----------------------------------------------------------------------===//
1538 #include "X86GenCallingConv.inc"
1541 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1542 MachineFunction &MF, bool isVarArg,
1543 const SmallVectorImpl<ISD::OutputArg> &Outs,
1544 LLVMContext &Context) const {
1545 SmallVector<CCValAssign, 16> RVLocs;
1546 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1548 return CCInfo.CheckReturn(Outs, RetCC_X86);
1552 X86TargetLowering::LowerReturn(SDValue Chain,
1553 CallingConv::ID CallConv, bool isVarArg,
1554 const SmallVectorImpl<ISD::OutputArg> &Outs,
1555 const SmallVectorImpl<SDValue> &OutVals,
1556 DebugLoc dl, SelectionDAG &DAG) const {
1557 MachineFunction &MF = DAG.getMachineFunction();
1558 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1560 SmallVector<CCValAssign, 16> RVLocs;
1561 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1562 RVLocs, *DAG.getContext());
1563 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1565 // Add the regs to the liveout set for the function.
1566 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1567 for (unsigned i = 0; i != RVLocs.size(); ++i)
1568 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg()))
1569 MRI.addLiveOut(RVLocs[i].getLocReg());
1573 SmallVector<SDValue, 6> RetOps;
1574 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1575 // Operand #1 = Bytes To Pop
1576 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1579 // Copy the result values into the output registers.
1580 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1581 CCValAssign &VA = RVLocs[i];
1582 assert(VA.isRegLoc() && "Can only return in registers!");
1583 SDValue ValToCopy = OutVals[i];
1584 EVT ValVT = ValToCopy.getValueType();
1586 // Promote values to the appropriate types
1587 if (VA.getLocInfo() == CCValAssign::SExt)
1588 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1589 else if (VA.getLocInfo() == CCValAssign::ZExt)
1590 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1591 else if (VA.getLocInfo() == CCValAssign::AExt)
1592 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1593 else if (VA.getLocInfo() == CCValAssign::BCvt)
1594 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1596 // If this is x86-64, and we disabled SSE, we can't return FP values,
1597 // or SSE or MMX vectors.
1598 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1599 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1600 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1601 report_fatal_error("SSE register return with SSE disabled");
1603 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1604 // llvm-gcc has never done it right and no one has noticed, so this
1605 // should be OK for now.
1606 if (ValVT == MVT::f64 &&
1607 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1608 report_fatal_error("SSE2 register return with SSE2 disabled");
1610 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1611 // the RET instruction and handled by the FP Stackifier.
1612 if (VA.getLocReg() == X86::ST0 ||
1613 VA.getLocReg() == X86::ST1) {
1614 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1615 // change the value to the FP stack register class.
1616 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1617 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1618 RetOps.push_back(ValToCopy);
1619 // Don't emit a copytoreg.
1623 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1624 // which is returned in RAX / RDX.
1625 if (Subtarget->is64Bit()) {
1626 if (ValVT == MVT::x86mmx) {
1627 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1628 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1629 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1631 // If we don't have SSE2 available, convert to v4f32 so the generated
1632 // register is legal.
1633 if (!Subtarget->hasSSE2())
1634 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1639 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1640 Flag = Chain.getValue(1);
1643 // The x86-64 ABI for returning structs by value requires that we copy
1644 // the sret argument into %rax for the return. We saved the argument into
1645 // a virtual register in the entry block, so now we copy the value out
1647 if (Subtarget->is64Bit() &&
1648 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1649 MachineFunction &MF = DAG.getMachineFunction();
1650 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1651 unsigned Reg = FuncInfo->getSRetReturnReg();
1653 "SRetReturnReg should have been set in LowerFormalArguments().");
1654 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1656 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1657 Flag = Chain.getValue(1);
1659 // RAX now acts like a return value.
1660 MRI.addLiveOut(X86::RAX);
1663 RetOps[0] = Chain; // Update chain.
1665 // Add the flag if we have it.
1667 RetOps.push_back(Flag);
1669 return DAG.getNode(X86ISD::RET_FLAG, dl,
1670 MVT::Other, &RetOps[0], RetOps.size());
1673 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1674 if (N->getNumValues() != 1)
1676 if (!N->hasNUsesOfValue(1, 0))
1679 SDValue TCChain = Chain;
1680 SDNode *Copy = *N->use_begin();
1681 if (Copy->getOpcode() == ISD::CopyToReg) {
1682 // If the copy has a glue operand, we conservatively assume it isn't safe to
1683 // perform a tail call.
1684 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1686 TCChain = Copy->getOperand(0);
1687 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1690 bool HasRet = false;
1691 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1693 if (UI->getOpcode() != X86ISD::RET_FLAG)
1706 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1707 ISD::NodeType ExtendKind) const {
1709 // TODO: Is this also valid on 32-bit?
1710 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1711 ReturnMVT = MVT::i8;
1713 ReturnMVT = MVT::i32;
1715 MVT MinVT = getRegisterType(ReturnMVT);
1716 return VT.bitsLT(MinVT) ? MinVT : VT;
1719 /// LowerCallResult - Lower the result values of a call into the
1720 /// appropriate copies out of appropriate physical registers.
1723 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1724 CallingConv::ID CallConv, bool isVarArg,
1725 const SmallVectorImpl<ISD::InputArg> &Ins,
1726 DebugLoc dl, SelectionDAG &DAG,
1727 SmallVectorImpl<SDValue> &InVals) const {
1729 // Assign locations to each value returned by this call.
1730 SmallVector<CCValAssign, 16> RVLocs;
1731 bool Is64Bit = Subtarget->is64Bit();
1732 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1733 getTargetMachine(), RVLocs, *DAG.getContext());
1734 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1736 // Copy all of the result registers out of their specified physreg.
1737 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1738 CCValAssign &VA = RVLocs[i];
1739 EVT CopyVT = VA.getValVT();
1741 // If this is x86-64, and we disabled SSE, we can't return FP values
1742 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1743 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1744 report_fatal_error("SSE register return with SSE disabled");
1749 // If this is a call to a function that returns an fp value on the floating
1750 // point stack, we must guarantee the value is popped from the stack, so
1751 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1752 // if the return value is not used. We use the FpPOP_RETVAL instruction
1754 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1755 // If we prefer to use the value in xmm registers, copy it out as f80 and
1756 // use a truncate to move it from fp stack reg to xmm reg.
1757 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1758 SDValue Ops[] = { Chain, InFlag };
1759 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1760 MVT::Other, MVT::Glue, Ops, 2), 1);
1761 Val = Chain.getValue(0);
1763 // Round the f80 to the right size, which also moves it to the appropriate
1765 if (CopyVT != VA.getValVT())
1766 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1767 // This truncation won't change the value.
1768 DAG.getIntPtrConstant(1));
1770 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1771 CopyVT, InFlag).getValue(1);
1772 Val = Chain.getValue(0);
1774 InFlag = Chain.getValue(2);
1775 InVals.push_back(Val);
1781 //===----------------------------------------------------------------------===//
1782 // C & StdCall & Fast Calling Convention implementation
1783 //===----------------------------------------------------------------------===//
1784 // StdCall calling convention seems to be standard for many Windows' API
1785 // routines and around. It differs from C calling convention just a little:
1786 // callee should clean up the stack, not caller. Symbols should be also
1787 // decorated in some fancy way :) It doesn't support any vector arguments.
1788 // For info on fast calling convention see Fast Calling Convention (tail call)
1789 // implementation LowerX86_32FastCCCallTo.
1791 /// CallIsStructReturn - Determines whether a call uses struct return
1793 enum StructReturnType {
1798 static StructReturnType
1799 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1801 return NotStructReturn;
1803 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1804 if (!Flags.isSRet())
1805 return NotStructReturn;
1806 if (Flags.isInReg())
1807 return RegStructReturn;
1808 return StackStructReturn;
1811 /// ArgsAreStructReturn - Determines whether a function uses struct
1812 /// return semantics.
1813 static StructReturnType
1814 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1816 return NotStructReturn;
1818 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1819 if (!Flags.isSRet())
1820 return NotStructReturn;
1821 if (Flags.isInReg())
1822 return RegStructReturn;
1823 return StackStructReturn;
1826 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1827 /// by "Src" to address "Dst" with size and alignment information specified by
1828 /// the specific parameter attribute. The copy will be passed as a byval
1829 /// function parameter.
1831 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1832 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1834 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1836 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1837 /*isVolatile*/false, /*AlwaysInline=*/true,
1838 MachinePointerInfo(), MachinePointerInfo());
1841 /// IsTailCallConvention - Return true if the calling convention is one that
1842 /// supports tail call optimization.
1843 static bool IsTailCallConvention(CallingConv::ID CC) {
1844 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1845 CC == CallingConv::HiPE);
1848 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1849 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1853 CallingConv::ID CalleeCC = CS.getCallingConv();
1854 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1860 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1861 /// a tailcall target by changing its ABI.
1862 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1863 bool GuaranteedTailCallOpt) {
1864 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1868 X86TargetLowering::LowerMemArgument(SDValue Chain,
1869 CallingConv::ID CallConv,
1870 const SmallVectorImpl<ISD::InputArg> &Ins,
1871 DebugLoc dl, SelectionDAG &DAG,
1872 const CCValAssign &VA,
1873 MachineFrameInfo *MFI,
1875 // Create the nodes corresponding to a load from this parameter slot.
1876 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1877 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1878 getTargetMachine().Options.GuaranteedTailCallOpt);
1879 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1882 // If value is passed by pointer we have address passed instead of the value
1884 if (VA.getLocInfo() == CCValAssign::Indirect)
1885 ValVT = VA.getLocVT();
1887 ValVT = VA.getValVT();
1889 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1890 // changed with more analysis.
1891 // In case of tail call optimization mark all arguments mutable. Since they
1892 // could be overwritten by lowering of arguments in case of a tail call.
1893 if (Flags.isByVal()) {
1894 unsigned Bytes = Flags.getByValSize();
1895 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1896 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1897 return DAG.getFrameIndex(FI, getPointerTy());
1899 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1900 VA.getLocMemOffset(), isImmutable);
1901 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1902 return DAG.getLoad(ValVT, dl, Chain, FIN,
1903 MachinePointerInfo::getFixedStack(FI),
1904 false, false, false, 0);
1909 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1910 CallingConv::ID CallConv,
1912 const SmallVectorImpl<ISD::InputArg> &Ins,
1915 SmallVectorImpl<SDValue> &InVals)
1917 MachineFunction &MF = DAG.getMachineFunction();
1918 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1920 const Function* Fn = MF.getFunction();
1921 if (Fn->hasExternalLinkage() &&
1922 Subtarget->isTargetCygMing() &&
1923 Fn->getName() == "main")
1924 FuncInfo->setForceFramePointer(true);
1926 MachineFrameInfo *MFI = MF.getFrameInfo();
1927 bool Is64Bit = Subtarget->is64Bit();
1928 bool IsWindows = Subtarget->isTargetWindows();
1929 bool IsWin64 = Subtarget->isTargetWin64();
1931 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1932 "Var args not supported with calling convention fastcc, ghc or hipe");
1934 // Assign locations to all of the incoming arguments.
1935 SmallVector<CCValAssign, 16> ArgLocs;
1936 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1937 ArgLocs, *DAG.getContext());
1939 // Allocate shadow area for Win64
1941 CCInfo.AllocateStack(32, 8);
1944 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1946 unsigned LastVal = ~0U;
1948 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1949 CCValAssign &VA = ArgLocs[i];
1950 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1952 assert(VA.getValNo() != LastVal &&
1953 "Don't support value assigned to multiple locs yet");
1955 LastVal = VA.getValNo();
1957 if (VA.isRegLoc()) {
1958 EVT RegVT = VA.getLocVT();
1959 const TargetRegisterClass *RC;
1960 if (RegVT == MVT::i32)
1961 RC = &X86::GR32RegClass;
1962 else if (Is64Bit && RegVT == MVT::i64)
1963 RC = &X86::GR64RegClass;
1964 else if (RegVT == MVT::f32)
1965 RC = &X86::FR32RegClass;
1966 else if (RegVT == MVT::f64)
1967 RC = &X86::FR64RegClass;
1968 else if (RegVT.is256BitVector())
1969 RC = &X86::VR256RegClass;
1970 else if (RegVT.is128BitVector())
1971 RC = &X86::VR128RegClass;
1972 else if (RegVT == MVT::x86mmx)
1973 RC = &X86::VR64RegClass;
1975 llvm_unreachable("Unknown argument type!");
1977 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1978 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1980 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1981 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1983 if (VA.getLocInfo() == CCValAssign::SExt)
1984 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1985 DAG.getValueType(VA.getValVT()));
1986 else if (VA.getLocInfo() == CCValAssign::ZExt)
1987 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1988 DAG.getValueType(VA.getValVT()));
1989 else if (VA.getLocInfo() == CCValAssign::BCvt)
1990 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
1992 if (VA.isExtInLoc()) {
1993 // Handle MMX values passed in XMM regs.
1994 if (RegVT.isVector())
1995 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
1997 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2000 assert(VA.isMemLoc());
2001 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2004 // If value is passed via pointer - do a load.
2005 if (VA.getLocInfo() == CCValAssign::Indirect)
2006 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2007 MachinePointerInfo(), false, false, false, 0);
2009 InVals.push_back(ArgValue);
2012 // The x86-64 ABI for returning structs by value requires that we copy
2013 // the sret argument into %rax for the return. Save the argument into
2014 // a virtual register so that we can access it from the return points.
2015 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
2016 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2017 unsigned Reg = FuncInfo->getSRetReturnReg();
2019 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
2020 FuncInfo->setSRetReturnReg(Reg);
2022 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2023 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2026 unsigned StackSize = CCInfo.getNextStackOffset();
2027 // Align stack specially for tail calls.
2028 if (FuncIsMadeTailCallSafe(CallConv,
2029 MF.getTarget().Options.GuaranteedTailCallOpt))
2030 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2032 // If the function takes variable number of arguments, make a frame index for
2033 // the start of the first vararg value... for expansion of llvm.va_start.
2035 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2036 CallConv != CallingConv::X86_ThisCall)) {
2037 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2040 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2042 // FIXME: We should really autogenerate these arrays
2043 static const uint16_t GPR64ArgRegsWin64[] = {
2044 X86::RCX, X86::RDX, X86::R8, X86::R9
2046 static const uint16_t GPR64ArgRegs64Bit[] = {
2047 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2049 static const uint16_t XMMArgRegs64Bit[] = {
2050 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2051 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2053 const uint16_t *GPR64ArgRegs;
2054 unsigned NumXMMRegs = 0;
2057 // The XMM registers which might contain var arg parameters are shadowed
2058 // in their paired GPR. So we only need to save the GPR to their home
2060 TotalNumIntRegs = 4;
2061 GPR64ArgRegs = GPR64ArgRegsWin64;
2063 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2064 GPR64ArgRegs = GPR64ArgRegs64Bit;
2066 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2069 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2072 bool NoImplicitFloatOps = Fn->getAttributes().
2073 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2074 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2075 "SSE register cannot be used when SSE is disabled!");
2076 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2077 NoImplicitFloatOps) &&
2078 "SSE register cannot be used when SSE is disabled!");
2079 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2080 !Subtarget->hasSSE1())
2081 // Kernel mode asks for SSE to be disabled, so don't push them
2083 TotalNumXMMRegs = 0;
2086 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2087 // Get to the caller-allocated home save location. Add 8 to account
2088 // for the return address.
2089 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2090 FuncInfo->setRegSaveFrameIndex(
2091 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2092 // Fixup to set vararg frame on shadow area (4 x i64).
2094 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2096 // For X86-64, if there are vararg parameters that are passed via
2097 // registers, then we must store them to their spots on the stack so
2098 // they may be loaded by deferencing the result of va_next.
2099 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2100 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2101 FuncInfo->setRegSaveFrameIndex(
2102 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2106 // Store the integer parameter registers.
2107 SmallVector<SDValue, 8> MemOps;
2108 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2110 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2111 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2112 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2113 DAG.getIntPtrConstant(Offset));
2114 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2115 &X86::GR64RegClass);
2116 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2118 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2119 MachinePointerInfo::getFixedStack(
2120 FuncInfo->getRegSaveFrameIndex(), Offset),
2122 MemOps.push_back(Store);
2126 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2127 // Now store the XMM (fp + vector) parameter registers.
2128 SmallVector<SDValue, 11> SaveXMMOps;
2129 SaveXMMOps.push_back(Chain);
2131 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2132 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2133 SaveXMMOps.push_back(ALVal);
2135 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2136 FuncInfo->getRegSaveFrameIndex()));
2137 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2138 FuncInfo->getVarArgsFPOffset()));
2140 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2141 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2142 &X86::VR128RegClass);
2143 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2144 SaveXMMOps.push_back(Val);
2146 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2148 &SaveXMMOps[0], SaveXMMOps.size()));
2151 if (!MemOps.empty())
2152 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2153 &MemOps[0], MemOps.size());
2157 // Some CCs need callee pop.
2158 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2159 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2160 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2162 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2163 // If this is an sret function, the return should pop the hidden pointer.
2164 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2165 argsAreStructReturn(Ins) == StackStructReturn)
2166 FuncInfo->setBytesToPopOnReturn(4);
2170 // RegSaveFrameIndex is X86-64 only.
2171 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2172 if (CallConv == CallingConv::X86_FastCall ||
2173 CallConv == CallingConv::X86_ThisCall)
2174 // fastcc functions can't have varargs.
2175 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2178 FuncInfo->setArgumentStackSize(StackSize);
2184 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2185 SDValue StackPtr, SDValue Arg,
2186 DebugLoc dl, SelectionDAG &DAG,
2187 const CCValAssign &VA,
2188 ISD::ArgFlagsTy Flags) const {
2189 unsigned LocMemOffset = VA.getLocMemOffset();
2190 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2191 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2192 if (Flags.isByVal())
2193 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2195 return DAG.getStore(Chain, dl, Arg, PtrOff,
2196 MachinePointerInfo::getStack(LocMemOffset),
2200 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2201 /// optimization is performed and it is required.
2203 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2204 SDValue &OutRetAddr, SDValue Chain,
2205 bool IsTailCall, bool Is64Bit,
2206 int FPDiff, DebugLoc dl) const {
2207 // Adjust the Return address stack slot.
2208 EVT VT = getPointerTy();
2209 OutRetAddr = getReturnAddressFrameIndex(DAG);
2211 // Load the "old" Return address.
2212 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2213 false, false, false, 0);
2214 return SDValue(OutRetAddr.getNode(), 1);
2217 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2218 /// optimization is performed and it is required (FPDiff!=0).
2220 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2221 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2222 unsigned SlotSize, int FPDiff, DebugLoc dl) {
2223 // Store the return address to the appropriate stack slot.
2224 if (!FPDiff) return Chain;
2225 // Calculate the new stack slot for the return address.
2226 int NewReturnAddrFI =
2227 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2228 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2229 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2230 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2236 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2237 SmallVectorImpl<SDValue> &InVals) const {
2238 SelectionDAG &DAG = CLI.DAG;
2239 DebugLoc &dl = CLI.DL;
2240 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2241 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2242 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2243 SDValue Chain = CLI.Chain;
2244 SDValue Callee = CLI.Callee;
2245 CallingConv::ID CallConv = CLI.CallConv;
2246 bool &isTailCall = CLI.IsTailCall;
2247 bool isVarArg = CLI.IsVarArg;
2249 MachineFunction &MF = DAG.getMachineFunction();
2250 bool Is64Bit = Subtarget->is64Bit();
2251 bool IsWin64 = Subtarget->isTargetWin64();
2252 bool IsWindows = Subtarget->isTargetWindows();
2253 StructReturnType SR = callIsStructReturn(Outs);
2254 bool IsSibcall = false;
2256 if (MF.getTarget().Options.DisableTailCalls)
2260 // Check if it's really possible to do a tail call.
2261 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2262 isVarArg, SR != NotStructReturn,
2263 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2264 Outs, OutVals, Ins, DAG);
2266 // Sibcalls are automatically detected tailcalls which do not require
2268 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2275 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2276 "Var args not supported with calling convention fastcc, ghc or hipe");
2278 // Analyze operands of the call, assigning locations to each operand.
2279 SmallVector<CCValAssign, 16> ArgLocs;
2280 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2281 ArgLocs, *DAG.getContext());
2283 // Allocate shadow area for Win64
2285 CCInfo.AllocateStack(32, 8);
2288 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2290 // Get a count of how many bytes are to be pushed on the stack.
2291 unsigned NumBytes = CCInfo.getNextStackOffset();
2293 // This is a sibcall. The memory operands are available in caller's
2294 // own caller's stack.
2296 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2297 IsTailCallConvention(CallConv))
2298 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2301 if (isTailCall && !IsSibcall) {
2302 // Lower arguments at fp - stackoffset + fpdiff.
2303 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2304 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2306 FPDiff = NumBytesCallerPushed - NumBytes;
2308 // Set the delta of movement of the returnaddr stackslot.
2309 // But only set if delta is greater than previous delta.
2310 if (FPDiff < X86Info->getTCReturnAddrDelta())
2311 X86Info->setTCReturnAddrDelta(FPDiff);
2315 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2317 SDValue RetAddrFrIdx;
2318 // Load return address for tail calls.
2319 if (isTailCall && FPDiff)
2320 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2321 Is64Bit, FPDiff, dl);
2323 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2324 SmallVector<SDValue, 8> MemOpChains;
2327 // Walk the register/memloc assignments, inserting copies/loads. In the case
2328 // of tail call optimization arguments are handle later.
2329 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2330 CCValAssign &VA = ArgLocs[i];
2331 EVT RegVT = VA.getLocVT();
2332 SDValue Arg = OutVals[i];
2333 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2334 bool isByVal = Flags.isByVal();
2336 // Promote the value if needed.
2337 switch (VA.getLocInfo()) {
2338 default: llvm_unreachable("Unknown loc info!");
2339 case CCValAssign::Full: break;
2340 case CCValAssign::SExt:
2341 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2343 case CCValAssign::ZExt:
2344 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2346 case CCValAssign::AExt:
2347 if (RegVT.is128BitVector()) {
2348 // Special case: passing MMX values in XMM registers.
2349 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2350 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2351 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2353 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2355 case CCValAssign::BCvt:
2356 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2358 case CCValAssign::Indirect: {
2359 // Store the argument.
2360 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2361 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2362 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2363 MachinePointerInfo::getFixedStack(FI),
2370 if (VA.isRegLoc()) {
2371 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2372 if (isVarArg && IsWin64) {
2373 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2374 // shadow reg if callee is a varargs function.
2375 unsigned ShadowReg = 0;
2376 switch (VA.getLocReg()) {
2377 case X86::XMM0: ShadowReg = X86::RCX; break;
2378 case X86::XMM1: ShadowReg = X86::RDX; break;
2379 case X86::XMM2: ShadowReg = X86::R8; break;
2380 case X86::XMM3: ShadowReg = X86::R9; break;
2383 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2385 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2386 assert(VA.isMemLoc());
2387 if (StackPtr.getNode() == 0)
2388 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2390 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2391 dl, DAG, VA, Flags));
2395 if (!MemOpChains.empty())
2396 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2397 &MemOpChains[0], MemOpChains.size());
2399 if (Subtarget->isPICStyleGOT()) {
2400 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2403 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2404 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2406 // If we are tail calling and generating PIC/GOT style code load the
2407 // address of the callee into ECX. The value in ecx is used as target of
2408 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2409 // for tail calls on PIC/GOT architectures. Normally we would just put the
2410 // address of GOT into ebx and then call target@PLT. But for tail calls
2411 // ebx would be restored (since ebx is callee saved) before jumping to the
2414 // Note: The actual moving to ECX is done further down.
2415 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2416 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2417 !G->getGlobal()->hasProtectedVisibility())
2418 Callee = LowerGlobalAddress(Callee, DAG);
2419 else if (isa<ExternalSymbolSDNode>(Callee))
2420 Callee = LowerExternalSymbol(Callee, DAG);
2424 if (Is64Bit && isVarArg && !IsWin64) {
2425 // From AMD64 ABI document:
2426 // For calls that may call functions that use varargs or stdargs
2427 // (prototype-less calls or calls to functions containing ellipsis (...) in
2428 // the declaration) %al is used as hidden argument to specify the number
2429 // of SSE registers used. The contents of %al do not need to match exactly
2430 // the number of registers, but must be an ubound on the number of SSE
2431 // registers used and is in the range 0 - 8 inclusive.
2433 // Count the number of XMM registers allocated.
2434 static const uint16_t XMMArgRegs[] = {
2435 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2436 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2438 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2439 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2440 && "SSE registers cannot be used when SSE is disabled");
2442 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2443 DAG.getConstant(NumXMMRegs, MVT::i8)));
2446 // For tail calls lower the arguments to the 'real' stack slot.
2448 // Force all the incoming stack arguments to be loaded from the stack
2449 // before any new outgoing arguments are stored to the stack, because the
2450 // outgoing stack slots may alias the incoming argument stack slots, and
2451 // the alias isn't otherwise explicit. This is slightly more conservative
2452 // than necessary, because it means that each store effectively depends
2453 // on every argument instead of just those arguments it would clobber.
2454 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2456 SmallVector<SDValue, 8> MemOpChains2;
2459 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2460 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2461 CCValAssign &VA = ArgLocs[i];
2464 assert(VA.isMemLoc());
2465 SDValue Arg = OutVals[i];
2466 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2467 // Create frame index.
2468 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2469 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2470 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2471 FIN = DAG.getFrameIndex(FI, getPointerTy());
2473 if (Flags.isByVal()) {
2474 // Copy relative to framepointer.
2475 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2476 if (StackPtr.getNode() == 0)
2477 StackPtr = DAG.getCopyFromReg(Chain, dl,
2478 RegInfo->getStackRegister(),
2480 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2482 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2486 // Store relative to framepointer.
2487 MemOpChains2.push_back(
2488 DAG.getStore(ArgChain, dl, Arg, FIN,
2489 MachinePointerInfo::getFixedStack(FI),
2495 if (!MemOpChains2.empty())
2496 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2497 &MemOpChains2[0], MemOpChains2.size());
2499 // Store the return address to the appropriate stack slot.
2500 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2501 getPointerTy(), RegInfo->getSlotSize(),
2505 // Build a sequence of copy-to-reg nodes chained together with token chain
2506 // and flag operands which copy the outgoing args into registers.
2508 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2509 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2510 RegsToPass[i].second, InFlag);
2511 InFlag = Chain.getValue(1);
2514 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2515 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2516 // In the 64-bit large code model, we have to make all calls
2517 // through a register, since the call instruction's 32-bit
2518 // pc-relative offset may not be large enough to hold the whole
2520 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2521 // If the callee is a GlobalAddress node (quite common, every direct call
2522 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2525 // We should use extra load for direct calls to dllimported functions in
2527 const GlobalValue *GV = G->getGlobal();
2528 if (!GV->hasDLLImportLinkage()) {
2529 unsigned char OpFlags = 0;
2530 bool ExtraLoad = false;
2531 unsigned WrapperKind = ISD::DELETED_NODE;
2533 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2534 // external symbols most go through the PLT in PIC mode. If the symbol
2535 // has hidden or protected visibility, or if it is static or local, then
2536 // we don't need to use the PLT - we can directly call it.
2537 if (Subtarget->isTargetELF() &&
2538 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2539 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2540 OpFlags = X86II::MO_PLT;
2541 } else if (Subtarget->isPICStyleStubAny() &&
2542 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2543 (!Subtarget->getTargetTriple().isMacOSX() ||
2544 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2545 // PC-relative references to external symbols should go through $stub,
2546 // unless we're building with the leopard linker or later, which
2547 // automatically synthesizes these stubs.
2548 OpFlags = X86II::MO_DARWIN_STUB;
2549 } else if (Subtarget->isPICStyleRIPRel() &&
2550 isa<Function>(GV) &&
2551 cast<Function>(GV)->getAttributes().
2552 hasAttribute(AttributeSet::FunctionIndex,
2553 Attribute::NonLazyBind)) {
2554 // If the function is marked as non-lazy, generate an indirect call
2555 // which loads from the GOT directly. This avoids runtime overhead
2556 // at the cost of eager binding (and one extra byte of encoding).
2557 OpFlags = X86II::MO_GOTPCREL;
2558 WrapperKind = X86ISD::WrapperRIP;
2562 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2563 G->getOffset(), OpFlags);
2565 // Add a wrapper if needed.
2566 if (WrapperKind != ISD::DELETED_NODE)
2567 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2568 // Add extra indirection if needed.
2570 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2571 MachinePointerInfo::getGOT(),
2572 false, false, false, 0);
2574 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2575 unsigned char OpFlags = 0;
2577 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2578 // external symbols should go through the PLT.
2579 if (Subtarget->isTargetELF() &&
2580 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2581 OpFlags = X86II::MO_PLT;
2582 } else if (Subtarget->isPICStyleStubAny() &&
2583 (!Subtarget->getTargetTriple().isMacOSX() ||
2584 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2585 // PC-relative references to external symbols should go through $stub,
2586 // unless we're building with the leopard linker or later, which
2587 // automatically synthesizes these stubs.
2588 OpFlags = X86II::MO_DARWIN_STUB;
2591 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2595 // Returns a chain & a flag for retval copy to use.
2596 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2597 SmallVector<SDValue, 8> Ops;
2599 if (!IsSibcall && isTailCall) {
2600 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2601 DAG.getIntPtrConstant(0, true), InFlag);
2602 InFlag = Chain.getValue(1);
2605 Ops.push_back(Chain);
2606 Ops.push_back(Callee);
2609 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2611 // Add argument registers to the end of the list so that they are known live
2613 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2614 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2615 RegsToPass[i].second.getValueType()));
2617 // Add a register mask operand representing the call-preserved registers.
2618 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2619 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2620 assert(Mask && "Missing call preserved mask for calling convention");
2621 Ops.push_back(DAG.getRegisterMask(Mask));
2623 if (InFlag.getNode())
2624 Ops.push_back(InFlag);
2628 //// If this is the first return lowered for this function, add the regs
2629 //// to the liveout set for the function.
2630 // This isn't right, although it's probably harmless on x86; liveouts
2631 // should be computed from returns not tail calls. Consider a void
2632 // function making a tail call to a function returning int.
2633 return DAG.getNode(X86ISD::TC_RETURN, dl,
2634 NodeTys, &Ops[0], Ops.size());
2637 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2638 InFlag = Chain.getValue(1);
2640 // Create the CALLSEQ_END node.
2641 unsigned NumBytesForCalleeToPush;
2642 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2643 getTargetMachine().Options.GuaranteedTailCallOpt))
2644 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2645 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2646 SR == StackStructReturn)
2647 // If this is a call to a struct-return function, the callee
2648 // pops the hidden struct pointer, so we have to push it back.
2649 // This is common for Darwin/X86, Linux & Mingw32 targets.
2650 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2651 NumBytesForCalleeToPush = 4;
2653 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2655 // Returns a flag for retval copy to use.
2657 Chain = DAG.getCALLSEQ_END(Chain,
2658 DAG.getIntPtrConstant(NumBytes, true),
2659 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2662 InFlag = Chain.getValue(1);
2665 // Handle result values, copying them out of physregs into vregs that we
2667 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2668 Ins, dl, DAG, InVals);
2671 //===----------------------------------------------------------------------===//
2672 // Fast Calling Convention (tail call) implementation
2673 //===----------------------------------------------------------------------===//
2675 // Like std call, callee cleans arguments, convention except that ECX is
2676 // reserved for storing the tail called function address. Only 2 registers are
2677 // free for argument passing (inreg). Tail call optimization is performed
2679 // * tailcallopt is enabled
2680 // * caller/callee are fastcc
2681 // On X86_64 architecture with GOT-style position independent code only local
2682 // (within module) calls are supported at the moment.
2683 // To keep the stack aligned according to platform abi the function
2684 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2685 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2686 // If a tail called function callee has more arguments than the caller the
2687 // caller needs to make sure that there is room to move the RETADDR to. This is
2688 // achieved by reserving an area the size of the argument delta right after the
2689 // original REtADDR, but before the saved framepointer or the spilled registers
2690 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2702 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2703 /// for a 16 byte align requirement.
2705 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2706 SelectionDAG& DAG) const {
2707 MachineFunction &MF = DAG.getMachineFunction();
2708 const TargetMachine &TM = MF.getTarget();
2709 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2710 unsigned StackAlignment = TFI.getStackAlignment();
2711 uint64_t AlignMask = StackAlignment - 1;
2712 int64_t Offset = StackSize;
2713 unsigned SlotSize = RegInfo->getSlotSize();
2714 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2715 // Number smaller than 12 so just add the difference.
2716 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2718 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2719 Offset = ((~AlignMask) & Offset) + StackAlignment +
2720 (StackAlignment-SlotSize);
2725 /// MatchingStackOffset - Return true if the given stack call argument is
2726 /// already available in the same position (relatively) of the caller's
2727 /// incoming argument stack.
2729 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2730 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2731 const X86InstrInfo *TII) {
2732 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2734 if (Arg.getOpcode() == ISD::CopyFromReg) {
2735 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2736 if (!TargetRegisterInfo::isVirtualRegister(VR))
2738 MachineInstr *Def = MRI->getVRegDef(VR);
2741 if (!Flags.isByVal()) {
2742 if (!TII->isLoadFromStackSlot(Def, FI))
2745 unsigned Opcode = Def->getOpcode();
2746 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2747 Def->getOperand(1).isFI()) {
2748 FI = Def->getOperand(1).getIndex();
2749 Bytes = Flags.getByValSize();
2753 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2754 if (Flags.isByVal())
2755 // ByVal argument is passed in as a pointer but it's now being
2756 // dereferenced. e.g.
2757 // define @foo(%struct.X* %A) {
2758 // tail call @bar(%struct.X* byval %A)
2761 SDValue Ptr = Ld->getBasePtr();
2762 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2765 FI = FINode->getIndex();
2766 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2767 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2768 FI = FINode->getIndex();
2769 Bytes = Flags.getByValSize();
2773 assert(FI != INT_MAX);
2774 if (!MFI->isFixedObjectIndex(FI))
2776 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2779 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2780 /// for tail call optimization. Targets which want to do tail call
2781 /// optimization should implement this function.
2783 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2784 CallingConv::ID CalleeCC,
2786 bool isCalleeStructRet,
2787 bool isCallerStructRet,
2789 const SmallVectorImpl<ISD::OutputArg> &Outs,
2790 const SmallVectorImpl<SDValue> &OutVals,
2791 const SmallVectorImpl<ISD::InputArg> &Ins,
2792 SelectionDAG& DAG) const {
2793 if (!IsTailCallConvention(CalleeCC) &&
2794 CalleeCC != CallingConv::C)
2797 // If -tailcallopt is specified, make fastcc functions tail-callable.
2798 const MachineFunction &MF = DAG.getMachineFunction();
2799 const Function *CallerF = DAG.getMachineFunction().getFunction();
2801 // If the function return type is x86_fp80 and the callee return type is not,
2802 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2803 // perform a tailcall optimization here.
2804 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
2807 CallingConv::ID CallerCC = CallerF->getCallingConv();
2808 bool CCMatch = CallerCC == CalleeCC;
2810 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2811 if (IsTailCallConvention(CalleeCC) && CCMatch)
2816 // Look for obvious safe cases to perform tail call optimization that do not
2817 // require ABI changes. This is what gcc calls sibcall.
2819 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2820 // emit a special epilogue.
2821 if (RegInfo->needsStackRealignment(MF))
2824 // Also avoid sibcall optimization if either caller or callee uses struct
2825 // return semantics.
2826 if (isCalleeStructRet || isCallerStructRet)
2829 // An stdcall caller is expected to clean up its arguments; the callee
2830 // isn't going to do that.
2831 if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
2834 // Do not sibcall optimize vararg calls unless all arguments are passed via
2836 if (isVarArg && !Outs.empty()) {
2838 // Optimizing for varargs on Win64 is unlikely to be safe without
2839 // additional testing.
2840 if (Subtarget->isTargetWin64())
2843 SmallVector<CCValAssign, 16> ArgLocs;
2844 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2845 getTargetMachine(), ArgLocs, *DAG.getContext());
2847 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2848 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2849 if (!ArgLocs[i].isRegLoc())
2853 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2854 // stack. Therefore, if it's not used by the call it is not safe to optimize
2855 // this into a sibcall.
2856 bool Unused = false;
2857 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2864 SmallVector<CCValAssign, 16> RVLocs;
2865 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2866 getTargetMachine(), RVLocs, *DAG.getContext());
2867 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2868 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2869 CCValAssign &VA = RVLocs[i];
2870 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2875 // If the calling conventions do not match, then we'd better make sure the
2876 // results are returned in the same way as what the caller expects.
2878 SmallVector<CCValAssign, 16> RVLocs1;
2879 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2880 getTargetMachine(), RVLocs1, *DAG.getContext());
2881 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2883 SmallVector<CCValAssign, 16> RVLocs2;
2884 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2885 getTargetMachine(), RVLocs2, *DAG.getContext());
2886 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2888 if (RVLocs1.size() != RVLocs2.size())
2890 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2891 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2893 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2895 if (RVLocs1[i].isRegLoc()) {
2896 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2899 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2905 // If the callee takes no arguments then go on to check the results of the
2907 if (!Outs.empty()) {
2908 // Check if stack adjustment is needed. For now, do not do this if any
2909 // argument is passed on the stack.
2910 SmallVector<CCValAssign, 16> ArgLocs;
2911 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2912 getTargetMachine(), ArgLocs, *DAG.getContext());
2914 // Allocate shadow area for Win64
2915 if (Subtarget->isTargetWin64()) {
2916 CCInfo.AllocateStack(32, 8);
2919 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2920 if (CCInfo.getNextStackOffset()) {
2921 MachineFunction &MF = DAG.getMachineFunction();
2922 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2925 // Check if the arguments are already laid out in the right way as
2926 // the caller's fixed stack objects.
2927 MachineFrameInfo *MFI = MF.getFrameInfo();
2928 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2929 const X86InstrInfo *TII =
2930 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
2931 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2932 CCValAssign &VA = ArgLocs[i];
2933 SDValue Arg = OutVals[i];
2934 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2935 if (VA.getLocInfo() == CCValAssign::Indirect)
2937 if (!VA.isRegLoc()) {
2938 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2945 // If the tailcall address may be in a register, then make sure it's
2946 // possible to register allocate for it. In 32-bit, the call address can
2947 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2948 // callee-saved registers are restored. These happen to be the same
2949 // registers used to pass 'inreg' arguments so watch out for those.
2950 if (!Subtarget->is64Bit() &&
2951 !isa<GlobalAddressSDNode>(Callee) &&
2952 !isa<ExternalSymbolSDNode>(Callee)) {
2953 unsigned NumInRegs = 0;
2954 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2955 CCValAssign &VA = ArgLocs[i];
2958 unsigned Reg = VA.getLocReg();
2961 case X86::EAX: case X86::EDX: case X86::ECX:
2962 if (++NumInRegs == 3)
2974 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
2975 const TargetLibraryInfo *libInfo) const {
2976 return X86::createFastISel(funcInfo, libInfo);
2979 //===----------------------------------------------------------------------===//
2980 // Other Lowering Hooks
2981 //===----------------------------------------------------------------------===//
2983 static bool MayFoldLoad(SDValue Op) {
2984 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
2987 static bool MayFoldIntoStore(SDValue Op) {
2988 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
2991 static bool isTargetShuffle(unsigned Opcode) {
2993 default: return false;
2994 case X86ISD::PSHUFD:
2995 case X86ISD::PSHUFHW:
2996 case X86ISD::PSHUFLW:
2998 case X86ISD::PALIGN:
2999 case X86ISD::MOVLHPS:
3000 case X86ISD::MOVLHPD:
3001 case X86ISD::MOVHLPS:
3002 case X86ISD::MOVLPS:
3003 case X86ISD::MOVLPD:
3004 case X86ISD::MOVSHDUP:
3005 case X86ISD::MOVSLDUP:
3006 case X86ISD::MOVDDUP:
3009 case X86ISD::UNPCKL:
3010 case X86ISD::UNPCKH:
3011 case X86ISD::VPERMILP:
3012 case X86ISD::VPERM2X128:
3013 case X86ISD::VPERMI:
3018 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3019 SDValue V1, SelectionDAG &DAG) {
3021 default: llvm_unreachable("Unknown x86 shuffle node");
3022 case X86ISD::MOVSHDUP:
3023 case X86ISD::MOVSLDUP:
3024 case X86ISD::MOVDDUP:
3025 return DAG.getNode(Opc, dl, VT, V1);
3029 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3030 SDValue V1, unsigned TargetMask,
3031 SelectionDAG &DAG) {
3033 default: llvm_unreachable("Unknown x86 shuffle node");
3034 case X86ISD::PSHUFD:
3035 case X86ISD::PSHUFHW:
3036 case X86ISD::PSHUFLW:
3037 case X86ISD::VPERMILP:
3038 case X86ISD::VPERMI:
3039 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3043 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3044 SDValue V1, SDValue V2, unsigned TargetMask,
3045 SelectionDAG &DAG) {
3047 default: llvm_unreachable("Unknown x86 shuffle node");
3048 case X86ISD::PALIGN:
3050 case X86ISD::VPERM2X128:
3051 return DAG.getNode(Opc, dl, VT, V1, V2,
3052 DAG.getConstant(TargetMask, MVT::i8));
3056 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3057 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3059 default: llvm_unreachable("Unknown x86 shuffle node");
3060 case X86ISD::MOVLHPS:
3061 case X86ISD::MOVLHPD:
3062 case X86ISD::MOVHLPS:
3063 case X86ISD::MOVLPS:
3064 case X86ISD::MOVLPD:
3067 case X86ISD::UNPCKL:
3068 case X86ISD::UNPCKH:
3069 return DAG.getNode(Opc, dl, VT, V1, V2);
3073 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3074 MachineFunction &MF = DAG.getMachineFunction();
3075 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3076 int ReturnAddrIndex = FuncInfo->getRAIndex();
3078 if (ReturnAddrIndex == 0) {
3079 // Set up a frame object for the return address.
3080 unsigned SlotSize = RegInfo->getSlotSize();
3081 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3083 FuncInfo->setRAIndex(ReturnAddrIndex);
3086 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3089 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3090 bool hasSymbolicDisplacement) {
3091 // Offset should fit into 32 bit immediate field.
3092 if (!isInt<32>(Offset))
3095 // If we don't have a symbolic displacement - we don't have any extra
3097 if (!hasSymbolicDisplacement)
3100 // FIXME: Some tweaks might be needed for medium code model.
3101 if (M != CodeModel::Small && M != CodeModel::Kernel)
3104 // For small code model we assume that latest object is 16MB before end of 31
3105 // bits boundary. We may also accept pretty large negative constants knowing
3106 // that all objects are in the positive half of address space.
3107 if (M == CodeModel::Small && Offset < 16*1024*1024)
3110 // For kernel code model we know that all object resist in the negative half
3111 // of 32bits address space. We may not accept negative offsets, since they may
3112 // be just off and we may accept pretty large positive ones.
3113 if (M == CodeModel::Kernel && Offset > 0)
3119 /// isCalleePop - Determines whether the callee is required to pop its
3120 /// own arguments. Callee pop is necessary to support tail calls.
3121 bool X86::isCalleePop(CallingConv::ID CallingConv,
3122 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3126 switch (CallingConv) {
3129 case CallingConv::X86_StdCall:
3131 case CallingConv::X86_FastCall:
3133 case CallingConv::X86_ThisCall:
3135 case CallingConv::Fast:
3137 case CallingConv::GHC:
3139 case CallingConv::HiPE:
3144 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3145 /// specific condition code, returning the condition code and the LHS/RHS of the
3146 /// comparison to make.
3147 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3148 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3150 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3151 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3152 // X > -1 -> X == 0, jump !sign.
3153 RHS = DAG.getConstant(0, RHS.getValueType());
3154 return X86::COND_NS;
3156 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3157 // X < 0 -> X == 0, jump on sign.
3160 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3162 RHS = DAG.getConstant(0, RHS.getValueType());
3163 return X86::COND_LE;
3167 switch (SetCCOpcode) {
3168 default: llvm_unreachable("Invalid integer condition!");
3169 case ISD::SETEQ: return X86::COND_E;
3170 case ISD::SETGT: return X86::COND_G;
3171 case ISD::SETGE: return X86::COND_GE;
3172 case ISD::SETLT: return X86::COND_L;
3173 case ISD::SETLE: return X86::COND_LE;
3174 case ISD::SETNE: return X86::COND_NE;
3175 case ISD::SETULT: return X86::COND_B;
3176 case ISD::SETUGT: return X86::COND_A;
3177 case ISD::SETULE: return X86::COND_BE;
3178 case ISD::SETUGE: return X86::COND_AE;
3182 // First determine if it is required or is profitable to flip the operands.
3184 // If LHS is a foldable load, but RHS is not, flip the condition.
3185 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3186 !ISD::isNON_EXTLoad(RHS.getNode())) {
3187 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3188 std::swap(LHS, RHS);
3191 switch (SetCCOpcode) {
3197 std::swap(LHS, RHS);
3201 // On a floating point condition, the flags are set as follows:
3203 // 0 | 0 | 0 | X > Y
3204 // 0 | 0 | 1 | X < Y
3205 // 1 | 0 | 0 | X == Y
3206 // 1 | 1 | 1 | unordered
3207 switch (SetCCOpcode) {
3208 default: llvm_unreachable("Condcode should be pre-legalized away");
3210 case ISD::SETEQ: return X86::COND_E;
3211 case ISD::SETOLT: // flipped
3213 case ISD::SETGT: return X86::COND_A;
3214 case ISD::SETOLE: // flipped
3216 case ISD::SETGE: return X86::COND_AE;
3217 case ISD::SETUGT: // flipped
3219 case ISD::SETLT: return X86::COND_B;
3220 case ISD::SETUGE: // flipped
3222 case ISD::SETLE: return X86::COND_BE;
3224 case ISD::SETNE: return X86::COND_NE;
3225 case ISD::SETUO: return X86::COND_P;
3226 case ISD::SETO: return X86::COND_NP;
3228 case ISD::SETUNE: return X86::COND_INVALID;
3232 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3233 /// code. Current x86 isa includes the following FP cmov instructions:
3234 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3235 static bool hasFPCMov(unsigned X86CC) {
3251 /// isFPImmLegal - Returns true if the target can instruction select the
3252 /// specified FP immediate natively. If false, the legalizer will
3253 /// materialize the FP immediate as a load from a constant pool.
3254 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3255 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3256 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3262 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3263 /// the specified range (L, H].
3264 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3265 return (Val < 0) || (Val >= Low && Val < Hi);
3268 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3269 /// specified value.
3270 static bool isUndefOrEqual(int Val, int CmpVal) {
3271 return (Val < 0 || Val == CmpVal);
3274 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3275 /// from position Pos and ending in Pos+Size, falls within the specified
3276 /// sequential range (L, L+Pos]. or is undef.
3277 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3278 unsigned Pos, unsigned Size, int Low) {
3279 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3280 if (!isUndefOrEqual(Mask[i], Low))
3285 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3286 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3287 /// the second operand.
3288 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3289 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3290 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3291 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3292 return (Mask[0] < 2 && Mask[1] < 2);
3296 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3297 /// is suitable for input to PSHUFHW.
3298 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3299 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3302 // Lower quadword copied in order or undef.
3303 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3306 // Upper quadword shuffled.
3307 for (unsigned i = 4; i != 8; ++i)
3308 if (!isUndefOrInRange(Mask[i], 4, 8))
3311 if (VT == MVT::v16i16) {
3312 // Lower quadword copied in order or undef.
3313 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3316 // Upper quadword shuffled.
3317 for (unsigned i = 12; i != 16; ++i)
3318 if (!isUndefOrInRange(Mask[i], 12, 16))
3325 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3326 /// is suitable for input to PSHUFLW.
3327 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3328 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3331 // Upper quadword copied in order.
3332 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3335 // Lower quadword shuffled.
3336 for (unsigned i = 0; i != 4; ++i)
3337 if (!isUndefOrInRange(Mask[i], 0, 4))
3340 if (VT == MVT::v16i16) {
3341 // Upper quadword copied in order.
3342 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3345 // Lower quadword shuffled.
3346 for (unsigned i = 8; i != 12; ++i)
3347 if (!isUndefOrInRange(Mask[i], 8, 12))
3354 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3355 /// is suitable for input to PALIGNR.
3356 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3357 const X86Subtarget *Subtarget) {
3358 if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
3359 (VT.getSizeInBits() == 256 && !Subtarget->hasInt256()))
3362 unsigned NumElts = VT.getVectorNumElements();
3363 unsigned NumLanes = VT.getSizeInBits()/128;
3364 unsigned NumLaneElts = NumElts/NumLanes;
3366 // Do not handle 64-bit element shuffles with palignr.
3367 if (NumLaneElts == 2)
3370 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3372 for (i = 0; i != NumLaneElts; ++i) {
3377 // Lane is all undef, go to next lane
3378 if (i == NumLaneElts)
3381 int Start = Mask[i+l];
3383 // Make sure its in this lane in one of the sources
3384 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3385 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3388 // If not lane 0, then we must match lane 0
3389 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3392 // Correct second source to be contiguous with first source
3393 if (Start >= (int)NumElts)
3394 Start -= NumElts - NumLaneElts;
3396 // Make sure we're shifting in the right direction.
3397 if (Start <= (int)(i+l))
3402 // Check the rest of the elements to see if they are consecutive.
3403 for (++i; i != NumLaneElts; ++i) {
3404 int Idx = Mask[i+l];
3406 // Make sure its in this lane
3407 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3408 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3411 // If not lane 0, then we must match lane 0
3412 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3415 if (Idx >= (int)NumElts)
3416 Idx -= NumElts - NumLaneElts;
3418 if (!isUndefOrEqual(Idx, Start+i))
3427 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3428 /// the two vector operands have swapped position.
3429 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3430 unsigned NumElems) {
3431 for (unsigned i = 0; i != NumElems; ++i) {
3435 else if (idx < (int)NumElems)
3436 Mask[i] = idx + NumElems;
3438 Mask[i] = idx - NumElems;
3442 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3443 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3444 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3445 /// reverse of what x86 shuffles want.
3446 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
3447 bool Commuted = false) {
3448 if (!HasFp256 && VT.getSizeInBits() == 256)
3451 unsigned NumElems = VT.getVectorNumElements();
3452 unsigned NumLanes = VT.getSizeInBits()/128;
3453 unsigned NumLaneElems = NumElems/NumLanes;
3455 if (NumLaneElems != 2 && NumLaneElems != 4)
3458 // VSHUFPSY divides the resulting vector into 4 chunks.
3459 // The sources are also splitted into 4 chunks, and each destination
3460 // chunk must come from a different source chunk.
3462 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3463 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3465 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3466 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3468 // VSHUFPDY divides the resulting vector into 4 chunks.
3469 // The sources are also splitted into 4 chunks, and each destination
3470 // chunk must come from a different source chunk.
3472 // SRC1 => X3 X2 X1 X0
3473 // SRC2 => Y3 Y2 Y1 Y0
3475 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3477 unsigned HalfLaneElems = NumLaneElems/2;
3478 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3479 for (unsigned i = 0; i != NumLaneElems; ++i) {
3480 int Idx = Mask[i+l];
3481 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3482 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3484 // For VSHUFPSY, the mask of the second half must be the same as the
3485 // first but with the appropriate offsets. This works in the same way as
3486 // VPERMILPS works with masks.
3487 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3489 if (!isUndefOrEqual(Idx, Mask[i]+l))
3497 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3498 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3499 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3500 if (!VT.is128BitVector())
3503 unsigned NumElems = VT.getVectorNumElements();
3508 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3509 return isUndefOrEqual(Mask[0], 6) &&
3510 isUndefOrEqual(Mask[1], 7) &&
3511 isUndefOrEqual(Mask[2], 2) &&
3512 isUndefOrEqual(Mask[3], 3);
3515 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3516 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3518 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3519 if (!VT.is128BitVector())
3522 unsigned NumElems = VT.getVectorNumElements();
3527 return isUndefOrEqual(Mask[0], 2) &&
3528 isUndefOrEqual(Mask[1], 3) &&
3529 isUndefOrEqual(Mask[2], 2) &&
3530 isUndefOrEqual(Mask[3], 3);
3533 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3534 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3535 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3536 if (!VT.is128BitVector())
3539 unsigned NumElems = VT.getVectorNumElements();
3541 if (NumElems != 2 && NumElems != 4)
3544 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3545 if (!isUndefOrEqual(Mask[i], i + NumElems))
3548 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3549 if (!isUndefOrEqual(Mask[i], i))
3555 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3556 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3557 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3558 if (!VT.is128BitVector())
3561 unsigned NumElems = VT.getVectorNumElements();
3563 if (NumElems != 2 && NumElems != 4)
3566 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3567 if (!isUndefOrEqual(Mask[i], i))
3570 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3571 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3578 // Some special combinations that can be optimized.
3581 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3582 SelectionDAG &DAG) {
3583 EVT VT = SVOp->getValueType(0);
3584 DebugLoc dl = SVOp->getDebugLoc();
3586 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3589 ArrayRef<int> Mask = SVOp->getMask();
3591 // These are the special masks that may be optimized.
3592 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3593 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3594 bool MatchEvenMask = true;
3595 bool MatchOddMask = true;
3596 for (int i=0; i<8; ++i) {
3597 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3598 MatchEvenMask = false;
3599 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3600 MatchOddMask = false;
3603 if (!MatchEvenMask && !MatchOddMask)
3606 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3608 SDValue Op0 = SVOp->getOperand(0);
3609 SDValue Op1 = SVOp->getOperand(1);
3611 if (MatchEvenMask) {
3612 // Shift the second operand right to 32 bits.
3613 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3614 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3616 // Shift the first operand left to 32 bits.
3617 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3618 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3620 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3621 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3624 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3625 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3626 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3627 bool HasInt256, bool V2IsSplat = false) {
3628 unsigned NumElts = VT.getVectorNumElements();
3630 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3631 "Unsupported vector type for unpckh");
3633 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3634 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3637 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3638 // independently on 128-bit lanes.
3639 unsigned NumLanes = VT.getSizeInBits()/128;
3640 unsigned NumLaneElts = NumElts/NumLanes;
3642 for (unsigned l = 0; l != NumLanes; ++l) {
3643 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3644 i != (l+1)*NumLaneElts;
3647 int BitI1 = Mask[i+1];
3648 if (!isUndefOrEqual(BitI, j))
3651 if (!isUndefOrEqual(BitI1, NumElts))
3654 if (!isUndefOrEqual(BitI1, j + NumElts))
3663 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3664 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3665 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3666 bool HasInt256, bool V2IsSplat = false) {
3667 unsigned NumElts = VT.getVectorNumElements();
3669 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3670 "Unsupported vector type for unpckh");
3672 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3673 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3676 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3677 // independently on 128-bit lanes.
3678 unsigned NumLanes = VT.getSizeInBits()/128;
3679 unsigned NumLaneElts = NumElts/NumLanes;
3681 for (unsigned l = 0; l != NumLanes; ++l) {
3682 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3683 i != (l+1)*NumLaneElts; i += 2, ++j) {
3685 int BitI1 = Mask[i+1];
3686 if (!isUndefOrEqual(BitI, j))
3689 if (isUndefOrEqual(BitI1, NumElts))
3692 if (!isUndefOrEqual(BitI1, j+NumElts))
3700 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3701 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3703 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT,
3705 unsigned NumElts = VT.getVectorNumElements();
3707 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3708 "Unsupported vector type for unpckh");
3710 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3711 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3714 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3715 // FIXME: Need a better way to get rid of this, there's no latency difference
3716 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3717 // the former later. We should also remove the "_undef" special mask.
3718 if (NumElts == 4 && VT.getSizeInBits() == 256)
3721 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3722 // independently on 128-bit lanes.
3723 unsigned NumLanes = VT.getSizeInBits()/128;
3724 unsigned NumLaneElts = NumElts/NumLanes;
3726 for (unsigned l = 0; l != NumLanes; ++l) {
3727 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3728 i != (l+1)*NumLaneElts;
3731 int BitI1 = Mask[i+1];
3733 if (!isUndefOrEqual(BitI, j))
3735 if (!isUndefOrEqual(BitI1, j))
3743 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3744 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3746 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3747 unsigned NumElts = VT.getVectorNumElements();
3749 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3750 "Unsupported vector type for unpckh");
3752 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8 &&
3753 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3756 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3757 // independently on 128-bit lanes.
3758 unsigned NumLanes = VT.getSizeInBits()/128;
3759 unsigned NumLaneElts = NumElts/NumLanes;
3761 for (unsigned l = 0; l != NumLanes; ++l) {
3762 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3763 i != (l+1)*NumLaneElts; i += 2, ++j) {
3765 int BitI1 = Mask[i+1];
3766 if (!isUndefOrEqual(BitI, j))
3768 if (!isUndefOrEqual(BitI1, j))
3775 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3776 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3777 /// MOVSD, and MOVD, i.e. setting the lowest element.
3778 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3779 if (VT.getVectorElementType().getSizeInBits() < 32)
3781 if (!VT.is128BitVector())
3784 unsigned NumElts = VT.getVectorNumElements();
3786 if (!isUndefOrEqual(Mask[0], NumElts))
3789 for (unsigned i = 1; i != NumElts; ++i)
3790 if (!isUndefOrEqual(Mask[i], i))
3796 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3797 /// as permutations between 128-bit chunks or halves. As an example: this
3799 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3800 /// The first half comes from the second half of V1 and the second half from the
3801 /// the second half of V2.
3802 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3803 if (!HasFp256 || !VT.is256BitVector())
3806 // The shuffle result is divided into half A and half B. In total the two
3807 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3808 // B must come from C, D, E or F.
3809 unsigned HalfSize = VT.getVectorNumElements()/2;
3810 bool MatchA = false, MatchB = false;
3812 // Check if A comes from one of C, D, E, F.
3813 for (unsigned Half = 0; Half != 4; ++Half) {
3814 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3820 // Check if B comes from one of C, D, E, F.
3821 for (unsigned Half = 0; Half != 4; ++Half) {
3822 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3828 return MatchA && MatchB;
3831 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3832 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3833 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3834 EVT VT = SVOp->getValueType(0);
3836 unsigned HalfSize = VT.getVectorNumElements()/2;
3838 unsigned FstHalf = 0, SndHalf = 0;
3839 for (unsigned i = 0; i < HalfSize; ++i) {
3840 if (SVOp->getMaskElt(i) > 0) {
3841 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3845 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3846 if (SVOp->getMaskElt(i) > 0) {
3847 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3852 return (FstHalf | (SndHalf << 4));
3855 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3856 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3857 /// Note that VPERMIL mask matching is different depending whether theunderlying
3858 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3859 /// to the same elements of the low, but to the higher half of the source.
3860 /// In VPERMILPD the two lanes could be shuffled independently of each other
3861 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3862 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3866 unsigned NumElts = VT.getVectorNumElements();
3867 // Only match 256-bit with 32/64-bit types
3868 if (VT.getSizeInBits() != 256 || (NumElts != 4 && NumElts != 8))
3871 unsigned NumLanes = VT.getSizeInBits()/128;
3872 unsigned LaneSize = NumElts/NumLanes;
3873 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3874 for (unsigned i = 0; i != LaneSize; ++i) {
3875 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3877 if (NumElts != 8 || l == 0)
3879 // VPERMILPS handling
3882 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3890 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3891 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3892 /// element of vector 2 and the other elements to come from vector 1 in order.
3893 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3894 bool V2IsSplat = false, bool V2IsUndef = false) {
3895 if (!VT.is128BitVector())
3898 unsigned NumOps = VT.getVectorNumElements();
3899 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3902 if (!isUndefOrEqual(Mask[0], 0))
3905 for (unsigned i = 1; i != NumOps; ++i)
3906 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3907 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3908 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3914 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3915 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3916 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3917 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3918 const X86Subtarget *Subtarget) {
3919 if (!Subtarget->hasSSE3())
3922 unsigned NumElems = VT.getVectorNumElements();
3924 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3925 (VT.getSizeInBits() == 256 && NumElems != 8))
3928 // "i+1" is the value the indexed mask element must have
3929 for (unsigned i = 0; i != NumElems; i += 2)
3930 if (!isUndefOrEqual(Mask[i], i+1) ||
3931 !isUndefOrEqual(Mask[i+1], i+1))
3937 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3938 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3939 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3940 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3941 const X86Subtarget *Subtarget) {
3942 if (!Subtarget->hasSSE3())
3945 unsigned NumElems = VT.getVectorNumElements();
3947 if ((VT.getSizeInBits() == 128 && NumElems != 4) ||
3948 (VT.getSizeInBits() == 256 && NumElems != 8))
3951 // "i" is the value the indexed mask element must have
3952 for (unsigned i = 0; i != NumElems; i += 2)
3953 if (!isUndefOrEqual(Mask[i], i) ||
3954 !isUndefOrEqual(Mask[i+1], i))
3960 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
3961 /// specifies a shuffle of elements that is suitable for input to 256-bit
3962 /// version of MOVDDUP.
3963 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3964 if (!HasFp256 || !VT.is256BitVector())
3967 unsigned NumElts = VT.getVectorNumElements();
3971 for (unsigned i = 0; i != NumElts/2; ++i)
3972 if (!isUndefOrEqual(Mask[i], 0))
3974 for (unsigned i = NumElts/2; i != NumElts; ++i)
3975 if (!isUndefOrEqual(Mask[i], NumElts/2))
3980 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3981 /// specifies a shuffle of elements that is suitable for input to 128-bit
3982 /// version of MOVDDUP.
3983 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
3984 if (!VT.is128BitVector())
3987 unsigned e = VT.getVectorNumElements() / 2;
3988 for (unsigned i = 0; i != e; ++i)
3989 if (!isUndefOrEqual(Mask[i], i))
3991 for (unsigned i = 0; i != e; ++i)
3992 if (!isUndefOrEqual(Mask[e+i], i))
3997 /// isVEXTRACTF128Index - Return true if the specified
3998 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3999 /// suitable for input to VEXTRACTF128.
4000 bool X86::isVEXTRACTF128Index(SDNode *N) {
4001 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4004 // The index should be aligned on a 128-bit boundary.
4006 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4008 unsigned VL = N->getValueType(0).getVectorNumElements();
4009 unsigned VBits = N->getValueType(0).getSizeInBits();
4010 unsigned ElSize = VBits / VL;
4011 bool Result = (Index * ElSize) % 128 == 0;
4016 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4017 /// operand specifies a subvector insert that is suitable for input to
4019 bool X86::isVINSERTF128Index(SDNode *N) {
4020 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4023 // The index should be aligned on a 128-bit boundary.
4025 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4027 unsigned VL = N->getValueType(0).getVectorNumElements();
4028 unsigned VBits = N->getValueType(0).getSizeInBits();
4029 unsigned ElSize = VBits / VL;
4030 bool Result = (Index * ElSize) % 128 == 0;
4035 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4036 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4037 /// Handles 128-bit and 256-bit.
4038 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4039 EVT VT = N->getValueType(0);
4041 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4042 "Unsupported vector type for PSHUF/SHUFP");
4044 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4045 // independently on 128-bit lanes.
4046 unsigned NumElts = VT.getVectorNumElements();
4047 unsigned NumLanes = VT.getSizeInBits()/128;
4048 unsigned NumLaneElts = NumElts/NumLanes;
4050 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4051 "Only supports 2 or 4 elements per lane");
4053 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4055 for (unsigned i = 0; i != NumElts; ++i) {
4056 int Elt = N->getMaskElt(i);
4057 if (Elt < 0) continue;
4058 Elt &= NumLaneElts - 1;
4059 unsigned ShAmt = (i << Shift) % 8;
4060 Mask |= Elt << ShAmt;
4066 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4067 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4068 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4069 EVT VT = N->getValueType(0);
4071 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4072 "Unsupported vector type for PSHUFHW");
4074 unsigned NumElts = VT.getVectorNumElements();
4077 for (unsigned l = 0; l != NumElts; l += 8) {
4078 // 8 nodes per lane, but we only care about the last 4.
4079 for (unsigned i = 0; i < 4; ++i) {
4080 int Elt = N->getMaskElt(l+i+4);
4081 if (Elt < 0) continue;
4082 Elt &= 0x3; // only 2-bits.
4083 Mask |= Elt << (i * 2);
4090 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4091 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4092 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4093 EVT VT = N->getValueType(0);
4095 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4096 "Unsupported vector type for PSHUFHW");
4098 unsigned NumElts = VT.getVectorNumElements();
4101 for (unsigned l = 0; l != NumElts; l += 8) {
4102 // 8 nodes per lane, but we only care about the first 4.
4103 for (unsigned i = 0; i < 4; ++i) {
4104 int Elt = N->getMaskElt(l+i);
4105 if (Elt < 0) continue;
4106 Elt &= 0x3; // only 2-bits
4107 Mask |= Elt << (i * 2);
4114 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4115 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4116 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4117 EVT VT = SVOp->getValueType(0);
4118 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4120 unsigned NumElts = VT.getVectorNumElements();
4121 unsigned NumLanes = VT.getSizeInBits()/128;
4122 unsigned NumLaneElts = NumElts/NumLanes;
4126 for (i = 0; i != NumElts; ++i) {
4127 Val = SVOp->getMaskElt(i);
4131 if (Val >= (int)NumElts)
4132 Val -= NumElts - NumLaneElts;
4134 assert(Val - i > 0 && "PALIGNR imm should be positive");
4135 return (Val - i) * EltSize;
4138 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4139 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4141 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4142 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4143 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4146 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4148 EVT VecVT = N->getOperand(0).getValueType();
4149 EVT ElVT = VecVT.getVectorElementType();
4151 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4152 return Index / NumElemsPerChunk;
4155 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4156 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4158 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4159 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4160 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4163 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4165 EVT VecVT = N->getValueType(0);
4166 EVT ElVT = VecVT.getVectorElementType();
4168 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4169 return Index / NumElemsPerChunk;
4172 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4173 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4174 /// Handles 256-bit.
4175 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4176 EVT VT = N->getValueType(0);
4178 unsigned NumElts = VT.getVectorNumElements();
4180 assert((VT.is256BitVector() && NumElts == 4) &&
4181 "Unsupported vector type for VPERMQ/VPERMPD");
4184 for (unsigned i = 0; i != NumElts; ++i) {
4185 int Elt = N->getMaskElt(i);
4188 Mask |= Elt << (i*2);
4193 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4195 bool X86::isZeroNode(SDValue Elt) {
4196 return ((isa<ConstantSDNode>(Elt) &&
4197 cast<ConstantSDNode>(Elt)->isNullValue()) ||
4198 (isa<ConstantFPSDNode>(Elt) &&
4199 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
4202 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4203 /// their permute mask.
4204 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4205 SelectionDAG &DAG) {
4206 EVT VT = SVOp->getValueType(0);
4207 unsigned NumElems = VT.getVectorNumElements();
4208 SmallVector<int, 8> MaskVec;
4210 for (unsigned i = 0; i != NumElems; ++i) {
4211 int Idx = SVOp->getMaskElt(i);
4213 if (Idx < (int)NumElems)
4218 MaskVec.push_back(Idx);
4220 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4221 SVOp->getOperand(0), &MaskVec[0]);
4224 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4225 /// match movhlps. The lower half elements should come from upper half of
4226 /// V1 (and in order), and the upper half elements should come from the upper
4227 /// half of V2 (and in order).
4228 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4229 if (!VT.is128BitVector())
4231 if (VT.getVectorNumElements() != 4)
4233 for (unsigned i = 0, e = 2; i != e; ++i)
4234 if (!isUndefOrEqual(Mask[i], i+2))
4236 for (unsigned i = 2; i != 4; ++i)
4237 if (!isUndefOrEqual(Mask[i], i+4))
4242 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4243 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4245 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4246 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4248 N = N->getOperand(0).getNode();
4249 if (!ISD::isNON_EXTLoad(N))
4252 *LD = cast<LoadSDNode>(N);
4256 // Test whether the given value is a vector value which will be legalized
4258 static bool WillBeConstantPoolLoad(SDNode *N) {
4259 if (N->getOpcode() != ISD::BUILD_VECTOR)
4262 // Check for any non-constant elements.
4263 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4264 switch (N->getOperand(i).getNode()->getOpcode()) {
4266 case ISD::ConstantFP:
4273 // Vectors of all-zeros and all-ones are materialized with special
4274 // instructions rather than being loaded.
4275 return !ISD::isBuildVectorAllZeros(N) &&
4276 !ISD::isBuildVectorAllOnes(N);
4279 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4280 /// match movlp{s|d}. The lower half elements should come from lower half of
4281 /// V1 (and in order), and the upper half elements should come from the upper
4282 /// half of V2 (and in order). And since V1 will become the source of the
4283 /// MOVLP, it must be either a vector load or a scalar load to vector.
4284 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4285 ArrayRef<int> Mask, EVT VT) {
4286 if (!VT.is128BitVector())
4289 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4291 // Is V2 is a vector load, don't do this transformation. We will try to use
4292 // load folding shufps op.
4293 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4296 unsigned NumElems = VT.getVectorNumElements();
4298 if (NumElems != 2 && NumElems != 4)
4300 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4301 if (!isUndefOrEqual(Mask[i], i))
4303 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4304 if (!isUndefOrEqual(Mask[i], i+NumElems))
4309 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4311 static bool isSplatVector(SDNode *N) {
4312 if (N->getOpcode() != ISD::BUILD_VECTOR)
4315 SDValue SplatValue = N->getOperand(0);
4316 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4317 if (N->getOperand(i) != SplatValue)
4322 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4323 /// to an zero vector.
4324 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4325 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4326 SDValue V1 = N->getOperand(0);
4327 SDValue V2 = N->getOperand(1);
4328 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4329 for (unsigned i = 0; i != NumElems; ++i) {
4330 int Idx = N->getMaskElt(i);
4331 if (Idx >= (int)NumElems) {
4332 unsigned Opc = V2.getOpcode();
4333 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4335 if (Opc != ISD::BUILD_VECTOR ||
4336 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4338 } else if (Idx >= 0) {
4339 unsigned Opc = V1.getOpcode();
4340 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4342 if (Opc != ISD::BUILD_VECTOR ||
4343 !X86::isZeroNode(V1.getOperand(Idx)))
4350 /// getZeroVector - Returns a vector of specified type with all zero elements.
4352 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4353 SelectionDAG &DAG, DebugLoc dl) {
4354 assert(VT.isVector() && "Expected a vector type");
4355 unsigned Size = VT.getSizeInBits();
4357 // Always build SSE zero vectors as <4 x i32> bitcasted
4358 // to their dest type. This ensures they get CSE'd.
4360 if (Size == 128) { // SSE
4361 if (Subtarget->hasSSE2()) { // SSE2
4362 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4363 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4365 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4366 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4368 } else if (Size == 256) { // AVX
4369 if (Subtarget->hasInt256()) { // AVX2
4370 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4371 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4372 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4374 // 256-bit logic and arithmetic instructions in AVX are all
4375 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4376 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4377 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4378 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8);
4381 llvm_unreachable("Unexpected vector type");
4383 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4386 /// getOnesVector - Returns a vector of specified type with all bits set.
4387 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4388 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4389 /// Then bitcast to their original type, ensuring they get CSE'd.
4390 static SDValue getOnesVector(EVT VT, bool HasInt256, SelectionDAG &DAG,
4392 assert(VT.isVector() && "Expected a vector type");
4393 unsigned Size = VT.getSizeInBits();
4395 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4398 if (HasInt256) { // AVX2
4399 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4400 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops, 8);
4402 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4403 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4405 } else if (Size == 128) {
4406 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4408 llvm_unreachable("Unexpected vector type");
4410 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4413 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4414 /// that point to V2 points to its first element.
4415 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4416 for (unsigned i = 0; i != NumElems; ++i) {
4417 if (Mask[i] > (int)NumElems) {
4423 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4424 /// operation of specified width.
4425 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4427 unsigned NumElems = VT.getVectorNumElements();
4428 SmallVector<int, 8> Mask;
4429 Mask.push_back(NumElems);
4430 for (unsigned i = 1; i != NumElems; ++i)
4432 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4435 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4436 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4438 unsigned NumElems = VT.getVectorNumElements();
4439 SmallVector<int, 8> Mask;
4440 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4442 Mask.push_back(i + NumElems);
4444 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4447 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4448 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4450 unsigned NumElems = VT.getVectorNumElements();
4451 SmallVector<int, 8> Mask;
4452 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4453 Mask.push_back(i + Half);
4454 Mask.push_back(i + NumElems + Half);
4456 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4459 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4460 // a generic shuffle instruction because the target has no such instructions.
4461 // Generate shuffles which repeat i16 and i8 several times until they can be
4462 // represented by v4f32 and then be manipulated by target suported shuffles.
4463 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4464 EVT VT = V.getValueType();
4465 int NumElems = VT.getVectorNumElements();
4466 DebugLoc dl = V.getDebugLoc();
4468 while (NumElems > 4) {
4469 if (EltNo < NumElems/2) {
4470 V = getUnpackl(DAG, dl, VT, V, V);
4472 V = getUnpackh(DAG, dl, VT, V, V);
4473 EltNo -= NumElems/2;
4480 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4481 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4482 EVT VT = V.getValueType();
4483 DebugLoc dl = V.getDebugLoc();
4484 unsigned Size = VT.getSizeInBits();
4487 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4488 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4489 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4491 } else if (Size == 256) {
4492 // To use VPERMILPS to splat scalars, the second half of indicies must
4493 // refer to the higher part, which is a duplication of the lower one,
4494 // because VPERMILPS can only handle in-lane permutations.
4495 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4496 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4498 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4499 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4502 llvm_unreachable("Vector size not supported");
4504 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4507 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4508 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4509 EVT SrcVT = SV->getValueType(0);
4510 SDValue V1 = SV->getOperand(0);
4511 DebugLoc dl = SV->getDebugLoc();
4513 int EltNo = SV->getSplatIndex();
4514 int NumElems = SrcVT.getVectorNumElements();
4515 unsigned Size = SrcVT.getSizeInBits();
4517 assert(((Size == 128 && NumElems > 4) || Size == 256) &&
4518 "Unknown how to promote splat for type");
4520 // Extract the 128-bit part containing the splat element and update
4521 // the splat element index when it refers to the higher register.
4523 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4524 if (EltNo >= NumElems/2)
4525 EltNo -= NumElems/2;
4528 // All i16 and i8 vector types can't be used directly by a generic shuffle
4529 // instruction because the target has no such instruction. Generate shuffles
4530 // which repeat i16 and i8 several times until they fit in i32, and then can
4531 // be manipulated by target suported shuffles.
4532 EVT EltVT = SrcVT.getVectorElementType();
4533 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4534 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4536 // Recreate the 256-bit vector and place the same 128-bit vector
4537 // into the low and high part. This is necessary because we want
4538 // to use VPERM* to shuffle the vectors
4540 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4543 return getLegalSplat(DAG, V1, EltNo);
4546 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4547 /// vector of zero or undef vector. This produces a shuffle where the low
4548 /// element of V2 is swizzled into the zero/undef vector, landing at element
4549 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4550 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4552 const X86Subtarget *Subtarget,
4553 SelectionDAG &DAG) {
4554 EVT VT = V2.getValueType();
4556 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4557 unsigned NumElems = VT.getVectorNumElements();
4558 SmallVector<int, 16> MaskVec;
4559 for (unsigned i = 0; i != NumElems; ++i)
4560 // If this is the insertion idx, put the low elt of V2 here.
4561 MaskVec.push_back(i == Idx ? NumElems : i);
4562 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4565 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4566 /// target specific opcode. Returns true if the Mask could be calculated.
4567 /// Sets IsUnary to true if only uses one source.
4568 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4569 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4570 unsigned NumElems = VT.getVectorNumElements();
4574 switch(N->getOpcode()) {
4576 ImmN = N->getOperand(N->getNumOperands()-1);
4577 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4579 case X86ISD::UNPCKH:
4580 DecodeUNPCKHMask(VT, Mask);
4582 case X86ISD::UNPCKL:
4583 DecodeUNPCKLMask(VT, Mask);
4585 case X86ISD::MOVHLPS:
4586 DecodeMOVHLPSMask(NumElems, Mask);
4588 case X86ISD::MOVLHPS:
4589 DecodeMOVLHPSMask(NumElems, Mask);
4591 case X86ISD::PSHUFD:
4592 case X86ISD::VPERMILP:
4593 ImmN = N->getOperand(N->getNumOperands()-1);
4594 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4597 case X86ISD::PSHUFHW:
4598 ImmN = N->getOperand(N->getNumOperands()-1);
4599 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4602 case X86ISD::PSHUFLW:
4603 ImmN = N->getOperand(N->getNumOperands()-1);
4604 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4607 case X86ISD::VPERMI:
4608 ImmN = N->getOperand(N->getNumOperands()-1);
4609 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4613 case X86ISD::MOVSD: {
4614 // The index 0 always comes from the first element of the second source,
4615 // this is why MOVSS and MOVSD are used in the first place. The other
4616 // elements come from the other positions of the first source vector
4617 Mask.push_back(NumElems);
4618 for (unsigned i = 1; i != NumElems; ++i) {
4623 case X86ISD::VPERM2X128:
4624 ImmN = N->getOperand(N->getNumOperands()-1);
4625 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4626 if (Mask.empty()) return false;
4628 case X86ISD::MOVDDUP:
4629 case X86ISD::MOVLHPD:
4630 case X86ISD::MOVLPD:
4631 case X86ISD::MOVLPS:
4632 case X86ISD::MOVSHDUP:
4633 case X86ISD::MOVSLDUP:
4634 case X86ISD::PALIGN:
4635 // Not yet implemented
4637 default: llvm_unreachable("unknown target shuffle node");
4643 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4644 /// element of the result of the vector shuffle.
4645 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4648 return SDValue(); // Limit search depth.
4650 SDValue V = SDValue(N, 0);
4651 EVT VT = V.getValueType();
4652 unsigned Opcode = V.getOpcode();
4654 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4655 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4656 int Elt = SV->getMaskElt(Index);
4659 return DAG.getUNDEF(VT.getVectorElementType());
4661 unsigned NumElems = VT.getVectorNumElements();
4662 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4663 : SV->getOperand(1);
4664 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4667 // Recurse into target specific vector shuffles to find scalars.
4668 if (isTargetShuffle(Opcode)) {
4669 MVT ShufVT = V.getValueType().getSimpleVT();
4670 unsigned NumElems = ShufVT.getVectorNumElements();
4671 SmallVector<int, 16> ShuffleMask;
4674 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4677 int Elt = ShuffleMask[Index];
4679 return DAG.getUNDEF(ShufVT.getVectorElementType());
4681 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4683 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4687 // Actual nodes that may contain scalar elements
4688 if (Opcode == ISD::BITCAST) {
4689 V = V.getOperand(0);
4690 EVT SrcVT = V.getValueType();
4691 unsigned NumElems = VT.getVectorNumElements();
4693 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4697 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4698 return (Index == 0) ? V.getOperand(0)
4699 : DAG.getUNDEF(VT.getVectorElementType());
4701 if (V.getOpcode() == ISD::BUILD_VECTOR)
4702 return V.getOperand(Index);
4707 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4708 /// shuffle operation which come from a consecutively from a zero. The
4709 /// search can start in two different directions, from left or right.
4711 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, unsigned NumElems,
4712 bool ZerosFromLeft, SelectionDAG &DAG) {
4714 for (i = 0; i != NumElems; ++i) {
4715 unsigned Index = ZerosFromLeft ? i : NumElems-i-1;
4716 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4717 if (!(Elt.getNode() &&
4718 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt))))
4725 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4726 /// correspond consecutively to elements from one of the vector operands,
4727 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4729 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4730 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4731 unsigned NumElems, unsigned &OpNum) {
4732 bool SeenV1 = false;
4733 bool SeenV2 = false;
4735 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4736 int Idx = SVOp->getMaskElt(i);
4737 // Ignore undef indicies
4741 if (Idx < (int)NumElems)
4746 // Only accept consecutive elements from the same vector
4747 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4751 OpNum = SeenV1 ? 0 : 1;
4755 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4756 /// logical left shift of a vector.
4757 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4758 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4759 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4760 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4761 false /* check zeros from right */, DAG);
4767 // Considering the elements in the mask that are not consecutive zeros,
4768 // check if they consecutively come from only one of the source vectors.
4770 // V1 = {X, A, B, C} 0
4772 // vector_shuffle V1, V2 <1, 2, 3, X>
4774 if (!isShuffleMaskConsecutive(SVOp,
4775 0, // Mask Start Index
4776 NumElems-NumZeros, // Mask End Index(exclusive)
4777 NumZeros, // Where to start looking in the src vector
4778 NumElems, // Number of elements in vector
4779 OpSrc)) // Which source operand ?
4784 ShVal = SVOp->getOperand(OpSrc);
4788 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4789 /// logical left shift of a vector.
4790 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4791 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4792 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4793 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems,
4794 true /* check zeros from left */, DAG);
4800 // Considering the elements in the mask that are not consecutive zeros,
4801 // check if they consecutively come from only one of the source vectors.
4803 // 0 { A, B, X, X } = V2
4805 // vector_shuffle V1, V2 <X, X, 4, 5>
4807 if (!isShuffleMaskConsecutive(SVOp,
4808 NumZeros, // Mask Start Index
4809 NumElems, // Mask End Index(exclusive)
4810 0, // Where to start looking in the src vector
4811 NumElems, // Number of elements in vector
4812 OpSrc)) // Which source operand ?
4817 ShVal = SVOp->getOperand(OpSrc);
4821 /// isVectorShift - Returns true if the shuffle can be implemented as a
4822 /// logical left or right shift of a vector.
4823 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4824 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4825 // Although the logic below support any bitwidth size, there are no
4826 // shift instructions which handle more than 128-bit vectors.
4827 if (!SVOp->getValueType(0).is128BitVector())
4830 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4831 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4837 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4839 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4840 unsigned NumNonZero, unsigned NumZero,
4842 const X86Subtarget* Subtarget,
4843 const TargetLowering &TLI) {
4847 DebugLoc dl = Op.getDebugLoc();
4850 for (unsigned i = 0; i < 16; ++i) {
4851 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4852 if (ThisIsNonZero && First) {
4854 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4856 V = DAG.getUNDEF(MVT::v8i16);
4861 SDValue ThisElt(0, 0), LastElt(0, 0);
4862 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4863 if (LastIsNonZero) {
4864 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4865 MVT::i16, Op.getOperand(i-1));
4867 if (ThisIsNonZero) {
4868 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4869 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4870 ThisElt, DAG.getConstant(8, MVT::i8));
4872 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4876 if (ThisElt.getNode())
4877 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4878 DAG.getIntPtrConstant(i/2));
4882 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4885 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4887 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4888 unsigned NumNonZero, unsigned NumZero,
4890 const X86Subtarget* Subtarget,
4891 const TargetLowering &TLI) {
4895 DebugLoc dl = Op.getDebugLoc();
4898 for (unsigned i = 0; i < 8; ++i) {
4899 bool isNonZero = (NonZeros & (1 << i)) != 0;
4903 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4905 V = DAG.getUNDEF(MVT::v8i16);
4908 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4909 MVT::v8i16, V, Op.getOperand(i),
4910 DAG.getIntPtrConstant(i));
4917 /// getVShift - Return a vector logical shift node.
4919 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4920 unsigned NumBits, SelectionDAG &DAG,
4921 const TargetLowering &TLI, DebugLoc dl) {
4922 assert(VT.is128BitVector() && "Unknown type for VShift");
4923 EVT ShVT = MVT::v2i64;
4924 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4925 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4926 return DAG.getNode(ISD::BITCAST, dl, VT,
4927 DAG.getNode(Opc, dl, ShVT, SrcOp,
4928 DAG.getConstant(NumBits,
4929 TLI.getShiftAmountTy(SrcOp.getValueType()))));
4933 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4934 SelectionDAG &DAG) const {
4936 // Check if the scalar load can be widened into a vector load. And if
4937 // the address is "base + cst" see if the cst can be "absorbed" into
4938 // the shuffle mask.
4939 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4940 SDValue Ptr = LD->getBasePtr();
4941 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4943 EVT PVT = LD->getValueType(0);
4944 if (PVT != MVT::i32 && PVT != MVT::f32)
4949 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4950 FI = FINode->getIndex();
4952 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4953 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4954 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4955 Offset = Ptr.getConstantOperandVal(1);
4956 Ptr = Ptr.getOperand(0);
4961 // FIXME: 256-bit vector instructions don't require a strict alignment,
4962 // improve this code to support it better.
4963 unsigned RequiredAlign = VT.getSizeInBits()/8;
4964 SDValue Chain = LD->getChain();
4965 // Make sure the stack object alignment is at least 16 or 32.
4966 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4967 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4968 if (MFI->isFixedObjectIndex(FI)) {
4969 // Can't change the alignment. FIXME: It's possible to compute
4970 // the exact stack offset and reference FI + adjust offset instead.
4971 // If someone *really* cares about this. That's the way to implement it.
4974 MFI->setObjectAlignment(FI, RequiredAlign);
4978 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4979 // Ptr + (Offset & ~15).
4982 if ((Offset % RequiredAlign) & 3)
4984 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4986 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
4987 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
4989 int EltNo = (Offset - StartOffset) >> 2;
4990 unsigned NumElems = VT.getVectorNumElements();
4992 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4993 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4994 LD->getPointerInfo().getWithOffset(StartOffset),
4995 false, false, false, 0);
4997 SmallVector<int, 8> Mask;
4998 for (unsigned i = 0; i != NumElems; ++i)
4999 Mask.push_back(EltNo);
5001 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5007 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5008 /// vector of type 'VT', see if the elements can be replaced by a single large
5009 /// load which has the same value as a build_vector whose operands are 'elts'.
5011 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5013 /// FIXME: we'd also like to handle the case where the last elements are zero
5014 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5015 /// There's even a handy isZeroNode for that purpose.
5016 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5017 DebugLoc &DL, SelectionDAG &DAG) {
5018 EVT EltVT = VT.getVectorElementType();
5019 unsigned NumElems = Elts.size();
5021 LoadSDNode *LDBase = NULL;
5022 unsigned LastLoadedElt = -1U;
5024 // For each element in the initializer, see if we've found a load or an undef.
5025 // If we don't find an initial load element, or later load elements are
5026 // non-consecutive, bail out.
5027 for (unsigned i = 0; i < NumElems; ++i) {
5028 SDValue Elt = Elts[i];
5030 if (!Elt.getNode() ||
5031 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5034 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5036 LDBase = cast<LoadSDNode>(Elt.getNode());
5040 if (Elt.getOpcode() == ISD::UNDEF)
5043 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5044 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5049 // If we have found an entire vector of loads and undefs, then return a large
5050 // load of the entire vector width starting at the base pointer. If we found
5051 // consecutive loads for the low half, generate a vzext_load node.
5052 if (LastLoadedElt == NumElems - 1) {
5053 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5054 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5055 LDBase->getPointerInfo(),
5056 LDBase->isVolatile(), LDBase->isNonTemporal(),
5057 LDBase->isInvariant(), 0);
5058 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5059 LDBase->getPointerInfo(),
5060 LDBase->isVolatile(), LDBase->isNonTemporal(),
5061 LDBase->isInvariant(), LDBase->getAlignment());
5063 if (NumElems == 4 && LastLoadedElt == 1 &&
5064 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5065 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5066 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5068 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64,
5069 LDBase->getPointerInfo(),
5070 LDBase->getAlignment(),
5071 false/*isVolatile*/, true/*ReadMem*/,
5074 // Make sure the newly-created LOAD is in the same position as LDBase in
5075 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5076 // update uses of LDBase's output chain to use the TokenFactor.
5077 if (LDBase->hasAnyUseOfValue(1)) {
5078 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5079 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5080 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5081 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5082 SDValue(ResNode.getNode(), 1));
5085 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5090 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5091 /// to generate a splat value for the following cases:
5092 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5093 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5094 /// a scalar load, or a constant.
5095 /// The VBROADCAST node is returned when a pattern is found,
5096 /// or SDValue() otherwise.
5098 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5099 if (!Subtarget->hasFp256())
5102 EVT VT = Op.getValueType();
5103 DebugLoc dl = Op.getDebugLoc();
5105 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5106 "Unsupported vector type for broadcast.");
5111 switch (Op.getOpcode()) {
5113 // Unknown pattern found.
5116 case ISD::BUILD_VECTOR: {
5117 // The BUILD_VECTOR node must be a splat.
5118 if (!isSplatVector(Op.getNode()))
5121 Ld = Op.getOperand(0);
5122 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5123 Ld.getOpcode() == ISD::ConstantFP);
5125 // The suspected load node has several users. Make sure that all
5126 // of its users are from the BUILD_VECTOR node.
5127 // Constants may have multiple users.
5128 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5133 case ISD::VECTOR_SHUFFLE: {
5134 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5136 // Shuffles must have a splat mask where the first element is
5138 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5141 SDValue Sc = Op.getOperand(0);
5142 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5143 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5145 if (!Subtarget->hasInt256())
5148 // Use the register form of the broadcast instruction available on AVX2.
5149 if (VT.is256BitVector())
5150 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5151 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5154 Ld = Sc.getOperand(0);
5155 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5156 Ld.getOpcode() == ISD::ConstantFP);
5158 // The scalar_to_vector node and the suspected
5159 // load node must have exactly one user.
5160 // Constants may have multiple users.
5161 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5167 bool Is256 = VT.is256BitVector();
5169 // Handle the broadcasting a single constant scalar from the constant pool
5170 // into a vector. On Sandybridge it is still better to load a constant vector
5171 // from the constant pool and not to broadcast it from a scalar.
5172 if (ConstSplatVal && Subtarget->hasInt256()) {
5173 EVT CVT = Ld.getValueType();
5174 assert(!CVT.isVector() && "Must not broadcast a vector type");
5175 unsigned ScalarSize = CVT.getSizeInBits();
5177 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5178 const Constant *C = 0;
5179 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5180 C = CI->getConstantIntValue();
5181 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5182 C = CF->getConstantFPValue();
5184 assert(C && "Invalid constant type");
5186 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5187 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5188 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5189 MachinePointerInfo::getConstantPool(),
5190 false, false, false, Alignment);
5192 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5196 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5197 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5199 // Handle AVX2 in-register broadcasts.
5200 if (!IsLoad && Subtarget->hasInt256() &&
5201 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5202 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5204 // The scalar source must be a normal load.
5208 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5209 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5211 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5212 // double since there is no vbroadcastsd xmm
5213 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5214 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5215 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5218 // Unsupported broadcast.
5223 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5224 EVT VT = Op.getValueType();
5226 // Skip if insert_vec_elt is not supported.
5227 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5230 DebugLoc DL = Op.getDebugLoc();
5231 unsigned NumElems = Op.getNumOperands();
5235 SmallVector<unsigned, 4> InsertIndices;
5236 SmallVector<int, 8> Mask(NumElems, -1);
5238 for (unsigned i = 0; i != NumElems; ++i) {
5239 unsigned Opc = Op.getOperand(i).getOpcode();
5241 if (Opc == ISD::UNDEF)
5244 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5245 // Quit if more than 1 elements need inserting.
5246 if (InsertIndices.size() > 1)
5249 InsertIndices.push_back(i);
5253 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5254 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5256 // Quit if extracted from vector of different type.
5257 if (ExtractedFromVec.getValueType() != VT)
5260 // Quit if non-constant index.
5261 if (!isa<ConstantSDNode>(ExtIdx))
5264 if (VecIn1.getNode() == 0)
5265 VecIn1 = ExtractedFromVec;
5266 else if (VecIn1 != ExtractedFromVec) {
5267 if (VecIn2.getNode() == 0)
5268 VecIn2 = ExtractedFromVec;
5269 else if (VecIn2 != ExtractedFromVec)
5270 // Quit if more than 2 vectors to shuffle
5274 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5276 if (ExtractedFromVec == VecIn1)
5278 else if (ExtractedFromVec == VecIn2)
5279 Mask[i] = Idx + NumElems;
5282 if (VecIn1.getNode() == 0)
5285 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5286 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5287 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5288 unsigned Idx = InsertIndices[i];
5289 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5290 DAG.getIntPtrConstant(Idx));
5297 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5298 DebugLoc dl = Op.getDebugLoc();
5300 EVT VT = Op.getValueType();
5301 EVT ExtVT = VT.getVectorElementType();
5302 unsigned NumElems = Op.getNumOperands();
5304 // Vectors containing all zeros can be matched by pxor and xorps later
5305 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5306 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5307 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5308 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5311 return getZeroVector(VT, Subtarget, DAG, dl);
5314 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5315 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5316 // vpcmpeqd on 256-bit vectors.
5317 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5318 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5321 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5324 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5325 if (Broadcast.getNode())
5328 unsigned EVTBits = ExtVT.getSizeInBits();
5330 unsigned NumZero = 0;
5331 unsigned NumNonZero = 0;
5332 unsigned NonZeros = 0;
5333 bool IsAllConstants = true;
5334 SmallSet<SDValue, 8> Values;
5335 for (unsigned i = 0; i < NumElems; ++i) {
5336 SDValue Elt = Op.getOperand(i);
5337 if (Elt.getOpcode() == ISD::UNDEF)
5340 if (Elt.getOpcode() != ISD::Constant &&
5341 Elt.getOpcode() != ISD::ConstantFP)
5342 IsAllConstants = false;
5343 if (X86::isZeroNode(Elt))
5346 NonZeros |= (1 << i);
5351 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5352 if (NumNonZero == 0)
5353 return DAG.getUNDEF(VT);
5355 // Special case for single non-zero, non-undef, element.
5356 if (NumNonZero == 1) {
5357 unsigned Idx = CountTrailingZeros_32(NonZeros);
5358 SDValue Item = Op.getOperand(Idx);
5360 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5361 // the value are obviously zero, truncate the value to i32 and do the
5362 // insertion that way. Only do this if the value is non-constant or if the
5363 // value is a constant being inserted into element 0. It is cheaper to do
5364 // a constant pool load than it is to do a movd + shuffle.
5365 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5366 (!IsAllConstants || Idx == 0)) {
5367 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5369 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5370 EVT VecVT = MVT::v4i32;
5371 unsigned VecElts = 4;
5373 // Truncate the value (which may itself be a constant) to i32, and
5374 // convert it to a vector with movd (S2V+shuffle to zero extend).
5375 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5376 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5377 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5379 // Now we have our 32-bit value zero extended in the low element of
5380 // a vector. If Idx != 0, swizzle it into place.
5382 SmallVector<int, 4> Mask;
5383 Mask.push_back(Idx);
5384 for (unsigned i = 1; i != VecElts; ++i)
5386 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5389 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5393 // If we have a constant or non-constant insertion into the low element of
5394 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5395 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5396 // depending on what the source datatype is.
5399 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5401 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5402 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5403 if (VT.is256BitVector()) {
5404 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5405 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5406 Item, DAG.getIntPtrConstant(0));
5408 assert(VT.is128BitVector() && "Expected an SSE value type!");
5409 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5410 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5411 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5414 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5415 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5416 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5417 if (VT.is256BitVector()) {
5418 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5419 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5421 assert(VT.is128BitVector() && "Expected an SSE value type!");
5422 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5424 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5428 // Is it a vector logical left shift?
5429 if (NumElems == 2 && Idx == 1 &&
5430 X86::isZeroNode(Op.getOperand(0)) &&
5431 !X86::isZeroNode(Op.getOperand(1))) {
5432 unsigned NumBits = VT.getSizeInBits();
5433 return getVShift(true, VT,
5434 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5435 VT, Op.getOperand(1)),
5436 NumBits/2, DAG, *this, dl);
5439 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5442 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5443 // is a non-constant being inserted into an element other than the low one,
5444 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5445 // movd/movss) to move this into the low element, then shuffle it into
5447 if (EVTBits == 32) {
5448 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5450 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5451 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5452 SmallVector<int, 8> MaskVec;
5453 for (unsigned i = 0; i != NumElems; ++i)
5454 MaskVec.push_back(i == Idx ? 0 : 1);
5455 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5459 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5460 if (Values.size() == 1) {
5461 if (EVTBits == 32) {
5462 // Instead of a shuffle like this:
5463 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5464 // Check if it's possible to issue this instead.
5465 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5466 unsigned Idx = CountTrailingZeros_32(NonZeros);
5467 SDValue Item = Op.getOperand(Idx);
5468 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5469 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5474 // A vector full of immediates; various special cases are already
5475 // handled, so this is best done with a single constant-pool load.
5479 // For AVX-length vectors, build the individual 128-bit pieces and use
5480 // shuffles to put them in place.
5481 if (VT.is256BitVector()) {
5482 SmallVector<SDValue, 32> V;
5483 for (unsigned i = 0; i != NumElems; ++i)
5484 V.push_back(Op.getOperand(i));
5486 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5488 // Build both the lower and upper subvector.
5489 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5490 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5493 // Recreate the wider vector with the lower and upper part.
5494 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5497 // Let legalizer expand 2-wide build_vectors.
5498 if (EVTBits == 64) {
5499 if (NumNonZero == 1) {
5500 // One half is zero or undef.
5501 unsigned Idx = CountTrailingZeros_32(NonZeros);
5502 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5503 Op.getOperand(Idx));
5504 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5509 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5510 if (EVTBits == 8 && NumElems == 16) {
5511 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5513 if (V.getNode()) return V;
5516 if (EVTBits == 16 && NumElems == 8) {
5517 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5519 if (V.getNode()) return V;
5522 // If element VT is == 32 bits, turn it into a number of shuffles.
5523 SmallVector<SDValue, 8> V(NumElems);
5524 if (NumElems == 4 && NumZero > 0) {
5525 for (unsigned i = 0; i < 4; ++i) {
5526 bool isZero = !(NonZeros & (1 << i));
5528 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5530 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5533 for (unsigned i = 0; i < 2; ++i) {
5534 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5537 V[i] = V[i*2]; // Must be a zero vector.
5540 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5543 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5546 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5551 bool Reverse1 = (NonZeros & 0x3) == 2;
5552 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5556 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5557 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5559 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5562 if (Values.size() > 1 && VT.is128BitVector()) {
5563 // Check for a build vector of consecutive loads.
5564 for (unsigned i = 0; i < NumElems; ++i)
5565 V[i] = Op.getOperand(i);
5567 // Check for elements which are consecutive loads.
5568 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5572 // Check for a build vector from mostly shuffle plus few inserting.
5573 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5577 // For SSE 4.1, use insertps to put the high elements into the low element.
5578 if (getSubtarget()->hasSSE41()) {
5580 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5581 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5583 Result = DAG.getUNDEF(VT);
5585 for (unsigned i = 1; i < NumElems; ++i) {
5586 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5587 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5588 Op.getOperand(i), DAG.getIntPtrConstant(i));
5593 // Otherwise, expand into a number of unpckl*, start by extending each of
5594 // our (non-undef) elements to the full vector width with the element in the
5595 // bottom slot of the vector (which generates no code for SSE).
5596 for (unsigned i = 0; i < NumElems; ++i) {
5597 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5598 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5600 V[i] = DAG.getUNDEF(VT);
5603 // Next, we iteratively mix elements, e.g. for v4f32:
5604 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5605 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5606 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5607 unsigned EltStride = NumElems >> 1;
5608 while (EltStride != 0) {
5609 for (unsigned i = 0; i < EltStride; ++i) {
5610 // If V[i+EltStride] is undef and this is the first round of mixing,
5611 // then it is safe to just drop this shuffle: V[i] is already in the
5612 // right place, the one element (since it's the first round) being
5613 // inserted as undef can be dropped. This isn't safe for successive
5614 // rounds because they will permute elements within both vectors.
5615 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5616 EltStride == NumElems/2)
5619 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5628 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5629 // to create 256-bit vectors from two other 128-bit ones.
5630 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5631 DebugLoc dl = Op.getDebugLoc();
5632 EVT ResVT = Op.getValueType();
5634 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5636 SDValue V1 = Op.getOperand(0);
5637 SDValue V2 = Op.getOperand(1);
5638 unsigned NumElems = ResVT.getVectorNumElements();
5640 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5643 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5644 assert(Op.getNumOperands() == 2);
5646 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5647 // from two other 128-bit ones.
5648 return LowerAVXCONCAT_VECTORS(Op, DAG);
5651 // Try to lower a shuffle node into a simple blend instruction.
5653 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5654 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5655 SDValue V1 = SVOp->getOperand(0);
5656 SDValue V2 = SVOp->getOperand(1);
5657 DebugLoc dl = SVOp->getDebugLoc();
5658 EVT VT = SVOp->getValueType(0);
5659 EVT EltVT = VT.getVectorElementType();
5660 unsigned NumElems = VT.getVectorNumElements();
5662 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
5664 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
5667 // Check the mask for BLEND and build the value.
5668 unsigned MaskValue = 0;
5669 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
5670 unsigned NumLanes = (NumElems-1)/8 + 1;
5671 unsigned NumElemsInLane = NumElems / NumLanes;
5673 // Blend for v16i16 should be symetric for the both lanes.
5674 for (unsigned i = 0; i < NumElemsInLane; ++i) {
5676 int SndLaneEltIdx = (NumLanes == 2) ?
5677 SVOp->getMaskElt(i + NumElemsInLane) : -1;
5678 int EltIdx = SVOp->getMaskElt(i);
5680 if ((EltIdx == -1 || EltIdx == (int)i) &&
5681 (SndLaneEltIdx == -1 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
5684 if (((unsigned)EltIdx == (i + NumElems)) &&
5685 (SndLaneEltIdx == -1 ||
5686 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
5687 MaskValue |= (1<<i);
5692 // Convert i32 vectors to floating point if it is not AVX2.
5693 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
5695 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
5696 BlendVT = EVT::getVectorVT(*DAG.getContext(),
5697 EVT::getFloatingPointVT(EltVT.getSizeInBits()),
5699 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
5700 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
5703 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
5704 DAG.getConstant(MaskValue, MVT::i32));
5705 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5708 // v8i16 shuffles - Prefer shuffles in the following order:
5709 // 1. [all] pshuflw, pshufhw, optional move
5710 // 2. [ssse3] 1 x pshufb
5711 // 3. [ssse3] 2 x pshufb + 1 x por
5712 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5714 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
5715 SelectionDAG &DAG) {
5716 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5717 SDValue V1 = SVOp->getOperand(0);
5718 SDValue V2 = SVOp->getOperand(1);
5719 DebugLoc dl = SVOp->getDebugLoc();
5720 SmallVector<int, 8> MaskVals;
5722 // Determine if more than 1 of the words in each of the low and high quadwords
5723 // of the result come from the same quadword of one of the two inputs. Undef
5724 // mask values count as coming from any quadword, for better codegen.
5725 unsigned LoQuad[] = { 0, 0, 0, 0 };
5726 unsigned HiQuad[] = { 0, 0, 0, 0 };
5727 std::bitset<4> InputQuads;
5728 for (unsigned i = 0; i < 8; ++i) {
5729 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5730 int EltIdx = SVOp->getMaskElt(i);
5731 MaskVals.push_back(EltIdx);
5740 InputQuads.set(EltIdx / 4);
5743 int BestLoQuad = -1;
5744 unsigned MaxQuad = 1;
5745 for (unsigned i = 0; i < 4; ++i) {
5746 if (LoQuad[i] > MaxQuad) {
5748 MaxQuad = LoQuad[i];
5752 int BestHiQuad = -1;
5754 for (unsigned i = 0; i < 4; ++i) {
5755 if (HiQuad[i] > MaxQuad) {
5757 MaxQuad = HiQuad[i];
5761 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5762 // of the two input vectors, shuffle them into one input vector so only a
5763 // single pshufb instruction is necessary. If There are more than 2 input
5764 // quads, disable the next transformation since it does not help SSSE3.
5765 bool V1Used = InputQuads[0] || InputQuads[1];
5766 bool V2Used = InputQuads[2] || InputQuads[3];
5767 if (Subtarget->hasSSSE3()) {
5768 if (InputQuads.count() == 2 && V1Used && V2Used) {
5769 BestLoQuad = InputQuads[0] ? 0 : 1;
5770 BestHiQuad = InputQuads[2] ? 2 : 3;
5772 if (InputQuads.count() > 2) {
5778 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5779 // the shuffle mask. If a quad is scored as -1, that means that it contains
5780 // words from all 4 input quadwords.
5782 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5784 BestLoQuad < 0 ? 0 : BestLoQuad,
5785 BestHiQuad < 0 ? 1 : BestHiQuad
5787 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5788 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5789 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5790 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5792 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5793 // source words for the shuffle, to aid later transformations.
5794 bool AllWordsInNewV = true;
5795 bool InOrder[2] = { true, true };
5796 for (unsigned i = 0; i != 8; ++i) {
5797 int idx = MaskVals[i];
5799 InOrder[i/4] = false;
5800 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5802 AllWordsInNewV = false;
5806 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5807 if (AllWordsInNewV) {
5808 for (int i = 0; i != 8; ++i) {
5809 int idx = MaskVals[i];
5812 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5813 if ((idx != i) && idx < 4)
5815 if ((idx != i) && idx > 3)
5824 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5825 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5826 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5827 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5828 unsigned TargetMask = 0;
5829 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5830 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5831 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5832 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5833 getShufflePSHUFLWImmediate(SVOp);
5834 V1 = NewV.getOperand(0);
5835 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5839 // If we have SSSE3, and all words of the result are from 1 input vector,
5840 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5841 // is present, fall back to case 4.
5842 if (Subtarget->hasSSSE3()) {
5843 SmallVector<SDValue,16> pshufbMask;
5845 // If we have elements from both input vectors, set the high bit of the
5846 // shuffle mask element to zero out elements that come from V2 in the V1
5847 // mask, and elements that come from V1 in the V2 mask, so that the two
5848 // results can be OR'd together.
5849 bool TwoInputs = V1Used && V2Used;
5850 for (unsigned i = 0; i != 8; ++i) {
5851 int EltIdx = MaskVals[i] * 2;
5852 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5853 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5854 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5855 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5857 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5858 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5859 DAG.getNode(ISD::BUILD_VECTOR, dl,
5860 MVT::v16i8, &pshufbMask[0], 16));
5862 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5864 // Calculate the shuffle mask for the second input, shuffle it, and
5865 // OR it with the first shuffled input.
5867 for (unsigned i = 0; i != 8; ++i) {
5868 int EltIdx = MaskVals[i] * 2;
5869 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5870 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5871 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5872 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5874 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5875 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5876 DAG.getNode(ISD::BUILD_VECTOR, dl,
5877 MVT::v16i8, &pshufbMask[0], 16));
5878 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5879 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5882 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5883 // and update MaskVals with new element order.
5884 std::bitset<8> InOrder;
5885 if (BestLoQuad >= 0) {
5886 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5887 for (int i = 0; i != 4; ++i) {
5888 int idx = MaskVals[i];
5891 } else if ((idx / 4) == BestLoQuad) {
5896 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5899 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5900 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5901 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5903 getShufflePSHUFLWImmediate(SVOp), DAG);
5907 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5908 // and update MaskVals with the new element order.
5909 if (BestHiQuad >= 0) {
5910 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5911 for (unsigned i = 4; i != 8; ++i) {
5912 int idx = MaskVals[i];
5915 } else if ((idx / 4) == BestHiQuad) {
5916 MaskV[i] = (idx & 3) + 4;
5920 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5923 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5924 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5925 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5927 getShufflePSHUFHWImmediate(SVOp), DAG);
5931 // In case BestHi & BestLo were both -1, which means each quadword has a word
5932 // from each of the four input quadwords, calculate the InOrder bitvector now
5933 // before falling through to the insert/extract cleanup.
5934 if (BestLoQuad == -1 && BestHiQuad == -1) {
5936 for (int i = 0; i != 8; ++i)
5937 if (MaskVals[i] < 0 || MaskVals[i] == i)
5941 // The other elements are put in the right place using pextrw and pinsrw.
5942 for (unsigned i = 0; i != 8; ++i) {
5945 int EltIdx = MaskVals[i];
5948 SDValue ExtOp = (EltIdx < 8) ?
5949 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
5950 DAG.getIntPtrConstant(EltIdx)) :
5951 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
5952 DAG.getIntPtrConstant(EltIdx - 8));
5953 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
5954 DAG.getIntPtrConstant(i));
5959 // v16i8 shuffles - Prefer shuffles in the following order:
5960 // 1. [ssse3] 1 x pshufb
5961 // 2. [ssse3] 2 x pshufb + 1 x por
5962 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
5964 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
5966 const X86TargetLowering &TLI) {
5967 SDValue V1 = SVOp->getOperand(0);
5968 SDValue V2 = SVOp->getOperand(1);
5969 DebugLoc dl = SVOp->getDebugLoc();
5970 ArrayRef<int> MaskVals = SVOp->getMask();
5972 // If we have SSSE3, case 1 is generated when all result bytes come from
5973 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
5974 // present, fall back to case 3.
5976 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
5977 if (TLI.getSubtarget()->hasSSSE3()) {
5978 SmallVector<SDValue,16> pshufbMask;
5980 // If all result elements are from one input vector, then only translate
5981 // undef mask values to 0x80 (zero out result) in the pshufb mask.
5983 // Otherwise, we have elements from both input vectors, and must zero out
5984 // elements that come from V2 in the first mask, and V1 in the second mask
5985 // so that we can OR them together.
5986 for (unsigned i = 0; i != 16; ++i) {
5987 int EltIdx = MaskVals[i];
5988 if (EltIdx < 0 || EltIdx >= 16)
5990 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
5992 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5993 DAG.getNode(ISD::BUILD_VECTOR, dl,
5994 MVT::v16i8, &pshufbMask[0], 16));
5996 // As PSHUFB will zero elements with negative indices, it's safe to ignore
5997 // the 2nd operand if it's undefined or zero.
5998 if (V2.getOpcode() == ISD::UNDEF ||
5999 ISD::isBuildVectorAllZeros(V2.getNode()))
6002 // Calculate the shuffle mask for the second input, shuffle it, and
6003 // OR it with the first shuffled input.
6005 for (unsigned i = 0; i != 16; ++i) {
6006 int EltIdx = MaskVals[i];
6007 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6008 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6010 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6011 DAG.getNode(ISD::BUILD_VECTOR, dl,
6012 MVT::v16i8, &pshufbMask[0], 16));
6013 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6016 // No SSSE3 - Calculate in place words and then fix all out of place words
6017 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6018 // the 16 different words that comprise the two doublequadword input vectors.
6019 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6020 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6022 for (int i = 0; i != 8; ++i) {
6023 int Elt0 = MaskVals[i*2];
6024 int Elt1 = MaskVals[i*2+1];
6026 // This word of the result is all undef, skip it.
6027 if (Elt0 < 0 && Elt1 < 0)
6030 // This word of the result is already in the correct place, skip it.
6031 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6034 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6035 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6038 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6039 // using a single extract together, load it and store it.
6040 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6041 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6042 DAG.getIntPtrConstant(Elt1 / 2));
6043 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6044 DAG.getIntPtrConstant(i));
6048 // If Elt1 is defined, extract it from the appropriate source. If the
6049 // source byte is not also odd, shift the extracted word left 8 bits
6050 // otherwise clear the bottom 8 bits if we need to do an or.
6052 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6053 DAG.getIntPtrConstant(Elt1 / 2));
6054 if ((Elt1 & 1) == 0)
6055 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6057 TLI.getShiftAmountTy(InsElt.getValueType())));
6059 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6060 DAG.getConstant(0xFF00, MVT::i16));
6062 // If Elt0 is defined, extract it from the appropriate source. If the
6063 // source byte is not also even, shift the extracted word right 8 bits. If
6064 // Elt1 was also defined, OR the extracted values together before
6065 // inserting them in the result.
6067 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6068 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6069 if ((Elt0 & 1) != 0)
6070 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6072 TLI.getShiftAmountTy(InsElt0.getValueType())));
6074 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6075 DAG.getConstant(0x00FF, MVT::i16));
6076 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6079 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6080 DAG.getIntPtrConstant(i));
6082 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6085 // v32i8 shuffles - Translate to VPSHUFB if possible.
6087 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6088 const X86Subtarget *Subtarget,
6089 SelectionDAG &DAG) {
6090 EVT VT = SVOp->getValueType(0);
6091 SDValue V1 = SVOp->getOperand(0);
6092 SDValue V2 = SVOp->getOperand(1);
6093 DebugLoc dl = SVOp->getDebugLoc();
6094 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6096 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6097 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6098 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6100 // VPSHUFB may be generated if
6101 // (1) one of input vector is undefined or zeroinitializer.
6102 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6103 // And (2) the mask indexes don't cross the 128-bit lane.
6104 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6105 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6108 if (V1IsAllZero && !V2IsAllZero) {
6109 CommuteVectorShuffleMask(MaskVals, 32);
6112 SmallVector<SDValue, 32> pshufbMask;
6113 for (unsigned i = 0; i != 32; i++) {
6114 int EltIdx = MaskVals[i];
6115 if (EltIdx < 0 || EltIdx >= 32)
6118 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6119 // Cross lane is not allowed.
6123 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6125 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6126 DAG.getNode(ISD::BUILD_VECTOR, dl,
6127 MVT::v32i8, &pshufbMask[0], 32));
6130 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6131 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6132 /// done when every pair / quad of shuffle mask elements point to elements in
6133 /// the right sequence. e.g.
6134 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6136 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6137 SelectionDAG &DAG, DebugLoc dl) {
6138 MVT VT = SVOp->getValueType(0).getSimpleVT();
6139 unsigned NumElems = VT.getVectorNumElements();
6142 switch (VT.SimpleTy) {
6143 default: llvm_unreachable("Unexpected!");
6144 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6145 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6146 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6147 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6148 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6149 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6152 SmallVector<int, 8> MaskVec;
6153 for (unsigned i = 0; i != NumElems; i += Scale) {
6155 for (unsigned j = 0; j != Scale; ++j) {
6156 int EltIdx = SVOp->getMaskElt(i+j);
6160 StartIdx = (EltIdx / Scale);
6161 if (EltIdx != (int)(StartIdx*Scale + j))
6164 MaskVec.push_back(StartIdx);
6167 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6168 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6169 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6172 /// getVZextMovL - Return a zero-extending vector move low node.
6174 static SDValue getVZextMovL(EVT VT, EVT OpVT,
6175 SDValue SrcOp, SelectionDAG &DAG,
6176 const X86Subtarget *Subtarget, DebugLoc dl) {
6177 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6178 LoadSDNode *LD = NULL;
6179 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6180 LD = dyn_cast<LoadSDNode>(SrcOp);
6182 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6184 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6185 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6186 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6187 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6188 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6190 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6191 return DAG.getNode(ISD::BITCAST, dl, VT,
6192 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6193 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6201 return DAG.getNode(ISD::BITCAST, dl, VT,
6202 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6203 DAG.getNode(ISD::BITCAST, dl,
6207 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6208 /// which could not be matched by any known target speficic shuffle
6210 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6212 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6213 if (NewOp.getNode())
6216 EVT VT = SVOp->getValueType(0);
6218 unsigned NumElems = VT.getVectorNumElements();
6219 unsigned NumLaneElems = NumElems / 2;
6221 DebugLoc dl = SVOp->getDebugLoc();
6222 MVT EltVT = VT.getVectorElementType().getSimpleVT();
6223 EVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6226 SmallVector<int, 16> Mask;
6227 for (unsigned l = 0; l < 2; ++l) {
6228 // Build a shuffle mask for the output, discovering on the fly which
6229 // input vectors to use as shuffle operands (recorded in InputUsed).
6230 // If building a suitable shuffle vector proves too hard, then bail
6231 // out with UseBuildVector set.
6232 bool UseBuildVector = false;
6233 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6234 unsigned LaneStart = l * NumLaneElems;
6235 for (unsigned i = 0; i != NumLaneElems; ++i) {
6236 // The mask element. This indexes into the input.
6237 int Idx = SVOp->getMaskElt(i+LaneStart);
6239 // the mask element does not index into any input vector.
6244 // The input vector this mask element indexes into.
6245 int Input = Idx / NumLaneElems;
6247 // Turn the index into an offset from the start of the input vector.
6248 Idx -= Input * NumLaneElems;
6250 // Find or create a shuffle vector operand to hold this input.
6252 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6253 if (InputUsed[OpNo] == Input)
6254 // This input vector is already an operand.
6256 if (InputUsed[OpNo] < 0) {
6257 // Create a new operand for this input vector.
6258 InputUsed[OpNo] = Input;
6263 if (OpNo >= array_lengthof(InputUsed)) {
6264 // More than two input vectors used! Give up on trying to create a
6265 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6266 UseBuildVector = true;
6270 // Add the mask index for the new shuffle vector.
6271 Mask.push_back(Idx + OpNo * NumLaneElems);
6274 if (UseBuildVector) {
6275 SmallVector<SDValue, 16> SVOps;
6276 for (unsigned i = 0; i != NumLaneElems; ++i) {
6277 // The mask element. This indexes into the input.
6278 int Idx = SVOp->getMaskElt(i+LaneStart);
6280 SVOps.push_back(DAG.getUNDEF(EltVT));
6284 // The input vector this mask element indexes into.
6285 int Input = Idx / NumElems;
6287 // Turn the index into an offset from the start of the input vector.
6288 Idx -= Input * NumElems;
6290 // Extract the vector element by hand.
6291 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6292 SVOp->getOperand(Input),
6293 DAG.getIntPtrConstant(Idx)));
6296 // Construct the output using a BUILD_VECTOR.
6297 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6299 } else if (InputUsed[0] < 0) {
6300 // No input vectors were used! The result is undefined.
6301 Output[l] = DAG.getUNDEF(NVT);
6303 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6304 (InputUsed[0] % 2) * NumLaneElems,
6306 // If only one input was used, use an undefined vector for the other.
6307 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6308 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6309 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6310 // At least one input vector was used. Create a new shuffle vector.
6311 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6317 // Concatenate the result back
6318 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6321 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6322 /// 4 elements, and match them with several different shuffle types.
6324 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6325 SDValue V1 = SVOp->getOperand(0);
6326 SDValue V2 = SVOp->getOperand(1);
6327 DebugLoc dl = SVOp->getDebugLoc();
6328 EVT VT = SVOp->getValueType(0);
6330 assert(VT.is128BitVector() && "Unsupported vector size");
6332 std::pair<int, int> Locs[4];
6333 int Mask1[] = { -1, -1, -1, -1 };
6334 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6338 for (unsigned i = 0; i != 4; ++i) {
6339 int Idx = PermMask[i];
6341 Locs[i] = std::make_pair(-1, -1);
6343 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6345 Locs[i] = std::make_pair(0, NumLo);
6349 Locs[i] = std::make_pair(1, NumHi);
6351 Mask1[2+NumHi] = Idx;
6357 if (NumLo <= 2 && NumHi <= 2) {
6358 // If no more than two elements come from either vector. This can be
6359 // implemented with two shuffles. First shuffle gather the elements.
6360 // The second shuffle, which takes the first shuffle as both of its
6361 // vector operands, put the elements into the right order.
6362 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6364 int Mask2[] = { -1, -1, -1, -1 };
6366 for (unsigned i = 0; i != 4; ++i)
6367 if (Locs[i].first != -1) {
6368 unsigned Idx = (i < 2) ? 0 : 4;
6369 Idx += Locs[i].first * 2 + Locs[i].second;
6373 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6376 if (NumLo == 3 || NumHi == 3) {
6377 // Otherwise, we must have three elements from one vector, call it X, and
6378 // one element from the other, call it Y. First, use a shufps to build an
6379 // intermediate vector with the one element from Y and the element from X
6380 // that will be in the same half in the final destination (the indexes don't
6381 // matter). Then, use a shufps to build the final vector, taking the half
6382 // containing the element from Y from the intermediate, and the other half
6385 // Normalize it so the 3 elements come from V1.
6386 CommuteVectorShuffleMask(PermMask, 4);
6390 // Find the element from V2.
6392 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6393 int Val = PermMask[HiIndex];
6400 Mask1[0] = PermMask[HiIndex];
6402 Mask1[2] = PermMask[HiIndex^1];
6404 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6407 Mask1[0] = PermMask[0];
6408 Mask1[1] = PermMask[1];
6409 Mask1[2] = HiIndex & 1 ? 6 : 4;
6410 Mask1[3] = HiIndex & 1 ? 4 : 6;
6411 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6414 Mask1[0] = HiIndex & 1 ? 2 : 0;
6415 Mask1[1] = HiIndex & 1 ? 0 : 2;
6416 Mask1[2] = PermMask[2];
6417 Mask1[3] = PermMask[3];
6422 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6425 // Break it into (shuffle shuffle_hi, shuffle_lo).
6426 int LoMask[] = { -1, -1, -1, -1 };
6427 int HiMask[] = { -1, -1, -1, -1 };
6429 int *MaskPtr = LoMask;
6430 unsigned MaskIdx = 0;
6433 for (unsigned i = 0; i != 4; ++i) {
6440 int Idx = PermMask[i];
6442 Locs[i] = std::make_pair(-1, -1);
6443 } else if (Idx < 4) {
6444 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6445 MaskPtr[LoIdx] = Idx;
6448 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6449 MaskPtr[HiIdx] = Idx;
6454 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6455 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6456 int MaskOps[] = { -1, -1, -1, -1 };
6457 for (unsigned i = 0; i != 4; ++i)
6458 if (Locs[i].first != -1)
6459 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6460 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6463 static bool MayFoldVectorLoad(SDValue V) {
6464 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6465 V = V.getOperand(0);
6467 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6468 V = V.getOperand(0);
6469 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6470 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6471 // BUILD_VECTOR (load), undef
6472 V = V.getOperand(0);
6474 return MayFoldLoad(V);
6478 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6479 EVT VT = Op.getValueType();
6481 // Canonizalize to v2f64.
6482 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6483 return DAG.getNode(ISD::BITCAST, dl, VT,
6484 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6489 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6491 SDValue V1 = Op.getOperand(0);
6492 SDValue V2 = Op.getOperand(1);
6493 EVT VT = Op.getValueType();
6495 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6497 if (HasSSE2 && VT == MVT::v2f64)
6498 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6500 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6501 return DAG.getNode(ISD::BITCAST, dl, VT,
6502 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6503 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6504 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6508 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6509 SDValue V1 = Op.getOperand(0);
6510 SDValue V2 = Op.getOperand(1);
6511 EVT VT = Op.getValueType();
6513 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6514 "unsupported shuffle type");
6516 if (V2.getOpcode() == ISD::UNDEF)
6520 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6524 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6525 SDValue V1 = Op.getOperand(0);
6526 SDValue V2 = Op.getOperand(1);
6527 EVT VT = Op.getValueType();
6528 unsigned NumElems = VT.getVectorNumElements();
6530 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6531 // operand of these instructions is only memory, so check if there's a
6532 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6534 bool CanFoldLoad = false;
6536 // Trivial case, when V2 comes from a load.
6537 if (MayFoldVectorLoad(V2))
6540 // When V1 is a load, it can be folded later into a store in isel, example:
6541 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6543 // (MOVLPSmr addr:$src1, VR128:$src2)
6544 // So, recognize this potential and also use MOVLPS or MOVLPD
6545 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6548 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6550 if (HasSSE2 && NumElems == 2)
6551 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6554 // If we don't care about the second element, proceed to use movss.
6555 if (SVOp->getMaskElt(1) != -1)
6556 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6559 // movl and movlp will both match v2i64, but v2i64 is never matched by
6560 // movl earlier because we make it strict to avoid messing with the movlp load
6561 // folding logic (see the code above getMOVLP call). Match it here then,
6562 // this is horrible, but will stay like this until we move all shuffle
6563 // matching to x86 specific nodes. Note that for the 1st condition all
6564 // types are matched with movsd.
6566 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6567 // as to remove this logic from here, as much as possible
6568 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6569 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6570 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6573 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6575 // Invert the operand order and use SHUFPS to match it.
6576 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6577 getShuffleSHUFImmediate(SVOp), DAG);
6580 // Reduce a vector shuffle to zext.
6582 X86TargetLowering::lowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
6583 // PMOVZX is only available from SSE41.
6584 if (!Subtarget->hasSSE41())
6587 EVT VT = Op.getValueType();
6589 // Only AVX2 support 256-bit vector integer extending.
6590 if (!Subtarget->hasInt256() && VT.is256BitVector())
6593 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6594 DebugLoc DL = Op.getDebugLoc();
6595 SDValue V1 = Op.getOperand(0);
6596 SDValue V2 = Op.getOperand(1);
6597 unsigned NumElems = VT.getVectorNumElements();
6599 // Extending is an unary operation and the element type of the source vector
6600 // won't be equal to or larger than i64.
6601 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6602 VT.getVectorElementType() == MVT::i64)
6605 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
6606 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
6607 while ((1U << Shift) < NumElems) {
6608 if (SVOp->getMaskElt(1U << Shift) == 1)
6611 // The maximal ratio is 8, i.e. from i8 to i64.
6616 // Check the shuffle mask.
6617 unsigned Mask = (1U << Shift) - 1;
6618 for (unsigned i = 0; i != NumElems; ++i) {
6619 int EltIdx = SVOp->getMaskElt(i);
6620 if ((i & Mask) != 0 && EltIdx != -1)
6622 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
6626 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
6627 EVT NeVT = EVT::getIntegerVT(*DAG.getContext(), NBits);
6628 EVT NVT = EVT::getVectorVT(*DAG.getContext(), NeVT, NumElems >> Shift);
6630 if (!isTypeLegal(NVT))
6633 // Simplify the operand as it's prepared to be fed into shuffle.
6634 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
6635 if (V1.getOpcode() == ISD::BITCAST &&
6636 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6637 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6639 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
6640 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
6641 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
6642 ConstantSDNode *CIdx =
6643 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
6644 // If it's foldable, i.e. normal load with single use, we will let code
6645 // selection to fold it. Otherwise, we will short the conversion sequence.
6646 if (CIdx && CIdx->getZExtValue() == 0 &&
6647 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse()))
6648 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6651 return DAG.getNode(ISD::BITCAST, DL, VT,
6652 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
6656 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6657 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6658 EVT VT = Op.getValueType();
6659 DebugLoc dl = Op.getDebugLoc();
6660 SDValue V1 = Op.getOperand(0);
6661 SDValue V2 = Op.getOperand(1);
6663 if (isZeroShuffle(SVOp))
6664 return getZeroVector(VT, Subtarget, DAG, dl);
6666 // Handle splat operations
6667 if (SVOp->isSplat()) {
6668 unsigned NumElem = VT.getVectorNumElements();
6669 int Size = VT.getSizeInBits();
6671 // Use vbroadcast whenever the splat comes from a foldable load
6672 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6673 if (Broadcast.getNode())
6676 // Handle splats by matching through known shuffle masks
6677 if ((Size == 128 && NumElem <= 4) ||
6678 (Size == 256 && NumElem <= 8))
6681 // All remaning splats are promoted to target supported vector shuffles.
6682 return PromoteSplat(SVOp, DAG);
6685 // Check integer expanding shuffles.
6686 SDValue NewOp = lowerVectorIntExtend(Op, DAG);
6687 if (NewOp.getNode())
6690 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6692 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6693 VT == MVT::v16i16 || VT == MVT::v32i8) {
6694 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6695 if (NewOp.getNode())
6696 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6697 } else if ((VT == MVT::v4i32 ||
6698 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6699 // FIXME: Figure out a cleaner way to do this.
6700 // Try to make use of movq to zero out the top part.
6701 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6702 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6703 if (NewOp.getNode()) {
6704 EVT NewVT = NewOp.getValueType();
6705 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6706 NewVT, true, false))
6707 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6708 DAG, Subtarget, dl);
6710 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6711 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl);
6712 if (NewOp.getNode()) {
6713 EVT NewVT = NewOp.getValueType();
6714 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6715 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6716 DAG, Subtarget, dl);
6724 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6725 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6726 SDValue V1 = Op.getOperand(0);
6727 SDValue V2 = Op.getOperand(1);
6728 EVT VT = Op.getValueType();
6729 DebugLoc dl = Op.getDebugLoc();
6730 unsigned NumElems = VT.getVectorNumElements();
6731 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6732 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6733 bool V1IsSplat = false;
6734 bool V2IsSplat = false;
6735 bool HasSSE2 = Subtarget->hasSSE2();
6736 bool HasFp256 = Subtarget->hasFp256();
6737 bool HasInt256 = Subtarget->hasInt256();
6738 MachineFunction &MF = DAG.getMachineFunction();
6739 bool OptForSize = MF.getFunction()->getAttributes().
6740 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6742 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6744 if (V1IsUndef && V2IsUndef)
6745 return DAG.getUNDEF(VT);
6747 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6749 // Vector shuffle lowering takes 3 steps:
6751 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6752 // narrowing and commutation of operands should be handled.
6753 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6755 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6756 // so the shuffle can be broken into other shuffles and the legalizer can
6757 // try the lowering again.
6759 // The general idea is that no vector_shuffle operation should be left to
6760 // be matched during isel, all of them must be converted to a target specific
6763 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6764 // narrowing and commutation of operands should be handled. The actual code
6765 // doesn't include all of those, work in progress...
6766 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6767 if (NewOp.getNode())
6770 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6772 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6773 // unpckh_undef). Only use pshufd if speed is more important than size.
6774 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6775 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6776 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6777 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6779 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6780 V2IsUndef && MayFoldVectorLoad(V1))
6781 return getMOVDDup(Op, dl, V1, DAG);
6783 if (isMOVHLPS_v_undef_Mask(M, VT))
6784 return getMOVHighToLow(Op, dl, DAG);
6786 // Use to match splats
6787 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
6788 (VT == MVT::v2f64 || VT == MVT::v2i64))
6789 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6791 if (isPSHUFDMask(M, VT)) {
6792 // The actual implementation will match the mask in the if above and then
6793 // during isel it can match several different instructions, not only pshufd
6794 // as its name says, sad but true, emulate the behavior for now...
6795 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6796 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6798 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6800 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6801 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6803 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
6804 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
6807 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6811 // Check if this can be converted into a logical shift.
6812 bool isLeft = false;
6815 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6816 if (isShift && ShVal.hasOneUse()) {
6817 // If the shifted value has multiple uses, it may be cheaper to use
6818 // v_set0 + movlhps or movhlps, etc.
6819 EVT EltVT = VT.getVectorElementType();
6820 ShAmt *= EltVT.getSizeInBits();
6821 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6824 if (isMOVLMask(M, VT)) {
6825 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6826 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6827 if (!isMOVLPMask(M, VT)) {
6828 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6829 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6831 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6832 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6836 // FIXME: fold these into legal mask.
6837 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
6838 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6840 if (isMOVHLPSMask(M, VT))
6841 return getMOVHighToLow(Op, dl, DAG);
6843 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6844 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6846 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6847 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6849 if (isMOVLPMask(M, VT))
6850 return getMOVLP(Op, dl, DAG, HasSSE2);
6852 if (ShouldXformToMOVHLPS(M, VT) ||
6853 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6854 return CommuteVectorShuffle(SVOp, DAG);
6857 // No better options. Use a vshldq / vsrldq.
6858 EVT EltVT = VT.getVectorElementType();
6859 ShAmt *= EltVT.getSizeInBits();
6860 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6863 bool Commuted = false;
6864 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6865 // 1,1,1,1 -> v8i16 though.
6866 V1IsSplat = isSplatVector(V1.getNode());
6867 V2IsSplat = isSplatVector(V2.getNode());
6869 // Canonicalize the splat or undef, if present, to be on the RHS.
6870 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6871 CommuteVectorShuffleMask(M, NumElems);
6873 std::swap(V1IsSplat, V2IsSplat);
6877 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6878 // Shuffling low element of v1 into undef, just return v1.
6881 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6882 // the instruction selector will not match, so get a canonical MOVL with
6883 // swapped operands to undo the commute.
6884 return getMOVL(DAG, dl, VT, V2, V1);
6887 if (isUNPCKLMask(M, VT, HasInt256))
6888 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6890 if (isUNPCKHMask(M, VT, HasInt256))
6891 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6894 // Normalize mask so all entries that point to V2 points to its first
6895 // element then try to match unpck{h|l} again. If match, return a
6896 // new vector_shuffle with the corrected mask.p
6897 SmallVector<int, 8> NewMask(M.begin(), M.end());
6898 NormalizeMask(NewMask, NumElems);
6899 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
6900 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6901 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
6902 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6906 // Commute is back and try unpck* again.
6907 // FIXME: this seems wrong.
6908 CommuteVectorShuffleMask(M, NumElems);
6910 std::swap(V1IsSplat, V2IsSplat);
6913 if (isUNPCKLMask(M, VT, HasInt256))
6914 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6916 if (isUNPCKHMask(M, VT, HasInt256))
6917 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6920 // Normalize the node to match x86 shuffle ops if needed
6921 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
6922 return CommuteVectorShuffle(SVOp, DAG);
6924 // The checks below are all present in isShuffleMaskLegal, but they are
6925 // inlined here right now to enable us to directly emit target specific
6926 // nodes, and remove one by one until they don't return Op anymore.
6928 if (isPALIGNRMask(M, VT, Subtarget))
6929 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
6930 getShufflePALIGNRImmediate(SVOp),
6933 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
6934 SVOp->getSplatIndex() == 0 && V2IsUndef) {
6935 if (VT == MVT::v2f64 || VT == MVT::v2i64)
6936 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6939 if (isPSHUFHWMask(M, VT, HasInt256))
6940 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
6941 getShufflePSHUFHWImmediate(SVOp),
6944 if (isPSHUFLWMask(M, VT, HasInt256))
6945 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
6946 getShufflePSHUFLWImmediate(SVOp),
6949 if (isSHUFPMask(M, VT, HasFp256))
6950 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
6951 getShuffleSHUFImmediate(SVOp), DAG);
6953 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6954 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6955 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6956 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6958 //===--------------------------------------------------------------------===//
6959 // Generate target specific nodes for 128 or 256-bit shuffles only
6960 // supported in the AVX instruction set.
6963 // Handle VMOVDDUPY permutations
6964 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
6965 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
6967 // Handle VPERMILPS/D* permutations
6968 if (isVPERMILPMask(M, VT, HasFp256)) {
6969 if (HasInt256 && VT == MVT::v8i32)
6970 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
6971 getShuffleSHUFImmediate(SVOp), DAG);
6972 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
6973 getShuffleSHUFImmediate(SVOp), DAG);
6976 // Handle VPERM2F128/VPERM2I128 permutations
6977 if (isVPERM2X128Mask(M, VT, HasFp256))
6978 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
6979 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
6981 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
6982 if (BlendOp.getNode())
6985 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
6986 SmallVector<SDValue, 8> permclMask;
6987 for (unsigned i = 0; i != 8; ++i) {
6988 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
6990 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
6992 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
6993 return DAG.getNode(X86ISD::VPERMV, dl, VT,
6994 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
6997 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
6998 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
6999 getShuffleCLImmediate(SVOp), DAG);
7001 //===--------------------------------------------------------------------===//
7002 // Since no target specific shuffle was selected for this generic one,
7003 // lower it into other known shuffles. FIXME: this isn't true yet, but
7004 // this is the plan.
7007 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7008 if (VT == MVT::v8i16) {
7009 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7010 if (NewOp.getNode())
7014 if (VT == MVT::v16i8) {
7015 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7016 if (NewOp.getNode())
7020 if (VT == MVT::v32i8) {
7021 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7022 if (NewOp.getNode())
7026 // Handle all 128-bit wide vectors with 4 elements, and match them with
7027 // several different shuffle types.
7028 if (NumElems == 4 && VT.is128BitVector())
7029 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7031 // Handle general 256-bit shuffles
7032 if (VT.is256BitVector())
7033 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7039 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
7040 SelectionDAG &DAG) const {
7041 EVT VT = Op.getValueType();
7042 DebugLoc dl = Op.getDebugLoc();
7044 if (!Op.getOperand(0).getValueType().is128BitVector())
7047 if (VT.getSizeInBits() == 8) {
7048 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7049 Op.getOperand(0), Op.getOperand(1));
7050 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7051 DAG.getValueType(VT));
7052 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7055 if (VT.getSizeInBits() == 16) {
7056 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7057 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7059 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7060 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7061 DAG.getNode(ISD::BITCAST, dl,
7065 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7066 Op.getOperand(0), Op.getOperand(1));
7067 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7068 DAG.getValueType(VT));
7069 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7072 if (VT == MVT::f32) {
7073 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7074 // the result back to FR32 register. It's only worth matching if the
7075 // result has a single use which is a store or a bitcast to i32. And in
7076 // the case of a store, it's not worth it if the index is a constant 0,
7077 // because a MOVSSmr can be used instead, which is smaller and faster.
7078 if (!Op.hasOneUse())
7080 SDNode *User = *Op.getNode()->use_begin();
7081 if ((User->getOpcode() != ISD::STORE ||
7082 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7083 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7084 (User->getOpcode() != ISD::BITCAST ||
7085 User->getValueType(0) != MVT::i32))
7087 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7088 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7091 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7094 if (VT == MVT::i32 || VT == MVT::i64) {
7095 // ExtractPS/pextrq works with constant index.
7096 if (isa<ConstantSDNode>(Op.getOperand(1)))
7103 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7104 SelectionDAG &DAG) const {
7105 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7108 SDValue Vec = Op.getOperand(0);
7109 EVT VecVT = Vec.getValueType();
7111 // If this is a 256-bit vector result, first extract the 128-bit vector and
7112 // then extract the element from the 128-bit vector.
7113 if (VecVT.is256BitVector()) {
7114 DebugLoc dl = Op.getNode()->getDebugLoc();
7115 unsigned NumElems = VecVT.getVectorNumElements();
7116 SDValue Idx = Op.getOperand(1);
7117 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7119 // Get the 128-bit vector.
7120 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7122 if (IdxVal >= NumElems/2)
7123 IdxVal -= NumElems/2;
7124 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7125 DAG.getConstant(IdxVal, MVT::i32));
7128 assert(VecVT.is128BitVector() && "Unexpected vector length");
7130 if (Subtarget->hasSSE41()) {
7131 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7136 EVT VT = Op.getValueType();
7137 DebugLoc dl = Op.getDebugLoc();
7138 // TODO: handle v16i8.
7139 if (VT.getSizeInBits() == 16) {
7140 SDValue Vec = Op.getOperand(0);
7141 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7143 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7144 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7145 DAG.getNode(ISD::BITCAST, dl,
7148 // Transform it so it match pextrw which produces a 32-bit result.
7149 EVT EltVT = MVT::i32;
7150 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7151 Op.getOperand(0), Op.getOperand(1));
7152 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7153 DAG.getValueType(VT));
7154 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7157 if (VT.getSizeInBits() == 32) {
7158 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7162 // SHUFPS the element to the lowest double word, then movss.
7163 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7164 EVT VVT = Op.getOperand(0).getValueType();
7165 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7166 DAG.getUNDEF(VVT), Mask);
7167 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7168 DAG.getIntPtrConstant(0));
7171 if (VT.getSizeInBits() == 64) {
7172 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7173 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7174 // to match extract_elt for f64.
7175 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7179 // UNPCKHPD the element to the lowest double word, then movsd.
7180 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7181 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7182 int Mask[2] = { 1, -1 };
7183 EVT VVT = Op.getOperand(0).getValueType();
7184 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7185 DAG.getUNDEF(VVT), Mask);
7186 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7187 DAG.getIntPtrConstant(0));
7194 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op,
7195 SelectionDAG &DAG) const {
7196 EVT VT = Op.getValueType();
7197 EVT EltVT = VT.getVectorElementType();
7198 DebugLoc dl = Op.getDebugLoc();
7200 SDValue N0 = Op.getOperand(0);
7201 SDValue N1 = Op.getOperand(1);
7202 SDValue N2 = Op.getOperand(2);
7204 if (!VT.is128BitVector())
7207 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7208 isa<ConstantSDNode>(N2)) {
7210 if (VT == MVT::v8i16)
7211 Opc = X86ISD::PINSRW;
7212 else if (VT == MVT::v16i8)
7213 Opc = X86ISD::PINSRB;
7215 Opc = X86ISD::PINSRB;
7217 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7219 if (N1.getValueType() != MVT::i32)
7220 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7221 if (N2.getValueType() != MVT::i32)
7222 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7223 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7226 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7227 // Bits [7:6] of the constant are the source select. This will always be
7228 // zero here. The DAG Combiner may combine an extract_elt index into these
7229 // bits. For example (insert (extract, 3), 2) could be matched by putting
7230 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7231 // Bits [5:4] of the constant are the destination select. This is the
7232 // value of the incoming immediate.
7233 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7234 // combine either bitwise AND or insert of float 0.0 to set these bits.
7235 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7236 // Create this as a scalar to vector..
7237 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7238 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7241 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7242 // PINSR* works with constant index.
7249 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7250 EVT VT = Op.getValueType();
7251 EVT EltVT = VT.getVectorElementType();
7253 DebugLoc dl = Op.getDebugLoc();
7254 SDValue N0 = Op.getOperand(0);
7255 SDValue N1 = Op.getOperand(1);
7256 SDValue N2 = Op.getOperand(2);
7258 // If this is a 256-bit vector result, first extract the 128-bit vector,
7259 // insert the element into the extracted half and then place it back.
7260 if (VT.is256BitVector()) {
7261 if (!isa<ConstantSDNode>(N2))
7264 // Get the desired 128-bit vector half.
7265 unsigned NumElems = VT.getVectorNumElements();
7266 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7267 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7269 // Insert the element into the desired half.
7270 bool Upper = IdxVal >= NumElems/2;
7271 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7272 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7274 // Insert the changed part back to the 256-bit vector
7275 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7278 if (Subtarget->hasSSE41())
7279 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7281 if (EltVT == MVT::i8)
7284 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7285 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7286 // as its second argument.
7287 if (N1.getValueType() != MVT::i32)
7288 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7289 if (N2.getValueType() != MVT::i32)
7290 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7291 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7296 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7297 LLVMContext *Context = DAG.getContext();
7298 DebugLoc dl = Op.getDebugLoc();
7299 EVT OpVT = Op.getValueType();
7301 // If this is a 256-bit vector result, first insert into a 128-bit
7302 // vector and then insert into the 256-bit vector.
7303 if (!OpVT.is128BitVector()) {
7304 // Insert into a 128-bit vector.
7305 EVT VT128 = EVT::getVectorVT(*Context,
7306 OpVT.getVectorElementType(),
7307 OpVT.getVectorNumElements() / 2);
7309 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7311 // Insert the 128-bit vector.
7312 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7315 if (OpVT == MVT::v1i64 &&
7316 Op.getOperand(0).getValueType() == MVT::i64)
7317 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7319 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7320 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7321 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7322 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7325 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7326 // a simple subregister reference or explicit instructions to grab
7327 // upper bits of a vector.
7328 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7329 SelectionDAG &DAG) {
7330 if (Subtarget->hasFp256()) {
7331 DebugLoc dl = Op.getNode()->getDebugLoc();
7332 SDValue Vec = Op.getNode()->getOperand(0);
7333 SDValue Idx = Op.getNode()->getOperand(1);
7335 if (Op.getNode()->getValueType(0).is128BitVector() &&
7336 Vec.getNode()->getValueType(0).is256BitVector() &&
7337 isa<ConstantSDNode>(Idx)) {
7338 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7339 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7345 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7346 // simple superregister reference or explicit instructions to insert
7347 // the upper bits of a vector.
7348 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7349 SelectionDAG &DAG) {
7350 if (Subtarget->hasFp256()) {
7351 DebugLoc dl = Op.getNode()->getDebugLoc();
7352 SDValue Vec = Op.getNode()->getOperand(0);
7353 SDValue SubVec = Op.getNode()->getOperand(1);
7354 SDValue Idx = Op.getNode()->getOperand(2);
7356 if (Op.getNode()->getValueType(0).is256BitVector() &&
7357 SubVec.getNode()->getValueType(0).is128BitVector() &&
7358 isa<ConstantSDNode>(Idx)) {
7359 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7360 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7366 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7367 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7368 // one of the above mentioned nodes. It has to be wrapped because otherwise
7369 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7370 // be used to form addressing mode. These wrapped nodes will be selected
7373 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7374 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7376 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7378 unsigned char OpFlag = 0;
7379 unsigned WrapperKind = X86ISD::Wrapper;
7380 CodeModel::Model M = getTargetMachine().getCodeModel();
7382 if (Subtarget->isPICStyleRIPRel() &&
7383 (M == CodeModel::Small || M == CodeModel::Kernel))
7384 WrapperKind = X86ISD::WrapperRIP;
7385 else if (Subtarget->isPICStyleGOT())
7386 OpFlag = X86II::MO_GOTOFF;
7387 else if (Subtarget->isPICStyleStubPIC())
7388 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7390 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7392 CP->getOffset(), OpFlag);
7393 DebugLoc DL = CP->getDebugLoc();
7394 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7395 // With PIC, the address is actually $g + Offset.
7397 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7398 DAG.getNode(X86ISD::GlobalBaseReg,
7399 DebugLoc(), getPointerTy()),
7406 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7407 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7409 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7411 unsigned char OpFlag = 0;
7412 unsigned WrapperKind = X86ISD::Wrapper;
7413 CodeModel::Model M = getTargetMachine().getCodeModel();
7415 if (Subtarget->isPICStyleRIPRel() &&
7416 (M == CodeModel::Small || M == CodeModel::Kernel))
7417 WrapperKind = X86ISD::WrapperRIP;
7418 else if (Subtarget->isPICStyleGOT())
7419 OpFlag = X86II::MO_GOTOFF;
7420 else if (Subtarget->isPICStyleStubPIC())
7421 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7423 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7425 DebugLoc DL = JT->getDebugLoc();
7426 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7428 // With PIC, the address is actually $g + Offset.
7430 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7431 DAG.getNode(X86ISD::GlobalBaseReg,
7432 DebugLoc(), getPointerTy()),
7439 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7440 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7442 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7444 unsigned char OpFlag = 0;
7445 unsigned WrapperKind = X86ISD::Wrapper;
7446 CodeModel::Model M = getTargetMachine().getCodeModel();
7448 if (Subtarget->isPICStyleRIPRel() &&
7449 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7450 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7451 OpFlag = X86II::MO_GOTPCREL;
7452 WrapperKind = X86ISD::WrapperRIP;
7453 } else if (Subtarget->isPICStyleGOT()) {
7454 OpFlag = X86II::MO_GOT;
7455 } else if (Subtarget->isPICStyleStubPIC()) {
7456 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7457 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7458 OpFlag = X86II::MO_DARWIN_NONLAZY;
7461 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7463 DebugLoc DL = Op.getDebugLoc();
7464 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7466 // With PIC, the address is actually $g + Offset.
7467 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7468 !Subtarget->is64Bit()) {
7469 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7470 DAG.getNode(X86ISD::GlobalBaseReg,
7471 DebugLoc(), getPointerTy()),
7475 // For symbols that require a load from a stub to get the address, emit the
7477 if (isGlobalStubReference(OpFlag))
7478 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7479 MachinePointerInfo::getGOT(), false, false, false, 0);
7485 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7486 // Create the TargetBlockAddressAddress node.
7487 unsigned char OpFlags =
7488 Subtarget->ClassifyBlockAddressReference();
7489 CodeModel::Model M = getTargetMachine().getCodeModel();
7490 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7491 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7492 DebugLoc dl = Op.getDebugLoc();
7493 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7496 if (Subtarget->isPICStyleRIPRel() &&
7497 (M == CodeModel::Small || M == CodeModel::Kernel))
7498 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7500 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7502 // With PIC, the address is actually $g + Offset.
7503 if (isGlobalRelativeToPICBase(OpFlags)) {
7504 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7505 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7513 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7515 SelectionDAG &DAG) const {
7516 // Create the TargetGlobalAddress node, folding in the constant
7517 // offset if it is legal.
7518 unsigned char OpFlags =
7519 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7520 CodeModel::Model M = getTargetMachine().getCodeModel();
7522 if (OpFlags == X86II::MO_NO_FLAG &&
7523 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7524 // A direct static reference to a global.
7525 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7528 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7531 if (Subtarget->isPICStyleRIPRel() &&
7532 (M == CodeModel::Small || M == CodeModel::Kernel))
7533 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7535 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7537 // With PIC, the address is actually $g + Offset.
7538 if (isGlobalRelativeToPICBase(OpFlags)) {
7539 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7540 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7544 // For globals that require a load from a stub to get the address, emit the
7546 if (isGlobalStubReference(OpFlags))
7547 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7548 MachinePointerInfo::getGOT(), false, false, false, 0);
7550 // If there was a non-zero offset that we didn't fold, create an explicit
7553 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7554 DAG.getConstant(Offset, getPointerTy()));
7560 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7561 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7562 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7563 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7567 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7568 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7569 unsigned char OperandFlags, bool LocalDynamic = false) {
7570 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7571 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7572 DebugLoc dl = GA->getDebugLoc();
7573 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7574 GA->getValueType(0),
7578 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7582 SDValue Ops[] = { Chain, TGA, *InFlag };
7583 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 3);
7585 SDValue Ops[] = { Chain, TGA };
7586 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, 2);
7589 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7590 MFI->setAdjustsStack(true);
7592 SDValue Flag = Chain.getValue(1);
7593 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7596 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7598 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7601 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7602 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7603 DAG.getNode(X86ISD::GlobalBaseReg,
7604 DebugLoc(), PtrVT), InFlag);
7605 InFlag = Chain.getValue(1);
7607 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7610 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7612 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7614 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7615 X86::RAX, X86II::MO_TLSGD);
7618 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7622 DebugLoc dl = GA->getDebugLoc();
7624 // Get the start address of the TLS block for this module.
7625 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7626 .getInfo<X86MachineFunctionInfo>();
7627 MFI->incNumLocalDynamicTLSAccesses();
7631 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7632 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7635 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7636 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7637 InFlag = Chain.getValue(1);
7638 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7639 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7642 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7646 unsigned char OperandFlags = X86II::MO_DTPOFF;
7647 unsigned WrapperKind = X86ISD::Wrapper;
7648 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7649 GA->getValueType(0),
7650 GA->getOffset(), OperandFlags);
7651 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7653 // Add x@dtpoff with the base.
7654 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7657 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7658 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7659 const EVT PtrVT, TLSModel::Model model,
7660 bool is64Bit, bool isPIC) {
7661 DebugLoc dl = GA->getDebugLoc();
7663 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7664 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7665 is64Bit ? 257 : 256));
7667 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7668 DAG.getIntPtrConstant(0),
7669 MachinePointerInfo(Ptr),
7670 false, false, false, 0);
7672 unsigned char OperandFlags = 0;
7673 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7675 unsigned WrapperKind = X86ISD::Wrapper;
7676 if (model == TLSModel::LocalExec) {
7677 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7678 } else if (model == TLSModel::InitialExec) {
7680 OperandFlags = X86II::MO_GOTTPOFF;
7681 WrapperKind = X86ISD::WrapperRIP;
7683 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7686 llvm_unreachable("Unexpected model");
7689 // emit "addl x@ntpoff,%eax" (local exec)
7690 // or "addl x@indntpoff,%eax" (initial exec)
7691 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7692 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7693 GA->getValueType(0),
7694 GA->getOffset(), OperandFlags);
7695 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7697 if (model == TLSModel::InitialExec) {
7698 if (isPIC && !is64Bit) {
7699 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7700 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7704 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7705 MachinePointerInfo::getGOT(), false, false, false,
7709 // The address of the thread local variable is the add of the thread
7710 // pointer with the offset of the variable.
7711 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7715 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7717 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7718 const GlobalValue *GV = GA->getGlobal();
7720 if (Subtarget->isTargetELF()) {
7721 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7724 case TLSModel::GeneralDynamic:
7725 if (Subtarget->is64Bit())
7726 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7727 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7728 case TLSModel::LocalDynamic:
7729 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7730 Subtarget->is64Bit());
7731 case TLSModel::InitialExec:
7732 case TLSModel::LocalExec:
7733 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7734 Subtarget->is64Bit(),
7735 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7737 llvm_unreachable("Unknown TLS model.");
7740 if (Subtarget->isTargetDarwin()) {
7741 // Darwin only has one model of TLS. Lower to that.
7742 unsigned char OpFlag = 0;
7743 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7744 X86ISD::WrapperRIP : X86ISD::Wrapper;
7746 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7748 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7749 !Subtarget->is64Bit();
7751 OpFlag = X86II::MO_TLVP_PIC_BASE;
7753 OpFlag = X86II::MO_TLVP;
7754 DebugLoc DL = Op.getDebugLoc();
7755 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7756 GA->getValueType(0),
7757 GA->getOffset(), OpFlag);
7758 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7760 // With PIC32, the address is actually $g + Offset.
7762 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7763 DAG.getNode(X86ISD::GlobalBaseReg,
7764 DebugLoc(), getPointerTy()),
7767 // Lowering the machine isd will make sure everything is in the right
7769 SDValue Chain = DAG.getEntryNode();
7770 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7771 SDValue Args[] = { Chain, Offset };
7772 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7774 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7775 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7776 MFI->setAdjustsStack(true);
7778 // And our return value (tls address) is in the standard call return value
7780 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7781 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7785 if (Subtarget->isTargetWindows()) {
7786 // Just use the implicit TLS architecture
7787 // Need to generate someting similar to:
7788 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7790 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7791 // mov rcx, qword [rdx+rcx*8]
7792 // mov eax, .tls$:tlsvar
7793 // [rax+rcx] contains the address
7794 // Windows 64bit: gs:0x58
7795 // Windows 32bit: fs:__tls_array
7797 // If GV is an alias then use the aliasee for determining
7798 // thread-localness.
7799 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7800 GV = GA->resolveAliasedGlobal(false);
7801 DebugLoc dl = GA->getDebugLoc();
7802 SDValue Chain = DAG.getEntryNode();
7804 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7805 // %gs:0x58 (64-bit).
7806 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7807 ? Type::getInt8PtrTy(*DAG.getContext(),
7809 : Type::getInt32PtrTy(*DAG.getContext(),
7812 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain,
7813 Subtarget->is64Bit()
7814 ? DAG.getIntPtrConstant(0x58)
7815 : DAG.getExternalSymbol("_tls_array",
7817 MachinePointerInfo(Ptr),
7818 false, false, false, 0);
7820 // Load the _tls_index variable
7821 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7822 if (Subtarget->is64Bit())
7823 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7824 IDX, MachinePointerInfo(), MVT::i32,
7827 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7828 false, false, false, 0);
7830 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7832 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7834 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7835 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7836 false, false, false, 0);
7838 // Get the offset of start of .tls section
7839 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7840 GA->getValueType(0),
7841 GA->getOffset(), X86II::MO_SECREL);
7842 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7844 // The address of the thread local variable is the add of the thread
7845 // pointer with the offset of the variable.
7846 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7849 llvm_unreachable("TLS not implemented for this target.");
7852 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7853 /// and take a 2 x i32 value to shift plus a shift amount.
7854 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7855 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7856 EVT VT = Op.getValueType();
7857 unsigned VTBits = VT.getSizeInBits();
7858 DebugLoc dl = Op.getDebugLoc();
7859 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7860 SDValue ShOpLo = Op.getOperand(0);
7861 SDValue ShOpHi = Op.getOperand(1);
7862 SDValue ShAmt = Op.getOperand(2);
7863 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7864 DAG.getConstant(VTBits - 1, MVT::i8))
7865 : DAG.getConstant(0, VT);
7868 if (Op.getOpcode() == ISD::SHL_PARTS) {
7869 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7870 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7872 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7873 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7876 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7877 DAG.getConstant(VTBits, MVT::i8));
7878 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7879 AndNode, DAG.getConstant(0, MVT::i8));
7882 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7883 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7884 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7886 if (Op.getOpcode() == ISD::SHL_PARTS) {
7887 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7888 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7890 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7891 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7894 SDValue Ops[2] = { Lo, Hi };
7895 return DAG.getMergeValues(Ops, 2, dl);
7898 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7899 SelectionDAG &DAG) const {
7900 EVT SrcVT = Op.getOperand(0).getValueType();
7902 if (SrcVT.isVector())
7905 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7906 "Unknown SINT_TO_FP to lower!");
7908 // These are really Legal; return the operand so the caller accepts it as
7910 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7912 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7913 Subtarget->is64Bit()) {
7917 DebugLoc dl = Op.getDebugLoc();
7918 unsigned Size = SrcVT.getSizeInBits()/8;
7919 MachineFunction &MF = DAG.getMachineFunction();
7920 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7921 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7922 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7924 MachinePointerInfo::getFixedStack(SSFI),
7926 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7929 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
7931 SelectionDAG &DAG) const {
7933 DebugLoc DL = Op.getDebugLoc();
7935 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
7937 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
7939 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
7941 unsigned ByteSize = SrcVT.getSizeInBits()/8;
7943 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
7944 MachineMemOperand *MMO;
7946 int SSFI = FI->getIndex();
7948 DAG.getMachineFunction()
7949 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7950 MachineMemOperand::MOLoad, ByteSize, ByteSize);
7952 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
7953 StackSlot = StackSlot.getOperand(1);
7955 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
7956 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
7958 Tys, Ops, array_lengthof(Ops),
7962 Chain = Result.getValue(1);
7963 SDValue InFlag = Result.getValue(2);
7965 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
7966 // shouldn't be necessary except that RFP cannot be live across
7967 // multiple blocks. When stackifier is fixed, they can be uncoupled.
7968 MachineFunction &MF = DAG.getMachineFunction();
7969 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
7970 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
7971 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7972 Tys = DAG.getVTList(MVT::Other);
7974 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
7976 MachineMemOperand *MMO =
7977 DAG.getMachineFunction()
7978 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
7979 MachineMemOperand::MOStore, SSFISize, SSFISize);
7981 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
7982 Ops, array_lengthof(Ops),
7983 Op.getValueType(), MMO);
7984 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
7985 MachinePointerInfo::getFixedStack(SSFI),
7986 false, false, false, 0);
7992 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
7993 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
7994 SelectionDAG &DAG) const {
7995 // This algorithm is not obvious. Here it is what we're trying to output:
7998 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
7999 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8003 pshufd $0x4e, %xmm0, %xmm1
8008 DebugLoc dl = Op.getDebugLoc();
8009 LLVMContext *Context = DAG.getContext();
8011 // Build some magic constants.
8012 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8013 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8014 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8016 SmallVector<Constant*,2> CV1;
8018 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
8020 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
8021 Constant *C1 = ConstantVector::get(CV1);
8022 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8024 // Load the 64-bit value into an XMM register.
8025 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8027 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8028 MachinePointerInfo::getConstantPool(),
8029 false, false, false, 16);
8030 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8031 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8034 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8035 MachinePointerInfo::getConstantPool(),
8036 false, false, false, 16);
8037 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8038 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8041 if (Subtarget->hasSSE3()) {
8042 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8043 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8045 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8046 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8048 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8049 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8053 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8054 DAG.getIntPtrConstant(0));
8057 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8058 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8059 SelectionDAG &DAG) const {
8060 DebugLoc dl = Op.getDebugLoc();
8061 // FP constant to bias correct the final result.
8062 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8065 // Load the 32-bit value into an XMM register.
8066 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8069 // Zero out the upper parts of the register.
8070 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8072 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8073 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8074 DAG.getIntPtrConstant(0));
8076 // Or the load with the bias.
8077 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8078 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8079 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8081 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8082 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8083 MVT::v2f64, Bias)));
8084 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8085 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8086 DAG.getIntPtrConstant(0));
8088 // Subtract the bias.
8089 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8091 // Handle final rounding.
8092 EVT DestVT = Op.getValueType();
8094 if (DestVT.bitsLT(MVT::f64))
8095 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8096 DAG.getIntPtrConstant(0));
8097 if (DestVT.bitsGT(MVT::f64))
8098 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8100 // Handle final rounding.
8104 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8105 SelectionDAG &DAG) const {
8106 SDValue N0 = Op.getOperand(0);
8107 EVT SVT = N0.getValueType();
8108 DebugLoc dl = Op.getDebugLoc();
8110 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8111 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8112 "Custom UINT_TO_FP is not supported!");
8114 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, SVT.getVectorNumElements());
8115 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8116 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8119 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8120 SelectionDAG &DAG) const {
8121 SDValue N0 = Op.getOperand(0);
8122 DebugLoc dl = Op.getDebugLoc();
8124 if (Op.getValueType().isVector())
8125 return lowerUINT_TO_FP_vec(Op, DAG);
8127 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8128 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8129 // the optimization here.
8130 if (DAG.SignBitIsZero(N0))
8131 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8133 EVT SrcVT = N0.getValueType();
8134 EVT DstVT = Op.getValueType();
8135 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8136 return LowerUINT_TO_FP_i64(Op, DAG);
8137 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8138 return LowerUINT_TO_FP_i32(Op, DAG);
8139 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8142 // Make a 64-bit buffer, and use it to build an FILD.
8143 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8144 if (SrcVT == MVT::i32) {
8145 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8146 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8147 getPointerTy(), StackSlot, WordOff);
8148 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8149 StackSlot, MachinePointerInfo(),
8151 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8152 OffsetSlot, MachinePointerInfo(),
8154 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8158 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8159 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8160 StackSlot, MachinePointerInfo(),
8162 // For i64 source, we need to add the appropriate power of 2 if the input
8163 // was negative. This is the same as the optimization in
8164 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8165 // we must be careful to do the computation in x87 extended precision, not
8166 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8167 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8168 MachineMemOperand *MMO =
8169 DAG.getMachineFunction()
8170 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8171 MachineMemOperand::MOLoad, 8, 8);
8173 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8174 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8175 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
8178 APInt FF(32, 0x5F800000ULL);
8180 // Check whether the sign bit is set.
8181 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
8182 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8185 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8186 SDValue FudgePtr = DAG.getConstantPool(
8187 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8190 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8191 SDValue Zero = DAG.getIntPtrConstant(0);
8192 SDValue Four = DAG.getIntPtrConstant(4);
8193 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8195 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8197 // Load the value out, extending it from f32 to f80.
8198 // FIXME: Avoid the extend by constructing the right constant pool?
8199 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8200 FudgePtr, MachinePointerInfo::getConstantPool(),
8201 MVT::f32, false, false, 4);
8202 // Extend everything to 80 bits to force it to be done on x87.
8203 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8204 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8207 std::pair<SDValue,SDValue> X86TargetLowering::
8208 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned, bool IsReplace) const {
8209 DebugLoc DL = Op.getDebugLoc();
8211 EVT DstTy = Op.getValueType();
8213 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8214 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8218 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8219 DstTy.getSimpleVT() >= MVT::i16 &&
8220 "Unknown FP_TO_INT to lower!");
8222 // These are really Legal.
8223 if (DstTy == MVT::i32 &&
8224 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8225 return std::make_pair(SDValue(), SDValue());
8226 if (Subtarget->is64Bit() &&
8227 DstTy == MVT::i64 &&
8228 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8229 return std::make_pair(SDValue(), SDValue());
8231 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8232 // stack slot, or into the FTOL runtime function.
8233 MachineFunction &MF = DAG.getMachineFunction();
8234 unsigned MemSize = DstTy.getSizeInBits()/8;
8235 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8236 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8239 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8240 Opc = X86ISD::WIN_FTOL;
8242 switch (DstTy.getSimpleVT().SimpleTy) {
8243 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8244 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8245 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8246 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8249 SDValue Chain = DAG.getEntryNode();
8250 SDValue Value = Op.getOperand(0);
8251 EVT TheVT = Op.getOperand(0).getValueType();
8252 // FIXME This causes a redundant load/store if the SSE-class value is already
8253 // in memory, such as if it is on the callstack.
8254 if (isScalarFPTypeInSSEReg(TheVT)) {
8255 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8256 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8257 MachinePointerInfo::getFixedStack(SSFI),
8259 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8261 Chain, StackSlot, DAG.getValueType(TheVT)
8264 MachineMemOperand *MMO =
8265 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8266 MachineMemOperand::MOLoad, MemSize, MemSize);
8267 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3,
8269 Chain = Value.getValue(1);
8270 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8271 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8274 MachineMemOperand *MMO =
8275 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8276 MachineMemOperand::MOStore, MemSize, MemSize);
8278 if (Opc != X86ISD::WIN_FTOL) {
8279 // Build the FP_TO_INT*_IN_MEM
8280 SDValue Ops[] = { Chain, Value, StackSlot };
8281 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8282 Ops, 3, DstTy, MMO);
8283 return std::make_pair(FIST, StackSlot);
8285 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8286 DAG.getVTList(MVT::Other, MVT::Glue),
8288 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8289 MVT::i32, ftol.getValue(1));
8290 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8291 MVT::i32, eax.getValue(2));
8292 SDValue Ops[] = { eax, edx };
8293 SDValue pair = IsReplace
8294 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, 2)
8295 : DAG.getMergeValues(Ops, 2, DL);
8296 return std::make_pair(pair, SDValue());
8300 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8301 const X86Subtarget *Subtarget) {
8302 EVT VT = Op->getValueType(0);
8303 SDValue In = Op->getOperand(0);
8304 EVT InVT = In.getValueType();
8305 DebugLoc dl = Op->getDebugLoc();
8307 // Optimize vectors in AVX mode:
8310 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8311 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8312 // Concat upper and lower parts.
8315 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8316 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8317 // Concat upper and lower parts.
8320 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8321 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8324 if (Subtarget->hasInt256())
8325 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8327 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8328 SDValue Undef = DAG.getUNDEF(InVT);
8329 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8330 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8331 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8333 EVT HVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8334 VT.getVectorNumElements()/2);
8336 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8337 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8339 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8342 SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
8343 SelectionDAG &DAG) const {
8344 if (Subtarget->hasFp256()) {
8345 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8352 SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
8353 SelectionDAG &DAG) const {
8354 DebugLoc DL = Op.getDebugLoc();
8355 EVT VT = Op.getValueType();
8356 SDValue In = Op.getOperand(0);
8357 EVT SVT = In.getValueType();
8359 if (Subtarget->hasFp256()) {
8360 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8365 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8366 VT.getVectorNumElements() != SVT.getVectorNumElements())
8369 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8371 // AVX2 has better support of integer extending.
8372 if (Subtarget->hasInt256())
8373 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8375 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8376 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8377 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8378 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8379 DAG.getUNDEF(MVT::v8i16),
8382 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8385 SDValue X86TargetLowering::lowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8386 DebugLoc DL = Op.getDebugLoc();
8387 EVT VT = Op.getValueType();
8388 SDValue In = Op.getOperand(0);
8389 EVT SVT = In.getValueType();
8391 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8392 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8393 if (Subtarget->hasInt256()) {
8394 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8395 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8396 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8398 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8399 DAG.getIntPtrConstant(0));
8402 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8403 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8404 DAG.getIntPtrConstant(0));
8405 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8406 DAG.getIntPtrConstant(2));
8408 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8409 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8412 static const int ShufMask1[] = {0, 2, 0, 0};
8413 SDValue Undef = DAG.getUNDEF(VT);
8414 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8415 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8417 // The MOVLHPS mask:
8418 static const int ShufMask2[] = {0, 1, 4, 5};
8419 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8422 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8423 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8424 if (Subtarget->hasInt256()) {
8425 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8427 SmallVector<SDValue,32> pshufbMask;
8428 for (unsigned i = 0; i < 2; ++i) {
8429 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8430 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8431 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8432 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8433 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8434 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8435 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8436 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8437 for (unsigned j = 0; j < 8; ++j)
8438 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8440 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8441 &pshufbMask[0], 32);
8442 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8443 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8445 static const int ShufMask[] = {0, 2, -1, -1};
8446 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8448 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8449 DAG.getIntPtrConstant(0));
8450 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8453 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8454 DAG.getIntPtrConstant(0));
8456 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8457 DAG.getIntPtrConstant(4));
8459 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8460 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8463 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8464 -1, -1, -1, -1, -1, -1, -1, -1};
8466 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8467 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8468 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8470 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8471 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8473 // The MOVLHPS Mask:
8474 static const int ShufMask2[] = {0, 1, 4, 5};
8475 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8476 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8479 // Handle truncation of V256 to V128 using shuffles.
8480 if (!VT.is128BitVector() || !SVT.is256BitVector())
8483 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
8485 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
8487 unsigned NumElems = VT.getVectorNumElements();
8488 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8491 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8492 // Prepare truncation shuffle mask
8493 for (unsigned i = 0; i != NumElems; ++i)
8495 SDValue V = DAG.getVectorShuffle(NVT, DL,
8496 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8497 DAG.getUNDEF(NVT), &MaskVec[0]);
8498 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8499 DAG.getIntPtrConstant(0));
8502 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8503 SelectionDAG &DAG) const {
8504 if (Op.getValueType().isVector()) {
8505 if (Op.getValueType() == MVT::v8i16)
8506 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), Op.getValueType(),
8507 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
8508 MVT::v8i32, Op.getOperand(0)));
8512 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8513 /*IsSigned=*/ true, /*IsReplace=*/ false);
8514 SDValue FIST = Vals.first, StackSlot = Vals.second;
8515 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8516 if (FIST.getNode() == 0) return Op;
8518 if (StackSlot.getNode())
8520 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8521 FIST, StackSlot, MachinePointerInfo(),
8522 false, false, false, 0);
8524 // The node is the result.
8528 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8529 SelectionDAG &DAG) const {
8530 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8531 /*IsSigned=*/ false, /*IsReplace=*/ false);
8532 SDValue FIST = Vals.first, StackSlot = Vals.second;
8533 assert(FIST.getNode() && "Unexpected failure");
8535 if (StackSlot.getNode())
8537 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8538 FIST, StackSlot, MachinePointerInfo(),
8539 false, false, false, 0);
8541 // The node is the result.
8545 SDValue X86TargetLowering::lowerFP_EXTEND(SDValue Op,
8546 SelectionDAG &DAG) const {
8547 DebugLoc DL = Op.getDebugLoc();
8548 EVT VT = Op.getValueType();
8549 SDValue In = Op.getOperand(0);
8550 EVT SVT = In.getValueType();
8552 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
8554 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
8555 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8556 In, DAG.getUNDEF(SVT)));
8559 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
8560 LLVMContext *Context = DAG.getContext();
8561 DebugLoc dl = Op.getDebugLoc();
8562 EVT VT = Op.getValueType();
8564 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8565 if (VT.isVector()) {
8566 EltVT = VT.getVectorElementType();
8567 NumElts = VT.getVectorNumElements();
8570 if (EltVT == MVT::f64)
8571 C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
8573 C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
8574 C = ConstantVector::getSplat(NumElts, C);
8575 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8576 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8577 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8578 MachinePointerInfo::getConstantPool(),
8579 false, false, false, Alignment);
8580 if (VT.isVector()) {
8581 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8582 return DAG.getNode(ISD::BITCAST, dl, VT,
8583 DAG.getNode(ISD::AND, dl, ANDVT,
8584 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8586 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8588 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8591 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8592 LLVMContext *Context = DAG.getContext();
8593 DebugLoc dl = Op.getDebugLoc();
8594 EVT VT = Op.getValueType();
8596 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8597 if (VT.isVector()) {
8598 EltVT = VT.getVectorElementType();
8599 NumElts = VT.getVectorNumElements();
8602 if (EltVT == MVT::f64)
8603 C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
8605 C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
8606 C = ConstantVector::getSplat(NumElts, C);
8607 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8608 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8609 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8610 MachinePointerInfo::getConstantPool(),
8611 false, false, false, Alignment);
8612 if (VT.isVector()) {
8613 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8614 return DAG.getNode(ISD::BITCAST, dl, VT,
8615 DAG.getNode(ISD::XOR, dl, XORVT,
8616 DAG.getNode(ISD::BITCAST, dl, XORVT,
8618 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8621 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8624 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8625 LLVMContext *Context = DAG.getContext();
8626 SDValue Op0 = Op.getOperand(0);
8627 SDValue Op1 = Op.getOperand(1);
8628 DebugLoc dl = Op.getDebugLoc();
8629 EVT VT = Op.getValueType();
8630 EVT SrcVT = Op1.getValueType();
8632 // If second operand is smaller, extend it first.
8633 if (SrcVT.bitsLT(VT)) {
8634 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8637 // And if it is bigger, shrink it first.
8638 if (SrcVT.bitsGT(VT)) {
8639 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8643 // At this point the operands and the result should have the same
8644 // type, and that won't be f80 since that is not custom lowered.
8646 // First get the sign bit of second operand.
8647 SmallVector<Constant*,4> CV;
8648 if (SrcVT == MVT::f64) {
8649 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
8650 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8652 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
8653 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8654 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8655 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8657 Constant *C = ConstantVector::get(CV);
8658 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8659 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8660 MachinePointerInfo::getConstantPool(),
8661 false, false, false, 16);
8662 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8664 // Shift sign bit right or left if the two operands have different types.
8665 if (SrcVT.bitsGT(VT)) {
8666 // Op0 is MVT::f32, Op1 is MVT::f64.
8667 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8668 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8669 DAG.getConstant(32, MVT::i32));
8670 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8671 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8672 DAG.getIntPtrConstant(0));
8675 // Clear first operand sign bit.
8677 if (VT == MVT::f64) {
8678 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
8679 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
8681 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
8682 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8683 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8684 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
8686 C = ConstantVector::get(CV);
8687 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8688 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8689 MachinePointerInfo::getConstantPool(),
8690 false, false, false, 16);
8691 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8693 // Or the value with the sign bit.
8694 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8697 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
8698 SDValue N0 = Op.getOperand(0);
8699 DebugLoc dl = Op.getDebugLoc();
8700 EVT VT = Op.getValueType();
8702 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8703 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8704 DAG.getConstant(1, VT));
8705 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8708 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
8710 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op, SelectionDAG &DAG) const {
8711 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8713 if (!Subtarget->hasSSE41())
8716 if (!Op->hasOneUse())
8719 SDNode *N = Op.getNode();
8720 DebugLoc DL = N->getDebugLoc();
8722 SmallVector<SDValue, 8> Opnds;
8723 DenseMap<SDValue, unsigned> VecInMap;
8724 EVT VT = MVT::Other;
8726 // Recognize a special case where a vector is casted into wide integer to
8728 Opnds.push_back(N->getOperand(0));
8729 Opnds.push_back(N->getOperand(1));
8731 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
8732 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot;
8733 // BFS traverse all OR'd operands.
8734 if (I->getOpcode() == ISD::OR) {
8735 Opnds.push_back(I->getOperand(0));
8736 Opnds.push_back(I->getOperand(1));
8737 // Re-evaluate the number of nodes to be traversed.
8738 e += 2; // 2 more nodes (LHS and RHS) are pushed.
8742 // Quit if a non-EXTRACT_VECTOR_ELT
8743 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8746 // Quit if without a constant index.
8747 SDValue Idx = I->getOperand(1);
8748 if (!isa<ConstantSDNode>(Idx))
8751 SDValue ExtractedFromVec = I->getOperand(0);
8752 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
8753 if (M == VecInMap.end()) {
8754 VT = ExtractedFromVec.getValueType();
8755 // Quit if not 128/256-bit vector.
8756 if (!VT.is128BitVector() && !VT.is256BitVector())
8758 // Quit if not the same type.
8759 if (VecInMap.begin() != VecInMap.end() &&
8760 VT != VecInMap.begin()->first.getValueType())
8762 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
8764 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
8767 assert((VT.is128BitVector() || VT.is256BitVector()) &&
8768 "Not extracted from 128-/256-bit vector.");
8770 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
8771 SmallVector<SDValue, 8> VecIns;
8773 for (DenseMap<SDValue, unsigned>::const_iterator
8774 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
8775 // Quit if not all elements are used.
8776 if (I->second != FullMask)
8778 VecIns.push_back(I->first);
8781 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8783 // Cast all vectors into TestVT for PTEST.
8784 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
8785 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
8787 // If more than one full vectors are evaluated, OR them first before PTEST.
8788 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
8789 // Each iteration will OR 2 nodes and append the result until there is only
8790 // 1 node left, i.e. the final OR'd value of all vectors.
8791 SDValue LHS = VecIns[Slot];
8792 SDValue RHS = VecIns[Slot + 1];
8793 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
8796 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
8797 VecIns.back(), VecIns.back());
8800 /// Emit nodes that will be selected as "test Op0,Op0", or something
8802 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8803 SelectionDAG &DAG) const {
8804 DebugLoc dl = Op.getDebugLoc();
8806 // CF and OF aren't always set the way we want. Determine which
8807 // of these we need.
8808 bool NeedCF = false;
8809 bool NeedOF = false;
8812 case X86::COND_A: case X86::COND_AE:
8813 case X86::COND_B: case X86::COND_BE:
8816 case X86::COND_G: case X86::COND_GE:
8817 case X86::COND_L: case X86::COND_LE:
8818 case X86::COND_O: case X86::COND_NO:
8823 // See if we can use the EFLAGS value from the operand instead of
8824 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8825 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8826 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8827 // Emit a CMP with 0, which is the TEST pattern.
8828 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8829 DAG.getConstant(0, Op.getValueType()));
8831 unsigned Opcode = 0;
8832 unsigned NumOperands = 0;
8834 // Truncate operations may prevent the merge of the SETCC instruction
8835 // and the arithmetic intruction before it. Attempt to truncate the operands
8836 // of the arithmetic instruction and use a reduced bit-width instruction.
8837 bool NeedTruncation = false;
8838 SDValue ArithOp = Op;
8839 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8840 SDValue Arith = Op->getOperand(0);
8841 // Both the trunc and the arithmetic op need to have one user each.
8842 if (Arith->hasOneUse())
8843 switch (Arith.getOpcode()) {
8850 NeedTruncation = true;
8856 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
8857 // which may be the result of a CAST. We use the variable 'Op', which is the
8858 // non-casted variable when we check for possible users.
8859 switch (ArithOp.getOpcode()) {
8861 // Due to an isel shortcoming, be conservative if this add is likely to be
8862 // selected as part of a load-modify-store instruction. When the root node
8863 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8864 // uses of other nodes in the match, such as the ADD in this case. This
8865 // leads to the ADD being left around and reselected, with the result being
8866 // two adds in the output. Alas, even if none our users are stores, that
8867 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8868 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8869 // climbing the DAG back to the root, and it doesn't seem to be worth the
8871 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8872 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8873 if (UI->getOpcode() != ISD::CopyToReg &&
8874 UI->getOpcode() != ISD::SETCC &&
8875 UI->getOpcode() != ISD::STORE)
8878 if (ConstantSDNode *C =
8879 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
8880 // An add of one will be selected as an INC.
8881 if (C->getAPIntValue() == 1) {
8882 Opcode = X86ISD::INC;
8887 // An add of negative one (subtract of one) will be selected as a DEC.
8888 if (C->getAPIntValue().isAllOnesValue()) {
8889 Opcode = X86ISD::DEC;
8895 // Otherwise use a regular EFLAGS-setting add.
8896 Opcode = X86ISD::ADD;
8900 // If the primary and result isn't used, don't bother using X86ISD::AND,
8901 // because a TEST instruction will be better.
8902 bool NonFlagUse = false;
8903 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8904 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8906 unsigned UOpNo = UI.getOperandNo();
8907 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8908 // Look pass truncate.
8909 UOpNo = User->use_begin().getOperandNo();
8910 User = *User->use_begin();
8913 if (User->getOpcode() != ISD::BRCOND &&
8914 User->getOpcode() != ISD::SETCC &&
8915 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
8928 // Due to the ISEL shortcoming noted above, be conservative if this op is
8929 // likely to be selected as part of a load-modify-store instruction.
8930 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8931 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8932 if (UI->getOpcode() == ISD::STORE)
8935 // Otherwise use a regular EFLAGS-setting instruction.
8936 switch (ArithOp.getOpcode()) {
8937 default: llvm_unreachable("unexpected operator!");
8938 case ISD::SUB: Opcode = X86ISD::SUB; break;
8939 case ISD::XOR: Opcode = X86ISD::XOR; break;
8940 case ISD::AND: Opcode = X86ISD::AND; break;
8942 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
8943 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
8944 if (EFLAGS.getNode())
8947 Opcode = X86ISD::OR;
8961 return SDValue(Op.getNode(), 1);
8967 // If we found that truncation is beneficial, perform the truncation and
8969 if (NeedTruncation) {
8970 EVT VT = Op.getValueType();
8971 SDValue WideVal = Op->getOperand(0);
8972 EVT WideVT = WideVal.getValueType();
8973 unsigned ConvertedOp = 0;
8974 // Use a target machine opcode to prevent further DAGCombine
8975 // optimizations that may separate the arithmetic operations
8976 // from the setcc node.
8977 switch (WideVal.getOpcode()) {
8979 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
8980 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
8981 case ISD::AND: ConvertedOp = X86ISD::AND; break;
8982 case ISD::OR: ConvertedOp = X86ISD::OR; break;
8983 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
8987 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8988 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
8989 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
8990 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
8991 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
8997 // Emit a CMP with 0, which is the TEST pattern.
8998 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8999 DAG.getConstant(0, Op.getValueType()));
9001 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9002 SmallVector<SDValue, 4> Ops;
9003 for (unsigned i = 0; i != NumOperands; ++i)
9004 Ops.push_back(Op.getOperand(i));
9006 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9007 DAG.ReplaceAllUsesWith(Op, New);
9008 return SDValue(New.getNode(), 1);
9011 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9013 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9014 SelectionDAG &DAG) const {
9015 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9016 if (C->getAPIntValue() == 0)
9017 return EmitTest(Op0, X86CC, DAG);
9019 DebugLoc dl = Op0.getDebugLoc();
9020 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9021 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9022 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9023 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9024 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9026 return SDValue(Sub.getNode(), 1);
9028 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9031 /// Convert a comparison if required by the subtarget.
9032 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9033 SelectionDAG &DAG) const {
9034 // If the subtarget does not support the FUCOMI instruction, floating-point
9035 // comparisons have to be converted.
9036 if (Subtarget->hasCMov() ||
9037 Cmp.getOpcode() != X86ISD::CMP ||
9038 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9039 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9042 // The instruction selector will select an FUCOM instruction instead of
9043 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9044 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9045 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9046 DebugLoc dl = Cmp.getDebugLoc();
9047 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9048 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9049 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9050 DAG.getConstant(8, MVT::i8));
9051 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9052 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9055 static bool isAllOnes(SDValue V) {
9056 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9057 return C && C->isAllOnesValue();
9060 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9061 /// if it's possible.
9062 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9063 DebugLoc dl, SelectionDAG &DAG) const {
9064 SDValue Op0 = And.getOperand(0);
9065 SDValue Op1 = And.getOperand(1);
9066 if (Op0.getOpcode() == ISD::TRUNCATE)
9067 Op0 = Op0.getOperand(0);
9068 if (Op1.getOpcode() == ISD::TRUNCATE)
9069 Op1 = Op1.getOperand(0);
9072 if (Op1.getOpcode() == ISD::SHL)
9073 std::swap(Op0, Op1);
9074 if (Op0.getOpcode() == ISD::SHL) {
9075 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9076 if (And00C->getZExtValue() == 1) {
9077 // If we looked past a truncate, check that it's only truncating away
9079 unsigned BitWidth = Op0.getValueSizeInBits();
9080 unsigned AndBitWidth = And.getValueSizeInBits();
9081 if (BitWidth > AndBitWidth) {
9083 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9084 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9088 RHS = Op0.getOperand(1);
9090 } else if (Op1.getOpcode() == ISD::Constant) {
9091 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9092 uint64_t AndRHSVal = AndRHS->getZExtValue();
9093 SDValue AndLHS = Op0;
9095 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9096 LHS = AndLHS.getOperand(0);
9097 RHS = AndLHS.getOperand(1);
9100 // Use BT if the immediate can't be encoded in a TEST instruction.
9101 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9103 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9107 if (LHS.getNode()) {
9108 // If the LHS is of the form (x ^ -1) then replace the LHS with x and flip
9109 // the condition code later.
9110 bool Invert = false;
9111 if (LHS.getOpcode() == ISD::XOR && isAllOnes(LHS.getOperand(1))) {
9113 LHS = LHS.getOperand(0);
9116 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9117 // instruction. Since the shift amount is in-range-or-undefined, we know
9118 // that doing a bittest on the i32 value is ok. We extend to i32 because
9119 // the encoding for the i16 version is larger than the i32 version.
9120 // Also promote i16 to i32 for performance / code size reason.
9121 if (LHS.getValueType() == MVT::i8 ||
9122 LHS.getValueType() == MVT::i16)
9123 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9125 // If the operand types disagree, extend the shift amount to match. Since
9126 // BT ignores high bits (like shifts) we can use anyextend.
9127 if (LHS.getValueType() != RHS.getValueType())
9128 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9130 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9131 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9132 // Flip the condition if the LHS was a not instruction
9134 Cond = X86::GetOppositeBranchCondition(Cond);
9135 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9136 DAG.getConstant(Cond, MVT::i8), BT);
9142 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9144 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG);
9146 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
9147 SDValue Op0 = Op.getOperand(0);
9148 SDValue Op1 = Op.getOperand(1);
9149 DebugLoc dl = Op.getDebugLoc();
9150 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9152 // Optimize to BT if possible.
9153 // Lower (X & (1 << N)) == 0 to BT(X, N).
9154 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9155 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9156 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9157 Op1.getOpcode() == ISD::Constant &&
9158 cast<ConstantSDNode>(Op1)->isNullValue() &&
9159 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9160 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9161 if (NewSetCC.getNode())
9165 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9167 if (Op1.getOpcode() == ISD::Constant &&
9168 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9169 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9170 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9172 // If the input is a setcc, then reuse the input setcc or use a new one with
9173 // the inverted condition.
9174 if (Op0.getOpcode() == X86ISD::SETCC) {
9175 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9176 bool Invert = (CC == ISD::SETNE) ^
9177 cast<ConstantSDNode>(Op1)->isNullValue();
9178 if (!Invert) return Op0;
9180 CCode = X86::GetOppositeBranchCondition(CCode);
9181 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9182 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9186 bool isFP = Op1.getValueType().isFloatingPoint();
9187 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9188 if (X86CC == X86::COND_INVALID)
9191 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9192 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9193 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9194 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9197 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9198 // ones, and then concatenate the result back.
9199 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9200 EVT VT = Op.getValueType();
9202 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9203 "Unsupported value type for operation");
9205 unsigned NumElems = VT.getVectorNumElements();
9206 DebugLoc dl = Op.getDebugLoc();
9207 SDValue CC = Op.getOperand(2);
9209 // Extract the LHS vectors
9210 SDValue LHS = Op.getOperand(0);
9211 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9212 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9214 // Extract the RHS vectors
9215 SDValue RHS = Op.getOperand(1);
9216 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9217 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9219 // Issue the operation on the smaller types and concatenate the result back
9220 MVT EltVT = VT.getVectorElementType().getSimpleVT();
9221 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9222 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9223 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9224 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9227 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
9229 SDValue Op0 = Op.getOperand(0);
9230 SDValue Op1 = Op.getOperand(1);
9231 SDValue CC = Op.getOperand(2);
9232 EVT VT = Op.getValueType();
9233 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9234 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
9235 DebugLoc dl = Op.getDebugLoc();
9239 EVT EltVT = Op0.getValueType().getVectorElementType();
9240 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9246 // SSE Condition code mapping:
9255 switch (SetCCOpcode) {
9256 default: llvm_unreachable("Unexpected SETCC condition");
9258 case ISD::SETEQ: SSECC = 0; break;
9260 case ISD::SETGT: Swap = true; // Fallthrough
9262 case ISD::SETOLT: SSECC = 1; break;
9264 case ISD::SETGE: Swap = true; // Fallthrough
9266 case ISD::SETOLE: SSECC = 2; break;
9267 case ISD::SETUO: SSECC = 3; break;
9269 case ISD::SETNE: SSECC = 4; break;
9270 case ISD::SETULE: Swap = true; // Fallthrough
9271 case ISD::SETUGE: SSECC = 5; break;
9272 case ISD::SETULT: Swap = true; // Fallthrough
9273 case ISD::SETUGT: SSECC = 6; break;
9274 case ISD::SETO: SSECC = 7; break;
9276 case ISD::SETONE: SSECC = 8; break;
9279 std::swap(Op0, Op1);
9281 // In the two special cases we can't handle, emit two comparisons.
9284 unsigned CombineOpc;
9285 if (SetCCOpcode == ISD::SETUEQ) {
9286 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9288 assert(SetCCOpcode == ISD::SETONE);
9289 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9292 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9293 DAG.getConstant(CC0, MVT::i8));
9294 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9295 DAG.getConstant(CC1, MVT::i8));
9296 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9298 // Handle all other FP comparisons here.
9299 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9300 DAG.getConstant(SSECC, MVT::i8));
9303 // Break 256-bit integer vector compare into smaller ones.
9304 if (VT.is256BitVector() && !Subtarget->hasInt256())
9305 return Lower256IntVSETCC(Op, DAG);
9307 // We are handling one of the integer comparisons here. Since SSE only has
9308 // GT and EQ comparisons for integer, swapping operands and multiple
9309 // operations may be required for some comparisons.
9311 bool Swap = false, Invert = false, FlipSigns = false;
9313 switch (SetCCOpcode) {
9314 default: llvm_unreachable("Unexpected SETCC condition");
9315 case ISD::SETNE: Invert = true;
9316 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9317 case ISD::SETLT: Swap = true;
9318 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9319 case ISD::SETGE: Swap = true;
9320 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9321 case ISD::SETULT: Swap = true;
9322 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9323 case ISD::SETUGE: Swap = true;
9324 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9327 std::swap(Op0, Op1);
9329 // Check that the operation in question is available (most are plain SSE2,
9330 // but PCMPGTQ and PCMPEQQ have different requirements).
9331 if (VT == MVT::v2i64) {
9332 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42())
9334 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9335 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9336 // pcmpeqd + pshufd + pand.
9337 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9339 // First cast everything to the right type,
9340 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9341 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9344 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9346 // Make sure the lower and upper halves are both all-ones.
9347 const int Mask[] = { 1, 0, 3, 2 };
9348 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9349 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9352 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9354 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9358 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9359 // bits of the inputs before performing those operations.
9361 EVT EltVT = VT.getVectorElementType();
9362 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
9364 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
9365 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
9367 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
9368 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
9371 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9373 // If the logical-not of the result is required, perform that now.
9375 Result = DAG.getNOT(dl, Result, VT);
9380 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9381 static bool isX86LogicalCmp(SDValue Op) {
9382 unsigned Opc = Op.getNode()->getOpcode();
9383 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9384 Opc == X86ISD::SAHF)
9386 if (Op.getResNo() == 1 &&
9387 (Opc == X86ISD::ADD ||
9388 Opc == X86ISD::SUB ||
9389 Opc == X86ISD::ADC ||
9390 Opc == X86ISD::SBB ||
9391 Opc == X86ISD::SMUL ||
9392 Opc == X86ISD::UMUL ||
9393 Opc == X86ISD::INC ||
9394 Opc == X86ISD::DEC ||
9395 Opc == X86ISD::OR ||
9396 Opc == X86ISD::XOR ||
9397 Opc == X86ISD::AND))
9400 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
9406 static bool isZero(SDValue V) {
9407 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9408 return C && C->isNullValue();
9411 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
9412 if (V.getOpcode() != ISD::TRUNCATE)
9415 SDValue VOp0 = V.getOperand(0);
9416 unsigned InBits = VOp0.getValueSizeInBits();
9417 unsigned Bits = V.getValueSizeInBits();
9418 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
9421 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
9422 bool addTest = true;
9423 SDValue Cond = Op.getOperand(0);
9424 SDValue Op1 = Op.getOperand(1);
9425 SDValue Op2 = Op.getOperand(2);
9426 DebugLoc DL = Op.getDebugLoc();
9429 if (Cond.getOpcode() == ISD::SETCC) {
9430 SDValue NewCond = LowerSETCC(Cond, DAG);
9431 if (NewCond.getNode())
9435 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
9436 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
9437 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
9438 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
9439 if (Cond.getOpcode() == X86ISD::SETCC &&
9440 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9441 isZero(Cond.getOperand(1).getOperand(1))) {
9442 SDValue Cmp = Cond.getOperand(1);
9444 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
9446 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
9447 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
9448 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
9450 SDValue CmpOp0 = Cmp.getOperand(0);
9451 // Apply further optimizations for special cases
9452 // (select (x != 0), -1, 0) -> neg & sbb
9453 // (select (x == 0), 0, -1) -> neg & sbb
9454 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
9455 if (YC->isNullValue() &&
9456 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
9457 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
9458 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
9459 DAG.getConstant(0, CmpOp0.getValueType()),
9461 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9462 DAG.getConstant(X86::COND_B, MVT::i8),
9463 SDValue(Neg.getNode(), 1));
9467 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
9468 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
9469 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9471 SDValue Res = // Res = 0 or -1.
9472 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9473 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
9475 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
9476 Res = DAG.getNOT(DL, Res, Res.getValueType());
9478 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
9479 if (N2C == 0 || !N2C->isNullValue())
9480 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9485 // Look past (and (setcc_carry (cmp ...)), 1).
9486 if (Cond.getOpcode() == ISD::AND &&
9487 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9488 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9489 if (C && C->getAPIntValue() == 1)
9490 Cond = Cond.getOperand(0);
9493 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9494 // setting operand in place of the X86ISD::SETCC.
9495 unsigned CondOpcode = Cond.getOpcode();
9496 if (CondOpcode == X86ISD::SETCC ||
9497 CondOpcode == X86ISD::SETCC_CARRY) {
9498 CC = Cond.getOperand(0);
9500 SDValue Cmp = Cond.getOperand(1);
9501 unsigned Opc = Cmp.getOpcode();
9502 EVT VT = Op.getValueType();
9504 bool IllegalFPCMov = false;
9505 if (VT.isFloatingPoint() && !VT.isVector() &&
9506 !isScalarFPTypeInSSEReg(VT)) // FPStack?
9507 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9509 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
9510 Opc == X86ISD::BT) { // FIXME
9514 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9515 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9516 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9517 Cond.getOperand(0).getValueType() != MVT::i8)) {
9518 SDValue LHS = Cond.getOperand(0);
9519 SDValue RHS = Cond.getOperand(1);
9523 switch (CondOpcode) {
9524 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9525 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9526 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9527 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9528 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9529 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9530 default: llvm_unreachable("unexpected overflowing operator");
9532 if (CondOpcode == ISD::UMULO)
9533 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9536 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9538 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
9540 if (CondOpcode == ISD::UMULO)
9541 Cond = X86Op.getValue(2);
9543 Cond = X86Op.getValue(1);
9545 CC = DAG.getConstant(X86Cond, MVT::i8);
9550 // Look pass the truncate if the high bits are known zero.
9551 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9552 Cond = Cond.getOperand(0);
9554 // We know the result of AND is compared against zero. Try to match
9556 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9557 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9558 if (NewSetCC.getNode()) {
9559 CC = NewSetCC.getOperand(0);
9560 Cond = NewSetCC.getOperand(1);
9567 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9568 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9571 // a < b ? -1 : 0 -> RES = ~setcc_carry
9572 // a < b ? 0 : -1 -> RES = setcc_carry
9573 // a >= b ? -1 : 0 -> RES = setcc_carry
9574 // a >= b ? 0 : -1 -> RES = ~setcc_carry
9575 if (Cond.getOpcode() == X86ISD::SUB) {
9576 Cond = ConvertCmpIfNecessary(Cond, DAG);
9577 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9579 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
9580 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9581 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9582 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9583 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9584 return DAG.getNOT(DL, Res, Res.getValueType());
9589 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
9590 // widen the cmov and push the truncate through. This avoids introducing a new
9591 // branch during isel and doesn't add any extensions.
9592 if (Op.getValueType() == MVT::i8 &&
9593 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9594 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
9595 if (T1.getValueType() == T2.getValueType() &&
9596 // Blacklist CopyFromReg to avoid partial register stalls.
9597 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9598 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
9599 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
9600 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
9604 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9605 // condition is true.
9606 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
9607 SDValue Ops[] = { Op2, Op1, CC, Cond };
9608 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9611 SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
9612 SelectionDAG &DAG) const {
9613 EVT VT = Op->getValueType(0);
9614 SDValue In = Op->getOperand(0);
9615 EVT InVT = In.getValueType();
9616 DebugLoc dl = Op->getDebugLoc();
9618 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
9619 (VT != MVT::v8i32 || InVT != MVT::v8i16))
9622 if (Subtarget->hasInt256())
9623 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
9625 // Optimize vectors in AVX mode
9626 // Sign extend v8i16 to v8i32 and
9629 // Divide input vector into two parts
9630 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
9631 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
9632 // concat the vectors to original VT
9634 unsigned NumElems = InVT.getVectorNumElements();
9635 SDValue Undef = DAG.getUNDEF(InVT);
9637 SmallVector<int,8> ShufMask1(NumElems, -1);
9638 for (unsigned i = 0; i != NumElems/2; ++i)
9641 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
9643 SmallVector<int,8> ShufMask2(NumElems, -1);
9644 for (unsigned i = 0; i != NumElems/2; ++i)
9645 ShufMask2[i] = i + NumElems/2;
9647 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
9649 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
9650 VT.getVectorNumElements()/2);
9652 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
9653 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
9655 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9658 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9659 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9660 // from the AND / OR.
9661 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9662 Opc = Op.getOpcode();
9663 if (Opc != ISD::OR && Opc != ISD::AND)
9665 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9666 Op.getOperand(0).hasOneUse() &&
9667 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9668 Op.getOperand(1).hasOneUse());
9671 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9672 // 1 and that the SETCC node has a single use.
9673 static bool isXor1OfSetCC(SDValue Op) {
9674 if (Op.getOpcode() != ISD::XOR)
9676 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9677 if (N1C && N1C->getAPIntValue() == 1) {
9678 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9679 Op.getOperand(0).hasOneUse();
9684 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9685 bool addTest = true;
9686 SDValue Chain = Op.getOperand(0);
9687 SDValue Cond = Op.getOperand(1);
9688 SDValue Dest = Op.getOperand(2);
9689 DebugLoc dl = Op.getDebugLoc();
9691 bool Inverted = false;
9693 if (Cond.getOpcode() == ISD::SETCC) {
9694 // Check for setcc([su]{add,sub,mul}o == 0).
9695 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9696 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9697 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9698 Cond.getOperand(0).getResNo() == 1 &&
9699 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9700 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9701 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9702 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9703 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9704 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9706 Cond = Cond.getOperand(0);
9708 SDValue NewCond = LowerSETCC(Cond, DAG);
9709 if (NewCond.getNode())
9714 // FIXME: LowerXALUO doesn't handle these!!
9715 else if (Cond.getOpcode() == X86ISD::ADD ||
9716 Cond.getOpcode() == X86ISD::SUB ||
9717 Cond.getOpcode() == X86ISD::SMUL ||
9718 Cond.getOpcode() == X86ISD::UMUL)
9719 Cond = LowerXALUO(Cond, DAG);
9722 // Look pass (and (setcc_carry (cmp ...)), 1).
9723 if (Cond.getOpcode() == ISD::AND &&
9724 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9725 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9726 if (C && C->getAPIntValue() == 1)
9727 Cond = Cond.getOperand(0);
9730 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9731 // setting operand in place of the X86ISD::SETCC.
9732 unsigned CondOpcode = Cond.getOpcode();
9733 if (CondOpcode == X86ISD::SETCC ||
9734 CondOpcode == X86ISD::SETCC_CARRY) {
9735 CC = Cond.getOperand(0);
9737 SDValue Cmp = Cond.getOperand(1);
9738 unsigned Opc = Cmp.getOpcode();
9739 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9740 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9744 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9748 // These can only come from an arithmetic instruction with overflow,
9749 // e.g. SADDO, UADDO.
9750 Cond = Cond.getNode()->getOperand(1);
9756 CondOpcode = Cond.getOpcode();
9757 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9758 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9759 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9760 Cond.getOperand(0).getValueType() != MVT::i8)) {
9761 SDValue LHS = Cond.getOperand(0);
9762 SDValue RHS = Cond.getOperand(1);
9766 switch (CondOpcode) {
9767 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9768 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9769 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9770 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9771 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9772 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9773 default: llvm_unreachable("unexpected overflowing operator");
9776 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9777 if (CondOpcode == ISD::UMULO)
9778 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9781 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9783 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9785 if (CondOpcode == ISD::UMULO)
9786 Cond = X86Op.getValue(2);
9788 Cond = X86Op.getValue(1);
9790 CC = DAG.getConstant(X86Cond, MVT::i8);
9794 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9795 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9796 if (CondOpc == ISD::OR) {
9797 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9798 // two branches instead of an explicit OR instruction with a
9800 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9801 isX86LogicalCmp(Cmp)) {
9802 CC = Cond.getOperand(0).getOperand(0);
9803 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9804 Chain, Dest, CC, Cmp);
9805 CC = Cond.getOperand(1).getOperand(0);
9809 } else { // ISD::AND
9810 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9811 // two branches instead of an explicit AND instruction with a
9812 // separate test. However, we only do this if this block doesn't
9813 // have a fall-through edge, because this requires an explicit
9814 // jmp when the condition is false.
9815 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9816 isX86LogicalCmp(Cmp) &&
9817 Op.getNode()->hasOneUse()) {
9818 X86::CondCode CCode =
9819 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9820 CCode = X86::GetOppositeBranchCondition(CCode);
9821 CC = DAG.getConstant(CCode, MVT::i8);
9822 SDNode *User = *Op.getNode()->use_begin();
9823 // Look for an unconditional branch following this conditional branch.
9824 // We need this because we need to reverse the successors in order
9825 // to implement FCMP_OEQ.
9826 if (User->getOpcode() == ISD::BR) {
9827 SDValue FalseBB = User->getOperand(1);
9829 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9830 assert(NewBR == User);
9834 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9835 Chain, Dest, CC, Cmp);
9836 X86::CondCode CCode =
9837 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9838 CCode = X86::GetOppositeBranchCondition(CCode);
9839 CC = DAG.getConstant(CCode, MVT::i8);
9845 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9846 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9847 // It should be transformed during dag combiner except when the condition
9848 // is set by a arithmetics with overflow node.
9849 X86::CondCode CCode =
9850 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9851 CCode = X86::GetOppositeBranchCondition(CCode);
9852 CC = DAG.getConstant(CCode, MVT::i8);
9853 Cond = Cond.getOperand(0).getOperand(1);
9855 } else if (Cond.getOpcode() == ISD::SETCC &&
9856 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9857 // For FCMP_OEQ, we can emit
9858 // two branches instead of an explicit AND instruction with a
9859 // separate test. However, we only do this if this block doesn't
9860 // have a fall-through edge, because this requires an explicit
9861 // jmp when the condition is false.
9862 if (Op.getNode()->hasOneUse()) {
9863 SDNode *User = *Op.getNode()->use_begin();
9864 // Look for an unconditional branch following this conditional branch.
9865 // We need this because we need to reverse the successors in order
9866 // to implement FCMP_OEQ.
9867 if (User->getOpcode() == ISD::BR) {
9868 SDValue FalseBB = User->getOperand(1);
9870 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9871 assert(NewBR == User);
9875 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9876 Cond.getOperand(0), Cond.getOperand(1));
9877 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9878 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9879 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9880 Chain, Dest, CC, Cmp);
9881 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9886 } else if (Cond.getOpcode() == ISD::SETCC &&
9887 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9888 // For FCMP_UNE, we can emit
9889 // two branches instead of an explicit AND instruction with a
9890 // separate test. However, we only do this if this block doesn't
9891 // have a fall-through edge, because this requires an explicit
9892 // jmp when the condition is false.
9893 if (Op.getNode()->hasOneUse()) {
9894 SDNode *User = *Op.getNode()->use_begin();
9895 // Look for an unconditional branch following this conditional branch.
9896 // We need this because we need to reverse the successors in order
9897 // to implement FCMP_UNE.
9898 if (User->getOpcode() == ISD::BR) {
9899 SDValue FalseBB = User->getOperand(1);
9901 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9902 assert(NewBR == User);
9905 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9906 Cond.getOperand(0), Cond.getOperand(1));
9907 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9908 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9909 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9910 Chain, Dest, CC, Cmp);
9911 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
9921 // Look pass the truncate if the high bits are known zero.
9922 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9923 Cond = Cond.getOperand(0);
9925 // We know the result of AND is compared against zero. Try to match
9927 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9928 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
9929 if (NewSetCC.getNode()) {
9930 CC = NewSetCC.getOperand(0);
9931 Cond = NewSetCC.getOperand(1);
9938 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9939 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9941 Cond = ConvertCmpIfNecessary(Cond, DAG);
9942 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9943 Chain, Dest, CC, Cond);
9946 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
9947 // Calls to _alloca is needed to probe the stack when allocating more than 4k
9948 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
9949 // that the guard pages used by the OS virtual memory manager are allocated in
9950 // correct sequence.
9952 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
9953 SelectionDAG &DAG) const {
9954 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
9955 getTargetMachine().Options.EnableSegmentedStacks) &&
9956 "This should be used only on Windows targets or when segmented stacks "
9958 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
9959 DebugLoc dl = Op.getDebugLoc();
9962 SDValue Chain = Op.getOperand(0);
9963 SDValue Size = Op.getOperand(1);
9964 // FIXME: Ensure alignment here
9966 bool Is64Bit = Subtarget->is64Bit();
9967 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
9969 if (getTargetMachine().Options.EnableSegmentedStacks) {
9970 MachineFunction &MF = DAG.getMachineFunction();
9971 MachineRegisterInfo &MRI = MF.getRegInfo();
9974 // The 64 bit implementation of segmented stacks needs to clobber both r10
9975 // r11. This makes it impossible to use it along with nested parameters.
9976 const Function *F = MF.getFunction();
9978 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
9980 if (I->hasNestAttr())
9981 report_fatal_error("Cannot use segmented stacks with functions that "
9982 "have nested arguments.");
9985 const TargetRegisterClass *AddrRegClass =
9986 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
9987 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
9988 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
9989 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
9990 DAG.getRegister(Vreg, SPTy));
9991 SDValue Ops1[2] = { Value, Chain };
9992 return DAG.getMergeValues(Ops1, 2, dl);
9995 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
9997 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
9998 Flag = Chain.getValue(1);
9999 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10001 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10002 Flag = Chain.getValue(1);
10004 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10007 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10008 return DAG.getMergeValues(Ops1, 2, dl);
10012 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10013 MachineFunction &MF = DAG.getMachineFunction();
10014 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10016 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10017 DebugLoc DL = Op.getDebugLoc();
10019 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10020 // vastart just stores the address of the VarArgsFrameIndex slot into the
10021 // memory location argument.
10022 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10024 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10025 MachinePointerInfo(SV), false, false, 0);
10029 // gp_offset (0 - 6 * 8)
10030 // fp_offset (48 - 48 + 8 * 16)
10031 // overflow_arg_area (point to parameters coming in memory).
10033 SmallVector<SDValue, 8> MemOps;
10034 SDValue FIN = Op.getOperand(1);
10036 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10037 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10039 FIN, MachinePointerInfo(SV), false, false, 0);
10040 MemOps.push_back(Store);
10043 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10044 FIN, DAG.getIntPtrConstant(4));
10045 Store = DAG.getStore(Op.getOperand(0), DL,
10046 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10048 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10049 MemOps.push_back(Store);
10051 // Store ptr to overflow_arg_area
10052 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10053 FIN, DAG.getIntPtrConstant(4));
10054 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10056 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10057 MachinePointerInfo(SV, 8),
10059 MemOps.push_back(Store);
10061 // Store ptr to reg_save_area.
10062 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10063 FIN, DAG.getIntPtrConstant(8));
10064 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10066 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10067 MachinePointerInfo(SV, 16), false, false, 0);
10068 MemOps.push_back(Store);
10069 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10070 &MemOps[0], MemOps.size());
10073 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10074 assert(Subtarget->is64Bit() &&
10075 "LowerVAARG only handles 64-bit va_arg!");
10076 assert((Subtarget->isTargetLinux() ||
10077 Subtarget->isTargetDarwin()) &&
10078 "Unhandled target in LowerVAARG");
10079 assert(Op.getNode()->getNumOperands() == 4);
10080 SDValue Chain = Op.getOperand(0);
10081 SDValue SrcPtr = Op.getOperand(1);
10082 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10083 unsigned Align = Op.getConstantOperandVal(3);
10084 DebugLoc dl = Op.getDebugLoc();
10086 EVT ArgVT = Op.getNode()->getValueType(0);
10087 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10088 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10091 // Decide which area this value should be read from.
10092 // TODO: Implement the AMD64 ABI in its entirety. This simple
10093 // selection mechanism works only for the basic types.
10094 if (ArgVT == MVT::f80) {
10095 llvm_unreachable("va_arg for f80 not yet implemented");
10096 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10097 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10098 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10099 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10101 llvm_unreachable("Unhandled argument type in LowerVAARG");
10104 if (ArgMode == 2) {
10105 // Sanity Check: Make sure using fp_offset makes sense.
10106 assert(!getTargetMachine().Options.UseSoftFloat &&
10107 !(DAG.getMachineFunction()
10108 .getFunction()->getAttributes()
10109 .hasAttribute(AttributeSet::FunctionIndex,
10110 Attribute::NoImplicitFloat)) &&
10111 Subtarget->hasSSE1());
10114 // Insert VAARG_64 node into the DAG
10115 // VAARG_64 returns two values: Variable Argument Address, Chain
10116 SmallVector<SDValue, 11> InstOps;
10117 InstOps.push_back(Chain);
10118 InstOps.push_back(SrcPtr);
10119 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10120 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10121 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10122 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10123 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10124 VTs, &InstOps[0], InstOps.size(),
10126 MachinePointerInfo(SV),
10128 /*Volatile=*/false,
10130 /*WriteMem=*/true);
10131 Chain = VAARG.getValue(1);
10133 // Load the next argument and return it
10134 return DAG.getLoad(ArgVT, dl,
10137 MachinePointerInfo(),
10138 false, false, false, 0);
10141 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10142 SelectionDAG &DAG) {
10143 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10144 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10145 SDValue Chain = Op.getOperand(0);
10146 SDValue DstPtr = Op.getOperand(1);
10147 SDValue SrcPtr = Op.getOperand(2);
10148 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10149 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10150 DebugLoc DL = Op.getDebugLoc();
10152 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10153 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10155 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10158 // getTargetVShiftNOde - Handle vector element shifts where the shift amount
10159 // may or may not be a constant. Takes immediate version of shift as input.
10160 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
10161 SDValue SrcOp, SDValue ShAmt,
10162 SelectionDAG &DAG) {
10163 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10165 if (isa<ConstantSDNode>(ShAmt)) {
10166 // Constant may be a TargetConstant. Use a regular constant.
10167 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10169 default: llvm_unreachable("Unknown target vector shift node");
10170 case X86ISD::VSHLI:
10171 case X86ISD::VSRLI:
10172 case X86ISD::VSRAI:
10173 return DAG.getNode(Opc, dl, VT, SrcOp,
10174 DAG.getConstant(ShiftAmt, MVT::i32));
10178 // Change opcode to non-immediate version
10180 default: llvm_unreachable("Unknown target vector shift node");
10181 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10182 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10183 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10186 // Need to build a vector containing shift amount
10187 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10190 ShOps[1] = DAG.getConstant(0, MVT::i32);
10191 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10192 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10194 // The return type has to be a 128-bit type with the same element
10195 // type as the input type.
10196 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10197 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10199 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10200 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10203 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10204 DebugLoc dl = Op.getDebugLoc();
10205 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10207 default: return SDValue(); // Don't custom lower most intrinsics.
10208 // Comparison intrinsics.
10209 case Intrinsic::x86_sse_comieq_ss:
10210 case Intrinsic::x86_sse_comilt_ss:
10211 case Intrinsic::x86_sse_comile_ss:
10212 case Intrinsic::x86_sse_comigt_ss:
10213 case Intrinsic::x86_sse_comige_ss:
10214 case Intrinsic::x86_sse_comineq_ss:
10215 case Intrinsic::x86_sse_ucomieq_ss:
10216 case Intrinsic::x86_sse_ucomilt_ss:
10217 case Intrinsic::x86_sse_ucomile_ss:
10218 case Intrinsic::x86_sse_ucomigt_ss:
10219 case Intrinsic::x86_sse_ucomige_ss:
10220 case Intrinsic::x86_sse_ucomineq_ss:
10221 case Intrinsic::x86_sse2_comieq_sd:
10222 case Intrinsic::x86_sse2_comilt_sd:
10223 case Intrinsic::x86_sse2_comile_sd:
10224 case Intrinsic::x86_sse2_comigt_sd:
10225 case Intrinsic::x86_sse2_comige_sd:
10226 case Intrinsic::x86_sse2_comineq_sd:
10227 case Intrinsic::x86_sse2_ucomieq_sd:
10228 case Intrinsic::x86_sse2_ucomilt_sd:
10229 case Intrinsic::x86_sse2_ucomile_sd:
10230 case Intrinsic::x86_sse2_ucomigt_sd:
10231 case Intrinsic::x86_sse2_ucomige_sd:
10232 case Intrinsic::x86_sse2_ucomineq_sd: {
10236 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10237 case Intrinsic::x86_sse_comieq_ss:
10238 case Intrinsic::x86_sse2_comieq_sd:
10239 Opc = X86ISD::COMI;
10242 case Intrinsic::x86_sse_comilt_ss:
10243 case Intrinsic::x86_sse2_comilt_sd:
10244 Opc = X86ISD::COMI;
10247 case Intrinsic::x86_sse_comile_ss:
10248 case Intrinsic::x86_sse2_comile_sd:
10249 Opc = X86ISD::COMI;
10252 case Intrinsic::x86_sse_comigt_ss:
10253 case Intrinsic::x86_sse2_comigt_sd:
10254 Opc = X86ISD::COMI;
10257 case Intrinsic::x86_sse_comige_ss:
10258 case Intrinsic::x86_sse2_comige_sd:
10259 Opc = X86ISD::COMI;
10262 case Intrinsic::x86_sse_comineq_ss:
10263 case Intrinsic::x86_sse2_comineq_sd:
10264 Opc = X86ISD::COMI;
10267 case Intrinsic::x86_sse_ucomieq_ss:
10268 case Intrinsic::x86_sse2_ucomieq_sd:
10269 Opc = X86ISD::UCOMI;
10272 case Intrinsic::x86_sse_ucomilt_ss:
10273 case Intrinsic::x86_sse2_ucomilt_sd:
10274 Opc = X86ISD::UCOMI;
10277 case Intrinsic::x86_sse_ucomile_ss:
10278 case Intrinsic::x86_sse2_ucomile_sd:
10279 Opc = X86ISD::UCOMI;
10282 case Intrinsic::x86_sse_ucomigt_ss:
10283 case Intrinsic::x86_sse2_ucomigt_sd:
10284 Opc = X86ISD::UCOMI;
10287 case Intrinsic::x86_sse_ucomige_ss:
10288 case Intrinsic::x86_sse2_ucomige_sd:
10289 Opc = X86ISD::UCOMI;
10292 case Intrinsic::x86_sse_ucomineq_ss:
10293 case Intrinsic::x86_sse2_ucomineq_sd:
10294 Opc = X86ISD::UCOMI;
10299 SDValue LHS = Op.getOperand(1);
10300 SDValue RHS = Op.getOperand(2);
10301 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10302 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10303 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10304 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10305 DAG.getConstant(X86CC, MVT::i8), Cond);
10306 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10309 // Arithmetic intrinsics.
10310 case Intrinsic::x86_sse2_pmulu_dq:
10311 case Intrinsic::x86_avx2_pmulu_dq:
10312 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10313 Op.getOperand(1), Op.getOperand(2));
10315 // SSE2/AVX2 sub with unsigned saturation intrinsics
10316 case Intrinsic::x86_sse2_psubus_b:
10317 case Intrinsic::x86_sse2_psubus_w:
10318 case Intrinsic::x86_avx2_psubus_b:
10319 case Intrinsic::x86_avx2_psubus_w:
10320 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10321 Op.getOperand(1), Op.getOperand(2));
10323 // SSE3/AVX horizontal add/sub intrinsics
10324 case Intrinsic::x86_sse3_hadd_ps:
10325 case Intrinsic::x86_sse3_hadd_pd:
10326 case Intrinsic::x86_avx_hadd_ps_256:
10327 case Intrinsic::x86_avx_hadd_pd_256:
10328 case Intrinsic::x86_sse3_hsub_ps:
10329 case Intrinsic::x86_sse3_hsub_pd:
10330 case Intrinsic::x86_avx_hsub_ps_256:
10331 case Intrinsic::x86_avx_hsub_pd_256:
10332 case Intrinsic::x86_ssse3_phadd_w_128:
10333 case Intrinsic::x86_ssse3_phadd_d_128:
10334 case Intrinsic::x86_avx2_phadd_w:
10335 case Intrinsic::x86_avx2_phadd_d:
10336 case Intrinsic::x86_ssse3_phsub_w_128:
10337 case Intrinsic::x86_ssse3_phsub_d_128:
10338 case Intrinsic::x86_avx2_phsub_w:
10339 case Intrinsic::x86_avx2_phsub_d: {
10342 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10343 case Intrinsic::x86_sse3_hadd_ps:
10344 case Intrinsic::x86_sse3_hadd_pd:
10345 case Intrinsic::x86_avx_hadd_ps_256:
10346 case Intrinsic::x86_avx_hadd_pd_256:
10347 Opcode = X86ISD::FHADD;
10349 case Intrinsic::x86_sse3_hsub_ps:
10350 case Intrinsic::x86_sse3_hsub_pd:
10351 case Intrinsic::x86_avx_hsub_ps_256:
10352 case Intrinsic::x86_avx_hsub_pd_256:
10353 Opcode = X86ISD::FHSUB;
10355 case Intrinsic::x86_ssse3_phadd_w_128:
10356 case Intrinsic::x86_ssse3_phadd_d_128:
10357 case Intrinsic::x86_avx2_phadd_w:
10358 case Intrinsic::x86_avx2_phadd_d:
10359 Opcode = X86ISD::HADD;
10361 case Intrinsic::x86_ssse3_phsub_w_128:
10362 case Intrinsic::x86_ssse3_phsub_d_128:
10363 case Intrinsic::x86_avx2_phsub_w:
10364 case Intrinsic::x86_avx2_phsub_d:
10365 Opcode = X86ISD::HSUB;
10368 return DAG.getNode(Opcode, dl, Op.getValueType(),
10369 Op.getOperand(1), Op.getOperand(2));
10372 // SSE2/SSE41/AVX2 integer max/min intrinsics.
10373 case Intrinsic::x86_sse2_pmaxu_b:
10374 case Intrinsic::x86_sse41_pmaxuw:
10375 case Intrinsic::x86_sse41_pmaxud:
10376 case Intrinsic::x86_avx2_pmaxu_b:
10377 case Intrinsic::x86_avx2_pmaxu_w:
10378 case Intrinsic::x86_avx2_pmaxu_d:
10379 case Intrinsic::x86_sse2_pminu_b:
10380 case Intrinsic::x86_sse41_pminuw:
10381 case Intrinsic::x86_sse41_pminud:
10382 case Intrinsic::x86_avx2_pminu_b:
10383 case Intrinsic::x86_avx2_pminu_w:
10384 case Intrinsic::x86_avx2_pminu_d:
10385 case Intrinsic::x86_sse41_pmaxsb:
10386 case Intrinsic::x86_sse2_pmaxs_w:
10387 case Intrinsic::x86_sse41_pmaxsd:
10388 case Intrinsic::x86_avx2_pmaxs_b:
10389 case Intrinsic::x86_avx2_pmaxs_w:
10390 case Intrinsic::x86_avx2_pmaxs_d:
10391 case Intrinsic::x86_sse41_pminsb:
10392 case Intrinsic::x86_sse2_pmins_w:
10393 case Intrinsic::x86_sse41_pminsd:
10394 case Intrinsic::x86_avx2_pmins_b:
10395 case Intrinsic::x86_avx2_pmins_w:
10396 case Intrinsic::x86_avx2_pmins_d: {
10399 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10400 case Intrinsic::x86_sse2_pmaxu_b:
10401 case Intrinsic::x86_sse41_pmaxuw:
10402 case Intrinsic::x86_sse41_pmaxud:
10403 case Intrinsic::x86_avx2_pmaxu_b:
10404 case Intrinsic::x86_avx2_pmaxu_w:
10405 case Intrinsic::x86_avx2_pmaxu_d:
10406 Opcode = X86ISD::UMAX;
10408 case Intrinsic::x86_sse2_pminu_b:
10409 case Intrinsic::x86_sse41_pminuw:
10410 case Intrinsic::x86_sse41_pminud:
10411 case Intrinsic::x86_avx2_pminu_b:
10412 case Intrinsic::x86_avx2_pminu_w:
10413 case Intrinsic::x86_avx2_pminu_d:
10414 Opcode = X86ISD::UMIN;
10416 case Intrinsic::x86_sse41_pmaxsb:
10417 case Intrinsic::x86_sse2_pmaxs_w:
10418 case Intrinsic::x86_sse41_pmaxsd:
10419 case Intrinsic::x86_avx2_pmaxs_b:
10420 case Intrinsic::x86_avx2_pmaxs_w:
10421 case Intrinsic::x86_avx2_pmaxs_d:
10422 Opcode = X86ISD::SMAX;
10424 case Intrinsic::x86_sse41_pminsb:
10425 case Intrinsic::x86_sse2_pmins_w:
10426 case Intrinsic::x86_sse41_pminsd:
10427 case Intrinsic::x86_avx2_pmins_b:
10428 case Intrinsic::x86_avx2_pmins_w:
10429 case Intrinsic::x86_avx2_pmins_d:
10430 Opcode = X86ISD::SMIN;
10433 return DAG.getNode(Opcode, dl, Op.getValueType(),
10434 Op.getOperand(1), Op.getOperand(2));
10437 // SSE/SSE2/AVX floating point max/min intrinsics.
10438 case Intrinsic::x86_sse_max_ps:
10439 case Intrinsic::x86_sse2_max_pd:
10440 case Intrinsic::x86_avx_max_ps_256:
10441 case Intrinsic::x86_avx_max_pd_256:
10442 case Intrinsic::x86_sse_min_ps:
10443 case Intrinsic::x86_sse2_min_pd:
10444 case Intrinsic::x86_avx_min_ps_256:
10445 case Intrinsic::x86_avx_min_pd_256: {
10448 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10449 case Intrinsic::x86_sse_max_ps:
10450 case Intrinsic::x86_sse2_max_pd:
10451 case Intrinsic::x86_avx_max_ps_256:
10452 case Intrinsic::x86_avx_max_pd_256:
10453 Opcode = X86ISD::FMAX;
10455 case Intrinsic::x86_sse_min_ps:
10456 case Intrinsic::x86_sse2_min_pd:
10457 case Intrinsic::x86_avx_min_ps_256:
10458 case Intrinsic::x86_avx_min_pd_256:
10459 Opcode = X86ISD::FMIN;
10462 return DAG.getNode(Opcode, dl, Op.getValueType(),
10463 Op.getOperand(1), Op.getOperand(2));
10466 // AVX2 variable shift intrinsics
10467 case Intrinsic::x86_avx2_psllv_d:
10468 case Intrinsic::x86_avx2_psllv_q:
10469 case Intrinsic::x86_avx2_psllv_d_256:
10470 case Intrinsic::x86_avx2_psllv_q_256:
10471 case Intrinsic::x86_avx2_psrlv_d:
10472 case Intrinsic::x86_avx2_psrlv_q:
10473 case Intrinsic::x86_avx2_psrlv_d_256:
10474 case Intrinsic::x86_avx2_psrlv_q_256:
10475 case Intrinsic::x86_avx2_psrav_d:
10476 case Intrinsic::x86_avx2_psrav_d_256: {
10479 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10480 case Intrinsic::x86_avx2_psllv_d:
10481 case Intrinsic::x86_avx2_psllv_q:
10482 case Intrinsic::x86_avx2_psllv_d_256:
10483 case Intrinsic::x86_avx2_psllv_q_256:
10486 case Intrinsic::x86_avx2_psrlv_d:
10487 case Intrinsic::x86_avx2_psrlv_q:
10488 case Intrinsic::x86_avx2_psrlv_d_256:
10489 case Intrinsic::x86_avx2_psrlv_q_256:
10492 case Intrinsic::x86_avx2_psrav_d:
10493 case Intrinsic::x86_avx2_psrav_d_256:
10497 return DAG.getNode(Opcode, dl, Op.getValueType(),
10498 Op.getOperand(1), Op.getOperand(2));
10501 case Intrinsic::x86_ssse3_pshuf_b_128:
10502 case Intrinsic::x86_avx2_pshuf_b:
10503 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
10504 Op.getOperand(1), Op.getOperand(2));
10506 case Intrinsic::x86_ssse3_psign_b_128:
10507 case Intrinsic::x86_ssse3_psign_w_128:
10508 case Intrinsic::x86_ssse3_psign_d_128:
10509 case Intrinsic::x86_avx2_psign_b:
10510 case Intrinsic::x86_avx2_psign_w:
10511 case Intrinsic::x86_avx2_psign_d:
10512 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
10513 Op.getOperand(1), Op.getOperand(2));
10515 case Intrinsic::x86_sse41_insertps:
10516 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
10517 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10519 case Intrinsic::x86_avx_vperm2f128_ps_256:
10520 case Intrinsic::x86_avx_vperm2f128_pd_256:
10521 case Intrinsic::x86_avx_vperm2f128_si_256:
10522 case Intrinsic::x86_avx2_vperm2i128:
10523 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
10524 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10526 case Intrinsic::x86_avx2_permd:
10527 case Intrinsic::x86_avx2_permps:
10528 // Operands intentionally swapped. Mask is last operand to intrinsic,
10529 // but second operand for node/intruction.
10530 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
10531 Op.getOperand(2), Op.getOperand(1));
10533 case Intrinsic::x86_sse_sqrt_ps:
10534 case Intrinsic::x86_sse2_sqrt_pd:
10535 case Intrinsic::x86_avx_sqrt_ps_256:
10536 case Intrinsic::x86_avx_sqrt_pd_256:
10537 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
10539 // ptest and testp intrinsics. The intrinsic these come from are designed to
10540 // return an integer value, not just an instruction so lower it to the ptest
10541 // or testp pattern and a setcc for the result.
10542 case Intrinsic::x86_sse41_ptestz:
10543 case Intrinsic::x86_sse41_ptestc:
10544 case Intrinsic::x86_sse41_ptestnzc:
10545 case Intrinsic::x86_avx_ptestz_256:
10546 case Intrinsic::x86_avx_ptestc_256:
10547 case Intrinsic::x86_avx_ptestnzc_256:
10548 case Intrinsic::x86_avx_vtestz_ps:
10549 case Intrinsic::x86_avx_vtestc_ps:
10550 case Intrinsic::x86_avx_vtestnzc_ps:
10551 case Intrinsic::x86_avx_vtestz_pd:
10552 case Intrinsic::x86_avx_vtestc_pd:
10553 case Intrinsic::x86_avx_vtestnzc_pd:
10554 case Intrinsic::x86_avx_vtestz_ps_256:
10555 case Intrinsic::x86_avx_vtestc_ps_256:
10556 case Intrinsic::x86_avx_vtestnzc_ps_256:
10557 case Intrinsic::x86_avx_vtestz_pd_256:
10558 case Intrinsic::x86_avx_vtestc_pd_256:
10559 case Intrinsic::x86_avx_vtestnzc_pd_256: {
10560 bool IsTestPacked = false;
10563 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
10564 case Intrinsic::x86_avx_vtestz_ps:
10565 case Intrinsic::x86_avx_vtestz_pd:
10566 case Intrinsic::x86_avx_vtestz_ps_256:
10567 case Intrinsic::x86_avx_vtestz_pd_256:
10568 IsTestPacked = true; // Fallthrough
10569 case Intrinsic::x86_sse41_ptestz:
10570 case Intrinsic::x86_avx_ptestz_256:
10572 X86CC = X86::COND_E;
10574 case Intrinsic::x86_avx_vtestc_ps:
10575 case Intrinsic::x86_avx_vtestc_pd:
10576 case Intrinsic::x86_avx_vtestc_ps_256:
10577 case Intrinsic::x86_avx_vtestc_pd_256:
10578 IsTestPacked = true; // Fallthrough
10579 case Intrinsic::x86_sse41_ptestc:
10580 case Intrinsic::x86_avx_ptestc_256:
10582 X86CC = X86::COND_B;
10584 case Intrinsic::x86_avx_vtestnzc_ps:
10585 case Intrinsic::x86_avx_vtestnzc_pd:
10586 case Intrinsic::x86_avx_vtestnzc_ps_256:
10587 case Intrinsic::x86_avx_vtestnzc_pd_256:
10588 IsTestPacked = true; // Fallthrough
10589 case Intrinsic::x86_sse41_ptestnzc:
10590 case Intrinsic::x86_avx_ptestnzc_256:
10592 X86CC = X86::COND_A;
10596 SDValue LHS = Op.getOperand(1);
10597 SDValue RHS = Op.getOperand(2);
10598 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
10599 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
10600 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
10601 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
10602 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10605 // SSE/AVX shift intrinsics
10606 case Intrinsic::x86_sse2_psll_w:
10607 case Intrinsic::x86_sse2_psll_d:
10608 case Intrinsic::x86_sse2_psll_q:
10609 case Intrinsic::x86_avx2_psll_w:
10610 case Intrinsic::x86_avx2_psll_d:
10611 case Intrinsic::x86_avx2_psll_q:
10612 case Intrinsic::x86_sse2_psrl_w:
10613 case Intrinsic::x86_sse2_psrl_d:
10614 case Intrinsic::x86_sse2_psrl_q:
10615 case Intrinsic::x86_avx2_psrl_w:
10616 case Intrinsic::x86_avx2_psrl_d:
10617 case Intrinsic::x86_avx2_psrl_q:
10618 case Intrinsic::x86_sse2_psra_w:
10619 case Intrinsic::x86_sse2_psra_d:
10620 case Intrinsic::x86_avx2_psra_w:
10621 case Intrinsic::x86_avx2_psra_d: {
10624 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10625 case Intrinsic::x86_sse2_psll_w:
10626 case Intrinsic::x86_sse2_psll_d:
10627 case Intrinsic::x86_sse2_psll_q:
10628 case Intrinsic::x86_avx2_psll_w:
10629 case Intrinsic::x86_avx2_psll_d:
10630 case Intrinsic::x86_avx2_psll_q:
10631 Opcode = X86ISD::VSHL;
10633 case Intrinsic::x86_sse2_psrl_w:
10634 case Intrinsic::x86_sse2_psrl_d:
10635 case Intrinsic::x86_sse2_psrl_q:
10636 case Intrinsic::x86_avx2_psrl_w:
10637 case Intrinsic::x86_avx2_psrl_d:
10638 case Intrinsic::x86_avx2_psrl_q:
10639 Opcode = X86ISD::VSRL;
10641 case Intrinsic::x86_sse2_psra_w:
10642 case Intrinsic::x86_sse2_psra_d:
10643 case Intrinsic::x86_avx2_psra_w:
10644 case Intrinsic::x86_avx2_psra_d:
10645 Opcode = X86ISD::VSRA;
10648 return DAG.getNode(Opcode, dl, Op.getValueType(),
10649 Op.getOperand(1), Op.getOperand(2));
10652 // SSE/AVX immediate shift intrinsics
10653 case Intrinsic::x86_sse2_pslli_w:
10654 case Intrinsic::x86_sse2_pslli_d:
10655 case Intrinsic::x86_sse2_pslli_q:
10656 case Intrinsic::x86_avx2_pslli_w:
10657 case Intrinsic::x86_avx2_pslli_d:
10658 case Intrinsic::x86_avx2_pslli_q:
10659 case Intrinsic::x86_sse2_psrli_w:
10660 case Intrinsic::x86_sse2_psrli_d:
10661 case Intrinsic::x86_sse2_psrli_q:
10662 case Intrinsic::x86_avx2_psrli_w:
10663 case Intrinsic::x86_avx2_psrli_d:
10664 case Intrinsic::x86_avx2_psrli_q:
10665 case Intrinsic::x86_sse2_psrai_w:
10666 case Intrinsic::x86_sse2_psrai_d:
10667 case Intrinsic::x86_avx2_psrai_w:
10668 case Intrinsic::x86_avx2_psrai_d: {
10671 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10672 case Intrinsic::x86_sse2_pslli_w:
10673 case Intrinsic::x86_sse2_pslli_d:
10674 case Intrinsic::x86_sse2_pslli_q:
10675 case Intrinsic::x86_avx2_pslli_w:
10676 case Intrinsic::x86_avx2_pslli_d:
10677 case Intrinsic::x86_avx2_pslli_q:
10678 Opcode = X86ISD::VSHLI;
10680 case Intrinsic::x86_sse2_psrli_w:
10681 case Intrinsic::x86_sse2_psrli_d:
10682 case Intrinsic::x86_sse2_psrli_q:
10683 case Intrinsic::x86_avx2_psrli_w:
10684 case Intrinsic::x86_avx2_psrli_d:
10685 case Intrinsic::x86_avx2_psrli_q:
10686 Opcode = X86ISD::VSRLI;
10688 case Intrinsic::x86_sse2_psrai_w:
10689 case Intrinsic::x86_sse2_psrai_d:
10690 case Intrinsic::x86_avx2_psrai_w:
10691 case Intrinsic::x86_avx2_psrai_d:
10692 Opcode = X86ISD::VSRAI;
10695 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
10696 Op.getOperand(1), Op.getOperand(2), DAG);
10699 case Intrinsic::x86_sse42_pcmpistria128:
10700 case Intrinsic::x86_sse42_pcmpestria128:
10701 case Intrinsic::x86_sse42_pcmpistric128:
10702 case Intrinsic::x86_sse42_pcmpestric128:
10703 case Intrinsic::x86_sse42_pcmpistrio128:
10704 case Intrinsic::x86_sse42_pcmpestrio128:
10705 case Intrinsic::x86_sse42_pcmpistris128:
10706 case Intrinsic::x86_sse42_pcmpestris128:
10707 case Intrinsic::x86_sse42_pcmpistriz128:
10708 case Intrinsic::x86_sse42_pcmpestriz128: {
10712 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10713 case Intrinsic::x86_sse42_pcmpistria128:
10714 Opcode = X86ISD::PCMPISTRI;
10715 X86CC = X86::COND_A;
10717 case Intrinsic::x86_sse42_pcmpestria128:
10718 Opcode = X86ISD::PCMPESTRI;
10719 X86CC = X86::COND_A;
10721 case Intrinsic::x86_sse42_pcmpistric128:
10722 Opcode = X86ISD::PCMPISTRI;
10723 X86CC = X86::COND_B;
10725 case Intrinsic::x86_sse42_pcmpestric128:
10726 Opcode = X86ISD::PCMPESTRI;
10727 X86CC = X86::COND_B;
10729 case Intrinsic::x86_sse42_pcmpistrio128:
10730 Opcode = X86ISD::PCMPISTRI;
10731 X86CC = X86::COND_O;
10733 case Intrinsic::x86_sse42_pcmpestrio128:
10734 Opcode = X86ISD::PCMPESTRI;
10735 X86CC = X86::COND_O;
10737 case Intrinsic::x86_sse42_pcmpistris128:
10738 Opcode = X86ISD::PCMPISTRI;
10739 X86CC = X86::COND_S;
10741 case Intrinsic::x86_sse42_pcmpestris128:
10742 Opcode = X86ISD::PCMPESTRI;
10743 X86CC = X86::COND_S;
10745 case Intrinsic::x86_sse42_pcmpistriz128:
10746 Opcode = X86ISD::PCMPISTRI;
10747 X86CC = X86::COND_E;
10749 case Intrinsic::x86_sse42_pcmpestriz128:
10750 Opcode = X86ISD::PCMPESTRI;
10751 X86CC = X86::COND_E;
10754 SmallVector<SDValue, 5> NewOps;
10755 NewOps.append(Op->op_begin()+1, Op->op_end());
10756 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10757 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10758 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10759 DAG.getConstant(X86CC, MVT::i8),
10760 SDValue(PCMP.getNode(), 1));
10761 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10764 case Intrinsic::x86_sse42_pcmpistri128:
10765 case Intrinsic::x86_sse42_pcmpestri128: {
10767 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10768 Opcode = X86ISD::PCMPISTRI;
10770 Opcode = X86ISD::PCMPESTRI;
10772 SmallVector<SDValue, 5> NewOps;
10773 NewOps.append(Op->op_begin()+1, Op->op_end());
10774 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10775 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10777 case Intrinsic::x86_fma_vfmadd_ps:
10778 case Intrinsic::x86_fma_vfmadd_pd:
10779 case Intrinsic::x86_fma_vfmsub_ps:
10780 case Intrinsic::x86_fma_vfmsub_pd:
10781 case Intrinsic::x86_fma_vfnmadd_ps:
10782 case Intrinsic::x86_fma_vfnmadd_pd:
10783 case Intrinsic::x86_fma_vfnmsub_ps:
10784 case Intrinsic::x86_fma_vfnmsub_pd:
10785 case Intrinsic::x86_fma_vfmaddsub_ps:
10786 case Intrinsic::x86_fma_vfmaddsub_pd:
10787 case Intrinsic::x86_fma_vfmsubadd_ps:
10788 case Intrinsic::x86_fma_vfmsubadd_pd:
10789 case Intrinsic::x86_fma_vfmadd_ps_256:
10790 case Intrinsic::x86_fma_vfmadd_pd_256:
10791 case Intrinsic::x86_fma_vfmsub_ps_256:
10792 case Intrinsic::x86_fma_vfmsub_pd_256:
10793 case Intrinsic::x86_fma_vfnmadd_ps_256:
10794 case Intrinsic::x86_fma_vfnmadd_pd_256:
10795 case Intrinsic::x86_fma_vfnmsub_ps_256:
10796 case Intrinsic::x86_fma_vfnmsub_pd_256:
10797 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10798 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10799 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10800 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
10803 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10804 case Intrinsic::x86_fma_vfmadd_ps:
10805 case Intrinsic::x86_fma_vfmadd_pd:
10806 case Intrinsic::x86_fma_vfmadd_ps_256:
10807 case Intrinsic::x86_fma_vfmadd_pd_256:
10808 Opc = X86ISD::FMADD;
10810 case Intrinsic::x86_fma_vfmsub_ps:
10811 case Intrinsic::x86_fma_vfmsub_pd:
10812 case Intrinsic::x86_fma_vfmsub_ps_256:
10813 case Intrinsic::x86_fma_vfmsub_pd_256:
10814 Opc = X86ISD::FMSUB;
10816 case Intrinsic::x86_fma_vfnmadd_ps:
10817 case Intrinsic::x86_fma_vfnmadd_pd:
10818 case Intrinsic::x86_fma_vfnmadd_ps_256:
10819 case Intrinsic::x86_fma_vfnmadd_pd_256:
10820 Opc = X86ISD::FNMADD;
10822 case Intrinsic::x86_fma_vfnmsub_ps:
10823 case Intrinsic::x86_fma_vfnmsub_pd:
10824 case Intrinsic::x86_fma_vfnmsub_ps_256:
10825 case Intrinsic::x86_fma_vfnmsub_pd_256:
10826 Opc = X86ISD::FNMSUB;
10828 case Intrinsic::x86_fma_vfmaddsub_ps:
10829 case Intrinsic::x86_fma_vfmaddsub_pd:
10830 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10831 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10832 Opc = X86ISD::FMADDSUB;
10834 case Intrinsic::x86_fma_vfmsubadd_ps:
10835 case Intrinsic::x86_fma_vfmsubadd_pd:
10836 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10837 case Intrinsic::x86_fma_vfmsubadd_pd_256:
10838 Opc = X86ISD::FMSUBADD;
10842 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
10843 Op.getOperand(2), Op.getOperand(3));
10848 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
10849 DebugLoc dl = Op.getDebugLoc();
10850 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10852 default: return SDValue(); // Don't custom lower most intrinsics.
10854 // RDRAND intrinsics.
10855 case Intrinsic::x86_rdrand_16:
10856 case Intrinsic::x86_rdrand_32:
10857 case Intrinsic::x86_rdrand_64: {
10858 // Emit the node with the right value type.
10859 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10860 SDValue Result = DAG.getNode(X86ISD::RDRAND, dl, VTs, Op.getOperand(0));
10862 // If the value returned by RDRAND was valid (CF=1), return 1. Otherwise
10863 // return the value from Rand, which is always 0, casted to i32.
10864 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10865 DAG.getConstant(1, Op->getValueType(1)),
10866 DAG.getConstant(X86::COND_B, MVT::i32),
10867 SDValue(Result.getNode(), 1) };
10868 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10869 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10872 // Return { result, isValid, chain }.
10873 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10874 SDValue(Result.getNode(), 2));
10879 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
10880 SelectionDAG &DAG) const {
10881 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10882 MFI->setReturnAddressIsTaken(true);
10884 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10885 DebugLoc dl = Op.getDebugLoc();
10886 EVT PtrVT = getPointerTy();
10889 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10891 DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
10892 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10893 DAG.getNode(ISD::ADD, dl, PtrVT,
10894 FrameAddr, Offset),
10895 MachinePointerInfo(), false, false, false, 0);
10898 // Just load the return address.
10899 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
10900 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
10901 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10904 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
10905 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
10906 MFI->setFrameAddressIsTaken(true);
10908 EVT VT = Op.getValueType();
10909 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
10910 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10911 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
10912 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
10914 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
10915 MachinePointerInfo(),
10916 false, false, false, 0);
10920 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
10921 SelectionDAG &DAG) const {
10922 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
10925 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
10926 SDValue Chain = Op.getOperand(0);
10927 SDValue Offset = Op.getOperand(1);
10928 SDValue Handler = Op.getOperand(2);
10929 DebugLoc dl = Op.getDebugLoc();
10931 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
10932 Subtarget->is64Bit() ? X86::RBP : X86::EBP,
10934 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
10936 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame,
10937 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
10938 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
10939 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
10941 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
10943 return DAG.getNode(X86ISD::EH_RETURN, dl,
10945 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
10948 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
10949 SelectionDAG &DAG) const {
10950 DebugLoc DL = Op.getDebugLoc();
10951 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
10952 DAG.getVTList(MVT::i32, MVT::Other),
10953 Op.getOperand(0), Op.getOperand(1));
10956 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
10957 SelectionDAG &DAG) const {
10958 DebugLoc DL = Op.getDebugLoc();
10959 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
10960 Op.getOperand(0), Op.getOperand(1));
10963 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
10964 return Op.getOperand(0);
10967 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
10968 SelectionDAG &DAG) const {
10969 SDValue Root = Op.getOperand(0);
10970 SDValue Trmp = Op.getOperand(1); // trampoline
10971 SDValue FPtr = Op.getOperand(2); // nested function
10972 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
10973 DebugLoc dl = Op.getDebugLoc();
10975 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10976 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
10978 if (Subtarget->is64Bit()) {
10979 SDValue OutChains[6];
10981 // Large code-model.
10982 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
10983 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
10985 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
10986 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
10988 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
10990 // Load the pointer to the nested function into R11.
10991 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
10992 SDValue Addr = Trmp;
10993 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
10994 Addr, MachinePointerInfo(TrmpAddr),
10997 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
10998 DAG.getConstant(2, MVT::i64));
10999 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11000 MachinePointerInfo(TrmpAddr, 2),
11003 // Load the 'nest' parameter value into R10.
11004 // R10 is specified in X86CallingConv.td
11005 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11006 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11007 DAG.getConstant(10, MVT::i64));
11008 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11009 Addr, MachinePointerInfo(TrmpAddr, 10),
11012 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11013 DAG.getConstant(12, MVT::i64));
11014 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11015 MachinePointerInfo(TrmpAddr, 12),
11018 // Jump to the nested function.
11019 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11020 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11021 DAG.getConstant(20, MVT::i64));
11022 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11023 Addr, MachinePointerInfo(TrmpAddr, 20),
11026 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11027 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11028 DAG.getConstant(22, MVT::i64));
11029 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11030 MachinePointerInfo(TrmpAddr, 22),
11033 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11035 const Function *Func =
11036 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11037 CallingConv::ID CC = Func->getCallingConv();
11042 llvm_unreachable("Unsupported calling convention");
11043 case CallingConv::C:
11044 case CallingConv::X86_StdCall: {
11045 // Pass 'nest' parameter in ECX.
11046 // Must be kept in sync with X86CallingConv.td
11047 NestReg = X86::ECX;
11049 // Check that ECX wasn't needed by an 'inreg' parameter.
11050 FunctionType *FTy = Func->getFunctionType();
11051 const AttributeSet &Attrs = Func->getAttributes();
11053 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11054 unsigned InRegCount = 0;
11057 for (FunctionType::param_iterator I = FTy->param_begin(),
11058 E = FTy->param_end(); I != E; ++I, ++Idx)
11059 if (Attrs.getParamAttributes(Idx).hasAttribute(Attribute::InReg))
11060 // FIXME: should only count parameters that are lowered to integers.
11061 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11063 if (InRegCount > 2) {
11064 report_fatal_error("Nest register in use - reduce number of inreg"
11070 case CallingConv::X86_FastCall:
11071 case CallingConv::X86_ThisCall:
11072 case CallingConv::Fast:
11073 // Pass 'nest' parameter in EAX.
11074 // Must be kept in sync with X86CallingConv.td
11075 NestReg = X86::EAX;
11079 SDValue OutChains[4];
11080 SDValue Addr, Disp;
11082 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11083 DAG.getConstant(10, MVT::i32));
11084 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11086 // This is storing the opcode for MOV32ri.
11087 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11088 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11089 OutChains[0] = DAG.getStore(Root, dl,
11090 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11091 Trmp, MachinePointerInfo(TrmpAddr),
11094 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11095 DAG.getConstant(1, MVT::i32));
11096 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11097 MachinePointerInfo(TrmpAddr, 1),
11100 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11101 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11102 DAG.getConstant(5, MVT::i32));
11103 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11104 MachinePointerInfo(TrmpAddr, 5),
11107 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11108 DAG.getConstant(6, MVT::i32));
11109 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11110 MachinePointerInfo(TrmpAddr, 6),
11113 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11117 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11118 SelectionDAG &DAG) const {
11120 The rounding mode is in bits 11:10 of FPSR, and has the following
11122 00 Round to nearest
11127 FLT_ROUNDS, on the other hand, expects the following:
11134 To perform the conversion, we do:
11135 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11138 MachineFunction &MF = DAG.getMachineFunction();
11139 const TargetMachine &TM = MF.getTarget();
11140 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11141 unsigned StackAlignment = TFI.getStackAlignment();
11142 EVT VT = Op.getValueType();
11143 DebugLoc DL = Op.getDebugLoc();
11145 // Save FP Control Word to stack slot
11146 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11147 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11149 MachineMemOperand *MMO =
11150 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11151 MachineMemOperand::MOStore, 2, 2);
11153 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11154 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11155 DAG.getVTList(MVT::Other),
11156 Ops, 2, MVT::i16, MMO);
11158 // Load FP Control Word from stack slot
11159 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11160 MachinePointerInfo(), false, false, false, 0);
11162 // Transform as necessary
11164 DAG.getNode(ISD::SRL, DL, MVT::i16,
11165 DAG.getNode(ISD::AND, DL, MVT::i16,
11166 CWD, DAG.getConstant(0x800, MVT::i16)),
11167 DAG.getConstant(11, MVT::i8));
11169 DAG.getNode(ISD::SRL, DL, MVT::i16,
11170 DAG.getNode(ISD::AND, DL, MVT::i16,
11171 CWD, DAG.getConstant(0x400, MVT::i16)),
11172 DAG.getConstant(9, MVT::i8));
11175 DAG.getNode(ISD::AND, DL, MVT::i16,
11176 DAG.getNode(ISD::ADD, DL, MVT::i16,
11177 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11178 DAG.getConstant(1, MVT::i16)),
11179 DAG.getConstant(3, MVT::i16));
11181 return DAG.getNode((VT.getSizeInBits() < 16 ?
11182 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11185 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11186 EVT VT = Op.getValueType();
11188 unsigned NumBits = VT.getSizeInBits();
11189 DebugLoc dl = Op.getDebugLoc();
11191 Op = Op.getOperand(0);
11192 if (VT == MVT::i8) {
11193 // Zero extend to i32 since there is not an i8 bsr.
11195 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11198 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11199 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11200 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11202 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11205 DAG.getConstant(NumBits+NumBits-1, OpVT),
11206 DAG.getConstant(X86::COND_E, MVT::i8),
11209 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11211 // Finally xor with NumBits-1.
11212 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11215 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11219 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11220 EVT VT = Op.getValueType();
11222 unsigned NumBits = VT.getSizeInBits();
11223 DebugLoc dl = Op.getDebugLoc();
11225 Op = Op.getOperand(0);
11226 if (VT == MVT::i8) {
11227 // Zero extend to i32 since there is not an i8 bsr.
11229 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11232 // Issue a bsr (scan bits in reverse).
11233 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11234 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11236 // And xor with NumBits-1.
11237 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11240 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11244 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11245 EVT VT = Op.getValueType();
11246 unsigned NumBits = VT.getSizeInBits();
11247 DebugLoc dl = Op.getDebugLoc();
11248 Op = Op.getOperand(0);
11250 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11251 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11252 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11254 // If src is zero (i.e. bsf sets ZF), returns NumBits.
11257 DAG.getConstant(NumBits, VT),
11258 DAG.getConstant(X86::COND_E, MVT::i8),
11261 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
11264 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
11265 // ones, and then concatenate the result back.
11266 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
11267 EVT VT = Op.getValueType();
11269 assert(VT.is256BitVector() && VT.isInteger() &&
11270 "Unsupported value type for operation");
11272 unsigned NumElems = VT.getVectorNumElements();
11273 DebugLoc dl = Op.getDebugLoc();
11275 // Extract the LHS vectors
11276 SDValue LHS = Op.getOperand(0);
11277 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11278 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11280 // Extract the RHS vectors
11281 SDValue RHS = Op.getOperand(1);
11282 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
11283 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
11285 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11286 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11288 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11289 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11290 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
11293 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
11294 assert(Op.getValueType().is256BitVector() &&
11295 Op.getValueType().isInteger() &&
11296 "Only handle AVX 256-bit vector integer operation");
11297 return Lower256IntArith(Op, DAG);
11300 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
11301 assert(Op.getValueType().is256BitVector() &&
11302 Op.getValueType().isInteger() &&
11303 "Only handle AVX 256-bit vector integer operation");
11304 return Lower256IntArith(Op, DAG);
11307 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
11308 SelectionDAG &DAG) {
11309 DebugLoc dl = Op.getDebugLoc();
11310 EVT VT = Op.getValueType();
11312 // Decompose 256-bit ops into smaller 128-bit ops.
11313 if (VT.is256BitVector() && !Subtarget->hasInt256())
11314 return Lower256IntArith(Op, DAG);
11316 SDValue A = Op.getOperand(0);
11317 SDValue B = Op.getOperand(1);
11319 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
11320 if (VT == MVT::v4i32) {
11321 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
11322 "Should not custom lower when pmuldq is available!");
11324 // Extract the odd parts.
11325 const int UnpackMask[] = { 1, -1, 3, -1 };
11326 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
11327 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
11329 // Multiply the even parts.
11330 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
11331 // Now multiply odd parts.
11332 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
11334 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
11335 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
11337 // Merge the two vectors back together with a shuffle. This expands into 2
11339 const int ShufMask[] = { 0, 4, 2, 6 };
11340 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
11343 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
11344 "Only know how to lower V2I64/V4I64 multiply");
11346 // Ahi = psrlqi(a, 32);
11347 // Bhi = psrlqi(b, 32);
11349 // AloBlo = pmuludq(a, b);
11350 // AloBhi = pmuludq(a, Bhi);
11351 // AhiBlo = pmuludq(Ahi, b);
11353 // AloBhi = psllqi(AloBhi, 32);
11354 // AhiBlo = psllqi(AhiBlo, 32);
11355 // return AloBlo + AloBhi + AhiBlo;
11357 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11359 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
11360 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
11362 // Bit cast to 32-bit vectors for MULUDQ
11363 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11364 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11365 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11366 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11367 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11369 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
11370 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
11371 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
11373 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
11374 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
11376 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11377 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11380 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
11382 EVT VT = Op.getValueType();
11383 DebugLoc dl = Op.getDebugLoc();
11384 SDValue R = Op.getOperand(0);
11385 SDValue Amt = Op.getOperand(1);
11386 LLVMContext *Context = DAG.getContext();
11388 if (!Subtarget->hasSSE2())
11391 // Optimize shl/srl/sra with constant shift amount.
11392 if (isSplatVector(Amt.getNode())) {
11393 SDValue SclrAmt = Amt->getOperand(0);
11394 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
11395 uint64_t ShiftAmt = C->getZExtValue();
11397 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
11398 (Subtarget->hasInt256() &&
11399 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
11400 if (Op.getOpcode() == ISD::SHL)
11401 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11402 DAG.getConstant(ShiftAmt, MVT::i32));
11403 if (Op.getOpcode() == ISD::SRL)
11404 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11405 DAG.getConstant(ShiftAmt, MVT::i32));
11406 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11407 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11408 DAG.getConstant(ShiftAmt, MVT::i32));
11411 if (VT == MVT::v16i8) {
11412 if (Op.getOpcode() == ISD::SHL) {
11413 // Make a large shift.
11414 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11415 DAG.getConstant(ShiftAmt, MVT::i32));
11416 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11417 // Zero out the rightmost bits.
11418 SmallVector<SDValue, 16> V(16,
11419 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11421 return DAG.getNode(ISD::AND, dl, VT, SHL,
11422 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11424 if (Op.getOpcode() == ISD::SRL) {
11425 // Make a large shift.
11426 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11427 DAG.getConstant(ShiftAmt, MVT::i32));
11428 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11429 // Zero out the leftmost bits.
11430 SmallVector<SDValue, 16> V(16,
11431 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11433 return DAG.getNode(ISD::AND, dl, VT, SRL,
11434 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11436 if (Op.getOpcode() == ISD::SRA) {
11437 if (ShiftAmt == 7) {
11438 // R s>> 7 === R s< 0
11439 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11440 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11443 // R s>> a === ((R u>> a) ^ m) - m
11444 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11445 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
11447 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11448 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11449 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11452 llvm_unreachable("Unknown shift opcode.");
11455 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
11456 if (Op.getOpcode() == ISD::SHL) {
11457 // Make a large shift.
11458 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11459 DAG.getConstant(ShiftAmt, MVT::i32));
11460 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11461 // Zero out the rightmost bits.
11462 SmallVector<SDValue, 32> V(32,
11463 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11465 return DAG.getNode(ISD::AND, dl, VT, SHL,
11466 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11468 if (Op.getOpcode() == ISD::SRL) {
11469 // Make a large shift.
11470 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11471 DAG.getConstant(ShiftAmt, MVT::i32));
11472 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11473 // Zero out the leftmost bits.
11474 SmallVector<SDValue, 32> V(32,
11475 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11477 return DAG.getNode(ISD::AND, dl, VT, SRL,
11478 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11480 if (Op.getOpcode() == ISD::SRA) {
11481 if (ShiftAmt == 7) {
11482 // R s>> 7 === R s< 0
11483 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11484 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11487 // R s>> a === ((R u>> a) ^ m) - m
11488 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11489 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
11491 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11492 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11493 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11496 llvm_unreachable("Unknown shift opcode.");
11501 // Lower SHL with variable shift amount.
11502 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11503 Op = DAG.getNode(X86ISD::VSHLI, dl, VT, Op.getOperand(1),
11504 DAG.getConstant(23, MVT::i32));
11506 const uint32_t CV[] = { 0x3f800000U, 0x3f800000U, 0x3f800000U, 0x3f800000U};
11507 Constant *C = ConstantDataVector::get(*Context, CV);
11508 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
11509 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
11510 MachinePointerInfo::getConstantPool(),
11511 false, false, false, 16);
11513 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend);
11514 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
11515 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
11516 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
11518 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11519 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
11522 Op = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, Op.getOperand(1),
11523 DAG.getConstant(5, MVT::i32));
11524 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
11526 // Turn 'a' into a mask suitable for VSELECT
11527 SDValue VSelM = DAG.getConstant(0x80, VT);
11528 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11529 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11531 SDValue CM1 = DAG.getConstant(0x0f, VT);
11532 SDValue CM2 = DAG.getConstant(0x3f, VT);
11534 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
11535 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
11536 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11537 DAG.getConstant(4, MVT::i32), DAG);
11538 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11539 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11542 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11543 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11544 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11546 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
11547 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
11548 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11549 DAG.getConstant(2, MVT::i32), DAG);
11550 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11551 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11554 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11555 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11556 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11558 // return VSELECT(r, r+r, a);
11559 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
11560 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
11564 // Decompose 256-bit shifts into smaller 128-bit shifts.
11565 if (VT.is256BitVector()) {
11566 unsigned NumElems = VT.getVectorNumElements();
11567 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11568 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11570 // Extract the two vectors
11571 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
11572 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
11574 // Recreate the shift amount vectors
11575 SDValue Amt1, Amt2;
11576 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11577 // Constant shift amount
11578 SmallVector<SDValue, 4> Amt1Csts;
11579 SmallVector<SDValue, 4> Amt2Csts;
11580 for (unsigned i = 0; i != NumElems/2; ++i)
11581 Amt1Csts.push_back(Amt->getOperand(i));
11582 for (unsigned i = NumElems/2; i != NumElems; ++i)
11583 Amt2Csts.push_back(Amt->getOperand(i));
11585 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11586 &Amt1Csts[0], NumElems/2);
11587 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11588 &Amt2Csts[0], NumElems/2);
11590 // Variable shift amount
11591 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
11592 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
11595 // Issue new vector shifts for the smaller types
11596 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
11597 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
11599 // Concatenate the result back
11600 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
11606 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
11607 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
11608 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
11609 // looks for this combo and may remove the "setcc" instruction if the "setcc"
11610 // has only one use.
11611 SDNode *N = Op.getNode();
11612 SDValue LHS = N->getOperand(0);
11613 SDValue RHS = N->getOperand(1);
11614 unsigned BaseOp = 0;
11616 DebugLoc DL = Op.getDebugLoc();
11617 switch (Op.getOpcode()) {
11618 default: llvm_unreachable("Unknown ovf instruction!");
11620 // A subtract of one will be selected as a INC. Note that INC doesn't
11621 // set CF, so we can't do this for UADDO.
11622 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11624 BaseOp = X86ISD::INC;
11625 Cond = X86::COND_O;
11628 BaseOp = X86ISD::ADD;
11629 Cond = X86::COND_O;
11632 BaseOp = X86ISD::ADD;
11633 Cond = X86::COND_B;
11636 // A subtract of one will be selected as a DEC. Note that DEC doesn't
11637 // set CF, so we can't do this for USUBO.
11638 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
11640 BaseOp = X86ISD::DEC;
11641 Cond = X86::COND_O;
11644 BaseOp = X86ISD::SUB;
11645 Cond = X86::COND_O;
11648 BaseOp = X86ISD::SUB;
11649 Cond = X86::COND_B;
11652 BaseOp = X86ISD::SMUL;
11653 Cond = X86::COND_O;
11655 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
11656 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
11658 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
11661 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
11662 DAG.getConstant(X86::COND_O, MVT::i32),
11663 SDValue(Sum.getNode(), 2));
11665 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11669 // Also sets EFLAGS.
11670 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
11671 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
11674 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
11675 DAG.getConstant(Cond, MVT::i32),
11676 SDValue(Sum.getNode(), 1));
11678 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
11681 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
11682 SelectionDAG &DAG) const {
11683 DebugLoc dl = Op.getDebugLoc();
11684 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
11685 EVT VT = Op.getValueType();
11687 if (!Subtarget->hasSSE2() || !VT.isVector())
11690 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
11691 ExtraVT.getScalarType().getSizeInBits();
11692 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
11694 switch (VT.getSimpleVT().SimpleTy) {
11695 default: return SDValue();
11698 if (!Subtarget->hasFp256())
11700 if (!Subtarget->hasInt256()) {
11701 // needs to be split
11702 unsigned NumElems = VT.getVectorNumElements();
11704 // Extract the LHS vectors
11705 SDValue LHS = Op.getOperand(0);
11706 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11707 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11709 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11710 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11712 EVT ExtraEltVT = ExtraVT.getVectorElementType();
11713 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
11714 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
11716 SDValue Extra = DAG.getValueType(ExtraVT);
11718 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
11719 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
11721 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
11726 SDValue Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT,
11727 Op.getOperand(0), ShAmt, DAG);
11728 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
11733 static SDValue LowerMEMBARRIER(SDValue Op, const X86Subtarget *Subtarget,
11734 SelectionDAG &DAG) {
11735 DebugLoc dl = Op.getDebugLoc();
11737 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2.
11738 // There isn't any reason to disable it if the target processor supports it.
11739 if (!Subtarget->hasSSE2() && !Subtarget->is64Bit()) {
11740 SDValue Chain = Op.getOperand(0);
11741 SDValue Zero = DAG.getConstant(0, MVT::i32);
11743 DAG.getRegister(X86::ESP, MVT::i32), // Base
11744 DAG.getTargetConstant(1, MVT::i8), // Scale
11745 DAG.getRegister(0, MVT::i32), // Index
11746 DAG.getTargetConstant(0, MVT::i32), // Disp
11747 DAG.getRegister(0, MVT::i32), // Segment.
11752 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11753 array_lengthof(Ops));
11754 return SDValue(Res, 0);
11757 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
11759 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11761 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11762 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
11763 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
11764 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
11766 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
11767 if (!Op1 && !Op2 && !Op3 && Op4)
11768 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
11770 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
11771 if (Op1 && !Op2 && !Op3 && !Op4)
11772 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
11774 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
11776 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11779 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
11780 SelectionDAG &DAG) {
11781 DebugLoc dl = Op.getDebugLoc();
11782 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
11783 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
11784 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
11785 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
11787 // The only fence that needs an instruction is a sequentially-consistent
11788 // cross-thread fence.
11789 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
11790 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
11791 // no-sse2). There isn't any reason to disable it if the target processor
11793 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
11794 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
11796 SDValue Chain = Op.getOperand(0);
11797 SDValue Zero = DAG.getConstant(0, MVT::i32);
11799 DAG.getRegister(X86::ESP, MVT::i32), // Base
11800 DAG.getTargetConstant(1, MVT::i8), // Scale
11801 DAG.getRegister(0, MVT::i32), // Index
11802 DAG.getTargetConstant(0, MVT::i32), // Disp
11803 DAG.getRegister(0, MVT::i32), // Segment.
11808 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
11809 array_lengthof(Ops));
11810 return SDValue(Res, 0);
11813 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
11814 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
11817 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
11818 SelectionDAG &DAG) {
11819 EVT T = Op.getValueType();
11820 DebugLoc DL = Op.getDebugLoc();
11823 switch(T.getSimpleVT().SimpleTy) {
11824 default: llvm_unreachable("Invalid value type!");
11825 case MVT::i8: Reg = X86::AL; size = 1; break;
11826 case MVT::i16: Reg = X86::AX; size = 2; break;
11827 case MVT::i32: Reg = X86::EAX; size = 4; break;
11829 assert(Subtarget->is64Bit() && "Node not type legal!");
11830 Reg = X86::RAX; size = 8;
11833 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
11834 Op.getOperand(2), SDValue());
11835 SDValue Ops[] = { cpIn.getValue(0),
11838 DAG.getTargetConstant(size, MVT::i8),
11839 cpIn.getValue(1) };
11840 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11841 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
11842 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
11845 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
11849 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
11850 SelectionDAG &DAG) {
11851 assert(Subtarget->is64Bit() && "Result not type legalized?");
11852 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
11853 SDValue TheChain = Op.getOperand(0);
11854 DebugLoc dl = Op.getDebugLoc();
11855 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
11856 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
11857 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
11859 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
11860 DAG.getConstant(32, MVT::i8));
11862 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
11865 return DAG.getMergeValues(Ops, 2, dl);
11868 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
11869 EVT SrcVT = Op.getOperand(0).getValueType();
11870 EVT DstVT = Op.getValueType();
11871 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
11872 Subtarget->hasMMX() && "Unexpected custom BITCAST");
11873 assert((DstVT == MVT::i64 ||
11874 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
11875 "Unexpected custom BITCAST");
11876 // i64 <=> MMX conversions are Legal.
11877 if (SrcVT==MVT::i64 && DstVT.isVector())
11879 if (DstVT==MVT::i64 && SrcVT.isVector())
11881 // MMX <=> MMX conversions are Legal.
11882 if (SrcVT.isVector() && DstVT.isVector())
11884 // All other conversions need to be expanded.
11888 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
11889 SDNode *Node = Op.getNode();
11890 DebugLoc dl = Node->getDebugLoc();
11891 EVT T = Node->getValueType(0);
11892 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
11893 DAG.getConstant(0, T), Node->getOperand(2));
11894 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
11895 cast<AtomicSDNode>(Node)->getMemoryVT(),
11896 Node->getOperand(0),
11897 Node->getOperand(1), negOp,
11898 cast<AtomicSDNode>(Node)->getSrcValue(),
11899 cast<AtomicSDNode>(Node)->getAlignment(),
11900 cast<AtomicSDNode>(Node)->getOrdering(),
11901 cast<AtomicSDNode>(Node)->getSynchScope());
11904 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
11905 SDNode *Node = Op.getNode();
11906 DebugLoc dl = Node->getDebugLoc();
11907 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
11909 // Convert seq_cst store -> xchg
11910 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
11911 // FIXME: On 32-bit, store -> fist or movq would be more efficient
11912 // (The only way to get a 16-byte store is cmpxchg16b)
11913 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
11914 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
11915 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
11916 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
11917 cast<AtomicSDNode>(Node)->getMemoryVT(),
11918 Node->getOperand(0),
11919 Node->getOperand(1), Node->getOperand(2),
11920 cast<AtomicSDNode>(Node)->getMemOperand(),
11921 cast<AtomicSDNode>(Node)->getOrdering(),
11922 cast<AtomicSDNode>(Node)->getSynchScope());
11923 return Swap.getValue(1);
11925 // Other atomic stores have a simple pattern.
11929 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
11930 EVT VT = Op.getNode()->getValueType(0);
11932 // Let legalize expand this if it isn't a legal type yet.
11933 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
11936 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11939 bool ExtraOp = false;
11940 switch (Op.getOpcode()) {
11941 default: llvm_unreachable("Invalid code");
11942 case ISD::ADDC: Opc = X86ISD::ADD; break;
11943 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
11944 case ISD::SUBC: Opc = X86ISD::SUB; break;
11945 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
11949 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11951 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
11952 Op.getOperand(1), Op.getOperand(2));
11955 /// LowerOperation - Provide custom lowering hooks for some operations.
11957 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
11958 switch (Op.getOpcode()) {
11959 default: llvm_unreachable("Should not custom lower this!");
11960 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
11961 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, Subtarget, DAG);
11962 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
11963 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
11964 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
11965 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
11966 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
11967 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
11968 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
11969 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
11970 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
11971 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
11972 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
11973 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
11974 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
11975 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
11976 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
11977 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
11978 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
11979 case ISD::SHL_PARTS:
11980 case ISD::SRA_PARTS:
11981 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
11982 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
11983 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
11984 case ISD::TRUNCATE: return lowerTRUNCATE(Op, DAG);
11985 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
11986 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
11987 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG);
11988 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
11989 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
11990 case ISD::FP_EXTEND: return lowerFP_EXTEND(Op, DAG);
11991 case ISD::FABS: return LowerFABS(Op, DAG);
11992 case ISD::FNEG: return LowerFNEG(Op, DAG);
11993 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
11994 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
11995 case ISD::SETCC: return LowerSETCC(Op, DAG);
11996 case ISD::SELECT: return LowerSELECT(Op, DAG);
11997 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
11998 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
11999 case ISD::VASTART: return LowerVASTART(Op, DAG);
12000 case ISD::VAARG: return LowerVAARG(Op, DAG);
12001 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12002 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12003 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12004 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12005 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12006 case ISD::FRAME_TO_ARGS_OFFSET:
12007 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
12008 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12009 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12010 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12011 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12012 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12013 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12014 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12015 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12016 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12017 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12018 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12021 case ISD::SHL: return LowerShift(Op, DAG);
12027 case ISD::UMULO: return LowerXALUO(Op, DAG);
12028 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
12029 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
12033 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
12034 case ISD::ADD: return LowerADD(Op, DAG);
12035 case ISD::SUB: return LowerSUB(Op, DAG);
12039 static void ReplaceATOMIC_LOAD(SDNode *Node,
12040 SmallVectorImpl<SDValue> &Results,
12041 SelectionDAG &DAG) {
12042 DebugLoc dl = Node->getDebugLoc();
12043 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12045 // Convert wide load -> cmpxchg8b/cmpxchg16b
12046 // FIXME: On 32-bit, load -> fild or movq would be more efficient
12047 // (The only way to get a 16-byte load is cmpxchg16b)
12048 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
12049 SDValue Zero = DAG.getConstant(0, VT);
12050 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
12051 Node->getOperand(0),
12052 Node->getOperand(1), Zero, Zero,
12053 cast<AtomicSDNode>(Node)->getMemOperand(),
12054 cast<AtomicSDNode>(Node)->getOrdering(),
12055 cast<AtomicSDNode>(Node)->getSynchScope());
12056 Results.push_back(Swap.getValue(0));
12057 Results.push_back(Swap.getValue(1));
12061 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
12062 SelectionDAG &DAG, unsigned NewOp) {
12063 DebugLoc dl = Node->getDebugLoc();
12064 assert (Node->getValueType(0) == MVT::i64 &&
12065 "Only know how to expand i64 atomics");
12067 SDValue Chain = Node->getOperand(0);
12068 SDValue In1 = Node->getOperand(1);
12069 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12070 Node->getOperand(2), DAG.getIntPtrConstant(0));
12071 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12072 Node->getOperand(2), DAG.getIntPtrConstant(1));
12073 SDValue Ops[] = { Chain, In1, In2L, In2H };
12074 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
12076 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64,
12077 cast<MemSDNode>(Node)->getMemOperand());
12078 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
12079 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
12080 Results.push_back(Result.getValue(2));
12083 /// ReplaceNodeResults - Replace a node with an illegal result type
12084 /// with a new node built out of custom code.
12085 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
12086 SmallVectorImpl<SDValue>&Results,
12087 SelectionDAG &DAG) const {
12088 DebugLoc dl = N->getDebugLoc();
12089 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12090 switch (N->getOpcode()) {
12092 llvm_unreachable("Do not know how to custom type legalize this operation!");
12093 case ISD::SIGN_EXTEND_INREG:
12098 // We don't want to expand or promote these.
12100 case ISD::FP_TO_SINT:
12101 case ISD::FP_TO_UINT: {
12102 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12104 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
12107 std::pair<SDValue,SDValue> Vals =
12108 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
12109 SDValue FIST = Vals.first, StackSlot = Vals.second;
12110 if (FIST.getNode() != 0) {
12111 EVT VT = N->getValueType(0);
12112 // Return a load from the stack slot.
12113 if (StackSlot.getNode() != 0)
12114 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
12115 MachinePointerInfo(),
12116 false, false, false, 0));
12118 Results.push_back(FIST);
12122 case ISD::UINT_TO_FP: {
12123 if (N->getOperand(0).getValueType() != MVT::v2i32 &&
12124 N->getValueType(0) != MVT::v2f32)
12126 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
12128 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12130 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
12131 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12132 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
12133 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12134 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12135 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12138 case ISD::FP_ROUND: {
12139 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
12141 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
12142 Results.push_back(V);
12145 case ISD::READCYCLECOUNTER: {
12146 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12147 SDValue TheChain = N->getOperand(0);
12148 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12149 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
12151 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
12153 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
12154 SDValue Ops[] = { eax, edx };
12155 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
12156 Results.push_back(edx.getValue(1));
12159 case ISD::ATOMIC_CMP_SWAP: {
12160 EVT T = N->getValueType(0);
12161 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
12162 bool Regs64bit = T == MVT::i128;
12163 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
12164 SDValue cpInL, cpInH;
12165 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12166 DAG.getConstant(0, HalfT));
12167 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12168 DAG.getConstant(1, HalfT));
12169 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
12170 Regs64bit ? X86::RAX : X86::EAX,
12172 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
12173 Regs64bit ? X86::RDX : X86::EDX,
12174 cpInH, cpInL.getValue(1));
12175 SDValue swapInL, swapInH;
12176 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12177 DAG.getConstant(0, HalfT));
12178 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12179 DAG.getConstant(1, HalfT));
12180 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
12181 Regs64bit ? X86::RBX : X86::EBX,
12182 swapInL, cpInH.getValue(1));
12183 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
12184 Regs64bit ? X86::RCX : X86::ECX,
12185 swapInH, swapInL.getValue(1));
12186 SDValue Ops[] = { swapInH.getValue(0),
12188 swapInH.getValue(1) };
12189 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12190 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
12191 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
12192 X86ISD::LCMPXCHG8_DAG;
12193 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
12195 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
12196 Regs64bit ? X86::RAX : X86::EAX,
12197 HalfT, Result.getValue(1));
12198 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
12199 Regs64bit ? X86::RDX : X86::EDX,
12200 HalfT, cpOutL.getValue(2));
12201 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
12202 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
12203 Results.push_back(cpOutH.getValue(1));
12206 case ISD::ATOMIC_LOAD_ADD:
12207 case ISD::ATOMIC_LOAD_AND:
12208 case ISD::ATOMIC_LOAD_NAND:
12209 case ISD::ATOMIC_LOAD_OR:
12210 case ISD::ATOMIC_LOAD_SUB:
12211 case ISD::ATOMIC_LOAD_XOR:
12212 case ISD::ATOMIC_LOAD_MAX:
12213 case ISD::ATOMIC_LOAD_MIN:
12214 case ISD::ATOMIC_LOAD_UMAX:
12215 case ISD::ATOMIC_LOAD_UMIN:
12216 case ISD::ATOMIC_SWAP: {
12218 switch (N->getOpcode()) {
12219 default: llvm_unreachable("Unexpected opcode");
12220 case ISD::ATOMIC_LOAD_ADD:
12221 Opc = X86ISD::ATOMADD64_DAG;
12223 case ISD::ATOMIC_LOAD_AND:
12224 Opc = X86ISD::ATOMAND64_DAG;
12226 case ISD::ATOMIC_LOAD_NAND:
12227 Opc = X86ISD::ATOMNAND64_DAG;
12229 case ISD::ATOMIC_LOAD_OR:
12230 Opc = X86ISD::ATOMOR64_DAG;
12232 case ISD::ATOMIC_LOAD_SUB:
12233 Opc = X86ISD::ATOMSUB64_DAG;
12235 case ISD::ATOMIC_LOAD_XOR:
12236 Opc = X86ISD::ATOMXOR64_DAG;
12238 case ISD::ATOMIC_LOAD_MAX:
12239 Opc = X86ISD::ATOMMAX64_DAG;
12241 case ISD::ATOMIC_LOAD_MIN:
12242 Opc = X86ISD::ATOMMIN64_DAG;
12244 case ISD::ATOMIC_LOAD_UMAX:
12245 Opc = X86ISD::ATOMUMAX64_DAG;
12247 case ISD::ATOMIC_LOAD_UMIN:
12248 Opc = X86ISD::ATOMUMIN64_DAG;
12250 case ISD::ATOMIC_SWAP:
12251 Opc = X86ISD::ATOMSWAP64_DAG;
12254 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
12257 case ISD::ATOMIC_LOAD:
12258 ReplaceATOMIC_LOAD(N, Results, DAG);
12262 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
12264 default: return NULL;
12265 case X86ISD::BSF: return "X86ISD::BSF";
12266 case X86ISD::BSR: return "X86ISD::BSR";
12267 case X86ISD::SHLD: return "X86ISD::SHLD";
12268 case X86ISD::SHRD: return "X86ISD::SHRD";
12269 case X86ISD::FAND: return "X86ISD::FAND";
12270 case X86ISD::FOR: return "X86ISD::FOR";
12271 case X86ISD::FXOR: return "X86ISD::FXOR";
12272 case X86ISD::FSRL: return "X86ISD::FSRL";
12273 case X86ISD::FILD: return "X86ISD::FILD";
12274 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
12275 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
12276 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
12277 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
12278 case X86ISD::FLD: return "X86ISD::FLD";
12279 case X86ISD::FST: return "X86ISD::FST";
12280 case X86ISD::CALL: return "X86ISD::CALL";
12281 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
12282 case X86ISD::BT: return "X86ISD::BT";
12283 case X86ISD::CMP: return "X86ISD::CMP";
12284 case X86ISD::COMI: return "X86ISD::COMI";
12285 case X86ISD::UCOMI: return "X86ISD::UCOMI";
12286 case X86ISD::SETCC: return "X86ISD::SETCC";
12287 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
12288 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
12289 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
12290 case X86ISD::CMOV: return "X86ISD::CMOV";
12291 case X86ISD::BRCOND: return "X86ISD::BRCOND";
12292 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
12293 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
12294 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
12295 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
12296 case X86ISD::Wrapper: return "X86ISD::Wrapper";
12297 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
12298 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
12299 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
12300 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
12301 case X86ISD::PINSRB: return "X86ISD::PINSRB";
12302 case X86ISD::PINSRW: return "X86ISD::PINSRW";
12303 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
12304 case X86ISD::ANDNP: return "X86ISD::ANDNP";
12305 case X86ISD::PSIGN: return "X86ISD::PSIGN";
12306 case X86ISD::BLENDV: return "X86ISD::BLENDV";
12307 case X86ISD::BLENDI: return "X86ISD::BLENDI";
12308 case X86ISD::SUBUS: return "X86ISD::SUBUS";
12309 case X86ISD::HADD: return "X86ISD::HADD";
12310 case X86ISD::HSUB: return "X86ISD::HSUB";
12311 case X86ISD::FHADD: return "X86ISD::FHADD";
12312 case X86ISD::FHSUB: return "X86ISD::FHSUB";
12313 case X86ISD::UMAX: return "X86ISD::UMAX";
12314 case X86ISD::UMIN: return "X86ISD::UMIN";
12315 case X86ISD::SMAX: return "X86ISD::SMAX";
12316 case X86ISD::SMIN: return "X86ISD::SMIN";
12317 case X86ISD::FMAX: return "X86ISD::FMAX";
12318 case X86ISD::FMIN: return "X86ISD::FMIN";
12319 case X86ISD::FMAXC: return "X86ISD::FMAXC";
12320 case X86ISD::FMINC: return "X86ISD::FMINC";
12321 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
12322 case X86ISD::FRCP: return "X86ISD::FRCP";
12323 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
12324 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
12325 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
12326 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
12327 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
12328 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
12329 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
12330 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
12331 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
12332 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
12333 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
12334 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
12335 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
12336 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
12337 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
12338 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
12339 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
12340 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
12341 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
12342 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
12343 case X86ISD::VZEXT: return "X86ISD::VZEXT";
12344 case X86ISD::VSEXT: return "X86ISD::VSEXT";
12345 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
12346 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
12347 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
12348 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
12349 case X86ISD::VSHL: return "X86ISD::VSHL";
12350 case X86ISD::VSRL: return "X86ISD::VSRL";
12351 case X86ISD::VSRA: return "X86ISD::VSRA";
12352 case X86ISD::VSHLI: return "X86ISD::VSHLI";
12353 case X86ISD::VSRLI: return "X86ISD::VSRLI";
12354 case X86ISD::VSRAI: return "X86ISD::VSRAI";
12355 case X86ISD::CMPP: return "X86ISD::CMPP";
12356 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
12357 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
12358 case X86ISD::ADD: return "X86ISD::ADD";
12359 case X86ISD::SUB: return "X86ISD::SUB";
12360 case X86ISD::ADC: return "X86ISD::ADC";
12361 case X86ISD::SBB: return "X86ISD::SBB";
12362 case X86ISD::SMUL: return "X86ISD::SMUL";
12363 case X86ISD::UMUL: return "X86ISD::UMUL";
12364 case X86ISD::INC: return "X86ISD::INC";
12365 case X86ISD::DEC: return "X86ISD::DEC";
12366 case X86ISD::OR: return "X86ISD::OR";
12367 case X86ISD::XOR: return "X86ISD::XOR";
12368 case X86ISD::AND: return "X86ISD::AND";
12369 case X86ISD::BLSI: return "X86ISD::BLSI";
12370 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
12371 case X86ISD::BLSR: return "X86ISD::BLSR";
12372 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
12373 case X86ISD::PTEST: return "X86ISD::PTEST";
12374 case X86ISD::TESTP: return "X86ISD::TESTP";
12375 case X86ISD::PALIGN: return "X86ISD::PALIGN";
12376 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
12377 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
12378 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
12379 case X86ISD::SHUFP: return "X86ISD::SHUFP";
12380 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
12381 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
12382 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
12383 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
12384 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
12385 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
12386 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
12387 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
12388 case X86ISD::MOVSD: return "X86ISD::MOVSD";
12389 case X86ISD::MOVSS: return "X86ISD::MOVSS";
12390 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
12391 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
12392 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
12393 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
12394 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
12395 case X86ISD::VPERMV: return "X86ISD::VPERMV";
12396 case X86ISD::VPERMI: return "X86ISD::VPERMI";
12397 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
12398 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
12399 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
12400 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
12401 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
12402 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
12403 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
12404 case X86ISD::SAHF: return "X86ISD::SAHF";
12405 case X86ISD::RDRAND: return "X86ISD::RDRAND";
12406 case X86ISD::FMADD: return "X86ISD::FMADD";
12407 case X86ISD::FMSUB: return "X86ISD::FMSUB";
12408 case X86ISD::FNMADD: return "X86ISD::FNMADD";
12409 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
12410 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
12411 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
12412 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
12413 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
12417 // isLegalAddressingMode - Return true if the addressing mode represented
12418 // by AM is legal for this target, for a load/store of the specified type.
12419 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
12421 // X86 supports extremely general addressing modes.
12422 CodeModel::Model M = getTargetMachine().getCodeModel();
12423 Reloc::Model R = getTargetMachine().getRelocationModel();
12425 // X86 allows a sign-extended 32-bit immediate field as a displacement.
12426 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
12431 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
12433 // If a reference to this global requires an extra load, we can't fold it.
12434 if (isGlobalStubReference(GVFlags))
12437 // If BaseGV requires a register for the PIC base, we cannot also have a
12438 // BaseReg specified.
12439 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
12442 // If lower 4G is not available, then we must use rip-relative addressing.
12443 if ((M != CodeModel::Small || R != Reloc::Static) &&
12444 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
12448 switch (AM.Scale) {
12454 // These scales always work.
12459 // These scales are formed with basereg+scalereg. Only accept if there is
12464 default: // Other stuff never works.
12471 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
12472 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
12474 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
12475 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
12476 return NumBits1 > NumBits2;
12479 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
12480 return isInt<32>(Imm);
12483 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
12484 // Can also use sub to handle negated immediates.
12485 return isInt<32>(Imm);
12488 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
12489 if (!VT1.isInteger() || !VT2.isInteger())
12491 unsigned NumBits1 = VT1.getSizeInBits();
12492 unsigned NumBits2 = VT2.getSizeInBits();
12493 return NumBits1 > NumBits2;
12496 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
12497 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12498 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
12501 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
12502 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12503 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
12506 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
12507 EVT VT1 = Val.getValueType();
12508 if (isZExtFree(VT1, VT2))
12511 if (Val.getOpcode() != ISD::LOAD)
12514 if (!VT1.isSimple() || !VT1.isInteger() ||
12515 !VT2.isSimple() || !VT2.isInteger())
12518 switch (VT1.getSimpleVT().SimpleTy) {
12523 // X86 has 8, 16, and 32-bit zero-extending loads.
12530 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
12531 // i16 instructions are longer (0x66 prefix) and potentially slower.
12532 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
12535 /// isShuffleMaskLegal - Targets can use this to indicate that they only
12536 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
12537 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
12538 /// are assumed to be legal.
12540 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
12542 // Very little shuffling can be done for 64-bit vectors right now.
12543 if (VT.getSizeInBits() == 64)
12546 // FIXME: pshufb, blends, shifts.
12547 return (VT.getVectorNumElements() == 2 ||
12548 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
12549 isMOVLMask(M, VT) ||
12550 isSHUFPMask(M, VT, Subtarget->hasFp256()) ||
12551 isPSHUFDMask(M, VT) ||
12552 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) ||
12553 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) ||
12554 isPALIGNRMask(M, VT, Subtarget) ||
12555 isUNPCKLMask(M, VT, Subtarget->hasInt256()) ||
12556 isUNPCKHMask(M, VT, Subtarget->hasInt256()) ||
12557 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) ||
12558 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256()));
12562 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
12564 unsigned NumElts = VT.getVectorNumElements();
12565 // FIXME: This collection of masks seems suspect.
12568 if (NumElts == 4 && VT.is128BitVector()) {
12569 return (isMOVLMask(Mask, VT) ||
12570 isCommutedMOVLMask(Mask, VT, true) ||
12571 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) ||
12572 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true));
12577 //===----------------------------------------------------------------------===//
12578 // X86 Scheduler Hooks
12579 //===----------------------------------------------------------------------===//
12581 /// Utility function to emit xbegin specifying the start of an RTM region.
12582 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
12583 const TargetInstrInfo *TII) {
12584 DebugLoc DL = MI->getDebugLoc();
12586 const BasicBlock *BB = MBB->getBasicBlock();
12587 MachineFunction::iterator I = MBB;
12590 // For the v = xbegin(), we generate
12601 MachineBasicBlock *thisMBB = MBB;
12602 MachineFunction *MF = MBB->getParent();
12603 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12604 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12605 MF->insert(I, mainMBB);
12606 MF->insert(I, sinkMBB);
12608 // Transfer the remainder of BB and its successor edges to sinkMBB.
12609 sinkMBB->splice(sinkMBB->begin(), MBB,
12610 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12611 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12615 // # fallthrough to mainMBB
12616 // # abortion to sinkMBB
12617 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
12618 thisMBB->addSuccessor(mainMBB);
12619 thisMBB->addSuccessor(sinkMBB);
12623 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
12624 mainMBB->addSuccessor(sinkMBB);
12627 // EAX is live into the sinkMBB
12628 sinkMBB->addLiveIn(X86::EAX);
12629 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12630 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
12633 MI->eraseFromParent();
12637 // Get CMPXCHG opcode for the specified data type.
12638 static unsigned getCmpXChgOpcode(EVT VT) {
12639 switch (VT.getSimpleVT().SimpleTy) {
12640 case MVT::i8: return X86::LCMPXCHG8;
12641 case MVT::i16: return X86::LCMPXCHG16;
12642 case MVT::i32: return X86::LCMPXCHG32;
12643 case MVT::i64: return X86::LCMPXCHG64;
12647 llvm_unreachable("Invalid operand size!");
12650 // Get LOAD opcode for the specified data type.
12651 static unsigned getLoadOpcode(EVT VT) {
12652 switch (VT.getSimpleVT().SimpleTy) {
12653 case MVT::i8: return X86::MOV8rm;
12654 case MVT::i16: return X86::MOV16rm;
12655 case MVT::i32: return X86::MOV32rm;
12656 case MVT::i64: return X86::MOV64rm;
12660 llvm_unreachable("Invalid operand size!");
12663 // Get opcode of the non-atomic one from the specified atomic instruction.
12664 static unsigned getNonAtomicOpcode(unsigned Opc) {
12666 case X86::ATOMAND8: return X86::AND8rr;
12667 case X86::ATOMAND16: return X86::AND16rr;
12668 case X86::ATOMAND32: return X86::AND32rr;
12669 case X86::ATOMAND64: return X86::AND64rr;
12670 case X86::ATOMOR8: return X86::OR8rr;
12671 case X86::ATOMOR16: return X86::OR16rr;
12672 case X86::ATOMOR32: return X86::OR32rr;
12673 case X86::ATOMOR64: return X86::OR64rr;
12674 case X86::ATOMXOR8: return X86::XOR8rr;
12675 case X86::ATOMXOR16: return X86::XOR16rr;
12676 case X86::ATOMXOR32: return X86::XOR32rr;
12677 case X86::ATOMXOR64: return X86::XOR64rr;
12679 llvm_unreachable("Unhandled atomic-load-op opcode!");
12682 // Get opcode of the non-atomic one from the specified atomic instruction with
12684 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
12685 unsigned &ExtraOpc) {
12687 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
12688 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
12689 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
12690 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
12691 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
12692 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
12693 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
12694 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
12695 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
12696 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
12697 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
12698 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
12699 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
12700 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
12701 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
12702 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
12703 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
12704 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
12705 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
12706 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
12708 llvm_unreachable("Unhandled atomic-load-op opcode!");
12711 // Get opcode of the non-atomic one from the specified atomic instruction for
12712 // 64-bit data type on 32-bit target.
12713 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
12715 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
12716 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
12717 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
12718 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
12719 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
12720 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
12721 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
12722 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
12723 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
12724 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
12726 llvm_unreachable("Unhandled atomic-load-op opcode!");
12729 // Get opcode of the non-atomic one from the specified atomic instruction for
12730 // 64-bit data type on 32-bit target with extra opcode.
12731 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
12733 unsigned &ExtraOpc) {
12735 case X86::ATOMNAND6432:
12736 ExtraOpc = X86::NOT32r;
12737 HiOpc = X86::AND32rr;
12738 return X86::AND32rr;
12740 llvm_unreachable("Unhandled atomic-load-op opcode!");
12743 // Get pseudo CMOV opcode from the specified data type.
12744 static unsigned getPseudoCMOVOpc(EVT VT) {
12745 switch (VT.getSimpleVT().SimpleTy) {
12746 case MVT::i8: return X86::CMOV_GR8;
12747 case MVT::i16: return X86::CMOV_GR16;
12748 case MVT::i32: return X86::CMOV_GR32;
12752 llvm_unreachable("Unknown CMOV opcode!");
12755 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
12756 // They will be translated into a spin-loop or compare-exchange loop from
12759 // dst = atomic-fetch-op MI.addr, MI.val
12765 // EAX = LOAD MI.addr
12767 // t1 = OP MI.val, EAX
12768 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12773 MachineBasicBlock *
12774 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
12775 MachineBasicBlock *MBB) const {
12776 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
12777 DebugLoc DL = MI->getDebugLoc();
12779 MachineFunction *MF = MBB->getParent();
12780 MachineRegisterInfo &MRI = MF->getRegInfo();
12782 const BasicBlock *BB = MBB->getBasicBlock();
12783 MachineFunction::iterator I = MBB;
12786 assert(MI->getNumOperands() <= X86::AddrNumOperands + 2 &&
12787 "Unexpected number of operands");
12789 assert(MI->hasOneMemOperand() &&
12790 "Expected atomic-load-op to have one memoperand");
12792 // Memory Reference
12793 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
12794 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
12796 unsigned DstReg, SrcReg;
12797 unsigned MemOpndSlot;
12799 unsigned CurOp = 0;
12801 DstReg = MI->getOperand(CurOp++).getReg();
12802 MemOpndSlot = CurOp;
12803 CurOp += X86::AddrNumOperands;
12804 SrcReg = MI->getOperand(CurOp++).getReg();
12806 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
12807 MVT::SimpleValueType VT = *RC->vt_begin();
12808 unsigned AccPhyReg = getX86SubSuperRegister(X86::EAX, VT);
12810 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
12811 unsigned LOADOpc = getLoadOpcode(VT);
12813 // For the atomic load-arith operator, we generate
12816 // EAX = LOAD [MI.addr]
12818 // t1 = OP MI.val, EAX
12819 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
12823 MachineBasicBlock *thisMBB = MBB;
12824 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
12825 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
12826 MF->insert(I, mainMBB);
12827 MF->insert(I, sinkMBB);
12829 MachineInstrBuilder MIB;
12831 // Transfer the remainder of BB and its successor edges to sinkMBB.
12832 sinkMBB->splice(sinkMBB->begin(), MBB,
12833 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
12834 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
12837 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), AccPhyReg);
12838 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12839 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12840 MIB.setMemRefs(MMOBegin, MMOEnd);
12842 thisMBB->addSuccessor(mainMBB);
12845 MachineBasicBlock *origMainMBB = mainMBB;
12846 mainMBB->addLiveIn(AccPhyReg);
12848 // Copy AccPhyReg as it is used more than once.
12849 unsigned AccReg = MRI.createVirtualRegister(RC);
12850 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccReg)
12851 .addReg(AccPhyReg);
12853 unsigned t1 = MRI.createVirtualRegister(RC);
12854 unsigned Opc = MI->getOpcode();
12857 llvm_unreachable("Unhandled atomic-load-op opcode!");
12858 case X86::ATOMAND8:
12859 case X86::ATOMAND16:
12860 case X86::ATOMAND32:
12861 case X86::ATOMAND64:
12863 case X86::ATOMOR16:
12864 case X86::ATOMOR32:
12865 case X86::ATOMOR64:
12866 case X86::ATOMXOR8:
12867 case X86::ATOMXOR16:
12868 case X86::ATOMXOR32:
12869 case X86::ATOMXOR64: {
12870 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
12871 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t1).addReg(SrcReg)
12875 case X86::ATOMNAND8:
12876 case X86::ATOMNAND16:
12877 case X86::ATOMNAND32:
12878 case X86::ATOMNAND64: {
12879 unsigned t2 = MRI.createVirtualRegister(RC);
12881 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
12882 BuildMI(mainMBB, DL, TII->get(ANDOpc), t2).addReg(SrcReg)
12884 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1).addReg(t2);
12887 case X86::ATOMMAX8:
12888 case X86::ATOMMAX16:
12889 case X86::ATOMMAX32:
12890 case X86::ATOMMAX64:
12891 case X86::ATOMMIN8:
12892 case X86::ATOMMIN16:
12893 case X86::ATOMMIN32:
12894 case X86::ATOMMIN64:
12895 case X86::ATOMUMAX8:
12896 case X86::ATOMUMAX16:
12897 case X86::ATOMUMAX32:
12898 case X86::ATOMUMAX64:
12899 case X86::ATOMUMIN8:
12900 case X86::ATOMUMIN16:
12901 case X86::ATOMUMIN32:
12902 case X86::ATOMUMIN64: {
12904 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
12906 BuildMI(mainMBB, DL, TII->get(CMPOpc))
12910 if (Subtarget->hasCMov()) {
12911 if (VT != MVT::i8) {
12913 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t1)
12917 // Promote i8 to i32 to use CMOV32
12918 const TargetRegisterClass *RC32 = getRegClassFor(MVT::i32);
12919 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
12920 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
12921 unsigned t2 = MRI.createVirtualRegister(RC32);
12923 unsigned Undef = MRI.createVirtualRegister(RC32);
12924 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
12926 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
12929 .addImm(X86::sub_8bit);
12930 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
12933 .addImm(X86::sub_8bit);
12935 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
12939 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t1)
12940 .addReg(t2, 0, X86::sub_8bit);
12943 // Use pseudo select and lower them.
12944 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
12945 "Invalid atomic-load-op transformation!");
12946 unsigned SelOpc = getPseudoCMOVOpc(VT);
12947 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
12948 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
12949 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t1)
12950 .addReg(SrcReg).addReg(AccReg)
12952 mainMBB = EmitLoweredSelect(MIB, mainMBB);
12958 // Copy AccPhyReg back from virtual register.
12959 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), AccPhyReg)
12962 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
12963 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
12964 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
12966 MIB.setMemRefs(MMOBegin, MMOEnd);
12968 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
12970 mainMBB->addSuccessor(origMainMBB);
12971 mainMBB->addSuccessor(sinkMBB);
12974 sinkMBB->addLiveIn(AccPhyReg);
12976 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
12977 TII->get(TargetOpcode::COPY), DstReg)
12978 .addReg(AccPhyReg);
12980 MI->eraseFromParent();
12984 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
12985 // instructions. They will be translated into a spin-loop or compare-exchange
12989 // dst = atomic-fetch-op MI.addr, MI.val
12995 // EAX = LOAD [MI.addr + 0]
12996 // EDX = LOAD [MI.addr + 4]
12998 // EBX = OP MI.val.lo, EAX
12999 // ECX = OP MI.val.hi, EDX
13000 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13005 MachineBasicBlock *
13006 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
13007 MachineBasicBlock *MBB) const {
13008 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13009 DebugLoc DL = MI->getDebugLoc();
13011 MachineFunction *MF = MBB->getParent();
13012 MachineRegisterInfo &MRI = MF->getRegInfo();
13014 const BasicBlock *BB = MBB->getBasicBlock();
13015 MachineFunction::iterator I = MBB;
13018 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
13019 "Unexpected number of operands");
13021 assert(MI->hasOneMemOperand() &&
13022 "Expected atomic-load-op32 to have one memoperand");
13024 // Memory Reference
13025 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13026 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13028 unsigned DstLoReg, DstHiReg;
13029 unsigned SrcLoReg, SrcHiReg;
13030 unsigned MemOpndSlot;
13032 unsigned CurOp = 0;
13034 DstLoReg = MI->getOperand(CurOp++).getReg();
13035 DstHiReg = MI->getOperand(CurOp++).getReg();
13036 MemOpndSlot = CurOp;
13037 CurOp += X86::AddrNumOperands;
13038 SrcLoReg = MI->getOperand(CurOp++).getReg();
13039 SrcHiReg = MI->getOperand(CurOp++).getReg();
13041 const TargetRegisterClass *RC = &X86::GR32RegClass;
13042 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
13044 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
13045 unsigned LOADOpc = X86::MOV32rm;
13047 // For the atomic load-arith operator, we generate
13050 // EAX = LOAD [MI.addr + 0]
13051 // EDX = LOAD [MI.addr + 4]
13053 // EBX = OP MI.vallo, EAX
13054 // ECX = OP MI.valhi, EDX
13055 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13059 MachineBasicBlock *thisMBB = MBB;
13060 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13061 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13062 MF->insert(I, mainMBB);
13063 MF->insert(I, sinkMBB);
13065 MachineInstrBuilder MIB;
13067 // Transfer the remainder of BB and its successor edges to sinkMBB.
13068 sinkMBB->splice(sinkMBB->begin(), MBB,
13069 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13070 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13074 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EAX);
13075 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13076 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13077 MIB.setMemRefs(MMOBegin, MMOEnd);
13079 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), X86::EDX);
13080 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13081 if (i == X86::AddrDisp)
13082 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
13084 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13086 MIB.setMemRefs(MMOBegin, MMOEnd);
13088 thisMBB->addSuccessor(mainMBB);
13091 MachineBasicBlock *origMainMBB = mainMBB;
13092 mainMBB->addLiveIn(X86::EAX);
13093 mainMBB->addLiveIn(X86::EDX);
13095 // Copy EDX:EAX as they are used more than once.
13096 unsigned LoReg = MRI.createVirtualRegister(RC);
13097 unsigned HiReg = MRI.createVirtualRegister(RC);
13098 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), LoReg).addReg(X86::EAX);
13099 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), HiReg).addReg(X86::EDX);
13101 unsigned t1L = MRI.createVirtualRegister(RC);
13102 unsigned t1H = MRI.createVirtualRegister(RC);
13104 unsigned Opc = MI->getOpcode();
13107 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
13108 case X86::ATOMAND6432:
13109 case X86::ATOMOR6432:
13110 case X86::ATOMXOR6432:
13111 case X86::ATOMADD6432:
13112 case X86::ATOMSUB6432: {
13114 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13115 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(LoReg).addReg(SrcLoReg);
13116 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(HiReg).addReg(SrcHiReg);
13119 case X86::ATOMNAND6432: {
13120 unsigned HiOpc, NOTOpc;
13121 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
13122 unsigned t2L = MRI.createVirtualRegister(RC);
13123 unsigned t2H = MRI.createVirtualRegister(RC);
13124 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg).addReg(LoReg);
13125 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg).addReg(HiReg);
13126 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1L).addReg(t2L);
13127 BuildMI(mainMBB, DL, TII->get(NOTOpc), t1H).addReg(t2H);
13130 case X86::ATOMMAX6432:
13131 case X86::ATOMMIN6432:
13132 case X86::ATOMUMAX6432:
13133 case X86::ATOMUMIN6432: {
13135 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13136 unsigned cL = MRI.createVirtualRegister(RC8);
13137 unsigned cH = MRI.createVirtualRegister(RC8);
13138 unsigned cL32 = MRI.createVirtualRegister(RC);
13139 unsigned cH32 = MRI.createVirtualRegister(RC);
13140 unsigned cc = MRI.createVirtualRegister(RC);
13141 // cl := cmp src_lo, lo
13142 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13143 .addReg(SrcLoReg).addReg(LoReg);
13144 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
13145 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
13146 // ch := cmp src_hi, hi
13147 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13148 .addReg(SrcHiReg).addReg(HiReg);
13149 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
13150 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
13151 // cc := if (src_hi == hi) ? cl : ch;
13152 if (Subtarget->hasCMov()) {
13153 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
13154 .addReg(cH32).addReg(cL32);
13156 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
13157 .addReg(cH32).addReg(cL32)
13158 .addImm(X86::COND_E);
13159 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13161 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
13162 if (Subtarget->hasCMov()) {
13163 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1L)
13164 .addReg(SrcLoReg).addReg(LoReg);
13165 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t1H)
13166 .addReg(SrcHiReg).addReg(HiReg);
13168 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1L)
13169 .addReg(SrcLoReg).addReg(LoReg)
13170 .addImm(X86::COND_NE);
13171 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13172 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t1H)
13173 .addReg(SrcHiReg).addReg(HiReg)
13174 .addImm(X86::COND_NE);
13175 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13179 case X86::ATOMSWAP6432: {
13181 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13182 BuildMI(mainMBB, DL, TII->get(LoOpc), t1L).addReg(SrcLoReg);
13183 BuildMI(mainMBB, DL, TII->get(HiOpc), t1H).addReg(SrcHiReg);
13188 // Copy EDX:EAX back from HiReg:LoReg
13189 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(LoReg);
13190 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(HiReg);
13191 // Copy ECX:EBX from t1H:t1L
13192 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t1L);
13193 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t1H);
13195 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13196 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
13197 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
13198 MIB.setMemRefs(MMOBegin, MMOEnd);
13200 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13202 mainMBB->addSuccessor(origMainMBB);
13203 mainMBB->addSuccessor(sinkMBB);
13206 sinkMBB->addLiveIn(X86::EAX);
13207 sinkMBB->addLiveIn(X86::EDX);
13209 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13210 TII->get(TargetOpcode::COPY), DstLoReg)
13212 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13213 TII->get(TargetOpcode::COPY), DstHiReg)
13216 MI->eraseFromParent();
13220 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
13221 // or XMM0_V32I8 in AVX all of this code can be replaced with that
13222 // in the .td file.
13223 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
13224 const TargetInstrInfo *TII) {
13226 switch (MI->getOpcode()) {
13227 default: llvm_unreachable("illegal opcode!");
13228 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
13229 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
13230 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
13231 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
13232 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
13233 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
13234 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
13235 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
13238 DebugLoc dl = MI->getDebugLoc();
13239 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13241 unsigned NumArgs = MI->getNumOperands();
13242 for (unsigned i = 1; i < NumArgs; ++i) {
13243 MachineOperand &Op = MI->getOperand(i);
13244 if (!(Op.isReg() && Op.isImplicit()))
13245 MIB.addOperand(Op);
13247 if (MI->hasOneMemOperand())
13248 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13250 BuildMI(*BB, MI, dl,
13251 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13252 .addReg(X86::XMM0);
13254 MI->eraseFromParent();
13258 // FIXME: Custom handling because TableGen doesn't support multiple implicit
13259 // defs in an instruction pattern
13260 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
13261 const TargetInstrInfo *TII) {
13263 switch (MI->getOpcode()) {
13264 default: llvm_unreachable("illegal opcode!");
13265 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
13266 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
13267 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
13268 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
13269 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
13270 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
13271 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
13272 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
13275 DebugLoc dl = MI->getDebugLoc();
13276 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13278 unsigned NumArgs = MI->getNumOperands(); // remove the results
13279 for (unsigned i = 1; i < NumArgs; ++i) {
13280 MachineOperand &Op = MI->getOperand(i);
13281 if (!(Op.isReg() && Op.isImplicit()))
13282 MIB.addOperand(Op);
13284 if (MI->hasOneMemOperand())
13285 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13287 BuildMI(*BB, MI, dl,
13288 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13291 MI->eraseFromParent();
13295 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
13296 const TargetInstrInfo *TII,
13297 const X86Subtarget* Subtarget) {
13298 DebugLoc dl = MI->getDebugLoc();
13300 // Address into RAX/EAX, other two args into ECX, EDX.
13301 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
13302 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13303 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
13304 for (int i = 0; i < X86::AddrNumOperands; ++i)
13305 MIB.addOperand(MI->getOperand(i));
13307 unsigned ValOps = X86::AddrNumOperands;
13308 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
13309 .addReg(MI->getOperand(ValOps).getReg());
13310 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
13311 .addReg(MI->getOperand(ValOps+1).getReg());
13313 // The instruction doesn't actually take any operands though.
13314 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
13316 MI->eraseFromParent(); // The pseudo is gone now.
13320 MachineBasicBlock *
13321 X86TargetLowering::EmitVAARG64WithCustomInserter(
13323 MachineBasicBlock *MBB) const {
13324 // Emit va_arg instruction on X86-64.
13326 // Operands to this pseudo-instruction:
13327 // 0 ) Output : destination address (reg)
13328 // 1-5) Input : va_list address (addr, i64mem)
13329 // 6 ) ArgSize : Size (in bytes) of vararg type
13330 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
13331 // 8 ) Align : Alignment of type
13332 // 9 ) EFLAGS (implicit-def)
13334 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
13335 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
13337 unsigned DestReg = MI->getOperand(0).getReg();
13338 MachineOperand &Base = MI->getOperand(1);
13339 MachineOperand &Scale = MI->getOperand(2);
13340 MachineOperand &Index = MI->getOperand(3);
13341 MachineOperand &Disp = MI->getOperand(4);
13342 MachineOperand &Segment = MI->getOperand(5);
13343 unsigned ArgSize = MI->getOperand(6).getImm();
13344 unsigned ArgMode = MI->getOperand(7).getImm();
13345 unsigned Align = MI->getOperand(8).getImm();
13347 // Memory Reference
13348 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
13349 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13350 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13352 // Machine Information
13353 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13354 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
13355 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
13356 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
13357 DebugLoc DL = MI->getDebugLoc();
13359 // struct va_list {
13362 // i64 overflow_area (address)
13363 // i64 reg_save_area (address)
13365 // sizeof(va_list) = 24
13366 // alignment(va_list) = 8
13368 unsigned TotalNumIntRegs = 6;
13369 unsigned TotalNumXMMRegs = 8;
13370 bool UseGPOffset = (ArgMode == 1);
13371 bool UseFPOffset = (ArgMode == 2);
13372 unsigned MaxOffset = TotalNumIntRegs * 8 +
13373 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
13375 /* Align ArgSize to a multiple of 8 */
13376 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
13377 bool NeedsAlign = (Align > 8);
13379 MachineBasicBlock *thisMBB = MBB;
13380 MachineBasicBlock *overflowMBB;
13381 MachineBasicBlock *offsetMBB;
13382 MachineBasicBlock *endMBB;
13384 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
13385 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
13386 unsigned OffsetReg = 0;
13388 if (!UseGPOffset && !UseFPOffset) {
13389 // If we only pull from the overflow region, we don't create a branch.
13390 // We don't need to alter control flow.
13391 OffsetDestReg = 0; // unused
13392 OverflowDestReg = DestReg;
13395 overflowMBB = thisMBB;
13398 // First emit code to check if gp_offset (or fp_offset) is below the bound.
13399 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
13400 // If not, pull from overflow_area. (branch to overflowMBB)
13405 // offsetMBB overflowMBB
13410 // Registers for the PHI in endMBB
13411 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
13412 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
13414 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13415 MachineFunction *MF = MBB->getParent();
13416 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13417 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13418 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13420 MachineFunction::iterator MBBIter = MBB;
13423 // Insert the new basic blocks
13424 MF->insert(MBBIter, offsetMBB);
13425 MF->insert(MBBIter, overflowMBB);
13426 MF->insert(MBBIter, endMBB);
13428 // Transfer the remainder of MBB and its successor edges to endMBB.
13429 endMBB->splice(endMBB->begin(), thisMBB,
13430 llvm::next(MachineBasicBlock::iterator(MI)),
13432 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
13434 // Make offsetMBB and overflowMBB successors of thisMBB
13435 thisMBB->addSuccessor(offsetMBB);
13436 thisMBB->addSuccessor(overflowMBB);
13438 // endMBB is a successor of both offsetMBB and overflowMBB
13439 offsetMBB->addSuccessor(endMBB);
13440 overflowMBB->addSuccessor(endMBB);
13442 // Load the offset value into a register
13443 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13444 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
13448 .addDisp(Disp, UseFPOffset ? 4 : 0)
13449 .addOperand(Segment)
13450 .setMemRefs(MMOBegin, MMOEnd);
13452 // Check if there is enough room left to pull this argument.
13453 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
13455 .addImm(MaxOffset + 8 - ArgSizeA8);
13457 // Branch to "overflowMBB" if offset >= max
13458 // Fall through to "offsetMBB" otherwise
13459 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
13460 .addMBB(overflowMBB);
13463 // In offsetMBB, emit code to use the reg_save_area.
13465 assert(OffsetReg != 0);
13467 // Read the reg_save_area address.
13468 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
13469 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
13474 .addOperand(Segment)
13475 .setMemRefs(MMOBegin, MMOEnd);
13477 // Zero-extend the offset
13478 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
13479 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
13482 .addImm(X86::sub_32bit);
13484 // Add the offset to the reg_save_area to get the final address.
13485 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
13486 .addReg(OffsetReg64)
13487 .addReg(RegSaveReg);
13489 // Compute the offset for the next argument
13490 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13491 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
13493 .addImm(UseFPOffset ? 16 : 8);
13495 // Store it back into the va_list.
13496 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
13500 .addDisp(Disp, UseFPOffset ? 4 : 0)
13501 .addOperand(Segment)
13502 .addReg(NextOffsetReg)
13503 .setMemRefs(MMOBegin, MMOEnd);
13506 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
13511 // Emit code to use overflow area
13514 // Load the overflow_area address into a register.
13515 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
13516 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
13521 .addOperand(Segment)
13522 .setMemRefs(MMOBegin, MMOEnd);
13524 // If we need to align it, do so. Otherwise, just copy the address
13525 // to OverflowDestReg.
13527 // Align the overflow address
13528 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
13529 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
13531 // aligned_addr = (addr + (align-1)) & ~(align-1)
13532 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
13533 .addReg(OverflowAddrReg)
13536 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
13538 .addImm(~(uint64_t)(Align-1));
13540 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
13541 .addReg(OverflowAddrReg);
13544 // Compute the next overflow address after this argument.
13545 // (the overflow address should be kept 8-byte aligned)
13546 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
13547 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
13548 .addReg(OverflowDestReg)
13549 .addImm(ArgSizeA8);
13551 // Store the new overflow address.
13552 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
13557 .addOperand(Segment)
13558 .addReg(NextAddrReg)
13559 .setMemRefs(MMOBegin, MMOEnd);
13561 // If we branched, emit the PHI to the front of endMBB.
13563 BuildMI(*endMBB, endMBB->begin(), DL,
13564 TII->get(X86::PHI), DestReg)
13565 .addReg(OffsetDestReg).addMBB(offsetMBB)
13566 .addReg(OverflowDestReg).addMBB(overflowMBB);
13569 // Erase the pseudo instruction
13570 MI->eraseFromParent();
13575 MachineBasicBlock *
13576 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
13578 MachineBasicBlock *MBB) const {
13579 // Emit code to save XMM registers to the stack. The ABI says that the
13580 // number of registers to save is given in %al, so it's theoretically
13581 // possible to do an indirect jump trick to avoid saving all of them,
13582 // however this code takes a simpler approach and just executes all
13583 // of the stores if %al is non-zero. It's less code, and it's probably
13584 // easier on the hardware branch predictor, and stores aren't all that
13585 // expensive anyway.
13587 // Create the new basic blocks. One block contains all the XMM stores,
13588 // and one block is the final destination regardless of whether any
13589 // stores were performed.
13590 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13591 MachineFunction *F = MBB->getParent();
13592 MachineFunction::iterator MBBIter = MBB;
13594 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
13595 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
13596 F->insert(MBBIter, XMMSaveMBB);
13597 F->insert(MBBIter, EndMBB);
13599 // Transfer the remainder of MBB and its successor edges to EndMBB.
13600 EndMBB->splice(EndMBB->begin(), MBB,
13601 llvm::next(MachineBasicBlock::iterator(MI)),
13603 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
13605 // The original block will now fall through to the XMM save block.
13606 MBB->addSuccessor(XMMSaveMBB);
13607 // The XMMSaveMBB will fall through to the end block.
13608 XMMSaveMBB->addSuccessor(EndMBB);
13610 // Now add the instructions.
13611 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13612 DebugLoc DL = MI->getDebugLoc();
13614 unsigned CountReg = MI->getOperand(0).getReg();
13615 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
13616 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
13618 if (!Subtarget->isTargetWin64()) {
13619 // If %al is 0, branch around the XMM save block.
13620 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
13621 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
13622 MBB->addSuccessor(EndMBB);
13625 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
13626 // In the XMM save block, save all the XMM argument registers.
13627 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
13628 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
13629 MachineMemOperand *MMO =
13630 F->getMachineMemOperand(
13631 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
13632 MachineMemOperand::MOStore,
13633 /*Size=*/16, /*Align=*/16);
13634 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
13635 .addFrameIndex(RegSaveFrameIndex)
13636 .addImm(/*Scale=*/1)
13637 .addReg(/*IndexReg=*/0)
13638 .addImm(/*Disp=*/Offset)
13639 .addReg(/*Segment=*/0)
13640 .addReg(MI->getOperand(i).getReg())
13641 .addMemOperand(MMO);
13644 MI->eraseFromParent(); // The pseudo instruction is gone now.
13649 // The EFLAGS operand of SelectItr might be missing a kill marker
13650 // because there were multiple uses of EFLAGS, and ISel didn't know
13651 // which to mark. Figure out whether SelectItr should have had a
13652 // kill marker, and set it if it should. Returns the correct kill
13654 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
13655 MachineBasicBlock* BB,
13656 const TargetRegisterInfo* TRI) {
13657 // Scan forward through BB for a use/def of EFLAGS.
13658 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
13659 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
13660 const MachineInstr& mi = *miI;
13661 if (mi.readsRegister(X86::EFLAGS))
13663 if (mi.definesRegister(X86::EFLAGS))
13664 break; // Should have kill-flag - update below.
13667 // If we hit the end of the block, check whether EFLAGS is live into a
13669 if (miI == BB->end()) {
13670 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
13671 sEnd = BB->succ_end();
13672 sItr != sEnd; ++sItr) {
13673 MachineBasicBlock* succ = *sItr;
13674 if (succ->isLiveIn(X86::EFLAGS))
13679 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
13680 // out. SelectMI should have a kill flag on EFLAGS.
13681 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
13685 MachineBasicBlock *
13686 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
13687 MachineBasicBlock *BB) const {
13688 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13689 DebugLoc DL = MI->getDebugLoc();
13691 // To "insert" a SELECT_CC instruction, we actually have to insert the
13692 // diamond control-flow pattern. The incoming instruction knows the
13693 // destination vreg to set, the condition code register to branch on, the
13694 // true/false values to select between, and a branch opcode to use.
13695 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13696 MachineFunction::iterator It = BB;
13702 // cmpTY ccX, r1, r2
13704 // fallthrough --> copy0MBB
13705 MachineBasicBlock *thisMBB = BB;
13706 MachineFunction *F = BB->getParent();
13707 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
13708 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
13709 F->insert(It, copy0MBB);
13710 F->insert(It, sinkMBB);
13712 // If the EFLAGS register isn't dead in the terminator, then claim that it's
13713 // live into the sink and copy blocks.
13714 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13715 if (!MI->killsRegister(X86::EFLAGS) &&
13716 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
13717 copy0MBB->addLiveIn(X86::EFLAGS);
13718 sinkMBB->addLiveIn(X86::EFLAGS);
13721 // Transfer the remainder of BB and its successor edges to sinkMBB.
13722 sinkMBB->splice(sinkMBB->begin(), BB,
13723 llvm::next(MachineBasicBlock::iterator(MI)),
13725 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
13727 // Add the true and fallthrough blocks as its successors.
13728 BB->addSuccessor(copy0MBB);
13729 BB->addSuccessor(sinkMBB);
13731 // Create the conditional branch instruction.
13733 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
13734 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
13737 // %FalseValue = ...
13738 // # fallthrough to sinkMBB
13739 copy0MBB->addSuccessor(sinkMBB);
13742 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
13744 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13745 TII->get(X86::PHI), MI->getOperand(0).getReg())
13746 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
13747 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
13749 MI->eraseFromParent(); // The pseudo instruction is gone now.
13753 MachineBasicBlock *
13754 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
13755 bool Is64Bit) const {
13756 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13757 DebugLoc DL = MI->getDebugLoc();
13758 MachineFunction *MF = BB->getParent();
13759 const BasicBlock *LLVM_BB = BB->getBasicBlock();
13761 assert(getTargetMachine().Options.EnableSegmentedStacks);
13763 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
13764 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
13767 // ... [Till the alloca]
13768 // If stacklet is not large enough, jump to mallocMBB
13771 // Allocate by subtracting from RSP
13772 // Jump to continueMBB
13775 // Allocate by call to runtime
13779 // [rest of original BB]
13782 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13783 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13784 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13786 MachineRegisterInfo &MRI = MF->getRegInfo();
13787 const TargetRegisterClass *AddrRegClass =
13788 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
13790 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13791 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
13792 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
13793 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
13794 sizeVReg = MI->getOperand(1).getReg(),
13795 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
13797 MachineFunction::iterator MBBIter = BB;
13800 MF->insert(MBBIter, bumpMBB);
13801 MF->insert(MBBIter, mallocMBB);
13802 MF->insert(MBBIter, continueMBB);
13804 continueMBB->splice(continueMBB->begin(), BB, llvm::next
13805 (MachineBasicBlock::iterator(MI)), BB->end());
13806 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
13808 // Add code to the main basic block to check if the stack limit has been hit,
13809 // and if so, jump to mallocMBB otherwise to bumpMBB.
13810 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
13811 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
13812 .addReg(tmpSPVReg).addReg(sizeVReg);
13813 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
13814 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
13815 .addReg(SPLimitVReg);
13816 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
13818 // bumpMBB simply decreases the stack pointer, since we know the current
13819 // stacklet has enough space.
13820 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
13821 .addReg(SPLimitVReg);
13822 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
13823 .addReg(SPLimitVReg);
13824 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13826 // Calls into a routine in libgcc to allocate more space from the heap.
13827 const uint32_t *RegMask =
13828 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13830 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
13832 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
13833 .addExternalSymbol("__morestack_allocate_stack_space")
13834 .addRegMask(RegMask)
13835 .addReg(X86::RDI, RegState::Implicit)
13836 .addReg(X86::RAX, RegState::ImplicitDefine);
13838 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
13840 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
13841 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
13842 .addExternalSymbol("__morestack_allocate_stack_space")
13843 .addRegMask(RegMask)
13844 .addReg(X86::EAX, RegState::ImplicitDefine);
13848 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
13851 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
13852 .addReg(Is64Bit ? X86::RAX : X86::EAX);
13853 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
13855 // Set up the CFG correctly.
13856 BB->addSuccessor(bumpMBB);
13857 BB->addSuccessor(mallocMBB);
13858 mallocMBB->addSuccessor(continueMBB);
13859 bumpMBB->addSuccessor(continueMBB);
13861 // Take care of the PHI nodes.
13862 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
13863 MI->getOperand(0).getReg())
13864 .addReg(mallocPtrVReg).addMBB(mallocMBB)
13865 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
13867 // Delete the original pseudo instruction.
13868 MI->eraseFromParent();
13871 return continueMBB;
13874 MachineBasicBlock *
13875 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
13876 MachineBasicBlock *BB) const {
13877 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13878 DebugLoc DL = MI->getDebugLoc();
13880 assert(!Subtarget->isTargetEnvMacho());
13882 // The lowering is pretty easy: we're just emitting the call to _alloca. The
13883 // non-trivial part is impdef of ESP.
13885 if (Subtarget->isTargetWin64()) {
13886 if (Subtarget->isTargetCygMing()) {
13887 // ___chkstk(Mingw64):
13888 // Clobbers R10, R11, RAX and EFLAGS.
13890 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
13891 .addExternalSymbol("___chkstk")
13892 .addReg(X86::RAX, RegState::Implicit)
13893 .addReg(X86::RSP, RegState::Implicit)
13894 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
13895 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
13896 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13898 // __chkstk(MSVCRT): does not update stack pointer.
13899 // Clobbers R10, R11 and EFLAGS.
13900 // FIXME: RAX(allocated size) might be reused and not killed.
13901 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
13902 .addExternalSymbol("__chkstk")
13903 .addReg(X86::RAX, RegState::Implicit)
13904 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13905 // RAX has the offset to subtracted from RSP.
13906 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
13911 const char *StackProbeSymbol =
13912 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
13914 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
13915 .addExternalSymbol(StackProbeSymbol)
13916 .addReg(X86::EAX, RegState::Implicit)
13917 .addReg(X86::ESP, RegState::Implicit)
13918 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
13919 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
13920 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
13923 MI->eraseFromParent(); // The pseudo instruction is gone now.
13927 MachineBasicBlock *
13928 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
13929 MachineBasicBlock *BB) const {
13930 // This is pretty easy. We're taking the value that we received from
13931 // our load from the relocation, sticking it in either RDI (x86-64)
13932 // or EAX and doing an indirect call. The return value will then
13933 // be in the normal return register.
13934 const X86InstrInfo *TII
13935 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
13936 DebugLoc DL = MI->getDebugLoc();
13937 MachineFunction *F = BB->getParent();
13939 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
13940 assert(MI->getOperand(3).isGlobal() && "This should be a global");
13942 // Get a register mask for the lowered call.
13943 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
13944 // proper register mask.
13945 const uint32_t *RegMask =
13946 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
13947 if (Subtarget->is64Bit()) {
13948 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13949 TII->get(X86::MOV64rm), X86::RDI)
13951 .addImm(0).addReg(0)
13952 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13953 MI->getOperand(3).getTargetFlags())
13955 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
13956 addDirectMem(MIB, X86::RDI);
13957 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
13958 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
13959 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13960 TII->get(X86::MOV32rm), X86::EAX)
13962 .addImm(0).addReg(0)
13963 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13964 MI->getOperand(3).getTargetFlags())
13966 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
13967 addDirectMem(MIB, X86::EAX);
13968 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
13970 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
13971 TII->get(X86::MOV32rm), X86::EAX)
13972 .addReg(TII->getGlobalBaseReg(F))
13973 .addImm(0).addReg(0)
13974 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
13975 MI->getOperand(3).getTargetFlags())
13977 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
13978 addDirectMem(MIB, X86::EAX);
13979 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
13982 MI->eraseFromParent(); // The pseudo instruction is gone now.
13986 MachineBasicBlock *
13987 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
13988 MachineBasicBlock *MBB) const {
13989 DebugLoc DL = MI->getDebugLoc();
13990 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13992 MachineFunction *MF = MBB->getParent();
13993 MachineRegisterInfo &MRI = MF->getRegInfo();
13995 const BasicBlock *BB = MBB->getBasicBlock();
13996 MachineFunction::iterator I = MBB;
13999 // Memory Reference
14000 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14001 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14004 unsigned MemOpndSlot = 0;
14006 unsigned CurOp = 0;
14008 DstReg = MI->getOperand(CurOp++).getReg();
14009 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14010 assert(RC->hasType(MVT::i32) && "Invalid destination!");
14011 unsigned mainDstReg = MRI.createVirtualRegister(RC);
14012 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
14014 MemOpndSlot = CurOp;
14016 MVT PVT = getPointerTy();
14017 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14018 "Invalid Pointer Size!");
14020 // For v = setjmp(buf), we generate
14023 // buf[LabelOffset] = restoreMBB
14024 // SjLjSetup restoreMBB
14030 // v = phi(main, restore)
14035 MachineBasicBlock *thisMBB = MBB;
14036 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14037 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14038 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
14039 MF->insert(I, mainMBB);
14040 MF->insert(I, sinkMBB);
14041 MF->push_back(restoreMBB);
14043 MachineInstrBuilder MIB;
14045 // Transfer the remainder of BB and its successor edges to sinkMBB.
14046 sinkMBB->splice(sinkMBB->begin(), MBB,
14047 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14048 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14051 unsigned PtrStoreOpc = 0;
14052 unsigned LabelReg = 0;
14053 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14054 Reloc::Model RM = getTargetMachine().getRelocationModel();
14055 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
14056 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
14058 // Prepare IP either in reg or imm.
14059 if (!UseImmLabel) {
14060 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
14061 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
14062 LabelReg = MRI.createVirtualRegister(PtrRC);
14063 if (Subtarget->is64Bit()) {
14064 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
14068 .addMBB(restoreMBB)
14071 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
14072 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
14073 .addReg(XII->getGlobalBaseReg(MF))
14076 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
14080 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
14082 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
14083 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14084 if (i == X86::AddrDisp)
14085 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
14087 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
14090 MIB.addReg(LabelReg);
14092 MIB.addMBB(restoreMBB);
14093 MIB.setMemRefs(MMOBegin, MMOEnd);
14095 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
14096 .addMBB(restoreMBB);
14097 MIB.addRegMask(RegInfo->getNoPreservedMask());
14098 thisMBB->addSuccessor(mainMBB);
14099 thisMBB->addSuccessor(restoreMBB);
14103 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
14104 mainMBB->addSuccessor(sinkMBB);
14107 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14108 TII->get(X86::PHI), DstReg)
14109 .addReg(mainDstReg).addMBB(mainMBB)
14110 .addReg(restoreDstReg).addMBB(restoreMBB);
14113 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
14114 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
14115 restoreMBB->addSuccessor(sinkMBB);
14117 MI->eraseFromParent();
14121 MachineBasicBlock *
14122 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
14123 MachineBasicBlock *MBB) const {
14124 DebugLoc DL = MI->getDebugLoc();
14125 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14127 MachineFunction *MF = MBB->getParent();
14128 MachineRegisterInfo &MRI = MF->getRegInfo();
14130 // Memory Reference
14131 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14132 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14134 MVT PVT = getPointerTy();
14135 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14136 "Invalid Pointer Size!");
14138 const TargetRegisterClass *RC =
14139 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
14140 unsigned Tmp = MRI.createVirtualRegister(RC);
14141 // Since FP is only updated here but NOT referenced, it's treated as GPR.
14142 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
14143 unsigned SP = RegInfo->getStackRegister();
14145 MachineInstrBuilder MIB;
14147 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14148 const int64_t SPOffset = 2 * PVT.getStoreSize();
14150 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
14151 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
14154 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
14155 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
14156 MIB.addOperand(MI->getOperand(i));
14157 MIB.setMemRefs(MMOBegin, MMOEnd);
14159 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
14160 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14161 if (i == X86::AddrDisp)
14162 MIB.addDisp(MI->getOperand(i), LabelOffset);
14164 MIB.addOperand(MI->getOperand(i));
14166 MIB.setMemRefs(MMOBegin, MMOEnd);
14168 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
14169 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14170 if (i == X86::AddrDisp)
14171 MIB.addDisp(MI->getOperand(i), SPOffset);
14173 MIB.addOperand(MI->getOperand(i));
14175 MIB.setMemRefs(MMOBegin, MMOEnd);
14177 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
14179 MI->eraseFromParent();
14183 MachineBasicBlock *
14184 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
14185 MachineBasicBlock *BB) const {
14186 switch (MI->getOpcode()) {
14187 default: llvm_unreachable("Unexpected instr type to insert");
14188 case X86::TAILJMPd64:
14189 case X86::TAILJMPr64:
14190 case X86::TAILJMPm64:
14191 llvm_unreachable("TAILJMP64 would not be touched here.");
14192 case X86::TCRETURNdi64:
14193 case X86::TCRETURNri64:
14194 case X86::TCRETURNmi64:
14196 case X86::WIN_ALLOCA:
14197 return EmitLoweredWinAlloca(MI, BB);
14198 case X86::SEG_ALLOCA_32:
14199 return EmitLoweredSegAlloca(MI, BB, false);
14200 case X86::SEG_ALLOCA_64:
14201 return EmitLoweredSegAlloca(MI, BB, true);
14202 case X86::TLSCall_32:
14203 case X86::TLSCall_64:
14204 return EmitLoweredTLSCall(MI, BB);
14205 case X86::CMOV_GR8:
14206 case X86::CMOV_FR32:
14207 case X86::CMOV_FR64:
14208 case X86::CMOV_V4F32:
14209 case X86::CMOV_V2F64:
14210 case X86::CMOV_V2I64:
14211 case X86::CMOV_V8F32:
14212 case X86::CMOV_V4F64:
14213 case X86::CMOV_V4I64:
14214 case X86::CMOV_GR16:
14215 case X86::CMOV_GR32:
14216 case X86::CMOV_RFP32:
14217 case X86::CMOV_RFP64:
14218 case X86::CMOV_RFP80:
14219 return EmitLoweredSelect(MI, BB);
14221 case X86::FP32_TO_INT16_IN_MEM:
14222 case X86::FP32_TO_INT32_IN_MEM:
14223 case X86::FP32_TO_INT64_IN_MEM:
14224 case X86::FP64_TO_INT16_IN_MEM:
14225 case X86::FP64_TO_INT32_IN_MEM:
14226 case X86::FP64_TO_INT64_IN_MEM:
14227 case X86::FP80_TO_INT16_IN_MEM:
14228 case X86::FP80_TO_INT32_IN_MEM:
14229 case X86::FP80_TO_INT64_IN_MEM: {
14230 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14231 DebugLoc DL = MI->getDebugLoc();
14233 // Change the floating point control register to use "round towards zero"
14234 // mode when truncating to an integer value.
14235 MachineFunction *F = BB->getParent();
14236 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
14237 addFrameReference(BuildMI(*BB, MI, DL,
14238 TII->get(X86::FNSTCW16m)), CWFrameIdx);
14240 // Load the old value of the high byte of the control word...
14242 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
14243 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
14246 // Set the high part to be round to zero...
14247 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
14250 // Reload the modified control word now...
14251 addFrameReference(BuildMI(*BB, MI, DL,
14252 TII->get(X86::FLDCW16m)), CWFrameIdx);
14254 // Restore the memory image of control word to original value
14255 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
14258 // Get the X86 opcode to use.
14260 switch (MI->getOpcode()) {
14261 default: llvm_unreachable("illegal opcode!");
14262 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
14263 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
14264 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
14265 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
14266 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
14267 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
14268 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
14269 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
14270 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
14274 MachineOperand &Op = MI->getOperand(0);
14276 AM.BaseType = X86AddressMode::RegBase;
14277 AM.Base.Reg = Op.getReg();
14279 AM.BaseType = X86AddressMode::FrameIndexBase;
14280 AM.Base.FrameIndex = Op.getIndex();
14282 Op = MI->getOperand(1);
14284 AM.Scale = Op.getImm();
14285 Op = MI->getOperand(2);
14287 AM.IndexReg = Op.getImm();
14288 Op = MI->getOperand(3);
14289 if (Op.isGlobal()) {
14290 AM.GV = Op.getGlobal();
14292 AM.Disp = Op.getImm();
14294 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
14295 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
14297 // Reload the original control word now.
14298 addFrameReference(BuildMI(*BB, MI, DL,
14299 TII->get(X86::FLDCW16m)), CWFrameIdx);
14301 MI->eraseFromParent(); // The pseudo instruction is gone now.
14304 // String/text processing lowering.
14305 case X86::PCMPISTRM128REG:
14306 case X86::VPCMPISTRM128REG:
14307 case X86::PCMPISTRM128MEM:
14308 case X86::VPCMPISTRM128MEM:
14309 case X86::PCMPESTRM128REG:
14310 case X86::VPCMPESTRM128REG:
14311 case X86::PCMPESTRM128MEM:
14312 case X86::VPCMPESTRM128MEM:
14313 assert(Subtarget->hasSSE42() &&
14314 "Target must have SSE4.2 or AVX features enabled");
14315 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
14317 // String/text processing lowering.
14318 case X86::PCMPISTRIREG:
14319 case X86::VPCMPISTRIREG:
14320 case X86::PCMPISTRIMEM:
14321 case X86::VPCMPISTRIMEM:
14322 case X86::PCMPESTRIREG:
14323 case X86::VPCMPESTRIREG:
14324 case X86::PCMPESTRIMEM:
14325 case X86::VPCMPESTRIMEM:
14326 assert(Subtarget->hasSSE42() &&
14327 "Target must have SSE4.2 or AVX features enabled");
14328 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
14330 // Thread synchronization.
14332 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
14336 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
14338 // Atomic Lowering.
14339 case X86::ATOMAND8:
14340 case X86::ATOMAND16:
14341 case X86::ATOMAND32:
14342 case X86::ATOMAND64:
14345 case X86::ATOMOR16:
14346 case X86::ATOMOR32:
14347 case X86::ATOMOR64:
14349 case X86::ATOMXOR16:
14350 case X86::ATOMXOR8:
14351 case X86::ATOMXOR32:
14352 case X86::ATOMXOR64:
14354 case X86::ATOMNAND8:
14355 case X86::ATOMNAND16:
14356 case X86::ATOMNAND32:
14357 case X86::ATOMNAND64:
14359 case X86::ATOMMAX8:
14360 case X86::ATOMMAX16:
14361 case X86::ATOMMAX32:
14362 case X86::ATOMMAX64:
14364 case X86::ATOMMIN8:
14365 case X86::ATOMMIN16:
14366 case X86::ATOMMIN32:
14367 case X86::ATOMMIN64:
14369 case X86::ATOMUMAX8:
14370 case X86::ATOMUMAX16:
14371 case X86::ATOMUMAX32:
14372 case X86::ATOMUMAX64:
14374 case X86::ATOMUMIN8:
14375 case X86::ATOMUMIN16:
14376 case X86::ATOMUMIN32:
14377 case X86::ATOMUMIN64:
14378 return EmitAtomicLoadArith(MI, BB);
14380 // This group does 64-bit operations on a 32-bit host.
14381 case X86::ATOMAND6432:
14382 case X86::ATOMOR6432:
14383 case X86::ATOMXOR6432:
14384 case X86::ATOMNAND6432:
14385 case X86::ATOMADD6432:
14386 case X86::ATOMSUB6432:
14387 case X86::ATOMMAX6432:
14388 case X86::ATOMMIN6432:
14389 case X86::ATOMUMAX6432:
14390 case X86::ATOMUMIN6432:
14391 case X86::ATOMSWAP6432:
14392 return EmitAtomicLoadArith6432(MI, BB);
14394 case X86::VASTART_SAVE_XMM_REGS:
14395 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
14397 case X86::VAARG_64:
14398 return EmitVAARG64WithCustomInserter(MI, BB);
14400 case X86::EH_SjLj_SetJmp32:
14401 case X86::EH_SjLj_SetJmp64:
14402 return emitEHSjLjSetJmp(MI, BB);
14404 case X86::EH_SjLj_LongJmp32:
14405 case X86::EH_SjLj_LongJmp64:
14406 return emitEHSjLjLongJmp(MI, BB);
14410 //===----------------------------------------------------------------------===//
14411 // X86 Optimization Hooks
14412 //===----------------------------------------------------------------------===//
14414 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
14417 const SelectionDAG &DAG,
14418 unsigned Depth) const {
14419 unsigned BitWidth = KnownZero.getBitWidth();
14420 unsigned Opc = Op.getOpcode();
14421 assert((Opc >= ISD::BUILTIN_OP_END ||
14422 Opc == ISD::INTRINSIC_WO_CHAIN ||
14423 Opc == ISD::INTRINSIC_W_CHAIN ||
14424 Opc == ISD::INTRINSIC_VOID) &&
14425 "Should use MaskedValueIsZero if you don't know whether Op"
14426 " is a target node!");
14428 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
14442 // These nodes' second result is a boolean.
14443 if (Op.getResNo() == 0)
14446 case X86ISD::SETCC:
14447 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
14449 case ISD::INTRINSIC_WO_CHAIN: {
14450 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14451 unsigned NumLoBits = 0;
14454 case Intrinsic::x86_sse_movmsk_ps:
14455 case Intrinsic::x86_avx_movmsk_ps_256:
14456 case Intrinsic::x86_sse2_movmsk_pd:
14457 case Intrinsic::x86_avx_movmsk_pd_256:
14458 case Intrinsic::x86_mmx_pmovmskb:
14459 case Intrinsic::x86_sse2_pmovmskb_128:
14460 case Intrinsic::x86_avx2_pmovmskb: {
14461 // High bits of movmskp{s|d}, pmovmskb are known zero.
14463 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14464 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
14465 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
14466 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
14467 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
14468 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
14469 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
14470 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
14472 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
14481 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
14482 unsigned Depth) const {
14483 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
14484 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
14485 return Op.getValueType().getScalarType().getSizeInBits();
14491 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
14492 /// node is a GlobalAddress + offset.
14493 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
14494 const GlobalValue* &GA,
14495 int64_t &Offset) const {
14496 if (N->getOpcode() == X86ISD::Wrapper) {
14497 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
14498 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
14499 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
14503 return TargetLowering::isGAPlusOffset(N, GA, Offset);
14506 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
14507 /// same as extracting the high 128-bit part of 256-bit vector and then
14508 /// inserting the result into the low part of a new 256-bit vector
14509 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
14510 EVT VT = SVOp->getValueType(0);
14511 unsigned NumElems = VT.getVectorNumElements();
14513 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14514 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
14515 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14516 SVOp->getMaskElt(j) >= 0)
14522 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
14523 /// same as extracting the low 128-bit part of 256-bit vector and then
14524 /// inserting the result into the high part of a new 256-bit vector
14525 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
14526 EVT VT = SVOp->getValueType(0);
14527 unsigned NumElems = VT.getVectorNumElements();
14529 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14530 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
14531 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
14532 SVOp->getMaskElt(j) >= 0)
14538 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
14539 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
14540 TargetLowering::DAGCombinerInfo &DCI,
14541 const X86Subtarget* Subtarget) {
14542 DebugLoc dl = N->getDebugLoc();
14543 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
14544 SDValue V1 = SVOp->getOperand(0);
14545 SDValue V2 = SVOp->getOperand(1);
14546 EVT VT = SVOp->getValueType(0);
14547 unsigned NumElems = VT.getVectorNumElements();
14549 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
14550 V2.getOpcode() == ISD::CONCAT_VECTORS) {
14554 // V UNDEF BUILD_VECTOR UNDEF
14556 // CONCAT_VECTOR CONCAT_VECTOR
14559 // RESULT: V + zero extended
14561 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
14562 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
14563 V1.getOperand(1).getOpcode() != ISD::UNDEF)
14566 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
14569 // To match the shuffle mask, the first half of the mask should
14570 // be exactly the first vector, and all the rest a splat with the
14571 // first element of the second one.
14572 for (unsigned i = 0; i != NumElems/2; ++i)
14573 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
14574 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
14577 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
14578 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
14579 if (Ld->hasNUsesOfValue(1, 0)) {
14580 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
14581 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
14583 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2,
14585 Ld->getPointerInfo(),
14586 Ld->getAlignment(),
14587 false/*isVolatile*/, true/*ReadMem*/,
14588 false/*WriteMem*/);
14590 // Make sure the newly-created LOAD is in the same position as Ld in
14591 // terms of dependency. We create a TokenFactor for Ld and ResNode,
14592 // and update uses of Ld's output chain to use the TokenFactor.
14593 if (Ld->hasAnyUseOfValue(1)) {
14594 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
14595 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
14596 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
14597 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
14598 SDValue(ResNode.getNode(), 1));
14601 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
14605 // Emit a zeroed vector and insert the desired subvector on its
14607 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
14608 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
14609 return DCI.CombineTo(N, InsV);
14612 //===--------------------------------------------------------------------===//
14613 // Combine some shuffles into subvector extracts and inserts:
14616 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
14617 if (isShuffleHigh128VectorInsertLow(SVOp)) {
14618 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
14619 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
14620 return DCI.CombineTo(N, InsV);
14623 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
14624 if (isShuffleLow128VectorInsertHigh(SVOp)) {
14625 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
14626 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
14627 return DCI.CombineTo(N, InsV);
14633 /// PerformShuffleCombine - Performs several different shuffle combines.
14634 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
14635 TargetLowering::DAGCombinerInfo &DCI,
14636 const X86Subtarget *Subtarget) {
14637 DebugLoc dl = N->getDebugLoc();
14638 EVT VT = N->getValueType(0);
14640 // Don't create instructions with illegal types after legalize types has run.
14641 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14642 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
14645 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
14646 if (Subtarget->hasFp256() && VT.is256BitVector() &&
14647 N->getOpcode() == ISD::VECTOR_SHUFFLE)
14648 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
14650 // Only handle 128 wide vector from here on.
14651 if (!VT.is128BitVector())
14654 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
14655 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
14656 // consecutive, non-overlapping, and in the right order.
14657 SmallVector<SDValue, 16> Elts;
14658 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
14659 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
14661 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
14664 /// PerformTruncateCombine - Converts truncate operation to
14665 /// a sequence of vector shuffle operations.
14666 /// It is possible when we truncate 256-bit vector to 128-bit vector
14667 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
14668 TargetLowering::DAGCombinerInfo &DCI,
14669 const X86Subtarget *Subtarget) {
14673 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
14674 /// specific shuffle of a load can be folded into a single element load.
14675 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
14676 /// shuffles have been customed lowered so we need to handle those here.
14677 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
14678 TargetLowering::DAGCombinerInfo &DCI) {
14679 if (DCI.isBeforeLegalizeOps())
14682 SDValue InVec = N->getOperand(0);
14683 SDValue EltNo = N->getOperand(1);
14685 if (!isa<ConstantSDNode>(EltNo))
14688 EVT VT = InVec.getValueType();
14690 bool HasShuffleIntoBitcast = false;
14691 if (InVec.getOpcode() == ISD::BITCAST) {
14692 // Don't duplicate a load with other uses.
14693 if (!InVec.hasOneUse())
14695 EVT BCVT = InVec.getOperand(0).getValueType();
14696 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
14698 InVec = InVec.getOperand(0);
14699 HasShuffleIntoBitcast = true;
14702 if (!isTargetShuffle(InVec.getOpcode()))
14705 // Don't duplicate a load with other uses.
14706 if (!InVec.hasOneUse())
14709 SmallVector<int, 16> ShuffleMask;
14711 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
14715 // Select the input vector, guarding against out of range extract vector.
14716 unsigned NumElems = VT.getVectorNumElements();
14717 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
14718 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
14719 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
14720 : InVec.getOperand(1);
14722 // If inputs to shuffle are the same for both ops, then allow 2 uses
14723 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
14725 if (LdNode.getOpcode() == ISD::BITCAST) {
14726 // Don't duplicate a load with other uses.
14727 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
14730 AllowedUses = 1; // only allow 1 load use if we have a bitcast
14731 LdNode = LdNode.getOperand(0);
14734 if (!ISD::isNormalLoad(LdNode.getNode()))
14737 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
14739 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
14742 if (HasShuffleIntoBitcast) {
14743 // If there's a bitcast before the shuffle, check if the load type and
14744 // alignment is valid.
14745 unsigned Align = LN0->getAlignment();
14746 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14747 unsigned NewAlign = TLI.getDataLayout()->
14748 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
14750 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
14754 // All checks match so transform back to vector_shuffle so that DAG combiner
14755 // can finish the job
14756 DebugLoc dl = N->getDebugLoc();
14758 // Create shuffle node taking into account the case that its a unary shuffle
14759 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
14760 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
14761 InVec.getOperand(0), Shuffle,
14763 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
14764 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
14768 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
14769 /// generation and convert it from being a bunch of shuffles and extracts
14770 /// to a simple store and scalar loads to extract the elements.
14771 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
14772 TargetLowering::DAGCombinerInfo &DCI) {
14773 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
14774 if (NewOp.getNode())
14777 SDValue InputVector = N->getOperand(0);
14778 // Detect whether we are trying to convert from mmx to i32 and the bitcast
14779 // from mmx to v2i32 has a single usage.
14780 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
14781 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
14782 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
14783 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(),
14784 N->getValueType(0),
14785 InputVector.getNode()->getOperand(0));
14787 // Only operate on vectors of 4 elements, where the alternative shuffling
14788 // gets to be more expensive.
14789 if (InputVector.getValueType() != MVT::v4i32)
14792 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
14793 // single use which is a sign-extend or zero-extend, and all elements are
14795 SmallVector<SDNode *, 4> Uses;
14796 unsigned ExtractedElements = 0;
14797 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
14798 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
14799 if (UI.getUse().getResNo() != InputVector.getResNo())
14802 SDNode *Extract = *UI;
14803 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
14806 if (Extract->getValueType(0) != MVT::i32)
14808 if (!Extract->hasOneUse())
14810 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
14811 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
14813 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
14816 // Record which element was extracted.
14817 ExtractedElements |=
14818 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
14820 Uses.push_back(Extract);
14823 // If not all the elements were used, this may not be worthwhile.
14824 if (ExtractedElements != 15)
14827 // Ok, we've now decided to do the transformation.
14828 DebugLoc dl = InputVector.getDebugLoc();
14830 // Store the value to a temporary stack slot.
14831 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
14832 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
14833 MachinePointerInfo(), false, false, 0);
14835 // Replace each use (extract) with a load of the appropriate element.
14836 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
14837 UE = Uses.end(); UI != UE; ++UI) {
14838 SDNode *Extract = *UI;
14840 // cOMpute the element's address.
14841 SDValue Idx = Extract->getOperand(1);
14843 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
14844 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
14845 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14846 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
14848 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
14849 StackPtr, OffsetVal);
14851 // Load the scalar.
14852 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
14853 ScalarAddr, MachinePointerInfo(),
14854 false, false, false, 0);
14856 // Replace the exact with the load.
14857 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
14860 // The replacement was made in place; don't return anything.
14864 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
14865 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
14866 SDValue RHS, SelectionDAG &DAG,
14867 const X86Subtarget *Subtarget) {
14868 if (!VT.isVector())
14871 switch (VT.getSimpleVT().SimpleTy) {
14876 if (!Subtarget->hasAVX2())
14881 if (!Subtarget->hasSSE2())
14885 // SSE2 has only a small subset of the operations.
14886 bool hasUnsigned = Subtarget->hasSSE41() ||
14887 (Subtarget->hasSSE2() && VT == MVT::v16i8);
14888 bool hasSigned = Subtarget->hasSSE41() ||
14889 (Subtarget->hasSSE2() && VT == MVT::v8i16);
14891 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14893 // Check for x CC y ? x : y.
14894 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
14895 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
14900 return hasUnsigned ? X86ISD::UMIN : 0;
14903 return hasUnsigned ? X86ISD::UMAX : 0;
14906 return hasSigned ? X86ISD::SMIN : 0;
14909 return hasSigned ? X86ISD::SMAX : 0;
14911 // Check for x CC y ? y : x -- a min/max with reversed arms.
14912 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
14913 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
14918 return hasUnsigned ? X86ISD::UMAX : 0;
14921 return hasUnsigned ? X86ISD::UMIN : 0;
14924 return hasSigned ? X86ISD::SMAX : 0;
14927 return hasSigned ? X86ISD::SMIN : 0;
14934 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
14936 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
14937 TargetLowering::DAGCombinerInfo &DCI,
14938 const X86Subtarget *Subtarget) {
14939 DebugLoc DL = N->getDebugLoc();
14940 SDValue Cond = N->getOperand(0);
14941 // Get the LHS/RHS of the select.
14942 SDValue LHS = N->getOperand(1);
14943 SDValue RHS = N->getOperand(2);
14944 EVT VT = LHS.getValueType();
14946 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
14947 // instructions match the semantics of the common C idiom x<y?x:y but not
14948 // x<=y?x:y, because of how they handle negative zero (which can be
14949 // ignored in unsafe-math mode).
14950 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
14951 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
14952 (Subtarget->hasSSE2() ||
14953 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
14954 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
14956 unsigned Opcode = 0;
14957 // Check for x CC y ? x : y.
14958 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
14959 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
14963 // Converting this to a min would handle NaNs incorrectly, and swapping
14964 // the operands would cause it to handle comparisons between positive
14965 // and negative zero incorrectly.
14966 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
14967 if (!DAG.getTarget().Options.UnsafeFPMath &&
14968 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
14970 std::swap(LHS, RHS);
14972 Opcode = X86ISD::FMIN;
14975 // Converting this to a min would handle comparisons between positive
14976 // and negative zero incorrectly.
14977 if (!DAG.getTarget().Options.UnsafeFPMath &&
14978 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
14980 Opcode = X86ISD::FMIN;
14983 // Converting this to a min would handle both negative zeros and NaNs
14984 // incorrectly, but we can swap the operands to fix both.
14985 std::swap(LHS, RHS);
14989 Opcode = X86ISD::FMIN;
14993 // Converting this to a max would handle comparisons between positive
14994 // and negative zero incorrectly.
14995 if (!DAG.getTarget().Options.UnsafeFPMath &&
14996 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
14998 Opcode = X86ISD::FMAX;
15001 // Converting this to a max would handle NaNs incorrectly, and swapping
15002 // the operands would cause it to handle comparisons between positive
15003 // and negative zero incorrectly.
15004 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15005 if (!DAG.getTarget().Options.UnsafeFPMath &&
15006 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15008 std::swap(LHS, RHS);
15010 Opcode = X86ISD::FMAX;
15013 // Converting this to a max would handle both negative zeros and NaNs
15014 // incorrectly, but we can swap the operands to fix both.
15015 std::swap(LHS, RHS);
15019 Opcode = X86ISD::FMAX;
15022 // Check for x CC y ? y : x -- a min/max with reversed arms.
15023 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15024 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15028 // Converting this to a min would handle comparisons between positive
15029 // and negative zero incorrectly, and swapping the operands would
15030 // cause it to handle NaNs incorrectly.
15031 if (!DAG.getTarget().Options.UnsafeFPMath &&
15032 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
15033 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15035 std::swap(LHS, RHS);
15037 Opcode = X86ISD::FMIN;
15040 // Converting this to a min would handle NaNs incorrectly.
15041 if (!DAG.getTarget().Options.UnsafeFPMath &&
15042 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
15044 Opcode = X86ISD::FMIN;
15047 // Converting this to a min would handle both negative zeros and NaNs
15048 // incorrectly, but we can swap the operands to fix both.
15049 std::swap(LHS, RHS);
15053 Opcode = X86ISD::FMIN;
15057 // Converting this to a max would handle NaNs incorrectly.
15058 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15060 Opcode = X86ISD::FMAX;
15063 // Converting this to a max would handle comparisons between positive
15064 // and negative zero incorrectly, and swapping the operands would
15065 // cause it to handle NaNs incorrectly.
15066 if (!DAG.getTarget().Options.UnsafeFPMath &&
15067 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
15068 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15070 std::swap(LHS, RHS);
15072 Opcode = X86ISD::FMAX;
15075 // Converting this to a max would handle both negative zeros and NaNs
15076 // incorrectly, but we can swap the operands to fix both.
15077 std::swap(LHS, RHS);
15081 Opcode = X86ISD::FMAX;
15087 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
15090 // If this is a select between two integer constants, try to do some
15092 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
15093 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
15094 // Don't do this for crazy integer types.
15095 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
15096 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
15097 // so that TrueC (the true value) is larger than FalseC.
15098 bool NeedsCondInvert = false;
15100 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
15101 // Efficiently invertible.
15102 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
15103 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
15104 isa<ConstantSDNode>(Cond.getOperand(1))))) {
15105 NeedsCondInvert = true;
15106 std::swap(TrueC, FalseC);
15109 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
15110 if (FalseC->getAPIntValue() == 0 &&
15111 TrueC->getAPIntValue().isPowerOf2()) {
15112 if (NeedsCondInvert) // Invert the condition if needed.
15113 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15114 DAG.getConstant(1, Cond.getValueType()));
15116 // Zero extend the condition if needed.
15117 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
15119 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15120 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
15121 DAG.getConstant(ShAmt, MVT::i8));
15124 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
15125 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15126 if (NeedsCondInvert) // Invert the condition if needed.
15127 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15128 DAG.getConstant(1, Cond.getValueType()));
15130 // Zero extend the condition if needed.
15131 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15132 FalseC->getValueType(0), Cond);
15133 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15134 SDValue(FalseC, 0));
15137 // Optimize cases that will turn into an LEA instruction. This requires
15138 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15139 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15140 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15141 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15143 bool isFastMultiplier = false;
15145 switch ((unsigned char)Diff) {
15147 case 1: // result = add base, cond
15148 case 2: // result = lea base( , cond*2)
15149 case 3: // result = lea base(cond, cond*2)
15150 case 4: // result = lea base( , cond*4)
15151 case 5: // result = lea base(cond, cond*4)
15152 case 8: // result = lea base( , cond*8)
15153 case 9: // result = lea base(cond, cond*8)
15154 isFastMultiplier = true;
15159 if (isFastMultiplier) {
15160 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15161 if (NeedsCondInvert) // Invert the condition if needed.
15162 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15163 DAG.getConstant(1, Cond.getValueType()));
15165 // Zero extend the condition if needed.
15166 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15168 // Scale the condition by the difference.
15170 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15171 DAG.getConstant(Diff, Cond.getValueType()));
15173 // Add the base if non-zero.
15174 if (FalseC->getAPIntValue() != 0)
15175 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15176 SDValue(FalseC, 0));
15183 // Canonicalize max and min:
15184 // (x > y) ? x : y -> (x >= y) ? x : y
15185 // (x < y) ? x : y -> (x <= y) ? x : y
15186 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
15187 // the need for an extra compare
15188 // against zero. e.g.
15189 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
15191 // testl %edi, %edi
15193 // cmovgl %edi, %eax
15197 // cmovsl %eax, %edi
15198 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
15199 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15200 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15201 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15206 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
15207 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
15208 Cond.getOperand(0), Cond.getOperand(1), NewCC);
15209 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
15214 // Match VSELECTs into subs with unsigned saturation.
15215 if (!DCI.isBeforeLegalize() &&
15216 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
15217 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
15218 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
15219 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
15220 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15222 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
15223 // left side invert the predicate to simplify logic below.
15225 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
15227 CC = ISD::getSetCCInverse(CC, true);
15228 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
15232 if (Other.getNode() && Other->getNumOperands() == 2 &&
15233 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
15234 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
15235 SDValue CondRHS = Cond->getOperand(1);
15237 // Look for a general sub with unsigned saturation first.
15238 // x >= y ? x-y : 0 --> subus x, y
15239 // x > y ? x-y : 0 --> subus x, y
15240 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
15241 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
15242 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15244 // If the RHS is a constant we have to reverse the const canonicalization.
15245 // x > C-1 ? x+-C : 0 --> subus x, C
15246 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
15247 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
15248 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15249 if (CondRHS.getConstantOperandVal(0) == -A-1) {
15250 SmallVector<SDValue, 32> V(VT.getVectorNumElements(),
15251 DAG.getConstant(-A, VT.getScalarType()));
15252 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
15253 DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
15254 V.data(), V.size()));
15258 // Another special case: If C was a sign bit, the sub has been
15259 // canonicalized into a xor.
15260 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
15261 // it's safe to decanonicalize the xor?
15262 // x s< 0 ? x^C : 0 --> subus x, C
15263 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
15264 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
15265 isSplatVector(OpRHS.getNode())) {
15266 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15268 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15273 // Try to match a min/max vector operation.
15274 if (!DCI.isBeforeLegalize() &&
15275 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
15276 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
15277 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
15279 // If we know that this node is legal then we know that it is going to be
15280 // matched by one of the SSE/AVX BLEND instructions. These instructions only
15281 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
15282 // to simplify previous instructions.
15283 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15284 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
15285 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
15286 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
15288 // Don't optimize vector selects that map to mask-registers.
15292 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
15293 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
15295 APInt KnownZero, KnownOne;
15296 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
15297 DCI.isBeforeLegalizeOps());
15298 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
15299 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
15300 DCI.CommitTargetLoweringOpt(TLO);
15306 // Check whether a boolean test is testing a boolean value generated by
15307 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
15310 // Simplify the following patterns:
15311 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
15312 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
15313 // to (Op EFLAGS Cond)
15315 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
15316 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
15317 // to (Op EFLAGS !Cond)
15319 // where Op could be BRCOND or CMOV.
15321 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
15322 // Quit if not CMP and SUB with its value result used.
15323 if (Cmp.getOpcode() != X86ISD::CMP &&
15324 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
15327 // Quit if not used as a boolean value.
15328 if (CC != X86::COND_E && CC != X86::COND_NE)
15331 // Check CMP operands. One of them should be 0 or 1 and the other should be
15332 // an SetCC or extended from it.
15333 SDValue Op1 = Cmp.getOperand(0);
15334 SDValue Op2 = Cmp.getOperand(1);
15337 const ConstantSDNode* C = 0;
15338 bool needOppositeCond = (CC == X86::COND_E);
15340 if ((C = dyn_cast<ConstantSDNode>(Op1)))
15342 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
15344 else // Quit if all operands are not constants.
15347 if (C->getZExtValue() == 1)
15348 needOppositeCond = !needOppositeCond;
15349 else if (C->getZExtValue() != 0)
15350 // Quit if the constant is neither 0 or 1.
15353 // Skip 'zext' node.
15354 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
15355 SetCC = SetCC.getOperand(0);
15357 switch (SetCC.getOpcode()) {
15358 case X86ISD::SETCC:
15359 // Set the condition code or opposite one if necessary.
15360 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
15361 if (needOppositeCond)
15362 CC = X86::GetOppositeBranchCondition(CC);
15363 return SetCC.getOperand(1);
15364 case X86ISD::CMOV: {
15365 // Check whether false/true value has canonical one, i.e. 0 or 1.
15366 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
15367 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
15368 // Quit if true value is not a constant.
15371 // Quit if false value is not a constant.
15373 // A special case for rdrand, where 0 is set if false cond is found.
15374 SDValue Op = SetCC.getOperand(0);
15375 if (Op.getOpcode() != X86ISD::RDRAND)
15378 // Quit if false value is not the constant 0 or 1.
15379 bool FValIsFalse = true;
15380 if (FVal && FVal->getZExtValue() != 0) {
15381 if (FVal->getZExtValue() != 1)
15383 // If FVal is 1, opposite cond is needed.
15384 needOppositeCond = !needOppositeCond;
15385 FValIsFalse = false;
15387 // Quit if TVal is not the constant opposite of FVal.
15388 if (FValIsFalse && TVal->getZExtValue() != 1)
15390 if (!FValIsFalse && TVal->getZExtValue() != 0)
15392 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
15393 if (needOppositeCond)
15394 CC = X86::GetOppositeBranchCondition(CC);
15395 return SetCC.getOperand(3);
15402 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
15403 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
15404 TargetLowering::DAGCombinerInfo &DCI,
15405 const X86Subtarget *Subtarget) {
15406 DebugLoc DL = N->getDebugLoc();
15408 // If the flag operand isn't dead, don't touch this CMOV.
15409 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
15412 SDValue FalseOp = N->getOperand(0);
15413 SDValue TrueOp = N->getOperand(1);
15414 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
15415 SDValue Cond = N->getOperand(3);
15417 if (CC == X86::COND_E || CC == X86::COND_NE) {
15418 switch (Cond.getOpcode()) {
15422 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
15423 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
15424 return (CC == X86::COND_E) ? FalseOp : TrueOp;
15430 Flags = checkBoolTestSetCCCombine(Cond, CC);
15431 if (Flags.getNode() &&
15432 // Extra check as FCMOV only supports a subset of X86 cond.
15433 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
15434 SDValue Ops[] = { FalseOp, TrueOp,
15435 DAG.getConstant(CC, MVT::i8), Flags };
15436 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
15437 Ops, array_lengthof(Ops));
15440 // If this is a select between two integer constants, try to do some
15441 // optimizations. Note that the operands are ordered the opposite of SELECT
15443 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
15444 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
15445 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
15446 // larger than FalseC (the false value).
15447 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
15448 CC = X86::GetOppositeBranchCondition(CC);
15449 std::swap(TrueC, FalseC);
15450 std::swap(TrueOp, FalseOp);
15453 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
15454 // This is efficient for any integer data type (including i8/i16) and
15456 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
15457 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15458 DAG.getConstant(CC, MVT::i8), Cond);
15460 // Zero extend the condition if needed.
15461 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
15463 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15464 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
15465 DAG.getConstant(ShAmt, MVT::i8));
15466 if (N->getNumValues() == 2) // Dead flag value?
15467 return DCI.CombineTo(N, Cond, SDValue());
15471 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
15472 // for any integer data type, including i8/i16.
15473 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15474 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15475 DAG.getConstant(CC, MVT::i8), Cond);
15477 // Zero extend the condition if needed.
15478 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15479 FalseC->getValueType(0), Cond);
15480 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15481 SDValue(FalseC, 0));
15483 if (N->getNumValues() == 2) // Dead flag value?
15484 return DCI.CombineTo(N, Cond, SDValue());
15488 // Optimize cases that will turn into an LEA instruction. This requires
15489 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15490 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15491 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15492 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15494 bool isFastMultiplier = false;
15496 switch ((unsigned char)Diff) {
15498 case 1: // result = add base, cond
15499 case 2: // result = lea base( , cond*2)
15500 case 3: // result = lea base(cond, cond*2)
15501 case 4: // result = lea base( , cond*4)
15502 case 5: // result = lea base(cond, cond*4)
15503 case 8: // result = lea base( , cond*8)
15504 case 9: // result = lea base(cond, cond*8)
15505 isFastMultiplier = true;
15510 if (isFastMultiplier) {
15511 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15512 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
15513 DAG.getConstant(CC, MVT::i8), Cond);
15514 // Zero extend the condition if needed.
15515 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15517 // Scale the condition by the difference.
15519 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15520 DAG.getConstant(Diff, Cond.getValueType()));
15522 // Add the base if non-zero.
15523 if (FalseC->getAPIntValue() != 0)
15524 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15525 SDValue(FalseC, 0));
15526 if (N->getNumValues() == 2) // Dead flag value?
15527 return DCI.CombineTo(N, Cond, SDValue());
15534 // Handle these cases:
15535 // (select (x != c), e, c) -> select (x != c), e, x),
15536 // (select (x == c), c, e) -> select (x == c), x, e)
15537 // where the c is an integer constant, and the "select" is the combination
15538 // of CMOV and CMP.
15540 // The rationale for this change is that the conditional-move from a constant
15541 // needs two instructions, however, conditional-move from a register needs
15542 // only one instruction.
15544 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
15545 // some instruction-combining opportunities. This opt needs to be
15546 // postponed as late as possible.
15548 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
15549 // the DCI.xxxx conditions are provided to postpone the optimization as
15550 // late as possible.
15552 ConstantSDNode *CmpAgainst = 0;
15553 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
15554 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
15555 dyn_cast<ConstantSDNode>(Cond.getOperand(0)) == 0) {
15557 if (CC == X86::COND_NE &&
15558 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
15559 CC = X86::GetOppositeBranchCondition(CC);
15560 std::swap(TrueOp, FalseOp);
15563 if (CC == X86::COND_E &&
15564 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
15565 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
15566 DAG.getConstant(CC, MVT::i8), Cond };
15567 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
15568 array_lengthof(Ops));
15576 /// PerformMulCombine - Optimize a single multiply with constant into two
15577 /// in order to implement it with two cheaper instructions, e.g.
15578 /// LEA + SHL, LEA + LEA.
15579 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
15580 TargetLowering::DAGCombinerInfo &DCI) {
15581 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
15584 EVT VT = N->getValueType(0);
15585 if (VT != MVT::i64)
15588 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
15591 uint64_t MulAmt = C->getZExtValue();
15592 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
15595 uint64_t MulAmt1 = 0;
15596 uint64_t MulAmt2 = 0;
15597 if ((MulAmt % 9) == 0) {
15599 MulAmt2 = MulAmt / 9;
15600 } else if ((MulAmt % 5) == 0) {
15602 MulAmt2 = MulAmt / 5;
15603 } else if ((MulAmt % 3) == 0) {
15605 MulAmt2 = MulAmt / 3;
15608 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
15609 DebugLoc DL = N->getDebugLoc();
15611 if (isPowerOf2_64(MulAmt2) &&
15612 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
15613 // If second multiplifer is pow2, issue it first. We want the multiply by
15614 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
15616 std::swap(MulAmt1, MulAmt2);
15619 if (isPowerOf2_64(MulAmt1))
15620 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
15621 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
15623 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
15624 DAG.getConstant(MulAmt1, VT));
15626 if (isPowerOf2_64(MulAmt2))
15627 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
15628 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
15630 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
15631 DAG.getConstant(MulAmt2, VT));
15633 // Do not add new nodes to DAG combiner worklist.
15634 DCI.CombineTo(N, NewMul, false);
15639 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
15640 SDValue N0 = N->getOperand(0);
15641 SDValue N1 = N->getOperand(1);
15642 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
15643 EVT VT = N0.getValueType();
15645 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
15646 // since the result of setcc_c is all zero's or all ones.
15647 if (VT.isInteger() && !VT.isVector() &&
15648 N1C && N0.getOpcode() == ISD::AND &&
15649 N0.getOperand(1).getOpcode() == ISD::Constant) {
15650 SDValue N00 = N0.getOperand(0);
15651 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
15652 ((N00.getOpcode() == ISD::ANY_EXTEND ||
15653 N00.getOpcode() == ISD::ZERO_EXTEND) &&
15654 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
15655 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
15656 APInt ShAmt = N1C->getAPIntValue();
15657 Mask = Mask.shl(ShAmt);
15659 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
15660 N00, DAG.getConstant(Mask, VT));
15664 // Hardware support for vector shifts is sparse which makes us scalarize the
15665 // vector operations in many cases. Also, on sandybridge ADD is faster than
15667 // (shl V, 1) -> add V,V
15668 if (isSplatVector(N1.getNode())) {
15669 assert(N0.getValueType().isVector() && "Invalid vector shift type");
15670 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
15671 // We shift all of the values by one. In many cases we do not have
15672 // hardware support for this operation. This is better expressed as an ADD
15674 if (N1C && (1 == N1C->getZExtValue())) {
15675 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
15682 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
15684 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
15685 TargetLowering::DAGCombinerInfo &DCI,
15686 const X86Subtarget *Subtarget) {
15687 EVT VT = N->getValueType(0);
15688 if (N->getOpcode() == ISD::SHL) {
15689 SDValue V = PerformSHLCombine(N, DAG);
15690 if (V.getNode()) return V;
15693 // On X86 with SSE2 support, we can transform this to a vector shift if
15694 // all elements are shifted by the same amount. We can't do this in legalize
15695 // because the a constant vector is typically transformed to a constant pool
15696 // so we have no knowledge of the shift amount.
15697 if (!Subtarget->hasSSE2())
15700 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
15701 (!Subtarget->hasInt256() ||
15702 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
15705 SDValue ShAmtOp = N->getOperand(1);
15706 EVT EltVT = VT.getVectorElementType();
15707 DebugLoc DL = N->getDebugLoc();
15708 SDValue BaseShAmt = SDValue();
15709 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
15710 unsigned NumElts = VT.getVectorNumElements();
15712 for (; i != NumElts; ++i) {
15713 SDValue Arg = ShAmtOp.getOperand(i);
15714 if (Arg.getOpcode() == ISD::UNDEF) continue;
15718 // Handle the case where the build_vector is all undef
15719 // FIXME: Should DAG allow this?
15723 for (; i != NumElts; ++i) {
15724 SDValue Arg = ShAmtOp.getOperand(i);
15725 if (Arg.getOpcode() == ISD::UNDEF) continue;
15726 if (Arg != BaseShAmt) {
15730 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
15731 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
15732 SDValue InVec = ShAmtOp.getOperand(0);
15733 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
15734 unsigned NumElts = InVec.getValueType().getVectorNumElements();
15736 for (; i != NumElts; ++i) {
15737 SDValue Arg = InVec.getOperand(i);
15738 if (Arg.getOpcode() == ISD::UNDEF) continue;
15742 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
15743 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
15744 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
15745 if (C->getZExtValue() == SplatIdx)
15746 BaseShAmt = InVec.getOperand(1);
15749 if (BaseShAmt.getNode() == 0) {
15750 // Don't create instructions with illegal types after legalize
15752 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
15753 !DCI.isBeforeLegalize())
15756 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
15757 DAG.getIntPtrConstant(0));
15762 // The shift amount is an i32.
15763 if (EltVT.bitsGT(MVT::i32))
15764 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
15765 else if (EltVT.bitsLT(MVT::i32))
15766 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
15768 // The shift amount is identical so we can do a vector shift.
15769 SDValue ValOp = N->getOperand(0);
15770 switch (N->getOpcode()) {
15772 llvm_unreachable("Unknown shift opcode!");
15774 switch (VT.getSimpleVT().SimpleTy) {
15775 default: return SDValue();
15782 return getTargetVShiftNode(X86ISD::VSHLI, DL, VT, ValOp, BaseShAmt, DAG);
15785 switch (VT.getSimpleVT().SimpleTy) {
15786 default: return SDValue();
15791 return getTargetVShiftNode(X86ISD::VSRAI, DL, VT, ValOp, BaseShAmt, DAG);
15794 switch (VT.getSimpleVT().SimpleTy) {
15795 default: return SDValue();
15802 return getTargetVShiftNode(X86ISD::VSRLI, DL, VT, ValOp, BaseShAmt, DAG);
15807 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
15808 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
15809 // and friends. Likewise for OR -> CMPNEQSS.
15810 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
15811 TargetLowering::DAGCombinerInfo &DCI,
15812 const X86Subtarget *Subtarget) {
15815 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
15816 // we're requiring SSE2 for both.
15817 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
15818 SDValue N0 = N->getOperand(0);
15819 SDValue N1 = N->getOperand(1);
15820 SDValue CMP0 = N0->getOperand(1);
15821 SDValue CMP1 = N1->getOperand(1);
15822 DebugLoc DL = N->getDebugLoc();
15824 // The SETCCs should both refer to the same CMP.
15825 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
15828 SDValue CMP00 = CMP0->getOperand(0);
15829 SDValue CMP01 = CMP0->getOperand(1);
15830 EVT VT = CMP00.getValueType();
15832 if (VT == MVT::f32 || VT == MVT::f64) {
15833 bool ExpectingFlags = false;
15834 // Check for any users that want flags:
15835 for (SDNode::use_iterator UI = N->use_begin(),
15837 !ExpectingFlags && UI != UE; ++UI)
15838 switch (UI->getOpcode()) {
15843 ExpectingFlags = true;
15845 case ISD::CopyToReg:
15846 case ISD::SIGN_EXTEND:
15847 case ISD::ZERO_EXTEND:
15848 case ISD::ANY_EXTEND:
15852 if (!ExpectingFlags) {
15853 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
15854 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
15856 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
15857 X86::CondCode tmp = cc0;
15862 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
15863 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
15864 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
15865 X86ISD::NodeType NTOperator = is64BitFP ?
15866 X86ISD::FSETCCsd : X86ISD::FSETCCss;
15867 // FIXME: need symbolic constants for these magic numbers.
15868 // See X86ATTInstPrinter.cpp:printSSECC().
15869 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
15870 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
15871 DAG.getConstant(x86cc, MVT::i8));
15872 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
15874 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
15875 DAG.getConstant(1, MVT::i32));
15876 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
15877 return OneBitOfTruth;
15885 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
15886 /// so it can be folded inside ANDNP.
15887 static bool CanFoldXORWithAllOnes(const SDNode *N) {
15888 EVT VT = N->getValueType(0);
15890 // Match direct AllOnes for 128 and 256-bit vectors
15891 if (ISD::isBuildVectorAllOnes(N))
15894 // Look through a bit convert.
15895 if (N->getOpcode() == ISD::BITCAST)
15896 N = N->getOperand(0).getNode();
15898 // Sometimes the operand may come from a insert_subvector building a 256-bit
15900 if (VT.is256BitVector() &&
15901 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
15902 SDValue V1 = N->getOperand(0);
15903 SDValue V2 = N->getOperand(1);
15905 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
15906 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
15907 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
15908 ISD::isBuildVectorAllOnes(V2.getNode()))
15915 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
15916 // register. In most cases we actually compare or select YMM-sized registers
15917 // and mixing the two types creates horrible code. This method optimizes
15918 // some of the transition sequences.
15919 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
15920 TargetLowering::DAGCombinerInfo &DCI,
15921 const X86Subtarget *Subtarget) {
15922 EVT VT = N->getValueType(0);
15923 if (VT.getSizeInBits() != 256)
15926 assert((N->getOpcode() == ISD::ANY_EXTEND ||
15927 N->getOpcode() == ISD::ZERO_EXTEND ||
15928 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
15930 SDValue Narrow = N->getOperand(0);
15931 EVT NarrowVT = Narrow->getValueType(0);
15932 if (NarrowVT.getSizeInBits() != 128)
15935 if (Narrow->getOpcode() != ISD::XOR &&
15936 Narrow->getOpcode() != ISD::AND &&
15937 Narrow->getOpcode() != ISD::OR)
15940 SDValue N0 = Narrow->getOperand(0);
15941 SDValue N1 = Narrow->getOperand(1);
15942 DebugLoc DL = Narrow->getDebugLoc();
15944 // The Left side has to be a trunc.
15945 if (N0.getOpcode() != ISD::TRUNCATE)
15948 // The type of the truncated inputs.
15949 EVT WideVT = N0->getOperand(0)->getValueType(0);
15953 // The right side has to be a 'trunc' or a constant vector.
15954 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
15955 bool RHSConst = (isSplatVector(N1.getNode()) &&
15956 isa<ConstantSDNode>(N1->getOperand(0)));
15957 if (!RHSTrunc && !RHSConst)
15960 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15962 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
15965 // Set N0 and N1 to hold the inputs to the new wide operation.
15966 N0 = N0->getOperand(0);
15968 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
15969 N1->getOperand(0));
15970 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
15971 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
15972 } else if (RHSTrunc) {
15973 N1 = N1->getOperand(0);
15976 // Generate the wide operation.
15977 SDValue Op = DAG.getNode(N->getOpcode(), DL, WideVT, N0, N1);
15978 unsigned Opcode = N->getOpcode();
15980 case ISD::ANY_EXTEND:
15982 case ISD::ZERO_EXTEND: {
15983 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
15984 APInt Mask = APInt::getAllOnesValue(InBits);
15985 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
15986 return DAG.getNode(ISD::AND, DL, VT,
15987 Op, DAG.getConstant(Mask, VT));
15989 case ISD::SIGN_EXTEND:
15990 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
15991 Op, DAG.getValueType(NarrowVT));
15993 llvm_unreachable("Unexpected opcode");
15997 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
15998 TargetLowering::DAGCombinerInfo &DCI,
15999 const X86Subtarget *Subtarget) {
16000 EVT VT = N->getValueType(0);
16001 if (DCI.isBeforeLegalizeOps())
16004 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16008 // Create BLSI, and BLSR instructions
16009 // BLSI is X & (-X)
16010 // BLSR is X & (X-1)
16011 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
16012 SDValue N0 = N->getOperand(0);
16013 SDValue N1 = N->getOperand(1);
16014 DebugLoc DL = N->getDebugLoc();
16016 // Check LHS for neg
16017 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
16018 isZero(N0.getOperand(0)))
16019 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
16021 // Check RHS for neg
16022 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
16023 isZero(N1.getOperand(0)))
16024 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
16026 // Check LHS for X-1
16027 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16028 isAllOnes(N0.getOperand(1)))
16029 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
16031 // Check RHS for X-1
16032 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16033 isAllOnes(N1.getOperand(1)))
16034 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
16039 // Want to form ANDNP nodes:
16040 // 1) In the hopes of then easily combining them with OR and AND nodes
16041 // to form PBLEND/PSIGN.
16042 // 2) To match ANDN packed intrinsics
16043 if (VT != MVT::v2i64 && VT != MVT::v4i64)
16046 SDValue N0 = N->getOperand(0);
16047 SDValue N1 = N->getOperand(1);
16048 DebugLoc DL = N->getDebugLoc();
16050 // Check LHS for vnot
16051 if (N0.getOpcode() == ISD::XOR &&
16052 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
16053 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
16054 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
16056 // Check RHS for vnot
16057 if (N1.getOpcode() == ISD::XOR &&
16058 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
16059 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
16060 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
16065 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
16066 TargetLowering::DAGCombinerInfo &DCI,
16067 const X86Subtarget *Subtarget) {
16068 EVT VT = N->getValueType(0);
16069 if (DCI.isBeforeLegalizeOps())
16072 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16076 SDValue N0 = N->getOperand(0);
16077 SDValue N1 = N->getOperand(1);
16079 // look for psign/blend
16080 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
16081 if (!Subtarget->hasSSSE3() ||
16082 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
16085 // Canonicalize pandn to RHS
16086 if (N0.getOpcode() == X86ISD::ANDNP)
16088 // or (and (m, y), (pandn m, x))
16089 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
16090 SDValue Mask = N1.getOperand(0);
16091 SDValue X = N1.getOperand(1);
16093 if (N0.getOperand(0) == Mask)
16094 Y = N0.getOperand(1);
16095 if (N0.getOperand(1) == Mask)
16096 Y = N0.getOperand(0);
16098 // Check to see if the mask appeared in both the AND and ANDNP and
16102 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
16103 // Look through mask bitcast.
16104 if (Mask.getOpcode() == ISD::BITCAST)
16105 Mask = Mask.getOperand(0);
16106 if (X.getOpcode() == ISD::BITCAST)
16107 X = X.getOperand(0);
16108 if (Y.getOpcode() == ISD::BITCAST)
16109 Y = Y.getOperand(0);
16111 EVT MaskVT = Mask.getValueType();
16113 // Validate that the Mask operand is a vector sra node.
16114 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
16115 // there is no psrai.b
16116 if (Mask.getOpcode() != X86ISD::VSRAI)
16119 // Check that the SRA is all signbits.
16120 SDValue SraC = Mask.getOperand(1);
16121 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
16122 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
16123 if ((SraAmt + 1) != EltBits)
16126 DebugLoc DL = N->getDebugLoc();
16128 // We are going to replace the AND, OR, NAND with either BLEND
16129 // or PSIGN, which only look at the MSB. The VSRAI instruction
16130 // does not affect the highest bit, so we can get rid of it.
16131 Mask = Mask.getOperand(0);
16133 // Now we know we at least have a plendvb with the mask val. See if
16134 // we can form a psignb/w/d.
16135 // psign = x.type == y.type == mask.type && y = sub(0, x);
16136 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
16137 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
16138 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
16139 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
16140 "Unsupported VT for PSIGN");
16141 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask);
16142 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16144 // PBLENDVB only available on SSE 4.1
16145 if (!Subtarget->hasSSE41())
16148 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
16150 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
16151 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
16152 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
16153 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
16154 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16158 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
16161 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
16162 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16164 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
16166 if (!N0.hasOneUse() || !N1.hasOneUse())
16169 SDValue ShAmt0 = N0.getOperand(1);
16170 if (ShAmt0.getValueType() != MVT::i8)
16172 SDValue ShAmt1 = N1.getOperand(1);
16173 if (ShAmt1.getValueType() != MVT::i8)
16175 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
16176 ShAmt0 = ShAmt0.getOperand(0);
16177 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
16178 ShAmt1 = ShAmt1.getOperand(0);
16180 DebugLoc DL = N->getDebugLoc();
16181 unsigned Opc = X86ISD::SHLD;
16182 SDValue Op0 = N0.getOperand(0);
16183 SDValue Op1 = N1.getOperand(0);
16184 if (ShAmt0.getOpcode() == ISD::SUB) {
16185 Opc = X86ISD::SHRD;
16186 std::swap(Op0, Op1);
16187 std::swap(ShAmt0, ShAmt1);
16190 unsigned Bits = VT.getSizeInBits();
16191 if (ShAmt1.getOpcode() == ISD::SUB) {
16192 SDValue Sum = ShAmt1.getOperand(0);
16193 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
16194 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
16195 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
16196 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
16197 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
16198 return DAG.getNode(Opc, DL, VT,
16200 DAG.getNode(ISD::TRUNCATE, DL,
16203 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
16204 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
16206 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
16207 return DAG.getNode(Opc, DL, VT,
16208 N0.getOperand(0), N1.getOperand(0),
16209 DAG.getNode(ISD::TRUNCATE, DL,
16216 // Generate NEG and CMOV for integer abs.
16217 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
16218 EVT VT = N->getValueType(0);
16220 // Since X86 does not have CMOV for 8-bit integer, we don't convert
16221 // 8-bit integer abs to NEG and CMOV.
16222 if (VT.isInteger() && VT.getSizeInBits() == 8)
16225 SDValue N0 = N->getOperand(0);
16226 SDValue N1 = N->getOperand(1);
16227 DebugLoc DL = N->getDebugLoc();
16229 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
16230 // and change it to SUB and CMOV.
16231 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
16232 N0.getOpcode() == ISD::ADD &&
16233 N0.getOperand(1) == N1 &&
16234 N1.getOpcode() == ISD::SRA &&
16235 N1.getOperand(0) == N0.getOperand(0))
16236 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
16237 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
16238 // Generate SUB & CMOV.
16239 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
16240 DAG.getConstant(0, VT), N0.getOperand(0));
16242 SDValue Ops[] = { N0.getOperand(0), Neg,
16243 DAG.getConstant(X86::COND_GE, MVT::i8),
16244 SDValue(Neg.getNode(), 1) };
16245 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
16246 Ops, array_lengthof(Ops));
16251 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
16252 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
16253 TargetLowering::DAGCombinerInfo &DCI,
16254 const X86Subtarget *Subtarget) {
16255 EVT VT = N->getValueType(0);
16256 if (DCI.isBeforeLegalizeOps())
16259 if (Subtarget->hasCMov()) {
16260 SDValue RV = performIntegerAbsCombine(N, DAG);
16265 // Try forming BMI if it is available.
16266 if (!Subtarget->hasBMI())
16269 if (VT != MVT::i32 && VT != MVT::i64)
16272 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
16274 // Create BLSMSK instructions by finding X ^ (X-1)
16275 SDValue N0 = N->getOperand(0);
16276 SDValue N1 = N->getOperand(1);
16277 DebugLoc DL = N->getDebugLoc();
16279 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16280 isAllOnes(N0.getOperand(1)))
16281 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
16283 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16284 isAllOnes(N1.getOperand(1)))
16285 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
16290 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
16291 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
16292 TargetLowering::DAGCombinerInfo &DCI,
16293 const X86Subtarget *Subtarget) {
16294 LoadSDNode *Ld = cast<LoadSDNode>(N);
16295 EVT RegVT = Ld->getValueType(0);
16296 EVT MemVT = Ld->getMemoryVT();
16297 DebugLoc dl = Ld->getDebugLoc();
16298 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16300 ISD::LoadExtType Ext = Ld->getExtensionType();
16302 // If this is a vector EXT Load then attempt to optimize it using a
16303 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
16304 // expansion is still better than scalar code.
16305 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
16306 // emit a shuffle and a arithmetic shift.
16307 // TODO: It is possible to support ZExt by zeroing the undef values
16308 // during the shuffle phase or after the shuffle.
16309 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
16310 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
16311 assert(MemVT != RegVT && "Cannot extend to the same type");
16312 assert(MemVT.isVector() && "Must load a vector from memory");
16314 unsigned NumElems = RegVT.getVectorNumElements();
16315 unsigned RegSz = RegVT.getSizeInBits();
16316 unsigned MemSz = MemVT.getSizeInBits();
16317 assert(RegSz > MemSz && "Register size must be greater than the mem size");
16319 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
16322 // All sizes must be a power of two.
16323 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
16326 // Attempt to load the original value using scalar loads.
16327 // Find the largest scalar type that divides the total loaded size.
16328 MVT SclrLoadTy = MVT::i8;
16329 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16330 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16331 MVT Tp = (MVT::SimpleValueType)tp;
16332 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16337 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16338 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16340 SclrLoadTy = MVT::f64;
16342 // Calculate the number of scalar loads that we need to perform
16343 // in order to load our vector from memory.
16344 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16345 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
16348 unsigned loadRegZize = RegSz;
16349 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16352 // Represent our vector as a sequence of elements which are the
16353 // largest scalar that we can load.
16354 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
16355 loadRegZize/SclrLoadTy.getSizeInBits());
16357 // Represent the data using the same element type that is stored in
16358 // memory. In practice, we ''widen'' MemVT.
16360 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16361 loadRegZize/MemVT.getScalarType().getSizeInBits());
16363 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16364 "Invalid vector type");
16366 // We can't shuffle using an illegal type.
16367 if (!TLI.isTypeLegal(WideVecVT))
16370 SmallVector<SDValue, 8> Chains;
16371 SDValue Ptr = Ld->getBasePtr();
16372 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
16373 TLI.getPointerTy());
16374 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16376 for (unsigned i = 0; i < NumLoads; ++i) {
16377 // Perform a single load.
16378 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
16379 Ptr, Ld->getPointerInfo(),
16380 Ld->isVolatile(), Ld->isNonTemporal(),
16381 Ld->isInvariant(), Ld->getAlignment());
16382 Chains.push_back(ScalarLoad.getValue(1));
16383 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16384 // another round of DAGCombining.
16386 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16388 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16389 ScalarLoad, DAG.getIntPtrConstant(i));
16391 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16394 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16397 // Bitcast the loaded value to a vector of the original element type, in
16398 // the size of the target vector type.
16399 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16400 unsigned SizeRatio = RegSz/MemSz;
16402 if (Ext == ISD::SEXTLOAD) {
16403 // If we have SSE4.1 we can directly emit a VSEXT node.
16404 if (Subtarget->hasSSE41()) {
16405 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16406 return DCI.CombineTo(N, Sext, TF, true);
16409 // Otherwise we'll shuffle the small elements in the high bits of the
16410 // larger type and perform an arithmetic shift. If the shift is not legal
16411 // it's better to scalarize.
16412 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
16415 // Redistribute the loaded elements into the different locations.
16416 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16417 for (unsigned i = 0; i != NumElems; ++i)
16418 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
16420 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16421 DAG.getUNDEF(WideVecVT),
16424 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16426 // Build the arithmetic shift.
16427 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16428 MemVT.getVectorElementType().getSizeInBits();
16429 SmallVector<SDValue, 8> C(NumElems,
16430 DAG.getConstant(Amt, RegVT.getScalarType()));
16431 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, RegVT, &C[0], C.size());
16432 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff, BV);
16434 return DCI.CombineTo(N, Shuff, TF, true);
16437 // Redistribute the loaded elements into the different locations.
16438 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16439 for (unsigned i = 0; i != NumElems; ++i)
16440 ShuffleVec[i*SizeRatio] = i;
16442 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16443 DAG.getUNDEF(WideVecVT),
16446 // Bitcast to the requested type.
16447 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16448 // Replace the original load with the new sequence
16449 // and return the new chain.
16450 return DCI.CombineTo(N, Shuff, TF, true);
16456 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
16457 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
16458 const X86Subtarget *Subtarget) {
16459 StoreSDNode *St = cast<StoreSDNode>(N);
16460 EVT VT = St->getValue().getValueType();
16461 EVT StVT = St->getMemoryVT();
16462 DebugLoc dl = St->getDebugLoc();
16463 SDValue StoredVal = St->getOperand(1);
16464 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16466 // If we are saving a concatenation of two XMM registers, perform two stores.
16467 // On Sandy Bridge, 256-bit memory operations are executed by two
16468 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
16469 // memory operation.
16470 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
16471 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS &&
16472 StoredVal.getNumOperands() == 2) {
16473 SDValue Value0 = StoredVal.getOperand(0);
16474 SDValue Value1 = StoredVal.getOperand(1);
16476 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
16477 SDValue Ptr0 = St->getBasePtr();
16478 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
16480 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
16481 St->getPointerInfo(), St->isVolatile(),
16482 St->isNonTemporal(), St->getAlignment());
16483 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
16484 St->getPointerInfo(), St->isVolatile(),
16485 St->isNonTemporal(), St->getAlignment());
16486 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
16489 // Optimize trunc store (of multiple scalars) to shuffle and store.
16490 // First, pack all of the elements in one place. Next, store to memory
16491 // in fewer chunks.
16492 if (St->isTruncatingStore() && VT.isVector()) {
16493 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16494 unsigned NumElems = VT.getVectorNumElements();
16495 assert(StVT != VT && "Cannot truncate to the same type");
16496 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
16497 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
16499 // From, To sizes and ElemCount must be pow of two
16500 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
16501 // We are going to use the original vector elt for storing.
16502 // Accumulated smaller vector elements must be a multiple of the store size.
16503 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
16505 unsigned SizeRatio = FromSz / ToSz;
16507 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
16509 // Create a type on which we perform the shuffle
16510 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
16511 StVT.getScalarType(), NumElems*SizeRatio);
16513 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
16515 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
16516 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16517 for (unsigned i = 0; i != NumElems; ++i)
16518 ShuffleVec[i] = i * SizeRatio;
16520 // Can't shuffle using an illegal type.
16521 if (!TLI.isTypeLegal(WideVecVT))
16524 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
16525 DAG.getUNDEF(WideVecVT),
16527 // At this point all of the data is stored at the bottom of the
16528 // register. We now need to save it to mem.
16530 // Find the largest store unit
16531 MVT StoreType = MVT::i8;
16532 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16533 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16534 MVT Tp = (MVT::SimpleValueType)tp;
16535 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
16539 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16540 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
16541 (64 <= NumElems * ToSz))
16542 StoreType = MVT::f64;
16544 // Bitcast the original vector into a vector of store-size units
16545 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
16546 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
16547 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
16548 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
16549 SmallVector<SDValue, 8> Chains;
16550 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
16551 TLI.getPointerTy());
16552 SDValue Ptr = St->getBasePtr();
16554 // Perform one or more big stores into memory.
16555 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
16556 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
16557 StoreType, ShuffWide,
16558 DAG.getIntPtrConstant(i));
16559 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
16560 St->getPointerInfo(), St->isVolatile(),
16561 St->isNonTemporal(), St->getAlignment());
16562 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16563 Chains.push_back(Ch);
16566 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16570 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
16571 // the FP state in cases where an emms may be missing.
16572 // A preferable solution to the general problem is to figure out the right
16573 // places to insert EMMS. This qualifies as a quick hack.
16575 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
16576 if (VT.getSizeInBits() != 64)
16579 const Function *F = DAG.getMachineFunction().getFunction();
16580 bool NoImplicitFloatOps = F->getAttributes().
16581 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
16582 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
16583 && Subtarget->hasSSE2();
16584 if ((VT.isVector() ||
16585 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
16586 isa<LoadSDNode>(St->getValue()) &&
16587 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
16588 St->getChain().hasOneUse() && !St->isVolatile()) {
16589 SDNode* LdVal = St->getValue().getNode();
16590 LoadSDNode *Ld = 0;
16591 int TokenFactorIndex = -1;
16592 SmallVector<SDValue, 8> Ops;
16593 SDNode* ChainVal = St->getChain().getNode();
16594 // Must be a store of a load. We currently handle two cases: the load
16595 // is a direct child, and it's under an intervening TokenFactor. It is
16596 // possible to dig deeper under nested TokenFactors.
16597 if (ChainVal == LdVal)
16598 Ld = cast<LoadSDNode>(St->getChain());
16599 else if (St->getValue().hasOneUse() &&
16600 ChainVal->getOpcode() == ISD::TokenFactor) {
16601 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
16602 if (ChainVal->getOperand(i).getNode() == LdVal) {
16603 TokenFactorIndex = i;
16604 Ld = cast<LoadSDNode>(St->getValue());
16606 Ops.push_back(ChainVal->getOperand(i));
16610 if (!Ld || !ISD::isNormalLoad(Ld))
16613 // If this is not the MMX case, i.e. we are just turning i64 load/store
16614 // into f64 load/store, avoid the transformation if there are multiple
16615 // uses of the loaded value.
16616 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
16619 DebugLoc LdDL = Ld->getDebugLoc();
16620 DebugLoc StDL = N->getDebugLoc();
16621 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
16622 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
16624 if (Subtarget->is64Bit() || F64IsLegal) {
16625 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
16626 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
16627 Ld->getPointerInfo(), Ld->isVolatile(),
16628 Ld->isNonTemporal(), Ld->isInvariant(),
16629 Ld->getAlignment());
16630 SDValue NewChain = NewLd.getValue(1);
16631 if (TokenFactorIndex != -1) {
16632 Ops.push_back(NewChain);
16633 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16636 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
16637 St->getPointerInfo(),
16638 St->isVolatile(), St->isNonTemporal(),
16639 St->getAlignment());
16642 // Otherwise, lower to two pairs of 32-bit loads / stores.
16643 SDValue LoAddr = Ld->getBasePtr();
16644 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
16645 DAG.getConstant(4, MVT::i32));
16647 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
16648 Ld->getPointerInfo(),
16649 Ld->isVolatile(), Ld->isNonTemporal(),
16650 Ld->isInvariant(), Ld->getAlignment());
16651 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
16652 Ld->getPointerInfo().getWithOffset(4),
16653 Ld->isVolatile(), Ld->isNonTemporal(),
16655 MinAlign(Ld->getAlignment(), 4));
16657 SDValue NewChain = LoLd.getValue(1);
16658 if (TokenFactorIndex != -1) {
16659 Ops.push_back(LoLd);
16660 Ops.push_back(HiLd);
16661 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
16665 LoAddr = St->getBasePtr();
16666 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
16667 DAG.getConstant(4, MVT::i32));
16669 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
16670 St->getPointerInfo(),
16671 St->isVolatile(), St->isNonTemporal(),
16672 St->getAlignment());
16673 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
16674 St->getPointerInfo().getWithOffset(4),
16676 St->isNonTemporal(),
16677 MinAlign(St->getAlignment(), 4));
16678 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
16683 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
16684 /// and return the operands for the horizontal operation in LHS and RHS. A
16685 /// horizontal operation performs the binary operation on successive elements
16686 /// of its first operand, then on successive elements of its second operand,
16687 /// returning the resulting values in a vector. For example, if
16688 /// A = < float a0, float a1, float a2, float a3 >
16690 /// B = < float b0, float b1, float b2, float b3 >
16691 /// then the result of doing a horizontal operation on A and B is
16692 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
16693 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
16694 /// A horizontal-op B, for some already available A and B, and if so then LHS is
16695 /// set to A, RHS to B, and the routine returns 'true'.
16696 /// Note that the binary operation should have the property that if one of the
16697 /// operands is UNDEF then the result is UNDEF.
16698 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
16699 // Look for the following pattern: if
16700 // A = < float a0, float a1, float a2, float a3 >
16701 // B = < float b0, float b1, float b2, float b3 >
16703 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
16704 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
16705 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
16706 // which is A horizontal-op B.
16708 // At least one of the operands should be a vector shuffle.
16709 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
16710 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
16713 EVT VT = LHS.getValueType();
16715 assert((VT.is128BitVector() || VT.is256BitVector()) &&
16716 "Unsupported vector type for horizontal add/sub");
16718 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
16719 // operate independently on 128-bit lanes.
16720 unsigned NumElts = VT.getVectorNumElements();
16721 unsigned NumLanes = VT.getSizeInBits()/128;
16722 unsigned NumLaneElts = NumElts / NumLanes;
16723 assert((NumLaneElts % 2 == 0) &&
16724 "Vector type should have an even number of elements in each lane");
16725 unsigned HalfLaneElts = NumLaneElts/2;
16727 // View LHS in the form
16728 // LHS = VECTOR_SHUFFLE A, B, LMask
16729 // If LHS is not a shuffle then pretend it is the shuffle
16730 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
16731 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
16734 SmallVector<int, 16> LMask(NumElts);
16735 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16736 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
16737 A = LHS.getOperand(0);
16738 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
16739 B = LHS.getOperand(1);
16740 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
16741 std::copy(Mask.begin(), Mask.end(), LMask.begin());
16743 if (LHS.getOpcode() != ISD::UNDEF)
16745 for (unsigned i = 0; i != NumElts; ++i)
16749 // Likewise, view RHS in the form
16750 // RHS = VECTOR_SHUFFLE C, D, RMask
16752 SmallVector<int, 16> RMask(NumElts);
16753 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
16754 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
16755 C = RHS.getOperand(0);
16756 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
16757 D = RHS.getOperand(1);
16758 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
16759 std::copy(Mask.begin(), Mask.end(), RMask.begin());
16761 if (RHS.getOpcode() != ISD::UNDEF)
16763 for (unsigned i = 0; i != NumElts; ++i)
16767 // Check that the shuffles are both shuffling the same vectors.
16768 if (!(A == C && B == D) && !(A == D && B == C))
16771 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
16772 if (!A.getNode() && !B.getNode())
16775 // If A and B occur in reverse order in RHS, then "swap" them (which means
16776 // rewriting the mask).
16778 CommuteVectorShuffleMask(RMask, NumElts);
16780 // At this point LHS and RHS are equivalent to
16781 // LHS = VECTOR_SHUFFLE A, B, LMask
16782 // RHS = VECTOR_SHUFFLE A, B, RMask
16783 // Check that the masks correspond to performing a horizontal operation.
16784 for (unsigned i = 0; i != NumElts; ++i) {
16785 int LIdx = LMask[i], RIdx = RMask[i];
16787 // Ignore any UNDEF components.
16788 if (LIdx < 0 || RIdx < 0 ||
16789 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
16790 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
16793 // Check that successive elements are being operated on. If not, this is
16794 // not a horizontal operation.
16795 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
16796 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
16797 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
16798 if (!(LIdx == Index && RIdx == Index + 1) &&
16799 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
16803 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
16804 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
16808 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
16809 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
16810 const X86Subtarget *Subtarget) {
16811 EVT VT = N->getValueType(0);
16812 SDValue LHS = N->getOperand(0);
16813 SDValue RHS = N->getOperand(1);
16815 // Try to synthesize horizontal adds from adds of shuffles.
16816 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16817 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16818 isHorizontalBinOp(LHS, RHS, true))
16819 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
16823 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
16824 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
16825 const X86Subtarget *Subtarget) {
16826 EVT VT = N->getValueType(0);
16827 SDValue LHS = N->getOperand(0);
16828 SDValue RHS = N->getOperand(1);
16830 // Try to synthesize horizontal subs from subs of shuffles.
16831 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
16832 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
16833 isHorizontalBinOp(LHS, RHS, false))
16834 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
16838 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
16839 /// X86ISD::FXOR nodes.
16840 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
16841 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
16842 // F[X]OR(0.0, x) -> x
16843 // F[X]OR(x, 0.0) -> x
16844 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
16845 if (C->getValueAPF().isPosZero())
16846 return N->getOperand(1);
16847 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
16848 if (C->getValueAPF().isPosZero())
16849 return N->getOperand(0);
16853 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
16854 /// X86ISD::FMAX nodes.
16855 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
16856 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
16858 // Only perform optimizations if UnsafeMath is used.
16859 if (!DAG.getTarget().Options.UnsafeFPMath)
16862 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
16863 // into FMINC and FMAXC, which are Commutative operations.
16864 unsigned NewOp = 0;
16865 switch (N->getOpcode()) {
16866 default: llvm_unreachable("unknown opcode");
16867 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
16868 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
16871 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),
16872 N->getOperand(0), N->getOperand(1));
16875 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
16876 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
16877 // FAND(0.0, x) -> 0.0
16878 // FAND(x, 0.0) -> 0.0
16879 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
16880 if (C->getValueAPF().isPosZero())
16881 return N->getOperand(0);
16882 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
16883 if (C->getValueAPF().isPosZero())
16884 return N->getOperand(1);
16888 static SDValue PerformBTCombine(SDNode *N,
16890 TargetLowering::DAGCombinerInfo &DCI) {
16891 // BT ignores high bits in the bit index operand.
16892 SDValue Op1 = N->getOperand(1);
16893 if (Op1.hasOneUse()) {
16894 unsigned BitWidth = Op1.getValueSizeInBits();
16895 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
16896 APInt KnownZero, KnownOne;
16897 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
16898 !DCI.isBeforeLegalizeOps());
16899 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16900 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
16901 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
16902 DCI.CommitTargetLoweringOpt(TLO);
16907 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
16908 SDValue Op = N->getOperand(0);
16909 if (Op.getOpcode() == ISD::BITCAST)
16910 Op = Op.getOperand(0);
16911 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
16912 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
16913 VT.getVectorElementType().getSizeInBits() ==
16914 OpVT.getVectorElementType().getSizeInBits()) {
16915 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
16920 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
16921 TargetLowering::DAGCombinerInfo &DCI,
16922 const X86Subtarget *Subtarget) {
16923 if (!DCI.isBeforeLegalizeOps())
16926 if (!Subtarget->hasFp256())
16929 EVT VT = N->getValueType(0);
16930 if (VT.isVector() && VT.getSizeInBits() == 256) {
16931 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
16939 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
16940 const X86Subtarget* Subtarget) {
16941 DebugLoc dl = N->getDebugLoc();
16942 EVT VT = N->getValueType(0);
16944 // Let legalize expand this if it isn't a legal type yet.
16945 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
16948 EVT ScalarVT = VT.getScalarType();
16949 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
16950 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
16953 SDValue A = N->getOperand(0);
16954 SDValue B = N->getOperand(1);
16955 SDValue C = N->getOperand(2);
16957 bool NegA = (A.getOpcode() == ISD::FNEG);
16958 bool NegB = (B.getOpcode() == ISD::FNEG);
16959 bool NegC = (C.getOpcode() == ISD::FNEG);
16961 // Negative multiplication when NegA xor NegB
16962 bool NegMul = (NegA != NegB);
16964 A = A.getOperand(0);
16966 B = B.getOperand(0);
16968 C = C.getOperand(0);
16972 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
16974 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
16976 return DAG.getNode(Opcode, dl, VT, A, B, C);
16979 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
16980 TargetLowering::DAGCombinerInfo &DCI,
16981 const X86Subtarget *Subtarget) {
16982 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
16983 // (and (i32 x86isd::setcc_carry), 1)
16984 // This eliminates the zext. This transformation is necessary because
16985 // ISD::SETCC is always legalized to i8.
16986 DebugLoc dl = N->getDebugLoc();
16987 SDValue N0 = N->getOperand(0);
16988 EVT VT = N->getValueType(0);
16990 if (N0.getOpcode() == ISD::AND &&
16992 N0.getOperand(0).hasOneUse()) {
16993 SDValue N00 = N0.getOperand(0);
16994 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
16995 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
16996 if (!C || C->getZExtValue() != 1)
16998 return DAG.getNode(ISD::AND, dl, VT,
16999 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
17000 N00.getOperand(0), N00.getOperand(1)),
17001 DAG.getConstant(1, VT));
17005 if (VT.isVector() && VT.getSizeInBits() == 256) {
17006 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17014 // Optimize x == -y --> x+y == 0
17015 // x != -y --> x+y != 0
17016 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
17017 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
17018 SDValue LHS = N->getOperand(0);
17019 SDValue RHS = N->getOperand(1);
17021 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
17022 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
17023 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
17024 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17025 LHS.getValueType(), RHS, LHS.getOperand(1));
17026 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17027 addV, DAG.getConstant(0, addV.getValueType()), CC);
17029 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
17030 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
17031 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
17032 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17033 RHS.getValueType(), LHS, RHS.getOperand(1));
17034 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17035 addV, DAG.getConstant(0, addV.getValueType()), CC);
17040 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
17041 // as "sbb reg,reg", since it can be extended without zext and produces
17042 // an all-ones bit which is more useful than 0/1 in some cases.
17043 static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
17044 return DAG.getNode(ISD::AND, DL, MVT::i8,
17045 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
17046 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
17047 DAG.getConstant(1, MVT::i8));
17050 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
17051 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
17052 TargetLowering::DAGCombinerInfo &DCI,
17053 const X86Subtarget *Subtarget) {
17054 DebugLoc DL = N->getDebugLoc();
17055 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
17056 SDValue EFLAGS = N->getOperand(1);
17058 if (CC == X86::COND_A) {
17059 // Try to convert COND_A into COND_B in an attempt to facilitate
17060 // materializing "setb reg".
17062 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
17063 // cannot take an immediate as its first operand.
17065 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
17066 EFLAGS.getValueType().isInteger() &&
17067 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
17068 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(),
17069 EFLAGS.getNode()->getVTList(),
17070 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
17071 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
17072 return MaterializeSETB(DL, NewEFLAGS, DAG);
17076 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
17077 // a zext and produces an all-ones bit which is more useful than 0/1 in some
17079 if (CC == X86::COND_B)
17080 return MaterializeSETB(DL, EFLAGS, DAG);
17084 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17085 if (Flags.getNode()) {
17086 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17087 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
17093 // Optimize branch condition evaluation.
17095 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
17096 TargetLowering::DAGCombinerInfo &DCI,
17097 const X86Subtarget *Subtarget) {
17098 DebugLoc DL = N->getDebugLoc();
17099 SDValue Chain = N->getOperand(0);
17100 SDValue Dest = N->getOperand(1);
17101 SDValue EFLAGS = N->getOperand(3);
17102 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
17106 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17107 if (Flags.getNode()) {
17108 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17109 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
17116 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
17117 const X86TargetLowering *XTLI) {
17118 SDValue Op0 = N->getOperand(0);
17119 EVT InVT = Op0->getValueType(0);
17121 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
17122 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
17123 DebugLoc dl = N->getDebugLoc();
17124 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
17125 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
17126 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
17129 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
17130 // a 32-bit target where SSE doesn't support i64->FP operations.
17131 if (Op0.getOpcode() == ISD::LOAD) {
17132 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
17133 EVT VT = Ld->getValueType(0);
17134 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
17135 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
17136 !XTLI->getSubtarget()->is64Bit() &&
17137 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17138 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
17139 Ld->getChain(), Op0, DAG);
17140 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
17147 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
17148 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
17149 X86TargetLowering::DAGCombinerInfo &DCI) {
17150 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
17151 // the result is either zero or one (depending on the input carry bit).
17152 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
17153 if (X86::isZeroNode(N->getOperand(0)) &&
17154 X86::isZeroNode(N->getOperand(1)) &&
17155 // We don't have a good way to replace an EFLAGS use, so only do this when
17157 SDValue(N, 1).use_empty()) {
17158 DebugLoc DL = N->getDebugLoc();
17159 EVT VT = N->getValueType(0);
17160 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
17161 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
17162 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
17163 DAG.getConstant(X86::COND_B,MVT::i8),
17165 DAG.getConstant(1, VT));
17166 return DCI.CombineTo(N, Res1, CarryOut);
17172 // fold (add Y, (sete X, 0)) -> adc 0, Y
17173 // (add Y, (setne X, 0)) -> sbb -1, Y
17174 // (sub (sete X, 0), Y) -> sbb 0, Y
17175 // (sub (setne X, 0), Y) -> adc -1, Y
17176 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
17177 DebugLoc DL = N->getDebugLoc();
17179 // Look through ZExts.
17180 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
17181 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
17184 SDValue SetCC = Ext.getOperand(0);
17185 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
17188 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
17189 if (CC != X86::COND_E && CC != X86::COND_NE)
17192 SDValue Cmp = SetCC.getOperand(1);
17193 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
17194 !X86::isZeroNode(Cmp.getOperand(1)) ||
17195 !Cmp.getOperand(0).getValueType().isInteger())
17198 SDValue CmpOp0 = Cmp.getOperand(0);
17199 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
17200 DAG.getConstant(1, CmpOp0.getValueType()));
17202 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
17203 if (CC == X86::COND_NE)
17204 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
17205 DL, OtherVal.getValueType(), OtherVal,
17206 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
17207 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
17208 DL, OtherVal.getValueType(), OtherVal,
17209 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
17212 /// PerformADDCombine - Do target-specific dag combines on integer adds.
17213 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
17214 const X86Subtarget *Subtarget) {
17215 EVT VT = N->getValueType(0);
17216 SDValue Op0 = N->getOperand(0);
17217 SDValue Op1 = N->getOperand(1);
17219 // Try to synthesize horizontal adds from adds of shuffles.
17220 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17221 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17222 isHorizontalBinOp(Op0, Op1, true))
17223 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
17225 return OptimizeConditionalInDecrement(N, DAG);
17228 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
17229 const X86Subtarget *Subtarget) {
17230 SDValue Op0 = N->getOperand(0);
17231 SDValue Op1 = N->getOperand(1);
17233 // X86 can't encode an immediate LHS of a sub. See if we can push the
17234 // negation into a preceding instruction.
17235 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
17236 // If the RHS of the sub is a XOR with one use and a constant, invert the
17237 // immediate. Then add one to the LHS of the sub so we can turn
17238 // X-Y -> X+~Y+1, saving one register.
17239 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
17240 isa<ConstantSDNode>(Op1.getOperand(1))) {
17241 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
17242 EVT VT = Op0.getValueType();
17243 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
17245 DAG.getConstant(~XorC, VT));
17246 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
17247 DAG.getConstant(C->getAPIntValue()+1, VT));
17251 // Try to synthesize horizontal adds from adds of shuffles.
17252 EVT VT = N->getValueType(0);
17253 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17254 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17255 isHorizontalBinOp(Op0, Op1, true))
17256 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
17258 return OptimizeConditionalInDecrement(N, DAG);
17261 /// performVZEXTCombine - Performs build vector combines
17262 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
17263 TargetLowering::DAGCombinerInfo &DCI,
17264 const X86Subtarget *Subtarget) {
17265 // (vzext (bitcast (vzext (x)) -> (vzext x)
17266 SDValue In = N->getOperand(0);
17267 while (In.getOpcode() == ISD::BITCAST)
17268 In = In.getOperand(0);
17270 if (In.getOpcode() != X86ISD::VZEXT)
17273 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0), In.getOperand(0));
17276 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
17277 DAGCombinerInfo &DCI) const {
17278 SelectionDAG &DAG = DCI.DAG;
17279 switch (N->getOpcode()) {
17281 case ISD::EXTRACT_VECTOR_ELT:
17282 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
17284 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
17285 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
17286 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
17287 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
17288 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
17289 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
17292 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
17293 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
17294 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
17295 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
17296 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
17297 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
17298 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
17299 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
17300 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
17302 case X86ISD::FOR: return PerformFORCombine(N, DAG);
17304 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
17305 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
17306 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
17307 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
17308 case ISD::ANY_EXTEND:
17309 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
17310 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
17311 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
17312 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
17313 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
17314 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
17315 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
17316 case X86ISD::SHUFP: // Handle all target specific shuffles
17317 case X86ISD::PALIGN:
17318 case X86ISD::UNPCKH:
17319 case X86ISD::UNPCKL:
17320 case X86ISD::MOVHLPS:
17321 case X86ISD::MOVLHPS:
17322 case X86ISD::PSHUFD:
17323 case X86ISD::PSHUFHW:
17324 case X86ISD::PSHUFLW:
17325 case X86ISD::MOVSS:
17326 case X86ISD::MOVSD:
17327 case X86ISD::VPERMILP:
17328 case X86ISD::VPERM2X128:
17329 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
17330 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
17336 /// isTypeDesirableForOp - Return true if the target has native support for
17337 /// the specified value type and it is 'desirable' to use the type for the
17338 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
17339 /// instruction encodings are longer and some i16 instructions are slow.
17340 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
17341 if (!isTypeLegal(VT))
17343 if (VT != MVT::i16)
17350 case ISD::SIGN_EXTEND:
17351 case ISD::ZERO_EXTEND:
17352 case ISD::ANY_EXTEND:
17365 /// IsDesirableToPromoteOp - This method query the target whether it is
17366 /// beneficial for dag combiner to promote the specified node. If true, it
17367 /// should return the desired promotion type by reference.
17368 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
17369 EVT VT = Op.getValueType();
17370 if (VT != MVT::i16)
17373 bool Promote = false;
17374 bool Commute = false;
17375 switch (Op.getOpcode()) {
17378 LoadSDNode *LD = cast<LoadSDNode>(Op);
17379 // If the non-extending load has a single use and it's not live out, then it
17380 // might be folded.
17381 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
17382 Op.hasOneUse()*/) {
17383 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
17384 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
17385 // The only case where we'd want to promote LOAD (rather then it being
17386 // promoted as an operand is when it's only use is liveout.
17387 if (UI->getOpcode() != ISD::CopyToReg)
17394 case ISD::SIGN_EXTEND:
17395 case ISD::ZERO_EXTEND:
17396 case ISD::ANY_EXTEND:
17401 SDValue N0 = Op.getOperand(0);
17402 // Look out for (store (shl (load), x)).
17403 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
17416 SDValue N0 = Op.getOperand(0);
17417 SDValue N1 = Op.getOperand(1);
17418 if (!Commute && MayFoldLoad(N1))
17420 // Avoid disabling potential load folding opportunities.
17421 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
17423 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
17433 //===----------------------------------------------------------------------===//
17434 // X86 Inline Assembly Support
17435 //===----------------------------------------------------------------------===//
17438 // Helper to match a string separated by whitespace.
17439 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
17440 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
17442 for (unsigned i = 0, e = args.size(); i != e; ++i) {
17443 StringRef piece(*args[i]);
17444 if (!s.startswith(piece)) // Check if the piece matches.
17447 s = s.substr(piece.size());
17448 StringRef::size_type pos = s.find_first_not_of(" \t");
17449 if (pos == 0) // We matched a prefix.
17457 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
17460 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
17461 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
17463 std::string AsmStr = IA->getAsmString();
17465 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
17466 if (!Ty || Ty->getBitWidth() % 16 != 0)
17469 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
17470 SmallVector<StringRef, 4> AsmPieces;
17471 SplitString(AsmStr, AsmPieces, ";\n");
17473 switch (AsmPieces.size()) {
17474 default: return false;
17476 // FIXME: this should verify that we are targeting a 486 or better. If not,
17477 // we will turn this bswap into something that will be lowered to logical
17478 // ops instead of emitting the bswap asm. For now, we don't support 486 or
17479 // lower so don't worry about this.
17481 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
17482 matchAsm(AsmPieces[0], "bswapl", "$0") ||
17483 matchAsm(AsmPieces[0], "bswapq", "$0") ||
17484 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
17485 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
17486 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
17487 // No need to check constraints, nothing other than the equivalent of
17488 // "=r,0" would be valid here.
17489 return IntrinsicLowering::LowerToByteSwap(CI);
17492 // rorw $$8, ${0:w} --> llvm.bswap.i16
17493 if (CI->getType()->isIntegerTy(16) &&
17494 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17495 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
17496 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
17498 const std::string &ConstraintsStr = IA->getConstraintString();
17499 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17500 std::sort(AsmPieces.begin(), AsmPieces.end());
17501 if (AsmPieces.size() == 4 &&
17502 AsmPieces[0] == "~{cc}" &&
17503 AsmPieces[1] == "~{dirflag}" &&
17504 AsmPieces[2] == "~{flags}" &&
17505 AsmPieces[3] == "~{fpsr}")
17506 return IntrinsicLowering::LowerToByteSwap(CI);
17510 if (CI->getType()->isIntegerTy(32) &&
17511 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
17512 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
17513 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
17514 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
17516 const std::string &ConstraintsStr = IA->getConstraintString();
17517 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
17518 std::sort(AsmPieces.begin(), AsmPieces.end());
17519 if (AsmPieces.size() == 4 &&
17520 AsmPieces[0] == "~{cc}" &&
17521 AsmPieces[1] == "~{dirflag}" &&
17522 AsmPieces[2] == "~{flags}" &&
17523 AsmPieces[3] == "~{fpsr}")
17524 return IntrinsicLowering::LowerToByteSwap(CI);
17527 if (CI->getType()->isIntegerTy(64)) {
17528 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
17529 if (Constraints.size() >= 2 &&
17530 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
17531 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
17532 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
17533 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
17534 matchAsm(AsmPieces[1], "bswap", "%edx") &&
17535 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
17536 return IntrinsicLowering::LowerToByteSwap(CI);
17544 /// getConstraintType - Given a constraint letter, return the type of
17545 /// constraint it is for this target.
17546 X86TargetLowering::ConstraintType
17547 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
17548 if (Constraint.size() == 1) {
17549 switch (Constraint[0]) {
17560 return C_RegisterClass;
17584 return TargetLowering::getConstraintType(Constraint);
17587 /// Examine constraint type and operand type and determine a weight value.
17588 /// This object must already have been set up with the operand type
17589 /// and the current alternative constraint selected.
17590 TargetLowering::ConstraintWeight
17591 X86TargetLowering::getSingleConstraintMatchWeight(
17592 AsmOperandInfo &info, const char *constraint) const {
17593 ConstraintWeight weight = CW_Invalid;
17594 Value *CallOperandVal = info.CallOperandVal;
17595 // If we don't have a value, we can't do a match,
17596 // but allow it at the lowest weight.
17597 if (CallOperandVal == NULL)
17599 Type *type = CallOperandVal->getType();
17600 // Look at the constraint type.
17601 switch (*constraint) {
17603 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
17614 if (CallOperandVal->getType()->isIntegerTy())
17615 weight = CW_SpecificReg;
17620 if (type->isFloatingPointTy())
17621 weight = CW_SpecificReg;
17624 if (type->isX86_MMXTy() && Subtarget->hasMMX())
17625 weight = CW_SpecificReg;
17629 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
17630 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
17631 weight = CW_Register;
17634 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
17635 if (C->getZExtValue() <= 31)
17636 weight = CW_Constant;
17640 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17641 if (C->getZExtValue() <= 63)
17642 weight = CW_Constant;
17646 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17647 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
17648 weight = CW_Constant;
17652 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17653 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
17654 weight = CW_Constant;
17658 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17659 if (C->getZExtValue() <= 3)
17660 weight = CW_Constant;
17664 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17665 if (C->getZExtValue() <= 0xff)
17666 weight = CW_Constant;
17671 if (dyn_cast<ConstantFP>(CallOperandVal)) {
17672 weight = CW_Constant;
17676 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17677 if ((C->getSExtValue() >= -0x80000000LL) &&
17678 (C->getSExtValue() <= 0x7fffffffLL))
17679 weight = CW_Constant;
17683 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
17684 if (C->getZExtValue() <= 0xffffffff)
17685 weight = CW_Constant;
17692 /// LowerXConstraint - try to replace an X constraint, which matches anything,
17693 /// with another that has more specific requirements based on the type of the
17694 /// corresponding operand.
17695 const char *X86TargetLowering::
17696 LowerXConstraint(EVT ConstraintVT) const {
17697 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
17698 // 'f' like normal targets.
17699 if (ConstraintVT.isFloatingPoint()) {
17700 if (Subtarget->hasSSE2())
17702 if (Subtarget->hasSSE1())
17706 return TargetLowering::LowerXConstraint(ConstraintVT);
17709 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
17710 /// vector. If it is invalid, don't add anything to Ops.
17711 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
17712 std::string &Constraint,
17713 std::vector<SDValue>&Ops,
17714 SelectionDAG &DAG) const {
17715 SDValue Result(0, 0);
17717 // Only support length 1 constraints for now.
17718 if (Constraint.length() > 1) return;
17720 char ConstraintLetter = Constraint[0];
17721 switch (ConstraintLetter) {
17724 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17725 if (C->getZExtValue() <= 31) {
17726 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17732 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17733 if (C->getZExtValue() <= 63) {
17734 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17741 if (isInt<8>(C->getSExtValue())) {
17742 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17748 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17749 if (C->getZExtValue() <= 255) {
17750 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17756 // 32-bit signed value
17757 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17758 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17759 C->getSExtValue())) {
17760 // Widen to 64 bits here to get it sign extended.
17761 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
17764 // FIXME gcc accepts some relocatable values here too, but only in certain
17765 // memory models; it's complicated.
17770 // 32-bit unsigned value
17771 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
17772 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
17773 C->getZExtValue())) {
17774 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
17778 // FIXME gcc accepts some relocatable values here too, but only in certain
17779 // memory models; it's complicated.
17783 // Literal immediates are always ok.
17784 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
17785 // Widen to 64 bits here to get it sign extended.
17786 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
17790 // In any sort of PIC mode addresses need to be computed at runtime by
17791 // adding in a register or some sort of table lookup. These can't
17792 // be used as immediates.
17793 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
17796 // If we are in non-pic codegen mode, we allow the address of a global (with
17797 // an optional displacement) to be used with 'i'.
17798 GlobalAddressSDNode *GA = 0;
17799 int64_t Offset = 0;
17801 // Match either (GA), (GA+C), (GA+C1+C2), etc.
17803 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
17804 Offset += GA->getOffset();
17806 } else if (Op.getOpcode() == ISD::ADD) {
17807 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17808 Offset += C->getZExtValue();
17809 Op = Op.getOperand(0);
17812 } else if (Op.getOpcode() == ISD::SUB) {
17813 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
17814 Offset += -C->getZExtValue();
17815 Op = Op.getOperand(0);
17820 // Otherwise, this isn't something we can handle, reject it.
17824 const GlobalValue *GV = GA->getGlobal();
17825 // If we require an extra load to get this address, as in PIC mode, we
17826 // can't accept it.
17827 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
17828 getTargetMachine())))
17831 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
17832 GA->getValueType(0), Offset);
17837 if (Result.getNode()) {
17838 Ops.push_back(Result);
17841 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
17844 std::pair<unsigned, const TargetRegisterClass*>
17845 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
17847 // First, see if this is a constraint that directly corresponds to an LLVM
17849 if (Constraint.size() == 1) {
17850 // GCC Constraint Letters
17851 switch (Constraint[0]) {
17853 // TODO: Slight differences here in allocation order and leaving
17854 // RIP in the class. Do they matter any more here than they do
17855 // in the normal allocation?
17856 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
17857 if (Subtarget->is64Bit()) {
17858 if (VT == MVT::i32 || VT == MVT::f32)
17859 return std::make_pair(0U, &X86::GR32RegClass);
17860 if (VT == MVT::i16)
17861 return std::make_pair(0U, &X86::GR16RegClass);
17862 if (VT == MVT::i8 || VT == MVT::i1)
17863 return std::make_pair(0U, &X86::GR8RegClass);
17864 if (VT == MVT::i64 || VT == MVT::f64)
17865 return std::make_pair(0U, &X86::GR64RegClass);
17868 // 32-bit fallthrough
17869 case 'Q': // Q_REGS
17870 if (VT == MVT::i32 || VT == MVT::f32)
17871 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
17872 if (VT == MVT::i16)
17873 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
17874 if (VT == MVT::i8 || VT == MVT::i1)
17875 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
17876 if (VT == MVT::i64)
17877 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
17879 case 'r': // GENERAL_REGS
17880 case 'l': // INDEX_REGS
17881 if (VT == MVT::i8 || VT == MVT::i1)
17882 return std::make_pair(0U, &X86::GR8RegClass);
17883 if (VT == MVT::i16)
17884 return std::make_pair(0U, &X86::GR16RegClass);
17885 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
17886 return std::make_pair(0U, &X86::GR32RegClass);
17887 return std::make_pair(0U, &X86::GR64RegClass);
17888 case 'R': // LEGACY_REGS
17889 if (VT == MVT::i8 || VT == MVT::i1)
17890 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
17891 if (VT == MVT::i16)
17892 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
17893 if (VT == MVT::i32 || !Subtarget->is64Bit())
17894 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
17895 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
17896 case 'f': // FP Stack registers.
17897 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
17898 // value to the correct fpstack register class.
17899 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
17900 return std::make_pair(0U, &X86::RFP32RegClass);
17901 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
17902 return std::make_pair(0U, &X86::RFP64RegClass);
17903 return std::make_pair(0U, &X86::RFP80RegClass);
17904 case 'y': // MMX_REGS if MMX allowed.
17905 if (!Subtarget->hasMMX()) break;
17906 return std::make_pair(0U, &X86::VR64RegClass);
17907 case 'Y': // SSE_REGS if SSE2 allowed
17908 if (!Subtarget->hasSSE2()) break;
17910 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
17911 if (!Subtarget->hasSSE1()) break;
17913 switch (VT.getSimpleVT().SimpleTy) {
17915 // Scalar SSE types.
17918 return std::make_pair(0U, &X86::FR32RegClass);
17921 return std::make_pair(0U, &X86::FR64RegClass);
17929 return std::make_pair(0U, &X86::VR128RegClass);
17937 return std::make_pair(0U, &X86::VR256RegClass);
17943 // Use the default implementation in TargetLowering to convert the register
17944 // constraint into a member of a register class.
17945 std::pair<unsigned, const TargetRegisterClass*> Res;
17946 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
17948 // Not found as a standard register?
17949 if (Res.second == 0) {
17950 // Map st(0) -> st(7) -> ST0
17951 if (Constraint.size() == 7 && Constraint[0] == '{' &&
17952 tolower(Constraint[1]) == 's' &&
17953 tolower(Constraint[2]) == 't' &&
17954 Constraint[3] == '(' &&
17955 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
17956 Constraint[5] == ')' &&
17957 Constraint[6] == '}') {
17959 Res.first = X86::ST0+Constraint[4]-'0';
17960 Res.second = &X86::RFP80RegClass;
17964 // GCC allows "st(0)" to be called just plain "st".
17965 if (StringRef("{st}").equals_lower(Constraint)) {
17966 Res.first = X86::ST0;
17967 Res.second = &X86::RFP80RegClass;
17972 if (StringRef("{flags}").equals_lower(Constraint)) {
17973 Res.first = X86::EFLAGS;
17974 Res.second = &X86::CCRRegClass;
17978 // 'A' means EAX + EDX.
17979 if (Constraint == "A") {
17980 Res.first = X86::EAX;
17981 Res.second = &X86::GR32_ADRegClass;
17987 // Otherwise, check to see if this is a register class of the wrong value
17988 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
17989 // turn into {ax},{dx}.
17990 if (Res.second->hasType(VT))
17991 return Res; // Correct type already, nothing to do.
17993 // All of the single-register GCC register classes map their values onto
17994 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
17995 // really want an 8-bit or 32-bit register, map to the appropriate register
17996 // class and return the appropriate register.
17997 if (Res.second == &X86::GR16RegClass) {
17998 if (VT == MVT::i8) {
17999 unsigned DestReg = 0;
18000 switch (Res.first) {
18002 case X86::AX: DestReg = X86::AL; break;
18003 case X86::DX: DestReg = X86::DL; break;
18004 case X86::CX: DestReg = X86::CL; break;
18005 case X86::BX: DestReg = X86::BL; break;
18008 Res.first = DestReg;
18009 Res.second = &X86::GR8RegClass;
18011 } else if (VT == MVT::i32) {
18012 unsigned DestReg = 0;
18013 switch (Res.first) {
18015 case X86::AX: DestReg = X86::EAX; break;
18016 case X86::DX: DestReg = X86::EDX; break;
18017 case X86::CX: DestReg = X86::ECX; break;
18018 case X86::BX: DestReg = X86::EBX; break;
18019 case X86::SI: DestReg = X86::ESI; break;
18020 case X86::DI: DestReg = X86::EDI; break;
18021 case X86::BP: DestReg = X86::EBP; break;
18022 case X86::SP: DestReg = X86::ESP; break;
18025 Res.first = DestReg;
18026 Res.second = &X86::GR32RegClass;
18028 } else if (VT == MVT::i64) {
18029 unsigned DestReg = 0;
18030 switch (Res.first) {
18032 case X86::AX: DestReg = X86::RAX; break;
18033 case X86::DX: DestReg = X86::RDX; break;
18034 case X86::CX: DestReg = X86::RCX; break;
18035 case X86::BX: DestReg = X86::RBX; break;
18036 case X86::SI: DestReg = X86::RSI; break;
18037 case X86::DI: DestReg = X86::RDI; break;
18038 case X86::BP: DestReg = X86::RBP; break;
18039 case X86::SP: DestReg = X86::RSP; break;
18042 Res.first = DestReg;
18043 Res.second = &X86::GR64RegClass;
18046 } else if (Res.second == &X86::FR32RegClass ||
18047 Res.second == &X86::FR64RegClass ||
18048 Res.second == &X86::VR128RegClass) {
18049 // Handle references to XMM physical registers that got mapped into the
18050 // wrong class. This can happen with constraints like {xmm0} where the
18051 // target independent register mapper will just pick the first match it can
18052 // find, ignoring the required type.
18054 if (VT == MVT::f32 || VT == MVT::i32)
18055 Res.second = &X86::FR32RegClass;
18056 else if (VT == MVT::f64 || VT == MVT::i64)
18057 Res.second = &X86::FR64RegClass;
18058 else if (X86::VR128RegClass.hasType(VT))
18059 Res.second = &X86::VR128RegClass;
18060 else if (X86::VR256RegClass.hasType(VT))
18061 Res.second = &X86::VR256RegClass;
18067 //===----------------------------------------------------------------------===//
18071 //===----------------------------------------------------------------------===//
18073 struct X86CostTblEntry {
18080 FindInTable(const X86CostTblEntry *Tbl, unsigned len, int ISD, MVT Ty) {
18081 for (unsigned int i = 0; i < len; ++i)
18082 if (Tbl[i].ISD == ISD && Tbl[i].Type == Ty)
18085 // Could not find an entry.
18089 struct X86TypeConversionCostTblEntry {
18097 FindInConvertTable(const X86TypeConversionCostTblEntry *Tbl, unsigned len,
18098 int ISD, MVT Dst, MVT Src) {
18099 for (unsigned int i = 0; i < len; ++i)
18100 if (Tbl[i].ISD == ISD && Tbl[i].Src == Src && Tbl[i].Dst == Dst)
18103 // Could not find an entry.
18107 ScalarTargetTransformInfo::PopcntHwSupport
18108 X86ScalarTargetTransformImpl::getPopcntHwSupport(unsigned TyWidth) const {
18109 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
18110 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget<X86Subtarget>();
18112 // TODO: Currently the __builtin_popcount() implementation using SSE3
18113 // instructions is inefficient. Once the problem is fixed, we should
18114 // call ST.hasSSE3() instead of ST.hasSSE4().
18115 return ST.hasSSE41() ? Fast : None;
18119 X86VectorTargetTransformInfo::getArithmeticInstrCost(unsigned Opcode,
18121 // Legalize the type.
18122 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(Ty);
18124 int ISD = InstructionOpcodeToISD(Opcode);
18125 assert(ISD && "Invalid opcode");
18127 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget<X86Subtarget>();
18129 static const X86CostTblEntry AVX1CostTable[] = {
18130 // We don't have to scalarize unsupported ops. We can issue two half-sized
18131 // operations and we only need to extract the upper YMM half.
18132 // Two ops + 1 extract + 1 insert = 4.
18133 { ISD::MUL, MVT::v8i32, 4 },
18134 { ISD::SUB, MVT::v8i32, 4 },
18135 { ISD::ADD, MVT::v8i32, 4 },
18136 { ISD::MUL, MVT::v4i64, 4 },
18137 { ISD::SUB, MVT::v4i64, 4 },
18138 { ISD::ADD, MVT::v4i64, 4 },
18141 // Look for AVX1 lowering tricks.
18143 int Idx = FindInTable(AVX1CostTable, array_lengthof(AVX1CostTable), ISD,
18146 return LT.first * AVX1CostTable[Idx].Cost;
18148 // Fallback to the default implementation.
18149 return VectorTargetTransformImpl::getArithmeticInstrCost(Opcode, Ty);
18153 X86VectorTargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
18154 unsigned Alignment,
18155 unsigned AddressSpace) const {
18156 // Legalize the type.
18157 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(Src);
18158 assert((Opcode == Instruction::Load || Opcode == Instruction::Store) &&
18161 const X86Subtarget &ST =
18162 TLI->getTargetMachine().getSubtarget<X86Subtarget>();
18164 // Each load/store unit costs 1.
18165 unsigned Cost = LT.first * 1;
18167 // On Sandybridge 256bit load/stores are double pumped
18168 // (but not on Haswell).
18169 if (LT.second.getSizeInBits() > 128 && !ST.hasAVX2())
18176 X86VectorTargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
18177 unsigned Index) const {
18178 assert(Val->isVectorTy() && "This must be a vector type");
18180 if (Index != -1U) {
18181 // Legalize the type.
18182 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(Val);
18184 // This type is legalized to a scalar type.
18185 if (!LT.second.isVector())
18188 // The type may be split. Normalize the index to the new type.
18189 unsigned Width = LT.second.getVectorNumElements();
18190 Index = Index % Width;
18192 // Floating point scalars are already located in index #0.
18193 if (Val->getScalarType()->isFloatingPointTy() && Index == 0)
18197 return VectorTargetTransformImpl::getVectorInstrCost(Opcode, Val, Index);
18200 unsigned X86VectorTargetTransformInfo::getCmpSelInstrCost(unsigned Opcode,
18202 Type *CondTy) const {
18203 // Legalize the type.
18204 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(ValTy);
18206 MVT MTy = LT.second;
18208 int ISD = InstructionOpcodeToISD(Opcode);
18209 assert(ISD && "Invalid opcode");
18211 const X86Subtarget &ST =
18212 TLI->getTargetMachine().getSubtarget<X86Subtarget>();
18214 static const X86CostTblEntry SSE42CostTbl[] = {
18215 { ISD::SETCC, MVT::v2f64, 1 },
18216 { ISD::SETCC, MVT::v4f32, 1 },
18217 { ISD::SETCC, MVT::v2i64, 1 },
18218 { ISD::SETCC, MVT::v4i32, 1 },
18219 { ISD::SETCC, MVT::v8i16, 1 },
18220 { ISD::SETCC, MVT::v16i8, 1 },
18223 static const X86CostTblEntry AVX1CostTbl[] = {
18224 { ISD::SETCC, MVT::v4f64, 1 },
18225 { ISD::SETCC, MVT::v8f32, 1 },
18226 // AVX1 does not support 8-wide integer compare.
18227 { ISD::SETCC, MVT::v4i64, 4 },
18228 { ISD::SETCC, MVT::v8i32, 4 },
18229 { ISD::SETCC, MVT::v16i16, 4 },
18230 { ISD::SETCC, MVT::v32i8, 4 },
18233 static const X86CostTblEntry AVX2CostTbl[] = {
18234 { ISD::SETCC, MVT::v4i64, 1 },
18235 { ISD::SETCC, MVT::v8i32, 1 },
18236 { ISD::SETCC, MVT::v16i16, 1 },
18237 { ISD::SETCC, MVT::v32i8, 1 },
18240 if (ST.hasAVX2()) {
18241 int Idx = FindInTable(AVX2CostTbl, array_lengthof(AVX2CostTbl), ISD, MTy);
18243 return LT.first * AVX2CostTbl[Idx].Cost;
18247 int Idx = FindInTable(AVX1CostTbl, array_lengthof(AVX1CostTbl), ISD, MTy);
18249 return LT.first * AVX1CostTbl[Idx].Cost;
18252 if (ST.hasSSE42()) {
18253 int Idx = FindInTable(SSE42CostTbl, array_lengthof(SSE42CostTbl), ISD, MTy);
18255 return LT.first * SSE42CostTbl[Idx].Cost;
18258 return VectorTargetTransformImpl::getCmpSelInstrCost(Opcode, ValTy, CondTy);
18261 unsigned X86VectorTargetTransformInfo::getCastInstrCost(unsigned Opcode,
18264 int ISD = InstructionOpcodeToISD(Opcode);
18265 assert(ISD && "Invalid opcode");
18267 EVT SrcTy = TLI->getValueType(Src);
18268 EVT DstTy = TLI->getValueType(Dst);
18270 if (!SrcTy.isSimple() || !DstTy.isSimple())
18271 return VectorTargetTransformImpl::getCastInstrCost(Opcode, Dst, Src);
18273 const X86Subtarget &ST = TLI->getTargetMachine().getSubtarget<X86Subtarget>();
18275 static const X86TypeConversionCostTblEntry AVXConversionTbl[] = {
18276 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
18277 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i16, 1 },
18278 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
18279 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i32, 1 },
18280 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 1 },
18281 { ISD::TRUNCATE, MVT::v8i16, MVT::v8i32, 1 },
18282 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
18283 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
18284 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i8, 1 },
18285 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 1 },
18286 { ISD::FP_TO_SINT, MVT::v8i8, MVT::v8f32, 1 },
18287 { ISD::FP_TO_SINT, MVT::v4i8, MVT::v4f32, 1 },
18288 { ISD::ZERO_EXTEND, MVT::v8i32, MVT::v8i1, 6 },
18289 { ISD::SIGN_EXTEND, MVT::v8i32, MVT::v8i1, 9 },
18290 { ISD::TRUNCATE, MVT::v8i32, MVT::v8i64, 3 },
18294 int Idx = FindInConvertTable(AVXConversionTbl,
18295 array_lengthof(AVXConversionTbl),
18296 ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT());
18298 return AVXConversionTbl[Idx].Cost;
18301 return VectorTargetTransformImpl::getCastInstrCost(Opcode, Dst, Src);
18305 unsigned X86VectorTargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Tp,
18307 // We only estimate the cost of reverse shuffles.
18308 if (Kind != Reverse)
18309 return VectorTargetTransformImpl::getShuffleCost(Kind, Tp, Index);
18311 std::pair<unsigned, MVT> LT = getTypeLegalizationCost(Tp);
18313 if (LT.second.getSizeInBits() > 128)
18314 Cost = 3; // Extract + insert + copy.
18316 // Multiple by the number of parts.
18317 return Cost * LT.first;