1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/Analysis/LibCallSemantics.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/WinEHFuncInfo.h"
37 #include "llvm/IR/CallSite.h"
38 #include "llvm/IR/CallingConv.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DerivedTypes.h"
41 #include "llvm/IR/Function.h"
42 #include "llvm/IR/GlobalAlias.h"
43 #include "llvm/IR/GlobalVariable.h"
44 #include "llvm/IR/Instructions.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCExpr.h"
49 #include "llvm/MC/MCSymbol.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/Debug.h"
52 #include "llvm/Support/ErrorHandling.h"
53 #include "llvm/Support/MathExtras.h"
54 #include "llvm/Target/TargetOptions.h"
55 #include "X86IntrinsicsInfo.h"
61 #define DEBUG_TYPE "x86-isel"
63 STATISTIC(NumTailCalls, "Number of tail calls");
65 static cl::opt<bool> ExperimentalVectorWideningLegalization(
66 "x86-experimental-vector-widening-legalization", cl::init(false),
67 cl::desc("Enable an experimental vector type legalization through widening "
68 "rather than promotion."),
71 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
72 const X86Subtarget &STI)
73 : TargetLowering(TM), Subtarget(&STI) {
74 X86ScalarSSEf64 = Subtarget->hasSSE2();
75 X86ScalarSSEf32 = Subtarget->hasSSE1();
76 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
78 // Set up the TargetLowering object.
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
204 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
205 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
207 if (!Subtarget->useSoftFloat()) {
208 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
209 // are Legal, f80 is custom lowered.
210 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
211 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
213 if (X86ScalarSSEf32) {
214 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
215 // f32 and f64 cases are Legal, f80 case is not
216 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
219 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
222 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
223 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Expand);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Expand);
227 // Handle FP_TO_UINT by promoting the destination to a larger signed
229 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
230 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
233 if (Subtarget->is64Bit()) {
234 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
235 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
237 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
239 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
240 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
242 } else if (!Subtarget->useSoftFloat()) {
243 // Since AVX is a superset of SSE3, only check for SSE here.
244 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
245 // Expand FP_TO_UINT into a select.
246 // FIXME: We would like to use a Custom expander here eventually to do
247 // the optimal thing for SSE vs. the default expansion in the legalizer.
248 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
250 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
251 // With SSE3 we can use fisttpll to convert to a signed i64; without
252 // SSE, we're stuck with a fistpll.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
255 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
258 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
259 if (!X86ScalarSSEf64) {
260 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
261 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
262 if (Subtarget->is64Bit()) {
263 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
264 // Without SSE, i64->f64 goes through memory.
265 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
269 // Scalar integer divide and remainder are lowered to use operations that
270 // produce two results, to match the available instructions. This exposes
271 // the two-result form to trivial CSE, which is able to combine x/y and x%y
272 // into a single instruction.
274 // Scalar integer multiply-high is also lowered to use two-result
275 // operations, to match the available instructions. However, plain multiply
276 // (low) operations are left as Legal, as there are single-result
277 // instructions for this in x86. Using the two-result multiply instructions
278 // when both high and low results are needed must be arranged by dagcombine.
279 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
280 setOperationAction(ISD::MULHS, VT, Expand);
281 setOperationAction(ISD::MULHU, VT, Expand);
282 setOperationAction(ISD::SDIV, VT, Expand);
283 setOperationAction(ISD::UDIV, VT, Expand);
284 setOperationAction(ISD::SREM, VT, Expand);
285 setOperationAction(ISD::UREM, VT, Expand);
287 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
288 setOperationAction(ISD::ADDC, VT, Custom);
289 setOperationAction(ISD::ADDE, VT, Custom);
290 setOperationAction(ISD::SUBC, VT, Custom);
291 setOperationAction(ISD::SUBE, VT, Custom);
294 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
295 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
296 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
298 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
302 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
309 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
310 if (Subtarget->is64Bit())
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
314 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
315 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
317 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
318 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
319 // is. We should promote the value to 64-bits to solve this.
320 // This is what the CRT headers do - `fmodf` is an inline header
321 // function casting to f64 and calling `fmod`.
322 setOperationAction(ISD::FREM , MVT::f32 , Promote);
324 setOperationAction(ISD::FREM , MVT::f32 , Expand);
327 setOperationAction(ISD::FREM , MVT::f64 , Expand);
328 setOperationAction(ISD::FREM , MVT::f80 , Expand);
329 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
331 // Promote the i8 variants and force them on up to i32 which has a shorter
333 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
334 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
336 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
337 if (Subtarget->hasBMI()) {
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
339 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
343 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
344 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
345 if (Subtarget->is64Bit())
346 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
349 if (Subtarget->hasLZCNT()) {
350 // When promoting the i8 variants, force them to i32 for a shorter
352 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
353 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
355 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
356 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
358 if (Subtarget->is64Bit())
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
361 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
362 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
363 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
365 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
366 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
367 if (Subtarget->is64Bit()) {
368 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
369 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
373 // Special handling for half-precision floating point conversions.
374 // If we don't have F16C support, then lower half float conversions
375 // into library calls.
376 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
377 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
378 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
381 // There's never any support for operations beyond MVT::f32.
382 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
383 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
384 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
385 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
387 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
388 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
389 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
390 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
391 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
392 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
394 if (Subtarget->hasPOPCNT()) {
395 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
397 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
398 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
399 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
400 if (Subtarget->is64Bit())
401 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
404 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
406 if (!Subtarget->hasMOVBE())
407 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
409 // These should be promoted to a larger select which is supported.
410 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
411 // X86 wants to expand cmov itself.
412 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
413 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
414 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
415 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
416 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
417 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
418 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
419 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
420 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
421 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
422 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
423 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
424 setOperationAction(ISD::SETCCE , MVT::i8 , Custom);
425 setOperationAction(ISD::SETCCE , MVT::i16 , Custom);
426 setOperationAction(ISD::SETCCE , MVT::i32 , Custom);
427 if (Subtarget->is64Bit()) {
428 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
429 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
430 setOperationAction(ISD::SETCCE , MVT::i64 , Custom);
432 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
433 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
434 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
435 // support continuation, user-level threading, and etc.. As a result, no
436 // other SjLj exception interfaces are implemented and please don't build
437 // your own exception handling based on them.
438 // LLVM/Clang supports zero-cost DWARF exception handling.
439 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
440 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
443 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
446 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
447 if (Subtarget->is64Bit())
448 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
449 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
450 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
451 if (Subtarget->is64Bit()) {
452 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
453 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
454 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
455 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
456 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
458 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
459 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
460 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
461 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
462 if (Subtarget->is64Bit()) {
463 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
464 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
465 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
468 if (Subtarget->hasSSE1())
469 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
471 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
473 // Expand certain atomics
474 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
475 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
476 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
477 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
480 if (Subtarget->hasCmpxchg16b()) {
481 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
484 // FIXME - use subtarget debug flags
485 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
486 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
487 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
491 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
493 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
494 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
496 setOperationAction(ISD::TRAP, MVT::Other, Legal);
497 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
499 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
500 setOperationAction(ISD::VASTART , MVT::Other, Custom);
501 setOperationAction(ISD::VAEND , MVT::Other, Expand);
502 if (Subtarget->is64Bit()) {
503 setOperationAction(ISD::VAARG , MVT::Other, Custom);
504 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
506 // TargetInfo::CharPtrBuiltinVaList
507 setOperationAction(ISD::VAARG , MVT::Other, Expand);
508 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
511 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
512 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
514 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
516 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
517 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
518 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
520 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
521 // f32 and f64 use SSE.
522 // Set up the FP register classes.
523 addRegisterClass(MVT::f32, &X86::FR32RegClass);
524 addRegisterClass(MVT::f64, &X86::FR64RegClass);
526 // Use ANDPD to simulate FABS.
527 setOperationAction(ISD::FABS , MVT::f64, Custom);
528 setOperationAction(ISD::FABS , MVT::f32, Custom);
530 // Use XORP to simulate FNEG.
531 setOperationAction(ISD::FNEG , MVT::f64, Custom);
532 setOperationAction(ISD::FNEG , MVT::f32, Custom);
534 // Use ANDPD and ORPD to simulate FCOPYSIGN.
535 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
536 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
538 // Lower this to FGETSIGNx86 plus an AND.
539 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
540 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
542 // We don't support sin/cos/fmod
543 setOperationAction(ISD::FSIN , MVT::f64, Expand);
544 setOperationAction(ISD::FCOS , MVT::f64, Expand);
545 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
546 setOperationAction(ISD::FSIN , MVT::f32, Expand);
547 setOperationAction(ISD::FCOS , MVT::f32, Expand);
548 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
550 // Expand FP immediates into loads from the stack, except for the special
552 addLegalFPImmediate(APFloat(+0.0)); // xorpd
553 addLegalFPImmediate(APFloat(+0.0f)); // xorps
554 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
555 // Use SSE for f32, x87 for f64.
556 // Set up the FP register classes.
557 addRegisterClass(MVT::f32, &X86::FR32RegClass);
558 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
560 // Use ANDPS to simulate FABS.
561 setOperationAction(ISD::FABS , MVT::f32, Custom);
563 // Use XORP to simulate FNEG.
564 setOperationAction(ISD::FNEG , MVT::f32, Custom);
566 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
568 // Use ANDPS and ORPS to simulate FCOPYSIGN.
569 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
570 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
572 // We don't support sin/cos/fmod
573 setOperationAction(ISD::FSIN , MVT::f32, Expand);
574 setOperationAction(ISD::FCOS , MVT::f32, Expand);
575 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
577 // Special cases we handle for FP constants.
578 addLegalFPImmediate(APFloat(+0.0f)); // xorps
579 addLegalFPImmediate(APFloat(+0.0)); // FLD0
580 addLegalFPImmediate(APFloat(+1.0)); // FLD1
581 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
582 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
584 if (!TM.Options.UnsafeFPMath) {
585 setOperationAction(ISD::FSIN , MVT::f64, Expand);
586 setOperationAction(ISD::FCOS , MVT::f64, Expand);
587 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
589 } else if (!Subtarget->useSoftFloat()) {
590 // f32 and f64 in x87.
591 // Set up the FP register classes.
592 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
593 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
595 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
596 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
598 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
600 if (!TM.Options.UnsafeFPMath) {
601 setOperationAction(ISD::FSIN , MVT::f64, Expand);
602 setOperationAction(ISD::FSIN , MVT::f32, Expand);
603 setOperationAction(ISD::FCOS , MVT::f64, Expand);
604 setOperationAction(ISD::FCOS , MVT::f32, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
608 addLegalFPImmediate(APFloat(+0.0)); // FLD0
609 addLegalFPImmediate(APFloat(+1.0)); // FLD1
610 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
611 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
612 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
613 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
614 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
615 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
618 // We don't support FMA.
619 setOperationAction(ISD::FMA, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f32, Expand);
622 // Long double always uses X87.
623 if (!Subtarget->useSoftFloat()) {
624 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
625 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
628 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
629 addLegalFPImmediate(TmpFlt); // FLD0
631 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
634 APFloat TmpFlt2(+1.0);
635 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
637 addLegalFPImmediate(TmpFlt2); // FLD1
638 TmpFlt2.changeSign();
639 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
642 if (!TM.Options.UnsafeFPMath) {
643 setOperationAction(ISD::FSIN , MVT::f80, Expand);
644 setOperationAction(ISD::FCOS , MVT::f80, Expand);
645 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
648 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
649 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
650 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
651 setOperationAction(ISD::FRINT, MVT::f80, Expand);
652 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
653 setOperationAction(ISD::FMA, MVT::f80, Expand);
656 // Always use a library call for pow.
657 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
659 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
661 setOperationAction(ISD::FLOG, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
663 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP, MVT::f80, Expand);
665 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
666 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
667 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
669 // First set operation action for all vector types to either promote
670 // (for widening) or expand (for scalarization). Then we will selectively
671 // turn on ones that can be effectively codegen'd.
672 for (MVT VT : MVT::vector_valuetypes()) {
673 setOperationAction(ISD::ADD , VT, Expand);
674 setOperationAction(ISD::SUB , VT, Expand);
675 setOperationAction(ISD::FADD, VT, Expand);
676 setOperationAction(ISD::FNEG, VT, Expand);
677 setOperationAction(ISD::FSUB, VT, Expand);
678 setOperationAction(ISD::MUL , VT, Expand);
679 setOperationAction(ISD::FMUL, VT, Expand);
680 setOperationAction(ISD::SDIV, VT, Expand);
681 setOperationAction(ISD::UDIV, VT, Expand);
682 setOperationAction(ISD::FDIV, VT, Expand);
683 setOperationAction(ISD::SREM, VT, Expand);
684 setOperationAction(ISD::UREM, VT, Expand);
685 setOperationAction(ISD::LOAD, VT, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
687 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
688 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
689 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
691 setOperationAction(ISD::FABS, VT, Expand);
692 setOperationAction(ISD::FSIN, VT, Expand);
693 setOperationAction(ISD::FSINCOS, VT, Expand);
694 setOperationAction(ISD::FCOS, VT, Expand);
695 setOperationAction(ISD::FSINCOS, VT, Expand);
696 setOperationAction(ISD::FREM, VT, Expand);
697 setOperationAction(ISD::FMA, VT, Expand);
698 setOperationAction(ISD::FPOWI, VT, Expand);
699 setOperationAction(ISD::FSQRT, VT, Expand);
700 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
701 setOperationAction(ISD::FFLOOR, VT, Expand);
702 setOperationAction(ISD::FCEIL, VT, Expand);
703 setOperationAction(ISD::FTRUNC, VT, Expand);
704 setOperationAction(ISD::FRINT, VT, Expand);
705 setOperationAction(ISD::FNEARBYINT, VT, Expand);
706 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
707 setOperationAction(ISD::MULHS, VT, Expand);
708 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
709 setOperationAction(ISD::MULHU, VT, Expand);
710 setOperationAction(ISD::SDIVREM, VT, Expand);
711 setOperationAction(ISD::UDIVREM, VT, Expand);
712 setOperationAction(ISD::FPOW, VT, Expand);
713 setOperationAction(ISD::CTPOP, VT, Expand);
714 setOperationAction(ISD::CTTZ, VT, Expand);
715 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
716 setOperationAction(ISD::CTLZ, VT, Expand);
717 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
718 setOperationAction(ISD::SHL, VT, Expand);
719 setOperationAction(ISD::SRA, VT, Expand);
720 setOperationAction(ISD::SRL, VT, Expand);
721 setOperationAction(ISD::ROTL, VT, Expand);
722 setOperationAction(ISD::ROTR, VT, Expand);
723 setOperationAction(ISD::BSWAP, VT, Expand);
724 setOperationAction(ISD::SETCC, VT, Expand);
725 setOperationAction(ISD::FLOG, VT, Expand);
726 setOperationAction(ISD::FLOG2, VT, Expand);
727 setOperationAction(ISD::FLOG10, VT, Expand);
728 setOperationAction(ISD::FEXP, VT, Expand);
729 setOperationAction(ISD::FEXP2, VT, Expand);
730 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
731 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
732 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
734 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
735 setOperationAction(ISD::TRUNCATE, VT, Expand);
736 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
737 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
738 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
739 setOperationAction(ISD::VSELECT, VT, Expand);
740 setOperationAction(ISD::SELECT_CC, VT, Expand);
741 for (MVT InnerVT : MVT::vector_valuetypes()) {
742 setTruncStoreAction(InnerVT, VT, Expand);
744 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
745 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
747 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
748 // types, we have to deal with them whether we ask for Expansion or not.
749 // Setting Expand causes its own optimisation problems though, so leave
751 if (VT.getVectorElementType() == MVT::i1)
752 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
754 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
755 // split/scalarized right now.
756 if (VT.getVectorElementType() == MVT::f16)
757 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
761 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
762 // with -msoft-float, disable use of MMX as well.
763 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
764 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
765 // No operations on x86mmx supported, everything uses intrinsics.
768 // MMX-sized vectors (other than x86mmx) are expected to be expanded
769 // into smaller operations.
770 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
771 setOperationAction(ISD::MULHS, MMXTy, Expand);
772 setOperationAction(ISD::AND, MMXTy, Expand);
773 setOperationAction(ISD::OR, MMXTy, Expand);
774 setOperationAction(ISD::XOR, MMXTy, Expand);
775 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
776 setOperationAction(ISD::SELECT, MMXTy, Expand);
777 setOperationAction(ISD::BITCAST, MMXTy, Expand);
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
781 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
782 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
784 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
785 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
786 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
787 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
789 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
790 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
791 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
792 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
793 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
794 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
796 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
797 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
800 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
801 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
803 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
804 // registers cannot be used even for integer operations.
805 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
806 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
807 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
808 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
810 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
811 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
812 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
813 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
814 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
815 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
816 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
817 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
819 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
820 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
821 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
822 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
823 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
824 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
825 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
826 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
832 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
834 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
835 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
836 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
837 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
839 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
840 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
841 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
842 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
845 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
848 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
853 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
857 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
858 // ISD::CTTZ v2i64 - scalarization is faster.
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
861 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
862 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
864 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
865 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
866 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
867 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
868 setOperationAction(ISD::VSELECT, VT, Custom);
869 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
872 // We support custom legalizing of sext and anyext loads for specific
873 // memory vector types which we can load as a scalar (or sequence of
874 // scalars) and extend in-register to a legal 128-bit vector type. For sext
875 // loads these must work with a single scalar load.
876 for (MVT VT : MVT::integer_vector_valuetypes()) {
877 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
878 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
879 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
880 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
881 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
882 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
883 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
888 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
889 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
890 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
891 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
892 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
893 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
894 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
895 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
897 if (Subtarget->is64Bit()) {
898 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
899 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
902 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
903 for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) {
904 setOperationAction(ISD::AND, VT, Promote);
905 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
906 setOperationAction(ISD::OR, VT, Promote);
907 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
908 setOperationAction(ISD::XOR, VT, Promote);
909 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
910 setOperationAction(ISD::LOAD, VT, Promote);
911 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
912 setOperationAction(ISD::SELECT, VT, Promote);
913 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
916 // Custom lower v2i64 and v2f64 selects.
917 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
918 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
919 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
922 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
925 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
927 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
928 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
929 // As there is no 64-bit GPR available, we need build a special custom
930 // sequence to convert from v2i32 to v2f32.
931 if (!Subtarget->is64Bit())
932 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
934 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
935 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
937 for (MVT VT : MVT::fp_vector_valuetypes())
938 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
940 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
941 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
942 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
945 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
946 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
947 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
948 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
949 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
950 setOperationAction(ISD::FRINT, RoundedTy, Legal);
951 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
954 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
955 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
957 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
958 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
959 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
960 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
961 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
963 // FIXME: Do we need to handle scalar-to-vector here?
964 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
966 // We directly match byte blends in the backend as they match the VSELECT
968 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
970 // SSE41 brings specific instructions for doing vector sign extend even in
971 // cases where we don't have SRA.
972 for (MVT VT : MVT::integer_vector_valuetypes()) {
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
974 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
975 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
978 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
983 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
984 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
990 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
991 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
993 // i8 and i16 vectors are custom because the source register and source
994 // source memory operand types are not the same width. f32 vectors are
995 // custom since the immediate controlling the insert encodes additional
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
999 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1000 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1004 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1005 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1007 // FIXME: these should be Legal, but that's only for the case where
1008 // the index is constant. For now custom expand to deal with that.
1009 if (Subtarget->is64Bit()) {
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1011 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1015 if (Subtarget->hasSSE2()) {
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1020 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1021 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1023 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1024 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1026 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1027 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1029 // In the customized shift lowering, the legal cases in AVX2 will be
1031 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1032 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1034 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1035 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1037 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1038 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1041 if (Subtarget->hasXOP()) {
1042 setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
1043 setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
1044 setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
1045 setOperationAction(ISD::ROTL, MVT::v2i64, Custom);
1046 setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
1047 setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
1048 setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
1049 setOperationAction(ISD::ROTL, MVT::v4i64, Custom);
1052 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1053 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1054 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1060 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1061 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1064 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1075 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1077 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1078 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1088 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1090 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1091 // even though v8i16 is a legal type.
1092 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1093 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1096 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1098 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1100 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1103 for (MVT VT : MVT::fp_vector_valuetypes())
1104 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1106 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1107 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1109 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1110 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1112 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1113 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1115 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1120 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1124 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1127 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1130 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1133 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1137 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1142 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1146 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1151 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1152 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1153 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1155 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1156 setOperationAction(ISD::FMA, MVT::f32, Legal);
1157 setOperationAction(ISD::FMA, MVT::f64, Legal);
1160 if (Subtarget->hasInt256()) {
1161 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1162 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1164 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1167 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1168 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1169 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1171 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1172 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1173 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1174 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1176 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1177 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1179 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1181 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1184 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1187 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1190 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1194 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1195 // when we have a 256bit-wide blend with immediate.
1196 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1198 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1199 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1206 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1213 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1214 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1215 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1216 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1218 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1219 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1220 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1221 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1223 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1224 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1225 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1226 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1228 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1231 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1234 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1237 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1242 // In the customized shift lowering, the legal cases in AVX2 will be
1244 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1245 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1247 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1248 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1250 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1251 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1253 // Custom lower several nodes for 256-bit types.
1254 for (MVT VT : MVT::vector_valuetypes()) {
1255 if (VT.getScalarSizeInBits() >= 32) {
1256 setOperationAction(ISD::MLOAD, VT, Legal);
1257 setOperationAction(ISD::MSTORE, VT, Legal);
1259 // Extract subvector is special because the value type
1260 // (result) is 128-bit but the source is 256-bit wide.
1261 if (VT.is128BitVector()) {
1262 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1264 // Do not attempt to custom lower other non-256-bit vectors
1265 if (!VT.is256BitVector())
1268 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1269 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1270 setOperationAction(ISD::VSELECT, VT, Custom);
1271 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1272 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1274 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1275 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1278 if (Subtarget->hasInt256())
1279 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1281 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1282 for (auto VT : { MVT::v32i8, MVT::v16i16, MVT::v8i32 }) {
1283 setOperationAction(ISD::AND, VT, Promote);
1284 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1285 setOperationAction(ISD::OR, VT, Promote);
1286 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1287 setOperationAction(ISD::XOR, VT, Promote);
1288 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1289 setOperationAction(ISD::LOAD, VT, Promote);
1290 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1291 setOperationAction(ISD::SELECT, VT, Promote);
1292 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1296 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1297 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1298 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1299 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1300 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1302 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1303 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1304 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1306 for (MVT VT : MVT::fp_vector_valuetypes())
1307 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1309 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1310 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1311 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1312 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1313 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1314 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1315 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1316 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1317 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1318 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1319 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1320 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1322 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1323 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1324 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1325 setOperationAction(ISD::XOR, MVT::i1, Legal);
1326 setOperationAction(ISD::OR, MVT::i1, Legal);
1327 setOperationAction(ISD::AND, MVT::i1, Legal);
1328 setOperationAction(ISD::SUB, MVT::i1, Custom);
1329 setOperationAction(ISD::ADD, MVT::i1, Custom);
1330 setOperationAction(ISD::MUL, MVT::i1, Custom);
1331 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1332 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1333 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1334 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1335 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1337 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1338 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1339 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1340 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1341 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1342 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1344 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1345 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1346 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1348 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1350 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1353 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1354 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1355 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1356 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1357 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1358 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1359 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1360 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1361 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1362 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1363 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1364 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1365 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1366 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1367 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1368 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1370 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1371 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1372 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1373 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1374 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1375 if (Subtarget->hasVLX()){
1376 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1377 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1378 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1379 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1380 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1382 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1383 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1384 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1385 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1386 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1388 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1389 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1390 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1391 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1392 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1393 if (Subtarget->hasDQI()) {
1394 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1395 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1397 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1398 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1399 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1400 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1401 if (Subtarget->hasVLX()) {
1402 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1403 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1404 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1406 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1407 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1408 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1409 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1412 if (Subtarget->hasVLX()) {
1413 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1414 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1415 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1417 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1418 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1419 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1420 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1422 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1423 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1424 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1425 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1426 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1427 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1428 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1429 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1430 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1431 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1432 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1433 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1434 if (Subtarget->hasDQI()) {
1435 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1438 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1439 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1440 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1441 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1442 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1443 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1444 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1445 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1446 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1447 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1449 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1450 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1451 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1452 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1453 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Custom);
1455 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1456 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1458 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1461 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1462 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1463 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1464 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1465 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1466 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1467 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1468 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1469 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1472 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1473 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1474 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1475 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1476 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1477 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1478 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1479 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1481 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1482 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1484 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1485 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1487 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1489 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1490 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1492 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1493 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1495 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1496 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1498 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1499 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1500 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1501 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1502 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1503 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1505 if (Subtarget->hasCDI()) {
1506 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1507 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1508 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1509 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1511 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1512 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1513 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1514 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1516 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1517 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1518 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1520 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1521 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1523 if (Subtarget->hasVLX()) {
1524 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1525 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1526 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1527 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1529 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1530 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1531 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1533 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1534 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1535 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1536 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1538 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1539 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1540 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1541 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1542 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1543 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1544 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1545 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1547 } // Subtarget->hasCDI()
1549 if (Subtarget->hasDQI()) {
1550 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1551 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1552 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1554 // Custom lower several nodes.
1555 for (MVT VT : MVT::vector_valuetypes()) {
1556 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1558 setOperationAction(ISD::AND, VT, Legal);
1559 setOperationAction(ISD::OR, VT, Legal);
1560 setOperationAction(ISD::XOR, VT, Legal);
1562 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1563 setOperationAction(ISD::MGATHER, VT, Custom);
1564 setOperationAction(ISD::MSCATTER, VT, Custom);
1566 // Extract subvector is special because the value type
1567 // (result) is 256/128-bit but the source is 512-bit wide.
1568 if (VT.is128BitVector() || VT.is256BitVector()) {
1569 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1571 if (VT.getVectorElementType() == MVT::i1)
1572 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1574 // Do not attempt to custom lower other non-512-bit vectors
1575 if (!VT.is512BitVector())
1578 if (EltSize >= 32) {
1579 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1580 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1581 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1582 setOperationAction(ISD::VSELECT, VT, Legal);
1583 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1584 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1585 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1586 setOperationAction(ISD::MLOAD, VT, Legal);
1587 setOperationAction(ISD::MSTORE, VT, Legal);
1590 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
1591 setOperationAction(ISD::SELECT, VT, Promote);
1592 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1596 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1597 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1598 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1600 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1601 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1603 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1604 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1605 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1606 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1607 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1608 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1609 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1610 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1611 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1612 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1613 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1614 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1615 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1616 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1617 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1618 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1619 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1620 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1621 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1622 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1623 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1624 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1625 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1626 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1627 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1628 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1629 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1630 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1631 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i8, Custom);
1632 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1633 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1634 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1635 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1636 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1637 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1638 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1639 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1640 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1641 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1642 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1646 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1647 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1648 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1649 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1650 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1651 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1652 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1653 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1655 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1656 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1657 if (Subtarget->hasVLX())
1658 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1660 if (Subtarget->hasCDI()) {
1661 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1662 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1663 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1664 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1667 for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
1668 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1669 setOperationAction(ISD::VSELECT, VT, Legal);
1673 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1674 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1675 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1677 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1678 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1679 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1680 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1681 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1682 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1683 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1684 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1685 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1686 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1687 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1688 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1690 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1691 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1692 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1693 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1694 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1695 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1696 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1697 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1699 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1700 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1701 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1702 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1703 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1704 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1705 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1706 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1709 // We want to custom lower some of our intrinsics.
1710 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1711 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1712 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1713 if (!Subtarget->is64Bit())
1714 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1716 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1717 // handle type legalization for these operations here.
1719 // FIXME: We really should do custom legalization for addition and
1720 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1721 // than generic legalization for 64-bit multiplication-with-overflow, though.
1722 for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }) {
1723 if (VT == MVT::i64 && !Subtarget->is64Bit())
1725 // Add/Sub/Mul with overflow operations are custom lowered.
1726 setOperationAction(ISD::SADDO, VT, Custom);
1727 setOperationAction(ISD::UADDO, VT, Custom);
1728 setOperationAction(ISD::SSUBO, VT, Custom);
1729 setOperationAction(ISD::USUBO, VT, Custom);
1730 setOperationAction(ISD::SMULO, VT, Custom);
1731 setOperationAction(ISD::UMULO, VT, Custom);
1734 if (!Subtarget->is64Bit()) {
1735 // These libcalls are not available in 32-bit.
1736 setLibcallName(RTLIB::SHL_I128, nullptr);
1737 setLibcallName(RTLIB::SRL_I128, nullptr);
1738 setLibcallName(RTLIB::SRA_I128, nullptr);
1741 // Combine sin / cos into one node or libcall if possible.
1742 if (Subtarget->hasSinCos()) {
1743 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1744 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1745 if (Subtarget->isTargetDarwin()) {
1746 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1747 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1748 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1749 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1753 if (Subtarget->isTargetWin64()) {
1754 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1755 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1756 setOperationAction(ISD::SREM, MVT::i128, Custom);
1757 setOperationAction(ISD::UREM, MVT::i128, Custom);
1758 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1759 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1762 // We have target-specific dag combine patterns for the following nodes:
1763 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1764 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1765 setTargetDAGCombine(ISD::BITCAST);
1766 setTargetDAGCombine(ISD::VSELECT);
1767 setTargetDAGCombine(ISD::SELECT);
1768 setTargetDAGCombine(ISD::SHL);
1769 setTargetDAGCombine(ISD::SRA);
1770 setTargetDAGCombine(ISD::SRL);
1771 setTargetDAGCombine(ISD::OR);
1772 setTargetDAGCombine(ISD::AND);
1773 setTargetDAGCombine(ISD::ADD);
1774 setTargetDAGCombine(ISD::FADD);
1775 setTargetDAGCombine(ISD::FSUB);
1776 setTargetDAGCombine(ISD::FNEG);
1777 setTargetDAGCombine(ISD::FMA);
1778 setTargetDAGCombine(ISD::SUB);
1779 setTargetDAGCombine(ISD::LOAD);
1780 setTargetDAGCombine(ISD::MLOAD);
1781 setTargetDAGCombine(ISD::STORE);
1782 setTargetDAGCombine(ISD::MSTORE);
1783 setTargetDAGCombine(ISD::TRUNCATE);
1784 setTargetDAGCombine(ISD::ZERO_EXTEND);
1785 setTargetDAGCombine(ISD::ANY_EXTEND);
1786 setTargetDAGCombine(ISD::SIGN_EXTEND);
1787 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1788 setTargetDAGCombine(ISD::SINT_TO_FP);
1789 setTargetDAGCombine(ISD::UINT_TO_FP);
1790 setTargetDAGCombine(ISD::SETCC);
1791 setTargetDAGCombine(ISD::BUILD_VECTOR);
1792 setTargetDAGCombine(ISD::MUL);
1793 setTargetDAGCombine(ISD::XOR);
1795 computeRegisterProperties(Subtarget->getRegisterInfo());
1797 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1798 MaxStoresPerMemsetOptSize = 8;
1799 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1800 MaxStoresPerMemcpyOptSize = 4;
1801 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1802 MaxStoresPerMemmoveOptSize = 4;
1803 setPrefLoopAlignment(4); // 2^4 bytes.
1805 // A predictable cmov does not hurt on an in-order CPU.
1806 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1807 PredictableSelectIsExpensive = !Subtarget->isAtom();
1808 EnableExtLdPromotion = true;
1809 setPrefFunctionAlignment(4); // 2^4 bytes.
1811 verifyIntrinsicTables();
1814 // This has so far only been implemented for 64-bit MachO.
1815 bool X86TargetLowering::useLoadStackGuardNode() const {
1816 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1819 TargetLoweringBase::LegalizeTypeAction
1820 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1821 if (ExperimentalVectorWideningLegalization &&
1822 VT.getVectorNumElements() != 1 &&
1823 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1824 return TypeWidenVector;
1826 return TargetLoweringBase::getPreferredVectorAction(VT);
1829 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1832 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1834 if (VT.isSimple()) {
1835 MVT VVT = VT.getSimpleVT();
1836 const unsigned NumElts = VVT.getVectorNumElements();
1837 const MVT EltVT = VVT.getVectorElementType();
1838 if (VVT.is512BitVector()) {
1839 if (Subtarget->hasAVX512())
1840 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1841 EltVT == MVT::f32 || EltVT == MVT::f64)
1843 case 8: return MVT::v8i1;
1844 case 16: return MVT::v16i1;
1846 if (Subtarget->hasBWI())
1847 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1849 case 32: return MVT::v32i1;
1850 case 64: return MVT::v64i1;
1854 if (VVT.is256BitVector() || VVT.is128BitVector()) {
1855 if (Subtarget->hasVLX())
1856 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1857 EltVT == MVT::f32 || EltVT == MVT::f64)
1859 case 2: return MVT::v2i1;
1860 case 4: return MVT::v4i1;
1861 case 8: return MVT::v8i1;
1863 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1864 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1866 case 8: return MVT::v8i1;
1867 case 16: return MVT::v16i1;
1868 case 32: return MVT::v32i1;
1873 return VT.changeVectorElementTypeToInteger();
1876 /// Helper for getByValTypeAlignment to determine
1877 /// the desired ByVal argument alignment.
1878 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1881 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1882 if (VTy->getBitWidth() == 128)
1884 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1885 unsigned EltAlign = 0;
1886 getMaxByValAlign(ATy->getElementType(), EltAlign);
1887 if (EltAlign > MaxAlign)
1888 MaxAlign = EltAlign;
1889 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1890 for (auto *EltTy : STy->elements()) {
1891 unsigned EltAlign = 0;
1892 getMaxByValAlign(EltTy, EltAlign);
1893 if (EltAlign > MaxAlign)
1894 MaxAlign = EltAlign;
1901 /// Return the desired alignment for ByVal aggregate
1902 /// function arguments in the caller parameter area. For X86, aggregates
1903 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1904 /// are at 4-byte boundaries.
1905 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1906 const DataLayout &DL) const {
1907 if (Subtarget->is64Bit()) {
1908 // Max of 8 and alignment of type.
1909 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1916 if (Subtarget->hasSSE1())
1917 getMaxByValAlign(Ty, Align);
1921 /// Returns the target specific optimal type for load
1922 /// and store operations as a result of memset, memcpy, and memmove
1923 /// lowering. If DstAlign is zero that means it's safe to destination
1924 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1925 /// means there isn't a need to check it against alignment requirement,
1926 /// probably because the source does not need to be loaded. If 'IsMemset' is
1927 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1928 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1929 /// source is constant so it does not need to be loaded.
1930 /// It returns EVT::Other if the type should be determined using generic
1931 /// target-independent logic.
1933 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1934 unsigned DstAlign, unsigned SrcAlign,
1935 bool IsMemset, bool ZeroMemset,
1937 MachineFunction &MF) const {
1938 const Function *F = MF.getFunction();
1939 if ((!IsMemset || ZeroMemset) &&
1940 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1942 (!Subtarget->isUnalignedMem16Slow() ||
1943 ((DstAlign == 0 || DstAlign >= 16) &&
1944 (SrcAlign == 0 || SrcAlign >= 16)))) {
1946 // FIXME: Check if unaligned 32-byte accesses are slow.
1947 if (Subtarget->hasInt256())
1949 if (Subtarget->hasFp256())
1952 if (Subtarget->hasSSE2())
1954 if (Subtarget->hasSSE1())
1956 } else if (!MemcpyStrSrc && Size >= 8 &&
1957 !Subtarget->is64Bit() &&
1958 Subtarget->hasSSE2()) {
1959 // Do not use f64 to lower memcpy if source is string constant. It's
1960 // better to use i32 to avoid the loads.
1964 // This is a compromise. If we reach here, unaligned accesses may be slow on
1965 // this target. However, creating smaller, aligned accesses could be even
1966 // slower and would certainly be a lot more code.
1967 if (Subtarget->is64Bit() && Size >= 8)
1972 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1974 return X86ScalarSSEf32;
1975 else if (VT == MVT::f64)
1976 return X86ScalarSSEf64;
1981 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1986 switch (VT.getSizeInBits()) {
1988 // 8-byte and under are always assumed to be fast.
1992 *Fast = !Subtarget->isUnalignedMem16Slow();
1995 *Fast = !Subtarget->isUnalignedMem32Slow();
1997 // TODO: What about AVX-512 (512-bit) accesses?
2000 // Misaligned accesses of any size are always allowed.
2004 /// Return the entry encoding for a jump table in the
2005 /// current function. The returned value is a member of the
2006 /// MachineJumpTableInfo::JTEntryKind enum.
2007 unsigned X86TargetLowering::getJumpTableEncoding() const {
2008 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2010 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2011 Subtarget->isPICStyleGOT())
2012 return MachineJumpTableInfo::EK_Custom32;
2014 // Otherwise, use the normal jump table encoding heuristics.
2015 return TargetLowering::getJumpTableEncoding();
2018 bool X86TargetLowering::useSoftFloat() const {
2019 return Subtarget->useSoftFloat();
2023 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2024 const MachineBasicBlock *MBB,
2025 unsigned uid,MCContext &Ctx) const{
2026 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2027 Subtarget->isPICStyleGOT());
2028 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2030 return MCSymbolRefExpr::create(MBB->getSymbol(),
2031 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2034 /// Returns relocation base for the given PIC jumptable.
2035 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2036 SelectionDAG &DAG) const {
2037 if (!Subtarget->is64Bit())
2038 // This doesn't have SDLoc associated with it, but is not really the
2039 // same as a Register.
2040 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2041 getPointerTy(DAG.getDataLayout()));
2045 /// This returns the relocation base for the given PIC jumptable,
2046 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2047 const MCExpr *X86TargetLowering::
2048 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2049 MCContext &Ctx) const {
2050 // X86-64 uses RIP relative addressing based on the jump table label.
2051 if (Subtarget->isPICStyleRIPRel())
2052 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2054 // Otherwise, the reference is relative to the PIC base.
2055 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2058 std::pair<const TargetRegisterClass *, uint8_t>
2059 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2061 const TargetRegisterClass *RRC = nullptr;
2063 switch (VT.SimpleTy) {
2065 return TargetLowering::findRepresentativeClass(TRI, VT);
2066 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2067 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2070 RRC = &X86::VR64RegClass;
2072 case MVT::f32: case MVT::f64:
2073 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2074 case MVT::v4f32: case MVT::v2f64:
2075 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2077 RRC = &X86::VR128RegClass;
2080 return std::make_pair(RRC, Cost);
2083 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2084 unsigned &Offset) const {
2085 if (!Subtarget->isTargetLinux())
2088 if (Subtarget->is64Bit()) {
2089 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2091 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2103 Value *X86TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
2104 if (!Subtarget->isTargetAndroid())
2105 return TargetLowering::getSafeStackPointerLocation(IRB);
2107 // Android provides a fixed TLS slot for the SafeStack pointer. See the
2108 // definition of TLS_SLOT_SAFESTACK in
2109 // https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2110 unsigned AddressSpace, Offset;
2111 if (Subtarget->is64Bit()) {
2112 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2114 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2124 return ConstantExpr::getIntToPtr(
2125 ConstantInt::get(Type::getInt32Ty(IRB.getContext()), Offset),
2126 Type::getInt8PtrTy(IRB.getContext())->getPointerTo(AddressSpace));
2129 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2130 unsigned DestAS) const {
2131 assert(SrcAS != DestAS && "Expected different address spaces!");
2133 return SrcAS < 256 && DestAS < 256;
2136 //===----------------------------------------------------------------------===//
2137 // Return Value Calling Convention Implementation
2138 //===----------------------------------------------------------------------===//
2140 #include "X86GenCallingConv.inc"
2142 bool X86TargetLowering::CanLowerReturn(
2143 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2144 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2145 SmallVector<CCValAssign, 16> RVLocs;
2146 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2147 return CCInfo.CheckReturn(Outs, RetCC_X86);
2150 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2151 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2156 X86TargetLowering::LowerReturn(SDValue Chain,
2157 CallingConv::ID CallConv, bool isVarArg,
2158 const SmallVectorImpl<ISD::OutputArg> &Outs,
2159 const SmallVectorImpl<SDValue> &OutVals,
2160 SDLoc dl, SelectionDAG &DAG) const {
2161 MachineFunction &MF = DAG.getMachineFunction();
2162 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2164 SmallVector<CCValAssign, 16> RVLocs;
2165 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2166 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2169 SmallVector<SDValue, 6> RetOps;
2170 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2171 // Operand #1 = Bytes To Pop
2172 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2175 // Copy the result values into the output registers.
2176 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2177 CCValAssign &VA = RVLocs[i];
2178 assert(VA.isRegLoc() && "Can only return in registers!");
2179 SDValue ValToCopy = OutVals[i];
2180 EVT ValVT = ValToCopy.getValueType();
2182 // Promote values to the appropriate types.
2183 if (VA.getLocInfo() == CCValAssign::SExt)
2184 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2185 else if (VA.getLocInfo() == CCValAssign::ZExt)
2186 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2187 else if (VA.getLocInfo() == CCValAssign::AExt) {
2188 if (ValVT.isVector() && ValVT.getVectorElementType() == MVT::i1)
2189 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2191 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2193 else if (VA.getLocInfo() == CCValAssign::BCvt)
2194 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2196 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2197 "Unexpected FP-extend for return value.");
2199 // If this is x86-64, and we disabled SSE, we can't return FP values,
2200 // or SSE or MMX vectors.
2201 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2202 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2203 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2204 report_fatal_error("SSE register return with SSE disabled");
2206 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2207 // llvm-gcc has never done it right and no one has noticed, so this
2208 // should be OK for now.
2209 if (ValVT == MVT::f64 &&
2210 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2211 report_fatal_error("SSE2 register return with SSE2 disabled");
2213 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2214 // the RET instruction and handled by the FP Stackifier.
2215 if (VA.getLocReg() == X86::FP0 ||
2216 VA.getLocReg() == X86::FP1) {
2217 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2218 // change the value to the FP stack register class.
2219 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2220 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2221 RetOps.push_back(ValToCopy);
2222 // Don't emit a copytoreg.
2226 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2227 // which is returned in RAX / RDX.
2228 if (Subtarget->is64Bit()) {
2229 if (ValVT == MVT::x86mmx) {
2230 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2231 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2232 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2234 // If we don't have SSE2 available, convert to v4f32 so the generated
2235 // register is legal.
2236 if (!Subtarget->hasSSE2())
2237 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2242 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2243 Flag = Chain.getValue(1);
2244 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2247 // All x86 ABIs require that for returning structs by value we copy
2248 // the sret argument into %rax/%eax (depending on ABI) for the return.
2249 // We saved the argument into a virtual register in the entry block,
2250 // so now we copy the value out and into %rax/%eax.
2252 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2253 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2254 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2255 // either case FuncInfo->setSRetReturnReg() will have been called.
2256 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2257 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2258 getPointerTy(MF.getDataLayout()));
2261 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2262 X86::RAX : X86::EAX;
2263 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2264 Flag = Chain.getValue(1);
2266 // RAX/EAX now acts like a return value.
2268 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2271 RetOps[0] = Chain; // Update chain.
2273 // Add the flag if we have it.
2275 RetOps.push_back(Flag);
2277 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2280 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2281 if (N->getNumValues() != 1)
2283 if (!N->hasNUsesOfValue(1, 0))
2286 SDValue TCChain = Chain;
2287 SDNode *Copy = *N->use_begin();
2288 if (Copy->getOpcode() == ISD::CopyToReg) {
2289 // If the copy has a glue operand, we conservatively assume it isn't safe to
2290 // perform a tail call.
2291 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2293 TCChain = Copy->getOperand(0);
2294 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2297 bool HasRet = false;
2298 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2300 if (UI->getOpcode() != X86ISD::RET_FLAG)
2302 // If we are returning more than one value, we can definitely
2303 // not make a tail call see PR19530
2304 if (UI->getNumOperands() > 4)
2306 if (UI->getNumOperands() == 4 &&
2307 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2320 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2321 ISD::NodeType ExtendKind) const {
2323 // TODO: Is this also valid on 32-bit?
2324 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2325 ReturnMVT = MVT::i8;
2327 ReturnMVT = MVT::i32;
2329 EVT MinVT = getRegisterType(Context, ReturnMVT);
2330 return VT.bitsLT(MinVT) ? MinVT : VT;
2333 /// Lower the result values of a call into the
2334 /// appropriate copies out of appropriate physical registers.
2337 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2338 CallingConv::ID CallConv, bool isVarArg,
2339 const SmallVectorImpl<ISD::InputArg> &Ins,
2340 SDLoc dl, SelectionDAG &DAG,
2341 SmallVectorImpl<SDValue> &InVals) const {
2343 // Assign locations to each value returned by this call.
2344 SmallVector<CCValAssign, 16> RVLocs;
2345 bool Is64Bit = Subtarget->is64Bit();
2346 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2348 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2350 // Copy all of the result registers out of their specified physreg.
2351 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2352 CCValAssign &VA = RVLocs[i];
2353 EVT CopyVT = VA.getLocVT();
2355 // If this is x86-64, and we disabled SSE, we can't return FP values
2356 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2357 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2358 report_fatal_error("SSE register return with SSE disabled");
2361 // If we prefer to use the value in xmm registers, copy it out as f80 and
2362 // use a truncate to move it from fp stack reg to xmm reg.
2363 bool RoundAfterCopy = false;
2364 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2365 isScalarFPTypeInSSEReg(VA.getValVT())) {
2367 RoundAfterCopy = (CopyVT != VA.getLocVT());
2370 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2371 CopyVT, InFlag).getValue(1);
2372 SDValue Val = Chain.getValue(0);
2375 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2376 // This truncation won't change the value.
2377 DAG.getIntPtrConstant(1, dl));
2379 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2380 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2382 InFlag = Chain.getValue(2);
2383 InVals.push_back(Val);
2389 //===----------------------------------------------------------------------===//
2390 // C & StdCall & Fast Calling Convention implementation
2391 //===----------------------------------------------------------------------===//
2392 // StdCall calling convention seems to be standard for many Windows' API
2393 // routines and around. It differs from C calling convention just a little:
2394 // callee should clean up the stack, not caller. Symbols should be also
2395 // decorated in some fancy way :) It doesn't support any vector arguments.
2396 // For info on fast calling convention see Fast Calling Convention (tail call)
2397 // implementation LowerX86_32FastCCCallTo.
2399 /// CallIsStructReturn - Determines whether a call uses struct return
2401 enum StructReturnType {
2406 static StructReturnType
2407 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2409 return NotStructReturn;
2411 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2412 if (!Flags.isSRet())
2413 return NotStructReturn;
2414 if (Flags.isInReg())
2415 return RegStructReturn;
2416 return StackStructReturn;
2419 /// Determines whether a function uses struct return semantics.
2420 static StructReturnType
2421 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2423 return NotStructReturn;
2425 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2426 if (!Flags.isSRet())
2427 return NotStructReturn;
2428 if (Flags.isInReg())
2429 return RegStructReturn;
2430 return StackStructReturn;
2433 /// Make a copy of an aggregate at address specified by "Src" to address
2434 /// "Dst" with size and alignment information specified by the specific
2435 /// parameter attribute. The copy will be passed as a byval function parameter.
2437 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2438 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2440 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2442 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2443 /*isVolatile*/false, /*AlwaysInline=*/true,
2444 /*isTailCall*/false,
2445 MachinePointerInfo(), MachinePointerInfo());
2448 /// Return true if the calling convention is one that we can guarantee TCO for.
2449 static bool canGuaranteeTCO(CallingConv::ID CC) {
2450 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2451 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2454 /// Return true if we might ever do TCO for calls with this calling convention.
2455 static bool mayTailCallThisCC(CallingConv::ID CC) {
2457 // C calling conventions:
2458 case CallingConv::C:
2459 case CallingConv::X86_64_Win64:
2460 case CallingConv::X86_64_SysV:
2461 // Callee pop conventions:
2462 case CallingConv::X86_ThisCall:
2463 case CallingConv::X86_StdCall:
2464 case CallingConv::X86_VectorCall:
2465 case CallingConv::X86_FastCall:
2468 return canGuaranteeTCO(CC);
2472 /// Return true if the function is being made into a tailcall target by
2473 /// changing its ABI.
2474 static bool shouldGuaranteeTCO(CallingConv::ID CC, bool GuaranteedTailCallOpt) {
2475 return GuaranteedTailCallOpt && canGuaranteeTCO(CC);
2478 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2480 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2481 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2485 CallingConv::ID CalleeCC = CS.getCallingConv();
2486 if (!mayTailCallThisCC(CalleeCC))
2493 X86TargetLowering::LowerMemArgument(SDValue Chain,
2494 CallingConv::ID CallConv,
2495 const SmallVectorImpl<ISD::InputArg> &Ins,
2496 SDLoc dl, SelectionDAG &DAG,
2497 const CCValAssign &VA,
2498 MachineFrameInfo *MFI,
2500 // Create the nodes corresponding to a load from this parameter slot.
2501 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2502 bool AlwaysUseMutable = shouldGuaranteeTCO(
2503 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2504 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2507 // If value is passed by pointer we have address passed instead of the value
2509 bool ExtendedInMem = VA.isExtInLoc() &&
2510 VA.getValVT().getScalarType() == MVT::i1;
2512 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2513 ValVT = VA.getLocVT();
2515 ValVT = VA.getValVT();
2517 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2518 // changed with more analysis.
2519 // In case of tail call optimization mark all arguments mutable. Since they
2520 // could be overwritten by lowering of arguments in case of a tail call.
2521 if (Flags.isByVal()) {
2522 unsigned Bytes = Flags.getByValSize();
2523 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2524 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2525 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2527 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2528 VA.getLocMemOffset(), isImmutable);
2529 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2530 SDValue Val = DAG.getLoad(
2531 ValVT, dl, Chain, FIN,
2532 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2534 return ExtendedInMem ?
2535 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2539 // FIXME: Get this from tablegen.
2540 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2541 const X86Subtarget *Subtarget) {
2542 assert(Subtarget->is64Bit());
2544 if (Subtarget->isCallingConvWin64(CallConv)) {
2545 static const MCPhysReg GPR64ArgRegsWin64[] = {
2546 X86::RCX, X86::RDX, X86::R8, X86::R9
2548 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2551 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2552 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2554 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2557 // FIXME: Get this from tablegen.
2558 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2559 CallingConv::ID CallConv,
2560 const X86Subtarget *Subtarget) {
2561 assert(Subtarget->is64Bit());
2562 if (Subtarget->isCallingConvWin64(CallConv)) {
2563 // The XMM registers which might contain var arg parameters are shadowed
2564 // in their paired GPR. So we only need to save the GPR to their home
2566 // TODO: __vectorcall will change this.
2570 const Function *Fn = MF.getFunction();
2571 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2572 bool isSoftFloat = Subtarget->useSoftFloat();
2573 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2574 "SSE register cannot be used when SSE is disabled!");
2575 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2576 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2580 static const MCPhysReg XMMArgRegs64Bit[] = {
2581 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2582 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2584 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2587 SDValue X86TargetLowering::LowerFormalArguments(
2588 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2589 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2590 SmallVectorImpl<SDValue> &InVals) const {
2591 MachineFunction &MF = DAG.getMachineFunction();
2592 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2593 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2595 const Function* Fn = MF.getFunction();
2596 if (Fn->hasExternalLinkage() &&
2597 Subtarget->isTargetCygMing() &&
2598 Fn->getName() == "main")
2599 FuncInfo->setForceFramePointer(true);
2601 MachineFrameInfo *MFI = MF.getFrameInfo();
2602 bool Is64Bit = Subtarget->is64Bit();
2603 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2605 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
2606 "Var args not supported with calling convention fastcc, ghc or hipe");
2608 // Assign locations to all of the incoming arguments.
2609 SmallVector<CCValAssign, 16> ArgLocs;
2610 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2612 // Allocate shadow area for Win64
2614 CCInfo.AllocateStack(32, 8);
2616 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2618 unsigned LastVal = ~0U;
2620 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2621 CCValAssign &VA = ArgLocs[i];
2622 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2624 assert(VA.getValNo() != LastVal &&
2625 "Don't support value assigned to multiple locs yet");
2627 LastVal = VA.getValNo();
2629 if (VA.isRegLoc()) {
2630 EVT RegVT = VA.getLocVT();
2631 const TargetRegisterClass *RC;
2632 if (RegVT == MVT::i32)
2633 RC = &X86::GR32RegClass;
2634 else if (Is64Bit && RegVT == MVT::i64)
2635 RC = &X86::GR64RegClass;
2636 else if (RegVT == MVT::f32)
2637 RC = &X86::FR32RegClass;
2638 else if (RegVT == MVT::f64)
2639 RC = &X86::FR64RegClass;
2640 else if (RegVT.is512BitVector())
2641 RC = &X86::VR512RegClass;
2642 else if (RegVT.is256BitVector())
2643 RC = &X86::VR256RegClass;
2644 else if (RegVT.is128BitVector())
2645 RC = &X86::VR128RegClass;
2646 else if (RegVT == MVT::x86mmx)
2647 RC = &X86::VR64RegClass;
2648 else if (RegVT == MVT::i1)
2649 RC = &X86::VK1RegClass;
2650 else if (RegVT == MVT::v8i1)
2651 RC = &X86::VK8RegClass;
2652 else if (RegVT == MVT::v16i1)
2653 RC = &X86::VK16RegClass;
2654 else if (RegVT == MVT::v32i1)
2655 RC = &X86::VK32RegClass;
2656 else if (RegVT == MVT::v64i1)
2657 RC = &X86::VK64RegClass;
2659 llvm_unreachable("Unknown argument type!");
2661 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2662 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2664 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2665 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2667 if (VA.getLocInfo() == CCValAssign::SExt)
2668 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2669 DAG.getValueType(VA.getValVT()));
2670 else if (VA.getLocInfo() == CCValAssign::ZExt)
2671 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2672 DAG.getValueType(VA.getValVT()));
2673 else if (VA.getLocInfo() == CCValAssign::BCvt)
2674 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2676 if (VA.isExtInLoc()) {
2677 // Handle MMX values passed in XMM regs.
2678 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2679 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2681 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2684 assert(VA.isMemLoc());
2685 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2688 // If value is passed via pointer - do a load.
2689 if (VA.getLocInfo() == CCValAssign::Indirect)
2690 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2691 MachinePointerInfo(), false, false, false, 0);
2693 InVals.push_back(ArgValue);
2696 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2697 // All x86 ABIs require that for returning structs by value we copy the
2698 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2699 // the argument into a virtual register so that we can access it from the
2701 if (Ins[i].Flags.isSRet()) {
2702 unsigned Reg = FuncInfo->getSRetReturnReg();
2704 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2705 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2706 FuncInfo->setSRetReturnReg(Reg);
2708 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2709 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2714 unsigned StackSize = CCInfo.getNextStackOffset();
2715 // Align stack specially for tail calls.
2716 if (shouldGuaranteeTCO(CallConv,
2717 MF.getTarget().Options.GuaranteedTailCallOpt))
2718 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2720 // If the function takes variable number of arguments, make a frame index for
2721 // the start of the first vararg value... for expansion of llvm.va_start. We
2722 // can skip this if there are no va_start calls.
2723 if (MFI->hasVAStart() &&
2724 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2725 CallConv != CallingConv::X86_ThisCall))) {
2726 FuncInfo->setVarArgsFrameIndex(
2727 MFI->CreateFixedObject(1, StackSize, true));
2730 // Figure out if XMM registers are in use.
2731 assert(!(Subtarget->useSoftFloat() &&
2732 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2733 "SSE register cannot be used when SSE is disabled!");
2735 // 64-bit calling conventions support varargs and register parameters, so we
2736 // have to do extra work to spill them in the prologue.
2737 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2738 // Find the first unallocated argument registers.
2739 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2740 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2741 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2742 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2743 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2744 "SSE register cannot be used when SSE is disabled!");
2746 // Gather all the live in physical registers.
2747 SmallVector<SDValue, 6> LiveGPRs;
2748 SmallVector<SDValue, 8> LiveXMMRegs;
2750 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2751 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2753 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2755 if (!ArgXMMs.empty()) {
2756 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2757 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2758 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2759 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2760 LiveXMMRegs.push_back(
2761 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2766 // Get to the caller-allocated home save location. Add 8 to account
2767 // for the return address.
2768 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2769 FuncInfo->setRegSaveFrameIndex(
2770 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2771 // Fixup to set vararg frame on shadow area (4 x i64).
2773 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2775 // For X86-64, if there are vararg parameters that are passed via
2776 // registers, then we must store them to their spots on the stack so
2777 // they may be loaded by deferencing the result of va_next.
2778 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2779 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2780 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2781 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2784 // Store the integer parameter registers.
2785 SmallVector<SDValue, 8> MemOps;
2786 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2787 getPointerTy(DAG.getDataLayout()));
2788 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2789 for (SDValue Val : LiveGPRs) {
2790 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2791 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2793 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2794 MachinePointerInfo::getFixedStack(
2795 DAG.getMachineFunction(),
2796 FuncInfo->getRegSaveFrameIndex(), Offset),
2798 MemOps.push_back(Store);
2802 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2803 // Now store the XMM (fp + vector) parameter registers.
2804 SmallVector<SDValue, 12> SaveXMMOps;
2805 SaveXMMOps.push_back(Chain);
2806 SaveXMMOps.push_back(ALVal);
2807 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2808 FuncInfo->getRegSaveFrameIndex(), dl));
2809 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2810 FuncInfo->getVarArgsFPOffset(), dl));
2811 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2813 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2814 MVT::Other, SaveXMMOps));
2817 if (!MemOps.empty())
2818 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2821 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2822 // Find the largest legal vector type.
2823 MVT VecVT = MVT::Other;
2824 // FIXME: Only some x86_32 calling conventions support AVX512.
2825 if (Subtarget->hasAVX512() &&
2826 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2827 CallConv == CallingConv::Intel_OCL_BI)))
2828 VecVT = MVT::v16f32;
2829 else if (Subtarget->hasAVX())
2831 else if (Subtarget->hasSSE2())
2834 // We forward some GPRs and some vector types.
2835 SmallVector<MVT, 2> RegParmTypes;
2836 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2837 RegParmTypes.push_back(IntVT);
2838 if (VecVT != MVT::Other)
2839 RegParmTypes.push_back(VecVT);
2841 // Compute the set of forwarded registers. The rest are scratch.
2842 SmallVectorImpl<ForwardedRegister> &Forwards =
2843 FuncInfo->getForwardedMustTailRegParms();
2844 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2846 // Conservatively forward AL on x86_64, since it might be used for varargs.
2847 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2848 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2849 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2852 // Copy all forwards from physical to virtual registers.
2853 for (ForwardedRegister &F : Forwards) {
2854 // FIXME: Can we use a less constrained schedule?
2855 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2856 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2857 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2861 // Some CCs need callee pop.
2862 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2863 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2864 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2866 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2867 // If this is an sret function, the return should pop the hidden pointer.
2868 if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
2869 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2870 argsAreStructReturn(Ins) == StackStructReturn)
2871 FuncInfo->setBytesToPopOnReturn(4);
2875 // RegSaveFrameIndex is X86-64 only.
2876 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2877 if (CallConv == CallingConv::X86_FastCall ||
2878 CallConv == CallingConv::X86_ThisCall)
2879 // fastcc functions can't have varargs.
2880 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2883 FuncInfo->setArgumentStackSize(StackSize);
2885 if (WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo()) {
2886 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
2887 if (Personality == EHPersonality::CoreCLR) {
2889 // TODO: Add a mechanism to frame lowering that will allow us to indicate
2890 // that we'd prefer this slot be allocated towards the bottom of the frame
2891 // (i.e. near the stack pointer after allocating the frame). Every
2892 // funclet needs a copy of this slot in its (mostly empty) frame, and the
2893 // offset from the bottom of this and each funclet's frame must be the
2894 // same, so the size of funclets' (mostly empty) frames is dictated by
2895 // how far this slot is from the bottom (since they allocate just enough
2896 // space to accomodate holding this slot at the correct offset).
2897 int PSPSymFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2898 EHInfo->PSPSymFrameIdx = PSPSymFI;
2906 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2907 SDValue StackPtr, SDValue Arg,
2908 SDLoc dl, SelectionDAG &DAG,
2909 const CCValAssign &VA,
2910 ISD::ArgFlagsTy Flags) const {
2911 unsigned LocMemOffset = VA.getLocMemOffset();
2912 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2913 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2915 if (Flags.isByVal())
2916 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2918 return DAG.getStore(
2919 Chain, dl, Arg, PtrOff,
2920 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2924 /// Emit a load of return address if tail call
2925 /// optimization is performed and it is required.
2927 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2928 SDValue &OutRetAddr, SDValue Chain,
2929 bool IsTailCall, bool Is64Bit,
2930 int FPDiff, SDLoc dl) const {
2931 // Adjust the Return address stack slot.
2932 EVT VT = getPointerTy(DAG.getDataLayout());
2933 OutRetAddr = getReturnAddressFrameIndex(DAG);
2935 // Load the "old" Return address.
2936 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2937 false, false, false, 0);
2938 return SDValue(OutRetAddr.getNode(), 1);
2941 /// Emit a store of the return address if tail call
2942 /// optimization is performed and it is required (FPDiff!=0).
2943 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2944 SDValue Chain, SDValue RetAddrFrIdx,
2945 EVT PtrVT, unsigned SlotSize,
2946 int FPDiff, SDLoc dl) {
2947 // Store the return address to the appropriate stack slot.
2948 if (!FPDiff) return Chain;
2949 // Calculate the new stack slot for the return address.
2950 int NewReturnAddrFI =
2951 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2953 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2954 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2955 MachinePointerInfo::getFixedStack(
2956 DAG.getMachineFunction(), NewReturnAddrFI),
2961 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2962 /// operation of specified width.
2963 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
2965 unsigned NumElems = VT.getVectorNumElements();
2966 SmallVector<int, 8> Mask;
2967 Mask.push_back(NumElems);
2968 for (unsigned i = 1; i != NumElems; ++i)
2970 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2974 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2975 SmallVectorImpl<SDValue> &InVals) const {
2976 SelectionDAG &DAG = CLI.DAG;
2978 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2979 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2980 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2981 SDValue Chain = CLI.Chain;
2982 SDValue Callee = CLI.Callee;
2983 CallingConv::ID CallConv = CLI.CallConv;
2984 bool &isTailCall = CLI.IsTailCall;
2985 bool isVarArg = CLI.IsVarArg;
2987 MachineFunction &MF = DAG.getMachineFunction();
2988 bool Is64Bit = Subtarget->is64Bit();
2989 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2990 StructReturnType SR = callIsStructReturn(Outs);
2991 bool IsSibcall = false;
2992 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2993 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2995 if (Attr.getValueAsString() == "true")
2998 if (Subtarget->isPICStyleGOT() &&
2999 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3000 // If we are using a GOT, disable tail calls to external symbols with
3001 // default visibility. Tail calling such a symbol requires using a GOT
3002 // relocation, which forces early binding of the symbol. This breaks code
3003 // that require lazy function symbol resolution. Using musttail or
3004 // GuaranteedTailCallOpt will override this.
3005 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3006 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3007 G->getGlobal()->hasDefaultVisibility()))
3011 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3013 // Force this to be a tail call. The verifier rules are enough to ensure
3014 // that we can lower this successfully without moving the return address
3017 } else if (isTailCall) {
3018 // Check if it's really possible to do a tail call.
3019 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3020 isVarArg, SR != NotStructReturn,
3021 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3022 Outs, OutVals, Ins, DAG);
3024 // Sibcalls are automatically detected tailcalls which do not require
3026 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3033 assert(!(isVarArg && canGuaranteeTCO(CallConv)) &&
3034 "Var args not supported with calling convention fastcc, ghc or hipe");
3036 // Analyze operands of the call, assigning locations to each operand.
3037 SmallVector<CCValAssign, 16> ArgLocs;
3038 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3040 // Allocate shadow area for Win64
3042 CCInfo.AllocateStack(32, 8);
3044 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3046 // Get a count of how many bytes are to be pushed on the stack.
3047 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3049 // This is a sibcall. The memory operands are available in caller's
3050 // own caller's stack.
3052 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3053 canGuaranteeTCO(CallConv))
3054 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3057 if (isTailCall && !IsSibcall && !IsMustTail) {
3058 // Lower arguments at fp - stackoffset + fpdiff.
3059 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3061 FPDiff = NumBytesCallerPushed - NumBytes;
3063 // Set the delta of movement of the returnaddr stackslot.
3064 // But only set if delta is greater than previous delta.
3065 if (FPDiff < X86Info->getTCReturnAddrDelta())
3066 X86Info->setTCReturnAddrDelta(FPDiff);
3069 unsigned NumBytesToPush = NumBytes;
3070 unsigned NumBytesToPop = NumBytes;
3072 // If we have an inalloca argument, all stack space has already been allocated
3073 // for us and be right at the top of the stack. We don't support multiple
3074 // arguments passed in memory when using inalloca.
3075 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3077 if (!ArgLocs.back().isMemLoc())
3078 report_fatal_error("cannot use inalloca attribute on a register "
3080 if (ArgLocs.back().getLocMemOffset() != 0)
3081 report_fatal_error("any parameter with the inalloca attribute must be "
3082 "the only memory argument");
3086 Chain = DAG.getCALLSEQ_START(
3087 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3089 SDValue RetAddrFrIdx;
3090 // Load return address for tail calls.
3091 if (isTailCall && FPDiff)
3092 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3093 Is64Bit, FPDiff, dl);
3095 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3096 SmallVector<SDValue, 8> MemOpChains;
3099 // Walk the register/memloc assignments, inserting copies/loads. In the case
3100 // of tail call optimization arguments are handle later.
3101 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3102 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3103 // Skip inalloca arguments, they have already been written.
3104 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3105 if (Flags.isInAlloca())
3108 CCValAssign &VA = ArgLocs[i];
3109 EVT RegVT = VA.getLocVT();
3110 SDValue Arg = OutVals[i];
3111 bool isByVal = Flags.isByVal();
3113 // Promote the value if needed.
3114 switch (VA.getLocInfo()) {
3115 default: llvm_unreachable("Unknown loc info!");
3116 case CCValAssign::Full: break;
3117 case CCValAssign::SExt:
3118 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3120 case CCValAssign::ZExt:
3121 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3123 case CCValAssign::AExt:
3124 if (Arg.getValueType().isVector() &&
3125 Arg.getValueType().getVectorElementType() == MVT::i1)
3126 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3127 else if (RegVT.is128BitVector()) {
3128 // Special case: passing MMX values in XMM registers.
3129 Arg = DAG.getBitcast(MVT::i64, Arg);
3130 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3131 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3133 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3135 case CCValAssign::BCvt:
3136 Arg = DAG.getBitcast(RegVT, Arg);
3138 case CCValAssign::Indirect: {
3139 // Store the argument.
3140 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3141 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3142 Chain = DAG.getStore(
3143 Chain, dl, Arg, SpillSlot,
3144 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3151 if (VA.isRegLoc()) {
3152 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3153 if (isVarArg && IsWin64) {
3154 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3155 // shadow reg if callee is a varargs function.
3156 unsigned ShadowReg = 0;
3157 switch (VA.getLocReg()) {
3158 case X86::XMM0: ShadowReg = X86::RCX; break;
3159 case X86::XMM1: ShadowReg = X86::RDX; break;
3160 case X86::XMM2: ShadowReg = X86::R8; break;
3161 case X86::XMM3: ShadowReg = X86::R9; break;
3164 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3166 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3167 assert(VA.isMemLoc());
3168 if (!StackPtr.getNode())
3169 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3170 getPointerTy(DAG.getDataLayout()));
3171 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3172 dl, DAG, VA, Flags));
3176 if (!MemOpChains.empty())
3177 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3179 if (Subtarget->isPICStyleGOT()) {
3180 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3183 RegsToPass.push_back(std::make_pair(
3184 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3185 getPointerTy(DAG.getDataLayout()))));
3187 // If we are tail calling and generating PIC/GOT style code load the
3188 // address of the callee into ECX. The value in ecx is used as target of
3189 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3190 // for tail calls on PIC/GOT architectures. Normally we would just put the
3191 // address of GOT into ebx and then call target@PLT. But for tail calls
3192 // ebx would be restored (since ebx is callee saved) before jumping to the
3195 // Note: The actual moving to ECX is done further down.
3196 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3197 if (G && !G->getGlobal()->hasLocalLinkage() &&
3198 G->getGlobal()->hasDefaultVisibility())
3199 Callee = LowerGlobalAddress(Callee, DAG);
3200 else if (isa<ExternalSymbolSDNode>(Callee))
3201 Callee = LowerExternalSymbol(Callee, DAG);
3205 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3206 // From AMD64 ABI document:
3207 // For calls that may call functions that use varargs or stdargs
3208 // (prototype-less calls or calls to functions containing ellipsis (...) in
3209 // the declaration) %al is used as hidden argument to specify the number
3210 // of SSE registers used. The contents of %al do not need to match exactly
3211 // the number of registers, but must be an ubound on the number of SSE
3212 // registers used and is in the range 0 - 8 inclusive.
3214 // Count the number of XMM registers allocated.
3215 static const MCPhysReg XMMArgRegs[] = {
3216 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3217 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3219 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3220 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3221 && "SSE registers cannot be used when SSE is disabled");
3223 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3224 DAG.getConstant(NumXMMRegs, dl,
3228 if (isVarArg && IsMustTail) {
3229 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3230 for (const auto &F : Forwards) {
3231 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3232 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3236 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3237 // don't need this because the eligibility check rejects calls that require
3238 // shuffling arguments passed in memory.
3239 if (!IsSibcall && isTailCall) {
3240 // Force all the incoming stack arguments to be loaded from the stack
3241 // before any new outgoing arguments are stored to the stack, because the
3242 // outgoing stack slots may alias the incoming argument stack slots, and
3243 // the alias isn't otherwise explicit. This is slightly more conservative
3244 // than necessary, because it means that each store effectively depends
3245 // on every argument instead of just those arguments it would clobber.
3246 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3248 SmallVector<SDValue, 8> MemOpChains2;
3251 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3252 CCValAssign &VA = ArgLocs[i];
3255 assert(VA.isMemLoc());
3256 SDValue Arg = OutVals[i];
3257 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3258 // Skip inalloca arguments. They don't require any work.
3259 if (Flags.isInAlloca())
3261 // Create frame index.
3262 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3263 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3264 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3265 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3267 if (Flags.isByVal()) {
3268 // Copy relative to framepointer.
3269 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3270 if (!StackPtr.getNode())
3271 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3272 getPointerTy(DAG.getDataLayout()));
3273 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3276 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3280 // Store relative to framepointer.
3281 MemOpChains2.push_back(DAG.getStore(
3282 ArgChain, dl, Arg, FIN,
3283 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3288 if (!MemOpChains2.empty())
3289 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3291 // Store the return address to the appropriate stack slot.
3292 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3293 getPointerTy(DAG.getDataLayout()),
3294 RegInfo->getSlotSize(), FPDiff, dl);
3297 // Build a sequence of copy-to-reg nodes chained together with token chain
3298 // and flag operands which copy the outgoing args into registers.
3300 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3301 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3302 RegsToPass[i].second, InFlag);
3303 InFlag = Chain.getValue(1);
3306 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3307 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3308 // In the 64-bit large code model, we have to make all calls
3309 // through a register, since the call instruction's 32-bit
3310 // pc-relative offset may not be large enough to hold the whole
3312 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3313 // If the callee is a GlobalAddress node (quite common, every direct call
3314 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3316 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3318 // We should use extra load for direct calls to dllimported functions in
3320 const GlobalValue *GV = G->getGlobal();
3321 if (!GV->hasDLLImportStorageClass()) {
3322 unsigned char OpFlags = 0;
3323 bool ExtraLoad = false;
3324 unsigned WrapperKind = ISD::DELETED_NODE;
3326 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3327 // external symbols most go through the PLT in PIC mode. If the symbol
3328 // has hidden or protected visibility, or if it is static or local, then
3329 // we don't need to use the PLT - we can directly call it.
3330 if (Subtarget->isTargetELF() &&
3331 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3332 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3333 OpFlags = X86II::MO_PLT;
3334 } else if (Subtarget->isPICStyleStubAny() &&
3335 !GV->isStrongDefinitionForLinker() &&
3336 (!Subtarget->getTargetTriple().isMacOSX() ||
3337 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3338 // PC-relative references to external symbols should go through $stub,
3339 // unless we're building with the leopard linker or later, which
3340 // automatically synthesizes these stubs.
3341 OpFlags = X86II::MO_DARWIN_STUB;
3342 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3343 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3344 // If the function is marked as non-lazy, generate an indirect call
3345 // which loads from the GOT directly. This avoids runtime overhead
3346 // at the cost of eager binding (and one extra byte of encoding).
3347 OpFlags = X86II::MO_GOTPCREL;
3348 WrapperKind = X86ISD::WrapperRIP;
3352 Callee = DAG.getTargetGlobalAddress(
3353 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3355 // Add a wrapper if needed.
3356 if (WrapperKind != ISD::DELETED_NODE)
3357 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3358 getPointerTy(DAG.getDataLayout()), Callee);
3359 // Add extra indirection if needed.
3361 Callee = DAG.getLoad(
3362 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3363 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3366 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3367 unsigned char OpFlags = 0;
3369 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3370 // external symbols should go through the PLT.
3371 if (Subtarget->isTargetELF() &&
3372 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3373 OpFlags = X86II::MO_PLT;
3374 } else if (Subtarget->isPICStyleStubAny() &&
3375 (!Subtarget->getTargetTriple().isMacOSX() ||
3376 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3377 // PC-relative references to external symbols should go through $stub,
3378 // unless we're building with the leopard linker or later, which
3379 // automatically synthesizes these stubs.
3380 OpFlags = X86II::MO_DARWIN_STUB;
3383 Callee = DAG.getTargetExternalSymbol(
3384 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3385 } else if (Subtarget->isTarget64BitILP32() &&
3386 Callee->getValueType(0) == MVT::i32) {
3387 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3388 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3391 // Returns a chain & a flag for retval copy to use.
3392 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3393 SmallVector<SDValue, 8> Ops;
3395 if (!IsSibcall && isTailCall) {
3396 Chain = DAG.getCALLSEQ_END(Chain,
3397 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3398 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3399 InFlag = Chain.getValue(1);
3402 Ops.push_back(Chain);
3403 Ops.push_back(Callee);
3406 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3408 // Add argument registers to the end of the list so that they are known live
3410 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3411 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3412 RegsToPass[i].second.getValueType()));
3414 // Add a register mask operand representing the call-preserved registers.
3415 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3416 assert(Mask && "Missing call preserved mask for calling convention");
3418 // If this is an invoke in a 32-bit function using a funclet-based
3419 // personality, assume the function clobbers all registers. If an exception
3420 // is thrown, the runtime will not restore CSRs.
3421 // FIXME: Model this more precisely so that we can register allocate across
3422 // the normal edge and spill and fill across the exceptional edge.
3423 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3424 const Function *CallerFn = MF.getFunction();
3425 EHPersonality Pers =
3426 CallerFn->hasPersonalityFn()
3427 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3428 : EHPersonality::Unknown;
3429 if (isFuncletEHPersonality(Pers))
3430 Mask = RegInfo->getNoPreservedMask();
3433 Ops.push_back(DAG.getRegisterMask(Mask));
3435 if (InFlag.getNode())
3436 Ops.push_back(InFlag);
3440 //// If this is the first return lowered for this function, add the regs
3441 //// to the liveout set for the function.
3442 // This isn't right, although it's probably harmless on x86; liveouts
3443 // should be computed from returns not tail calls. Consider a void
3444 // function making a tail call to a function returning int.
3445 MF.getFrameInfo()->setHasTailCall();
3446 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3449 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3450 InFlag = Chain.getValue(1);
3452 // Create the CALLSEQ_END node.
3453 unsigned NumBytesForCalleeToPop;
3454 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3455 DAG.getTarget().Options.GuaranteedTailCallOpt))
3456 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3457 else if (!Is64Bit && !canGuaranteeTCO(CallConv) &&
3458 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3459 SR == StackStructReturn)
3460 // If this is a call to a struct-return function, the callee
3461 // pops the hidden struct pointer, so we have to push it back.
3462 // This is common for Darwin/X86, Linux & Mingw32 targets.
3463 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3464 NumBytesForCalleeToPop = 4;
3466 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3468 // Returns a flag for retval copy to use.
3470 Chain = DAG.getCALLSEQ_END(Chain,
3471 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3472 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3475 InFlag = Chain.getValue(1);
3478 // Handle result values, copying them out of physregs into vregs that we
3480 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3481 Ins, dl, DAG, InVals);
3484 //===----------------------------------------------------------------------===//
3485 // Fast Calling Convention (tail call) implementation
3486 //===----------------------------------------------------------------------===//
3488 // Like std call, callee cleans arguments, convention except that ECX is
3489 // reserved for storing the tail called function address. Only 2 registers are
3490 // free for argument passing (inreg). Tail call optimization is performed
3492 // * tailcallopt is enabled
3493 // * caller/callee are fastcc
3494 // On X86_64 architecture with GOT-style position independent code only local
3495 // (within module) calls are supported at the moment.
3496 // To keep the stack aligned according to platform abi the function
3497 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3498 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3499 // If a tail called function callee has more arguments than the caller the
3500 // caller needs to make sure that there is room to move the RETADDR to. This is
3501 // achieved by reserving an area the size of the argument delta right after the
3502 // original RETADDR, but before the saved framepointer or the spilled registers
3503 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3515 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3518 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3519 SelectionDAG& DAG) const {
3520 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3521 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3522 unsigned StackAlignment = TFI.getStackAlignment();
3523 uint64_t AlignMask = StackAlignment - 1;
3524 int64_t Offset = StackSize;
3525 unsigned SlotSize = RegInfo->getSlotSize();
3526 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3527 // Number smaller than 12 so just add the difference.
3528 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3530 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3531 Offset = ((~AlignMask) & Offset) + StackAlignment +
3532 (StackAlignment-SlotSize);
3537 /// Return true if the given stack call argument is already available in the
3538 /// same position (relatively) of the caller's incoming argument stack.
3540 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3541 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3542 const X86InstrInfo *TII) {
3543 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3545 if (Arg.getOpcode() == ISD::CopyFromReg) {
3546 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3547 if (!TargetRegisterInfo::isVirtualRegister(VR))
3549 MachineInstr *Def = MRI->getVRegDef(VR);
3552 if (!Flags.isByVal()) {
3553 if (!TII->isLoadFromStackSlot(Def, FI))
3556 unsigned Opcode = Def->getOpcode();
3557 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3558 Opcode == X86::LEA64_32r) &&
3559 Def->getOperand(1).isFI()) {
3560 FI = Def->getOperand(1).getIndex();
3561 Bytes = Flags.getByValSize();
3565 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3566 if (Flags.isByVal())
3567 // ByVal argument is passed in as a pointer but it's now being
3568 // dereferenced. e.g.
3569 // define @foo(%struct.X* %A) {
3570 // tail call @bar(%struct.X* byval %A)
3573 SDValue Ptr = Ld->getBasePtr();
3574 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3577 FI = FINode->getIndex();
3578 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3579 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3580 FI = FINode->getIndex();
3581 Bytes = Flags.getByValSize();
3585 assert(FI != INT_MAX);
3586 if (!MFI->isFixedObjectIndex(FI))
3588 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3591 /// Check whether the call is eligible for tail call optimization. Targets
3592 /// that want to do tail call optimization should implement this function.
3593 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3594 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3595 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3596 const SmallVectorImpl<ISD::OutputArg> &Outs,
3597 const SmallVectorImpl<SDValue> &OutVals,
3598 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3599 if (!mayTailCallThisCC(CalleeCC))
3602 // If -tailcallopt is specified, make fastcc functions tail-callable.
3603 MachineFunction &MF = DAG.getMachineFunction();
3604 const Function *CallerF = MF.getFunction();
3606 // If the function return type is x86_fp80 and the callee return type is not,
3607 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3608 // perform a tailcall optimization here.
3609 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3612 CallingConv::ID CallerCC = CallerF->getCallingConv();
3613 bool CCMatch = CallerCC == CalleeCC;
3614 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3615 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3617 // Win64 functions have extra shadow space for argument homing. Don't do the
3618 // sibcall if the caller and callee have mismatched expectations for this
3620 if (IsCalleeWin64 != IsCallerWin64)
3623 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3624 if (canGuaranteeTCO(CalleeCC) && CCMatch)
3629 // Look for obvious safe cases to perform tail call optimization that do not
3630 // require ABI changes. This is what gcc calls sibcall.
3632 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3633 // emit a special epilogue.
3634 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3635 if (RegInfo->needsStackRealignment(MF))
3638 // Also avoid sibcall optimization if either caller or callee uses struct
3639 // return semantics.
3640 if (isCalleeStructRet || isCallerStructRet)
3643 // Do not sibcall optimize vararg calls unless all arguments are passed via
3645 if (isVarArg && !Outs.empty()) {
3646 // Optimizing for varargs on Win64 is unlikely to be safe without
3647 // additional testing.
3648 if (IsCalleeWin64 || IsCallerWin64)
3651 SmallVector<CCValAssign, 16> ArgLocs;
3652 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3655 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3656 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3657 if (!ArgLocs[i].isRegLoc())
3661 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3662 // stack. Therefore, if it's not used by the call it is not safe to optimize
3663 // this into a sibcall.
3664 bool Unused = false;
3665 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3672 SmallVector<CCValAssign, 16> RVLocs;
3673 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3675 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3676 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3677 CCValAssign &VA = RVLocs[i];
3678 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3683 // If the calling conventions do not match, then we'd better make sure the
3684 // results are returned in the same way as what the caller expects.
3686 SmallVector<CCValAssign, 16> RVLocs1;
3687 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3689 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3691 SmallVector<CCValAssign, 16> RVLocs2;
3692 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3694 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3696 if (RVLocs1.size() != RVLocs2.size())
3698 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3699 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3701 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3703 if (RVLocs1[i].isRegLoc()) {
3704 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3707 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3713 unsigned StackArgsSize = 0;
3715 // If the callee takes no arguments then go on to check the results of the
3717 if (!Outs.empty()) {
3718 // Check if stack adjustment is needed. For now, do not do this if any
3719 // argument is passed on the stack.
3720 SmallVector<CCValAssign, 16> ArgLocs;
3721 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3724 // Allocate shadow area for Win64
3726 CCInfo.AllocateStack(32, 8);
3728 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3729 StackArgsSize = CCInfo.getNextStackOffset();
3731 if (CCInfo.getNextStackOffset()) {
3732 // Check if the arguments are already laid out in the right way as
3733 // the caller's fixed stack objects.
3734 MachineFrameInfo *MFI = MF.getFrameInfo();
3735 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3736 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3737 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3738 CCValAssign &VA = ArgLocs[i];
3739 SDValue Arg = OutVals[i];
3740 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3741 if (VA.getLocInfo() == CCValAssign::Indirect)
3743 if (!VA.isRegLoc()) {
3744 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3751 // If the tailcall address may be in a register, then make sure it's
3752 // possible to register allocate for it. In 32-bit, the call address can
3753 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3754 // callee-saved registers are restored. These happen to be the same
3755 // registers used to pass 'inreg' arguments so watch out for those.
3756 if (!Subtarget->is64Bit() &&
3757 ((!isa<GlobalAddressSDNode>(Callee) &&
3758 !isa<ExternalSymbolSDNode>(Callee)) ||
3759 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3760 unsigned NumInRegs = 0;
3761 // In PIC we need an extra register to formulate the address computation
3763 unsigned MaxInRegs =
3764 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3766 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3767 CCValAssign &VA = ArgLocs[i];
3770 unsigned Reg = VA.getLocReg();
3773 case X86::EAX: case X86::EDX: case X86::ECX:
3774 if (++NumInRegs == MaxInRegs)
3782 bool CalleeWillPop =
3783 X86::isCalleePop(CalleeCC, Subtarget->is64Bit(), isVarArg,
3784 MF.getTarget().Options.GuaranteedTailCallOpt);
3786 if (unsigned BytesToPop =
3787 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) {
3788 // If we have bytes to pop, the callee must pop them.
3789 bool CalleePopMatches = CalleeWillPop && BytesToPop == StackArgsSize;
3790 if (!CalleePopMatches)
3792 } else if (CalleeWillPop && StackArgsSize > 0) {
3793 // If we don't have bytes to pop, make sure the callee doesn't pop any.
3801 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3802 const TargetLibraryInfo *libInfo) const {
3803 return X86::createFastISel(funcInfo, libInfo);
3806 //===----------------------------------------------------------------------===//
3807 // Other Lowering Hooks
3808 //===----------------------------------------------------------------------===//
3810 static bool MayFoldLoad(SDValue Op) {
3811 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3814 static bool MayFoldIntoStore(SDValue Op) {
3815 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3818 static bool isTargetShuffle(unsigned Opcode) {
3820 default: return false;
3821 case X86ISD::BLENDI:
3822 case X86ISD::PSHUFB:
3823 case X86ISD::PSHUFD:
3824 case X86ISD::PSHUFHW:
3825 case X86ISD::PSHUFLW:
3827 case X86ISD::PALIGNR:
3828 case X86ISD::MOVLHPS:
3829 case X86ISD::MOVLHPD:
3830 case X86ISD::MOVHLPS:
3831 case X86ISD::MOVLPS:
3832 case X86ISD::MOVLPD:
3833 case X86ISD::MOVSHDUP:
3834 case X86ISD::MOVSLDUP:
3835 case X86ISD::MOVDDUP:
3838 case X86ISD::UNPCKL:
3839 case X86ISD::UNPCKH:
3840 case X86ISD::VPERMILPI:
3841 case X86ISD::VPERM2X128:
3842 case X86ISD::VPERMI:
3843 case X86ISD::VPERMV:
3844 case X86ISD::VPERMV3:
3849 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3850 SDValue V1, unsigned TargetMask,
3851 SelectionDAG &DAG) {
3853 default: llvm_unreachable("Unknown x86 shuffle node");
3854 case X86ISD::PSHUFD:
3855 case X86ISD::PSHUFHW:
3856 case X86ISD::PSHUFLW:
3857 case X86ISD::VPERMILPI:
3858 case X86ISD::VPERMI:
3859 return DAG.getNode(Opc, dl, VT, V1,
3860 DAG.getConstant(TargetMask, dl, MVT::i8));
3864 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, MVT VT,
3865 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3867 default: llvm_unreachable("Unknown x86 shuffle node");
3868 case X86ISD::MOVLHPS:
3869 case X86ISD::MOVLHPD:
3870 case X86ISD::MOVHLPS:
3871 case X86ISD::MOVLPS:
3872 case X86ISD::MOVLPD:
3875 case X86ISD::UNPCKL:
3876 case X86ISD::UNPCKH:
3877 return DAG.getNode(Opc, dl, VT, V1, V2);
3881 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3882 MachineFunction &MF = DAG.getMachineFunction();
3883 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3884 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3885 int ReturnAddrIndex = FuncInfo->getRAIndex();
3887 if (ReturnAddrIndex == 0) {
3888 // Set up a frame object for the return address.
3889 unsigned SlotSize = RegInfo->getSlotSize();
3890 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3893 FuncInfo->setRAIndex(ReturnAddrIndex);
3896 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3899 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3900 bool hasSymbolicDisplacement) {
3901 // Offset should fit into 32 bit immediate field.
3902 if (!isInt<32>(Offset))
3905 // If we don't have a symbolic displacement - we don't have any extra
3907 if (!hasSymbolicDisplacement)
3910 // FIXME: Some tweaks might be needed for medium code model.
3911 if (M != CodeModel::Small && M != CodeModel::Kernel)
3914 // For small code model we assume that latest object is 16MB before end of 31
3915 // bits boundary. We may also accept pretty large negative constants knowing
3916 // that all objects are in the positive half of address space.
3917 if (M == CodeModel::Small && Offset < 16*1024*1024)
3920 // For kernel code model we know that all object resist in the negative half
3921 // of 32bits address space. We may not accept negative offsets, since they may
3922 // be just off and we may accept pretty large positive ones.
3923 if (M == CodeModel::Kernel && Offset >= 0)
3929 /// Determines whether the callee is required to pop its own arguments.
3930 /// Callee pop is necessary to support tail calls.
3931 bool X86::isCalleePop(CallingConv::ID CallingConv,
3932 bool is64Bit, bool IsVarArg, bool GuaranteeTCO) {
3933 // If GuaranteeTCO is true, we force some calls to be callee pop so that we
3934 // can guarantee TCO.
3935 if (!IsVarArg && shouldGuaranteeTCO(CallingConv, GuaranteeTCO))
3938 switch (CallingConv) {
3941 case CallingConv::X86_StdCall:
3942 case CallingConv::X86_FastCall:
3943 case CallingConv::X86_ThisCall:
3944 case CallingConv::X86_VectorCall:
3949 /// \brief Return true if the condition is an unsigned comparison operation.
3950 static bool isX86CCUnsigned(unsigned X86CC) {
3952 default: llvm_unreachable("Invalid integer condition!");
3953 case X86::COND_E: return true;
3954 case X86::COND_G: return false;
3955 case X86::COND_GE: return false;
3956 case X86::COND_L: return false;
3957 case X86::COND_LE: return false;
3958 case X86::COND_NE: return true;
3959 case X86::COND_B: return true;
3960 case X86::COND_A: return true;
3961 case X86::COND_BE: return true;
3962 case X86::COND_AE: return true;
3966 static X86::CondCode TranslateIntegerX86CC(ISD::CondCode SetCCOpcode) {
3967 switch (SetCCOpcode) {
3968 default: llvm_unreachable("Invalid integer condition!");
3969 case ISD::SETEQ: return X86::COND_E;
3970 case ISD::SETGT: return X86::COND_G;
3971 case ISD::SETGE: return X86::COND_GE;
3972 case ISD::SETLT: return X86::COND_L;
3973 case ISD::SETLE: return X86::COND_LE;
3974 case ISD::SETNE: return X86::COND_NE;
3975 case ISD::SETULT: return X86::COND_B;
3976 case ISD::SETUGT: return X86::COND_A;
3977 case ISD::SETULE: return X86::COND_BE;
3978 case ISD::SETUGE: return X86::COND_AE;
3982 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3983 /// condition code, returning the condition code and the LHS/RHS of the
3984 /// comparison to make.
3985 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3986 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3988 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3989 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3990 // X > -1 -> X == 0, jump !sign.
3991 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3992 return X86::COND_NS;
3994 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3995 // X < 0 -> X == 0, jump on sign.
3998 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
4000 RHS = DAG.getConstant(0, DL, RHS.getValueType());
4001 return X86::COND_LE;
4005 return TranslateIntegerX86CC(SetCCOpcode);
4008 // First determine if it is required or is profitable to flip the operands.
4010 // If LHS is a foldable load, but RHS is not, flip the condition.
4011 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4012 !ISD::isNON_EXTLoad(RHS.getNode())) {
4013 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4014 std::swap(LHS, RHS);
4017 switch (SetCCOpcode) {
4023 std::swap(LHS, RHS);
4027 // On a floating point condition, the flags are set as follows:
4029 // 0 | 0 | 0 | X > Y
4030 // 0 | 0 | 1 | X < Y
4031 // 1 | 0 | 0 | X == Y
4032 // 1 | 1 | 1 | unordered
4033 switch (SetCCOpcode) {
4034 default: llvm_unreachable("Condcode should be pre-legalized away");
4036 case ISD::SETEQ: return X86::COND_E;
4037 case ISD::SETOLT: // flipped
4039 case ISD::SETGT: return X86::COND_A;
4040 case ISD::SETOLE: // flipped
4042 case ISD::SETGE: return X86::COND_AE;
4043 case ISD::SETUGT: // flipped
4045 case ISD::SETLT: return X86::COND_B;
4046 case ISD::SETUGE: // flipped
4048 case ISD::SETLE: return X86::COND_BE;
4050 case ISD::SETNE: return X86::COND_NE;
4051 case ISD::SETUO: return X86::COND_P;
4052 case ISD::SETO: return X86::COND_NP;
4054 case ISD::SETUNE: return X86::COND_INVALID;
4058 /// Is there a floating point cmov for the specific X86 condition code?
4059 /// Current x86 isa includes the following FP cmov instructions:
4060 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4061 static bool hasFPCMov(unsigned X86CC) {
4077 /// Returns true if the target can instruction select the
4078 /// specified FP immediate natively. If false, the legalizer will
4079 /// materialize the FP immediate as a load from a constant pool.
4080 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4081 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4082 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4088 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4089 ISD::LoadExtType ExtTy,
4091 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4092 // relocation target a movq or addq instruction: don't let the load shrink.
4093 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4094 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4095 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4096 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4100 /// \brief Returns true if it is beneficial to convert a load of a constant
4101 /// to just the constant itself.
4102 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4104 assert(Ty->isIntegerTy());
4106 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4107 if (BitSize == 0 || BitSize > 64)
4112 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4113 unsigned Index) const {
4114 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4117 return (Index == 0 || Index == ResVT.getVectorNumElements());
4120 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4121 // Speculate cttz only if we can directly use TZCNT.
4122 return Subtarget->hasBMI();
4125 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4126 // Speculate ctlz only if we can directly use LZCNT.
4127 return Subtarget->hasLZCNT();
4130 /// Return true if every element in Mask, beginning
4131 /// from position Pos and ending in Pos+Size is undef.
4132 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4133 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4139 /// Return true if Val is undef or if its value falls within the
4140 /// specified range (L, H].
4141 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4142 return (Val < 0) || (Val >= Low && Val < Hi);
4145 /// Val is either less than zero (undef) or equal to the specified value.
4146 static bool isUndefOrEqual(int Val, int CmpVal) {
4147 return (Val < 0 || Val == CmpVal);
4150 /// Return true if every element in Mask, beginning
4151 /// from position Pos and ending in Pos+Size, falls within the specified
4152 /// sequential range (Low, Low+Size]. or is undef.
4153 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4154 unsigned Pos, unsigned Size, int Low) {
4155 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4156 if (!isUndefOrEqual(Mask[i], Low))
4161 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4162 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4163 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4164 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4165 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4168 // The index should be aligned on a vecWidth-bit boundary.
4170 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4172 MVT VT = N->getSimpleValueType(0);
4173 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4174 bool Result = (Index * ElSize) % vecWidth == 0;
4179 /// Return true if the specified INSERT_SUBVECTOR
4180 /// operand specifies a subvector insert that is suitable for input to
4181 /// insertion of 128 or 256-bit subvectors
4182 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4183 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4184 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4186 // The index should be aligned on a vecWidth-bit boundary.
4188 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4190 MVT VT = N->getSimpleValueType(0);
4191 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4192 bool Result = (Index * ElSize) % vecWidth == 0;
4197 bool X86::isVINSERT128Index(SDNode *N) {
4198 return isVINSERTIndex(N, 128);
4201 bool X86::isVINSERT256Index(SDNode *N) {
4202 return isVINSERTIndex(N, 256);
4205 bool X86::isVEXTRACT128Index(SDNode *N) {
4206 return isVEXTRACTIndex(N, 128);
4209 bool X86::isVEXTRACT256Index(SDNode *N) {
4210 return isVEXTRACTIndex(N, 256);
4213 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4214 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4215 assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
4216 "Illegal extract subvector for VEXTRACT");
4219 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4221 MVT VecVT = N->getOperand(0).getSimpleValueType();
4222 MVT ElVT = VecVT.getVectorElementType();
4224 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4225 return Index / NumElemsPerChunk;
4228 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4229 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4230 assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
4231 "Illegal insert subvector for VINSERT");
4234 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4236 MVT VecVT = N->getSimpleValueType(0);
4237 MVT ElVT = VecVT.getVectorElementType();
4239 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4240 return Index / NumElemsPerChunk;
4243 /// Return the appropriate immediate to extract the specified
4244 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4245 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4246 return getExtractVEXTRACTImmediate(N, 128);
4249 /// Return the appropriate immediate to extract the specified
4250 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4251 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4252 return getExtractVEXTRACTImmediate(N, 256);
4255 /// Return the appropriate immediate to insert at the specified
4256 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4257 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4258 return getInsertVINSERTImmediate(N, 128);
4261 /// Return the appropriate immediate to insert at the specified
4262 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4263 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4264 return getInsertVINSERTImmediate(N, 256);
4267 /// Returns true if V is a constant integer zero.
4268 static bool isZero(SDValue V) {
4269 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4270 return C && C->isNullValue();
4273 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4274 bool X86::isZeroNode(SDValue Elt) {
4277 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4278 return CFP->getValueAPF().isPosZero();
4282 // Build a vector of constants
4283 // Use an UNDEF node if MaskElt == -1.
4284 // Spilt 64-bit constants in the 32-bit mode.
4285 static SDValue getConstVector(ArrayRef<int> Values, MVT VT,
4287 SDLoc dl, bool IsMask = false) {
4289 SmallVector<SDValue, 32> Ops;
4292 MVT ConstVecVT = VT;
4293 unsigned NumElts = VT.getVectorNumElements();
4294 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4295 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) {
4296 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4300 MVT EltVT = ConstVecVT.getVectorElementType();
4301 for (unsigned i = 0; i < NumElts; ++i) {
4302 bool IsUndef = Values[i] < 0 && IsMask;
4303 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4304 DAG.getConstant(Values[i], dl, EltVT);
4305 Ops.push_back(OpNode);
4307 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4308 DAG.getConstant(0, dl, EltVT));
4310 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4312 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4316 /// Returns a vector of specified type with all zero elements.
4317 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4318 SelectionDAG &DAG, SDLoc dl) {
4319 assert(VT.isVector() && "Expected a vector type");
4321 // Always build SSE zero vectors as <4 x i32> bitcasted
4322 // to their dest type. This ensures they get CSE'd.
4324 if (VT.is128BitVector()) { // SSE
4325 if (Subtarget->hasSSE2()) { // SSE2
4326 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4327 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4329 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4330 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4332 } else if (VT.is256BitVector()) { // AVX
4333 if (Subtarget->hasInt256()) { // AVX2
4334 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4335 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4336 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4338 // 256-bit logic and arithmetic instructions in AVX are all
4339 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4340 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4341 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4342 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4344 } else if (VT.is512BitVector()) { // AVX-512
4345 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4346 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4347 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4348 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4349 } else if (VT.getVectorElementType() == MVT::i1) {
4351 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4352 && "Unexpected vector type");
4353 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4354 && "Unexpected vector type");
4355 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4356 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4357 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4359 llvm_unreachable("Unexpected vector type");
4361 return DAG.getBitcast(VT, Vec);
4364 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4365 SelectionDAG &DAG, SDLoc dl,
4366 unsigned vectorWidth) {
4367 assert((vectorWidth == 128 || vectorWidth == 256) &&
4368 "Unsupported vector width");
4369 EVT VT = Vec.getValueType();
4370 EVT ElVT = VT.getVectorElementType();
4371 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4372 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4373 VT.getVectorNumElements()/Factor);
4375 // Extract from UNDEF is UNDEF.
4376 if (Vec.getOpcode() == ISD::UNDEF)
4377 return DAG.getUNDEF(ResultVT);
4379 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4380 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4381 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4383 // This is the index of the first element of the vectorWidth-bit chunk
4384 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4385 IdxVal &= ~(ElemsPerChunk - 1);
4387 // If the input is a buildvector just emit a smaller one.
4388 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4389 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4390 makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4392 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4393 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4396 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4397 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4398 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4399 /// instructions or a simple subregister reference. Idx is an index in the
4400 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4401 /// lowering EXTRACT_VECTOR_ELT operations easier.
4402 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4403 SelectionDAG &DAG, SDLoc dl) {
4404 assert((Vec.getValueType().is256BitVector() ||
4405 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4406 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4409 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4410 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4411 SelectionDAG &DAG, SDLoc dl) {
4412 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4413 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4416 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4417 unsigned IdxVal, SelectionDAG &DAG,
4418 SDLoc dl, unsigned vectorWidth) {
4419 assert((vectorWidth == 128 || vectorWidth == 256) &&
4420 "Unsupported vector width");
4421 // Inserting UNDEF is Result
4422 if (Vec.getOpcode() == ISD::UNDEF)
4424 EVT VT = Vec.getValueType();
4425 EVT ElVT = VT.getVectorElementType();
4426 EVT ResultVT = Result.getValueType();
4428 // Insert the relevant vectorWidth bits.
4429 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4430 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
4432 // This is the index of the first element of the vectorWidth-bit chunk
4433 // we want. Since ElemsPerChunk is a power of 2 just need to clear bits.
4434 IdxVal &= ~(ElemsPerChunk - 1);
4436 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4437 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4440 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4441 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4442 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4443 /// simple superregister reference. Idx is an index in the 128 bits
4444 /// we want. It need not be aligned to a 128-bit boundary. That makes
4445 /// lowering INSERT_VECTOR_ELT operations easier.
4446 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4447 SelectionDAG &DAG, SDLoc dl) {
4448 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4450 // For insertion into the zero index (low half) of a 256-bit vector, it is
4451 // more efficient to generate a blend with immediate instead of an insert*128.
4452 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4453 // extend the subvector to the size of the result vector. Make sure that
4454 // we are not recursing on that node by checking for undef here.
4455 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4456 Result.getOpcode() != ISD::UNDEF) {
4457 EVT ResultVT = Result.getValueType();
4458 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4459 SDValue Undef = DAG.getUNDEF(ResultVT);
4460 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4463 // The blend instruction, and therefore its mask, depend on the data type.
4464 MVT ScalarType = ResultVT.getVectorElementType().getSimpleVT();
4465 if (ScalarType.isFloatingPoint()) {
4466 // Choose either vblendps (float) or vblendpd (double).
4467 unsigned ScalarSize = ScalarType.getSizeInBits();
4468 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4469 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4470 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4471 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4474 const X86Subtarget &Subtarget =
4475 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4477 // AVX2 is needed for 256-bit integer blend support.
4478 // Integers must be cast to 32-bit because there is only vpblendd;
4479 // vpblendw can't be used for this because it has a handicapped mask.
4481 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4482 // is still more efficient than using the wrong domain vinsertf128 that
4483 // will be created by InsertSubVector().
4484 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4486 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4487 Vec256 = DAG.getBitcast(CastVT, Vec256);
4488 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4489 return DAG.getBitcast(ResultVT, Vec256);
4492 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4495 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4496 SelectionDAG &DAG, SDLoc dl) {
4497 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4498 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4501 /// Insert i1-subvector to i1-vector.
4502 static SDValue Insert1BitVector(SDValue Op, SelectionDAG &DAG) {
4505 SDValue Vec = Op.getOperand(0);
4506 SDValue SubVec = Op.getOperand(1);
4507 SDValue Idx = Op.getOperand(2);
4509 if (!isa<ConstantSDNode>(Idx))
4512 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4513 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4516 MVT OpVT = Op.getSimpleValueType();
4517 MVT SubVecVT = SubVec.getSimpleValueType();
4518 unsigned NumElems = OpVT.getVectorNumElements();
4519 unsigned SubVecNumElems = SubVecVT.getVectorNumElements();
4521 assert(IdxVal + SubVecNumElems <= NumElems &&
4522 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4523 "Unexpected index value in INSERT_SUBVECTOR");
4525 // There are 3 possible cases:
4526 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4527 // 2. Subvector should be inserted in the upper part
4528 // (IdxVal + SubVecNumElems == NumElems)
4529 // 3. Subvector should be inserted in the middle (for example v2i1
4530 // to v16i1, index 2)
4532 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
4533 SDValue Undef = DAG.getUNDEF(OpVT);
4534 SDValue WideSubVec =
4535 DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, SubVec, ZeroIdx);
4537 return DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4538 DAG.getConstant(IdxVal, dl, MVT::i8));
4540 if (ISD::isBuildVectorAllZeros(Vec.getNode())) {
4541 unsigned ShiftLeft = NumElems - SubVecNumElems;
4542 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4543 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, WideSubVec,
4544 DAG.getConstant(ShiftLeft, dl, MVT::i8));
4545 return ShiftRight ? DAG.getNode(X86ISD::VSRLI, dl, OpVT, WideSubVec,
4546 DAG.getConstant(ShiftRight, dl, MVT::i8)) : WideSubVec;
4550 // Zero lower bits of the Vec
4551 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4552 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4553 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4554 // Merge them together
4555 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4558 // Simple case when we put subvector in the upper part
4559 if (IdxVal + SubVecNumElems == NumElems) {
4560 // Zero upper bits of the Vec
4561 WideSubVec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec,
4562 DAG.getConstant(IdxVal, dl, MVT::i8));
4563 SDValue ShiftBits = DAG.getConstant(SubVecNumElems, dl, MVT::i8);
4564 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
4565 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
4566 return DAG.getNode(ISD::OR, dl, OpVT, Vec, WideSubVec);
4568 // Subvector should be inserted in the middle - use shuffle
4569 SmallVector<int, 64> Mask;
4570 for (unsigned i = 0; i < NumElems; ++i)
4571 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
4573 return DAG.getVectorShuffle(OpVT, dl, WideSubVec, Vec, Mask);
4576 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4577 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4578 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4579 /// large BUILD_VECTORS.
4580 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4581 unsigned NumElems, SelectionDAG &DAG,
4583 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4584 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4587 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4588 unsigned NumElems, SelectionDAG &DAG,
4590 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4591 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4594 /// Returns a vector of specified type with all bits set.
4595 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4596 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4597 /// Then bitcast to their original type, ensuring they get CSE'd.
4598 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4599 SelectionDAG &DAG, SDLoc dl) {
4600 assert(VT.isVector() && "Expected a vector type");
4602 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4604 if (VT.is512BitVector()) {
4605 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4606 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4607 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4608 } else if (VT.is256BitVector()) {
4609 if (Subtarget->hasInt256()) { // AVX2
4610 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4611 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4613 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4614 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4616 } else if (VT.is128BitVector()) {
4617 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4619 llvm_unreachable("Unexpected vector type");
4621 return DAG.getBitcast(VT, Vec);
4624 /// Returns a vector_shuffle node for an unpackl operation.
4625 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4627 unsigned NumElems = VT.getVectorNumElements();
4628 SmallVector<int, 8> Mask;
4629 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4631 Mask.push_back(i + NumElems);
4633 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4636 /// Returns a vector_shuffle node for an unpackh operation.
4637 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4639 unsigned NumElems = VT.getVectorNumElements();
4640 SmallVector<int, 8> Mask;
4641 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4642 Mask.push_back(i + Half);
4643 Mask.push_back(i + NumElems + Half);
4645 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4648 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4649 /// This produces a shuffle where the low element of V2 is swizzled into the
4650 /// zero/undef vector, landing at element Idx.
4651 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4652 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4654 const X86Subtarget *Subtarget,
4655 SelectionDAG &DAG) {
4656 MVT VT = V2.getSimpleValueType();
4658 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4659 unsigned NumElems = VT.getVectorNumElements();
4660 SmallVector<int, 16> MaskVec;
4661 for (unsigned i = 0; i != NumElems; ++i)
4662 // If this is the insertion idx, put the low elt of V2 here.
4663 MaskVec.push_back(i == Idx ? NumElems : i);
4664 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4667 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4668 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4669 /// uses one source. Note that this will set IsUnary for shuffles which use a
4670 /// single input multiple times, and in those cases it will
4671 /// adjust the mask to only have indices within that single input.
4672 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4673 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4674 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4675 unsigned NumElems = VT.getVectorNumElements();
4679 bool IsFakeUnary = false;
4680 switch(N->getOpcode()) {
4681 case X86ISD::BLENDI:
4682 ImmN = N->getOperand(N->getNumOperands()-1);
4683 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4686 ImmN = N->getOperand(N->getNumOperands()-1);
4687 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4688 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4690 case X86ISD::UNPCKH:
4691 DecodeUNPCKHMask(VT, Mask);
4692 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4694 case X86ISD::UNPCKL:
4695 DecodeUNPCKLMask(VT, Mask);
4696 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4698 case X86ISD::MOVHLPS:
4699 DecodeMOVHLPSMask(NumElems, Mask);
4700 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4702 case X86ISD::MOVLHPS:
4703 DecodeMOVLHPSMask(NumElems, Mask);
4704 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4706 case X86ISD::PALIGNR:
4707 ImmN = N->getOperand(N->getNumOperands()-1);
4708 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4710 case X86ISD::PSHUFD:
4711 case X86ISD::VPERMILPI:
4712 ImmN = N->getOperand(N->getNumOperands()-1);
4713 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4716 case X86ISD::PSHUFHW:
4717 ImmN = N->getOperand(N->getNumOperands()-1);
4718 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4721 case X86ISD::PSHUFLW:
4722 ImmN = N->getOperand(N->getNumOperands()-1);
4723 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4726 case X86ISD::PSHUFB: {
4728 SDValue MaskNode = N->getOperand(1);
4729 while (MaskNode->getOpcode() == ISD::BITCAST)
4730 MaskNode = MaskNode->getOperand(0);
4732 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4733 // If we have a build-vector, then things are easy.
4734 MVT VT = MaskNode.getSimpleValueType();
4735 assert(VT.isVector() &&
4736 "Can't produce a non-vector with a build_vector!");
4737 if (!VT.isInteger())
4740 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4742 SmallVector<uint64_t, 32> RawMask;
4743 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4744 SDValue Op = MaskNode->getOperand(i);
4745 if (Op->getOpcode() == ISD::UNDEF) {
4746 RawMask.push_back((uint64_t)SM_SentinelUndef);
4749 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4752 APInt MaskElement = CN->getAPIntValue();
4754 // We now have to decode the element which could be any integer size and
4755 // extract each byte of it.
4756 for (int j = 0; j < NumBytesPerElement; ++j) {
4757 // Note that this is x86 and so always little endian: the low byte is
4758 // the first byte of the mask.
4759 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4760 MaskElement = MaskElement.lshr(8);
4763 DecodePSHUFBMask(RawMask, Mask);
4767 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4771 SDValue Ptr = MaskLoad->getBasePtr();
4772 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4773 Ptr->getOpcode() == X86ISD::WrapperRIP)
4774 Ptr = Ptr->getOperand(0);
4776 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4777 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4780 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4781 DecodePSHUFBMask(C, Mask);
4789 case X86ISD::VPERMI:
4790 ImmN = N->getOperand(N->getNumOperands()-1);
4791 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4796 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4798 case X86ISD::VPERM2X128:
4799 ImmN = N->getOperand(N->getNumOperands()-1);
4800 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4801 if (Mask.empty()) return false;
4802 // Mask only contains negative index if an element is zero.
4803 if (std::any_of(Mask.begin(), Mask.end(),
4804 [](int M){ return M == SM_SentinelZero; }))
4807 case X86ISD::MOVSLDUP:
4808 DecodeMOVSLDUPMask(VT, Mask);
4811 case X86ISD::MOVSHDUP:
4812 DecodeMOVSHDUPMask(VT, Mask);
4815 case X86ISD::MOVDDUP:
4816 DecodeMOVDDUPMask(VT, Mask);
4819 case X86ISD::MOVLHPD:
4820 case X86ISD::MOVLPD:
4821 case X86ISD::MOVLPS:
4822 // Not yet implemented
4824 case X86ISD::VPERMV: {
4826 SDValue MaskNode = N->getOperand(0);
4827 while (MaskNode->getOpcode() == ISD::BITCAST)
4828 MaskNode = MaskNode->getOperand(0);
4830 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4831 SmallVector<uint64_t, 32> RawMask;
4832 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4833 // If we have a build-vector, then things are easy.
4834 assert(MaskNode.getSimpleValueType().isInteger() &&
4835 MaskNode.getSimpleValueType().getVectorNumElements() ==
4836 VT.getVectorNumElements());
4838 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4839 SDValue Op = MaskNode->getOperand(i);
4840 if (Op->getOpcode() == ISD::UNDEF)
4841 RawMask.push_back((uint64_t)SM_SentinelUndef);
4842 else if (isa<ConstantSDNode>(Op)) {
4843 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4844 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4848 DecodeVPERMVMask(RawMask, Mask);
4851 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4852 unsigned NumEltsInMask = MaskNode->getNumOperands();
4853 MaskNode = MaskNode->getOperand(0);
4854 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4856 APInt MaskEltValue = CN->getAPIntValue();
4857 for (unsigned i = 0; i < NumEltsInMask; ++i)
4858 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4859 DecodeVPERMVMask(RawMask, Mask);
4862 // It may be a scalar load
4865 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4869 SDValue Ptr = MaskLoad->getBasePtr();
4870 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4871 Ptr->getOpcode() == X86ISD::WrapperRIP)
4872 Ptr = Ptr->getOperand(0);
4874 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4875 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4878 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4880 DecodeVPERMVMask(C, VT, Mask);
4887 case X86ISD::VPERMV3: {
4889 SDValue MaskNode = N->getOperand(1);
4890 while (MaskNode->getOpcode() == ISD::BITCAST)
4891 MaskNode = MaskNode->getOperand(1);
4893 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4894 // If we have a build-vector, then things are easy.
4895 assert(MaskNode.getSimpleValueType().isInteger() &&
4896 MaskNode.getSimpleValueType().getVectorNumElements() ==
4897 VT.getVectorNumElements());
4899 SmallVector<uint64_t, 32> RawMask;
4900 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4902 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4903 SDValue Op = MaskNode->getOperand(i);
4904 if (Op->getOpcode() == ISD::UNDEF)
4905 RawMask.push_back((uint64_t)SM_SentinelUndef);
4907 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4910 APInt MaskElement = CN->getAPIntValue();
4911 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4914 DecodeVPERMV3Mask(RawMask, Mask);
4918 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4922 SDValue Ptr = MaskLoad->getBasePtr();
4923 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4924 Ptr->getOpcode() == X86ISD::WrapperRIP)
4925 Ptr = Ptr->getOperand(0);
4927 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4928 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4931 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4933 DecodeVPERMV3Mask(C, VT, Mask);
4940 default: llvm_unreachable("unknown target shuffle node");
4943 // If we have a fake unary shuffle, the shuffle mask is spread across two
4944 // inputs that are actually the same node. Re-map the mask to always point
4945 // into the first input.
4948 if (M >= (int)Mask.size())
4954 /// Returns the scalar element that will make up the ith
4955 /// element of the result of the vector shuffle.
4956 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4959 return SDValue(); // Limit search depth.
4961 SDValue V = SDValue(N, 0);
4962 EVT VT = V.getValueType();
4963 unsigned Opcode = V.getOpcode();
4965 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4966 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4967 int Elt = SV->getMaskElt(Index);
4970 return DAG.getUNDEF(VT.getVectorElementType());
4972 unsigned NumElems = VT.getVectorNumElements();
4973 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4974 : SV->getOperand(1);
4975 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4978 // Recurse into target specific vector shuffles to find scalars.
4979 if (isTargetShuffle(Opcode)) {
4980 MVT ShufVT = V.getSimpleValueType();
4981 unsigned NumElems = ShufVT.getVectorNumElements();
4982 SmallVector<int, 16> ShuffleMask;
4985 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4988 int Elt = ShuffleMask[Index];
4990 return DAG.getUNDEF(ShufVT.getVectorElementType());
4992 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4994 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4998 // Actual nodes that may contain scalar elements
4999 if (Opcode == ISD::BITCAST) {
5000 V = V.getOperand(0);
5001 EVT SrcVT = V.getValueType();
5002 unsigned NumElems = VT.getVectorNumElements();
5004 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
5008 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
5009 return (Index == 0) ? V.getOperand(0)
5010 : DAG.getUNDEF(VT.getVectorElementType());
5012 if (V.getOpcode() == ISD::BUILD_VECTOR)
5013 return V.getOperand(Index);
5018 /// Custom lower build_vector of v16i8.
5019 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
5020 unsigned NumNonZero, unsigned NumZero,
5022 const X86Subtarget* Subtarget,
5023 const TargetLowering &TLI) {
5031 // SSE4.1 - use PINSRB to insert each byte directly.
5032 if (Subtarget->hasSSE41()) {
5033 for (unsigned i = 0; i < 16; ++i) {
5034 bool isNonZero = (NonZeros & (1 << i)) != 0;
5038 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
5040 V = DAG.getUNDEF(MVT::v16i8);
5043 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5044 MVT::v16i8, V, Op.getOperand(i),
5045 DAG.getIntPtrConstant(i, dl));
5052 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
5053 for (unsigned i = 0; i < 16; ++i) {
5054 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
5055 if (ThisIsNonZero && First) {
5057 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5059 V = DAG.getUNDEF(MVT::v8i16);
5064 SDValue ThisElt, LastElt;
5065 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
5066 if (LastIsNonZero) {
5067 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
5068 MVT::i16, Op.getOperand(i-1));
5070 if (ThisIsNonZero) {
5071 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
5072 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
5073 ThisElt, DAG.getConstant(8, dl, MVT::i8));
5075 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5079 if (ThisElt.getNode())
5080 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5081 DAG.getIntPtrConstant(i/2, dl));
5085 return DAG.getBitcast(MVT::v16i8, V);
5088 /// Custom lower build_vector of v8i16.
5089 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5090 unsigned NumNonZero, unsigned NumZero,
5092 const X86Subtarget* Subtarget,
5093 const TargetLowering &TLI) {
5100 for (unsigned i = 0; i < 8; ++i) {
5101 bool isNonZero = (NonZeros & (1 << i)) != 0;
5105 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5107 V = DAG.getUNDEF(MVT::v8i16);
5110 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5111 MVT::v8i16, V, Op.getOperand(i),
5112 DAG.getIntPtrConstant(i, dl));
5119 /// Custom lower build_vector of v4i32 or v4f32.
5120 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5121 const X86Subtarget *Subtarget,
5122 const TargetLowering &TLI) {
5123 // Find all zeroable elements.
5124 std::bitset<4> Zeroable;
5125 for (int i=0; i < 4; ++i) {
5126 SDValue Elt = Op->getOperand(i);
5127 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5129 assert(Zeroable.size() - Zeroable.count() > 1 &&
5130 "We expect at least two non-zero elements!");
5132 // We only know how to deal with build_vector nodes where elements are either
5133 // zeroable or extract_vector_elt with constant index.
5134 SDValue FirstNonZero;
5135 unsigned FirstNonZeroIdx;
5136 for (unsigned i=0; i < 4; ++i) {
5139 SDValue Elt = Op->getOperand(i);
5140 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5141 !isa<ConstantSDNode>(Elt.getOperand(1)))
5143 // Make sure that this node is extracting from a 128-bit vector.
5144 MVT VT = Elt.getOperand(0).getSimpleValueType();
5145 if (!VT.is128BitVector())
5147 if (!FirstNonZero.getNode()) {
5149 FirstNonZeroIdx = i;
5153 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5154 SDValue V1 = FirstNonZero.getOperand(0);
5155 MVT VT = V1.getSimpleValueType();
5157 // See if this build_vector can be lowered as a blend with zero.
5159 unsigned EltMaskIdx, EltIdx;
5161 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5162 if (Zeroable[EltIdx]) {
5163 // The zero vector will be on the right hand side.
5164 Mask[EltIdx] = EltIdx+4;
5168 Elt = Op->getOperand(EltIdx);
5169 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5170 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5171 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5173 Mask[EltIdx] = EltIdx;
5177 // Let the shuffle legalizer deal with blend operations.
5178 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5179 if (V1.getSimpleValueType() != VT)
5180 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5181 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5184 // See if we can lower this build_vector to a INSERTPS.
5185 if (!Subtarget->hasSSE41())
5188 SDValue V2 = Elt.getOperand(0);
5189 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5192 bool CanFold = true;
5193 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5197 SDValue Current = Op->getOperand(i);
5198 SDValue SrcVector = Current->getOperand(0);
5201 CanFold = SrcVector == V1 &&
5202 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5208 assert(V1.getNode() && "Expected at least two non-zero elements!");
5209 if (V1.getSimpleValueType() != MVT::v4f32)
5210 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5211 if (V2.getSimpleValueType() != MVT::v4f32)
5212 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5214 // Ok, we can emit an INSERTPS instruction.
5215 unsigned ZMask = Zeroable.to_ulong();
5217 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5218 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5220 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5221 DAG.getIntPtrConstant(InsertPSMask, DL));
5222 return DAG.getBitcast(VT, Result);
5225 /// Return a vector logical shift node.
5226 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5227 unsigned NumBits, SelectionDAG &DAG,
5228 const TargetLowering &TLI, SDLoc dl) {
5229 assert(VT.is128BitVector() && "Unknown type for VShift");
5230 MVT ShVT = MVT::v2i64;
5231 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5232 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5233 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5234 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5235 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5236 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5240 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5242 // Check if the scalar load can be widened into a vector load. And if
5243 // the address is "base + cst" see if the cst can be "absorbed" into
5244 // the shuffle mask.
5245 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5246 SDValue Ptr = LD->getBasePtr();
5247 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5249 EVT PVT = LD->getValueType(0);
5250 if (PVT != MVT::i32 && PVT != MVT::f32)
5255 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5256 FI = FINode->getIndex();
5258 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5259 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5260 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5261 Offset = Ptr.getConstantOperandVal(1);
5262 Ptr = Ptr.getOperand(0);
5267 // FIXME: 256-bit vector instructions don't require a strict alignment,
5268 // improve this code to support it better.
5269 unsigned RequiredAlign = VT.getSizeInBits()/8;
5270 SDValue Chain = LD->getChain();
5271 // Make sure the stack object alignment is at least 16 or 32.
5272 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5273 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5274 if (MFI->isFixedObjectIndex(FI)) {
5275 // Can't change the alignment. FIXME: It's possible to compute
5276 // the exact stack offset and reference FI + adjust offset instead.
5277 // If someone *really* cares about this. That's the way to implement it.
5280 MFI->setObjectAlignment(FI, RequiredAlign);
5284 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5285 // Ptr + (Offset & ~15).
5288 if ((Offset % RequiredAlign) & 3)
5290 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5293 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5294 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5297 int EltNo = (Offset - StartOffset) >> 2;
5298 unsigned NumElems = VT.getVectorNumElements();
5300 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5301 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5302 LD->getPointerInfo().getWithOffset(StartOffset),
5303 false, false, false, 0);
5305 SmallVector<int, 8> Mask(NumElems, EltNo);
5307 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5313 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5314 /// elements can be replaced by a single large load which has the same value as
5315 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5317 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5319 /// FIXME: we'd also like to handle the case where the last elements are zero
5320 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5321 /// There's even a handy isZeroNode for that purpose.
5322 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5323 SDLoc &DL, SelectionDAG &DAG,
5324 bool isAfterLegalize) {
5325 unsigned NumElems = Elts.size();
5327 LoadSDNode *LDBase = nullptr;
5328 unsigned LastLoadedElt = -1U;
5330 // For each element in the initializer, see if we've found a load or an undef.
5331 // If we don't find an initial load element, or later load elements are
5332 // non-consecutive, bail out.
5333 for (unsigned i = 0; i < NumElems; ++i) {
5334 SDValue Elt = Elts[i];
5335 // Look through a bitcast.
5336 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5337 Elt = Elt.getOperand(0);
5338 if (!Elt.getNode() ||
5339 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5342 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5344 LDBase = cast<LoadSDNode>(Elt.getNode());
5348 if (Elt.getOpcode() == ISD::UNDEF)
5351 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5352 EVT LdVT = Elt.getValueType();
5353 // Each loaded element must be the correct fractional portion of the
5354 // requested vector load.
5355 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5357 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5362 // If we have found an entire vector of loads and undefs, then return a large
5363 // load of the entire vector width starting at the base pointer. If we found
5364 // consecutive loads for the low half, generate a vzext_load node.
5365 if (LastLoadedElt == NumElems - 1) {
5366 assert(LDBase && "Did not find base load for merging consecutive loads");
5367 EVT EltVT = LDBase->getValueType(0);
5368 // Ensure that the input vector size for the merged loads matches the
5369 // cumulative size of the input elements.
5370 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5373 if (isAfterLegalize &&
5374 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5377 SDValue NewLd = SDValue();
5379 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5380 LDBase->getPointerInfo(), LDBase->isVolatile(),
5381 LDBase->isNonTemporal(), LDBase->isInvariant(),
5382 LDBase->getAlignment());
5384 if (LDBase->hasAnyUseOfValue(1)) {
5385 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5387 SDValue(NewLd.getNode(), 1));
5388 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5389 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5390 SDValue(NewLd.getNode(), 1));
5396 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5397 //of a v4i32 / v4f32. It's probably worth generalizing.
5398 EVT EltVT = VT.getVectorElementType();
5399 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5400 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5401 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5402 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5404 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5405 LDBase->getPointerInfo(),
5406 LDBase->getAlignment(),
5407 false/*isVolatile*/, true/*ReadMem*/,
5410 // Make sure the newly-created LOAD is in the same position as LDBase in
5411 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5412 // update uses of LDBase's output chain to use the TokenFactor.
5413 if (LDBase->hasAnyUseOfValue(1)) {
5414 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5415 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5416 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5417 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5418 SDValue(ResNode.getNode(), 1));
5421 return DAG.getBitcast(VT, ResNode);
5426 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5427 /// to generate a splat value for the following cases:
5428 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5429 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5430 /// a scalar load, or a constant.
5431 /// The VBROADCAST node is returned when a pattern is found,
5432 /// or SDValue() otherwise.
5433 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5434 SelectionDAG &DAG) {
5435 // VBROADCAST requires AVX.
5436 // TODO: Splats could be generated for non-AVX CPUs using SSE
5437 // instructions, but there's less potential gain for only 128-bit vectors.
5438 if (!Subtarget->hasAVX())
5441 MVT VT = Op.getSimpleValueType();
5444 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5445 "Unsupported vector type for broadcast.");
5450 switch (Op.getOpcode()) {
5452 // Unknown pattern found.
5455 case ISD::BUILD_VECTOR: {
5456 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5457 BitVector UndefElements;
5458 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5460 // We need a splat of a single value to use broadcast, and it doesn't
5461 // make any sense if the value is only in one element of the vector.
5462 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5466 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5467 Ld.getOpcode() == ISD::ConstantFP);
5469 // Make sure that all of the users of a non-constant load are from the
5470 // BUILD_VECTOR node.
5471 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5476 case ISD::VECTOR_SHUFFLE: {
5477 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5479 // Shuffles must have a splat mask where the first element is
5481 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5484 SDValue Sc = Op.getOperand(0);
5485 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5486 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5488 if (!Subtarget->hasInt256())
5491 // Use the register form of the broadcast instruction available on AVX2.
5492 if (VT.getSizeInBits() >= 256)
5493 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5494 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5497 Ld = Sc.getOperand(0);
5498 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5499 Ld.getOpcode() == ISD::ConstantFP);
5501 // The scalar_to_vector node and the suspected
5502 // load node must have exactly one user.
5503 // Constants may have multiple users.
5505 // AVX-512 has register version of the broadcast
5506 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5507 Ld.getValueType().getSizeInBits() >= 32;
5508 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5515 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5516 bool IsGE256 = (VT.getSizeInBits() >= 256);
5518 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5519 // instruction to save 8 or more bytes of constant pool data.
5520 // TODO: If multiple splats are generated to load the same constant,
5521 // it may be detrimental to overall size. There needs to be a way to detect
5522 // that condition to know if this is truly a size win.
5523 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5525 // Handle broadcasting a single constant scalar from the constant pool
5527 // On Sandybridge (no AVX2), it is still better to load a constant vector
5528 // from the constant pool and not to broadcast it from a scalar.
5529 // But override that restriction when optimizing for size.
5530 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5531 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5532 EVT CVT = Ld.getValueType();
5533 assert(!CVT.isVector() && "Must not broadcast a vector type");
5535 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5536 // For size optimization, also splat v2f64 and v2i64, and for size opt
5537 // with AVX2, also splat i8 and i16.
5538 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5539 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5540 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5541 const Constant *C = nullptr;
5542 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5543 C = CI->getConstantIntValue();
5544 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5545 C = CF->getConstantFPValue();
5547 assert(C && "Invalid constant type");
5549 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5551 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5552 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5554 CVT, dl, DAG.getEntryNode(), CP,
5555 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5556 false, false, Alignment);
5558 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5562 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5564 // Handle AVX2 in-register broadcasts.
5565 if (!IsLoad && Subtarget->hasInt256() &&
5566 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5567 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5569 // The scalar source must be a normal load.
5573 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5574 (Subtarget->hasVLX() && ScalarSize == 64))
5575 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5577 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5578 // double since there is no vbroadcastsd xmm
5579 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5580 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5581 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5584 // Unsupported broadcast.
5588 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5589 /// underlying vector and index.
5591 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5593 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5595 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5596 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5599 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5601 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5603 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5604 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5607 // In this case the vector is the extract_subvector expression and the index
5608 // is 2, as specified by the shuffle.
5609 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5610 SDValue ShuffleVec = SVOp->getOperand(0);
5611 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5612 assert(ShuffleVecVT.getVectorElementType() ==
5613 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5615 int ShuffleIdx = SVOp->getMaskElt(Idx);
5616 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5617 ExtractedFromVec = ShuffleVec;
5623 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5624 MVT VT = Op.getSimpleValueType();
5626 // Skip if insert_vec_elt is not supported.
5627 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5628 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5632 unsigned NumElems = Op.getNumOperands();
5636 SmallVector<unsigned, 4> InsertIndices;
5637 SmallVector<int, 8> Mask(NumElems, -1);
5639 for (unsigned i = 0; i != NumElems; ++i) {
5640 unsigned Opc = Op.getOperand(i).getOpcode();
5642 if (Opc == ISD::UNDEF)
5645 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5646 // Quit if more than 1 elements need inserting.
5647 if (InsertIndices.size() > 1)
5650 InsertIndices.push_back(i);
5654 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5655 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5656 // Quit if non-constant index.
5657 if (!isa<ConstantSDNode>(ExtIdx))
5659 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5661 // Quit if extracted from vector of different type.
5662 if (ExtractedFromVec.getValueType() != VT)
5665 if (!VecIn1.getNode())
5666 VecIn1 = ExtractedFromVec;
5667 else if (VecIn1 != ExtractedFromVec) {
5668 if (!VecIn2.getNode())
5669 VecIn2 = ExtractedFromVec;
5670 else if (VecIn2 != ExtractedFromVec)
5671 // Quit if more than 2 vectors to shuffle
5675 if (ExtractedFromVec == VecIn1)
5677 else if (ExtractedFromVec == VecIn2)
5678 Mask[i] = Idx + NumElems;
5681 if (!VecIn1.getNode())
5684 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5685 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5686 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5687 unsigned Idx = InsertIndices[i];
5688 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5689 DAG.getIntPtrConstant(Idx, DL));
5695 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5696 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5697 Op.getScalarValueSizeInBits() == 1 &&
5698 "Can not convert non-constant vector");
5699 uint64_t Immediate = 0;
5700 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5701 SDValue In = Op.getOperand(idx);
5702 if (In.getOpcode() != ISD::UNDEF)
5703 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5707 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5708 return DAG.getConstant(Immediate, dl, VT);
5710 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5712 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5714 MVT VT = Op.getSimpleValueType();
5715 assert((VT.getVectorElementType() == MVT::i1) &&
5716 "Unexpected type in LowerBUILD_VECTORvXi1!");
5719 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5720 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5721 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5722 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5725 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5726 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5727 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5728 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5731 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5732 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5733 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5734 return DAG.getBitcast(VT, Imm);
5735 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5736 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5737 DAG.getIntPtrConstant(0, dl));
5740 // Vector has one or more non-const elements
5741 uint64_t Immediate = 0;
5742 SmallVector<unsigned, 16> NonConstIdx;
5743 bool IsSplat = true;
5744 bool HasConstElts = false;
5746 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5747 SDValue In = Op.getOperand(idx);
5748 if (In.getOpcode() == ISD::UNDEF)
5750 if (!isa<ConstantSDNode>(In))
5751 NonConstIdx.push_back(idx);
5753 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5754 HasConstElts = true;
5758 else if (In != Op.getOperand(SplatIdx))
5762 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5764 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5765 DAG.getConstant(1, dl, VT),
5766 DAG.getConstant(0, dl, VT));
5768 // insert elements one by one
5772 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5773 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5775 else if (HasConstElts)
5776 Imm = DAG.getConstant(0, dl, VT);
5778 Imm = DAG.getUNDEF(VT);
5779 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5780 DstVec = DAG.getBitcast(VT, Imm);
5782 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5783 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5784 DAG.getIntPtrConstant(0, dl));
5787 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5788 unsigned InsertIdx = NonConstIdx[i];
5789 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5790 Op.getOperand(InsertIdx),
5791 DAG.getIntPtrConstant(InsertIdx, dl));
5796 /// \brief Return true if \p N implements a horizontal binop and return the
5797 /// operands for the horizontal binop into V0 and V1.
5799 /// This is a helper function of LowerToHorizontalOp().
5800 /// This function checks that the build_vector \p N in input implements a
5801 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5802 /// operation to match.
5803 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5804 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5805 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5808 /// This function only analyzes elements of \p N whose indices are
5809 /// in range [BaseIdx, LastIdx).
5810 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5812 unsigned BaseIdx, unsigned LastIdx,
5813 SDValue &V0, SDValue &V1) {
5814 EVT VT = N->getValueType(0);
5816 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5817 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5818 "Invalid Vector in input!");
5820 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5821 bool CanFold = true;
5822 unsigned ExpectedVExtractIdx = BaseIdx;
5823 unsigned NumElts = LastIdx - BaseIdx;
5824 V0 = DAG.getUNDEF(VT);
5825 V1 = DAG.getUNDEF(VT);
5827 // Check if N implements a horizontal binop.
5828 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5829 SDValue Op = N->getOperand(i + BaseIdx);
5832 if (Op->getOpcode() == ISD::UNDEF) {
5833 // Update the expected vector extract index.
5834 if (i * 2 == NumElts)
5835 ExpectedVExtractIdx = BaseIdx;
5836 ExpectedVExtractIdx += 2;
5840 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5845 SDValue Op0 = Op.getOperand(0);
5846 SDValue Op1 = Op.getOperand(1);
5848 // Try to match the following pattern:
5849 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5850 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5851 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5852 Op0.getOperand(0) == Op1.getOperand(0) &&
5853 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5854 isa<ConstantSDNode>(Op1.getOperand(1)));
5858 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5859 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5861 if (i * 2 < NumElts) {
5862 if (V0.getOpcode() == ISD::UNDEF) {
5863 V0 = Op0.getOperand(0);
5864 if (V0.getValueType() != VT)
5868 if (V1.getOpcode() == ISD::UNDEF) {
5869 V1 = Op0.getOperand(0);
5870 if (V1.getValueType() != VT)
5873 if (i * 2 == NumElts)
5874 ExpectedVExtractIdx = BaseIdx;
5877 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5878 if (I0 == ExpectedVExtractIdx)
5879 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5880 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5881 // Try to match the following dag sequence:
5882 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5883 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5887 ExpectedVExtractIdx += 2;
5893 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5894 /// a concat_vector.
5896 /// This is a helper function of LowerToHorizontalOp().
5897 /// This function expects two 256-bit vectors called V0 and V1.
5898 /// At first, each vector is split into two separate 128-bit vectors.
5899 /// Then, the resulting 128-bit vectors are used to implement two
5900 /// horizontal binary operations.
5902 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5904 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5905 /// the two new horizontal binop.
5906 /// When Mode is set, the first horizontal binop dag node would take as input
5907 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5908 /// horizontal binop dag node would take as input the lower 128-bit of V1
5909 /// and the upper 128-bit of V1.
5911 /// HADD V0_LO, V0_HI
5912 /// HADD V1_LO, V1_HI
5914 /// Otherwise, the first horizontal binop dag node takes as input the lower
5915 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5916 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5918 /// HADD V0_LO, V1_LO
5919 /// HADD V0_HI, V1_HI
5921 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5922 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5923 /// the upper 128-bits of the result.
5924 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5925 SDLoc DL, SelectionDAG &DAG,
5926 unsigned X86Opcode, bool Mode,
5927 bool isUndefLO, bool isUndefHI) {
5928 EVT VT = V0.getValueType();
5929 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5930 "Invalid nodes in input!");
5932 unsigned NumElts = VT.getVectorNumElements();
5933 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5934 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5935 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5936 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5937 EVT NewVT = V0_LO.getValueType();
5939 SDValue LO = DAG.getUNDEF(NewVT);
5940 SDValue HI = DAG.getUNDEF(NewVT);
5943 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5944 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5945 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5946 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5947 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5949 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5950 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5951 V1_LO->getOpcode() != ISD::UNDEF))
5952 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5954 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5955 V1_HI->getOpcode() != ISD::UNDEF))
5956 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5959 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5962 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5964 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5965 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5966 MVT VT = BV->getSimpleValueType(0);
5967 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5968 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5972 unsigned NumElts = VT.getVectorNumElements();
5973 SDValue InVec0 = DAG.getUNDEF(VT);
5974 SDValue InVec1 = DAG.getUNDEF(VT);
5976 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5977 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5979 // Odd-numbered elements in the input build vector are obtained from
5980 // adding two integer/float elements.
5981 // Even-numbered elements in the input build vector are obtained from
5982 // subtracting two integer/float elements.
5983 unsigned ExpectedOpcode = ISD::FSUB;
5984 unsigned NextExpectedOpcode = ISD::FADD;
5985 bool AddFound = false;
5986 bool SubFound = false;
5988 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5989 SDValue Op = BV->getOperand(i);
5991 // Skip 'undef' values.
5992 unsigned Opcode = Op.getOpcode();
5993 if (Opcode == ISD::UNDEF) {
5994 std::swap(ExpectedOpcode, NextExpectedOpcode);
5998 // Early exit if we found an unexpected opcode.
5999 if (Opcode != ExpectedOpcode)
6002 SDValue Op0 = Op.getOperand(0);
6003 SDValue Op1 = Op.getOperand(1);
6005 // Try to match the following pattern:
6006 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
6007 // Early exit if we cannot match that sequence.
6008 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6009 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6010 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
6011 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
6012 Op0.getOperand(1) != Op1.getOperand(1))
6015 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
6019 // We found a valid add/sub node. Update the information accordingly.
6025 // Update InVec0 and InVec1.
6026 if (InVec0.getOpcode() == ISD::UNDEF) {
6027 InVec0 = Op0.getOperand(0);
6028 if (InVec0.getSimpleValueType() != VT)
6031 if (InVec1.getOpcode() == ISD::UNDEF) {
6032 InVec1 = Op1.getOperand(0);
6033 if (InVec1.getSimpleValueType() != VT)
6037 // Make sure that operands in input to each add/sub node always
6038 // come from a same pair of vectors.
6039 if (InVec0 != Op0.getOperand(0)) {
6040 if (ExpectedOpcode == ISD::FSUB)
6043 // FADD is commutable. Try to commute the operands
6044 // and then test again.
6045 std::swap(Op0, Op1);
6046 if (InVec0 != Op0.getOperand(0))
6050 if (InVec1 != Op1.getOperand(0))
6053 // Update the pair of expected opcodes.
6054 std::swap(ExpectedOpcode, NextExpectedOpcode);
6057 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
6058 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
6059 InVec1.getOpcode() != ISD::UNDEF)
6060 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
6065 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
6066 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
6067 const X86Subtarget *Subtarget,
6068 SelectionDAG &DAG) {
6069 MVT VT = BV->getSimpleValueType(0);
6070 unsigned NumElts = VT.getVectorNumElements();
6071 unsigned NumUndefsLO = 0;
6072 unsigned NumUndefsHI = 0;
6073 unsigned Half = NumElts/2;
6075 // Count the number of UNDEF operands in the build_vector in input.
6076 for (unsigned i = 0, e = Half; i != e; ++i)
6077 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6080 for (unsigned i = Half, e = NumElts; i != e; ++i)
6081 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6084 // Early exit if this is either a build_vector of all UNDEFs or all the
6085 // operands but one are UNDEF.
6086 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6090 SDValue InVec0, InVec1;
6091 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6092 // Try to match an SSE3 float HADD/HSUB.
6093 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6094 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6096 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6097 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6098 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6099 // Try to match an SSSE3 integer HADD/HSUB.
6100 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6101 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6103 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6104 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6107 if (!Subtarget->hasAVX())
6110 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6111 // Try to match an AVX horizontal add/sub of packed single/double
6112 // precision floating point values from 256-bit vectors.
6113 SDValue InVec2, InVec3;
6114 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6115 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6116 ((InVec0.getOpcode() == ISD::UNDEF ||
6117 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6118 ((InVec1.getOpcode() == ISD::UNDEF ||
6119 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6120 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6122 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6123 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6124 ((InVec0.getOpcode() == ISD::UNDEF ||
6125 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6126 ((InVec1.getOpcode() == ISD::UNDEF ||
6127 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6128 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6129 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6130 // Try to match an AVX2 horizontal add/sub of signed integers.
6131 SDValue InVec2, InVec3;
6133 bool CanFold = true;
6135 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6136 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6137 ((InVec0.getOpcode() == ISD::UNDEF ||
6138 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6139 ((InVec1.getOpcode() == ISD::UNDEF ||
6140 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6141 X86Opcode = X86ISD::HADD;
6142 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6143 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6144 ((InVec0.getOpcode() == ISD::UNDEF ||
6145 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6146 ((InVec1.getOpcode() == ISD::UNDEF ||
6147 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6148 X86Opcode = X86ISD::HSUB;
6153 // Fold this build_vector into a single horizontal add/sub.
6154 // Do this only if the target has AVX2.
6155 if (Subtarget->hasAVX2())
6156 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6158 // Do not try to expand this build_vector into a pair of horizontal
6159 // add/sub if we can emit a pair of scalar add/sub.
6160 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6163 // Convert this build_vector into a pair of horizontal binop followed by
6165 bool isUndefLO = NumUndefsLO == Half;
6166 bool isUndefHI = NumUndefsHI == Half;
6167 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6168 isUndefLO, isUndefHI);
6172 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6173 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6175 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6176 X86Opcode = X86ISD::HADD;
6177 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6178 X86Opcode = X86ISD::HSUB;
6179 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6180 X86Opcode = X86ISD::FHADD;
6181 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6182 X86Opcode = X86ISD::FHSUB;
6186 // Don't try to expand this build_vector into a pair of horizontal add/sub
6187 // if we can simply emit a pair of scalar add/sub.
6188 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6191 // Convert this build_vector into two horizontal add/sub followed by
6193 bool isUndefLO = NumUndefsLO == Half;
6194 bool isUndefHI = NumUndefsHI == Half;
6195 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6196 isUndefLO, isUndefHI);
6203 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6206 MVT VT = Op.getSimpleValueType();
6207 MVT ExtVT = VT.getVectorElementType();
6208 unsigned NumElems = Op.getNumOperands();
6210 // Generate vectors for predicate vectors.
6211 if (VT.getVectorElementType() == MVT::i1 && Subtarget->hasAVX512())
6212 return LowerBUILD_VECTORvXi1(Op, DAG);
6214 // Vectors containing all zeros can be matched by pxor and xorps later
6215 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6216 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6217 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6218 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6221 return getZeroVector(VT, Subtarget, DAG, dl);
6224 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6225 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6226 // vpcmpeqd on 256-bit vectors.
6227 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6228 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6231 if (!VT.is512BitVector())
6232 return getOnesVector(VT, Subtarget, DAG, dl);
6235 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6236 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6238 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6239 return HorizontalOp;
6240 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6243 unsigned EVTBits = ExtVT.getSizeInBits();
6245 unsigned NumZero = 0;
6246 unsigned NumNonZero = 0;
6247 unsigned NonZeros = 0;
6248 bool IsAllConstants = true;
6249 SmallSet<SDValue, 8> Values;
6250 for (unsigned i = 0; i < NumElems; ++i) {
6251 SDValue Elt = Op.getOperand(i);
6252 if (Elt.getOpcode() == ISD::UNDEF)
6255 if (Elt.getOpcode() != ISD::Constant &&
6256 Elt.getOpcode() != ISD::ConstantFP)
6257 IsAllConstants = false;
6258 if (X86::isZeroNode(Elt))
6261 NonZeros |= (1 << i);
6266 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6267 if (NumNonZero == 0)
6268 return DAG.getUNDEF(VT);
6270 // Special case for single non-zero, non-undef, element.
6271 if (NumNonZero == 1) {
6272 unsigned Idx = countTrailingZeros(NonZeros);
6273 SDValue Item = Op.getOperand(Idx);
6275 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6276 // the value are obviously zero, truncate the value to i32 and do the
6277 // insertion that way. Only do this if the value is non-constant or if the
6278 // value is a constant being inserted into element 0. It is cheaper to do
6279 // a constant pool load than it is to do a movd + shuffle.
6280 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6281 (!IsAllConstants || Idx == 0)) {
6282 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6284 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6285 MVT VecVT = MVT::v4i32;
6287 // Truncate the value (which may itself be a constant) to i32, and
6288 // convert it to a vector with movd (S2V+shuffle to zero extend).
6289 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6290 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6291 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6292 Item, Idx * 2, true, Subtarget, DAG));
6296 // If we have a constant or non-constant insertion into the low element of
6297 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6298 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6299 // depending on what the source datatype is.
6302 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6304 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6305 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6306 if (VT.is512BitVector()) {
6307 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6308 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6309 Item, DAG.getIntPtrConstant(0, dl));
6311 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6312 "Expected an SSE value type!");
6313 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6314 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6315 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6318 // We can't directly insert an i8 or i16 into a vector, so zero extend
6320 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6321 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6322 if (VT.is256BitVector()) {
6323 if (Subtarget->hasAVX()) {
6324 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6325 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6327 // Without AVX, we need to extend to a 128-bit vector and then
6328 // insert into the 256-bit vector.
6329 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6330 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6331 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6334 assert(VT.is128BitVector() && "Expected an SSE value type!");
6335 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6336 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6338 return DAG.getBitcast(VT, Item);
6342 // Is it a vector logical left shift?
6343 if (NumElems == 2 && Idx == 1 &&
6344 X86::isZeroNode(Op.getOperand(0)) &&
6345 !X86::isZeroNode(Op.getOperand(1))) {
6346 unsigned NumBits = VT.getSizeInBits();
6347 return getVShift(true, VT,
6348 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6349 VT, Op.getOperand(1)),
6350 NumBits/2, DAG, *this, dl);
6353 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6356 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6357 // is a non-constant being inserted into an element other than the low one,
6358 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6359 // movd/movss) to move this into the low element, then shuffle it into
6361 if (EVTBits == 32) {
6362 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6363 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6367 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6368 if (Values.size() == 1) {
6369 if (EVTBits == 32) {
6370 // Instead of a shuffle like this:
6371 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6372 // Check if it's possible to issue this instead.
6373 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6374 unsigned Idx = countTrailingZeros(NonZeros);
6375 SDValue Item = Op.getOperand(Idx);
6376 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6377 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6382 // A vector full of immediates; various special cases are already
6383 // handled, so this is best done with a single constant-pool load.
6387 // For AVX-length vectors, see if we can use a vector load to get all of the
6388 // elements, otherwise build the individual 128-bit pieces and use
6389 // shuffles to put them in place.
6390 if (VT.is256BitVector() || VT.is512BitVector()) {
6391 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6393 // Check for a build vector of consecutive loads.
6394 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6397 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6399 // Build both the lower and upper subvector.
6400 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6401 makeArrayRef(&V[0], NumElems/2));
6402 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6403 makeArrayRef(&V[NumElems / 2], NumElems/2));
6405 // Recreate the wider vector with the lower and upper part.
6406 if (VT.is256BitVector())
6407 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6408 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6411 // Let legalizer expand 2-wide build_vectors.
6412 if (EVTBits == 64) {
6413 if (NumNonZero == 1) {
6414 // One half is zero or undef.
6415 unsigned Idx = countTrailingZeros(NonZeros);
6416 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6417 Op.getOperand(Idx));
6418 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6423 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6424 if (EVTBits == 8 && NumElems == 16)
6425 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros, NumNonZero, NumZero,
6426 DAG, Subtarget, *this))
6429 if (EVTBits == 16 && NumElems == 8)
6430 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros, NumNonZero, NumZero,
6431 DAG, Subtarget, *this))
6434 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6435 if (EVTBits == 32 && NumElems == 4)
6436 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6439 // If element VT is == 32 bits, turn it into a number of shuffles.
6440 SmallVector<SDValue, 8> V(NumElems);
6441 if (NumElems == 4 && NumZero > 0) {
6442 for (unsigned i = 0; i < 4; ++i) {
6443 bool isZero = !(NonZeros & (1 << i));
6445 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6447 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6450 for (unsigned i = 0; i < 2; ++i) {
6451 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6454 V[i] = V[i*2]; // Must be a zero vector.
6457 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6460 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6463 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6468 bool Reverse1 = (NonZeros & 0x3) == 2;
6469 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6473 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6474 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6476 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6479 if (Values.size() > 1 && VT.is128BitVector()) {
6480 // Check for a build vector of consecutive loads.
6481 for (unsigned i = 0; i < NumElems; ++i)
6482 V[i] = Op.getOperand(i);
6484 // Check for elements which are consecutive loads.
6485 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6488 // Check for a build vector from mostly shuffle plus few inserting.
6489 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6492 // For SSE 4.1, use insertps to put the high elements into the low element.
6493 if (Subtarget->hasSSE41()) {
6495 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6496 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6498 Result = DAG.getUNDEF(VT);
6500 for (unsigned i = 1; i < NumElems; ++i) {
6501 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6502 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6503 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6508 // Otherwise, expand into a number of unpckl*, start by extending each of
6509 // our (non-undef) elements to the full vector width with the element in the
6510 // bottom slot of the vector (which generates no code for SSE).
6511 for (unsigned i = 0; i < NumElems; ++i) {
6512 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6513 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6515 V[i] = DAG.getUNDEF(VT);
6518 // Next, we iteratively mix elements, e.g. for v4f32:
6519 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6520 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6521 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6522 unsigned EltStride = NumElems >> 1;
6523 while (EltStride != 0) {
6524 for (unsigned i = 0; i < EltStride; ++i) {
6525 // If V[i+EltStride] is undef and this is the first round of mixing,
6526 // then it is safe to just drop this shuffle: V[i] is already in the
6527 // right place, the one element (since it's the first round) being
6528 // inserted as undef can be dropped. This isn't safe for successive
6529 // rounds because they will permute elements within both vectors.
6530 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6531 EltStride == NumElems/2)
6534 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6543 // 256-bit AVX can use the vinsertf128 instruction
6544 // to create 256-bit vectors from two other 128-bit ones.
6545 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6547 MVT ResVT = Op.getSimpleValueType();
6549 assert((ResVT.is256BitVector() ||
6550 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6552 SDValue V1 = Op.getOperand(0);
6553 SDValue V2 = Op.getOperand(1);
6554 unsigned NumElems = ResVT.getVectorNumElements();
6555 if (ResVT.is256BitVector())
6556 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6558 if (Op.getNumOperands() == 4) {
6559 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6560 ResVT.getVectorNumElements()/2);
6561 SDValue V3 = Op.getOperand(2);
6562 SDValue V4 = Op.getOperand(3);
6563 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6564 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6566 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6569 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6570 const X86Subtarget *Subtarget,
6571 SelectionDAG & DAG) {
6573 MVT ResVT = Op.getSimpleValueType();
6574 unsigned NumOfOperands = Op.getNumOperands();
6576 assert(isPowerOf2_32(NumOfOperands) &&
6577 "Unexpected number of operands in CONCAT_VECTORS");
6579 SDValue Undef = DAG.getUNDEF(ResVT);
6580 if (NumOfOperands > 2) {
6581 // Specialize the cases when all, or all but one, of the operands are undef.
6582 unsigned NumOfDefinedOps = 0;
6584 for (unsigned i = 0; i < NumOfOperands; i++)
6585 if (!Op.getOperand(i).isUndef()) {
6589 if (NumOfDefinedOps == 0)
6591 if (NumOfDefinedOps == 1) {
6592 unsigned SubVecNumElts =
6593 Op.getOperand(OpIdx).getValueType().getVectorNumElements();
6594 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6595 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef,
6596 Op.getOperand(OpIdx), IdxVal);
6599 MVT HalfVT = MVT::getVectorVT(ResVT.getVectorElementType(),
6600 ResVT.getVectorNumElements()/2);
6601 SmallVector<SDValue, 2> Ops;
6602 for (unsigned i = 0; i < NumOfOperands/2; i++)
6603 Ops.push_back(Op.getOperand(i));
6604 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6606 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6607 Ops.push_back(Op.getOperand(i));
6608 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6609 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6613 SDValue V1 = Op.getOperand(0);
6614 SDValue V2 = Op.getOperand(1);
6615 unsigned NumElems = ResVT.getVectorNumElements();
6616 assert(V1.getValueType() == V2.getValueType() &&
6617 V1.getValueType().getVectorNumElements() == NumElems/2 &&
6618 "Unexpected operands in CONCAT_VECTORS");
6620 if (ResVT.getSizeInBits() >= 16)
6621 return Op; // The operation is legal with KUNPCK
6623 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6624 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6625 SDValue ZeroVec = getZeroVector(ResVT, Subtarget, DAG, dl);
6626 if (IsZeroV1 && IsZeroV2)
6629 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6631 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6633 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx);
6635 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6637 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6640 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
6642 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6643 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
6646 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6647 const X86Subtarget *Subtarget,
6648 SelectionDAG &DAG) {
6649 MVT VT = Op.getSimpleValueType();
6650 if (VT.getVectorElementType() == MVT::i1)
6651 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6653 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6654 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6655 Op.getNumOperands() == 4)));
6657 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6658 // from two other 128-bit ones.
6660 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6661 return LowerAVXCONCAT_VECTORS(Op, DAG);
6664 //===----------------------------------------------------------------------===//
6665 // Vector shuffle lowering
6667 // This is an experimental code path for lowering vector shuffles on x86. It is
6668 // designed to handle arbitrary vector shuffles and blends, gracefully
6669 // degrading performance as necessary. It works hard to recognize idiomatic
6670 // shuffles and lower them to optimal instruction patterns without leaving
6671 // a framework that allows reasonably efficient handling of all vector shuffle
6673 //===----------------------------------------------------------------------===//
6675 /// \brief Tiny helper function to identify a no-op mask.
6677 /// This is a somewhat boring predicate function. It checks whether the mask
6678 /// array input, which is assumed to be a single-input shuffle mask of the kind
6679 /// used by the X86 shuffle instructions (not a fully general
6680 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6681 /// in-place shuffle are 'no-op's.
6682 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6683 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6684 if (Mask[i] != -1 && Mask[i] != i)
6689 /// \brief Helper function to classify a mask as a single-input mask.
6691 /// This isn't a generic single-input test because in the vector shuffle
6692 /// lowering we canonicalize single inputs to be the first input operand. This
6693 /// means we can more quickly test for a single input by only checking whether
6694 /// an input from the second operand exists. We also assume that the size of
6695 /// mask corresponds to the size of the input vectors which isn't true in the
6696 /// fully general case.
6697 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6699 if (M >= (int)Mask.size())
6704 /// \brief Test whether there are elements crossing 128-bit lanes in this
6707 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6708 /// and we routinely test for these.
6709 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6710 int LaneSize = 128 / VT.getScalarSizeInBits();
6711 int Size = Mask.size();
6712 for (int i = 0; i < Size; ++i)
6713 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6718 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6720 /// This checks a shuffle mask to see if it is performing the same
6721 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6722 /// that it is also not lane-crossing. It may however involve a blend from the
6723 /// same lane of a second vector.
6725 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6726 /// non-trivial to compute in the face of undef lanes. The representation is
6727 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6728 /// entries from both V1 and V2 inputs to the wider mask.
6730 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6731 SmallVectorImpl<int> &RepeatedMask) {
6732 int LaneSize = 128 / VT.getScalarSizeInBits();
6733 RepeatedMask.resize(LaneSize, -1);
6734 int Size = Mask.size();
6735 for (int i = 0; i < Size; ++i) {
6738 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6739 // This entry crosses lanes, so there is no way to model this shuffle.
6742 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6743 if (RepeatedMask[i % LaneSize] == -1)
6744 // This is the first non-undef entry in this slot of a 128-bit lane.
6745 RepeatedMask[i % LaneSize] =
6746 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6747 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6748 // Found a mismatch with the repeated mask.
6754 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6757 /// This is a fast way to test a shuffle mask against a fixed pattern:
6759 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6761 /// It returns true if the mask is exactly as wide as the argument list, and
6762 /// each element of the mask is either -1 (signifying undef) or the value given
6763 /// in the argument.
6764 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6765 ArrayRef<int> ExpectedMask) {
6766 if (Mask.size() != ExpectedMask.size())
6769 int Size = Mask.size();
6771 // If the values are build vectors, we can look through them to find
6772 // equivalent inputs that make the shuffles equivalent.
6773 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6774 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6776 for (int i = 0; i < Size; ++i)
6777 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6778 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6779 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6780 if (!MaskBV || !ExpectedBV ||
6781 MaskBV->getOperand(Mask[i] % Size) !=
6782 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6789 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6791 /// This helper function produces an 8-bit shuffle immediate corresponding to
6792 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6793 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6796 /// NB: We rely heavily on "undef" masks preserving the input lane.
6797 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6798 SelectionDAG &DAG) {
6799 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6800 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6801 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6802 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6803 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6806 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6807 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6808 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6809 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6810 return DAG.getConstant(Imm, DL, MVT::i8);
6813 /// \brief Compute whether each element of a shuffle is zeroable.
6815 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6816 /// Either it is an undef element in the shuffle mask, the element of the input
6817 /// referenced is undef, or the element of the input referenced is known to be
6818 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6819 /// as many lanes with this technique as possible to simplify the remaining
6821 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6822 SDValue V1, SDValue V2) {
6823 SmallBitVector Zeroable(Mask.size(), false);
6825 while (V1.getOpcode() == ISD::BITCAST)
6826 V1 = V1->getOperand(0);
6827 while (V2.getOpcode() == ISD::BITCAST)
6828 V2 = V2->getOperand(0);
6830 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6831 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6833 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6835 // Handle the easy cases.
6836 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6841 // If this is an index into a build_vector node (which has the same number
6842 // of elements), dig out the input value and use it.
6843 SDValue V = M < Size ? V1 : V2;
6844 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6847 SDValue Input = V.getOperand(M % Size);
6848 // The UNDEF opcode check really should be dead code here, but not quite
6849 // worth asserting on (it isn't invalid, just unexpected).
6850 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6857 // X86 has dedicated unpack instructions that can handle specific blend
6858 // operations: UNPCKH and UNPCKL.
6859 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6860 SDValue V1, SDValue V2,
6861 SelectionDAG &DAG) {
6862 int NumElts = VT.getVectorNumElements();
6863 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6864 SmallVector<int, 8> Unpckl;
6865 SmallVector<int, 8> Unpckh;
6867 for (int i = 0; i < NumElts; ++i) {
6868 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6869 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6870 int HiPos = LoPos + NumEltsInLane / 2;
6871 Unpckl.push_back(LoPos);
6872 Unpckh.push_back(HiPos);
6875 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6876 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6877 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6878 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6880 // Commute and try again.
6881 ShuffleVectorSDNode::commuteMask(Unpckl);
6882 if (isShuffleEquivalent(V1, V2, Mask, Unpckl))
6883 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6885 ShuffleVectorSDNode::commuteMask(Unpckh);
6886 if (isShuffleEquivalent(V1, V2, Mask, Unpckh))
6887 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6892 /// \brief Try to emit a bitmask instruction for a shuffle.
6894 /// This handles cases where we can model a blend exactly as a bitmask due to
6895 /// one of the inputs being zeroable.
6896 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6897 SDValue V2, ArrayRef<int> Mask,
6898 SelectionDAG &DAG) {
6899 MVT EltVT = VT.getVectorElementType();
6900 int NumEltBits = EltVT.getSizeInBits();
6901 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6902 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6903 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6905 if (EltVT.isFloatingPoint()) {
6906 Zero = DAG.getBitcast(EltVT, Zero);
6907 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6909 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6910 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6912 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6915 if (Mask[i] % Size != i)
6916 return SDValue(); // Not a blend.
6918 V = Mask[i] < Size ? V1 : V2;
6919 else if (V != (Mask[i] < Size ? V1 : V2))
6920 return SDValue(); // Can only let one input through the mask.
6922 VMaskOps[i] = AllOnes;
6925 return SDValue(); // No non-zeroable elements!
6927 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6928 V = DAG.getNode(VT.isFloatingPoint()
6929 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6934 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6936 /// This is used as a fallback approach when first class blend instructions are
6937 /// unavailable. Currently it is only suitable for integer vectors, but could
6938 /// be generalized for floating point vectors if desirable.
6939 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6940 SDValue V2, ArrayRef<int> Mask,
6941 SelectionDAG &DAG) {
6942 assert(VT.isInteger() && "Only supports integer vector types!");
6943 MVT EltVT = VT.getVectorElementType();
6944 int NumEltBits = EltVT.getSizeInBits();
6945 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6946 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6948 SmallVector<SDValue, 16> MaskOps;
6949 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6950 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6951 return SDValue(); // Shuffled input!
6952 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6955 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6956 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6957 // We have to cast V2 around.
6958 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6959 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6960 DAG.getBitcast(MaskVT, V1Mask),
6961 DAG.getBitcast(MaskVT, V2)));
6962 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6965 /// \brief Try to emit a blend instruction for a shuffle.
6967 /// This doesn't do any checks for the availability of instructions for blending
6968 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6969 /// be matched in the backend with the type given. What it does check for is
6970 /// that the shuffle mask is a blend, or convertible into a blend with zero.
6971 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6972 SDValue V2, ArrayRef<int> Original,
6973 const X86Subtarget *Subtarget,
6974 SelectionDAG &DAG) {
6975 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6976 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6977 SmallVector<int, 8> Mask(Original.begin(), Original.end());
6978 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6979 bool ForceV1Zero = false, ForceV2Zero = false;
6981 // Attempt to generate the binary blend mask. If an input is zero then
6982 // we can use any lane.
6983 // TODO: generalize the zero matching to any scalar like isShuffleEquivalent.
6984 unsigned BlendMask = 0;
6985 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6991 if (M == i + Size) {
6992 BlendMask |= 1u << i;
7003 BlendMask |= 1u << i;
7008 return SDValue(); // Shuffled input!
7011 // Create a REAL zero vector - ISD::isBuildVectorAllZeros allows UNDEFs.
7013 V1 = getZeroVector(VT, Subtarget, DAG, DL);
7015 V2 = getZeroVector(VT, Subtarget, DAG, DL);
7017 auto ScaleBlendMask = [](unsigned BlendMask, int Size, int Scale) {
7018 unsigned ScaledMask = 0;
7019 for (int i = 0; i != Size; ++i)
7020 if (BlendMask & (1u << i))
7021 for (int j = 0; j != Scale; ++j)
7022 ScaledMask |= 1u << (i * Scale + j);
7026 switch (VT.SimpleTy) {
7031 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
7032 DAG.getConstant(BlendMask, DL, MVT::i8));
7036 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7040 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
7041 // that instruction.
7042 if (Subtarget->hasAVX2()) {
7043 // Scale the blend by the number of 32-bit dwords per element.
7044 int Scale = VT.getScalarSizeInBits() / 32;
7045 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7046 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
7047 V1 = DAG.getBitcast(BlendVT, V1);
7048 V2 = DAG.getBitcast(BlendVT, V2);
7049 return DAG.getBitcast(
7050 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
7051 DAG.getConstant(BlendMask, DL, MVT::i8)));
7055 // For integer shuffles we need to expand the mask and cast the inputs to
7056 // v8i16s prior to blending.
7057 int Scale = 8 / VT.getVectorNumElements();
7058 BlendMask = ScaleBlendMask(BlendMask, Mask.size(), Scale);
7059 V1 = DAG.getBitcast(MVT::v8i16, V1);
7060 V2 = DAG.getBitcast(MVT::v8i16, V2);
7061 return DAG.getBitcast(VT,
7062 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
7063 DAG.getConstant(BlendMask, DL, MVT::i8)));
7067 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
7068 SmallVector<int, 8> RepeatedMask;
7069 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
7070 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
7071 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
7073 for (int i = 0; i < 8; ++i)
7074 if (RepeatedMask[i] >= 16)
7075 BlendMask |= 1u << i;
7076 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
7077 DAG.getConstant(BlendMask, DL, MVT::i8));
7083 assert((VT.is128BitVector() || Subtarget->hasAVX2()) &&
7084 "256-bit byte-blends require AVX2 support!");
7086 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
7087 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
7090 // Scale the blend by the number of bytes per element.
7091 int Scale = VT.getScalarSizeInBits() / 8;
7093 // This form of blend is always done on bytes. Compute the byte vector
7095 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
7097 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7098 // mix of LLVM's code generator and the x86 backend. We tell the code
7099 // generator that boolean values in the elements of an x86 vector register
7100 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
7101 // mapping a select to operand #1, and 'false' mapping to operand #2. The
7102 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
7103 // of the element (the remaining are ignored) and 0 in that high bit would
7104 // mean operand #1 while 1 in the high bit would mean operand #2. So while
7105 // the LLVM model for boolean values in vector elements gets the relevant
7106 // bit set, it is set backwards and over constrained relative to x86's
7108 SmallVector<SDValue, 32> VSELECTMask;
7109 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7110 for (int j = 0; j < Scale; ++j)
7111 VSELECTMask.push_back(
7112 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
7113 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
7116 V1 = DAG.getBitcast(BlendVT, V1);
7117 V2 = DAG.getBitcast(BlendVT, V2);
7118 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
7119 DAG.getNode(ISD::BUILD_VECTOR, DL,
7120 BlendVT, VSELECTMask),
7125 llvm_unreachable("Not a supported integer vector type!");
7129 /// \brief Try to lower as a blend of elements from two inputs followed by
7130 /// a single-input permutation.
7132 /// This matches the pattern where we can blend elements from two inputs and
7133 /// then reduce the shuffle to a single-input permutation.
7134 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7137 SelectionDAG &DAG) {
7138 // We build up the blend mask while checking whether a blend is a viable way
7139 // to reduce the shuffle.
7140 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7141 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7143 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7147 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7149 if (BlendMask[Mask[i] % Size] == -1)
7150 BlendMask[Mask[i] % Size] = Mask[i];
7151 else if (BlendMask[Mask[i] % Size] != Mask[i])
7152 return SDValue(); // Can't blend in the needed input!
7154 PermuteMask[i] = Mask[i] % Size;
7157 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7158 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7161 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7162 /// blends and permutes.
7164 /// This matches the extremely common pattern for handling combined
7165 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7166 /// operations. It will try to pick the best arrangement of shuffles and
7168 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7172 SelectionDAG &DAG) {
7173 // Shuffle the input elements into the desired positions in V1 and V2 and
7174 // blend them together.
7175 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7176 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7177 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7178 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7179 if (Mask[i] >= 0 && Mask[i] < Size) {
7180 V1Mask[i] = Mask[i];
7182 } else if (Mask[i] >= Size) {
7183 V2Mask[i] = Mask[i] - Size;
7184 BlendMask[i] = i + Size;
7187 // Try to lower with the simpler initial blend strategy unless one of the
7188 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7189 // shuffle may be able to fold with a load or other benefit. However, when
7190 // we'll have to do 2x as many shuffles in order to achieve this, blending
7191 // first is a better strategy.
7192 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7193 if (SDValue BlendPerm =
7194 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7197 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7198 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7199 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7202 /// \brief Try to lower a vector shuffle as a byte rotation.
7204 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7205 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7206 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7207 /// try to generically lower a vector shuffle through such an pattern. It
7208 /// does not check for the profitability of lowering either as PALIGNR or
7209 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7210 /// This matches shuffle vectors that look like:
7212 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7214 /// Essentially it concatenates V1 and V2, shifts right by some number of
7215 /// elements, and takes the low elements as the result. Note that while this is
7216 /// specified as a *right shift* because x86 is little-endian, it is a *left
7217 /// rotate* of the vector lanes.
7218 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7221 const X86Subtarget *Subtarget,
7222 SelectionDAG &DAG) {
7223 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7225 int NumElts = Mask.size();
7226 int NumLanes = VT.getSizeInBits() / 128;
7227 int NumLaneElts = NumElts / NumLanes;
7229 // We need to detect various ways of spelling a rotation:
7230 // [11, 12, 13, 14, 15, 0, 1, 2]
7231 // [-1, 12, 13, 14, -1, -1, 1, -1]
7232 // [-1, -1, -1, -1, -1, -1, 1, 2]
7233 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7234 // [-1, 4, 5, 6, -1, -1, 9, -1]
7235 // [-1, 4, 5, 6, -1, -1, -1, -1]
7238 for (int l = 0; l < NumElts; l += NumLaneElts) {
7239 for (int i = 0; i < NumLaneElts; ++i) {
7240 if (Mask[l + i] == -1)
7242 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7244 // Get the mod-Size index and lane correct it.
7245 int LaneIdx = (Mask[l + i] % NumElts) - l;
7246 // Make sure it was in this lane.
7247 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7250 // Determine where a rotated vector would have started.
7251 int StartIdx = i - LaneIdx;
7253 // The identity rotation isn't interesting, stop.
7256 // If we found the tail of a vector the rotation must be the missing
7257 // front. If we found the head of a vector, it must be how much of the
7259 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7262 Rotation = CandidateRotation;
7263 else if (Rotation != CandidateRotation)
7264 // The rotations don't match, so we can't match this mask.
7267 // Compute which value this mask is pointing at.
7268 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7270 // Compute which of the two target values this index should be assigned
7271 // to. This reflects whether the high elements are remaining or the low
7272 // elements are remaining.
7273 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7275 // Either set up this value if we've not encountered it before, or check
7276 // that it remains consistent.
7279 else if (TargetV != MaskV)
7280 // This may be a rotation, but it pulls from the inputs in some
7281 // unsupported interleaving.
7286 // Check that we successfully analyzed the mask, and normalize the results.
7287 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7288 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7294 // The actual rotate instruction rotates bytes, so we need to scale the
7295 // rotation based on how many bytes are in the vector lane.
7296 int Scale = 16 / NumLaneElts;
7298 // SSSE3 targets can use the palignr instruction.
7299 if (Subtarget->hasSSSE3()) {
7300 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7301 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7302 Lo = DAG.getBitcast(AlignVT, Lo);
7303 Hi = DAG.getBitcast(AlignVT, Hi);
7305 return DAG.getBitcast(
7306 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7307 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7310 assert(VT.is128BitVector() &&
7311 "Rotate-based lowering only supports 128-bit lowering!");
7312 assert(Mask.size() <= 16 &&
7313 "Can shuffle at most 16 bytes in a 128-bit vector!");
7315 // Default SSE2 implementation
7316 int LoByteShift = 16 - Rotation * Scale;
7317 int HiByteShift = Rotation * Scale;
7319 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7320 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7321 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7323 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7324 DAG.getConstant(LoByteShift, DL, MVT::i8));
7325 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7326 DAG.getConstant(HiByteShift, DL, MVT::i8));
7327 return DAG.getBitcast(VT,
7328 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7331 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7333 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7334 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7335 /// matches elements from one of the input vectors shuffled to the left or
7336 /// right with zeroable elements 'shifted in'. It handles both the strictly
7337 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7340 /// PSHL : (little-endian) left bit shift.
7341 /// [ zz, 0, zz, 2 ]
7342 /// [ -1, 4, zz, -1 ]
7343 /// PSRL : (little-endian) right bit shift.
7345 /// [ -1, -1, 7, zz]
7346 /// PSLLDQ : (little-endian) left byte shift
7347 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7348 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7349 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7350 /// PSRLDQ : (little-endian) right byte shift
7351 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7352 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7353 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7354 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7355 SDValue V2, ArrayRef<int> Mask,
7356 SelectionDAG &DAG) {
7357 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7359 int Size = Mask.size();
7360 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7362 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7363 for (int i = 0; i < Size; i += Scale)
7364 for (int j = 0; j < Shift; ++j)
7365 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7371 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7372 for (int i = 0; i != Size; i += Scale) {
7373 unsigned Pos = Left ? i + Shift : i;
7374 unsigned Low = Left ? i : i + Shift;
7375 unsigned Len = Scale - Shift;
7376 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7377 Low + (V == V1 ? 0 : Size)))
7381 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7382 bool ByteShift = ShiftEltBits > 64;
7383 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7384 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7385 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7387 // Normalize the scale for byte shifts to still produce an i64 element
7389 Scale = ByteShift ? Scale / 2 : Scale;
7391 // We need to round trip through the appropriate type for the shift.
7392 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7393 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7394 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7395 "Illegal integer vector type");
7396 V = DAG.getBitcast(ShiftVT, V);
7398 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7399 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7400 return DAG.getBitcast(VT, V);
7403 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7404 // keep doubling the size of the integer elements up to that. We can
7405 // then shift the elements of the integer vector by whole multiples of
7406 // their width within the elements of the larger integer vector. Test each
7407 // multiple to see if we can find a match with the moved element indices
7408 // and that the shifted in elements are all zeroable.
7409 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7410 for (int Shift = 1; Shift != Scale; ++Shift)
7411 for (bool Left : {true, false})
7412 if (CheckZeros(Shift, Scale, Left))
7413 for (SDValue V : {V1, V2})
7414 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7421 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7422 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7423 SDValue V2, ArrayRef<int> Mask,
7424 SelectionDAG &DAG) {
7425 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7426 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7428 int Size = Mask.size();
7429 int HalfSize = Size / 2;
7430 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7432 // Upper half must be undefined.
7433 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7436 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7437 // Remainder of lower half result is zero and upper half is all undef.
7438 auto LowerAsEXTRQ = [&]() {
7439 // Determine the extraction length from the part of the
7440 // lower half that isn't zeroable.
7442 for (; Len > 0; --Len)
7443 if (!Zeroable[Len - 1])
7445 assert(Len > 0 && "Zeroable shuffle mask");
7447 // Attempt to match first Len sequential elements from the lower half.
7450 for (int i = 0; i != Len; ++i) {
7454 SDValue &V = (M < Size ? V1 : V2);
7457 // The extracted elements must start at a valid index and all mask
7458 // elements must be in the lower half.
7459 if (i > M || M >= HalfSize)
7462 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7473 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7474 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7475 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7476 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7477 DAG.getConstant(BitLen, DL, MVT::i8),
7478 DAG.getConstant(BitIdx, DL, MVT::i8));
7481 if (SDValue ExtrQ = LowerAsEXTRQ())
7484 // INSERTQ: Extract lowest Len elements from lower half of second source and
7485 // insert over first source, starting at Idx.
7486 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7487 auto LowerAsInsertQ = [&]() {
7488 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7491 // Attempt to match first source from mask before insertion point.
7492 if (isUndefInRange(Mask, 0, Idx)) {
7494 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7496 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7502 // Extend the extraction length looking to match both the insertion of
7503 // the second source and the remaining elements of the first.
7504 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7509 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7511 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7517 // Match the remaining elements of the lower half.
7518 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7520 } else if ((!Base || (Base == V1)) &&
7521 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7523 } else if ((!Base || (Base == V2)) &&
7524 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7531 // We may not have a base (first source) - this can safely be undefined.
7533 Base = DAG.getUNDEF(VT);
7535 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7536 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7537 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7538 DAG.getConstant(BitLen, DL, MVT::i8),
7539 DAG.getConstant(BitIdx, DL, MVT::i8));
7546 if (SDValue InsertQ = LowerAsInsertQ())
7552 /// \brief Lower a vector shuffle as a zero or any extension.
7554 /// Given a specific number of elements, element bit width, and extension
7555 /// stride, produce either a zero or any extension based on the available
7556 /// features of the subtarget. The extended elements are consecutive and
7557 /// begin and can start from an offseted element index in the input; to
7558 /// avoid excess shuffling the offset must either being in the bottom lane
7559 /// or at the start of a higher lane. All extended elements must be from
7561 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7562 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7563 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7564 assert(Scale > 1 && "Need a scale to extend.");
7565 int EltBits = VT.getScalarSizeInBits();
7566 int NumElements = VT.getVectorNumElements();
7567 int NumEltsPerLane = 128 / EltBits;
7568 int OffsetLane = Offset / NumEltsPerLane;
7569 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7570 "Only 8, 16, and 32 bit elements can be extended.");
7571 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7572 assert(0 <= Offset && "Extension offset must be positive.");
7573 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7574 "Extension offset must be in the first lane or start an upper lane.");
7576 // Check that an index is in same lane as the base offset.
7577 auto SafeOffset = [&](int Idx) {
7578 return OffsetLane == (Idx / NumEltsPerLane);
7581 // Shift along an input so that the offset base moves to the first element.
7582 auto ShuffleOffset = [&](SDValue V) {
7586 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7587 for (int i = 0; i * Scale < NumElements; ++i) {
7588 int SrcIdx = i + Offset;
7589 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7591 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7594 // Found a valid zext mask! Try various lowering strategies based on the
7595 // input type and available ISA extensions.
7596 if (Subtarget->hasSSE41()) {
7597 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7598 // PUNPCK will catch this in a later shuffle match.
7599 if (Offset && Scale == 2 && VT.is128BitVector())
7601 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7602 NumElements / Scale);
7603 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7604 return DAG.getBitcast(VT, InputV);
7607 assert(VT.is128BitVector() && "Only 128-bit vectors can be extended.");
7609 // For any extends we can cheat for larger element sizes and use shuffle
7610 // instructions that can fold with a load and/or copy.
7611 if (AnyExt && EltBits == 32) {
7612 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7614 return DAG.getBitcast(
7615 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7616 DAG.getBitcast(MVT::v4i32, InputV),
7617 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7619 if (AnyExt && EltBits == 16 && Scale > 2) {
7620 int PSHUFDMask[4] = {Offset / 2, -1,
7621 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7622 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7623 DAG.getBitcast(MVT::v4i32, InputV),
7624 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7625 int PSHUFWMask[4] = {1, -1, -1, -1};
7626 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7627 return DAG.getBitcast(
7628 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7629 DAG.getBitcast(MVT::v8i16, InputV),
7630 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7633 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7635 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7636 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7637 assert(VT.is128BitVector() && "Unexpected vector width!");
7639 int LoIdx = Offset * EltBits;
7640 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7641 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7642 DAG.getConstant(EltBits, DL, MVT::i8),
7643 DAG.getConstant(LoIdx, DL, MVT::i8)));
7645 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7646 !SafeOffset(Offset + 1))
7647 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7649 int HiIdx = (Offset + 1) * EltBits;
7650 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7651 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7652 DAG.getConstant(EltBits, DL, MVT::i8),
7653 DAG.getConstant(HiIdx, DL, MVT::i8)));
7654 return DAG.getNode(ISD::BITCAST, DL, VT,
7655 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7658 // If this would require more than 2 unpack instructions to expand, use
7659 // pshufb when available. We can only use more than 2 unpack instructions
7660 // when zero extending i8 elements which also makes it easier to use pshufb.
7661 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7662 assert(NumElements == 16 && "Unexpected byte vector width!");
7663 SDValue PSHUFBMask[16];
7664 for (int i = 0; i < 16; ++i) {
7665 int Idx = Offset + (i / Scale);
7666 PSHUFBMask[i] = DAG.getConstant(
7667 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7669 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7670 return DAG.getBitcast(VT,
7671 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7672 DAG.getNode(ISD::BUILD_VECTOR, DL,
7673 MVT::v16i8, PSHUFBMask)));
7676 // If we are extending from an offset, ensure we start on a boundary that
7677 // we can unpack from.
7678 int AlignToUnpack = Offset % (NumElements / Scale);
7679 if (AlignToUnpack) {
7680 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7681 for (int i = AlignToUnpack; i < NumElements; ++i)
7682 ShMask[i - AlignToUnpack] = i;
7683 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7684 Offset -= AlignToUnpack;
7687 // Otherwise emit a sequence of unpacks.
7689 unsigned UnpackLoHi = X86ISD::UNPCKL;
7690 if (Offset >= (NumElements / 2)) {
7691 UnpackLoHi = X86ISD::UNPCKH;
7692 Offset -= (NumElements / 2);
7695 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7696 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7697 : getZeroVector(InputVT, Subtarget, DAG, DL);
7698 InputV = DAG.getBitcast(InputVT, InputV);
7699 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7703 } while (Scale > 1);
7704 return DAG.getBitcast(VT, InputV);
7707 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7709 /// This routine will try to do everything in its power to cleverly lower
7710 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7711 /// check for the profitability of this lowering, it tries to aggressively
7712 /// match this pattern. It will use all of the micro-architectural details it
7713 /// can to emit an efficient lowering. It handles both blends with all-zero
7714 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7715 /// masking out later).
7717 /// The reason we have dedicated lowering for zext-style shuffles is that they
7718 /// are both incredibly common and often quite performance sensitive.
7719 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7720 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7721 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7722 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7724 int Bits = VT.getSizeInBits();
7725 int NumLanes = Bits / 128;
7726 int NumElements = VT.getVectorNumElements();
7727 int NumEltsPerLane = NumElements / NumLanes;
7728 assert(VT.getScalarSizeInBits() <= 32 &&
7729 "Exceeds 32-bit integer zero extension limit");
7730 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7732 // Define a helper function to check a particular ext-scale and lower to it if
7734 auto Lower = [&](int Scale) -> SDValue {
7739 for (int i = 0; i < NumElements; ++i) {
7742 continue; // Valid anywhere but doesn't tell us anything.
7743 if (i % Scale != 0) {
7744 // Each of the extended elements need to be zeroable.
7748 // We no longer are in the anyext case.
7753 // Each of the base elements needs to be consecutive indices into the
7754 // same input vector.
7755 SDValue V = M < NumElements ? V1 : V2;
7756 M = M % NumElements;
7759 Offset = M - (i / Scale);
7760 } else if (InputV != V)
7761 return SDValue(); // Flip-flopping inputs.
7763 // Offset must start in the lowest 128-bit lane or at the start of an
7765 // FIXME: Is it ever worth allowing a negative base offset?
7766 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7767 (Offset % NumEltsPerLane) == 0))
7770 // If we are offsetting, all referenced entries must come from the same
7772 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7775 if ((M % NumElements) != (Offset + (i / Scale)))
7776 return SDValue(); // Non-consecutive strided elements.
7780 // If we fail to find an input, we have a zero-shuffle which should always
7781 // have already been handled.
7782 // FIXME: Maybe handle this here in case during blending we end up with one?
7786 // If we are offsetting, don't extend if we only match a single input, we
7787 // can always do better by using a basic PSHUF or PUNPCK.
7788 if (Offset != 0 && Matches < 2)
7791 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7792 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7795 // The widest scale possible for extending is to a 64-bit integer.
7796 assert(Bits % 64 == 0 &&
7797 "The number of bits in a vector must be divisible by 64 on x86!");
7798 int NumExtElements = Bits / 64;
7800 // Each iteration, try extending the elements half as much, but into twice as
7802 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7803 assert(NumElements % NumExtElements == 0 &&
7804 "The input vector size must be divisible by the extended size.");
7805 if (SDValue V = Lower(NumElements / NumExtElements))
7809 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7813 // Returns one of the source operands if the shuffle can be reduced to a
7814 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7815 auto CanZExtLowHalf = [&]() {
7816 for (int i = NumElements / 2; i != NumElements; ++i)
7819 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7821 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7826 if (SDValue V = CanZExtLowHalf()) {
7827 V = DAG.getBitcast(MVT::v2i64, V);
7828 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7829 return DAG.getBitcast(VT, V);
7832 // No viable ext lowering found.
7836 /// \brief Try to get a scalar value for a specific element of a vector.
7838 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7839 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7840 SelectionDAG &DAG) {
7841 MVT VT = V.getSimpleValueType();
7842 MVT EltVT = VT.getVectorElementType();
7843 while (V.getOpcode() == ISD::BITCAST)
7844 V = V.getOperand(0);
7845 // If the bitcasts shift the element size, we can't extract an equivalent
7847 MVT NewVT = V.getSimpleValueType();
7848 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7851 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7852 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7853 // Ensure the scalar operand is the same size as the destination.
7854 // FIXME: Add support for scalar truncation where possible.
7855 SDValue S = V.getOperand(Idx);
7856 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7857 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7863 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7865 /// This is particularly important because the set of instructions varies
7866 /// significantly based on whether the operand is a load or not.
7867 static bool isShuffleFoldableLoad(SDValue V) {
7868 while (V.getOpcode() == ISD::BITCAST)
7869 V = V.getOperand(0);
7871 return ISD::isNON_EXTLoad(V.getNode());
7874 /// \brief Try to lower insertion of a single element into a zero vector.
7876 /// This is a common pattern that we have especially efficient patterns to lower
7877 /// across all subtarget feature sets.
7878 static SDValue lowerVectorShuffleAsElementInsertion(
7879 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7880 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7881 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7883 MVT EltVT = VT.getVectorElementType();
7885 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7886 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7888 bool IsV1Zeroable = true;
7889 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7890 if (i != V2Index && !Zeroable[i]) {
7891 IsV1Zeroable = false;
7895 // Check for a single input from a SCALAR_TO_VECTOR node.
7896 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7897 // all the smarts here sunk into that routine. However, the current
7898 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7899 // vector shuffle lowering is dead.
7900 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7902 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7903 // We need to zext the scalar if it is smaller than an i32.
7904 V2S = DAG.getBitcast(EltVT, V2S);
7905 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7906 // Using zext to expand a narrow element won't work for non-zero
7911 // Zero-extend directly to i32.
7913 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7915 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7916 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7917 EltVT == MVT::i16) {
7918 // Either not inserting from the low element of the input or the input
7919 // element size is too small to use VZEXT_MOVL to clear the high bits.
7923 if (!IsV1Zeroable) {
7924 // If V1 can't be treated as a zero vector we have fewer options to lower
7925 // this. We can't support integer vectors or non-zero targets cheaply, and
7926 // the V1 elements can't be permuted in any way.
7927 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7928 if (!VT.isFloatingPoint() || V2Index != 0)
7930 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7931 V1Mask[V2Index] = -1;
7932 if (!isNoopShuffleMask(V1Mask))
7934 // This is essentially a special case blend operation, but if we have
7935 // general purpose blend operations, they are always faster. Bail and let
7936 // the rest of the lowering handle these as blends.
7937 if (Subtarget->hasSSE41())
7940 // Otherwise, use MOVSD or MOVSS.
7941 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7942 "Only two types of floating point element types to handle!");
7943 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7947 // This lowering only works for the low element with floating point vectors.
7948 if (VT.isFloatingPoint() && V2Index != 0)
7951 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7953 V2 = DAG.getBitcast(VT, V2);
7956 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7957 // the desired position. Otherwise it is more efficient to do a vector
7958 // shift left. We know that we can do a vector shift left because all
7959 // the inputs are zero.
7960 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7961 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7962 V2Shuffle[V2Index] = 0;
7963 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7965 V2 = DAG.getBitcast(MVT::v2i64, V2);
7967 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7968 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7969 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7970 DAG.getDataLayout(), VT)));
7971 V2 = DAG.getBitcast(VT, V2);
7977 /// \brief Try to lower broadcast of a single - truncated - integer element,
7978 /// coming from a scalar_to_vector/build_vector node \p V0 with larger elements.
7980 /// This assumes we have AVX2.
7981 static SDValue lowerVectorShuffleAsTruncBroadcast(SDLoc DL, MVT VT, SDValue V0,
7983 const X86Subtarget *Subtarget,
7984 SelectionDAG &DAG) {
7985 assert(Subtarget->hasAVX2() &&
7986 "We can only lower integer broadcasts with AVX2!");
7988 EVT EltVT = VT.getVectorElementType();
7989 EVT V0VT = V0.getValueType();
7991 assert(VT.isInteger() && "Unexpected non-integer trunc broadcast!");
7992 assert(V0VT.isVector() && "Unexpected non-vector vector-sized value!");
7994 EVT V0EltVT = V0VT.getVectorElementType();
7995 if (!V0EltVT.isInteger())
7998 const unsigned EltSize = EltVT.getSizeInBits();
7999 const unsigned V0EltSize = V0EltVT.getSizeInBits();
8001 // This is only a truncation if the original element type is larger.
8002 if (V0EltSize <= EltSize)
8005 assert(((V0EltSize % EltSize) == 0) &&
8006 "Scalar type sizes must all be powers of 2 on x86!");
8008 const unsigned V0Opc = V0.getOpcode();
8009 const unsigned Scale = V0EltSize / EltSize;
8010 const unsigned V0BroadcastIdx = BroadcastIdx / Scale;
8012 if ((V0Opc != ISD::SCALAR_TO_VECTOR || V0BroadcastIdx != 0) &&
8013 V0Opc != ISD::BUILD_VECTOR)
8016 SDValue Scalar = V0.getOperand(V0BroadcastIdx);
8018 // If we're extracting non-least-significant bits, shift so we can truncate.
8019 // Hopefully, we can fold away the trunc/srl/load into the broadcast.
8020 // Even if we can't (and !isShuffleFoldableLoad(Scalar)), prefer
8021 // vpbroadcast+vmovd+shr to vpshufb(m)+vmovd.
8022 if (const int OffsetIdx = BroadcastIdx % Scale)
8023 Scalar = DAG.getNode(ISD::SRL, DL, Scalar.getValueType(), Scalar,
8024 DAG.getConstant(OffsetIdx * EltSize, DL, Scalar.getValueType()));
8026 return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
8027 DAG.getNode(ISD::TRUNCATE, DL, EltVT, Scalar));
8030 /// \brief Try to lower broadcast of a single element.
8032 /// For convenience, this code also bundles all of the subtarget feature set
8033 /// filtering. While a little annoying to re-dispatch on type here, there isn't
8034 /// a convenient way to factor it out.
8035 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
8037 const X86Subtarget *Subtarget,
8038 SelectionDAG &DAG) {
8039 if (!Subtarget->hasAVX())
8041 if (VT.isInteger() && !Subtarget->hasAVX2())
8044 // Check that the mask is a broadcast.
8045 int BroadcastIdx = -1;
8047 if (M >= 0 && BroadcastIdx == -1)
8049 else if (M >= 0 && M != BroadcastIdx)
8052 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
8053 "a sorted mask where the broadcast "
8056 // Go up the chain of (vector) values to find a scalar load that we can
8057 // combine with the broadcast.
8059 switch (V.getOpcode()) {
8060 case ISD::CONCAT_VECTORS: {
8061 int OperandSize = Mask.size() / V.getNumOperands();
8062 V = V.getOperand(BroadcastIdx / OperandSize);
8063 BroadcastIdx %= OperandSize;
8067 case ISD::INSERT_SUBVECTOR: {
8068 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
8069 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
8073 int BeginIdx = (int)ConstantIdx->getZExtValue();
8075 BeginIdx + (int)VInner.getSimpleValueType().getVectorNumElements();
8076 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
8077 BroadcastIdx -= BeginIdx;
8088 // Check if this is a broadcast of a scalar. We special case lowering
8089 // for scalars so that we can more effectively fold with loads.
8090 // First, look through bitcast: if the original value has a larger element
8091 // type than the shuffle, the broadcast element is in essence truncated.
8092 // Make that explicit to ease folding.
8093 if (V.getOpcode() == ISD::BITCAST && VT.isInteger())
8094 if (SDValue TruncBroadcast = lowerVectorShuffleAsTruncBroadcast(
8095 DL, VT, V.getOperand(0), BroadcastIdx, Subtarget, DAG))
8096 return TruncBroadcast;
8098 // Also check the simpler case, where we can directly reuse the scalar.
8099 if (V.getOpcode() == ISD::BUILD_VECTOR ||
8100 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
8101 V = V.getOperand(BroadcastIdx);
8103 // If the scalar isn't a load, we can't broadcast from it in AVX1.
8104 // Only AVX2 has register broadcasts.
8105 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
8107 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
8108 // We can't broadcast from a vector register without AVX2, and we can only
8109 // broadcast from the zero-element of a vector register.
8113 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
8116 // Check for whether we can use INSERTPS to perform the shuffle. We only use
8117 // INSERTPS when the V1 elements are already in the correct locations
8118 // because otherwise we can just always use two SHUFPS instructions which
8119 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
8120 // perform INSERTPS if a single V1 element is out of place and all V2
8121 // elements are zeroable.
8122 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
8124 SelectionDAG &DAG) {
8125 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8126 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8127 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8128 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8130 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8133 int V1DstIndex = -1;
8134 int V2DstIndex = -1;
8135 bool V1UsedInPlace = false;
8137 for (int i = 0; i < 4; ++i) {
8138 // Synthesize a zero mask from the zeroable elements (includes undefs).
8144 // Flag if we use any V1 inputs in place.
8146 V1UsedInPlace = true;
8150 // We can only insert a single non-zeroable element.
8151 if (V1DstIndex != -1 || V2DstIndex != -1)
8155 // V1 input out of place for insertion.
8158 // V2 input for insertion.
8163 // Don't bother if we have no (non-zeroable) element for insertion.
8164 if (V1DstIndex == -1 && V2DstIndex == -1)
8167 // Determine element insertion src/dst indices. The src index is from the
8168 // start of the inserted vector, not the start of the concatenated vector.
8169 unsigned V2SrcIndex = 0;
8170 if (V1DstIndex != -1) {
8171 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8172 // and don't use the original V2 at all.
8173 V2SrcIndex = Mask[V1DstIndex];
8174 V2DstIndex = V1DstIndex;
8177 V2SrcIndex = Mask[V2DstIndex] - 4;
8180 // If no V1 inputs are used in place, then the result is created only from
8181 // the zero mask and the V2 insertion - so remove V1 dependency.
8183 V1 = DAG.getUNDEF(MVT::v4f32);
8185 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8186 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8188 // Insert the V2 element into the desired position.
8190 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8191 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8194 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8195 /// UNPCK instruction.
8197 /// This specifically targets cases where we end up with alternating between
8198 /// the two inputs, and so can permute them into something that feeds a single
8199 /// UNPCK instruction. Note that this routine only targets integer vectors
8200 /// because for floating point vectors we have a generalized SHUFPS lowering
8201 /// strategy that handles everything that doesn't *exactly* match an unpack,
8202 /// making this clever lowering unnecessary.
8203 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8204 SDValue V1, SDValue V2,
8206 SelectionDAG &DAG) {
8207 assert(!VT.isFloatingPoint() &&
8208 "This routine only supports integer vectors.");
8209 assert(!isSingleInputShuffleMask(Mask) &&
8210 "This routine should only be used when blending two inputs.");
8211 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8213 int Size = Mask.size();
8215 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8216 return M >= 0 && M % Size < Size / 2;
8218 int NumHiInputs = std::count_if(
8219 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8221 bool UnpackLo = NumLoInputs >= NumHiInputs;
8223 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8224 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8225 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8227 for (int i = 0; i < Size; ++i) {
8231 // Each element of the unpack contains Scale elements from this mask.
8232 int UnpackIdx = i / Scale;
8234 // We only handle the case where V1 feeds the first slots of the unpack.
8235 // We rely on canonicalization to ensure this is the case.
8236 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8239 // Setup the mask for this input. The indexing is tricky as we have to
8240 // handle the unpack stride.
8241 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8242 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8246 // If we will have to shuffle both inputs to use the unpack, check whether
8247 // we can just unpack first and shuffle the result. If so, skip this unpack.
8248 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8249 !isNoopShuffleMask(V2Mask))
8252 // Shuffle the inputs into place.
8253 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8254 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8256 // Cast the inputs to the type we will use to unpack them.
8257 V1 = DAG.getBitcast(UnpackVT, V1);
8258 V2 = DAG.getBitcast(UnpackVT, V2);
8260 // Unpack the inputs and cast the result back to the desired type.
8261 return DAG.getBitcast(
8262 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8266 // We try each unpack from the largest to the smallest to try and find one
8267 // that fits this mask.
8268 int OrigNumElements = VT.getVectorNumElements();
8269 int OrigScalarSize = VT.getScalarSizeInBits();
8270 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8271 int Scale = ScalarSize / OrigScalarSize;
8272 int NumElements = OrigNumElements / Scale;
8273 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8274 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8278 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8280 if (NumLoInputs == 0 || NumHiInputs == 0) {
8281 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8282 "We have to have *some* inputs!");
8283 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8285 // FIXME: We could consider the total complexity of the permute of each
8286 // possible unpacking. Or at the least we should consider how many
8287 // half-crossings are created.
8288 // FIXME: We could consider commuting the unpacks.
8290 SmallVector<int, 32> PermMask;
8291 PermMask.assign(Size, -1);
8292 for (int i = 0; i < Size; ++i) {
8296 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8299 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8301 return DAG.getVectorShuffle(
8302 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8304 DAG.getUNDEF(VT), PermMask);
8310 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8312 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8313 /// support for floating point shuffles but not integer shuffles. These
8314 /// instructions will incur a domain crossing penalty on some chips though so
8315 /// it is better to avoid lowering through this for integer vectors where
8317 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8318 const X86Subtarget *Subtarget,
8319 SelectionDAG &DAG) {
8321 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8322 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8323 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8324 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8325 ArrayRef<int> Mask = SVOp->getMask();
8326 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8328 if (isSingleInputShuffleMask(Mask)) {
8329 // Use low duplicate instructions for masks that match their pattern.
8330 if (Subtarget->hasSSE3())
8331 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8332 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8334 // Straight shuffle of a single input vector. Simulate this by using the
8335 // single input as both of the "inputs" to this instruction..
8336 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8338 if (Subtarget->hasAVX()) {
8339 // If we have AVX, we can use VPERMILPS which will allow folding a load
8340 // into the shuffle.
8341 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8342 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8345 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8346 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8348 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8349 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8351 // If we have a single input, insert that into V1 if we can do so cheaply.
8352 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8353 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8354 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8356 // Try inverting the insertion since for v2 masks it is easy to do and we
8357 // can't reliably sort the mask one way or the other.
8358 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8359 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8360 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8361 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8365 // Try to use one of the special instruction patterns to handle two common
8366 // blend patterns if a zero-blend above didn't work.
8367 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8368 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8369 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8370 // We can either use a special instruction to load over the low double or
8371 // to move just the low double.
8373 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8375 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8377 if (Subtarget->hasSSE41())
8378 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8382 // Use dedicated unpack instructions for masks that match their pattern.
8384 lowerVectorShuffleWithUNPCK(DL, MVT::v2f64, Mask, V1, V2, DAG))
8387 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8388 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8389 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8392 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8394 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8395 /// the integer unit to minimize domain crossing penalties. However, for blends
8396 /// it falls back to the floating point shuffle operation with appropriate bit
8398 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8399 const X86Subtarget *Subtarget,
8400 SelectionDAG &DAG) {
8402 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8403 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8404 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8405 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8406 ArrayRef<int> Mask = SVOp->getMask();
8407 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8409 if (isSingleInputShuffleMask(Mask)) {
8410 // Check for being able to broadcast a single element.
8411 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8412 Mask, Subtarget, DAG))
8415 // Straight shuffle of a single input vector. For everything from SSE2
8416 // onward this has a single fast instruction with no scary immediates.
8417 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8418 V1 = DAG.getBitcast(MVT::v4i32, V1);
8419 int WidenedMask[4] = {
8420 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8421 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8422 return DAG.getBitcast(
8424 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8425 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8427 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8428 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8429 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8430 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8432 // If we have a blend of two PACKUS operations an the blend aligns with the
8433 // low and half halves, we can just merge the PACKUS operations. This is
8434 // particularly important as it lets us merge shuffles that this routine itself
8436 auto GetPackNode = [](SDValue V) {
8437 while (V.getOpcode() == ISD::BITCAST)
8438 V = V.getOperand(0);
8440 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8442 if (SDValue V1Pack = GetPackNode(V1))
8443 if (SDValue V2Pack = GetPackNode(V2))
8444 return DAG.getBitcast(MVT::v2i64,
8445 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8446 Mask[0] == 0 ? V1Pack.getOperand(0)
8447 : V1Pack.getOperand(1),
8448 Mask[1] == 2 ? V2Pack.getOperand(0)
8449 : V2Pack.getOperand(1)));
8451 // Try to use shift instructions.
8453 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8456 // When loading a scalar and then shuffling it into a vector we can often do
8457 // the insertion cheaply.
8458 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8459 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8461 // Try inverting the insertion since for v2 masks it is easy to do and we
8462 // can't reliably sort the mask one way or the other.
8463 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8464 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8465 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8468 // We have different paths for blend lowering, but they all must use the
8469 // *exact* same predicate.
8470 bool IsBlendSupported = Subtarget->hasSSE41();
8471 if (IsBlendSupported)
8472 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8476 // Use dedicated unpack instructions for masks that match their pattern.
8478 lowerVectorShuffleWithUNPCK(DL, MVT::v2i64, Mask, V1, V2, DAG))
8481 // Try to use byte rotation instructions.
8482 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8483 if (Subtarget->hasSSSE3())
8484 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8485 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8488 // If we have direct support for blends, we should lower by decomposing into
8489 // a permute. That will be faster than the domain cross.
8490 if (IsBlendSupported)
8491 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8494 // We implement this with SHUFPD which is pretty lame because it will likely
8495 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8496 // However, all the alternatives are still more cycles and newer chips don't
8497 // have this problem. It would be really nice if x86 had better shuffles here.
8498 V1 = DAG.getBitcast(MVT::v2f64, V1);
8499 V2 = DAG.getBitcast(MVT::v2f64, V2);
8500 return DAG.getBitcast(MVT::v2i64,
8501 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8504 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8506 /// This is used to disable more specialized lowerings when the shufps lowering
8507 /// will happen to be efficient.
8508 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8509 // This routine only handles 128-bit shufps.
8510 assert(Mask.size() == 4 && "Unsupported mask size!");
8512 // To lower with a single SHUFPS we need to have the low half and high half
8513 // each requiring a single input.
8514 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8516 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8522 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8524 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8525 /// It makes no assumptions about whether this is the *best* lowering, it simply
8527 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8528 ArrayRef<int> Mask, SDValue V1,
8529 SDValue V2, SelectionDAG &DAG) {
8530 SDValue LowV = V1, HighV = V2;
8531 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8534 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8536 if (NumV2Elements == 1) {
8538 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8541 // Compute the index adjacent to V2Index and in the same half by toggling
8543 int V2AdjIndex = V2Index ^ 1;
8545 if (Mask[V2AdjIndex] == -1) {
8546 // Handles all the cases where we have a single V2 element and an undef.
8547 // This will only ever happen in the high lanes because we commute the
8548 // vector otherwise.
8550 std::swap(LowV, HighV);
8551 NewMask[V2Index] -= 4;
8553 // Handle the case where the V2 element ends up adjacent to a V1 element.
8554 // To make this work, blend them together as the first step.
8555 int V1Index = V2AdjIndex;
8556 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8557 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8558 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8560 // Now proceed to reconstruct the final blend as we have the necessary
8561 // high or low half formed.
8568 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8569 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8571 } else if (NumV2Elements == 2) {
8572 if (Mask[0] < 4 && Mask[1] < 4) {
8573 // Handle the easy case where we have V1 in the low lanes and V2 in the
8577 } else if (Mask[2] < 4 && Mask[3] < 4) {
8578 // We also handle the reversed case because this utility may get called
8579 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8580 // arrange things in the right direction.
8586 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8587 // trying to place elements directly, just blend them and set up the final
8588 // shuffle to place them.
8590 // The first two blend mask elements are for V1, the second two are for
8592 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8593 Mask[2] < 4 ? Mask[2] : Mask[3],
8594 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8595 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8596 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8597 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8599 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8602 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8603 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8604 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8605 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8608 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8609 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8612 /// \brief Lower 4-lane 32-bit floating point shuffles.
8614 /// Uses instructions exclusively from the floating point unit to minimize
8615 /// domain crossing penalties, as these are sufficient to implement all v4f32
8617 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8618 const X86Subtarget *Subtarget,
8619 SelectionDAG &DAG) {
8621 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8622 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8623 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8624 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8625 ArrayRef<int> Mask = SVOp->getMask();
8626 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8629 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8631 if (NumV2Elements == 0) {
8632 // Check for being able to broadcast a single element.
8633 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8634 Mask, Subtarget, DAG))
8637 // Use even/odd duplicate instructions for masks that match their pattern.
8638 if (Subtarget->hasSSE3()) {
8639 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8640 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8641 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8642 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8645 if (Subtarget->hasAVX()) {
8646 // If we have AVX, we can use VPERMILPS which will allow folding a load
8647 // into the shuffle.
8648 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8649 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8652 // Otherwise, use a straight shuffle of a single input vector. We pass the
8653 // input vector to both operands to simulate this with a SHUFPS.
8654 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8655 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8658 // There are special ways we can lower some single-element blends. However, we
8659 // have custom ways we can lower more complex single-element blends below that
8660 // we defer to if both this and BLENDPS fail to match, so restrict this to
8661 // when the V2 input is targeting element 0 of the mask -- that is the fast
8663 if (NumV2Elements == 1 && Mask[0] >= 4)
8664 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8665 Mask, Subtarget, DAG))
8668 if (Subtarget->hasSSE41()) {
8669 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8673 // Use INSERTPS if we can complete the shuffle efficiently.
8674 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8677 if (!isSingleSHUFPSMask(Mask))
8678 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8679 DL, MVT::v4f32, V1, V2, Mask, DAG))
8683 // Use dedicated unpack instructions for masks that match their pattern.
8685 lowerVectorShuffleWithUNPCK(DL, MVT::v4f32, Mask, V1, V2, DAG))
8688 // Otherwise fall back to a SHUFPS lowering strategy.
8689 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8692 /// \brief Lower 4-lane i32 vector shuffles.
8694 /// We try to handle these with integer-domain shuffles where we can, but for
8695 /// blends we use the floating point domain blend instructions.
8696 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8697 const X86Subtarget *Subtarget,
8698 SelectionDAG &DAG) {
8700 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8701 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8702 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8703 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8704 ArrayRef<int> Mask = SVOp->getMask();
8705 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8707 // Whenever we can lower this as a zext, that instruction is strictly faster
8708 // than any alternative. It also allows us to fold memory operands into the
8709 // shuffle in many cases.
8710 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8711 Mask, Subtarget, DAG))
8715 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8717 if (NumV2Elements == 0) {
8718 // Check for being able to broadcast a single element.
8719 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8720 Mask, Subtarget, DAG))
8723 // Straight shuffle of a single input vector. For everything from SSE2
8724 // onward this has a single fast instruction with no scary immediates.
8725 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8726 // but we aren't actually going to use the UNPCK instruction because doing
8727 // so prevents folding a load into this instruction or making a copy.
8728 const int UnpackLoMask[] = {0, 0, 1, 1};
8729 const int UnpackHiMask[] = {2, 2, 3, 3};
8730 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8731 Mask = UnpackLoMask;
8732 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8733 Mask = UnpackHiMask;
8735 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8736 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8739 // Try to use shift instructions.
8741 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8744 // There are special ways we can lower some single-element blends.
8745 if (NumV2Elements == 1)
8746 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8747 Mask, Subtarget, DAG))
8750 // We have different paths for blend lowering, but they all must use the
8751 // *exact* same predicate.
8752 bool IsBlendSupported = Subtarget->hasSSE41();
8753 if (IsBlendSupported)
8754 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8758 if (SDValue Masked =
8759 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8762 // Use dedicated unpack instructions for masks that match their pattern.
8764 lowerVectorShuffleWithUNPCK(DL, MVT::v4i32, Mask, V1, V2, DAG))
8767 // Try to use byte rotation instructions.
8768 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8769 if (Subtarget->hasSSSE3())
8770 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8771 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8774 // If we have direct support for blends, we should lower by decomposing into
8775 // a permute. That will be faster than the domain cross.
8776 if (IsBlendSupported)
8777 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8780 // Try to lower by permuting the inputs into an unpack instruction.
8781 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8785 // We implement this with SHUFPS because it can blend from two vectors.
8786 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8787 // up the inputs, bypassing domain shift penalties that we would encur if we
8788 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8790 return DAG.getBitcast(
8792 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8793 DAG.getBitcast(MVT::v4f32, V2), Mask));
8796 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8797 /// shuffle lowering, and the most complex part.
8799 /// The lowering strategy is to try to form pairs of input lanes which are
8800 /// targeted at the same half of the final vector, and then use a dword shuffle
8801 /// to place them onto the right half, and finally unpack the paired lanes into
8802 /// their final position.
8804 /// The exact breakdown of how to form these dword pairs and align them on the
8805 /// correct sides is really tricky. See the comments within the function for
8806 /// more of the details.
8808 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8809 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8810 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8811 /// vector, form the analogous 128-bit 8-element Mask.
8812 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8813 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8814 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8815 assert(VT.getVectorElementType() == MVT::i16 && "Bad input type!");
8816 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8818 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8819 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8820 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8822 SmallVector<int, 4> LoInputs;
8823 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8824 [](int M) { return M >= 0; });
8825 std::sort(LoInputs.begin(), LoInputs.end());
8826 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8827 SmallVector<int, 4> HiInputs;
8828 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8829 [](int M) { return M >= 0; });
8830 std::sort(HiInputs.begin(), HiInputs.end());
8831 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8833 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8834 int NumHToL = LoInputs.size() - NumLToL;
8836 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8837 int NumHToH = HiInputs.size() - NumLToH;
8838 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8839 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8840 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8841 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8843 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8844 // such inputs we can swap two of the dwords across the half mark and end up
8845 // with <=2 inputs to each half in each half. Once there, we can fall through
8846 // to the generic code below. For example:
8848 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8849 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8851 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8852 // and an existing 2-into-2 on the other half. In this case we may have to
8853 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8854 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8855 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8856 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8857 // half than the one we target for fixing) will be fixed when we re-enter this
8858 // path. We will also combine away any sequence of PSHUFD instructions that
8859 // result into a single instruction. Here is an example of the tricky case:
8861 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8862 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8864 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8866 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8867 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8869 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8870 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8872 // The result is fine to be handled by the generic logic.
8873 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8874 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8875 int AOffset, int BOffset) {
8876 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8877 "Must call this with A having 3 or 1 inputs from the A half.");
8878 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8879 "Must call this with B having 1 or 3 inputs from the B half.");
8880 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8881 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8883 bool ThreeAInputs = AToAInputs.size() == 3;
8885 // Compute the index of dword with only one word among the three inputs in
8886 // a half by taking the sum of the half with three inputs and subtracting
8887 // the sum of the actual three inputs. The difference is the remaining
8890 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8891 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8892 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8893 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8894 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8895 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8896 int TripleNonInputIdx =
8897 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8898 TripleDWord = TripleNonInputIdx / 2;
8900 // We use xor with one to compute the adjacent DWord to whichever one the
8902 OneInputDWord = (OneInput / 2) ^ 1;
8904 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8905 // and BToA inputs. If there is also such a problem with the BToB and AToB
8906 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8907 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8908 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8909 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8910 // Compute how many inputs will be flipped by swapping these DWords. We
8912 // to balance this to ensure we don't form a 3-1 shuffle in the other
8914 int NumFlippedAToBInputs =
8915 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8916 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8917 int NumFlippedBToBInputs =
8918 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8919 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8920 if ((NumFlippedAToBInputs == 1 &&
8921 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8922 (NumFlippedBToBInputs == 1 &&
8923 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8924 // We choose whether to fix the A half or B half based on whether that
8925 // half has zero flipped inputs. At zero, we may not be able to fix it
8926 // with that half. We also bias towards fixing the B half because that
8927 // will more commonly be the high half, and we have to bias one way.
8928 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8929 ArrayRef<int> Inputs) {
8930 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8931 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8932 PinnedIdx ^ 1) != Inputs.end();
8933 // Determine whether the free index is in the flipped dword or the
8934 // unflipped dword based on where the pinned index is. We use this bit
8935 // in an xor to conditionally select the adjacent dword.
8936 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8937 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8938 FixFreeIdx) != Inputs.end();
8939 if (IsFixIdxInput == IsFixFreeIdxInput)
8941 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8942 FixFreeIdx) != Inputs.end();
8943 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8944 "We need to be changing the number of flipped inputs!");
8945 int PSHUFHalfMask[] = {0, 1, 2, 3};
8946 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8947 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8949 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8952 if (M != -1 && M == FixIdx)
8954 else if (M != -1 && M == FixFreeIdx)
8957 if (NumFlippedBToBInputs != 0) {
8959 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8960 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8962 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8963 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8964 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8969 int PSHUFDMask[] = {0, 1, 2, 3};
8970 PSHUFDMask[ADWord] = BDWord;
8971 PSHUFDMask[BDWord] = ADWord;
8974 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8975 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8977 // Adjust the mask to match the new locations of A and B.
8979 if (M != -1 && M/2 == ADWord)
8980 M = 2 * BDWord + M % 2;
8981 else if (M != -1 && M/2 == BDWord)
8982 M = 2 * ADWord + M % 2;
8984 // Recurse back into this routine to re-compute state now that this isn't
8985 // a 3 and 1 problem.
8986 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8989 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8990 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8991 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8992 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8994 // At this point there are at most two inputs to the low and high halves from
8995 // each half. That means the inputs can always be grouped into dwords and
8996 // those dwords can then be moved to the correct half with a dword shuffle.
8997 // We use at most one low and one high word shuffle to collect these paired
8998 // inputs into dwords, and finally a dword shuffle to place them.
8999 int PSHUFLMask[4] = {-1, -1, -1, -1};
9000 int PSHUFHMask[4] = {-1, -1, -1, -1};
9001 int PSHUFDMask[4] = {-1, -1, -1, -1};
9003 // First fix the masks for all the inputs that are staying in their
9004 // original halves. This will then dictate the targets of the cross-half
9006 auto fixInPlaceInputs =
9007 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
9008 MutableArrayRef<int> SourceHalfMask,
9009 MutableArrayRef<int> HalfMask, int HalfOffset) {
9010 if (InPlaceInputs.empty())
9012 if (InPlaceInputs.size() == 1) {
9013 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9014 InPlaceInputs[0] - HalfOffset;
9015 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
9018 if (IncomingInputs.empty()) {
9019 // Just fix all of the in place inputs.
9020 for (int Input : InPlaceInputs) {
9021 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
9022 PSHUFDMask[Input / 2] = Input / 2;
9027 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
9028 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
9029 InPlaceInputs[0] - HalfOffset;
9030 // Put the second input next to the first so that they are packed into
9031 // a dword. We find the adjacent index by toggling the low bit.
9032 int AdjIndex = InPlaceInputs[0] ^ 1;
9033 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
9034 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
9035 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
9037 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
9038 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
9040 // Now gather the cross-half inputs and place them into a free dword of
9041 // their target half.
9042 // FIXME: This operation could almost certainly be simplified dramatically to
9043 // look more like the 3-1 fixing operation.
9044 auto moveInputsToRightHalf = [&PSHUFDMask](
9045 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
9046 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
9047 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
9049 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
9050 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
9052 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
9054 int LowWord = Word & ~1;
9055 int HighWord = Word | 1;
9056 return isWordClobbered(SourceHalfMask, LowWord) ||
9057 isWordClobbered(SourceHalfMask, HighWord);
9060 if (IncomingInputs.empty())
9063 if (ExistingInputs.empty()) {
9064 // Map any dwords with inputs from them into the right half.
9065 for (int Input : IncomingInputs) {
9066 // If the source half mask maps over the inputs, turn those into
9067 // swaps and use the swapped lane.
9068 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
9069 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
9070 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
9071 Input - SourceOffset;
9072 // We have to swap the uses in our half mask in one sweep.
9073 for (int &M : HalfMask)
9074 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
9076 else if (M == Input)
9077 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9079 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
9080 Input - SourceOffset &&
9081 "Previous placement doesn't match!");
9083 // Note that this correctly re-maps both when we do a swap and when
9084 // we observe the other side of the swap above. We rely on that to
9085 // avoid swapping the members of the input list directly.
9086 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
9089 // Map the input's dword into the correct half.
9090 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
9091 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
9093 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
9095 "Previous placement doesn't match!");
9098 // And just directly shift any other-half mask elements to be same-half
9099 // as we will have mirrored the dword containing the element into the
9100 // same position within that half.
9101 for (int &M : HalfMask)
9102 if (M >= SourceOffset && M < SourceOffset + 4) {
9103 M = M - SourceOffset + DestOffset;
9104 assert(M >= 0 && "This should never wrap below zero!");
9109 // Ensure we have the input in a viable dword of its current half. This
9110 // is particularly tricky because the original position may be clobbered
9111 // by inputs being moved and *staying* in that half.
9112 if (IncomingInputs.size() == 1) {
9113 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9114 int InputFixed = std::find(std::begin(SourceHalfMask),
9115 std::end(SourceHalfMask), -1) -
9116 std::begin(SourceHalfMask) + SourceOffset;
9117 SourceHalfMask[InputFixed - SourceOffset] =
9118 IncomingInputs[0] - SourceOffset;
9119 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
9121 IncomingInputs[0] = InputFixed;
9123 } else if (IncomingInputs.size() == 2) {
9124 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
9125 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
9126 // We have two non-adjacent or clobbered inputs we need to extract from
9127 // the source half. To do this, we need to map them into some adjacent
9128 // dword slot in the source mask.
9129 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
9130 IncomingInputs[1] - SourceOffset};
9132 // If there is a free slot in the source half mask adjacent to one of
9133 // the inputs, place the other input in it. We use (Index XOR 1) to
9134 // compute an adjacent index.
9135 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
9136 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
9137 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
9138 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9139 InputsFixed[1] = InputsFixed[0] ^ 1;
9140 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
9141 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
9142 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
9143 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
9144 InputsFixed[0] = InputsFixed[1] ^ 1;
9145 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
9146 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
9147 // The two inputs are in the same DWord but it is clobbered and the
9148 // adjacent DWord isn't used at all. Move both inputs to the free
9150 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
9151 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
9152 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
9153 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
9155 // The only way we hit this point is if there is no clobbering
9156 // (because there are no off-half inputs to this half) and there is no
9157 // free slot adjacent to one of the inputs. In this case, we have to
9158 // swap an input with a non-input.
9159 for (int i = 0; i < 4; ++i)
9160 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9161 "We can't handle any clobbers here!");
9162 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9163 "Cannot have adjacent inputs here!");
9165 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9166 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9168 // We also have to update the final source mask in this case because
9169 // it may need to undo the above swap.
9170 for (int &M : FinalSourceHalfMask)
9171 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9172 M = InputsFixed[1] + SourceOffset;
9173 else if (M == InputsFixed[1] + SourceOffset)
9174 M = (InputsFixed[0] ^ 1) + SourceOffset;
9176 InputsFixed[1] = InputsFixed[0] ^ 1;
9179 // Point everything at the fixed inputs.
9180 for (int &M : HalfMask)
9181 if (M == IncomingInputs[0])
9182 M = InputsFixed[0] + SourceOffset;
9183 else if (M == IncomingInputs[1])
9184 M = InputsFixed[1] + SourceOffset;
9186 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9187 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9190 llvm_unreachable("Unhandled input size!");
9193 // Now hoist the DWord down to the right half.
9194 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9195 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9196 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9197 for (int &M : HalfMask)
9198 for (int Input : IncomingInputs)
9200 M = FreeDWord * 2 + Input % 2;
9202 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9203 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9204 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9205 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9207 // Now enact all the shuffles we've computed to move the inputs into their
9209 if (!isNoopShuffleMask(PSHUFLMask))
9210 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9211 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9212 if (!isNoopShuffleMask(PSHUFHMask))
9213 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9214 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9215 if (!isNoopShuffleMask(PSHUFDMask))
9218 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9219 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9221 // At this point, each half should contain all its inputs, and we can then
9222 // just shuffle them into their final position.
9223 assert(std::count_if(LoMask.begin(), LoMask.end(),
9224 [](int M) { return M >= 4; }) == 0 &&
9225 "Failed to lift all the high half inputs to the low mask!");
9226 assert(std::count_if(HiMask.begin(), HiMask.end(),
9227 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9228 "Failed to lift all the low half inputs to the high mask!");
9230 // Do a half shuffle for the low mask.
9231 if (!isNoopShuffleMask(LoMask))
9232 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9233 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9235 // Do a half shuffle with the high mask after shifting its values down.
9236 for (int &M : HiMask)
9239 if (!isNoopShuffleMask(HiMask))
9240 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9241 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9246 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9247 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9248 SDValue V2, ArrayRef<int> Mask,
9249 SelectionDAG &DAG, bool &V1InUse,
9251 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9257 int Size = Mask.size();
9258 int Scale = 16 / Size;
9259 for (int i = 0; i < 16; ++i) {
9260 if (Mask[i / Scale] == -1) {
9261 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9263 const int ZeroMask = 0x80;
9264 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9266 int V2Idx = Mask[i / Scale] < Size
9268 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9269 if (Zeroable[i / Scale])
9270 V1Idx = V2Idx = ZeroMask;
9271 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9272 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9273 V1InUse |= (ZeroMask != V1Idx);
9274 V2InUse |= (ZeroMask != V2Idx);
9279 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9280 DAG.getBitcast(MVT::v16i8, V1),
9281 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9283 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9284 DAG.getBitcast(MVT::v16i8, V2),
9285 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9287 // If we need shuffled inputs from both, blend the two.
9289 if (V1InUse && V2InUse)
9290 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9292 V = V1InUse ? V1 : V2;
9294 // Cast the result back to the correct type.
9295 return DAG.getBitcast(VT, V);
9298 /// \brief Generic lowering of 8-lane i16 shuffles.
9300 /// This handles both single-input shuffles and combined shuffle/blends with
9301 /// two inputs. The single input shuffles are immediately delegated to
9302 /// a dedicated lowering routine.
9304 /// The blends are lowered in one of three fundamental ways. If there are few
9305 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9306 /// of the input is significantly cheaper when lowered as an interleaving of
9307 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9308 /// halves of the inputs separately (making them have relatively few inputs)
9309 /// and then concatenate them.
9310 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9311 const X86Subtarget *Subtarget,
9312 SelectionDAG &DAG) {
9314 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9315 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9316 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9317 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9318 ArrayRef<int> OrigMask = SVOp->getMask();
9319 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9320 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9321 MutableArrayRef<int> Mask(MaskStorage);
9323 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9325 // Whenever we can lower this as a zext, that instruction is strictly faster
9326 // than any alternative.
9327 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9328 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9331 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9333 auto isV2 = [](int M) { return M >= 8; };
9335 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9337 if (NumV2Inputs == 0) {
9338 // Check for being able to broadcast a single element.
9339 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9340 Mask, Subtarget, DAG))
9343 // Try to use shift instructions.
9345 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9348 // Use dedicated unpack instructions for masks that match their pattern.
9350 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9353 // Try to use byte rotation instructions.
9354 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9355 Mask, Subtarget, DAG))
9358 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9362 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9363 "All single-input shuffles should be canonicalized to be V1-input "
9366 // Try to use shift instructions.
9368 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9371 // See if we can use SSE4A Extraction / Insertion.
9372 if (Subtarget->hasSSE4A())
9373 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9376 // There are special ways we can lower some single-element blends.
9377 if (NumV2Inputs == 1)
9378 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9379 Mask, Subtarget, DAG))
9382 // We have different paths for blend lowering, but they all must use the
9383 // *exact* same predicate.
9384 bool IsBlendSupported = Subtarget->hasSSE41();
9385 if (IsBlendSupported)
9386 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9390 if (SDValue Masked =
9391 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9394 // Use dedicated unpack instructions for masks that match their pattern.
9396 lowerVectorShuffleWithUNPCK(DL, MVT::v8i16, Mask, V1, V2, DAG))
9399 // Try to use byte rotation instructions.
9400 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9401 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9404 if (SDValue BitBlend =
9405 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9408 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9412 // If we can't directly blend but can use PSHUFB, that will be better as it
9413 // can both shuffle and set up the inefficient blend.
9414 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9415 bool V1InUse, V2InUse;
9416 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9420 // We can always bit-blend if we have to so the fallback strategy is to
9421 // decompose into single-input permutes and blends.
9422 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9426 /// \brief Check whether a compaction lowering can be done by dropping even
9427 /// elements and compute how many times even elements must be dropped.
9429 /// This handles shuffles which take every Nth element where N is a power of
9430 /// two. Example shuffle masks:
9432 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9433 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9434 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9435 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9436 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9437 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9439 /// Any of these lanes can of course be undef.
9441 /// This routine only supports N <= 3.
9442 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9445 /// \returns N above, or the number of times even elements must be dropped if
9446 /// there is such a number. Otherwise returns zero.
9447 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9448 // Figure out whether we're looping over two inputs or just one.
9449 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9451 // The modulus for the shuffle vector entries is based on whether this is
9452 // a single input or not.
9453 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9454 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9455 "We should only be called with masks with a power-of-2 size!");
9457 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9459 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9460 // and 2^3 simultaneously. This is because we may have ambiguity with
9461 // partially undef inputs.
9462 bool ViableForN[3] = {true, true, true};
9464 for (int i = 0, e = Mask.size(); i < e; ++i) {
9465 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9470 bool IsAnyViable = false;
9471 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9472 if (ViableForN[j]) {
9475 // The shuffle mask must be equal to (i * 2^N) % M.
9476 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9479 ViableForN[j] = false;
9481 // Early exit if we exhaust the possible powers of two.
9486 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9490 // Return 0 as there is no viable power of two.
9494 /// \brief Generic lowering of v16i8 shuffles.
9496 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9497 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9498 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9499 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9501 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9502 const X86Subtarget *Subtarget,
9503 SelectionDAG &DAG) {
9505 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9506 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9507 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9508 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9509 ArrayRef<int> Mask = SVOp->getMask();
9510 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9512 // Try to use shift instructions.
9514 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9517 // Try to use byte rotation instructions.
9518 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9519 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9522 // Try to use a zext lowering.
9523 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9524 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9527 // See if we can use SSE4A Extraction / Insertion.
9528 if (Subtarget->hasSSE4A())
9529 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9533 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9535 // For single-input shuffles, there are some nicer lowering tricks we can use.
9536 if (NumV2Elements == 0) {
9537 // Check for being able to broadcast a single element.
9538 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9539 Mask, Subtarget, DAG))
9542 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9543 // Notably, this handles splat and partial-splat shuffles more efficiently.
9544 // However, it only makes sense if the pre-duplication shuffle simplifies
9545 // things significantly. Currently, this means we need to be able to
9546 // express the pre-duplication shuffle as an i16 shuffle.
9548 // FIXME: We should check for other patterns which can be widened into an
9549 // i16 shuffle as well.
9550 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9551 for (int i = 0; i < 16; i += 2)
9552 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9557 auto tryToWidenViaDuplication = [&]() -> SDValue {
9558 if (!canWidenViaDuplication(Mask))
9560 SmallVector<int, 4> LoInputs;
9561 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9562 [](int M) { return M >= 0 && M < 8; });
9563 std::sort(LoInputs.begin(), LoInputs.end());
9564 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9566 SmallVector<int, 4> HiInputs;
9567 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9568 [](int M) { return M >= 8; });
9569 std::sort(HiInputs.begin(), HiInputs.end());
9570 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9573 bool TargetLo = LoInputs.size() >= HiInputs.size();
9574 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9575 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9577 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9578 SmallDenseMap<int, int, 8> LaneMap;
9579 for (int I : InPlaceInputs) {
9580 PreDupI16Shuffle[I/2] = I/2;
9583 int j = TargetLo ? 0 : 4, je = j + 4;
9584 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9585 // Check if j is already a shuffle of this input. This happens when
9586 // there are two adjacent bytes after we move the low one.
9587 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9588 // If we haven't yet mapped the input, search for a slot into which
9590 while (j < je && PreDupI16Shuffle[j] != -1)
9594 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9597 // Map this input with the i16 shuffle.
9598 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9601 // Update the lane map based on the mapping we ended up with.
9602 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9604 V1 = DAG.getBitcast(
9606 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9607 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9609 // Unpack the bytes to form the i16s that will be shuffled into place.
9610 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9611 MVT::v16i8, V1, V1);
9613 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9614 for (int i = 0; i < 16; ++i)
9615 if (Mask[i] != -1) {
9616 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9617 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9618 if (PostDupI16Shuffle[i / 2] == -1)
9619 PostDupI16Shuffle[i / 2] = MappedMask;
9621 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9622 "Conflicting entrties in the original shuffle!");
9624 return DAG.getBitcast(
9626 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9627 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9629 if (SDValue V = tryToWidenViaDuplication())
9633 if (SDValue Masked =
9634 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9637 // Use dedicated unpack instructions for masks that match their pattern.
9639 lowerVectorShuffleWithUNPCK(DL, MVT::v16i8, Mask, V1, V2, DAG))
9642 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9643 // with PSHUFB. It is important to do this before we attempt to generate any
9644 // blends but after all of the single-input lowerings. If the single input
9645 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9646 // want to preserve that and we can DAG combine any longer sequences into
9647 // a PSHUFB in the end. But once we start blending from multiple inputs,
9648 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9649 // and there are *very* few patterns that would actually be faster than the
9650 // PSHUFB approach because of its ability to zero lanes.
9652 // FIXME: The only exceptions to the above are blends which are exact
9653 // interleavings with direct instructions supporting them. We currently don't
9654 // handle those well here.
9655 if (Subtarget->hasSSSE3()) {
9656 bool V1InUse = false;
9657 bool V2InUse = false;
9659 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9660 DAG, V1InUse, V2InUse);
9662 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9663 // do so. This avoids using them to handle blends-with-zero which is
9664 // important as a single pshufb is significantly faster for that.
9665 if (V1InUse && V2InUse) {
9666 if (Subtarget->hasSSE41())
9667 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9668 Mask, Subtarget, DAG))
9671 // We can use an unpack to do the blending rather than an or in some
9672 // cases. Even though the or may be (very minorly) more efficient, we
9673 // preference this lowering because there are common cases where part of
9674 // the complexity of the shuffles goes away when we do the final blend as
9676 // FIXME: It might be worth trying to detect if the unpack-feeding
9677 // shuffles will both be pshufb, in which case we shouldn't bother with
9679 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9680 DL, MVT::v16i8, V1, V2, Mask, DAG))
9687 // There are special ways we can lower some single-element blends.
9688 if (NumV2Elements == 1)
9689 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9690 Mask, Subtarget, DAG))
9693 if (SDValue BitBlend =
9694 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9697 // Check whether a compaction lowering can be done. This handles shuffles
9698 // which take every Nth element for some even N. See the helper function for
9701 // We special case these as they can be particularly efficiently handled with
9702 // the PACKUSB instruction on x86 and they show up in common patterns of
9703 // rearranging bytes to truncate wide elements.
9704 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9705 // NumEvenDrops is the power of two stride of the elements. Another way of
9706 // thinking about it is that we need to drop the even elements this many
9707 // times to get the original input.
9708 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9710 // First we need to zero all the dropped bytes.
9711 assert(NumEvenDrops <= 3 &&
9712 "No support for dropping even elements more than 3 times.");
9713 // We use the mask type to pick which bytes are preserved based on how many
9714 // elements are dropped.
9715 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9716 SDValue ByteClearMask = DAG.getBitcast(
9717 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9718 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9720 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9722 // Now pack things back together.
9723 V1 = DAG.getBitcast(MVT::v8i16, V1);
9724 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9725 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9726 for (int i = 1; i < NumEvenDrops; ++i) {
9727 Result = DAG.getBitcast(MVT::v8i16, Result);
9728 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9734 // Handle multi-input cases by blending single-input shuffles.
9735 if (NumV2Elements > 0)
9736 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9739 // The fallback path for single-input shuffles widens this into two v8i16
9740 // vectors with unpacks, shuffles those, and then pulls them back together
9744 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9745 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9746 for (int i = 0; i < 16; ++i)
9748 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9750 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9752 SDValue VLoHalf, VHiHalf;
9753 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9754 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9756 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9757 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9758 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9759 [](int M) { return M >= 0 && M % 2 == 1; })) {
9760 // Use a mask to drop the high bytes.
9761 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9762 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9763 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9765 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9766 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9768 // Squash the masks to point directly into VLoHalf.
9769 for (int &M : LoBlendMask)
9772 for (int &M : HiBlendMask)
9776 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9777 // VHiHalf so that we can blend them as i16s.
9778 VLoHalf = DAG.getBitcast(
9779 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9780 VHiHalf = DAG.getBitcast(
9781 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9784 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9785 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9787 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9790 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9792 /// This routine breaks down the specific type of 128-bit shuffle and
9793 /// dispatches to the lowering routines accordingly.
9794 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9795 MVT VT, const X86Subtarget *Subtarget,
9796 SelectionDAG &DAG) {
9797 switch (VT.SimpleTy) {
9799 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9801 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9803 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9805 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9807 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9809 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9812 llvm_unreachable("Unimplemented!");
9816 /// \brief Helper function to test whether a shuffle mask could be
9817 /// simplified by widening the elements being shuffled.
9819 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9820 /// leaves it in an unspecified state.
9822 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9823 /// shuffle masks. The latter have the special property of a '-2' representing
9824 /// a zero-ed lane of a vector.
9825 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9826 SmallVectorImpl<int> &WidenedMask) {
9827 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9828 // If both elements are undef, its trivial.
9829 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9830 WidenedMask.push_back(SM_SentinelUndef);
9834 // Check for an undef mask and a mask value properly aligned to fit with
9835 // a pair of values. If we find such a case, use the non-undef mask's value.
9836 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9837 WidenedMask.push_back(Mask[i + 1] / 2);
9840 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9841 WidenedMask.push_back(Mask[i] / 2);
9845 // When zeroing, we need to spread the zeroing across both lanes to widen.
9846 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9847 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9848 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9849 WidenedMask.push_back(SM_SentinelZero);
9855 // Finally check if the two mask values are adjacent and aligned with
9857 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9858 WidenedMask.push_back(Mask[i] / 2);
9862 // Otherwise we can't safely widen the elements used in this shuffle.
9865 assert(WidenedMask.size() == Mask.size() / 2 &&
9866 "Incorrect size of mask after widening the elements!");
9871 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9873 /// This routine just extracts two subvectors, shuffles them independently, and
9874 /// then concatenates them back together. This should work effectively with all
9875 /// AVX vector shuffle types.
9876 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9877 SDValue V2, ArrayRef<int> Mask,
9878 SelectionDAG &DAG) {
9879 assert(VT.getSizeInBits() >= 256 &&
9880 "Only for 256-bit or wider vector shuffles!");
9881 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9882 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9884 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9885 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9887 int NumElements = VT.getVectorNumElements();
9888 int SplitNumElements = NumElements / 2;
9889 MVT ScalarVT = VT.getVectorElementType();
9890 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9892 // Rather than splitting build-vectors, just build two narrower build
9893 // vectors. This helps shuffling with splats and zeros.
9894 auto SplitVector = [&](SDValue V) {
9895 while (V.getOpcode() == ISD::BITCAST)
9896 V = V->getOperand(0);
9898 MVT OrigVT = V.getSimpleValueType();
9899 int OrigNumElements = OrigVT.getVectorNumElements();
9900 int OrigSplitNumElements = OrigNumElements / 2;
9901 MVT OrigScalarVT = OrigVT.getVectorElementType();
9902 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9906 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9908 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9909 DAG.getIntPtrConstant(0, DL));
9910 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9911 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9914 SmallVector<SDValue, 16> LoOps, HiOps;
9915 for (int i = 0; i < OrigSplitNumElements; ++i) {
9916 LoOps.push_back(BV->getOperand(i));
9917 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9919 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9920 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9922 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9923 DAG.getBitcast(SplitVT, HiV));
9926 SDValue LoV1, HiV1, LoV2, HiV2;
9927 std::tie(LoV1, HiV1) = SplitVector(V1);
9928 std::tie(LoV2, HiV2) = SplitVector(V2);
9930 // Now create two 4-way blends of these half-width vectors.
9931 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9932 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9933 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9934 for (int i = 0; i < SplitNumElements; ++i) {
9935 int M = HalfMask[i];
9936 if (M >= NumElements) {
9937 if (M >= NumElements + SplitNumElements)
9941 V2BlendMask.push_back(M - NumElements);
9942 V1BlendMask.push_back(-1);
9943 BlendMask.push_back(SplitNumElements + i);
9944 } else if (M >= 0) {
9945 if (M >= SplitNumElements)
9949 V2BlendMask.push_back(-1);
9950 V1BlendMask.push_back(M);
9951 BlendMask.push_back(i);
9953 V2BlendMask.push_back(-1);
9954 V1BlendMask.push_back(-1);
9955 BlendMask.push_back(-1);
9959 // Because the lowering happens after all combining takes place, we need to
9960 // manually combine these blend masks as much as possible so that we create
9961 // a minimal number of high-level vector shuffle nodes.
9963 // First try just blending the halves of V1 or V2.
9964 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9965 return DAG.getUNDEF(SplitVT);
9966 if (!UseLoV2 && !UseHiV2)
9967 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9968 if (!UseLoV1 && !UseHiV1)
9969 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9971 SDValue V1Blend, V2Blend;
9972 if (UseLoV1 && UseHiV1) {
9974 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9976 // We only use half of V1 so map the usage down into the final blend mask.
9977 V1Blend = UseLoV1 ? LoV1 : HiV1;
9978 for (int i = 0; i < SplitNumElements; ++i)
9979 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9980 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9982 if (UseLoV2 && UseHiV2) {
9984 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9986 // We only use half of V2 so map the usage down into the final blend mask.
9987 V2Blend = UseLoV2 ? LoV2 : HiV2;
9988 for (int i = 0; i < SplitNumElements; ++i)
9989 if (BlendMask[i] >= SplitNumElements)
9990 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9992 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9994 SDValue Lo = HalfBlend(LoMask);
9995 SDValue Hi = HalfBlend(HiMask);
9996 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9999 /// \brief Either split a vector in halves or decompose the shuffles and the
10002 /// This is provided as a good fallback for many lowerings of non-single-input
10003 /// shuffles with more than one 128-bit lane. In those cases, we want to select
10004 /// between splitting the shuffle into 128-bit components and stitching those
10005 /// back together vs. extracting the single-input shuffles and blending those
10007 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
10008 SDValue V2, ArrayRef<int> Mask,
10009 SelectionDAG &DAG) {
10010 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
10011 "lower single-input shuffles as it "
10012 "could then recurse on itself.");
10013 int Size = Mask.size();
10015 // If this can be modeled as a broadcast of two elements followed by a blend,
10016 // prefer that lowering. This is especially important because broadcasts can
10017 // often fold with memory operands.
10018 auto DoBothBroadcast = [&] {
10019 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
10022 if (V2BroadcastIdx == -1)
10023 V2BroadcastIdx = M - Size;
10024 else if (M - Size != V2BroadcastIdx)
10026 } else if (M >= 0) {
10027 if (V1BroadcastIdx == -1)
10028 V1BroadcastIdx = M;
10029 else if (M != V1BroadcastIdx)
10034 if (DoBothBroadcast())
10035 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
10038 // If the inputs all stem from a single 128-bit lane of each input, then we
10039 // split them rather than blending because the split will decompose to
10040 // unusually few instructions.
10041 int LaneCount = VT.getSizeInBits() / 128;
10042 int LaneSize = Size / LaneCount;
10043 SmallBitVector LaneInputs[2];
10044 LaneInputs[0].resize(LaneCount, false);
10045 LaneInputs[1].resize(LaneCount, false);
10046 for (int i = 0; i < Size; ++i)
10048 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
10049 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
10050 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10052 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
10053 // that the decomposed single-input shuffles don't end up here.
10054 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10057 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
10058 /// a permutation and blend of those lanes.
10060 /// This essentially blends the out-of-lane inputs to each lane into the lane
10061 /// from a permuted copy of the vector. This lowering strategy results in four
10062 /// instructions in the worst case for a single-input cross lane shuffle which
10063 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
10064 /// of. Special cases for each particular shuffle pattern should be handled
10065 /// prior to trying this lowering.
10066 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
10067 SDValue V1, SDValue V2,
10068 ArrayRef<int> Mask,
10069 SelectionDAG &DAG) {
10070 // FIXME: This should probably be generalized for 512-bit vectors as well.
10071 assert(VT.is256BitVector() && "Only for 256-bit vector shuffles!");
10072 int LaneSize = Mask.size() / 2;
10074 // If there are only inputs from one 128-bit lane, splitting will in fact be
10075 // less expensive. The flags track whether the given lane contains an element
10076 // that crosses to another lane.
10077 bool LaneCrossing[2] = {false, false};
10078 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10079 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
10080 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
10081 if (!LaneCrossing[0] || !LaneCrossing[1])
10082 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10084 if (isSingleInputShuffleMask(Mask)) {
10085 SmallVector<int, 32> FlippedBlendMask;
10086 for (int i = 0, Size = Mask.size(); i < Size; ++i)
10087 FlippedBlendMask.push_back(
10088 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
10090 : Mask[i] % LaneSize +
10091 (i / LaneSize) * LaneSize + Size));
10093 // Flip the vector, and blend the results which should now be in-lane. The
10094 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
10095 // 5 for the high source. The value 3 selects the high half of source 2 and
10096 // the value 2 selects the low half of source 2. We only use source 2 to
10097 // allow folding it into a memory operand.
10098 unsigned PERMMask = 3 | 2 << 4;
10099 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
10100 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
10101 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
10104 // This now reduces to two single-input shuffles of V1 and V2 which at worst
10105 // will be handled by the above logic and a blend of the results, much like
10106 // other patterns in AVX.
10107 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
10110 /// \brief Handle lowering 2-lane 128-bit shuffles.
10111 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
10112 SDValue V2, ArrayRef<int> Mask,
10113 const X86Subtarget *Subtarget,
10114 SelectionDAG &DAG) {
10115 // TODO: If minimizing size and one of the inputs is a zero vector and the
10116 // the zero vector has only one use, we could use a VPERM2X128 to save the
10117 // instruction bytes needed to explicitly generate the zero vector.
10119 // Blends are faster and handle all the non-lane-crossing cases.
10120 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
10124 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
10125 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
10127 // If either input operand is a zero vector, use VPERM2X128 because its mask
10128 // allows us to replace the zero input with an implicit zero.
10129 if (!IsV1Zero && !IsV2Zero) {
10130 // Check for patterns which can be matched with a single insert of a 128-bit
10132 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
10133 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
10134 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
10135 VT.getVectorNumElements() / 2);
10136 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
10137 DAG.getIntPtrConstant(0, DL));
10138 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
10139 OnlyUsesV1 ? V1 : V2,
10140 DAG.getIntPtrConstant(0, DL));
10141 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
10145 // Otherwise form a 128-bit permutation. After accounting for undefs,
10146 // convert the 64-bit shuffle mask selection values into 128-bit
10147 // selection bits by dividing the indexes by 2 and shifting into positions
10148 // defined by a vperm2*128 instruction's immediate control byte.
10150 // The immediate permute control byte looks like this:
10151 // [1:0] - select 128 bits from sources for low half of destination
10153 // [3] - zero low half of destination
10154 // [5:4] - select 128 bits from sources for high half of destination
10156 // [7] - zero high half of destination
10158 int MaskLO = Mask[0];
10159 if (MaskLO == SM_SentinelUndef)
10160 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10162 int MaskHI = Mask[2];
10163 if (MaskHI == SM_SentinelUndef)
10164 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10166 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10168 // If either input is a zero vector, replace it with an undef input.
10169 // Shuffle mask values < 4 are selecting elements of V1.
10170 // Shuffle mask values >= 4 are selecting elements of V2.
10171 // Adjust each half of the permute mask by clearing the half that was
10172 // selecting the zero vector and setting the zero mask bit.
10174 V1 = DAG.getUNDEF(VT);
10176 PermMask = (PermMask & 0xf0) | 0x08;
10178 PermMask = (PermMask & 0x0f) | 0x80;
10181 V2 = DAG.getUNDEF(VT);
10183 PermMask = (PermMask & 0xf0) | 0x08;
10185 PermMask = (PermMask & 0x0f) | 0x80;
10188 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10189 DAG.getConstant(PermMask, DL, MVT::i8));
10192 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10193 /// shuffling each lane.
10195 /// This will only succeed when the result of fixing the 128-bit lanes results
10196 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10197 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10198 /// the lane crosses early and then use simpler shuffles within each lane.
10200 /// FIXME: It might be worthwhile at some point to support this without
10201 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10202 /// in x86 only floating point has interesting non-repeating shuffles, and even
10203 /// those are still *marginally* more expensive.
10204 static SDValue lowerVectorShuffleByMerging128BitLanes(
10205 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10206 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10207 assert(!isSingleInputShuffleMask(Mask) &&
10208 "This is only useful with multiple inputs.");
10210 int Size = Mask.size();
10211 int LaneSize = 128 / VT.getScalarSizeInBits();
10212 int NumLanes = Size / LaneSize;
10213 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10215 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10216 // check whether the in-128-bit lane shuffles share a repeating pattern.
10217 SmallVector<int, 4> Lanes;
10218 Lanes.resize(NumLanes, -1);
10219 SmallVector<int, 4> InLaneMask;
10220 InLaneMask.resize(LaneSize, -1);
10221 for (int i = 0; i < Size; ++i) {
10225 int j = i / LaneSize;
10227 if (Lanes[j] < 0) {
10228 // First entry we've seen for this lane.
10229 Lanes[j] = Mask[i] / LaneSize;
10230 } else if (Lanes[j] != Mask[i] / LaneSize) {
10231 // This doesn't match the lane selected previously!
10235 // Check that within each lane we have a consistent shuffle mask.
10236 int k = i % LaneSize;
10237 if (InLaneMask[k] < 0) {
10238 InLaneMask[k] = Mask[i] % LaneSize;
10239 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10240 // This doesn't fit a repeating in-lane mask.
10245 // First shuffle the lanes into place.
10246 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10247 VT.getSizeInBits() / 64);
10248 SmallVector<int, 8> LaneMask;
10249 LaneMask.resize(NumLanes * 2, -1);
10250 for (int i = 0; i < NumLanes; ++i)
10251 if (Lanes[i] >= 0) {
10252 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10253 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10256 V1 = DAG.getBitcast(LaneVT, V1);
10257 V2 = DAG.getBitcast(LaneVT, V2);
10258 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10260 // Cast it back to the type we actually want.
10261 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10263 // Now do a simple shuffle that isn't lane crossing.
10264 SmallVector<int, 8> NewMask;
10265 NewMask.resize(Size, -1);
10266 for (int i = 0; i < Size; ++i)
10268 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10269 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10270 "Must not introduce lane crosses at this point!");
10272 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10275 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10278 /// This returns true if the elements from a particular input are already in the
10279 /// slot required by the given mask and require no permutation.
10280 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10281 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10282 int Size = Mask.size();
10283 for (int i = 0; i < Size; ++i)
10284 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10290 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10291 ArrayRef<int> Mask, SDValue V1,
10292 SDValue V2, SelectionDAG &DAG) {
10294 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10295 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10296 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10297 int NumElts = VT.getVectorNumElements();
10298 bool ShufpdMask = true;
10299 bool CommutableMask = true;
10300 unsigned Immediate = 0;
10301 for (int i = 0; i < NumElts; ++i) {
10304 int Val = (i & 6) + NumElts * (i & 1);
10305 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10306 if (Mask[i] < Val || Mask[i] > Val + 1)
10307 ShufpdMask = false;
10308 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10309 CommutableMask = false;
10310 Immediate |= (Mask[i] % 2) << i;
10313 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10314 DAG.getConstant(Immediate, DL, MVT::i8));
10315 if (CommutableMask)
10316 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10317 DAG.getConstant(Immediate, DL, MVT::i8));
10321 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10323 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10324 /// isn't available.
10325 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10326 const X86Subtarget *Subtarget,
10327 SelectionDAG &DAG) {
10329 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10330 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10331 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10332 ArrayRef<int> Mask = SVOp->getMask();
10333 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10335 SmallVector<int, 4> WidenedMask;
10336 if (canWidenShuffleElements(Mask, WidenedMask))
10337 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10340 if (isSingleInputShuffleMask(Mask)) {
10341 // Check for being able to broadcast a single element.
10342 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10343 Mask, Subtarget, DAG))
10346 // Use low duplicate instructions for masks that match their pattern.
10347 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10348 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10350 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10351 // Non-half-crossing single input shuffles can be lowerid with an
10352 // interleaved permutation.
10353 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10354 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10355 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10356 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10359 // With AVX2 we have direct support for this permutation.
10360 if (Subtarget->hasAVX2())
10361 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10362 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10364 // Otherwise, fall back.
10365 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10369 // Use dedicated unpack instructions for masks that match their pattern.
10371 lowerVectorShuffleWithUNPCK(DL, MVT::v4f64, Mask, V1, V2, DAG))
10374 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10378 // Check if the blend happens to exactly fit that of SHUFPD.
10380 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10383 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10384 // shuffle. However, if we have AVX2 and either inputs are already in place,
10385 // we will be able to shuffle even across lanes the other input in a single
10386 // instruction so skip this pattern.
10387 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10388 isShuffleMaskInputInPlace(1, Mask))))
10389 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10390 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10393 // If we have AVX2 then we always want to lower with a blend because an v4 we
10394 // can fully permute the elements.
10395 if (Subtarget->hasAVX2())
10396 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10399 // Otherwise fall back on generic lowering.
10400 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10403 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10405 /// This routine is only called when we have AVX2 and thus a reasonable
10406 /// instruction set for v4i64 shuffling..
10407 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10408 const X86Subtarget *Subtarget,
10409 SelectionDAG &DAG) {
10411 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10412 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10413 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10414 ArrayRef<int> Mask = SVOp->getMask();
10415 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10416 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10418 SmallVector<int, 4> WidenedMask;
10419 if (canWidenShuffleElements(Mask, WidenedMask))
10420 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10423 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10427 // Check for being able to broadcast a single element.
10428 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10429 Mask, Subtarget, DAG))
10432 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10433 // use lower latency instructions that will operate on both 128-bit lanes.
10434 SmallVector<int, 2> RepeatedMask;
10435 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10436 if (isSingleInputShuffleMask(Mask)) {
10437 int PSHUFDMask[] = {-1, -1, -1, -1};
10438 for (int i = 0; i < 2; ++i)
10439 if (RepeatedMask[i] >= 0) {
10440 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10441 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10443 return DAG.getBitcast(
10445 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10446 DAG.getBitcast(MVT::v8i32, V1),
10447 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10451 // AVX2 provides a direct instruction for permuting a single input across
10453 if (isSingleInputShuffleMask(Mask))
10454 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10455 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10457 // Try to use shift instructions.
10458 if (SDValue Shift =
10459 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10462 // Use dedicated unpack instructions for masks that match their pattern.
10464 lowerVectorShuffleWithUNPCK(DL, MVT::v4i64, Mask, V1, V2, DAG))
10467 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10468 // shuffle. However, if we have AVX2 and either inputs are already in place,
10469 // we will be able to shuffle even across lanes the other input in a single
10470 // instruction so skip this pattern.
10471 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10472 isShuffleMaskInputInPlace(1, Mask))))
10473 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10474 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10477 // Otherwise fall back on generic blend lowering.
10478 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10482 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10484 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10485 /// isn't available.
10486 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10487 const X86Subtarget *Subtarget,
10488 SelectionDAG &DAG) {
10490 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10491 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10492 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10493 ArrayRef<int> Mask = SVOp->getMask();
10494 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10496 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10500 // Check for being able to broadcast a single element.
10501 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10502 Mask, Subtarget, DAG))
10505 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10506 // options to efficiently lower the shuffle.
10507 SmallVector<int, 4> RepeatedMask;
10508 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10509 assert(RepeatedMask.size() == 4 &&
10510 "Repeated masks must be half the mask width!");
10512 // Use even/odd duplicate instructions for masks that match their pattern.
10513 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10514 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10515 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10516 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10518 if (isSingleInputShuffleMask(Mask))
10519 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10520 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10522 // Use dedicated unpack instructions for masks that match their pattern.
10524 lowerVectorShuffleWithUNPCK(DL, MVT::v8f32, Mask, V1, V2, DAG))
10527 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10528 // have already handled any direct blends. We also need to squash the
10529 // repeated mask into a simulated v4f32 mask.
10530 for (int i = 0; i < 4; ++i)
10531 if (RepeatedMask[i] >= 8)
10532 RepeatedMask[i] -= 4;
10533 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10536 // If we have a single input shuffle with different shuffle patterns in the
10537 // two 128-bit lanes use the variable mask to VPERMILPS.
10538 if (isSingleInputShuffleMask(Mask)) {
10539 SDValue VPermMask[8];
10540 for (int i = 0; i < 8; ++i)
10541 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10542 : DAG.getConstant(Mask[i], DL, MVT::i32);
10543 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10544 return DAG.getNode(
10545 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10546 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10548 if (Subtarget->hasAVX2())
10549 return DAG.getNode(
10550 X86ISD::VPERMV, DL, MVT::v8f32,
10551 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10552 MVT::v8i32, VPermMask)),
10555 // Otherwise, fall back.
10556 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10560 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10562 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10563 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10566 // If we have AVX2 then we always want to lower with a blend because at v8 we
10567 // can fully permute the elements.
10568 if (Subtarget->hasAVX2())
10569 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10572 // Otherwise fall back on generic lowering.
10573 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10576 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10578 /// This routine is only called when we have AVX2 and thus a reasonable
10579 /// instruction set for v8i32 shuffling..
10580 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10581 const X86Subtarget *Subtarget,
10582 SelectionDAG &DAG) {
10584 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10585 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10586 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10587 ArrayRef<int> Mask = SVOp->getMask();
10588 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10589 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10591 // Whenever we can lower this as a zext, that instruction is strictly faster
10592 // than any alternative. It also allows us to fold memory operands into the
10593 // shuffle in many cases.
10594 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10595 Mask, Subtarget, DAG))
10598 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10602 // Check for being able to broadcast a single element.
10603 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10604 Mask, Subtarget, DAG))
10607 // If the shuffle mask is repeated in each 128-bit lane we can use more
10608 // efficient instructions that mirror the shuffles across the two 128-bit
10610 SmallVector<int, 4> RepeatedMask;
10611 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10612 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10613 if (isSingleInputShuffleMask(Mask))
10614 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10615 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10617 // Use dedicated unpack instructions for masks that match their pattern.
10619 lowerVectorShuffleWithUNPCK(DL, MVT::v8i32, Mask, V1, V2, DAG))
10623 // Try to use shift instructions.
10624 if (SDValue Shift =
10625 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10628 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10629 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10632 // If the shuffle patterns aren't repeated but it is a single input, directly
10633 // generate a cross-lane VPERMD instruction.
10634 if (isSingleInputShuffleMask(Mask)) {
10635 SDValue VPermMask[8];
10636 for (int i = 0; i < 8; ++i)
10637 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10638 : DAG.getConstant(Mask[i], DL, MVT::i32);
10639 return DAG.getNode(
10640 X86ISD::VPERMV, DL, MVT::v8i32,
10641 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10644 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10646 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10647 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10650 // Otherwise fall back on generic blend lowering.
10651 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10655 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10657 /// This routine is only called when we have AVX2 and thus a reasonable
10658 /// instruction set for v16i16 shuffling..
10659 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10660 const X86Subtarget *Subtarget,
10661 SelectionDAG &DAG) {
10663 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10664 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10665 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10666 ArrayRef<int> Mask = SVOp->getMask();
10667 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10668 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10670 // Whenever we can lower this as a zext, that instruction is strictly faster
10671 // than any alternative. It also allows us to fold memory operands into the
10672 // shuffle in many cases.
10673 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10674 Mask, Subtarget, DAG))
10677 // Check for being able to broadcast a single element.
10678 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10679 Mask, Subtarget, DAG))
10682 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10686 // Use dedicated unpack instructions for masks that match their pattern.
10688 lowerVectorShuffleWithUNPCK(DL, MVT::v16i16, Mask, V1, V2, DAG))
10691 // Try to use shift instructions.
10692 if (SDValue Shift =
10693 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10696 // Try to use byte rotation instructions.
10697 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10698 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10701 if (isSingleInputShuffleMask(Mask)) {
10702 // There are no generalized cross-lane shuffle operations available on i16
10704 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10705 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10708 SmallVector<int, 8> RepeatedMask;
10709 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10710 // As this is a single-input shuffle, the repeated mask should be
10711 // a strictly valid v8i16 mask that we can pass through to the v8i16
10712 // lowering to handle even the v16 case.
10713 return lowerV8I16GeneralSingleInputVectorShuffle(
10714 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10717 SDValue PSHUFBMask[32];
10718 for (int i = 0; i < 16; ++i) {
10719 if (Mask[i] == -1) {
10720 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10724 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10725 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10726 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10727 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10729 return DAG.getBitcast(MVT::v16i16,
10730 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10731 DAG.getBitcast(MVT::v32i8, V1),
10732 DAG.getNode(ISD::BUILD_VECTOR, DL,
10733 MVT::v32i8, PSHUFBMask)));
10736 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10738 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10739 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10742 // Otherwise fall back on generic lowering.
10743 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10746 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10748 /// This routine is only called when we have AVX2 and thus a reasonable
10749 /// instruction set for v32i8 shuffling..
10750 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10751 const X86Subtarget *Subtarget,
10752 SelectionDAG &DAG) {
10754 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10755 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10756 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10757 ArrayRef<int> Mask = SVOp->getMask();
10758 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10759 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10761 // Whenever we can lower this as a zext, that instruction is strictly faster
10762 // than any alternative. It also allows us to fold memory operands into the
10763 // shuffle in many cases.
10764 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10765 Mask, Subtarget, DAG))
10768 // Check for being able to broadcast a single element.
10769 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10770 Mask, Subtarget, DAG))
10773 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10777 // Use dedicated unpack instructions for masks that match their pattern.
10779 lowerVectorShuffleWithUNPCK(DL, MVT::v32i8, Mask, V1, V2, DAG))
10782 // Try to use shift instructions.
10783 if (SDValue Shift =
10784 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10787 // Try to use byte rotation instructions.
10788 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10789 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10792 if (isSingleInputShuffleMask(Mask)) {
10793 // There are no generalized cross-lane shuffle operations available on i8
10795 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10796 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10799 SDValue PSHUFBMask[32];
10800 for (int i = 0; i < 32; ++i)
10803 ? DAG.getUNDEF(MVT::i8)
10804 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10807 return DAG.getNode(
10808 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10809 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10812 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10814 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10815 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10818 // Otherwise fall back on generic lowering.
10819 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10822 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10824 /// This routine either breaks down the specific type of a 256-bit x86 vector
10825 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10826 /// together based on the available instructions.
10827 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10828 MVT VT, const X86Subtarget *Subtarget,
10829 SelectionDAG &DAG) {
10831 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10832 ArrayRef<int> Mask = SVOp->getMask();
10834 // If we have a single input to the zero element, insert that into V1 if we
10835 // can do so cheaply.
10836 int NumElts = VT.getVectorNumElements();
10837 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10838 return M >= NumElts;
10841 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10842 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10843 DL, VT, V1, V2, Mask, Subtarget, DAG))
10846 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10847 // can check for those subtargets here and avoid much of the subtarget
10848 // querying in the per-vector-type lowering routines. With AVX1 we have
10849 // essentially *zero* ability to manipulate a 256-bit vector with integer
10850 // types. Since we'll use floating point types there eventually, just
10851 // immediately cast everything to a float and operate entirely in that domain.
10852 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10853 int ElementBits = VT.getScalarSizeInBits();
10854 if (ElementBits < 32)
10855 // No floating point type available, decompose into 128-bit vectors.
10856 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10858 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10859 VT.getVectorNumElements());
10860 V1 = DAG.getBitcast(FpVT, V1);
10861 V2 = DAG.getBitcast(FpVT, V2);
10862 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10865 switch (VT.SimpleTy) {
10867 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10869 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10871 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10873 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10875 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10877 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10880 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10884 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10885 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10886 ArrayRef<int> Mask,
10887 SDValue V1, SDValue V2,
10888 SelectionDAG &DAG) {
10889 assert(VT.getScalarSizeInBits() == 64 &&
10890 "Unexpected element type size for 128bit shuffle.");
10892 // To handle 256 bit vector requires VLX and most probably
10893 // function lowerV2X128VectorShuffle() is better solution.
10894 assert(VT.is512BitVector() && "Unexpected vector size for 128bit shuffle.");
10896 SmallVector<int, 4> WidenedMask;
10897 if (!canWidenShuffleElements(Mask, WidenedMask))
10900 // Form a 128-bit permutation.
10901 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10902 // bits defined by a vshuf64x2 instruction's immediate control byte.
10903 unsigned PermMask = 0, Imm = 0;
10904 unsigned ControlBitsNum = WidenedMask.size() / 2;
10906 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10907 if (WidenedMask[i] == SM_SentinelZero)
10910 // Use first element in place of undef mask.
10911 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10912 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10915 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10916 DAG.getConstant(PermMask, DL, MVT::i8));
10919 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10920 ArrayRef<int> Mask, SDValue V1,
10921 SDValue V2, SelectionDAG &DAG) {
10923 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10925 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10926 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10928 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10929 if (isSingleInputShuffleMask(Mask))
10930 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10932 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10935 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10936 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10937 const X86Subtarget *Subtarget,
10938 SelectionDAG &DAG) {
10940 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10941 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10942 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10943 ArrayRef<int> Mask = SVOp->getMask();
10944 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10946 if (SDValue Shuf128 =
10947 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10950 if (SDValue Unpck =
10951 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10954 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10957 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10958 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10959 const X86Subtarget *Subtarget,
10960 SelectionDAG &DAG) {
10962 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10963 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10964 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10965 ArrayRef<int> Mask = SVOp->getMask();
10966 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10968 if (SDValue Unpck =
10969 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10972 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10975 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10976 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10977 const X86Subtarget *Subtarget,
10978 SelectionDAG &DAG) {
10980 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10981 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10982 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10983 ArrayRef<int> Mask = SVOp->getMask();
10984 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10986 if (SDValue Shuf128 =
10987 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10990 if (SDValue Unpck =
10991 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10994 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10997 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10998 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10999 const X86Subtarget *Subtarget,
11000 SelectionDAG &DAG) {
11002 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11003 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
11004 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11005 ArrayRef<int> Mask = SVOp->getMask();
11006 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
11008 if (SDValue Unpck =
11009 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
11012 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
11015 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
11016 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11017 const X86Subtarget *Subtarget,
11018 SelectionDAG &DAG) {
11020 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11021 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
11022 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11023 ArrayRef<int> Mask = SVOp->getMask();
11024 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
11025 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
11027 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
11030 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
11031 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11032 const X86Subtarget *Subtarget,
11033 SelectionDAG &DAG) {
11035 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11036 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
11037 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11038 ArrayRef<int> Mask = SVOp->getMask();
11039 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
11040 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
11042 // FIXME: Implement direct support for this type!
11043 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
11046 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
11048 /// This routine either breaks down the specific type of a 512-bit x86 vector
11049 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
11050 /// together based on the available instructions.
11051 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11052 MVT VT, const X86Subtarget *Subtarget,
11053 SelectionDAG &DAG) {
11055 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11056 ArrayRef<int> Mask = SVOp->getMask();
11057 assert(Subtarget->hasAVX512() &&
11058 "Cannot lower 512-bit vectors w/ basic ISA!");
11060 // Check for being able to broadcast a single element.
11061 if (SDValue Broadcast =
11062 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
11065 // Dispatch to each element type for lowering. If we don't have supprot for
11066 // specific element type shuffles at 512 bits, immediately split them and
11067 // lower them. Each lowering routine of a given type is allowed to assume that
11068 // the requisite ISA extensions for that element type are available.
11069 switch (VT.SimpleTy) {
11071 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11073 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11075 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
11077 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
11079 if (Subtarget->hasBWI())
11080 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
11083 if (Subtarget->hasBWI())
11084 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
11088 llvm_unreachable("Not a valid 512-bit x86 vector type!");
11091 // Otherwise fall back on splitting.
11092 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
11095 // Lower vXi1 vector shuffles.
11096 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
11097 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
11098 // vector, shuffle and then truncate it back.
11099 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
11100 MVT VT, const X86Subtarget *Subtarget,
11101 SelectionDAG &DAG) {
11103 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11104 ArrayRef<int> Mask = SVOp->getMask();
11105 assert(Subtarget->hasAVX512() &&
11106 "Cannot lower 512-bit vectors w/o basic ISA!");
11108 switch (VT.SimpleTy) {
11110 llvm_unreachable("Expected a vector of i1 elements");
11112 ExtVT = MVT::v2i64;
11115 ExtVT = MVT::v4i32;
11118 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11121 ExtVT = MVT::v16i32;
11124 ExtVT = MVT::v32i16;
11127 ExtVT = MVT::v64i8;
11131 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11132 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11133 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11134 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11136 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11139 V2 = DAG.getUNDEF(ExtVT);
11140 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11141 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11142 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11143 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11145 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11146 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11147 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11149 /// \brief Top-level lowering for x86 vector shuffles.
11151 /// This handles decomposition, canonicalization, and lowering of all x86
11152 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11153 /// above in helper routines. The canonicalization attempts to widen shuffles
11154 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11155 /// s.t. only one of the two inputs needs to be tested, etc.
11156 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11157 SelectionDAG &DAG) {
11158 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11159 ArrayRef<int> Mask = SVOp->getMask();
11160 SDValue V1 = Op.getOperand(0);
11161 SDValue V2 = Op.getOperand(1);
11162 MVT VT = Op.getSimpleValueType();
11163 int NumElements = VT.getVectorNumElements();
11165 bool Is1BitVector = (VT.getVectorElementType() == MVT::i1);
11167 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11168 "Can't lower MMX shuffles");
11170 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11171 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11172 if (V1IsUndef && V2IsUndef)
11173 return DAG.getUNDEF(VT);
11175 // When we create a shuffle node we put the UNDEF node to second operand,
11176 // but in some cases the first operand may be transformed to UNDEF.
11177 // In this case we should just commute the node.
11179 return DAG.getCommutedVectorShuffle(*SVOp);
11181 // Check for non-undef masks pointing at an undef vector and make the masks
11182 // undef as well. This makes it easier to match the shuffle based solely on
11186 if (M >= NumElements) {
11187 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11188 for (int &M : NewMask)
11189 if (M >= NumElements)
11191 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11194 // We actually see shuffles that are entirely re-arrangements of a set of
11195 // zero inputs. This mostly happens while decomposing complex shuffles into
11196 // simple ones. Directly lower these as a buildvector of zeros.
11197 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11198 if (Zeroable.all())
11199 return getZeroVector(VT, Subtarget, DAG, dl);
11201 // Try to collapse shuffles into using a vector type with fewer elements but
11202 // wider element types. We cap this to not form integers or floating point
11203 // elements wider than 64 bits, but it might be interesting to form i128
11204 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11205 SmallVector<int, 16> WidenedMask;
11206 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11207 canWidenShuffleElements(Mask, WidenedMask)) {
11208 MVT NewEltVT = VT.isFloatingPoint()
11209 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11210 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11211 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11212 // Make sure that the new vector type is legal. For example, v2f64 isn't
11214 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11215 V1 = DAG.getBitcast(NewVT, V1);
11216 V2 = DAG.getBitcast(NewVT, V2);
11217 return DAG.getBitcast(
11218 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11222 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11223 for (int M : SVOp->getMask())
11225 ++NumUndefElements;
11226 else if (M < NumElements)
11231 // Commute the shuffle as needed such that more elements come from V1 than
11232 // V2. This allows us to match the shuffle pattern strictly on how many
11233 // elements come from V1 without handling the symmetric cases.
11234 if (NumV2Elements > NumV1Elements)
11235 return DAG.getCommutedVectorShuffle(*SVOp);
11237 // When the number of V1 and V2 elements are the same, try to minimize the
11238 // number of uses of V2 in the low half of the vector. When that is tied,
11239 // ensure that the sum of indices for V1 is equal to or lower than the sum
11240 // indices for V2. When those are equal, try to ensure that the number of odd
11241 // indices for V1 is lower than the number of odd indices for V2.
11242 if (NumV1Elements == NumV2Elements) {
11243 int LowV1Elements = 0, LowV2Elements = 0;
11244 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11245 if (M >= NumElements)
11249 if (LowV2Elements > LowV1Elements) {
11250 return DAG.getCommutedVectorShuffle(*SVOp);
11251 } else if (LowV2Elements == LowV1Elements) {
11252 int SumV1Indices = 0, SumV2Indices = 0;
11253 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11254 if (SVOp->getMask()[i] >= NumElements)
11256 else if (SVOp->getMask()[i] >= 0)
11258 if (SumV2Indices < SumV1Indices) {
11259 return DAG.getCommutedVectorShuffle(*SVOp);
11260 } else if (SumV2Indices == SumV1Indices) {
11261 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11262 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11263 if (SVOp->getMask()[i] >= NumElements)
11264 NumV2OddIndices += i % 2;
11265 else if (SVOp->getMask()[i] >= 0)
11266 NumV1OddIndices += i % 2;
11267 if (NumV2OddIndices < NumV1OddIndices)
11268 return DAG.getCommutedVectorShuffle(*SVOp);
11273 // For each vector width, delegate to a specialized lowering routine.
11274 if (VT.is128BitVector())
11275 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11277 if (VT.is256BitVector())
11278 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11280 if (VT.is512BitVector())
11281 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11284 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11285 llvm_unreachable("Unimplemented!");
11288 // This function assumes its argument is a BUILD_VECTOR of constants or
11289 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11291 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11292 unsigned &MaskValue) {
11294 unsigned NumElems = BuildVector->getNumOperands();
11296 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11297 // We don't handle the >2 lanes case right now.
11298 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11302 unsigned NumElemsInLane = NumElems / NumLanes;
11304 // Blend for v16i16 should be symmetric for the both lanes.
11305 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11306 SDValue EltCond = BuildVector->getOperand(i);
11307 SDValue SndLaneEltCond =
11308 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11310 int Lane1Cond = -1, Lane2Cond = -1;
11311 if (isa<ConstantSDNode>(EltCond))
11312 Lane1Cond = !isZero(EltCond);
11313 if (isa<ConstantSDNode>(SndLaneEltCond))
11314 Lane2Cond = !isZero(SndLaneEltCond);
11316 unsigned LaneMask = 0;
11317 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11318 // Lane1Cond != 0, means we want the first argument.
11319 // Lane1Cond == 0, means we want the second argument.
11320 // The encoding of this argument is 0 for the first argument, 1
11321 // for the second. Therefore, invert the condition.
11322 LaneMask = !Lane1Cond << i;
11323 else if (Lane1Cond < 0)
11324 LaneMask = !Lane2Cond << i;
11328 MaskValue |= LaneMask;
11330 MaskValue |= LaneMask << NumElemsInLane;
11335 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11336 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11337 const X86Subtarget *Subtarget,
11338 SelectionDAG &DAG) {
11339 SDValue Cond = Op.getOperand(0);
11340 SDValue LHS = Op.getOperand(1);
11341 SDValue RHS = Op.getOperand(2);
11343 MVT VT = Op.getSimpleValueType();
11345 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11347 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11349 // Only non-legal VSELECTs reach this lowering, convert those into generic
11350 // shuffles and re-use the shuffle lowering path for blends.
11351 SmallVector<int, 32> Mask;
11352 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11353 SDValue CondElt = CondBV->getOperand(i);
11355 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11357 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11360 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11361 // A vselect where all conditions and data are constants can be optimized into
11362 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11363 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11364 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11365 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11368 // Try to lower this to a blend-style vector shuffle. This can handle all
11369 // constant condition cases.
11370 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11373 // Variable blends are only legal from SSE4.1 onward.
11374 if (!Subtarget->hasSSE41())
11377 // Only some types will be legal on some subtargets. If we can emit a legal
11378 // VSELECT-matching blend, return Op, and but if we need to expand, return
11380 switch (Op.getSimpleValueType().SimpleTy) {
11382 // Most of the vector types have blends past SSE4.1.
11386 // The byte blends for AVX vectors were introduced only in AVX2.
11387 if (Subtarget->hasAVX2())
11394 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11395 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11398 // FIXME: We should custom lower this by fixing the condition and using i8
11404 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11405 MVT VT = Op.getSimpleValueType();
11408 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11411 if (VT.getSizeInBits() == 8) {
11412 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11413 Op.getOperand(0), Op.getOperand(1));
11414 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11415 DAG.getValueType(VT));
11416 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11419 if (VT.getSizeInBits() == 16) {
11420 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11421 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11423 return DAG.getNode(
11424 ISD::TRUNCATE, dl, MVT::i16,
11425 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11426 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11427 Op.getOperand(1)));
11428 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11429 Op.getOperand(0), Op.getOperand(1));
11430 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11431 DAG.getValueType(VT));
11432 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11435 if (VT == MVT::f32) {
11436 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11437 // the result back to FR32 register. It's only worth matching if the
11438 // result has a single use which is a store or a bitcast to i32. And in
11439 // the case of a store, it's not worth it if the index is a constant 0,
11440 // because a MOVSSmr can be used instead, which is smaller and faster.
11441 if (!Op.hasOneUse())
11443 SDNode *User = *Op.getNode()->use_begin();
11444 if ((User->getOpcode() != ISD::STORE ||
11445 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11446 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11447 (User->getOpcode() != ISD::BITCAST ||
11448 User->getValueType(0) != MVT::i32))
11450 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11451 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11453 return DAG.getBitcast(MVT::f32, Extract);
11456 if (VT == MVT::i32 || VT == MVT::i64) {
11457 // ExtractPS/pextrq works with constant index.
11458 if (isa<ConstantSDNode>(Op.getOperand(1)))
11464 /// Extract one bit from mask vector, like v16i1 or v8i1.
11465 /// AVX-512 feature.
11467 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11468 SDValue Vec = Op.getOperand(0);
11470 MVT VecVT = Vec.getSimpleValueType();
11471 SDValue Idx = Op.getOperand(1);
11472 MVT EltVT = Op.getSimpleValueType();
11474 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11475 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11476 "Unexpected vector type in ExtractBitFromMaskVector");
11478 // variable index can't be handled in mask registers,
11479 // extend vector to VR512
11480 if (!isa<ConstantSDNode>(Idx)) {
11481 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11482 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11483 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11484 ExtVT.getVectorElementType(), Ext, Idx);
11485 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11488 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11489 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11490 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11491 rc = getRegClassFor(MVT::v16i1);
11492 unsigned MaxSift = rc->getSize()*8 - 1;
11493 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11494 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11495 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11496 DAG.getConstant(MaxSift, dl, MVT::i8));
11497 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11498 DAG.getIntPtrConstant(0, dl));
11502 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11503 SelectionDAG &DAG) const {
11505 SDValue Vec = Op.getOperand(0);
11506 MVT VecVT = Vec.getSimpleValueType();
11507 SDValue Idx = Op.getOperand(1);
11509 if (Op.getSimpleValueType() == MVT::i1)
11510 return ExtractBitFromMaskVector(Op, DAG);
11512 if (!isa<ConstantSDNode>(Idx)) {
11513 if (VecVT.is512BitVector() ||
11514 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11515 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11518 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11519 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11520 MaskEltVT.getSizeInBits());
11522 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11523 auto PtrVT = getPointerTy(DAG.getDataLayout());
11524 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11525 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11526 DAG.getConstant(0, dl, PtrVT));
11527 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11528 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11529 DAG.getConstant(0, dl, PtrVT));
11534 // If this is a 256-bit vector result, first extract the 128-bit vector and
11535 // then extract the element from the 128-bit vector.
11536 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11538 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11539 // Get the 128-bit vector.
11540 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11541 MVT EltVT = VecVT.getVectorElementType();
11543 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11544 assert(isPowerOf2_32(ElemsPerChunk) && "Elements per chunk not power of 2");
11546 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
11547 // this can be done with a mask.
11548 IdxVal &= ElemsPerChunk - 1;
11549 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11550 DAG.getConstant(IdxVal, dl, MVT::i32));
11553 assert(VecVT.is128BitVector() && "Unexpected vector length");
11555 if (Subtarget->hasSSE41())
11556 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11559 MVT VT = Op.getSimpleValueType();
11560 // TODO: handle v16i8.
11561 if (VT.getSizeInBits() == 16) {
11562 SDValue Vec = Op.getOperand(0);
11563 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11565 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11566 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11567 DAG.getBitcast(MVT::v4i32, Vec),
11568 Op.getOperand(1)));
11569 // Transform it so it match pextrw which produces a 32-bit result.
11570 MVT EltVT = MVT::i32;
11571 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11572 Op.getOperand(0), Op.getOperand(1));
11573 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11574 DAG.getValueType(VT));
11575 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11578 if (VT.getSizeInBits() == 32) {
11579 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11583 // SHUFPS the element to the lowest double word, then movss.
11584 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11585 MVT VVT = Op.getOperand(0).getSimpleValueType();
11586 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11587 DAG.getUNDEF(VVT), Mask);
11588 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11589 DAG.getIntPtrConstant(0, dl));
11592 if (VT.getSizeInBits() == 64) {
11593 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11594 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11595 // to match extract_elt for f64.
11596 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11600 // UNPCKHPD the element to the lowest double word, then movsd.
11601 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11602 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11603 int Mask[2] = { 1, -1 };
11604 MVT VVT = Op.getOperand(0).getSimpleValueType();
11605 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11606 DAG.getUNDEF(VVT), Mask);
11607 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11608 DAG.getIntPtrConstant(0, dl));
11614 /// Insert one bit to mask vector, like v16i1 or v8i1.
11615 /// AVX-512 feature.
11617 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11619 SDValue Vec = Op.getOperand(0);
11620 SDValue Elt = Op.getOperand(1);
11621 SDValue Idx = Op.getOperand(2);
11622 MVT VecVT = Vec.getSimpleValueType();
11624 if (!isa<ConstantSDNode>(Idx)) {
11625 // Non constant index. Extend source and destination,
11626 // insert element and then truncate the result.
11627 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11628 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11629 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11630 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11631 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11632 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11635 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11636 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11638 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11639 DAG.getConstant(IdxVal, dl, MVT::i8));
11640 if (Vec.getOpcode() == ISD::UNDEF)
11642 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11645 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11646 SelectionDAG &DAG) const {
11647 MVT VT = Op.getSimpleValueType();
11648 MVT EltVT = VT.getVectorElementType();
11650 if (EltVT == MVT::i1)
11651 return InsertBitToMaskVector(Op, DAG);
11654 SDValue N0 = Op.getOperand(0);
11655 SDValue N1 = Op.getOperand(1);
11656 SDValue N2 = Op.getOperand(2);
11657 if (!isa<ConstantSDNode>(N2))
11659 auto *N2C = cast<ConstantSDNode>(N2);
11660 unsigned IdxVal = N2C->getZExtValue();
11662 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11663 // into that, and then insert the subvector back into the result.
11664 if (VT.is256BitVector() || VT.is512BitVector()) {
11665 // With a 256-bit vector, we can insert into the zero element efficiently
11666 // using a blend if we have AVX or AVX2 and the right data type.
11667 if (VT.is256BitVector() && IdxVal == 0) {
11668 // TODO: It is worthwhile to cast integer to floating point and back
11669 // and incur a domain crossing penalty if that's what we'll end up
11670 // doing anyway after extracting to a 128-bit vector.
11671 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11672 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11673 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11674 N2 = DAG.getIntPtrConstant(1, dl);
11675 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11679 // Get the desired 128-bit vector chunk.
11680 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11682 // Insert the element into the desired chunk.
11683 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11684 assert(isPowerOf2_32(NumEltsIn128));
11685 // Since NumEltsIn128 is a power of 2 we can use mask instead of modulo.
11686 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
11688 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11689 DAG.getConstant(IdxIn128, dl, MVT::i32));
11691 // Insert the changed part back into the bigger vector
11692 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11694 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11696 if (Subtarget->hasSSE41()) {
11697 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11699 if (VT == MVT::v8i16) {
11700 Opc = X86ISD::PINSRW;
11702 assert(VT == MVT::v16i8);
11703 Opc = X86ISD::PINSRB;
11706 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11708 if (N1.getValueType() != MVT::i32)
11709 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11710 if (N2.getValueType() != MVT::i32)
11711 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11712 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11715 if (EltVT == MVT::f32) {
11716 // Bits [7:6] of the constant are the source select. This will always be
11717 // zero here. The DAG Combiner may combine an extract_elt index into
11718 // these bits. For example (insert (extract, 3), 2) could be matched by
11719 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11720 // Bits [5:4] of the constant are the destination select. This is the
11721 // value of the incoming immediate.
11722 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11723 // combine either bitwise AND or insert of float 0.0 to set these bits.
11725 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11726 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11727 // If this is an insertion of 32-bits into the low 32-bits of
11728 // a vector, we prefer to generate a blend with immediate rather
11729 // than an insertps. Blends are simpler operations in hardware and so
11730 // will always have equal or better performance than insertps.
11731 // But if optimizing for size and there's a load folding opportunity,
11732 // generate insertps because blendps does not have a 32-bit memory
11734 N2 = DAG.getIntPtrConstant(1, dl);
11735 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11736 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11738 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11739 // Create this as a scalar to vector..
11740 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11741 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11744 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11745 // PINSR* works with constant index.
11750 if (EltVT == MVT::i8)
11753 if (EltVT.getSizeInBits() == 16) {
11754 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11755 // as its second argument.
11756 if (N1.getValueType() != MVT::i32)
11757 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11758 if (N2.getValueType() != MVT::i32)
11759 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11760 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11765 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11767 MVT OpVT = Op.getSimpleValueType();
11769 // If this is a 256-bit vector result, first insert into a 128-bit
11770 // vector and then insert into the 256-bit vector.
11771 if (!OpVT.is128BitVector()) {
11772 // Insert into a 128-bit vector.
11773 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11774 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11775 OpVT.getVectorNumElements() / SizeFactor);
11777 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11779 // Insert the 128-bit vector.
11780 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11783 if (OpVT == MVT::v1i64 &&
11784 Op.getOperand(0).getValueType() == MVT::i64)
11785 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11787 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11788 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11789 return DAG.getBitcast(
11790 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11793 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11794 // a simple subregister reference or explicit instructions to grab
11795 // upper bits of a vector.
11796 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11797 SelectionDAG &DAG) {
11799 SDValue In = Op.getOperand(0);
11800 SDValue Idx = Op.getOperand(1);
11801 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11802 MVT ResVT = Op.getSimpleValueType();
11803 MVT InVT = In.getSimpleValueType();
11805 if (Subtarget->hasFp256()) {
11806 if (ResVT.is128BitVector() &&
11807 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11808 isa<ConstantSDNode>(Idx)) {
11809 return Extract128BitVector(In, IdxVal, DAG, dl);
11811 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11812 isa<ConstantSDNode>(Idx)) {
11813 return Extract256BitVector(In, IdxVal, DAG, dl);
11819 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11820 // simple superregister reference or explicit instructions to insert
11821 // the upper bits of a vector.
11822 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11823 SelectionDAG &DAG) {
11824 if (!Subtarget->hasAVX())
11828 SDValue Vec = Op.getOperand(0);
11829 SDValue SubVec = Op.getOperand(1);
11830 SDValue Idx = Op.getOperand(2);
11832 if (!isa<ConstantSDNode>(Idx))
11835 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11836 MVT OpVT = Op.getSimpleValueType();
11837 MVT SubVecVT = SubVec.getSimpleValueType();
11839 // Fold two 16-byte subvector loads into one 32-byte load:
11840 // (insert_subvector (insert_subvector undef, (load addr), 0),
11841 // (load addr + 16), Elts/2)
11843 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11844 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11845 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11846 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11847 if (Idx2 && Idx2->getZExtValue() == 0) {
11848 SDValue SubVec2 = Vec.getOperand(1);
11849 // If needed, look through a bitcast to get to the load.
11850 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11851 SubVec2 = SubVec2.getOperand(0);
11853 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11855 unsigned Alignment = FirstLd->getAlignment();
11856 unsigned AS = FirstLd->getAddressSpace();
11857 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11858 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11859 OpVT, AS, Alignment, &Fast) && Fast) {
11860 SDValue Ops[] = { SubVec2, SubVec };
11861 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11868 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11869 SubVecVT.is128BitVector())
11870 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11872 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11873 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11875 if (OpVT.getVectorElementType() == MVT::i1)
11876 return Insert1BitVector(Op, DAG);
11881 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11882 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11883 // one of the above mentioned nodes. It has to be wrapped because otherwise
11884 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11885 // be used to form addressing mode. These wrapped nodes will be selected
11888 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11889 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11891 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11892 // global base reg.
11893 unsigned char OpFlag = 0;
11894 unsigned WrapperKind = X86ISD::Wrapper;
11895 CodeModel::Model M = DAG.getTarget().getCodeModel();
11897 if (Subtarget->isPICStyleRIPRel() &&
11898 (M == CodeModel::Small || M == CodeModel::Kernel))
11899 WrapperKind = X86ISD::WrapperRIP;
11900 else if (Subtarget->isPICStyleGOT())
11901 OpFlag = X86II::MO_GOTOFF;
11902 else if (Subtarget->isPICStyleStubPIC())
11903 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11905 auto PtrVT = getPointerTy(DAG.getDataLayout());
11906 SDValue Result = DAG.getTargetConstantPool(
11907 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11909 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11910 // With PIC, the address is actually $g + Offset.
11913 DAG.getNode(ISD::ADD, DL, PtrVT,
11914 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11920 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11921 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11923 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11924 // global base reg.
11925 unsigned char OpFlag = 0;
11926 unsigned WrapperKind = X86ISD::Wrapper;
11927 CodeModel::Model M = DAG.getTarget().getCodeModel();
11929 if (Subtarget->isPICStyleRIPRel() &&
11930 (M == CodeModel::Small || M == CodeModel::Kernel))
11931 WrapperKind = X86ISD::WrapperRIP;
11932 else if (Subtarget->isPICStyleGOT())
11933 OpFlag = X86II::MO_GOTOFF;
11934 else if (Subtarget->isPICStyleStubPIC())
11935 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11937 auto PtrVT = getPointerTy(DAG.getDataLayout());
11938 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11940 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11942 // With PIC, the address is actually $g + Offset.
11945 DAG.getNode(ISD::ADD, DL, PtrVT,
11946 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11952 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11953 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11955 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11956 // global base reg.
11957 unsigned char OpFlag = 0;
11958 unsigned WrapperKind = X86ISD::Wrapper;
11959 CodeModel::Model M = DAG.getTarget().getCodeModel();
11961 if (Subtarget->isPICStyleRIPRel() &&
11962 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11963 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11964 OpFlag = X86II::MO_GOTPCREL;
11965 WrapperKind = X86ISD::WrapperRIP;
11966 } else if (Subtarget->isPICStyleGOT()) {
11967 OpFlag = X86II::MO_GOT;
11968 } else if (Subtarget->isPICStyleStubPIC()) {
11969 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11970 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11971 OpFlag = X86II::MO_DARWIN_NONLAZY;
11974 auto PtrVT = getPointerTy(DAG.getDataLayout());
11975 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11978 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11980 // With PIC, the address is actually $g + Offset.
11981 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11982 !Subtarget->is64Bit()) {
11984 DAG.getNode(ISD::ADD, DL, PtrVT,
11985 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11988 // For symbols that require a load from a stub to get the address, emit the
11990 if (isGlobalStubReference(OpFlag))
11991 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11992 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11993 false, false, false, 0);
11999 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
12000 // Create the TargetBlockAddressAddress node.
12001 unsigned char OpFlags =
12002 Subtarget->ClassifyBlockAddressReference();
12003 CodeModel::Model M = DAG.getTarget().getCodeModel();
12004 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
12005 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
12007 auto PtrVT = getPointerTy(DAG.getDataLayout());
12008 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
12010 if (Subtarget->isPICStyleRIPRel() &&
12011 (M == CodeModel::Small || M == CodeModel::Kernel))
12012 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12014 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12016 // With PIC, the address is actually $g + Offset.
12017 if (isGlobalRelativeToPICBase(OpFlags)) {
12018 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12019 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12026 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
12027 int64_t Offset, SelectionDAG &DAG) const {
12028 // Create the TargetGlobalAddress node, folding in the constant
12029 // offset if it is legal.
12030 unsigned char OpFlags =
12031 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
12032 CodeModel::Model M = DAG.getTarget().getCodeModel();
12033 auto PtrVT = getPointerTy(DAG.getDataLayout());
12035 if (OpFlags == X86II::MO_NO_FLAG &&
12036 X86::isOffsetSuitableForCodeModel(Offset, M)) {
12037 // A direct static reference to a global.
12038 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
12041 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
12044 if (Subtarget->isPICStyleRIPRel() &&
12045 (M == CodeModel::Small || M == CodeModel::Kernel))
12046 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
12048 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
12050 // With PIC, the address is actually $g + Offset.
12051 if (isGlobalRelativeToPICBase(OpFlags)) {
12052 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
12053 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
12056 // For globals that require a load from a stub to get the address, emit the
12058 if (isGlobalStubReference(OpFlags))
12059 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
12060 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12061 false, false, false, 0);
12063 // If there was a non-zero offset that we didn't fold, create an explicit
12064 // addition for it.
12066 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
12067 DAG.getConstant(Offset, dl, PtrVT));
12073 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
12074 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
12075 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
12076 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12080 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12081 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12082 unsigned char OperandFlags, bool LocalDynamic = false) {
12083 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12084 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12086 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12087 GA->getValueType(0),
12091 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12095 SDValue Ops[] = { Chain, TGA, *InFlag };
12096 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12098 SDValue Ops[] = { Chain, TGA };
12099 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12102 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12103 MFI->setAdjustsStack(true);
12104 MFI->setHasCalls(true);
12106 SDValue Flag = Chain.getValue(1);
12107 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12110 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12112 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12115 SDLoc dl(GA); // ? function entry point might be better
12116 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12117 DAG.getNode(X86ISD::GlobalBaseReg,
12118 SDLoc(), PtrVT), InFlag);
12119 InFlag = Chain.getValue(1);
12121 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12124 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12126 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12128 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12129 X86::RAX, X86II::MO_TLSGD);
12132 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12138 // Get the start address of the TLS block for this module.
12139 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12140 .getInfo<X86MachineFunctionInfo>();
12141 MFI->incNumLocalDynamicTLSAccesses();
12145 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12146 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12149 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12150 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12151 InFlag = Chain.getValue(1);
12152 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12153 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12156 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12160 unsigned char OperandFlags = X86II::MO_DTPOFF;
12161 unsigned WrapperKind = X86ISD::Wrapper;
12162 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12163 GA->getValueType(0),
12164 GA->getOffset(), OperandFlags);
12165 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12167 // Add x@dtpoff with the base.
12168 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12171 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12172 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12173 const EVT PtrVT, TLSModel::Model model,
12174 bool is64Bit, bool isPIC) {
12177 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12178 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12179 is64Bit ? 257 : 256));
12181 SDValue ThreadPointer =
12182 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12183 MachinePointerInfo(Ptr), false, false, false, 0);
12185 unsigned char OperandFlags = 0;
12186 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12188 unsigned WrapperKind = X86ISD::Wrapper;
12189 if (model == TLSModel::LocalExec) {
12190 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12191 } else if (model == TLSModel::InitialExec) {
12193 OperandFlags = X86II::MO_GOTTPOFF;
12194 WrapperKind = X86ISD::WrapperRIP;
12196 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12199 llvm_unreachable("Unexpected model");
12202 // emit "addl x@ntpoff,%eax" (local exec)
12203 // or "addl x@indntpoff,%eax" (initial exec)
12204 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12206 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12207 GA->getOffset(), OperandFlags);
12208 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12210 if (model == TLSModel::InitialExec) {
12211 if (isPIC && !is64Bit) {
12212 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12213 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12217 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12218 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12219 false, false, false, 0);
12222 // The address of the thread local variable is the add of the thread
12223 // pointer with the offset of the variable.
12224 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12228 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12230 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12231 const GlobalValue *GV = GA->getGlobal();
12232 auto PtrVT = getPointerTy(DAG.getDataLayout());
12234 if (Subtarget->isTargetELF()) {
12235 if (DAG.getTarget().Options.EmulatedTLS)
12236 return LowerToTLSEmulatedModel(GA, DAG);
12237 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12239 case TLSModel::GeneralDynamic:
12240 if (Subtarget->is64Bit())
12241 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12242 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12243 case TLSModel::LocalDynamic:
12244 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12245 Subtarget->is64Bit());
12246 case TLSModel::InitialExec:
12247 case TLSModel::LocalExec:
12248 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12249 DAG.getTarget().getRelocationModel() ==
12252 llvm_unreachable("Unknown TLS model.");
12255 if (Subtarget->isTargetDarwin()) {
12256 // Darwin only has one model of TLS. Lower to that.
12257 unsigned char OpFlag = 0;
12258 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12259 X86ISD::WrapperRIP : X86ISD::Wrapper;
12261 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12262 // global base reg.
12263 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12264 !Subtarget->is64Bit();
12266 OpFlag = X86II::MO_TLVP_PIC_BASE;
12268 OpFlag = X86II::MO_TLVP;
12270 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12271 GA->getValueType(0),
12272 GA->getOffset(), OpFlag);
12273 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12275 // With PIC32, the address is actually $g + Offset.
12277 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12278 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12281 // Lowering the machine isd will make sure everything is in the right
12283 SDValue Chain = DAG.getEntryNode();
12284 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12285 SDValue Args[] = { Chain, Offset };
12286 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12288 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12289 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12290 MFI->setAdjustsStack(true);
12292 // And our return value (tls address) is in the standard call return value
12294 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12295 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12298 if (Subtarget->isTargetKnownWindowsMSVC() ||
12299 Subtarget->isTargetWindowsGNU()) {
12300 // Just use the implicit TLS architecture
12301 // Need to generate someting similar to:
12302 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12304 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12305 // mov rcx, qword [rdx+rcx*8]
12306 // mov eax, .tls$:tlsvar
12307 // [rax+rcx] contains the address
12308 // Windows 64bit: gs:0x58
12309 // Windows 32bit: fs:__tls_array
12312 SDValue Chain = DAG.getEntryNode();
12314 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12315 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12316 // use its literal value of 0x2C.
12317 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12318 ? Type::getInt8PtrTy(*DAG.getContext(),
12320 : Type::getInt32PtrTy(*DAG.getContext(),
12323 SDValue TlsArray = Subtarget->is64Bit()
12324 ? DAG.getIntPtrConstant(0x58, dl)
12325 : (Subtarget->isTargetWindowsGNU()
12326 ? DAG.getIntPtrConstant(0x2C, dl)
12327 : DAG.getExternalSymbol("_tls_array", PtrVT));
12329 SDValue ThreadPointer =
12330 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12334 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12335 res = ThreadPointer;
12337 // Load the _tls_index variable
12338 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12339 if (Subtarget->is64Bit())
12340 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12341 MachinePointerInfo(), MVT::i32, false, false,
12344 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12347 auto &DL = DAG.getDataLayout();
12349 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12350 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12352 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12355 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12358 // Get the offset of start of .tls section
12359 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12360 GA->getValueType(0),
12361 GA->getOffset(), X86II::MO_SECREL);
12362 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12364 // The address of the thread local variable is the add of the thread
12365 // pointer with the offset of the variable.
12366 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12369 llvm_unreachable("TLS not implemented for this target.");
12372 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12373 /// and take a 2 x i32 value to shift plus a shift amount.
12374 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12375 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12376 MVT VT = Op.getSimpleValueType();
12377 unsigned VTBits = VT.getSizeInBits();
12379 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12380 SDValue ShOpLo = Op.getOperand(0);
12381 SDValue ShOpHi = Op.getOperand(1);
12382 SDValue ShAmt = Op.getOperand(2);
12383 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12384 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12386 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12387 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12388 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12389 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12390 : DAG.getConstant(0, dl, VT);
12392 SDValue Tmp2, Tmp3;
12393 if (Op.getOpcode() == ISD::SHL_PARTS) {
12394 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12395 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12397 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12398 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12401 // If the shift amount is larger or equal than the width of a part we can't
12402 // rely on the results of shld/shrd. Insert a test and select the appropriate
12403 // values for large shift amounts.
12404 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12405 DAG.getConstant(VTBits, dl, MVT::i8));
12406 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12407 AndNode, DAG.getConstant(0, dl, MVT::i8));
12410 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12411 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12412 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12414 if (Op.getOpcode() == ISD::SHL_PARTS) {
12415 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12416 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12418 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12419 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12422 SDValue Ops[2] = { Lo, Hi };
12423 return DAG.getMergeValues(Ops, dl);
12426 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12427 SelectionDAG &DAG) const {
12428 SDValue Src = Op.getOperand(0);
12429 MVT SrcVT = Src.getSimpleValueType();
12430 MVT VT = Op.getSimpleValueType();
12433 if (SrcVT.isVector()) {
12434 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12435 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12436 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12437 DAG.getUNDEF(SrcVT)));
12439 if (SrcVT.getVectorElementType() == MVT::i1) {
12440 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12441 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12442 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12447 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12448 "Unknown SINT_TO_FP to lower!");
12450 // These are really Legal; return the operand so the caller accepts it as
12452 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12454 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12455 Subtarget->is64Bit()) {
12459 unsigned Size = SrcVT.getSizeInBits()/8;
12460 MachineFunction &MF = DAG.getMachineFunction();
12461 auto PtrVT = getPointerTy(MF.getDataLayout());
12462 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12463 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12464 SDValue Chain = DAG.getStore(
12465 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12466 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12468 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12471 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12473 SelectionDAG &DAG) const {
12477 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12479 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12481 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12483 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12485 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12486 MachineMemOperand *MMO;
12488 int SSFI = FI->getIndex();
12489 MMO = DAG.getMachineFunction().getMachineMemOperand(
12490 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12491 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12493 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12494 StackSlot = StackSlot.getOperand(1);
12496 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12497 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12499 Tys, Ops, SrcVT, MMO);
12502 Chain = Result.getValue(1);
12503 SDValue InFlag = Result.getValue(2);
12505 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12506 // shouldn't be necessary except that RFP cannot be live across
12507 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12508 MachineFunction &MF = DAG.getMachineFunction();
12509 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12510 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12511 auto PtrVT = getPointerTy(MF.getDataLayout());
12512 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12513 Tys = DAG.getVTList(MVT::Other);
12515 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12517 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12518 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12519 MachineMemOperand::MOStore, SSFISize, SSFISize);
12521 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12522 Ops, Op.getValueType(), MMO);
12523 Result = DAG.getLoad(
12524 Op.getValueType(), DL, Chain, StackSlot,
12525 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12526 false, false, false, 0);
12532 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12533 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12534 SelectionDAG &DAG) const {
12535 // This algorithm is not obvious. Here it is what we're trying to output:
12538 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12539 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12541 haddpd %xmm0, %xmm0
12543 pshufd $0x4e, %xmm0, %xmm1
12549 LLVMContext *Context = DAG.getContext();
12551 // Build some magic constants.
12552 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12553 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12554 auto PtrVT = getPointerTy(DAG.getDataLayout());
12555 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12557 SmallVector<Constant*,2> CV1;
12559 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12560 APInt(64, 0x4330000000000000ULL))));
12562 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12563 APInt(64, 0x4530000000000000ULL))));
12564 Constant *C1 = ConstantVector::get(CV1);
12565 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12567 // Load the 64-bit value into an XMM register.
12568 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12571 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12572 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12573 false, false, false, 16);
12575 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12578 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12579 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12580 false, false, false, 16);
12581 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12582 // TODO: Are there any fast-math-flags to propagate here?
12583 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12586 if (Subtarget->hasSSE3()) {
12587 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12588 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12590 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12591 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12593 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12594 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12597 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12598 DAG.getIntPtrConstant(0, dl));
12601 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12602 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12603 SelectionDAG &DAG) const {
12605 // FP constant to bias correct the final result.
12606 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12609 // Load the 32-bit value into an XMM register.
12610 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12613 // Zero out the upper parts of the register.
12614 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12616 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12617 DAG.getBitcast(MVT::v2f64, Load),
12618 DAG.getIntPtrConstant(0, dl));
12620 // Or the load with the bias.
12621 SDValue Or = DAG.getNode(
12622 ISD::OR, dl, MVT::v2i64,
12623 DAG.getBitcast(MVT::v2i64,
12624 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12625 DAG.getBitcast(MVT::v2i64,
12626 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12628 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12629 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12631 // Subtract the bias.
12632 // TODO: Are there any fast-math-flags to propagate here?
12633 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12635 // Handle final rounding.
12636 MVT DestVT = Op.getSimpleValueType();
12638 if (DestVT.bitsLT(MVT::f64))
12639 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12640 DAG.getIntPtrConstant(0, dl));
12641 if (DestVT.bitsGT(MVT::f64))
12642 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12644 // Handle final rounding.
12648 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12649 const X86Subtarget &Subtarget) {
12650 // The algorithm is the following:
12651 // #ifdef __SSE4_1__
12652 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12653 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12654 // (uint4) 0x53000000, 0xaa);
12656 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12657 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12659 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12660 // return (float4) lo + fhi;
12662 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12663 // reassociate the two FADDs, and if we do that, the algorithm fails
12664 // spectacularly (PR24512).
12665 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12666 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12667 // there's also the MachineCombiner reassociations happening on Machine IR.
12668 if (DAG.getTarget().Options.UnsafeFPMath)
12672 SDValue V = Op->getOperand(0);
12673 MVT VecIntVT = V.getSimpleValueType();
12674 bool Is128 = VecIntVT == MVT::v4i32;
12675 MVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12676 // If we convert to something else than the supported type, e.g., to v4f64,
12678 if (VecFloatVT != Op->getSimpleValueType(0))
12681 unsigned NumElts = VecIntVT.getVectorNumElements();
12682 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12683 "Unsupported custom type");
12684 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12686 // In the #idef/#else code, we have in common:
12687 // - The vector of constants:
12693 // Create the splat vector for 0x4b000000.
12694 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12695 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12696 CstLow, CstLow, CstLow, CstLow};
12697 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12698 makeArrayRef(&CstLowArray[0], NumElts));
12699 // Create the splat vector for 0x53000000.
12700 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12701 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12702 CstHigh, CstHigh, CstHigh, CstHigh};
12703 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12704 makeArrayRef(&CstHighArray[0], NumElts));
12706 // Create the right shift.
12707 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12708 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12709 CstShift, CstShift, CstShift, CstShift};
12710 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12711 makeArrayRef(&CstShiftArray[0], NumElts));
12712 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12715 if (Subtarget.hasSSE41()) {
12716 MVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12717 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12718 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12719 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12720 // Low will be bitcasted right away, so do not bother bitcasting back to its
12722 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12723 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12724 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12725 // (uint4) 0x53000000, 0xaa);
12726 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12727 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12728 // High will be bitcasted right away, so do not bother bitcasting back to
12729 // its original type.
12730 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12731 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12733 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12734 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12735 CstMask, CstMask, CstMask);
12736 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12737 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12738 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12740 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12741 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12744 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12745 SDValue CstFAdd = DAG.getConstantFP(
12746 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12747 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12748 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12749 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12750 makeArrayRef(&CstFAddArray[0], NumElts));
12752 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12753 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12754 // TODO: Are there any fast-math-flags to propagate here?
12756 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12757 // return (float4) lo + fhi;
12758 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12759 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12762 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12763 SelectionDAG &DAG) const {
12764 SDValue N0 = Op.getOperand(0);
12765 MVT SVT = N0.getSimpleValueType();
12768 switch (SVT.SimpleTy) {
12770 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12775 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12776 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12777 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12781 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12784 assert(Subtarget->hasAVX512());
12785 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12786 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12790 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12791 SelectionDAG &DAG) const {
12792 SDValue N0 = Op.getOperand(0);
12794 auto PtrVT = getPointerTy(DAG.getDataLayout());
12796 if (Op.getSimpleValueType().isVector())
12797 return lowerUINT_TO_FP_vec(Op, DAG);
12799 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12800 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12801 // the optimization here.
12802 if (DAG.SignBitIsZero(N0))
12803 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12805 MVT SrcVT = N0.getSimpleValueType();
12806 MVT DstVT = Op.getSimpleValueType();
12808 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12809 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12810 // Conversions from unsigned i32 to f32/f64 are legal,
12811 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12815 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12816 return LowerUINT_TO_FP_i64(Op, DAG);
12817 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12818 return LowerUINT_TO_FP_i32(Op, DAG);
12819 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12822 // Make a 64-bit buffer, and use it to build an FILD.
12823 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12824 if (SrcVT == MVT::i32) {
12825 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12826 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12827 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12828 StackSlot, MachinePointerInfo(),
12830 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12831 OffsetSlot, MachinePointerInfo(),
12833 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12837 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12838 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12839 StackSlot, MachinePointerInfo(),
12841 // For i64 source, we need to add the appropriate power of 2 if the input
12842 // was negative. This is the same as the optimization in
12843 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12844 // we must be careful to do the computation in x87 extended precision, not
12845 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12846 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12847 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12848 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12849 MachineMemOperand::MOLoad, 8, 8);
12851 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12852 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12853 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12856 APInt FF(32, 0x5F800000ULL);
12858 // Check whether the sign bit is set.
12859 SDValue SignSet = DAG.getSetCC(
12860 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12861 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12863 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12864 SDValue FudgePtr = DAG.getConstantPool(
12865 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12867 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12868 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12869 SDValue Four = DAG.getIntPtrConstant(4, dl);
12870 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12872 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12874 // Load the value out, extending it from f32 to f80.
12875 // FIXME: Avoid the extend by constructing the right constant pool?
12876 SDValue Fudge = DAG.getExtLoad(
12877 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12878 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12879 false, false, false, 4);
12880 // Extend everything to 80 bits to force it to be done on x87.
12881 // TODO: Are there any fast-math-flags to propagate here?
12882 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12883 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12884 DAG.getIntPtrConstant(0, dl));
12887 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12888 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12889 // just return an <SDValue(), SDValue()> pair.
12890 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12891 // to i16, i32 or i64, and we lower it to a legal sequence.
12892 // If lowered to the final integer result we return a <result, SDValue()> pair.
12893 // Otherwise we lower it to a sequence ending with a FIST, return a
12894 // <FIST, StackSlot> pair, and the caller is responsible for loading
12895 // the final integer result from StackSlot.
12896 std::pair<SDValue,SDValue>
12897 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12898 bool IsSigned, bool IsReplace) const {
12901 EVT DstTy = Op.getValueType();
12902 EVT TheVT = Op.getOperand(0).getValueType();
12903 auto PtrVT = getPointerTy(DAG.getDataLayout());
12905 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12906 // f16 must be promoted before using the lowering in this routine.
12907 // fp128 does not use this lowering.
12908 return std::make_pair(SDValue(), SDValue());
12911 // If using FIST to compute an unsigned i64, we'll need some fixup
12912 // to handle values above the maximum signed i64. A FIST is always
12913 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12914 bool UnsignedFixup = !IsSigned &&
12915 DstTy == MVT::i64 &&
12916 (!Subtarget->is64Bit() ||
12917 !isScalarFPTypeInSSEReg(TheVT));
12919 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12920 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12921 // The low 32 bits of the fist result will have the correct uint32 result.
12922 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12926 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12927 DstTy.getSimpleVT() >= MVT::i16 &&
12928 "Unknown FP_TO_INT to lower!");
12930 // These are really Legal.
12931 if (DstTy == MVT::i32 &&
12932 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12933 return std::make_pair(SDValue(), SDValue());
12934 if (Subtarget->is64Bit() &&
12935 DstTy == MVT::i64 &&
12936 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12937 return std::make_pair(SDValue(), SDValue());
12939 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12941 MachineFunction &MF = DAG.getMachineFunction();
12942 unsigned MemSize = DstTy.getSizeInBits()/8;
12943 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12944 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12947 switch (DstTy.getSimpleVT().SimpleTy) {
12948 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12949 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12950 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12951 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12954 SDValue Chain = DAG.getEntryNode();
12955 SDValue Value = Op.getOperand(0);
12956 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12958 if (UnsignedFixup) {
12960 // Conversion to unsigned i64 is implemented with a select,
12961 // depending on whether the source value fits in the range
12962 // of a signed i64. Let Thresh be the FP equivalent of
12963 // 0x8000000000000000ULL.
12965 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12966 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12967 // Fist-to-mem64 FistSrc
12968 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12969 // to XOR'ing the high 32 bits with Adjust.
12971 // Being a power of 2, Thresh is exactly representable in all FP formats.
12972 // For X87 we'd like to use the smallest FP type for this constant, but
12973 // for DAG type consistency we have to match the FP operand type.
12975 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12976 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12977 bool LosesInfo = false;
12978 if (TheVT == MVT::f64)
12979 // The rounding mode is irrelevant as the conversion should be exact.
12980 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12982 else if (TheVT == MVT::f80)
12983 Status = Thresh.convert(APFloat::x87DoubleExtended,
12984 APFloat::rmNearestTiesToEven, &LosesInfo);
12986 assert(Status == APFloat::opOK && !LosesInfo &&
12987 "FP conversion should have been exact");
12989 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12991 SDValue Cmp = DAG.getSetCC(DL,
12992 getSetCCResultType(DAG.getDataLayout(),
12993 *DAG.getContext(), TheVT),
12994 Value, ThreshVal, ISD::SETLT);
12995 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12996 DAG.getConstant(0, DL, MVT::i32),
12997 DAG.getConstant(0x80000000, DL, MVT::i32));
12998 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12999 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
13000 *DAG.getContext(), TheVT),
13001 Value, ThreshVal, ISD::SETLT);
13002 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
13005 // FIXME This causes a redundant load/store if the SSE-class value is already
13006 // in memory, such as if it is on the callstack.
13007 if (isScalarFPTypeInSSEReg(TheVT)) {
13008 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
13009 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
13010 MachinePointerInfo::getFixedStack(MF, SSFI), false,
13012 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
13014 Chain, StackSlot, DAG.getValueType(TheVT)
13017 MachineMemOperand *MMO =
13018 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13019 MachineMemOperand::MOLoad, MemSize, MemSize);
13020 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
13021 Chain = Value.getValue(1);
13022 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
13023 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
13026 MachineMemOperand *MMO =
13027 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
13028 MachineMemOperand::MOStore, MemSize, MemSize);
13030 if (UnsignedFixup) {
13032 // Insert the FIST, load its result as two i32's,
13033 // and XOR the high i32 with Adjust.
13035 SDValue FistOps[] = { Chain, Value, StackSlot };
13036 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13037 FistOps, DstTy, MMO);
13039 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
13040 MachinePointerInfo(),
13041 false, false, false, 0);
13042 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
13043 DAG.getConstant(4, DL, PtrVT));
13045 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
13046 MachinePointerInfo(),
13047 false, false, false, 0);
13048 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
13050 if (Subtarget->is64Bit()) {
13051 // Join High32 and Low32 into a 64-bit result.
13052 // (High32 << 32) | Low32
13053 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
13054 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
13055 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
13056 DAG.getConstant(32, DL, MVT::i8));
13057 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
13058 return std::make_pair(Result, SDValue());
13061 SDValue ResultOps[] = { Low32, High32 };
13063 SDValue pair = IsReplace
13064 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
13065 : DAG.getMergeValues(ResultOps, DL);
13066 return std::make_pair(pair, SDValue());
13068 // Build the FP_TO_INT*_IN_MEM
13069 SDValue Ops[] = { Chain, Value, StackSlot };
13070 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
13072 return std::make_pair(FIST, StackSlot);
13076 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13077 const X86Subtarget *Subtarget) {
13078 MVT VT = Op->getSimpleValueType(0);
13079 SDValue In = Op->getOperand(0);
13080 MVT InVT = In.getSimpleValueType();
13083 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
13084 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13086 // Optimize vectors in AVX mode:
13089 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13090 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13091 // Concat upper and lower parts.
13094 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13095 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13096 // Concat upper and lower parts.
13099 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13100 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13101 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13104 if (Subtarget->hasInt256())
13105 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13107 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13108 SDValue Undef = DAG.getUNDEF(InVT);
13109 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13110 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13111 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13113 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13114 VT.getVectorNumElements()/2);
13116 OpLo = DAG.getBitcast(HVT, OpLo);
13117 OpHi = DAG.getBitcast(HVT, OpHi);
13119 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13122 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13123 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13124 MVT VT = Op->getSimpleValueType(0);
13125 SDValue In = Op->getOperand(0);
13126 MVT InVT = In.getSimpleValueType();
13128 unsigned int NumElts = VT.getVectorNumElements();
13129 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13132 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13133 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13135 assert(InVT.getVectorElementType() == MVT::i1);
13136 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13138 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13140 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13142 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13143 if (VT.is512BitVector())
13145 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13148 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13149 SelectionDAG &DAG) {
13150 if (Subtarget->hasFp256())
13151 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13157 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13158 SelectionDAG &DAG) {
13160 MVT VT = Op.getSimpleValueType();
13161 SDValue In = Op.getOperand(0);
13162 MVT SVT = In.getSimpleValueType();
13164 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13165 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13167 if (Subtarget->hasFp256())
13168 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13171 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13172 VT.getVectorNumElements() != SVT.getVectorNumElements());
13176 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13178 MVT VT = Op.getSimpleValueType();
13179 SDValue In = Op.getOperand(0);
13180 MVT InVT = In.getSimpleValueType();
13182 if (VT == MVT::i1) {
13183 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13184 "Invalid scalar TRUNCATE operation");
13185 if (InVT.getSizeInBits() >= 32)
13187 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13188 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13190 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13191 "Invalid TRUNCATE operation");
13193 // move vector to mask - truncate solution for SKX
13194 if (VT.getVectorElementType() == MVT::i1) {
13195 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13196 Subtarget->hasBWI())
13197 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13198 if ((InVT.is256BitVector() || InVT.is128BitVector())
13199 && InVT.getScalarSizeInBits() <= 16 &&
13200 Subtarget->hasBWI() && Subtarget->hasVLX())
13201 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13202 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13203 Subtarget->hasDQI())
13204 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13205 if ((InVT.is256BitVector() || InVT.is128BitVector())
13206 && InVT.getScalarSizeInBits() >= 32 &&
13207 Subtarget->hasDQI() && Subtarget->hasVLX())
13208 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13211 if (VT.getVectorElementType() == MVT::i1) {
13212 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13213 unsigned NumElts = InVT.getVectorNumElements();
13214 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13215 if (InVT.getSizeInBits() < 512) {
13216 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13217 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13222 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13223 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13224 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13227 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13228 if (Subtarget->hasAVX512()) {
13229 // word to byte only under BWI
13230 if (InVT == MVT::v16i16 && !Subtarget->hasBWI()) // v16i16 -> v16i8
13231 return DAG.getNode(X86ISD::VTRUNC, DL, VT,
13232 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In));
13233 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13235 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13236 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13237 if (Subtarget->hasInt256()) {
13238 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13239 In = DAG.getBitcast(MVT::v8i32, In);
13240 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13242 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13243 DAG.getIntPtrConstant(0, DL));
13246 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13247 DAG.getIntPtrConstant(0, DL));
13248 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13249 DAG.getIntPtrConstant(2, DL));
13250 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13251 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13252 static const int ShufMask[] = {0, 2, 4, 6};
13253 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13256 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13257 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13258 if (Subtarget->hasInt256()) {
13259 In = DAG.getBitcast(MVT::v32i8, In);
13261 SmallVector<SDValue,32> pshufbMask;
13262 for (unsigned i = 0; i < 2; ++i) {
13263 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13264 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13265 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13266 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13267 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13268 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13269 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13270 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13271 for (unsigned j = 0; j < 8; ++j)
13272 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13274 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13275 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13276 In = DAG.getBitcast(MVT::v4i64, In);
13278 static const int ShufMask[] = {0, 2, -1, -1};
13279 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13281 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13282 DAG.getIntPtrConstant(0, DL));
13283 return DAG.getBitcast(VT, In);
13286 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13287 DAG.getIntPtrConstant(0, DL));
13289 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13290 DAG.getIntPtrConstant(4, DL));
13292 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13293 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13295 // The PSHUFB mask:
13296 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13297 -1, -1, -1, -1, -1, -1, -1, -1};
13299 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13300 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13301 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13303 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13304 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13306 // The MOVLHPS Mask:
13307 static const int ShufMask2[] = {0, 1, 4, 5};
13308 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13309 return DAG.getBitcast(MVT::v8i16, res);
13312 // Handle truncation of V256 to V128 using shuffles.
13313 if (!VT.is128BitVector() || !InVT.is256BitVector())
13316 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13318 unsigned NumElems = VT.getVectorNumElements();
13319 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13321 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13322 // Prepare truncation shuffle mask
13323 for (unsigned i = 0; i != NumElems; ++i)
13324 MaskVec[i] = i * 2;
13325 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13326 DAG.getUNDEF(NVT), &MaskVec[0]);
13327 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13328 DAG.getIntPtrConstant(0, DL));
13331 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13332 SelectionDAG &DAG) const {
13333 assert(!Op.getSimpleValueType().isVector());
13335 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13336 /*IsSigned=*/ true, /*IsReplace=*/ false);
13337 SDValue FIST = Vals.first, StackSlot = Vals.second;
13338 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13339 if (!FIST.getNode())
13342 if (StackSlot.getNode())
13343 // Load the result.
13344 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13345 FIST, StackSlot, MachinePointerInfo(),
13346 false, false, false, 0);
13348 // The node is the result.
13352 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13353 SelectionDAG &DAG) const {
13354 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13355 /*IsSigned=*/ false, /*IsReplace=*/ false);
13356 SDValue FIST = Vals.first, StackSlot = Vals.second;
13357 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13358 if (!FIST.getNode())
13361 if (StackSlot.getNode())
13362 // Load the result.
13363 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13364 FIST, StackSlot, MachinePointerInfo(),
13365 false, false, false, 0);
13367 // The node is the result.
13371 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13373 MVT VT = Op.getSimpleValueType();
13374 SDValue In = Op.getOperand(0);
13375 MVT SVT = In.getSimpleValueType();
13377 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13379 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13380 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13381 In, DAG.getUNDEF(SVT)));
13384 /// The only differences between FABS and FNEG are the mask and the logic op.
13385 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13386 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13387 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13388 "Wrong opcode for lowering FABS or FNEG.");
13390 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13392 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13393 // into an FNABS. We'll lower the FABS after that if it is still in use.
13395 for (SDNode *User : Op->uses())
13396 if (User->getOpcode() == ISD::FNEG)
13400 MVT VT = Op.getSimpleValueType();
13402 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13403 // decide if we should generate a 16-byte constant mask when we only need 4 or
13404 // 8 bytes for the scalar case.
13410 if (VT.isVector()) {
13412 EltVT = VT.getVectorElementType();
13413 NumElts = VT.getVectorNumElements();
13415 // There are no scalar bitwise logical SSE/AVX instructions, so we
13416 // generate a 16-byte vector constant and logic op even for the scalar case.
13417 // Using a 16-byte mask allows folding the load of the mask with
13418 // the logic op, so it can save (~4 bytes) on code size.
13419 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13421 NumElts = (VT == MVT::f64) ? 2 : 4;
13424 unsigned EltBits = EltVT.getSizeInBits();
13425 LLVMContext *Context = DAG.getContext();
13426 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13428 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13429 Constant *C = ConstantInt::get(*Context, MaskElt);
13430 C = ConstantVector::getSplat(NumElts, C);
13431 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13432 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13433 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13435 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13436 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13437 false, false, false, Alignment);
13439 SDValue Op0 = Op.getOperand(0);
13440 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13442 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13443 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13446 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13448 // For the scalar case extend to a 128-bit vector, perform the logic op,
13449 // and extract the scalar result back out.
13450 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13451 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13452 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13453 DAG.getIntPtrConstant(0, dl));
13456 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13457 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13458 LLVMContext *Context = DAG.getContext();
13459 SDValue Op0 = Op.getOperand(0);
13460 SDValue Op1 = Op.getOperand(1);
13462 MVT VT = Op.getSimpleValueType();
13463 MVT SrcVT = Op1.getSimpleValueType();
13465 // If second operand is smaller, extend it first.
13466 if (SrcVT.bitsLT(VT)) {
13467 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13470 // And if it is bigger, shrink it first.
13471 if (SrcVT.bitsGT(VT)) {
13472 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13476 // At this point the operands and the result should have the same
13477 // type, and that won't be f80 since that is not custom lowered.
13479 const fltSemantics &Sem =
13480 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13481 const unsigned SizeInBits = VT.getSizeInBits();
13483 SmallVector<Constant *, 4> CV(
13484 VT == MVT::f64 ? 2 : 4,
13485 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13487 // First, clear all bits but the sign bit from the second operand (sign).
13488 CV[0] = ConstantFP::get(*Context,
13489 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13490 Constant *C = ConstantVector::get(CV);
13491 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13492 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13494 // Perform all logic operations as 16-byte vectors because there are no
13495 // scalar FP logic instructions in SSE. This allows load folding of the
13496 // constants into the logic instructions.
13497 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13499 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13500 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13501 false, false, false, 16);
13502 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13503 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13505 // Next, clear the sign bit from the first operand (magnitude).
13506 // If it's a constant, we can clear it here.
13507 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13508 APFloat APF = Op0CN->getValueAPF();
13509 // If the magnitude is a positive zero, the sign bit alone is enough.
13510 if (APF.isPosZero())
13511 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13512 DAG.getIntPtrConstant(0, dl));
13514 CV[0] = ConstantFP::get(*Context, APF);
13516 CV[0] = ConstantFP::get(
13518 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13520 C = ConstantVector::get(CV);
13521 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13523 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13524 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13525 false, false, false, 16);
13526 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13527 if (!isa<ConstantFPSDNode>(Op0)) {
13528 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13529 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13531 // OR the magnitude value with the sign bit.
13532 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13533 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13534 DAG.getIntPtrConstant(0, dl));
13537 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13538 SDValue N0 = Op.getOperand(0);
13540 MVT VT = Op.getSimpleValueType();
13542 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13543 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13544 DAG.getConstant(1, dl, VT));
13545 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13548 // Check whether an OR'd tree is PTEST-able.
13549 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13550 SelectionDAG &DAG) {
13551 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13553 if (!Subtarget->hasSSE41())
13556 if (!Op->hasOneUse())
13559 SDNode *N = Op.getNode();
13562 SmallVector<SDValue, 8> Opnds;
13563 DenseMap<SDValue, unsigned> VecInMap;
13564 SmallVector<SDValue, 8> VecIns;
13565 EVT VT = MVT::Other;
13567 // Recognize a special case where a vector is casted into wide integer to
13569 Opnds.push_back(N->getOperand(0));
13570 Opnds.push_back(N->getOperand(1));
13572 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13573 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13574 // BFS traverse all OR'd operands.
13575 if (I->getOpcode() == ISD::OR) {
13576 Opnds.push_back(I->getOperand(0));
13577 Opnds.push_back(I->getOperand(1));
13578 // Re-evaluate the number of nodes to be traversed.
13579 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13583 // Quit if a non-EXTRACT_VECTOR_ELT
13584 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13587 // Quit if without a constant index.
13588 SDValue Idx = I->getOperand(1);
13589 if (!isa<ConstantSDNode>(Idx))
13592 SDValue ExtractedFromVec = I->getOperand(0);
13593 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13594 if (M == VecInMap.end()) {
13595 VT = ExtractedFromVec.getValueType();
13596 // Quit if not 128/256-bit vector.
13597 if (!VT.is128BitVector() && !VT.is256BitVector())
13599 // Quit if not the same type.
13600 if (VecInMap.begin() != VecInMap.end() &&
13601 VT != VecInMap.begin()->first.getValueType())
13603 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13604 VecIns.push_back(ExtractedFromVec);
13606 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13609 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13610 "Not extracted from 128-/256-bit vector.");
13612 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13614 for (DenseMap<SDValue, unsigned>::const_iterator
13615 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13616 // Quit if not all elements are used.
13617 if (I->second != FullMask)
13621 MVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13623 // Cast all vectors into TestVT for PTEST.
13624 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13625 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13627 // If more than one full vectors are evaluated, OR them first before PTEST.
13628 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13629 // Each iteration will OR 2 nodes and append the result until there is only
13630 // 1 node left, i.e. the final OR'd value of all vectors.
13631 SDValue LHS = VecIns[Slot];
13632 SDValue RHS = VecIns[Slot + 1];
13633 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13636 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13637 VecIns.back(), VecIns.back());
13640 /// \brief return true if \c Op has a use that doesn't just read flags.
13641 static bool hasNonFlagsUse(SDValue Op) {
13642 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13644 SDNode *User = *UI;
13645 unsigned UOpNo = UI.getOperandNo();
13646 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13647 // Look pass truncate.
13648 UOpNo = User->use_begin().getOperandNo();
13649 User = *User->use_begin();
13652 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13653 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13659 /// Emit nodes that will be selected as "test Op0,Op0", or something
13661 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13662 SelectionDAG &DAG) const {
13663 if (Op.getValueType() == MVT::i1) {
13664 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13665 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13666 DAG.getConstant(0, dl, MVT::i8));
13668 // CF and OF aren't always set the way we want. Determine which
13669 // of these we need.
13670 bool NeedCF = false;
13671 bool NeedOF = false;
13674 case X86::COND_A: case X86::COND_AE:
13675 case X86::COND_B: case X86::COND_BE:
13678 case X86::COND_G: case X86::COND_GE:
13679 case X86::COND_L: case X86::COND_LE:
13680 case X86::COND_O: case X86::COND_NO: {
13681 // Check if we really need to set the
13682 // Overflow flag. If NoSignedWrap is present
13683 // that is not actually needed.
13684 switch (Op->getOpcode()) {
13689 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13690 if (BinNode->Flags.hasNoSignedWrap())
13700 // See if we can use the EFLAGS value from the operand instead of
13701 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13702 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13703 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13704 // Emit a CMP with 0, which is the TEST pattern.
13705 //if (Op.getValueType() == MVT::i1)
13706 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13707 // DAG.getConstant(0, MVT::i1));
13708 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13709 DAG.getConstant(0, dl, Op.getValueType()));
13711 unsigned Opcode = 0;
13712 unsigned NumOperands = 0;
13714 // Truncate operations may prevent the merge of the SETCC instruction
13715 // and the arithmetic instruction before it. Attempt to truncate the operands
13716 // of the arithmetic instruction and use a reduced bit-width instruction.
13717 bool NeedTruncation = false;
13718 SDValue ArithOp = Op;
13719 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13720 SDValue Arith = Op->getOperand(0);
13721 // Both the trunc and the arithmetic op need to have one user each.
13722 if (Arith->hasOneUse())
13723 switch (Arith.getOpcode()) {
13730 NeedTruncation = true;
13736 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13737 // which may be the result of a CAST. We use the variable 'Op', which is the
13738 // non-casted variable when we check for possible users.
13739 switch (ArithOp.getOpcode()) {
13741 // Due to an isel shortcoming, be conservative if this add is likely to be
13742 // selected as part of a load-modify-store instruction. When the root node
13743 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13744 // uses of other nodes in the match, such as the ADD in this case. This
13745 // leads to the ADD being left around and reselected, with the result being
13746 // two adds in the output. Alas, even if none our users are stores, that
13747 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13748 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13749 // climbing the DAG back to the root, and it doesn't seem to be worth the
13751 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13752 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13753 if (UI->getOpcode() != ISD::CopyToReg &&
13754 UI->getOpcode() != ISD::SETCC &&
13755 UI->getOpcode() != ISD::STORE)
13758 if (ConstantSDNode *C =
13759 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13760 // An add of one will be selected as an INC.
13761 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13762 Opcode = X86ISD::INC;
13767 // An add of negative one (subtract of one) will be selected as a DEC.
13768 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13769 Opcode = X86ISD::DEC;
13775 // Otherwise use a regular EFLAGS-setting add.
13776 Opcode = X86ISD::ADD;
13781 // If we have a constant logical shift that's only used in a comparison
13782 // against zero turn it into an equivalent AND. This allows turning it into
13783 // a TEST instruction later.
13784 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13785 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13786 EVT VT = Op.getValueType();
13787 unsigned BitWidth = VT.getSizeInBits();
13788 unsigned ShAmt = Op->getConstantOperandVal(1);
13789 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13791 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13792 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13793 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13794 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13796 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13797 DAG.getConstant(Mask, dl, VT));
13798 DAG.ReplaceAllUsesWith(Op, New);
13804 // If the primary and result isn't used, don't bother using X86ISD::AND,
13805 // because a TEST instruction will be better.
13806 if (!hasNonFlagsUse(Op))
13812 // Due to the ISEL shortcoming noted above, be conservative if this op is
13813 // likely to be selected as part of a load-modify-store instruction.
13814 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13815 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13816 if (UI->getOpcode() == ISD::STORE)
13819 // Otherwise use a regular EFLAGS-setting instruction.
13820 switch (ArithOp.getOpcode()) {
13821 default: llvm_unreachable("unexpected operator!");
13822 case ISD::SUB: Opcode = X86ISD::SUB; break;
13823 case ISD::XOR: Opcode = X86ISD::XOR; break;
13824 case ISD::AND: Opcode = X86ISD::AND; break;
13826 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13827 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13828 if (EFLAGS.getNode())
13831 Opcode = X86ISD::OR;
13845 return SDValue(Op.getNode(), 1);
13851 // If we found that truncation is beneficial, perform the truncation and
13853 if (NeedTruncation) {
13854 EVT VT = Op.getValueType();
13855 SDValue WideVal = Op->getOperand(0);
13856 EVT WideVT = WideVal.getValueType();
13857 unsigned ConvertedOp = 0;
13858 // Use a target machine opcode to prevent further DAGCombine
13859 // optimizations that may separate the arithmetic operations
13860 // from the setcc node.
13861 switch (WideVal.getOpcode()) {
13863 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13864 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13865 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13866 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13867 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13871 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13872 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13873 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13874 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13875 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13881 // Emit a CMP with 0, which is the TEST pattern.
13882 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13883 DAG.getConstant(0, dl, Op.getValueType()));
13885 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13886 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13888 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13889 DAG.ReplaceAllUsesWith(Op, New);
13890 return SDValue(New.getNode(), 1);
13893 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13895 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13896 SDLoc dl, SelectionDAG &DAG) const {
13897 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13898 if (C->getAPIntValue() == 0)
13899 return EmitTest(Op0, X86CC, dl, DAG);
13901 assert(Op0.getValueType() != MVT::i1 &&
13902 "Unexpected comparison operation for MVT::i1 operands");
13905 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13906 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13907 // Do the comparison at i32 if it's smaller, besides the Atom case.
13908 // This avoids subregister aliasing issues. Keep the smaller reference
13909 // if we're optimizing for size, however, as that'll allow better folding
13910 // of memory operations.
13911 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13912 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13913 !Subtarget->isAtom()) {
13914 unsigned ExtendOp =
13915 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13916 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13917 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13919 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13920 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13921 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13923 return SDValue(Sub.getNode(), 1);
13925 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13928 /// Convert a comparison if required by the subtarget.
13929 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13930 SelectionDAG &DAG) const {
13931 // If the subtarget does not support the FUCOMI instruction, floating-point
13932 // comparisons have to be converted.
13933 if (Subtarget->hasCMov() ||
13934 Cmp.getOpcode() != X86ISD::CMP ||
13935 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13936 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13939 // The instruction selector will select an FUCOM instruction instead of
13940 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13941 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13942 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13944 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13945 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13946 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13947 DAG.getConstant(8, dl, MVT::i8));
13948 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13949 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13952 /// The minimum architected relative accuracy is 2^-12. We need one
13953 /// Newton-Raphson step to have a good float result (24 bits of precision).
13954 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13955 DAGCombinerInfo &DCI,
13956 unsigned &RefinementSteps,
13957 bool &UseOneConstNR) const {
13958 EVT VT = Op.getValueType();
13959 const char *RecipOp;
13961 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13962 // TODO: Add support for AVX512 (v16f32).
13963 // It is likely not profitable to do this for f64 because a double-precision
13964 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13965 // instructions: convert to single, rsqrtss, convert back to double, refine
13966 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13967 // along with FMA, this could be a throughput win.
13968 if (VT == MVT::f32 && Subtarget->hasSSE1())
13970 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13971 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13972 RecipOp = "vec-sqrtf";
13976 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13977 if (!Recips.isEnabled(RecipOp))
13980 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13981 UseOneConstNR = false;
13982 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13985 /// The minimum architected relative accuracy is 2^-12. We need one
13986 /// Newton-Raphson step to have a good float result (24 bits of precision).
13987 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13988 DAGCombinerInfo &DCI,
13989 unsigned &RefinementSteps) const {
13990 EVT VT = Op.getValueType();
13991 const char *RecipOp;
13993 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13994 // TODO: Add support for AVX512 (v16f32).
13995 // It is likely not profitable to do this for f64 because a double-precision
13996 // reciprocal estimate with refinement on x86 prior to FMA requires
13997 // 15 instructions: convert to single, rcpss, convert back to double, refine
13998 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13999 // along with FMA, this could be a throughput win.
14000 if (VT == MVT::f32 && Subtarget->hasSSE1())
14002 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
14003 (VT == MVT::v8f32 && Subtarget->hasAVX()))
14004 RecipOp = "vec-divf";
14008 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
14009 if (!Recips.isEnabled(RecipOp))
14012 RefinementSteps = Recips.getRefinementSteps(RecipOp);
14013 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
14016 /// If we have at least two divisions that use the same divisor, convert to
14017 /// multplication by a reciprocal. This may need to be adjusted for a given
14018 /// CPU if a division's cost is not at least twice the cost of a multiplication.
14019 /// This is because we still need one division to calculate the reciprocal and
14020 /// then we need two multiplies by that reciprocal as replacements for the
14021 /// original divisions.
14022 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
14026 static bool isAllOnes(SDValue V) {
14027 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
14028 return C && C->isAllOnesValue();
14031 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
14032 /// if it's possible.
14033 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
14034 SDLoc dl, SelectionDAG &DAG) const {
14035 SDValue Op0 = And.getOperand(0);
14036 SDValue Op1 = And.getOperand(1);
14037 if (Op0.getOpcode() == ISD::TRUNCATE)
14038 Op0 = Op0.getOperand(0);
14039 if (Op1.getOpcode() == ISD::TRUNCATE)
14040 Op1 = Op1.getOperand(0);
14043 if (Op1.getOpcode() == ISD::SHL)
14044 std::swap(Op0, Op1);
14045 if (Op0.getOpcode() == ISD::SHL) {
14046 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
14047 if (And00C->getZExtValue() == 1) {
14048 // If we looked past a truncate, check that it's only truncating away
14050 unsigned BitWidth = Op0.getValueSizeInBits();
14051 unsigned AndBitWidth = And.getValueSizeInBits();
14052 if (BitWidth > AndBitWidth) {
14054 DAG.computeKnownBits(Op0, Zeros, Ones);
14055 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
14059 RHS = Op0.getOperand(1);
14061 } else if (Op1.getOpcode() == ISD::Constant) {
14062 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
14063 uint64_t AndRHSVal = AndRHS->getZExtValue();
14064 SDValue AndLHS = Op0;
14066 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
14067 LHS = AndLHS.getOperand(0);
14068 RHS = AndLHS.getOperand(1);
14071 // Use BT if the immediate can't be encoded in a TEST instruction.
14072 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
14074 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
14078 if (LHS.getNode()) {
14079 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14080 // instruction. Since the shift amount is in-range-or-undefined, we know
14081 // that doing a bittest on the i32 value is ok. We extend to i32 because
14082 // the encoding for the i16 version is larger than the i32 version.
14083 // Also promote i16 to i32 for performance / code size reason.
14084 if (LHS.getValueType() == MVT::i8 ||
14085 LHS.getValueType() == MVT::i16)
14086 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14088 // If the operand types disagree, extend the shift amount to match. Since
14089 // BT ignores high bits (like shifts) we can use anyextend.
14090 if (LHS.getValueType() != RHS.getValueType())
14091 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14093 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14094 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14095 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14096 DAG.getConstant(Cond, dl, MVT::i8), BT);
14102 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14104 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14109 // SSE Condition code mapping:
14118 switch (SetCCOpcode) {
14119 default: llvm_unreachable("Unexpected SETCC condition");
14121 case ISD::SETEQ: SSECC = 0; break;
14123 case ISD::SETGT: Swap = true; // Fallthrough
14125 case ISD::SETOLT: SSECC = 1; break;
14127 case ISD::SETGE: Swap = true; // Fallthrough
14129 case ISD::SETOLE: SSECC = 2; break;
14130 case ISD::SETUO: SSECC = 3; break;
14132 case ISD::SETNE: SSECC = 4; break;
14133 case ISD::SETULE: Swap = true; // Fallthrough
14134 case ISD::SETUGE: SSECC = 5; break;
14135 case ISD::SETULT: Swap = true; // Fallthrough
14136 case ISD::SETUGT: SSECC = 6; break;
14137 case ISD::SETO: SSECC = 7; break;
14139 case ISD::SETONE: SSECC = 8; break;
14142 std::swap(Op0, Op1);
14147 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14148 // ones, and then concatenate the result back.
14149 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14150 MVT VT = Op.getSimpleValueType();
14152 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14153 "Unsupported value type for operation");
14155 unsigned NumElems = VT.getVectorNumElements();
14157 SDValue CC = Op.getOperand(2);
14159 // Extract the LHS vectors
14160 SDValue LHS = Op.getOperand(0);
14161 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14162 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14164 // Extract the RHS vectors
14165 SDValue RHS = Op.getOperand(1);
14166 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14167 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14169 // Issue the operation on the smaller types and concatenate the result back
14170 MVT EltVT = VT.getVectorElementType();
14171 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14172 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14173 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14174 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14177 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14178 SDValue Op0 = Op.getOperand(0);
14179 SDValue Op1 = Op.getOperand(1);
14180 SDValue CC = Op.getOperand(2);
14181 MVT VT = Op.getSimpleValueType();
14184 assert(Op0.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14185 "Unexpected type for boolean compare operation");
14186 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14187 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14188 DAG.getConstant(-1, dl, VT));
14189 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14190 DAG.getConstant(-1, dl, VT));
14191 switch (SetCCOpcode) {
14192 default: llvm_unreachable("Unexpected SETCC condition");
14194 // (x == y) -> ~(x ^ y)
14195 return DAG.getNode(ISD::XOR, dl, VT,
14196 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14197 DAG.getConstant(-1, dl, VT));
14199 // (x != y) -> (x ^ y)
14200 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14203 // (x > y) -> (x & ~y)
14204 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14207 // (x < y) -> (~x & y)
14208 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14211 // (x <= y) -> (~x | y)
14212 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14215 // (x >=y) -> (x | ~y)
14216 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14220 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14221 const X86Subtarget *Subtarget) {
14222 SDValue Op0 = Op.getOperand(0);
14223 SDValue Op1 = Op.getOperand(1);
14224 SDValue CC = Op.getOperand(2);
14225 MVT VT = Op.getSimpleValueType();
14228 assert(Op0.getSimpleValueType().getVectorElementType().getSizeInBits() >= 8 &&
14229 Op.getSimpleValueType().getVectorElementType() == MVT::i1 &&
14230 "Cannot set masked compare for this operation");
14232 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14234 bool Unsigned = false;
14237 switch (SetCCOpcode) {
14238 default: llvm_unreachable("Unexpected SETCC condition");
14239 case ISD::SETNE: SSECC = 4; break;
14240 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14241 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14242 case ISD::SETLT: Swap = true; //fall-through
14243 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14244 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14245 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14246 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14247 case ISD::SETULE: Unsigned = true; //fall-through
14248 case ISD::SETLE: SSECC = 2; break;
14252 std::swap(Op0, Op1);
14254 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14255 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14256 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14257 DAG.getConstant(SSECC, dl, MVT::i8));
14260 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14261 /// operand \p Op1. If non-trivial (for example because it's not constant)
14262 /// return an empty value.
14263 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14265 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14269 MVT VT = Op1.getSimpleValueType();
14270 MVT EVT = VT.getVectorElementType();
14271 unsigned n = VT.getVectorNumElements();
14272 SmallVector<SDValue, 8> ULTOp1;
14274 for (unsigned i = 0; i < n; ++i) {
14275 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14276 if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
14279 // Avoid underflow.
14280 APInt Val = Elt->getAPIntValue();
14284 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14287 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14290 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14291 SelectionDAG &DAG) {
14292 SDValue Op0 = Op.getOperand(0);
14293 SDValue Op1 = Op.getOperand(1);
14294 SDValue CC = Op.getOperand(2);
14295 MVT VT = Op.getSimpleValueType();
14296 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14297 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14302 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14303 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14306 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14307 unsigned Opc = X86ISD::CMPP;
14308 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14309 assert(VT.getVectorNumElements() <= 16);
14310 Opc = X86ISD::CMPM;
14312 // In the two special cases we can't handle, emit two comparisons.
14315 unsigned CombineOpc;
14316 if (SetCCOpcode == ISD::SETUEQ) {
14317 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14319 assert(SetCCOpcode == ISD::SETONE);
14320 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14323 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14324 DAG.getConstant(CC0, dl, MVT::i8));
14325 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14326 DAG.getConstant(CC1, dl, MVT::i8));
14327 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14329 // Handle all other FP comparisons here.
14330 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14331 DAG.getConstant(SSECC, dl, MVT::i8));
14334 MVT VTOp0 = Op0.getSimpleValueType();
14335 assert(VTOp0 == Op1.getSimpleValueType() &&
14336 "Expected operands with same type!");
14337 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14338 "Invalid number of packed elements for source and destination!");
14340 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14341 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14342 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14343 // legalizer firstly checks if the first operand in input to the setcc has
14344 // a legal type. If so, then it promotes the return type to that same type.
14345 // Otherwise, the return type is promoted to the 'next legal type' which,
14346 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14348 // We reach this code only if the following two conditions are met:
14349 // 1. Both return type and operand type have been promoted to wider types
14350 // by the type legalizer.
14351 // 2. The original operand type has been promoted to a 256-bit vector.
14353 // Note that condition 2. only applies for AVX targets.
14354 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14355 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14358 // The non-AVX512 code below works under the assumption that source and
14359 // destination types are the same.
14360 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14361 "Value types for source and destination must be the same!");
14363 // Break 256-bit integer vector compare into smaller ones.
14364 if (VT.is256BitVector() && !Subtarget->hasInt256())
14365 return Lower256IntVSETCC(Op, DAG);
14367 MVT OpVT = Op1.getSimpleValueType();
14368 if (OpVT.getVectorElementType() == MVT::i1)
14369 return LowerBoolVSETCC_AVX512(Op, DAG);
14371 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14372 if (Subtarget->hasAVX512()) {
14373 if (Op1.getSimpleValueType().is512BitVector() ||
14374 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14375 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14376 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14378 // In AVX-512 architecture setcc returns mask with i1 elements,
14379 // But there is no compare instruction for i8 and i16 elements in KNL.
14380 // We are not talking about 512-bit operands in this case, these
14381 // types are illegal.
14383 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14384 OpVT.getVectorElementType().getSizeInBits() >= 8))
14385 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14386 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14389 // Lower using XOP integer comparisons.
14390 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14391 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14392 // Translate compare code to XOP PCOM compare mode.
14393 unsigned CmpMode = 0;
14394 switch (SetCCOpcode) {
14395 default: llvm_unreachable("Unexpected SETCC condition");
14397 case ISD::SETLT: CmpMode = 0x00; break;
14399 case ISD::SETLE: CmpMode = 0x01; break;
14401 case ISD::SETGT: CmpMode = 0x02; break;
14403 case ISD::SETGE: CmpMode = 0x03; break;
14404 case ISD::SETEQ: CmpMode = 0x04; break;
14405 case ISD::SETNE: CmpMode = 0x05; break;
14408 // Are we comparing unsigned or signed integers?
14409 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14410 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14412 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14413 DAG.getConstant(CmpMode, dl, MVT::i8));
14416 // We are handling one of the integer comparisons here. Since SSE only has
14417 // GT and EQ comparisons for integer, swapping operands and multiple
14418 // operations may be required for some comparisons.
14420 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14421 bool Subus = false;
14423 switch (SetCCOpcode) {
14424 default: llvm_unreachable("Unexpected SETCC condition");
14425 case ISD::SETNE: Invert = true;
14426 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14427 case ISD::SETLT: Swap = true;
14428 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14429 case ISD::SETGE: Swap = true;
14430 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14431 Invert = true; break;
14432 case ISD::SETULT: Swap = true;
14433 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14434 FlipSigns = true; break;
14435 case ISD::SETUGE: Swap = true;
14436 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14437 FlipSigns = true; Invert = true; break;
14440 // Special case: Use min/max operations for SETULE/SETUGE
14441 MVT VET = VT.getVectorElementType();
14443 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14444 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14447 switch (SetCCOpcode) {
14449 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14450 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14453 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14456 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14457 if (!MinMax && hasSubus) {
14458 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14460 // t = psubus Op0, Op1
14461 // pcmpeq t, <0..0>
14462 switch (SetCCOpcode) {
14464 case ISD::SETULT: {
14465 // If the comparison is against a constant we can turn this into a
14466 // setule. With psubus, setule does not require a swap. This is
14467 // beneficial because the constant in the register is no longer
14468 // destructed as the destination so it can be hoisted out of a loop.
14469 // Only do this pre-AVX since vpcmp* is no longer destructive.
14470 if (Subtarget->hasAVX())
14472 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14473 if (ULEOp1.getNode()) {
14475 Subus = true; Invert = false; Swap = false;
14479 // Psubus is better than flip-sign because it requires no inversion.
14480 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14481 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14485 Opc = X86ISD::SUBUS;
14491 std::swap(Op0, Op1);
14493 // Check that the operation in question is available (most are plain SSE2,
14494 // but PCMPGTQ and PCMPEQQ have different requirements).
14495 if (VT == MVT::v2i64) {
14496 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14497 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14499 // First cast everything to the right type.
14500 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14501 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14503 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14504 // bits of the inputs before performing those operations. The lower
14505 // compare is always unsigned.
14508 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14510 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14511 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14512 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14513 Sign, Zero, Sign, Zero);
14515 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14516 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14518 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14519 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14520 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14522 // Create masks for only the low parts/high parts of the 64 bit integers.
14523 static const int MaskHi[] = { 1, 1, 3, 3 };
14524 static const int MaskLo[] = { 0, 0, 2, 2 };
14525 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14526 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14527 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14529 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14530 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14533 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14535 return DAG.getBitcast(VT, Result);
14538 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14539 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14540 // pcmpeqd + pshufd + pand.
14541 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14543 // First cast everything to the right type.
14544 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14545 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14548 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14550 // Make sure the lower and upper halves are both all-ones.
14551 static const int Mask[] = { 1, 0, 3, 2 };
14552 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14553 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14556 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14558 return DAG.getBitcast(VT, Result);
14562 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14563 // bits of the inputs before performing those operations.
14565 MVT EltVT = VT.getVectorElementType();
14566 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14568 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14569 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14572 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14574 // If the logical-not of the result is required, perform that now.
14576 Result = DAG.getNOT(dl, Result, VT);
14579 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14582 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14583 getZeroVector(VT, Subtarget, DAG, dl));
14588 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14590 MVT VT = Op.getSimpleValueType();
14592 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14594 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14595 && "SetCC type must be 8-bit or 1-bit integer");
14596 SDValue Op0 = Op.getOperand(0);
14597 SDValue Op1 = Op.getOperand(1);
14599 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14601 // Optimize to BT if possible.
14602 // Lower (X & (1 << N)) == 0 to BT(X, N).
14603 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14604 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14605 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14606 Op1.getOpcode() == ISD::Constant &&
14607 cast<ConstantSDNode>(Op1)->isNullValue() &&
14608 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14609 if (SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG)) {
14611 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14616 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14618 if (Op1.getOpcode() == ISD::Constant &&
14619 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14620 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14621 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14623 // If the input is a setcc, then reuse the input setcc or use a new one with
14624 // the inverted condition.
14625 if (Op0.getOpcode() == X86ISD::SETCC) {
14626 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14627 bool Invert = (CC == ISD::SETNE) ^
14628 cast<ConstantSDNode>(Op1)->isNullValue();
14632 CCode = X86::GetOppositeBranchCondition(CCode);
14633 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14634 DAG.getConstant(CCode, dl, MVT::i8),
14635 Op0.getOperand(1));
14637 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14641 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14642 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14643 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14645 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14646 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14649 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14650 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14651 if (X86CC == X86::COND_INVALID)
14654 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14655 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14656 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14657 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14659 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14663 SDValue X86TargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
14664 SDValue LHS = Op.getOperand(0);
14665 SDValue RHS = Op.getOperand(1);
14666 SDValue Carry = Op.getOperand(2);
14667 SDValue Cond = Op.getOperand(3);
14670 assert(LHS.getSimpleValueType().isInteger() && "SETCCE is integer only.");
14671 X86::CondCode CC = TranslateIntegerX86CC(cast<CondCodeSDNode>(Cond)->get());
14673 assert(Carry.getOpcode() != ISD::CARRY_FALSE);
14674 SDVTList VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14675 SDValue Cmp = DAG.getNode(X86ISD::SBB, DL, VTs, LHS, RHS, Carry);
14676 return DAG.getNode(X86ISD::SETCC, DL, Op.getValueType(),
14677 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1));
14680 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14681 static bool isX86LogicalCmp(SDValue Op) {
14682 unsigned Opc = Op.getNode()->getOpcode();
14683 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14684 Opc == X86ISD::SAHF)
14686 if (Op.getResNo() == 1 &&
14687 (Opc == X86ISD::ADD ||
14688 Opc == X86ISD::SUB ||
14689 Opc == X86ISD::ADC ||
14690 Opc == X86ISD::SBB ||
14691 Opc == X86ISD::SMUL ||
14692 Opc == X86ISD::UMUL ||
14693 Opc == X86ISD::INC ||
14694 Opc == X86ISD::DEC ||
14695 Opc == X86ISD::OR ||
14696 Opc == X86ISD::XOR ||
14697 Opc == X86ISD::AND))
14700 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14706 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14707 if (V.getOpcode() != ISD::TRUNCATE)
14710 SDValue VOp0 = V.getOperand(0);
14711 unsigned InBits = VOp0.getValueSizeInBits();
14712 unsigned Bits = V.getValueSizeInBits();
14713 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14716 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14717 bool addTest = true;
14718 SDValue Cond = Op.getOperand(0);
14719 SDValue Op1 = Op.getOperand(1);
14720 SDValue Op2 = Op.getOperand(2);
14722 MVT VT = Op1.getSimpleValueType();
14725 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14726 // are available or VBLENDV if AVX is available.
14727 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14728 if (Cond.getOpcode() == ISD::SETCC &&
14729 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14730 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14731 VT == Cond.getOperand(0).getSimpleValueType() && Cond->hasOneUse()) {
14732 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14733 int SSECC = translateX86FSETCC(
14734 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14737 if (Subtarget->hasAVX512()) {
14738 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14739 DAG.getConstant(SSECC, DL, MVT::i8));
14740 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14743 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14744 DAG.getConstant(SSECC, DL, MVT::i8));
14746 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14747 // of 3 logic instructions for size savings and potentially speed.
14748 // Unfortunately, there is no scalar form of VBLENDV.
14750 // If either operand is a constant, don't try this. We can expect to
14751 // optimize away at least one of the logic instructions later in that
14752 // case, so that sequence would be faster than a variable blend.
14754 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14755 // uses XMM0 as the selection register. That may need just as many
14756 // instructions as the AND/ANDN/OR sequence due to register moves, so
14759 if (Subtarget->hasAVX() &&
14760 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14762 // Convert to vectors, do a VSELECT, and convert back to scalar.
14763 // All of the conversions should be optimized away.
14765 MVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14766 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14767 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14768 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14770 MVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14771 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14773 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14775 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14776 VSel, DAG.getIntPtrConstant(0, DL));
14778 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14779 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14780 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14784 if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
14786 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14787 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14788 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14789 Op1Scalar = Op1.getOperand(0);
14791 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14792 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14793 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14794 Op2Scalar = Op2.getOperand(0);
14795 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14796 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14797 Op1Scalar.getValueType(),
14798 Cond, Op1Scalar, Op2Scalar);
14799 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14800 return DAG.getBitcast(VT, newSelect);
14801 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14802 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14803 DAG.getIntPtrConstant(0, DL));
14807 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14808 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14809 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14810 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14811 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14812 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14813 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14815 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14818 if (Cond.getOpcode() == ISD::SETCC) {
14819 SDValue NewCond = LowerSETCC(Cond, DAG);
14820 if (NewCond.getNode())
14824 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14825 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14826 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14827 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14828 if (Cond.getOpcode() == X86ISD::SETCC &&
14829 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14830 isZero(Cond.getOperand(1).getOperand(1))) {
14831 SDValue Cmp = Cond.getOperand(1);
14833 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14835 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14836 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14837 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14839 SDValue CmpOp0 = Cmp.getOperand(0);
14840 // Apply further optimizations for special cases
14841 // (select (x != 0), -1, 0) -> neg & sbb
14842 // (select (x == 0), 0, -1) -> neg & sbb
14843 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14844 if (YC->isNullValue() &&
14845 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14846 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14847 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14848 DAG.getConstant(0, DL,
14849 CmpOp0.getValueType()),
14851 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14852 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14853 SDValue(Neg.getNode(), 1));
14857 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14858 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14859 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14861 SDValue Res = // Res = 0 or -1.
14862 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14863 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14865 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14866 Res = DAG.getNOT(DL, Res, Res.getValueType());
14868 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14869 if (!N2C || !N2C->isNullValue())
14870 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14875 // Look past (and (setcc_carry (cmp ...)), 1).
14876 if (Cond.getOpcode() == ISD::AND &&
14877 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14878 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14879 if (C && C->getAPIntValue() == 1)
14880 Cond = Cond.getOperand(0);
14883 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14884 // setting operand in place of the X86ISD::SETCC.
14885 unsigned CondOpcode = Cond.getOpcode();
14886 if (CondOpcode == X86ISD::SETCC ||
14887 CondOpcode == X86ISD::SETCC_CARRY) {
14888 CC = Cond.getOperand(0);
14890 SDValue Cmp = Cond.getOperand(1);
14891 unsigned Opc = Cmp.getOpcode();
14892 MVT VT = Op.getSimpleValueType();
14894 bool IllegalFPCMov = false;
14895 if (VT.isFloatingPoint() && !VT.isVector() &&
14896 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14897 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14899 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14900 Opc == X86ISD::BT) { // FIXME
14904 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14905 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14906 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14907 Cond.getOperand(0).getValueType() != MVT::i8)) {
14908 SDValue LHS = Cond.getOperand(0);
14909 SDValue RHS = Cond.getOperand(1);
14910 unsigned X86Opcode;
14913 switch (CondOpcode) {
14914 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14915 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14916 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14917 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14918 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14919 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14920 default: llvm_unreachable("unexpected overflowing operator");
14922 if (CondOpcode == ISD::UMULO)
14923 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14926 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14928 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14930 if (CondOpcode == ISD::UMULO)
14931 Cond = X86Op.getValue(2);
14933 Cond = X86Op.getValue(1);
14935 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14940 // Look past the truncate if the high bits are known zero.
14941 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14942 Cond = Cond.getOperand(0);
14944 // We know the result of AND is compared against zero. Try to match
14946 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14947 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG)) {
14948 CC = NewSetCC.getOperand(0);
14949 Cond = NewSetCC.getOperand(1);
14956 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14957 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14960 // a < b ? -1 : 0 -> RES = ~setcc_carry
14961 // a < b ? 0 : -1 -> RES = setcc_carry
14962 // a >= b ? -1 : 0 -> RES = setcc_carry
14963 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14964 if (Cond.getOpcode() == X86ISD::SUB) {
14965 Cond = ConvertCmpIfNecessary(Cond, DAG);
14966 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14968 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14969 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14970 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14971 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14973 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14974 return DAG.getNOT(DL, Res, Res.getValueType());
14979 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14980 // widen the cmov and push the truncate through. This avoids introducing a new
14981 // branch during isel and doesn't add any extensions.
14982 if (Op.getValueType() == MVT::i8 &&
14983 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14984 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14985 if (T1.getValueType() == T2.getValueType() &&
14986 // Blacklist CopyFromReg to avoid partial register stalls.
14987 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14988 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14989 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14990 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14994 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14995 // condition is true.
14996 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14997 SDValue Ops[] = { Op2, Op1, CC, Cond };
14998 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
15001 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
15002 const X86Subtarget *Subtarget,
15003 SelectionDAG &DAG) {
15004 MVT VT = Op->getSimpleValueType(0);
15005 SDValue In = Op->getOperand(0);
15006 MVT InVT = In.getSimpleValueType();
15007 MVT VTElt = VT.getVectorElementType();
15008 MVT InVTElt = InVT.getVectorElementType();
15012 if ((InVTElt == MVT::i1) &&
15013 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
15014 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
15016 ((Subtarget->hasBWI() && VT.is512BitVector() &&
15017 VTElt.getSizeInBits() <= 16)) ||
15019 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
15020 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
15022 ((Subtarget->hasDQI() && VT.is512BitVector() &&
15023 VTElt.getSizeInBits() >= 32))))
15024 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15026 unsigned int NumElts = VT.getVectorNumElements();
15028 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
15031 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
15032 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
15033 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
15034 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15037 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
15038 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
15040 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
15043 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
15045 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
15046 if (VT.is512BitVector())
15048 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
15051 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
15052 const X86Subtarget *Subtarget,
15053 SelectionDAG &DAG) {
15054 SDValue In = Op->getOperand(0);
15055 MVT VT = Op->getSimpleValueType(0);
15056 MVT InVT = In.getSimpleValueType();
15057 assert(VT.getSizeInBits() == InVT.getSizeInBits());
15059 MVT InSVT = InVT.getVectorElementType();
15060 assert(VT.getVectorElementType().getSizeInBits() > InSVT.getSizeInBits());
15062 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
15064 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
15069 // SSE41 targets can use the pmovsx* instructions directly.
15070 if (Subtarget->hasSSE41())
15071 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15073 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
15077 // As SRAI is only available on i16/i32 types, we expand only up to i32
15078 // and handle i64 separately.
15079 while (CurrVT != VT && CurrVT.getVectorElementType() != MVT::i32) {
15080 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
15081 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
15082 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
15083 Curr = DAG.getBitcast(CurrVT, Curr);
15086 SDValue SignExt = Curr;
15087 if (CurrVT != InVT) {
15088 unsigned SignExtShift =
15089 CurrVT.getVectorElementType().getSizeInBits() - InSVT.getSizeInBits();
15090 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15091 DAG.getConstant(SignExtShift, dl, MVT::i8));
15097 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15098 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15099 DAG.getConstant(31, dl, MVT::i8));
15100 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15101 return DAG.getBitcast(VT, Ext);
15107 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15108 SelectionDAG &DAG) {
15109 MVT VT = Op->getSimpleValueType(0);
15110 SDValue In = Op->getOperand(0);
15111 MVT InVT = In.getSimpleValueType();
15114 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15115 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15117 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15118 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15119 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15122 if (Subtarget->hasInt256())
15123 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15125 // Optimize vectors in AVX mode
15126 // Sign extend v8i16 to v8i32 and
15129 // Divide input vector into two parts
15130 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15131 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15132 // concat the vectors to original VT
15134 unsigned NumElems = InVT.getVectorNumElements();
15135 SDValue Undef = DAG.getUNDEF(InVT);
15137 SmallVector<int,8> ShufMask1(NumElems, -1);
15138 for (unsigned i = 0; i != NumElems/2; ++i)
15141 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15143 SmallVector<int,8> ShufMask2(NumElems, -1);
15144 for (unsigned i = 0; i != NumElems/2; ++i)
15145 ShufMask2[i] = i + NumElems/2;
15147 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15149 MVT HalfVT = MVT::getVectorVT(VT.getVectorElementType(),
15150 VT.getVectorNumElements()/2);
15152 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15153 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15155 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15158 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15159 // may emit an illegal shuffle but the expansion is still better than scalar
15160 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15161 // we'll emit a shuffle and a arithmetic shift.
15162 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15163 // TODO: It is possible to support ZExt by zeroing the undef values during
15164 // the shuffle phase or after the shuffle.
15165 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15166 SelectionDAG &DAG) {
15167 MVT RegVT = Op.getSimpleValueType();
15168 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15169 assert(RegVT.isInteger() &&
15170 "We only custom lower integer vector sext loads.");
15172 // Nothing useful we can do without SSE2 shuffles.
15173 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15175 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15177 EVT MemVT = Ld->getMemoryVT();
15178 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15179 unsigned RegSz = RegVT.getSizeInBits();
15181 ISD::LoadExtType Ext = Ld->getExtensionType();
15183 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15184 && "Only anyext and sext are currently implemented.");
15185 assert(MemVT != RegVT && "Cannot extend to the same type");
15186 assert(MemVT.isVector() && "Must load a vector from memory");
15188 unsigned NumElems = RegVT.getVectorNumElements();
15189 unsigned MemSz = MemVT.getSizeInBits();
15190 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15192 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15193 // The only way in which we have a legal 256-bit vector result but not the
15194 // integer 256-bit operations needed to directly lower a sextload is if we
15195 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15196 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15197 // correctly legalized. We do this late to allow the canonical form of
15198 // sextload to persist throughout the rest of the DAG combiner -- it wants
15199 // to fold together any extensions it can, and so will fuse a sign_extend
15200 // of an sextload into a sextload targeting a wider value.
15202 if (MemSz == 128) {
15203 // Just switch this to a normal load.
15204 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15205 "it must be a legal 128-bit vector "
15207 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15208 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15209 Ld->isInvariant(), Ld->getAlignment());
15211 assert(MemSz < 128 &&
15212 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15213 // Do an sext load to a 128-bit vector type. We want to use the same
15214 // number of elements, but elements half as wide. This will end up being
15215 // recursively lowered by this routine, but will succeed as we definitely
15216 // have all the necessary features if we're using AVX1.
15218 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15219 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15221 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15222 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15223 Ld->isNonTemporal(), Ld->isInvariant(),
15224 Ld->getAlignment());
15227 // Replace chain users with the new chain.
15228 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15229 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15231 // Finally, do a normal sign-extend to the desired register.
15232 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15235 // All sizes must be a power of two.
15236 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15237 "Non-power-of-two elements are not custom lowered!");
15239 // Attempt to load the original value using scalar loads.
15240 // Find the largest scalar type that divides the total loaded size.
15241 MVT SclrLoadTy = MVT::i8;
15242 for (MVT Tp : MVT::integer_valuetypes()) {
15243 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15248 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15249 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15251 SclrLoadTy = MVT::f64;
15253 // Calculate the number of scalar loads that we need to perform
15254 // in order to load our vector from memory.
15255 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15257 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15258 "Can only lower sext loads with a single scalar load!");
15260 unsigned loadRegZize = RegSz;
15261 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15264 // Represent our vector as a sequence of elements which are the
15265 // largest scalar that we can load.
15266 EVT LoadUnitVecVT = EVT::getVectorVT(
15267 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15269 // Represent the data using the same element type that is stored in
15270 // memory. In practice, we ''widen'' MemVT.
15272 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15273 loadRegZize / MemVT.getScalarSizeInBits());
15275 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15276 "Invalid vector type");
15278 // We can't shuffle using an illegal type.
15279 assert(TLI.isTypeLegal(WideVecVT) &&
15280 "We only lower types that form legal widened vector types");
15282 SmallVector<SDValue, 8> Chains;
15283 SDValue Ptr = Ld->getBasePtr();
15284 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15285 TLI.getPointerTy(DAG.getDataLayout()));
15286 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15288 for (unsigned i = 0; i < NumLoads; ++i) {
15289 // Perform a single load.
15290 SDValue ScalarLoad =
15291 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15292 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15293 Ld->getAlignment());
15294 Chains.push_back(ScalarLoad.getValue(1));
15295 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15296 // another round of DAGCombining.
15298 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15300 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15301 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15303 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15306 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15308 // Bitcast the loaded value to a vector of the original element type, in
15309 // the size of the target vector type.
15310 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15311 unsigned SizeRatio = RegSz / MemSz;
15313 if (Ext == ISD::SEXTLOAD) {
15314 // If we have SSE4.1, we can directly emit a VSEXT node.
15315 if (Subtarget->hasSSE41()) {
15316 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15317 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15321 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15323 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15324 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15326 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15327 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15331 // Redistribute the loaded elements into the different locations.
15332 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15333 for (unsigned i = 0; i != NumElems; ++i)
15334 ShuffleVec[i * SizeRatio] = i;
15336 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15337 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15339 // Bitcast to the requested type.
15340 Shuff = DAG.getBitcast(RegVT, Shuff);
15341 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15345 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15346 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15347 // from the AND / OR.
15348 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15349 Opc = Op.getOpcode();
15350 if (Opc != ISD::OR && Opc != ISD::AND)
15352 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15353 Op.getOperand(0).hasOneUse() &&
15354 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15355 Op.getOperand(1).hasOneUse());
15358 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15359 // 1 and that the SETCC node has a single use.
15360 static bool isXor1OfSetCC(SDValue Op) {
15361 if (Op.getOpcode() != ISD::XOR)
15363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15364 if (N1C && N1C->getAPIntValue() == 1) {
15365 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15366 Op.getOperand(0).hasOneUse();
15371 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15372 bool addTest = true;
15373 SDValue Chain = Op.getOperand(0);
15374 SDValue Cond = Op.getOperand(1);
15375 SDValue Dest = Op.getOperand(2);
15378 bool Inverted = false;
15380 if (Cond.getOpcode() == ISD::SETCC) {
15381 // Check for setcc([su]{add,sub,mul}o == 0).
15382 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15383 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15384 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15385 Cond.getOperand(0).getResNo() == 1 &&
15386 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15387 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15388 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15389 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15390 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15391 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15393 Cond = Cond.getOperand(0);
15395 SDValue NewCond = LowerSETCC(Cond, DAG);
15396 if (NewCond.getNode())
15401 // FIXME: LowerXALUO doesn't handle these!!
15402 else if (Cond.getOpcode() == X86ISD::ADD ||
15403 Cond.getOpcode() == X86ISD::SUB ||
15404 Cond.getOpcode() == X86ISD::SMUL ||
15405 Cond.getOpcode() == X86ISD::UMUL)
15406 Cond = LowerXALUO(Cond, DAG);
15409 // Look pass (and (setcc_carry (cmp ...)), 1).
15410 if (Cond.getOpcode() == ISD::AND &&
15411 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15412 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15413 if (C && C->getAPIntValue() == 1)
15414 Cond = Cond.getOperand(0);
15417 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15418 // setting operand in place of the X86ISD::SETCC.
15419 unsigned CondOpcode = Cond.getOpcode();
15420 if (CondOpcode == X86ISD::SETCC ||
15421 CondOpcode == X86ISD::SETCC_CARRY) {
15422 CC = Cond.getOperand(0);
15424 SDValue Cmp = Cond.getOperand(1);
15425 unsigned Opc = Cmp.getOpcode();
15426 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15427 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15431 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15435 // These can only come from an arithmetic instruction with overflow,
15436 // e.g. SADDO, UADDO.
15437 Cond = Cond.getNode()->getOperand(1);
15443 CondOpcode = Cond.getOpcode();
15444 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15445 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15446 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15447 Cond.getOperand(0).getValueType() != MVT::i8)) {
15448 SDValue LHS = Cond.getOperand(0);
15449 SDValue RHS = Cond.getOperand(1);
15450 unsigned X86Opcode;
15453 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15454 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15456 switch (CondOpcode) {
15457 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15459 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15461 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15464 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15465 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15467 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15469 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15472 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15473 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15474 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15475 default: llvm_unreachable("unexpected overflowing operator");
15478 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15479 if (CondOpcode == ISD::UMULO)
15480 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15483 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15485 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15487 if (CondOpcode == ISD::UMULO)
15488 Cond = X86Op.getValue(2);
15490 Cond = X86Op.getValue(1);
15492 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15496 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15497 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15498 if (CondOpc == ISD::OR) {
15499 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15500 // two branches instead of an explicit OR instruction with a
15502 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15503 isX86LogicalCmp(Cmp)) {
15504 CC = Cond.getOperand(0).getOperand(0);
15505 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15506 Chain, Dest, CC, Cmp);
15507 CC = Cond.getOperand(1).getOperand(0);
15511 } else { // ISD::AND
15512 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15513 // two branches instead of an explicit AND instruction with a
15514 // separate test. However, we only do this if this block doesn't
15515 // have a fall-through edge, because this requires an explicit
15516 // jmp when the condition is false.
15517 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15518 isX86LogicalCmp(Cmp) &&
15519 Op.getNode()->hasOneUse()) {
15520 X86::CondCode CCode =
15521 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15522 CCode = X86::GetOppositeBranchCondition(CCode);
15523 CC = DAG.getConstant(CCode, dl, MVT::i8);
15524 SDNode *User = *Op.getNode()->use_begin();
15525 // Look for an unconditional branch following this conditional branch.
15526 // We need this because we need to reverse the successors in order
15527 // to implement FCMP_OEQ.
15528 if (User->getOpcode() == ISD::BR) {
15529 SDValue FalseBB = User->getOperand(1);
15531 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15532 assert(NewBR == User);
15536 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15537 Chain, Dest, CC, Cmp);
15538 X86::CondCode CCode =
15539 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15540 CCode = X86::GetOppositeBranchCondition(CCode);
15541 CC = DAG.getConstant(CCode, dl, MVT::i8);
15547 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15548 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15549 // It should be transformed during dag combiner except when the condition
15550 // is set by a arithmetics with overflow node.
15551 X86::CondCode CCode =
15552 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15553 CCode = X86::GetOppositeBranchCondition(CCode);
15554 CC = DAG.getConstant(CCode, dl, MVT::i8);
15555 Cond = Cond.getOperand(0).getOperand(1);
15557 } else if (Cond.getOpcode() == ISD::SETCC &&
15558 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15559 // For FCMP_OEQ, we can emit
15560 // two branches instead of an explicit AND instruction with a
15561 // separate test. However, we only do this if this block doesn't
15562 // have a fall-through edge, because this requires an explicit
15563 // jmp when the condition is false.
15564 if (Op.getNode()->hasOneUse()) {
15565 SDNode *User = *Op.getNode()->use_begin();
15566 // Look for an unconditional branch following this conditional branch.
15567 // We need this because we need to reverse the successors in order
15568 // to implement FCMP_OEQ.
15569 if (User->getOpcode() == ISD::BR) {
15570 SDValue FalseBB = User->getOperand(1);
15572 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15573 assert(NewBR == User);
15577 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15578 Cond.getOperand(0), Cond.getOperand(1));
15579 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15580 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15581 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15582 Chain, Dest, CC, Cmp);
15583 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15588 } else if (Cond.getOpcode() == ISD::SETCC &&
15589 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15590 // For FCMP_UNE, we can emit
15591 // two branches instead of an explicit AND instruction with a
15592 // separate test. However, we only do this if this block doesn't
15593 // have a fall-through edge, because this requires an explicit
15594 // jmp when the condition is false.
15595 if (Op.getNode()->hasOneUse()) {
15596 SDNode *User = *Op.getNode()->use_begin();
15597 // Look for an unconditional branch following this conditional branch.
15598 // We need this because we need to reverse the successors in order
15599 // to implement FCMP_UNE.
15600 if (User->getOpcode() == ISD::BR) {
15601 SDValue FalseBB = User->getOperand(1);
15603 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15604 assert(NewBR == User);
15607 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15608 Cond.getOperand(0), Cond.getOperand(1));
15609 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15610 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15611 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15612 Chain, Dest, CC, Cmp);
15613 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15623 // Look pass the truncate if the high bits are known zero.
15624 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15625 Cond = Cond.getOperand(0);
15627 // We know the result of AND is compared against zero. Try to match
15629 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15630 if (SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG)) {
15631 CC = NewSetCC.getOperand(0);
15632 Cond = NewSetCC.getOperand(1);
15639 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15640 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15641 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15643 Cond = ConvertCmpIfNecessary(Cond, DAG);
15644 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15645 Chain, Dest, CC, Cond);
15648 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15649 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15650 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15651 // that the guard pages used by the OS virtual memory manager are allocated in
15652 // correct sequence.
15654 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15655 SelectionDAG &DAG) const {
15656 MachineFunction &MF = DAG.getMachineFunction();
15657 bool SplitStack = MF.shouldSplitStack();
15658 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15663 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15664 SDNode* Node = Op.getNode();
15666 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15667 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15668 " not tell us which reg is the stack pointer!");
15669 EVT VT = Node->getValueType(0);
15670 SDValue Tmp1 = SDValue(Node, 0);
15671 SDValue Tmp2 = SDValue(Node, 1);
15672 SDValue Tmp3 = Node->getOperand(2);
15673 SDValue Chain = Tmp1.getOperand(0);
15675 // Chain the dynamic stack allocation so that it doesn't modify the stack
15676 // pointer when other instructions are using the stack.
15677 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15680 SDValue Size = Tmp2.getOperand(1);
15681 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15682 Chain = SP.getValue(1);
15683 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15684 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15685 unsigned StackAlign = TFI.getStackAlignment();
15686 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15687 if (Align > StackAlign)
15688 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15689 DAG.getConstant(-(uint64_t)Align, dl, VT));
15690 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15692 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15693 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15696 SDValue Ops[2] = { Tmp1, Tmp2 };
15697 return DAG.getMergeValues(Ops, dl);
15701 SDValue Chain = Op.getOperand(0);
15702 SDValue Size = Op.getOperand(1);
15703 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15704 EVT VT = Op.getNode()->getValueType(0);
15706 bool Is64Bit = Subtarget->is64Bit();
15707 MVT SPTy = getPointerTy(DAG.getDataLayout());
15710 MachineRegisterInfo &MRI = MF.getRegInfo();
15713 // The 64 bit implementation of segmented stacks needs to clobber both r10
15714 // r11. This makes it impossible to use it along with nested parameters.
15715 const Function *F = MF.getFunction();
15717 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15719 if (I->hasNestAttr())
15720 report_fatal_error("Cannot use segmented stacks with functions that "
15721 "have nested arguments.");
15724 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15725 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15726 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15727 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15728 DAG.getRegister(Vreg, SPTy));
15729 SDValue Ops1[2] = { Value, Chain };
15730 return DAG.getMergeValues(Ops1, dl);
15733 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15735 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15736 Flag = Chain.getValue(1);
15737 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15739 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15741 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15742 unsigned SPReg = RegInfo->getStackRegister();
15743 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15744 Chain = SP.getValue(1);
15747 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15748 DAG.getConstant(-(uint64_t)Align, dl, VT));
15749 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15752 SDValue Ops1[2] = { SP, Chain };
15753 return DAG.getMergeValues(Ops1, dl);
15757 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15758 MachineFunction &MF = DAG.getMachineFunction();
15759 auto PtrVT = getPointerTy(MF.getDataLayout());
15760 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15762 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15765 if (!Subtarget->is64Bit() ||
15766 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15767 // vastart just stores the address of the VarArgsFrameIndex slot into the
15768 // memory location argument.
15769 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15770 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15771 MachinePointerInfo(SV), false, false, 0);
15775 // gp_offset (0 - 6 * 8)
15776 // fp_offset (48 - 48 + 8 * 16)
15777 // overflow_arg_area (point to parameters coming in memory).
15779 SmallVector<SDValue, 8> MemOps;
15780 SDValue FIN = Op.getOperand(1);
15782 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15783 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15785 FIN, MachinePointerInfo(SV), false, false, 0);
15786 MemOps.push_back(Store);
15789 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15790 Store = DAG.getStore(Op.getOperand(0), DL,
15791 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15793 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15794 MemOps.push_back(Store);
15796 // Store ptr to overflow_arg_area
15797 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15798 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15799 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15800 MachinePointerInfo(SV, 8),
15802 MemOps.push_back(Store);
15804 // Store ptr to reg_save_area.
15805 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15806 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15807 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15808 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15809 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15810 MemOps.push_back(Store);
15811 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15814 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15815 assert(Subtarget->is64Bit() &&
15816 "LowerVAARG only handles 64-bit va_arg!");
15817 assert(Op.getNode()->getNumOperands() == 4);
15819 MachineFunction &MF = DAG.getMachineFunction();
15820 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15821 // The Win64 ABI uses char* instead of a structure.
15822 return DAG.expandVAArg(Op.getNode());
15824 SDValue Chain = Op.getOperand(0);
15825 SDValue SrcPtr = Op.getOperand(1);
15826 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15827 unsigned Align = Op.getConstantOperandVal(3);
15830 EVT ArgVT = Op.getNode()->getValueType(0);
15831 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15832 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15835 // Decide which area this value should be read from.
15836 // TODO: Implement the AMD64 ABI in its entirety. This simple
15837 // selection mechanism works only for the basic types.
15838 if (ArgVT == MVT::f80) {
15839 llvm_unreachable("va_arg for f80 not yet implemented");
15840 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15841 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15842 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15843 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15845 llvm_unreachable("Unhandled argument type in LowerVAARG");
15848 if (ArgMode == 2) {
15849 // Sanity Check: Make sure using fp_offset makes sense.
15850 assert(!Subtarget->useSoftFloat() &&
15851 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15852 Subtarget->hasSSE1());
15855 // Insert VAARG_64 node into the DAG
15856 // VAARG_64 returns two values: Variable Argument Address, Chain
15857 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15858 DAG.getConstant(ArgMode, dl, MVT::i8),
15859 DAG.getConstant(Align, dl, MVT::i32)};
15860 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15861 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15862 VTs, InstOps, MVT::i64,
15863 MachinePointerInfo(SV),
15865 /*Volatile=*/false,
15867 /*WriteMem=*/true);
15868 Chain = VAARG.getValue(1);
15870 // Load the next argument and return it
15871 return DAG.getLoad(ArgVT, dl,
15874 MachinePointerInfo(),
15875 false, false, false, 0);
15878 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15879 SelectionDAG &DAG) {
15880 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15881 // where a va_list is still an i8*.
15882 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15883 if (Subtarget->isCallingConvWin64(
15884 DAG.getMachineFunction().getFunction()->getCallingConv()))
15885 // Probably a Win64 va_copy.
15886 return DAG.expandVACopy(Op.getNode());
15888 SDValue Chain = Op.getOperand(0);
15889 SDValue DstPtr = Op.getOperand(1);
15890 SDValue SrcPtr = Op.getOperand(2);
15891 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15892 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15895 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15896 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15898 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15901 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15902 // amount is a constant. Takes immediate version of shift as input.
15903 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15904 SDValue SrcOp, uint64_t ShiftAmt,
15905 SelectionDAG &DAG) {
15906 MVT ElementType = VT.getVectorElementType();
15908 // Fold this packed shift into its first operand if ShiftAmt is 0.
15912 // Check for ShiftAmt >= element width
15913 if (ShiftAmt >= ElementType.getSizeInBits()) {
15914 if (Opc == X86ISD::VSRAI)
15915 ShiftAmt = ElementType.getSizeInBits() - 1;
15917 return DAG.getConstant(0, dl, VT);
15920 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15921 && "Unknown target vector shift-by-constant node");
15923 // Fold this packed vector shift into a build vector if SrcOp is a
15924 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15925 if (VT == SrcOp.getSimpleValueType() &&
15926 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15927 SmallVector<SDValue, 8> Elts;
15928 unsigned NumElts = SrcOp->getNumOperands();
15929 ConstantSDNode *ND;
15932 default: llvm_unreachable(nullptr);
15933 case X86ISD::VSHLI:
15934 for (unsigned i=0; i!=NumElts; ++i) {
15935 SDValue CurrentOp = SrcOp->getOperand(i);
15936 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15937 Elts.push_back(CurrentOp);
15940 ND = cast<ConstantSDNode>(CurrentOp);
15941 const APInt &C = ND->getAPIntValue();
15942 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15945 case X86ISD::VSRLI:
15946 for (unsigned i=0; i!=NumElts; ++i) {
15947 SDValue CurrentOp = SrcOp->getOperand(i);
15948 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15949 Elts.push_back(CurrentOp);
15952 ND = cast<ConstantSDNode>(CurrentOp);
15953 const APInt &C = ND->getAPIntValue();
15954 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15957 case X86ISD::VSRAI:
15958 for (unsigned i=0; i!=NumElts; ++i) {
15959 SDValue CurrentOp = SrcOp->getOperand(i);
15960 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15961 Elts.push_back(CurrentOp);
15964 ND = cast<ConstantSDNode>(CurrentOp);
15965 const APInt &C = ND->getAPIntValue();
15966 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15971 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15974 return DAG.getNode(Opc, dl, VT, SrcOp,
15975 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15978 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15979 // may or may not be a constant. Takes immediate version of shift as input.
15980 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15981 SDValue SrcOp, SDValue ShAmt,
15982 SelectionDAG &DAG) {
15983 MVT SVT = ShAmt.getSimpleValueType();
15984 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15986 // Catch shift-by-constant.
15987 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15988 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15989 CShAmt->getZExtValue(), DAG);
15991 // Change opcode to non-immediate version
15993 default: llvm_unreachable("Unknown target vector shift node");
15994 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15995 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15996 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15999 const X86Subtarget &Subtarget =
16000 static_cast<const X86Subtarget &>(DAG.getSubtarget());
16001 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
16002 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
16003 // Let the shuffle legalizer expand this shift amount node.
16004 SDValue Op0 = ShAmt.getOperand(0);
16005 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
16006 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
16008 // Need to build a vector containing shift amount.
16009 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
16010 SmallVector<SDValue, 4> ShOps;
16011 ShOps.push_back(ShAmt);
16012 if (SVT == MVT::i32) {
16013 ShOps.push_back(DAG.getConstant(0, dl, SVT));
16014 ShOps.push_back(DAG.getUNDEF(SVT));
16016 ShOps.push_back(DAG.getUNDEF(SVT));
16018 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
16019 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
16022 // The return type has to be a 128-bit type with the same element
16023 // type as the input type.
16024 MVT EltVT = VT.getVectorElementType();
16025 MVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
16027 ShAmt = DAG.getBitcast(ShVT, ShAmt);
16028 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
16031 /// \brief Return (and \p Op, \p Mask) for compare instructions or
16032 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
16033 /// necessary casting or extending for \p Mask when lowering masking intrinsics
16034 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
16035 SDValue PreservedSrc,
16036 const X86Subtarget *Subtarget,
16037 SelectionDAG &DAG) {
16038 MVT VT = Op.getSimpleValueType();
16039 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16041 unsigned OpcodeSelect = ISD::VSELECT;
16044 if (isAllOnes(Mask))
16047 if (MaskVT.bitsGT(Mask.getSimpleValueType())) {
16048 MVT newMaskVT = MVT::getIntegerVT(MaskVT.getSizeInBits());
16049 VMask = DAG.getBitcast(MaskVT,
16050 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
16052 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16053 Mask.getSimpleValueType().getSizeInBits());
16054 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16055 // are extracted by EXTRACT_SUBVECTOR.
16056 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16057 DAG.getBitcast(BitcastVT, Mask),
16058 DAG.getIntPtrConstant(0, dl));
16061 switch (Op.getOpcode()) {
16063 case X86ISD::PCMPEQM:
16064 case X86ISD::PCMPGTM:
16066 case X86ISD::CMPMU:
16067 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
16068 case X86ISD::VFPCLASS:
16069 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
16070 case X86ISD::VTRUNC:
16071 case X86ISD::VTRUNCS:
16072 case X86ISD::VTRUNCUS:
16073 // We can't use ISD::VSELECT here because it is not always "Legal"
16074 // for the destination type. For example vpmovqb require only AVX512
16075 // and vselect that can operate on byte element type require BWI
16076 OpcodeSelect = X86ISD::SELECT;
16079 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16080 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16081 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
16084 /// \brief Creates an SDNode for a predicated scalar operation.
16085 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
16086 /// The mask is coming as MVT::i8 and it should be truncated
16087 /// to MVT::i1 while lowering masking intrinsics.
16088 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16089 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16090 /// for a scalar instruction.
16091 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16092 SDValue PreservedSrc,
16093 const X86Subtarget *Subtarget,
16094 SelectionDAG &DAG) {
16095 if (isAllOnes(Mask))
16098 MVT VT = Op.getSimpleValueType();
16100 // The mask should be of type MVT::i1
16101 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16103 if (Op.getOpcode() == X86ISD::FSETCC)
16104 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16105 if (Op.getOpcode() == X86ISD::VFPCLASS)
16106 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16108 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16109 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16110 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16113 static int getSEHRegistrationNodeSize(const Function *Fn) {
16114 if (!Fn->hasPersonalityFn())
16115 report_fatal_error(
16116 "querying registration node size for function without personality");
16117 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16118 // WinEHStatePass for the full struct definition.
16119 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16120 case EHPersonality::MSVC_X86SEH: return 24;
16121 case EHPersonality::MSVC_CXX: return 16;
16124 report_fatal_error("can only recover FP for MSVC EH personality functions");
16127 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16128 /// function or when returning to a parent frame after catching an exception, we
16129 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16130 /// Here's the math:
16131 /// RegNodeBase = EntryEBP - RegNodeSize
16132 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16133 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16134 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16135 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16136 SDValue EntryEBP) {
16137 MachineFunction &MF = DAG.getMachineFunction();
16140 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16141 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16143 // It's possible that the parent function no longer has a personality function
16144 // if the exceptional code was optimized away, in which case we just return
16145 // the incoming EBP.
16146 if (!Fn->hasPersonalityFn())
16149 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16151 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16153 MCSymbol *OffsetSym =
16154 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16155 GlobalValue::getRealLinkageName(Fn->getName()));
16156 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16157 SDValue RegNodeFrameOffset =
16158 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16160 // RegNodeBase = EntryEBP - RegNodeSize
16161 // ParentFP = RegNodeBase - RegNodeFrameOffset
16162 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16163 DAG.getConstant(RegNodeSize, dl, PtrVT));
16164 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16167 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16168 SelectionDAG &DAG) {
16170 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16171 MVT VT = Op.getSimpleValueType();
16172 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16174 switch(IntrData->Type) {
16175 case INTR_TYPE_1OP:
16176 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16177 case INTR_TYPE_2OP:
16178 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16180 case INTR_TYPE_2OP_IMM8:
16181 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16182 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16183 case INTR_TYPE_3OP:
16184 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16185 Op.getOperand(2), Op.getOperand(3));
16186 case INTR_TYPE_4OP:
16187 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16188 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16189 case INTR_TYPE_1OP_MASK_RM: {
16190 SDValue Src = Op.getOperand(1);
16191 SDValue PassThru = Op.getOperand(2);
16192 SDValue Mask = Op.getOperand(3);
16193 SDValue RoundingMode;
16194 // We allways add rounding mode to the Node.
16195 // If the rounding mode is not specified, we add the
16196 // "current direction" mode.
16197 if (Op.getNumOperands() == 4)
16199 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16201 RoundingMode = Op.getOperand(4);
16202 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16203 if (IntrWithRoundingModeOpcode != 0)
16204 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16205 X86::STATIC_ROUNDING::CUR_DIRECTION)
16206 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16207 dl, Op.getValueType(), Src, RoundingMode),
16208 Mask, PassThru, Subtarget, DAG);
16209 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16211 Mask, PassThru, Subtarget, DAG);
16213 case INTR_TYPE_1OP_MASK: {
16214 SDValue Src = Op.getOperand(1);
16215 SDValue PassThru = Op.getOperand(2);
16216 SDValue Mask = Op.getOperand(3);
16217 // We add rounding mode to the Node when
16218 // - RM Opcode is specified and
16219 // - RM is not "current direction".
16220 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16221 if (IntrWithRoundingModeOpcode != 0) {
16222 SDValue Rnd = Op.getOperand(4);
16223 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16224 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16225 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16226 dl, Op.getValueType(),
16228 Mask, PassThru, Subtarget, DAG);
16231 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16232 Mask, PassThru, Subtarget, DAG);
16234 case INTR_TYPE_SCALAR_MASK: {
16235 SDValue Src1 = Op.getOperand(1);
16236 SDValue Src2 = Op.getOperand(2);
16237 SDValue passThru = Op.getOperand(3);
16238 SDValue Mask = Op.getOperand(4);
16239 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16240 Mask, passThru, Subtarget, DAG);
16242 case INTR_TYPE_SCALAR_MASK_RM: {
16243 SDValue Src1 = Op.getOperand(1);
16244 SDValue Src2 = Op.getOperand(2);
16245 SDValue Src0 = Op.getOperand(3);
16246 SDValue Mask = Op.getOperand(4);
16247 // There are 2 kinds of intrinsics in this group:
16248 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16249 // (2) With rounding mode and sae - 7 operands.
16250 if (Op.getNumOperands() == 6) {
16251 SDValue Sae = Op.getOperand(5);
16252 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16253 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16255 Mask, Src0, Subtarget, DAG);
16257 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16258 SDValue RoundingMode = Op.getOperand(5);
16259 SDValue Sae = Op.getOperand(6);
16260 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16261 RoundingMode, Sae),
16262 Mask, Src0, Subtarget, DAG);
16264 case INTR_TYPE_2OP_MASK:
16265 case INTR_TYPE_2OP_IMM8_MASK: {
16266 SDValue Src1 = Op.getOperand(1);
16267 SDValue Src2 = Op.getOperand(2);
16268 SDValue PassThru = Op.getOperand(3);
16269 SDValue Mask = Op.getOperand(4);
16271 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16272 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16274 // We specify 2 possible opcodes for intrinsics with rounding modes.
16275 // First, we check if the intrinsic may have non-default rounding mode,
16276 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16277 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16278 if (IntrWithRoundingModeOpcode != 0) {
16279 SDValue Rnd = Op.getOperand(5);
16280 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16281 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16282 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16283 dl, Op.getValueType(),
16285 Mask, PassThru, Subtarget, DAG);
16288 // TODO: Intrinsics should have fast-math-flags to propagate.
16289 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16290 Mask, PassThru, Subtarget, DAG);
16292 case INTR_TYPE_2OP_MASK_RM: {
16293 SDValue Src1 = Op.getOperand(1);
16294 SDValue Src2 = Op.getOperand(2);
16295 SDValue PassThru = Op.getOperand(3);
16296 SDValue Mask = Op.getOperand(4);
16297 // We specify 2 possible modes for intrinsics, with/without rounding
16299 // First, we check if the intrinsic have rounding mode (6 operands),
16300 // if not, we set rounding mode to "current".
16302 if (Op.getNumOperands() == 6)
16303 Rnd = Op.getOperand(5);
16305 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16306 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16308 Mask, PassThru, Subtarget, DAG);
16310 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16311 SDValue Src1 = Op.getOperand(1);
16312 SDValue Src2 = Op.getOperand(2);
16313 SDValue Src3 = Op.getOperand(3);
16314 SDValue PassThru = Op.getOperand(4);
16315 SDValue Mask = Op.getOperand(5);
16316 SDValue Sae = Op.getOperand(6);
16318 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16320 Mask, PassThru, Subtarget, DAG);
16322 case INTR_TYPE_3OP_MASK_RM: {
16323 SDValue Src1 = Op.getOperand(1);
16324 SDValue Src2 = Op.getOperand(2);
16325 SDValue Imm = Op.getOperand(3);
16326 SDValue PassThru = Op.getOperand(4);
16327 SDValue Mask = Op.getOperand(5);
16328 // We specify 2 possible modes for intrinsics, with/without rounding
16330 // First, we check if the intrinsic have rounding mode (7 operands),
16331 // if not, we set rounding mode to "current".
16333 if (Op.getNumOperands() == 7)
16334 Rnd = Op.getOperand(6);
16336 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16337 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16338 Src1, Src2, Imm, Rnd),
16339 Mask, PassThru, Subtarget, DAG);
16341 case INTR_TYPE_3OP_IMM8_MASK:
16342 case INTR_TYPE_3OP_MASK:
16343 case INSERT_SUBVEC: {
16344 SDValue Src1 = Op.getOperand(1);
16345 SDValue Src2 = Op.getOperand(2);
16346 SDValue Src3 = Op.getOperand(3);
16347 SDValue PassThru = Op.getOperand(4);
16348 SDValue Mask = Op.getOperand(5);
16350 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16351 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16352 else if (IntrData->Type == INSERT_SUBVEC) {
16353 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16354 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16355 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16356 Imm *= Src2.getSimpleValueType().getVectorNumElements();
16357 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16360 // We specify 2 possible opcodes for intrinsics with rounding modes.
16361 // First, we check if the intrinsic may have non-default rounding mode,
16362 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16363 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16364 if (IntrWithRoundingModeOpcode != 0) {
16365 SDValue Rnd = Op.getOperand(6);
16366 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16367 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16368 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16369 dl, Op.getValueType(),
16370 Src1, Src2, Src3, Rnd),
16371 Mask, PassThru, Subtarget, DAG);
16374 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16376 Mask, PassThru, Subtarget, DAG);
16378 case VPERM_3OP_MASKZ:
16379 case VPERM_3OP_MASK:
16382 case FMA_OP_MASK: {
16383 SDValue Src1 = Op.getOperand(1);
16384 SDValue Src2 = Op.getOperand(2);
16385 SDValue Src3 = Op.getOperand(3);
16386 SDValue Mask = Op.getOperand(4);
16387 MVT VT = Op.getSimpleValueType();
16388 SDValue PassThru = SDValue();
16390 // set PassThru element
16391 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16392 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16393 else if (IntrData->Type == FMA_OP_MASK3)
16398 // We specify 2 possible opcodes for intrinsics with rounding modes.
16399 // First, we check if the intrinsic may have non-default rounding mode,
16400 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16401 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16402 if (IntrWithRoundingModeOpcode != 0) {
16403 SDValue Rnd = Op.getOperand(5);
16404 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16405 X86::STATIC_ROUNDING::CUR_DIRECTION)
16406 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16407 dl, Op.getValueType(),
16408 Src1, Src2, Src3, Rnd),
16409 Mask, PassThru, Subtarget, DAG);
16411 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16412 dl, Op.getValueType(),
16414 Mask, PassThru, Subtarget, DAG);
16416 case TERLOG_OP_MASK:
16417 case TERLOG_OP_MASKZ: {
16418 SDValue Src1 = Op.getOperand(1);
16419 SDValue Src2 = Op.getOperand(2);
16420 SDValue Src3 = Op.getOperand(3);
16421 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16422 SDValue Mask = Op.getOperand(5);
16423 MVT VT = Op.getSimpleValueType();
16424 SDValue PassThru = Src1;
16425 // Set PassThru element.
16426 if (IntrData->Type == TERLOG_OP_MASKZ)
16427 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16429 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16430 Src1, Src2, Src3, Src4),
16431 Mask, PassThru, Subtarget, DAG);
16434 // FPclass intrinsics with mask
16435 SDValue Src1 = Op.getOperand(1);
16436 MVT VT = Src1.getSimpleValueType();
16437 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16438 SDValue Imm = Op.getOperand(2);
16439 SDValue Mask = Op.getOperand(3);
16440 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16441 Mask.getSimpleValueType().getSizeInBits());
16442 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16443 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16444 DAG.getTargetConstant(0, dl, MaskVT),
16446 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16447 DAG.getUNDEF(BitcastVT), FPclassMask,
16448 DAG.getIntPtrConstant(0, dl));
16449 return DAG.getBitcast(Op.getValueType(), Res);
16452 SDValue Src1 = Op.getOperand(1);
16453 SDValue Imm = Op.getOperand(2);
16454 SDValue Mask = Op.getOperand(3);
16455 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16456 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16457 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16458 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16461 case CMP_MASK_CC: {
16462 // Comparison intrinsics with masks.
16463 // Example of transformation:
16464 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16465 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16467 // (v8i1 (insert_subvector undef,
16468 // (v2i1 (and (PCMPEQM %a, %b),
16469 // (extract_subvector
16470 // (v8i1 (bitcast %mask)), 0))), 0))))
16471 MVT VT = Op.getOperand(1).getSimpleValueType();
16472 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16473 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16474 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16475 Mask.getSimpleValueType().getSizeInBits());
16477 if (IntrData->Type == CMP_MASK_CC) {
16478 SDValue CC = Op.getOperand(3);
16479 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16480 // We specify 2 possible opcodes for intrinsics with rounding modes.
16481 // First, we check if the intrinsic may have non-default rounding mode,
16482 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16483 if (IntrData->Opc1 != 0) {
16484 SDValue Rnd = Op.getOperand(5);
16485 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16486 X86::STATIC_ROUNDING::CUR_DIRECTION)
16487 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16488 Op.getOperand(2), CC, Rnd);
16490 //default rounding mode
16492 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16493 Op.getOperand(2), CC);
16496 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16497 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16500 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16501 DAG.getTargetConstant(0, dl,
16504 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16505 DAG.getUNDEF(BitcastVT), CmpMask,
16506 DAG.getIntPtrConstant(0, dl));
16507 return DAG.getBitcast(Op.getValueType(), Res);
16509 case CMP_MASK_SCALAR_CC: {
16510 SDValue Src1 = Op.getOperand(1);
16511 SDValue Src2 = Op.getOperand(2);
16512 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16513 SDValue Mask = Op.getOperand(4);
16516 if (IntrData->Opc1 != 0) {
16517 SDValue Rnd = Op.getOperand(5);
16518 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16519 X86::STATIC_ROUNDING::CUR_DIRECTION)
16520 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16522 //default rounding mode
16524 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16526 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16527 DAG.getTargetConstant(0, dl,
16531 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16532 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16533 DAG.getValueType(MVT::i1));
16535 case COMI: { // Comparison intrinsics
16536 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16537 SDValue LHS = Op.getOperand(1);
16538 SDValue RHS = Op.getOperand(2);
16539 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16540 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16541 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16542 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16543 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16544 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16547 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16548 Op.getOperand(1), Op.getOperand(2), DAG);
16550 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16551 Op.getSimpleValueType(),
16553 Op.getOperand(2), DAG),
16554 Op.getOperand(4), Op.getOperand(3), Subtarget,
16556 case COMPRESS_EXPAND_IN_REG: {
16557 SDValue Mask = Op.getOperand(3);
16558 SDValue DataToCompress = Op.getOperand(1);
16559 SDValue PassThru = Op.getOperand(2);
16560 if (isAllOnes(Mask)) // return data as is
16561 return Op.getOperand(1);
16563 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16565 Mask, PassThru, Subtarget, DAG);
16568 SDValue Mask = Op.getOperand(1);
16569 MVT MaskVT = MVT::getVectorVT(MVT::i1, Mask.getSimpleValueType().getSizeInBits());
16570 Mask = DAG.getBitcast(MaskVT, Mask);
16571 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Mask);
16574 SDValue Mask = Op.getOperand(3);
16575 MVT VT = Op.getSimpleValueType();
16576 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
16577 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16578 Mask.getSimpleValueType().getSizeInBits());
16580 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16581 DAG.getBitcast(BitcastVT, Mask),
16582 DAG.getIntPtrConstant(0, dl));
16583 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16592 default: return SDValue(); // Don't custom lower most intrinsics.
16594 case Intrinsic::x86_avx2_permd:
16595 case Intrinsic::x86_avx2_permps:
16596 // Operands intentionally swapped. Mask is last operand to intrinsic,
16597 // but second operand for node/instruction.
16598 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16599 Op.getOperand(2), Op.getOperand(1));
16601 // ptest and testp intrinsics. The intrinsic these come from are designed to
16602 // return an integer value, not just an instruction so lower it to the ptest
16603 // or testp pattern and a setcc for the result.
16604 case Intrinsic::x86_sse41_ptestz:
16605 case Intrinsic::x86_sse41_ptestc:
16606 case Intrinsic::x86_sse41_ptestnzc:
16607 case Intrinsic::x86_avx_ptestz_256:
16608 case Intrinsic::x86_avx_ptestc_256:
16609 case Intrinsic::x86_avx_ptestnzc_256:
16610 case Intrinsic::x86_avx_vtestz_ps:
16611 case Intrinsic::x86_avx_vtestc_ps:
16612 case Intrinsic::x86_avx_vtestnzc_ps:
16613 case Intrinsic::x86_avx_vtestz_pd:
16614 case Intrinsic::x86_avx_vtestc_pd:
16615 case Intrinsic::x86_avx_vtestnzc_pd:
16616 case Intrinsic::x86_avx_vtestz_ps_256:
16617 case Intrinsic::x86_avx_vtestc_ps_256:
16618 case Intrinsic::x86_avx_vtestnzc_ps_256:
16619 case Intrinsic::x86_avx_vtestz_pd_256:
16620 case Intrinsic::x86_avx_vtestc_pd_256:
16621 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16622 bool IsTestPacked = false;
16625 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16626 case Intrinsic::x86_avx_vtestz_ps:
16627 case Intrinsic::x86_avx_vtestz_pd:
16628 case Intrinsic::x86_avx_vtestz_ps_256:
16629 case Intrinsic::x86_avx_vtestz_pd_256:
16630 IsTestPacked = true; // Fallthrough
16631 case Intrinsic::x86_sse41_ptestz:
16632 case Intrinsic::x86_avx_ptestz_256:
16634 X86CC = X86::COND_E;
16636 case Intrinsic::x86_avx_vtestc_ps:
16637 case Intrinsic::x86_avx_vtestc_pd:
16638 case Intrinsic::x86_avx_vtestc_ps_256:
16639 case Intrinsic::x86_avx_vtestc_pd_256:
16640 IsTestPacked = true; // Fallthrough
16641 case Intrinsic::x86_sse41_ptestc:
16642 case Intrinsic::x86_avx_ptestc_256:
16644 X86CC = X86::COND_B;
16646 case Intrinsic::x86_avx_vtestnzc_ps:
16647 case Intrinsic::x86_avx_vtestnzc_pd:
16648 case Intrinsic::x86_avx_vtestnzc_ps_256:
16649 case Intrinsic::x86_avx_vtestnzc_pd_256:
16650 IsTestPacked = true; // Fallthrough
16651 case Intrinsic::x86_sse41_ptestnzc:
16652 case Intrinsic::x86_avx_ptestnzc_256:
16654 X86CC = X86::COND_A;
16658 SDValue LHS = Op.getOperand(1);
16659 SDValue RHS = Op.getOperand(2);
16660 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16661 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16662 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16663 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16664 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16666 case Intrinsic::x86_avx512_kortestz_w:
16667 case Intrinsic::x86_avx512_kortestc_w: {
16668 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16669 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16670 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16671 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16672 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16673 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16674 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16677 case Intrinsic::x86_sse42_pcmpistria128:
16678 case Intrinsic::x86_sse42_pcmpestria128:
16679 case Intrinsic::x86_sse42_pcmpistric128:
16680 case Intrinsic::x86_sse42_pcmpestric128:
16681 case Intrinsic::x86_sse42_pcmpistrio128:
16682 case Intrinsic::x86_sse42_pcmpestrio128:
16683 case Intrinsic::x86_sse42_pcmpistris128:
16684 case Intrinsic::x86_sse42_pcmpestris128:
16685 case Intrinsic::x86_sse42_pcmpistriz128:
16686 case Intrinsic::x86_sse42_pcmpestriz128: {
16690 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16691 case Intrinsic::x86_sse42_pcmpistria128:
16692 Opcode = X86ISD::PCMPISTRI;
16693 X86CC = X86::COND_A;
16695 case Intrinsic::x86_sse42_pcmpestria128:
16696 Opcode = X86ISD::PCMPESTRI;
16697 X86CC = X86::COND_A;
16699 case Intrinsic::x86_sse42_pcmpistric128:
16700 Opcode = X86ISD::PCMPISTRI;
16701 X86CC = X86::COND_B;
16703 case Intrinsic::x86_sse42_pcmpestric128:
16704 Opcode = X86ISD::PCMPESTRI;
16705 X86CC = X86::COND_B;
16707 case Intrinsic::x86_sse42_pcmpistrio128:
16708 Opcode = X86ISD::PCMPISTRI;
16709 X86CC = X86::COND_O;
16711 case Intrinsic::x86_sse42_pcmpestrio128:
16712 Opcode = X86ISD::PCMPESTRI;
16713 X86CC = X86::COND_O;
16715 case Intrinsic::x86_sse42_pcmpistris128:
16716 Opcode = X86ISD::PCMPISTRI;
16717 X86CC = X86::COND_S;
16719 case Intrinsic::x86_sse42_pcmpestris128:
16720 Opcode = X86ISD::PCMPESTRI;
16721 X86CC = X86::COND_S;
16723 case Intrinsic::x86_sse42_pcmpistriz128:
16724 Opcode = X86ISD::PCMPISTRI;
16725 X86CC = X86::COND_E;
16727 case Intrinsic::x86_sse42_pcmpestriz128:
16728 Opcode = X86ISD::PCMPESTRI;
16729 X86CC = X86::COND_E;
16732 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16733 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16734 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16735 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16736 DAG.getConstant(X86CC, dl, MVT::i8),
16737 SDValue(PCMP.getNode(), 1));
16738 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16741 case Intrinsic::x86_sse42_pcmpistri128:
16742 case Intrinsic::x86_sse42_pcmpestri128: {
16744 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16745 Opcode = X86ISD::PCMPISTRI;
16747 Opcode = X86ISD::PCMPESTRI;
16749 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16750 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16751 return DAG.getNode(Opcode, dl, VTs, NewOps);
16754 case Intrinsic::x86_seh_lsda: {
16755 // Compute the symbol for the LSDA. We know it'll get emitted later.
16756 MachineFunction &MF = DAG.getMachineFunction();
16757 SDValue Op1 = Op.getOperand(1);
16758 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16759 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16760 GlobalValue::getRealLinkageName(Fn->getName()));
16762 // Generate a simple absolute symbol reference. This intrinsic is only
16763 // supported on 32-bit Windows, which isn't PIC.
16764 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16765 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16768 case Intrinsic::x86_seh_recoverfp: {
16769 SDValue FnOp = Op.getOperand(1);
16770 SDValue IncomingFPOp = Op.getOperand(2);
16771 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16772 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16774 report_fatal_error(
16775 "llvm.x86.seh.recoverfp must take a function as the first argument");
16776 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16779 case Intrinsic::localaddress: {
16780 // Returns one of the stack, base, or frame pointer registers, depending on
16781 // which is used to reference local variables.
16782 MachineFunction &MF = DAG.getMachineFunction();
16783 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16785 if (RegInfo->hasBasePointer(MF))
16786 Reg = RegInfo->getBaseRegister();
16787 else // This function handles the SP or FP case.
16788 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16789 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16794 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16795 SDValue Src, SDValue Mask, SDValue Base,
16796 SDValue Index, SDValue ScaleOp, SDValue Chain,
16797 const X86Subtarget * Subtarget) {
16799 auto *C = cast<ConstantSDNode>(ScaleOp);
16800 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16801 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16802 Index.getSimpleValueType().getVectorNumElements());
16804 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16806 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16808 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16809 Mask.getSimpleValueType().getSizeInBits());
16811 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16812 // are extracted by EXTRACT_SUBVECTOR.
16813 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16814 DAG.getBitcast(BitcastVT, Mask),
16815 DAG.getIntPtrConstant(0, dl));
16817 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16818 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16819 SDValue Segment = DAG.getRegister(0, MVT::i32);
16820 if (Src.getOpcode() == ISD::UNDEF)
16821 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16822 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16823 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16824 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16825 return DAG.getMergeValues(RetOps, dl);
16828 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16829 SDValue Src, SDValue Mask, SDValue Base,
16830 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16832 auto *C = cast<ConstantSDNode>(ScaleOp);
16833 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16834 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16835 SDValue Segment = DAG.getRegister(0, MVT::i32);
16836 MVT MaskVT = MVT::getVectorVT(MVT::i1,
16837 Index.getSimpleValueType().getVectorNumElements());
16839 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16841 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16843 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
16844 Mask.getSimpleValueType().getSizeInBits());
16846 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16847 // are extracted by EXTRACT_SUBVECTOR.
16848 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16849 DAG.getBitcast(BitcastVT, Mask),
16850 DAG.getIntPtrConstant(0, dl));
16852 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16853 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16854 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16855 return SDValue(Res, 1);
16858 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16859 SDValue Mask, SDValue Base, SDValue Index,
16860 SDValue ScaleOp, SDValue Chain) {
16862 auto *C = cast<ConstantSDNode>(ScaleOp);
16863 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16864 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16865 SDValue Segment = DAG.getRegister(0, MVT::i32);
16867 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16869 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16871 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16873 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16874 //SDVTList VTs = DAG.getVTList(MVT::Other);
16875 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16876 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16877 return SDValue(Res, 0);
16880 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16881 // read performance monitor counters (x86_rdpmc).
16882 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16883 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16884 SmallVectorImpl<SDValue> &Results) {
16885 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16886 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16889 // The ECX register is used to select the index of the performance counter
16891 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16893 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16895 // Reads the content of a 64-bit performance counter and returns it in the
16896 // registers EDX:EAX.
16897 if (Subtarget->is64Bit()) {
16898 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16899 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16902 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16903 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16906 Chain = HI.getValue(1);
16908 if (Subtarget->is64Bit()) {
16909 // The EAX register is loaded with the low-order 32 bits. The EDX register
16910 // is loaded with the supported high-order bits of the counter.
16911 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16912 DAG.getConstant(32, DL, MVT::i8));
16913 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16914 Results.push_back(Chain);
16918 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16919 SDValue Ops[] = { LO, HI };
16920 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16921 Results.push_back(Pair);
16922 Results.push_back(Chain);
16925 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16926 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16927 // also used to custom lower READCYCLECOUNTER nodes.
16928 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16929 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16930 SmallVectorImpl<SDValue> &Results) {
16931 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16932 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16935 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16936 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16937 // and the EAX register is loaded with the low-order 32 bits.
16938 if (Subtarget->is64Bit()) {
16939 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16940 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16943 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16944 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16947 SDValue Chain = HI.getValue(1);
16949 if (Opcode == X86ISD::RDTSCP_DAG) {
16950 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16952 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16953 // the ECX register. Add 'ecx' explicitly to the chain.
16954 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16956 // Explicitly store the content of ECX at the location passed in input
16957 // to the 'rdtscp' intrinsic.
16958 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16959 MachinePointerInfo(), false, false, 0);
16962 if (Subtarget->is64Bit()) {
16963 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16964 // the EAX register is loaded with the low-order 32 bits.
16965 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16966 DAG.getConstant(32, DL, MVT::i8));
16967 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16968 Results.push_back(Chain);
16972 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16973 SDValue Ops[] = { LO, HI };
16974 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16975 Results.push_back(Pair);
16976 Results.push_back(Chain);
16979 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16980 SelectionDAG &DAG) {
16981 SmallVector<SDValue, 2> Results;
16983 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16985 return DAG.getMergeValues(Results, DL);
16988 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16989 SelectionDAG &DAG) {
16990 MachineFunction &MF = DAG.getMachineFunction();
16991 const Function *Fn = MF.getFunction();
16993 SDValue Chain = Op.getOperand(0);
16995 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16996 "using llvm.x86.seh.restoreframe requires a frame pointer");
16998 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16999 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
17001 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17002 unsigned FrameReg =
17003 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17004 unsigned SPReg = RegInfo->getStackRegister();
17005 unsigned SlotSize = RegInfo->getSlotSize();
17007 // Get incoming EBP.
17008 SDValue IncomingEBP =
17009 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
17011 // SP is saved in the first field of every registration node, so load
17012 // [EBP-RegNodeSize] into SP.
17013 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
17014 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
17015 DAG.getConstant(-RegNodeSize, dl, VT));
17017 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
17018 false, VT.getScalarSizeInBits() / 8);
17019 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
17021 if (!RegInfo->needsStackRealignment(MF)) {
17022 // Adjust EBP to point back to the original frame position.
17023 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
17024 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
17026 assert(RegInfo->hasBasePointer(MF) &&
17027 "functions with Win32 EH must use frame or base pointer register");
17029 // Reload the base pointer (ESI) with the adjusted incoming EBP.
17030 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
17031 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
17033 // Reload the spilled EBP value, now that the stack and base pointers are
17035 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
17036 X86FI->setHasSEHFramePtrSave(true);
17037 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
17038 X86FI->setSEHFramePtrSaveIndex(FI);
17039 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
17040 MachinePointerInfo(), false, false, false,
17041 VT.getScalarSizeInBits() / 8);
17042 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
17048 static SDValue MarkEHRegistrationNode(SDValue Op, SelectionDAG &DAG) {
17049 MachineFunction &MF = DAG.getMachineFunction();
17050 SDValue Chain = Op.getOperand(0);
17051 SDValue RegNode = Op.getOperand(2);
17052 WinEHFuncInfo *EHInfo = MF.getWinEHFuncInfo();
17054 report_fatal_error("EH registrations only live in functions using WinEH");
17056 // Cast the operand to an alloca, and remember the frame index.
17057 auto *FINode = dyn_cast<FrameIndexSDNode>(RegNode);
17059 report_fatal_error("llvm.x86.seh.ehregnode expects a static alloca");
17060 EHInfo->EHRegNodeFrameIndex = FINode->getIndex();
17062 // Return the chain operand without making any DAG nodes.
17066 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
17067 /// return truncate Store/MaskedStore Node
17068 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
17072 SDValue Mask = Op.getOperand(4);
17073 SDValue DataToTruncate = Op.getOperand(3);
17074 SDValue Addr = Op.getOperand(2);
17075 SDValue Chain = Op.getOperand(0);
17077 MVT VT = DataToTruncate.getSimpleValueType();
17078 MVT SVT = MVT::getVectorVT(ElementType, VT.getVectorNumElements());
17080 if (isAllOnes(Mask)) // return just a truncate store
17081 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
17082 MachinePointerInfo(), SVT, false, false,
17083 SVT.getScalarSizeInBits()/8);
17085 MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
17086 MVT BitcastVT = MVT::getVectorVT(MVT::i1,
17087 Mask.getSimpleValueType().getSizeInBits());
17088 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
17089 // are extracted by EXTRACT_SUBVECTOR.
17090 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
17091 DAG.getBitcast(BitcastVT, Mask),
17092 DAG.getIntPtrConstant(0, dl));
17094 MachineMemOperand *MMO = DAG.getMachineFunction().
17095 getMachineMemOperand(MachinePointerInfo(),
17096 MachineMemOperand::MOStore, SVT.getStoreSize(),
17097 SVT.getScalarSizeInBits()/8);
17099 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17100 VMask, SVT, MMO, true);
17103 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17104 SelectionDAG &DAG) {
17105 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17107 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17109 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17110 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17111 else if (IntNo == llvm::Intrinsic::x86_seh_ehregnode)
17112 return MarkEHRegistrationNode(Op, DAG);
17117 switch(IntrData->Type) {
17118 default: llvm_unreachable("Unknown Intrinsic Type");
17121 // Emit the node with the right value type.
17122 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17123 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17125 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17126 // Otherwise return the value from Rand, which is always 0, casted to i32.
17127 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17128 DAG.getConstant(1, dl, Op->getValueType(1)),
17129 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17130 SDValue(Result.getNode(), 1) };
17131 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17132 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17135 // Return { result, isValid, chain }.
17136 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17137 SDValue(Result.getNode(), 2));
17140 //gather(v1, mask, index, base, scale);
17141 SDValue Chain = Op.getOperand(0);
17142 SDValue Src = Op.getOperand(2);
17143 SDValue Base = Op.getOperand(3);
17144 SDValue Index = Op.getOperand(4);
17145 SDValue Mask = Op.getOperand(5);
17146 SDValue Scale = Op.getOperand(6);
17147 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17151 //scatter(base, mask, index, v1, scale);
17152 SDValue Chain = Op.getOperand(0);
17153 SDValue Base = Op.getOperand(2);
17154 SDValue Mask = Op.getOperand(3);
17155 SDValue Index = Op.getOperand(4);
17156 SDValue Src = Op.getOperand(5);
17157 SDValue Scale = Op.getOperand(6);
17158 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17162 SDValue Hint = Op.getOperand(6);
17163 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17164 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17165 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17166 SDValue Chain = Op.getOperand(0);
17167 SDValue Mask = Op.getOperand(2);
17168 SDValue Index = Op.getOperand(3);
17169 SDValue Base = Op.getOperand(4);
17170 SDValue Scale = Op.getOperand(5);
17171 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17173 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17175 SmallVector<SDValue, 2> Results;
17176 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17178 return DAG.getMergeValues(Results, dl);
17180 // Read Performance Monitoring Counters.
17182 SmallVector<SDValue, 2> Results;
17183 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17184 return DAG.getMergeValues(Results, dl);
17186 // XTEST intrinsics.
17188 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17189 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17190 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17191 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17193 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17194 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17195 Ret, SDValue(InTrans.getNode(), 1));
17199 SmallVector<SDValue, 2> Results;
17200 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17201 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17202 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17203 DAG.getConstant(-1, dl, MVT::i8));
17204 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17205 Op.getOperand(4), GenCF.getValue(1));
17206 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17207 Op.getOperand(5), MachinePointerInfo(),
17209 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17210 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17212 Results.push_back(SetCC);
17213 Results.push_back(Store);
17214 return DAG.getMergeValues(Results, dl);
17216 case COMPRESS_TO_MEM: {
17218 SDValue Mask = Op.getOperand(4);
17219 SDValue DataToCompress = Op.getOperand(3);
17220 SDValue Addr = Op.getOperand(2);
17221 SDValue Chain = Op.getOperand(0);
17223 MVT VT = DataToCompress.getSimpleValueType();
17224 if (isAllOnes(Mask)) // return just a store
17225 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17226 MachinePointerInfo(), false, false,
17227 VT.getScalarSizeInBits()/8);
17229 SDValue Compressed =
17230 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17231 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17232 return DAG.getStore(Chain, dl, Compressed, Addr,
17233 MachinePointerInfo(), false, false,
17234 VT.getScalarSizeInBits()/8);
17236 case TRUNCATE_TO_MEM_VI8:
17237 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17238 case TRUNCATE_TO_MEM_VI16:
17239 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17240 case TRUNCATE_TO_MEM_VI32:
17241 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17242 case EXPAND_FROM_MEM: {
17244 SDValue Mask = Op.getOperand(4);
17245 SDValue PassThru = Op.getOperand(3);
17246 SDValue Addr = Op.getOperand(2);
17247 SDValue Chain = Op.getOperand(0);
17248 MVT VT = Op.getSimpleValueType();
17250 if (isAllOnes(Mask)) // return just a load
17251 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17252 false, VT.getScalarSizeInBits()/8);
17254 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17255 false, false, false,
17256 VT.getScalarSizeInBits()/8);
17258 SDValue Results[] = {
17259 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17260 Mask, PassThru, Subtarget, DAG), Chain};
17261 return DAG.getMergeValues(Results, dl);
17266 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17267 SelectionDAG &DAG) const {
17268 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17269 MFI->setReturnAddressIsTaken(true);
17271 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17274 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17276 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17279 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17280 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17281 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17282 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17283 DAG.getNode(ISD::ADD, dl, PtrVT,
17284 FrameAddr, Offset),
17285 MachinePointerInfo(), false, false, false, 0);
17288 // Just load the return address.
17289 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17290 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17291 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17294 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17295 MachineFunction &MF = DAG.getMachineFunction();
17296 MachineFrameInfo *MFI = MF.getFrameInfo();
17297 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17298 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17299 EVT VT = Op.getValueType();
17301 MFI->setFrameAddressIsTaken(true);
17303 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17304 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17305 // is not possible to crawl up the stack without looking at the unwind codes
17307 int FrameAddrIndex = FuncInfo->getFAIndex();
17308 if (!FrameAddrIndex) {
17309 // Set up a frame object for the return address.
17310 unsigned SlotSize = RegInfo->getSlotSize();
17311 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17312 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17313 FuncInfo->setFAIndex(FrameAddrIndex);
17315 return DAG.getFrameIndex(FrameAddrIndex, VT);
17318 unsigned FrameReg =
17319 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17320 SDLoc dl(Op); // FIXME probably not meaningful
17321 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17322 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17323 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17324 "Invalid Frame Register!");
17325 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17327 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17328 MachinePointerInfo(),
17329 false, false, false, 0);
17333 // FIXME? Maybe this could be a TableGen attribute on some registers and
17334 // this table could be generated automatically from RegInfo.
17335 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17336 SelectionDAG &DAG) const {
17337 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17338 const MachineFunction &MF = DAG.getMachineFunction();
17340 unsigned Reg = StringSwitch<unsigned>(RegName)
17341 .Case("esp", X86::ESP)
17342 .Case("rsp", X86::RSP)
17343 .Case("ebp", X86::EBP)
17344 .Case("rbp", X86::RBP)
17347 if (Reg == X86::EBP || Reg == X86::RBP) {
17348 if (!TFI.hasFP(MF))
17349 report_fatal_error("register " + StringRef(RegName) +
17350 " is allocatable: function has no frame pointer");
17353 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17354 unsigned FrameReg =
17355 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17356 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17357 "Invalid Frame Register!");
17365 report_fatal_error("Invalid register name global variable");
17368 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17369 SelectionDAG &DAG) const {
17370 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17371 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17374 unsigned X86TargetLowering::getExceptionPointerRegister(
17375 const Constant *PersonalityFn) const {
17376 if (classifyEHPersonality(PersonalityFn) == EHPersonality::CoreCLR)
17377 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17379 return Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX;
17382 unsigned X86TargetLowering::getExceptionSelectorRegister(
17383 const Constant *PersonalityFn) const {
17384 // Funclet personalities don't use selectors (the runtime does the selection).
17385 assert(!isFuncletEHPersonality(classifyEHPersonality(PersonalityFn)));
17386 return Subtarget->isTarget64BitLP64() ? X86::RDX : X86::EDX;
17389 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17390 SDValue Chain = Op.getOperand(0);
17391 SDValue Offset = Op.getOperand(1);
17392 SDValue Handler = Op.getOperand(2);
17395 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17396 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17397 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17398 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17399 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17400 "Invalid Frame Register!");
17401 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17402 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17404 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17405 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17407 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17408 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17410 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17412 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17413 DAG.getRegister(StoreAddrReg, PtrVT));
17416 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17417 SelectionDAG &DAG) const {
17419 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17420 DAG.getVTList(MVT::i32, MVT::Other),
17421 Op.getOperand(0), Op.getOperand(1));
17424 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17425 SelectionDAG &DAG) const {
17427 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17428 Op.getOperand(0), Op.getOperand(1));
17431 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17432 return Op.getOperand(0);
17435 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17436 SelectionDAG &DAG) const {
17437 SDValue Root = Op.getOperand(0);
17438 SDValue Trmp = Op.getOperand(1); // trampoline
17439 SDValue FPtr = Op.getOperand(2); // nested function
17440 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17443 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17444 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17446 if (Subtarget->is64Bit()) {
17447 SDValue OutChains[6];
17449 // Large code-model.
17450 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17451 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17453 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17454 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17456 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17458 // Load the pointer to the nested function into R11.
17459 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17460 SDValue Addr = Trmp;
17461 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17462 Addr, MachinePointerInfo(TrmpAddr),
17465 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17466 DAG.getConstant(2, dl, MVT::i64));
17467 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17468 MachinePointerInfo(TrmpAddr, 2),
17471 // Load the 'nest' parameter value into R10.
17472 // R10 is specified in X86CallingConv.td
17473 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17474 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17475 DAG.getConstant(10, dl, MVT::i64));
17476 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17477 Addr, MachinePointerInfo(TrmpAddr, 10),
17480 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17481 DAG.getConstant(12, dl, MVT::i64));
17482 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17483 MachinePointerInfo(TrmpAddr, 12),
17486 // Jump to the nested function.
17487 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17488 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17489 DAG.getConstant(20, dl, MVT::i64));
17490 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17491 Addr, MachinePointerInfo(TrmpAddr, 20),
17494 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17495 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17496 DAG.getConstant(22, dl, MVT::i64));
17497 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17498 Addr, MachinePointerInfo(TrmpAddr, 22),
17501 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17503 const Function *Func =
17504 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17505 CallingConv::ID CC = Func->getCallingConv();
17510 llvm_unreachable("Unsupported calling convention");
17511 case CallingConv::C:
17512 case CallingConv::X86_StdCall: {
17513 // Pass 'nest' parameter in ECX.
17514 // Must be kept in sync with X86CallingConv.td
17515 NestReg = X86::ECX;
17517 // Check that ECX wasn't needed by an 'inreg' parameter.
17518 FunctionType *FTy = Func->getFunctionType();
17519 const AttributeSet &Attrs = Func->getAttributes();
17521 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17522 unsigned InRegCount = 0;
17525 for (FunctionType::param_iterator I = FTy->param_begin(),
17526 E = FTy->param_end(); I != E; ++I, ++Idx)
17527 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17528 auto &DL = DAG.getDataLayout();
17529 // FIXME: should only count parameters that are lowered to integers.
17530 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17533 if (InRegCount > 2) {
17534 report_fatal_error("Nest register in use - reduce number of inreg"
17540 case CallingConv::X86_FastCall:
17541 case CallingConv::X86_ThisCall:
17542 case CallingConv::Fast:
17543 // Pass 'nest' parameter in EAX.
17544 // Must be kept in sync with X86CallingConv.td
17545 NestReg = X86::EAX;
17549 SDValue OutChains[4];
17550 SDValue Addr, Disp;
17552 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17553 DAG.getConstant(10, dl, MVT::i32));
17554 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17556 // This is storing the opcode for MOV32ri.
17557 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17558 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17559 OutChains[0] = DAG.getStore(Root, dl,
17560 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17561 Trmp, MachinePointerInfo(TrmpAddr),
17564 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17565 DAG.getConstant(1, dl, MVT::i32));
17566 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17567 MachinePointerInfo(TrmpAddr, 1),
17570 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17571 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17572 DAG.getConstant(5, dl, MVT::i32));
17573 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17574 Addr, MachinePointerInfo(TrmpAddr, 5),
17577 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17578 DAG.getConstant(6, dl, MVT::i32));
17579 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17580 MachinePointerInfo(TrmpAddr, 6),
17583 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17587 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17588 SelectionDAG &DAG) const {
17590 The rounding mode is in bits 11:10 of FPSR, and has the following
17592 00 Round to nearest
17597 FLT_ROUNDS, on the other hand, expects the following:
17604 To perform the conversion, we do:
17605 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17608 MachineFunction &MF = DAG.getMachineFunction();
17609 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17610 unsigned StackAlignment = TFI.getStackAlignment();
17611 MVT VT = Op.getSimpleValueType();
17614 // Save FP Control Word to stack slot
17615 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17616 SDValue StackSlot =
17617 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17619 MachineMemOperand *MMO =
17620 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17621 MachineMemOperand::MOStore, 2, 2);
17623 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17624 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17625 DAG.getVTList(MVT::Other),
17626 Ops, MVT::i16, MMO);
17628 // Load FP Control Word from stack slot
17629 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17630 MachinePointerInfo(), false, false, false, 0);
17632 // Transform as necessary
17634 DAG.getNode(ISD::SRL, DL, MVT::i16,
17635 DAG.getNode(ISD::AND, DL, MVT::i16,
17636 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17637 DAG.getConstant(11, DL, MVT::i8));
17639 DAG.getNode(ISD::SRL, DL, MVT::i16,
17640 DAG.getNode(ISD::AND, DL, MVT::i16,
17641 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17642 DAG.getConstant(9, DL, MVT::i8));
17645 DAG.getNode(ISD::AND, DL, MVT::i16,
17646 DAG.getNode(ISD::ADD, DL, MVT::i16,
17647 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17648 DAG.getConstant(1, DL, MVT::i16)),
17649 DAG.getConstant(3, DL, MVT::i16));
17651 return DAG.getNode((VT.getSizeInBits() < 16 ?
17652 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17655 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17657 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17658 // to 512-bit vector.
17659 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17660 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17661 // split the vector, perform operation on it's Lo a Hi part and
17662 // concatenate the results.
17663 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17665 MVT VT = Op.getSimpleValueType();
17666 MVT EltVT = VT.getVectorElementType();
17667 unsigned NumElems = VT.getVectorNumElements();
17669 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17670 // Extend to 512 bit vector.
17671 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17672 "Unsupported value type for operation");
17674 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17675 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17676 DAG.getUNDEF(NewVT),
17678 DAG.getIntPtrConstant(0, dl));
17679 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17681 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17682 DAG.getIntPtrConstant(0, dl));
17685 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17686 "Unsupported element type");
17688 if (16 < NumElems) {
17689 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17691 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17692 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17694 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17695 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17697 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17700 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17702 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17703 "Unsupported value type for operation");
17705 // Use native supported vector instruction vplzcntd.
17706 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17707 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17708 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17709 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17711 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17714 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17715 SelectionDAG &DAG) {
17716 MVT VT = Op.getSimpleValueType();
17718 unsigned NumBits = VT.getSizeInBits();
17721 if (VT.isVector() && Subtarget->hasAVX512())
17722 return LowerVectorCTLZ_AVX512(Op, DAG);
17724 Op = Op.getOperand(0);
17725 if (VT == MVT::i8) {
17726 // Zero extend to i32 since there is not an i8 bsr.
17728 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17731 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17732 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17733 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17735 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17738 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17739 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17742 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17744 // Finally xor with NumBits-1.
17745 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17746 DAG.getConstant(NumBits - 1, dl, OpVT));
17749 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17753 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17754 SelectionDAG &DAG) {
17755 MVT VT = Op.getSimpleValueType();
17757 unsigned NumBits = VT.getSizeInBits();
17760 if (VT.isVector() && Subtarget->hasAVX512())
17761 return LowerVectorCTLZ_AVX512(Op, DAG);
17763 Op = Op.getOperand(0);
17764 if (VT == MVT::i8) {
17765 // Zero extend to i32 since there is not an i8 bsr.
17767 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17770 // Issue a bsr (scan bits in reverse).
17771 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17772 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17774 // And xor with NumBits-1.
17775 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17776 DAG.getConstant(NumBits - 1, dl, OpVT));
17779 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17783 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17784 MVT VT = Op.getSimpleValueType();
17785 unsigned NumBits = VT.getScalarSizeInBits();
17788 if (VT.isVector()) {
17789 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17791 SDValue N0 = Op.getOperand(0);
17792 SDValue Zero = DAG.getConstant(0, dl, VT);
17794 // lsb(x) = (x & -x)
17795 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17796 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17798 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17799 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17800 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17801 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17802 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17803 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17806 // cttz(x) = ctpop(lsb - 1)
17807 SDValue One = DAG.getConstant(1, dl, VT);
17808 return DAG.getNode(ISD::CTPOP, dl, VT,
17809 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17812 assert(Op.getOpcode() == ISD::CTTZ &&
17813 "Only scalar CTTZ requires custom lowering");
17815 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17816 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17817 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17819 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17822 DAG.getConstant(NumBits, dl, VT),
17823 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17826 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17829 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17830 // ones, and then concatenate the result back.
17831 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17832 MVT VT = Op.getSimpleValueType();
17834 assert(VT.is256BitVector() && VT.isInteger() &&
17835 "Unsupported value type for operation");
17837 unsigned NumElems = VT.getVectorNumElements();
17840 // Extract the LHS vectors
17841 SDValue LHS = Op.getOperand(0);
17842 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17843 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17845 // Extract the RHS vectors
17846 SDValue RHS = Op.getOperand(1);
17847 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17848 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17850 MVT EltVT = VT.getVectorElementType();
17851 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17853 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17854 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17855 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17858 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17859 if (Op.getValueType() == MVT::i1)
17860 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17861 Op.getOperand(0), Op.getOperand(1));
17862 assert(Op.getSimpleValueType().is256BitVector() &&
17863 Op.getSimpleValueType().isInteger() &&
17864 "Only handle AVX 256-bit vector integer operation");
17865 return Lower256IntArith(Op, DAG);
17868 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17869 if (Op.getValueType() == MVT::i1)
17870 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17871 Op.getOperand(0), Op.getOperand(1));
17872 assert(Op.getSimpleValueType().is256BitVector() &&
17873 Op.getSimpleValueType().isInteger() &&
17874 "Only handle AVX 256-bit vector integer operation");
17875 return Lower256IntArith(Op, DAG);
17878 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17879 assert(Op.getSimpleValueType().is256BitVector() &&
17880 Op.getSimpleValueType().isInteger() &&
17881 "Only handle AVX 256-bit vector integer operation");
17882 return Lower256IntArith(Op, DAG);
17885 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17886 SelectionDAG &DAG) {
17888 MVT VT = Op.getSimpleValueType();
17891 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17893 // Decompose 256-bit ops into smaller 128-bit ops.
17894 if (VT.is256BitVector() && !Subtarget->hasInt256())
17895 return Lower256IntArith(Op, DAG);
17897 SDValue A = Op.getOperand(0);
17898 SDValue B = Op.getOperand(1);
17900 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17901 // pairs, multiply and truncate.
17902 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17903 if (Subtarget->hasInt256()) {
17904 if (VT == MVT::v32i8) {
17905 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17906 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17907 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17908 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17909 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17910 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17911 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17912 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17913 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17914 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17917 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17918 return DAG.getNode(
17919 ISD::TRUNCATE, dl, VT,
17920 DAG.getNode(ISD::MUL, dl, ExVT,
17921 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17922 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17925 assert(VT == MVT::v16i8 &&
17926 "Pre-AVX2 support only supports v16i8 multiplication");
17927 MVT ExVT = MVT::v8i16;
17929 // Extract the lo parts and sign extend to i16
17931 if (Subtarget->hasSSE41()) {
17932 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17933 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17935 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17936 -1, 4, -1, 5, -1, 6, -1, 7};
17937 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17938 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17939 ALo = DAG.getBitcast(ExVT, ALo);
17940 BLo = DAG.getBitcast(ExVT, BLo);
17941 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17942 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17945 // Extract the hi parts and sign extend to i16
17947 if (Subtarget->hasSSE41()) {
17948 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17949 -1, -1, -1, -1, -1, -1, -1, -1};
17950 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17951 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17952 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17953 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17955 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17956 -1, 12, -1, 13, -1, 14, -1, 15};
17957 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17958 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17959 AHi = DAG.getBitcast(ExVT, AHi);
17960 BHi = DAG.getBitcast(ExVT, BHi);
17961 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17962 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17965 // Multiply, mask the lower 8bits of the lo/hi results and pack
17966 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17967 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17968 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17969 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17970 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17973 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17974 if (VT == MVT::v4i32) {
17975 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17976 "Should not custom lower when pmuldq is available!");
17978 // Extract the odd parts.
17979 static const int UnpackMask[] = { 1, -1, 3, -1 };
17980 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17981 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17983 // Multiply the even parts.
17984 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17985 // Now multiply odd parts.
17986 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17988 Evens = DAG.getBitcast(VT, Evens);
17989 Odds = DAG.getBitcast(VT, Odds);
17991 // Merge the two vectors back together with a shuffle. This expands into 2
17993 static const int ShufMask[] = { 0, 4, 2, 6 };
17994 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17997 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17998 "Only know how to lower V2I64/V4I64/V8I64 multiply");
18000 // Ahi = psrlqi(a, 32);
18001 // Bhi = psrlqi(b, 32);
18003 // AloBlo = pmuludq(a, b);
18004 // AloBhi = pmuludq(a, Bhi);
18005 // AhiBlo = pmuludq(Ahi, b);
18007 // AloBhi = psllqi(AloBhi, 32);
18008 // AhiBlo = psllqi(AhiBlo, 32);
18009 // return AloBlo + AloBhi + AhiBlo;
18011 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
18012 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
18014 SDValue AhiBlo = Ahi;
18015 SDValue AloBhi = Bhi;
18016 // Bit cast to 32-bit vectors for MULUDQ
18017 MVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
18018 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
18019 A = DAG.getBitcast(MulVT, A);
18020 B = DAG.getBitcast(MulVT, B);
18021 Ahi = DAG.getBitcast(MulVT, Ahi);
18022 Bhi = DAG.getBitcast(MulVT, Bhi);
18024 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
18025 // After shifting right const values the result may be all-zero.
18026 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
18027 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
18028 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
18030 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
18031 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
18032 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
18035 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
18036 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
18039 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
18040 assert(Subtarget->isTargetWin64() && "Unexpected target");
18041 EVT VT = Op.getValueType();
18042 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
18043 "Unexpected return type for lowering");
18047 switch (Op->getOpcode()) {
18048 default: llvm_unreachable("Unexpected request for libcall!");
18049 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
18050 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
18051 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
18052 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
18053 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
18054 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
18058 SDValue InChain = DAG.getEntryNode();
18060 TargetLowering::ArgListTy Args;
18061 TargetLowering::ArgListEntry Entry;
18062 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
18063 EVT ArgVT = Op->getOperand(i).getValueType();
18064 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
18065 "Unexpected argument type for lowering");
18066 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
18067 Entry.Node = StackPtr;
18068 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
18070 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18071 Entry.Ty = PointerType::get(ArgTy,0);
18072 Entry.isSExt = false;
18073 Entry.isZExt = false;
18074 Args.push_back(Entry);
18077 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
18078 getPointerTy(DAG.getDataLayout()));
18080 TargetLowering::CallLoweringInfo CLI(DAG);
18081 CLI.setDebugLoc(dl).setChain(InChain)
18082 .setCallee(getLibcallCallingConv(LC),
18083 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
18084 Callee, std::move(Args), 0)
18085 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
18087 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
18088 return DAG.getBitcast(VT, CallInfo.first);
18091 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
18092 SelectionDAG &DAG) {
18093 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
18094 MVT VT = Op0.getSimpleValueType();
18097 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
18098 (VT == MVT::v8i32 && Subtarget->hasInt256()));
18100 // PMULxD operations multiply each even value (starting at 0) of LHS with
18101 // the related value of RHS and produce a widen result.
18102 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18103 // => <2 x i64> <ae|cg>
18105 // In other word, to have all the results, we need to perform two PMULxD:
18106 // 1. one with the even values.
18107 // 2. one with the odd values.
18108 // To achieve #2, with need to place the odd values at an even position.
18110 // Place the odd value at an even position (basically, shift all values 1
18111 // step to the left):
18112 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18113 // <a|b|c|d> => <b|undef|d|undef>
18114 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18115 // <e|f|g|h> => <f|undef|h|undef>
18116 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18118 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18120 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18121 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18123 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18124 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18125 // => <2 x i64> <ae|cg>
18126 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18127 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18128 // => <2 x i64> <bf|dh>
18129 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18131 // Shuffle it back into the right order.
18132 SDValue Highs, Lows;
18133 if (VT == MVT::v8i32) {
18134 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18135 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18136 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18137 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18139 const int HighMask[] = {1, 5, 3, 7};
18140 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18141 const int LowMask[] = {0, 4, 2, 6};
18142 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18145 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18146 // unsigned multiply.
18147 if (IsSigned && !Subtarget->hasSSE41()) {
18148 SDValue ShAmt = DAG.getConstant(
18150 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18151 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18152 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18153 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18154 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18156 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18157 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18160 // The first result of MUL_LOHI is actually the low value, followed by the
18162 SDValue Ops[] = {Lows, Highs};
18163 return DAG.getMergeValues(Ops, dl);
18166 // Return true if the required (according to Opcode) shift-imm form is natively
18167 // supported by the Subtarget
18168 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18170 if (VT.getScalarSizeInBits() < 16)
18173 if (VT.is512BitVector() &&
18174 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18177 bool LShift = VT.is128BitVector() ||
18178 (VT.is256BitVector() && Subtarget->hasInt256());
18180 bool AShift = LShift && (Subtarget->hasVLX() ||
18181 (VT != MVT::v2i64 && VT != MVT::v4i64));
18182 return (Opcode == ISD::SRA) ? AShift : LShift;
18185 // The shift amount is a variable, but it is the same for all vector lanes.
18186 // These instructions are defined together with shift-immediate.
18188 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18190 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18193 // Return true if the required (according to Opcode) variable-shift form is
18194 // natively supported by the Subtarget
18195 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18198 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18201 // vXi16 supported only on AVX-512, BWI
18202 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18205 if (VT.is512BitVector() || Subtarget->hasVLX())
18208 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18209 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18210 return (Opcode == ISD::SRA) ? AShift : LShift;
18213 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18214 const X86Subtarget *Subtarget) {
18215 MVT VT = Op.getSimpleValueType();
18217 SDValue R = Op.getOperand(0);
18218 SDValue Amt = Op.getOperand(1);
18220 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18221 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18223 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18224 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18225 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18226 SDValue Ex = DAG.getBitcast(ExVT, R);
18228 if (ShiftAmt >= 32) {
18229 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18231 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18232 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18233 ShiftAmt - 32, DAG);
18234 if (VT == MVT::v2i64)
18235 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18236 if (VT == MVT::v4i64)
18237 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18238 {9, 1, 11, 3, 13, 5, 15, 7});
18240 // SRA upper i32, SHL whole i64 and select lower i32.
18241 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18244 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18245 Lower = DAG.getBitcast(ExVT, Lower);
18246 if (VT == MVT::v2i64)
18247 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18248 if (VT == MVT::v4i64)
18249 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18250 {8, 1, 10, 3, 12, 5, 14, 7});
18252 return DAG.getBitcast(VT, Ex);
18255 // Optimize shl/srl/sra with constant shift amount.
18256 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18257 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18258 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18260 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18261 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18263 // i64 SRA needs to be performed as partial shifts.
18264 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18265 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18266 return ArithmeticShiftRight64(ShiftAmt);
18268 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18269 unsigned NumElts = VT.getVectorNumElements();
18270 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18272 // Simple i8 add case
18273 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18274 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18276 // ashr(R, 7) === cmp_slt(R, 0)
18277 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18278 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18279 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18282 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18283 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18286 if (Op.getOpcode() == ISD::SHL) {
18287 // Make a large shift.
18288 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18290 SHL = DAG.getBitcast(VT, SHL);
18291 // Zero out the rightmost bits.
18292 SmallVector<SDValue, 32> V(
18293 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18294 return DAG.getNode(ISD::AND, dl, VT, SHL,
18295 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18297 if (Op.getOpcode() == ISD::SRL) {
18298 // Make a large shift.
18299 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18301 SRL = DAG.getBitcast(VT, SRL);
18302 // Zero out the leftmost bits.
18303 SmallVector<SDValue, 32> V(
18304 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18305 return DAG.getNode(ISD::AND, dl, VT, SRL,
18306 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18308 if (Op.getOpcode() == ISD::SRA) {
18309 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18310 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18311 SmallVector<SDValue, 32> V(NumElts,
18312 DAG.getConstant(128 >> ShiftAmt, dl,
18314 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18315 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18316 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18319 llvm_unreachable("Unknown shift opcode.");
18324 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18325 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18326 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18328 // Peek through any splat that was introduced for i64 shift vectorization.
18329 int SplatIndex = -1;
18330 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18331 if (SVN->isSplat()) {
18332 SplatIndex = SVN->getSplatIndex();
18333 Amt = Amt.getOperand(0);
18334 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18335 "Splat shuffle referencing second operand");
18338 if (Amt.getOpcode() != ISD::BITCAST ||
18339 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18342 Amt = Amt.getOperand(0);
18343 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18344 VT.getVectorNumElements();
18345 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18346 uint64_t ShiftAmt = 0;
18347 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18348 for (unsigned i = 0; i != Ratio; ++i) {
18349 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18353 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18356 // Check remaining shift amounts (if not a splat).
18357 if (SplatIndex < 0) {
18358 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18359 uint64_t ShAmt = 0;
18360 for (unsigned j = 0; j != Ratio; ++j) {
18361 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18365 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18367 if (ShAmt != ShiftAmt)
18372 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18373 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18375 if (Op.getOpcode() == ISD::SRA)
18376 return ArithmeticShiftRight64(ShiftAmt);
18382 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18383 const X86Subtarget* Subtarget) {
18384 MVT VT = Op.getSimpleValueType();
18386 SDValue R = Op.getOperand(0);
18387 SDValue Amt = Op.getOperand(1);
18389 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18390 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18392 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18393 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18395 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18397 MVT EltVT = VT.getVectorElementType();
18399 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18400 // Check if this build_vector node is doing a splat.
18401 // If so, then set BaseShAmt equal to the splat value.
18402 BaseShAmt = BV->getSplatValue();
18403 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18404 BaseShAmt = SDValue();
18406 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18407 Amt = Amt.getOperand(0);
18409 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18410 if (SVN && SVN->isSplat()) {
18411 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18412 SDValue InVec = Amt.getOperand(0);
18413 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18414 assert((SplatIdx < InVec.getSimpleValueType().getVectorNumElements()) &&
18415 "Unexpected shuffle index found!");
18416 BaseShAmt = InVec.getOperand(SplatIdx);
18417 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18418 if (ConstantSDNode *C =
18419 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18420 if (C->getZExtValue() == SplatIdx)
18421 BaseShAmt = InVec.getOperand(1);
18426 // Avoid introducing an extract element from a shuffle.
18427 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18428 DAG.getIntPtrConstant(SplatIdx, dl));
18432 if (BaseShAmt.getNode()) {
18433 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18434 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18435 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18436 else if (EltVT.bitsLT(MVT::i32))
18437 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18439 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18443 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18444 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18445 Amt.getOpcode() == ISD::BITCAST &&
18446 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18447 Amt = Amt.getOperand(0);
18448 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18449 VT.getVectorNumElements();
18450 std::vector<SDValue> Vals(Ratio);
18451 for (unsigned i = 0; i != Ratio; ++i)
18452 Vals[i] = Amt.getOperand(i);
18453 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18454 for (unsigned j = 0; j != Ratio; ++j)
18455 if (Vals[j] != Amt.getOperand(i + j))
18459 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18460 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18465 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18466 SelectionDAG &DAG) {
18467 MVT VT = Op.getSimpleValueType();
18469 SDValue R = Op.getOperand(0);
18470 SDValue Amt = Op.getOperand(1);
18472 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18473 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18475 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18478 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18481 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18484 // XOP has 128-bit variable logical/arithmetic shifts.
18485 // +ve/-ve Amt = shift left/right.
18486 if (Subtarget->hasXOP() &&
18487 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18488 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18489 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18490 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18491 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18493 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18494 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18495 if (Op.getOpcode() == ISD::SRA)
18496 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18499 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18500 // shifts per-lane and then shuffle the partial results back together.
18501 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18502 // Splat the shift amounts so the scalar shifts above will catch it.
18503 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18504 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18505 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18506 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18507 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18510 // i64 vector arithmetic shift can be emulated with the transform:
18511 // M = lshr(SIGN_BIT, Amt)
18512 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18513 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18514 Op.getOpcode() == ISD::SRA) {
18515 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18516 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18517 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18518 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18519 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18523 // If possible, lower this packed shift into a vector multiply instead of
18524 // expanding it into a sequence of scalar shifts.
18525 // Do this only if the vector shift count is a constant build_vector.
18526 if (Op.getOpcode() == ISD::SHL &&
18527 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18528 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18529 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18530 SmallVector<SDValue, 8> Elts;
18531 MVT SVT = VT.getVectorElementType();
18532 unsigned SVTBits = SVT.getSizeInBits();
18533 APInt One(SVTBits, 1);
18534 unsigned NumElems = VT.getVectorNumElements();
18536 for (unsigned i=0; i !=NumElems; ++i) {
18537 SDValue Op = Amt->getOperand(i);
18538 if (Op->getOpcode() == ISD::UNDEF) {
18539 Elts.push_back(Op);
18543 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18544 APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
18545 uint64_t ShAmt = C.getZExtValue();
18546 if (ShAmt >= SVTBits) {
18547 Elts.push_back(DAG.getUNDEF(SVT));
18550 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18552 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18553 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18556 // Lower SHL with variable shift amount.
18557 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18558 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18560 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18561 DAG.getConstant(0x3f800000U, dl, VT));
18562 Op = DAG.getBitcast(MVT::v4f32, Op);
18563 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18564 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18567 // If possible, lower this shift as a sequence of two shifts by
18568 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18570 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18572 // Could be rewritten as:
18573 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18575 // The advantage is that the two shifts from the example would be
18576 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18577 // the vector shift into four scalar shifts plus four pairs of vector
18579 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18580 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18581 unsigned TargetOpcode = X86ISD::MOVSS;
18582 bool CanBeSimplified;
18583 // The splat value for the first packed shift (the 'X' from the example).
18584 SDValue Amt1 = Amt->getOperand(0);
18585 // The splat value for the second packed shift (the 'Y' from the example).
18586 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18587 Amt->getOperand(2);
18589 // See if it is possible to replace this node with a sequence of
18590 // two shifts followed by a MOVSS/MOVSD
18591 if (VT == MVT::v4i32) {
18592 // Check if it is legal to use a MOVSS.
18593 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18594 Amt2 == Amt->getOperand(3);
18595 if (!CanBeSimplified) {
18596 // Otherwise, check if we can still simplify this node using a MOVSD.
18597 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18598 Amt->getOperand(2) == Amt->getOperand(3);
18599 TargetOpcode = X86ISD::MOVSD;
18600 Amt2 = Amt->getOperand(2);
18603 // Do similar checks for the case where the machine value type
18605 CanBeSimplified = Amt1 == Amt->getOperand(1);
18606 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18607 CanBeSimplified = Amt2 == Amt->getOperand(i);
18609 if (!CanBeSimplified) {
18610 TargetOpcode = X86ISD::MOVSD;
18611 CanBeSimplified = true;
18612 Amt2 = Amt->getOperand(4);
18613 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18614 CanBeSimplified = Amt1 == Amt->getOperand(i);
18615 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18616 CanBeSimplified = Amt2 == Amt->getOperand(j);
18620 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18621 isa<ConstantSDNode>(Amt2)) {
18622 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18623 MVT CastVT = MVT::v4i32;
18625 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18626 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18628 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18629 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18630 if (TargetOpcode == X86ISD::MOVSD)
18631 CastVT = MVT::v2i64;
18632 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18633 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18634 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18636 return DAG.getBitcast(VT, Result);
18640 // v4i32 Non Uniform Shifts.
18641 // If the shift amount is constant we can shift each lane using the SSE2
18642 // immediate shifts, else we need to zero-extend each lane to the lower i64
18643 // and shift using the SSE2 variable shifts.
18644 // The separate results can then be blended together.
18645 if (VT == MVT::v4i32) {
18646 unsigned Opc = Op.getOpcode();
18647 SDValue Amt0, Amt1, Amt2, Amt3;
18648 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18649 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18650 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18651 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18652 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18654 // ISD::SHL is handled above but we include it here for completeness.
18657 llvm_unreachable("Unknown target vector shift node");
18659 Opc = X86ISD::VSHL;
18662 Opc = X86ISD::VSRL;
18665 Opc = X86ISD::VSRA;
18668 // The SSE2 shifts use the lower i64 as the same shift amount for
18669 // all lanes and the upper i64 is ignored. These shuffle masks
18670 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18671 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18672 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18673 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18674 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18675 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18678 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18679 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18680 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18681 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18682 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18683 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18684 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18687 if (VT == MVT::v16i8 ||
18688 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18689 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18690 unsigned ShiftOpcode = Op->getOpcode();
18692 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18693 // On SSE41 targets we make use of the fact that VSELECT lowers
18694 // to PBLENDVB which selects bytes based just on the sign bit.
18695 if (Subtarget->hasSSE41()) {
18696 V0 = DAG.getBitcast(VT, V0);
18697 V1 = DAG.getBitcast(VT, V1);
18698 Sel = DAG.getBitcast(VT, Sel);
18699 return DAG.getBitcast(SelVT,
18700 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18702 // On pre-SSE41 targets we test for the sign bit by comparing to
18703 // zero - a negative value will set all bits of the lanes to true
18704 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18705 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18706 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18707 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18710 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18711 // We can safely do this using i16 shifts as we're only interested in
18712 // the 3 lower bits of each byte.
18713 Amt = DAG.getBitcast(ExtVT, Amt);
18714 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18715 Amt = DAG.getBitcast(VT, Amt);
18717 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18718 // r = VSELECT(r, shift(r, 4), a);
18720 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18721 R = SignBitSelect(VT, Amt, M, R);
18724 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18726 // r = VSELECT(r, shift(r, 2), a);
18727 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18728 R = SignBitSelect(VT, Amt, M, R);
18731 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18733 // return VSELECT(r, shift(r, 1), a);
18734 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18735 R = SignBitSelect(VT, Amt, M, R);
18739 if (Op->getOpcode() == ISD::SRA) {
18740 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18741 // so we can correctly sign extend. We don't care what happens to the
18743 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18744 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18745 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18746 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18747 ALo = DAG.getBitcast(ExtVT, ALo);
18748 AHi = DAG.getBitcast(ExtVT, AHi);
18749 RLo = DAG.getBitcast(ExtVT, RLo);
18750 RHi = DAG.getBitcast(ExtVT, RHi);
18752 // r = VSELECT(r, shift(r, 4), a);
18753 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18754 DAG.getConstant(4, dl, ExtVT));
18755 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18756 DAG.getConstant(4, dl, ExtVT));
18757 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18758 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18761 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18762 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18764 // r = VSELECT(r, shift(r, 2), a);
18765 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18766 DAG.getConstant(2, dl, ExtVT));
18767 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18768 DAG.getConstant(2, dl, ExtVT));
18769 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18770 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18773 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18774 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18776 // r = VSELECT(r, shift(r, 1), a);
18777 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18778 DAG.getConstant(1, dl, ExtVT));
18779 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18780 DAG.getConstant(1, dl, ExtVT));
18781 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18782 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18784 // Logical shift the result back to the lower byte, leaving a zero upper
18786 // meaning that we can safely pack with PACKUSWB.
18788 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18790 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18791 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18795 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18796 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18797 // solution better.
18798 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18799 MVT ExtVT = MVT::v8i32;
18801 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18802 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18803 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18804 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18805 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18808 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18809 MVT ExtVT = MVT::v8i32;
18810 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18811 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18812 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18813 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18814 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18815 ALo = DAG.getBitcast(ExtVT, ALo);
18816 AHi = DAG.getBitcast(ExtVT, AHi);
18817 RLo = DAG.getBitcast(ExtVT, RLo);
18818 RHi = DAG.getBitcast(ExtVT, RHi);
18819 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18820 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18821 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18822 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18823 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18826 if (VT == MVT::v8i16) {
18827 unsigned ShiftOpcode = Op->getOpcode();
18829 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18830 // On SSE41 targets we make use of the fact that VSELECT lowers
18831 // to PBLENDVB which selects bytes based just on the sign bit.
18832 if (Subtarget->hasSSE41()) {
18833 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18834 V0 = DAG.getBitcast(ExtVT, V0);
18835 V1 = DAG.getBitcast(ExtVT, V1);
18836 Sel = DAG.getBitcast(ExtVT, Sel);
18837 return DAG.getBitcast(
18838 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18840 // On pre-SSE41 targets we splat the sign bit - a negative value will
18841 // set all bits of the lanes to true and VSELECT uses that in
18842 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18844 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18845 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18848 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18849 if (Subtarget->hasSSE41()) {
18850 // On SSE41 targets we need to replicate the shift mask in both
18851 // bytes for PBLENDVB.
18854 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18855 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18857 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18860 // r = VSELECT(r, shift(r, 8), a);
18861 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18862 R = SignBitSelect(Amt, M, R);
18865 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18867 // r = VSELECT(r, shift(r, 4), a);
18868 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18869 R = SignBitSelect(Amt, M, R);
18872 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18874 // r = VSELECT(r, shift(r, 2), a);
18875 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18876 R = SignBitSelect(Amt, M, R);
18879 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18881 // return VSELECT(r, shift(r, 1), a);
18882 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18883 R = SignBitSelect(Amt, M, R);
18887 // Decompose 256-bit shifts into smaller 128-bit shifts.
18888 if (VT.is256BitVector()) {
18889 unsigned NumElems = VT.getVectorNumElements();
18890 MVT EltVT = VT.getVectorElementType();
18891 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18893 // Extract the two vectors
18894 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18895 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18897 // Recreate the shift amount vectors
18898 SDValue Amt1, Amt2;
18899 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18900 // Constant shift amount
18901 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18902 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18903 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18905 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18906 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18908 // Variable shift amount
18909 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18910 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18913 // Issue new vector shifts for the smaller types
18914 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18915 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18917 // Concatenate the result back
18918 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18924 static SDValue LowerRotate(SDValue Op, const X86Subtarget *Subtarget,
18925 SelectionDAG &DAG) {
18926 MVT VT = Op.getSimpleValueType();
18928 SDValue R = Op.getOperand(0);
18929 SDValue Amt = Op.getOperand(1);
18931 assert(VT.isVector() && "Custom lowering only for vector rotates!");
18932 assert(Subtarget->hasXOP() && "XOP support required for vector rotates!");
18933 assert((Op.getOpcode() == ISD::ROTL) && "Only ROTL supported");
18935 // XOP has 128-bit vector variable + immediate rotates.
18936 // +ve/-ve Amt = rotate left/right.
18938 // Split 256-bit integers.
18939 if (VT.is256BitVector())
18940 return Lower256IntArith(Op, DAG);
18942 assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
18944 // Attempt to rotate by immediate.
18945 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18946 if (auto *RotateConst = BVAmt->getConstantSplatNode()) {
18947 uint64_t RotateAmt = RotateConst->getAPIntValue().getZExtValue();
18948 assert(RotateAmt < VT.getScalarSizeInBits() && "Rotation out of range");
18949 return DAG.getNode(X86ISD::VPROTI, DL, VT, R,
18950 DAG.getConstant(RotateAmt, DL, MVT::i8));
18954 // Use general rotate by variable (per-element).
18955 return DAG.getNode(X86ISD::VPROT, DL, VT, R, Amt);
18958 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18959 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18960 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18961 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18962 // has only one use.
18963 SDNode *N = Op.getNode();
18964 SDValue LHS = N->getOperand(0);
18965 SDValue RHS = N->getOperand(1);
18966 unsigned BaseOp = 0;
18969 switch (Op.getOpcode()) {
18970 default: llvm_unreachable("Unknown ovf instruction!");
18972 // A subtract of one will be selected as a INC. Note that INC doesn't
18973 // set CF, so we can't do this for UADDO.
18974 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18976 BaseOp = X86ISD::INC;
18977 Cond = X86::COND_O;
18980 BaseOp = X86ISD::ADD;
18981 Cond = X86::COND_O;
18984 BaseOp = X86ISD::ADD;
18985 Cond = X86::COND_B;
18988 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18989 // set CF, so we can't do this for USUBO.
18990 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18992 BaseOp = X86ISD::DEC;
18993 Cond = X86::COND_O;
18996 BaseOp = X86ISD::SUB;
18997 Cond = X86::COND_O;
19000 BaseOp = X86ISD::SUB;
19001 Cond = X86::COND_B;
19004 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
19005 Cond = X86::COND_O;
19007 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
19008 if (N->getValueType(0) == MVT::i8) {
19009 BaseOp = X86ISD::UMUL8;
19010 Cond = X86::COND_O;
19013 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
19015 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
19018 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
19019 DAG.getConstant(X86::COND_O, DL, MVT::i32),
19020 SDValue(Sum.getNode(), 2));
19022 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19026 // Also sets EFLAGS.
19027 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
19028 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
19031 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
19032 DAG.getConstant(Cond, DL, MVT::i32),
19033 SDValue(Sum.getNode(), 1));
19035 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
19038 /// Returns true if the operand type is exactly twice the native width, and
19039 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
19040 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
19041 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
19042 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
19043 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
19046 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
19047 else if (OpWidth == 128)
19048 return Subtarget->hasCmpxchg16b();
19053 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
19054 return needsCmpXchgNb(SI->getValueOperand()->getType());
19057 // Note: this turns large loads into lock cmpxchg8b/16b.
19058 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
19059 TargetLowering::AtomicExpansionKind
19060 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
19061 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
19062 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
19063 : AtomicExpansionKind::None;
19066 TargetLowering::AtomicExpansionKind
19067 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
19068 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19069 Type *MemType = AI->getType();
19071 // If the operand is too big, we must see if cmpxchg8/16b is available
19072 // and default to library calls otherwise.
19073 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
19074 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
19075 : AtomicExpansionKind::None;
19078 AtomicRMWInst::BinOp Op = AI->getOperation();
19081 llvm_unreachable("Unknown atomic operation");
19082 case AtomicRMWInst::Xchg:
19083 case AtomicRMWInst::Add:
19084 case AtomicRMWInst::Sub:
19085 // It's better to use xadd, xsub or xchg for these in all cases.
19086 return AtomicExpansionKind::None;
19087 case AtomicRMWInst::Or:
19088 case AtomicRMWInst::And:
19089 case AtomicRMWInst::Xor:
19090 // If the atomicrmw's result isn't actually used, we can just add a "lock"
19091 // prefix to a normal instruction for these operations.
19092 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
19093 : AtomicExpansionKind::None;
19094 case AtomicRMWInst::Nand:
19095 case AtomicRMWInst::Max:
19096 case AtomicRMWInst::Min:
19097 case AtomicRMWInst::UMax:
19098 case AtomicRMWInst::UMin:
19099 // These always require a non-trivial set of data operations on x86. We must
19100 // use a cmpxchg loop.
19101 return AtomicExpansionKind::CmpXChg;
19105 static bool hasMFENCE(const X86Subtarget& Subtarget) {
19106 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
19107 // no-sse2). There isn't any reason to disable it if the target processor
19109 return Subtarget.hasSSE2() || Subtarget.is64Bit();
19113 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
19114 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
19115 Type *MemType = AI->getType();
19116 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
19117 // there is no benefit in turning such RMWs into loads, and it is actually
19118 // harmful as it introduces a mfence.
19119 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
19122 auto Builder = IRBuilder<>(AI);
19123 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
19124 auto SynchScope = AI->getSynchScope();
19125 // We must restrict the ordering to avoid generating loads with Release or
19126 // ReleaseAcquire orderings.
19127 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
19128 auto Ptr = AI->getPointerOperand();
19130 // Before the load we need a fence. Here is an example lifted from
19131 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
19134 // x.store(1, relaxed);
19135 // r1 = y.fetch_add(0, release);
19137 // y.fetch_add(42, acquire);
19138 // r2 = x.load(relaxed);
19139 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
19140 // lowered to just a load without a fence. A mfence flushes the store buffer,
19141 // making the optimization clearly correct.
19142 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
19143 // otherwise, we might be able to be more aggressive on relaxed idempotent
19144 // rmw. In practice, they do not look useful, so we don't try to be
19145 // especially clever.
19146 if (SynchScope == SingleThread)
19147 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19148 // the IR level, so we must wrap it in an intrinsic.
19151 if (!hasMFENCE(*Subtarget))
19152 // FIXME: it might make sense to use a locked operation here but on a
19153 // different cache-line to prevent cache-line bouncing. In practice it
19154 // is probably a small win, and x86 processors without mfence are rare
19155 // enough that we do not bother.
19159 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19160 Builder.CreateCall(MFence, {});
19162 // Finally we can emit the atomic load.
19163 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19164 AI->getType()->getPrimitiveSizeInBits());
19165 Loaded->setAtomic(Order, SynchScope);
19166 AI->replaceAllUsesWith(Loaded);
19167 AI->eraseFromParent();
19171 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19172 SelectionDAG &DAG) {
19174 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19175 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19176 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19177 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19179 // The only fence that needs an instruction is a sequentially-consistent
19180 // cross-thread fence.
19181 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19182 if (hasMFENCE(*Subtarget))
19183 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19185 SDValue Chain = Op.getOperand(0);
19186 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19188 DAG.getRegister(X86::ESP, MVT::i32), // Base
19189 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19190 DAG.getRegister(0, MVT::i32), // Index
19191 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19192 DAG.getRegister(0, MVT::i32), // Segment.
19196 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19197 return SDValue(Res, 0);
19200 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19201 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19204 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19205 SelectionDAG &DAG) {
19206 MVT T = Op.getSimpleValueType();
19210 switch(T.SimpleTy) {
19211 default: llvm_unreachable("Invalid value type!");
19212 case MVT::i8: Reg = X86::AL; size = 1; break;
19213 case MVT::i16: Reg = X86::AX; size = 2; break;
19214 case MVT::i32: Reg = X86::EAX; size = 4; break;
19216 assert(Subtarget->is64Bit() && "Node not type legal!");
19217 Reg = X86::RAX; size = 8;
19220 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19221 Op.getOperand(2), SDValue());
19222 SDValue Ops[] = { cpIn.getValue(0),
19225 DAG.getTargetConstant(size, DL, MVT::i8),
19226 cpIn.getValue(1) };
19227 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19228 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19229 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19233 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19234 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19235 MVT::i32, cpOut.getValue(2));
19236 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19237 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19240 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19241 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19242 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19246 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19247 SelectionDAG &DAG) {
19248 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19249 MVT DstVT = Op.getSimpleValueType();
19251 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19252 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19253 if (DstVT != MVT::f64)
19254 // This conversion needs to be expanded.
19257 SDValue InVec = Op->getOperand(0);
19259 unsigned NumElts = SrcVT.getVectorNumElements();
19260 MVT SVT = SrcVT.getVectorElementType();
19262 // Widen the vector in input in the case of MVT::v2i32.
19263 // Example: from MVT::v2i32 to MVT::v4i32.
19264 SmallVector<SDValue, 16> Elts;
19265 for (unsigned i = 0, e = NumElts; i != e; ++i)
19266 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19267 DAG.getIntPtrConstant(i, dl)));
19269 // Explicitly mark the extra elements as Undef.
19270 Elts.append(NumElts, DAG.getUNDEF(SVT));
19272 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19273 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19274 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19275 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19276 DAG.getIntPtrConstant(0, dl));
19279 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19280 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19281 assert((DstVT == MVT::i64 ||
19282 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19283 "Unexpected custom BITCAST");
19284 // i64 <=> MMX conversions are Legal.
19285 if (SrcVT==MVT::i64 && DstVT.isVector())
19287 if (DstVT==MVT::i64 && SrcVT.isVector())
19289 // MMX <=> MMX conversions are Legal.
19290 if (SrcVT.isVector() && DstVT.isVector())
19292 // All other conversions need to be expanded.
19296 /// Compute the horizontal sum of bytes in V for the elements of VT.
19298 /// Requires V to be a byte vector and VT to be an integer vector type with
19299 /// wider elements than V's type. The width of the elements of VT determines
19300 /// how many bytes of V are summed horizontally to produce each element of the
19302 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19303 const X86Subtarget *Subtarget,
19304 SelectionDAG &DAG) {
19306 MVT ByteVecVT = V.getSimpleValueType();
19307 MVT EltVT = VT.getVectorElementType();
19308 int NumElts = VT.getVectorNumElements();
19309 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19310 "Expected value to have byte element type.");
19311 assert(EltVT != MVT::i8 &&
19312 "Horizontal byte sum only makes sense for wider elements!");
19313 unsigned VecSize = VT.getSizeInBits();
19314 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19316 // PSADBW instruction horizontally add all bytes and leave the result in i64
19317 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19318 if (EltVT == MVT::i64) {
19319 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19320 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19321 V = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT, V, Zeros);
19322 return DAG.getBitcast(VT, V);
19325 if (EltVT == MVT::i32) {
19326 // We unpack the low half and high half into i32s interleaved with zeros so
19327 // that we can use PSADBW to horizontally sum them. The most useful part of
19328 // this is that it lines up the results of two PSADBW instructions to be
19329 // two v2i64 vectors which concatenated are the 4 population counts. We can
19330 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19331 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19332 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19333 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19335 // Do the horizontal sums into two v2i64s.
19336 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19337 MVT SadVecVT = MVT::getVectorVT(MVT::i64, VecSize / 64);
19338 Low = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19339 DAG.getBitcast(ByteVecVT, Low), Zeros);
19340 High = DAG.getNode(X86ISD::PSADBW, DL, SadVecVT,
19341 DAG.getBitcast(ByteVecVT, High), Zeros);
19343 // Merge them together.
19344 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19345 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19346 DAG.getBitcast(ShortVecVT, Low),
19347 DAG.getBitcast(ShortVecVT, High));
19349 return DAG.getBitcast(VT, V);
19352 // The only element type left is i16.
19353 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19355 // To obtain pop count for each i16 element starting from the pop count for
19356 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19357 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19358 // directly supported.
19359 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19360 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19361 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19362 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19363 DAG.getBitcast(ByteVecVT, V));
19364 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19367 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19368 const X86Subtarget *Subtarget,
19369 SelectionDAG &DAG) {
19370 MVT VT = Op.getSimpleValueType();
19371 MVT EltVT = VT.getVectorElementType();
19372 unsigned VecSize = VT.getSizeInBits();
19374 // Implement a lookup table in register by using an algorithm based on:
19375 // http://wm.ite.pl/articles/sse-popcount.html
19377 // The general idea is that every lower byte nibble in the input vector is an
19378 // index into a in-register pre-computed pop count table. We then split up the
19379 // input vector in two new ones: (1) a vector with only the shifted-right
19380 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19381 // masked out higher ones) for each byte. PSHUB is used separately with both
19382 // to index the in-register table. Next, both are added and the result is a
19383 // i8 vector where each element contains the pop count for input byte.
19385 // To obtain the pop count for elements != i8, we follow up with the same
19386 // approach and use additional tricks as described below.
19388 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19389 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19390 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19391 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19393 int NumByteElts = VecSize / 8;
19394 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19395 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19396 SmallVector<SDValue, 16> LUTVec;
19397 for (int i = 0; i < NumByteElts; ++i)
19398 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19399 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19400 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19401 DAG.getConstant(0x0F, DL, MVT::i8));
19402 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19405 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19406 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19407 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19410 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19412 // The input vector is used as the shuffle mask that index elements into the
19413 // LUT. After counting low and high nibbles, add the vector to obtain the
19414 // final pop count per i8 element.
19415 SDValue HighPopCnt =
19416 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19417 SDValue LowPopCnt =
19418 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19419 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19421 if (EltVT == MVT::i8)
19424 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19427 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19428 const X86Subtarget *Subtarget,
19429 SelectionDAG &DAG) {
19430 MVT VT = Op.getSimpleValueType();
19431 assert(VT.is128BitVector() &&
19432 "Only 128-bit vector bitmath lowering supported.");
19434 int VecSize = VT.getSizeInBits();
19435 MVT EltVT = VT.getVectorElementType();
19436 int Len = EltVT.getSizeInBits();
19438 // This is the vectorized version of the "best" algorithm from
19439 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19440 // with a minor tweak to use a series of adds + shifts instead of vector
19441 // multiplications. Implemented for all integer vector types. We only use
19442 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19443 // much faster, even faster than using native popcnt instructions.
19445 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19446 MVT VT = V.getSimpleValueType();
19447 SmallVector<SDValue, 32> Shifters(
19448 VT.getVectorNumElements(),
19449 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19450 return DAG.getNode(OpCode, DL, VT, V,
19451 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19453 auto GetMask = [&](SDValue V, APInt Mask) {
19454 MVT VT = V.getSimpleValueType();
19455 SmallVector<SDValue, 32> Masks(
19456 VT.getVectorNumElements(),
19457 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19458 return DAG.getNode(ISD::AND, DL, VT, V,
19459 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19462 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19463 // x86, so set the SRL type to have elements at least i16 wide. This is
19464 // correct because all of our SRLs are followed immediately by a mask anyways
19465 // that handles any bits that sneak into the high bits of the byte elements.
19466 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19470 // v = v - ((v >> 1) & 0x55555555...)
19472 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19473 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19474 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19476 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19477 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19478 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19479 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19480 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19482 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19483 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19484 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19485 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19487 // At this point, V contains the byte-wise population count, and we are
19488 // merely doing a horizontal sum if necessary to get the wider element
19490 if (EltVT == MVT::i8)
19493 return LowerHorizontalByteSum(
19494 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19498 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19499 SelectionDAG &DAG) {
19500 MVT VT = Op.getSimpleValueType();
19501 // FIXME: Need to add AVX-512 support here!
19502 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19503 "Unknown CTPOP type to handle");
19504 SDLoc DL(Op.getNode());
19505 SDValue Op0 = Op.getOperand(0);
19507 if (!Subtarget->hasSSSE3()) {
19508 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19509 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19510 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19513 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19514 unsigned NumElems = VT.getVectorNumElements();
19516 // Extract each 128-bit vector, compute pop count and concat the result.
19517 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19518 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19520 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19521 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19522 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19525 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19528 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19529 SelectionDAG &DAG) {
19530 assert(Op.getSimpleValueType().isVector() &&
19531 "We only do custom lowering for vector population count.");
19532 return LowerVectorCTPOP(Op, Subtarget, DAG);
19535 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19536 SDNode *Node = Op.getNode();
19538 EVT T = Node->getValueType(0);
19539 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19540 DAG.getConstant(0, dl, T), Node->getOperand(2));
19541 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19542 cast<AtomicSDNode>(Node)->getMemoryVT(),
19543 Node->getOperand(0),
19544 Node->getOperand(1), negOp,
19545 cast<AtomicSDNode>(Node)->getMemOperand(),
19546 cast<AtomicSDNode>(Node)->getOrdering(),
19547 cast<AtomicSDNode>(Node)->getSynchScope());
19550 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19551 SDNode *Node = Op.getNode();
19553 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19555 // Convert seq_cst store -> xchg
19556 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19557 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19558 // (The only way to get a 16-byte store is cmpxchg16b)
19559 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19560 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19561 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19562 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19563 cast<AtomicSDNode>(Node)->getMemoryVT(),
19564 Node->getOperand(0),
19565 Node->getOperand(1), Node->getOperand(2),
19566 cast<AtomicSDNode>(Node)->getMemOperand(),
19567 cast<AtomicSDNode>(Node)->getOrdering(),
19568 cast<AtomicSDNode>(Node)->getSynchScope());
19569 return Swap.getValue(1);
19571 // Other atomic stores have a simple pattern.
19575 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19576 MVT VT = Op.getNode()->getSimpleValueType(0);
19578 // Let legalize expand this if it isn't a legal type yet.
19579 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19582 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19585 bool ExtraOp = false;
19586 switch (Op.getOpcode()) {
19587 default: llvm_unreachable("Invalid code");
19588 case ISD::ADDC: Opc = X86ISD::ADD; break;
19589 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19590 case ISD::SUBC: Opc = X86ISD::SUB; break;
19591 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19595 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19597 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19598 Op.getOperand(1), Op.getOperand(2));
19601 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19602 SelectionDAG &DAG) {
19603 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19605 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19606 // which returns the values as { float, float } (in XMM0) or
19607 // { double, double } (which is returned in XMM0, XMM1).
19609 SDValue Arg = Op.getOperand(0);
19610 EVT ArgVT = Arg.getValueType();
19611 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19613 TargetLowering::ArgListTy Args;
19614 TargetLowering::ArgListEntry Entry;
19618 Entry.isSExt = false;
19619 Entry.isZExt = false;
19620 Args.push_back(Entry);
19622 bool isF64 = ArgVT == MVT::f64;
19623 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19624 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19625 // the results are returned via SRet in memory.
19626 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19627 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19629 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19631 Type *RetTy = isF64
19632 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19633 : (Type*)VectorType::get(ArgTy, 4);
19635 TargetLowering::CallLoweringInfo CLI(DAG);
19636 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19637 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19639 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19642 // Returned in xmm0 and xmm1.
19643 return CallResult.first;
19645 // Returned in bits 0:31 and 32:64 xmm0.
19646 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19647 CallResult.first, DAG.getIntPtrConstant(0, dl));
19648 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19649 CallResult.first, DAG.getIntPtrConstant(1, dl));
19650 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19651 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19654 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19655 SelectionDAG &DAG) {
19656 assert(Subtarget->hasAVX512() &&
19657 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19659 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19660 MVT VT = N->getValue().getSimpleValueType();
19661 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19664 // X86 scatter kills mask register, so its type should be added to
19665 // the list of return values
19666 if (N->getNumValues() == 1) {
19667 SDValue Index = N->getIndex();
19668 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19669 !Index.getSimpleValueType().is512BitVector())
19670 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19672 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19673 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19674 N->getOperand(3), Index };
19676 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19677 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19678 return SDValue(NewScatter.getNode(), 0);
19683 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19684 SelectionDAG &DAG) {
19685 assert(Subtarget->hasAVX512() &&
19686 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19688 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19689 MVT VT = Op.getSimpleValueType();
19690 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19693 SDValue Index = N->getIndex();
19694 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19695 !Index.getSimpleValueType().is512BitVector()) {
19696 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19697 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19698 N->getOperand(3), Index };
19699 DAG.UpdateNodeOperands(N, Ops);
19704 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19705 SelectionDAG &DAG) const {
19706 // TODO: Eventually, the lowering of these nodes should be informed by or
19707 // deferred to the GC strategy for the function in which they appear. For
19708 // now, however, they must be lowered to something. Since they are logically
19709 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19710 // require special handling for these nodes), lower them as literal NOOPs for
19712 SmallVector<SDValue, 2> Ops;
19714 Ops.push_back(Op.getOperand(0));
19715 if (Op->getGluedNode())
19716 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19719 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19720 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19725 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19726 SelectionDAG &DAG) const {
19727 // TODO: Eventually, the lowering of these nodes should be informed by or
19728 // deferred to the GC strategy for the function in which they appear. For
19729 // now, however, they must be lowered to something. Since they are logically
19730 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19731 // require special handling for these nodes), lower them as literal NOOPs for
19733 SmallVector<SDValue, 2> Ops;
19735 Ops.push_back(Op.getOperand(0));
19736 if (Op->getGluedNode())
19737 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19740 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19741 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19746 /// LowerOperation - Provide custom lowering hooks for some operations.
19748 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19749 switch (Op.getOpcode()) {
19750 default: llvm_unreachable("Should not custom lower this!");
19751 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19752 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19753 return LowerCMP_SWAP(Op, Subtarget, DAG);
19754 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19755 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19756 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19757 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19758 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19759 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19760 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19761 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19762 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19763 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19764 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19765 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19766 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19767 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19768 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19769 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19770 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19771 case ISD::SHL_PARTS:
19772 case ISD::SRA_PARTS:
19773 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19774 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19775 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19776 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19777 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19778 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19779 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19780 case ISD::SIGN_EXTEND_VECTOR_INREG:
19781 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19782 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19783 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19784 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19785 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19787 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19788 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19789 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19790 case ISD::SETCC: return LowerSETCC(Op, DAG);
19791 case ISD::SETCCE: return LowerSETCCE(Op, DAG);
19792 case ISD::SELECT: return LowerSELECT(Op, DAG);
19793 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19794 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19795 case ISD::VASTART: return LowerVASTART(Op, DAG);
19796 case ISD::VAARG: return LowerVAARG(Op, DAG);
19797 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19798 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19799 case ISD::INTRINSIC_VOID:
19800 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19801 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19802 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19803 case ISD::FRAME_TO_ARGS_OFFSET:
19804 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19805 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19806 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19807 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19808 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19809 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19810 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19811 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19812 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19813 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19815 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19816 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19817 case ISD::UMUL_LOHI:
19818 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19819 case ISD::ROTL: return LowerRotate(Op, Subtarget, DAG);
19822 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19828 case ISD::UMULO: return LowerXALUO(Op, DAG);
19829 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19830 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19834 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19835 case ISD::ADD: return LowerADD(Op, DAG);
19836 case ISD::SUB: return LowerSUB(Op, DAG);
19840 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19841 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19842 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19843 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19844 case ISD::GC_TRANSITION_START:
19845 return LowerGC_TRANSITION_START(Op, DAG);
19846 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19850 /// ReplaceNodeResults - Replace a node with an illegal result type
19851 /// with a new node built out of custom code.
19852 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19853 SmallVectorImpl<SDValue>&Results,
19854 SelectionDAG &DAG) const {
19856 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19857 switch (N->getOpcode()) {
19859 llvm_unreachable("Do not know how to custom type legalize this operation!");
19860 case X86ISD::AVG: {
19861 // Legalize types for X86ISD::AVG by expanding vectors.
19862 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19864 auto InVT = N->getValueType(0);
19865 auto InVTSize = InVT.getSizeInBits();
19866 const unsigned RegSize =
19867 (InVTSize > 128) ? ((InVTSize > 256) ? 512 : 256) : 128;
19868 assert((!Subtarget->hasAVX512() || RegSize < 512) &&
19869 "512-bit vector requires AVX512");
19870 assert((!Subtarget->hasAVX2() || RegSize < 256) &&
19871 "256-bit vector requires AVX2");
19873 auto ElemVT = InVT.getVectorElementType();
19874 auto RegVT = EVT::getVectorVT(*DAG.getContext(), ElemVT,
19875 RegSize / ElemVT.getSizeInBits());
19876 assert(RegSize % InVT.getSizeInBits() == 0);
19877 unsigned NumConcat = RegSize / InVT.getSizeInBits();
19879 SmallVector<SDValue, 16> Ops(NumConcat, DAG.getUNDEF(InVT));
19880 Ops[0] = N->getOperand(0);
19881 SDValue InVec0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
19882 Ops[0] = N->getOperand(1);
19883 SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
19885 SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
19886 Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
19887 DAG.getIntPtrConstant(0, dl)));
19890 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19891 case X86ISD::FMINC:
19893 case X86ISD::FMAXC:
19894 case X86ISD::FMAX: {
19895 EVT VT = N->getValueType(0);
19896 assert(VT == MVT::v2f32 && "Unexpected type (!= v2f32) on FMIN/FMAX.");
19897 SDValue UNDEF = DAG.getUNDEF(VT);
19898 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19899 N->getOperand(0), UNDEF);
19900 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19901 N->getOperand(1), UNDEF);
19902 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19905 case ISD::SIGN_EXTEND_INREG:
19910 // We don't want to expand or promote these.
19917 case ISD::UDIVREM: {
19918 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19919 Results.push_back(V);
19922 case ISD::FP_TO_SINT:
19923 case ISD::FP_TO_UINT: {
19924 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19926 std::pair<SDValue,SDValue> Vals =
19927 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19928 SDValue FIST = Vals.first, StackSlot = Vals.second;
19929 if (FIST.getNode()) {
19930 EVT VT = N->getValueType(0);
19931 // Return a load from the stack slot.
19932 if (StackSlot.getNode())
19933 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19934 MachinePointerInfo(),
19935 false, false, false, 0));
19937 Results.push_back(FIST);
19941 case ISD::UINT_TO_FP: {
19942 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19943 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19944 N->getValueType(0) != MVT::v2f32)
19946 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19948 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19950 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19951 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19952 DAG.getBitcast(MVT::v2i64, VBias));
19953 Or = DAG.getBitcast(MVT::v2f64, Or);
19954 // TODO: Are there any fast-math-flags to propagate here?
19955 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19956 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19959 case ISD::FP_ROUND: {
19960 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19962 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19963 Results.push_back(V);
19966 case ISD::FP_EXTEND: {
19967 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19968 // No other ValueType for FP_EXTEND should reach this point.
19969 assert(N->getValueType(0) == MVT::v2f32 &&
19970 "Do not know how to legalize this Node");
19973 case ISD::INTRINSIC_W_CHAIN: {
19974 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19976 default : llvm_unreachable("Do not know how to custom type "
19977 "legalize this intrinsic operation!");
19978 case Intrinsic::x86_rdtsc:
19979 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19981 case Intrinsic::x86_rdtscp:
19982 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19984 case Intrinsic::x86_rdpmc:
19985 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19988 case ISD::READCYCLECOUNTER: {
19989 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19992 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19993 EVT T = N->getValueType(0);
19994 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19995 bool Regs64bit = T == MVT::i128;
19996 MVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19997 SDValue cpInL, cpInH;
19998 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19999 DAG.getConstant(0, dl, HalfT));
20000 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
20001 DAG.getConstant(1, dl, HalfT));
20002 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
20003 Regs64bit ? X86::RAX : X86::EAX,
20005 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
20006 Regs64bit ? X86::RDX : X86::EDX,
20007 cpInH, cpInL.getValue(1));
20008 SDValue swapInL, swapInH;
20009 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20010 DAG.getConstant(0, dl, HalfT));
20011 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
20012 DAG.getConstant(1, dl, HalfT));
20013 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
20014 Regs64bit ? X86::RBX : X86::EBX,
20015 swapInL, cpInH.getValue(1));
20016 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
20017 Regs64bit ? X86::RCX : X86::ECX,
20018 swapInH, swapInL.getValue(1));
20019 SDValue Ops[] = { swapInH.getValue(0),
20021 swapInH.getValue(1) };
20022 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
20023 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
20024 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
20025 X86ISD::LCMPXCHG8_DAG;
20026 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
20027 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
20028 Regs64bit ? X86::RAX : X86::EAX,
20029 HalfT, Result.getValue(1));
20030 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
20031 Regs64bit ? X86::RDX : X86::EDX,
20032 HalfT, cpOutL.getValue(2));
20033 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
20035 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
20036 MVT::i32, cpOutH.getValue(2));
20038 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
20039 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
20040 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
20042 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
20043 Results.push_back(Success);
20044 Results.push_back(EFLAGS.getValue(1));
20047 case ISD::ATOMIC_SWAP:
20048 case ISD::ATOMIC_LOAD_ADD:
20049 case ISD::ATOMIC_LOAD_SUB:
20050 case ISD::ATOMIC_LOAD_AND:
20051 case ISD::ATOMIC_LOAD_OR:
20052 case ISD::ATOMIC_LOAD_XOR:
20053 case ISD::ATOMIC_LOAD_NAND:
20054 case ISD::ATOMIC_LOAD_MIN:
20055 case ISD::ATOMIC_LOAD_MAX:
20056 case ISD::ATOMIC_LOAD_UMIN:
20057 case ISD::ATOMIC_LOAD_UMAX:
20058 case ISD::ATOMIC_LOAD: {
20059 // Delegate to generic TypeLegalization. Situations we can really handle
20060 // should have already been dealt with by AtomicExpandPass.cpp.
20063 case ISD::BITCAST: {
20064 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
20065 EVT DstVT = N->getValueType(0);
20066 EVT SrcVT = N->getOperand(0)->getValueType(0);
20068 if (SrcVT != MVT::f64 ||
20069 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
20072 unsigned NumElts = DstVT.getVectorNumElements();
20073 EVT SVT = DstVT.getVectorElementType();
20074 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
20075 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
20076 MVT::v2f64, N->getOperand(0));
20077 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
20079 if (ExperimentalVectorWideningLegalization) {
20080 // If we are legalizing vectors by widening, we already have the desired
20081 // legal vector type, just return it.
20082 Results.push_back(ToVecInt);
20086 SmallVector<SDValue, 8> Elts;
20087 for (unsigned i = 0, e = NumElts; i != e; ++i)
20088 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
20089 ToVecInt, DAG.getIntPtrConstant(i, dl)));
20091 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
20096 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
20097 switch ((X86ISD::NodeType)Opcode) {
20098 case X86ISD::FIRST_NUMBER: break;
20099 case X86ISD::BSF: return "X86ISD::BSF";
20100 case X86ISD::BSR: return "X86ISD::BSR";
20101 case X86ISD::SHLD: return "X86ISD::SHLD";
20102 case X86ISD::SHRD: return "X86ISD::SHRD";
20103 case X86ISD::FAND: return "X86ISD::FAND";
20104 case X86ISD::FANDN: return "X86ISD::FANDN";
20105 case X86ISD::FOR: return "X86ISD::FOR";
20106 case X86ISD::FXOR: return "X86ISD::FXOR";
20107 case X86ISD::FILD: return "X86ISD::FILD";
20108 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
20109 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
20110 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
20111 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
20112 case X86ISD::FLD: return "X86ISD::FLD";
20113 case X86ISD::FST: return "X86ISD::FST";
20114 case X86ISD::CALL: return "X86ISD::CALL";
20115 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
20116 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
20117 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
20118 case X86ISD::BT: return "X86ISD::BT";
20119 case X86ISD::CMP: return "X86ISD::CMP";
20120 case X86ISD::COMI: return "X86ISD::COMI";
20121 case X86ISD::UCOMI: return "X86ISD::UCOMI";
20122 case X86ISD::CMPM: return "X86ISD::CMPM";
20123 case X86ISD::CMPMU: return "X86ISD::CMPMU";
20124 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
20125 case X86ISD::SETCC: return "X86ISD::SETCC";
20126 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
20127 case X86ISD::FSETCC: return "X86ISD::FSETCC";
20128 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
20129 case X86ISD::CMOV: return "X86ISD::CMOV";
20130 case X86ISD::BRCOND: return "X86ISD::BRCOND";
20131 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
20132 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
20133 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
20134 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
20135 case X86ISD::Wrapper: return "X86ISD::Wrapper";
20136 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
20137 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
20138 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
20139 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
20140 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
20141 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
20142 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
20143 case X86ISD::PINSRB: return "X86ISD::PINSRB";
20144 case X86ISD::PINSRW: return "X86ISD::PINSRW";
20145 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
20146 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
20147 case X86ISD::ANDNP: return "X86ISD::ANDNP";
20148 case X86ISD::PSIGN: return "X86ISD::PSIGN";
20149 case X86ISD::BLENDI: return "X86ISD::BLENDI";
20150 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
20151 case X86ISD::ADDUS: return "X86ISD::ADDUS";
20152 case X86ISD::SUBUS: return "X86ISD::SUBUS";
20153 case X86ISD::HADD: return "X86ISD::HADD";
20154 case X86ISD::HSUB: return "X86ISD::HSUB";
20155 case X86ISD::FHADD: return "X86ISD::FHADD";
20156 case X86ISD::FHSUB: return "X86ISD::FHSUB";
20157 case X86ISD::ABS: return "X86ISD::ABS";
20158 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
20159 case X86ISD::FMAX: return "X86ISD::FMAX";
20160 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
20161 case X86ISD::FMIN: return "X86ISD::FMIN";
20162 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
20163 case X86ISD::FMAXC: return "X86ISD::FMAXC";
20164 case X86ISD::FMINC: return "X86ISD::FMINC";
20165 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
20166 case X86ISD::FRCP: return "X86ISD::FRCP";
20167 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
20168 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
20169 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
20170 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
20171 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
20172 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
20173 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
20174 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
20175 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
20176 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20177 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20178 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20179 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20180 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20181 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20182 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20183 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20184 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20185 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20186 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20187 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20188 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20189 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20190 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20191 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20192 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20193 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20194 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20195 case X86ISD::VSHL: return "X86ISD::VSHL";
20196 case X86ISD::VSRL: return "X86ISD::VSRL";
20197 case X86ISD::VSRA: return "X86ISD::VSRA";
20198 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20199 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20200 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20201 case X86ISD::CMPP: return "X86ISD::CMPP";
20202 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20203 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20204 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20205 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20206 case X86ISD::ADD: return "X86ISD::ADD";
20207 case X86ISD::SUB: return "X86ISD::SUB";
20208 case X86ISD::ADC: return "X86ISD::ADC";
20209 case X86ISD::SBB: return "X86ISD::SBB";
20210 case X86ISD::SMUL: return "X86ISD::SMUL";
20211 case X86ISD::UMUL: return "X86ISD::UMUL";
20212 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20213 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20214 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20215 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20216 case X86ISD::INC: return "X86ISD::INC";
20217 case X86ISD::DEC: return "X86ISD::DEC";
20218 case X86ISD::OR: return "X86ISD::OR";
20219 case X86ISD::XOR: return "X86ISD::XOR";
20220 case X86ISD::AND: return "X86ISD::AND";
20221 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20222 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20223 case X86ISD::PTEST: return "X86ISD::PTEST";
20224 case X86ISD::TESTP: return "X86ISD::TESTP";
20225 case X86ISD::TESTM: return "X86ISD::TESTM";
20226 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20227 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20228 case X86ISD::KTEST: return "X86ISD::KTEST";
20229 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20230 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20231 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20232 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20233 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20234 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20235 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20236 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20237 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20238 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20239 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20240 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20241 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20242 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20243 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20244 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20245 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20246 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20247 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20248 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20249 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20250 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20251 case X86ISD::VBROADCASTM: return "X86ISD::VBROADCASTM";
20252 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20253 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20254 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20255 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20256 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20257 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20258 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20259 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20260 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20261 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20262 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20263 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20264 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20265 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20266 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20267 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20268 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20269 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20270 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20271 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20272 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20273 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20274 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20275 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20276 case X86ISD::SAHF: return "X86ISD::SAHF";
20277 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20278 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20279 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20280 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20281 case X86ISD::VPROT: return "X86ISD::VPROT";
20282 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20283 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20284 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20285 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20286 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20287 case X86ISD::FMADD: return "X86ISD::FMADD";
20288 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20289 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20290 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20291 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20292 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20293 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20294 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20295 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20296 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20297 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20298 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20299 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20300 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20301 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20302 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20303 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20304 case X86ISD::XTEST: return "X86ISD::XTEST";
20305 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20306 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20307 case X86ISD::SELECT: return "X86ISD::SELECT";
20308 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20309 case X86ISD::RCP28: return "X86ISD::RCP28";
20310 case X86ISD::EXP2: return "X86ISD::EXP2";
20311 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20312 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20313 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20314 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20315 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20316 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20317 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20318 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20319 case X86ISD::ADDS: return "X86ISD::ADDS";
20320 case X86ISD::SUBS: return "X86ISD::SUBS";
20321 case X86ISD::AVG: return "X86ISD::AVG";
20322 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20323 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20324 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20325 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20326 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20327 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20332 // isLegalAddressingMode - Return true if the addressing mode represented
20333 // by AM is legal for this target, for a load/store of the specified type.
20334 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20335 const AddrMode &AM, Type *Ty,
20336 unsigned AS) const {
20337 // X86 supports extremely general addressing modes.
20338 CodeModel::Model M = getTargetMachine().getCodeModel();
20339 Reloc::Model R = getTargetMachine().getRelocationModel();
20341 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20342 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20347 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20349 // If a reference to this global requires an extra load, we can't fold it.
20350 if (isGlobalStubReference(GVFlags))
20353 // If BaseGV requires a register for the PIC base, we cannot also have a
20354 // BaseReg specified.
20355 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20358 // If lower 4G is not available, then we must use rip-relative addressing.
20359 if ((M != CodeModel::Small || R != Reloc::Static) &&
20360 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20364 switch (AM.Scale) {
20370 // These scales always work.
20375 // These scales are formed with basereg+scalereg. Only accept if there is
20380 default: // Other stuff never works.
20387 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20388 unsigned Bits = Ty->getScalarSizeInBits();
20390 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20391 // particularly cheaper than those without.
20395 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20396 // variable shifts just as cheap as scalar ones.
20397 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20400 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20401 // fully general vector.
20405 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20406 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20408 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20409 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20410 return NumBits1 > NumBits2;
20413 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20414 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20417 if (!isTypeLegal(EVT::getEVT(Ty1)))
20420 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20422 // Assuming the caller doesn't have a zeroext or signext return parameter,
20423 // truncation all the way down to i1 is valid.
20427 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20428 return isInt<32>(Imm);
20431 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20432 // Can also use sub to handle negated immediates.
20433 return isInt<32>(Imm);
20436 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20437 if (!VT1.isInteger() || !VT2.isInteger())
20439 unsigned NumBits1 = VT1.getSizeInBits();
20440 unsigned NumBits2 = VT2.getSizeInBits();
20441 return NumBits1 > NumBits2;
20444 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20445 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20446 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20449 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20450 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20451 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20454 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20455 EVT VT1 = Val.getValueType();
20456 if (isZExtFree(VT1, VT2))
20459 if (Val.getOpcode() != ISD::LOAD)
20462 if (!VT1.isSimple() || !VT1.isInteger() ||
20463 !VT2.isSimple() || !VT2.isInteger())
20466 switch (VT1.getSimpleVT().SimpleTy) {
20471 // X86 has 8, 16, and 32-bit zero-extending loads.
20478 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20481 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20482 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20485 VT = VT.getScalarType();
20487 if (!VT.isSimple())
20490 switch (VT.getSimpleVT().SimpleTy) {
20501 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20502 // i16 instructions are longer (0x66 prefix) and potentially slower.
20503 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20506 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20507 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20508 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20509 /// are assumed to be legal.
20511 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20513 if (!VT.isSimple())
20516 // Not for i1 vectors
20517 if (VT.getSimpleVT().getScalarType() == MVT::i1)
20520 // Very little shuffling can be done for 64-bit vectors right now.
20521 if (VT.getSimpleVT().getSizeInBits() == 64)
20524 // We only care that the types being shuffled are legal. The lowering can
20525 // handle any possible shuffle mask that results.
20526 return isTypeLegal(VT.getSimpleVT());
20530 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20532 // Just delegate to the generic legality, clear masks aren't special.
20533 return isShuffleMaskLegal(Mask, VT);
20536 //===----------------------------------------------------------------------===//
20537 // X86 Scheduler Hooks
20538 //===----------------------------------------------------------------------===//
20540 /// Utility function to emit xbegin specifying the start of an RTM region.
20541 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20542 const TargetInstrInfo *TII) {
20543 DebugLoc DL = MI->getDebugLoc();
20545 const BasicBlock *BB = MBB->getBasicBlock();
20546 MachineFunction::iterator I = ++MBB->getIterator();
20548 // For the v = xbegin(), we generate
20559 MachineBasicBlock *thisMBB = MBB;
20560 MachineFunction *MF = MBB->getParent();
20561 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20562 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20563 MF->insert(I, mainMBB);
20564 MF->insert(I, sinkMBB);
20566 // Transfer the remainder of BB and its successor edges to sinkMBB.
20567 sinkMBB->splice(sinkMBB->begin(), MBB,
20568 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20569 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20573 // # fallthrough to mainMBB
20574 // # abortion to sinkMBB
20575 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20576 thisMBB->addSuccessor(mainMBB);
20577 thisMBB->addSuccessor(sinkMBB);
20581 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20582 mainMBB->addSuccessor(sinkMBB);
20585 // EAX is live into the sinkMBB
20586 sinkMBB->addLiveIn(X86::EAX);
20587 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20588 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20591 MI->eraseFromParent();
20595 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20596 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20597 // in the .td file.
20598 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20599 const TargetInstrInfo *TII) {
20601 switch (MI->getOpcode()) {
20602 default: llvm_unreachable("illegal opcode!");
20603 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20604 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20605 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20606 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20607 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20608 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20609 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20610 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20613 DebugLoc dl = MI->getDebugLoc();
20614 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20616 unsigned NumArgs = MI->getNumOperands();
20617 for (unsigned i = 1; i < NumArgs; ++i) {
20618 MachineOperand &Op = MI->getOperand(i);
20619 if (!(Op.isReg() && Op.isImplicit()))
20620 MIB.addOperand(Op);
20622 if (MI->hasOneMemOperand())
20623 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20625 BuildMI(*BB, MI, dl,
20626 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20627 .addReg(X86::XMM0);
20629 MI->eraseFromParent();
20633 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20634 // defs in an instruction pattern
20635 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20636 const TargetInstrInfo *TII) {
20638 switch (MI->getOpcode()) {
20639 default: llvm_unreachable("illegal opcode!");
20640 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20641 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20642 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20643 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20644 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20645 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20646 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20647 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20650 DebugLoc dl = MI->getDebugLoc();
20651 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20653 unsigned NumArgs = MI->getNumOperands(); // remove the results
20654 for (unsigned i = 1; i < NumArgs; ++i) {
20655 MachineOperand &Op = MI->getOperand(i);
20656 if (!(Op.isReg() && Op.isImplicit()))
20657 MIB.addOperand(Op);
20659 if (MI->hasOneMemOperand())
20660 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20662 BuildMI(*BB, MI, dl,
20663 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20666 MI->eraseFromParent();
20670 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20671 const X86Subtarget *Subtarget) {
20672 DebugLoc dl = MI->getDebugLoc();
20673 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20674 // Address into RAX/EAX, other two args into ECX, EDX.
20675 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20676 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20677 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20678 for (int i = 0; i < X86::AddrNumOperands; ++i)
20679 MIB.addOperand(MI->getOperand(i));
20681 unsigned ValOps = X86::AddrNumOperands;
20682 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20683 .addReg(MI->getOperand(ValOps).getReg());
20684 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20685 .addReg(MI->getOperand(ValOps+1).getReg());
20687 // The instruction doesn't actually take any operands though.
20688 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20690 MI->eraseFromParent(); // The pseudo is gone now.
20694 MachineBasicBlock *
20695 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20696 MachineBasicBlock *MBB) const {
20697 // Emit va_arg instruction on X86-64.
20699 // Operands to this pseudo-instruction:
20700 // 0 ) Output : destination address (reg)
20701 // 1-5) Input : va_list address (addr, i64mem)
20702 // 6 ) ArgSize : Size (in bytes) of vararg type
20703 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20704 // 8 ) Align : Alignment of type
20705 // 9 ) EFLAGS (implicit-def)
20707 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20708 static_assert(X86::AddrNumOperands == 5,
20709 "VAARG_64 assumes 5 address operands");
20711 unsigned DestReg = MI->getOperand(0).getReg();
20712 MachineOperand &Base = MI->getOperand(1);
20713 MachineOperand &Scale = MI->getOperand(2);
20714 MachineOperand &Index = MI->getOperand(3);
20715 MachineOperand &Disp = MI->getOperand(4);
20716 MachineOperand &Segment = MI->getOperand(5);
20717 unsigned ArgSize = MI->getOperand(6).getImm();
20718 unsigned ArgMode = MI->getOperand(7).getImm();
20719 unsigned Align = MI->getOperand(8).getImm();
20721 // Memory Reference
20722 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20723 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20724 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20726 // Machine Information
20727 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20728 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20729 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20730 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20731 DebugLoc DL = MI->getDebugLoc();
20733 // struct va_list {
20736 // i64 overflow_area (address)
20737 // i64 reg_save_area (address)
20739 // sizeof(va_list) = 24
20740 // alignment(va_list) = 8
20742 unsigned TotalNumIntRegs = 6;
20743 unsigned TotalNumXMMRegs = 8;
20744 bool UseGPOffset = (ArgMode == 1);
20745 bool UseFPOffset = (ArgMode == 2);
20746 unsigned MaxOffset = TotalNumIntRegs * 8 +
20747 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20749 /* Align ArgSize to a multiple of 8 */
20750 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20751 bool NeedsAlign = (Align > 8);
20753 MachineBasicBlock *thisMBB = MBB;
20754 MachineBasicBlock *overflowMBB;
20755 MachineBasicBlock *offsetMBB;
20756 MachineBasicBlock *endMBB;
20758 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20759 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20760 unsigned OffsetReg = 0;
20762 if (!UseGPOffset && !UseFPOffset) {
20763 // If we only pull from the overflow region, we don't create a branch.
20764 // We don't need to alter control flow.
20765 OffsetDestReg = 0; // unused
20766 OverflowDestReg = DestReg;
20768 offsetMBB = nullptr;
20769 overflowMBB = thisMBB;
20772 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20773 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20774 // If not, pull from overflow_area. (branch to overflowMBB)
20779 // offsetMBB overflowMBB
20784 // Registers for the PHI in endMBB
20785 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20786 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20788 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20789 MachineFunction *MF = MBB->getParent();
20790 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20791 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20792 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20794 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20796 // Insert the new basic blocks
20797 MF->insert(MBBIter, offsetMBB);
20798 MF->insert(MBBIter, overflowMBB);
20799 MF->insert(MBBIter, endMBB);
20801 // Transfer the remainder of MBB and its successor edges to endMBB.
20802 endMBB->splice(endMBB->begin(), thisMBB,
20803 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20804 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20806 // Make offsetMBB and overflowMBB successors of thisMBB
20807 thisMBB->addSuccessor(offsetMBB);
20808 thisMBB->addSuccessor(overflowMBB);
20810 // endMBB is a successor of both offsetMBB and overflowMBB
20811 offsetMBB->addSuccessor(endMBB);
20812 overflowMBB->addSuccessor(endMBB);
20814 // Load the offset value into a register
20815 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20816 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20820 .addDisp(Disp, UseFPOffset ? 4 : 0)
20821 .addOperand(Segment)
20822 .setMemRefs(MMOBegin, MMOEnd);
20824 // Check if there is enough room left to pull this argument.
20825 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20827 .addImm(MaxOffset + 8 - ArgSizeA8);
20829 // Branch to "overflowMBB" if offset >= max
20830 // Fall through to "offsetMBB" otherwise
20831 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20832 .addMBB(overflowMBB);
20835 // In offsetMBB, emit code to use the reg_save_area.
20837 assert(OffsetReg != 0);
20839 // Read the reg_save_area address.
20840 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20841 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20846 .addOperand(Segment)
20847 .setMemRefs(MMOBegin, MMOEnd);
20849 // Zero-extend the offset
20850 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20851 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20854 .addImm(X86::sub_32bit);
20856 // Add the offset to the reg_save_area to get the final address.
20857 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20858 .addReg(OffsetReg64)
20859 .addReg(RegSaveReg);
20861 // Compute the offset for the next argument
20862 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20863 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20865 .addImm(UseFPOffset ? 16 : 8);
20867 // Store it back into the va_list.
20868 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20872 .addDisp(Disp, UseFPOffset ? 4 : 0)
20873 .addOperand(Segment)
20874 .addReg(NextOffsetReg)
20875 .setMemRefs(MMOBegin, MMOEnd);
20878 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20883 // Emit code to use overflow area
20886 // Load the overflow_area address into a register.
20887 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20888 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20893 .addOperand(Segment)
20894 .setMemRefs(MMOBegin, MMOEnd);
20896 // If we need to align it, do so. Otherwise, just copy the address
20897 // to OverflowDestReg.
20899 // Align the overflow address
20900 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20901 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20903 // aligned_addr = (addr + (align-1)) & ~(align-1)
20904 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20905 .addReg(OverflowAddrReg)
20908 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20910 .addImm(~(uint64_t)(Align-1));
20912 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20913 .addReg(OverflowAddrReg);
20916 // Compute the next overflow address after this argument.
20917 // (the overflow address should be kept 8-byte aligned)
20918 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20919 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20920 .addReg(OverflowDestReg)
20921 .addImm(ArgSizeA8);
20923 // Store the new overflow address.
20924 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20929 .addOperand(Segment)
20930 .addReg(NextAddrReg)
20931 .setMemRefs(MMOBegin, MMOEnd);
20933 // If we branched, emit the PHI to the front of endMBB.
20935 BuildMI(*endMBB, endMBB->begin(), DL,
20936 TII->get(X86::PHI), DestReg)
20937 .addReg(OffsetDestReg).addMBB(offsetMBB)
20938 .addReg(OverflowDestReg).addMBB(overflowMBB);
20941 // Erase the pseudo instruction
20942 MI->eraseFromParent();
20947 MachineBasicBlock *
20948 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20950 MachineBasicBlock *MBB) const {
20951 // Emit code to save XMM registers to the stack. The ABI says that the
20952 // number of registers to save is given in %al, so it's theoretically
20953 // possible to do an indirect jump trick to avoid saving all of them,
20954 // however this code takes a simpler approach and just executes all
20955 // of the stores if %al is non-zero. It's less code, and it's probably
20956 // easier on the hardware branch predictor, and stores aren't all that
20957 // expensive anyway.
20959 // Create the new basic blocks. One block contains all the XMM stores,
20960 // and one block is the final destination regardless of whether any
20961 // stores were performed.
20962 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20963 MachineFunction *F = MBB->getParent();
20964 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20965 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20966 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20967 F->insert(MBBIter, XMMSaveMBB);
20968 F->insert(MBBIter, EndMBB);
20970 // Transfer the remainder of MBB and its successor edges to EndMBB.
20971 EndMBB->splice(EndMBB->begin(), MBB,
20972 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20973 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20975 // The original block will now fall through to the XMM save block.
20976 MBB->addSuccessor(XMMSaveMBB);
20977 // The XMMSaveMBB will fall through to the end block.
20978 XMMSaveMBB->addSuccessor(EndMBB);
20980 // Now add the instructions.
20981 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20982 DebugLoc DL = MI->getDebugLoc();
20984 unsigned CountReg = MI->getOperand(0).getReg();
20985 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20986 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20988 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20989 // If %al is 0, branch around the XMM save block.
20990 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20991 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20992 MBB->addSuccessor(EndMBB);
20995 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20996 // that was just emitted, but clearly shouldn't be "saved".
20997 assert((MI->getNumOperands() <= 3 ||
20998 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20999 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
21000 && "Expected last argument to be EFLAGS");
21001 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
21002 // In the XMM save block, save all the XMM argument registers.
21003 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
21004 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
21005 MachineMemOperand *MMO = F->getMachineMemOperand(
21006 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
21007 MachineMemOperand::MOStore,
21008 /*Size=*/16, /*Align=*/16);
21009 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
21010 .addFrameIndex(RegSaveFrameIndex)
21011 .addImm(/*Scale=*/1)
21012 .addReg(/*IndexReg=*/0)
21013 .addImm(/*Disp=*/Offset)
21014 .addReg(/*Segment=*/0)
21015 .addReg(MI->getOperand(i).getReg())
21016 .addMemOperand(MMO);
21019 MI->eraseFromParent(); // The pseudo instruction is gone now.
21024 // The EFLAGS operand of SelectItr might be missing a kill marker
21025 // because there were multiple uses of EFLAGS, and ISel didn't know
21026 // which to mark. Figure out whether SelectItr should have had a
21027 // kill marker, and set it if it should. Returns the correct kill
21029 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
21030 MachineBasicBlock* BB,
21031 const TargetRegisterInfo* TRI) {
21032 // Scan forward through BB for a use/def of EFLAGS.
21033 MachineBasicBlock::iterator miI(std::next(SelectItr));
21034 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
21035 const MachineInstr& mi = *miI;
21036 if (mi.readsRegister(X86::EFLAGS))
21038 if (mi.definesRegister(X86::EFLAGS))
21039 break; // Should have kill-flag - update below.
21042 // If we hit the end of the block, check whether EFLAGS is live into a
21044 if (miI == BB->end()) {
21045 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
21046 sEnd = BB->succ_end();
21047 sItr != sEnd; ++sItr) {
21048 MachineBasicBlock* succ = *sItr;
21049 if (succ->isLiveIn(X86::EFLAGS))
21054 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
21055 // out. SelectMI should have a kill flag on EFLAGS.
21056 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
21060 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
21061 // together with other CMOV pseudo-opcodes into a single basic-block with
21062 // conditional jump around it.
21063 static bool isCMOVPseudo(MachineInstr *MI) {
21064 switch (MI->getOpcode()) {
21065 case X86::CMOV_FR32:
21066 case X86::CMOV_FR64:
21067 case X86::CMOV_GR8:
21068 case X86::CMOV_GR16:
21069 case X86::CMOV_GR32:
21070 case X86::CMOV_RFP32:
21071 case X86::CMOV_RFP64:
21072 case X86::CMOV_RFP80:
21073 case X86::CMOV_V2F64:
21074 case X86::CMOV_V2I64:
21075 case X86::CMOV_V4F32:
21076 case X86::CMOV_V4F64:
21077 case X86::CMOV_V4I64:
21078 case X86::CMOV_V16F32:
21079 case X86::CMOV_V8F32:
21080 case X86::CMOV_V8F64:
21081 case X86::CMOV_V8I64:
21082 case X86::CMOV_V8I1:
21083 case X86::CMOV_V16I1:
21084 case X86::CMOV_V32I1:
21085 case X86::CMOV_V64I1:
21093 MachineBasicBlock *
21094 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
21095 MachineBasicBlock *BB) const {
21096 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21097 DebugLoc DL = MI->getDebugLoc();
21099 // To "insert" a SELECT_CC instruction, we actually have to insert the
21100 // diamond control-flow pattern. The incoming instruction knows the
21101 // destination vreg to set, the condition code register to branch on, the
21102 // true/false values to select between, and a branch opcode to use.
21103 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21104 MachineFunction::iterator It = ++BB->getIterator();
21109 // cmpTY ccX, r1, r2
21111 // fallthrough --> copy0MBB
21112 MachineBasicBlock *thisMBB = BB;
21113 MachineFunction *F = BB->getParent();
21115 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
21116 // as described above, by inserting a BB, and then making a PHI at the join
21117 // point to select the true and false operands of the CMOV in the PHI.
21119 // The code also handles two different cases of multiple CMOV opcodes
21123 // In this case, there are multiple CMOVs in a row, all which are based on
21124 // the same condition setting (or the exact opposite condition setting).
21125 // In this case we can lower all the CMOVs using a single inserted BB, and
21126 // then make a number of PHIs at the join point to model the CMOVs. The only
21127 // trickiness here, is that in a case like:
21129 // t2 = CMOV cond1 t1, f1
21130 // t3 = CMOV cond1 t2, f2
21132 // when rewriting this into PHIs, we have to perform some renaming on the
21133 // temps since you cannot have a PHI operand refer to a PHI result earlier
21134 // in the same block. The "simple" but wrong lowering would be:
21136 // t2 = PHI t1(BB1), f1(BB2)
21137 // t3 = PHI t2(BB1), f2(BB2)
21139 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
21140 // renaming is to note that on the path through BB1, t2 is really just a
21141 // copy of t1, and do that renaming, properly generating:
21143 // t2 = PHI t1(BB1), f1(BB2)
21144 // t3 = PHI t1(BB1), f2(BB2)
21146 // Case 2, we lower cascaded CMOVs such as
21148 // (CMOV (CMOV F, T, cc1), T, cc2)
21150 // to two successives branches. For that, we look for another CMOV as the
21151 // following instruction.
21153 // Without this, we would add a PHI between the two jumps, which ends up
21154 // creating a few copies all around. For instance, for
21156 // (sitofp (zext (fcmp une)))
21158 // we would generate:
21160 // ucomiss %xmm1, %xmm0
21161 // movss <1.0f>, %xmm0
21162 // movaps %xmm0, %xmm1
21164 // xorps %xmm1, %xmm1
21167 // movaps %xmm1, %xmm0
21171 // because this custom-inserter would have generated:
21183 // A: X = ...; Y = ...
21185 // C: Z = PHI [X, A], [Y, B]
21187 // E: PHI [X, C], [Z, D]
21189 // If we lower both CMOVs in a single step, we can instead generate:
21201 // A: X = ...; Y = ...
21203 // E: PHI [X, A], [X, C], [Y, D]
21205 // Which, in our sitofp/fcmp example, gives us something like:
21207 // ucomiss %xmm1, %xmm0
21208 // movss <1.0f>, %xmm0
21211 // xorps %xmm0, %xmm0
21215 MachineInstr *CascadedCMOV = nullptr;
21216 MachineInstr *LastCMOV = MI;
21217 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21218 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21219 MachineBasicBlock::iterator NextMIIt =
21220 std::next(MachineBasicBlock::iterator(MI));
21222 // Check for case 1, where there are multiple CMOVs with the same condition
21223 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21224 // number of jumps the most.
21226 if (isCMOVPseudo(MI)) {
21227 // See if we have a string of CMOVS with the same condition.
21228 while (NextMIIt != BB->end() &&
21229 isCMOVPseudo(NextMIIt) &&
21230 (NextMIIt->getOperand(3).getImm() == CC ||
21231 NextMIIt->getOperand(3).getImm() == OppCC)) {
21232 LastCMOV = &*NextMIIt;
21237 // This checks for case 2, but only do this if we didn't already find
21238 // case 1, as indicated by LastCMOV == MI.
21239 if (LastCMOV == MI &&
21240 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21241 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21242 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21243 CascadedCMOV = &*NextMIIt;
21246 MachineBasicBlock *jcc1MBB = nullptr;
21248 // If we have a cascaded CMOV, we lower it to two successive branches to
21249 // the same block. EFLAGS is used by both, so mark it as live in the second.
21250 if (CascadedCMOV) {
21251 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21252 F->insert(It, jcc1MBB);
21253 jcc1MBB->addLiveIn(X86::EFLAGS);
21256 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21257 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21258 F->insert(It, copy0MBB);
21259 F->insert(It, sinkMBB);
21261 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21262 // live into the sink and copy blocks.
21263 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21265 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21266 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21267 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21268 copy0MBB->addLiveIn(X86::EFLAGS);
21269 sinkMBB->addLiveIn(X86::EFLAGS);
21272 // Transfer the remainder of BB and its successor edges to sinkMBB.
21273 sinkMBB->splice(sinkMBB->begin(), BB,
21274 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21275 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21277 // Add the true and fallthrough blocks as its successors.
21278 if (CascadedCMOV) {
21279 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21280 BB->addSuccessor(jcc1MBB);
21282 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21283 // jump to the sinkMBB.
21284 jcc1MBB->addSuccessor(copy0MBB);
21285 jcc1MBB->addSuccessor(sinkMBB);
21287 BB->addSuccessor(copy0MBB);
21290 // The true block target of the first (or only) branch is always sinkMBB.
21291 BB->addSuccessor(sinkMBB);
21293 // Create the conditional branch instruction.
21294 unsigned Opc = X86::GetCondBranchFromCond(CC);
21295 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21297 if (CascadedCMOV) {
21298 unsigned Opc2 = X86::GetCondBranchFromCond(
21299 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21300 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21304 // %FalseValue = ...
21305 // # fallthrough to sinkMBB
21306 copy0MBB->addSuccessor(sinkMBB);
21309 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21311 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21312 MachineBasicBlock::iterator MIItEnd =
21313 std::next(MachineBasicBlock::iterator(LastCMOV));
21314 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21315 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21316 MachineInstrBuilder MIB;
21318 // As we are creating the PHIs, we have to be careful if there is more than
21319 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21320 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21321 // That also means that PHI construction must work forward from earlier to
21322 // later, and that the code must maintain a mapping from earlier PHI's
21323 // destination registers, and the registers that went into the PHI.
21325 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21326 unsigned DestReg = MIIt->getOperand(0).getReg();
21327 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21328 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21330 // If this CMOV we are generating is the opposite condition from
21331 // the jump we generated, then we have to swap the operands for the
21332 // PHI that is going to be generated.
21333 if (MIIt->getOperand(3).getImm() == OppCC)
21334 std::swap(Op1Reg, Op2Reg);
21336 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21337 Op1Reg = RegRewriteTable[Op1Reg].first;
21339 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21340 Op2Reg = RegRewriteTable[Op2Reg].second;
21342 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21343 TII->get(X86::PHI), DestReg)
21344 .addReg(Op1Reg).addMBB(copy0MBB)
21345 .addReg(Op2Reg).addMBB(thisMBB);
21347 // Add this PHI to the rewrite table.
21348 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21351 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21352 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21353 if (CascadedCMOV) {
21354 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21355 // Copy the PHI result to the register defined by the second CMOV.
21356 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21357 DL, TII->get(TargetOpcode::COPY),
21358 CascadedCMOV->getOperand(0).getReg())
21359 .addReg(MI->getOperand(0).getReg());
21360 CascadedCMOV->eraseFromParent();
21363 // Now remove the CMOV(s).
21364 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21365 (MIIt++)->eraseFromParent();
21370 MachineBasicBlock *
21371 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21372 MachineBasicBlock *BB) const {
21373 // Combine the following atomic floating-point modification pattern:
21374 // a.store(reg OP a.load(acquire), release)
21375 // Transform them into:
21376 // OPss (%gpr), %xmm
21377 // movss %xmm, (%gpr)
21378 // Or sd equivalent for 64-bit operations.
21380 switch (MI->getOpcode()) {
21381 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21382 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21383 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21385 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21386 DebugLoc DL = MI->getDebugLoc();
21387 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21388 MachineOperand MSrc = MI->getOperand(0);
21389 unsigned VSrc = MI->getOperand(5).getReg();
21390 const MachineOperand &Disp = MI->getOperand(3);
21391 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21392 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21393 if (hasDisp && MSrc.isReg())
21394 MSrc.setIsKill(false);
21395 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21396 .addOperand(/*Base=*/MSrc)
21397 .addImm(/*Scale=*/1)
21398 .addReg(/*Index=*/0)
21399 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21401 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21402 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21404 .addOperand(/*Base=*/MSrc)
21405 .addImm(/*Scale=*/1)
21406 .addReg(/*Index=*/0)
21407 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21408 .addReg(/*Segment=*/0);
21409 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21410 MI->eraseFromParent(); // The pseudo instruction is gone now.
21414 MachineBasicBlock *
21415 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21416 MachineBasicBlock *BB) const {
21417 MachineFunction *MF = BB->getParent();
21418 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21419 DebugLoc DL = MI->getDebugLoc();
21420 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21422 assert(MF->shouldSplitStack());
21424 const bool Is64Bit = Subtarget->is64Bit();
21425 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21427 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21428 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21431 // ... [Till the alloca]
21432 // If stacklet is not large enough, jump to mallocMBB
21435 // Allocate by subtracting from RSP
21436 // Jump to continueMBB
21439 // Allocate by call to runtime
21443 // [rest of original BB]
21446 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21447 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21448 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21450 MachineRegisterInfo &MRI = MF->getRegInfo();
21451 const TargetRegisterClass *AddrRegClass =
21452 getRegClassFor(getPointerTy(MF->getDataLayout()));
21454 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21455 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21456 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21457 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21458 sizeVReg = MI->getOperand(1).getReg(),
21459 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21461 MachineFunction::iterator MBBIter = ++BB->getIterator();
21463 MF->insert(MBBIter, bumpMBB);
21464 MF->insert(MBBIter, mallocMBB);
21465 MF->insert(MBBIter, continueMBB);
21467 continueMBB->splice(continueMBB->begin(), BB,
21468 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21469 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21471 // Add code to the main basic block to check if the stack limit has been hit,
21472 // and if so, jump to mallocMBB otherwise to bumpMBB.
21473 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21474 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21475 .addReg(tmpSPVReg).addReg(sizeVReg);
21476 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21477 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21478 .addReg(SPLimitVReg);
21479 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21481 // bumpMBB simply decreases the stack pointer, since we know the current
21482 // stacklet has enough space.
21483 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21484 .addReg(SPLimitVReg);
21485 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21486 .addReg(SPLimitVReg);
21487 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21489 // Calls into a routine in libgcc to allocate more space from the heap.
21490 const uint32_t *RegMask =
21491 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21493 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21495 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21496 .addExternalSymbol("__morestack_allocate_stack_space")
21497 .addRegMask(RegMask)
21498 .addReg(X86::RDI, RegState::Implicit)
21499 .addReg(X86::RAX, RegState::ImplicitDefine);
21500 } else if (Is64Bit) {
21501 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21503 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21504 .addExternalSymbol("__morestack_allocate_stack_space")
21505 .addRegMask(RegMask)
21506 .addReg(X86::EDI, RegState::Implicit)
21507 .addReg(X86::EAX, RegState::ImplicitDefine);
21509 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21511 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21512 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21513 .addExternalSymbol("__morestack_allocate_stack_space")
21514 .addRegMask(RegMask)
21515 .addReg(X86::EAX, RegState::ImplicitDefine);
21519 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21522 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21523 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21524 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21526 // Set up the CFG correctly.
21527 BB->addSuccessor(bumpMBB);
21528 BB->addSuccessor(mallocMBB);
21529 mallocMBB->addSuccessor(continueMBB);
21530 bumpMBB->addSuccessor(continueMBB);
21532 // Take care of the PHI nodes.
21533 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21534 MI->getOperand(0).getReg())
21535 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21536 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21538 // Delete the original pseudo instruction.
21539 MI->eraseFromParent();
21542 return continueMBB;
21545 MachineBasicBlock *
21546 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21547 MachineBasicBlock *BB) const {
21548 assert(!Subtarget->isTargetMachO());
21549 DebugLoc DL = MI->getDebugLoc();
21550 MachineInstr *ResumeMI = Subtarget->getFrameLowering()->emitStackProbe(
21551 *BB->getParent(), *BB, MI, DL, false);
21552 MachineBasicBlock *ResumeBB = ResumeMI->getParent();
21553 MI->eraseFromParent(); // The pseudo instruction is gone now.
21557 MachineBasicBlock *
21558 X86TargetLowering::EmitLoweredCatchRet(MachineInstr *MI,
21559 MachineBasicBlock *BB) const {
21560 MachineFunction *MF = BB->getParent();
21561 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21562 MachineBasicBlock *TargetMBB = MI->getOperand(0).getMBB();
21563 DebugLoc DL = MI->getDebugLoc();
21565 assert(!isAsynchronousEHPersonality(
21566 classifyEHPersonality(MF->getFunction()->getPersonalityFn())) &&
21567 "SEH does not use catchret!");
21569 // Only 32-bit EH needs to worry about manually restoring stack pointers.
21570 if (!Subtarget->is32Bit())
21573 // C++ EH creates a new target block to hold the restore code, and wires up
21574 // the new block to the return destination with a normal JMP_4.
21575 MachineBasicBlock *RestoreMBB =
21576 MF->CreateMachineBasicBlock(BB->getBasicBlock());
21577 assert(BB->succ_size() == 1);
21578 MF->insert(std::next(BB->getIterator()), RestoreMBB);
21579 RestoreMBB->transferSuccessorsAndUpdatePHIs(BB);
21580 BB->addSuccessor(RestoreMBB);
21581 MI->getOperand(0).setMBB(RestoreMBB);
21583 auto RestoreMBBI = RestoreMBB->begin();
21584 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::EH_RESTORE));
21585 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
21589 MachineBasicBlock *
21590 X86TargetLowering::EmitLoweredCatchPad(MachineInstr *MI,
21591 MachineBasicBlock *BB) const {
21592 MachineFunction *MF = BB->getParent();
21593 const Constant *PerFn = MF->getFunction()->getPersonalityFn();
21594 bool IsSEH = isAsynchronousEHPersonality(classifyEHPersonality(PerFn));
21595 // Only 32-bit SEH requires special handling for catchpad.
21596 if (IsSEH && Subtarget->is32Bit()) {
21597 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21598 DebugLoc DL = MI->getDebugLoc();
21599 BuildMI(*BB, MI, DL, TII.get(X86::EH_RESTORE));
21601 MI->eraseFromParent();
21605 MachineBasicBlock *
21606 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21607 MachineBasicBlock *BB) const {
21608 // This is pretty easy. We're taking the value that we received from
21609 // our load from the relocation, sticking it in either RDI (x86-64)
21610 // or EAX and doing an indirect call. The return value will then
21611 // be in the normal return register.
21612 MachineFunction *F = BB->getParent();
21613 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21614 DebugLoc DL = MI->getDebugLoc();
21616 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21617 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21619 // Get a register mask for the lowered call.
21620 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21621 // proper register mask.
21622 const uint32_t *RegMask =
21623 Subtarget->is64Bit() ?
21624 Subtarget->getRegisterInfo()->getDarwinTLSCallPreservedMask() :
21625 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21626 if (Subtarget->is64Bit()) {
21627 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21628 TII->get(X86::MOV64rm), X86::RDI)
21630 .addImm(0).addReg(0)
21631 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21632 MI->getOperand(3).getTargetFlags())
21634 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21635 addDirectMem(MIB, X86::RDI);
21636 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21637 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21638 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21639 TII->get(X86::MOV32rm), X86::EAX)
21641 .addImm(0).addReg(0)
21642 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21643 MI->getOperand(3).getTargetFlags())
21645 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21646 addDirectMem(MIB, X86::EAX);
21647 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21649 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21650 TII->get(X86::MOV32rm), X86::EAX)
21651 .addReg(TII->getGlobalBaseReg(F))
21652 .addImm(0).addReg(0)
21653 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21654 MI->getOperand(3).getTargetFlags())
21656 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21657 addDirectMem(MIB, X86::EAX);
21658 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21661 MI->eraseFromParent(); // The pseudo instruction is gone now.
21665 MachineBasicBlock *
21666 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21667 MachineBasicBlock *MBB) const {
21668 DebugLoc DL = MI->getDebugLoc();
21669 MachineFunction *MF = MBB->getParent();
21670 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21671 MachineRegisterInfo &MRI = MF->getRegInfo();
21673 const BasicBlock *BB = MBB->getBasicBlock();
21674 MachineFunction::iterator I = ++MBB->getIterator();
21676 // Memory Reference
21677 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21678 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21681 unsigned MemOpndSlot = 0;
21683 unsigned CurOp = 0;
21685 DstReg = MI->getOperand(CurOp++).getReg();
21686 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21687 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21688 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21689 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21691 MemOpndSlot = CurOp;
21693 MVT PVT = getPointerTy(MF->getDataLayout());
21694 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21695 "Invalid Pointer Size!");
21697 // For v = setjmp(buf), we generate
21700 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21701 // SjLjSetup restoreMBB
21707 // v = phi(main, restore)
21710 // if base pointer being used, load it from frame
21713 MachineBasicBlock *thisMBB = MBB;
21714 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21715 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21716 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21717 MF->insert(I, mainMBB);
21718 MF->insert(I, sinkMBB);
21719 MF->push_back(restoreMBB);
21720 restoreMBB->setHasAddressTaken();
21722 MachineInstrBuilder MIB;
21724 // Transfer the remainder of BB and its successor edges to sinkMBB.
21725 sinkMBB->splice(sinkMBB->begin(), MBB,
21726 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21727 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21730 unsigned PtrStoreOpc = 0;
21731 unsigned LabelReg = 0;
21732 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21733 Reloc::Model RM = MF->getTarget().getRelocationModel();
21734 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21735 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21737 // Prepare IP either in reg or imm.
21738 if (!UseImmLabel) {
21739 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21740 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21741 LabelReg = MRI.createVirtualRegister(PtrRC);
21742 if (Subtarget->is64Bit()) {
21743 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21747 .addMBB(restoreMBB)
21750 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21751 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21752 .addReg(XII->getGlobalBaseReg(MF))
21755 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21759 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21761 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21762 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21763 if (i == X86::AddrDisp)
21764 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21766 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21769 MIB.addReg(LabelReg);
21771 MIB.addMBB(restoreMBB);
21772 MIB.setMemRefs(MMOBegin, MMOEnd);
21774 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21775 .addMBB(restoreMBB);
21777 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21778 MIB.addRegMask(RegInfo->getNoPreservedMask());
21779 thisMBB->addSuccessor(mainMBB);
21780 thisMBB->addSuccessor(restoreMBB);
21784 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21785 mainMBB->addSuccessor(sinkMBB);
21788 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21789 TII->get(X86::PHI), DstReg)
21790 .addReg(mainDstReg).addMBB(mainMBB)
21791 .addReg(restoreDstReg).addMBB(restoreMBB);
21794 if (RegInfo->hasBasePointer(*MF)) {
21795 const bool Uses64BitFramePtr =
21796 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21797 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21798 X86FI->setRestoreBasePointer(MF);
21799 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21800 unsigned BasePtr = RegInfo->getBaseRegister();
21801 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21802 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21803 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21804 .setMIFlag(MachineInstr::FrameSetup);
21806 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21807 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21808 restoreMBB->addSuccessor(sinkMBB);
21810 MI->eraseFromParent();
21814 MachineBasicBlock *
21815 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21816 MachineBasicBlock *MBB) const {
21817 DebugLoc DL = MI->getDebugLoc();
21818 MachineFunction *MF = MBB->getParent();
21819 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21820 MachineRegisterInfo &MRI = MF->getRegInfo();
21822 // Memory Reference
21823 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21824 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21826 MVT PVT = getPointerTy(MF->getDataLayout());
21827 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21828 "Invalid Pointer Size!");
21830 const TargetRegisterClass *RC =
21831 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21832 unsigned Tmp = MRI.createVirtualRegister(RC);
21833 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21834 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21835 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21836 unsigned SP = RegInfo->getStackRegister();
21838 MachineInstrBuilder MIB;
21840 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21841 const int64_t SPOffset = 2 * PVT.getStoreSize();
21843 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21844 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21847 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21848 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21849 MIB.addOperand(MI->getOperand(i));
21850 MIB.setMemRefs(MMOBegin, MMOEnd);
21852 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21853 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21854 if (i == X86::AddrDisp)
21855 MIB.addDisp(MI->getOperand(i), LabelOffset);
21857 MIB.addOperand(MI->getOperand(i));
21859 MIB.setMemRefs(MMOBegin, MMOEnd);
21861 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21862 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21863 if (i == X86::AddrDisp)
21864 MIB.addDisp(MI->getOperand(i), SPOffset);
21866 MIB.addOperand(MI->getOperand(i));
21868 MIB.setMemRefs(MMOBegin, MMOEnd);
21870 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21872 MI->eraseFromParent();
21876 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21877 // accumulator loops. Writing back to the accumulator allows the coalescer
21878 // to remove extra copies in the loop.
21879 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21880 MachineBasicBlock *
21881 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21882 MachineBasicBlock *MBB) const {
21883 MachineOperand &AddendOp = MI->getOperand(3);
21885 // Bail out early if the addend isn't a register - we can't switch these.
21886 if (!AddendOp.isReg())
21889 MachineFunction &MF = *MBB->getParent();
21890 MachineRegisterInfo &MRI = MF.getRegInfo();
21892 // Check whether the addend is defined by a PHI:
21893 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21894 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21895 if (!AddendDef.isPHI())
21898 // Look for the following pattern:
21900 // %addend = phi [%entry, 0], [%loop, %result]
21902 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21906 // %addend = phi [%entry, 0], [%loop, %result]
21908 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21910 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21911 assert(AddendDef.getOperand(i).isReg());
21912 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21913 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21914 if (&PHISrcInst == MI) {
21915 // Found a matching instruction.
21916 unsigned NewFMAOpc = 0;
21917 switch (MI->getOpcode()) {
21918 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21919 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21920 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21921 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21922 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21923 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21924 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21925 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21926 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21927 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21928 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21929 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21930 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21931 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21932 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21933 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21934 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21935 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21936 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21937 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21939 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21940 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21941 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21942 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21943 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21944 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21945 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21946 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21947 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21948 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21949 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21950 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21951 default: llvm_unreachable("Unrecognized FMA variant.");
21954 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21955 MachineInstrBuilder MIB =
21956 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21957 .addOperand(MI->getOperand(0))
21958 .addOperand(MI->getOperand(3))
21959 .addOperand(MI->getOperand(2))
21960 .addOperand(MI->getOperand(1));
21961 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21962 MI->eraseFromParent();
21969 MachineBasicBlock *
21970 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21971 MachineBasicBlock *BB) const {
21972 switch (MI->getOpcode()) {
21973 default: llvm_unreachable("Unexpected instr type to insert");
21974 case X86::TAILJMPd64:
21975 case X86::TAILJMPr64:
21976 case X86::TAILJMPm64:
21977 case X86::TAILJMPd64_REX:
21978 case X86::TAILJMPr64_REX:
21979 case X86::TAILJMPm64_REX:
21980 llvm_unreachable("TAILJMP64 would not be touched here.");
21981 case X86::TCRETURNdi64:
21982 case X86::TCRETURNri64:
21983 case X86::TCRETURNmi64:
21985 case X86::WIN_ALLOCA:
21986 return EmitLoweredWinAlloca(MI, BB);
21987 case X86::CATCHRET:
21988 return EmitLoweredCatchRet(MI, BB);
21989 case X86::CATCHPAD:
21990 return EmitLoweredCatchPad(MI, BB);
21991 case X86::SEG_ALLOCA_32:
21992 case X86::SEG_ALLOCA_64:
21993 return EmitLoweredSegAlloca(MI, BB);
21994 case X86::TLSCall_32:
21995 case X86::TLSCall_64:
21996 return EmitLoweredTLSCall(MI, BB);
21997 case X86::CMOV_FR32:
21998 case X86::CMOV_FR64:
21999 case X86::CMOV_GR8:
22000 case X86::CMOV_GR16:
22001 case X86::CMOV_GR32:
22002 case X86::CMOV_RFP32:
22003 case X86::CMOV_RFP64:
22004 case X86::CMOV_RFP80:
22005 case X86::CMOV_V2F64:
22006 case X86::CMOV_V2I64:
22007 case X86::CMOV_V4F32:
22008 case X86::CMOV_V4F64:
22009 case X86::CMOV_V4I64:
22010 case X86::CMOV_V16F32:
22011 case X86::CMOV_V8F32:
22012 case X86::CMOV_V8F64:
22013 case X86::CMOV_V8I64:
22014 case X86::CMOV_V8I1:
22015 case X86::CMOV_V16I1:
22016 case X86::CMOV_V32I1:
22017 case X86::CMOV_V64I1:
22018 return EmitLoweredSelect(MI, BB);
22020 case X86::RELEASE_FADD32mr:
22021 case X86::RELEASE_FADD64mr:
22022 return EmitLoweredAtomicFP(MI, BB);
22024 case X86::FP32_TO_INT16_IN_MEM:
22025 case X86::FP32_TO_INT32_IN_MEM:
22026 case X86::FP32_TO_INT64_IN_MEM:
22027 case X86::FP64_TO_INT16_IN_MEM:
22028 case X86::FP64_TO_INT32_IN_MEM:
22029 case X86::FP64_TO_INT64_IN_MEM:
22030 case X86::FP80_TO_INT16_IN_MEM:
22031 case X86::FP80_TO_INT32_IN_MEM:
22032 case X86::FP80_TO_INT64_IN_MEM: {
22033 MachineFunction *F = BB->getParent();
22034 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
22035 DebugLoc DL = MI->getDebugLoc();
22037 // Change the floating point control register to use "round towards zero"
22038 // mode when truncating to an integer value.
22039 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
22040 addFrameReference(BuildMI(*BB, MI, DL,
22041 TII->get(X86::FNSTCW16m)), CWFrameIdx);
22043 // Load the old value of the high byte of the control word...
22045 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
22046 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
22049 // Set the high part to be round to zero...
22050 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
22053 // Reload the modified control word now...
22054 addFrameReference(BuildMI(*BB, MI, DL,
22055 TII->get(X86::FLDCW16m)), CWFrameIdx);
22057 // Restore the memory image of control word to original value
22058 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
22061 // Get the X86 opcode to use.
22063 switch (MI->getOpcode()) {
22064 default: llvm_unreachable("illegal opcode!");
22065 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
22066 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
22067 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
22068 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
22069 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
22070 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
22071 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
22072 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
22073 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
22077 MachineOperand &Op = MI->getOperand(0);
22079 AM.BaseType = X86AddressMode::RegBase;
22080 AM.Base.Reg = Op.getReg();
22082 AM.BaseType = X86AddressMode::FrameIndexBase;
22083 AM.Base.FrameIndex = Op.getIndex();
22085 Op = MI->getOperand(1);
22087 AM.Scale = Op.getImm();
22088 Op = MI->getOperand(2);
22090 AM.IndexReg = Op.getImm();
22091 Op = MI->getOperand(3);
22092 if (Op.isGlobal()) {
22093 AM.GV = Op.getGlobal();
22095 AM.Disp = Op.getImm();
22097 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
22098 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
22100 // Reload the original control word now.
22101 addFrameReference(BuildMI(*BB, MI, DL,
22102 TII->get(X86::FLDCW16m)), CWFrameIdx);
22104 MI->eraseFromParent(); // The pseudo instruction is gone now.
22107 // String/text processing lowering.
22108 case X86::PCMPISTRM128REG:
22109 case X86::VPCMPISTRM128REG:
22110 case X86::PCMPISTRM128MEM:
22111 case X86::VPCMPISTRM128MEM:
22112 case X86::PCMPESTRM128REG:
22113 case X86::VPCMPESTRM128REG:
22114 case X86::PCMPESTRM128MEM:
22115 case X86::VPCMPESTRM128MEM:
22116 assert(Subtarget->hasSSE42() &&
22117 "Target must have SSE4.2 or AVX features enabled");
22118 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
22120 // String/text processing lowering.
22121 case X86::PCMPISTRIREG:
22122 case X86::VPCMPISTRIREG:
22123 case X86::PCMPISTRIMEM:
22124 case X86::VPCMPISTRIMEM:
22125 case X86::PCMPESTRIREG:
22126 case X86::VPCMPESTRIREG:
22127 case X86::PCMPESTRIMEM:
22128 case X86::VPCMPESTRIMEM:
22129 assert(Subtarget->hasSSE42() &&
22130 "Target must have SSE4.2 or AVX features enabled");
22131 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
22133 // Thread synchronization.
22135 return EmitMonitor(MI, BB, Subtarget);
22139 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
22141 case X86::VASTART_SAVE_XMM_REGS:
22142 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
22144 case X86::VAARG_64:
22145 return EmitVAARG64WithCustomInserter(MI, BB);
22147 case X86::EH_SjLj_SetJmp32:
22148 case X86::EH_SjLj_SetJmp64:
22149 return emitEHSjLjSetJmp(MI, BB);
22151 case X86::EH_SjLj_LongJmp32:
22152 case X86::EH_SjLj_LongJmp64:
22153 return emitEHSjLjLongJmp(MI, BB);
22155 case TargetOpcode::STATEPOINT:
22156 // As an implementation detail, STATEPOINT shares the STACKMAP format at
22157 // this point in the process. We diverge later.
22158 return emitPatchPoint(MI, BB);
22160 case TargetOpcode::STACKMAP:
22161 case TargetOpcode::PATCHPOINT:
22162 return emitPatchPoint(MI, BB);
22164 case X86::VFMADDPDr213r:
22165 case X86::VFMADDPSr213r:
22166 case X86::VFMADDSDr213r:
22167 case X86::VFMADDSSr213r:
22168 case X86::VFMSUBPDr213r:
22169 case X86::VFMSUBPSr213r:
22170 case X86::VFMSUBSDr213r:
22171 case X86::VFMSUBSSr213r:
22172 case X86::VFNMADDPDr213r:
22173 case X86::VFNMADDPSr213r:
22174 case X86::VFNMADDSDr213r:
22175 case X86::VFNMADDSSr213r:
22176 case X86::VFNMSUBPDr213r:
22177 case X86::VFNMSUBPSr213r:
22178 case X86::VFNMSUBSDr213r:
22179 case X86::VFNMSUBSSr213r:
22180 case X86::VFMADDSUBPDr213r:
22181 case X86::VFMADDSUBPSr213r:
22182 case X86::VFMSUBADDPDr213r:
22183 case X86::VFMSUBADDPSr213r:
22184 case X86::VFMADDPDr213rY:
22185 case X86::VFMADDPSr213rY:
22186 case X86::VFMSUBPDr213rY:
22187 case X86::VFMSUBPSr213rY:
22188 case X86::VFNMADDPDr213rY:
22189 case X86::VFNMADDPSr213rY:
22190 case X86::VFNMSUBPDr213rY:
22191 case X86::VFNMSUBPSr213rY:
22192 case X86::VFMADDSUBPDr213rY:
22193 case X86::VFMADDSUBPSr213rY:
22194 case X86::VFMSUBADDPDr213rY:
22195 case X86::VFMSUBADDPSr213rY:
22196 return emitFMA3Instr(MI, BB);
22200 //===----------------------------------------------------------------------===//
22201 // X86 Optimization Hooks
22202 //===----------------------------------------------------------------------===//
22204 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
22207 const SelectionDAG &DAG,
22208 unsigned Depth) const {
22209 unsigned BitWidth = KnownZero.getBitWidth();
22210 unsigned Opc = Op.getOpcode();
22211 assert((Opc >= ISD::BUILTIN_OP_END ||
22212 Opc == ISD::INTRINSIC_WO_CHAIN ||
22213 Opc == ISD::INTRINSIC_W_CHAIN ||
22214 Opc == ISD::INTRINSIC_VOID) &&
22215 "Should use MaskedValueIsZero if you don't know whether Op"
22216 " is a target node!");
22218 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22232 // These nodes' second result is a boolean.
22233 if (Op.getResNo() == 0)
22236 case X86ISD::SETCC:
22237 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22239 case ISD::INTRINSIC_WO_CHAIN: {
22240 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22241 unsigned NumLoBits = 0;
22244 case Intrinsic::x86_sse_movmsk_ps:
22245 case Intrinsic::x86_avx_movmsk_ps_256:
22246 case Intrinsic::x86_sse2_movmsk_pd:
22247 case Intrinsic::x86_avx_movmsk_pd_256:
22248 case Intrinsic::x86_mmx_pmovmskb:
22249 case Intrinsic::x86_sse2_pmovmskb_128:
22250 case Intrinsic::x86_avx2_pmovmskb: {
22251 // High bits of movmskp{s|d}, pmovmskb are known zero.
22253 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22254 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22255 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22256 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22257 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22258 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22259 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22260 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22262 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22271 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22273 const SelectionDAG &,
22274 unsigned Depth) const {
22275 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22276 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22277 return Op.getValueType().getScalarSizeInBits();
22283 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22284 /// node is a GlobalAddress + offset.
22285 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22286 const GlobalValue* &GA,
22287 int64_t &Offset) const {
22288 if (N->getOpcode() == X86ISD::Wrapper) {
22289 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22290 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22291 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22295 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22298 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22299 /// same as extracting the high 128-bit part of 256-bit vector and then
22300 /// inserting the result into the low part of a new 256-bit vector
22301 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22302 EVT VT = SVOp->getValueType(0);
22303 unsigned NumElems = VT.getVectorNumElements();
22305 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22306 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22307 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22308 SVOp->getMaskElt(j) >= 0)
22314 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22315 /// same as extracting the low 128-bit part of 256-bit vector and then
22316 /// inserting the result into the high part of a new 256-bit vector
22317 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22318 EVT VT = SVOp->getValueType(0);
22319 unsigned NumElems = VT.getVectorNumElements();
22321 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22322 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22323 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22324 SVOp->getMaskElt(j) >= 0)
22330 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22331 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22332 TargetLowering::DAGCombinerInfo &DCI,
22333 const X86Subtarget* Subtarget) {
22335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22336 SDValue V1 = SVOp->getOperand(0);
22337 SDValue V2 = SVOp->getOperand(1);
22338 EVT VT = SVOp->getValueType(0);
22339 unsigned NumElems = VT.getVectorNumElements();
22341 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22342 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22346 // V UNDEF BUILD_VECTOR UNDEF
22348 // CONCAT_VECTOR CONCAT_VECTOR
22351 // RESULT: V + zero extended
22353 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22354 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22355 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22358 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22361 // To match the shuffle mask, the first half of the mask should
22362 // be exactly the first vector, and all the rest a splat with the
22363 // first element of the second one.
22364 for (unsigned i = 0; i != NumElems/2; ++i)
22365 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22366 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22369 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22370 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22371 if (Ld->hasNUsesOfValue(1, 0)) {
22372 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22373 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22375 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22377 Ld->getPointerInfo(),
22378 Ld->getAlignment(),
22379 false/*isVolatile*/, true/*ReadMem*/,
22380 false/*WriteMem*/);
22382 // Make sure the newly-created LOAD is in the same position as Ld in
22383 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22384 // and update uses of Ld's output chain to use the TokenFactor.
22385 if (Ld->hasAnyUseOfValue(1)) {
22386 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22387 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22388 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22389 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22390 SDValue(ResNode.getNode(), 1));
22393 return DAG.getBitcast(VT, ResNode);
22397 // Emit a zeroed vector and insert the desired subvector on its
22399 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22400 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22401 return DCI.CombineTo(N, InsV);
22404 //===--------------------------------------------------------------------===//
22405 // Combine some shuffles into subvector extracts and inserts:
22408 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22409 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22410 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22411 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22412 return DCI.CombineTo(N, InsV);
22415 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22416 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22417 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22418 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22419 return DCI.CombineTo(N, InsV);
22425 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22428 /// This is the leaf of the recursive combinine below. When we have found some
22429 /// chain of single-use x86 shuffle instructions and accumulated the combined
22430 /// shuffle mask represented by them, this will try to pattern match that mask
22431 /// into either a single instruction if there is a special purpose instruction
22432 /// for this operation, or into a PSHUFB instruction which is a fully general
22433 /// instruction but should only be used to replace chains over a certain depth.
22434 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22435 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22436 TargetLowering::DAGCombinerInfo &DCI,
22437 const X86Subtarget *Subtarget) {
22438 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22440 // Find the operand that enters the chain. Note that multiple uses are OK
22441 // here, we're not going to remove the operand we find.
22442 SDValue Input = Op.getOperand(0);
22443 while (Input.getOpcode() == ISD::BITCAST)
22444 Input = Input.getOperand(0);
22446 MVT VT = Input.getSimpleValueType();
22447 MVT RootVT = Root.getSimpleValueType();
22450 if (Mask.size() == 1) {
22451 int Index = Mask[0];
22452 assert((Index >= 0 || Index == SM_SentinelUndef ||
22453 Index == SM_SentinelZero) &&
22454 "Invalid shuffle index found!");
22456 // We may end up with an accumulated mask of size 1 as a result of
22457 // widening of shuffle operands (see function canWidenShuffleElements).
22458 // If the only shuffle index is equal to SM_SentinelZero then propagate
22459 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22460 // mask, and therefore the entire chain of shuffles can be folded away.
22461 if (Index == SM_SentinelZero)
22462 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22464 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22469 // Use the float domain if the operand type is a floating point type.
22470 bool FloatDomain = VT.isFloatingPoint();
22472 // For floating point shuffles, we don't have free copies in the shuffle
22473 // instructions or the ability to load as part of the instruction, so
22474 // canonicalize their shuffles to UNPCK or MOV variants.
22476 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22477 // vectors because it can have a load folded into it that UNPCK cannot. This
22478 // doesn't preclude something switching to the shorter encoding post-RA.
22480 // FIXME: Should teach these routines about AVX vector widths.
22481 if (FloatDomain && VT.is128BitVector()) {
22482 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22483 bool Lo = Mask.equals({0, 0});
22486 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22487 // is no slower than UNPCKLPD but has the option to fold the input operand
22488 // into even an unaligned memory load.
22489 if (Lo && Subtarget->hasSSE3()) {
22490 Shuffle = X86ISD::MOVDDUP;
22491 ShuffleVT = MVT::v2f64;
22493 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22494 // than the UNPCK variants.
22495 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22496 ShuffleVT = MVT::v4f32;
22498 if (Depth == 1 && Root->getOpcode() == Shuffle)
22499 return false; // Nothing to do!
22500 Op = DAG.getBitcast(ShuffleVT, Input);
22501 DCI.AddToWorklist(Op.getNode());
22502 if (Shuffle == X86ISD::MOVDDUP)
22503 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22505 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22506 DCI.AddToWorklist(Op.getNode());
22507 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22511 if (Subtarget->hasSSE3() &&
22512 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22513 bool Lo = Mask.equals({0, 0, 2, 2});
22514 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22515 MVT ShuffleVT = MVT::v4f32;
22516 if (Depth == 1 && Root->getOpcode() == Shuffle)
22517 return false; // Nothing to do!
22518 Op = DAG.getBitcast(ShuffleVT, Input);
22519 DCI.AddToWorklist(Op.getNode());
22520 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22521 DCI.AddToWorklist(Op.getNode());
22522 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22526 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22527 bool Lo = Mask.equals({0, 0, 1, 1});
22528 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22529 MVT ShuffleVT = MVT::v4f32;
22530 if (Depth == 1 && Root->getOpcode() == Shuffle)
22531 return false; // Nothing to do!
22532 Op = DAG.getBitcast(ShuffleVT, Input);
22533 DCI.AddToWorklist(Op.getNode());
22534 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22535 DCI.AddToWorklist(Op.getNode());
22536 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22542 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22543 // variants as none of these have single-instruction variants that are
22544 // superior to the UNPCK formulation.
22545 if (!FloatDomain && VT.is128BitVector() &&
22546 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22547 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22548 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22550 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22551 bool Lo = Mask[0] == 0;
22552 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22553 if (Depth == 1 && Root->getOpcode() == Shuffle)
22554 return false; // Nothing to do!
22556 switch (Mask.size()) {
22558 ShuffleVT = MVT::v8i16;
22561 ShuffleVT = MVT::v16i8;
22564 llvm_unreachable("Impossible mask size!");
22566 Op = DAG.getBitcast(ShuffleVT, Input);
22567 DCI.AddToWorklist(Op.getNode());
22568 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22569 DCI.AddToWorklist(Op.getNode());
22570 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22575 // Don't try to re-form single instruction chains under any circumstances now
22576 // that we've done encoding canonicalization for them.
22580 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22581 // can replace them with a single PSHUFB instruction profitably. Intel's
22582 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22583 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22584 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22585 SmallVector<SDValue, 16> PSHUFBMask;
22586 int NumBytes = VT.getSizeInBits() / 8;
22587 int Ratio = NumBytes / Mask.size();
22588 for (int i = 0; i < NumBytes; ++i) {
22589 if (Mask[i / Ratio] == SM_SentinelUndef) {
22590 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22593 int M = Mask[i / Ratio] != SM_SentinelZero
22594 ? Ratio * Mask[i / Ratio] + i % Ratio
22596 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22598 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22599 Op = DAG.getBitcast(ByteVT, Input);
22600 DCI.AddToWorklist(Op.getNode());
22601 SDValue PSHUFBMaskOp =
22602 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22603 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22604 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22605 DCI.AddToWorklist(Op.getNode());
22606 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22611 // Failed to find any combines.
22615 /// \brief Fully generic combining of x86 shuffle instructions.
22617 /// This should be the last combine run over the x86 shuffle instructions. Once
22618 /// they have been fully optimized, this will recursively consider all chains
22619 /// of single-use shuffle instructions, build a generic model of the cumulative
22620 /// shuffle operation, and check for simpler instructions which implement this
22621 /// operation. We use this primarily for two purposes:
22623 /// 1) Collapse generic shuffles to specialized single instructions when
22624 /// equivalent. In most cases, this is just an encoding size win, but
22625 /// sometimes we will collapse multiple generic shuffles into a single
22626 /// special-purpose shuffle.
22627 /// 2) Look for sequences of shuffle instructions with 3 or more total
22628 /// instructions, and replace them with the slightly more expensive SSSE3
22629 /// PSHUFB instruction if available. We do this as the last combining step
22630 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22631 /// a suitable short sequence of other instructions. The PHUFB will either
22632 /// use a register or have to read from memory and so is slightly (but only
22633 /// slightly) more expensive than the other shuffle instructions.
22635 /// Because this is inherently a quadratic operation (for each shuffle in
22636 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22637 /// This should never be an issue in practice as the shuffle lowering doesn't
22638 /// produce sequences of more than 8 instructions.
22640 /// FIXME: We will currently miss some cases where the redundant shuffling
22641 /// would simplify under the threshold for PSHUFB formation because of
22642 /// combine-ordering. To fix this, we should do the redundant instruction
22643 /// combining in this recursive walk.
22644 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22645 ArrayRef<int> RootMask,
22646 int Depth, bool HasPSHUFB,
22648 TargetLowering::DAGCombinerInfo &DCI,
22649 const X86Subtarget *Subtarget) {
22650 // Bound the depth of our recursive combine because this is ultimately
22651 // quadratic in nature.
22655 // Directly rip through bitcasts to find the underlying operand.
22656 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22657 Op = Op.getOperand(0);
22659 MVT VT = Op.getSimpleValueType();
22660 if (!VT.isVector())
22661 return false; // Bail if we hit a non-vector.
22663 assert(Root.getSimpleValueType().isVector() &&
22664 "Shuffles operate on vector types!");
22665 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22666 "Can only combine shuffles of the same vector register size.");
22668 if (!isTargetShuffle(Op.getOpcode()))
22670 SmallVector<int, 16> OpMask;
22672 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22673 // We only can combine unary shuffles which we can decode the mask for.
22674 if (!HaveMask || !IsUnary)
22677 assert(VT.getVectorNumElements() == OpMask.size() &&
22678 "Different mask size from vector size!");
22679 assert(((RootMask.size() > OpMask.size() &&
22680 RootMask.size() % OpMask.size() == 0) ||
22681 (OpMask.size() > RootMask.size() &&
22682 OpMask.size() % RootMask.size() == 0) ||
22683 OpMask.size() == RootMask.size()) &&
22684 "The smaller number of elements must divide the larger.");
22685 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22686 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22687 assert(((RootRatio == 1 && OpRatio == 1) ||
22688 (RootRatio == 1) != (OpRatio == 1)) &&
22689 "Must not have a ratio for both incoming and op masks!");
22691 SmallVector<int, 16> Mask;
22692 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22694 // Merge this shuffle operation's mask into our accumulated mask. Note that
22695 // this shuffle's mask will be the first applied to the input, followed by the
22696 // root mask to get us all the way to the root value arrangement. The reason
22697 // for this order is that we are recursing up the operation chain.
22698 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22699 int RootIdx = i / RootRatio;
22700 if (RootMask[RootIdx] < 0) {
22701 // This is a zero or undef lane, we're done.
22702 Mask.push_back(RootMask[RootIdx]);
22706 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22707 int OpIdx = RootMaskedIdx / OpRatio;
22708 if (OpMask[OpIdx] < 0) {
22709 // The incoming lanes are zero or undef, it doesn't matter which ones we
22711 Mask.push_back(OpMask[OpIdx]);
22715 // Ok, we have non-zero lanes, map them through.
22716 Mask.push_back(OpMask[OpIdx] * OpRatio +
22717 RootMaskedIdx % OpRatio);
22720 // See if we can recurse into the operand to combine more things.
22721 switch (Op.getOpcode()) {
22722 case X86ISD::PSHUFB:
22724 case X86ISD::PSHUFD:
22725 case X86ISD::PSHUFHW:
22726 case X86ISD::PSHUFLW:
22727 if (Op.getOperand(0).hasOneUse() &&
22728 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22729 HasPSHUFB, DAG, DCI, Subtarget))
22733 case X86ISD::UNPCKL:
22734 case X86ISD::UNPCKH:
22735 assert(Op.getOperand(0) == Op.getOperand(1) &&
22736 "We only combine unary shuffles!");
22737 // We can't check for single use, we have to check that this shuffle is the
22739 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22740 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22741 HasPSHUFB, DAG, DCI, Subtarget))
22746 // Minor canonicalization of the accumulated shuffle mask to make it easier
22747 // to match below. All this does is detect masks with squential pairs of
22748 // elements, and shrink them to the half-width mask. It does this in a loop
22749 // so it will reduce the size of the mask to the minimal width mask which
22750 // performs an equivalent shuffle.
22751 SmallVector<int, 16> WidenedMask;
22752 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22753 Mask = std::move(WidenedMask);
22754 WidenedMask.clear();
22757 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22761 /// \brief Get the PSHUF-style mask from PSHUF node.
22763 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22764 /// PSHUF-style masks that can be reused with such instructions.
22765 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22766 MVT VT = N.getSimpleValueType();
22767 SmallVector<int, 4> Mask;
22769 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22773 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22774 // matter. Check that the upper masks are repeats and remove them.
22775 if (VT.getSizeInBits() > 128) {
22776 int LaneElts = 128 / VT.getScalarSizeInBits();
22778 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22779 for (int j = 0; j < LaneElts; ++j)
22780 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22781 "Mask doesn't repeat in high 128-bit lanes!");
22783 Mask.resize(LaneElts);
22786 switch (N.getOpcode()) {
22787 case X86ISD::PSHUFD:
22789 case X86ISD::PSHUFLW:
22792 case X86ISD::PSHUFHW:
22793 Mask.erase(Mask.begin(), Mask.begin() + 4);
22794 for (int &M : Mask)
22798 llvm_unreachable("No valid shuffle instruction found!");
22802 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22804 /// We walk up the chain and look for a combinable shuffle, skipping over
22805 /// shuffles that we could hoist this shuffle's transformation past without
22806 /// altering anything.
22808 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22810 TargetLowering::DAGCombinerInfo &DCI) {
22811 assert(N.getOpcode() == X86ISD::PSHUFD &&
22812 "Called with something other than an x86 128-bit half shuffle!");
22815 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22816 // of the shuffles in the chain so that we can form a fresh chain to replace
22818 SmallVector<SDValue, 8> Chain;
22819 SDValue V = N.getOperand(0);
22820 for (; V.hasOneUse(); V = V.getOperand(0)) {
22821 switch (V.getOpcode()) {
22823 return SDValue(); // Nothing combined!
22826 // Skip bitcasts as we always know the type for the target specific
22830 case X86ISD::PSHUFD:
22831 // Found another dword shuffle.
22834 case X86ISD::PSHUFLW:
22835 // Check that the low words (being shuffled) are the identity in the
22836 // dword shuffle, and the high words are self-contained.
22837 if (Mask[0] != 0 || Mask[1] != 1 ||
22838 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22841 Chain.push_back(V);
22844 case X86ISD::PSHUFHW:
22845 // Check that the high words (being shuffled) are the identity in the
22846 // dword shuffle, and the low words are self-contained.
22847 if (Mask[2] != 2 || Mask[3] != 3 ||
22848 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22851 Chain.push_back(V);
22854 case X86ISD::UNPCKL:
22855 case X86ISD::UNPCKH:
22856 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22857 // shuffle into a preceding word shuffle.
22858 if (V.getSimpleValueType().getVectorElementType() != MVT::i8 &&
22859 V.getSimpleValueType().getVectorElementType() != MVT::i16)
22862 // Search for a half-shuffle which we can combine with.
22863 unsigned CombineOp =
22864 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22865 if (V.getOperand(0) != V.getOperand(1) ||
22866 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22868 Chain.push_back(V);
22869 V = V.getOperand(0);
22871 switch (V.getOpcode()) {
22873 return SDValue(); // Nothing to combine.
22875 case X86ISD::PSHUFLW:
22876 case X86ISD::PSHUFHW:
22877 if (V.getOpcode() == CombineOp)
22880 Chain.push_back(V);
22884 V = V.getOperand(0);
22888 } while (V.hasOneUse());
22891 // Break out of the loop if we break out of the switch.
22895 if (!V.hasOneUse())
22896 // We fell out of the loop without finding a viable combining instruction.
22899 // Merge this node's mask and our incoming mask.
22900 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22901 for (int &M : Mask)
22903 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22904 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22906 // Rebuild the chain around this new shuffle.
22907 while (!Chain.empty()) {
22908 SDValue W = Chain.pop_back_val();
22910 if (V.getValueType() != W.getOperand(0).getValueType())
22911 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22913 switch (W.getOpcode()) {
22915 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22917 case X86ISD::UNPCKL:
22918 case X86ISD::UNPCKH:
22919 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22922 case X86ISD::PSHUFD:
22923 case X86ISD::PSHUFLW:
22924 case X86ISD::PSHUFHW:
22925 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22929 if (V.getValueType() != N.getValueType())
22930 V = DAG.getBitcast(N.getValueType(), V);
22932 // Return the new chain to replace N.
22936 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22939 /// We walk up the chain, skipping shuffles of the other half and looking
22940 /// through shuffles which switch halves trying to find a shuffle of the same
22941 /// pair of dwords.
22942 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22944 TargetLowering::DAGCombinerInfo &DCI) {
22946 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22947 "Called with something other than an x86 128-bit half shuffle!");
22949 unsigned CombineOpcode = N.getOpcode();
22951 // Walk up a single-use chain looking for a combinable shuffle.
22952 SDValue V = N.getOperand(0);
22953 for (; V.hasOneUse(); V = V.getOperand(0)) {
22954 switch (V.getOpcode()) {
22956 return false; // Nothing combined!
22959 // Skip bitcasts as we always know the type for the target specific
22963 case X86ISD::PSHUFLW:
22964 case X86ISD::PSHUFHW:
22965 if (V.getOpcode() == CombineOpcode)
22968 // Other-half shuffles are no-ops.
22971 // Break out of the loop if we break out of the switch.
22975 if (!V.hasOneUse())
22976 // We fell out of the loop without finding a viable combining instruction.
22979 // Combine away the bottom node as its shuffle will be accumulated into
22980 // a preceding shuffle.
22981 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22983 // Record the old value.
22986 // Merge this node's mask and our incoming mask (adjusted to account for all
22987 // the pshufd instructions encountered).
22988 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22989 for (int &M : Mask)
22991 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22992 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22994 // Check that the shuffles didn't cancel each other out. If not, we need to
22995 // combine to the new one.
22997 // Replace the combinable shuffle with the combined one, updating all users
22998 // so that we re-evaluate the chain here.
22999 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
23004 /// \brief Try to combine x86 target specific shuffles.
23005 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
23006 TargetLowering::DAGCombinerInfo &DCI,
23007 const X86Subtarget *Subtarget) {
23009 MVT VT = N.getSimpleValueType();
23010 SmallVector<int, 4> Mask;
23012 switch (N.getOpcode()) {
23013 case X86ISD::PSHUFD:
23014 case X86ISD::PSHUFLW:
23015 case X86ISD::PSHUFHW:
23016 Mask = getPSHUFShuffleMask(N);
23017 assert(Mask.size() == 4);
23019 case X86ISD::UNPCKL: {
23020 // Combine X86ISD::UNPCKL and ISD::VECTOR_SHUFFLE into X86ISD::UNPCKH, in
23021 // which X86ISD::UNPCKL has a ISD::UNDEF operand, and ISD::VECTOR_SHUFFLE
23022 // moves upper half elements into the lower half part. For example:
23024 // t2: v16i8 = vector_shuffle<8,9,10,11,12,13,14,15,u,u,u,u,u,u,u,u> t1,
23026 // t3: v16i8 = X86ISD::UNPCKL undef:v16i8, t2
23028 // will be combined to:
23030 // t3: v16i8 = X86ISD::UNPCKH undef:v16i8, t1
23032 // This is only for 128-bit vectors. From SSE4.1 onward this combine may not
23033 // happen due to advanced instructions.
23034 if (!VT.is128BitVector())
23037 auto Op0 = N.getOperand(0);
23038 auto Op1 = N.getOperand(1);
23039 if (Op0.getOpcode() == ISD::UNDEF &&
23040 Op1.getNode()->getOpcode() == ISD::VECTOR_SHUFFLE) {
23041 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op1.getNode())->getMask();
23043 unsigned NumElts = VT.getVectorNumElements();
23044 SmallVector<int, 8> ExpectedMask(NumElts, -1);
23045 std::iota(ExpectedMask.begin(), ExpectedMask.begin() + NumElts / 2,
23048 auto ShufOp = Op1.getOperand(0);
23049 if (isShuffleEquivalent(Op1, ShufOp, Mask, ExpectedMask))
23050 return DAG.getNode(X86ISD::UNPCKH, DL, VT, N.getOperand(0), ShufOp);
23058 // Nuke no-op shuffles that show up after combining.
23059 if (isNoopShuffleMask(Mask))
23060 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
23062 // Look for simplifications involving one or two shuffle instructions.
23063 SDValue V = N.getOperand(0);
23064 switch (N.getOpcode()) {
23067 case X86ISD::PSHUFLW:
23068 case X86ISD::PSHUFHW:
23069 assert(VT.getVectorElementType() == MVT::i16 && "Bad word shuffle type!");
23071 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
23072 return SDValue(); // We combined away this shuffle, so we're done.
23074 // See if this reduces to a PSHUFD which is no more expensive and can
23075 // combine with more operations. Note that it has to at least flip the
23076 // dwords as otherwise it would have been removed as a no-op.
23077 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
23078 int DMask[] = {0, 1, 2, 3};
23079 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
23080 DMask[DOffset + 0] = DOffset + 1;
23081 DMask[DOffset + 1] = DOffset + 0;
23082 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
23083 V = DAG.getBitcast(DVT, V);
23084 DCI.AddToWorklist(V.getNode());
23085 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
23086 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
23087 DCI.AddToWorklist(V.getNode());
23088 return DAG.getBitcast(VT, V);
23091 // Look for shuffle patterns which can be implemented as a single unpack.
23092 // FIXME: This doesn't handle the location of the PSHUFD generically, and
23093 // only works when we have a PSHUFD followed by two half-shuffles.
23094 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
23095 (V.getOpcode() == X86ISD::PSHUFLW ||
23096 V.getOpcode() == X86ISD::PSHUFHW) &&
23097 V.getOpcode() != N.getOpcode() &&
23099 SDValue D = V.getOperand(0);
23100 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
23101 D = D.getOperand(0);
23102 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
23103 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
23104 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
23105 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23106 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
23108 for (int i = 0; i < 4; ++i) {
23109 WordMask[i + NOffset] = Mask[i] + NOffset;
23110 WordMask[i + VOffset] = VMask[i] + VOffset;
23112 // Map the word mask through the DWord mask.
23114 for (int i = 0; i < 8; ++i)
23115 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
23116 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
23117 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
23118 // We can replace all three shuffles with an unpack.
23119 V = DAG.getBitcast(VT, D.getOperand(0));
23120 DCI.AddToWorklist(V.getNode());
23121 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
23130 case X86ISD::PSHUFD:
23131 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
23140 /// \brief Try to combine a shuffle into a target-specific add-sub node.
23142 /// We combine this directly on the abstract vector shuffle nodes so it is
23143 /// easier to generically match. We also insert dummy vector shuffle nodes for
23144 /// the operands which explicitly discard the lanes which are unused by this
23145 /// operation to try to flow through the rest of the combiner the fact that
23146 /// they're unused.
23147 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
23149 EVT VT = N->getValueType(0);
23151 // We only handle target-independent shuffles.
23152 // FIXME: It would be easy and harmless to use the target shuffle mask
23153 // extraction tool to support more.
23154 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
23157 auto *SVN = cast<ShuffleVectorSDNode>(N);
23158 ArrayRef<int> Mask = SVN->getMask();
23159 SDValue V1 = N->getOperand(0);
23160 SDValue V2 = N->getOperand(1);
23162 // We require the first shuffle operand to be the SUB node, and the second to
23163 // be the ADD node.
23164 // FIXME: We should support the commuted patterns.
23165 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
23168 // If there are other uses of these operations we can't fold them.
23169 if (!V1->hasOneUse() || !V2->hasOneUse())
23172 // Ensure that both operations have the same operands. Note that we can
23173 // commute the FADD operands.
23174 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
23175 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
23176 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
23179 // We're looking for blends between FADD and FSUB nodes. We insist on these
23180 // nodes being lined up in a specific expected pattern.
23181 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
23182 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
23183 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
23186 // Only specific types are legal at this point, assert so we notice if and
23187 // when these change.
23188 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
23189 VT == MVT::v4f64) &&
23190 "Unknown vector type encountered!");
23192 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
23195 /// PerformShuffleCombine - Performs several different shuffle combines.
23196 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
23197 TargetLowering::DAGCombinerInfo &DCI,
23198 const X86Subtarget *Subtarget) {
23200 SDValue N0 = N->getOperand(0);
23201 SDValue N1 = N->getOperand(1);
23202 EVT VT = N->getValueType(0);
23204 // Don't create instructions with illegal types after legalize types has run.
23205 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23206 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
23209 // If we have legalized the vector types, look for blends of FADD and FSUB
23210 // nodes that we can fuse into an ADDSUB node.
23211 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
23212 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
23215 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
23216 if (Subtarget->hasFp256() && VT.is256BitVector() &&
23217 N->getOpcode() == ISD::VECTOR_SHUFFLE)
23218 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
23220 // During Type Legalization, when promoting illegal vector types,
23221 // the backend might introduce new shuffle dag nodes and bitcasts.
23223 // This code performs the following transformation:
23224 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
23225 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
23227 // We do this only if both the bitcast and the BINOP dag nodes have
23228 // one use. Also, perform this transformation only if the new binary
23229 // operation is legal. This is to avoid introducing dag nodes that
23230 // potentially need to be further expanded (or custom lowered) into a
23231 // less optimal sequence of dag nodes.
23232 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
23233 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
23234 N0.getOpcode() == ISD::BITCAST) {
23235 SDValue BC0 = N0.getOperand(0);
23236 EVT SVT = BC0.getValueType();
23237 unsigned Opcode = BC0.getOpcode();
23238 unsigned NumElts = VT.getVectorNumElements();
23240 if (BC0.hasOneUse() && SVT.isVector() &&
23241 SVT.getVectorNumElements() * 2 == NumElts &&
23242 TLI.isOperationLegal(Opcode, VT)) {
23243 bool CanFold = false;
23255 unsigned SVTNumElts = SVT.getVectorNumElements();
23256 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
23257 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
23258 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
23259 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
23260 CanFold = SVOp->getMaskElt(i) < 0;
23263 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
23264 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23265 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23266 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23271 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23272 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23273 // consecutive, non-overlapping, and in the right order.
23274 SmallVector<SDValue, 16> Elts;
23275 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23276 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23278 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23281 if (isTargetShuffle(N->getOpcode())) {
23283 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23284 if (Shuffle.getNode())
23287 // Try recursively combining arbitrary sequences of x86 shuffle
23288 // instructions into higher-order shuffles. We do this after combining
23289 // specific PSHUF instruction sequences into their minimal form so that we
23290 // can evaluate how many specialized shuffle instructions are involved in
23291 // a particular chain.
23292 SmallVector<int, 1> NonceMask; // Just a placeholder.
23293 NonceMask.push_back(0);
23294 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23295 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23297 return SDValue(); // This routine will use CombineTo to replace N.
23303 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23304 /// specific shuffle of a load can be folded into a single element load.
23305 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23306 /// shuffles have been custom lowered so we need to handle those here.
23307 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23308 TargetLowering::DAGCombinerInfo &DCI) {
23309 if (DCI.isBeforeLegalizeOps())
23312 SDValue InVec = N->getOperand(0);
23313 SDValue EltNo = N->getOperand(1);
23315 if (!isa<ConstantSDNode>(EltNo))
23318 EVT OriginalVT = InVec.getValueType();
23320 if (InVec.getOpcode() == ISD::BITCAST) {
23321 // Don't duplicate a load with other uses.
23322 if (!InVec.hasOneUse())
23324 EVT BCVT = InVec.getOperand(0).getValueType();
23325 if (!BCVT.isVector() ||
23326 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23328 InVec = InVec.getOperand(0);
23331 EVT CurrentVT = InVec.getValueType();
23333 if (!isTargetShuffle(InVec.getOpcode()))
23336 // Don't duplicate a load with other uses.
23337 if (!InVec.hasOneUse())
23340 SmallVector<int, 16> ShuffleMask;
23342 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23343 ShuffleMask, UnaryShuffle))
23346 // Select the input vector, guarding against out of range extract vector.
23347 unsigned NumElems = CurrentVT.getVectorNumElements();
23348 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23349 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23350 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23351 : InVec.getOperand(1);
23353 // If inputs to shuffle are the same for both ops, then allow 2 uses
23354 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23355 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23357 if (LdNode.getOpcode() == ISD::BITCAST) {
23358 // Don't duplicate a load with other uses.
23359 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23362 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23363 LdNode = LdNode.getOperand(0);
23366 if (!ISD::isNormalLoad(LdNode.getNode()))
23369 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23371 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23374 EVT EltVT = N->getValueType(0);
23375 // If there's a bitcast before the shuffle, check if the load type and
23376 // alignment is valid.
23377 unsigned Align = LN0->getAlignment();
23378 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23379 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23380 EltVT.getTypeForEVT(*DAG.getContext()));
23382 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23385 // All checks match so transform back to vector_shuffle so that DAG combiner
23386 // can finish the job
23389 // Create shuffle node taking into account the case that its a unary shuffle
23390 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23391 : InVec.getOperand(1);
23392 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23393 InVec.getOperand(0), Shuffle,
23395 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23396 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23400 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG,
23401 const X86Subtarget *Subtarget) {
23402 SDValue N0 = N->getOperand(0);
23403 EVT VT = N->getValueType(0);
23405 // Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23406 // special and don't usually play with other vector types, it's better to
23407 // handle them early to be sure we emit efficient code by avoiding
23408 // store-load conversions.
23409 if (VT == MVT::x86mmx && N0.getOpcode() == ISD::BUILD_VECTOR &&
23410 N0.getValueType() == MVT::v2i32 &&
23411 isa<ConstantSDNode>(N0.getOperand(1))) {
23412 SDValue N00 = N0->getOperand(0);
23413 if (N0.getConstantOperandVal(1) == 0 && N00.getValueType() == MVT::i32)
23414 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(N00), VT, N00);
23417 // Convert a bitcasted integer logic operation that has one bitcasted
23418 // floating-point operand and one constant operand into a floating-point
23419 // logic operation. This may create a load of the constant, but that is
23420 // cheaper than materializing the constant in an integer register and
23421 // transferring it to an SSE register or transferring the SSE operand to
23422 // integer register and back.
23424 switch (N0.getOpcode()) {
23425 case ISD::AND: FPOpcode = X86ISD::FAND; break;
23426 case ISD::OR: FPOpcode = X86ISD::FOR; break;
23427 case ISD::XOR: FPOpcode = X86ISD::FXOR; break;
23428 default: return SDValue();
23430 if (((Subtarget->hasSSE1() && VT == MVT::f32) ||
23431 (Subtarget->hasSSE2() && VT == MVT::f64)) &&
23432 isa<ConstantSDNode>(N0.getOperand(1)) &&
23433 N0.getOperand(0).getOpcode() == ISD::BITCAST &&
23434 N0.getOperand(0).getOperand(0).getValueType() == VT) {
23435 SDValue N000 = N0.getOperand(0).getOperand(0);
23436 SDValue FPConst = DAG.getBitcast(VT, N0.getOperand(1));
23437 return DAG.getNode(FPOpcode, SDLoc(N0), VT, N000, FPConst);
23443 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23444 /// generation and convert it from being a bunch of shuffles and extracts
23445 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23446 /// storing the value and loading scalars back, while for x64 we should
23447 /// use 64-bit extracts and shifts.
23448 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23449 TargetLowering::DAGCombinerInfo &DCI) {
23450 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23453 SDValue InputVector = N->getOperand(0);
23454 SDLoc dl(InputVector);
23455 // Detect mmx to i32 conversion through a v2i32 elt extract.
23456 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23457 N->getValueType(0) == MVT::i32 &&
23458 InputVector.getValueType() == MVT::v2i32) {
23460 // The bitcast source is a direct mmx result.
23461 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23462 if (MMXSrc.getValueType() == MVT::x86mmx)
23463 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23464 N->getValueType(0),
23465 InputVector.getNode()->getOperand(0));
23467 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23468 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23469 MMXSrc.getValueType() == MVT::i64) {
23470 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23471 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23472 MMXSrcOp.getValueType() == MVT::v1i64 &&
23473 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23474 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23475 N->getValueType(0), MMXSrcOp.getOperand(0));
23479 EVT VT = N->getValueType(0);
23481 if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
23482 InputVector.getOpcode() == ISD::BITCAST &&
23483 isa<ConstantSDNode>(InputVector.getOperand(0))) {
23484 uint64_t ExtractedElt =
23485 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23486 uint64_t InputValue =
23487 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23488 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23489 return DAG.getConstant(Res, dl, MVT::i1);
23491 // Only operate on vectors of 4 elements, where the alternative shuffling
23492 // gets to be more expensive.
23493 if (InputVector.getValueType() != MVT::v4i32)
23496 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23497 // single use which is a sign-extend or zero-extend, and all elements are
23499 SmallVector<SDNode *, 4> Uses;
23500 unsigned ExtractedElements = 0;
23501 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23502 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23503 if (UI.getUse().getResNo() != InputVector.getResNo())
23506 SDNode *Extract = *UI;
23507 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23510 if (Extract->getValueType(0) != MVT::i32)
23512 if (!Extract->hasOneUse())
23514 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23515 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23517 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23520 // Record which element was extracted.
23521 ExtractedElements |=
23522 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23524 Uses.push_back(Extract);
23527 // If not all the elements were used, this may not be worthwhile.
23528 if (ExtractedElements != 15)
23531 // Ok, we've now decided to do the transformation.
23532 // If 64-bit shifts are legal, use the extract-shift sequence,
23533 // otherwise bounce the vector off the cache.
23534 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23537 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23538 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23539 auto &DL = DAG.getDataLayout();
23540 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23541 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23542 DAG.getConstant(0, dl, VecIdxTy));
23543 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23544 DAG.getConstant(1, dl, VecIdxTy));
23546 SDValue ShAmt = DAG.getConstant(
23547 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23548 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23549 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23550 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23551 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23552 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23553 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23555 // Store the value to a temporary stack slot.
23556 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23557 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23558 MachinePointerInfo(), false, false, 0);
23560 EVT ElementType = InputVector.getValueType().getVectorElementType();
23561 unsigned EltSize = ElementType.getSizeInBits() / 8;
23563 // Replace each use (extract) with a load of the appropriate element.
23564 for (unsigned i = 0; i < 4; ++i) {
23565 uint64_t Offset = EltSize * i;
23566 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23567 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23569 SDValue ScalarAddr =
23570 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23572 // Load the scalar.
23573 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23574 ScalarAddr, MachinePointerInfo(),
23575 false, false, false, 0);
23580 // Replace the extracts
23581 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23582 UE = Uses.end(); UI != UE; ++UI) {
23583 SDNode *Extract = *UI;
23585 SDValue Idx = Extract->getOperand(1);
23586 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23587 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23590 // The replacement was made in place; don't return anything.
23595 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23596 const X86Subtarget *Subtarget) {
23598 SDValue Cond = N->getOperand(0);
23599 SDValue LHS = N->getOperand(1);
23600 SDValue RHS = N->getOperand(2);
23602 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23603 SDValue CondSrc = Cond->getOperand(0);
23604 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23605 Cond = CondSrc->getOperand(0);
23608 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23611 // A vselect where all conditions and data are constants can be optimized into
23612 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23613 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23614 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23617 unsigned MaskValue = 0;
23618 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23621 MVT VT = N->getSimpleValueType(0);
23622 unsigned NumElems = VT.getVectorNumElements();
23623 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23624 for (unsigned i = 0; i < NumElems; ++i) {
23625 // Be sure we emit undef where we can.
23626 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23627 ShuffleMask[i] = -1;
23629 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23632 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23633 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23635 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23638 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23640 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23641 TargetLowering::DAGCombinerInfo &DCI,
23642 const X86Subtarget *Subtarget) {
23644 SDValue Cond = N->getOperand(0);
23645 // Get the LHS/RHS of the select.
23646 SDValue LHS = N->getOperand(1);
23647 SDValue RHS = N->getOperand(2);
23648 EVT VT = LHS.getValueType();
23649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23651 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23652 // instructions match the semantics of the common C idiom x<y?x:y but not
23653 // x<=y?x:y, because of how they handle negative zero (which can be
23654 // ignored in unsafe-math mode).
23655 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23656 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23657 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23658 (Subtarget->hasSSE2() ||
23659 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23660 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23662 unsigned Opcode = 0;
23663 // Check for x CC y ? x : y.
23664 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23665 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23669 // Converting this to a min would handle NaNs incorrectly, and swapping
23670 // the operands would cause it to handle comparisons between positive
23671 // and negative zero incorrectly.
23672 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23673 if (!DAG.getTarget().Options.UnsafeFPMath &&
23674 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23676 std::swap(LHS, RHS);
23678 Opcode = X86ISD::FMIN;
23681 // Converting this to a min would handle comparisons between positive
23682 // and negative zero incorrectly.
23683 if (!DAG.getTarget().Options.UnsafeFPMath &&
23684 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23686 Opcode = X86ISD::FMIN;
23689 // Converting this to a min would handle both negative zeros and NaNs
23690 // incorrectly, but we can swap the operands to fix both.
23691 std::swap(LHS, RHS);
23695 Opcode = X86ISD::FMIN;
23699 // Converting this to a max would handle comparisons between positive
23700 // and negative zero incorrectly.
23701 if (!DAG.getTarget().Options.UnsafeFPMath &&
23702 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23704 Opcode = X86ISD::FMAX;
23707 // Converting this to a max would handle NaNs incorrectly, and swapping
23708 // the operands would cause it to handle comparisons between positive
23709 // and negative zero incorrectly.
23710 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23711 if (!DAG.getTarget().Options.UnsafeFPMath &&
23712 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23714 std::swap(LHS, RHS);
23716 Opcode = X86ISD::FMAX;
23719 // Converting this to a max would handle both negative zeros and NaNs
23720 // incorrectly, but we can swap the operands to fix both.
23721 std::swap(LHS, RHS);
23725 Opcode = X86ISD::FMAX;
23728 // Check for x CC y ? y : x -- a min/max with reversed arms.
23729 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23730 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23734 // Converting this to a min would handle comparisons between positive
23735 // and negative zero incorrectly, and swapping the operands would
23736 // cause it to handle NaNs incorrectly.
23737 if (!DAG.getTarget().Options.UnsafeFPMath &&
23738 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23739 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23741 std::swap(LHS, RHS);
23743 Opcode = X86ISD::FMIN;
23746 // Converting this to a min would handle NaNs incorrectly.
23747 if (!DAG.getTarget().Options.UnsafeFPMath &&
23748 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23750 Opcode = X86ISD::FMIN;
23753 // Converting this to a min would handle both negative zeros and NaNs
23754 // incorrectly, but we can swap the operands to fix both.
23755 std::swap(LHS, RHS);
23759 Opcode = X86ISD::FMIN;
23763 // Converting this to a max would handle NaNs incorrectly.
23764 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23766 Opcode = X86ISD::FMAX;
23769 // Converting this to a max would handle comparisons between positive
23770 // and negative zero incorrectly, and swapping the operands would
23771 // cause it to handle NaNs incorrectly.
23772 if (!DAG.getTarget().Options.UnsafeFPMath &&
23773 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23774 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23776 std::swap(LHS, RHS);
23778 Opcode = X86ISD::FMAX;
23781 // Converting this to a max would handle both negative zeros and NaNs
23782 // incorrectly, but we can swap the operands to fix both.
23783 std::swap(LHS, RHS);
23787 Opcode = X86ISD::FMAX;
23793 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23796 EVT CondVT = Cond.getValueType();
23797 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23798 CondVT.getVectorElementType() == MVT::i1) {
23799 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23800 // lowering on KNL. In this case we convert it to
23801 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23802 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23803 // Since SKX these selects have a proper lowering.
23804 EVT OpVT = LHS.getValueType();
23805 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23806 (OpVT.getVectorElementType() == MVT::i8 ||
23807 OpVT.getVectorElementType() == MVT::i16) &&
23808 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23809 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23810 DCI.AddToWorklist(Cond.getNode());
23811 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23814 // If this is a select between two integer constants, try to do some
23816 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23817 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23818 // Don't do this for crazy integer types.
23819 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23820 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23821 // so that TrueC (the true value) is larger than FalseC.
23822 bool NeedsCondInvert = false;
23824 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23825 // Efficiently invertible.
23826 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23827 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23828 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23829 NeedsCondInvert = true;
23830 std::swap(TrueC, FalseC);
23833 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23834 if (FalseC->getAPIntValue() == 0 &&
23835 TrueC->getAPIntValue().isPowerOf2()) {
23836 if (NeedsCondInvert) // Invert the condition if needed.
23837 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23838 DAG.getConstant(1, DL, Cond.getValueType()));
23840 // Zero extend the condition if needed.
23841 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23843 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23844 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23845 DAG.getConstant(ShAmt, DL, MVT::i8));
23848 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23849 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23850 if (NeedsCondInvert) // Invert the condition if needed.
23851 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23852 DAG.getConstant(1, DL, Cond.getValueType()));
23854 // Zero extend the condition if needed.
23855 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23856 FalseC->getValueType(0), Cond);
23857 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23858 SDValue(FalseC, 0));
23861 // Optimize cases that will turn into an LEA instruction. This requires
23862 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23863 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23864 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23865 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23867 bool isFastMultiplier = false;
23869 switch ((unsigned char)Diff) {
23871 case 1: // result = add base, cond
23872 case 2: // result = lea base( , cond*2)
23873 case 3: // result = lea base(cond, cond*2)
23874 case 4: // result = lea base( , cond*4)
23875 case 5: // result = lea base(cond, cond*4)
23876 case 8: // result = lea base( , cond*8)
23877 case 9: // result = lea base(cond, cond*8)
23878 isFastMultiplier = true;
23883 if (isFastMultiplier) {
23884 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23885 if (NeedsCondInvert) // Invert the condition if needed.
23886 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23887 DAG.getConstant(1, DL, Cond.getValueType()));
23889 // Zero extend the condition if needed.
23890 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23892 // Scale the condition by the difference.
23894 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23895 DAG.getConstant(Diff, DL,
23896 Cond.getValueType()));
23898 // Add the base if non-zero.
23899 if (FalseC->getAPIntValue() != 0)
23900 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23901 SDValue(FalseC, 0));
23908 // Canonicalize max and min:
23909 // (x > y) ? x : y -> (x >= y) ? x : y
23910 // (x < y) ? x : y -> (x <= y) ? x : y
23911 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23912 // the need for an extra compare
23913 // against zero. e.g.
23914 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23916 // testl %edi, %edi
23918 // cmovgl %edi, %eax
23922 // cmovsl %eax, %edi
23923 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23924 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23925 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23926 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23931 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23932 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23933 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23934 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23939 // Early exit check
23940 if (!TLI.isTypeLegal(VT))
23943 // Match VSELECTs into subs with unsigned saturation.
23944 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23945 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23946 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23947 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23948 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23950 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23951 // left side invert the predicate to simplify logic below.
23953 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23955 CC = ISD::getSetCCInverse(CC, true);
23956 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23960 if (Other.getNode() && Other->getNumOperands() == 2 &&
23961 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23962 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23963 SDValue CondRHS = Cond->getOperand(1);
23965 // Look for a general sub with unsigned saturation first.
23966 // x >= y ? x-y : 0 --> subus x, y
23967 // x > y ? x-y : 0 --> subus x, y
23968 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23969 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23970 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23972 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23973 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23974 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23975 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23976 // If the RHS is a constant we have to reverse the const
23977 // canonicalization.
23978 // x > C-1 ? x+-C : 0 --> subus x, C
23979 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23980 CondRHSConst->getAPIntValue() ==
23981 (-OpRHSConst->getAPIntValue() - 1))
23982 return DAG.getNode(
23983 X86ISD::SUBUS, DL, VT, OpLHS,
23984 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23986 // Another special case: If C was a sign bit, the sub has been
23987 // canonicalized into a xor.
23988 // FIXME: Would it be better to use computeKnownBits to determine
23989 // whether it's safe to decanonicalize the xor?
23990 // x s< 0 ? x^C : 0 --> subus x, C
23991 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23992 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23993 OpRHSConst->getAPIntValue().isSignBit())
23994 // Note that we have to rebuild the RHS constant here to ensure we
23995 // don't rely on particular values of undef lanes.
23996 return DAG.getNode(
23997 X86ISD::SUBUS, DL, VT, OpLHS,
23998 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
24003 // Simplify vector selection if condition value type matches vselect
24005 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
24006 assert(Cond.getValueType().isVector() &&
24007 "vector select expects a vector selector!");
24009 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
24010 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
24012 // Try invert the condition if true value is not all 1s and false value
24014 if (!TValIsAllOnes && !FValIsAllZeros &&
24015 // Check if the selector will be produced by CMPP*/PCMP*
24016 Cond.getOpcode() == ISD::SETCC &&
24017 // Check if SETCC has already been promoted
24018 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
24020 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
24021 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
24023 if (TValIsAllZeros || FValIsAllOnes) {
24024 SDValue CC = Cond.getOperand(2);
24025 ISD::CondCode NewCC =
24026 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
24027 Cond.getOperand(0).getValueType().isInteger());
24028 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
24029 std::swap(LHS, RHS);
24030 TValIsAllOnes = FValIsAllOnes;
24031 FValIsAllZeros = TValIsAllZeros;
24035 if (TValIsAllOnes || FValIsAllZeros) {
24038 if (TValIsAllOnes && FValIsAllZeros)
24040 else if (TValIsAllOnes)
24042 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
24043 else if (FValIsAllZeros)
24044 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
24045 DAG.getBitcast(CondVT, LHS));
24047 return DAG.getBitcast(VT, Ret);
24051 // We should generate an X86ISD::BLENDI from a vselect if its argument
24052 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
24053 // constants. This specific pattern gets generated when we split a
24054 // selector for a 512 bit vector in a machine without AVX512 (but with
24055 // 256-bit vectors), during legalization:
24057 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
24059 // Iff we find this pattern and the build_vectors are built from
24060 // constants, we translate the vselect into a shuffle_vector that we
24061 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
24062 if ((N->getOpcode() == ISD::VSELECT ||
24063 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
24064 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
24065 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
24066 if (Shuffle.getNode())
24070 // If this is a *dynamic* select (non-constant condition) and we can match
24071 // this node with one of the variable blend instructions, restructure the
24072 // condition so that the blends can use the high bit of each element and use
24073 // SimplifyDemandedBits to simplify the condition operand.
24074 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
24075 !DCI.isBeforeLegalize() &&
24076 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
24077 unsigned BitWidth = Cond.getValueType().getScalarSizeInBits();
24079 // Don't optimize vector selects that map to mask-registers.
24083 // We can only handle the cases where VSELECT is directly legal on the
24084 // subtarget. We custom lower VSELECT nodes with constant conditions and
24085 // this makes it hard to see whether a dynamic VSELECT will correctly
24086 // lower, so we both check the operation's status and explicitly handle the
24087 // cases where a *dynamic* blend will fail even though a constant-condition
24088 // blend could be custom lowered.
24089 // FIXME: We should find a better way to handle this class of problems.
24090 // Potentially, we should combine constant-condition vselect nodes
24091 // pre-legalization into shuffles and not mark as many types as custom
24093 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
24095 // FIXME: We don't support i16-element blends currently. We could and
24096 // should support them by making *all* the bits in the condition be set
24097 // rather than just the high bit and using an i8-element blend.
24098 if (VT.getVectorElementType() == MVT::i16)
24100 // Dynamic blending was only available from SSE4.1 onward.
24101 if (VT.is128BitVector() && !Subtarget->hasSSE41())
24103 // Byte blends are only available in AVX2
24104 if (VT == MVT::v32i8 && !Subtarget->hasAVX2())
24107 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
24108 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
24110 APInt KnownZero, KnownOne;
24111 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
24112 DCI.isBeforeLegalizeOps());
24113 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
24114 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
24116 // If we changed the computation somewhere in the DAG, this change
24117 // will affect all users of Cond.
24118 // Make sure it is fine and update all the nodes so that we do not
24119 // use the generic VSELECT anymore. Otherwise, we may perform
24120 // wrong optimizations as we messed up with the actual expectation
24121 // for the vector boolean values.
24122 if (Cond != TLO.Old) {
24123 // Check all uses of that condition operand to check whether it will be
24124 // consumed by non-BLEND instructions, which may depend on all bits are
24126 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24128 if (I->getOpcode() != ISD::VSELECT)
24129 // TODO: Add other opcodes eventually lowered into BLEND.
24132 // Update all the users of the condition, before committing the change,
24133 // so that the VSELECT optimizations that expect the correct vector
24134 // boolean value will not be triggered.
24135 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
24137 DAG.ReplaceAllUsesOfValueWith(
24139 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
24140 Cond, I->getOperand(1), I->getOperand(2)));
24141 DCI.CommitTargetLoweringOpt(TLO);
24144 // At this point, only Cond is changed. Change the condition
24145 // just for N to keep the opportunity to optimize all other
24146 // users their own way.
24147 DAG.ReplaceAllUsesOfValueWith(
24149 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
24150 TLO.New, N->getOperand(1), N->getOperand(2)));
24158 // Check whether a boolean test is testing a boolean value generated by
24159 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
24162 // Simplify the following patterns:
24163 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
24164 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
24165 // to (Op EFLAGS Cond)
24167 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
24168 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
24169 // to (Op EFLAGS !Cond)
24171 // where Op could be BRCOND or CMOV.
24173 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
24174 // Quit if not CMP and SUB with its value result used.
24175 if (Cmp.getOpcode() != X86ISD::CMP &&
24176 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
24179 // Quit if not used as a boolean value.
24180 if (CC != X86::COND_E && CC != X86::COND_NE)
24183 // Check CMP operands. One of them should be 0 or 1 and the other should be
24184 // an SetCC or extended from it.
24185 SDValue Op1 = Cmp.getOperand(0);
24186 SDValue Op2 = Cmp.getOperand(1);
24189 const ConstantSDNode* C = nullptr;
24190 bool needOppositeCond = (CC == X86::COND_E);
24191 bool checkAgainstTrue = false; // Is it a comparison against 1?
24193 if ((C = dyn_cast<ConstantSDNode>(Op1)))
24195 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
24197 else // Quit if all operands are not constants.
24200 if (C->getZExtValue() == 1) {
24201 needOppositeCond = !needOppositeCond;
24202 checkAgainstTrue = true;
24203 } else if (C->getZExtValue() != 0)
24204 // Quit if the constant is neither 0 or 1.
24207 bool truncatedToBoolWithAnd = false;
24208 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
24209 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
24210 SetCC.getOpcode() == ISD::TRUNCATE ||
24211 SetCC.getOpcode() == ISD::AND) {
24212 if (SetCC.getOpcode() == ISD::AND) {
24214 ConstantSDNode *CS;
24215 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
24216 CS->getZExtValue() == 1)
24218 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
24219 CS->getZExtValue() == 1)
24223 SetCC = SetCC.getOperand(OpIdx);
24224 truncatedToBoolWithAnd = true;
24226 SetCC = SetCC.getOperand(0);
24229 switch (SetCC.getOpcode()) {
24230 case X86ISD::SETCC_CARRY:
24231 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
24232 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
24233 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
24234 // truncated to i1 using 'and'.
24235 if (checkAgainstTrue && !truncatedToBoolWithAnd)
24237 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
24238 "Invalid use of SETCC_CARRY!");
24240 case X86ISD::SETCC:
24241 // Set the condition code or opposite one if necessary.
24242 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
24243 if (needOppositeCond)
24244 CC = X86::GetOppositeBranchCondition(CC);
24245 return SetCC.getOperand(1);
24246 case X86ISD::CMOV: {
24247 // Check whether false/true value has canonical one, i.e. 0 or 1.
24248 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
24249 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
24250 // Quit if true value is not a constant.
24253 // Quit if false value is not a constant.
24255 SDValue Op = SetCC.getOperand(0);
24256 // Skip 'zext' or 'trunc' node.
24257 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
24258 Op.getOpcode() == ISD::TRUNCATE)
24259 Op = Op.getOperand(0);
24260 // A special case for rdrand/rdseed, where 0 is set if false cond is
24262 if ((Op.getOpcode() != X86ISD::RDRAND &&
24263 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
24266 // Quit if false value is not the constant 0 or 1.
24267 bool FValIsFalse = true;
24268 if (FVal && FVal->getZExtValue() != 0) {
24269 if (FVal->getZExtValue() != 1)
24271 // If FVal is 1, opposite cond is needed.
24272 needOppositeCond = !needOppositeCond;
24273 FValIsFalse = false;
24275 // Quit if TVal is not the constant opposite of FVal.
24276 if (FValIsFalse && TVal->getZExtValue() != 1)
24278 if (!FValIsFalse && TVal->getZExtValue() != 0)
24280 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
24281 if (needOppositeCond)
24282 CC = X86::GetOppositeBranchCondition(CC);
24283 return SetCC.getOperand(3);
24290 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24292 /// (X86or (X86setcc) (X86setcc))
24293 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24294 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24295 X86::CondCode &CC1, SDValue &Flags,
24297 if (Cond->getOpcode() == X86ISD::CMP) {
24298 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
24299 if (!CondOp1C || !CondOp1C->isNullValue())
24302 Cond = Cond->getOperand(0);
24307 SDValue SetCC0, SetCC1;
24308 switch (Cond->getOpcode()) {
24309 default: return false;
24316 SetCC0 = Cond->getOperand(0);
24317 SetCC1 = Cond->getOperand(1);
24321 // Make sure we have SETCC nodes, using the same flags value.
24322 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24323 SetCC1.getOpcode() != X86ISD::SETCC ||
24324 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24327 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24328 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24329 Flags = SetCC0->getOperand(1);
24333 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24334 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24335 TargetLowering::DAGCombinerInfo &DCI,
24336 const X86Subtarget *Subtarget) {
24339 // If the flag operand isn't dead, don't touch this CMOV.
24340 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24343 SDValue FalseOp = N->getOperand(0);
24344 SDValue TrueOp = N->getOperand(1);
24345 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24346 SDValue Cond = N->getOperand(3);
24348 if (CC == X86::COND_E || CC == X86::COND_NE) {
24349 switch (Cond.getOpcode()) {
24353 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24354 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24355 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24361 Flags = checkBoolTestSetCCCombine(Cond, CC);
24362 if (Flags.getNode() &&
24363 // Extra check as FCMOV only supports a subset of X86 cond.
24364 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24365 SDValue Ops[] = { FalseOp, TrueOp,
24366 DAG.getConstant(CC, DL, MVT::i8), Flags };
24367 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24370 // If this is a select between two integer constants, try to do some
24371 // optimizations. Note that the operands are ordered the opposite of SELECT
24373 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24374 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24375 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24376 // larger than FalseC (the false value).
24377 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24378 CC = X86::GetOppositeBranchCondition(CC);
24379 std::swap(TrueC, FalseC);
24380 std::swap(TrueOp, FalseOp);
24383 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24384 // This is efficient for any integer data type (including i8/i16) and
24386 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24387 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24388 DAG.getConstant(CC, DL, MVT::i8), Cond);
24390 // Zero extend the condition if needed.
24391 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24393 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24394 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24395 DAG.getConstant(ShAmt, DL, MVT::i8));
24396 if (N->getNumValues() == 2) // Dead flag value?
24397 return DCI.CombineTo(N, Cond, SDValue());
24401 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24402 // for any integer data type, including i8/i16.
24403 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24404 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24405 DAG.getConstant(CC, DL, MVT::i8), Cond);
24407 // Zero extend the condition if needed.
24408 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24409 FalseC->getValueType(0), Cond);
24410 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24411 SDValue(FalseC, 0));
24413 if (N->getNumValues() == 2) // Dead flag value?
24414 return DCI.CombineTo(N, Cond, SDValue());
24418 // Optimize cases that will turn into an LEA instruction. This requires
24419 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24420 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24421 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24422 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24424 bool isFastMultiplier = false;
24426 switch ((unsigned char)Diff) {
24428 case 1: // result = add base, cond
24429 case 2: // result = lea base( , cond*2)
24430 case 3: // result = lea base(cond, cond*2)
24431 case 4: // result = lea base( , cond*4)
24432 case 5: // result = lea base(cond, cond*4)
24433 case 8: // result = lea base( , cond*8)
24434 case 9: // result = lea base(cond, cond*8)
24435 isFastMultiplier = true;
24440 if (isFastMultiplier) {
24441 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24442 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24443 DAG.getConstant(CC, DL, MVT::i8), Cond);
24444 // Zero extend the condition if needed.
24445 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24447 // Scale the condition by the difference.
24449 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24450 DAG.getConstant(Diff, DL, Cond.getValueType()));
24452 // Add the base if non-zero.
24453 if (FalseC->getAPIntValue() != 0)
24454 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24455 SDValue(FalseC, 0));
24456 if (N->getNumValues() == 2) // Dead flag value?
24457 return DCI.CombineTo(N, Cond, SDValue());
24464 // Handle these cases:
24465 // (select (x != c), e, c) -> select (x != c), e, x),
24466 // (select (x == c), c, e) -> select (x == c), x, e)
24467 // where the c is an integer constant, and the "select" is the combination
24468 // of CMOV and CMP.
24470 // The rationale for this change is that the conditional-move from a constant
24471 // needs two instructions, however, conditional-move from a register needs
24472 // only one instruction.
24474 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24475 // some instruction-combining opportunities. This opt needs to be
24476 // postponed as late as possible.
24478 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24479 // the DCI.xxxx conditions are provided to postpone the optimization as
24480 // late as possible.
24482 ConstantSDNode *CmpAgainst = nullptr;
24483 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24484 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24485 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24487 if (CC == X86::COND_NE &&
24488 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24489 CC = X86::GetOppositeBranchCondition(CC);
24490 std::swap(TrueOp, FalseOp);
24493 if (CC == X86::COND_E &&
24494 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24495 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24496 DAG.getConstant(CC, DL, MVT::i8), Cond };
24497 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24502 // Fold and/or of setcc's to double CMOV:
24503 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24504 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24506 // This combine lets us generate:
24507 // cmovcc1 (jcc1 if we don't have CMOV)
24513 // cmovne (jne if we don't have CMOV)
24514 // When we can't use the CMOV instruction, it might increase branch
24516 // When we can use CMOV, or when there is no mispredict, this improves
24517 // throughput and reduces register pressure.
24519 if (CC == X86::COND_NE) {
24521 X86::CondCode CC0, CC1;
24523 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24525 std::swap(FalseOp, TrueOp);
24526 CC0 = X86::GetOppositeBranchCondition(CC0);
24527 CC1 = X86::GetOppositeBranchCondition(CC1);
24530 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24532 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24533 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24534 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24535 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24543 /// PerformMulCombine - Optimize a single multiply with constant into two
24544 /// in order to implement it with two cheaper instructions, e.g.
24545 /// LEA + SHL, LEA + LEA.
24546 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24547 TargetLowering::DAGCombinerInfo &DCI) {
24548 // An imul is usually smaller than the alternative sequence.
24549 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24552 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24555 EVT VT = N->getValueType(0);
24556 if (VT != MVT::i64 && VT != MVT::i32)
24559 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24562 uint64_t MulAmt = C->getZExtValue();
24563 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24566 uint64_t MulAmt1 = 0;
24567 uint64_t MulAmt2 = 0;
24568 if ((MulAmt % 9) == 0) {
24570 MulAmt2 = MulAmt / 9;
24571 } else if ((MulAmt % 5) == 0) {
24573 MulAmt2 = MulAmt / 5;
24574 } else if ((MulAmt % 3) == 0) {
24576 MulAmt2 = MulAmt / 3;
24579 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24582 if (isPowerOf2_64(MulAmt2) &&
24583 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24584 // If second multiplifer is pow2, issue it first. We want the multiply by
24585 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24587 std::swap(MulAmt1, MulAmt2);
24590 if (isPowerOf2_64(MulAmt1))
24591 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24592 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24594 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24595 DAG.getConstant(MulAmt1, DL, VT));
24597 if (isPowerOf2_64(MulAmt2))
24598 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24599 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24601 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24602 DAG.getConstant(MulAmt2, DL, VT));
24604 // Do not add new nodes to DAG combiner worklist.
24605 DCI.CombineTo(N, NewMul, false);
24610 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24611 SDValue N0 = N->getOperand(0);
24612 SDValue N1 = N->getOperand(1);
24613 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24614 EVT VT = N0.getValueType();
24616 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24617 // since the result of setcc_c is all zero's or all ones.
24618 if (VT.isInteger() && !VT.isVector() &&
24619 N1C && N0.getOpcode() == ISD::AND &&
24620 N0.getOperand(1).getOpcode() == ISD::Constant) {
24621 SDValue N00 = N0.getOperand(0);
24622 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24623 APInt ShAmt = N1C->getAPIntValue();
24624 Mask = Mask.shl(ShAmt);
24625 bool MaskOK = false;
24626 // We can handle cases concerning bit-widening nodes containing setcc_c if
24627 // we carefully interrogate the mask to make sure we are semantics
24629 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24630 // of the underlying setcc_c operation if the setcc_c was zero extended.
24631 // Consider the following example:
24632 // zext(setcc_c) -> i32 0x0000FFFF
24633 // c1 -> i32 0x0000FFFF
24634 // c2 -> i32 0x00000001
24635 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24636 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24637 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24639 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24640 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24642 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24643 N00.getOpcode() == ISD::ANY_EXTEND) &&
24644 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24645 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24647 if (MaskOK && Mask != 0) {
24649 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24653 // Hardware support for vector shifts is sparse which makes us scalarize the
24654 // vector operations in many cases. Also, on sandybridge ADD is faster than
24656 // (shl V, 1) -> add V,V
24657 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24658 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24659 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24660 // We shift all of the values by one. In many cases we do not have
24661 // hardware support for this operation. This is better expressed as an ADD
24663 if (N1SplatC->getAPIntValue() == 1)
24664 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24670 /// \brief Returns a vector of 0s if the node in input is a vector logical
24671 /// shift by a constant amount which is known to be bigger than or equal
24672 /// to the vector element size in bits.
24673 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24674 const X86Subtarget *Subtarget) {
24675 EVT VT = N->getValueType(0);
24677 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24678 (!Subtarget->hasInt256() ||
24679 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24682 SDValue Amt = N->getOperand(1);
24684 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24685 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24686 APInt ShiftAmt = AmtSplat->getAPIntValue();
24687 unsigned MaxAmount =
24688 VT.getSimpleVT().getVectorElementType().getSizeInBits();
24690 // SSE2/AVX2 logical shifts always return a vector of 0s
24691 // if the shift amount is bigger than or equal to
24692 // the element size. The constant shift amount will be
24693 // encoded as a 8-bit immediate.
24694 if (ShiftAmt.trunc(8).uge(MaxAmount))
24695 return getZeroVector(VT, Subtarget, DAG, DL);
24701 /// PerformShiftCombine - Combine shifts.
24702 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24703 TargetLowering::DAGCombinerInfo &DCI,
24704 const X86Subtarget *Subtarget) {
24705 if (N->getOpcode() == ISD::SHL)
24706 if (SDValue V = PerformSHLCombine(N, DAG))
24709 // Try to fold this logical shift into a zero vector.
24710 if (N->getOpcode() != ISD::SRA)
24711 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24717 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24718 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24719 // and friends. Likewise for OR -> CMPNEQSS.
24720 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24721 TargetLowering::DAGCombinerInfo &DCI,
24722 const X86Subtarget *Subtarget) {
24725 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24726 // we're requiring SSE2 for both.
24727 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24728 SDValue N0 = N->getOperand(0);
24729 SDValue N1 = N->getOperand(1);
24730 SDValue CMP0 = N0->getOperand(1);
24731 SDValue CMP1 = N1->getOperand(1);
24734 // The SETCCs should both refer to the same CMP.
24735 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24738 SDValue CMP00 = CMP0->getOperand(0);
24739 SDValue CMP01 = CMP0->getOperand(1);
24740 EVT VT = CMP00.getValueType();
24742 if (VT == MVT::f32 || VT == MVT::f64) {
24743 bool ExpectingFlags = false;
24744 // Check for any users that want flags:
24745 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24746 !ExpectingFlags && UI != UE; ++UI)
24747 switch (UI->getOpcode()) {
24752 ExpectingFlags = true;
24754 case ISD::CopyToReg:
24755 case ISD::SIGN_EXTEND:
24756 case ISD::ZERO_EXTEND:
24757 case ISD::ANY_EXTEND:
24761 if (!ExpectingFlags) {
24762 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24763 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24765 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24766 X86::CondCode tmp = cc0;
24771 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24772 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24773 // FIXME: need symbolic constants for these magic numbers.
24774 // See X86ATTInstPrinter.cpp:printSSECC().
24775 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24776 if (Subtarget->hasAVX512()) {
24777 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24779 DAG.getConstant(x86cc, DL, MVT::i8));
24780 if (N->getValueType(0) != MVT::i1)
24781 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24785 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24786 CMP00.getValueType(), CMP00, CMP01,
24787 DAG.getConstant(x86cc, DL,
24790 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24791 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24793 if (is64BitFP && !Subtarget->is64Bit()) {
24794 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24795 // 64-bit integer, since that's not a legal type. Since
24796 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24797 // bits, but can do this little dance to extract the lowest 32 bits
24798 // and work with those going forward.
24799 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24801 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24802 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24803 Vector32, DAG.getIntPtrConstant(0, DL));
24807 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24808 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24809 DAG.getConstant(1, DL, IntVT));
24810 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24812 return OneBitOfTruth;
24820 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24821 /// so it can be folded inside ANDNP.
24822 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24823 EVT VT = N->getValueType(0);
24825 // Match direct AllOnes for 128 and 256-bit vectors
24826 if (ISD::isBuildVectorAllOnes(N))
24829 // Look through a bit convert.
24830 if (N->getOpcode() == ISD::BITCAST)
24831 N = N->getOperand(0).getNode();
24833 // Sometimes the operand may come from a insert_subvector building a 256-bit
24835 if (VT.is256BitVector() &&
24836 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24837 SDValue V1 = N->getOperand(0);
24838 SDValue V2 = N->getOperand(1);
24840 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24841 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24842 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24843 ISD::isBuildVectorAllOnes(V2.getNode()))
24850 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24851 // register. In most cases we actually compare or select YMM-sized registers
24852 // and mixing the two types creates horrible code. This method optimizes
24853 // some of the transition sequences.
24854 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24855 TargetLowering::DAGCombinerInfo &DCI,
24856 const X86Subtarget *Subtarget) {
24857 EVT VT = N->getValueType(0);
24858 if (!VT.is256BitVector())
24861 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24862 N->getOpcode() == ISD::ZERO_EXTEND ||
24863 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24865 SDValue Narrow = N->getOperand(0);
24866 EVT NarrowVT = Narrow->getValueType(0);
24867 if (!NarrowVT.is128BitVector())
24870 if (Narrow->getOpcode() != ISD::XOR &&
24871 Narrow->getOpcode() != ISD::AND &&
24872 Narrow->getOpcode() != ISD::OR)
24875 SDValue N0 = Narrow->getOperand(0);
24876 SDValue N1 = Narrow->getOperand(1);
24879 // The Left side has to be a trunc.
24880 if (N0.getOpcode() != ISD::TRUNCATE)
24883 // The type of the truncated inputs.
24884 EVT WideVT = N0->getOperand(0)->getValueType(0);
24888 // The right side has to be a 'trunc' or a constant vector.
24889 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24890 ConstantSDNode *RHSConstSplat = nullptr;
24891 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24892 RHSConstSplat = RHSBV->getConstantSplatNode();
24893 if (!RHSTrunc && !RHSConstSplat)
24896 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24898 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24901 // Set N0 and N1 to hold the inputs to the new wide operation.
24902 N0 = N0->getOperand(0);
24903 if (RHSConstSplat) {
24904 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getVectorElementType(),
24905 SDValue(RHSConstSplat, 0));
24906 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24907 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24908 } else if (RHSTrunc) {
24909 N1 = N1->getOperand(0);
24912 // Generate the wide operation.
24913 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24914 unsigned Opcode = N->getOpcode();
24916 case ISD::ANY_EXTEND:
24918 case ISD::ZERO_EXTEND: {
24919 unsigned InBits = NarrowVT.getScalarSizeInBits();
24920 APInt Mask = APInt::getAllOnesValue(InBits);
24921 Mask = Mask.zext(VT.getScalarSizeInBits());
24922 return DAG.getNode(ISD::AND, DL, VT,
24923 Op, DAG.getConstant(Mask, DL, VT));
24925 case ISD::SIGN_EXTEND:
24926 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24927 Op, DAG.getValueType(NarrowVT));
24929 llvm_unreachable("Unexpected opcode");
24933 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24934 TargetLowering::DAGCombinerInfo &DCI,
24935 const X86Subtarget *Subtarget) {
24936 SDValue N0 = N->getOperand(0);
24937 SDValue N1 = N->getOperand(1);
24940 // A vector zext_in_reg may be represented as a shuffle,
24941 // feeding into a bitcast (this represents anyext) feeding into
24942 // an and with a mask.
24943 // We'd like to try to combine that into a shuffle with zero
24944 // plus a bitcast, removing the and.
24945 if (N0.getOpcode() != ISD::BITCAST ||
24946 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24949 // The other side of the AND should be a splat of 2^C, where C
24950 // is the number of bits in the source type.
24951 if (N1.getOpcode() == ISD::BITCAST)
24952 N1 = N1.getOperand(0);
24953 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24955 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24957 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24958 EVT SrcType = Shuffle->getValueType(0);
24960 // We expect a single-source shuffle
24961 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24964 unsigned SrcSize = SrcType.getScalarSizeInBits();
24966 APInt SplatValue, SplatUndef;
24967 unsigned SplatBitSize;
24969 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24970 SplatBitSize, HasAnyUndefs))
24973 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24974 // Make sure the splat matches the mask we expect
24975 if (SplatBitSize > ResSize ||
24976 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24979 // Make sure the input and output size make sense
24980 if (SrcSize >= ResSize || ResSize % SrcSize)
24983 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24984 // The number of u's between each two values depends on the ratio between
24985 // the source and dest type.
24986 unsigned ZextRatio = ResSize / SrcSize;
24987 bool IsZext = true;
24988 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24989 if (i % ZextRatio) {
24990 if (Shuffle->getMaskElt(i) > 0) {
24996 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24997 // Expected element number
25007 // Ok, perform the transformation - replace the shuffle with
25008 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
25009 // (instead of undef) where the k elements come from the zero vector.
25010 SmallVector<int, 8> Mask;
25011 unsigned NumElems = SrcType.getVectorNumElements();
25012 for (unsigned i = 0; i < NumElems; ++i)
25014 Mask.push_back(NumElems);
25016 Mask.push_back(i / ZextRatio);
25018 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
25019 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
25020 return DAG.getBitcast(N0.getValueType(), NewShuffle);
25023 /// If both input operands of a logic op are being cast from floating point
25024 /// types, try to convert this into a floating point logic node to avoid
25025 /// unnecessary moves from SSE to integer registers.
25026 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
25027 const X86Subtarget *Subtarget) {
25028 unsigned FPOpcode = ISD::DELETED_NODE;
25029 if (N->getOpcode() == ISD::AND)
25030 FPOpcode = X86ISD::FAND;
25031 else if (N->getOpcode() == ISD::OR)
25032 FPOpcode = X86ISD::FOR;
25033 else if (N->getOpcode() == ISD::XOR)
25034 FPOpcode = X86ISD::FXOR;
25036 assert(FPOpcode != ISD::DELETED_NODE &&
25037 "Unexpected input node for FP logic conversion");
25039 EVT VT = N->getValueType(0);
25040 SDValue N0 = N->getOperand(0);
25041 SDValue N1 = N->getOperand(1);
25043 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
25044 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
25045 (Subtarget->hasSSE2() && VT == MVT::i64))) {
25046 SDValue N00 = N0.getOperand(0);
25047 SDValue N10 = N1.getOperand(0);
25048 EVT N00Type = N00.getValueType();
25049 EVT N10Type = N10.getValueType();
25050 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
25051 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
25052 return DAG.getBitcast(VT, FPLogic);
25058 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
25059 TargetLowering::DAGCombinerInfo &DCI,
25060 const X86Subtarget *Subtarget) {
25061 if (DCI.isBeforeLegalizeOps())
25064 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
25067 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25070 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25073 EVT VT = N->getValueType(0);
25074 SDValue N0 = N->getOperand(0);
25075 SDValue N1 = N->getOperand(1);
25078 // Create BEXTR instructions
25079 // BEXTR is ((X >> imm) & (2**size-1))
25080 if (VT == MVT::i32 || VT == MVT::i64) {
25081 // Check for BEXTR.
25082 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
25083 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
25084 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
25085 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
25086 if (MaskNode && ShiftNode) {
25087 uint64_t Mask = MaskNode->getZExtValue();
25088 uint64_t Shift = ShiftNode->getZExtValue();
25089 if (isMask_64(Mask)) {
25090 uint64_t MaskSize = countPopulation(Mask);
25091 if (Shift + MaskSize <= VT.getSizeInBits())
25092 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
25093 DAG.getConstant(Shift | (MaskSize << 8), DL,
25102 // Want to form ANDNP nodes:
25103 // 1) In the hopes of then easily combining them with OR and AND nodes
25104 // to form PBLEND/PSIGN.
25105 // 2) To match ANDN packed intrinsics
25106 if (VT != MVT::v2i64 && VT != MVT::v4i64)
25109 // Check LHS for vnot
25110 if (N0.getOpcode() == ISD::XOR &&
25111 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
25112 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
25113 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
25115 // Check RHS for vnot
25116 if (N1.getOpcode() == ISD::XOR &&
25117 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
25118 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
25119 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
25124 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
25125 TargetLowering::DAGCombinerInfo &DCI,
25126 const X86Subtarget *Subtarget) {
25127 if (DCI.isBeforeLegalizeOps())
25130 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
25133 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25136 SDValue N0 = N->getOperand(0);
25137 SDValue N1 = N->getOperand(1);
25138 EVT VT = N->getValueType(0);
25140 // look for psign/blend
25141 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
25142 if (!Subtarget->hasSSSE3() ||
25143 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
25146 // Canonicalize pandn to RHS
25147 if (N0.getOpcode() == X86ISD::ANDNP)
25149 // or (and (m, y), (pandn m, x))
25150 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
25151 SDValue Mask = N1.getOperand(0);
25152 SDValue X = N1.getOperand(1);
25154 if (N0.getOperand(0) == Mask)
25155 Y = N0.getOperand(1);
25156 if (N0.getOperand(1) == Mask)
25157 Y = N0.getOperand(0);
25159 // Check to see if the mask appeared in both the AND and ANDNP and
25163 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
25164 // Look through mask bitcast.
25165 if (Mask.getOpcode() == ISD::BITCAST)
25166 Mask = Mask.getOperand(0);
25167 if (X.getOpcode() == ISD::BITCAST)
25168 X = X.getOperand(0);
25169 if (Y.getOpcode() == ISD::BITCAST)
25170 Y = Y.getOperand(0);
25172 EVT MaskVT = Mask.getValueType();
25174 // Validate that the Mask operand is a vector sra node.
25175 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
25176 // there is no psrai.b
25177 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
25178 unsigned SraAmt = ~0;
25179 if (Mask.getOpcode() == ISD::SRA) {
25180 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
25181 if (auto *AmtConst = AmtBV->getConstantSplatNode())
25182 SraAmt = AmtConst->getZExtValue();
25183 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
25184 SDValue SraC = Mask.getOperand(1);
25185 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
25187 if ((SraAmt + 1) != EltBits)
25192 // Now we know we at least have a plendvb with the mask val. See if
25193 // we can form a psignb/w/d.
25194 // psign = x.type == y.type == mask.type && y = sub(0, x);
25195 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
25196 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
25197 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
25198 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
25199 "Unsupported VT for PSIGN");
25200 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
25201 return DAG.getBitcast(VT, Mask);
25203 // PBLENDVB only available on SSE 4.1
25204 if (!Subtarget->hasSSE41())
25207 MVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
25209 X = DAG.getBitcast(BlendVT, X);
25210 Y = DAG.getBitcast(BlendVT, Y);
25211 Mask = DAG.getBitcast(BlendVT, Mask);
25212 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
25213 return DAG.getBitcast(VT, Mask);
25217 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
25220 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
25221 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
25223 // SHLD/SHRD instructions have lower register pressure, but on some
25224 // platforms they have higher latency than the equivalent
25225 // series of shifts/or that would otherwise be generated.
25226 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
25227 // have higher latencies and we are not optimizing for size.
25228 if (!OptForSize && Subtarget->isSHLDSlow())
25231 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
25233 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
25235 if (!N0.hasOneUse() || !N1.hasOneUse())
25238 SDValue ShAmt0 = N0.getOperand(1);
25239 if (ShAmt0.getValueType() != MVT::i8)
25241 SDValue ShAmt1 = N1.getOperand(1);
25242 if (ShAmt1.getValueType() != MVT::i8)
25244 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
25245 ShAmt0 = ShAmt0.getOperand(0);
25246 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
25247 ShAmt1 = ShAmt1.getOperand(0);
25250 unsigned Opc = X86ISD::SHLD;
25251 SDValue Op0 = N0.getOperand(0);
25252 SDValue Op1 = N1.getOperand(0);
25253 if (ShAmt0.getOpcode() == ISD::SUB) {
25254 Opc = X86ISD::SHRD;
25255 std::swap(Op0, Op1);
25256 std::swap(ShAmt0, ShAmt1);
25259 unsigned Bits = VT.getSizeInBits();
25260 if (ShAmt1.getOpcode() == ISD::SUB) {
25261 SDValue Sum = ShAmt1.getOperand(0);
25262 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
25263 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
25264 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
25265 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
25266 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
25267 return DAG.getNode(Opc, DL, VT,
25269 DAG.getNode(ISD::TRUNCATE, DL,
25272 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
25273 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
25275 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
25276 return DAG.getNode(Opc, DL, VT,
25277 N0.getOperand(0), N1.getOperand(0),
25278 DAG.getNode(ISD::TRUNCATE, DL,
25285 // Generate NEG and CMOV for integer abs.
25286 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
25287 EVT VT = N->getValueType(0);
25289 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25290 // 8-bit integer abs to NEG and CMOV.
25291 if (VT.isInteger() && VT.getSizeInBits() == 8)
25294 SDValue N0 = N->getOperand(0);
25295 SDValue N1 = N->getOperand(1);
25298 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25299 // and change it to SUB and CMOV.
25300 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25301 N0.getOpcode() == ISD::ADD &&
25302 N0.getOperand(1) == N1 &&
25303 N1.getOpcode() == ISD::SRA &&
25304 N1.getOperand(0) == N0.getOperand(0))
25305 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25306 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25307 // Generate SUB & CMOV.
25308 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25309 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25311 SDValue Ops[] = { N0.getOperand(0), Neg,
25312 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25313 SDValue(Neg.getNode(), 1) };
25314 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25319 // Try to turn tests against the signbit in the form of:
25320 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25323 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25324 // This is only worth doing if the output type is i8.
25325 if (N->getValueType(0) != MVT::i8)
25328 SDValue N0 = N->getOperand(0);
25329 SDValue N1 = N->getOperand(1);
25331 // We should be performing an xor against a truncated shift.
25332 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25335 // Make sure we are performing an xor against one.
25336 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25339 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25340 SDValue Shift = N0.getOperand(0);
25341 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25344 // Make sure we are truncating from one of i16, i32 or i64.
25345 EVT ShiftTy = Shift.getValueType();
25346 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25349 // Make sure the shift amount extracts the sign bit.
25350 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25351 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25354 // Create a greater-than comparison against -1.
25355 // N.B. Using SETGE against 0 works but we want a canonical looking
25356 // comparison, using SETGT matches up with what TranslateX86CC.
25358 SDValue ShiftOp = Shift.getOperand(0);
25359 EVT ShiftOpTy = ShiftOp.getValueType();
25360 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25361 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25365 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25366 TargetLowering::DAGCombinerInfo &DCI,
25367 const X86Subtarget *Subtarget) {
25368 if (DCI.isBeforeLegalizeOps())
25371 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25374 if (Subtarget->hasCMov())
25375 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25378 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25384 /// This function detects the AVG pattern between vectors of unsigned i8/i16,
25385 /// which is c = (a + b + 1) / 2, and replace this operation with the efficient
25386 /// X86ISD::AVG instruction.
25387 static SDValue detectAVGPattern(SDValue In, EVT VT, SelectionDAG &DAG,
25388 const X86Subtarget *Subtarget, SDLoc DL) {
25389 if (!VT.isVector() || !VT.isSimple())
25391 EVT InVT = In.getValueType();
25392 unsigned NumElems = VT.getVectorNumElements();
25394 EVT ScalarVT = VT.getVectorElementType();
25395 if (!((ScalarVT == MVT::i8 || ScalarVT == MVT::i16) &&
25396 isPowerOf2_32(NumElems)))
25399 // InScalarVT is the intermediate type in AVG pattern and it should be greater
25400 // than the original input type (i8/i16).
25401 EVT InScalarVT = InVT.getVectorElementType();
25402 if (InScalarVT.getSizeInBits() <= ScalarVT.getSizeInBits())
25405 if (Subtarget->hasAVX512()) {
25406 if (VT.getSizeInBits() > 512)
25408 } else if (Subtarget->hasAVX2()) {
25409 if (VT.getSizeInBits() > 256)
25412 if (VT.getSizeInBits() > 128)
25416 // Detect the following pattern:
25418 // %1 = zext <N x i8> %a to <N x i32>
25419 // %2 = zext <N x i8> %b to <N x i32>
25420 // %3 = add nuw nsw <N x i32> %1, <i32 1 x N>
25421 // %4 = add nuw nsw <N x i32> %3, %2
25422 // %5 = lshr <N x i32> %N, <i32 1 x N>
25423 // %6 = trunc <N x i32> %5 to <N x i8>
25425 // In AVX512, the last instruction can also be a trunc store.
25427 if (In.getOpcode() != ISD::SRL)
25430 // A lambda checking the given SDValue is a constant vector and each element
25431 // is in the range [Min, Max].
25432 auto IsConstVectorInRange = [](SDValue V, unsigned Min, unsigned Max) {
25433 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(V);
25434 if (!BV || !BV->isConstant())
25436 for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
25437 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
25440 uint64_t Val = C->getZExtValue();
25441 if (Val < Min || Val > Max)
25447 // Check if each element of the vector is left-shifted by one.
25448 auto LHS = In.getOperand(0);
25449 auto RHS = In.getOperand(1);
25450 if (!IsConstVectorInRange(RHS, 1, 1))
25452 if (LHS.getOpcode() != ISD::ADD)
25455 // Detect a pattern of a + b + 1 where the order doesn't matter.
25456 SDValue Operands[3];
25457 Operands[0] = LHS.getOperand(0);
25458 Operands[1] = LHS.getOperand(1);
25460 // Take care of the case when one of the operands is a constant vector whose
25461 // element is in the range [1, 256].
25462 if (IsConstVectorInRange(Operands[1], 1, ScalarVT == MVT::i8 ? 256 : 65536) &&
25463 Operands[0].getOpcode() == ISD::ZERO_EXTEND &&
25464 Operands[0].getOperand(0).getValueType() == VT) {
25465 // The pattern is detected. Subtract one from the constant vector, then
25466 // demote it and emit X86ISD::AVG instruction.
25467 SDValue One = DAG.getConstant(1, DL, InScalarVT);
25468 SDValue Ones = DAG.getNode(ISD::BUILD_VECTOR, DL, InVT,
25469 SmallVector<SDValue, 8>(NumElems, One));
25470 Operands[1] = DAG.getNode(ISD::SUB, DL, InVT, Operands[1], Ones);
25471 Operands[1] = DAG.getNode(ISD::TRUNCATE, DL, VT, Operands[1]);
25472 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25476 if (Operands[0].getOpcode() == ISD::ADD)
25477 std::swap(Operands[0], Operands[1]);
25478 else if (Operands[1].getOpcode() != ISD::ADD)
25480 Operands[2] = Operands[1].getOperand(0);
25481 Operands[1] = Operands[1].getOperand(1);
25483 // Now we have three operands of two additions. Check that one of them is a
25484 // constant vector with ones, and the other two are promoted from i8/i16.
25485 for (int i = 0; i < 3; ++i) {
25486 if (!IsConstVectorInRange(Operands[i], 1, 1))
25488 std::swap(Operands[i], Operands[2]);
25490 // Check if Operands[0] and Operands[1] are results of type promotion.
25491 for (int j = 0; j < 2; ++j)
25492 if (Operands[j].getOpcode() != ISD::ZERO_EXTEND ||
25493 Operands[j].getOperand(0).getValueType() != VT)
25496 // The pattern is detected, emit X86ISD::AVG instruction.
25497 return DAG.getNode(X86ISD::AVG, DL, VT, Operands[0].getOperand(0),
25498 Operands[1].getOperand(0));
25504 static SDValue PerformTRUNCATECombine(SDNode *N, SelectionDAG &DAG,
25505 const X86Subtarget *Subtarget) {
25506 return detectAVGPattern(N->getOperand(0), N->getValueType(0), DAG, Subtarget,
25510 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25511 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25512 TargetLowering::DAGCombinerInfo &DCI,
25513 const X86Subtarget *Subtarget) {
25514 LoadSDNode *Ld = cast<LoadSDNode>(N);
25515 EVT RegVT = Ld->getValueType(0);
25516 EVT MemVT = Ld->getMemoryVT();
25518 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25520 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25521 // into two 16-byte operations.
25522 ISD::LoadExtType Ext = Ld->getExtensionType();
25524 unsigned AddressSpace = Ld->getAddressSpace();
25525 unsigned Alignment = Ld->getAlignment();
25526 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25527 Ext == ISD::NON_EXTLOAD &&
25528 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25529 AddressSpace, Alignment, &Fast) && !Fast) {
25530 unsigned NumElems = RegVT.getVectorNumElements();
25534 SDValue Ptr = Ld->getBasePtr();
25535 SDValue Increment =
25536 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25538 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25540 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25541 Ld->getPointerInfo(), Ld->isVolatile(),
25542 Ld->isNonTemporal(), Ld->isInvariant(),
25544 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25545 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25546 Ld->getPointerInfo(), Ld->isVolatile(),
25547 Ld->isNonTemporal(), Ld->isInvariant(),
25548 std::min(16U, Alignment));
25549 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25551 Load2.getValue(1));
25553 SDValue NewVec = DAG.getUNDEF(RegVT);
25554 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25555 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25556 return DCI.CombineTo(N, NewVec, TF, true);
25562 /// PerformMLOADCombine - Resolve extending loads
25563 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25564 TargetLowering::DAGCombinerInfo &DCI,
25565 const X86Subtarget *Subtarget) {
25566 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25567 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25570 EVT VT = Mld->getValueType(0);
25571 unsigned NumElems = VT.getVectorNumElements();
25572 EVT LdVT = Mld->getMemoryVT();
25575 assert(LdVT != VT && "Cannot extend to the same type");
25576 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25577 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25578 // From, To sizes and ElemCount must be pow of two
25579 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25580 "Unexpected size for extending masked load");
25582 unsigned SizeRatio = ToSz / FromSz;
25583 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25585 // Create a type on which we perform the shuffle
25586 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25587 LdVT.getScalarType(), NumElems*SizeRatio);
25588 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25590 // Convert Src0 value
25591 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25592 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25593 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25594 for (unsigned i = 0; i != NumElems; ++i)
25595 ShuffleVec[i] = i * SizeRatio;
25597 // Can't shuffle using an illegal type.
25598 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25599 "WideVecVT should be legal");
25600 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25601 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25603 // Prepare the new mask
25605 SDValue Mask = Mld->getMask();
25606 if (Mask.getValueType() == VT) {
25607 // Mask and original value have the same type
25608 NewMask = DAG.getBitcast(WideVecVT, Mask);
25609 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25610 for (unsigned i = 0; i != NumElems; ++i)
25611 ShuffleVec[i] = i * SizeRatio;
25612 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25613 ShuffleVec[i] = NumElems*SizeRatio;
25614 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25615 DAG.getConstant(0, dl, WideVecVT),
25619 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25620 unsigned WidenNumElts = NumElems*SizeRatio;
25621 unsigned MaskNumElts = VT.getVectorNumElements();
25622 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25625 unsigned NumConcat = WidenNumElts / MaskNumElts;
25626 SmallVector<SDValue, 16> Ops(NumConcat);
25627 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25629 for (unsigned i = 1; i != NumConcat; ++i)
25632 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25635 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25636 Mld->getBasePtr(), NewMask, WideSrc0,
25637 Mld->getMemoryVT(), Mld->getMemOperand(),
25639 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25640 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25642 /// PerformMSTORECombine - Resolve truncating stores
25643 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25644 const X86Subtarget *Subtarget) {
25645 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25646 if (!Mst->isTruncatingStore())
25649 EVT VT = Mst->getValue().getValueType();
25650 unsigned NumElems = VT.getVectorNumElements();
25651 EVT StVT = Mst->getMemoryVT();
25654 assert(StVT != VT && "Cannot truncate to the same type");
25655 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25656 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25658 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25660 // The truncating store is legal in some cases. For example
25661 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25662 // are designated for truncate store.
25663 // In this case we don't need any further transformations.
25664 if (TLI.isTruncStoreLegal(VT, StVT))
25667 // From, To sizes and ElemCount must be pow of two
25668 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25669 "Unexpected size for truncating masked store");
25670 // We are going to use the original vector elt for storing.
25671 // Accumulated smaller vector elements must be a multiple of the store size.
25672 assert (((NumElems * FromSz) % ToSz) == 0 &&
25673 "Unexpected ratio for truncating masked store");
25675 unsigned SizeRatio = FromSz / ToSz;
25676 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25678 // Create a type on which we perform the shuffle
25679 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25680 StVT.getScalarType(), NumElems*SizeRatio);
25682 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25684 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25685 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25686 for (unsigned i = 0; i != NumElems; ++i)
25687 ShuffleVec[i] = i * SizeRatio;
25689 // Can't shuffle using an illegal type.
25690 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25691 "WideVecVT should be legal");
25693 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25694 DAG.getUNDEF(WideVecVT),
25698 SDValue Mask = Mst->getMask();
25699 if (Mask.getValueType() == VT) {
25700 // Mask and original value have the same type
25701 NewMask = DAG.getBitcast(WideVecVT, Mask);
25702 for (unsigned i = 0; i != NumElems; ++i)
25703 ShuffleVec[i] = i * SizeRatio;
25704 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25705 ShuffleVec[i] = NumElems*SizeRatio;
25706 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25707 DAG.getConstant(0, dl, WideVecVT),
25711 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25712 unsigned WidenNumElts = NumElems*SizeRatio;
25713 unsigned MaskNumElts = VT.getVectorNumElements();
25714 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25717 unsigned NumConcat = WidenNumElts / MaskNumElts;
25718 SmallVector<SDValue, 16> Ops(NumConcat);
25719 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25721 for (unsigned i = 1; i != NumConcat; ++i)
25724 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25727 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25728 NewMask, StVT, Mst->getMemOperand(), false);
25730 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25731 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25732 const X86Subtarget *Subtarget) {
25733 StoreSDNode *St = cast<StoreSDNode>(N);
25734 EVT VT = St->getValue().getValueType();
25735 EVT StVT = St->getMemoryVT();
25737 SDValue StoredVal = St->getOperand(1);
25738 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25740 // If we are saving a concatenation of two XMM registers and 32-byte stores
25741 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25743 unsigned AddressSpace = St->getAddressSpace();
25744 unsigned Alignment = St->getAlignment();
25745 if (VT.is256BitVector() && StVT == VT &&
25746 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25747 AddressSpace, Alignment, &Fast) && !Fast) {
25748 unsigned NumElems = VT.getVectorNumElements();
25752 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25753 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25756 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25757 SDValue Ptr0 = St->getBasePtr();
25758 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25760 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25761 St->getPointerInfo(), St->isVolatile(),
25762 St->isNonTemporal(), Alignment);
25763 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25764 St->getPointerInfo(), St->isVolatile(),
25765 St->isNonTemporal(),
25766 std::min(16U, Alignment));
25767 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25770 // Optimize trunc store (of multiple scalars) to shuffle and store.
25771 // First, pack all of the elements in one place. Next, store to memory
25772 // in fewer chunks.
25773 if (St->isTruncatingStore() && VT.isVector()) {
25774 // Check if we can detect an AVG pattern from the truncation. If yes,
25775 // replace the trunc store by a normal store with the result of X86ISD::AVG
25778 detectAVGPattern(St->getValue(), St->getMemoryVT(), DAG, Subtarget, dl);
25780 return DAG.getStore(St->getChain(), dl, Avg, St->getBasePtr(),
25781 St->getPointerInfo(), St->isVolatile(),
25782 St->isNonTemporal(), St->getAlignment());
25784 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25785 unsigned NumElems = VT.getVectorNumElements();
25786 assert(StVT != VT && "Cannot truncate to the same type");
25787 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25788 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25790 // The truncating store is legal in some cases. For example
25791 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25792 // are designated for truncate store.
25793 // In this case we don't need any further transformations.
25794 if (TLI.isTruncStoreLegal(VT, StVT))
25797 // From, To sizes and ElemCount must be pow of two
25798 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25799 // We are going to use the original vector elt for storing.
25800 // Accumulated smaller vector elements must be a multiple of the store size.
25801 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25803 unsigned SizeRatio = FromSz / ToSz;
25805 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25807 // Create a type on which we perform the shuffle
25808 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25809 StVT.getScalarType(), NumElems*SizeRatio);
25811 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25813 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25814 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25815 for (unsigned i = 0; i != NumElems; ++i)
25816 ShuffleVec[i] = i * SizeRatio;
25818 // Can't shuffle using an illegal type.
25819 if (!TLI.isTypeLegal(WideVecVT))
25822 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25823 DAG.getUNDEF(WideVecVT),
25825 // At this point all of the data is stored at the bottom of the
25826 // register. We now need to save it to mem.
25828 // Find the largest store unit
25829 MVT StoreType = MVT::i8;
25830 for (MVT Tp : MVT::integer_valuetypes()) {
25831 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25835 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25836 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25837 (64 <= NumElems * ToSz))
25838 StoreType = MVT::f64;
25840 // Bitcast the original vector into a vector of store-size units
25841 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25842 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25843 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25844 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25845 SmallVector<SDValue, 8> Chains;
25846 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25847 TLI.getPointerTy(DAG.getDataLayout()));
25848 SDValue Ptr = St->getBasePtr();
25850 // Perform one or more big stores into memory.
25851 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25852 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25853 StoreType, ShuffWide,
25854 DAG.getIntPtrConstant(i, dl));
25855 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25856 St->getPointerInfo(), St->isVolatile(),
25857 St->isNonTemporal(), St->getAlignment());
25858 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25859 Chains.push_back(Ch);
25862 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25865 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25866 // the FP state in cases where an emms may be missing.
25867 // A preferable solution to the general problem is to figure out the right
25868 // places to insert EMMS. This qualifies as a quick hack.
25870 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25871 if (VT.getSizeInBits() != 64)
25874 const Function *F = DAG.getMachineFunction().getFunction();
25875 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25877 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25878 if ((VT.isVector() ||
25879 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25880 isa<LoadSDNode>(St->getValue()) &&
25881 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25882 St->getChain().hasOneUse() && !St->isVolatile()) {
25883 SDNode* LdVal = St->getValue().getNode();
25884 LoadSDNode *Ld = nullptr;
25885 int TokenFactorIndex = -1;
25886 SmallVector<SDValue, 8> Ops;
25887 SDNode* ChainVal = St->getChain().getNode();
25888 // Must be a store of a load. We currently handle two cases: the load
25889 // is a direct child, and it's under an intervening TokenFactor. It is
25890 // possible to dig deeper under nested TokenFactors.
25891 if (ChainVal == LdVal)
25892 Ld = cast<LoadSDNode>(St->getChain());
25893 else if (St->getValue().hasOneUse() &&
25894 ChainVal->getOpcode() == ISD::TokenFactor) {
25895 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25896 if (ChainVal->getOperand(i).getNode() == LdVal) {
25897 TokenFactorIndex = i;
25898 Ld = cast<LoadSDNode>(St->getValue());
25900 Ops.push_back(ChainVal->getOperand(i));
25904 if (!Ld || !ISD::isNormalLoad(Ld))
25907 // If this is not the MMX case, i.e. we are just turning i64 load/store
25908 // into f64 load/store, avoid the transformation if there are multiple
25909 // uses of the loaded value.
25910 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25915 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25916 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25918 if (Subtarget->is64Bit() || F64IsLegal) {
25919 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25920 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25921 Ld->getPointerInfo(), Ld->isVolatile(),
25922 Ld->isNonTemporal(), Ld->isInvariant(),
25923 Ld->getAlignment());
25924 SDValue NewChain = NewLd.getValue(1);
25925 if (TokenFactorIndex != -1) {
25926 Ops.push_back(NewChain);
25927 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25929 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25930 St->getPointerInfo(),
25931 St->isVolatile(), St->isNonTemporal(),
25932 St->getAlignment());
25935 // Otherwise, lower to two pairs of 32-bit loads / stores.
25936 SDValue LoAddr = Ld->getBasePtr();
25937 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25938 DAG.getConstant(4, LdDL, MVT::i32));
25940 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25941 Ld->getPointerInfo(),
25942 Ld->isVolatile(), Ld->isNonTemporal(),
25943 Ld->isInvariant(), Ld->getAlignment());
25944 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25945 Ld->getPointerInfo().getWithOffset(4),
25946 Ld->isVolatile(), Ld->isNonTemporal(),
25948 MinAlign(Ld->getAlignment(), 4));
25950 SDValue NewChain = LoLd.getValue(1);
25951 if (TokenFactorIndex != -1) {
25952 Ops.push_back(LoLd);
25953 Ops.push_back(HiLd);
25954 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25957 LoAddr = St->getBasePtr();
25958 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25959 DAG.getConstant(4, StDL, MVT::i32));
25961 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25962 St->getPointerInfo(),
25963 St->isVolatile(), St->isNonTemporal(),
25964 St->getAlignment());
25965 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25966 St->getPointerInfo().getWithOffset(4),
25968 St->isNonTemporal(),
25969 MinAlign(St->getAlignment(), 4));
25970 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25973 // This is similar to the above case, but here we handle a scalar 64-bit
25974 // integer store that is extracted from a vector on a 32-bit target.
25975 // If we have SSE2, then we can treat it like a floating-point double
25976 // to get past legalization. The execution dependencies fixup pass will
25977 // choose the optimal machine instruction for the store if this really is
25978 // an integer or v2f32 rather than an f64.
25979 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25980 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25981 SDValue OldExtract = St->getOperand(1);
25982 SDValue ExtOp0 = OldExtract.getOperand(0);
25983 unsigned VecSize = ExtOp0.getValueSizeInBits();
25984 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25985 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25986 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25987 BitCast, OldExtract.getOperand(1));
25988 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25989 St->getPointerInfo(), St->isVolatile(),
25990 St->isNonTemporal(), St->getAlignment());
25996 /// Return 'true' if this vector operation is "horizontal"
25997 /// and return the operands for the horizontal operation in LHS and RHS. A
25998 /// horizontal operation performs the binary operation on successive elements
25999 /// of its first operand, then on successive elements of its second operand,
26000 /// returning the resulting values in a vector. For example, if
26001 /// A = < float a0, float a1, float a2, float a3 >
26003 /// B = < float b0, float b1, float b2, float b3 >
26004 /// then the result of doing a horizontal operation on A and B is
26005 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
26006 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
26007 /// A horizontal-op B, for some already available A and B, and if so then LHS is
26008 /// set to A, RHS to B, and the routine returns 'true'.
26009 /// Note that the binary operation should have the property that if one of the
26010 /// operands is UNDEF then the result is UNDEF.
26011 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
26012 // Look for the following pattern: if
26013 // A = < float a0, float a1, float a2, float a3 >
26014 // B = < float b0, float b1, float b2, float b3 >
26016 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
26017 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
26018 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
26019 // which is A horizontal-op B.
26021 // At least one of the operands should be a vector shuffle.
26022 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
26023 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
26026 MVT VT = LHS.getSimpleValueType();
26028 assert((VT.is128BitVector() || VT.is256BitVector()) &&
26029 "Unsupported vector type for horizontal add/sub");
26031 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
26032 // operate independently on 128-bit lanes.
26033 unsigned NumElts = VT.getVectorNumElements();
26034 unsigned NumLanes = VT.getSizeInBits()/128;
26035 unsigned NumLaneElts = NumElts / NumLanes;
26036 assert((NumLaneElts % 2 == 0) &&
26037 "Vector type should have an even number of elements in each lane");
26038 unsigned HalfLaneElts = NumLaneElts/2;
26040 // View LHS in the form
26041 // LHS = VECTOR_SHUFFLE A, B, LMask
26042 // If LHS is not a shuffle then pretend it is the shuffle
26043 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
26044 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
26047 SmallVector<int, 16> LMask(NumElts);
26048 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26049 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
26050 A = LHS.getOperand(0);
26051 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
26052 B = LHS.getOperand(1);
26053 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
26054 std::copy(Mask.begin(), Mask.end(), LMask.begin());
26056 if (LHS.getOpcode() != ISD::UNDEF)
26058 for (unsigned i = 0; i != NumElts; ++i)
26062 // Likewise, view RHS in the form
26063 // RHS = VECTOR_SHUFFLE C, D, RMask
26065 SmallVector<int, 16> RMask(NumElts);
26066 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
26067 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
26068 C = RHS.getOperand(0);
26069 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
26070 D = RHS.getOperand(1);
26071 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
26072 std::copy(Mask.begin(), Mask.end(), RMask.begin());
26074 if (RHS.getOpcode() != ISD::UNDEF)
26076 for (unsigned i = 0; i != NumElts; ++i)
26080 // Check that the shuffles are both shuffling the same vectors.
26081 if (!(A == C && B == D) && !(A == D && B == C))
26084 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
26085 if (!A.getNode() && !B.getNode())
26088 // If A and B occur in reverse order in RHS, then "swap" them (which means
26089 // rewriting the mask).
26091 ShuffleVectorSDNode::commuteMask(RMask);
26093 // At this point LHS and RHS are equivalent to
26094 // LHS = VECTOR_SHUFFLE A, B, LMask
26095 // RHS = VECTOR_SHUFFLE A, B, RMask
26096 // Check that the masks correspond to performing a horizontal operation.
26097 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
26098 for (unsigned i = 0; i != NumLaneElts; ++i) {
26099 int LIdx = LMask[i+l], RIdx = RMask[i+l];
26101 // Ignore any UNDEF components.
26102 if (LIdx < 0 || RIdx < 0 ||
26103 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
26104 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
26107 // Check that successive elements are being operated on. If not, this is
26108 // not a horizontal operation.
26109 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
26110 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
26111 if (!(LIdx == Index && RIdx == Index + 1) &&
26112 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
26117 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
26118 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
26122 /// Do target-specific dag combines on floating point adds.
26123 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
26124 const X86Subtarget *Subtarget) {
26125 EVT VT = N->getValueType(0);
26126 SDValue LHS = N->getOperand(0);
26127 SDValue RHS = N->getOperand(1);
26129 // Try to synthesize horizontal adds from adds of shuffles.
26130 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26131 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26132 isHorizontalBinOp(LHS, RHS, true))
26133 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
26137 /// Do target-specific dag combines on floating point subs.
26138 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
26139 const X86Subtarget *Subtarget) {
26140 EVT VT = N->getValueType(0);
26141 SDValue LHS = N->getOperand(0);
26142 SDValue RHS = N->getOperand(1);
26144 // Try to synthesize horizontal subs from subs of shuffles.
26145 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
26146 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
26147 isHorizontalBinOp(LHS, RHS, false))
26148 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
26152 /// Do target-specific dag combines on floating point negations.
26153 static SDValue PerformFNEGCombine(SDNode *N, SelectionDAG &DAG,
26154 const X86Subtarget *Subtarget) {
26155 EVT VT = N->getValueType(0);
26156 SDValue Arg = N->getOperand(0);
26158 // If we're negating a FMA node, then we can adjust the
26159 // instruction to include the extra negation.
26160 if (Arg.hasOneUse()) {
26161 switch (Arg.getOpcode()) {
26162 case X86ISD::FMADD:
26163 return DAG.getNode(X86ISD::FNMSUB, SDLoc(N), VT, Arg.getOperand(0),
26164 Arg.getOperand(1), Arg.getOperand(2));
26165 case X86ISD::FMSUB:
26166 return DAG.getNode(X86ISD::FNMADD, SDLoc(N), VT, Arg.getOperand(0),
26167 Arg.getOperand(1), Arg.getOperand(2));
26168 case X86ISD::FNMADD:
26169 return DAG.getNode(X86ISD::FMSUB, SDLoc(N), VT, Arg.getOperand(0),
26170 Arg.getOperand(1), Arg.getOperand(2));
26171 case X86ISD::FNMSUB:
26172 return DAG.getNode(X86ISD::FMADD, SDLoc(N), VT, Arg.getOperand(0),
26173 Arg.getOperand(1), Arg.getOperand(2));
26179 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
26180 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
26181 const X86Subtarget *Subtarget) {
26182 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
26184 // F[X]OR(0.0, x) -> x
26185 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26186 if (C->getValueAPF().isPosZero())
26187 return N->getOperand(1);
26189 // F[X]OR(x, 0.0) -> x
26190 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26191 if (C->getValueAPF().isPosZero())
26192 return N->getOperand(0);
26194 EVT VT = N->getValueType(0);
26195 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
26197 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
26198 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
26200 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
26201 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
26202 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
26203 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
26204 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
26209 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
26210 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
26211 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
26213 // Only perform optimizations if UnsafeMath is used.
26214 if (!DAG.getTarget().Options.UnsafeFPMath)
26217 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
26218 // into FMINC and FMAXC, which are Commutative operations.
26219 unsigned NewOp = 0;
26220 switch (N->getOpcode()) {
26221 default: llvm_unreachable("unknown opcode");
26222 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
26223 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
26226 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
26227 N->getOperand(0), N->getOperand(1));
26230 /// Do target-specific dag combines on X86ISD::FAND nodes.
26231 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
26232 // FAND(0.0, x) -> 0.0
26233 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26234 if (C->getValueAPF().isPosZero())
26235 return N->getOperand(0);
26237 // FAND(x, 0.0) -> 0.0
26238 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26239 if (C->getValueAPF().isPosZero())
26240 return N->getOperand(1);
26245 /// Do target-specific dag combines on X86ISD::FANDN nodes
26246 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
26247 // FANDN(0.0, x) -> x
26248 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
26249 if (C->getValueAPF().isPosZero())
26250 return N->getOperand(1);
26252 // FANDN(x, 0.0) -> 0.0
26253 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
26254 if (C->getValueAPF().isPosZero())
26255 return N->getOperand(1);
26260 static SDValue PerformBTCombine(SDNode *N,
26262 TargetLowering::DAGCombinerInfo &DCI) {
26263 // BT ignores high bits in the bit index operand.
26264 SDValue Op1 = N->getOperand(1);
26265 if (Op1.hasOneUse()) {
26266 unsigned BitWidth = Op1.getValueSizeInBits();
26267 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
26268 APInt KnownZero, KnownOne;
26269 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
26270 !DCI.isBeforeLegalizeOps());
26271 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26272 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
26273 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
26274 DCI.CommitTargetLoweringOpt(TLO);
26279 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
26280 SDValue Op = N->getOperand(0);
26281 if (Op.getOpcode() == ISD::BITCAST)
26282 Op = Op.getOperand(0);
26283 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
26284 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
26285 VT.getVectorElementType().getSizeInBits() ==
26286 OpVT.getVectorElementType().getSizeInBits()) {
26287 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
26292 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
26293 const X86Subtarget *Subtarget) {
26294 EVT VT = N->getValueType(0);
26295 if (!VT.isVector())
26298 SDValue N0 = N->getOperand(0);
26299 SDValue N1 = N->getOperand(1);
26300 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
26303 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
26304 // both SSE and AVX2 since there is no sign-extended shift right
26305 // operation on a vector with 64-bit elements.
26306 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
26307 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
26308 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
26309 N0.getOpcode() == ISD::SIGN_EXTEND)) {
26310 SDValue N00 = N0.getOperand(0);
26312 // EXTLOAD has a better solution on AVX2,
26313 // it may be replaced with X86ISD::VSEXT node.
26314 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
26315 if (!ISD::isNormalLoad(N00.getNode()))
26318 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
26319 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
26321 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
26327 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
26328 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
26329 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
26330 /// eliminate extend, add, and shift instructions.
26331 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
26332 const X86Subtarget *Subtarget) {
26333 // TODO: This should be valid for other integer types.
26334 EVT VT = Sext->getValueType(0);
26335 if (VT != MVT::i64)
26338 // We need an 'add nsw' feeding into the 'sext'.
26339 SDValue Add = Sext->getOperand(0);
26340 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
26343 // Having a constant operand to the 'add' ensures that we are not increasing
26344 // the instruction count because the constant is extended for free below.
26345 // A constant operand can also become the displacement field of an LEA.
26346 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
26350 // Don't make the 'add' bigger if there's no hope of combining it with some
26351 // other 'add' or 'shl' instruction.
26352 // TODO: It may be profitable to generate simpler LEA instructions in place
26353 // of single 'add' instructions, but the cost model for selecting an LEA
26354 // currently has a high threshold.
26355 bool HasLEAPotential = false;
26356 for (auto *User : Sext->uses()) {
26357 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
26358 HasLEAPotential = true;
26362 if (!HasLEAPotential)
26365 // Everything looks good, so pull the 'sext' ahead of the 'add'.
26366 int64_t AddConstant = AddOp1->getSExtValue();
26367 SDValue AddOp0 = Add.getOperand(0);
26368 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
26369 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
26371 // The wider add is guaranteed to not wrap because both operands are
26374 Flags.setNoSignedWrap(true);
26375 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
26378 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
26379 TargetLowering::DAGCombinerInfo &DCI,
26380 const X86Subtarget *Subtarget) {
26381 SDValue N0 = N->getOperand(0);
26382 EVT VT = N->getValueType(0);
26383 EVT SVT = VT.getScalarType();
26384 EVT InVT = N0.getValueType();
26385 EVT InSVT = InVT.getScalarType();
26388 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
26389 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
26390 // This exposes the sext to the sdivrem lowering, so that it directly extends
26391 // from AH (which we otherwise need to do contortions to access).
26392 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
26393 InVT == MVT::i8 && VT == MVT::i32) {
26394 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26395 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
26396 N0.getOperand(0), N0.getOperand(1));
26397 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26398 return R.getValue(1);
26401 if (!DCI.isBeforeLegalizeOps()) {
26402 if (InVT == MVT::i1) {
26403 SDValue Zero = DAG.getConstant(0, DL, VT);
26405 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
26406 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
26411 if (VT.isVector() && Subtarget->hasSSE2()) {
26412 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
26413 EVT InVT = N.getValueType();
26414 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
26415 Size / InVT.getScalarSizeInBits());
26416 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
26417 DAG.getUNDEF(InVT));
26419 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
26422 // If target-size is less than 128-bits, extend to a type that would extend
26423 // to 128 bits, extend that and extract the original target vector.
26424 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
26425 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26426 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26427 unsigned Scale = 128 / VT.getSizeInBits();
26429 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
26430 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
26431 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
26432 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
26433 DAG.getIntPtrConstant(0, DL));
26436 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
26437 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
26438 if (VT.getSizeInBits() == 128 &&
26439 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26440 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26441 SDValue ExOp = ExtendVecSize(DL, N0, 128);
26442 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
26445 // On pre-AVX2 targets, split into 128-bit nodes of
26446 // ISD::SIGN_EXTEND_VECTOR_INREG.
26447 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
26448 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
26449 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
26450 unsigned NumVecs = VT.getSizeInBits() / 128;
26451 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26452 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26453 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26455 SmallVector<SDValue, 8> Opnds;
26456 for (unsigned i = 0, Offset = 0; i != NumVecs;
26457 ++i, Offset += NumSubElts) {
26458 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26459 DAG.getIntPtrConstant(Offset, DL));
26460 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26461 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26462 Opnds.push_back(SrcVec);
26464 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26468 if (Subtarget->hasAVX() && VT.is256BitVector())
26469 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26472 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26478 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26479 const X86Subtarget* Subtarget) {
26481 EVT VT = N->getValueType(0);
26483 // Let legalize expand this if it isn't a legal type yet.
26484 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26487 EVT ScalarVT = VT.getScalarType();
26488 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26489 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26490 !Subtarget->hasAVX512()))
26493 SDValue A = N->getOperand(0);
26494 SDValue B = N->getOperand(1);
26495 SDValue C = N->getOperand(2);
26497 bool NegA = (A.getOpcode() == ISD::FNEG);
26498 bool NegB = (B.getOpcode() == ISD::FNEG);
26499 bool NegC = (C.getOpcode() == ISD::FNEG);
26501 // Negative multiplication when NegA xor NegB
26502 bool NegMul = (NegA != NegB);
26504 A = A.getOperand(0);
26506 B = B.getOperand(0);
26508 C = C.getOperand(0);
26512 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26514 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26516 return DAG.getNode(Opcode, dl, VT, A, B, C);
26519 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26520 TargetLowering::DAGCombinerInfo &DCI,
26521 const X86Subtarget *Subtarget) {
26522 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26523 // (and (i32 x86isd::setcc_carry), 1)
26524 // This eliminates the zext. This transformation is necessary because
26525 // ISD::SETCC is always legalized to i8.
26527 SDValue N0 = N->getOperand(0);
26528 EVT VT = N->getValueType(0);
26530 if (N0.getOpcode() == ISD::AND &&
26532 N0.getOperand(0).hasOneUse()) {
26533 SDValue N00 = N0.getOperand(0);
26534 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26535 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26536 if (!C || C->getZExtValue() != 1)
26538 return DAG.getNode(ISD::AND, dl, VT,
26539 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26540 N00.getOperand(0), N00.getOperand(1)),
26541 DAG.getConstant(1, dl, VT));
26545 if (N0.getOpcode() == ISD::TRUNCATE &&
26547 N0.getOperand(0).hasOneUse()) {
26548 SDValue N00 = N0.getOperand(0);
26549 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26550 return DAG.getNode(ISD::AND, dl, VT,
26551 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26552 N00.getOperand(0), N00.getOperand(1)),
26553 DAG.getConstant(1, dl, VT));
26557 if (VT.is256BitVector())
26558 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26561 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26562 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26563 // This exposes the zext to the udivrem lowering, so that it directly extends
26564 // from AH (which we otherwise need to do contortions to access).
26565 if (N0.getOpcode() == ISD::UDIVREM &&
26566 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26567 (VT == MVT::i32 || VT == MVT::i64)) {
26568 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26569 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26570 N0.getOperand(0), N0.getOperand(1));
26571 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26572 return R.getValue(1);
26578 // Optimize x == -y --> x+y == 0
26579 // x != -y --> x+y != 0
26580 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26581 const X86Subtarget* Subtarget) {
26582 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26583 SDValue LHS = N->getOperand(0);
26584 SDValue RHS = N->getOperand(1);
26585 EVT VT = N->getValueType(0);
26588 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26589 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26590 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26591 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26592 LHS.getOperand(1));
26593 return DAG.getSetCC(DL, N->getValueType(0), addV,
26594 DAG.getConstant(0, DL, addV.getValueType()), CC);
26596 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26597 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26598 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26599 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26600 RHS.getOperand(1));
26601 return DAG.getSetCC(DL, N->getValueType(0), addV,
26602 DAG.getConstant(0, DL, addV.getValueType()), CC);
26605 if (VT.getScalarType() == MVT::i1 &&
26606 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26608 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26609 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26610 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26612 if (!IsSEXT0 || !IsVZero1) {
26613 // Swap the operands and update the condition code.
26614 std::swap(LHS, RHS);
26615 CC = ISD::getSetCCSwappedOperands(CC);
26617 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26618 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26619 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26622 if (IsSEXT0 && IsVZero1) {
26623 assert(VT == LHS.getOperand(0).getValueType() &&
26624 "Uexpected operand type");
26625 if (CC == ISD::SETGT)
26626 return DAG.getConstant(0, DL, VT);
26627 if (CC == ISD::SETLE)
26628 return DAG.getConstant(1, DL, VT);
26629 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26630 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26632 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26633 "Unexpected condition code!");
26634 return LHS.getOperand(0);
26641 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26642 SDValue V0 = N->getOperand(0);
26643 SDValue V1 = N->getOperand(1);
26645 EVT VT = N->getValueType(0);
26647 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26648 // operands and changing the mask to 1. This saves us a bunch of
26649 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26650 // x86InstrInfo knows how to commute this back after instruction selection
26651 // if it would help register allocation.
26653 // TODO: If optimizing for size or a processor that doesn't suffer from
26654 // partial register update stalls, this should be transformed into a MOVSD
26655 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26657 if (VT == MVT::v2f64)
26658 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26659 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26660 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26661 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26667 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26668 // as "sbb reg,reg", since it can be extended without zext and produces
26669 // an all-ones bit which is more useful than 0/1 in some cases.
26670 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26673 return DAG.getNode(ISD::AND, DL, VT,
26674 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26675 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26677 DAG.getConstant(1, DL, VT));
26678 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26679 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26680 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26681 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26685 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26686 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26687 TargetLowering::DAGCombinerInfo &DCI,
26688 const X86Subtarget *Subtarget) {
26690 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26691 SDValue EFLAGS = N->getOperand(1);
26693 if (CC == X86::COND_A) {
26694 // Try to convert COND_A into COND_B in an attempt to facilitate
26695 // materializing "setb reg".
26697 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26698 // cannot take an immediate as its first operand.
26700 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26701 EFLAGS.getValueType().isInteger() &&
26702 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26703 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26704 EFLAGS.getNode()->getVTList(),
26705 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26706 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26707 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26711 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26712 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26714 if (CC == X86::COND_B)
26715 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26717 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26718 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26719 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26725 // Optimize branch condition evaluation.
26727 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26728 TargetLowering::DAGCombinerInfo &DCI,
26729 const X86Subtarget *Subtarget) {
26731 SDValue Chain = N->getOperand(0);
26732 SDValue Dest = N->getOperand(1);
26733 SDValue EFLAGS = N->getOperand(3);
26734 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26736 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26737 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26738 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26745 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26746 SelectionDAG &DAG) {
26747 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26748 // optimize away operation when it's from a constant.
26750 // The general transformation is:
26751 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26752 // AND(VECTOR_CMP(x,y), constant2)
26753 // constant2 = UNARYOP(constant)
26755 // Early exit if this isn't a vector operation, the operand of the
26756 // unary operation isn't a bitwise AND, or if the sizes of the operations
26757 // aren't the same.
26758 EVT VT = N->getValueType(0);
26759 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26760 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26761 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26764 // Now check that the other operand of the AND is a constant. We could
26765 // make the transformation for non-constant splats as well, but it's unclear
26766 // that would be a benefit as it would not eliminate any operations, just
26767 // perform one more step in scalar code before moving to the vector unit.
26768 if (BuildVectorSDNode *BV =
26769 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26770 // Bail out if the vector isn't a constant.
26771 if (!BV->isConstant())
26774 // Everything checks out. Build up the new and improved node.
26776 EVT IntVT = BV->getValueType(0);
26777 // Create a new constant of the appropriate type for the transformed
26779 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26780 // The AND node needs bitcasts to/from an integer vector type around it.
26781 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26782 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26783 N->getOperand(0)->getOperand(0), MaskConst);
26784 SDValue Res = DAG.getBitcast(VT, NewAnd);
26791 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26792 const X86Subtarget *Subtarget) {
26793 SDValue Op0 = N->getOperand(0);
26794 EVT VT = N->getValueType(0);
26795 EVT InVT = Op0.getValueType();
26796 EVT InSVT = InVT.getScalarType();
26797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26799 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26800 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26801 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26803 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26804 InVT.getVectorNumElements());
26805 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26807 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26808 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26810 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26816 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26817 const X86Subtarget *Subtarget) {
26818 // First try to optimize away the conversion entirely when it's
26819 // conditionally from a constant. Vectors only.
26820 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26823 // Now move on to more general possibilities.
26824 SDValue Op0 = N->getOperand(0);
26825 EVT VT = N->getValueType(0);
26826 EVT InVT = Op0.getValueType();
26827 EVT InSVT = InVT.getScalarType();
26829 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26830 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26831 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26833 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26834 InVT.getVectorNumElements());
26835 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26836 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26839 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26840 // a 32-bit target where SSE doesn't support i64->FP operations.
26841 if (!Subtarget->useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
26842 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26843 EVT LdVT = Ld->getValueType(0);
26845 // This transformation is not supported if the result type is f16
26846 if (VT == MVT::f16)
26849 if (!Ld->isVolatile() && !VT.isVector() &&
26850 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26851 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26852 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26853 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26854 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26861 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26862 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26863 X86TargetLowering::DAGCombinerInfo &DCI) {
26864 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26865 // the result is either zero or one (depending on the input carry bit).
26866 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26867 if (X86::isZeroNode(N->getOperand(0)) &&
26868 X86::isZeroNode(N->getOperand(1)) &&
26869 // We don't have a good way to replace an EFLAGS use, so only do this when
26871 SDValue(N, 1).use_empty()) {
26873 EVT VT = N->getValueType(0);
26874 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26875 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26876 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26877 DAG.getConstant(X86::COND_B, DL,
26880 DAG.getConstant(1, DL, VT));
26881 return DCI.CombineTo(N, Res1, CarryOut);
26887 // fold (add Y, (sete X, 0)) -> adc 0, Y
26888 // (add Y, (setne X, 0)) -> sbb -1, Y
26889 // (sub (sete X, 0), Y) -> sbb 0, Y
26890 // (sub (setne X, 0), Y) -> adc -1, Y
26891 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26894 // Look through ZExts.
26895 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26896 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26899 SDValue SetCC = Ext.getOperand(0);
26900 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26903 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26904 if (CC != X86::COND_E && CC != X86::COND_NE)
26907 SDValue Cmp = SetCC.getOperand(1);
26908 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26909 !X86::isZeroNode(Cmp.getOperand(1)) ||
26910 !Cmp.getOperand(0).getValueType().isInteger())
26913 SDValue CmpOp0 = Cmp.getOperand(0);
26914 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26915 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26917 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26918 if (CC == X86::COND_NE)
26919 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26920 DL, OtherVal.getValueType(), OtherVal,
26921 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26923 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26924 DL, OtherVal.getValueType(), OtherVal,
26925 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26928 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26929 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26930 const X86Subtarget *Subtarget) {
26931 EVT VT = N->getValueType(0);
26932 SDValue Op0 = N->getOperand(0);
26933 SDValue Op1 = N->getOperand(1);
26935 // Try to synthesize horizontal adds from adds of shuffles.
26936 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26937 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26938 isHorizontalBinOp(Op0, Op1, true))
26939 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26941 return OptimizeConditionalInDecrement(N, DAG);
26944 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26945 const X86Subtarget *Subtarget) {
26946 SDValue Op0 = N->getOperand(0);
26947 SDValue Op1 = N->getOperand(1);
26949 // X86 can't encode an immediate LHS of a sub. See if we can push the
26950 // negation into a preceding instruction.
26951 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26952 // If the RHS of the sub is a XOR with one use and a constant, invert the
26953 // immediate. Then add one to the LHS of the sub so we can turn
26954 // X-Y -> X+~Y+1, saving one register.
26955 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26956 isa<ConstantSDNode>(Op1.getOperand(1))) {
26957 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26958 EVT VT = Op0.getValueType();
26959 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26961 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26962 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26963 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26967 // Try to synthesize horizontal adds from adds of shuffles.
26968 EVT VT = N->getValueType(0);
26969 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26970 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26971 isHorizontalBinOp(Op0, Op1, true))
26972 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26974 return OptimizeConditionalInDecrement(N, DAG);
26977 /// performVZEXTCombine - Performs build vector combines
26978 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26979 TargetLowering::DAGCombinerInfo &DCI,
26980 const X86Subtarget *Subtarget) {
26982 MVT VT = N->getSimpleValueType(0);
26983 SDValue Op = N->getOperand(0);
26984 MVT OpVT = Op.getSimpleValueType();
26985 MVT OpEltVT = OpVT.getVectorElementType();
26986 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26988 // (vzext (bitcast (vzext (x)) -> (vzext x)
26990 while (V.getOpcode() == ISD::BITCAST)
26991 V = V.getOperand(0);
26993 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26994 MVT InnerVT = V.getSimpleValueType();
26995 MVT InnerEltVT = InnerVT.getVectorElementType();
26997 // If the element sizes match exactly, we can just do one larger vzext. This
26998 // is always an exact type match as vzext operates on integer types.
26999 if (OpEltVT == InnerEltVT) {
27000 assert(OpVT == InnerVT && "Types must match for vzext!");
27001 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
27004 // The only other way we can combine them is if only a single element of the
27005 // inner vzext is used in the input to the outer vzext.
27006 if (InnerEltVT.getSizeInBits() < InputBits)
27009 // In this case, the inner vzext is completely dead because we're going to
27010 // only look at bits inside of the low element. Just do the outer vzext on
27011 // a bitcast of the input to the inner.
27012 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
27015 // Check if we can bypass extracting and re-inserting an element of an input
27016 // vector. Essentially:
27017 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
27018 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
27019 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
27020 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
27021 SDValue ExtractedV = V.getOperand(0);
27022 SDValue OrigV = ExtractedV.getOperand(0);
27023 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
27024 if (ExtractIdx->getZExtValue() == 0) {
27025 MVT OrigVT = OrigV.getSimpleValueType();
27026 // Extract a subvector if necessary...
27027 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
27028 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
27029 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
27030 OrigVT.getVectorNumElements() / Ratio);
27031 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
27032 DAG.getIntPtrConstant(0, DL));
27034 Op = DAG.getBitcast(OpVT, OrigV);
27035 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
27042 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
27043 DAGCombinerInfo &DCI) const {
27044 SelectionDAG &DAG = DCI.DAG;
27045 switch (N->getOpcode()) {
27047 case ISD::EXTRACT_VECTOR_ELT:
27048 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
27051 case X86ISD::SHRUNKBLEND:
27052 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
27053 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG, Subtarget);
27054 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
27055 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
27056 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
27057 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
27058 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
27061 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
27062 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
27063 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
27064 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
27065 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
27066 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
27067 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
27068 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
27069 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
27070 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
27071 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
27072 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
27073 case ISD::FNEG: return PerformFNEGCombine(N, DAG, Subtarget);
27074 case ISD::TRUNCATE: return PerformTRUNCATECombine(N, DAG, Subtarget);
27076 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
27078 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
27079 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
27080 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
27081 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
27082 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
27083 case ISD::ANY_EXTEND:
27084 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
27085 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
27086 case ISD::SIGN_EXTEND_INREG:
27087 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
27088 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
27089 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
27090 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
27091 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
27092 case X86ISD::SHUFP: // Handle all target specific shuffles
27093 case X86ISD::PALIGNR:
27094 case X86ISD::UNPCKH:
27095 case X86ISD::UNPCKL:
27096 case X86ISD::MOVHLPS:
27097 case X86ISD::MOVLHPS:
27098 case X86ISD::PSHUFB:
27099 case X86ISD::PSHUFD:
27100 case X86ISD::PSHUFHW:
27101 case X86ISD::PSHUFLW:
27102 case X86ISD::MOVSS:
27103 case X86ISD::MOVSD:
27104 case X86ISD::VPERMILPI:
27105 case X86ISD::VPERM2X128:
27106 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
27107 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
27108 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
27114 /// isTypeDesirableForOp - Return true if the target has native support for
27115 /// the specified value type and it is 'desirable' to use the type for the
27116 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
27117 /// instruction encodings are longer and some i16 instructions are slow.
27118 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
27119 if (!isTypeLegal(VT))
27121 if (VT != MVT::i16)
27128 case ISD::SIGN_EXTEND:
27129 case ISD::ZERO_EXTEND:
27130 case ISD::ANY_EXTEND:
27143 /// IsDesirableToPromoteOp - This method query the target whether it is
27144 /// beneficial for dag combiner to promote the specified node. If true, it
27145 /// should return the desired promotion type by reference.
27146 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
27147 EVT VT = Op.getValueType();
27148 if (VT != MVT::i16)
27151 bool Promote = false;
27152 bool Commute = false;
27153 switch (Op.getOpcode()) {
27156 LoadSDNode *LD = cast<LoadSDNode>(Op);
27157 // If the non-extending load has a single use and it's not live out, then it
27158 // might be folded.
27159 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
27160 Op.hasOneUse()*/) {
27161 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
27162 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
27163 // The only case where we'd want to promote LOAD (rather then it being
27164 // promoted as an operand is when it's only use is liveout.
27165 if (UI->getOpcode() != ISD::CopyToReg)
27172 case ISD::SIGN_EXTEND:
27173 case ISD::ZERO_EXTEND:
27174 case ISD::ANY_EXTEND:
27179 SDValue N0 = Op.getOperand(0);
27180 // Look out for (store (shl (load), x)).
27181 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
27194 SDValue N0 = Op.getOperand(0);
27195 SDValue N1 = Op.getOperand(1);
27196 if (!Commute && MayFoldLoad(N1))
27198 // Avoid disabling potential load folding opportunities.
27199 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
27201 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
27211 //===----------------------------------------------------------------------===//
27212 // X86 Inline Assembly Support
27213 //===----------------------------------------------------------------------===//
27215 // Helper to match a string separated by whitespace.
27216 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
27217 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
27219 for (StringRef Piece : Pieces) {
27220 if (!S.startswith(Piece)) // Check if the piece matches.
27223 S = S.substr(Piece.size());
27224 StringRef::size_type Pos = S.find_first_not_of(" \t");
27225 if (Pos == 0) // We matched a prefix.
27234 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
27236 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
27237 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
27238 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
27239 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
27241 if (AsmPieces.size() == 3)
27243 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
27250 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
27251 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
27253 std::string AsmStr = IA->getAsmString();
27255 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
27256 if (!Ty || Ty->getBitWidth() % 16 != 0)
27259 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
27260 SmallVector<StringRef, 4> AsmPieces;
27261 SplitString(AsmStr, AsmPieces, ";\n");
27263 switch (AsmPieces.size()) {
27264 default: return false;
27266 // FIXME: this should verify that we are targeting a 486 or better. If not,
27267 // we will turn this bswap into something that will be lowered to logical
27268 // ops instead of emitting the bswap asm. For now, we don't support 486 or
27269 // lower so don't worry about this.
27271 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
27272 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
27273 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
27274 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
27275 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
27276 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
27277 // No need to check constraints, nothing other than the equivalent of
27278 // "=r,0" would be valid here.
27279 return IntrinsicLowering::LowerToByteSwap(CI);
27282 // rorw $$8, ${0:w} --> llvm.bswap.i16
27283 if (CI->getType()->isIntegerTy(16) &&
27284 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27285 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
27286 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
27288 StringRef ConstraintsStr = IA->getConstraintString();
27289 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27290 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27291 if (clobbersFlagRegisters(AsmPieces))
27292 return IntrinsicLowering::LowerToByteSwap(CI);
27296 if (CI->getType()->isIntegerTy(32) &&
27297 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
27298 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
27299 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
27300 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
27302 StringRef ConstraintsStr = IA->getConstraintString();
27303 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
27304 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
27305 if (clobbersFlagRegisters(AsmPieces))
27306 return IntrinsicLowering::LowerToByteSwap(CI);
27309 if (CI->getType()->isIntegerTy(64)) {
27310 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
27311 if (Constraints.size() >= 2 &&
27312 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
27313 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
27314 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
27315 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
27316 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
27317 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
27318 return IntrinsicLowering::LowerToByteSwap(CI);
27326 /// getConstraintType - Given a constraint letter, return the type of
27327 /// constraint it is for this target.
27328 X86TargetLowering::ConstraintType
27329 X86TargetLowering::getConstraintType(StringRef Constraint) const {
27330 if (Constraint.size() == 1) {
27331 switch (Constraint[0]) {
27342 return C_RegisterClass;
27366 return TargetLowering::getConstraintType(Constraint);
27369 /// Examine constraint type and operand type and determine a weight value.
27370 /// This object must already have been set up with the operand type
27371 /// and the current alternative constraint selected.
27372 TargetLowering::ConstraintWeight
27373 X86TargetLowering::getSingleConstraintMatchWeight(
27374 AsmOperandInfo &info, const char *constraint) const {
27375 ConstraintWeight weight = CW_Invalid;
27376 Value *CallOperandVal = info.CallOperandVal;
27377 // If we don't have a value, we can't do a match,
27378 // but allow it at the lowest weight.
27379 if (!CallOperandVal)
27381 Type *type = CallOperandVal->getType();
27382 // Look at the constraint type.
27383 switch (*constraint) {
27385 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
27396 if (CallOperandVal->getType()->isIntegerTy())
27397 weight = CW_SpecificReg;
27402 if (type->isFloatingPointTy())
27403 weight = CW_SpecificReg;
27406 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27407 weight = CW_SpecificReg;
27411 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27412 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27413 weight = CW_Register;
27416 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27417 if (C->getZExtValue() <= 31)
27418 weight = CW_Constant;
27422 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27423 if (C->getZExtValue() <= 63)
27424 weight = CW_Constant;
27428 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27429 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27430 weight = CW_Constant;
27434 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27435 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27436 weight = CW_Constant;
27440 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27441 if (C->getZExtValue() <= 3)
27442 weight = CW_Constant;
27446 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27447 if (C->getZExtValue() <= 0xff)
27448 weight = CW_Constant;
27453 if (isa<ConstantFP>(CallOperandVal)) {
27454 weight = CW_Constant;
27458 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27459 if ((C->getSExtValue() >= -0x80000000LL) &&
27460 (C->getSExtValue() <= 0x7fffffffLL))
27461 weight = CW_Constant;
27465 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27466 if (C->getZExtValue() <= 0xffffffff)
27467 weight = CW_Constant;
27474 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27475 /// with another that has more specific requirements based on the type of the
27476 /// corresponding operand.
27477 const char *X86TargetLowering::
27478 LowerXConstraint(EVT ConstraintVT) const {
27479 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27480 // 'f' like normal targets.
27481 if (ConstraintVT.isFloatingPoint()) {
27482 if (Subtarget->hasSSE2())
27484 if (Subtarget->hasSSE1())
27488 return TargetLowering::LowerXConstraint(ConstraintVT);
27491 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27492 /// vector. If it is invalid, don't add anything to Ops.
27493 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27494 std::string &Constraint,
27495 std::vector<SDValue>&Ops,
27496 SelectionDAG &DAG) const {
27499 // Only support length 1 constraints for now.
27500 if (Constraint.length() > 1) return;
27502 char ConstraintLetter = Constraint[0];
27503 switch (ConstraintLetter) {
27506 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27507 if (C->getZExtValue() <= 31) {
27508 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27509 Op.getValueType());
27515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27516 if (C->getZExtValue() <= 63) {
27517 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27518 Op.getValueType());
27524 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27525 if (isInt<8>(C->getSExtValue())) {
27526 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27527 Op.getValueType());
27533 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27534 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27535 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27536 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27537 Op.getValueType());
27543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27544 if (C->getZExtValue() <= 3) {
27545 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27546 Op.getValueType());
27552 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27553 if (C->getZExtValue() <= 255) {
27554 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27555 Op.getValueType());
27561 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27562 if (C->getZExtValue() <= 127) {
27563 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27564 Op.getValueType());
27570 // 32-bit signed value
27571 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27572 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27573 C->getSExtValue())) {
27574 // Widen to 64 bits here to get it sign extended.
27575 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27578 // FIXME gcc accepts some relocatable values here too, but only in certain
27579 // memory models; it's complicated.
27584 // 32-bit unsigned value
27585 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27586 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27587 C->getZExtValue())) {
27588 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27589 Op.getValueType());
27593 // FIXME gcc accepts some relocatable values here too, but only in certain
27594 // memory models; it's complicated.
27598 // Literal immediates are always ok.
27599 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27600 // Widen to 64 bits here to get it sign extended.
27601 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27605 // In any sort of PIC mode addresses need to be computed at runtime by
27606 // adding in a register or some sort of table lookup. These can't
27607 // be used as immediates.
27608 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27611 // If we are in non-pic codegen mode, we allow the address of a global (with
27612 // an optional displacement) to be used with 'i'.
27613 GlobalAddressSDNode *GA = nullptr;
27614 int64_t Offset = 0;
27616 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27618 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27619 Offset += GA->getOffset();
27621 } else if (Op.getOpcode() == ISD::ADD) {
27622 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27623 Offset += C->getZExtValue();
27624 Op = Op.getOperand(0);
27627 } else if (Op.getOpcode() == ISD::SUB) {
27628 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27629 Offset += -C->getZExtValue();
27630 Op = Op.getOperand(0);
27635 // Otherwise, this isn't something we can handle, reject it.
27639 const GlobalValue *GV = GA->getGlobal();
27640 // If we require an extra load to get this address, as in PIC mode, we
27641 // can't accept it.
27642 if (isGlobalStubReference(
27643 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27646 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27647 GA->getValueType(0), Offset);
27652 if (Result.getNode()) {
27653 Ops.push_back(Result);
27656 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27659 std::pair<unsigned, const TargetRegisterClass *>
27660 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27661 StringRef Constraint,
27663 // First, see if this is a constraint that directly corresponds to an LLVM
27665 if (Constraint.size() == 1) {
27666 // GCC Constraint Letters
27667 switch (Constraint[0]) {
27669 // TODO: Slight differences here in allocation order and leaving
27670 // RIP in the class. Do they matter any more here than they do
27671 // in the normal allocation?
27672 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27673 if (Subtarget->is64Bit()) {
27674 if (VT == MVT::i32 || VT == MVT::f32)
27675 return std::make_pair(0U, &X86::GR32RegClass);
27676 if (VT == MVT::i16)
27677 return std::make_pair(0U, &X86::GR16RegClass);
27678 if (VT == MVT::i8 || VT == MVT::i1)
27679 return std::make_pair(0U, &X86::GR8RegClass);
27680 if (VT == MVT::i64 || VT == MVT::f64)
27681 return std::make_pair(0U, &X86::GR64RegClass);
27684 // 32-bit fallthrough
27685 case 'Q': // Q_REGS
27686 if (VT == MVT::i32 || VT == MVT::f32)
27687 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27688 if (VT == MVT::i16)
27689 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27690 if (VT == MVT::i8 || VT == MVT::i1)
27691 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27692 if (VT == MVT::i64)
27693 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27695 case 'r': // GENERAL_REGS
27696 case 'l': // INDEX_REGS
27697 if (VT == MVT::i8 || VT == MVT::i1)
27698 return std::make_pair(0U, &X86::GR8RegClass);
27699 if (VT == MVT::i16)
27700 return std::make_pair(0U, &X86::GR16RegClass);
27701 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27702 return std::make_pair(0U, &X86::GR32RegClass);
27703 return std::make_pair(0U, &X86::GR64RegClass);
27704 case 'R': // LEGACY_REGS
27705 if (VT == MVT::i8 || VT == MVT::i1)
27706 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27707 if (VT == MVT::i16)
27708 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27709 if (VT == MVT::i32 || !Subtarget->is64Bit())
27710 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27711 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27712 case 'f': // FP Stack registers.
27713 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27714 // value to the correct fpstack register class.
27715 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27716 return std::make_pair(0U, &X86::RFP32RegClass);
27717 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27718 return std::make_pair(0U, &X86::RFP64RegClass);
27719 return std::make_pair(0U, &X86::RFP80RegClass);
27720 case 'y': // MMX_REGS if MMX allowed.
27721 if (!Subtarget->hasMMX()) break;
27722 return std::make_pair(0U, &X86::VR64RegClass);
27723 case 'Y': // SSE_REGS if SSE2 allowed
27724 if (!Subtarget->hasSSE2()) break;
27726 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27727 if (!Subtarget->hasSSE1()) break;
27729 switch (VT.SimpleTy) {
27731 // Scalar SSE types.
27734 return std::make_pair(0U, &X86::FR32RegClass);
27737 return std::make_pair(0U, &X86::FR64RegClass);
27745 return std::make_pair(0U, &X86::VR128RegClass);
27753 return std::make_pair(0U, &X86::VR256RegClass);
27758 return std::make_pair(0U, &X86::VR512RegClass);
27764 // Use the default implementation in TargetLowering to convert the register
27765 // constraint into a member of a register class.
27766 std::pair<unsigned, const TargetRegisterClass*> Res;
27767 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27769 // Not found as a standard register?
27771 // Map st(0) -> st(7) -> ST0
27772 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27773 tolower(Constraint[1]) == 's' &&
27774 tolower(Constraint[2]) == 't' &&
27775 Constraint[3] == '(' &&
27776 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27777 Constraint[5] == ')' &&
27778 Constraint[6] == '}') {
27780 Res.first = X86::FP0+Constraint[4]-'0';
27781 Res.second = &X86::RFP80RegClass;
27785 // GCC allows "st(0)" to be called just plain "st".
27786 if (StringRef("{st}").equals_lower(Constraint)) {
27787 Res.first = X86::FP0;
27788 Res.second = &X86::RFP80RegClass;
27793 if (StringRef("{flags}").equals_lower(Constraint)) {
27794 Res.first = X86::EFLAGS;
27795 Res.second = &X86::CCRRegClass;
27799 // 'A' means EAX + EDX.
27800 if (Constraint == "A") {
27801 Res.first = X86::EAX;
27802 Res.second = &X86::GR32_ADRegClass;
27808 // Otherwise, check to see if this is a register class of the wrong value
27809 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27810 // turn into {ax},{dx}.
27811 // MVT::Other is used to specify clobber names.
27812 if (Res.second->hasType(VT) || VT == MVT::Other)
27813 return Res; // Correct type already, nothing to do.
27815 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27816 // return "eax". This should even work for things like getting 64bit integer
27817 // registers when given an f64 type.
27818 const TargetRegisterClass *Class = Res.second;
27819 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27820 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27821 unsigned Size = VT.getSizeInBits();
27822 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27823 : Size == 16 ? MVT::i16
27824 : Size == 32 ? MVT::i32
27825 : Size == 64 ? MVT::i64
27827 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27829 Res.first = DestReg;
27830 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27831 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27832 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27833 : &X86::GR64RegClass;
27834 assert(Res.second->contains(Res.first) && "Register in register class");
27836 // No register found/type mismatch.
27838 Res.second = nullptr;
27840 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27841 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27842 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27843 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27844 Class == &X86::VR512RegClass) {
27845 // Handle references to XMM physical registers that got mapped into the
27846 // wrong class. This can happen with constraints like {xmm0} where the
27847 // target independent register mapper will just pick the first match it can
27848 // find, ignoring the required type.
27850 if (VT == MVT::f32 || VT == MVT::i32)
27851 Res.second = &X86::FR32RegClass;
27852 else if (VT == MVT::f64 || VT == MVT::i64)
27853 Res.second = &X86::FR64RegClass;
27854 else if (X86::VR128RegClass.hasType(VT))
27855 Res.second = &X86::VR128RegClass;
27856 else if (X86::VR256RegClass.hasType(VT))
27857 Res.second = &X86::VR256RegClass;
27858 else if (X86::VR512RegClass.hasType(VT))
27859 Res.second = &X86::VR512RegClass;
27861 // Type mismatch and not a clobber: Return an error;
27863 Res.second = nullptr;
27870 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27871 const AddrMode &AM, Type *Ty,
27872 unsigned AS) const {
27873 // Scaling factors are not free at all.
27874 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27875 // will take 2 allocations in the out of order engine instead of 1
27876 // for plain addressing mode, i.e. inst (reg1).
27878 // vaddps (%rsi,%drx), %ymm0, %ymm1
27879 // Requires two allocations (one for the load, one for the computation)
27881 // vaddps (%rsi), %ymm0, %ymm1
27882 // Requires just 1 allocation, i.e., freeing allocations for other operations
27883 // and having less micro operations to execute.
27885 // For some X86 architectures, this is even worse because for instance for
27886 // stores, the complex addressing mode forces the instruction to use the
27887 // "load" ports instead of the dedicated "store" port.
27888 // E.g., on Haswell:
27889 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27890 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27891 if (isLegalAddressingMode(DL, AM, Ty, AS))
27892 // Scale represents reg2 * scale, thus account for 1
27893 // as soon as we use a second register.
27894 return AM.Scale != 0;
27898 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27899 // Integer division on x86 is expensive. However, when aggressively optimizing
27900 // for code size, we prefer to use a div instruction, as it is usually smaller
27901 // than the alternative sequence.
27902 // The exception to this is vector division. Since x86 doesn't have vector
27903 // integer division, leaving the division as-is is a loss even in terms of
27904 // size, because it will have to be scalarized, while the alternative code
27905 // sequence can be performed in vector form.
27906 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27907 Attribute::MinSize);
27908 return OptSize && !VT.isVector();
27911 void X86TargetLowering::markInRegArguments(SelectionDAG &DAG,
27912 TargetLowering::ArgListTy& Args) const {
27913 // The MCU psABI requires some arguments to be passed in-register.
27914 // For regular calls, the inreg arguments are marked by the front-end.
27915 // However, for compiler generated library calls, we have to patch this
27917 if (!Subtarget->isTargetMCU() || !Args.size())
27920 unsigned FreeRegs = 3;
27921 for (auto &Arg : Args) {
27922 // For library functions, we do not expect any fancy types.
27923 unsigned Size = DAG.getDataLayout().getTypeSizeInBits(Arg.Ty);
27924 unsigned SizeInRegs = (Size + 31) / 32;
27925 if (SizeInRegs > 2 || SizeInRegs > FreeRegs)
27928 Arg.isInReg = true;
27929 FreeRegs -= SizeInRegs;