1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
71 const X86Subtarget &STI)
72 : TargetLowering(TM), Subtarget(&STI) {
73 X86ScalarSSEf64 = Subtarget->hasSSE2();
74 X86ScalarSSEf32 = Subtarget->hasSSE1();
75 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
77 // Set up the TargetLowering object.
78 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
81 setBooleanContents(ZeroOrOneBooleanContent);
82 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
83 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
85 // For 64-bit, since we have so many registers, use the ILP scheduler.
86 // For 32-bit, use the register pressure specific scheduling.
87 // For Atom, always use ILP scheduling.
88 if (Subtarget->isAtom())
89 setSchedulingPreference(Sched::ILP);
90 else if (Subtarget->is64Bit())
91 setSchedulingPreference(Sched::ILP);
93 setSchedulingPreference(Sched::RegPressure);
94 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
95 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
97 // Bypass expensive divides on Atom when compiling with O2.
98 if (TM.getOptLevel() >= CodeGenOpt::Default) {
99 if (Subtarget->hasSlowDivide32())
100 addBypassSlowDiv(32, 8);
101 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
102 addBypassSlowDiv(64, 16);
105 if (Subtarget->isTargetKnownWindowsMSVC()) {
106 // Setup Windows compiler runtime calls.
107 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
108 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
109 setLibcallName(RTLIB::SREM_I64, "_allrem");
110 setLibcallName(RTLIB::UREM_I64, "_aullrem");
111 setLibcallName(RTLIB::MUL_I64, "_allmul");
112 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
113 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
114 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
115 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
116 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
119 if (Subtarget->isTargetDarwin()) {
120 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
121 setUseUnderscoreSetJmp(false);
122 setUseUnderscoreLongJmp(false);
123 } else if (Subtarget->isTargetWindowsGNU()) {
124 // MS runtime is weird: it exports _setjmp, but longjmp!
125 setUseUnderscoreSetJmp(true);
126 setUseUnderscoreLongJmp(false);
128 setUseUnderscoreSetJmp(true);
129 setUseUnderscoreLongJmp(true);
132 // Set up the register classes.
133 addRegisterClass(MVT::i8, &X86::GR8RegClass);
134 addRegisterClass(MVT::i16, &X86::GR16RegClass);
135 addRegisterClass(MVT::i32, &X86::GR32RegClass);
136 if (Subtarget->is64Bit())
137 addRegisterClass(MVT::i64, &X86::GR64RegClass);
139 for (MVT VT : MVT::integer_valuetypes())
140 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
142 // We don't accept any truncstore of integer registers.
143 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
144 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
145 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
146 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
147 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
148 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
150 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
152 // SETOEQ and SETUNE require checking two conditions.
153 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
154 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
155 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
156 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
157 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
158 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
160 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
162 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
163 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
164 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
166 if (Subtarget->is64Bit()) {
167 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512())
168 // f32/f64 are legal, f80 is custom.
169 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
171 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
172 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
173 } else if (!Subtarget->useSoftFloat()) {
174 // We have an algorithm for SSE2->double, and we turn this into a
175 // 64-bit FILD followed by conditional FADD for other targets.
176 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
177 // We have an algorithm for SSE2, and we turn this into a 64-bit
178 // FILD or VCVTUSI2SS/SD for other targets.
179 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
182 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
184 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
185 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
187 if (!Subtarget->useSoftFloat()) {
188 // SSE has no i16 to fp conversion, only i32
189 if (X86ScalarSSEf32) {
190 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
191 // f32 and f64 cases are Legal, f80 case is not
192 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
194 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
195 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
202 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
203 // are Legal, f80 is custom lowered.
204 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
207 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
209 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
210 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
212 if (X86ScalarSSEf32) {
213 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
214 // f32 and f64 cases are Legal, f80 case is not
215 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
218 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
221 // Handle FP_TO_UINT by promoting the destination to a larger signed
223 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
224 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
225 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
227 if (Subtarget->is64Bit()) {
228 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
229 // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
230 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
233 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
234 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 } else if (!Subtarget->useSoftFloat()) {
237 // Since AVX is a superset of SSE3, only check for SSE here.
238 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
239 // Expand FP_TO_UINT into a select.
240 // FIXME: We would like to use a Custom expander here eventually to do
241 // the optimal thing for SSE vs. the default expansion in the legalizer.
242 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
244 // With AVX512 we can use vcvts[ds]2usi for f32/f64->i32, f80 is custom.
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
249 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
252 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
253 if (!X86ScalarSSEf64) {
254 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
255 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
256 if (Subtarget->is64Bit()) {
257 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
258 // Without SSE, i64->f64 goes through memory.
259 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
263 // Scalar integer divide and remainder are lowered to use operations that
264 // produce two results, to match the available instructions. This exposes
265 // the two-result form to trivial CSE, which is able to combine x/y and x%y
266 // into a single instruction.
268 // Scalar integer multiply-high is also lowered to use two-result
269 // operations, to match the available instructions. However, plain multiply
270 // (low) operations are left as Legal, as there are single-result
271 // instructions for this in x86. Using the two-result multiply instructions
272 // when both high and low results are needed must be arranged by dagcombine.
273 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
275 setOperationAction(ISD::MULHS, VT, Expand);
276 setOperationAction(ISD::MULHU, VT, Expand);
277 setOperationAction(ISD::SDIV, VT, Expand);
278 setOperationAction(ISD::UDIV, VT, Expand);
279 setOperationAction(ISD::SREM, VT, Expand);
280 setOperationAction(ISD::UREM, VT, Expand);
282 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
283 setOperationAction(ISD::ADDC, VT, Custom);
284 setOperationAction(ISD::ADDE, VT, Custom);
285 setOperationAction(ISD::SUBC, VT, Custom);
286 setOperationAction(ISD::SUBE, VT, Custom);
289 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
290 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
291 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
292 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
293 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
294 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
295 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
296 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
297 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
298 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
299 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
300 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
301 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
305 if (Subtarget->is64Bit())
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
308 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
309 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
310 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
312 if (Subtarget->is32Bit() && Subtarget->isTargetKnownWindowsMSVC()) {
313 // On 32 bit MSVC, `fmodf(f32)` is not defined - only `fmod(f64)`
314 // is. We should promote the value to 64-bits to solve this.
315 // This is what the CRT headers do - `fmodf` is an inline header
316 // function casting to f64 and calling `fmod`.
317 setOperationAction(ISD::FREM , MVT::f32 , Promote);
319 setOperationAction(ISD::FREM , MVT::f32 , Expand);
322 setOperationAction(ISD::FREM , MVT::f64 , Expand);
323 setOperationAction(ISD::FREM , MVT::f80 , Expand);
324 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
326 // Promote the i8 variants and force them on up to i32 which has a shorter
328 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
329 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
331 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
332 if (Subtarget->hasBMI()) {
333 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
334 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
335 if (Subtarget->is64Bit())
336 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
338 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
339 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
340 if (Subtarget->is64Bit())
341 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
344 if (Subtarget->hasLZCNT()) {
345 // When promoting the i8 variants, force them to i32 for a shorter
347 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
348 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
350 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
352 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
353 if (Subtarget->is64Bit())
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
356 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
357 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
358 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
359 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
360 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
364 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
368 // Special handling for half-precision floating point conversions.
369 // If we don't have F16C support, then lower half float conversions
370 // into library calls.
371 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
372 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
376 // There's never any support for operations beyond MVT::f32.
377 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
378 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
380 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
382 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
383 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
384 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
385 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
386 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
387 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
389 if (Subtarget->hasPOPCNT()) {
390 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
392 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
393 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
394 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
395 if (Subtarget->is64Bit())
396 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
399 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
401 if (!Subtarget->hasMOVBE())
402 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
404 // These should be promoted to a larger select which is supported.
405 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
406 // X86 wants to expand cmov itself.
407 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
408 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
409 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
410 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
411 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
412 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
413 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
414 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
416 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
417 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
418 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
419 if (Subtarget->is64Bit()) {
420 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
421 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
423 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
424 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
425 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
426 // support continuation, user-level threading, and etc.. As a result, no
427 // other SjLj exception interfaces are implemented and please don't build
428 // your own exception handling based on them.
429 // LLVM/Clang supports zero-cost DWARF exception handling.
430 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
431 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
434 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
435 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
436 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
437 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
438 if (Subtarget->is64Bit())
439 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
440 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
442 if (Subtarget->is64Bit()) {
443 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
444 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
445 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
446 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
447 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
449 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
450 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
452 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
453 if (Subtarget->is64Bit()) {
454 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
456 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
459 if (Subtarget->hasSSE1())
460 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
462 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
464 // Expand certain atomics
465 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
468 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
469 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
472 if (Subtarget->hasCmpxchg16b()) {
473 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
476 // FIXME - use subtarget debug flags
477 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
478 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
479 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
482 if (Subtarget->isTarget64BitLP64()) {
483 setExceptionPointerRegister(X86::RAX);
484 setExceptionSelectorRegister(X86::RDX);
486 setExceptionPointerRegister(X86::EAX);
487 setExceptionSelectorRegister(X86::EDX);
489 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
490 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
492 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
493 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
495 setOperationAction(ISD::TRAP, MVT::Other, Legal);
496 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
498 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
499 setOperationAction(ISD::VASTART , MVT::Other, Custom);
500 setOperationAction(ISD::VAEND , MVT::Other, Expand);
501 if (Subtarget->is64Bit()) {
502 setOperationAction(ISD::VAARG , MVT::Other, Custom);
503 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
505 // TargetInfo::CharPtrBuiltinVaList
506 setOperationAction(ISD::VAARG , MVT::Other, Expand);
507 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
510 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
511 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
513 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
515 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
516 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
517 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
519 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
520 // f32 and f64 use SSE.
521 // Set up the FP register classes.
522 addRegisterClass(MVT::f32, &X86::FR32RegClass);
523 addRegisterClass(MVT::f64, &X86::FR64RegClass);
525 // Use ANDPD to simulate FABS.
526 setOperationAction(ISD::FABS , MVT::f64, Custom);
527 setOperationAction(ISD::FABS , MVT::f32, Custom);
529 // Use XORP to simulate FNEG.
530 setOperationAction(ISD::FNEG , MVT::f64, Custom);
531 setOperationAction(ISD::FNEG , MVT::f32, Custom);
533 // Use ANDPD and ORPD to simulate FCOPYSIGN.
534 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
535 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
537 // Lower this to FGETSIGNx86 plus an AND.
538 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
539 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
541 // We don't support sin/cos/fmod
542 setOperationAction(ISD::FSIN , MVT::f64, Expand);
543 setOperationAction(ISD::FCOS , MVT::f64, Expand);
544 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
545 setOperationAction(ISD::FSIN , MVT::f32, Expand);
546 setOperationAction(ISD::FCOS , MVT::f32, Expand);
547 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
549 // Expand FP immediates into loads from the stack, except for the special
551 addLegalFPImmediate(APFloat(+0.0)); // xorpd
552 addLegalFPImmediate(APFloat(+0.0f)); // xorps
553 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
554 // Use SSE for f32, x87 for f64.
555 // Set up the FP register classes.
556 addRegisterClass(MVT::f32, &X86::FR32RegClass);
557 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
559 // Use ANDPS to simulate FABS.
560 setOperationAction(ISD::FABS , MVT::f32, Custom);
562 // Use XORP to simulate FNEG.
563 setOperationAction(ISD::FNEG , MVT::f32, Custom);
565 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
567 // Use ANDPS and ORPS to simulate FCOPYSIGN.
568 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
569 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
571 // We don't support sin/cos/fmod
572 setOperationAction(ISD::FSIN , MVT::f32, Expand);
573 setOperationAction(ISD::FCOS , MVT::f32, Expand);
574 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
576 // Special cases we handle for FP constants.
577 addLegalFPImmediate(APFloat(+0.0f)); // xorps
578 addLegalFPImmediate(APFloat(+0.0)); // FLD0
579 addLegalFPImmediate(APFloat(+1.0)); // FLD1
580 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
581 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
583 if (!TM.Options.UnsafeFPMath) {
584 setOperationAction(ISD::FSIN , MVT::f64, Expand);
585 setOperationAction(ISD::FCOS , MVT::f64, Expand);
586 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
588 } else if (!Subtarget->useSoftFloat()) {
589 // f32 and f64 in x87.
590 // Set up the FP register classes.
591 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
592 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
594 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
595 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
596 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
597 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
599 if (!TM.Options.UnsafeFPMath) {
600 setOperationAction(ISD::FSIN , MVT::f64, Expand);
601 setOperationAction(ISD::FSIN , MVT::f32, Expand);
602 setOperationAction(ISD::FCOS , MVT::f64, Expand);
603 setOperationAction(ISD::FCOS , MVT::f32, Expand);
604 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
605 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
607 addLegalFPImmediate(APFloat(+0.0)); // FLD0
608 addLegalFPImmediate(APFloat(+1.0)); // FLD1
609 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
610 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
611 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
612 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
613 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
614 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
617 // We don't support FMA.
618 setOperationAction(ISD::FMA, MVT::f64, Expand);
619 setOperationAction(ISD::FMA, MVT::f32, Expand);
621 // Long double always uses X87.
622 if (!Subtarget->useSoftFloat()) {
623 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
624 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
627 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
628 addLegalFPImmediate(TmpFlt); // FLD0
630 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
633 APFloat TmpFlt2(+1.0);
634 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
636 addLegalFPImmediate(TmpFlt2); // FLD1
637 TmpFlt2.changeSign();
638 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
641 if (!TM.Options.UnsafeFPMath) {
642 setOperationAction(ISD::FSIN , MVT::f80, Expand);
643 setOperationAction(ISD::FCOS , MVT::f80, Expand);
644 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
647 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
648 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
649 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
650 setOperationAction(ISD::FRINT, MVT::f80, Expand);
651 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
652 setOperationAction(ISD::FMA, MVT::f80, Expand);
655 // Always use a library call for pow.
656 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
657 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
658 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
660 setOperationAction(ISD::FLOG, MVT::f80, Expand);
661 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
662 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
663 setOperationAction(ISD::FEXP, MVT::f80, Expand);
664 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
665 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
666 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
668 // First set operation action for all vector types to either promote
669 // (for widening) or expand (for scalarization). Then we will selectively
670 // turn on ones that can be effectively codegen'd.
671 for (MVT VT : MVT::vector_valuetypes()) {
672 setOperationAction(ISD::ADD , VT, Expand);
673 setOperationAction(ISD::SUB , VT, Expand);
674 setOperationAction(ISD::FADD, VT, Expand);
675 setOperationAction(ISD::FNEG, VT, Expand);
676 setOperationAction(ISD::FSUB, VT, Expand);
677 setOperationAction(ISD::MUL , VT, Expand);
678 setOperationAction(ISD::FMUL, VT, Expand);
679 setOperationAction(ISD::SDIV, VT, Expand);
680 setOperationAction(ISD::UDIV, VT, Expand);
681 setOperationAction(ISD::FDIV, VT, Expand);
682 setOperationAction(ISD::SREM, VT, Expand);
683 setOperationAction(ISD::UREM, VT, Expand);
684 setOperationAction(ISD::LOAD, VT, Expand);
685 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
686 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
687 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
688 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
689 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
690 setOperationAction(ISD::FABS, VT, Expand);
691 setOperationAction(ISD::FSIN, VT, Expand);
692 setOperationAction(ISD::FSINCOS, VT, Expand);
693 setOperationAction(ISD::FCOS, VT, Expand);
694 setOperationAction(ISD::FSINCOS, VT, Expand);
695 setOperationAction(ISD::FREM, VT, Expand);
696 setOperationAction(ISD::FMA, VT, Expand);
697 setOperationAction(ISD::FPOWI, VT, Expand);
698 setOperationAction(ISD::FSQRT, VT, Expand);
699 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
700 setOperationAction(ISD::FFLOOR, VT, Expand);
701 setOperationAction(ISD::FCEIL, VT, Expand);
702 setOperationAction(ISD::FTRUNC, VT, Expand);
703 setOperationAction(ISD::FRINT, VT, Expand);
704 setOperationAction(ISD::FNEARBYINT, VT, Expand);
705 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
706 setOperationAction(ISD::MULHS, VT, Expand);
707 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
708 setOperationAction(ISD::MULHU, VT, Expand);
709 setOperationAction(ISD::SDIVREM, VT, Expand);
710 setOperationAction(ISD::UDIVREM, VT, Expand);
711 setOperationAction(ISD::FPOW, VT, Expand);
712 setOperationAction(ISD::CTPOP, VT, Expand);
713 setOperationAction(ISD::CTTZ, VT, Expand);
714 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
715 setOperationAction(ISD::CTLZ, VT, Expand);
716 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
717 setOperationAction(ISD::SHL, VT, Expand);
718 setOperationAction(ISD::SRA, VT, Expand);
719 setOperationAction(ISD::SRL, VT, Expand);
720 setOperationAction(ISD::ROTL, VT, Expand);
721 setOperationAction(ISD::ROTR, VT, Expand);
722 setOperationAction(ISD::BSWAP, VT, Expand);
723 setOperationAction(ISD::SETCC, VT, Expand);
724 setOperationAction(ISD::FLOG, VT, Expand);
725 setOperationAction(ISD::FLOG2, VT, Expand);
726 setOperationAction(ISD::FLOG10, VT, Expand);
727 setOperationAction(ISD::FEXP, VT, Expand);
728 setOperationAction(ISD::FEXP2, VT, Expand);
729 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
730 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
731 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
732 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
733 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
734 setOperationAction(ISD::TRUNCATE, VT, Expand);
735 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
736 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
737 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
738 setOperationAction(ISD::VSELECT, VT, Expand);
739 setOperationAction(ISD::SELECT_CC, VT, Expand);
740 for (MVT InnerVT : MVT::vector_valuetypes()) {
741 setTruncStoreAction(InnerVT, VT, Expand);
743 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
744 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
746 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
747 // types, we have to deal with them whether we ask for Expansion or not.
748 // Setting Expand causes its own optimisation problems though, so leave
750 if (VT.getVectorElementType() == MVT::i1)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
753 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
754 // split/scalarized right now.
755 if (VT.getVectorElementType() == MVT::f16)
756 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
760 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
761 // with -msoft-float, disable use of MMX as well.
762 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
763 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
764 // No operations on x86mmx supported, everything uses intrinsics.
767 // MMX-sized vectors (other than x86mmx) are expected to be expanded
768 // into smaller operations.
769 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
770 setOperationAction(ISD::MULHS, MMXTy, Expand);
771 setOperationAction(ISD::AND, MMXTy, Expand);
772 setOperationAction(ISD::OR, MMXTy, Expand);
773 setOperationAction(ISD::XOR, MMXTy, Expand);
774 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
775 setOperationAction(ISD::SELECT, MMXTy, Expand);
776 setOperationAction(ISD::BITCAST, MMXTy, Expand);
778 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
780 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
781 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
783 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
784 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
785 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
786 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
788 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
789 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
790 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
791 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
792 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
793 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
795 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
796 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
799 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
800 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
802 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
803 // registers cannot be used even for integer operations.
804 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
805 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
806 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
807 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
809 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
810 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
811 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
812 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
813 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
814 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
815 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
816 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
817 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
818 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
819 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
820 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
821 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
822 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
823 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
824 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
825 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
826 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
827 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
828 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
829 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
830 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
831 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
833 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
834 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
835 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
836 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
838 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
839 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
840 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
841 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
843 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
844 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
845 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
846 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
847 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
849 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
850 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
851 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
852 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
854 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
855 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
856 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
857 // ISD::CTTZ v2i64 - scalarization is faster.
858 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
859 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
860 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
861 // ISD::CTTZ_ZERO_UNDEF v2i64 - scalarization is faster.
863 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
864 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
865 MVT VT = (MVT::SimpleValueType)i;
866 // Do not attempt to custom lower non-power-of-2 vectors
867 if (!isPowerOf2_32(VT.getVectorNumElements()))
869 // Do not attempt to custom lower non-128-bit vectors
870 if (!VT.is128BitVector())
872 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
873 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
874 setOperationAction(ISD::VSELECT, VT, Custom);
875 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
878 // We support custom legalizing of sext and anyext loads for specific
879 // memory vector types which we can load as a scalar (or sequence of
880 // scalars) and extend in-register to a legal 128-bit vector type. For sext
881 // loads these must work with a single scalar load.
882 for (MVT VT : MVT::integer_vector_valuetypes()) {
883 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
884 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
885 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
886 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
887 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
888 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
889 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
890 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
891 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
894 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
895 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
896 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
897 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
898 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
899 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
900 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
901 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
903 if (Subtarget->is64Bit()) {
904 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
905 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
908 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
909 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
910 MVT VT = (MVT::SimpleValueType)i;
912 // Do not attempt to promote non-128-bit vectors
913 if (!VT.is128BitVector())
916 setOperationAction(ISD::AND, VT, Promote);
917 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
918 setOperationAction(ISD::OR, VT, Promote);
919 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
920 setOperationAction(ISD::XOR, VT, Promote);
921 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
922 setOperationAction(ISD::LOAD, VT, Promote);
923 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
924 setOperationAction(ISD::SELECT, VT, Promote);
925 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
928 // Custom lower v2i64 and v2f64 selects.
929 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
930 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
931 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
932 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
934 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
935 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
937 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
939 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
940 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
941 // As there is no 64-bit GPR available, we need build a special custom
942 // sequence to convert from v2i32 to v2f32.
943 if (!Subtarget->is64Bit())
944 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
946 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
947 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
949 for (MVT VT : MVT::fp_vector_valuetypes())
950 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
952 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
953 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
954 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
957 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
958 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
959 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
960 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
961 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
962 setOperationAction(ISD::FRINT, RoundedTy, Legal);
963 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
966 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
967 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
968 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
969 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
970 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
971 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
972 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
973 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
975 // FIXME: Do we need to handle scalar-to-vector here?
976 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
978 // We directly match byte blends in the backend as they match the VSELECT
980 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
982 // SSE41 brings specific instructions for doing vector sign extend even in
983 // cases where we don't have SRA.
984 for (MVT VT : MVT::integer_vector_valuetypes()) {
985 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
986 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
987 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
990 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
991 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
992 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
993 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
994 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
995 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
996 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
998 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
999 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
1000 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
1001 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
1002 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
1003 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
1005 // i8 and i16 vectors are custom because the source register and source
1006 // source memory operand types are not the same width. f32 vectors are
1007 // custom since the immediate controlling the insert encodes additional
1009 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1010 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1011 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1012 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1014 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1015 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1016 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1017 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1019 // FIXME: these should be Legal, but that's only for the case where
1020 // the index is constant. For now custom expand to deal with that.
1021 if (Subtarget->is64Bit()) {
1022 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1023 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1027 if (Subtarget->hasSSE2()) {
1028 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1029 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1030 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1032 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1033 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1035 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1036 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1038 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1039 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1041 // In the customized shift lowering, the legal cases in AVX2 will be
1043 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1044 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1046 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1047 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1049 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1050 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1053 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1054 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1055 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1056 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1057 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1058 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1059 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1061 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1062 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1063 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1065 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1066 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1067 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1068 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1069 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1070 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1071 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1072 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1073 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1074 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1075 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1076 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1078 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1079 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1080 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1081 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1082 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1083 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1084 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1085 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1086 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1087 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1088 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1089 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1091 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1092 // even though v8i16 is a legal type.
1093 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1094 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1095 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1097 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1098 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1099 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1101 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1102 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1104 for (MVT VT : MVT::fp_vector_valuetypes())
1105 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1107 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1108 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1110 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1111 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1113 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1114 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1116 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1117 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1118 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1119 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1121 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1122 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1123 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1125 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1126 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1127 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1129 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1130 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1131 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1132 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1133 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1134 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1135 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1136 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1138 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1139 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1140 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1141 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1143 setOperationAction(ISD::CTTZ, MVT::v32i8, Custom);
1144 setOperationAction(ISD::CTTZ, MVT::v16i16, Custom);
1145 setOperationAction(ISD::CTTZ, MVT::v8i32, Custom);
1146 setOperationAction(ISD::CTTZ, MVT::v4i64, Custom);
1147 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v32i8, Custom);
1148 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i16, Custom);
1149 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1150 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1152 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1153 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1154 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1155 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1156 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1157 setOperationAction(ISD::FMA, MVT::f32, Legal);
1158 setOperationAction(ISD::FMA, MVT::f64, Legal);
1161 if (Subtarget->hasInt256()) {
1162 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1163 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1164 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1165 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1167 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1168 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1169 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1170 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1172 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1173 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1174 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1175 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1177 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1178 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1179 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1180 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1182 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1183 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1185 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1186 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1187 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1188 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1189 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1190 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1191 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1192 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1193 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1195 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1196 // when we have a 256bit-wide blend with immediate.
1197 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1199 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1200 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1201 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1202 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1203 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1204 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1205 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1207 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1209 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1210 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1212 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1214 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1215 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1216 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1217 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1219 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1220 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1221 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1222 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1224 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1225 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1226 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1227 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1229 setOperationAction(ISD::SMAX, MVT::v32i8, Custom);
1230 setOperationAction(ISD::SMAX, MVT::v16i16, Custom);
1231 setOperationAction(ISD::SMAX, MVT::v8i32, Custom);
1232 setOperationAction(ISD::UMAX, MVT::v32i8, Custom);
1233 setOperationAction(ISD::UMAX, MVT::v16i16, Custom);
1234 setOperationAction(ISD::UMAX, MVT::v8i32, Custom);
1235 setOperationAction(ISD::SMIN, MVT::v32i8, Custom);
1236 setOperationAction(ISD::SMIN, MVT::v16i16, Custom);
1237 setOperationAction(ISD::SMIN, MVT::v8i32, Custom);
1238 setOperationAction(ISD::UMIN, MVT::v32i8, Custom);
1239 setOperationAction(ISD::UMIN, MVT::v16i16, Custom);
1240 setOperationAction(ISD::UMIN, MVT::v8i32, Custom);
1243 // In the customized shift lowering, the legal cases in AVX2 will be
1245 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1246 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1248 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1249 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1251 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1252 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1254 // Custom lower several nodes for 256-bit types.
1255 for (MVT VT : MVT::vector_valuetypes()) {
1256 if (VT.getScalarSizeInBits() >= 32) {
1257 setOperationAction(ISD::MLOAD, VT, Legal);
1258 setOperationAction(ISD::MSTORE, VT, Legal);
1260 // Extract subvector is special because the value type
1261 // (result) is 128-bit but the source is 256-bit wide.
1262 if (VT.is128BitVector()) {
1263 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1265 // Do not attempt to custom lower other non-256-bit vectors
1266 if (!VT.is256BitVector())
1269 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1270 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1271 setOperationAction(ISD::VSELECT, VT, Custom);
1272 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1273 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1274 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1275 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1276 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1279 if (Subtarget->hasInt256())
1280 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1282 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1283 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1284 MVT VT = (MVT::SimpleValueType)i;
1286 // Do not attempt to promote non-256-bit vectors
1287 if (!VT.is256BitVector())
1290 setOperationAction(ISD::AND, VT, Promote);
1291 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1292 setOperationAction(ISD::OR, VT, Promote);
1293 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1294 setOperationAction(ISD::XOR, VT, Promote);
1295 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1296 setOperationAction(ISD::LOAD, VT, Promote);
1297 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1298 setOperationAction(ISD::SELECT, VT, Promote);
1299 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1303 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1304 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1305 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1306 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1307 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1309 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1310 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1311 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1313 for (MVT VT : MVT::fp_vector_valuetypes())
1314 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1316 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1317 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1318 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1319 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1320 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1321 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1322 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1323 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1324 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1325 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1326 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1327 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1329 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1330 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1331 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
1332 setOperationAction(ISD::XOR, MVT::i1, Legal);
1333 setOperationAction(ISD::OR, MVT::i1, Legal);
1334 setOperationAction(ISD::AND, MVT::i1, Legal);
1335 setOperationAction(ISD::SUB, MVT::i1, Custom);
1336 setOperationAction(ISD::ADD, MVT::i1, Custom);
1337 setOperationAction(ISD::MUL, MVT::i1, Custom);
1338 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1339 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1340 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1341 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1342 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1344 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1345 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1347 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1349 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1351 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1352 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1354 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1355 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1356 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1357 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1358 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1360 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1361 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1362 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1363 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1364 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1365 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1366 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1367 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1368 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1369 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1370 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1371 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1372 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1373 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1374 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1375 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1377 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1378 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1379 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1380 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);
1381 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);
1382 if (Subtarget->hasVLX()){
1383 setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);
1384 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);
1385 setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);
1386 setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);
1387 setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);
1389 setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);
1390 setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);
1391 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);
1392 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);
1393 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);
1395 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1396 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1397 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1398 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i1, Custom);
1399 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i1, Custom);
1400 if (Subtarget->hasDQI()) {
1401 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1402 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1404 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1405 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1406 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1407 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1408 if (Subtarget->hasVLX()) {
1409 setOperationAction(ISD::SINT_TO_FP, MVT::v4i64, Legal);
1410 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
1411 setOperationAction(ISD::UINT_TO_FP, MVT::v4i64, Legal);
1412 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
1413 setOperationAction(ISD::FP_TO_SINT, MVT::v4i64, Legal);
1414 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
1415 setOperationAction(ISD::FP_TO_UINT, MVT::v4i64, Legal);
1416 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
1419 if (Subtarget->hasVLX()) {
1420 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1421 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1422 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1423 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
1425 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1426 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
1427 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1429 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1430 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1431 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1432 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1433 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1434 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1435 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1436 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1437 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1438 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1439 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1440 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1441 if (Subtarget->hasDQI()) {
1442 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1443 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1445 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1446 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1447 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1448 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1449 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1450 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1451 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1452 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1453 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1454 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1456 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1457 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1458 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1459 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1460 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1462 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1463 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1465 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1467 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1468 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1469 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1470 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1471 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1472 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1473 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1474 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1475 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1476 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1477 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1479 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1480 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1481 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1482 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1483 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1484 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1485 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1486 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1488 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1489 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1491 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1492 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1494 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1496 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1497 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1499 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1500 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1502 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1503 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1505 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1506 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1507 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1508 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1509 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1510 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1512 if (Subtarget->hasCDI()) {
1513 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1514 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1515 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1516 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i32, Legal);
1518 setOperationAction(ISD::CTLZ, MVT::v8i16, Custom);
1519 setOperationAction(ISD::CTLZ, MVT::v16i8, Custom);
1520 setOperationAction(ISD::CTLZ, MVT::v16i16, Custom);
1521 setOperationAction(ISD::CTLZ, MVT::v32i8, Custom);
1522 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i16, Custom);
1523 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i8, Custom);
1524 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v16i16, Custom);
1525 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i8, Custom);
1527 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1528 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i32, Custom);
1530 if (Subtarget->hasVLX()) {
1531 setOperationAction(ISD::CTLZ, MVT::v4i64, Legal);
1532 setOperationAction(ISD::CTLZ, MVT::v8i32, Legal);
1533 setOperationAction(ISD::CTLZ, MVT::v2i64, Legal);
1534 setOperationAction(ISD::CTLZ, MVT::v4i32, Legal);
1535 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Legal);
1536 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Legal);
1537 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Legal);
1538 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Legal);
1540 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i64, Custom);
1541 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i32, Custom);
1542 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
1543 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
1545 setOperationAction(ISD::CTLZ, MVT::v4i64, Custom);
1546 setOperationAction(ISD::CTLZ, MVT::v8i32, Custom);
1547 setOperationAction(ISD::CTLZ, MVT::v2i64, Custom);
1548 setOperationAction(ISD::CTLZ, MVT::v4i32, Custom);
1549 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i64, Custom);
1550 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i32, Custom);
1551 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v2i64, Custom);
1552 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v4i32, Custom);
1554 } // Subtarget->hasCDI()
1556 if (Subtarget->hasDQI()) {
1557 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1558 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1559 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1561 // Custom lower several nodes.
1562 for (MVT VT : MVT::vector_valuetypes()) {
1563 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1565 setOperationAction(ISD::AND, VT, Legal);
1566 setOperationAction(ISD::OR, VT, Legal);
1567 setOperationAction(ISD::XOR, VT, Legal);
1569 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1570 setOperationAction(ISD::MGATHER, VT, Custom);
1571 setOperationAction(ISD::MSCATTER, VT, Custom);
1573 // Extract subvector is special because the value type
1574 // (result) is 256/128-bit but the source is 512-bit wide.
1575 if (VT.is128BitVector() || VT.is256BitVector()) {
1576 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1578 if (VT.getVectorElementType() == MVT::i1)
1579 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1581 // Do not attempt to custom lower other non-512-bit vectors
1582 if (!VT.is512BitVector())
1585 if (EltSize >= 32) {
1586 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1587 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1588 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1589 setOperationAction(ISD::VSELECT, VT, Legal);
1590 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1591 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1592 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1593 setOperationAction(ISD::MLOAD, VT, Legal);
1594 setOperationAction(ISD::MSTORE, VT, Legal);
1597 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1598 MVT VT = (MVT::SimpleValueType)i;
1600 // Do not attempt to promote non-512-bit vectors.
1601 if (!VT.is512BitVector())
1604 setOperationAction(ISD::SELECT, VT, Promote);
1605 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1609 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1610 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1611 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1613 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1614 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1616 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1617 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1618 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1619 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1620 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1621 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1622 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1623 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1624 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1625 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1626 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1627 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Legal);
1628 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Legal);
1629 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i16, Custom);
1630 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i8, Custom);
1631 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1632 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1633 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i16, Custom);
1634 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i8, Custom);
1635 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v32i16, Custom);
1636 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v64i8, Custom);
1637 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1638 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1639 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1640 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1641 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1642 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i16, Custom);
1644 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1645 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1646 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1647 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1648 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i16, Custom);
1649 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i8, Custom);
1650 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1651 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1652 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1653 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1654 setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);
1655 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);
1656 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v64i1, Custom);
1658 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1659 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1660 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1661 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1662 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1663 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1664 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1665 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1667 setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);
1668 setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);
1669 if (Subtarget->hasVLX())
1670 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);
1672 if (Subtarget->hasCDI()) {
1673 setOperationAction(ISD::CTLZ, MVT::v32i16, Custom);
1674 setOperationAction(ISD::CTLZ, MVT::v64i8, Custom);
1675 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v32i16, Custom);
1676 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v64i8, Custom);
1679 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1680 const MVT VT = (MVT::SimpleValueType)i;
1682 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1684 // Do not attempt to promote non-512-bit vectors.
1685 if (!VT.is512BitVector())
1689 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1690 setOperationAction(ISD::VSELECT, VT, Legal);
1695 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1696 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1697 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1699 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1700 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1701 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1702 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1703 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1704 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1705 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1706 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1707 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1708 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1709 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i1, Custom);
1710 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i1, Custom);
1712 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1713 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1714 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1715 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1716 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1717 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1718 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1719 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1721 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1722 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1723 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1724 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1725 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1726 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1727 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1728 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1731 // We want to custom lower some of our intrinsics.
1732 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1733 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1734 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1735 if (!Subtarget->is64Bit())
1736 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1738 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1739 // handle type legalization for these operations here.
1741 // FIXME: We really should do custom legalization for addition and
1742 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1743 // than generic legalization for 64-bit multiplication-with-overflow, though.
1744 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1745 // Add/Sub/Mul with overflow operations are custom lowered.
1747 setOperationAction(ISD::SADDO, VT, Custom);
1748 setOperationAction(ISD::UADDO, VT, Custom);
1749 setOperationAction(ISD::SSUBO, VT, Custom);
1750 setOperationAction(ISD::USUBO, VT, Custom);
1751 setOperationAction(ISD::SMULO, VT, Custom);
1752 setOperationAction(ISD::UMULO, VT, Custom);
1755 if (!Subtarget->is64Bit()) {
1756 // These libcalls are not available in 32-bit.
1757 setLibcallName(RTLIB::SHL_I128, nullptr);
1758 setLibcallName(RTLIB::SRL_I128, nullptr);
1759 setLibcallName(RTLIB::SRA_I128, nullptr);
1762 // Combine sin / cos into one node or libcall if possible.
1763 if (Subtarget->hasSinCos()) {
1764 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1765 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1766 if (Subtarget->isTargetDarwin()) {
1767 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1768 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1769 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1770 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1774 if (Subtarget->isTargetWin64()) {
1775 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1776 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1777 setOperationAction(ISD::SREM, MVT::i128, Custom);
1778 setOperationAction(ISD::UREM, MVT::i128, Custom);
1779 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1780 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1783 // We have target-specific dag combine patterns for the following nodes:
1784 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1785 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1786 setTargetDAGCombine(ISD::BITCAST);
1787 setTargetDAGCombine(ISD::VSELECT);
1788 setTargetDAGCombine(ISD::SELECT);
1789 setTargetDAGCombine(ISD::SHL);
1790 setTargetDAGCombine(ISD::SRA);
1791 setTargetDAGCombine(ISD::SRL);
1792 setTargetDAGCombine(ISD::OR);
1793 setTargetDAGCombine(ISD::AND);
1794 setTargetDAGCombine(ISD::ADD);
1795 setTargetDAGCombine(ISD::FADD);
1796 setTargetDAGCombine(ISD::FSUB);
1797 setTargetDAGCombine(ISD::FMA);
1798 setTargetDAGCombine(ISD::SUB);
1799 setTargetDAGCombine(ISD::LOAD);
1800 setTargetDAGCombine(ISD::MLOAD);
1801 setTargetDAGCombine(ISD::STORE);
1802 setTargetDAGCombine(ISD::MSTORE);
1803 setTargetDAGCombine(ISD::ZERO_EXTEND);
1804 setTargetDAGCombine(ISD::ANY_EXTEND);
1805 setTargetDAGCombine(ISD::SIGN_EXTEND);
1806 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1807 setTargetDAGCombine(ISD::SINT_TO_FP);
1808 setTargetDAGCombine(ISD::UINT_TO_FP);
1809 setTargetDAGCombine(ISD::SETCC);
1810 setTargetDAGCombine(ISD::BUILD_VECTOR);
1811 setTargetDAGCombine(ISD::MUL);
1812 setTargetDAGCombine(ISD::XOR);
1814 computeRegisterProperties(Subtarget->getRegisterInfo());
1816 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1817 MaxStoresPerMemsetOptSize = 8;
1818 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1819 MaxStoresPerMemcpyOptSize = 4;
1820 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1821 MaxStoresPerMemmoveOptSize = 4;
1822 setPrefLoopAlignment(4); // 2^4 bytes.
1824 // A predictable cmov does not hurt on an in-order CPU.
1825 // FIXME: Use a CPU attribute to trigger this, not a CPU model.
1826 PredictableSelectIsExpensive = !Subtarget->isAtom();
1827 EnableExtLdPromotion = true;
1828 setPrefFunctionAlignment(4); // 2^4 bytes.
1830 verifyIntrinsicTables();
1833 // This has so far only been implemented for 64-bit MachO.
1834 bool X86TargetLowering::useLoadStackGuardNode() const {
1835 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1838 TargetLoweringBase::LegalizeTypeAction
1839 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1840 if (ExperimentalVectorWideningLegalization &&
1841 VT.getVectorNumElements() != 1 &&
1842 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1843 return TypeWidenVector;
1845 return TargetLoweringBase::getPreferredVectorAction(VT);
1848 EVT X86TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1851 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1853 const unsigned NumElts = VT.getVectorNumElements();
1854 const EVT EltVT = VT.getVectorElementType();
1855 if (VT.is512BitVector()) {
1856 if (Subtarget->hasAVX512())
1857 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1858 EltVT == MVT::f32 || EltVT == MVT::f64)
1860 case 8: return MVT::v8i1;
1861 case 16: return MVT::v16i1;
1863 if (Subtarget->hasBWI())
1864 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1866 case 32: return MVT::v32i1;
1867 case 64: return MVT::v64i1;
1871 if (VT.is256BitVector() || VT.is128BitVector()) {
1872 if (Subtarget->hasVLX())
1873 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1874 EltVT == MVT::f32 || EltVT == MVT::f64)
1876 case 2: return MVT::v2i1;
1877 case 4: return MVT::v4i1;
1878 case 8: return MVT::v8i1;
1880 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1881 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1883 case 8: return MVT::v8i1;
1884 case 16: return MVT::v16i1;
1885 case 32: return MVT::v32i1;
1889 return VT.changeVectorElementTypeToInteger();
1892 /// Helper for getByValTypeAlignment to determine
1893 /// the desired ByVal argument alignment.
1894 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1897 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1898 if (VTy->getBitWidth() == 128)
1900 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1901 unsigned EltAlign = 0;
1902 getMaxByValAlign(ATy->getElementType(), EltAlign);
1903 if (EltAlign > MaxAlign)
1904 MaxAlign = EltAlign;
1905 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1906 for (auto *EltTy : STy->elements()) {
1907 unsigned EltAlign = 0;
1908 getMaxByValAlign(EltTy, EltAlign);
1909 if (EltAlign > MaxAlign)
1910 MaxAlign = EltAlign;
1917 /// Return the desired alignment for ByVal aggregate
1918 /// function arguments in the caller parameter area. For X86, aggregates
1919 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1920 /// are at 4-byte boundaries.
1921 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty,
1922 const DataLayout &DL) const {
1923 if (Subtarget->is64Bit()) {
1924 // Max of 8 and alignment of type.
1925 unsigned TyAlign = DL.getABITypeAlignment(Ty);
1932 if (Subtarget->hasSSE1())
1933 getMaxByValAlign(Ty, Align);
1937 /// Returns the target specific optimal type for load
1938 /// and store operations as a result of memset, memcpy, and memmove
1939 /// lowering. If DstAlign is zero that means it's safe to destination
1940 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1941 /// means there isn't a need to check it against alignment requirement,
1942 /// probably because the source does not need to be loaded. If 'IsMemset' is
1943 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1944 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1945 /// source is constant so it does not need to be loaded.
1946 /// It returns EVT::Other if the type should be determined using generic
1947 /// target-independent logic.
1949 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1950 unsigned DstAlign, unsigned SrcAlign,
1951 bool IsMemset, bool ZeroMemset,
1953 MachineFunction &MF) const {
1954 const Function *F = MF.getFunction();
1955 if ((!IsMemset || ZeroMemset) &&
1956 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1958 (!Subtarget->isUnalignedMem16Slow() ||
1959 ((DstAlign == 0 || DstAlign >= 16) &&
1960 (SrcAlign == 0 || SrcAlign >= 16)))) {
1962 // FIXME: Check if unaligned 32-byte accesses are slow.
1963 if (Subtarget->hasInt256())
1965 if (Subtarget->hasFp256())
1968 if (Subtarget->hasSSE2())
1970 if (Subtarget->hasSSE1())
1972 } else if (!MemcpyStrSrc && Size >= 8 &&
1973 !Subtarget->is64Bit() &&
1974 Subtarget->hasSSE2()) {
1975 // Do not use f64 to lower memcpy if source is string constant. It's
1976 // better to use i32 to avoid the loads.
1980 // This is a compromise. If we reach here, unaligned accesses may be slow on
1981 // this target. However, creating smaller, aligned accesses could be even
1982 // slower and would certainly be a lot more code.
1983 if (Subtarget->is64Bit() && Size >= 8)
1988 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1990 return X86ScalarSSEf32;
1991 else if (VT == MVT::f64)
1992 return X86ScalarSSEf64;
1997 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
2002 switch (VT.getSizeInBits()) {
2004 // 8-byte and under are always assumed to be fast.
2008 *Fast = !Subtarget->isUnalignedMem16Slow();
2011 *Fast = !Subtarget->isUnalignedMem32Slow();
2013 // TODO: What about AVX-512 (512-bit) accesses?
2016 // Misaligned accesses of any size are always allowed.
2020 /// Return the entry encoding for a jump table in the
2021 /// current function. The returned value is a member of the
2022 /// MachineJumpTableInfo::JTEntryKind enum.
2023 unsigned X86TargetLowering::getJumpTableEncoding() const {
2024 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
2026 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2027 Subtarget->isPICStyleGOT())
2028 return MachineJumpTableInfo::EK_Custom32;
2030 // Otherwise, use the normal jump table encoding heuristics.
2031 return TargetLowering::getJumpTableEncoding();
2034 bool X86TargetLowering::useSoftFloat() const {
2035 return Subtarget->useSoftFloat();
2039 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
2040 const MachineBasicBlock *MBB,
2041 unsigned uid,MCContext &Ctx) const{
2042 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
2043 Subtarget->isPICStyleGOT());
2044 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
2046 return MCSymbolRefExpr::create(MBB->getSymbol(),
2047 MCSymbolRefExpr::VK_GOTOFF, Ctx);
2050 /// Returns relocation base for the given PIC jumptable.
2051 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
2052 SelectionDAG &DAG) const {
2053 if (!Subtarget->is64Bit())
2054 // This doesn't have SDLoc associated with it, but is not really the
2055 // same as a Register.
2056 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
2057 getPointerTy(DAG.getDataLayout()));
2061 /// This returns the relocation base for the given PIC jumptable,
2062 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
2063 const MCExpr *X86TargetLowering::
2064 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
2065 MCContext &Ctx) const {
2066 // X86-64 uses RIP relative addressing based on the jump table label.
2067 if (Subtarget->isPICStyleRIPRel())
2068 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
2070 // Otherwise, the reference is relative to the PIC base.
2071 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
2074 std::pair<const TargetRegisterClass *, uint8_t>
2075 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2077 const TargetRegisterClass *RRC = nullptr;
2079 switch (VT.SimpleTy) {
2081 return TargetLowering::findRepresentativeClass(TRI, VT);
2082 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
2083 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
2086 RRC = &X86::VR64RegClass;
2088 case MVT::f32: case MVT::f64:
2089 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
2090 case MVT::v4f32: case MVT::v2f64:
2091 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
2093 RRC = &X86::VR128RegClass;
2096 return std::make_pair(RRC, Cost);
2099 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
2100 unsigned &Offset) const {
2101 if (!Subtarget->isTargetLinux())
2104 if (Subtarget->is64Bit()) {
2105 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
2107 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2119 /// Android provides a fixed TLS slot for the SafeStack pointer.
2120 /// See the definition of TLS_SLOT_SAFESTACK in
2121 /// https://android.googlesource.com/platform/bionic/+/master/libc/private/bionic_tls.h
2122 bool X86TargetLowering::getSafeStackPointerLocation(unsigned &AddressSpace,
2123 unsigned &Offset) const {
2124 if (!Subtarget->isTargetAndroid())
2127 if (Subtarget->is64Bit()) {
2128 // %fs:0x48, unless we're using a Kernel code model, in which case it's %gs:
2130 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
2142 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
2143 unsigned DestAS) const {
2144 assert(SrcAS != DestAS && "Expected different address spaces!");
2146 return SrcAS < 256 && DestAS < 256;
2149 //===----------------------------------------------------------------------===//
2150 // Return Value Calling Convention Implementation
2151 //===----------------------------------------------------------------------===//
2153 #include "X86GenCallingConv.inc"
2155 bool X86TargetLowering::CanLowerReturn(
2156 CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg,
2157 const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
2158 SmallVector<CCValAssign, 16> RVLocs;
2159 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2160 return CCInfo.CheckReturn(Outs, RetCC_X86);
2163 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
2164 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
2169 X86TargetLowering::LowerReturn(SDValue Chain,
2170 CallingConv::ID CallConv, bool isVarArg,
2171 const SmallVectorImpl<ISD::OutputArg> &Outs,
2172 const SmallVectorImpl<SDValue> &OutVals,
2173 SDLoc dl, SelectionDAG &DAG) const {
2174 MachineFunction &MF = DAG.getMachineFunction();
2175 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2177 SmallVector<CCValAssign, 16> RVLocs;
2178 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2179 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2182 SmallVector<SDValue, 6> RetOps;
2183 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2184 // Operand #1 = Bytes To Pop
2185 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2188 // Copy the result values into the output registers.
2189 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2190 CCValAssign &VA = RVLocs[i];
2191 assert(VA.isRegLoc() && "Can only return in registers!");
2192 SDValue ValToCopy = OutVals[i];
2193 EVT ValVT = ValToCopy.getValueType();
2195 // Promote values to the appropriate types.
2196 if (VA.getLocInfo() == CCValAssign::SExt)
2197 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2198 else if (VA.getLocInfo() == CCValAssign::ZExt)
2199 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2200 else if (VA.getLocInfo() == CCValAssign::AExt) {
2201 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2202 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2204 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2206 else if (VA.getLocInfo() == CCValAssign::BCvt)
2207 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2209 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2210 "Unexpected FP-extend for return value.");
2212 // If this is x86-64, and we disabled SSE, we can't return FP values,
2213 // or SSE or MMX vectors.
2214 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2215 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2216 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2217 report_fatal_error("SSE register return with SSE disabled");
2219 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2220 // llvm-gcc has never done it right and no one has noticed, so this
2221 // should be OK for now.
2222 if (ValVT == MVT::f64 &&
2223 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2224 report_fatal_error("SSE2 register return with SSE2 disabled");
2226 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2227 // the RET instruction and handled by the FP Stackifier.
2228 if (VA.getLocReg() == X86::FP0 ||
2229 VA.getLocReg() == X86::FP1) {
2230 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2231 // change the value to the FP stack register class.
2232 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2233 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2234 RetOps.push_back(ValToCopy);
2235 // Don't emit a copytoreg.
2239 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2240 // which is returned in RAX / RDX.
2241 if (Subtarget->is64Bit()) {
2242 if (ValVT == MVT::x86mmx) {
2243 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2244 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2245 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2247 // If we don't have SSE2 available, convert to v4f32 so the generated
2248 // register is legal.
2249 if (!Subtarget->hasSSE2())
2250 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2255 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2256 Flag = Chain.getValue(1);
2257 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2260 // All x86 ABIs require that for returning structs by value we copy
2261 // the sret argument into %rax/%eax (depending on ABI) for the return.
2262 // We saved the argument into a virtual register in the entry block,
2263 // so now we copy the value out and into %rax/%eax.
2265 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2266 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2267 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2268 // either case FuncInfo->setSRetReturnReg() will have been called.
2269 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2270 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg,
2271 getPointerTy(MF.getDataLayout()));
2274 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2275 X86::RAX : X86::EAX;
2276 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2277 Flag = Chain.getValue(1);
2279 // RAX/EAX now acts like a return value.
2281 DAG.getRegister(RetValReg, getPointerTy(DAG.getDataLayout())));
2284 RetOps[0] = Chain; // Update chain.
2286 // Add the flag if we have it.
2288 RetOps.push_back(Flag);
2290 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2293 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2294 if (N->getNumValues() != 1)
2296 if (!N->hasNUsesOfValue(1, 0))
2299 SDValue TCChain = Chain;
2300 SDNode *Copy = *N->use_begin();
2301 if (Copy->getOpcode() == ISD::CopyToReg) {
2302 // If the copy has a glue operand, we conservatively assume it isn't safe to
2303 // perform a tail call.
2304 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2306 TCChain = Copy->getOperand(0);
2307 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2310 bool HasRet = false;
2311 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2313 if (UI->getOpcode() != X86ISD::RET_FLAG)
2315 // If we are returning more than one value, we can definitely
2316 // not make a tail call see PR19530
2317 if (UI->getNumOperands() > 4)
2319 if (UI->getNumOperands() == 4 &&
2320 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2333 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2334 ISD::NodeType ExtendKind) const {
2336 // TODO: Is this also valid on 32-bit?
2337 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2338 ReturnMVT = MVT::i8;
2340 ReturnMVT = MVT::i32;
2342 EVT MinVT = getRegisterType(Context, ReturnMVT);
2343 return VT.bitsLT(MinVT) ? MinVT : VT;
2346 /// Lower the result values of a call into the
2347 /// appropriate copies out of appropriate physical registers.
2350 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2351 CallingConv::ID CallConv, bool isVarArg,
2352 const SmallVectorImpl<ISD::InputArg> &Ins,
2353 SDLoc dl, SelectionDAG &DAG,
2354 SmallVectorImpl<SDValue> &InVals) const {
2356 // Assign locations to each value returned by this call.
2357 SmallVector<CCValAssign, 16> RVLocs;
2358 bool Is64Bit = Subtarget->is64Bit();
2359 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2361 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2363 // Copy all of the result registers out of their specified physreg.
2364 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2365 CCValAssign &VA = RVLocs[i];
2366 EVT CopyVT = VA.getLocVT();
2368 // If this is x86-64, and we disabled SSE, we can't return FP values
2369 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2370 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2371 report_fatal_error("SSE register return with SSE disabled");
2374 // If we prefer to use the value in xmm registers, copy it out as f80 and
2375 // use a truncate to move it from fp stack reg to xmm reg.
2376 bool RoundAfterCopy = false;
2377 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2378 isScalarFPTypeInSSEReg(VA.getValVT())) {
2380 RoundAfterCopy = (CopyVT != VA.getLocVT());
2383 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2384 CopyVT, InFlag).getValue(1);
2385 SDValue Val = Chain.getValue(0);
2388 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2389 // This truncation won't change the value.
2390 DAG.getIntPtrConstant(1, dl));
2392 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2393 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2395 InFlag = Chain.getValue(2);
2396 InVals.push_back(Val);
2402 //===----------------------------------------------------------------------===//
2403 // C & StdCall & Fast Calling Convention implementation
2404 //===----------------------------------------------------------------------===//
2405 // StdCall calling convention seems to be standard for many Windows' API
2406 // routines and around. It differs from C calling convention just a little:
2407 // callee should clean up the stack, not caller. Symbols should be also
2408 // decorated in some fancy way :) It doesn't support any vector arguments.
2409 // For info on fast calling convention see Fast Calling Convention (tail call)
2410 // implementation LowerX86_32FastCCCallTo.
2412 /// CallIsStructReturn - Determines whether a call uses struct return
2414 enum StructReturnType {
2419 static StructReturnType
2420 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2422 return NotStructReturn;
2424 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2425 if (!Flags.isSRet())
2426 return NotStructReturn;
2427 if (Flags.isInReg())
2428 return RegStructReturn;
2429 return StackStructReturn;
2432 /// Determines whether a function uses struct return semantics.
2433 static StructReturnType
2434 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2436 return NotStructReturn;
2438 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2439 if (!Flags.isSRet())
2440 return NotStructReturn;
2441 if (Flags.isInReg())
2442 return RegStructReturn;
2443 return StackStructReturn;
2446 /// Make a copy of an aggregate at address specified by "Src" to address
2447 /// "Dst" with size and alignment information specified by the specific
2448 /// parameter attribute. The copy will be passed as a byval function parameter.
2450 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2451 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2453 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2455 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2456 /*isVolatile*/false, /*AlwaysInline=*/true,
2457 /*isTailCall*/false,
2458 MachinePointerInfo(), MachinePointerInfo());
2461 /// Return true if the calling convention is one that
2462 /// supports tail call optimization.
2463 static bool IsTailCallConvention(CallingConv::ID CC) {
2464 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2465 CC == CallingConv::HiPE || CC == CallingConv::HHVM);
2468 /// \brief Return true if the calling convention is a C calling convention.
2469 static bool IsCCallConvention(CallingConv::ID CC) {
2470 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2471 CC == CallingConv::X86_64_SysV);
2474 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2476 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2477 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2481 CallingConv::ID CalleeCC = CS.getCallingConv();
2482 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2488 /// Return true if the function is being made into
2489 /// a tailcall target by changing its ABI.
2490 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2491 bool GuaranteedTailCallOpt) {
2492 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2496 X86TargetLowering::LowerMemArgument(SDValue Chain,
2497 CallingConv::ID CallConv,
2498 const SmallVectorImpl<ISD::InputArg> &Ins,
2499 SDLoc dl, SelectionDAG &DAG,
2500 const CCValAssign &VA,
2501 MachineFrameInfo *MFI,
2503 // Create the nodes corresponding to a load from this parameter slot.
2504 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2505 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2506 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2507 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2510 // If value is passed by pointer we have address passed instead of the value
2512 bool ExtendedInMem = VA.isExtInLoc() &&
2513 VA.getValVT().getScalarType() == MVT::i1;
2515 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2516 ValVT = VA.getLocVT();
2518 ValVT = VA.getValVT();
2520 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2521 // changed with more analysis.
2522 // In case of tail call optimization mark all arguments mutable. Since they
2523 // could be overwritten by lowering of arguments in case of a tail call.
2524 if (Flags.isByVal()) {
2525 unsigned Bytes = Flags.getByValSize();
2526 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2527 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2528 return DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2530 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2531 VA.getLocMemOffset(), isImmutable);
2532 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2533 SDValue Val = DAG.getLoad(
2534 ValVT, dl, Chain, FIN,
2535 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2537 return ExtendedInMem ?
2538 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2542 // FIXME: Get this from tablegen.
2543 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2544 const X86Subtarget *Subtarget) {
2545 assert(Subtarget->is64Bit());
2547 if (Subtarget->isCallingConvWin64(CallConv)) {
2548 static const MCPhysReg GPR64ArgRegsWin64[] = {
2549 X86::RCX, X86::RDX, X86::R8, X86::R9
2551 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2554 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2555 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2557 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2560 // FIXME: Get this from tablegen.
2561 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2562 CallingConv::ID CallConv,
2563 const X86Subtarget *Subtarget) {
2564 assert(Subtarget->is64Bit());
2565 if (Subtarget->isCallingConvWin64(CallConv)) {
2566 // The XMM registers which might contain var arg parameters are shadowed
2567 // in their paired GPR. So we only need to save the GPR to their home
2569 // TODO: __vectorcall will change this.
2573 const Function *Fn = MF.getFunction();
2574 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2575 bool isSoftFloat = Subtarget->useSoftFloat();
2576 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2577 "SSE register cannot be used when SSE is disabled!");
2578 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2579 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2583 static const MCPhysReg XMMArgRegs64Bit[] = {
2584 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2585 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2587 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2590 SDValue X86TargetLowering::LowerFormalArguments(
2591 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2592 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2593 SmallVectorImpl<SDValue> &InVals) const {
2594 MachineFunction &MF = DAG.getMachineFunction();
2595 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2596 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2598 const Function* Fn = MF.getFunction();
2599 if (Fn->hasExternalLinkage() &&
2600 Subtarget->isTargetCygMing() &&
2601 Fn->getName() == "main")
2602 FuncInfo->setForceFramePointer(true);
2604 MachineFrameInfo *MFI = MF.getFrameInfo();
2605 bool Is64Bit = Subtarget->is64Bit();
2606 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2608 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2609 "Var args not supported with calling convention fastcc, ghc or hipe");
2611 // Assign locations to all of the incoming arguments.
2612 SmallVector<CCValAssign, 16> ArgLocs;
2613 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2615 // Allocate shadow area for Win64
2617 CCInfo.AllocateStack(32, 8);
2619 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2621 unsigned LastVal = ~0U;
2623 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2624 CCValAssign &VA = ArgLocs[i];
2625 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2627 assert(VA.getValNo() != LastVal &&
2628 "Don't support value assigned to multiple locs yet");
2630 LastVal = VA.getValNo();
2632 if (VA.isRegLoc()) {
2633 EVT RegVT = VA.getLocVT();
2634 const TargetRegisterClass *RC;
2635 if (RegVT == MVT::i32)
2636 RC = &X86::GR32RegClass;
2637 else if (Is64Bit && RegVT == MVT::i64)
2638 RC = &X86::GR64RegClass;
2639 else if (RegVT == MVT::f32)
2640 RC = &X86::FR32RegClass;
2641 else if (RegVT == MVT::f64)
2642 RC = &X86::FR64RegClass;
2643 else if (RegVT.is512BitVector())
2644 RC = &X86::VR512RegClass;
2645 else if (RegVT.is256BitVector())
2646 RC = &X86::VR256RegClass;
2647 else if (RegVT.is128BitVector())
2648 RC = &X86::VR128RegClass;
2649 else if (RegVT == MVT::x86mmx)
2650 RC = &X86::VR64RegClass;
2651 else if (RegVT == MVT::i1)
2652 RC = &X86::VK1RegClass;
2653 else if (RegVT == MVT::v8i1)
2654 RC = &X86::VK8RegClass;
2655 else if (RegVT == MVT::v16i1)
2656 RC = &X86::VK16RegClass;
2657 else if (RegVT == MVT::v32i1)
2658 RC = &X86::VK32RegClass;
2659 else if (RegVT == MVT::v64i1)
2660 RC = &X86::VK64RegClass;
2662 llvm_unreachable("Unknown argument type!");
2664 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2665 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2667 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2668 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2670 if (VA.getLocInfo() == CCValAssign::SExt)
2671 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2672 DAG.getValueType(VA.getValVT()));
2673 else if (VA.getLocInfo() == CCValAssign::ZExt)
2674 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2675 DAG.getValueType(VA.getValVT()));
2676 else if (VA.getLocInfo() == CCValAssign::BCvt)
2677 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2679 if (VA.isExtInLoc()) {
2680 // Handle MMX values passed in XMM regs.
2681 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2682 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2684 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2687 assert(VA.isMemLoc());
2688 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2691 // If value is passed via pointer - do a load.
2692 if (VA.getLocInfo() == CCValAssign::Indirect)
2693 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2694 MachinePointerInfo(), false, false, false, 0);
2696 InVals.push_back(ArgValue);
2699 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2700 // All x86 ABIs require that for returning structs by value we copy the
2701 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2702 // the argument into a virtual register so that we can access it from the
2704 if (Ins[i].Flags.isSRet()) {
2705 unsigned Reg = FuncInfo->getSRetReturnReg();
2707 MVT PtrTy = getPointerTy(DAG.getDataLayout());
2708 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2709 FuncInfo->setSRetReturnReg(Reg);
2711 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2712 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2717 unsigned StackSize = CCInfo.getNextStackOffset();
2718 // Align stack specially for tail calls.
2719 if (FuncIsMadeTailCallSafe(CallConv,
2720 MF.getTarget().Options.GuaranteedTailCallOpt))
2721 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2723 // If the function takes variable number of arguments, make a frame index for
2724 // the start of the first vararg value... for expansion of llvm.va_start. We
2725 // can skip this if there are no va_start calls.
2726 if (MFI->hasVAStart() &&
2727 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2728 CallConv != CallingConv::X86_ThisCall))) {
2729 FuncInfo->setVarArgsFrameIndex(
2730 MFI->CreateFixedObject(1, StackSize, true));
2733 MachineModuleInfo &MMI = MF.getMMI();
2735 // Figure out if XMM registers are in use.
2736 assert(!(Subtarget->useSoftFloat() &&
2737 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2738 "SSE register cannot be used when SSE is disabled!");
2740 // 64-bit calling conventions support varargs and register parameters, so we
2741 // have to do extra work to spill them in the prologue.
2742 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2743 // Find the first unallocated argument registers.
2744 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2745 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2746 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2747 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2748 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2749 "SSE register cannot be used when SSE is disabled!");
2751 // Gather all the live in physical registers.
2752 SmallVector<SDValue, 6> LiveGPRs;
2753 SmallVector<SDValue, 8> LiveXMMRegs;
2755 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2756 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2758 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2760 if (!ArgXMMs.empty()) {
2761 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2762 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2763 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2764 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2765 LiveXMMRegs.push_back(
2766 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2771 // Get to the caller-allocated home save location. Add 8 to account
2772 // for the return address.
2773 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2774 FuncInfo->setRegSaveFrameIndex(
2775 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2776 // Fixup to set vararg frame on shadow area (4 x i64).
2778 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2780 // For X86-64, if there are vararg parameters that are passed via
2781 // registers, then we must store them to their spots on the stack so
2782 // they may be loaded by deferencing the result of va_next.
2783 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2784 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2785 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2786 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2789 // Store the integer parameter registers.
2790 SmallVector<SDValue, 8> MemOps;
2791 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2792 getPointerTy(DAG.getDataLayout()));
2793 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2794 for (SDValue Val : LiveGPRs) {
2795 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2796 RSFIN, DAG.getIntPtrConstant(Offset, dl));
2798 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2799 MachinePointerInfo::getFixedStack(
2800 DAG.getMachineFunction(),
2801 FuncInfo->getRegSaveFrameIndex(), Offset),
2803 MemOps.push_back(Store);
2807 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2808 // Now store the XMM (fp + vector) parameter registers.
2809 SmallVector<SDValue, 12> SaveXMMOps;
2810 SaveXMMOps.push_back(Chain);
2811 SaveXMMOps.push_back(ALVal);
2812 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2813 FuncInfo->getRegSaveFrameIndex(), dl));
2814 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2815 FuncInfo->getVarArgsFPOffset(), dl));
2816 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2818 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2819 MVT::Other, SaveXMMOps));
2822 if (!MemOps.empty())
2823 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2826 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2827 // Find the largest legal vector type.
2828 MVT VecVT = MVT::Other;
2829 // FIXME: Only some x86_32 calling conventions support AVX512.
2830 if (Subtarget->hasAVX512() &&
2831 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2832 CallConv == CallingConv::Intel_OCL_BI)))
2833 VecVT = MVT::v16f32;
2834 else if (Subtarget->hasAVX())
2836 else if (Subtarget->hasSSE2())
2839 // We forward some GPRs and some vector types.
2840 SmallVector<MVT, 2> RegParmTypes;
2841 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2842 RegParmTypes.push_back(IntVT);
2843 if (VecVT != MVT::Other)
2844 RegParmTypes.push_back(VecVT);
2846 // Compute the set of forwarded registers. The rest are scratch.
2847 SmallVectorImpl<ForwardedRegister> &Forwards =
2848 FuncInfo->getForwardedMustTailRegParms();
2849 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2851 // Conservatively forward AL on x86_64, since it might be used for varargs.
2852 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2853 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2854 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2857 // Copy all forwards from physical to virtual registers.
2858 for (ForwardedRegister &F : Forwards) {
2859 // FIXME: Can we use a less constrained schedule?
2860 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2861 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2862 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2866 // Some CCs need callee pop.
2867 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2868 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2869 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2871 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2872 // If this is an sret function, the return should pop the hidden pointer.
2873 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2874 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2875 argsAreStructReturn(Ins) == StackStructReturn)
2876 FuncInfo->setBytesToPopOnReturn(4);
2880 // RegSaveFrameIndex is X86-64 only.
2881 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2882 if (CallConv == CallingConv::X86_FastCall ||
2883 CallConv == CallingConv::X86_ThisCall)
2884 // fastcc functions can't have varargs.
2885 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2888 FuncInfo->setArgumentStackSize(StackSize);
2890 if (MMI.hasWinEHFuncInfo(Fn)) {
2892 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2893 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2894 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2895 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2896 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2897 MachinePointerInfo::getFixedStack(
2898 DAG.getMachineFunction(), UnwindHelpFI),
2899 /*isVolatile=*/true,
2900 /*isNonTemporal=*/false, /*Alignment=*/0);
2902 // Functions using Win32 EH are considered to have opaque SP adjustments
2903 // to force local variables to be addressed from the frame or base
2905 MFI->setHasOpaqueSPAdjustment(true);
2913 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2914 SDValue StackPtr, SDValue Arg,
2915 SDLoc dl, SelectionDAG &DAG,
2916 const CCValAssign &VA,
2917 ISD::ArgFlagsTy Flags) const {
2918 unsigned LocMemOffset = VA.getLocMemOffset();
2919 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2920 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
2922 if (Flags.isByVal())
2923 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2925 return DAG.getStore(
2926 Chain, dl, Arg, PtrOff,
2927 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
2931 /// Emit a load of return address if tail call
2932 /// optimization is performed and it is required.
2934 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2935 SDValue &OutRetAddr, SDValue Chain,
2936 bool IsTailCall, bool Is64Bit,
2937 int FPDiff, SDLoc dl) const {
2938 // Adjust the Return address stack slot.
2939 EVT VT = getPointerTy(DAG.getDataLayout());
2940 OutRetAddr = getReturnAddressFrameIndex(DAG);
2942 // Load the "old" Return address.
2943 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2944 false, false, false, 0);
2945 return SDValue(OutRetAddr.getNode(), 1);
2948 /// Emit a store of the return address if tail call
2949 /// optimization is performed and it is required (FPDiff!=0).
2950 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2951 SDValue Chain, SDValue RetAddrFrIdx,
2952 EVT PtrVT, unsigned SlotSize,
2953 int FPDiff, SDLoc dl) {
2954 // Store the return address to the appropriate stack slot.
2955 if (!FPDiff) return Chain;
2956 // Calculate the new stack slot for the return address.
2957 int NewReturnAddrFI =
2958 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2960 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2961 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2962 MachinePointerInfo::getFixedStack(
2963 DAG.getMachineFunction(), NewReturnAddrFI),
2968 /// Returns a vector_shuffle mask for an movs{s|d}, movd
2969 /// operation of specified width.
2970 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
2972 unsigned NumElems = VT.getVectorNumElements();
2973 SmallVector<int, 8> Mask;
2974 Mask.push_back(NumElems);
2975 for (unsigned i = 1; i != NumElems; ++i)
2977 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2981 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2982 SmallVectorImpl<SDValue> &InVals) const {
2983 SelectionDAG &DAG = CLI.DAG;
2985 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2986 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2987 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2988 SDValue Chain = CLI.Chain;
2989 SDValue Callee = CLI.Callee;
2990 CallingConv::ID CallConv = CLI.CallConv;
2991 bool &isTailCall = CLI.IsTailCall;
2992 bool isVarArg = CLI.IsVarArg;
2994 MachineFunction &MF = DAG.getMachineFunction();
2995 bool Is64Bit = Subtarget->is64Bit();
2996 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2997 StructReturnType SR = callIsStructReturn(Outs);
2998 bool IsSibcall = false;
2999 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
3000 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
3002 if (Attr.getValueAsString() == "true")
3005 if (Subtarget->isPICStyleGOT() &&
3006 !MF.getTarget().Options.GuaranteedTailCallOpt) {
3007 // If we are using a GOT, disable tail calls to external symbols with
3008 // default visibility. Tail calling such a symbol requires using a GOT
3009 // relocation, which forces early binding of the symbol. This breaks code
3010 // that require lazy function symbol resolution. Using musttail or
3011 // GuaranteedTailCallOpt will override this.
3012 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3013 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
3014 G->getGlobal()->hasDefaultVisibility()))
3018 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
3020 // Force this to be a tail call. The verifier rules are enough to ensure
3021 // that we can lower this successfully without moving the return address
3024 } else if (isTailCall) {
3025 // Check if it's really possible to do a tail call.
3026 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
3027 isVarArg, SR != NotStructReturn,
3028 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
3029 Outs, OutVals, Ins, DAG);
3031 // Sibcalls are automatically detected tailcalls which do not require
3033 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
3040 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
3041 "Var args not supported with calling convention fastcc, ghc or hipe");
3043 // Analyze operands of the call, assigning locations to each operand.
3044 SmallVector<CCValAssign, 16> ArgLocs;
3045 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
3047 // Allocate shadow area for Win64
3049 CCInfo.AllocateStack(32, 8);
3051 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3053 // Get a count of how many bytes are to be pushed on the stack.
3054 unsigned NumBytes = CCInfo.getAlignedCallFrameSize();
3056 // This is a sibcall. The memory operands are available in caller's
3057 // own caller's stack.
3059 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
3060 IsTailCallConvention(CallConv))
3061 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
3064 if (isTailCall && !IsSibcall && !IsMustTail) {
3065 // Lower arguments at fp - stackoffset + fpdiff.
3066 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
3068 FPDiff = NumBytesCallerPushed - NumBytes;
3070 // Set the delta of movement of the returnaddr stackslot.
3071 // But only set if delta is greater than previous delta.
3072 if (FPDiff < X86Info->getTCReturnAddrDelta())
3073 X86Info->setTCReturnAddrDelta(FPDiff);
3076 unsigned NumBytesToPush = NumBytes;
3077 unsigned NumBytesToPop = NumBytes;
3079 // If we have an inalloca argument, all stack space has already been allocated
3080 // for us and be right at the top of the stack. We don't support multiple
3081 // arguments passed in memory when using inalloca.
3082 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
3084 if (!ArgLocs.back().isMemLoc())
3085 report_fatal_error("cannot use inalloca attribute on a register "
3087 if (ArgLocs.back().getLocMemOffset() != 0)
3088 report_fatal_error("any parameter with the inalloca attribute must be "
3089 "the only memory argument");
3093 Chain = DAG.getCALLSEQ_START(
3094 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
3096 SDValue RetAddrFrIdx;
3097 // Load return address for tail calls.
3098 if (isTailCall && FPDiff)
3099 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
3100 Is64Bit, FPDiff, dl);
3102 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3103 SmallVector<SDValue, 8> MemOpChains;
3106 // Walk the register/memloc assignments, inserting copies/loads. In the case
3107 // of tail call optimization arguments are handle later.
3108 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3109 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3110 // Skip inalloca arguments, they have already been written.
3111 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3112 if (Flags.isInAlloca())
3115 CCValAssign &VA = ArgLocs[i];
3116 EVT RegVT = VA.getLocVT();
3117 SDValue Arg = OutVals[i];
3118 bool isByVal = Flags.isByVal();
3120 // Promote the value if needed.
3121 switch (VA.getLocInfo()) {
3122 default: llvm_unreachable("Unknown loc info!");
3123 case CCValAssign::Full: break;
3124 case CCValAssign::SExt:
3125 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3127 case CCValAssign::ZExt:
3128 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
3130 case CCValAssign::AExt:
3131 if (Arg.getValueType().isVector() &&
3132 Arg.getValueType().getScalarType() == MVT::i1)
3133 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
3134 else if (RegVT.is128BitVector()) {
3135 // Special case: passing MMX values in XMM registers.
3136 Arg = DAG.getBitcast(MVT::i64, Arg);
3137 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
3138 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
3140 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
3142 case CCValAssign::BCvt:
3143 Arg = DAG.getBitcast(RegVT, Arg);
3145 case CCValAssign::Indirect: {
3146 // Store the argument.
3147 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
3148 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
3149 Chain = DAG.getStore(
3150 Chain, dl, Arg, SpillSlot,
3151 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3158 if (VA.isRegLoc()) {
3159 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3160 if (isVarArg && IsWin64) {
3161 // Win64 ABI requires argument XMM reg to be copied to the corresponding
3162 // shadow reg if callee is a varargs function.
3163 unsigned ShadowReg = 0;
3164 switch (VA.getLocReg()) {
3165 case X86::XMM0: ShadowReg = X86::RCX; break;
3166 case X86::XMM1: ShadowReg = X86::RDX; break;
3167 case X86::XMM2: ShadowReg = X86::R8; break;
3168 case X86::XMM3: ShadowReg = X86::R9; break;
3171 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3173 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3174 assert(VA.isMemLoc());
3175 if (!StackPtr.getNode())
3176 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3177 getPointerTy(DAG.getDataLayout()));
3178 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3179 dl, DAG, VA, Flags));
3183 if (!MemOpChains.empty())
3184 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3186 if (Subtarget->isPICStyleGOT()) {
3187 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3190 RegsToPass.push_back(std::make_pair(
3191 unsigned(X86::EBX), DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(),
3192 getPointerTy(DAG.getDataLayout()))));
3194 // If we are tail calling and generating PIC/GOT style code load the
3195 // address of the callee into ECX. The value in ecx is used as target of
3196 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3197 // for tail calls on PIC/GOT architectures. Normally we would just put the
3198 // address of GOT into ebx and then call target@PLT. But for tail calls
3199 // ebx would be restored (since ebx is callee saved) before jumping to the
3202 // Note: The actual moving to ECX is done further down.
3203 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3204 if (G && !G->getGlobal()->hasLocalLinkage() &&
3205 G->getGlobal()->hasDefaultVisibility())
3206 Callee = LowerGlobalAddress(Callee, DAG);
3207 else if (isa<ExternalSymbolSDNode>(Callee))
3208 Callee = LowerExternalSymbol(Callee, DAG);
3212 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3213 // From AMD64 ABI document:
3214 // For calls that may call functions that use varargs or stdargs
3215 // (prototype-less calls or calls to functions containing ellipsis (...) in
3216 // the declaration) %al is used as hidden argument to specify the number
3217 // of SSE registers used. The contents of %al do not need to match exactly
3218 // the number of registers, but must be an ubound on the number of SSE
3219 // registers used and is in the range 0 - 8 inclusive.
3221 // Count the number of XMM registers allocated.
3222 static const MCPhysReg XMMArgRegs[] = {
3223 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3224 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3226 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3227 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3228 && "SSE registers cannot be used when SSE is disabled");
3230 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3231 DAG.getConstant(NumXMMRegs, dl,
3235 if (isVarArg && IsMustTail) {
3236 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3237 for (const auto &F : Forwards) {
3238 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3239 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3243 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3244 // don't need this because the eligibility check rejects calls that require
3245 // shuffling arguments passed in memory.
3246 if (!IsSibcall && isTailCall) {
3247 // Force all the incoming stack arguments to be loaded from the stack
3248 // before any new outgoing arguments are stored to the stack, because the
3249 // outgoing stack slots may alias the incoming argument stack slots, and
3250 // the alias isn't otherwise explicit. This is slightly more conservative
3251 // than necessary, because it means that each store effectively depends
3252 // on every argument instead of just those arguments it would clobber.
3253 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3255 SmallVector<SDValue, 8> MemOpChains2;
3258 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3259 CCValAssign &VA = ArgLocs[i];
3262 assert(VA.isMemLoc());
3263 SDValue Arg = OutVals[i];
3264 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3265 // Skip inalloca arguments. They don't require any work.
3266 if (Flags.isInAlloca())
3268 // Create frame index.
3269 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3270 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3271 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3272 FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3274 if (Flags.isByVal()) {
3275 // Copy relative to framepointer.
3276 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3277 if (!StackPtr.getNode())
3278 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3279 getPointerTy(DAG.getDataLayout()));
3280 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
3283 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3287 // Store relative to framepointer.
3288 MemOpChains2.push_back(DAG.getStore(
3289 ArgChain, dl, Arg, FIN,
3290 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3295 if (!MemOpChains2.empty())
3296 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3298 // Store the return address to the appropriate stack slot.
3299 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3300 getPointerTy(DAG.getDataLayout()),
3301 RegInfo->getSlotSize(), FPDiff, dl);
3304 // Build a sequence of copy-to-reg nodes chained together with token chain
3305 // and flag operands which copy the outgoing args into registers.
3307 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3308 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3309 RegsToPass[i].second, InFlag);
3310 InFlag = Chain.getValue(1);
3313 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3314 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3315 // In the 64-bit large code model, we have to make all calls
3316 // through a register, since the call instruction's 32-bit
3317 // pc-relative offset may not be large enough to hold the whole
3319 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3320 // If the callee is a GlobalAddress node (quite common, every direct call
3321 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3323 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3325 // We should use extra load for direct calls to dllimported functions in
3327 const GlobalValue *GV = G->getGlobal();
3328 if (!GV->hasDLLImportStorageClass()) {
3329 unsigned char OpFlags = 0;
3330 bool ExtraLoad = false;
3331 unsigned WrapperKind = ISD::DELETED_NODE;
3333 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3334 // external symbols most go through the PLT in PIC mode. If the symbol
3335 // has hidden or protected visibility, or if it is static or local, then
3336 // we don't need to use the PLT - we can directly call it.
3337 if (Subtarget->isTargetELF() &&
3338 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3339 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3340 OpFlags = X86II::MO_PLT;
3341 } else if (Subtarget->isPICStyleStubAny() &&
3342 !GV->isStrongDefinitionForLinker() &&
3343 (!Subtarget->getTargetTriple().isMacOSX() ||
3344 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3345 // PC-relative references to external symbols should go through $stub,
3346 // unless we're building with the leopard linker or later, which
3347 // automatically synthesizes these stubs.
3348 OpFlags = X86II::MO_DARWIN_STUB;
3349 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3350 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3351 // If the function is marked as non-lazy, generate an indirect call
3352 // which loads from the GOT directly. This avoids runtime overhead
3353 // at the cost of eager binding (and one extra byte of encoding).
3354 OpFlags = X86II::MO_GOTPCREL;
3355 WrapperKind = X86ISD::WrapperRIP;
3359 Callee = DAG.getTargetGlobalAddress(
3360 GV, dl, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags);
3362 // Add a wrapper if needed.
3363 if (WrapperKind != ISD::DELETED_NODE)
3364 Callee = DAG.getNode(X86ISD::WrapperRIP, dl,
3365 getPointerTy(DAG.getDataLayout()), Callee);
3366 // Add extra indirection if needed.
3368 Callee = DAG.getLoad(
3369 getPointerTy(DAG.getDataLayout()), dl, DAG.getEntryNode(), Callee,
3370 MachinePointerInfo::getGOT(DAG.getMachineFunction()), false, false,
3373 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3374 unsigned char OpFlags = 0;
3376 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3377 // external symbols should go through the PLT.
3378 if (Subtarget->isTargetELF() &&
3379 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3380 OpFlags = X86II::MO_PLT;
3381 } else if (Subtarget->isPICStyleStubAny() &&
3382 (!Subtarget->getTargetTriple().isMacOSX() ||
3383 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3384 // PC-relative references to external symbols should go through $stub,
3385 // unless we're building with the leopard linker or later, which
3386 // automatically synthesizes these stubs.
3387 OpFlags = X86II::MO_DARWIN_STUB;
3390 Callee = DAG.getTargetExternalSymbol(
3391 S->getSymbol(), getPointerTy(DAG.getDataLayout()), OpFlags);
3392 } else if (Subtarget->isTarget64BitILP32() &&
3393 Callee->getValueType(0) == MVT::i32) {
3394 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3395 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3398 // Returns a chain & a flag for retval copy to use.
3399 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3400 SmallVector<SDValue, 8> Ops;
3402 if (!IsSibcall && isTailCall) {
3403 Chain = DAG.getCALLSEQ_END(Chain,
3404 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3405 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3406 InFlag = Chain.getValue(1);
3409 Ops.push_back(Chain);
3410 Ops.push_back(Callee);
3413 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3415 // Add argument registers to the end of the list so that they are known live
3417 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3418 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3419 RegsToPass[i].second.getValueType()));
3421 // Add a register mask operand representing the call-preserved registers.
3422 const uint32_t *Mask = RegInfo->getCallPreservedMask(MF, CallConv);
3423 assert(Mask && "Missing call preserved mask for calling convention");
3425 // If this is an invoke in a 32-bit function using a funclet-based
3426 // personality, assume the function clobbers all registers. If an exception
3427 // is thrown, the runtime will not restore CSRs.
3428 // FIXME: Model this more precisely so that we can register allocate across
3429 // the normal edge and spill and fill across the exceptional edge.
3430 if (!Is64Bit && CLI.CS && CLI.CS->isInvoke()) {
3431 const Function *CallerFn = MF.getFunction();
3432 EHPersonality Pers =
3433 CallerFn->hasPersonalityFn()
3434 ? classifyEHPersonality(CallerFn->getPersonalityFn())
3435 : EHPersonality::Unknown;
3436 if (isFuncletEHPersonality(Pers))
3437 Mask = RegInfo->getNoPreservedMask();
3440 Ops.push_back(DAG.getRegisterMask(Mask));
3442 if (InFlag.getNode())
3443 Ops.push_back(InFlag);
3447 //// If this is the first return lowered for this function, add the regs
3448 //// to the liveout set for the function.
3449 // This isn't right, although it's probably harmless on x86; liveouts
3450 // should be computed from returns not tail calls. Consider a void
3451 // function making a tail call to a function returning int.
3452 MF.getFrameInfo()->setHasTailCall();
3453 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3456 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3457 InFlag = Chain.getValue(1);
3459 // Create the CALLSEQ_END node.
3460 unsigned NumBytesForCalleeToPop;
3461 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3462 DAG.getTarget().Options.GuaranteedTailCallOpt))
3463 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3464 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3465 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3466 SR == StackStructReturn)
3467 // If this is a call to a struct-return function, the callee
3468 // pops the hidden struct pointer, so we have to push it back.
3469 // This is common for Darwin/X86, Linux & Mingw32 targets.
3470 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3471 NumBytesForCalleeToPop = 4;
3473 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3475 // Returns a flag for retval copy to use.
3477 Chain = DAG.getCALLSEQ_END(Chain,
3478 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3479 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3482 InFlag = Chain.getValue(1);
3485 // Handle result values, copying them out of physregs into vregs that we
3487 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3488 Ins, dl, DAG, InVals);
3491 //===----------------------------------------------------------------------===//
3492 // Fast Calling Convention (tail call) implementation
3493 //===----------------------------------------------------------------------===//
3495 // Like std call, callee cleans arguments, convention except that ECX is
3496 // reserved for storing the tail called function address. Only 2 registers are
3497 // free for argument passing (inreg). Tail call optimization is performed
3499 // * tailcallopt is enabled
3500 // * caller/callee are fastcc
3501 // On X86_64 architecture with GOT-style position independent code only local
3502 // (within module) calls are supported at the moment.
3503 // To keep the stack aligned according to platform abi the function
3504 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3505 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3506 // If a tail called function callee has more arguments than the caller the
3507 // caller needs to make sure that there is room to move the RETADDR to. This is
3508 // achieved by reserving an area the size of the argument delta right after the
3509 // original RETADDR, but before the saved framepointer or the spilled registers
3510 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3522 /// Make the stack size align e.g 16n + 12 aligned for a 16-byte align
3525 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3526 SelectionDAG& DAG) const {
3527 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3528 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3529 unsigned StackAlignment = TFI.getStackAlignment();
3530 uint64_t AlignMask = StackAlignment - 1;
3531 int64_t Offset = StackSize;
3532 unsigned SlotSize = RegInfo->getSlotSize();
3533 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3534 // Number smaller than 12 so just add the difference.
3535 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3537 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3538 Offset = ((~AlignMask) & Offset) + StackAlignment +
3539 (StackAlignment-SlotSize);
3544 /// Return true if the given stack call argument is already available in the
3545 /// same position (relatively) of the caller's incoming argument stack.
3547 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3548 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3549 const X86InstrInfo *TII) {
3550 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3552 if (Arg.getOpcode() == ISD::CopyFromReg) {
3553 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3554 if (!TargetRegisterInfo::isVirtualRegister(VR))
3556 MachineInstr *Def = MRI->getVRegDef(VR);
3559 if (!Flags.isByVal()) {
3560 if (!TII->isLoadFromStackSlot(Def, FI))
3563 unsigned Opcode = Def->getOpcode();
3564 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3565 Opcode == X86::LEA64_32r) &&
3566 Def->getOperand(1).isFI()) {
3567 FI = Def->getOperand(1).getIndex();
3568 Bytes = Flags.getByValSize();
3572 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3573 if (Flags.isByVal())
3574 // ByVal argument is passed in as a pointer but it's now being
3575 // dereferenced. e.g.
3576 // define @foo(%struct.X* %A) {
3577 // tail call @bar(%struct.X* byval %A)
3580 SDValue Ptr = Ld->getBasePtr();
3581 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3584 FI = FINode->getIndex();
3585 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3586 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3587 FI = FINode->getIndex();
3588 Bytes = Flags.getByValSize();
3592 assert(FI != INT_MAX);
3593 if (!MFI->isFixedObjectIndex(FI))
3595 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3598 /// Check whether the call is eligible for tail call optimization. Targets
3599 /// that want to do tail call optimization should implement this function.
3600 bool X86TargetLowering::IsEligibleForTailCallOptimization(
3601 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
3602 bool isCalleeStructRet, bool isCallerStructRet, Type *RetTy,
3603 const SmallVectorImpl<ISD::OutputArg> &Outs,
3604 const SmallVectorImpl<SDValue> &OutVals,
3605 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const {
3606 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3609 // If -tailcallopt is specified, make fastcc functions tail-callable.
3610 const MachineFunction &MF = DAG.getMachineFunction();
3611 const Function *CallerF = MF.getFunction();
3613 // If the function return type is x86_fp80 and the callee return type is not,
3614 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3615 // perform a tailcall optimization here.
3616 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3619 CallingConv::ID CallerCC = CallerF->getCallingConv();
3620 bool CCMatch = CallerCC == CalleeCC;
3621 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3622 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3624 // Win64 functions have extra shadow space for argument homing. Don't do the
3625 // sibcall if the caller and callee have mismatched expectations for this
3627 if (IsCalleeWin64 != IsCallerWin64)
3630 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3631 if (IsTailCallConvention(CalleeCC) && CCMatch)
3636 // Look for obvious safe cases to perform tail call optimization that do not
3637 // require ABI changes. This is what gcc calls sibcall.
3639 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3640 // emit a special epilogue.
3641 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3642 if (RegInfo->needsStackRealignment(MF))
3645 // Also avoid sibcall optimization if either caller or callee uses struct
3646 // return semantics.
3647 if (isCalleeStructRet || isCallerStructRet)
3650 // An stdcall/thiscall caller is expected to clean up its arguments; the
3651 // callee isn't going to do that.
3652 // FIXME: this is more restrictive than needed. We could produce a tailcall
3653 // when the stack adjustment matches. For example, with a thiscall that takes
3654 // only one argument.
3655 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3656 CallerCC == CallingConv::X86_ThisCall))
3659 // Do not sibcall optimize vararg calls unless all arguments are passed via
3661 if (isVarArg && !Outs.empty()) {
3663 // Optimizing for varargs on Win64 is unlikely to be safe without
3664 // additional testing.
3665 if (IsCalleeWin64 || IsCallerWin64)
3668 SmallVector<CCValAssign, 16> ArgLocs;
3669 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3672 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3673 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3674 if (!ArgLocs[i].isRegLoc())
3678 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3679 // stack. Therefore, if it's not used by the call it is not safe to optimize
3680 // this into a sibcall.
3681 bool Unused = false;
3682 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3689 SmallVector<CCValAssign, 16> RVLocs;
3690 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3692 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3693 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3694 CCValAssign &VA = RVLocs[i];
3695 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3700 // If the calling conventions do not match, then we'd better make sure the
3701 // results are returned in the same way as what the caller expects.
3703 SmallVector<CCValAssign, 16> RVLocs1;
3704 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3706 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3708 SmallVector<CCValAssign, 16> RVLocs2;
3709 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3711 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3713 if (RVLocs1.size() != RVLocs2.size())
3715 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3716 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3718 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3720 if (RVLocs1[i].isRegLoc()) {
3721 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3724 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3730 // If the callee takes no arguments then go on to check the results of the
3732 if (!Outs.empty()) {
3733 // Check if stack adjustment is needed. For now, do not do this if any
3734 // argument is passed on the stack.
3735 SmallVector<CCValAssign, 16> ArgLocs;
3736 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3739 // Allocate shadow area for Win64
3741 CCInfo.AllocateStack(32, 8);
3743 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3744 if (CCInfo.getNextStackOffset()) {
3745 MachineFunction &MF = DAG.getMachineFunction();
3746 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3749 // Check if the arguments are already laid out in the right way as
3750 // the caller's fixed stack objects.
3751 MachineFrameInfo *MFI = MF.getFrameInfo();
3752 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3753 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3754 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3755 CCValAssign &VA = ArgLocs[i];
3756 SDValue Arg = OutVals[i];
3757 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3758 if (VA.getLocInfo() == CCValAssign::Indirect)
3760 if (!VA.isRegLoc()) {
3761 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3768 // If the tailcall address may be in a register, then make sure it's
3769 // possible to register allocate for it. In 32-bit, the call address can
3770 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3771 // callee-saved registers are restored. These happen to be the same
3772 // registers used to pass 'inreg' arguments so watch out for those.
3773 if (!Subtarget->is64Bit() &&
3774 ((!isa<GlobalAddressSDNode>(Callee) &&
3775 !isa<ExternalSymbolSDNode>(Callee)) ||
3776 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3777 unsigned NumInRegs = 0;
3778 // In PIC we need an extra register to formulate the address computation
3780 unsigned MaxInRegs =
3781 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3783 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3784 CCValAssign &VA = ArgLocs[i];
3787 unsigned Reg = VA.getLocReg();
3790 case X86::EAX: case X86::EDX: case X86::ECX:
3791 if (++NumInRegs == MaxInRegs)
3803 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3804 const TargetLibraryInfo *libInfo) const {
3805 return X86::createFastISel(funcInfo, libInfo);
3808 //===----------------------------------------------------------------------===//
3809 // Other Lowering Hooks
3810 //===----------------------------------------------------------------------===//
3812 static bool MayFoldLoad(SDValue Op) {
3813 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3816 static bool MayFoldIntoStore(SDValue Op) {
3817 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3820 static bool isTargetShuffle(unsigned Opcode) {
3822 default: return false;
3823 case X86ISD::BLENDI:
3824 case X86ISD::PSHUFB:
3825 case X86ISD::PSHUFD:
3826 case X86ISD::PSHUFHW:
3827 case X86ISD::PSHUFLW:
3829 case X86ISD::PALIGNR:
3830 case X86ISD::MOVLHPS:
3831 case X86ISD::MOVLHPD:
3832 case X86ISD::MOVHLPS:
3833 case X86ISD::MOVLPS:
3834 case X86ISD::MOVLPD:
3835 case X86ISD::MOVSHDUP:
3836 case X86ISD::MOVSLDUP:
3837 case X86ISD::MOVDDUP:
3840 case X86ISD::UNPCKL:
3841 case X86ISD::UNPCKH:
3842 case X86ISD::VPERMILPI:
3843 case X86ISD::VPERM2X128:
3844 case X86ISD::VPERMI:
3845 case X86ISD::VPERMV:
3846 case X86ISD::VPERMV3:
3851 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3852 SDValue V1, unsigned TargetMask,
3853 SelectionDAG &DAG) {
3855 default: llvm_unreachable("Unknown x86 shuffle node");
3856 case X86ISD::PSHUFD:
3857 case X86ISD::PSHUFHW:
3858 case X86ISD::PSHUFLW:
3859 case X86ISD::VPERMILPI:
3860 case X86ISD::VPERMI:
3861 return DAG.getNode(Opc, dl, VT, V1,
3862 DAG.getConstant(TargetMask, dl, MVT::i8));
3866 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3867 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3869 default: llvm_unreachable("Unknown x86 shuffle node");
3870 case X86ISD::MOVLHPS:
3871 case X86ISD::MOVLHPD:
3872 case X86ISD::MOVHLPS:
3873 case X86ISD::MOVLPS:
3874 case X86ISD::MOVLPD:
3877 case X86ISD::UNPCKL:
3878 case X86ISD::UNPCKH:
3879 return DAG.getNode(Opc, dl, VT, V1, V2);
3883 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3884 MachineFunction &MF = DAG.getMachineFunction();
3885 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3886 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3887 int ReturnAddrIndex = FuncInfo->getRAIndex();
3889 if (ReturnAddrIndex == 0) {
3890 // Set up a frame object for the return address.
3891 unsigned SlotSize = RegInfo->getSlotSize();
3892 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3895 FuncInfo->setRAIndex(ReturnAddrIndex);
3898 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout()));
3901 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3902 bool hasSymbolicDisplacement) {
3903 // Offset should fit into 32 bit immediate field.
3904 if (!isInt<32>(Offset))
3907 // If we don't have a symbolic displacement - we don't have any extra
3909 if (!hasSymbolicDisplacement)
3912 // FIXME: Some tweaks might be needed for medium code model.
3913 if (M != CodeModel::Small && M != CodeModel::Kernel)
3916 // For small code model we assume that latest object is 16MB before end of 31
3917 // bits boundary. We may also accept pretty large negative constants knowing
3918 // that all objects are in the positive half of address space.
3919 if (M == CodeModel::Small && Offset < 16*1024*1024)
3922 // For kernel code model we know that all object resist in the negative half
3923 // of 32bits address space. We may not accept negative offsets, since they may
3924 // be just off and we may accept pretty large positive ones.
3925 if (M == CodeModel::Kernel && Offset >= 0)
3931 /// Determines whether the callee is required to pop its own arguments.
3932 /// Callee pop is necessary to support tail calls.
3933 bool X86::isCalleePop(CallingConv::ID CallingConv,
3934 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3936 if (IsTailCallConvention(CallingConv))
3937 return IsVarArg ? false : TailCallOpt;
3939 switch (CallingConv) {
3942 case CallingConv::X86_StdCall:
3943 case CallingConv::X86_FastCall:
3944 case CallingConv::X86_ThisCall:
3949 /// \brief Return true if the condition is an unsigned comparison operation.
3950 static bool isX86CCUnsigned(unsigned X86CC) {
3952 default: llvm_unreachable("Invalid integer condition!");
3953 case X86::COND_E: return true;
3954 case X86::COND_G: return false;
3955 case X86::COND_GE: return false;
3956 case X86::COND_L: return false;
3957 case X86::COND_LE: return false;
3958 case X86::COND_NE: return true;
3959 case X86::COND_B: return true;
3960 case X86::COND_A: return true;
3961 case X86::COND_BE: return true;
3962 case X86::COND_AE: return true;
3964 llvm_unreachable("covered switch fell through?!");
3967 /// Do a one-to-one translation of a ISD::CondCode to the X86-specific
3968 /// condition code, returning the condition code and the LHS/RHS of the
3969 /// comparison to make.
3970 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3971 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3973 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3974 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3975 // X > -1 -> X == 0, jump !sign.
3976 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3977 return X86::COND_NS;
3979 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3980 // X < 0 -> X == 0, jump on sign.
3983 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3985 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3986 return X86::COND_LE;
3990 switch (SetCCOpcode) {
3991 default: llvm_unreachable("Invalid integer condition!");
3992 case ISD::SETEQ: return X86::COND_E;
3993 case ISD::SETGT: return X86::COND_G;
3994 case ISD::SETGE: return X86::COND_GE;
3995 case ISD::SETLT: return X86::COND_L;
3996 case ISD::SETLE: return X86::COND_LE;
3997 case ISD::SETNE: return X86::COND_NE;
3998 case ISD::SETULT: return X86::COND_B;
3999 case ISD::SETUGT: return X86::COND_A;
4000 case ISD::SETULE: return X86::COND_BE;
4001 case ISD::SETUGE: return X86::COND_AE;
4005 // First determine if it is required or is profitable to flip the operands.
4007 // If LHS is a foldable load, but RHS is not, flip the condition.
4008 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
4009 !ISD::isNON_EXTLoad(RHS.getNode())) {
4010 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
4011 std::swap(LHS, RHS);
4014 switch (SetCCOpcode) {
4020 std::swap(LHS, RHS);
4024 // On a floating point condition, the flags are set as follows:
4026 // 0 | 0 | 0 | X > Y
4027 // 0 | 0 | 1 | X < Y
4028 // 1 | 0 | 0 | X == Y
4029 // 1 | 1 | 1 | unordered
4030 switch (SetCCOpcode) {
4031 default: llvm_unreachable("Condcode should be pre-legalized away");
4033 case ISD::SETEQ: return X86::COND_E;
4034 case ISD::SETOLT: // flipped
4036 case ISD::SETGT: return X86::COND_A;
4037 case ISD::SETOLE: // flipped
4039 case ISD::SETGE: return X86::COND_AE;
4040 case ISD::SETUGT: // flipped
4042 case ISD::SETLT: return X86::COND_B;
4043 case ISD::SETUGE: // flipped
4045 case ISD::SETLE: return X86::COND_BE;
4047 case ISD::SETNE: return X86::COND_NE;
4048 case ISD::SETUO: return X86::COND_P;
4049 case ISD::SETO: return X86::COND_NP;
4051 case ISD::SETUNE: return X86::COND_INVALID;
4055 /// Is there a floating point cmov for the specific X86 condition code?
4056 /// Current x86 isa includes the following FP cmov instructions:
4057 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
4058 static bool hasFPCMov(unsigned X86CC) {
4074 /// Returns true if the target can instruction select the
4075 /// specified FP immediate natively. If false, the legalizer will
4076 /// materialize the FP immediate as a load from a constant pool.
4077 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4078 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
4079 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
4085 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
4086 ISD::LoadExtType ExtTy,
4088 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
4089 // relocation target a movq or addq instruction: don't let the load shrink.
4090 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
4091 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
4092 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
4093 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
4097 /// \brief Returns true if it is beneficial to convert a load of a constant
4098 /// to just the constant itself.
4099 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
4101 assert(Ty->isIntegerTy());
4103 unsigned BitSize = Ty->getPrimitiveSizeInBits();
4104 if (BitSize == 0 || BitSize > 64)
4109 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
4110 unsigned Index) const {
4111 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
4114 return (Index == 0 || Index == ResVT.getVectorNumElements());
4117 bool X86TargetLowering::isCheapToSpeculateCttz() const {
4118 // Speculate cttz only if we can directly use TZCNT.
4119 return Subtarget->hasBMI();
4122 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
4123 // Speculate ctlz only if we can directly use LZCNT.
4124 return Subtarget->hasLZCNT();
4127 /// Return true if every element in Mask, beginning
4128 /// from position Pos and ending in Pos+Size is undef.
4129 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
4130 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
4136 /// Return true if Val is undef or if its value falls within the
4137 /// specified range (L, H].
4138 static bool isUndefOrInRange(int Val, int Low, int Hi) {
4139 return (Val < 0) || (Val >= Low && Val < Hi);
4142 /// Val is either less than zero (undef) or equal to the specified value.
4143 static bool isUndefOrEqual(int Val, int CmpVal) {
4144 return (Val < 0 || Val == CmpVal);
4147 /// Return true if every element in Mask, beginning
4148 /// from position Pos and ending in Pos+Size, falls within the specified
4149 /// sequential range (Low, Low+Size]. or is undef.
4150 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
4151 unsigned Pos, unsigned Size, int Low) {
4152 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
4153 if (!isUndefOrEqual(Mask[i], Low))
4158 /// Return true if the specified EXTRACT_SUBVECTOR operand specifies a vector
4159 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
4160 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
4161 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4162 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4165 // The index should be aligned on a vecWidth-bit boundary.
4167 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4169 MVT VT = N->getSimpleValueType(0);
4170 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4171 bool Result = (Index * ElSize) % vecWidth == 0;
4176 /// Return true if the specified INSERT_SUBVECTOR
4177 /// operand specifies a subvector insert that is suitable for input to
4178 /// insertion of 128 or 256-bit subvectors
4179 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
4180 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
4181 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4183 // The index should be aligned on a vecWidth-bit boundary.
4185 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4187 MVT VT = N->getSimpleValueType(0);
4188 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4189 bool Result = (Index * ElSize) % vecWidth == 0;
4194 bool X86::isVINSERT128Index(SDNode *N) {
4195 return isVINSERTIndex(N, 128);
4198 bool X86::isVINSERT256Index(SDNode *N) {
4199 return isVINSERTIndex(N, 256);
4202 bool X86::isVEXTRACT128Index(SDNode *N) {
4203 return isVEXTRACTIndex(N, 128);
4206 bool X86::isVEXTRACT256Index(SDNode *N) {
4207 return isVEXTRACTIndex(N, 256);
4210 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4211 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4212 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4213 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4216 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4218 MVT VecVT = N->getOperand(0).getSimpleValueType();
4219 MVT ElVT = VecVT.getVectorElementType();
4221 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4222 return Index / NumElemsPerChunk;
4225 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4226 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4227 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4228 llvm_unreachable("Illegal insert subvector for VINSERT");
4231 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4233 MVT VecVT = N->getSimpleValueType(0);
4234 MVT ElVT = VecVT.getVectorElementType();
4236 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4237 return Index / NumElemsPerChunk;
4240 /// Return the appropriate immediate to extract the specified
4241 /// EXTRACT_SUBVECTOR index with VEXTRACTF128 and VINSERTI128 instructions.
4242 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4243 return getExtractVEXTRACTImmediate(N, 128);
4246 /// Return the appropriate immediate to extract the specified
4247 /// EXTRACT_SUBVECTOR index with VEXTRACTF64x4 and VINSERTI64x4 instructions.
4248 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4249 return getExtractVEXTRACTImmediate(N, 256);
4252 /// Return the appropriate immediate to insert at the specified
4253 /// INSERT_SUBVECTOR index with VINSERTF128 and VINSERTI128 instructions.
4254 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4255 return getInsertVINSERTImmediate(N, 128);
4258 /// Return the appropriate immediate to insert at the specified
4259 /// INSERT_SUBVECTOR index with VINSERTF46x4 and VINSERTI64x4 instructions.
4260 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4261 return getInsertVINSERTImmediate(N, 256);
4264 /// Returns true if V is a constant integer zero.
4265 static bool isZero(SDValue V) {
4266 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4267 return C && C->isNullValue();
4270 /// Returns true if Elt is a constant zero or a floating point constant +0.0.
4271 bool X86::isZeroNode(SDValue Elt) {
4274 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4275 return CFP->getValueAPF().isPosZero();
4279 // Build a vector of constants
4280 // Use an UNDEF node if MaskElt == -1.
4281 // Spilt 64-bit constants in the 32-bit mode.
4282 static SDValue getConstVector(ArrayRef<int> Values, EVT VT,
4284 SDLoc dl, bool IsMask = false) {
4286 SmallVector<SDValue, 32> Ops;
4289 EVT ConstVecVT = VT;
4290 unsigned NumElts = VT.getVectorNumElements();
4291 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64);
4292 if (!In64BitMode && VT.getScalarType() == MVT::i64) {
4293 ConstVecVT = MVT::getVectorVT(MVT::i32, NumElts * 2);
4297 EVT EltVT = ConstVecVT.getScalarType();
4298 for (unsigned i = 0; i < NumElts; ++i) {
4299 bool IsUndef = Values[i] < 0 && IsMask;
4300 SDValue OpNode = IsUndef ? DAG.getUNDEF(EltVT) :
4301 DAG.getConstant(Values[i], dl, EltVT);
4302 Ops.push_back(OpNode);
4304 Ops.push_back(IsUndef ? DAG.getUNDEF(EltVT) :
4305 DAG.getConstant(0, dl, EltVT));
4307 SDValue ConstsNode = DAG.getNode(ISD::BUILD_VECTOR, dl, ConstVecVT, Ops);
4309 ConstsNode = DAG.getBitcast(VT, ConstsNode);
4313 /// Returns a vector of specified type with all zero elements.
4314 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4315 SelectionDAG &DAG, SDLoc dl) {
4316 assert(VT.isVector() && "Expected a vector type");
4318 // Always build SSE zero vectors as <4 x i32> bitcasted
4319 // to their dest type. This ensures they get CSE'd.
4321 if (VT.is128BitVector()) { // SSE
4322 if (Subtarget->hasSSE2()) { // SSE2
4323 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4324 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4326 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4327 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4329 } else if (VT.is256BitVector()) { // AVX
4330 if (Subtarget->hasInt256()) { // AVX2
4331 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4332 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4333 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4335 // 256-bit logic and arithmetic instructions in AVX are all
4336 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4337 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4338 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4339 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4341 } else if (VT.is512BitVector()) { // AVX-512
4342 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4343 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4344 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4345 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4346 } else if (VT.getScalarType() == MVT::i1) {
4348 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4349 && "Unexpected vector type");
4350 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4351 && "Unexpected vector type");
4352 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4353 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4354 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4356 llvm_unreachable("Unexpected vector type");
4358 return DAG.getBitcast(VT, Vec);
4361 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4362 SelectionDAG &DAG, SDLoc dl,
4363 unsigned vectorWidth) {
4364 assert((vectorWidth == 128 || vectorWidth == 256) &&
4365 "Unsupported vector width");
4366 EVT VT = Vec.getValueType();
4367 EVT ElVT = VT.getVectorElementType();
4368 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4369 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4370 VT.getVectorNumElements()/Factor);
4372 // Extract from UNDEF is UNDEF.
4373 if (Vec.getOpcode() == ISD::UNDEF)
4374 return DAG.getUNDEF(ResultVT);
4376 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4377 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4379 // This is the index of the first element of the vectorWidth-bit chunk
4381 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4384 // If the input is a buildvector just emit a smaller one.
4385 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4386 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4387 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4390 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4391 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4394 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4395 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4396 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4397 /// instructions or a simple subregister reference. Idx is an index in the
4398 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4399 /// lowering EXTRACT_VECTOR_ELT operations easier.
4400 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4401 SelectionDAG &DAG, SDLoc dl) {
4402 assert((Vec.getValueType().is256BitVector() ||
4403 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4404 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4407 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4408 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4409 SelectionDAG &DAG, SDLoc dl) {
4410 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4411 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4414 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4415 unsigned IdxVal, SelectionDAG &DAG,
4416 SDLoc dl, unsigned vectorWidth) {
4417 assert((vectorWidth == 128 || vectorWidth == 256) &&
4418 "Unsupported vector width");
4419 // Inserting UNDEF is Result
4420 if (Vec.getOpcode() == ISD::UNDEF)
4422 EVT VT = Vec.getValueType();
4423 EVT ElVT = VT.getVectorElementType();
4424 EVT ResultVT = Result.getValueType();
4426 // Insert the relevant vectorWidth bits.
4427 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4429 // This is the index of the first element of the vectorWidth-bit chunk
4431 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4434 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4435 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4438 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4439 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4440 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4441 /// simple superregister reference. Idx is an index in the 128 bits
4442 /// we want. It need not be aligned to a 128-bit boundary. That makes
4443 /// lowering INSERT_VECTOR_ELT operations easier.
4444 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4445 SelectionDAG &DAG, SDLoc dl) {
4446 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4448 // For insertion into the zero index (low half) of a 256-bit vector, it is
4449 // more efficient to generate a blend with immediate instead of an insert*128.
4450 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4451 // extend the subvector to the size of the result vector. Make sure that
4452 // we are not recursing on that node by checking for undef here.
4453 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4454 Result.getOpcode() != ISD::UNDEF) {
4455 EVT ResultVT = Result.getValueType();
4456 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4457 SDValue Undef = DAG.getUNDEF(ResultVT);
4458 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4461 // The blend instruction, and therefore its mask, depend on the data type.
4462 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4463 if (ScalarType.isFloatingPoint()) {
4464 // Choose either vblendps (float) or vblendpd (double).
4465 unsigned ScalarSize = ScalarType.getSizeInBits();
4466 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4467 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4468 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4469 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4472 const X86Subtarget &Subtarget =
4473 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4475 // AVX2 is needed for 256-bit integer blend support.
4476 // Integers must be cast to 32-bit because there is only vpblendd;
4477 // vpblendw can't be used for this because it has a handicapped mask.
4479 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4480 // is still more efficient than using the wrong domain vinsertf128 that
4481 // will be created by InsertSubVector().
4482 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4484 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4485 Vec256 = DAG.getBitcast(CastVT, Vec256);
4486 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4487 return DAG.getBitcast(ResultVT, Vec256);
4490 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4493 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4494 SelectionDAG &DAG, SDLoc dl) {
4495 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4496 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4499 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4500 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4501 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4502 /// large BUILD_VECTORS.
4503 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4504 unsigned NumElems, SelectionDAG &DAG,
4506 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4507 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4510 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4511 unsigned NumElems, SelectionDAG &DAG,
4513 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4514 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4517 /// Returns a vector of specified type with all bits set.
4518 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4519 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4520 /// Then bitcast to their original type, ensuring they get CSE'd.
4521 static SDValue getOnesVector(EVT VT, const X86Subtarget *Subtarget,
4522 SelectionDAG &DAG, SDLoc dl) {
4523 assert(VT.isVector() && "Expected a vector type");
4525 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4527 if (VT.is512BitVector()) {
4528 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4529 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4530 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4531 } else if (VT.is256BitVector()) {
4532 if (Subtarget->hasInt256()) { // AVX2
4533 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4534 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4536 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4537 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4539 } else if (VT.is128BitVector()) {
4540 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4542 llvm_unreachable("Unexpected vector type");
4544 return DAG.getBitcast(VT, Vec);
4547 /// Returns a vector_shuffle node for an unpackl operation.
4548 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4550 unsigned NumElems = VT.getVectorNumElements();
4551 SmallVector<int, 8> Mask;
4552 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4554 Mask.push_back(i + NumElems);
4556 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4559 /// Returns a vector_shuffle node for an unpackh operation.
4560 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4562 unsigned NumElems = VT.getVectorNumElements();
4563 SmallVector<int, 8> Mask;
4564 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4565 Mask.push_back(i + Half);
4566 Mask.push_back(i + NumElems + Half);
4568 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4571 /// Return a vector_shuffle of the specified vector of zero or undef vector.
4572 /// This produces a shuffle where the low element of V2 is swizzled into the
4573 /// zero/undef vector, landing at element Idx.
4574 /// This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4575 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4577 const X86Subtarget *Subtarget,
4578 SelectionDAG &DAG) {
4579 MVT VT = V2.getSimpleValueType();
4581 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4582 unsigned NumElems = VT.getVectorNumElements();
4583 SmallVector<int, 16> MaskVec;
4584 for (unsigned i = 0; i != NumElems; ++i)
4585 // If this is the insertion idx, put the low elt of V2 here.
4586 MaskVec.push_back(i == Idx ? NumElems : i);
4587 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4590 /// Calculates the shuffle mask corresponding to the target-specific opcode.
4591 /// Returns true if the Mask could be calculated. Sets IsUnary to true if only
4592 /// uses one source. Note that this will set IsUnary for shuffles which use a
4593 /// single input multiple times, and in those cases it will
4594 /// adjust the mask to only have indices within that single input.
4595 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4596 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4597 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4598 unsigned NumElems = VT.getVectorNumElements();
4602 bool IsFakeUnary = false;
4603 switch(N->getOpcode()) {
4604 case X86ISD::BLENDI:
4605 ImmN = N->getOperand(N->getNumOperands()-1);
4606 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4609 ImmN = N->getOperand(N->getNumOperands()-1);
4610 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4611 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4613 case X86ISD::UNPCKH:
4614 DecodeUNPCKHMask(VT, Mask);
4615 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4617 case X86ISD::UNPCKL:
4618 DecodeUNPCKLMask(VT, Mask);
4619 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4621 case X86ISD::MOVHLPS:
4622 DecodeMOVHLPSMask(NumElems, Mask);
4623 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4625 case X86ISD::MOVLHPS:
4626 DecodeMOVLHPSMask(NumElems, Mask);
4627 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4629 case X86ISD::PALIGNR:
4630 ImmN = N->getOperand(N->getNumOperands()-1);
4631 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4633 case X86ISD::PSHUFD:
4634 case X86ISD::VPERMILPI:
4635 ImmN = N->getOperand(N->getNumOperands()-1);
4636 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4639 case X86ISD::PSHUFHW:
4640 ImmN = N->getOperand(N->getNumOperands()-1);
4641 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4644 case X86ISD::PSHUFLW:
4645 ImmN = N->getOperand(N->getNumOperands()-1);
4646 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4649 case X86ISD::PSHUFB: {
4651 SDValue MaskNode = N->getOperand(1);
4652 while (MaskNode->getOpcode() == ISD::BITCAST)
4653 MaskNode = MaskNode->getOperand(0);
4655 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4656 // If we have a build-vector, then things are easy.
4657 EVT VT = MaskNode.getValueType();
4658 assert(VT.isVector() &&
4659 "Can't produce a non-vector with a build_vector!");
4660 if (!VT.isInteger())
4663 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4665 SmallVector<uint64_t, 32> RawMask;
4666 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4667 SDValue Op = MaskNode->getOperand(i);
4668 if (Op->getOpcode() == ISD::UNDEF) {
4669 RawMask.push_back((uint64_t)SM_SentinelUndef);
4672 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4675 APInt MaskElement = CN->getAPIntValue();
4677 // We now have to decode the element which could be any integer size and
4678 // extract each byte of it.
4679 for (int j = 0; j < NumBytesPerElement; ++j) {
4680 // Note that this is x86 and so always little endian: the low byte is
4681 // the first byte of the mask.
4682 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4683 MaskElement = MaskElement.lshr(8);
4686 DecodePSHUFBMask(RawMask, Mask);
4690 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4694 SDValue Ptr = MaskLoad->getBasePtr();
4695 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4696 Ptr->getOpcode() == X86ISD::WrapperRIP)
4697 Ptr = Ptr->getOperand(0);
4699 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4700 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4703 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4704 DecodePSHUFBMask(C, Mask);
4712 case X86ISD::VPERMI:
4713 ImmN = N->getOperand(N->getNumOperands()-1);
4714 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4719 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4721 case X86ISD::VPERM2X128:
4722 ImmN = N->getOperand(N->getNumOperands()-1);
4723 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4724 if (Mask.empty()) return false;
4725 // Mask only contains negative index if an element is zero.
4726 if (std::any_of(Mask.begin(), Mask.end(),
4727 [](int M){ return M == SM_SentinelZero; }))
4730 case X86ISD::MOVSLDUP:
4731 DecodeMOVSLDUPMask(VT, Mask);
4734 case X86ISD::MOVSHDUP:
4735 DecodeMOVSHDUPMask(VT, Mask);
4738 case X86ISD::MOVDDUP:
4739 DecodeMOVDDUPMask(VT, Mask);
4742 case X86ISD::MOVLHPD:
4743 case X86ISD::MOVLPD:
4744 case X86ISD::MOVLPS:
4745 // Not yet implemented
4747 case X86ISD::VPERMV: {
4749 SDValue MaskNode = N->getOperand(0);
4750 while (MaskNode->getOpcode() == ISD::BITCAST)
4751 MaskNode = MaskNode->getOperand(0);
4753 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements());
4754 SmallVector<uint64_t, 32> RawMask;
4755 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4756 // If we have a build-vector, then things are easy.
4757 assert(MaskNode.getValueType().isInteger() &&
4758 MaskNode.getValueType().getVectorNumElements() ==
4759 VT.getVectorNumElements());
4761 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4762 SDValue Op = MaskNode->getOperand(i);
4763 if (Op->getOpcode() == ISD::UNDEF)
4764 RawMask.push_back((uint64_t)SM_SentinelUndef);
4765 else if (isa<ConstantSDNode>(Op)) {
4766 APInt MaskElement = cast<ConstantSDNode>(Op)->getAPIntValue();
4767 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4771 DecodeVPERMVMask(RawMask, Mask);
4774 if (MaskNode->getOpcode() == X86ISD::VBROADCAST) {
4775 unsigned NumEltsInMask = MaskNode->getNumOperands();
4776 MaskNode = MaskNode->getOperand(0);
4777 auto *CN = dyn_cast<ConstantSDNode>(MaskNode);
4779 APInt MaskEltValue = CN->getAPIntValue();
4780 for (unsigned i = 0; i < NumEltsInMask; ++i)
4781 RawMask.push_back(MaskEltValue.getLoBits(MaskLoBits).getZExtValue());
4782 DecodeVPERMVMask(RawMask, Mask);
4785 // It may be a scalar load
4788 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4792 SDValue Ptr = MaskLoad->getBasePtr();
4793 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4794 Ptr->getOpcode() == X86ISD::WrapperRIP)
4795 Ptr = Ptr->getOperand(0);
4797 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4798 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4801 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4803 DecodeVPERMVMask(C, VT, Mask);
4810 case X86ISD::VPERMV3: {
4812 SDValue MaskNode = N->getOperand(1);
4813 while (MaskNode->getOpcode() == ISD::BITCAST)
4814 MaskNode = MaskNode->getOperand(1);
4816 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4817 // If we have a build-vector, then things are easy.
4818 assert(MaskNode.getValueType().isInteger() &&
4819 MaskNode.getValueType().getVectorNumElements() ==
4820 VT.getVectorNumElements());
4822 SmallVector<uint64_t, 32> RawMask;
4823 unsigned MaskLoBits = Log2_64(VT.getVectorNumElements()*2);
4825 for (unsigned i = 0; i < MaskNode->getNumOperands(); ++i) {
4826 SDValue Op = MaskNode->getOperand(i);
4827 if (Op->getOpcode() == ISD::UNDEF)
4828 RawMask.push_back((uint64_t)SM_SentinelUndef);
4830 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4833 APInt MaskElement = CN->getAPIntValue();
4834 RawMask.push_back(MaskElement.getLoBits(MaskLoBits).getZExtValue());
4837 DecodeVPERMV3Mask(RawMask, Mask);
4841 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4845 SDValue Ptr = MaskLoad->getBasePtr();
4846 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4847 Ptr->getOpcode() == X86ISD::WrapperRIP)
4848 Ptr = Ptr->getOperand(0);
4850 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4851 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4854 auto *C = dyn_cast<Constant>(MaskCP->getConstVal());
4856 DecodeVPERMV3Mask(C, VT, Mask);
4863 default: llvm_unreachable("unknown target shuffle node");
4866 // If we have a fake unary shuffle, the shuffle mask is spread across two
4867 // inputs that are actually the same node. Re-map the mask to always point
4868 // into the first input.
4871 if (M >= (int)Mask.size())
4877 /// Returns the scalar element that will make up the ith
4878 /// element of the result of the vector shuffle.
4879 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4882 return SDValue(); // Limit search depth.
4884 SDValue V = SDValue(N, 0);
4885 EVT VT = V.getValueType();
4886 unsigned Opcode = V.getOpcode();
4888 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4889 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4890 int Elt = SV->getMaskElt(Index);
4893 return DAG.getUNDEF(VT.getVectorElementType());
4895 unsigned NumElems = VT.getVectorNumElements();
4896 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4897 : SV->getOperand(1);
4898 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4901 // Recurse into target specific vector shuffles to find scalars.
4902 if (isTargetShuffle(Opcode)) {
4903 MVT ShufVT = V.getSimpleValueType();
4904 unsigned NumElems = ShufVT.getVectorNumElements();
4905 SmallVector<int, 16> ShuffleMask;
4908 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4911 int Elt = ShuffleMask[Index];
4913 return DAG.getUNDEF(ShufVT.getVectorElementType());
4915 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4917 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4921 // Actual nodes that may contain scalar elements
4922 if (Opcode == ISD::BITCAST) {
4923 V = V.getOperand(0);
4924 EVT SrcVT = V.getValueType();
4925 unsigned NumElems = VT.getVectorNumElements();
4927 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4931 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4932 return (Index == 0) ? V.getOperand(0)
4933 : DAG.getUNDEF(VT.getVectorElementType());
4935 if (V.getOpcode() == ISD::BUILD_VECTOR)
4936 return V.getOperand(Index);
4941 /// Custom lower build_vector of v16i8.
4942 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4943 unsigned NumNonZero, unsigned NumZero,
4945 const X86Subtarget* Subtarget,
4946 const TargetLowering &TLI) {
4954 // SSE4.1 - use PINSRB to insert each byte directly.
4955 if (Subtarget->hasSSE41()) {
4956 for (unsigned i = 0; i < 16; ++i) {
4957 bool isNonZero = (NonZeros & (1 << i)) != 0;
4961 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4963 V = DAG.getUNDEF(MVT::v16i8);
4966 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4967 MVT::v16i8, V, Op.getOperand(i),
4968 DAG.getIntPtrConstant(i, dl));
4975 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4976 for (unsigned i = 0; i < 16; ++i) {
4977 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4978 if (ThisIsNonZero && First) {
4980 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4982 V = DAG.getUNDEF(MVT::v8i16);
4987 SDValue ThisElt, LastElt;
4988 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4989 if (LastIsNonZero) {
4990 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4991 MVT::i16, Op.getOperand(i-1));
4993 if (ThisIsNonZero) {
4994 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4995 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4996 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4998 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
5002 if (ThisElt.getNode())
5003 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
5004 DAG.getIntPtrConstant(i/2, dl));
5008 return DAG.getBitcast(MVT::v16i8, V);
5011 /// Custom lower build_vector of v8i16.
5012 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
5013 unsigned NumNonZero, unsigned NumZero,
5015 const X86Subtarget* Subtarget,
5016 const TargetLowering &TLI) {
5023 for (unsigned i = 0; i < 8; ++i) {
5024 bool isNonZero = (NonZeros & (1 << i)) != 0;
5028 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
5030 V = DAG.getUNDEF(MVT::v8i16);
5033 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
5034 MVT::v8i16, V, Op.getOperand(i),
5035 DAG.getIntPtrConstant(i, dl));
5042 /// Custom lower build_vector of v4i32 or v4f32.
5043 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
5044 const X86Subtarget *Subtarget,
5045 const TargetLowering &TLI) {
5046 // Find all zeroable elements.
5047 std::bitset<4> Zeroable;
5048 for (int i=0; i < 4; ++i) {
5049 SDValue Elt = Op->getOperand(i);
5050 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
5052 assert(Zeroable.size() - Zeroable.count() > 1 &&
5053 "We expect at least two non-zero elements!");
5055 // We only know how to deal with build_vector nodes where elements are either
5056 // zeroable or extract_vector_elt with constant index.
5057 SDValue FirstNonZero;
5058 unsigned FirstNonZeroIdx;
5059 for (unsigned i=0; i < 4; ++i) {
5062 SDValue Elt = Op->getOperand(i);
5063 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5064 !isa<ConstantSDNode>(Elt.getOperand(1)))
5066 // Make sure that this node is extracting from a 128-bit vector.
5067 MVT VT = Elt.getOperand(0).getSimpleValueType();
5068 if (!VT.is128BitVector())
5070 if (!FirstNonZero.getNode()) {
5072 FirstNonZeroIdx = i;
5076 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
5077 SDValue V1 = FirstNonZero.getOperand(0);
5078 MVT VT = V1.getSimpleValueType();
5080 // See if this build_vector can be lowered as a blend with zero.
5082 unsigned EltMaskIdx, EltIdx;
5084 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
5085 if (Zeroable[EltIdx]) {
5086 // The zero vector will be on the right hand side.
5087 Mask[EltIdx] = EltIdx+4;
5091 Elt = Op->getOperand(EltIdx);
5092 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
5093 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
5094 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
5096 Mask[EltIdx] = EltIdx;
5100 // Let the shuffle legalizer deal with blend operations.
5101 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
5102 if (V1.getSimpleValueType() != VT)
5103 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
5104 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
5107 // See if we can lower this build_vector to a INSERTPS.
5108 if (!Subtarget->hasSSE41())
5111 SDValue V2 = Elt.getOperand(0);
5112 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
5115 bool CanFold = true;
5116 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
5120 SDValue Current = Op->getOperand(i);
5121 SDValue SrcVector = Current->getOperand(0);
5124 CanFold = SrcVector == V1 &&
5125 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
5131 assert(V1.getNode() && "Expected at least two non-zero elements!");
5132 if (V1.getSimpleValueType() != MVT::v4f32)
5133 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
5134 if (V2.getSimpleValueType() != MVT::v4f32)
5135 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
5137 // Ok, we can emit an INSERTPS instruction.
5138 unsigned ZMask = Zeroable.to_ulong();
5140 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
5141 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
5143 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
5144 DAG.getIntPtrConstant(InsertPSMask, DL));
5145 return DAG.getBitcast(VT, Result);
5148 /// Return a vector logical shift node.
5149 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
5150 unsigned NumBits, SelectionDAG &DAG,
5151 const TargetLowering &TLI, SDLoc dl) {
5152 assert(VT.is128BitVector() && "Unknown type for VShift");
5153 MVT ShVT = MVT::v2i64;
5154 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
5155 SrcOp = DAG.getBitcast(ShVT, SrcOp);
5156 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(DAG.getDataLayout(), VT);
5157 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
5158 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
5159 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
5163 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
5165 // Check if the scalar load can be widened into a vector load. And if
5166 // the address is "base + cst" see if the cst can be "absorbed" into
5167 // the shuffle mask.
5168 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
5169 SDValue Ptr = LD->getBasePtr();
5170 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5172 EVT PVT = LD->getValueType(0);
5173 if (PVT != MVT::i32 && PVT != MVT::f32)
5178 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5179 FI = FINode->getIndex();
5181 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5182 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5183 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5184 Offset = Ptr.getConstantOperandVal(1);
5185 Ptr = Ptr.getOperand(0);
5190 // FIXME: 256-bit vector instructions don't require a strict alignment,
5191 // improve this code to support it better.
5192 unsigned RequiredAlign = VT.getSizeInBits()/8;
5193 SDValue Chain = LD->getChain();
5194 // Make sure the stack object alignment is at least 16 or 32.
5195 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5196 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5197 if (MFI->isFixedObjectIndex(FI)) {
5198 // Can't change the alignment. FIXME: It's possible to compute
5199 // the exact stack offset and reference FI + adjust offset instead.
5200 // If someone *really* cares about this. That's the way to implement it.
5203 MFI->setObjectAlignment(FI, RequiredAlign);
5207 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5208 // Ptr + (Offset & ~15).
5211 if ((Offset % RequiredAlign) & 3)
5213 int64_t StartOffset = Offset & ~int64_t(RequiredAlign - 1);
5216 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5217 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
5220 int EltNo = (Offset - StartOffset) >> 2;
5221 unsigned NumElems = VT.getVectorNumElements();
5223 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5224 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5225 LD->getPointerInfo().getWithOffset(StartOffset),
5226 false, false, false, 0);
5228 SmallVector<int, 8> Mask(NumElems, EltNo);
5230 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5236 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
5237 /// elements can be replaced by a single large load which has the same value as
5238 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
5240 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5242 /// FIXME: we'd also like to handle the case where the last elements are zero
5243 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5244 /// There's even a handy isZeroNode for that purpose.
5245 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
5246 SDLoc &DL, SelectionDAG &DAG,
5247 bool isAfterLegalize) {
5248 unsigned NumElems = Elts.size();
5250 LoadSDNode *LDBase = nullptr;
5251 unsigned LastLoadedElt = -1U;
5253 // For each element in the initializer, see if we've found a load or an undef.
5254 // If we don't find an initial load element, or later load elements are
5255 // non-consecutive, bail out.
5256 for (unsigned i = 0; i < NumElems; ++i) {
5257 SDValue Elt = Elts[i];
5258 // Look through a bitcast.
5259 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
5260 Elt = Elt.getOperand(0);
5261 if (!Elt.getNode() ||
5262 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5265 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5267 LDBase = cast<LoadSDNode>(Elt.getNode());
5271 if (Elt.getOpcode() == ISD::UNDEF)
5274 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5275 EVT LdVT = Elt.getValueType();
5276 // Each loaded element must be the correct fractional portion of the
5277 // requested vector load.
5278 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
5280 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
5285 // If we have found an entire vector of loads and undefs, then return a large
5286 // load of the entire vector width starting at the base pointer. If we found
5287 // consecutive loads for the low half, generate a vzext_load node.
5288 if (LastLoadedElt == NumElems - 1) {
5289 assert(LDBase && "Did not find base load for merging consecutive loads");
5290 EVT EltVT = LDBase->getValueType(0);
5291 // Ensure that the input vector size for the merged loads matches the
5292 // cumulative size of the input elements.
5293 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
5296 if (isAfterLegalize &&
5297 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
5300 SDValue NewLd = SDValue();
5302 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5303 LDBase->getPointerInfo(), LDBase->isVolatile(),
5304 LDBase->isNonTemporal(), LDBase->isInvariant(),
5305 LDBase->getAlignment());
5307 if (LDBase->hasAnyUseOfValue(1)) {
5308 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5310 SDValue(NewLd.getNode(), 1));
5311 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5312 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5313 SDValue(NewLd.getNode(), 1));
5319 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5320 //of a v4i32 / v4f32. It's probably worth generalizing.
5321 EVT EltVT = VT.getVectorElementType();
5322 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5323 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5324 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5325 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5327 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5328 LDBase->getPointerInfo(),
5329 LDBase->getAlignment(),
5330 false/*isVolatile*/, true/*ReadMem*/,
5333 // Make sure the newly-created LOAD is in the same position as LDBase in
5334 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5335 // update uses of LDBase's output chain to use the TokenFactor.
5336 if (LDBase->hasAnyUseOfValue(1)) {
5337 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5338 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5339 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5340 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5341 SDValue(ResNode.getNode(), 1));
5344 return DAG.getBitcast(VT, ResNode);
5349 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5350 /// to generate a splat value for the following cases:
5351 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5352 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5353 /// a scalar load, or a constant.
5354 /// The VBROADCAST node is returned when a pattern is found,
5355 /// or SDValue() otherwise.
5356 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5357 SelectionDAG &DAG) {
5358 // VBROADCAST requires AVX.
5359 // TODO: Splats could be generated for non-AVX CPUs using SSE
5360 // instructions, but there's less potential gain for only 128-bit vectors.
5361 if (!Subtarget->hasAVX())
5364 MVT VT = Op.getSimpleValueType();
5367 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5368 "Unsupported vector type for broadcast.");
5373 switch (Op.getOpcode()) {
5375 // Unknown pattern found.
5378 case ISD::BUILD_VECTOR: {
5379 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5380 BitVector UndefElements;
5381 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5383 // We need a splat of a single value to use broadcast, and it doesn't
5384 // make any sense if the value is only in one element of the vector.
5385 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5389 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5390 Ld.getOpcode() == ISD::ConstantFP);
5392 // Make sure that all of the users of a non-constant load are from the
5393 // BUILD_VECTOR node.
5394 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5399 case ISD::VECTOR_SHUFFLE: {
5400 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5402 // Shuffles must have a splat mask where the first element is
5404 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5407 SDValue Sc = Op.getOperand(0);
5408 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5409 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5411 if (!Subtarget->hasInt256())
5414 // Use the register form of the broadcast instruction available on AVX2.
5415 if (VT.getSizeInBits() >= 256)
5416 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5417 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5420 Ld = Sc.getOperand(0);
5421 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5422 Ld.getOpcode() == ISD::ConstantFP);
5424 // The scalar_to_vector node and the suspected
5425 // load node must have exactly one user.
5426 // Constants may have multiple users.
5428 // AVX-512 has register version of the broadcast
5429 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5430 Ld.getValueType().getSizeInBits() >= 32;
5431 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5438 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5439 bool IsGE256 = (VT.getSizeInBits() >= 256);
5441 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5442 // instruction to save 8 or more bytes of constant pool data.
5443 // TODO: If multiple splats are generated to load the same constant,
5444 // it may be detrimental to overall size. There needs to be a way to detect
5445 // that condition to know if this is truly a size win.
5446 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
5448 // Handle broadcasting a single constant scalar from the constant pool
5450 // On Sandybridge (no AVX2), it is still better to load a constant vector
5451 // from the constant pool and not to broadcast it from a scalar.
5452 // But override that restriction when optimizing for size.
5453 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5454 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5455 EVT CVT = Ld.getValueType();
5456 assert(!CVT.isVector() && "Must not broadcast a vector type");
5458 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5459 // For size optimization, also splat v2f64 and v2i64, and for size opt
5460 // with AVX2, also splat i8 and i16.
5461 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5462 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5463 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5464 const Constant *C = nullptr;
5465 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5466 C = CI->getConstantIntValue();
5467 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5468 C = CF->getConstantFPValue();
5470 assert(C && "Invalid constant type");
5472 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5474 DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
5475 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5477 CVT, dl, DAG.getEntryNode(), CP,
5478 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
5479 false, false, Alignment);
5481 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5485 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5487 // Handle AVX2 in-register broadcasts.
5488 if (!IsLoad && Subtarget->hasInt256() &&
5489 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5490 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5492 // The scalar source must be a normal load.
5496 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5497 (Subtarget->hasVLX() && ScalarSize == 64))
5498 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5500 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5501 // double since there is no vbroadcastsd xmm
5502 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5503 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5504 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5507 // Unsupported broadcast.
5511 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5512 /// underlying vector and index.
5514 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5516 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5518 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5519 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5522 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5524 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5526 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5527 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5530 // In this case the vector is the extract_subvector expression and the index
5531 // is 2, as specified by the shuffle.
5532 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5533 SDValue ShuffleVec = SVOp->getOperand(0);
5534 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5535 assert(ShuffleVecVT.getVectorElementType() ==
5536 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5538 int ShuffleIdx = SVOp->getMaskElt(Idx);
5539 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5540 ExtractedFromVec = ShuffleVec;
5546 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5547 MVT VT = Op.getSimpleValueType();
5549 // Skip if insert_vec_elt is not supported.
5550 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5551 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5555 unsigned NumElems = Op.getNumOperands();
5559 SmallVector<unsigned, 4> InsertIndices;
5560 SmallVector<int, 8> Mask(NumElems, -1);
5562 for (unsigned i = 0; i != NumElems; ++i) {
5563 unsigned Opc = Op.getOperand(i).getOpcode();
5565 if (Opc == ISD::UNDEF)
5568 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5569 // Quit if more than 1 elements need inserting.
5570 if (InsertIndices.size() > 1)
5573 InsertIndices.push_back(i);
5577 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5578 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5579 // Quit if non-constant index.
5580 if (!isa<ConstantSDNode>(ExtIdx))
5582 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5584 // Quit if extracted from vector of different type.
5585 if (ExtractedFromVec.getValueType() != VT)
5588 if (!VecIn1.getNode())
5589 VecIn1 = ExtractedFromVec;
5590 else if (VecIn1 != ExtractedFromVec) {
5591 if (!VecIn2.getNode())
5592 VecIn2 = ExtractedFromVec;
5593 else if (VecIn2 != ExtractedFromVec)
5594 // Quit if more than 2 vectors to shuffle
5598 if (ExtractedFromVec == VecIn1)
5600 else if (ExtractedFromVec == VecIn2)
5601 Mask[i] = Idx + NumElems;
5604 if (!VecIn1.getNode())
5607 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5608 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5609 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5610 unsigned Idx = InsertIndices[i];
5611 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5612 DAG.getIntPtrConstant(Idx, DL));
5618 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
5619 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5620 Op.getScalarValueSizeInBits() == 1 &&
5621 "Can not convert non-constant vector");
5622 uint64_t Immediate = 0;
5623 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5624 SDValue In = Op.getOperand(idx);
5625 if (In.getOpcode() != ISD::UNDEF)
5626 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5630 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5631 return DAG.getConstant(Immediate, dl, VT);
5633 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5635 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5637 MVT VT = Op.getSimpleValueType();
5638 assert((VT.getVectorElementType() == MVT::i1) &&
5639 "Unexpected type in LowerBUILD_VECTORvXi1!");
5642 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5643 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5644 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5645 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5648 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5649 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5650 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5651 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5654 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5655 SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
5656 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5657 return DAG.getBitcast(VT, Imm);
5658 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5659 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5660 DAG.getIntPtrConstant(0, dl));
5663 // Vector has one or more non-const elements
5664 uint64_t Immediate = 0;
5665 SmallVector<unsigned, 16> NonConstIdx;
5666 bool IsSplat = true;
5667 bool HasConstElts = false;
5669 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5670 SDValue In = Op.getOperand(idx);
5671 if (In.getOpcode() == ISD::UNDEF)
5673 if (!isa<ConstantSDNode>(In))
5674 NonConstIdx.push_back(idx);
5676 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5677 HasConstElts = true;
5681 else if (In != Op.getOperand(SplatIdx))
5685 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5687 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5688 DAG.getConstant(1, dl, VT),
5689 DAG.getConstant(0, dl, VT));
5691 // insert elements one by one
5695 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5696 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5698 else if (HasConstElts)
5699 Imm = DAG.getConstant(0, dl, VT);
5701 Imm = DAG.getUNDEF(VT);
5702 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5703 DstVec = DAG.getBitcast(VT, Imm);
5705 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5706 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5707 DAG.getIntPtrConstant(0, dl));
5710 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5711 unsigned InsertIdx = NonConstIdx[i];
5712 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5713 Op.getOperand(InsertIdx),
5714 DAG.getIntPtrConstant(InsertIdx, dl));
5719 /// \brief Return true if \p N implements a horizontal binop and return the
5720 /// operands for the horizontal binop into V0 and V1.
5722 /// This is a helper function of LowerToHorizontalOp().
5723 /// This function checks that the build_vector \p N in input implements a
5724 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5725 /// operation to match.
5726 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5727 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5728 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5731 /// This function only analyzes elements of \p N whose indices are
5732 /// in range [BaseIdx, LastIdx).
5733 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5735 unsigned BaseIdx, unsigned LastIdx,
5736 SDValue &V0, SDValue &V1) {
5737 EVT VT = N->getValueType(0);
5739 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5740 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5741 "Invalid Vector in input!");
5743 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5744 bool CanFold = true;
5745 unsigned ExpectedVExtractIdx = BaseIdx;
5746 unsigned NumElts = LastIdx - BaseIdx;
5747 V0 = DAG.getUNDEF(VT);
5748 V1 = DAG.getUNDEF(VT);
5750 // Check if N implements a horizontal binop.
5751 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5752 SDValue Op = N->getOperand(i + BaseIdx);
5755 if (Op->getOpcode() == ISD::UNDEF) {
5756 // Update the expected vector extract index.
5757 if (i * 2 == NumElts)
5758 ExpectedVExtractIdx = BaseIdx;
5759 ExpectedVExtractIdx += 2;
5763 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5768 SDValue Op0 = Op.getOperand(0);
5769 SDValue Op1 = Op.getOperand(1);
5771 // Try to match the following pattern:
5772 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5773 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5774 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5775 Op0.getOperand(0) == Op1.getOperand(0) &&
5776 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5777 isa<ConstantSDNode>(Op1.getOperand(1)));
5781 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5782 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5784 if (i * 2 < NumElts) {
5785 if (V0.getOpcode() == ISD::UNDEF) {
5786 V0 = Op0.getOperand(0);
5787 if (V0.getValueType() != VT)
5791 if (V1.getOpcode() == ISD::UNDEF) {
5792 V1 = Op0.getOperand(0);
5793 if (V1.getValueType() != VT)
5796 if (i * 2 == NumElts)
5797 ExpectedVExtractIdx = BaseIdx;
5800 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5801 if (I0 == ExpectedVExtractIdx)
5802 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5803 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5804 // Try to match the following dag sequence:
5805 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5806 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5810 ExpectedVExtractIdx += 2;
5816 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5817 /// a concat_vector.
5819 /// This is a helper function of LowerToHorizontalOp().
5820 /// This function expects two 256-bit vectors called V0 and V1.
5821 /// At first, each vector is split into two separate 128-bit vectors.
5822 /// Then, the resulting 128-bit vectors are used to implement two
5823 /// horizontal binary operations.
5825 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5827 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5828 /// the two new horizontal binop.
5829 /// When Mode is set, the first horizontal binop dag node would take as input
5830 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5831 /// horizontal binop dag node would take as input the lower 128-bit of V1
5832 /// and the upper 128-bit of V1.
5834 /// HADD V0_LO, V0_HI
5835 /// HADD V1_LO, V1_HI
5837 /// Otherwise, the first horizontal binop dag node takes as input the lower
5838 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5839 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5841 /// HADD V0_LO, V1_LO
5842 /// HADD V0_HI, V1_HI
5844 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5845 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5846 /// the upper 128-bits of the result.
5847 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5848 SDLoc DL, SelectionDAG &DAG,
5849 unsigned X86Opcode, bool Mode,
5850 bool isUndefLO, bool isUndefHI) {
5851 EVT VT = V0.getValueType();
5852 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5853 "Invalid nodes in input!");
5855 unsigned NumElts = VT.getVectorNumElements();
5856 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5857 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5858 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5859 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5860 EVT NewVT = V0_LO.getValueType();
5862 SDValue LO = DAG.getUNDEF(NewVT);
5863 SDValue HI = DAG.getUNDEF(NewVT);
5866 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5867 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5868 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5869 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5870 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5872 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5873 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5874 V1_LO->getOpcode() != ISD::UNDEF))
5875 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5877 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5878 V1_HI->getOpcode() != ISD::UNDEF))
5879 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5882 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5885 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5887 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5888 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5889 EVT VT = BV->getValueType(0);
5890 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5891 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5895 unsigned NumElts = VT.getVectorNumElements();
5896 SDValue InVec0 = DAG.getUNDEF(VT);
5897 SDValue InVec1 = DAG.getUNDEF(VT);
5899 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5900 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5902 // Odd-numbered elements in the input build vector are obtained from
5903 // adding two integer/float elements.
5904 // Even-numbered elements in the input build vector are obtained from
5905 // subtracting two integer/float elements.
5906 unsigned ExpectedOpcode = ISD::FSUB;
5907 unsigned NextExpectedOpcode = ISD::FADD;
5908 bool AddFound = false;
5909 bool SubFound = false;
5911 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5912 SDValue Op = BV->getOperand(i);
5914 // Skip 'undef' values.
5915 unsigned Opcode = Op.getOpcode();
5916 if (Opcode == ISD::UNDEF) {
5917 std::swap(ExpectedOpcode, NextExpectedOpcode);
5921 // Early exit if we found an unexpected opcode.
5922 if (Opcode != ExpectedOpcode)
5925 SDValue Op0 = Op.getOperand(0);
5926 SDValue Op1 = Op.getOperand(1);
5928 // Try to match the following pattern:
5929 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5930 // Early exit if we cannot match that sequence.
5931 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5932 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5933 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5934 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5935 Op0.getOperand(1) != Op1.getOperand(1))
5938 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5942 // We found a valid add/sub node. Update the information accordingly.
5948 // Update InVec0 and InVec1.
5949 if (InVec0.getOpcode() == ISD::UNDEF) {
5950 InVec0 = Op0.getOperand(0);
5951 if (InVec0.getValueType() != VT)
5954 if (InVec1.getOpcode() == ISD::UNDEF) {
5955 InVec1 = Op1.getOperand(0);
5956 if (InVec1.getValueType() != VT)
5960 // Make sure that operands in input to each add/sub node always
5961 // come from a same pair of vectors.
5962 if (InVec0 != Op0.getOperand(0)) {
5963 if (ExpectedOpcode == ISD::FSUB)
5966 // FADD is commutable. Try to commute the operands
5967 // and then test again.
5968 std::swap(Op0, Op1);
5969 if (InVec0 != Op0.getOperand(0))
5973 if (InVec1 != Op1.getOperand(0))
5976 // Update the pair of expected opcodes.
5977 std::swap(ExpectedOpcode, NextExpectedOpcode);
5980 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5981 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5982 InVec1.getOpcode() != ISD::UNDEF)
5983 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5988 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5989 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5990 const X86Subtarget *Subtarget,
5991 SelectionDAG &DAG) {
5992 EVT VT = BV->getValueType(0);
5993 unsigned NumElts = VT.getVectorNumElements();
5994 unsigned NumUndefsLO = 0;
5995 unsigned NumUndefsHI = 0;
5996 unsigned Half = NumElts/2;
5998 // Count the number of UNDEF operands in the build_vector in input.
5999 for (unsigned i = 0, e = Half; i != e; ++i)
6000 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6003 for (unsigned i = Half, e = NumElts; i != e; ++i)
6004 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
6007 // Early exit if this is either a build_vector of all UNDEFs or all the
6008 // operands but one are UNDEF.
6009 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
6013 SDValue InVec0, InVec1;
6014 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
6015 // Try to match an SSE3 float HADD/HSUB.
6016 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6017 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6019 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6020 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6021 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
6022 // Try to match an SSSE3 integer HADD/HSUB.
6023 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6024 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
6026 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6027 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
6030 if (!Subtarget->hasAVX())
6033 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
6034 // Try to match an AVX horizontal add/sub of packed single/double
6035 // precision floating point values from 256-bit vectors.
6036 SDValue InVec2, InVec3;
6037 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
6038 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
6039 ((InVec0.getOpcode() == ISD::UNDEF ||
6040 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6041 ((InVec1.getOpcode() == ISD::UNDEF ||
6042 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6043 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
6045 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
6046 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
6047 ((InVec0.getOpcode() == ISD::UNDEF ||
6048 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6049 ((InVec1.getOpcode() == ISD::UNDEF ||
6050 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6051 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
6052 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
6053 // Try to match an AVX2 horizontal add/sub of signed integers.
6054 SDValue InVec2, InVec3;
6056 bool CanFold = true;
6058 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
6059 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
6060 ((InVec0.getOpcode() == ISD::UNDEF ||
6061 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6062 ((InVec1.getOpcode() == ISD::UNDEF ||
6063 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6064 X86Opcode = X86ISD::HADD;
6065 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
6066 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
6067 ((InVec0.getOpcode() == ISD::UNDEF ||
6068 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
6069 ((InVec1.getOpcode() == ISD::UNDEF ||
6070 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
6071 X86Opcode = X86ISD::HSUB;
6076 // Fold this build_vector into a single horizontal add/sub.
6077 // Do this only if the target has AVX2.
6078 if (Subtarget->hasAVX2())
6079 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
6081 // Do not try to expand this build_vector into a pair of horizontal
6082 // add/sub if we can emit a pair of scalar add/sub.
6083 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6086 // Convert this build_vector into a pair of horizontal binop followed by
6088 bool isUndefLO = NumUndefsLO == Half;
6089 bool isUndefHI = NumUndefsHI == Half;
6090 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
6091 isUndefLO, isUndefHI);
6095 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
6096 VT == MVT::v16i16) && Subtarget->hasAVX()) {
6098 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
6099 X86Opcode = X86ISD::HADD;
6100 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
6101 X86Opcode = X86ISD::HSUB;
6102 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
6103 X86Opcode = X86ISD::FHADD;
6104 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
6105 X86Opcode = X86ISD::FHSUB;
6109 // Don't try to expand this build_vector into a pair of horizontal add/sub
6110 // if we can simply emit a pair of scalar add/sub.
6111 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
6114 // Convert this build_vector into two horizontal add/sub followed by
6116 bool isUndefLO = NumUndefsLO == Half;
6117 bool isUndefHI = NumUndefsHI == Half;
6118 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
6119 isUndefLO, isUndefHI);
6126 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
6129 MVT VT = Op.getSimpleValueType();
6130 MVT ExtVT = VT.getVectorElementType();
6131 unsigned NumElems = Op.getNumOperands();
6133 // Generate vectors for predicate vectors.
6134 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
6135 return LowerBUILD_VECTORvXi1(Op, DAG);
6137 // Vectors containing all zeros can be matched by pxor and xorps later
6138 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
6139 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
6140 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
6141 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
6144 return getZeroVector(VT, Subtarget, DAG, dl);
6147 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
6148 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
6149 // vpcmpeqd on 256-bit vectors.
6150 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
6151 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
6154 if (!VT.is512BitVector())
6155 return getOnesVector(VT, Subtarget, DAG, dl);
6158 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
6159 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
6161 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
6162 return HorizontalOp;
6163 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
6166 unsigned EVTBits = ExtVT.getSizeInBits();
6168 unsigned NumZero = 0;
6169 unsigned NumNonZero = 0;
6170 unsigned NonZeros = 0;
6171 bool IsAllConstants = true;
6172 SmallSet<SDValue, 8> Values;
6173 for (unsigned i = 0; i < NumElems; ++i) {
6174 SDValue Elt = Op.getOperand(i);
6175 if (Elt.getOpcode() == ISD::UNDEF)
6178 if (Elt.getOpcode() != ISD::Constant &&
6179 Elt.getOpcode() != ISD::ConstantFP)
6180 IsAllConstants = false;
6181 if (X86::isZeroNode(Elt))
6184 NonZeros |= (1 << i);
6189 // All undef vector. Return an UNDEF. All zero vectors were handled above.
6190 if (NumNonZero == 0)
6191 return DAG.getUNDEF(VT);
6193 // Special case for single non-zero, non-undef, element.
6194 if (NumNonZero == 1) {
6195 unsigned Idx = countTrailingZeros(NonZeros);
6196 SDValue Item = Op.getOperand(Idx);
6198 // If this is an insertion of an i64 value on x86-32, and if the top bits of
6199 // the value are obviously zero, truncate the value to i32 and do the
6200 // insertion that way. Only do this if the value is non-constant or if the
6201 // value is a constant being inserted into element 0. It is cheaper to do
6202 // a constant pool load than it is to do a movd + shuffle.
6203 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
6204 (!IsAllConstants || Idx == 0)) {
6205 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
6207 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
6208 EVT VecVT = MVT::v4i32;
6210 // Truncate the value (which may itself be a constant) to i32, and
6211 // convert it to a vector with movd (S2V+shuffle to zero extend).
6212 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
6213 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
6214 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
6215 Item, Idx * 2, true, Subtarget, DAG));
6219 // If we have a constant or non-constant insertion into the low element of
6220 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
6221 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6222 // depending on what the source datatype is.
6225 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6227 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
6228 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
6229 if (VT.is512BitVector()) {
6230 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
6231 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
6232 Item, DAG.getIntPtrConstant(0, dl));
6234 assert((VT.is128BitVector() || VT.is256BitVector()) &&
6235 "Expected an SSE value type!");
6236 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6237 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
6238 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6241 // We can't directly insert an i8 or i16 into a vector, so zero extend
6243 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
6244 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
6245 if (VT.is256BitVector()) {
6246 if (Subtarget->hasAVX()) {
6247 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
6248 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6250 // Without AVX, we need to extend to a 128-bit vector and then
6251 // insert into the 256-bit vector.
6252 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6253 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
6254 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
6257 assert(VT.is128BitVector() && "Expected an SSE value type!");
6258 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
6259 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
6261 return DAG.getBitcast(VT, Item);
6265 // Is it a vector logical left shift?
6266 if (NumElems == 2 && Idx == 1 &&
6267 X86::isZeroNode(Op.getOperand(0)) &&
6268 !X86::isZeroNode(Op.getOperand(1))) {
6269 unsigned NumBits = VT.getSizeInBits();
6270 return getVShift(true, VT,
6271 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6272 VT, Op.getOperand(1)),
6273 NumBits/2, DAG, *this, dl);
6276 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
6279 // Otherwise, if this is a vector with i32 or f32 elements, and the element
6280 // is a non-constant being inserted into an element other than the low one,
6281 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
6282 // movd/movss) to move this into the low element, then shuffle it into
6284 if (EVTBits == 32) {
6285 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
6286 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
6290 // Splat is obviously ok. Let legalizer expand it to a shuffle.
6291 if (Values.size() == 1) {
6292 if (EVTBits == 32) {
6293 // Instead of a shuffle like this:
6294 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
6295 // Check if it's possible to issue this instead.
6296 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
6297 unsigned Idx = countTrailingZeros(NonZeros);
6298 SDValue Item = Op.getOperand(Idx);
6299 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
6300 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
6305 // A vector full of immediates; various special cases are already
6306 // handled, so this is best done with a single constant-pool load.
6310 // For AVX-length vectors, see if we can use a vector load to get all of the
6311 // elements, otherwise build the individual 128-bit pieces and use
6312 // shuffles to put them in place.
6313 if (VT.is256BitVector() || VT.is512BitVector()) {
6314 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
6316 // Check for a build vector of consecutive loads.
6317 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6320 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6322 // Build both the lower and upper subvector.
6323 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6324 makeArrayRef(&V[0], NumElems/2));
6325 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6326 makeArrayRef(&V[NumElems / 2], NumElems/2));
6328 // Recreate the wider vector with the lower and upper part.
6329 if (VT.is256BitVector())
6330 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6331 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6334 // Let legalizer expand 2-wide build_vectors.
6335 if (EVTBits == 64) {
6336 if (NumNonZero == 1) {
6337 // One half is zero or undef.
6338 unsigned Idx = countTrailingZeros(NonZeros);
6339 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6340 Op.getOperand(Idx));
6341 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6346 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6347 if (EVTBits == 8 && NumElems == 16)
6348 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6352 if (EVTBits == 16 && NumElems == 8)
6353 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6357 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6358 if (EVTBits == 32 && NumElems == 4)
6359 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6362 // If element VT is == 32 bits, turn it into a number of shuffles.
6363 SmallVector<SDValue, 8> V(NumElems);
6364 if (NumElems == 4 && NumZero > 0) {
6365 for (unsigned i = 0; i < 4; ++i) {
6366 bool isZero = !(NonZeros & (1 << i));
6368 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6370 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6373 for (unsigned i = 0; i < 2; ++i) {
6374 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6377 V[i] = V[i*2]; // Must be a zero vector.
6380 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6383 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6386 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6391 bool Reverse1 = (NonZeros & 0x3) == 2;
6392 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6396 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6397 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6399 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6402 if (Values.size() > 1 && VT.is128BitVector()) {
6403 // Check for a build vector of consecutive loads.
6404 for (unsigned i = 0; i < NumElems; ++i)
6405 V[i] = Op.getOperand(i);
6407 // Check for elements which are consecutive loads.
6408 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6411 // Check for a build vector from mostly shuffle plus few inserting.
6412 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6415 // For SSE 4.1, use insertps to put the high elements into the low element.
6416 if (Subtarget->hasSSE41()) {
6418 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6419 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6421 Result = DAG.getUNDEF(VT);
6423 for (unsigned i = 1; i < NumElems; ++i) {
6424 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6425 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6426 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6431 // Otherwise, expand into a number of unpckl*, start by extending each of
6432 // our (non-undef) elements to the full vector width with the element in the
6433 // bottom slot of the vector (which generates no code for SSE).
6434 for (unsigned i = 0; i < NumElems; ++i) {
6435 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6436 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6438 V[i] = DAG.getUNDEF(VT);
6441 // Next, we iteratively mix elements, e.g. for v4f32:
6442 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6443 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6444 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6445 unsigned EltStride = NumElems >> 1;
6446 while (EltStride != 0) {
6447 for (unsigned i = 0; i < EltStride; ++i) {
6448 // If V[i+EltStride] is undef and this is the first round of mixing,
6449 // then it is safe to just drop this shuffle: V[i] is already in the
6450 // right place, the one element (since it's the first round) being
6451 // inserted as undef can be dropped. This isn't safe for successive
6452 // rounds because they will permute elements within both vectors.
6453 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6454 EltStride == NumElems/2)
6457 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6466 // 256-bit AVX can use the vinsertf128 instruction
6467 // to create 256-bit vectors from two other 128-bit ones.
6468 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6470 MVT ResVT = Op.getSimpleValueType();
6472 assert((ResVT.is256BitVector() ||
6473 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6475 SDValue V1 = Op.getOperand(0);
6476 SDValue V2 = Op.getOperand(1);
6477 unsigned NumElems = ResVT.getVectorNumElements();
6478 if (ResVT.is256BitVector())
6479 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6481 if (Op.getNumOperands() == 4) {
6482 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6483 ResVT.getVectorNumElements()/2);
6484 SDValue V3 = Op.getOperand(2);
6485 SDValue V4 = Op.getOperand(3);
6486 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6487 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6489 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6492 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6493 const X86Subtarget *Subtarget,
6494 SelectionDAG & DAG) {
6496 MVT ResVT = Op.getSimpleValueType();
6497 unsigned NumOfOperands = Op.getNumOperands();
6499 assert(isPowerOf2_32(NumOfOperands) &&
6500 "Unexpected number of operands in CONCAT_VECTORS");
6502 if (NumOfOperands > 2) {
6503 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6504 ResVT.getVectorNumElements()/2);
6505 SmallVector<SDValue, 2> Ops;
6506 for (unsigned i = 0; i < NumOfOperands/2; i++)
6507 Ops.push_back(Op.getOperand(i));
6508 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6510 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6511 Ops.push_back(Op.getOperand(i));
6512 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6513 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6516 SDValue V1 = Op.getOperand(0);
6517 SDValue V2 = Op.getOperand(1);
6518 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6519 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6521 if (IsZeroV1 && IsZeroV2)
6522 return getZeroVector(ResVT, Subtarget, DAG, dl);
6524 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6525 SDValue Undef = DAG.getUNDEF(ResVT);
6526 unsigned NumElems = ResVT.getVectorNumElements();
6527 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6529 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6530 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6534 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6535 // Zero the upper bits of V1
6536 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6537 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6540 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6543 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6544 const X86Subtarget *Subtarget,
6545 SelectionDAG &DAG) {
6546 MVT VT = Op.getSimpleValueType();
6547 if (VT.getVectorElementType() == MVT::i1)
6548 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6550 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6551 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6552 Op.getNumOperands() == 4)));
6554 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6555 // from two other 128-bit ones.
6557 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6558 return LowerAVXCONCAT_VECTORS(Op, DAG);
6561 //===----------------------------------------------------------------------===//
6562 // Vector shuffle lowering
6564 // This is an experimental code path for lowering vector shuffles on x86. It is
6565 // designed to handle arbitrary vector shuffles and blends, gracefully
6566 // degrading performance as necessary. It works hard to recognize idiomatic
6567 // shuffles and lower them to optimal instruction patterns without leaving
6568 // a framework that allows reasonably efficient handling of all vector shuffle
6570 //===----------------------------------------------------------------------===//
6572 /// \brief Tiny helper function to identify a no-op mask.
6574 /// This is a somewhat boring predicate function. It checks whether the mask
6575 /// array input, which is assumed to be a single-input shuffle mask of the kind
6576 /// used by the X86 shuffle instructions (not a fully general
6577 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6578 /// in-place shuffle are 'no-op's.
6579 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6580 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6581 if (Mask[i] != -1 && Mask[i] != i)
6586 /// \brief Helper function to classify a mask as a single-input mask.
6588 /// This isn't a generic single-input test because in the vector shuffle
6589 /// lowering we canonicalize single inputs to be the first input operand. This
6590 /// means we can more quickly test for a single input by only checking whether
6591 /// an input from the second operand exists. We also assume that the size of
6592 /// mask corresponds to the size of the input vectors which isn't true in the
6593 /// fully general case.
6594 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6596 if (M >= (int)Mask.size())
6601 /// \brief Test whether there are elements crossing 128-bit lanes in this
6604 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6605 /// and we routinely test for these.
6606 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6607 int LaneSize = 128 / VT.getScalarSizeInBits();
6608 int Size = Mask.size();
6609 for (int i = 0; i < Size; ++i)
6610 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6615 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6617 /// This checks a shuffle mask to see if it is performing the same
6618 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6619 /// that it is also not lane-crossing. It may however involve a blend from the
6620 /// same lane of a second vector.
6622 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6623 /// non-trivial to compute in the face of undef lanes. The representation is
6624 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6625 /// entries from both V1 and V2 inputs to the wider mask.
6627 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6628 SmallVectorImpl<int> &RepeatedMask) {
6629 int LaneSize = 128 / VT.getScalarSizeInBits();
6630 RepeatedMask.resize(LaneSize, -1);
6631 int Size = Mask.size();
6632 for (int i = 0; i < Size; ++i) {
6635 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6636 // This entry crosses lanes, so there is no way to model this shuffle.
6639 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6640 if (RepeatedMask[i % LaneSize] == -1)
6641 // This is the first non-undef entry in this slot of a 128-bit lane.
6642 RepeatedMask[i % LaneSize] =
6643 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6644 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6645 // Found a mismatch with the repeated mask.
6651 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6654 /// This is a fast way to test a shuffle mask against a fixed pattern:
6656 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6658 /// It returns true if the mask is exactly as wide as the argument list, and
6659 /// each element of the mask is either -1 (signifying undef) or the value given
6660 /// in the argument.
6661 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6662 ArrayRef<int> ExpectedMask) {
6663 if (Mask.size() != ExpectedMask.size())
6666 int Size = Mask.size();
6668 // If the values are build vectors, we can look through them to find
6669 // equivalent inputs that make the shuffles equivalent.
6670 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6671 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6673 for (int i = 0; i < Size; ++i)
6674 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6675 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6676 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6677 if (!MaskBV || !ExpectedBV ||
6678 MaskBV->getOperand(Mask[i] % Size) !=
6679 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6686 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6688 /// This helper function produces an 8-bit shuffle immediate corresponding to
6689 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6690 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6693 /// NB: We rely heavily on "undef" masks preserving the input lane.
6694 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6695 SelectionDAG &DAG) {
6696 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6697 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6698 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6699 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6700 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6703 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6704 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6705 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6706 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6707 return DAG.getConstant(Imm, DL, MVT::i8);
6710 /// \brief Compute whether each element of a shuffle is zeroable.
6712 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6713 /// Either it is an undef element in the shuffle mask, the element of the input
6714 /// referenced is undef, or the element of the input referenced is known to be
6715 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6716 /// as many lanes with this technique as possible to simplify the remaining
6718 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6719 SDValue V1, SDValue V2) {
6720 SmallBitVector Zeroable(Mask.size(), false);
6722 while (V1.getOpcode() == ISD::BITCAST)
6723 V1 = V1->getOperand(0);
6724 while (V2.getOpcode() == ISD::BITCAST)
6725 V2 = V2->getOperand(0);
6727 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6728 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6730 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6732 // Handle the easy cases.
6733 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6738 // If this is an index into a build_vector node (which has the same number
6739 // of elements), dig out the input value and use it.
6740 SDValue V = M < Size ? V1 : V2;
6741 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6744 SDValue Input = V.getOperand(M % Size);
6745 // The UNDEF opcode check really should be dead code here, but not quite
6746 // worth asserting on (it isn't invalid, just unexpected).
6747 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6754 // X86 has dedicated unpack instructions that can handle specific blend
6755 // operations: UNPCKH and UNPCKL.
6756 static SDValue lowerVectorShuffleWithUNPCK(SDLoc DL, MVT VT, ArrayRef<int> Mask,
6757 SDValue V1, SDValue V2,
6758 SelectionDAG &DAG) {
6759 int NumElts = VT.getVectorNumElements();
6762 bool UnpcklSwapped = true;
6763 bool UnpckhSwapped = true;
6764 int NumEltsInLane = 128 / VT.getScalarSizeInBits();
6766 for (int i = 0; i < NumElts; ++i) {
6767 unsigned LaneStart = (i / NumEltsInLane) * NumEltsInLane;
6769 int LoPos = (i % NumEltsInLane) / 2 + LaneStart + NumElts * (i % 2);
6770 int HiPos = LoPos + NumEltsInLane / 2;
6771 int LoPosSwapped = (LoPos + NumElts) % (NumElts * 2);
6772 int HiPosSwapped = (HiPos + NumElts) % (NumElts * 2);
6776 if (Mask[i] != LoPos)
6778 if (Mask[i] != HiPos)
6780 if (Mask[i] != LoPosSwapped)
6781 UnpcklSwapped = false;
6782 if (Mask[i] != HiPosSwapped)
6783 UnpckhSwapped = false;
6784 if (!Unpckl && !Unpckh && !UnpcklSwapped && !UnpckhSwapped)
6788 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V1, V2);
6790 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V1, V2);
6792 return DAG.getNode(X86ISD::UNPCKL, DL, VT, V2, V1);
6794 return DAG.getNode(X86ISD::UNPCKH, DL, VT, V2, V1);
6796 llvm_unreachable("Unexpected result of UNPCK mask analysis");
6800 /// \brief Try to emit a bitmask instruction for a shuffle.
6802 /// This handles cases where we can model a blend exactly as a bitmask due to
6803 /// one of the inputs being zeroable.
6804 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6805 SDValue V2, ArrayRef<int> Mask,
6806 SelectionDAG &DAG) {
6807 MVT EltVT = VT.getScalarType();
6808 int NumEltBits = EltVT.getSizeInBits();
6809 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6810 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6811 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6813 if (EltVT.isFloatingPoint()) {
6814 Zero = DAG.getBitcast(EltVT, Zero);
6815 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6817 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6818 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6820 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6823 if (Mask[i] % Size != i)
6824 return SDValue(); // Not a blend.
6826 V = Mask[i] < Size ? V1 : V2;
6827 else if (V != (Mask[i] < Size ? V1 : V2))
6828 return SDValue(); // Can only let one input through the mask.
6830 VMaskOps[i] = AllOnes;
6833 return SDValue(); // No non-zeroable elements!
6835 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6836 V = DAG.getNode(VT.isFloatingPoint()
6837 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6842 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6844 /// This is used as a fallback approach when first class blend instructions are
6845 /// unavailable. Currently it is only suitable for integer vectors, but could
6846 /// be generalized for floating point vectors if desirable.
6847 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6848 SDValue V2, ArrayRef<int> Mask,
6849 SelectionDAG &DAG) {
6850 assert(VT.isInteger() && "Only supports integer vector types!");
6851 MVT EltVT = VT.getScalarType();
6852 int NumEltBits = EltVT.getSizeInBits();
6853 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6854 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6856 SmallVector<SDValue, 16> MaskOps;
6857 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6858 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6859 return SDValue(); // Shuffled input!
6860 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6863 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6864 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6865 // We have to cast V2 around.
6866 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6867 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6868 DAG.getBitcast(MaskVT, V1Mask),
6869 DAG.getBitcast(MaskVT, V2)));
6870 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6873 /// \brief Try to emit a blend instruction for a shuffle.
6875 /// This doesn't do any checks for the availability of instructions for blending
6876 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6877 /// be matched in the backend with the type given. What it does check for is
6878 /// that the shuffle mask is in fact a blend.
6879 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6880 SDValue V2, ArrayRef<int> Mask,
6881 const X86Subtarget *Subtarget,
6882 SelectionDAG &DAG) {
6883 unsigned BlendMask = 0;
6884 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6885 if (Mask[i] >= Size) {
6886 if (Mask[i] != i + Size)
6887 return SDValue(); // Shuffled V2 input!
6888 BlendMask |= 1u << i;
6891 if (Mask[i] >= 0 && Mask[i] != i)
6892 return SDValue(); // Shuffled V1 input!
6894 switch (VT.SimpleTy) {
6899 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6900 DAG.getConstant(BlendMask, DL, MVT::i8));
6904 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6908 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6909 // that instruction.
6910 if (Subtarget->hasAVX2()) {
6911 // Scale the blend by the number of 32-bit dwords per element.
6912 int Scale = VT.getScalarSizeInBits() / 32;
6914 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6915 if (Mask[i] >= Size)
6916 for (int j = 0; j < Scale; ++j)
6917 BlendMask |= 1u << (i * Scale + j);
6919 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6920 V1 = DAG.getBitcast(BlendVT, V1);
6921 V2 = DAG.getBitcast(BlendVT, V2);
6922 return DAG.getBitcast(
6923 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6924 DAG.getConstant(BlendMask, DL, MVT::i8)));
6928 // For integer shuffles we need to expand the mask and cast the inputs to
6929 // v8i16s prior to blending.
6930 int Scale = 8 / VT.getVectorNumElements();
6932 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6933 if (Mask[i] >= Size)
6934 for (int j = 0; j < Scale; ++j)
6935 BlendMask |= 1u << (i * Scale + j);
6937 V1 = DAG.getBitcast(MVT::v8i16, V1);
6938 V2 = DAG.getBitcast(MVT::v8i16, V2);
6939 return DAG.getBitcast(VT,
6940 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6941 DAG.getConstant(BlendMask, DL, MVT::i8)));
6945 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6946 SmallVector<int, 8> RepeatedMask;
6947 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6948 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6949 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6951 for (int i = 0; i < 8; ++i)
6952 if (RepeatedMask[i] >= 16)
6953 BlendMask |= 1u << i;
6954 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6955 DAG.getConstant(BlendMask, DL, MVT::i8));
6961 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6962 "256-bit byte-blends require AVX2 support!");
6964 // Attempt to lower to a bitmask if we can. VPAND is faster than VPBLENDVB.
6965 if (SDValue Masked = lowerVectorShuffleAsBitMask(DL, VT, V1, V2, Mask, DAG))
6968 // Scale the blend by the number of bytes per element.
6969 int Scale = VT.getScalarSizeInBits() / 8;
6971 // This form of blend is always done on bytes. Compute the byte vector
6973 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6975 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6976 // mix of LLVM's code generator and the x86 backend. We tell the code
6977 // generator that boolean values in the elements of an x86 vector register
6978 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6979 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6980 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6981 // of the element (the remaining are ignored) and 0 in that high bit would
6982 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6983 // the LLVM model for boolean values in vector elements gets the relevant
6984 // bit set, it is set backwards and over constrained relative to x86's
6986 SmallVector<SDValue, 32> VSELECTMask;
6987 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6988 for (int j = 0; j < Scale; ++j)
6989 VSELECTMask.push_back(
6990 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6991 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6994 V1 = DAG.getBitcast(BlendVT, V1);
6995 V2 = DAG.getBitcast(BlendVT, V2);
6996 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6997 DAG.getNode(ISD::BUILD_VECTOR, DL,
6998 BlendVT, VSELECTMask),
7003 llvm_unreachable("Not a supported integer vector type!");
7007 /// \brief Try to lower as a blend of elements from two inputs followed by
7008 /// a single-input permutation.
7010 /// This matches the pattern where we can blend elements from two inputs and
7011 /// then reduce the shuffle to a single-input permutation.
7012 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
7015 SelectionDAG &DAG) {
7016 // We build up the blend mask while checking whether a blend is a viable way
7017 // to reduce the shuffle.
7018 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7019 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
7021 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
7025 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
7027 if (BlendMask[Mask[i] % Size] == -1)
7028 BlendMask[Mask[i] % Size] = Mask[i];
7029 else if (BlendMask[Mask[i] % Size] != Mask[i])
7030 return SDValue(); // Can't blend in the needed input!
7032 PermuteMask[i] = Mask[i] % Size;
7035 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7036 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
7039 /// \brief Generic routine to decompose a shuffle and blend into indepndent
7040 /// blends and permutes.
7042 /// This matches the extremely common pattern for handling combined
7043 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
7044 /// operations. It will try to pick the best arrangement of shuffles and
7046 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
7050 SelectionDAG &DAG) {
7051 // Shuffle the input elements into the desired positions in V1 and V2 and
7052 // blend them together.
7053 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7054 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7055 SmallVector<int, 32> BlendMask(Mask.size(), -1);
7056 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7057 if (Mask[i] >= 0 && Mask[i] < Size) {
7058 V1Mask[i] = Mask[i];
7060 } else if (Mask[i] >= Size) {
7061 V2Mask[i] = Mask[i] - Size;
7062 BlendMask[i] = i + Size;
7065 // Try to lower with the simpler initial blend strategy unless one of the
7066 // input shuffles would be a no-op. We prefer to shuffle inputs as the
7067 // shuffle may be able to fold with a load or other benefit. However, when
7068 // we'll have to do 2x as many shuffles in order to achieve this, blending
7069 // first is a better strategy.
7070 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
7071 if (SDValue BlendPerm =
7072 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
7075 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7076 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7077 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
7080 /// \brief Try to lower a vector shuffle as a byte rotation.
7082 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
7083 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
7084 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
7085 /// try to generically lower a vector shuffle through such an pattern. It
7086 /// does not check for the profitability of lowering either as PALIGNR or
7087 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
7088 /// This matches shuffle vectors that look like:
7090 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
7092 /// Essentially it concatenates V1 and V2, shifts right by some number of
7093 /// elements, and takes the low elements as the result. Note that while this is
7094 /// specified as a *right shift* because x86 is little-endian, it is a *left
7095 /// rotate* of the vector lanes.
7096 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
7099 const X86Subtarget *Subtarget,
7100 SelectionDAG &DAG) {
7101 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
7103 int NumElts = Mask.size();
7104 int NumLanes = VT.getSizeInBits() / 128;
7105 int NumLaneElts = NumElts / NumLanes;
7107 // We need to detect various ways of spelling a rotation:
7108 // [11, 12, 13, 14, 15, 0, 1, 2]
7109 // [-1, 12, 13, 14, -1, -1, 1, -1]
7110 // [-1, -1, -1, -1, -1, -1, 1, 2]
7111 // [ 3, 4, 5, 6, 7, 8, 9, 10]
7112 // [-1, 4, 5, 6, -1, -1, 9, -1]
7113 // [-1, 4, 5, 6, -1, -1, -1, -1]
7116 for (int l = 0; l < NumElts; l += NumLaneElts) {
7117 for (int i = 0; i < NumLaneElts; ++i) {
7118 if (Mask[l + i] == -1)
7120 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
7122 // Get the mod-Size index and lane correct it.
7123 int LaneIdx = (Mask[l + i] % NumElts) - l;
7124 // Make sure it was in this lane.
7125 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
7128 // Determine where a rotated vector would have started.
7129 int StartIdx = i - LaneIdx;
7131 // The identity rotation isn't interesting, stop.
7134 // If we found the tail of a vector the rotation must be the missing
7135 // front. If we found the head of a vector, it must be how much of the
7137 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
7140 Rotation = CandidateRotation;
7141 else if (Rotation != CandidateRotation)
7142 // The rotations don't match, so we can't match this mask.
7145 // Compute which value this mask is pointing at.
7146 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
7148 // Compute which of the two target values this index should be assigned
7149 // to. This reflects whether the high elements are remaining or the low
7150 // elements are remaining.
7151 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
7153 // Either set up this value if we've not encountered it before, or check
7154 // that it remains consistent.
7157 else if (TargetV != MaskV)
7158 // This may be a rotation, but it pulls from the inputs in some
7159 // unsupported interleaving.
7164 // Check that we successfully analyzed the mask, and normalize the results.
7165 assert(Rotation != 0 && "Failed to locate a viable rotation!");
7166 assert((Lo || Hi) && "Failed to find a rotated input vector!");
7172 // The actual rotate instruction rotates bytes, so we need to scale the
7173 // rotation based on how many bytes are in the vector lane.
7174 int Scale = 16 / NumLaneElts;
7176 // SSSE3 targets can use the palignr instruction.
7177 if (Subtarget->hasSSSE3()) {
7178 // Cast the inputs to i8 vector of correct length to match PALIGNR.
7179 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
7180 Lo = DAG.getBitcast(AlignVT, Lo);
7181 Hi = DAG.getBitcast(AlignVT, Hi);
7183 return DAG.getBitcast(
7184 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Lo, Hi,
7185 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
7188 assert(VT.getSizeInBits() == 128 &&
7189 "Rotate-based lowering only supports 128-bit lowering!");
7190 assert(Mask.size() <= 16 &&
7191 "Can shuffle at most 16 bytes in a 128-bit vector!");
7193 // Default SSE2 implementation
7194 int LoByteShift = 16 - Rotation * Scale;
7195 int HiByteShift = Rotation * Scale;
7197 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
7198 Lo = DAG.getBitcast(MVT::v2i64, Lo);
7199 Hi = DAG.getBitcast(MVT::v2i64, Hi);
7201 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
7202 DAG.getConstant(LoByteShift, DL, MVT::i8));
7203 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
7204 DAG.getConstant(HiByteShift, DL, MVT::i8));
7205 return DAG.getBitcast(VT,
7206 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
7209 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
7211 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
7212 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
7213 /// matches elements from one of the input vectors shuffled to the left or
7214 /// right with zeroable elements 'shifted in'. It handles both the strictly
7215 /// bit-wise element shifts and the byte shift across an entire 128-bit double
7218 /// PSHL : (little-endian) left bit shift.
7219 /// [ zz, 0, zz, 2 ]
7220 /// [ -1, 4, zz, -1 ]
7221 /// PSRL : (little-endian) right bit shift.
7223 /// [ -1, -1, 7, zz]
7224 /// PSLLDQ : (little-endian) left byte shift
7225 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
7226 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
7227 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
7228 /// PSRLDQ : (little-endian) right byte shift
7229 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
7230 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
7231 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
7232 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
7233 SDValue V2, ArrayRef<int> Mask,
7234 SelectionDAG &DAG) {
7235 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7237 int Size = Mask.size();
7238 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7240 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
7241 for (int i = 0; i < Size; i += Scale)
7242 for (int j = 0; j < Shift; ++j)
7243 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
7249 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
7250 for (int i = 0; i != Size; i += Scale) {
7251 unsigned Pos = Left ? i + Shift : i;
7252 unsigned Low = Left ? i : i + Shift;
7253 unsigned Len = Scale - Shift;
7254 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
7255 Low + (V == V1 ? 0 : Size)))
7259 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
7260 bool ByteShift = ShiftEltBits > 64;
7261 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
7262 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
7263 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
7265 // Normalize the scale for byte shifts to still produce an i64 element
7267 Scale = ByteShift ? Scale / 2 : Scale;
7269 // We need to round trip through the appropriate type for the shift.
7270 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
7271 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
7272 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
7273 "Illegal integer vector type");
7274 V = DAG.getBitcast(ShiftVT, V);
7276 V = DAG.getNode(OpCode, DL, ShiftVT, V,
7277 DAG.getConstant(ShiftAmt, DL, MVT::i8));
7278 return DAG.getBitcast(VT, V);
7281 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
7282 // keep doubling the size of the integer elements up to that. We can
7283 // then shift the elements of the integer vector by whole multiples of
7284 // their width within the elements of the larger integer vector. Test each
7285 // multiple to see if we can find a match with the moved element indices
7286 // and that the shifted in elements are all zeroable.
7287 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
7288 for (int Shift = 1; Shift != Scale; ++Shift)
7289 for (bool Left : {true, false})
7290 if (CheckZeros(Shift, Scale, Left))
7291 for (SDValue V : {V1, V2})
7292 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
7299 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
7300 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
7301 SDValue V2, ArrayRef<int> Mask,
7302 SelectionDAG &DAG) {
7303 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7304 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
7306 int Size = Mask.size();
7307 int HalfSize = Size / 2;
7308 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
7310 // Upper half must be undefined.
7311 if (!isUndefInRange(Mask, HalfSize, HalfSize))
7314 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
7315 // Remainder of lower half result is zero and upper half is all undef.
7316 auto LowerAsEXTRQ = [&]() {
7317 // Determine the extraction length from the part of the
7318 // lower half that isn't zeroable.
7320 for (; Len >= 0; --Len)
7321 if (!Zeroable[Len - 1])
7323 assert(Len > 0 && "Zeroable shuffle mask");
7325 // Attempt to match first Len sequential elements from the lower half.
7328 for (int i = 0; i != Len; ++i) {
7332 SDValue &V = (M < Size ? V1 : V2);
7335 // All mask elements must be in the lower half.
7339 if (Idx < 0 || (Src == V && Idx == (M - i))) {
7350 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
7351 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7352 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7353 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
7354 DAG.getConstant(BitLen, DL, MVT::i8),
7355 DAG.getConstant(BitIdx, DL, MVT::i8));
7358 if (SDValue ExtrQ = LowerAsEXTRQ())
7361 // INSERTQ: Extract lowest Len elements from lower half of second source and
7362 // insert over first source, starting at Idx.
7363 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
7364 auto LowerAsInsertQ = [&]() {
7365 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7368 // Attempt to match first source from mask before insertion point.
7369 if (isUndefInRange(Mask, 0, Idx)) {
7371 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7373 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7379 // Extend the extraction length looking to match both the insertion of
7380 // the second source and the remaining elements of the first.
7381 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7386 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7388 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7394 // Match the remaining elements of the lower half.
7395 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7397 } else if ((!Base || (Base == V1)) &&
7398 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7400 } else if ((!Base || (Base == V2)) &&
7401 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7408 // We may not have a base (first source) - this can safely be undefined.
7410 Base = DAG.getUNDEF(VT);
7412 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7413 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7414 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7415 DAG.getConstant(BitLen, DL, MVT::i8),
7416 DAG.getConstant(BitIdx, DL, MVT::i8));
7423 if (SDValue InsertQ = LowerAsInsertQ())
7429 /// \brief Lower a vector shuffle as a zero or any extension.
7431 /// Given a specific number of elements, element bit width, and extension
7432 /// stride, produce either a zero or any extension based on the available
7433 /// features of the subtarget. The extended elements are consecutive and
7434 /// begin and can start from an offseted element index in the input; to
7435 /// avoid excess shuffling the offset must either being in the bottom lane
7436 /// or at the start of a higher lane. All extended elements must be from
7438 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7439 SDLoc DL, MVT VT, int Scale, int Offset, bool AnyExt, SDValue InputV,
7440 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7441 assert(Scale > 1 && "Need a scale to extend.");
7442 int EltBits = VT.getScalarSizeInBits();
7443 int NumElements = VT.getVectorNumElements();
7444 int NumEltsPerLane = 128 / EltBits;
7445 int OffsetLane = Offset / NumEltsPerLane;
7446 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7447 "Only 8, 16, and 32 bit elements can be extended.");
7448 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7449 assert(0 <= Offset && "Extension offset must be positive.");
7450 assert((Offset < NumEltsPerLane || Offset % NumEltsPerLane == 0) &&
7451 "Extension offset must be in the first lane or start an upper lane.");
7453 // Check that an index is in same lane as the base offset.
7454 auto SafeOffset = [&](int Idx) {
7455 return OffsetLane == (Idx / NumEltsPerLane);
7458 // Shift along an input so that the offset base moves to the first element.
7459 auto ShuffleOffset = [&](SDValue V) {
7463 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7464 for (int i = 0; i * Scale < NumElements; ++i) {
7465 int SrcIdx = i + Offset;
7466 ShMask[i] = SafeOffset(SrcIdx) ? SrcIdx : -1;
7468 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), ShMask);
7471 // Found a valid zext mask! Try various lowering strategies based on the
7472 // input type and available ISA extensions.
7473 if (Subtarget->hasSSE41()) {
7474 // Not worth offseting 128-bit vectors if scale == 2, a pattern using
7475 // PUNPCK will catch this in a later shuffle match.
7476 if (Offset && Scale == 2 && VT.getSizeInBits() == 128)
7478 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7479 NumElements / Scale);
7480 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, ShuffleOffset(InputV));
7481 return DAG.getBitcast(VT, InputV);
7484 assert(VT.getSizeInBits() == 128 && "Only 128-bit vectors can be extended.");
7486 // For any extends we can cheat for larger element sizes and use shuffle
7487 // instructions that can fold with a load and/or copy.
7488 if (AnyExt && EltBits == 32) {
7489 int PSHUFDMask[4] = {Offset, -1, SafeOffset(Offset + 1) ? Offset + 1 : -1,
7491 return DAG.getBitcast(
7492 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7493 DAG.getBitcast(MVT::v4i32, InputV),
7494 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7496 if (AnyExt && EltBits == 16 && Scale > 2) {
7497 int PSHUFDMask[4] = {Offset / 2, -1,
7498 SafeOffset(Offset + 1) ? (Offset + 1) / 2 : -1, -1};
7499 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7500 DAG.getBitcast(MVT::v4i32, InputV),
7501 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7502 int PSHUFWMask[4] = {1, -1, -1, -1};
7503 unsigned OddEvenOp = (Offset & 1 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW);
7504 return DAG.getBitcast(
7505 VT, DAG.getNode(OddEvenOp, DL, MVT::v8i16,
7506 DAG.getBitcast(MVT::v8i16, InputV),
7507 getV4X86ShuffleImm8ForMask(PSHUFWMask, DL, DAG)));
7510 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7512 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7513 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7514 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7516 int LoIdx = Offset * EltBits;
7517 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7518 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7519 DAG.getConstant(EltBits, DL, MVT::i8),
7520 DAG.getConstant(LoIdx, DL, MVT::i8)));
7522 if (isUndefInRange(Mask, NumElements / 2, NumElements / 2) ||
7523 !SafeOffset(Offset + 1))
7524 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7526 int HiIdx = (Offset + 1) * EltBits;
7527 SDValue Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7528 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7529 DAG.getConstant(EltBits, DL, MVT::i8),
7530 DAG.getConstant(HiIdx, DL, MVT::i8)));
7531 return DAG.getNode(ISD::BITCAST, DL, VT,
7532 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7535 // If this would require more than 2 unpack instructions to expand, use
7536 // pshufb when available. We can only use more than 2 unpack instructions
7537 // when zero extending i8 elements which also makes it easier to use pshufb.
7538 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7539 assert(NumElements == 16 && "Unexpected byte vector width!");
7540 SDValue PSHUFBMask[16];
7541 for (int i = 0; i < 16; ++i) {
7542 int Idx = Offset + (i / Scale);
7543 PSHUFBMask[i] = DAG.getConstant(
7544 (i % Scale == 0 && SafeOffset(Idx)) ? Idx : 0x80, DL, MVT::i8);
7546 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7547 return DAG.getBitcast(VT,
7548 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7549 DAG.getNode(ISD::BUILD_VECTOR, DL,
7550 MVT::v16i8, PSHUFBMask)));
7553 // If we are extending from an offset, ensure we start on a boundary that
7554 // we can unpack from.
7555 int AlignToUnpack = Offset % (NumElements / Scale);
7556 if (AlignToUnpack) {
7557 SmallVector<int, 8> ShMask((unsigned)NumElements, -1);
7558 for (int i = AlignToUnpack; i < NumElements; ++i)
7559 ShMask[i - AlignToUnpack] = i;
7560 InputV = DAG.getVectorShuffle(VT, DL, InputV, DAG.getUNDEF(VT), ShMask);
7561 Offset -= AlignToUnpack;
7564 // Otherwise emit a sequence of unpacks.
7566 unsigned UnpackLoHi = X86ISD::UNPCKL;
7567 if (Offset >= (NumElements / 2)) {
7568 UnpackLoHi = X86ISD::UNPCKH;
7569 Offset -= (NumElements / 2);
7572 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7573 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7574 : getZeroVector(InputVT, Subtarget, DAG, DL);
7575 InputV = DAG.getBitcast(InputVT, InputV);
7576 InputV = DAG.getNode(UnpackLoHi, DL, InputVT, InputV, Ext);
7580 } while (Scale > 1);
7581 return DAG.getBitcast(VT, InputV);
7584 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7586 /// This routine will try to do everything in its power to cleverly lower
7587 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7588 /// check for the profitability of this lowering, it tries to aggressively
7589 /// match this pattern. It will use all of the micro-architectural details it
7590 /// can to emit an efficient lowering. It handles both blends with all-zero
7591 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7592 /// masking out later).
7594 /// The reason we have dedicated lowering for zext-style shuffles is that they
7595 /// are both incredibly common and often quite performance sensitive.
7596 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7597 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7598 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7599 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7601 int Bits = VT.getSizeInBits();
7602 int NumLanes = Bits / 128;
7603 int NumElements = VT.getVectorNumElements();
7604 int NumEltsPerLane = NumElements / NumLanes;
7605 assert(VT.getScalarSizeInBits() <= 32 &&
7606 "Exceeds 32-bit integer zero extension limit");
7607 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7609 // Define a helper function to check a particular ext-scale and lower to it if
7611 auto Lower = [&](int Scale) -> SDValue {
7616 for (int i = 0; i < NumElements; ++i) {
7619 continue; // Valid anywhere but doesn't tell us anything.
7620 if (i % Scale != 0) {
7621 // Each of the extended elements need to be zeroable.
7625 // We no longer are in the anyext case.
7630 // Each of the base elements needs to be consecutive indices into the
7631 // same input vector.
7632 SDValue V = M < NumElements ? V1 : V2;
7633 M = M % NumElements;
7636 Offset = M - (i / Scale);
7637 } else if (InputV != V)
7638 return SDValue(); // Flip-flopping inputs.
7640 // Offset must start in the lowest 128-bit lane or at the start of an
7642 // FIXME: Is it ever worth allowing a negative base offset?
7643 if (!((0 <= Offset && Offset < NumEltsPerLane) ||
7644 (Offset % NumEltsPerLane) == 0))
7647 // If we are offsetting, all referenced entries must come from the same
7649 if (Offset && (Offset / NumEltsPerLane) != (M / NumEltsPerLane))
7652 if ((M % NumElements) != (Offset + (i / Scale)))
7653 return SDValue(); // Non-consecutive strided elements.
7657 // If we fail to find an input, we have a zero-shuffle which should always
7658 // have already been handled.
7659 // FIXME: Maybe handle this here in case during blending we end up with one?
7663 // If we are offsetting, don't extend if we only match a single input, we
7664 // can always do better by using a basic PSHUF or PUNPCK.
7665 if (Offset != 0 && Matches < 2)
7668 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7669 DL, VT, Scale, Offset, AnyExt, InputV, Mask, Subtarget, DAG);
7672 // The widest scale possible for extending is to a 64-bit integer.
7673 assert(Bits % 64 == 0 &&
7674 "The number of bits in a vector must be divisible by 64 on x86!");
7675 int NumExtElements = Bits / 64;
7677 // Each iteration, try extending the elements half as much, but into twice as
7679 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7680 assert(NumElements % NumExtElements == 0 &&
7681 "The input vector size must be divisible by the extended size.");
7682 if (SDValue V = Lower(NumElements / NumExtElements))
7686 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7690 // Returns one of the source operands if the shuffle can be reduced to a
7691 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7692 auto CanZExtLowHalf = [&]() {
7693 for (int i = NumElements / 2; i != NumElements; ++i)
7696 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7698 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7703 if (SDValue V = CanZExtLowHalf()) {
7704 V = DAG.getBitcast(MVT::v2i64, V);
7705 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7706 return DAG.getBitcast(VT, V);
7709 // No viable ext lowering found.
7713 /// \brief Try to get a scalar value for a specific element of a vector.
7715 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7716 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7717 SelectionDAG &DAG) {
7718 MVT VT = V.getSimpleValueType();
7719 MVT EltVT = VT.getVectorElementType();
7720 while (V.getOpcode() == ISD::BITCAST)
7721 V = V.getOperand(0);
7722 // If the bitcasts shift the element size, we can't extract an equivalent
7724 MVT NewVT = V.getSimpleValueType();
7725 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7728 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7729 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7730 // Ensure the scalar operand is the same size as the destination.
7731 // FIXME: Add support for scalar truncation where possible.
7732 SDValue S = V.getOperand(Idx);
7733 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7734 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7740 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7742 /// This is particularly important because the set of instructions varies
7743 /// significantly based on whether the operand is a load or not.
7744 static bool isShuffleFoldableLoad(SDValue V) {
7745 while (V.getOpcode() == ISD::BITCAST)
7746 V = V.getOperand(0);
7748 return ISD::isNON_EXTLoad(V.getNode());
7751 /// \brief Try to lower insertion of a single element into a zero vector.
7753 /// This is a common pattern that we have especially efficient patterns to lower
7754 /// across all subtarget feature sets.
7755 static SDValue lowerVectorShuffleAsElementInsertion(
7756 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7757 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7758 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7760 MVT EltVT = VT.getVectorElementType();
7762 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7763 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7765 bool IsV1Zeroable = true;
7766 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7767 if (i != V2Index && !Zeroable[i]) {
7768 IsV1Zeroable = false;
7772 // Check for a single input from a SCALAR_TO_VECTOR node.
7773 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7774 // all the smarts here sunk into that routine. However, the current
7775 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7776 // vector shuffle lowering is dead.
7777 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(),
7779 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) {
7780 // We need to zext the scalar if it is smaller than an i32.
7781 V2S = DAG.getBitcast(EltVT, V2S);
7782 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7783 // Using zext to expand a narrow element won't work for non-zero
7788 // Zero-extend directly to i32.
7790 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7792 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7793 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7794 EltVT == MVT::i16) {
7795 // Either not inserting from the low element of the input or the input
7796 // element size is too small to use VZEXT_MOVL to clear the high bits.
7800 if (!IsV1Zeroable) {
7801 // If V1 can't be treated as a zero vector we have fewer options to lower
7802 // this. We can't support integer vectors or non-zero targets cheaply, and
7803 // the V1 elements can't be permuted in any way.
7804 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7805 if (!VT.isFloatingPoint() || V2Index != 0)
7807 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7808 V1Mask[V2Index] = -1;
7809 if (!isNoopShuffleMask(V1Mask))
7811 // This is essentially a special case blend operation, but if we have
7812 // general purpose blend operations, they are always faster. Bail and let
7813 // the rest of the lowering handle these as blends.
7814 if (Subtarget->hasSSE41())
7817 // Otherwise, use MOVSD or MOVSS.
7818 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7819 "Only two types of floating point element types to handle!");
7820 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7824 // This lowering only works for the low element with floating point vectors.
7825 if (VT.isFloatingPoint() && V2Index != 0)
7828 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7830 V2 = DAG.getBitcast(VT, V2);
7833 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7834 // the desired position. Otherwise it is more efficient to do a vector
7835 // shift left. We know that we can do a vector shift left because all
7836 // the inputs are zero.
7837 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7838 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7839 V2Shuffle[V2Index] = 0;
7840 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7842 V2 = DAG.getBitcast(MVT::v2i64, V2);
7844 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7845 DAG.getConstant(V2Index * EltVT.getSizeInBits() / 8, DL,
7846 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(
7847 DAG.getDataLayout(), VT)));
7848 V2 = DAG.getBitcast(VT, V2);
7854 /// \brief Try to lower broadcast of a single element.
7856 /// For convenience, this code also bundles all of the subtarget feature set
7857 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7858 /// a convenient way to factor it out.
7859 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7861 const X86Subtarget *Subtarget,
7862 SelectionDAG &DAG) {
7863 if (!Subtarget->hasAVX())
7865 if (VT.isInteger() && !Subtarget->hasAVX2())
7868 // Check that the mask is a broadcast.
7869 int BroadcastIdx = -1;
7871 if (M >= 0 && BroadcastIdx == -1)
7873 else if (M >= 0 && M != BroadcastIdx)
7876 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7877 "a sorted mask where the broadcast "
7880 // Go up the chain of (vector) values to find a scalar load that we can
7881 // combine with the broadcast.
7883 switch (V.getOpcode()) {
7884 case ISD::CONCAT_VECTORS: {
7885 int OperandSize = Mask.size() / V.getNumOperands();
7886 V = V.getOperand(BroadcastIdx / OperandSize);
7887 BroadcastIdx %= OperandSize;
7891 case ISD::INSERT_SUBVECTOR: {
7892 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7893 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7897 int BeginIdx = (int)ConstantIdx->getZExtValue();
7899 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7900 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7901 BroadcastIdx -= BeginIdx;
7912 // Check if this is a broadcast of a scalar. We special case lowering
7913 // for scalars so that we can more effectively fold with loads.
7914 // First, look through bitcast: if the original value has a larger element
7915 // type than the shuffle, the broadcast element is in essence truncated.
7916 // Make that explicit to ease folding.
7917 if (V.getOpcode() == ISD::BITCAST && VT.isInteger()) {
7918 EVT EltVT = VT.getVectorElementType();
7919 SDValue V0 = V.getOperand(0);
7920 EVT V0VT = V0.getValueType();
7922 if (V0VT.isInteger() && V0VT.getVectorElementType().bitsGT(EltVT) &&
7923 ((V0.getOpcode() == ISD::BUILD_VECTOR ||
7924 (V0.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)))) {
7925 V = DAG.getNode(ISD::TRUNCATE, DL, EltVT, V0.getOperand(BroadcastIdx));
7930 // Also check the simpler case, where we can directly reuse the scalar.
7931 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7932 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7933 V = V.getOperand(BroadcastIdx);
7935 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7936 // Only AVX2 has register broadcasts.
7937 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7939 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7940 // We can't broadcast from a vector register without AVX2, and we can only
7941 // broadcast from the zero-element of a vector register.
7945 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7948 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7949 // INSERTPS when the V1 elements are already in the correct locations
7950 // because otherwise we can just always use two SHUFPS instructions which
7951 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7952 // perform INSERTPS if a single V1 element is out of place and all V2
7953 // elements are zeroable.
7954 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7956 SelectionDAG &DAG) {
7957 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7958 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7959 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7960 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7962 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7965 int V1DstIndex = -1;
7966 int V2DstIndex = -1;
7967 bool V1UsedInPlace = false;
7969 for (int i = 0; i < 4; ++i) {
7970 // Synthesize a zero mask from the zeroable elements (includes undefs).
7976 // Flag if we use any V1 inputs in place.
7978 V1UsedInPlace = true;
7982 // We can only insert a single non-zeroable element.
7983 if (V1DstIndex != -1 || V2DstIndex != -1)
7987 // V1 input out of place for insertion.
7990 // V2 input for insertion.
7995 // Don't bother if we have no (non-zeroable) element for insertion.
7996 if (V1DstIndex == -1 && V2DstIndex == -1)
7999 // Determine element insertion src/dst indices. The src index is from the
8000 // start of the inserted vector, not the start of the concatenated vector.
8001 unsigned V2SrcIndex = 0;
8002 if (V1DstIndex != -1) {
8003 // If we have a V1 input out of place, we use V1 as the V2 element insertion
8004 // and don't use the original V2 at all.
8005 V2SrcIndex = Mask[V1DstIndex];
8006 V2DstIndex = V1DstIndex;
8009 V2SrcIndex = Mask[V2DstIndex] - 4;
8012 // If no V1 inputs are used in place, then the result is created only from
8013 // the zero mask and the V2 insertion - so remove V1 dependency.
8015 V1 = DAG.getUNDEF(MVT::v4f32);
8017 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
8018 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
8020 // Insert the V2 element into the desired position.
8022 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
8023 DAG.getConstant(InsertPSMask, DL, MVT::i8));
8026 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
8027 /// UNPCK instruction.
8029 /// This specifically targets cases where we end up with alternating between
8030 /// the two inputs, and so can permute them into something that feeds a single
8031 /// UNPCK instruction. Note that this routine only targets integer vectors
8032 /// because for floating point vectors we have a generalized SHUFPS lowering
8033 /// strategy that handles everything that doesn't *exactly* match an unpack,
8034 /// making this clever lowering unnecessary.
8035 static SDValue lowerVectorShuffleAsPermuteAndUnpack(SDLoc DL, MVT VT,
8036 SDValue V1, SDValue V2,
8038 SelectionDAG &DAG) {
8039 assert(!VT.isFloatingPoint() &&
8040 "This routine only supports integer vectors.");
8041 assert(!isSingleInputShuffleMask(Mask) &&
8042 "This routine should only be used when blending two inputs.");
8043 assert(Mask.size() >= 2 && "Single element masks are invalid.");
8045 int Size = Mask.size();
8047 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
8048 return M >= 0 && M % Size < Size / 2;
8050 int NumHiInputs = std::count_if(
8051 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
8053 bool UnpackLo = NumLoInputs >= NumHiInputs;
8055 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
8056 SmallVector<int, 32> V1Mask(Mask.size(), -1);
8057 SmallVector<int, 32> V2Mask(Mask.size(), -1);
8059 for (int i = 0; i < Size; ++i) {
8063 // Each element of the unpack contains Scale elements from this mask.
8064 int UnpackIdx = i / Scale;
8066 // We only handle the case where V1 feeds the first slots of the unpack.
8067 // We rely on canonicalization to ensure this is the case.
8068 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
8071 // Setup the mask for this input. The indexing is tricky as we have to
8072 // handle the unpack stride.
8073 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
8074 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
8078 // If we will have to shuffle both inputs to use the unpack, check whether
8079 // we can just unpack first and shuffle the result. If so, skip this unpack.
8080 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
8081 !isNoopShuffleMask(V2Mask))
8084 // Shuffle the inputs into place.
8085 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
8086 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
8088 // Cast the inputs to the type we will use to unpack them.
8089 V1 = DAG.getBitcast(UnpackVT, V1);
8090 V2 = DAG.getBitcast(UnpackVT, V2);
8092 // Unpack the inputs and cast the result back to the desired type.
8093 return DAG.getBitcast(
8094 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8098 // We try each unpack from the largest to the smallest to try and find one
8099 // that fits this mask.
8100 int OrigNumElements = VT.getVectorNumElements();
8101 int OrigScalarSize = VT.getScalarSizeInBits();
8102 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
8103 int Scale = ScalarSize / OrigScalarSize;
8104 int NumElements = OrigNumElements / Scale;
8105 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
8106 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
8110 // If none of the unpack-rooted lowerings worked (or were profitable) try an
8112 if (NumLoInputs == 0 || NumHiInputs == 0) {
8113 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
8114 "We have to have *some* inputs!");
8115 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
8117 // FIXME: We could consider the total complexity of the permute of each
8118 // possible unpacking. Or at the least we should consider how many
8119 // half-crossings are created.
8120 // FIXME: We could consider commuting the unpacks.
8122 SmallVector<int, 32> PermMask;
8123 PermMask.assign(Size, -1);
8124 for (int i = 0; i < Size; ++i) {
8128 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
8131 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
8133 return DAG.getVectorShuffle(
8134 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
8136 DAG.getUNDEF(VT), PermMask);
8142 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
8144 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
8145 /// support for floating point shuffles but not integer shuffles. These
8146 /// instructions will incur a domain crossing penalty on some chips though so
8147 /// it is better to avoid lowering through this for integer vectors where
8149 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8150 const X86Subtarget *Subtarget,
8151 SelectionDAG &DAG) {
8153 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
8154 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8155 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
8156 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8157 ArrayRef<int> Mask = SVOp->getMask();
8158 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8160 if (isSingleInputShuffleMask(Mask)) {
8161 // Use low duplicate instructions for masks that match their pattern.
8162 if (Subtarget->hasSSE3())
8163 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
8164 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
8166 // Straight shuffle of a single input vector. Simulate this by using the
8167 // single input as both of the "inputs" to this instruction..
8168 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
8170 if (Subtarget->hasAVX()) {
8171 // If we have AVX, we can use VPERMILPS which will allow folding a load
8172 // into the shuffle.
8173 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
8174 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8177 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
8178 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8180 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
8181 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
8183 // If we have a single input, insert that into V1 if we can do so cheaply.
8184 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
8185 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8186 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
8188 // Try inverting the insertion since for v2 masks it is easy to do and we
8189 // can't reliably sort the mask one way or the other.
8190 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
8191 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
8192 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8193 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
8197 // Try to use one of the special instruction patterns to handle two common
8198 // blend patterns if a zero-blend above didn't work.
8199 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
8200 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8201 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
8202 // We can either use a special instruction to load over the low double or
8203 // to move just the low double.
8205 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
8207 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
8209 if (Subtarget->hasSSE41())
8210 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
8214 // Use dedicated unpack instructions for masks that match their pattern.
8215 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8216 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
8217 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8218 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
8220 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
8221 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
8222 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
8225 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
8227 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
8228 /// the integer unit to minimize domain crossing penalties. However, for blends
8229 /// it falls back to the floating point shuffle operation with appropriate bit
8231 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8232 const X86Subtarget *Subtarget,
8233 SelectionDAG &DAG) {
8235 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
8236 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8237 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
8238 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8239 ArrayRef<int> Mask = SVOp->getMask();
8240 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
8242 if (isSingleInputShuffleMask(Mask)) {
8243 // Check for being able to broadcast a single element.
8244 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
8245 Mask, Subtarget, DAG))
8248 // Straight shuffle of a single input vector. For everything from SSE2
8249 // onward this has a single fast instruction with no scary immediates.
8250 // We have to map the mask as it is actually a v4i32 shuffle instruction.
8251 V1 = DAG.getBitcast(MVT::v4i32, V1);
8252 int WidenedMask[4] = {
8253 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
8254 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
8255 return DAG.getBitcast(
8257 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8258 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
8260 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
8261 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
8262 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
8263 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
8265 // If we have a blend of two PACKUS operations an the blend aligns with the
8266 // low and half halves, we can just merge the PACKUS operations. This is
8267 // particularly important as it lets us merge shuffles that this routine itself
8269 auto GetPackNode = [](SDValue V) {
8270 while (V.getOpcode() == ISD::BITCAST)
8271 V = V.getOperand(0);
8273 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
8275 if (SDValue V1Pack = GetPackNode(V1))
8276 if (SDValue V2Pack = GetPackNode(V2))
8277 return DAG.getBitcast(MVT::v2i64,
8278 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
8279 Mask[0] == 0 ? V1Pack.getOperand(0)
8280 : V1Pack.getOperand(1),
8281 Mask[1] == 2 ? V2Pack.getOperand(0)
8282 : V2Pack.getOperand(1)));
8284 // Try to use shift instructions.
8286 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
8289 // When loading a scalar and then shuffling it into a vector we can often do
8290 // the insertion cheaply.
8291 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8292 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8294 // Try inverting the insertion since for v2 masks it is easy to do and we
8295 // can't reliably sort the mask one way or the other.
8296 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
8297 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
8298 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
8301 // We have different paths for blend lowering, but they all must use the
8302 // *exact* same predicate.
8303 bool IsBlendSupported = Subtarget->hasSSE41();
8304 if (IsBlendSupported)
8305 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
8309 // Use dedicated unpack instructions for masks that match their pattern.
8310 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
8311 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
8312 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
8313 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
8315 // Try to use byte rotation instructions.
8316 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8317 if (Subtarget->hasSSSE3())
8318 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8319 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
8322 // If we have direct support for blends, we should lower by decomposing into
8323 // a permute. That will be faster than the domain cross.
8324 if (IsBlendSupported)
8325 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
8328 // We implement this with SHUFPD which is pretty lame because it will likely
8329 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
8330 // However, all the alternatives are still more cycles and newer chips don't
8331 // have this problem. It would be really nice if x86 had better shuffles here.
8332 V1 = DAG.getBitcast(MVT::v2f64, V1);
8333 V2 = DAG.getBitcast(MVT::v2f64, V2);
8334 return DAG.getBitcast(MVT::v2i64,
8335 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
8338 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
8340 /// This is used to disable more specialized lowerings when the shufps lowering
8341 /// will happen to be efficient.
8342 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
8343 // This routine only handles 128-bit shufps.
8344 assert(Mask.size() == 4 && "Unsupported mask size!");
8346 // To lower with a single SHUFPS we need to have the low half and high half
8347 // each requiring a single input.
8348 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
8350 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
8356 /// \brief Lower a vector shuffle using the SHUFPS instruction.
8358 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
8359 /// It makes no assumptions about whether this is the *best* lowering, it simply
8361 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
8362 ArrayRef<int> Mask, SDValue V1,
8363 SDValue V2, SelectionDAG &DAG) {
8364 SDValue LowV = V1, HighV = V2;
8365 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
8368 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8370 if (NumV2Elements == 1) {
8372 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
8375 // Compute the index adjacent to V2Index and in the same half by toggling
8377 int V2AdjIndex = V2Index ^ 1;
8379 if (Mask[V2AdjIndex] == -1) {
8380 // Handles all the cases where we have a single V2 element and an undef.
8381 // This will only ever happen in the high lanes because we commute the
8382 // vector otherwise.
8384 std::swap(LowV, HighV);
8385 NewMask[V2Index] -= 4;
8387 // Handle the case where the V2 element ends up adjacent to a V1 element.
8388 // To make this work, blend them together as the first step.
8389 int V1Index = V2AdjIndex;
8390 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
8391 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
8392 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8394 // Now proceed to reconstruct the final blend as we have the necessary
8395 // high or low half formed.
8402 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
8403 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
8405 } else if (NumV2Elements == 2) {
8406 if (Mask[0] < 4 && Mask[1] < 4) {
8407 // Handle the easy case where we have V1 in the low lanes and V2 in the
8411 } else if (Mask[2] < 4 && Mask[3] < 4) {
8412 // We also handle the reversed case because this utility may get called
8413 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
8414 // arrange things in the right direction.
8420 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
8421 // trying to place elements directly, just blend them and set up the final
8422 // shuffle to place them.
8424 // The first two blend mask elements are for V1, the second two are for
8426 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
8427 Mask[2] < 4 ? Mask[2] : Mask[3],
8428 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
8429 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
8430 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
8431 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
8433 // Now we do a normal shuffle of V1 by giving V1 as both operands to
8436 NewMask[0] = Mask[0] < 4 ? 0 : 2;
8437 NewMask[1] = Mask[0] < 4 ? 2 : 0;
8438 NewMask[2] = Mask[2] < 4 ? 1 : 3;
8439 NewMask[3] = Mask[2] < 4 ? 3 : 1;
8442 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
8443 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
8446 /// \brief Lower 4-lane 32-bit floating point shuffles.
8448 /// Uses instructions exclusively from the floating point unit to minimize
8449 /// domain crossing penalties, as these are sufficient to implement all v4f32
8451 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8452 const X86Subtarget *Subtarget,
8453 SelectionDAG &DAG) {
8455 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
8456 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8457 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
8458 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8459 ArrayRef<int> Mask = SVOp->getMask();
8460 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8463 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8465 if (NumV2Elements == 0) {
8466 // Check for being able to broadcast a single element.
8467 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
8468 Mask, Subtarget, DAG))
8471 // Use even/odd duplicate instructions for masks that match their pattern.
8472 if (Subtarget->hasSSE3()) {
8473 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8474 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8475 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8476 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8479 if (Subtarget->hasAVX()) {
8480 // If we have AVX, we can use VPERMILPS which will allow folding a load
8481 // into the shuffle.
8482 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8483 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8486 // Otherwise, use a straight shuffle of a single input vector. We pass the
8487 // input vector to both operands to simulate this with a SHUFPS.
8488 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8489 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8492 // There are special ways we can lower some single-element blends. However, we
8493 // have custom ways we can lower more complex single-element blends below that
8494 // we defer to if both this and BLENDPS fail to match, so restrict this to
8495 // when the V2 input is targeting element 0 of the mask -- that is the fast
8497 if (NumV2Elements == 1 && Mask[0] >= 4)
8498 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8499 Mask, Subtarget, DAG))
8502 if (Subtarget->hasSSE41()) {
8503 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8507 // Use INSERTPS if we can complete the shuffle efficiently.
8508 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8511 if (!isSingleSHUFPSMask(Mask))
8512 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8513 DL, MVT::v4f32, V1, V2, Mask, DAG))
8517 // Use dedicated unpack instructions for masks that match their pattern.
8518 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8519 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8520 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8521 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8522 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8523 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8524 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8525 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8527 // Otherwise fall back to a SHUFPS lowering strategy.
8528 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8531 /// \brief Lower 4-lane i32 vector shuffles.
8533 /// We try to handle these with integer-domain shuffles where we can, but for
8534 /// blends we use the floating point domain blend instructions.
8535 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8536 const X86Subtarget *Subtarget,
8537 SelectionDAG &DAG) {
8539 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8540 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8541 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8542 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8543 ArrayRef<int> Mask = SVOp->getMask();
8544 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8546 // Whenever we can lower this as a zext, that instruction is strictly faster
8547 // than any alternative. It also allows us to fold memory operands into the
8548 // shuffle in many cases.
8549 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8550 Mask, Subtarget, DAG))
8554 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8556 if (NumV2Elements == 0) {
8557 // Check for being able to broadcast a single element.
8558 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8559 Mask, Subtarget, DAG))
8562 // Straight shuffle of a single input vector. For everything from SSE2
8563 // onward this has a single fast instruction with no scary immediates.
8564 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8565 // but we aren't actually going to use the UNPCK instruction because doing
8566 // so prevents folding a load into this instruction or making a copy.
8567 const int UnpackLoMask[] = {0, 0, 1, 1};
8568 const int UnpackHiMask[] = {2, 2, 3, 3};
8569 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8570 Mask = UnpackLoMask;
8571 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8572 Mask = UnpackHiMask;
8574 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8575 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8578 // Try to use shift instructions.
8580 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8583 // There are special ways we can lower some single-element blends.
8584 if (NumV2Elements == 1)
8585 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8586 Mask, Subtarget, DAG))
8589 // We have different paths for blend lowering, but they all must use the
8590 // *exact* same predicate.
8591 bool IsBlendSupported = Subtarget->hasSSE41();
8592 if (IsBlendSupported)
8593 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8597 if (SDValue Masked =
8598 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8601 // Use dedicated unpack instructions for masks that match their pattern.
8602 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8603 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8604 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8605 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8606 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8607 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8608 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8609 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8611 // Try to use byte rotation instructions.
8612 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8613 if (Subtarget->hasSSSE3())
8614 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8615 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8618 // If we have direct support for blends, we should lower by decomposing into
8619 // a permute. That will be faster than the domain cross.
8620 if (IsBlendSupported)
8621 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8624 // Try to lower by permuting the inputs into an unpack instruction.
8625 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v4i32, V1,
8629 // We implement this with SHUFPS because it can blend from two vectors.
8630 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8631 // up the inputs, bypassing domain shift penalties that we would encur if we
8632 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8634 return DAG.getBitcast(
8636 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8637 DAG.getBitcast(MVT::v4f32, V2), Mask));
8640 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8641 /// shuffle lowering, and the most complex part.
8643 /// The lowering strategy is to try to form pairs of input lanes which are
8644 /// targeted at the same half of the final vector, and then use a dword shuffle
8645 /// to place them onto the right half, and finally unpack the paired lanes into
8646 /// their final position.
8648 /// The exact breakdown of how to form these dword pairs and align them on the
8649 /// correct sides is really tricky. See the comments within the function for
8650 /// more of the details.
8652 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8653 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8654 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8655 /// vector, form the analogous 128-bit 8-element Mask.
8656 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8657 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8658 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8659 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8660 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8662 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8663 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8664 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8666 SmallVector<int, 4> LoInputs;
8667 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8668 [](int M) { return M >= 0; });
8669 std::sort(LoInputs.begin(), LoInputs.end());
8670 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8671 SmallVector<int, 4> HiInputs;
8672 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8673 [](int M) { return M >= 0; });
8674 std::sort(HiInputs.begin(), HiInputs.end());
8675 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8677 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8678 int NumHToL = LoInputs.size() - NumLToL;
8680 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8681 int NumHToH = HiInputs.size() - NumLToH;
8682 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8683 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8684 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8685 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8687 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8688 // such inputs we can swap two of the dwords across the half mark and end up
8689 // with <=2 inputs to each half in each half. Once there, we can fall through
8690 // to the generic code below. For example:
8692 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8693 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8695 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8696 // and an existing 2-into-2 on the other half. In this case we may have to
8697 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8698 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8699 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8700 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8701 // half than the one we target for fixing) will be fixed when we re-enter this
8702 // path. We will also combine away any sequence of PSHUFD instructions that
8703 // result into a single instruction. Here is an example of the tricky case:
8705 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8706 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8708 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8710 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8711 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8713 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8714 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8716 // The result is fine to be handled by the generic logic.
8717 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8718 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8719 int AOffset, int BOffset) {
8720 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8721 "Must call this with A having 3 or 1 inputs from the A half.");
8722 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8723 "Must call this with B having 1 or 3 inputs from the B half.");
8724 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8725 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8727 bool ThreeAInputs = AToAInputs.size() == 3;
8729 // Compute the index of dword with only one word among the three inputs in
8730 // a half by taking the sum of the half with three inputs and subtracting
8731 // the sum of the actual three inputs. The difference is the remaining
8734 int &TripleDWord = ThreeAInputs ? ADWord : BDWord;
8735 int &OneInputDWord = ThreeAInputs ? BDWord : ADWord;
8736 int TripleInputOffset = ThreeAInputs ? AOffset : BOffset;
8737 ArrayRef<int> TripleInputs = ThreeAInputs ? AToAInputs : BToAInputs;
8738 int OneInput = ThreeAInputs ? BToAInputs[0] : AToAInputs[0];
8739 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8740 int TripleNonInputIdx =
8741 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8742 TripleDWord = TripleNonInputIdx / 2;
8744 // We use xor with one to compute the adjacent DWord to whichever one the
8746 OneInputDWord = (OneInput / 2) ^ 1;
8748 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8749 // and BToA inputs. If there is also such a problem with the BToB and AToB
8750 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8751 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8752 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8753 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8754 // Compute how many inputs will be flipped by swapping these DWords. We
8756 // to balance this to ensure we don't form a 3-1 shuffle in the other
8758 int NumFlippedAToBInputs =
8759 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8760 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8761 int NumFlippedBToBInputs =
8762 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8763 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8764 if ((NumFlippedAToBInputs == 1 &&
8765 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8766 (NumFlippedBToBInputs == 1 &&
8767 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8768 // We choose whether to fix the A half or B half based on whether that
8769 // half has zero flipped inputs. At zero, we may not be able to fix it
8770 // with that half. We also bias towards fixing the B half because that
8771 // will more commonly be the high half, and we have to bias one way.
8772 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8773 ArrayRef<int> Inputs) {
8774 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8775 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8776 PinnedIdx ^ 1) != Inputs.end();
8777 // Determine whether the free index is in the flipped dword or the
8778 // unflipped dword based on where the pinned index is. We use this bit
8779 // in an xor to conditionally select the adjacent dword.
8780 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8781 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8782 FixFreeIdx) != Inputs.end();
8783 if (IsFixIdxInput == IsFixFreeIdxInput)
8785 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8786 FixFreeIdx) != Inputs.end();
8787 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8788 "We need to be changing the number of flipped inputs!");
8789 int PSHUFHalfMask[] = {0, 1, 2, 3};
8790 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8791 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8793 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8796 if (M != -1 && M == FixIdx)
8798 else if (M != -1 && M == FixFreeIdx)
8801 if (NumFlippedBToBInputs != 0) {
8803 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8804 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8806 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8807 int APinnedIdx = ThreeAInputs ? TripleNonInputIdx : OneInput;
8808 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8813 int PSHUFDMask[] = {0, 1, 2, 3};
8814 PSHUFDMask[ADWord] = BDWord;
8815 PSHUFDMask[BDWord] = ADWord;
8818 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8819 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8821 // Adjust the mask to match the new locations of A and B.
8823 if (M != -1 && M/2 == ADWord)
8824 M = 2 * BDWord + M % 2;
8825 else if (M != -1 && M/2 == BDWord)
8826 M = 2 * ADWord + M % 2;
8828 // Recurse back into this routine to re-compute state now that this isn't
8829 // a 3 and 1 problem.
8830 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8833 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8834 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8835 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8836 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8838 // At this point there are at most two inputs to the low and high halves from
8839 // each half. That means the inputs can always be grouped into dwords and
8840 // those dwords can then be moved to the correct half with a dword shuffle.
8841 // We use at most one low and one high word shuffle to collect these paired
8842 // inputs into dwords, and finally a dword shuffle to place them.
8843 int PSHUFLMask[4] = {-1, -1, -1, -1};
8844 int PSHUFHMask[4] = {-1, -1, -1, -1};
8845 int PSHUFDMask[4] = {-1, -1, -1, -1};
8847 // First fix the masks for all the inputs that are staying in their
8848 // original halves. This will then dictate the targets of the cross-half
8850 auto fixInPlaceInputs =
8851 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8852 MutableArrayRef<int> SourceHalfMask,
8853 MutableArrayRef<int> HalfMask, int HalfOffset) {
8854 if (InPlaceInputs.empty())
8856 if (InPlaceInputs.size() == 1) {
8857 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8858 InPlaceInputs[0] - HalfOffset;
8859 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8862 if (IncomingInputs.empty()) {
8863 // Just fix all of the in place inputs.
8864 for (int Input : InPlaceInputs) {
8865 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8866 PSHUFDMask[Input / 2] = Input / 2;
8871 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8872 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8873 InPlaceInputs[0] - HalfOffset;
8874 // Put the second input next to the first so that they are packed into
8875 // a dword. We find the adjacent index by toggling the low bit.
8876 int AdjIndex = InPlaceInputs[0] ^ 1;
8877 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8878 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8879 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8881 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8882 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8884 // Now gather the cross-half inputs and place them into a free dword of
8885 // their target half.
8886 // FIXME: This operation could almost certainly be simplified dramatically to
8887 // look more like the 3-1 fixing operation.
8888 auto moveInputsToRightHalf = [&PSHUFDMask](
8889 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8890 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8891 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8893 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8894 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8896 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8898 int LowWord = Word & ~1;
8899 int HighWord = Word | 1;
8900 return isWordClobbered(SourceHalfMask, LowWord) ||
8901 isWordClobbered(SourceHalfMask, HighWord);
8904 if (IncomingInputs.empty())
8907 if (ExistingInputs.empty()) {
8908 // Map any dwords with inputs from them into the right half.
8909 for (int Input : IncomingInputs) {
8910 // If the source half mask maps over the inputs, turn those into
8911 // swaps and use the swapped lane.
8912 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8913 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8914 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8915 Input - SourceOffset;
8916 // We have to swap the uses in our half mask in one sweep.
8917 for (int &M : HalfMask)
8918 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8920 else if (M == Input)
8921 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8923 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8924 Input - SourceOffset &&
8925 "Previous placement doesn't match!");
8927 // Note that this correctly re-maps both when we do a swap and when
8928 // we observe the other side of the swap above. We rely on that to
8929 // avoid swapping the members of the input list directly.
8930 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8933 // Map the input's dword into the correct half.
8934 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8935 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8937 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8939 "Previous placement doesn't match!");
8942 // And just directly shift any other-half mask elements to be same-half
8943 // as we will have mirrored the dword containing the element into the
8944 // same position within that half.
8945 for (int &M : HalfMask)
8946 if (M >= SourceOffset && M < SourceOffset + 4) {
8947 M = M - SourceOffset + DestOffset;
8948 assert(M >= 0 && "This should never wrap below zero!");
8953 // Ensure we have the input in a viable dword of its current half. This
8954 // is particularly tricky because the original position may be clobbered
8955 // by inputs being moved and *staying* in that half.
8956 if (IncomingInputs.size() == 1) {
8957 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8958 int InputFixed = std::find(std::begin(SourceHalfMask),
8959 std::end(SourceHalfMask), -1) -
8960 std::begin(SourceHalfMask) + SourceOffset;
8961 SourceHalfMask[InputFixed - SourceOffset] =
8962 IncomingInputs[0] - SourceOffset;
8963 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8965 IncomingInputs[0] = InputFixed;
8967 } else if (IncomingInputs.size() == 2) {
8968 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8969 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8970 // We have two non-adjacent or clobbered inputs we need to extract from
8971 // the source half. To do this, we need to map them into some adjacent
8972 // dword slot in the source mask.
8973 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8974 IncomingInputs[1] - SourceOffset};
8976 // If there is a free slot in the source half mask adjacent to one of
8977 // the inputs, place the other input in it. We use (Index XOR 1) to
8978 // compute an adjacent index.
8979 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8980 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8981 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8982 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8983 InputsFixed[1] = InputsFixed[0] ^ 1;
8984 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8985 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8986 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8987 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8988 InputsFixed[0] = InputsFixed[1] ^ 1;
8989 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8990 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8991 // The two inputs are in the same DWord but it is clobbered and the
8992 // adjacent DWord isn't used at all. Move both inputs to the free
8994 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8995 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8996 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8997 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8999 // The only way we hit this point is if there is no clobbering
9000 // (because there are no off-half inputs to this half) and there is no
9001 // free slot adjacent to one of the inputs. In this case, we have to
9002 // swap an input with a non-input.
9003 for (int i = 0; i < 4; ++i)
9004 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
9005 "We can't handle any clobbers here!");
9006 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
9007 "Cannot have adjacent inputs here!");
9009 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
9010 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
9012 // We also have to update the final source mask in this case because
9013 // it may need to undo the above swap.
9014 for (int &M : FinalSourceHalfMask)
9015 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
9016 M = InputsFixed[1] + SourceOffset;
9017 else if (M == InputsFixed[1] + SourceOffset)
9018 M = (InputsFixed[0] ^ 1) + SourceOffset;
9020 InputsFixed[1] = InputsFixed[0] ^ 1;
9023 // Point everything at the fixed inputs.
9024 for (int &M : HalfMask)
9025 if (M == IncomingInputs[0])
9026 M = InputsFixed[0] + SourceOffset;
9027 else if (M == IncomingInputs[1])
9028 M = InputsFixed[1] + SourceOffset;
9030 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
9031 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
9034 llvm_unreachable("Unhandled input size!");
9037 // Now hoist the DWord down to the right half.
9038 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
9039 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
9040 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
9041 for (int &M : HalfMask)
9042 for (int Input : IncomingInputs)
9044 M = FreeDWord * 2 + Input % 2;
9046 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
9047 /*SourceOffset*/ 4, /*DestOffset*/ 0);
9048 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
9049 /*SourceOffset*/ 0, /*DestOffset*/ 4);
9051 // Now enact all the shuffles we've computed to move the inputs into their
9053 if (!isNoopShuffleMask(PSHUFLMask))
9054 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9055 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
9056 if (!isNoopShuffleMask(PSHUFHMask))
9057 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9058 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
9059 if (!isNoopShuffleMask(PSHUFDMask))
9062 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
9063 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9065 // At this point, each half should contain all its inputs, and we can then
9066 // just shuffle them into their final position.
9067 assert(std::count_if(LoMask.begin(), LoMask.end(),
9068 [](int M) { return M >= 4; }) == 0 &&
9069 "Failed to lift all the high half inputs to the low mask!");
9070 assert(std::count_if(HiMask.begin(), HiMask.end(),
9071 [](int M) { return M >= 0 && M < 4; }) == 0 &&
9072 "Failed to lift all the low half inputs to the high mask!");
9074 // Do a half shuffle for the low mask.
9075 if (!isNoopShuffleMask(LoMask))
9076 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
9077 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
9079 // Do a half shuffle with the high mask after shifting its values down.
9080 for (int &M : HiMask)
9083 if (!isNoopShuffleMask(HiMask))
9084 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
9085 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
9090 /// \brief Helper to form a PSHUFB-based shuffle+blend.
9091 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
9092 SDValue V2, ArrayRef<int> Mask,
9093 SelectionDAG &DAG, bool &V1InUse,
9095 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
9101 int Size = Mask.size();
9102 int Scale = 16 / Size;
9103 for (int i = 0; i < 16; ++i) {
9104 if (Mask[i / Scale] == -1) {
9105 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
9107 const int ZeroMask = 0x80;
9108 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
9110 int V2Idx = Mask[i / Scale] < Size
9112 : (Mask[i / Scale] - Size) * Scale + i % Scale;
9113 if (Zeroable[i / Scale])
9114 V1Idx = V2Idx = ZeroMask;
9115 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
9116 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
9117 V1InUse |= (ZeroMask != V1Idx);
9118 V2InUse |= (ZeroMask != V2Idx);
9123 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9124 DAG.getBitcast(MVT::v16i8, V1),
9125 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
9127 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
9128 DAG.getBitcast(MVT::v16i8, V2),
9129 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
9131 // If we need shuffled inputs from both, blend the two.
9133 if (V1InUse && V2InUse)
9134 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
9136 V = V1InUse ? V1 : V2;
9138 // Cast the result back to the correct type.
9139 return DAG.getBitcast(VT, V);
9142 /// \brief Generic lowering of 8-lane i16 shuffles.
9144 /// This handles both single-input shuffles and combined shuffle/blends with
9145 /// two inputs. The single input shuffles are immediately delegated to
9146 /// a dedicated lowering routine.
9148 /// The blends are lowered in one of three fundamental ways. If there are few
9149 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
9150 /// of the input is significantly cheaper when lowered as an interleaving of
9151 /// the two inputs, try to interleave them. Otherwise, blend the low and high
9152 /// halves of the inputs separately (making them have relatively few inputs)
9153 /// and then concatenate them.
9154 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9155 const X86Subtarget *Subtarget,
9156 SelectionDAG &DAG) {
9158 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
9159 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9160 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
9161 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9162 ArrayRef<int> OrigMask = SVOp->getMask();
9163 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
9164 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
9165 MutableArrayRef<int> Mask(MaskStorage);
9167 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9169 // Whenever we can lower this as a zext, that instruction is strictly faster
9170 // than any alternative.
9171 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9172 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
9175 auto isV1 = [](int M) { return M >= 0 && M < 8; };
9177 auto isV2 = [](int M) { return M >= 8; };
9179 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
9181 if (NumV2Inputs == 0) {
9182 // Check for being able to broadcast a single element.
9183 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
9184 Mask, Subtarget, DAG))
9187 // Try to use shift instructions.
9189 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
9192 // Use dedicated unpack instructions for masks that match their pattern.
9193 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
9194 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
9195 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
9196 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
9198 // Try to use byte rotation instructions.
9199 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
9200 Mask, Subtarget, DAG))
9203 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
9207 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
9208 "All single-input shuffles should be canonicalized to be V1-input "
9211 // Try to use shift instructions.
9213 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
9216 // See if we can use SSE4A Extraction / Insertion.
9217 if (Subtarget->hasSSE4A())
9218 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
9221 // There are special ways we can lower some single-element blends.
9222 if (NumV2Inputs == 1)
9223 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
9224 Mask, Subtarget, DAG))
9227 // We have different paths for blend lowering, but they all must use the
9228 // *exact* same predicate.
9229 bool IsBlendSupported = Subtarget->hasSSE41();
9230 if (IsBlendSupported)
9231 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
9235 if (SDValue Masked =
9236 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
9239 // Use dedicated unpack instructions for masks that match their pattern.
9240 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
9241 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
9242 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
9243 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
9245 // Try to use byte rotation instructions.
9246 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9247 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
9250 if (SDValue BitBlend =
9251 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
9254 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(DL, MVT::v8i16, V1,
9258 // If we can't directly blend but can use PSHUFB, that will be better as it
9259 // can both shuffle and set up the inefficient blend.
9260 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
9261 bool V1InUse, V2InUse;
9262 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
9266 // We can always bit-blend if we have to so the fallback strategy is to
9267 // decompose into single-input permutes and blends.
9268 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
9272 /// \brief Check whether a compaction lowering can be done by dropping even
9273 /// elements and compute how many times even elements must be dropped.
9275 /// This handles shuffles which take every Nth element where N is a power of
9276 /// two. Example shuffle masks:
9278 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
9279 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
9280 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
9281 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
9282 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
9283 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
9285 /// Any of these lanes can of course be undef.
9287 /// This routine only supports N <= 3.
9288 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
9291 /// \returns N above, or the number of times even elements must be dropped if
9292 /// there is such a number. Otherwise returns zero.
9293 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
9294 // Figure out whether we're looping over two inputs or just one.
9295 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9297 // The modulus for the shuffle vector entries is based on whether this is
9298 // a single input or not.
9299 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
9300 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
9301 "We should only be called with masks with a power-of-2 size!");
9303 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
9305 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
9306 // and 2^3 simultaneously. This is because we may have ambiguity with
9307 // partially undef inputs.
9308 bool ViableForN[3] = {true, true, true};
9310 for (int i = 0, e = Mask.size(); i < e; ++i) {
9311 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
9316 bool IsAnyViable = false;
9317 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9318 if (ViableForN[j]) {
9321 // The shuffle mask must be equal to (i * 2^N) % M.
9322 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
9325 ViableForN[j] = false;
9327 // Early exit if we exhaust the possible powers of two.
9332 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
9336 // Return 0 as there is no viable power of two.
9340 /// \brief Generic lowering of v16i8 shuffles.
9342 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
9343 /// detect any complexity reducing interleaving. If that doesn't help, it uses
9344 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
9345 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
9347 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9348 const X86Subtarget *Subtarget,
9349 SelectionDAG &DAG) {
9351 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
9352 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9353 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
9354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9355 ArrayRef<int> Mask = SVOp->getMask();
9356 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9358 // Try to use shift instructions.
9360 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
9363 // Try to use byte rotation instructions.
9364 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9365 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9368 // Try to use a zext lowering.
9369 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
9370 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
9373 // See if we can use SSE4A Extraction / Insertion.
9374 if (Subtarget->hasSSE4A())
9375 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
9379 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
9381 // For single-input shuffles, there are some nicer lowering tricks we can use.
9382 if (NumV2Elements == 0) {
9383 // Check for being able to broadcast a single element.
9384 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
9385 Mask, Subtarget, DAG))
9388 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
9389 // Notably, this handles splat and partial-splat shuffles more efficiently.
9390 // However, it only makes sense if the pre-duplication shuffle simplifies
9391 // things significantly. Currently, this means we need to be able to
9392 // express the pre-duplication shuffle as an i16 shuffle.
9394 // FIXME: We should check for other patterns which can be widened into an
9395 // i16 shuffle as well.
9396 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
9397 for (int i = 0; i < 16; i += 2)
9398 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
9403 auto tryToWidenViaDuplication = [&]() -> SDValue {
9404 if (!canWidenViaDuplication(Mask))
9406 SmallVector<int, 4> LoInputs;
9407 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
9408 [](int M) { return M >= 0 && M < 8; });
9409 std::sort(LoInputs.begin(), LoInputs.end());
9410 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
9412 SmallVector<int, 4> HiInputs;
9413 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
9414 [](int M) { return M >= 8; });
9415 std::sort(HiInputs.begin(), HiInputs.end());
9416 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
9419 bool TargetLo = LoInputs.size() >= HiInputs.size();
9420 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
9421 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
9423 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
9424 SmallDenseMap<int, int, 8> LaneMap;
9425 for (int I : InPlaceInputs) {
9426 PreDupI16Shuffle[I/2] = I/2;
9429 int j = TargetLo ? 0 : 4, je = j + 4;
9430 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
9431 // Check if j is already a shuffle of this input. This happens when
9432 // there are two adjacent bytes after we move the low one.
9433 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
9434 // If we haven't yet mapped the input, search for a slot into which
9436 while (j < je && PreDupI16Shuffle[j] != -1)
9440 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
9443 // Map this input with the i16 shuffle.
9444 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
9447 // Update the lane map based on the mapping we ended up with.
9448 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
9450 V1 = DAG.getBitcast(
9452 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9453 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
9455 // Unpack the bytes to form the i16s that will be shuffled into place.
9456 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
9457 MVT::v16i8, V1, V1);
9459 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9460 for (int i = 0; i < 16; ++i)
9461 if (Mask[i] != -1) {
9462 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
9463 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
9464 if (PostDupI16Shuffle[i / 2] == -1)
9465 PostDupI16Shuffle[i / 2] = MappedMask;
9467 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
9468 "Conflicting entrties in the original shuffle!");
9470 return DAG.getBitcast(
9472 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9473 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9475 if (SDValue V = tryToWidenViaDuplication())
9479 if (SDValue Masked =
9480 lowerVectorShuffleAsBitMask(DL, MVT::v16i8, V1, V2, Mask, DAG))
9483 // Use dedicated unpack instructions for masks that match their pattern.
9484 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9485 0, 16, 1, 17, 2, 18, 3, 19,
9487 4, 20, 5, 21, 6, 22, 7, 23}))
9488 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9489 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9490 8, 24, 9, 25, 10, 26, 11, 27,
9492 12, 28, 13, 29, 14, 30, 15, 31}))
9493 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9495 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9496 // with PSHUFB. It is important to do this before we attempt to generate any
9497 // blends but after all of the single-input lowerings. If the single input
9498 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9499 // want to preserve that and we can DAG combine any longer sequences into
9500 // a PSHUFB in the end. But once we start blending from multiple inputs,
9501 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9502 // and there are *very* few patterns that would actually be faster than the
9503 // PSHUFB approach because of its ability to zero lanes.
9505 // FIXME: The only exceptions to the above are blends which are exact
9506 // interleavings with direct instructions supporting them. We currently don't
9507 // handle those well here.
9508 if (Subtarget->hasSSSE3()) {
9509 bool V1InUse = false;
9510 bool V2InUse = false;
9512 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9513 DAG, V1InUse, V2InUse);
9515 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9516 // do so. This avoids using them to handle blends-with-zero which is
9517 // important as a single pshufb is significantly faster for that.
9518 if (V1InUse && V2InUse) {
9519 if (Subtarget->hasSSE41())
9520 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9521 Mask, Subtarget, DAG))
9524 // We can use an unpack to do the blending rather than an or in some
9525 // cases. Even though the or may be (very minorly) more efficient, we
9526 // preference this lowering because there are common cases where part of
9527 // the complexity of the shuffles goes away when we do the final blend as
9529 // FIXME: It might be worth trying to detect if the unpack-feeding
9530 // shuffles will both be pshufb, in which case we shouldn't bother with
9532 if (SDValue Unpack = lowerVectorShuffleAsPermuteAndUnpack(
9533 DL, MVT::v16i8, V1, V2, Mask, DAG))
9540 // There are special ways we can lower some single-element blends.
9541 if (NumV2Elements == 1)
9542 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9543 Mask, Subtarget, DAG))
9546 if (SDValue BitBlend =
9547 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9550 // Check whether a compaction lowering can be done. This handles shuffles
9551 // which take every Nth element for some even N. See the helper function for
9554 // We special case these as they can be particularly efficiently handled with
9555 // the PACKUSB instruction on x86 and they show up in common patterns of
9556 // rearranging bytes to truncate wide elements.
9557 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9558 // NumEvenDrops is the power of two stride of the elements. Another way of
9559 // thinking about it is that we need to drop the even elements this many
9560 // times to get the original input.
9561 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9563 // First we need to zero all the dropped bytes.
9564 assert(NumEvenDrops <= 3 &&
9565 "No support for dropping even elements more than 3 times.");
9566 // We use the mask type to pick which bytes are preserved based on how many
9567 // elements are dropped.
9568 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9569 SDValue ByteClearMask = DAG.getBitcast(
9570 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9571 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9573 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9575 // Now pack things back together.
9576 V1 = DAG.getBitcast(MVT::v8i16, V1);
9577 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9578 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9579 for (int i = 1; i < NumEvenDrops; ++i) {
9580 Result = DAG.getBitcast(MVT::v8i16, Result);
9581 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9587 // Handle multi-input cases by blending single-input shuffles.
9588 if (NumV2Elements > 0)
9589 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9592 // The fallback path for single-input shuffles widens this into two v8i16
9593 // vectors with unpacks, shuffles those, and then pulls them back together
9597 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9598 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9599 for (int i = 0; i < 16; ++i)
9601 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9603 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9605 SDValue VLoHalf, VHiHalf;
9606 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9607 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9609 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9610 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9611 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9612 [](int M) { return M >= 0 && M % 2 == 1; })) {
9613 // Use a mask to drop the high bytes.
9614 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9615 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9616 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9618 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9619 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9621 // Squash the masks to point directly into VLoHalf.
9622 for (int &M : LoBlendMask)
9625 for (int &M : HiBlendMask)
9629 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9630 // VHiHalf so that we can blend them as i16s.
9631 VLoHalf = DAG.getBitcast(
9632 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9633 VHiHalf = DAG.getBitcast(
9634 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9637 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9638 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9640 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9643 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9645 /// This routine breaks down the specific type of 128-bit shuffle and
9646 /// dispatches to the lowering routines accordingly.
9647 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9648 MVT VT, const X86Subtarget *Subtarget,
9649 SelectionDAG &DAG) {
9650 switch (VT.SimpleTy) {
9652 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9654 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9656 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9658 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9660 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9662 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9665 llvm_unreachable("Unimplemented!");
9669 /// \brief Helper function to test whether a shuffle mask could be
9670 /// simplified by widening the elements being shuffled.
9672 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9673 /// leaves it in an unspecified state.
9675 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9676 /// shuffle masks. The latter have the special property of a '-2' representing
9677 /// a zero-ed lane of a vector.
9678 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9679 SmallVectorImpl<int> &WidenedMask) {
9680 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9681 // If both elements are undef, its trivial.
9682 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9683 WidenedMask.push_back(SM_SentinelUndef);
9687 // Check for an undef mask and a mask value properly aligned to fit with
9688 // a pair of values. If we find such a case, use the non-undef mask's value.
9689 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9690 WidenedMask.push_back(Mask[i + 1] / 2);
9693 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9694 WidenedMask.push_back(Mask[i] / 2);
9698 // When zeroing, we need to spread the zeroing across both lanes to widen.
9699 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9700 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9701 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9702 WidenedMask.push_back(SM_SentinelZero);
9708 // Finally check if the two mask values are adjacent and aligned with
9710 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9711 WidenedMask.push_back(Mask[i] / 2);
9715 // Otherwise we can't safely widen the elements used in this shuffle.
9718 assert(WidenedMask.size() == Mask.size() / 2 &&
9719 "Incorrect size of mask after widening the elements!");
9724 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9726 /// This routine just extracts two subvectors, shuffles them independently, and
9727 /// then concatenates them back together. This should work effectively with all
9728 /// AVX vector shuffle types.
9729 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9730 SDValue V2, ArrayRef<int> Mask,
9731 SelectionDAG &DAG) {
9732 assert(VT.getSizeInBits() >= 256 &&
9733 "Only for 256-bit or wider vector shuffles!");
9734 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9735 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9737 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9738 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9740 int NumElements = VT.getVectorNumElements();
9741 int SplitNumElements = NumElements / 2;
9742 MVT ScalarVT = VT.getScalarType();
9743 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9745 // Rather than splitting build-vectors, just build two narrower build
9746 // vectors. This helps shuffling with splats and zeros.
9747 auto SplitVector = [&](SDValue V) {
9748 while (V.getOpcode() == ISD::BITCAST)
9749 V = V->getOperand(0);
9751 MVT OrigVT = V.getSimpleValueType();
9752 int OrigNumElements = OrigVT.getVectorNumElements();
9753 int OrigSplitNumElements = OrigNumElements / 2;
9754 MVT OrigScalarVT = OrigVT.getScalarType();
9755 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9759 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9761 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9762 DAG.getIntPtrConstant(0, DL));
9763 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9764 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9767 SmallVector<SDValue, 16> LoOps, HiOps;
9768 for (int i = 0; i < OrigSplitNumElements; ++i) {
9769 LoOps.push_back(BV->getOperand(i));
9770 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9772 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9773 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9775 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9776 DAG.getBitcast(SplitVT, HiV));
9779 SDValue LoV1, HiV1, LoV2, HiV2;
9780 std::tie(LoV1, HiV1) = SplitVector(V1);
9781 std::tie(LoV2, HiV2) = SplitVector(V2);
9783 // Now create two 4-way blends of these half-width vectors.
9784 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9785 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9786 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9787 for (int i = 0; i < SplitNumElements; ++i) {
9788 int M = HalfMask[i];
9789 if (M >= NumElements) {
9790 if (M >= NumElements + SplitNumElements)
9794 V2BlendMask.push_back(M - NumElements);
9795 V1BlendMask.push_back(-1);
9796 BlendMask.push_back(SplitNumElements + i);
9797 } else if (M >= 0) {
9798 if (M >= SplitNumElements)
9802 V2BlendMask.push_back(-1);
9803 V1BlendMask.push_back(M);
9804 BlendMask.push_back(i);
9806 V2BlendMask.push_back(-1);
9807 V1BlendMask.push_back(-1);
9808 BlendMask.push_back(-1);
9812 // Because the lowering happens after all combining takes place, we need to
9813 // manually combine these blend masks as much as possible so that we create
9814 // a minimal number of high-level vector shuffle nodes.
9816 // First try just blending the halves of V1 or V2.
9817 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9818 return DAG.getUNDEF(SplitVT);
9819 if (!UseLoV2 && !UseHiV2)
9820 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9821 if (!UseLoV1 && !UseHiV1)
9822 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9824 SDValue V1Blend, V2Blend;
9825 if (UseLoV1 && UseHiV1) {
9827 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9829 // We only use half of V1 so map the usage down into the final blend mask.
9830 V1Blend = UseLoV1 ? LoV1 : HiV1;
9831 for (int i = 0; i < SplitNumElements; ++i)
9832 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9833 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9835 if (UseLoV2 && UseHiV2) {
9837 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9839 // We only use half of V2 so map the usage down into the final blend mask.
9840 V2Blend = UseLoV2 ? LoV2 : HiV2;
9841 for (int i = 0; i < SplitNumElements; ++i)
9842 if (BlendMask[i] >= SplitNumElements)
9843 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9845 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9847 SDValue Lo = HalfBlend(LoMask);
9848 SDValue Hi = HalfBlend(HiMask);
9849 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9852 /// \brief Either split a vector in halves or decompose the shuffles and the
9855 /// This is provided as a good fallback for many lowerings of non-single-input
9856 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9857 /// between splitting the shuffle into 128-bit components and stitching those
9858 /// back together vs. extracting the single-input shuffles and blending those
9860 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9861 SDValue V2, ArrayRef<int> Mask,
9862 SelectionDAG &DAG) {
9863 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9864 "lower single-input shuffles as it "
9865 "could then recurse on itself.");
9866 int Size = Mask.size();
9868 // If this can be modeled as a broadcast of two elements followed by a blend,
9869 // prefer that lowering. This is especially important because broadcasts can
9870 // often fold with memory operands.
9871 auto DoBothBroadcast = [&] {
9872 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9875 if (V2BroadcastIdx == -1)
9876 V2BroadcastIdx = M - Size;
9877 else if (M - Size != V2BroadcastIdx)
9879 } else if (M >= 0) {
9880 if (V1BroadcastIdx == -1)
9882 else if (M != V1BroadcastIdx)
9887 if (DoBothBroadcast())
9888 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9891 // If the inputs all stem from a single 128-bit lane of each input, then we
9892 // split them rather than blending because the split will decompose to
9893 // unusually few instructions.
9894 int LaneCount = VT.getSizeInBits() / 128;
9895 int LaneSize = Size / LaneCount;
9896 SmallBitVector LaneInputs[2];
9897 LaneInputs[0].resize(LaneCount, false);
9898 LaneInputs[1].resize(LaneCount, false);
9899 for (int i = 0; i < Size; ++i)
9901 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9902 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9903 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9905 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9906 // that the decomposed single-input shuffles don't end up here.
9907 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9910 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9911 /// a permutation and blend of those lanes.
9913 /// This essentially blends the out-of-lane inputs to each lane into the lane
9914 /// from a permuted copy of the vector. This lowering strategy results in four
9915 /// instructions in the worst case for a single-input cross lane shuffle which
9916 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9917 /// of. Special cases for each particular shuffle pattern should be handled
9918 /// prior to trying this lowering.
9919 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9920 SDValue V1, SDValue V2,
9922 SelectionDAG &DAG) {
9923 // FIXME: This should probably be generalized for 512-bit vectors as well.
9924 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9925 int LaneSize = Mask.size() / 2;
9927 // If there are only inputs from one 128-bit lane, splitting will in fact be
9928 // less expensive. The flags track whether the given lane contains an element
9929 // that crosses to another lane.
9930 bool LaneCrossing[2] = {false, false};
9931 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9932 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9933 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9934 if (!LaneCrossing[0] || !LaneCrossing[1])
9935 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9937 if (isSingleInputShuffleMask(Mask)) {
9938 SmallVector<int, 32> FlippedBlendMask;
9939 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9940 FlippedBlendMask.push_back(
9941 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9943 : Mask[i] % LaneSize +
9944 (i / LaneSize) * LaneSize + Size));
9946 // Flip the vector, and blend the results which should now be in-lane. The
9947 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9948 // 5 for the high source. The value 3 selects the high half of source 2 and
9949 // the value 2 selects the low half of source 2. We only use source 2 to
9950 // allow folding it into a memory operand.
9951 unsigned PERMMask = 3 | 2 << 4;
9952 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9953 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9954 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9957 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9958 // will be handled by the above logic and a blend of the results, much like
9959 // other patterns in AVX.
9960 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9963 /// \brief Handle lowering 2-lane 128-bit shuffles.
9964 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9965 SDValue V2, ArrayRef<int> Mask,
9966 const X86Subtarget *Subtarget,
9967 SelectionDAG &DAG) {
9968 // TODO: If minimizing size and one of the inputs is a zero vector and the
9969 // the zero vector has only one use, we could use a VPERM2X128 to save the
9970 // instruction bytes needed to explicitly generate the zero vector.
9972 // Blends are faster and handle all the non-lane-crossing cases.
9973 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9977 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9978 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9980 // If either input operand is a zero vector, use VPERM2X128 because its mask
9981 // allows us to replace the zero input with an implicit zero.
9982 if (!IsV1Zero && !IsV2Zero) {
9983 // Check for patterns which can be matched with a single insert of a 128-bit
9985 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9986 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9987 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9988 VT.getVectorNumElements() / 2);
9989 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9990 DAG.getIntPtrConstant(0, DL));
9991 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9992 OnlyUsesV1 ? V1 : V2,
9993 DAG.getIntPtrConstant(0, DL));
9994 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9998 // Otherwise form a 128-bit permutation. After accounting for undefs,
9999 // convert the 64-bit shuffle mask selection values into 128-bit
10000 // selection bits by dividing the indexes by 2 and shifting into positions
10001 // defined by a vperm2*128 instruction's immediate control byte.
10003 // The immediate permute control byte looks like this:
10004 // [1:0] - select 128 bits from sources for low half of destination
10006 // [3] - zero low half of destination
10007 // [5:4] - select 128 bits from sources for high half of destination
10009 // [7] - zero high half of destination
10011 int MaskLO = Mask[0];
10012 if (MaskLO == SM_SentinelUndef)
10013 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
10015 int MaskHI = Mask[2];
10016 if (MaskHI == SM_SentinelUndef)
10017 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
10019 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
10021 // If either input is a zero vector, replace it with an undef input.
10022 // Shuffle mask values < 4 are selecting elements of V1.
10023 // Shuffle mask values >= 4 are selecting elements of V2.
10024 // Adjust each half of the permute mask by clearing the half that was
10025 // selecting the zero vector and setting the zero mask bit.
10027 V1 = DAG.getUNDEF(VT);
10029 PermMask = (PermMask & 0xf0) | 0x08;
10031 PermMask = (PermMask & 0x0f) | 0x80;
10034 V2 = DAG.getUNDEF(VT);
10036 PermMask = (PermMask & 0xf0) | 0x08;
10038 PermMask = (PermMask & 0x0f) | 0x80;
10041 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
10042 DAG.getConstant(PermMask, DL, MVT::i8));
10045 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
10046 /// shuffling each lane.
10048 /// This will only succeed when the result of fixing the 128-bit lanes results
10049 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
10050 /// each 128-bit lanes. This handles many cases where we can quickly blend away
10051 /// the lane crosses early and then use simpler shuffles within each lane.
10053 /// FIXME: It might be worthwhile at some point to support this without
10054 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
10055 /// in x86 only floating point has interesting non-repeating shuffles, and even
10056 /// those are still *marginally* more expensive.
10057 static SDValue lowerVectorShuffleByMerging128BitLanes(
10058 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
10059 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
10060 assert(!isSingleInputShuffleMask(Mask) &&
10061 "This is only useful with multiple inputs.");
10063 int Size = Mask.size();
10064 int LaneSize = 128 / VT.getScalarSizeInBits();
10065 int NumLanes = Size / LaneSize;
10066 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
10068 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
10069 // check whether the in-128-bit lane shuffles share a repeating pattern.
10070 SmallVector<int, 4> Lanes;
10071 Lanes.resize(NumLanes, -1);
10072 SmallVector<int, 4> InLaneMask;
10073 InLaneMask.resize(LaneSize, -1);
10074 for (int i = 0; i < Size; ++i) {
10078 int j = i / LaneSize;
10080 if (Lanes[j] < 0) {
10081 // First entry we've seen for this lane.
10082 Lanes[j] = Mask[i] / LaneSize;
10083 } else if (Lanes[j] != Mask[i] / LaneSize) {
10084 // This doesn't match the lane selected previously!
10088 // Check that within each lane we have a consistent shuffle mask.
10089 int k = i % LaneSize;
10090 if (InLaneMask[k] < 0) {
10091 InLaneMask[k] = Mask[i] % LaneSize;
10092 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
10093 // This doesn't fit a repeating in-lane mask.
10098 // First shuffle the lanes into place.
10099 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
10100 VT.getSizeInBits() / 64);
10101 SmallVector<int, 8> LaneMask;
10102 LaneMask.resize(NumLanes * 2, -1);
10103 for (int i = 0; i < NumLanes; ++i)
10104 if (Lanes[i] >= 0) {
10105 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
10106 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
10109 V1 = DAG.getBitcast(LaneVT, V1);
10110 V2 = DAG.getBitcast(LaneVT, V2);
10111 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
10113 // Cast it back to the type we actually want.
10114 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
10116 // Now do a simple shuffle that isn't lane crossing.
10117 SmallVector<int, 8> NewMask;
10118 NewMask.resize(Size, -1);
10119 for (int i = 0; i < Size; ++i)
10121 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
10122 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
10123 "Must not introduce lane crosses at this point!");
10125 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
10128 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
10131 /// This returns true if the elements from a particular input are already in the
10132 /// slot required by the given mask and require no permutation.
10133 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
10134 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
10135 int Size = Mask.size();
10136 for (int i = 0; i < Size; ++i)
10137 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
10143 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
10144 ArrayRef<int> Mask, SDValue V1,
10145 SDValue V2, SelectionDAG &DAG) {
10147 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
10148 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
10149 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
10150 int NumElts = VT.getVectorNumElements();
10151 bool ShufpdMask = true;
10152 bool CommutableMask = true;
10153 unsigned Immediate = 0;
10154 for (int i = 0; i < NumElts; ++i) {
10157 int Val = (i & 6) + NumElts * (i & 1);
10158 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
10159 if (Mask[i] < Val || Mask[i] > Val + 1)
10160 ShufpdMask = false;
10161 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
10162 CommutableMask = false;
10163 Immediate |= (Mask[i] % 2) << i;
10166 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
10167 DAG.getConstant(Immediate, DL, MVT::i8));
10168 if (CommutableMask)
10169 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
10170 DAG.getConstant(Immediate, DL, MVT::i8));
10174 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
10176 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
10177 /// isn't available.
10178 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10179 const X86Subtarget *Subtarget,
10180 SelectionDAG &DAG) {
10182 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10183 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
10184 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10185 ArrayRef<int> Mask = SVOp->getMask();
10186 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10188 SmallVector<int, 4> WidenedMask;
10189 if (canWidenShuffleElements(Mask, WidenedMask))
10190 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
10193 if (isSingleInputShuffleMask(Mask)) {
10194 // Check for being able to broadcast a single element.
10195 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
10196 Mask, Subtarget, DAG))
10199 // Use low duplicate instructions for masks that match their pattern.
10200 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
10201 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
10203 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
10204 // Non-half-crossing single input shuffles can be lowerid with an
10205 // interleaved permutation.
10206 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
10207 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
10208 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
10209 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
10212 // With AVX2 we have direct support for this permutation.
10213 if (Subtarget->hasAVX2())
10214 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
10215 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10217 // Otherwise, fall back.
10218 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
10222 // X86 has dedicated unpack instructions that can handle specific blend
10223 // operations: UNPCKH and UNPCKL.
10224 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10225 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
10226 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10227 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
10228 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10229 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
10230 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10231 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
10233 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
10237 // Check if the blend happens to exactly fit that of SHUFPD.
10239 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
10242 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10243 // shuffle. However, if we have AVX2 and either inputs are already in place,
10244 // we will be able to shuffle even across lanes the other input in a single
10245 // instruction so skip this pattern.
10246 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10247 isShuffleMaskInputInPlace(1, Mask))))
10248 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10249 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
10252 // If we have AVX2 then we always want to lower with a blend because an v4 we
10253 // can fully permute the elements.
10254 if (Subtarget->hasAVX2())
10255 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
10258 // Otherwise fall back on generic lowering.
10259 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
10262 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
10264 /// This routine is only called when we have AVX2 and thus a reasonable
10265 /// instruction set for v4i64 shuffling..
10266 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10267 const X86Subtarget *Subtarget,
10268 SelectionDAG &DAG) {
10270 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10271 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
10272 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10273 ArrayRef<int> Mask = SVOp->getMask();
10274 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
10275 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
10277 SmallVector<int, 4> WidenedMask;
10278 if (canWidenShuffleElements(Mask, WidenedMask))
10279 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
10282 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
10286 // Check for being able to broadcast a single element.
10287 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
10288 Mask, Subtarget, DAG))
10291 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
10292 // use lower latency instructions that will operate on both 128-bit lanes.
10293 SmallVector<int, 2> RepeatedMask;
10294 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
10295 if (isSingleInputShuffleMask(Mask)) {
10296 int PSHUFDMask[] = {-1, -1, -1, -1};
10297 for (int i = 0; i < 2; ++i)
10298 if (RepeatedMask[i] >= 0) {
10299 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
10300 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
10302 return DAG.getBitcast(
10304 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
10305 DAG.getBitcast(MVT::v8i32, V1),
10306 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
10310 // AVX2 provides a direct instruction for permuting a single input across
10312 if (isSingleInputShuffleMask(Mask))
10313 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
10314 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
10316 // Try to use shift instructions.
10317 if (SDValue Shift =
10318 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
10321 // Use dedicated unpack instructions for masks that match their pattern.
10322 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
10323 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
10324 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
10325 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
10326 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
10327 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
10328 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
10329 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
10331 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10332 // shuffle. However, if we have AVX2 and either inputs are already in place,
10333 // we will be able to shuffle even across lanes the other input in a single
10334 // instruction so skip this pattern.
10335 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
10336 isShuffleMaskInputInPlace(1, Mask))))
10337 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10338 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
10341 // Otherwise fall back on generic blend lowering.
10342 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
10346 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
10348 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
10349 /// isn't available.
10350 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10351 const X86Subtarget *Subtarget,
10352 SelectionDAG &DAG) {
10354 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10355 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
10356 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10357 ArrayRef<int> Mask = SVOp->getMask();
10358 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10360 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
10364 // Check for being able to broadcast a single element.
10365 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
10366 Mask, Subtarget, DAG))
10369 // If the shuffle mask is repeated in each 128-bit lane, we have many more
10370 // options to efficiently lower the shuffle.
10371 SmallVector<int, 4> RepeatedMask;
10372 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
10373 assert(RepeatedMask.size() == 4 &&
10374 "Repeated masks must be half the mask width!");
10376 // Use even/odd duplicate instructions for masks that match their pattern.
10377 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
10378 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
10379 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
10380 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
10382 if (isSingleInputShuffleMask(Mask))
10383 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
10384 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10386 // Use dedicated unpack instructions for masks that match their pattern.
10387 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10388 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
10389 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10390 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
10391 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10392 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
10393 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10394 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
10396 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
10397 // have already handled any direct blends. We also need to squash the
10398 // repeated mask into a simulated v4f32 mask.
10399 for (int i = 0; i < 4; ++i)
10400 if (RepeatedMask[i] >= 8)
10401 RepeatedMask[i] -= 4;
10402 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
10405 // If we have a single input shuffle with different shuffle patterns in the
10406 // two 128-bit lanes use the variable mask to VPERMILPS.
10407 if (isSingleInputShuffleMask(Mask)) {
10408 SDValue VPermMask[8];
10409 for (int i = 0; i < 8; ++i)
10410 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10411 : DAG.getConstant(Mask[i], DL, MVT::i32);
10412 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
10413 return DAG.getNode(
10414 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
10415 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
10417 if (Subtarget->hasAVX2())
10418 return DAG.getNode(
10419 X86ISD::VPERMV, DL, MVT::v8f32,
10420 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
10421 MVT::v8i32, VPermMask)),
10424 // Otherwise, fall back.
10425 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
10429 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10431 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10432 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
10435 // If we have AVX2 then we always want to lower with a blend because at v8 we
10436 // can fully permute the elements.
10437 if (Subtarget->hasAVX2())
10438 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
10441 // Otherwise fall back on generic lowering.
10442 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
10445 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
10447 /// This routine is only called when we have AVX2 and thus a reasonable
10448 /// instruction set for v8i32 shuffling..
10449 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10450 const X86Subtarget *Subtarget,
10451 SelectionDAG &DAG) {
10453 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10454 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
10455 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10456 ArrayRef<int> Mask = SVOp->getMask();
10457 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10458 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
10460 // Whenever we can lower this as a zext, that instruction is strictly faster
10461 // than any alternative. It also allows us to fold memory operands into the
10462 // shuffle in many cases.
10463 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
10464 Mask, Subtarget, DAG))
10467 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
10471 // Check for being able to broadcast a single element.
10472 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
10473 Mask, Subtarget, DAG))
10476 // If the shuffle mask is repeated in each 128-bit lane we can use more
10477 // efficient instructions that mirror the shuffles across the two 128-bit
10479 SmallVector<int, 4> RepeatedMask;
10480 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10481 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10482 if (isSingleInputShuffleMask(Mask))
10483 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10484 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10486 // Use dedicated unpack instructions for masks that match their pattern.
10487 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10488 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10489 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10490 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10491 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10492 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10493 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10494 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10497 // Try to use shift instructions.
10498 if (SDValue Shift =
10499 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10502 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10503 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10506 // If the shuffle patterns aren't repeated but it is a single input, directly
10507 // generate a cross-lane VPERMD instruction.
10508 if (isSingleInputShuffleMask(Mask)) {
10509 SDValue VPermMask[8];
10510 for (int i = 0; i < 8; ++i)
10511 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10512 : DAG.getConstant(Mask[i], DL, MVT::i32);
10513 return DAG.getNode(
10514 X86ISD::VPERMV, DL, MVT::v8i32,
10515 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10518 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10520 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10521 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10524 // Otherwise fall back on generic blend lowering.
10525 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10529 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10531 /// This routine is only called when we have AVX2 and thus a reasonable
10532 /// instruction set for v16i16 shuffling..
10533 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10534 const X86Subtarget *Subtarget,
10535 SelectionDAG &DAG) {
10537 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10538 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10539 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10540 ArrayRef<int> Mask = SVOp->getMask();
10541 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10542 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10544 // Whenever we can lower this as a zext, that instruction is strictly faster
10545 // than any alternative. It also allows us to fold memory operands into the
10546 // shuffle in many cases.
10547 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10548 Mask, Subtarget, DAG))
10551 // Check for being able to broadcast a single element.
10552 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10553 Mask, Subtarget, DAG))
10556 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10560 // Use dedicated unpack instructions for masks that match their pattern.
10561 if (isShuffleEquivalent(V1, V2, Mask,
10562 {// First 128-bit lane:
10563 0, 16, 1, 17, 2, 18, 3, 19,
10564 // Second 128-bit lane:
10565 8, 24, 9, 25, 10, 26, 11, 27}))
10566 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10567 if (isShuffleEquivalent(V1, V2, Mask,
10568 {// First 128-bit lane:
10569 4, 20, 5, 21, 6, 22, 7, 23,
10570 // Second 128-bit lane:
10571 12, 28, 13, 29, 14, 30, 15, 31}))
10572 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10574 // Try to use shift instructions.
10575 if (SDValue Shift =
10576 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10579 // Try to use byte rotation instructions.
10580 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10581 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10584 if (isSingleInputShuffleMask(Mask)) {
10585 // There are no generalized cross-lane shuffle operations available on i16
10587 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10588 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10591 SmallVector<int, 8> RepeatedMask;
10592 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10593 // As this is a single-input shuffle, the repeated mask should be
10594 // a strictly valid v8i16 mask that we can pass through to the v8i16
10595 // lowering to handle even the v16 case.
10596 return lowerV8I16GeneralSingleInputVectorShuffle(
10597 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10600 SDValue PSHUFBMask[32];
10601 for (int i = 0; i < 16; ++i) {
10602 if (Mask[i] == -1) {
10603 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10607 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10608 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10609 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10610 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10612 return DAG.getBitcast(MVT::v16i16,
10613 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10614 DAG.getBitcast(MVT::v32i8, V1),
10615 DAG.getNode(ISD::BUILD_VECTOR, DL,
10616 MVT::v32i8, PSHUFBMask)));
10619 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10621 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10622 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10625 // Otherwise fall back on generic lowering.
10626 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10629 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10631 /// This routine is only called when we have AVX2 and thus a reasonable
10632 /// instruction set for v32i8 shuffling..
10633 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10634 const X86Subtarget *Subtarget,
10635 SelectionDAG &DAG) {
10637 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10638 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10639 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10640 ArrayRef<int> Mask = SVOp->getMask();
10641 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10642 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10644 // Whenever we can lower this as a zext, that instruction is strictly faster
10645 // than any alternative. It also allows us to fold memory operands into the
10646 // shuffle in many cases.
10647 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10648 Mask, Subtarget, DAG))
10651 // Check for being able to broadcast a single element.
10652 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10653 Mask, Subtarget, DAG))
10656 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10660 // Use dedicated unpack instructions for masks that match their pattern.
10661 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10663 if (isShuffleEquivalent(
10665 {// First 128-bit lane:
10666 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10667 // Second 128-bit lane:
10668 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10669 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10670 if (isShuffleEquivalent(
10672 {// First 128-bit lane:
10673 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10674 // Second 128-bit lane:
10675 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10676 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10678 // Try to use shift instructions.
10679 if (SDValue Shift =
10680 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10683 // Try to use byte rotation instructions.
10684 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10685 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10688 if (isSingleInputShuffleMask(Mask)) {
10689 // There are no generalized cross-lane shuffle operations available on i8
10691 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10692 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10695 SDValue PSHUFBMask[32];
10696 for (int i = 0; i < 32; ++i)
10699 ? DAG.getUNDEF(MVT::i8)
10700 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10703 return DAG.getNode(
10704 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10705 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10708 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10710 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10711 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10714 // Otherwise fall back on generic lowering.
10715 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10718 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10720 /// This routine either breaks down the specific type of a 256-bit x86 vector
10721 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10722 /// together based on the available instructions.
10723 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10724 MVT VT, const X86Subtarget *Subtarget,
10725 SelectionDAG &DAG) {
10727 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10728 ArrayRef<int> Mask = SVOp->getMask();
10730 // If we have a single input to the zero element, insert that into V1 if we
10731 // can do so cheaply.
10732 int NumElts = VT.getVectorNumElements();
10733 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10734 return M >= NumElts;
10737 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10738 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10739 DL, VT, V1, V2, Mask, Subtarget, DAG))
10742 // There is a really nice hard cut-over between AVX1 and AVX2 that means we
10743 // can check for those subtargets here and avoid much of the subtarget
10744 // querying in the per-vector-type lowering routines. With AVX1 we have
10745 // essentially *zero* ability to manipulate a 256-bit vector with integer
10746 // types. Since we'll use floating point types there eventually, just
10747 // immediately cast everything to a float and operate entirely in that domain.
10748 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10749 int ElementBits = VT.getScalarSizeInBits();
10750 if (ElementBits < 32)
10751 // No floating point type available, decompose into 128-bit vectors.
10752 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10754 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10755 VT.getVectorNumElements());
10756 V1 = DAG.getBitcast(FpVT, V1);
10757 V2 = DAG.getBitcast(FpVT, V2);
10758 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10761 switch (VT.SimpleTy) {
10763 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10765 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10767 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10769 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10771 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10773 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10776 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10780 /// \brief Try to lower a vector shuffle as a 128-bit shuffles.
10781 static SDValue lowerV4X128VectorShuffle(SDLoc DL, MVT VT,
10782 ArrayRef<int> Mask,
10783 SDValue V1, SDValue V2,
10784 SelectionDAG &DAG) {
10785 assert(VT.getScalarSizeInBits() == 64 &&
10786 "Unexpected element type size for 128bit shuffle.");
10788 // To handle 256 bit vector requires VLX and most probably
10789 // function lowerV2X128VectorShuffle() is better solution.
10790 assert(VT.getSizeInBits() == 512 &&
10791 "Unexpected vector size for 128bit shuffle.");
10793 SmallVector<int, 4> WidenedMask;
10794 if (!canWidenShuffleElements(Mask, WidenedMask))
10797 // Form a 128-bit permutation.
10798 // Convert the 64-bit shuffle mask selection values into 128-bit selection
10799 // bits defined by a vshuf64x2 instruction's immediate control byte.
10800 unsigned PermMask = 0, Imm = 0;
10801 unsigned ControlBitsNum = WidenedMask.size() / 2;
10803 for (int i = 0, Size = WidenedMask.size(); i < Size; ++i) {
10804 if (WidenedMask[i] == SM_SentinelZero)
10807 // Use first element in place of undef mask.
10808 Imm = (WidenedMask[i] == SM_SentinelUndef) ? 0 : WidenedMask[i];
10809 PermMask |= (Imm % WidenedMask.size()) << (i * ControlBitsNum);
10812 return DAG.getNode(X86ISD::SHUF128, DL, VT, V1, V2,
10813 DAG.getConstant(PermMask, DL, MVT::i8));
10816 static SDValue lowerVectorShuffleWithPERMV(SDLoc DL, MVT VT,
10817 ArrayRef<int> Mask, SDValue V1,
10818 SDValue V2, SelectionDAG &DAG) {
10820 assert(VT.getScalarSizeInBits() >= 16 && "Unexpected data type for PERMV");
10822 MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
10823 MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
10825 SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
10826 if (isSingleInputShuffleMask(Mask))
10827 return DAG.getNode(X86ISD::VPERMV, DL, VT, MaskNode, V1);
10829 return DAG.getNode(X86ISD::VPERMV3, DL, VT, V1, MaskNode, V2);
10832 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10833 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10834 const X86Subtarget *Subtarget,
10835 SelectionDAG &DAG) {
10837 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10838 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10839 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10840 ArrayRef<int> Mask = SVOp->getMask();
10841 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10843 if (SDValue Shuf128 =
10844 lowerV4X128VectorShuffle(DL, MVT::v8f64, Mask, V1, V2, DAG))
10847 if (SDValue Unpck =
10848 lowerVectorShuffleWithUNPCK(DL, MVT::v8f64, Mask, V1, V2, DAG))
10851 return lowerVectorShuffleWithPERMV(DL, MVT::v8f64, Mask, V1, V2, DAG);
10854 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10855 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10856 const X86Subtarget *Subtarget,
10857 SelectionDAG &DAG) {
10859 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10860 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10861 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10862 ArrayRef<int> Mask = SVOp->getMask();
10863 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10865 if (SDValue Unpck =
10866 lowerVectorShuffleWithUNPCK(DL, MVT::v16f32, Mask, V1, V2, DAG))
10869 return lowerVectorShuffleWithPERMV(DL, MVT::v16f32, Mask, V1, V2, DAG);
10872 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10873 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10874 const X86Subtarget *Subtarget,
10875 SelectionDAG &DAG) {
10877 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10878 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10879 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10880 ArrayRef<int> Mask = SVOp->getMask();
10881 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10883 if (SDValue Shuf128 =
10884 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
10887 if (SDValue Unpck =
10888 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
10891 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
10894 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10895 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10896 const X86Subtarget *Subtarget,
10897 SelectionDAG &DAG) {
10899 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10900 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10901 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10902 ArrayRef<int> Mask = SVOp->getMask();
10903 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10905 if (SDValue Unpck =
10906 lowerVectorShuffleWithUNPCK(DL, MVT::v16i32, Mask, V1, V2, DAG))
10909 return lowerVectorShuffleWithPERMV(DL, MVT::v16i32, Mask, V1, V2, DAG);
10912 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10913 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10914 const X86Subtarget *Subtarget,
10915 SelectionDAG &DAG) {
10917 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10918 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10919 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10920 ArrayRef<int> Mask = SVOp->getMask();
10921 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10922 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10924 return lowerVectorShuffleWithPERMV(DL, MVT::v32i16, Mask, V1, V2, DAG);
10927 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10928 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10929 const X86Subtarget *Subtarget,
10930 SelectionDAG &DAG) {
10932 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10933 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10934 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10935 ArrayRef<int> Mask = SVOp->getMask();
10936 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10937 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10939 // FIXME: Implement direct support for this type!
10940 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10943 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10945 /// This routine either breaks down the specific type of a 512-bit x86 vector
10946 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10947 /// together based on the available instructions.
10948 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10949 MVT VT, const X86Subtarget *Subtarget,
10950 SelectionDAG &DAG) {
10952 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10953 ArrayRef<int> Mask = SVOp->getMask();
10954 assert(Subtarget->hasAVX512() &&
10955 "Cannot lower 512-bit vectors w/ basic ISA!");
10957 // Check for being able to broadcast a single element.
10958 if (SDValue Broadcast =
10959 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10962 // Dispatch to each element type for lowering. If we don't have supprot for
10963 // specific element type shuffles at 512 bits, immediately split them and
10964 // lower them. Each lowering routine of a given type is allowed to assume that
10965 // the requisite ISA extensions for that element type are available.
10966 switch (VT.SimpleTy) {
10968 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10970 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10972 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10974 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10976 if (Subtarget->hasBWI())
10977 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10980 if (Subtarget->hasBWI())
10981 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10985 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10988 // Otherwise fall back on splitting.
10989 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10992 // Lower vXi1 vector shuffles.
10993 // There is no a dedicated instruction on AVX-512 that shuffles the masks.
10994 // The only way to shuffle bits is to sign-extend the mask vector to SIMD
10995 // vector, shuffle and then truncate it back.
10996 static SDValue lower1BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10997 MVT VT, const X86Subtarget *Subtarget,
10998 SelectionDAG &DAG) {
11000 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11001 ArrayRef<int> Mask = SVOp->getMask();
11002 assert(Subtarget->hasAVX512() &&
11003 "Cannot lower 512-bit vectors w/o basic ISA!");
11005 switch (VT.SimpleTy) {
11007 assert(false && "Expected a vector of i1 elements");
11010 ExtVT = MVT::v2i64;
11013 ExtVT = MVT::v4i32;
11016 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11019 ExtVT = MVT::v16i32;
11022 ExtVT = MVT::v32i16;
11025 ExtVT = MVT::v64i8;
11029 if (ISD::isBuildVectorAllZeros(V1.getNode()))
11030 V1 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11031 else if (ISD::isBuildVectorAllOnes(V1.getNode()))
11032 V1 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11034 V1 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V1);
11037 V2 = DAG.getUNDEF(ExtVT);
11038 else if (ISD::isBuildVectorAllZeros(V2.getNode()))
11039 V2 = getZeroVector(ExtVT, Subtarget, DAG, DL);
11040 else if (ISD::isBuildVectorAllOnes(V2.getNode()))
11041 V2 = getOnesVector(ExtVT, Subtarget, DAG, DL);
11043 V2 = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, V2);
11044 return DAG.getNode(ISD::TRUNCATE, DL, VT,
11045 DAG.getVectorShuffle(ExtVT, DL, V1, V2, Mask));
11047 /// \brief Top-level lowering for x86 vector shuffles.
11049 /// This handles decomposition, canonicalization, and lowering of all x86
11050 /// vector shuffles. Most of the specific lowering strategies are encapsulated
11051 /// above in helper routines. The canonicalization attempts to widen shuffles
11052 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
11053 /// s.t. only one of the two inputs needs to be tested, etc.
11054 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
11055 SelectionDAG &DAG) {
11056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
11057 ArrayRef<int> Mask = SVOp->getMask();
11058 SDValue V1 = Op.getOperand(0);
11059 SDValue V2 = Op.getOperand(1);
11060 MVT VT = Op.getSimpleValueType();
11061 int NumElements = VT.getVectorNumElements();
11063 bool Is1BitVector = (VT.getScalarType() == MVT::i1);
11065 assert((VT.getSizeInBits() != 64 || Is1BitVector) &&
11066 "Can't lower MMX shuffles");
11068 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
11069 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
11070 if (V1IsUndef && V2IsUndef)
11071 return DAG.getUNDEF(VT);
11073 // When we create a shuffle node we put the UNDEF node to second operand,
11074 // but in some cases the first operand may be transformed to UNDEF.
11075 // In this case we should just commute the node.
11077 return DAG.getCommutedVectorShuffle(*SVOp);
11079 // Check for non-undef masks pointing at an undef vector and make the masks
11080 // undef as well. This makes it easier to match the shuffle based solely on
11084 if (M >= NumElements) {
11085 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
11086 for (int &M : NewMask)
11087 if (M >= NumElements)
11089 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
11092 // We actually see shuffles that are entirely re-arrangements of a set of
11093 // zero inputs. This mostly happens while decomposing complex shuffles into
11094 // simple ones. Directly lower these as a buildvector of zeros.
11095 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
11096 if (Zeroable.all())
11097 return getZeroVector(VT, Subtarget, DAG, dl);
11099 // Try to collapse shuffles into using a vector type with fewer elements but
11100 // wider element types. We cap this to not form integers or floating point
11101 // elements wider than 64 bits, but it might be interesting to form i128
11102 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
11103 SmallVector<int, 16> WidenedMask;
11104 if (VT.getScalarSizeInBits() < 64 && !Is1BitVector &&
11105 canWidenShuffleElements(Mask, WidenedMask)) {
11106 MVT NewEltVT = VT.isFloatingPoint()
11107 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
11108 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
11109 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
11110 // Make sure that the new vector type is legal. For example, v2f64 isn't
11112 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
11113 V1 = DAG.getBitcast(NewVT, V1);
11114 V2 = DAG.getBitcast(NewVT, V2);
11115 return DAG.getBitcast(
11116 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
11120 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
11121 for (int M : SVOp->getMask())
11123 ++NumUndefElements;
11124 else if (M < NumElements)
11129 // Commute the shuffle as needed such that more elements come from V1 than
11130 // V2. This allows us to match the shuffle pattern strictly on how many
11131 // elements come from V1 without handling the symmetric cases.
11132 if (NumV2Elements > NumV1Elements)
11133 return DAG.getCommutedVectorShuffle(*SVOp);
11135 // When the number of V1 and V2 elements are the same, try to minimize the
11136 // number of uses of V2 in the low half of the vector. When that is tied,
11137 // ensure that the sum of indices for V1 is equal to or lower than the sum
11138 // indices for V2. When those are equal, try to ensure that the number of odd
11139 // indices for V1 is lower than the number of odd indices for V2.
11140 if (NumV1Elements == NumV2Elements) {
11141 int LowV1Elements = 0, LowV2Elements = 0;
11142 for (int M : SVOp->getMask().slice(0, NumElements / 2))
11143 if (M >= NumElements)
11147 if (LowV2Elements > LowV1Elements) {
11148 return DAG.getCommutedVectorShuffle(*SVOp);
11149 } else if (LowV2Elements == LowV1Elements) {
11150 int SumV1Indices = 0, SumV2Indices = 0;
11151 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11152 if (SVOp->getMask()[i] >= NumElements)
11154 else if (SVOp->getMask()[i] >= 0)
11156 if (SumV2Indices < SumV1Indices) {
11157 return DAG.getCommutedVectorShuffle(*SVOp);
11158 } else if (SumV2Indices == SumV1Indices) {
11159 int NumV1OddIndices = 0, NumV2OddIndices = 0;
11160 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
11161 if (SVOp->getMask()[i] >= NumElements)
11162 NumV2OddIndices += i % 2;
11163 else if (SVOp->getMask()[i] >= 0)
11164 NumV1OddIndices += i % 2;
11165 if (NumV2OddIndices < NumV1OddIndices)
11166 return DAG.getCommutedVectorShuffle(*SVOp);
11171 // For each vector width, delegate to a specialized lowering routine.
11172 if (VT.getSizeInBits() == 128)
11173 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11175 if (VT.getSizeInBits() == 256)
11176 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11178 if (VT.getSizeInBits() == 512)
11179 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11182 return lower1BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
11183 llvm_unreachable("Unimplemented!");
11186 // This function assumes its argument is a BUILD_VECTOR of constants or
11187 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
11189 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
11190 unsigned &MaskValue) {
11192 unsigned NumElems = BuildVector->getNumOperands();
11194 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
11195 // We don't handle the >2 lanes case right now.
11196 unsigned NumLanes = (NumElems - 1) / 8 + 1;
11200 unsigned NumElemsInLane = NumElems / NumLanes;
11202 // Blend for v16i16 should be symmetric for the both lanes.
11203 for (unsigned i = 0; i < NumElemsInLane; ++i) {
11204 SDValue EltCond = BuildVector->getOperand(i);
11205 SDValue SndLaneEltCond =
11206 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
11208 int Lane1Cond = -1, Lane2Cond = -1;
11209 if (isa<ConstantSDNode>(EltCond))
11210 Lane1Cond = !isZero(EltCond);
11211 if (isa<ConstantSDNode>(SndLaneEltCond))
11212 Lane2Cond = !isZero(SndLaneEltCond);
11214 unsigned LaneMask = 0;
11215 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
11216 // Lane1Cond != 0, means we want the first argument.
11217 // Lane1Cond == 0, means we want the second argument.
11218 // The encoding of this argument is 0 for the first argument, 1
11219 // for the second. Therefore, invert the condition.
11220 LaneMask = !Lane1Cond << i;
11221 else if (Lane1Cond < 0)
11222 LaneMask = !Lane2Cond << i;
11226 MaskValue |= LaneMask;
11228 MaskValue |= LaneMask << NumElemsInLane;
11233 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
11234 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
11235 const X86Subtarget *Subtarget,
11236 SelectionDAG &DAG) {
11237 SDValue Cond = Op.getOperand(0);
11238 SDValue LHS = Op.getOperand(1);
11239 SDValue RHS = Op.getOperand(2);
11241 MVT VT = Op.getSimpleValueType();
11243 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
11245 auto *CondBV = cast<BuildVectorSDNode>(Cond);
11247 // Only non-legal VSELECTs reach this lowering, convert those into generic
11248 // shuffles and re-use the shuffle lowering path for blends.
11249 SmallVector<int, 32> Mask;
11250 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
11251 SDValue CondElt = CondBV->getOperand(i);
11253 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
11255 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
11258 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
11259 // A vselect where all conditions and data are constants can be optimized into
11260 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
11261 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
11262 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
11263 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
11266 // Try to lower this to a blend-style vector shuffle. This can handle all
11267 // constant condition cases.
11268 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
11271 // Variable blends are only legal from SSE4.1 onward.
11272 if (!Subtarget->hasSSE41())
11275 // Only some types will be legal on some subtargets. If we can emit a legal
11276 // VSELECT-matching blend, return Op, and but if we need to expand, return
11278 switch (Op.getSimpleValueType().SimpleTy) {
11280 // Most of the vector types have blends past SSE4.1.
11284 // The byte blends for AVX vectors were introduced only in AVX2.
11285 if (Subtarget->hasAVX2())
11292 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
11293 if (Subtarget->hasBWI() && Subtarget->hasVLX())
11296 // FIXME: We should custom lower this by fixing the condition and using i8
11302 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
11303 MVT VT = Op.getSimpleValueType();
11306 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
11309 if (VT.getSizeInBits() == 8) {
11310 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
11311 Op.getOperand(0), Op.getOperand(1));
11312 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11313 DAG.getValueType(VT));
11314 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11317 if (VT.getSizeInBits() == 16) {
11318 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11319 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
11321 return DAG.getNode(
11322 ISD::TRUNCATE, dl, MVT::i16,
11323 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11324 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11325 Op.getOperand(1)));
11326 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
11327 Op.getOperand(0), Op.getOperand(1));
11328 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
11329 DAG.getValueType(VT));
11330 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11333 if (VT == MVT::f32) {
11334 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
11335 // the result back to FR32 register. It's only worth matching if the
11336 // result has a single use which is a store or a bitcast to i32. And in
11337 // the case of a store, it's not worth it if the index is a constant 0,
11338 // because a MOVSSmr can be used instead, which is smaller and faster.
11339 if (!Op.hasOneUse())
11341 SDNode *User = *Op.getNode()->use_begin();
11342 if ((User->getOpcode() != ISD::STORE ||
11343 (isa<ConstantSDNode>(Op.getOperand(1)) &&
11344 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
11345 (User->getOpcode() != ISD::BITCAST ||
11346 User->getValueType(0) != MVT::i32))
11348 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11349 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
11351 return DAG.getBitcast(MVT::f32, Extract);
11354 if (VT == MVT::i32 || VT == MVT::i64) {
11355 // ExtractPS/pextrq works with constant index.
11356 if (isa<ConstantSDNode>(Op.getOperand(1)))
11362 /// Extract one bit from mask vector, like v16i1 or v8i1.
11363 /// AVX-512 feature.
11365 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
11366 SDValue Vec = Op.getOperand(0);
11368 MVT VecVT = Vec.getSimpleValueType();
11369 SDValue Idx = Op.getOperand(1);
11370 MVT EltVT = Op.getSimpleValueType();
11372 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
11373 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
11374 "Unexpected vector type in ExtractBitFromMaskVector");
11376 // variable index can't be handled in mask registers,
11377 // extend vector to VR512
11378 if (!isa<ConstantSDNode>(Idx)) {
11379 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11380 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
11381 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
11382 ExtVT.getVectorElementType(), Ext, Idx);
11383 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
11386 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11387 const TargetRegisterClass* rc = getRegClassFor(VecVT);
11388 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
11389 rc = getRegClassFor(MVT::v16i1);
11390 unsigned MaxSift = rc->getSize()*8 - 1;
11391 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
11392 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
11393 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
11394 DAG.getConstant(MaxSift, dl, MVT::i8));
11395 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
11396 DAG.getIntPtrConstant(0, dl));
11400 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
11401 SelectionDAG &DAG) const {
11403 SDValue Vec = Op.getOperand(0);
11404 MVT VecVT = Vec.getSimpleValueType();
11405 SDValue Idx = Op.getOperand(1);
11407 if (Op.getSimpleValueType() == MVT::i1)
11408 return ExtractBitFromMaskVector(Op, DAG);
11410 if (!isa<ConstantSDNode>(Idx)) {
11411 if (VecVT.is512BitVector() ||
11412 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
11413 VecVT.getVectorElementType().getSizeInBits() == 32)) {
11416 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
11417 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
11418 MaskEltVT.getSizeInBits());
11420 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
11421 auto PtrVT = getPointerTy(DAG.getDataLayout());
11422 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
11423 getZeroVector(MaskVT, Subtarget, DAG, dl), Idx,
11424 DAG.getConstant(0, dl, PtrVT));
11425 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
11426 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Perm,
11427 DAG.getConstant(0, dl, PtrVT));
11432 // If this is a 256-bit vector result, first extract the 128-bit vector and
11433 // then extract the element from the 128-bit vector.
11434 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
11436 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11437 // Get the 128-bit vector.
11438 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
11439 MVT EltVT = VecVT.getVectorElementType();
11441 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
11443 //if (IdxVal >= NumElems/2)
11444 // IdxVal -= NumElems/2;
11445 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
11446 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
11447 DAG.getConstant(IdxVal, dl, MVT::i32));
11450 assert(VecVT.is128BitVector() && "Unexpected vector length");
11452 if (Subtarget->hasSSE41())
11453 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
11456 MVT VT = Op.getSimpleValueType();
11457 // TODO: handle v16i8.
11458 if (VT.getSizeInBits() == 16) {
11459 SDValue Vec = Op.getOperand(0);
11460 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11462 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
11463 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
11464 DAG.getBitcast(MVT::v4i32, Vec),
11465 Op.getOperand(1)));
11466 // Transform it so it match pextrw which produces a 32-bit result.
11467 MVT EltVT = MVT::i32;
11468 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
11469 Op.getOperand(0), Op.getOperand(1));
11470 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
11471 DAG.getValueType(VT));
11472 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
11475 if (VT.getSizeInBits() == 32) {
11476 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11480 // SHUFPS the element to the lowest double word, then movss.
11481 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
11482 MVT VVT = Op.getOperand(0).getSimpleValueType();
11483 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11484 DAG.getUNDEF(VVT), Mask);
11485 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11486 DAG.getIntPtrConstant(0, dl));
11489 if (VT.getSizeInBits() == 64) {
11490 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
11491 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
11492 // to match extract_elt for f64.
11493 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
11497 // UNPCKHPD the element to the lowest double word, then movsd.
11498 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
11499 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
11500 int Mask[2] = { 1, -1 };
11501 MVT VVT = Op.getOperand(0).getSimpleValueType();
11502 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
11503 DAG.getUNDEF(VVT), Mask);
11504 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
11505 DAG.getIntPtrConstant(0, dl));
11511 /// Insert one bit to mask vector, like v16i1 or v8i1.
11512 /// AVX-512 feature.
11514 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
11516 SDValue Vec = Op.getOperand(0);
11517 SDValue Elt = Op.getOperand(1);
11518 SDValue Idx = Op.getOperand(2);
11519 MVT VecVT = Vec.getSimpleValueType();
11521 if (!isa<ConstantSDNode>(Idx)) {
11522 // Non constant index. Extend source and destination,
11523 // insert element and then truncate the result.
11524 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11525 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
11526 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
11527 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
11528 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
11529 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
11532 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11533 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
11535 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
11536 DAG.getConstant(IdxVal, dl, MVT::i8));
11537 if (Vec.getOpcode() == ISD::UNDEF)
11539 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
11542 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
11543 SelectionDAG &DAG) const {
11544 MVT VT = Op.getSimpleValueType();
11545 MVT EltVT = VT.getVectorElementType();
11547 if (EltVT == MVT::i1)
11548 return InsertBitToMaskVector(Op, DAG);
11551 SDValue N0 = Op.getOperand(0);
11552 SDValue N1 = Op.getOperand(1);
11553 SDValue N2 = Op.getOperand(2);
11554 if (!isa<ConstantSDNode>(N2))
11556 auto *N2C = cast<ConstantSDNode>(N2);
11557 unsigned IdxVal = N2C->getZExtValue();
11559 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
11560 // into that, and then insert the subvector back into the result.
11561 if (VT.is256BitVector() || VT.is512BitVector()) {
11562 // With a 256-bit vector, we can insert into the zero element efficiently
11563 // using a blend if we have AVX or AVX2 and the right data type.
11564 if (VT.is256BitVector() && IdxVal == 0) {
11565 // TODO: It is worthwhile to cast integer to floating point and back
11566 // and incur a domain crossing penalty if that's what we'll end up
11567 // doing anyway after extracting to a 128-bit vector.
11568 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
11569 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
11570 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11571 N2 = DAG.getIntPtrConstant(1, dl);
11572 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11576 // Get the desired 128-bit vector chunk.
11577 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11579 // Insert the element into the desired chunk.
11580 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11581 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11583 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11584 DAG.getConstant(IdxIn128, dl, MVT::i32));
11586 // Insert the changed part back into the bigger vector
11587 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11589 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11591 if (Subtarget->hasSSE41()) {
11592 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11594 if (VT == MVT::v8i16) {
11595 Opc = X86ISD::PINSRW;
11597 assert(VT == MVT::v16i8);
11598 Opc = X86ISD::PINSRB;
11601 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11603 if (N1.getValueType() != MVT::i32)
11604 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11605 if (N2.getValueType() != MVT::i32)
11606 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11607 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11610 if (EltVT == MVT::f32) {
11611 // Bits [7:6] of the constant are the source select. This will always be
11612 // zero here. The DAG Combiner may combine an extract_elt index into
11613 // these bits. For example (insert (extract, 3), 2) could be matched by
11614 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11615 // Bits [5:4] of the constant are the destination select. This is the
11616 // value of the incoming immediate.
11617 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11618 // combine either bitwise AND or insert of float 0.0 to set these bits.
11620 bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize();
11621 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11622 // If this is an insertion of 32-bits into the low 32-bits of
11623 // a vector, we prefer to generate a blend with immediate rather
11624 // than an insertps. Blends are simpler operations in hardware and so
11625 // will always have equal or better performance than insertps.
11626 // But if optimizing for size and there's a load folding opportunity,
11627 // generate insertps because blendps does not have a 32-bit memory
11629 N2 = DAG.getIntPtrConstant(1, dl);
11630 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11631 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11633 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11634 // Create this as a scalar to vector..
11635 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11636 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11639 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11640 // PINSR* works with constant index.
11645 if (EltVT == MVT::i8)
11648 if (EltVT.getSizeInBits() == 16) {
11649 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11650 // as its second argument.
11651 if (N1.getValueType() != MVT::i32)
11652 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11653 if (N2.getValueType() != MVT::i32)
11654 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11655 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11660 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11662 MVT OpVT = Op.getSimpleValueType();
11664 // If this is a 256-bit vector result, first insert into a 128-bit
11665 // vector and then insert into the 256-bit vector.
11666 if (!OpVT.is128BitVector()) {
11667 // Insert into a 128-bit vector.
11668 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11669 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11670 OpVT.getVectorNumElements() / SizeFactor);
11672 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11674 // Insert the 128-bit vector.
11675 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11678 if (OpVT == MVT::v1i64 &&
11679 Op.getOperand(0).getValueType() == MVT::i64)
11680 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11682 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11683 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11684 return DAG.getBitcast(
11685 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11688 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11689 // a simple subregister reference or explicit instructions to grab
11690 // upper bits of a vector.
11691 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11692 SelectionDAG &DAG) {
11694 SDValue In = Op.getOperand(0);
11695 SDValue Idx = Op.getOperand(1);
11696 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11697 MVT ResVT = Op.getSimpleValueType();
11698 MVT InVT = In.getSimpleValueType();
11700 if (Subtarget->hasFp256()) {
11701 if (ResVT.is128BitVector() &&
11702 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11703 isa<ConstantSDNode>(Idx)) {
11704 return Extract128BitVector(In, IdxVal, DAG, dl);
11706 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11707 isa<ConstantSDNode>(Idx)) {
11708 return Extract256BitVector(In, IdxVal, DAG, dl);
11714 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11715 // simple superregister reference or explicit instructions to insert
11716 // the upper bits of a vector.
11717 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11718 SelectionDAG &DAG) {
11719 if (!Subtarget->hasAVX())
11723 SDValue Vec = Op.getOperand(0);
11724 SDValue SubVec = Op.getOperand(1);
11725 SDValue Idx = Op.getOperand(2);
11727 if (!isa<ConstantSDNode>(Idx))
11730 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11731 MVT OpVT = Op.getSimpleValueType();
11732 MVT SubVecVT = SubVec.getSimpleValueType();
11734 // Fold two 16-byte subvector loads into one 32-byte load:
11735 // (insert_subvector (insert_subvector undef, (load addr), 0),
11736 // (load addr + 16), Elts/2)
11738 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11739 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11740 OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
11741 auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
11742 if (Idx2 && Idx2->getZExtValue() == 0) {
11743 SDValue SubVec2 = Vec.getOperand(1);
11744 // If needed, look through a bitcast to get to the load.
11745 if (SubVec2.getNode() && SubVec2.getOpcode() == ISD::BITCAST)
11746 SubVec2 = SubVec2.getOperand(0);
11748 if (auto *FirstLd = dyn_cast<LoadSDNode>(SubVec2)) {
11750 unsigned Alignment = FirstLd->getAlignment();
11751 unsigned AS = FirstLd->getAddressSpace();
11752 const X86TargetLowering *TLI = Subtarget->getTargetLowering();
11753 if (TLI->allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
11754 OpVT, AS, Alignment, &Fast) && Fast) {
11755 SDValue Ops[] = { SubVec2, SubVec };
11756 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11763 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11764 SubVecVT.is128BitVector())
11765 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11767 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11768 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11770 if (OpVT.getVectorElementType() == MVT::i1) {
11771 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11773 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11774 SDValue Undef = DAG.getUNDEF(OpVT);
11775 unsigned NumElems = OpVT.getVectorNumElements();
11776 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11778 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11779 // Zero upper bits of the Vec
11780 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11781 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11783 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11785 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11786 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11789 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11791 // Zero upper bits of the Vec2
11792 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11793 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11794 // Zero lower bits of the Vec
11795 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11796 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11797 // Merge them together
11798 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11804 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11805 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11806 // one of the above mentioned nodes. It has to be wrapped because otherwise
11807 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11808 // be used to form addressing mode. These wrapped nodes will be selected
11811 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11812 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11814 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11815 // global base reg.
11816 unsigned char OpFlag = 0;
11817 unsigned WrapperKind = X86ISD::Wrapper;
11818 CodeModel::Model M = DAG.getTarget().getCodeModel();
11820 if (Subtarget->isPICStyleRIPRel() &&
11821 (M == CodeModel::Small || M == CodeModel::Kernel))
11822 WrapperKind = X86ISD::WrapperRIP;
11823 else if (Subtarget->isPICStyleGOT())
11824 OpFlag = X86II::MO_GOTOFF;
11825 else if (Subtarget->isPICStyleStubPIC())
11826 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11828 auto PtrVT = getPointerTy(DAG.getDataLayout());
11829 SDValue Result = DAG.getTargetConstantPool(
11830 CP->getConstVal(), PtrVT, CP->getAlignment(), CP->getOffset(), OpFlag);
11832 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11833 // With PIC, the address is actually $g + Offset.
11836 DAG.getNode(ISD::ADD, DL, PtrVT,
11837 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11843 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11844 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11846 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11847 // global base reg.
11848 unsigned char OpFlag = 0;
11849 unsigned WrapperKind = X86ISD::Wrapper;
11850 CodeModel::Model M = DAG.getTarget().getCodeModel();
11852 if (Subtarget->isPICStyleRIPRel() &&
11853 (M == CodeModel::Small || M == CodeModel::Kernel))
11854 WrapperKind = X86ISD::WrapperRIP;
11855 else if (Subtarget->isPICStyleGOT())
11856 OpFlag = X86II::MO_GOTOFF;
11857 else if (Subtarget->isPICStyleStubPIC())
11858 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11860 auto PtrVT = getPointerTy(DAG.getDataLayout());
11861 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
11863 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11865 // With PIC, the address is actually $g + Offset.
11868 DAG.getNode(ISD::ADD, DL, PtrVT,
11869 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11875 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11876 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11878 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11879 // global base reg.
11880 unsigned char OpFlag = 0;
11881 unsigned WrapperKind = X86ISD::Wrapper;
11882 CodeModel::Model M = DAG.getTarget().getCodeModel();
11884 if (Subtarget->isPICStyleRIPRel() &&
11885 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11886 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11887 OpFlag = X86II::MO_GOTPCREL;
11888 WrapperKind = X86ISD::WrapperRIP;
11889 } else if (Subtarget->isPICStyleGOT()) {
11890 OpFlag = X86II::MO_GOT;
11891 } else if (Subtarget->isPICStyleStubPIC()) {
11892 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11893 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11894 OpFlag = X86II::MO_DARWIN_NONLAZY;
11897 auto PtrVT = getPointerTy(DAG.getDataLayout());
11898 SDValue Result = DAG.getTargetExternalSymbol(Sym, PtrVT, OpFlag);
11901 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result);
11903 // With PIC, the address is actually $g + Offset.
11904 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11905 !Subtarget->is64Bit()) {
11907 DAG.getNode(ISD::ADD, DL, PtrVT,
11908 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), Result);
11911 // For symbols that require a load from a stub to get the address, emit the
11913 if (isGlobalStubReference(OpFlag))
11914 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
11915 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11916 false, false, false, 0);
11922 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11923 // Create the TargetBlockAddressAddress node.
11924 unsigned char OpFlags =
11925 Subtarget->ClassifyBlockAddressReference();
11926 CodeModel::Model M = DAG.getTarget().getCodeModel();
11927 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11928 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11930 auto PtrVT = getPointerTy(DAG.getDataLayout());
11931 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset, OpFlags);
11933 if (Subtarget->isPICStyleRIPRel() &&
11934 (M == CodeModel::Small || M == CodeModel::Kernel))
11935 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11937 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11939 // With PIC, the address is actually $g + Offset.
11940 if (isGlobalRelativeToPICBase(OpFlags)) {
11941 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11942 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11949 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11950 int64_t Offset, SelectionDAG &DAG) const {
11951 // Create the TargetGlobalAddress node, folding in the constant
11952 // offset if it is legal.
11953 unsigned char OpFlags =
11954 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11955 CodeModel::Model M = DAG.getTarget().getCodeModel();
11956 auto PtrVT = getPointerTy(DAG.getDataLayout());
11958 if (OpFlags == X86II::MO_NO_FLAG &&
11959 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11960 // A direct static reference to a global.
11961 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
11964 Result = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, OpFlags);
11967 if (Subtarget->isPICStyleRIPRel() &&
11968 (M == CodeModel::Small || M == CodeModel::Kernel))
11969 Result = DAG.getNode(X86ISD::WrapperRIP, dl, PtrVT, Result);
11971 Result = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, Result);
11973 // With PIC, the address is actually $g + Offset.
11974 if (isGlobalRelativeToPICBase(OpFlags)) {
11975 Result = DAG.getNode(ISD::ADD, dl, PtrVT,
11976 DAG.getNode(X86ISD::GlobalBaseReg, dl, PtrVT), Result);
11979 // For globals that require a load from a stub to get the address, emit the
11981 if (isGlobalStubReference(OpFlags))
11982 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
11983 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
11984 false, false, false, 0);
11986 // If there was a non-zero offset that we didn't fold, create an explicit
11987 // addition for it.
11989 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result,
11990 DAG.getConstant(Offset, dl, PtrVT));
11996 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11997 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11998 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11999 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
12003 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
12004 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
12005 unsigned char OperandFlags, bool LocalDynamic = false) {
12006 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12007 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12009 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12010 GA->getValueType(0),
12014 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
12018 SDValue Ops[] = { Chain, TGA, *InFlag };
12019 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12021 SDValue Ops[] = { Chain, TGA };
12022 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
12025 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
12026 MFI->setAdjustsStack(true);
12027 MFI->setHasCalls(true);
12029 SDValue Flag = Chain.getValue(1);
12030 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
12033 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
12035 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12038 SDLoc dl(GA); // ? function entry point might be better
12039 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12040 DAG.getNode(X86ISD::GlobalBaseReg,
12041 SDLoc(), PtrVT), InFlag);
12042 InFlag = Chain.getValue(1);
12044 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
12047 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
12049 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12051 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
12052 X86::RAX, X86II::MO_TLSGD);
12055 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
12061 // Get the start address of the TLS block for this module.
12062 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
12063 .getInfo<X86MachineFunctionInfo>();
12064 MFI->incNumLocalDynamicTLSAccesses();
12068 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
12069 X86II::MO_TLSLD, /*LocalDynamic=*/true);
12072 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
12073 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
12074 InFlag = Chain.getValue(1);
12075 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
12076 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
12079 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
12083 unsigned char OperandFlags = X86II::MO_DTPOFF;
12084 unsigned WrapperKind = X86ISD::Wrapper;
12085 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12086 GA->getValueType(0),
12087 GA->getOffset(), OperandFlags);
12088 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12090 // Add x@dtpoff with the base.
12091 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
12094 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
12095 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
12096 const EVT PtrVT, TLSModel::Model model,
12097 bool is64Bit, bool isPIC) {
12100 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
12101 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
12102 is64Bit ? 257 : 256));
12104 SDValue ThreadPointer =
12105 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
12106 MachinePointerInfo(Ptr), false, false, false, 0);
12108 unsigned char OperandFlags = 0;
12109 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
12111 unsigned WrapperKind = X86ISD::Wrapper;
12112 if (model == TLSModel::LocalExec) {
12113 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
12114 } else if (model == TLSModel::InitialExec) {
12116 OperandFlags = X86II::MO_GOTTPOFF;
12117 WrapperKind = X86ISD::WrapperRIP;
12119 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
12122 llvm_unreachable("Unexpected model");
12125 // emit "addl x@ntpoff,%eax" (local exec)
12126 // or "addl x@indntpoff,%eax" (initial exec)
12127 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
12129 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
12130 GA->getOffset(), OperandFlags);
12131 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
12133 if (model == TLSModel::InitialExec) {
12134 if (isPIC && !is64Bit) {
12135 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
12136 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12140 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
12141 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
12142 false, false, false, 0);
12145 // The address of the thread local variable is the add of the thread
12146 // pointer with the offset of the variable.
12147 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
12151 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
12153 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
12154 const GlobalValue *GV = GA->getGlobal();
12155 auto PtrVT = getPointerTy(DAG.getDataLayout());
12157 if (Subtarget->isTargetELF()) {
12158 if (DAG.getTarget().Options.EmulatedTLS)
12159 return LowerToTLSEmulatedModel(GA, DAG);
12160 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
12162 case TLSModel::GeneralDynamic:
12163 if (Subtarget->is64Bit())
12164 return LowerToTLSGeneralDynamicModel64(GA, DAG, PtrVT);
12165 return LowerToTLSGeneralDynamicModel32(GA, DAG, PtrVT);
12166 case TLSModel::LocalDynamic:
12167 return LowerToTLSLocalDynamicModel(GA, DAG, PtrVT,
12168 Subtarget->is64Bit());
12169 case TLSModel::InitialExec:
12170 case TLSModel::LocalExec:
12171 return LowerToTLSExecModel(GA, DAG, PtrVT, model, Subtarget->is64Bit(),
12172 DAG.getTarget().getRelocationModel() ==
12175 llvm_unreachable("Unknown TLS model.");
12178 if (Subtarget->isTargetDarwin()) {
12179 // Darwin only has one model of TLS. Lower to that.
12180 unsigned char OpFlag = 0;
12181 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
12182 X86ISD::WrapperRIP : X86ISD::Wrapper;
12184 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
12185 // global base reg.
12186 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
12187 !Subtarget->is64Bit();
12189 OpFlag = X86II::MO_TLVP_PIC_BASE;
12191 OpFlag = X86II::MO_TLVP;
12193 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
12194 GA->getValueType(0),
12195 GA->getOffset(), OpFlag);
12196 SDValue Offset = DAG.getNode(WrapperKind, DL, PtrVT, Result);
12198 // With PIC32, the address is actually $g + Offset.
12200 Offset = DAG.getNode(ISD::ADD, DL, PtrVT,
12201 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
12204 // Lowering the machine isd will make sure everything is in the right
12206 SDValue Chain = DAG.getEntryNode();
12207 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
12208 SDValue Args[] = { Chain, Offset };
12209 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
12211 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
12212 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
12213 MFI->setAdjustsStack(true);
12215 // And our return value (tls address) is in the standard call return value
12217 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
12218 return DAG.getCopyFromReg(Chain, DL, Reg, PtrVT, Chain.getValue(1));
12221 if (Subtarget->isTargetKnownWindowsMSVC() ||
12222 Subtarget->isTargetWindowsGNU()) {
12223 // Just use the implicit TLS architecture
12224 // Need to generate someting similar to:
12225 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
12227 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
12228 // mov rcx, qword [rdx+rcx*8]
12229 // mov eax, .tls$:tlsvar
12230 // [rax+rcx] contains the address
12231 // Windows 64bit: gs:0x58
12232 // Windows 32bit: fs:__tls_array
12235 SDValue Chain = DAG.getEntryNode();
12237 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
12238 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
12239 // use its literal value of 0x2C.
12240 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
12241 ? Type::getInt8PtrTy(*DAG.getContext(),
12243 : Type::getInt32PtrTy(*DAG.getContext(),
12246 SDValue TlsArray = Subtarget->is64Bit()
12247 ? DAG.getIntPtrConstant(0x58, dl)
12248 : (Subtarget->isTargetWindowsGNU()
12249 ? DAG.getIntPtrConstant(0x2C, dl)
12250 : DAG.getExternalSymbol("_tls_array", PtrVT));
12252 SDValue ThreadPointer =
12253 DAG.getLoad(PtrVT, dl, Chain, TlsArray, MachinePointerInfo(Ptr), false,
12257 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
12258 res = ThreadPointer;
12260 // Load the _tls_index variable
12261 SDValue IDX = DAG.getExternalSymbol("_tls_index", PtrVT);
12262 if (Subtarget->is64Bit())
12263 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
12264 MachinePointerInfo(), MVT::i32, false, false,
12267 IDX = DAG.getLoad(PtrVT, dl, Chain, IDX, MachinePointerInfo(), false,
12270 auto &DL = DAG.getDataLayout();
12272 DAG.getConstant(Log2_64_Ceil(DL.getPointerSize()), dl, PtrVT);
12273 IDX = DAG.getNode(ISD::SHL, dl, PtrVT, IDX, Scale);
12275 res = DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, IDX);
12278 res = DAG.getLoad(PtrVT, dl, Chain, res, MachinePointerInfo(), false, false,
12281 // Get the offset of start of .tls section
12282 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
12283 GA->getValueType(0),
12284 GA->getOffset(), X86II::MO_SECREL);
12285 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, PtrVT, TGA);
12287 // The address of the thread local variable is the add of the thread
12288 // pointer with the offset of the variable.
12289 return DAG.getNode(ISD::ADD, dl, PtrVT, res, Offset);
12292 llvm_unreachable("TLS not implemented for this target.");
12295 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
12296 /// and take a 2 x i32 value to shift plus a shift amount.
12297 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
12298 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
12299 MVT VT = Op.getSimpleValueType();
12300 unsigned VTBits = VT.getSizeInBits();
12302 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
12303 SDValue ShOpLo = Op.getOperand(0);
12304 SDValue ShOpHi = Op.getOperand(1);
12305 SDValue ShAmt = Op.getOperand(2);
12306 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
12307 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
12309 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12310 DAG.getConstant(VTBits - 1, dl, MVT::i8));
12311 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
12312 DAG.getConstant(VTBits - 1, dl, MVT::i8))
12313 : DAG.getConstant(0, dl, VT);
12315 SDValue Tmp2, Tmp3;
12316 if (Op.getOpcode() == ISD::SHL_PARTS) {
12317 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
12318 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
12320 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
12321 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
12324 // If the shift amount is larger or equal than the width of a part we can't
12325 // rely on the results of shld/shrd. Insert a test and select the appropriate
12326 // values for large shift amounts.
12327 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
12328 DAG.getConstant(VTBits, dl, MVT::i8));
12329 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
12330 AndNode, DAG.getConstant(0, dl, MVT::i8));
12333 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
12334 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
12335 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12337 if (Op.getOpcode() == ISD::SHL_PARTS) {
12338 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12339 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12341 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
12342 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
12345 SDValue Ops[2] = { Lo, Hi };
12346 return DAG.getMergeValues(Ops, dl);
12349 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
12350 SelectionDAG &DAG) const {
12351 SDValue Src = Op.getOperand(0);
12352 MVT SrcVT = Src.getSimpleValueType();
12353 MVT VT = Op.getSimpleValueType();
12356 if (SrcVT.isVector()) {
12357 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
12358 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
12359 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
12360 DAG.getUNDEF(SrcVT)));
12362 if (SrcVT.getVectorElementType() == MVT::i1) {
12363 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
12364 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12365 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
12370 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
12371 "Unknown SINT_TO_FP to lower!");
12373 // These are really Legal; return the operand so the caller accepts it as
12375 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
12377 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
12378 Subtarget->is64Bit()) {
12382 unsigned Size = SrcVT.getSizeInBits()/8;
12383 MachineFunction &MF = DAG.getMachineFunction();
12384 auto PtrVT = getPointerTy(MF.getDataLayout());
12385 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
12386 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12387 SDValue Chain = DAG.getStore(
12388 DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot,
12389 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI), false,
12391 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
12394 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
12396 SelectionDAG &DAG) const {
12400 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
12402 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
12404 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
12406 unsigned ByteSize = SrcVT.getSizeInBits()/8;
12408 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
12409 MachineMemOperand *MMO;
12411 int SSFI = FI->getIndex();
12412 MMO = DAG.getMachineFunction().getMachineMemOperand(
12413 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12414 MachineMemOperand::MOLoad, ByteSize, ByteSize);
12416 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
12417 StackSlot = StackSlot.getOperand(1);
12419 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
12420 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
12422 Tys, Ops, SrcVT, MMO);
12425 Chain = Result.getValue(1);
12426 SDValue InFlag = Result.getValue(2);
12428 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
12429 // shouldn't be necessary except that RFP cannot be live across
12430 // multiple blocks. When stackifier is fixed, they can be uncoupled.
12431 MachineFunction &MF = DAG.getMachineFunction();
12432 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
12433 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
12434 auto PtrVT = getPointerTy(MF.getDataLayout());
12435 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12436 Tys = DAG.getVTList(MVT::Other);
12438 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
12440 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12441 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12442 MachineMemOperand::MOStore, SSFISize, SSFISize);
12444 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
12445 Ops, Op.getValueType(), MMO);
12446 Result = DAG.getLoad(
12447 Op.getValueType(), DL, Chain, StackSlot,
12448 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12449 false, false, false, 0);
12455 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
12456 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
12457 SelectionDAG &DAG) const {
12458 // This algorithm is not obvious. Here it is what we're trying to output:
12461 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
12462 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
12464 haddpd %xmm0, %xmm0
12466 pshufd $0x4e, %xmm0, %xmm1
12472 LLVMContext *Context = DAG.getContext();
12474 // Build some magic constants.
12475 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
12476 Constant *C0 = ConstantDataVector::get(*Context, CV0);
12477 auto PtrVT = getPointerTy(DAG.getDataLayout());
12478 SDValue CPIdx0 = DAG.getConstantPool(C0, PtrVT, 16);
12480 SmallVector<Constant*,2> CV1;
12482 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12483 APInt(64, 0x4330000000000000ULL))));
12485 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
12486 APInt(64, 0x4530000000000000ULL))));
12487 Constant *C1 = ConstantVector::get(CV1);
12488 SDValue CPIdx1 = DAG.getConstantPool(C1, PtrVT, 16);
12490 // Load the 64-bit value into an XMM register.
12491 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
12494 DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
12495 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12496 false, false, false, 16);
12498 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
12501 DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
12502 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
12503 false, false, false, 16);
12504 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
12505 // TODO: Are there any fast-math-flags to propagate here?
12506 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
12509 if (Subtarget->hasSSE3()) {
12510 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
12511 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
12513 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
12514 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
12516 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
12517 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
12520 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
12521 DAG.getIntPtrConstant(0, dl));
12524 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
12525 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
12526 SelectionDAG &DAG) const {
12528 // FP constant to bias correct the final result.
12529 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
12532 // Load the 32-bit value into an XMM register.
12533 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
12536 // Zero out the upper parts of the register.
12537 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
12539 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12540 DAG.getBitcast(MVT::v2f64, Load),
12541 DAG.getIntPtrConstant(0, dl));
12543 // Or the load with the bias.
12544 SDValue Or = DAG.getNode(
12545 ISD::OR, dl, MVT::v2i64,
12546 DAG.getBitcast(MVT::v2i64,
12547 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
12548 DAG.getBitcast(MVT::v2i64,
12549 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
12551 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
12552 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
12554 // Subtract the bias.
12555 // TODO: Are there any fast-math-flags to propagate here?
12556 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
12558 // Handle final rounding.
12559 EVT DestVT = Op.getValueType();
12561 if (DestVT.bitsLT(MVT::f64))
12562 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
12563 DAG.getIntPtrConstant(0, dl));
12564 if (DestVT.bitsGT(MVT::f64))
12565 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
12567 // Handle final rounding.
12571 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
12572 const X86Subtarget &Subtarget) {
12573 // The algorithm is the following:
12574 // #ifdef __SSE4_1__
12575 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12576 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12577 // (uint4) 0x53000000, 0xaa);
12579 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12580 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12582 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12583 // return (float4) lo + fhi;
12585 // We shouldn't use it when unsafe-fp-math is enabled though: we might later
12586 // reassociate the two FADDs, and if we do that, the algorithm fails
12587 // spectacularly (PR24512).
12588 // FIXME: If we ever have some kind of Machine FMF, this should be marked
12589 // as non-fast and always be enabled. Why isn't SDAG FMF enough? Because
12590 // there's also the MachineCombiner reassociations happening on Machine IR.
12591 if (DAG.getTarget().Options.UnsafeFPMath)
12595 SDValue V = Op->getOperand(0);
12596 EVT VecIntVT = V.getValueType();
12597 bool Is128 = VecIntVT == MVT::v4i32;
12598 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12599 // If we convert to something else than the supported type, e.g., to v4f64,
12601 if (VecFloatVT != Op->getValueType(0))
12604 unsigned NumElts = VecIntVT.getVectorNumElements();
12605 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12606 "Unsupported custom type");
12607 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12609 // In the #idef/#else code, we have in common:
12610 // - The vector of constants:
12616 // Create the splat vector for 0x4b000000.
12617 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12618 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12619 CstLow, CstLow, CstLow, CstLow};
12620 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12621 makeArrayRef(&CstLowArray[0], NumElts));
12622 // Create the splat vector for 0x53000000.
12623 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12624 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12625 CstHigh, CstHigh, CstHigh, CstHigh};
12626 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12627 makeArrayRef(&CstHighArray[0], NumElts));
12629 // Create the right shift.
12630 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12631 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12632 CstShift, CstShift, CstShift, CstShift};
12633 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12634 makeArrayRef(&CstShiftArray[0], NumElts));
12635 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12638 if (Subtarget.hasSSE41()) {
12639 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12640 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12641 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12642 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12643 // Low will be bitcasted right away, so do not bother bitcasting back to its
12645 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12646 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12647 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12648 // (uint4) 0x53000000, 0xaa);
12649 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12650 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12651 // High will be bitcasted right away, so do not bother bitcasting back to
12652 // its original type.
12653 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12654 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12656 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12657 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12658 CstMask, CstMask, CstMask);
12659 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12660 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12661 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12663 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12664 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12667 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12668 SDValue CstFAdd = DAG.getConstantFP(
12669 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12670 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12671 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12672 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12673 makeArrayRef(&CstFAddArray[0], NumElts));
12675 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12676 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12677 // TODO: Are there any fast-math-flags to propagate here?
12679 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12680 // return (float4) lo + fhi;
12681 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12682 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12685 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12686 SelectionDAG &DAG) const {
12687 SDValue N0 = Op.getOperand(0);
12688 MVT SVT = N0.getSimpleValueType();
12691 switch (SVT.SimpleTy) {
12693 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12698 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12699 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12700 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12704 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12707 if (Subtarget->hasAVX512())
12708 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12709 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12711 llvm_unreachable(nullptr);
12714 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12715 SelectionDAG &DAG) const {
12716 SDValue N0 = Op.getOperand(0);
12718 auto PtrVT = getPointerTy(DAG.getDataLayout());
12720 if (Op.getValueType().isVector())
12721 return lowerUINT_TO_FP_vec(Op, DAG);
12723 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12724 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12725 // the optimization here.
12726 if (DAG.SignBitIsZero(N0))
12727 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12729 MVT SrcVT = N0.getSimpleValueType();
12730 MVT DstVT = Op.getSimpleValueType();
12732 if (Subtarget->hasAVX512() && isScalarFPTypeInSSEReg(DstVT) &&
12733 (SrcVT == MVT::i32 || (SrcVT == MVT::i64 && Subtarget->is64Bit()))) {
12734 // Conversions from unsigned i32 to f32/f64 are legal,
12735 // using VCVTUSI2SS/SD. Same for i64 in 64-bit mode.
12739 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12740 return LowerUINT_TO_FP_i64(Op, DAG);
12741 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12742 return LowerUINT_TO_FP_i32(Op, DAG);
12743 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12746 // Make a 64-bit buffer, and use it to build an FILD.
12747 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12748 if (SrcVT == MVT::i32) {
12749 SDValue WordOff = DAG.getConstant(4, dl, PtrVT);
12750 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, WordOff);
12751 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12752 StackSlot, MachinePointerInfo(),
12754 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12755 OffsetSlot, MachinePointerInfo(),
12757 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12761 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12762 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12763 StackSlot, MachinePointerInfo(),
12765 // For i64 source, we need to add the appropriate power of 2 if the input
12766 // was negative. This is the same as the optimization in
12767 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12768 // we must be careful to do the computation in x87 extended precision, not
12769 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12770 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12771 MachineMemOperand *MMO = DAG.getMachineFunction().getMachineMemOperand(
12772 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SSFI),
12773 MachineMemOperand::MOLoad, 8, 8);
12775 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12776 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12777 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12780 APInt FF(32, 0x5F800000ULL);
12782 // Check whether the sign bit is set.
12783 SDValue SignSet = DAG.getSetCC(
12784 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64),
12785 Op.getOperand(0), DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12787 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12788 SDValue FudgePtr = DAG.getConstantPool(
12789 ConstantInt::get(*DAG.getContext(), FF.zext(64)), PtrVT);
12791 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12792 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12793 SDValue Four = DAG.getIntPtrConstant(4, dl);
12794 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12796 FudgePtr = DAG.getNode(ISD::ADD, dl, PtrVT, FudgePtr, Offset);
12798 // Load the value out, extending it from f32 to f80.
12799 // FIXME: Avoid the extend by constructing the right constant pool?
12800 SDValue Fudge = DAG.getExtLoad(
12801 ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), FudgePtr,
12802 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
12803 false, false, false, 4);
12804 // Extend everything to 80 bits to force it to be done on x87.
12805 // TODO: Are there any fast-math-flags to propagate here?
12806 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12807 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12808 DAG.getIntPtrConstant(0, dl));
12811 // If the given FP_TO_SINT (IsSigned) or FP_TO_UINT (!IsSigned) operation
12812 // is legal, or has an fp128 or f16 source (which needs to be promoted to f32),
12813 // just return an <SDValue(), SDValue()> pair.
12814 // Otherwise it is assumed to be a conversion from one of f32, f64 or f80
12815 // to i16, i32 or i64, and we lower it to a legal sequence.
12816 // If lowered to the final integer result we return a <result, SDValue()> pair.
12817 // Otherwise we lower it to a sequence ending with a FIST, return a
12818 // <FIST, StackSlot> pair, and the caller is responsible for loading
12819 // the final integer result from StackSlot.
12820 std::pair<SDValue,SDValue>
12821 X86TargetLowering::FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12822 bool IsSigned, bool IsReplace) const {
12825 EVT DstTy = Op.getValueType();
12826 EVT TheVT = Op.getOperand(0).getValueType();
12827 auto PtrVT = getPointerTy(DAG.getDataLayout());
12829 if (TheVT != MVT::f32 && TheVT != MVT::f64 && TheVT != MVT::f80) {
12830 // f16 must be promoted before using the lowering in this routine.
12831 // fp128 does not use this lowering.
12832 return std::make_pair(SDValue(), SDValue());
12835 // If using FIST to compute an unsigned i64, we'll need some fixup
12836 // to handle values above the maximum signed i64. A FIST is always
12837 // used for the 32-bit subtarget, but also for f80 on a 64-bit target.
12838 bool UnsignedFixup = !IsSigned &&
12839 DstTy == MVT::i64 &&
12840 (!Subtarget->is64Bit() ||
12841 !isScalarFPTypeInSSEReg(TheVT));
12843 if (!IsSigned && DstTy != MVT::i64 && !Subtarget->hasAVX512()) {
12844 // Replace the fp-to-uint32 operation with an fp-to-sint64 FIST.
12845 // The low 32 bits of the fist result will have the correct uint32 result.
12846 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12850 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12851 DstTy.getSimpleVT() >= MVT::i16 &&
12852 "Unknown FP_TO_INT to lower!");
12854 // These are really Legal.
12855 if (DstTy == MVT::i32 &&
12856 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12857 return std::make_pair(SDValue(), SDValue());
12858 if (Subtarget->is64Bit() &&
12859 DstTy == MVT::i64 &&
12860 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12861 return std::make_pair(SDValue(), SDValue());
12863 // We lower FP->int64 into FISTP64 followed by a load from a temporary
12865 MachineFunction &MF = DAG.getMachineFunction();
12866 unsigned MemSize = DstTy.getSizeInBits()/8;
12867 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12868 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12871 switch (DstTy.getSimpleVT().SimpleTy) {
12872 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12873 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12874 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12875 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12878 SDValue Chain = DAG.getEntryNode();
12879 SDValue Value = Op.getOperand(0);
12880 SDValue Adjust; // 0x0 or 0x80000000, for result sign bit adjustment.
12882 if (UnsignedFixup) {
12884 // Conversion to unsigned i64 is implemented with a select,
12885 // depending on whether the source value fits in the range
12886 // of a signed i64. Let Thresh be the FP equivalent of
12887 // 0x8000000000000000ULL.
12889 // Adjust i32 = (Value < Thresh) ? 0 : 0x80000000;
12890 // FistSrc = (Value < Thresh) ? Value : (Value - Thresh);
12891 // Fist-to-mem64 FistSrc
12892 // Add 0 or 0x800...0ULL to the 64-bit result, which is equivalent
12893 // to XOR'ing the high 32 bits with Adjust.
12895 // Being a power of 2, Thresh is exactly representable in all FP formats.
12896 // For X87 we'd like to use the smallest FP type for this constant, but
12897 // for DAG type consistency we have to match the FP operand type.
12899 APFloat Thresh(APFloat::IEEEsingle, APInt(32, 0x5f000000));
12900 LLVM_ATTRIBUTE_UNUSED APFloat::opStatus Status = APFloat::opOK;
12901 bool LosesInfo = false;
12902 if (TheVT == MVT::f64)
12903 // The rounding mode is irrelevant as the conversion should be exact.
12904 Status = Thresh.convert(APFloat::IEEEdouble, APFloat::rmNearestTiesToEven,
12906 else if (TheVT == MVT::f80)
12907 Status = Thresh.convert(APFloat::x87DoubleExtended,
12908 APFloat::rmNearestTiesToEven, &LosesInfo);
12910 assert(Status == APFloat::opOK && !LosesInfo &&
12911 "FP conversion should have been exact");
12913 SDValue ThreshVal = DAG.getConstantFP(Thresh, DL, TheVT);
12915 SDValue Cmp = DAG.getSetCC(DL,
12916 getSetCCResultType(DAG.getDataLayout(),
12917 *DAG.getContext(), TheVT),
12918 Value, ThreshVal, ISD::SETLT);
12919 Adjust = DAG.getSelect(DL, MVT::i32, Cmp,
12920 DAG.getConstant(0, DL, MVT::i32),
12921 DAG.getConstant(0x80000000, DL, MVT::i32));
12922 SDValue Sub = DAG.getNode(ISD::FSUB, DL, TheVT, Value, ThreshVal);
12923 Cmp = DAG.getSetCC(DL, getSetCCResultType(DAG.getDataLayout(),
12924 *DAG.getContext(), TheVT),
12925 Value, ThreshVal, ISD::SETLT);
12926 Value = DAG.getSelect(DL, TheVT, Cmp, Value, Sub);
12929 // FIXME This causes a redundant load/store if the SSE-class value is already
12930 // in memory, such as if it is on the callstack.
12931 if (isScalarFPTypeInSSEReg(TheVT)) {
12932 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12933 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12934 MachinePointerInfo::getFixedStack(MF, SSFI), false,
12936 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12938 Chain, StackSlot, DAG.getValueType(TheVT)
12941 MachineMemOperand *MMO =
12942 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12943 MachineMemOperand::MOLoad, MemSize, MemSize);
12944 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12945 Chain = Value.getValue(1);
12946 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12947 StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
12950 MachineMemOperand *MMO =
12951 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
12952 MachineMemOperand::MOStore, MemSize, MemSize);
12954 if (UnsignedFixup) {
12956 // Insert the FIST, load its result as two i32's,
12957 // and XOR the high i32 with Adjust.
12959 SDValue FistOps[] = { Chain, Value, StackSlot };
12960 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12961 FistOps, DstTy, MMO);
12963 SDValue Low32 = DAG.getLoad(MVT::i32, DL, FIST, StackSlot,
12964 MachinePointerInfo(),
12965 false, false, false, 0);
12966 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackSlot,
12967 DAG.getConstant(4, DL, PtrVT));
12969 SDValue High32 = DAG.getLoad(MVT::i32, DL, FIST, HighAddr,
12970 MachinePointerInfo(),
12971 false, false, false, 0);
12972 High32 = DAG.getNode(ISD::XOR, DL, MVT::i32, High32, Adjust);
12974 if (Subtarget->is64Bit()) {
12975 // Join High32 and Low32 into a 64-bit result.
12976 // (High32 << 32) | Low32
12977 Low32 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Low32);
12978 High32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, High32);
12979 High32 = DAG.getNode(ISD::SHL, DL, MVT::i64, High32,
12980 DAG.getConstant(32, DL, MVT::i8));
12981 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i64, High32, Low32);
12982 return std::make_pair(Result, SDValue());
12985 SDValue ResultOps[] = { Low32, High32 };
12987 SDValue pair = IsReplace
12988 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResultOps)
12989 : DAG.getMergeValues(ResultOps, DL);
12990 return std::make_pair(pair, SDValue());
12992 // Build the FP_TO_INT*_IN_MEM
12993 SDValue Ops[] = { Chain, Value, StackSlot };
12994 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12996 return std::make_pair(FIST, StackSlot);
13000 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
13001 const X86Subtarget *Subtarget) {
13002 MVT VT = Op->getSimpleValueType(0);
13003 SDValue In = Op->getOperand(0);
13004 MVT InVT = In.getSimpleValueType();
13007 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
13008 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
13010 // Optimize vectors in AVX mode:
13013 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
13014 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
13015 // Concat upper and lower parts.
13018 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
13019 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
13020 // Concat upper and lower parts.
13023 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
13024 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
13025 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
13028 if (Subtarget->hasInt256())
13029 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
13031 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
13032 SDValue Undef = DAG.getUNDEF(InVT);
13033 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
13034 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13035 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
13037 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
13038 VT.getVectorNumElements()/2);
13040 OpLo = DAG.getBitcast(HVT, OpLo);
13041 OpHi = DAG.getBitcast(HVT, OpHi);
13043 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
13046 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
13047 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
13048 MVT VT = Op->getSimpleValueType(0);
13049 SDValue In = Op->getOperand(0);
13050 MVT InVT = In.getSimpleValueType();
13052 unsigned int NumElts = VT.getVectorNumElements();
13053 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13056 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
13057 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
13059 assert(InVT.getVectorElementType() == MVT::i1);
13060 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13062 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
13064 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
13066 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
13067 if (VT.is512BitVector())
13069 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
13072 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13073 SelectionDAG &DAG) {
13074 if (Subtarget->hasFp256())
13075 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13081 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13082 SelectionDAG &DAG) {
13084 MVT VT = Op.getSimpleValueType();
13085 SDValue In = Op.getOperand(0);
13086 MVT SVT = In.getSimpleValueType();
13088 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
13089 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
13091 if (Subtarget->hasFp256())
13092 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
13095 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
13096 VT.getVectorNumElements() != SVT.getVectorNumElements());
13100 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
13102 MVT VT = Op.getSimpleValueType();
13103 SDValue In = Op.getOperand(0);
13104 MVT InVT = In.getSimpleValueType();
13106 if (VT == MVT::i1) {
13107 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
13108 "Invalid scalar TRUNCATE operation");
13109 if (InVT.getSizeInBits() >= 32)
13111 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
13112 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
13114 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
13115 "Invalid TRUNCATE operation");
13117 // move vector to mask - truncate solution for SKX
13118 if (VT.getVectorElementType() == MVT::i1) {
13119 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
13120 Subtarget->hasBWI())
13121 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13122 if ((InVT.is256BitVector() || InVT.is128BitVector())
13123 && InVT.getScalarSizeInBits() <= 16 &&
13124 Subtarget->hasBWI() && Subtarget->hasVLX())
13125 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
13126 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
13127 Subtarget->hasDQI())
13128 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
13129 if ((InVT.is256BitVector() || InVT.is128BitVector())
13130 && InVT.getScalarSizeInBits() >= 32 &&
13131 Subtarget->hasDQI() && Subtarget->hasVLX())
13132 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
13135 if (VT.getVectorElementType() == MVT::i1) {
13136 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13137 unsigned NumElts = InVT.getVectorNumElements();
13138 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
13139 if (InVT.getSizeInBits() < 512) {
13140 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
13141 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
13146 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
13147 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
13148 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
13151 // vpmovqb/w/d, vpmovdb/w, vpmovwb
13152 if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&
13153 (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))
13154 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
13156 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
13157 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
13158 if (Subtarget->hasInt256()) {
13159 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
13160 In = DAG.getBitcast(MVT::v8i32, In);
13161 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
13163 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
13164 DAG.getIntPtrConstant(0, DL));
13167 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13168 DAG.getIntPtrConstant(0, DL));
13169 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13170 DAG.getIntPtrConstant(2, DL));
13171 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13172 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13173 static const int ShufMask[] = {0, 2, 4, 6};
13174 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
13177 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
13178 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
13179 if (Subtarget->hasInt256()) {
13180 In = DAG.getBitcast(MVT::v32i8, In);
13182 SmallVector<SDValue,32> pshufbMask;
13183 for (unsigned i = 0; i < 2; ++i) {
13184 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
13185 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
13186 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
13187 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
13188 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
13189 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
13190 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
13191 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
13192 for (unsigned j = 0; j < 8; ++j)
13193 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
13195 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
13196 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
13197 In = DAG.getBitcast(MVT::v4i64, In);
13199 static const int ShufMask[] = {0, 2, -1, -1};
13200 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
13202 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
13203 DAG.getIntPtrConstant(0, DL));
13204 return DAG.getBitcast(VT, In);
13207 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13208 DAG.getIntPtrConstant(0, DL));
13210 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
13211 DAG.getIntPtrConstant(4, DL));
13213 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
13214 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
13216 // The PSHUFB mask:
13217 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
13218 -1, -1, -1, -1, -1, -1, -1, -1};
13220 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
13221 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
13222 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
13224 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
13225 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
13227 // The MOVLHPS Mask:
13228 static const int ShufMask2[] = {0, 1, 4, 5};
13229 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
13230 return DAG.getBitcast(MVT::v8i16, res);
13233 // Handle truncation of V256 to V128 using shuffles.
13234 if (!VT.is128BitVector() || !InVT.is256BitVector())
13237 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
13239 unsigned NumElems = VT.getVectorNumElements();
13240 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
13242 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
13243 // Prepare truncation shuffle mask
13244 for (unsigned i = 0; i != NumElems; ++i)
13245 MaskVec[i] = i * 2;
13246 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
13247 DAG.getUNDEF(NVT), &MaskVec[0]);
13248 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
13249 DAG.getIntPtrConstant(0, DL));
13252 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
13253 SelectionDAG &DAG) const {
13254 assert(!Op.getSimpleValueType().isVector());
13256 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13257 /*IsSigned=*/ true, /*IsReplace=*/ false);
13258 SDValue FIST = Vals.first, StackSlot = Vals.second;
13259 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13260 if (!FIST.getNode())
13263 if (StackSlot.getNode())
13264 // Load the result.
13265 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13266 FIST, StackSlot, MachinePointerInfo(),
13267 false, false, false, 0);
13269 // The node is the result.
13273 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
13274 SelectionDAG &DAG) const {
13275 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
13276 /*IsSigned=*/ false, /*IsReplace=*/ false);
13277 SDValue FIST = Vals.first, StackSlot = Vals.second;
13278 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
13279 if (!FIST.getNode())
13282 if (StackSlot.getNode())
13283 // Load the result.
13284 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
13285 FIST, StackSlot, MachinePointerInfo(),
13286 false, false, false, 0);
13288 // The node is the result.
13292 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
13294 MVT VT = Op.getSimpleValueType();
13295 SDValue In = Op.getOperand(0);
13296 MVT SVT = In.getSimpleValueType();
13298 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
13300 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
13301 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
13302 In, DAG.getUNDEF(SVT)));
13305 /// The only differences between FABS and FNEG are the mask and the logic op.
13306 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
13307 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
13308 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
13309 "Wrong opcode for lowering FABS or FNEG.");
13311 bool IsFABS = (Op.getOpcode() == ISD::FABS);
13313 // If this is a FABS and it has an FNEG user, bail out to fold the combination
13314 // into an FNABS. We'll lower the FABS after that if it is still in use.
13316 for (SDNode *User : Op->uses())
13317 if (User->getOpcode() == ISD::FNEG)
13321 MVT VT = Op.getSimpleValueType();
13323 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
13324 // decide if we should generate a 16-byte constant mask when we only need 4 or
13325 // 8 bytes for the scalar case.
13331 if (VT.isVector()) {
13333 EltVT = VT.getVectorElementType();
13334 NumElts = VT.getVectorNumElements();
13336 // There are no scalar bitwise logical SSE/AVX instructions, so we
13337 // generate a 16-byte vector constant and logic op even for the scalar case.
13338 // Using a 16-byte mask allows folding the load of the mask with
13339 // the logic op, so it can save (~4 bytes) on code size.
13340 LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13342 NumElts = (VT == MVT::f64) ? 2 : 4;
13345 unsigned EltBits = EltVT.getSizeInBits();
13346 LLVMContext *Context = DAG.getContext();
13347 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
13349 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
13350 Constant *C = ConstantInt::get(*Context, MaskElt);
13351 C = ConstantVector::getSplat(NumElts, C);
13352 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13353 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));
13354 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13356 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13357 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13358 false, false, false, Alignment);
13360 SDValue Op0 = Op.getOperand(0);
13361 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
13363 IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
13364 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
13367 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13369 // For the scalar case extend to a 128-bit vector, perform the logic op,
13370 // and extract the scalar result back out.
13371 Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);
13372 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);
13373 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,
13374 DAG.getIntPtrConstant(0, dl));
13377 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
13378 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13379 LLVMContext *Context = DAG.getContext();
13380 SDValue Op0 = Op.getOperand(0);
13381 SDValue Op1 = Op.getOperand(1);
13383 MVT VT = Op.getSimpleValueType();
13384 MVT SrcVT = Op1.getSimpleValueType();
13386 // If second operand is smaller, extend it first.
13387 if (SrcVT.bitsLT(VT)) {
13388 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
13391 // And if it is bigger, shrink it first.
13392 if (SrcVT.bitsGT(VT)) {
13393 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
13397 // At this point the operands and the result should have the same
13398 // type, and that won't be f80 since that is not custom lowered.
13400 const fltSemantics &Sem =
13401 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
13402 const unsigned SizeInBits = VT.getSizeInBits();
13404 SmallVector<Constant *, 4> CV(
13405 VT == MVT::f64 ? 2 : 4,
13406 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
13408 // First, clear all bits but the sign bit from the second operand (sign).
13409 CV[0] = ConstantFP::get(*Context,
13410 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
13411 Constant *C = ConstantVector::get(CV);
13412 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
13413 SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13415 // Perform all logic operations as 16-byte vectors because there are no
13416 // scalar FP logic instructions in SSE. This allows load folding of the
13417 // constants into the logic instructions.
13418 MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;
13420 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13421 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13422 false, false, false, 16);
13423 Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);
13424 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);
13426 // Next, clear the sign bit from the first operand (magnitude).
13427 // If it's a constant, we can clear it here.
13428 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
13429 APFloat APF = Op0CN->getValueAPF();
13430 // If the magnitude is a positive zero, the sign bit alone is enough.
13431 if (APF.isPosZero())
13432 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,
13433 DAG.getIntPtrConstant(0, dl));
13435 CV[0] = ConstantFP::get(*Context, APF);
13437 CV[0] = ConstantFP::get(
13439 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
13441 C = ConstantVector::get(CV);
13442 CPIdx = DAG.getConstantPool(C, PtrVT, 16);
13444 DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,
13445 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
13446 false, false, false, 16);
13447 // If the magnitude operand wasn't a constant, we need to AND out the sign.
13448 if (!isa<ConstantFPSDNode>(Op0)) {
13449 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);
13450 Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);
13452 // OR the magnitude value with the sign bit.
13453 Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);
13454 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,
13455 DAG.getIntPtrConstant(0, dl));
13458 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
13459 SDValue N0 = Op.getOperand(0);
13461 MVT VT = Op.getSimpleValueType();
13463 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
13464 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
13465 DAG.getConstant(1, dl, VT));
13466 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
13469 // Check whether an OR'd tree is PTEST-able.
13470 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
13471 SelectionDAG &DAG) {
13472 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
13474 if (!Subtarget->hasSSE41())
13477 if (!Op->hasOneUse())
13480 SDNode *N = Op.getNode();
13483 SmallVector<SDValue, 8> Opnds;
13484 DenseMap<SDValue, unsigned> VecInMap;
13485 SmallVector<SDValue, 8> VecIns;
13486 EVT VT = MVT::Other;
13488 // Recognize a special case where a vector is casted into wide integer to
13490 Opnds.push_back(N->getOperand(0));
13491 Opnds.push_back(N->getOperand(1));
13493 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
13494 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
13495 // BFS traverse all OR'd operands.
13496 if (I->getOpcode() == ISD::OR) {
13497 Opnds.push_back(I->getOperand(0));
13498 Opnds.push_back(I->getOperand(1));
13499 // Re-evaluate the number of nodes to be traversed.
13500 e += 2; // 2 more nodes (LHS and RHS) are pushed.
13504 // Quit if a non-EXTRACT_VECTOR_ELT
13505 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
13508 // Quit if without a constant index.
13509 SDValue Idx = I->getOperand(1);
13510 if (!isa<ConstantSDNode>(Idx))
13513 SDValue ExtractedFromVec = I->getOperand(0);
13514 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
13515 if (M == VecInMap.end()) {
13516 VT = ExtractedFromVec.getValueType();
13517 // Quit if not 128/256-bit vector.
13518 if (!VT.is128BitVector() && !VT.is256BitVector())
13520 // Quit if not the same type.
13521 if (VecInMap.begin() != VecInMap.end() &&
13522 VT != VecInMap.begin()->first.getValueType())
13524 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
13525 VecIns.push_back(ExtractedFromVec);
13527 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
13530 assert((VT.is128BitVector() || VT.is256BitVector()) &&
13531 "Not extracted from 128-/256-bit vector.");
13533 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
13535 for (DenseMap<SDValue, unsigned>::const_iterator
13536 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
13537 // Quit if not all elements are used.
13538 if (I->second != FullMask)
13542 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
13544 // Cast all vectors into TestVT for PTEST.
13545 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
13546 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
13548 // If more than one full vectors are evaluated, OR them first before PTEST.
13549 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
13550 // Each iteration will OR 2 nodes and append the result until there is only
13551 // 1 node left, i.e. the final OR'd value of all vectors.
13552 SDValue LHS = VecIns[Slot];
13553 SDValue RHS = VecIns[Slot + 1];
13554 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
13557 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
13558 VecIns.back(), VecIns.back());
13561 /// \brief return true if \c Op has a use that doesn't just read flags.
13562 static bool hasNonFlagsUse(SDValue Op) {
13563 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
13565 SDNode *User = *UI;
13566 unsigned UOpNo = UI.getOperandNo();
13567 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
13568 // Look pass truncate.
13569 UOpNo = User->use_begin().getOperandNo();
13570 User = *User->use_begin();
13573 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
13574 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
13580 /// Emit nodes that will be selected as "test Op0,Op0", or something
13582 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
13583 SelectionDAG &DAG) const {
13584 if (Op.getValueType() == MVT::i1) {
13585 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
13586 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
13587 DAG.getConstant(0, dl, MVT::i8));
13589 // CF and OF aren't always set the way we want. Determine which
13590 // of these we need.
13591 bool NeedCF = false;
13592 bool NeedOF = false;
13595 case X86::COND_A: case X86::COND_AE:
13596 case X86::COND_B: case X86::COND_BE:
13599 case X86::COND_G: case X86::COND_GE:
13600 case X86::COND_L: case X86::COND_LE:
13601 case X86::COND_O: case X86::COND_NO: {
13602 // Check if we really need to set the
13603 // Overflow flag. If NoSignedWrap is present
13604 // that is not actually needed.
13605 switch (Op->getOpcode()) {
13610 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
13611 if (BinNode->Flags.hasNoSignedWrap())
13621 // See if we can use the EFLAGS value from the operand instead of
13622 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
13623 // we prove that the arithmetic won't overflow, we can't use OF or CF.
13624 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
13625 // Emit a CMP with 0, which is the TEST pattern.
13626 //if (Op.getValueType() == MVT::i1)
13627 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
13628 // DAG.getConstant(0, MVT::i1));
13629 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13630 DAG.getConstant(0, dl, Op.getValueType()));
13632 unsigned Opcode = 0;
13633 unsigned NumOperands = 0;
13635 // Truncate operations may prevent the merge of the SETCC instruction
13636 // and the arithmetic instruction before it. Attempt to truncate the operands
13637 // of the arithmetic instruction and use a reduced bit-width instruction.
13638 bool NeedTruncation = false;
13639 SDValue ArithOp = Op;
13640 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
13641 SDValue Arith = Op->getOperand(0);
13642 // Both the trunc and the arithmetic op need to have one user each.
13643 if (Arith->hasOneUse())
13644 switch (Arith.getOpcode()) {
13651 NeedTruncation = true;
13657 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
13658 // which may be the result of a CAST. We use the variable 'Op', which is the
13659 // non-casted variable when we check for possible users.
13660 switch (ArithOp.getOpcode()) {
13662 // Due to an isel shortcoming, be conservative if this add is likely to be
13663 // selected as part of a load-modify-store instruction. When the root node
13664 // in a match is a store, isel doesn't know how to remap non-chain non-flag
13665 // uses of other nodes in the match, such as the ADD in this case. This
13666 // leads to the ADD being left around and reselected, with the result being
13667 // two adds in the output. Alas, even if none our users are stores, that
13668 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
13669 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
13670 // climbing the DAG back to the root, and it doesn't seem to be worth the
13672 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13673 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13674 if (UI->getOpcode() != ISD::CopyToReg &&
13675 UI->getOpcode() != ISD::SETCC &&
13676 UI->getOpcode() != ISD::STORE)
13679 if (ConstantSDNode *C =
13680 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
13681 // An add of one will be selected as an INC.
13682 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
13683 Opcode = X86ISD::INC;
13688 // An add of negative one (subtract of one) will be selected as a DEC.
13689 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
13690 Opcode = X86ISD::DEC;
13696 // Otherwise use a regular EFLAGS-setting add.
13697 Opcode = X86ISD::ADD;
13702 // If we have a constant logical shift that's only used in a comparison
13703 // against zero turn it into an equivalent AND. This allows turning it into
13704 // a TEST instruction later.
13705 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
13706 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
13707 EVT VT = Op.getValueType();
13708 unsigned BitWidth = VT.getSizeInBits();
13709 unsigned ShAmt = Op->getConstantOperandVal(1);
13710 if (ShAmt >= BitWidth) // Avoid undefined shifts.
13712 APInt Mask = ArithOp.getOpcode() == ISD::SRL
13713 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
13714 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
13715 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
13717 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
13718 DAG.getConstant(Mask, dl, VT));
13719 DAG.ReplaceAllUsesWith(Op, New);
13725 // If the primary and result isn't used, don't bother using X86ISD::AND,
13726 // because a TEST instruction will be better.
13727 if (!hasNonFlagsUse(Op))
13733 // Due to the ISEL shortcoming noted above, be conservative if this op is
13734 // likely to be selected as part of a load-modify-store instruction.
13735 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13736 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13737 if (UI->getOpcode() == ISD::STORE)
13740 // Otherwise use a regular EFLAGS-setting instruction.
13741 switch (ArithOp.getOpcode()) {
13742 default: llvm_unreachable("unexpected operator!");
13743 case ISD::SUB: Opcode = X86ISD::SUB; break;
13744 case ISD::XOR: Opcode = X86ISD::XOR; break;
13745 case ISD::AND: Opcode = X86ISD::AND; break;
13747 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13748 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13749 if (EFLAGS.getNode())
13752 Opcode = X86ISD::OR;
13766 return SDValue(Op.getNode(), 1);
13772 // If we found that truncation is beneficial, perform the truncation and
13774 if (NeedTruncation) {
13775 EVT VT = Op.getValueType();
13776 SDValue WideVal = Op->getOperand(0);
13777 EVT WideVT = WideVal.getValueType();
13778 unsigned ConvertedOp = 0;
13779 // Use a target machine opcode to prevent further DAGCombine
13780 // optimizations that may separate the arithmetic operations
13781 // from the setcc node.
13782 switch (WideVal.getOpcode()) {
13784 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13785 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13786 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13787 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13788 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13792 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13793 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13794 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13795 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13796 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13802 // Emit a CMP with 0, which is the TEST pattern.
13803 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13804 DAG.getConstant(0, dl, Op.getValueType()));
13806 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13807 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13809 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13810 DAG.ReplaceAllUsesWith(Op, New);
13811 return SDValue(New.getNode(), 1);
13814 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13816 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13817 SDLoc dl, SelectionDAG &DAG) const {
13818 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13819 if (C->getAPIntValue() == 0)
13820 return EmitTest(Op0, X86CC, dl, DAG);
13822 if (Op0.getValueType() == MVT::i1)
13823 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13826 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13827 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13828 // Do the comparison at i32 if it's smaller, besides the Atom case.
13829 // This avoids subregister aliasing issues. Keep the smaller reference
13830 // if we're optimizing for size, however, as that'll allow better folding
13831 // of memory operations.
13832 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13833 !DAG.getMachineFunction().getFunction()->optForMinSize() &&
13834 !Subtarget->isAtom()) {
13835 unsigned ExtendOp =
13836 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13837 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13838 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13840 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13841 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13842 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13844 return SDValue(Sub.getNode(), 1);
13846 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13849 /// Convert a comparison if required by the subtarget.
13850 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13851 SelectionDAG &DAG) const {
13852 // If the subtarget does not support the FUCOMI instruction, floating-point
13853 // comparisons have to be converted.
13854 if (Subtarget->hasCMov() ||
13855 Cmp.getOpcode() != X86ISD::CMP ||
13856 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13857 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13860 // The instruction selector will select an FUCOM instruction instead of
13861 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13862 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13863 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13865 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13866 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13867 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13868 DAG.getConstant(8, dl, MVT::i8));
13869 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13870 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13873 /// The minimum architected relative accuracy is 2^-12. We need one
13874 /// Newton-Raphson step to have a good float result (24 bits of precision).
13875 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13876 DAGCombinerInfo &DCI,
13877 unsigned &RefinementSteps,
13878 bool &UseOneConstNR) const {
13879 EVT VT = Op.getValueType();
13880 const char *RecipOp;
13882 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13883 // TODO: Add support for AVX512 (v16f32).
13884 // It is likely not profitable to do this for f64 because a double-precision
13885 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13886 // instructions: convert to single, rsqrtss, convert back to double, refine
13887 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13888 // along with FMA, this could be a throughput win.
13889 if (VT == MVT::f32 && Subtarget->hasSSE1())
13891 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13892 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13893 RecipOp = "vec-sqrtf";
13897 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13898 if (!Recips.isEnabled(RecipOp))
13901 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13902 UseOneConstNR = false;
13903 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13906 /// The minimum architected relative accuracy is 2^-12. We need one
13907 /// Newton-Raphson step to have a good float result (24 bits of precision).
13908 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13909 DAGCombinerInfo &DCI,
13910 unsigned &RefinementSteps) const {
13911 EVT VT = Op.getValueType();
13912 const char *RecipOp;
13914 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13915 // TODO: Add support for AVX512 (v16f32).
13916 // It is likely not profitable to do this for f64 because a double-precision
13917 // reciprocal estimate with refinement on x86 prior to FMA requires
13918 // 15 instructions: convert to single, rcpss, convert back to double, refine
13919 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13920 // along with FMA, this could be a throughput win.
13921 if (VT == MVT::f32 && Subtarget->hasSSE1())
13923 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13924 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13925 RecipOp = "vec-divf";
13929 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13930 if (!Recips.isEnabled(RecipOp))
13933 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13934 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13937 /// If we have at least two divisions that use the same divisor, convert to
13938 /// multplication by a reciprocal. This may need to be adjusted for a given
13939 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13940 /// This is because we still need one division to calculate the reciprocal and
13941 /// then we need two multiplies by that reciprocal as replacements for the
13942 /// original divisions.
13943 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
13947 static bool isAllOnes(SDValue V) {
13948 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13949 return C && C->isAllOnesValue();
13952 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13953 /// if it's possible.
13954 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13955 SDLoc dl, SelectionDAG &DAG) const {
13956 SDValue Op0 = And.getOperand(0);
13957 SDValue Op1 = And.getOperand(1);
13958 if (Op0.getOpcode() == ISD::TRUNCATE)
13959 Op0 = Op0.getOperand(0);
13960 if (Op1.getOpcode() == ISD::TRUNCATE)
13961 Op1 = Op1.getOperand(0);
13964 if (Op1.getOpcode() == ISD::SHL)
13965 std::swap(Op0, Op1);
13966 if (Op0.getOpcode() == ISD::SHL) {
13967 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13968 if (And00C->getZExtValue() == 1) {
13969 // If we looked past a truncate, check that it's only truncating away
13971 unsigned BitWidth = Op0.getValueSizeInBits();
13972 unsigned AndBitWidth = And.getValueSizeInBits();
13973 if (BitWidth > AndBitWidth) {
13975 DAG.computeKnownBits(Op0, Zeros, Ones);
13976 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13980 RHS = Op0.getOperand(1);
13982 } else if (Op1.getOpcode() == ISD::Constant) {
13983 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13984 uint64_t AndRHSVal = AndRHS->getZExtValue();
13985 SDValue AndLHS = Op0;
13987 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13988 LHS = AndLHS.getOperand(0);
13989 RHS = AndLHS.getOperand(1);
13992 // Use BT if the immediate can't be encoded in a TEST instruction.
13993 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13995 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13999 if (LHS.getNode()) {
14000 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
14001 // instruction. Since the shift amount is in-range-or-undefined, we know
14002 // that doing a bittest on the i32 value is ok. We extend to i32 because
14003 // the encoding for the i16 version is larger than the i32 version.
14004 // Also promote i16 to i32 for performance / code size reason.
14005 if (LHS.getValueType() == MVT::i8 ||
14006 LHS.getValueType() == MVT::i16)
14007 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
14009 // If the operand types disagree, extend the shift amount to match. Since
14010 // BT ignores high bits (like shifts) we can use anyextend.
14011 if (LHS.getValueType() != RHS.getValueType())
14012 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
14014 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
14015 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
14016 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14017 DAG.getConstant(Cond, dl, MVT::i8), BT);
14023 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
14025 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
14030 // SSE Condition code mapping:
14039 switch (SetCCOpcode) {
14040 default: llvm_unreachable("Unexpected SETCC condition");
14042 case ISD::SETEQ: SSECC = 0; break;
14044 case ISD::SETGT: Swap = true; // Fallthrough
14046 case ISD::SETOLT: SSECC = 1; break;
14048 case ISD::SETGE: Swap = true; // Fallthrough
14050 case ISD::SETOLE: SSECC = 2; break;
14051 case ISD::SETUO: SSECC = 3; break;
14053 case ISD::SETNE: SSECC = 4; break;
14054 case ISD::SETULE: Swap = true; // Fallthrough
14055 case ISD::SETUGE: SSECC = 5; break;
14056 case ISD::SETULT: Swap = true; // Fallthrough
14057 case ISD::SETUGT: SSECC = 6; break;
14058 case ISD::SETO: SSECC = 7; break;
14060 case ISD::SETONE: SSECC = 8; break;
14063 std::swap(Op0, Op1);
14068 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
14069 // ones, and then concatenate the result back.
14070 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
14071 MVT VT = Op.getSimpleValueType();
14073 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
14074 "Unsupported value type for operation");
14076 unsigned NumElems = VT.getVectorNumElements();
14078 SDValue CC = Op.getOperand(2);
14080 // Extract the LHS vectors
14081 SDValue LHS = Op.getOperand(0);
14082 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
14083 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
14085 // Extract the RHS vectors
14086 SDValue RHS = Op.getOperand(1);
14087 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
14088 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
14090 // Issue the operation on the smaller types and concatenate the result back
14091 MVT EltVT = VT.getVectorElementType();
14092 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
14093 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
14094 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
14095 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
14098 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
14099 SDValue Op0 = Op.getOperand(0);
14100 SDValue Op1 = Op.getOperand(1);
14101 SDValue CC = Op.getOperand(2);
14102 MVT VT = Op.getSimpleValueType();
14105 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
14106 "Unexpected type for boolean compare operation");
14107 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14108 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
14109 DAG.getConstant(-1, dl, VT));
14110 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
14111 DAG.getConstant(-1, dl, VT));
14112 switch (SetCCOpcode) {
14113 default: llvm_unreachable("Unexpected SETCC condition");
14115 // (x == y) -> ~(x ^ y)
14116 return DAG.getNode(ISD::XOR, dl, VT,
14117 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
14118 DAG.getConstant(-1, dl, VT));
14120 // (x != y) -> (x ^ y)
14121 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
14124 // (x > y) -> (x & ~y)
14125 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
14128 // (x < y) -> (~x & y)
14129 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
14132 // (x <= y) -> (~x | y)
14133 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
14136 // (x >=y) -> (x | ~y)
14137 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
14141 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
14142 const X86Subtarget *Subtarget) {
14143 SDValue Op0 = Op.getOperand(0);
14144 SDValue Op1 = Op.getOperand(1);
14145 SDValue CC = Op.getOperand(2);
14146 MVT VT = Op.getSimpleValueType();
14149 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
14150 Op.getValueType().getScalarType() == MVT::i1 &&
14151 "Cannot set masked compare for this operation");
14153 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14155 bool Unsigned = false;
14158 switch (SetCCOpcode) {
14159 default: llvm_unreachable("Unexpected SETCC condition");
14160 case ISD::SETNE: SSECC = 4; break;
14161 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
14162 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
14163 case ISD::SETLT: Swap = true; //fall-through
14164 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
14165 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
14166 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
14167 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
14168 case ISD::SETULE: Unsigned = true; //fall-through
14169 case ISD::SETLE: SSECC = 2; break;
14173 std::swap(Op0, Op1);
14175 return DAG.getNode(Opc, dl, VT, Op0, Op1);
14176 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
14177 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14178 DAG.getConstant(SSECC, dl, MVT::i8));
14181 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
14182 /// operand \p Op1. If non-trivial (for example because it's not constant)
14183 /// return an empty value.
14184 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
14186 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
14190 MVT VT = Op1.getSimpleValueType();
14191 MVT EVT = VT.getVectorElementType();
14192 unsigned n = VT.getVectorNumElements();
14193 SmallVector<SDValue, 8> ULTOp1;
14195 for (unsigned i = 0; i < n; ++i) {
14196 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
14197 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
14200 // Avoid underflow.
14201 APInt Val = Elt->getAPIntValue();
14205 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
14208 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
14211 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
14212 SelectionDAG &DAG) {
14213 SDValue Op0 = Op.getOperand(0);
14214 SDValue Op1 = Op.getOperand(1);
14215 SDValue CC = Op.getOperand(2);
14216 MVT VT = Op.getSimpleValueType();
14217 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
14218 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
14223 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
14224 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
14227 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
14228 unsigned Opc = X86ISD::CMPP;
14229 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
14230 assert(VT.getVectorNumElements() <= 16);
14231 Opc = X86ISD::CMPM;
14233 // In the two special cases we can't handle, emit two comparisons.
14236 unsigned CombineOpc;
14237 if (SetCCOpcode == ISD::SETUEQ) {
14238 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
14240 assert(SetCCOpcode == ISD::SETONE);
14241 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
14244 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14245 DAG.getConstant(CC0, dl, MVT::i8));
14246 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
14247 DAG.getConstant(CC1, dl, MVT::i8));
14248 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
14250 // Handle all other FP comparisons here.
14251 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14252 DAG.getConstant(SSECC, dl, MVT::i8));
14255 MVT VTOp0 = Op0.getSimpleValueType();
14256 assert(VTOp0 == Op1.getSimpleValueType() &&
14257 "Expected operands with same type!");
14258 assert(VT.getVectorNumElements() == VTOp0.getVectorNumElements() &&
14259 "Invalid number of packed elements for source and destination!");
14261 if (VT.is128BitVector() && VTOp0.is256BitVector()) {
14262 // On non-AVX512 targets, a vector of MVT::i1 is promoted by the type
14263 // legalizer to a wider vector type. In the case of 'vsetcc' nodes, the
14264 // legalizer firstly checks if the first operand in input to the setcc has
14265 // a legal type. If so, then it promotes the return type to that same type.
14266 // Otherwise, the return type is promoted to the 'next legal type' which,
14267 // for a vector of MVT::i1 is always a 128-bit integer vector type.
14269 // We reach this code only if the following two conditions are met:
14270 // 1. Both return type and operand type have been promoted to wider types
14271 // by the type legalizer.
14272 // 2. The original operand type has been promoted to a 256-bit vector.
14274 // Note that condition 2. only applies for AVX targets.
14275 SDValue NewOp = DAG.getSetCC(dl, VTOp0, Op0, Op1, SetCCOpcode);
14276 return DAG.getZExtOrTrunc(NewOp, dl, VT);
14279 // The non-AVX512 code below works under the assumption that source and
14280 // destination types are the same.
14281 assert((Subtarget->hasAVX512() || (VT == VTOp0)) &&
14282 "Value types for source and destination must be the same!");
14284 // Break 256-bit integer vector compare into smaller ones.
14285 if (VT.is256BitVector() && !Subtarget->hasInt256())
14286 return Lower256IntVSETCC(Op, DAG);
14288 EVT OpVT = Op1.getValueType();
14289 if (OpVT.getVectorElementType() == MVT::i1)
14290 return LowerBoolVSETCC_AVX512(Op, DAG);
14292 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
14293 if (Subtarget->hasAVX512()) {
14294 if (Op1.getValueType().is512BitVector() ||
14295 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
14296 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
14297 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
14299 // In AVX-512 architecture setcc returns mask with i1 elements,
14300 // But there is no compare instruction for i8 and i16 elements in KNL.
14301 // We are not talking about 512-bit operands in this case, these
14302 // types are illegal.
14304 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
14305 OpVT.getVectorElementType().getSizeInBits() >= 8))
14306 return DAG.getNode(ISD::TRUNCATE, dl, VT,
14307 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
14310 // Lower using XOP integer comparisons.
14311 if ((VT == MVT::v16i8 || VT == MVT::v8i16 ||
14312 VT == MVT::v4i32 || VT == MVT::v2i64) && Subtarget->hasXOP()) {
14313 // Translate compare code to XOP PCOM compare mode.
14314 unsigned CmpMode = 0;
14315 switch (SetCCOpcode) {
14316 default: llvm_unreachable("Unexpected SETCC condition");
14318 case ISD::SETLT: CmpMode = 0x00; break;
14320 case ISD::SETLE: CmpMode = 0x01; break;
14322 case ISD::SETGT: CmpMode = 0x02; break;
14324 case ISD::SETGE: CmpMode = 0x03; break;
14325 case ISD::SETEQ: CmpMode = 0x04; break;
14326 case ISD::SETNE: CmpMode = 0x05; break;
14329 // Are we comparing unsigned or signed integers?
14330 unsigned Opc = ISD::isUnsignedIntSetCC(SetCCOpcode)
14331 ? X86ISD::VPCOMU : X86ISD::VPCOM;
14333 return DAG.getNode(Opc, dl, VT, Op0, Op1,
14334 DAG.getConstant(CmpMode, dl, MVT::i8));
14337 // We are handling one of the integer comparisons here. Since SSE only has
14338 // GT and EQ comparisons for integer, swapping operands and multiple
14339 // operations may be required for some comparisons.
14341 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
14342 bool Subus = false;
14344 switch (SetCCOpcode) {
14345 default: llvm_unreachable("Unexpected SETCC condition");
14346 case ISD::SETNE: Invert = true;
14347 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
14348 case ISD::SETLT: Swap = true;
14349 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
14350 case ISD::SETGE: Swap = true;
14351 case ISD::SETLE: Opc = X86ISD::PCMPGT;
14352 Invert = true; break;
14353 case ISD::SETULT: Swap = true;
14354 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
14355 FlipSigns = true; break;
14356 case ISD::SETUGE: Swap = true;
14357 case ISD::SETULE: Opc = X86ISD::PCMPGT;
14358 FlipSigns = true; Invert = true; break;
14361 // Special case: Use min/max operations for SETULE/SETUGE
14362 MVT VET = VT.getVectorElementType();
14364 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
14365 || (Subtarget->hasSSE2() && (VET == MVT::i8));
14368 switch (SetCCOpcode) {
14370 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
14371 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
14374 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
14377 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
14378 if (!MinMax && hasSubus) {
14379 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
14381 // t = psubus Op0, Op1
14382 // pcmpeq t, <0..0>
14383 switch (SetCCOpcode) {
14385 case ISD::SETULT: {
14386 // If the comparison is against a constant we can turn this into a
14387 // setule. With psubus, setule does not require a swap. This is
14388 // beneficial because the constant in the register is no longer
14389 // destructed as the destination so it can be hoisted out of a loop.
14390 // Only do this pre-AVX since vpcmp* is no longer destructive.
14391 if (Subtarget->hasAVX())
14393 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
14394 if (ULEOp1.getNode()) {
14396 Subus = true; Invert = false; Swap = false;
14400 // Psubus is better than flip-sign because it requires no inversion.
14401 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
14402 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
14406 Opc = X86ISD::SUBUS;
14412 std::swap(Op0, Op1);
14414 // Check that the operation in question is available (most are plain SSE2,
14415 // but PCMPGTQ and PCMPEQQ have different requirements).
14416 if (VT == MVT::v2i64) {
14417 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
14418 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
14420 // First cast everything to the right type.
14421 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14422 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14424 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14425 // bits of the inputs before performing those operations. The lower
14426 // compare is always unsigned.
14429 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
14431 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
14432 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
14433 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
14434 Sign, Zero, Sign, Zero);
14436 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
14437 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
14439 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
14440 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
14441 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
14443 // Create masks for only the low parts/high parts of the 64 bit integers.
14444 static const int MaskHi[] = { 1, 1, 3, 3 };
14445 static const int MaskLo[] = { 0, 0, 2, 2 };
14446 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
14447 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
14448 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
14450 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
14451 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
14454 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14456 return DAG.getBitcast(VT, Result);
14459 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
14460 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
14461 // pcmpeqd + pshufd + pand.
14462 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
14464 // First cast everything to the right type.
14465 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
14466 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
14469 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
14471 // Make sure the lower and upper halves are both all-ones.
14472 static const int Mask[] = { 1, 0, 3, 2 };
14473 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
14474 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
14477 Result = DAG.getNOT(dl, Result, MVT::v4i32);
14479 return DAG.getBitcast(VT, Result);
14483 // Since SSE has no unsigned integer comparisons, we need to flip the sign
14484 // bits of the inputs before performing those operations.
14486 EVT EltVT = VT.getVectorElementType();
14487 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
14489 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
14490 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
14493 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
14495 // If the logical-not of the result is required, perform that now.
14497 Result = DAG.getNOT(dl, Result, VT);
14500 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
14503 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
14504 getZeroVector(VT, Subtarget, DAG, dl));
14509 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
14511 MVT VT = Op.getSimpleValueType();
14513 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
14515 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
14516 && "SetCC type must be 8-bit or 1-bit integer");
14517 SDValue Op0 = Op.getOperand(0);
14518 SDValue Op1 = Op.getOperand(1);
14520 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
14522 // Optimize to BT if possible.
14523 // Lower (X & (1 << N)) == 0 to BT(X, N).
14524 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
14525 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
14526 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
14527 Op1.getOpcode() == ISD::Constant &&
14528 cast<ConstantSDNode>(Op1)->isNullValue() &&
14529 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14530 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
14531 if (NewSetCC.getNode()) {
14533 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
14538 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
14540 if (Op1.getOpcode() == ISD::Constant &&
14541 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
14542 cast<ConstantSDNode>(Op1)->isNullValue()) &&
14543 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14545 // If the input is a setcc, then reuse the input setcc or use a new one with
14546 // the inverted condition.
14547 if (Op0.getOpcode() == X86ISD::SETCC) {
14548 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
14549 bool Invert = (CC == ISD::SETNE) ^
14550 cast<ConstantSDNode>(Op1)->isNullValue();
14554 CCode = X86::GetOppositeBranchCondition(CCode);
14555 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14556 DAG.getConstant(CCode, dl, MVT::i8),
14557 Op0.getOperand(1));
14559 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14563 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
14564 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
14565 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
14567 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
14568 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
14571 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
14572 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
14573 if (X86CC == X86::COND_INVALID)
14576 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
14577 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
14578 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
14579 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
14581 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
14585 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
14586 static bool isX86LogicalCmp(SDValue Op) {
14587 unsigned Opc = Op.getNode()->getOpcode();
14588 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
14589 Opc == X86ISD::SAHF)
14591 if (Op.getResNo() == 1 &&
14592 (Opc == X86ISD::ADD ||
14593 Opc == X86ISD::SUB ||
14594 Opc == X86ISD::ADC ||
14595 Opc == X86ISD::SBB ||
14596 Opc == X86ISD::SMUL ||
14597 Opc == X86ISD::UMUL ||
14598 Opc == X86ISD::INC ||
14599 Opc == X86ISD::DEC ||
14600 Opc == X86ISD::OR ||
14601 Opc == X86ISD::XOR ||
14602 Opc == X86ISD::AND))
14605 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
14611 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
14612 if (V.getOpcode() != ISD::TRUNCATE)
14615 SDValue VOp0 = V.getOperand(0);
14616 unsigned InBits = VOp0.getValueSizeInBits();
14617 unsigned Bits = V.getValueSizeInBits();
14618 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
14621 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
14622 bool addTest = true;
14623 SDValue Cond = Op.getOperand(0);
14624 SDValue Op1 = Op.getOperand(1);
14625 SDValue Op2 = Op.getOperand(2);
14627 EVT VT = Op1.getValueType();
14630 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
14631 // are available or VBLENDV if AVX is available.
14632 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
14633 if (Cond.getOpcode() == ISD::SETCC &&
14634 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
14635 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
14636 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
14637 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
14638 int SSECC = translateX86FSETCC(
14639 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
14642 if (Subtarget->hasAVX512()) {
14643 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
14644 DAG.getConstant(SSECC, DL, MVT::i8));
14645 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
14648 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
14649 DAG.getConstant(SSECC, DL, MVT::i8));
14651 // If we have AVX, we can use a variable vector select (VBLENDV) instead
14652 // of 3 logic instructions for size savings and potentially speed.
14653 // Unfortunately, there is no scalar form of VBLENDV.
14655 // If either operand is a constant, don't try this. We can expect to
14656 // optimize away at least one of the logic instructions later in that
14657 // case, so that sequence would be faster than a variable blend.
14659 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
14660 // uses XMM0 as the selection register. That may need just as many
14661 // instructions as the AND/ANDN/OR sequence due to register moves, so
14664 if (Subtarget->hasAVX() &&
14665 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
14667 // Convert to vectors, do a VSELECT, and convert back to scalar.
14668 // All of the conversions should be optimized away.
14670 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
14671 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
14672 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
14673 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
14675 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
14676 VCmp = DAG.getBitcast(VCmpVT, VCmp);
14678 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
14680 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
14681 VSel, DAG.getIntPtrConstant(0, DL));
14683 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
14684 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
14685 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
14689 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
14691 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
14692 Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
14693 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
14694 Op1Scalar = Op1.getOperand(0);
14696 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
14697 Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
14698 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
14699 Op2Scalar = Op2.getOperand(0);
14700 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
14701 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
14702 Op1Scalar.getValueType(),
14703 Cond, Op1Scalar, Op2Scalar);
14704 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
14705 return DAG.getBitcast(VT, newSelect);
14706 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
14707 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
14708 DAG.getIntPtrConstant(0, DL));
14712 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
14713 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
14714 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14715 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
14716 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
14717 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
14718 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
14720 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
14723 if (Cond.getOpcode() == ISD::SETCC) {
14724 SDValue NewCond = LowerSETCC(Cond, DAG);
14725 if (NewCond.getNode())
14729 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
14730 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
14731 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
14732 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
14733 if (Cond.getOpcode() == X86ISD::SETCC &&
14734 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
14735 isZero(Cond.getOperand(1).getOperand(1))) {
14736 SDValue Cmp = Cond.getOperand(1);
14738 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
14740 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
14741 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
14742 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
14744 SDValue CmpOp0 = Cmp.getOperand(0);
14745 // Apply further optimizations for special cases
14746 // (select (x != 0), -1, 0) -> neg & sbb
14747 // (select (x == 0), 0, -1) -> neg & sbb
14748 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
14749 if (YC->isNullValue() &&
14750 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
14751 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
14752 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
14753 DAG.getConstant(0, DL,
14754 CmpOp0.getValueType()),
14756 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14757 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14758 SDValue(Neg.getNode(), 1));
14762 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
14763 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
14764 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14766 SDValue Res = // Res = 0 or -1.
14767 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14768 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
14770 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
14771 Res = DAG.getNOT(DL, Res, Res.getValueType());
14773 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
14774 if (!N2C || !N2C->isNullValue())
14775 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14780 // Look past (and (setcc_carry (cmp ...)), 1).
14781 if (Cond.getOpcode() == ISD::AND &&
14782 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14783 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14784 if (C && C->getAPIntValue() == 1)
14785 Cond = Cond.getOperand(0);
14788 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14789 // setting operand in place of the X86ISD::SETCC.
14790 unsigned CondOpcode = Cond.getOpcode();
14791 if (CondOpcode == X86ISD::SETCC ||
14792 CondOpcode == X86ISD::SETCC_CARRY) {
14793 CC = Cond.getOperand(0);
14795 SDValue Cmp = Cond.getOperand(1);
14796 unsigned Opc = Cmp.getOpcode();
14797 MVT VT = Op.getSimpleValueType();
14799 bool IllegalFPCMov = false;
14800 if (VT.isFloatingPoint() && !VT.isVector() &&
14801 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14802 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14804 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14805 Opc == X86ISD::BT) { // FIXME
14809 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14810 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14811 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14812 Cond.getOperand(0).getValueType() != MVT::i8)) {
14813 SDValue LHS = Cond.getOperand(0);
14814 SDValue RHS = Cond.getOperand(1);
14815 unsigned X86Opcode;
14818 switch (CondOpcode) {
14819 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14820 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14821 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14822 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14823 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14824 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14825 default: llvm_unreachable("unexpected overflowing operator");
14827 if (CondOpcode == ISD::UMULO)
14828 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14831 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14833 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14835 if (CondOpcode == ISD::UMULO)
14836 Cond = X86Op.getValue(2);
14838 Cond = X86Op.getValue(1);
14840 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14845 // Look past the truncate if the high bits are known zero.
14846 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14847 Cond = Cond.getOperand(0);
14849 // We know the result of AND is compared against zero. Try to match
14851 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14852 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14853 if (NewSetCC.getNode()) {
14854 CC = NewSetCC.getOperand(0);
14855 Cond = NewSetCC.getOperand(1);
14862 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14863 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14866 // a < b ? -1 : 0 -> RES = ~setcc_carry
14867 // a < b ? 0 : -1 -> RES = setcc_carry
14868 // a >= b ? -1 : 0 -> RES = setcc_carry
14869 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14870 if (Cond.getOpcode() == X86ISD::SUB) {
14871 Cond = ConvertCmpIfNecessary(Cond, DAG);
14872 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14874 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14875 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14876 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14877 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14879 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14880 return DAG.getNOT(DL, Res, Res.getValueType());
14885 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14886 // widen the cmov and push the truncate through. This avoids introducing a new
14887 // branch during isel and doesn't add any extensions.
14888 if (Op.getValueType() == MVT::i8 &&
14889 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14890 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14891 if (T1.getValueType() == T2.getValueType() &&
14892 // Blacklist CopyFromReg to avoid partial register stalls.
14893 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14894 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14895 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14896 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14900 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14901 // condition is true.
14902 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14903 SDValue Ops[] = { Op2, Op1, CC, Cond };
14904 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14907 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14908 const X86Subtarget *Subtarget,
14909 SelectionDAG &DAG) {
14910 MVT VT = Op->getSimpleValueType(0);
14911 SDValue In = Op->getOperand(0);
14912 MVT InVT = In.getSimpleValueType();
14913 MVT VTElt = VT.getVectorElementType();
14914 MVT InVTElt = InVT.getVectorElementType();
14918 if ((InVTElt == MVT::i1) &&
14919 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14920 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14922 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14923 VTElt.getSizeInBits() <= 16)) ||
14925 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14926 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14928 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14929 VTElt.getSizeInBits() >= 32))))
14930 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14932 unsigned int NumElts = VT.getVectorNumElements();
14934 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14937 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14938 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14939 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14940 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14943 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14944 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14946 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14949 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14951 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14952 if (VT.is512BitVector())
14954 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14957 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14958 const X86Subtarget *Subtarget,
14959 SelectionDAG &DAG) {
14960 SDValue In = Op->getOperand(0);
14961 MVT VT = Op->getSimpleValueType(0);
14962 MVT InVT = In.getSimpleValueType();
14963 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14965 MVT InSVT = InVT.getScalarType();
14966 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14968 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14970 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14975 // SSE41 targets can use the pmovsx* instructions directly.
14976 if (Subtarget->hasSSE41())
14977 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14979 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14983 // As SRAI is only available on i16/i32 types, we expand only up to i32
14984 // and handle i64 separately.
14985 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14986 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14987 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14988 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14989 Curr = DAG.getBitcast(CurrVT, Curr);
14992 SDValue SignExt = Curr;
14993 if (CurrVT != InVT) {
14994 unsigned SignExtShift =
14995 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14996 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14997 DAG.getConstant(SignExtShift, dl, MVT::i8));
15003 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
15004 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
15005 DAG.getConstant(31, dl, MVT::i8));
15006 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
15007 return DAG.getBitcast(VT, Ext);
15013 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
15014 SelectionDAG &DAG) {
15015 MVT VT = Op->getSimpleValueType(0);
15016 SDValue In = Op->getOperand(0);
15017 MVT InVT = In.getSimpleValueType();
15020 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
15021 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
15023 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
15024 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
15025 (VT != MVT::v16i16 || InVT != MVT::v16i8))
15028 if (Subtarget->hasInt256())
15029 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
15031 // Optimize vectors in AVX mode
15032 // Sign extend v8i16 to v8i32 and
15035 // Divide input vector into two parts
15036 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
15037 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
15038 // concat the vectors to original VT
15040 unsigned NumElems = InVT.getVectorNumElements();
15041 SDValue Undef = DAG.getUNDEF(InVT);
15043 SmallVector<int,8> ShufMask1(NumElems, -1);
15044 for (unsigned i = 0; i != NumElems/2; ++i)
15047 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
15049 SmallVector<int,8> ShufMask2(NumElems, -1);
15050 for (unsigned i = 0; i != NumElems/2; ++i)
15051 ShufMask2[i] = i + NumElems/2;
15053 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
15055 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
15056 VT.getVectorNumElements()/2);
15058 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
15059 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
15061 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
15064 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
15065 // may emit an illegal shuffle but the expansion is still better than scalar
15066 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
15067 // we'll emit a shuffle and a arithmetic shift.
15068 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
15069 // TODO: It is possible to support ZExt by zeroing the undef values during
15070 // the shuffle phase or after the shuffle.
15071 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
15072 SelectionDAG &DAG) {
15073 MVT RegVT = Op.getSimpleValueType();
15074 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
15075 assert(RegVT.isInteger() &&
15076 "We only custom lower integer vector sext loads.");
15078 // Nothing useful we can do without SSE2 shuffles.
15079 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
15081 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
15083 EVT MemVT = Ld->getMemoryVT();
15084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15085 unsigned RegSz = RegVT.getSizeInBits();
15087 ISD::LoadExtType Ext = Ld->getExtensionType();
15089 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
15090 && "Only anyext and sext are currently implemented.");
15091 assert(MemVT != RegVT && "Cannot extend to the same type");
15092 assert(MemVT.isVector() && "Must load a vector from memory");
15094 unsigned NumElems = RegVT.getVectorNumElements();
15095 unsigned MemSz = MemVT.getSizeInBits();
15096 assert(RegSz > MemSz && "Register size must be greater than the mem size");
15098 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
15099 // The only way in which we have a legal 256-bit vector result but not the
15100 // integer 256-bit operations needed to directly lower a sextload is if we
15101 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
15102 // a 128-bit vector and a normal sign_extend to 256-bits that should get
15103 // correctly legalized. We do this late to allow the canonical form of
15104 // sextload to persist throughout the rest of the DAG combiner -- it wants
15105 // to fold together any extensions it can, and so will fuse a sign_extend
15106 // of an sextload into a sextload targeting a wider value.
15108 if (MemSz == 128) {
15109 // Just switch this to a normal load.
15110 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
15111 "it must be a legal 128-bit vector "
15113 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
15114 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
15115 Ld->isInvariant(), Ld->getAlignment());
15117 assert(MemSz < 128 &&
15118 "Can't extend a type wider than 128 bits to a 256 bit vector!");
15119 // Do an sext load to a 128-bit vector type. We want to use the same
15120 // number of elements, but elements half as wide. This will end up being
15121 // recursively lowered by this routine, but will succeed as we definitely
15122 // have all the necessary features if we're using AVX1.
15124 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
15125 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
15127 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
15128 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
15129 Ld->isNonTemporal(), Ld->isInvariant(),
15130 Ld->getAlignment());
15133 // Replace chain users with the new chain.
15134 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
15135 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
15137 // Finally, do a normal sign-extend to the desired register.
15138 return DAG.getSExtOrTrunc(Load, dl, RegVT);
15141 // All sizes must be a power of two.
15142 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
15143 "Non-power-of-two elements are not custom lowered!");
15145 // Attempt to load the original value using scalar loads.
15146 // Find the largest scalar type that divides the total loaded size.
15147 MVT SclrLoadTy = MVT::i8;
15148 for (MVT Tp : MVT::integer_valuetypes()) {
15149 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
15154 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
15155 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
15157 SclrLoadTy = MVT::f64;
15159 // Calculate the number of scalar loads that we need to perform
15160 // in order to load our vector from memory.
15161 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
15163 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
15164 "Can only lower sext loads with a single scalar load!");
15166 unsigned loadRegZize = RegSz;
15167 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
15170 // Represent our vector as a sequence of elements which are the
15171 // largest scalar that we can load.
15172 EVT LoadUnitVecVT = EVT::getVectorVT(
15173 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
15175 // Represent the data using the same element type that is stored in
15176 // memory. In practice, we ''widen'' MemVT.
15178 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
15179 loadRegZize / MemVT.getScalarType().getSizeInBits());
15181 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
15182 "Invalid vector type");
15184 // We can't shuffle using an illegal type.
15185 assert(TLI.isTypeLegal(WideVecVT) &&
15186 "We only lower types that form legal widened vector types");
15188 SmallVector<SDValue, 8> Chains;
15189 SDValue Ptr = Ld->getBasePtr();
15190 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl,
15191 TLI.getPointerTy(DAG.getDataLayout()));
15192 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
15194 for (unsigned i = 0; i < NumLoads; ++i) {
15195 // Perform a single load.
15196 SDValue ScalarLoad =
15197 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
15198 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
15199 Ld->getAlignment());
15200 Chains.push_back(ScalarLoad.getValue(1));
15201 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
15202 // another round of DAGCombining.
15204 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
15206 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
15207 ScalarLoad, DAG.getIntPtrConstant(i, dl));
15209 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
15212 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
15214 // Bitcast the loaded value to a vector of the original element type, in
15215 // the size of the target vector type.
15216 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
15217 unsigned SizeRatio = RegSz / MemSz;
15219 if (Ext == ISD::SEXTLOAD) {
15220 // If we have SSE4.1, we can directly emit a VSEXT node.
15221 if (Subtarget->hasSSE41()) {
15222 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
15223 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15227 // Otherwise we'll use SIGN_EXTEND_VECTOR_INREG to sign extend the lowest
15229 assert(TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND_VECTOR_INREG, RegVT) &&
15230 "We can't implement a sext load without SIGN_EXTEND_VECTOR_INREG!");
15232 SDValue Shuff = DAG.getSignExtendVectorInReg(SlicedVec, dl, RegVT);
15233 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15237 // Redistribute the loaded elements into the different locations.
15238 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
15239 for (unsigned i = 0; i != NumElems; ++i)
15240 ShuffleVec[i * SizeRatio] = i;
15242 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
15243 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
15245 // Bitcast to the requested type.
15246 Shuff = DAG.getBitcast(RegVT, Shuff);
15247 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
15251 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
15252 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
15253 // from the AND / OR.
15254 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
15255 Opc = Op.getOpcode();
15256 if (Opc != ISD::OR && Opc != ISD::AND)
15258 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15259 Op.getOperand(0).hasOneUse() &&
15260 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
15261 Op.getOperand(1).hasOneUse());
15264 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
15265 // 1 and that the SETCC node has a single use.
15266 static bool isXor1OfSetCC(SDValue Op) {
15267 if (Op.getOpcode() != ISD::XOR)
15269 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
15270 if (N1C && N1C->getAPIntValue() == 1) {
15271 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
15272 Op.getOperand(0).hasOneUse();
15277 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
15278 bool addTest = true;
15279 SDValue Chain = Op.getOperand(0);
15280 SDValue Cond = Op.getOperand(1);
15281 SDValue Dest = Op.getOperand(2);
15284 bool Inverted = false;
15286 if (Cond.getOpcode() == ISD::SETCC) {
15287 // Check for setcc([su]{add,sub,mul}o == 0).
15288 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
15289 isa<ConstantSDNode>(Cond.getOperand(1)) &&
15290 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
15291 Cond.getOperand(0).getResNo() == 1 &&
15292 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
15293 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
15294 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
15295 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
15296 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
15297 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
15299 Cond = Cond.getOperand(0);
15301 SDValue NewCond = LowerSETCC(Cond, DAG);
15302 if (NewCond.getNode())
15307 // FIXME: LowerXALUO doesn't handle these!!
15308 else if (Cond.getOpcode() == X86ISD::ADD ||
15309 Cond.getOpcode() == X86ISD::SUB ||
15310 Cond.getOpcode() == X86ISD::SMUL ||
15311 Cond.getOpcode() == X86ISD::UMUL)
15312 Cond = LowerXALUO(Cond, DAG);
15315 // Look pass (and (setcc_carry (cmp ...)), 1).
15316 if (Cond.getOpcode() == ISD::AND &&
15317 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
15318 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
15319 if (C && C->getAPIntValue() == 1)
15320 Cond = Cond.getOperand(0);
15323 // If condition flag is set by a X86ISD::CMP, then use it as the condition
15324 // setting operand in place of the X86ISD::SETCC.
15325 unsigned CondOpcode = Cond.getOpcode();
15326 if (CondOpcode == X86ISD::SETCC ||
15327 CondOpcode == X86ISD::SETCC_CARRY) {
15328 CC = Cond.getOperand(0);
15330 SDValue Cmp = Cond.getOperand(1);
15331 unsigned Opc = Cmp.getOpcode();
15332 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
15333 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
15337 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
15341 // These can only come from an arithmetic instruction with overflow,
15342 // e.g. SADDO, UADDO.
15343 Cond = Cond.getNode()->getOperand(1);
15349 CondOpcode = Cond.getOpcode();
15350 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
15351 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
15352 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
15353 Cond.getOperand(0).getValueType() != MVT::i8)) {
15354 SDValue LHS = Cond.getOperand(0);
15355 SDValue RHS = Cond.getOperand(1);
15356 unsigned X86Opcode;
15359 // Keep this in sync with LowerXALUO, otherwise we might create redundant
15360 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
15362 switch (CondOpcode) {
15363 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
15365 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15367 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
15370 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
15371 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
15373 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
15375 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
15378 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
15379 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
15380 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
15381 default: llvm_unreachable("unexpected overflowing operator");
15384 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
15385 if (CondOpcode == ISD::UMULO)
15386 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
15389 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
15391 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
15393 if (CondOpcode == ISD::UMULO)
15394 Cond = X86Op.getValue(2);
15396 Cond = X86Op.getValue(1);
15398 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15402 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
15403 SDValue Cmp = Cond.getOperand(0).getOperand(1);
15404 if (CondOpc == ISD::OR) {
15405 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
15406 // two branches instead of an explicit OR instruction with a
15408 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15409 isX86LogicalCmp(Cmp)) {
15410 CC = Cond.getOperand(0).getOperand(0);
15411 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15412 Chain, Dest, CC, Cmp);
15413 CC = Cond.getOperand(1).getOperand(0);
15417 } else { // ISD::AND
15418 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
15419 // two branches instead of an explicit AND instruction with a
15420 // separate test. However, we only do this if this block doesn't
15421 // have a fall-through edge, because this requires an explicit
15422 // jmp when the condition is false.
15423 if (Cmp == Cond.getOperand(1).getOperand(1) &&
15424 isX86LogicalCmp(Cmp) &&
15425 Op.getNode()->hasOneUse()) {
15426 X86::CondCode CCode =
15427 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15428 CCode = X86::GetOppositeBranchCondition(CCode);
15429 CC = DAG.getConstant(CCode, dl, MVT::i8);
15430 SDNode *User = *Op.getNode()->use_begin();
15431 // Look for an unconditional branch following this conditional branch.
15432 // We need this because we need to reverse the successors in order
15433 // to implement FCMP_OEQ.
15434 if (User->getOpcode() == ISD::BR) {
15435 SDValue FalseBB = User->getOperand(1);
15437 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15438 assert(NewBR == User);
15442 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15443 Chain, Dest, CC, Cmp);
15444 X86::CondCode CCode =
15445 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
15446 CCode = X86::GetOppositeBranchCondition(CCode);
15447 CC = DAG.getConstant(CCode, dl, MVT::i8);
15453 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
15454 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
15455 // It should be transformed during dag combiner except when the condition
15456 // is set by a arithmetics with overflow node.
15457 X86::CondCode CCode =
15458 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
15459 CCode = X86::GetOppositeBranchCondition(CCode);
15460 CC = DAG.getConstant(CCode, dl, MVT::i8);
15461 Cond = Cond.getOperand(0).getOperand(1);
15463 } else if (Cond.getOpcode() == ISD::SETCC &&
15464 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
15465 // For FCMP_OEQ, we can emit
15466 // two branches instead of an explicit AND instruction with a
15467 // separate test. However, we only do this if this block doesn't
15468 // have a fall-through edge, because this requires an explicit
15469 // jmp when the condition is false.
15470 if (Op.getNode()->hasOneUse()) {
15471 SDNode *User = *Op.getNode()->use_begin();
15472 // Look for an unconditional branch following this conditional branch.
15473 // We need this because we need to reverse the successors in order
15474 // to implement FCMP_OEQ.
15475 if (User->getOpcode() == ISD::BR) {
15476 SDValue FalseBB = User->getOperand(1);
15478 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15479 assert(NewBR == User);
15483 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15484 Cond.getOperand(0), Cond.getOperand(1));
15485 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15486 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15487 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15488 Chain, Dest, CC, Cmp);
15489 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
15494 } else if (Cond.getOpcode() == ISD::SETCC &&
15495 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
15496 // For FCMP_UNE, we can emit
15497 // two branches instead of an explicit AND instruction with a
15498 // separate test. However, we only do this if this block doesn't
15499 // have a fall-through edge, because this requires an explicit
15500 // jmp when the condition is false.
15501 if (Op.getNode()->hasOneUse()) {
15502 SDNode *User = *Op.getNode()->use_begin();
15503 // Look for an unconditional branch following this conditional branch.
15504 // We need this because we need to reverse the successors in order
15505 // to implement FCMP_UNE.
15506 if (User->getOpcode() == ISD::BR) {
15507 SDValue FalseBB = User->getOperand(1);
15509 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
15510 assert(NewBR == User);
15513 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
15514 Cond.getOperand(0), Cond.getOperand(1));
15515 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
15516 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
15517 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15518 Chain, Dest, CC, Cmp);
15519 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
15529 // Look pass the truncate if the high bits are known zero.
15530 if (isTruncWithZeroHighBitsInput(Cond, DAG))
15531 Cond = Cond.getOperand(0);
15533 // We know the result of AND is compared against zero. Try to match
15535 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
15536 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
15537 if (NewSetCC.getNode()) {
15538 CC = NewSetCC.getOperand(0);
15539 Cond = NewSetCC.getOperand(1);
15546 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
15547 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
15548 Cond = EmitTest(Cond, X86Cond, dl, DAG);
15550 Cond = ConvertCmpIfNecessary(Cond, DAG);
15551 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
15552 Chain, Dest, CC, Cond);
15555 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
15556 // Calls to _alloca are needed to probe the stack when allocating more than 4k
15557 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
15558 // that the guard pages used by the OS virtual memory manager are allocated in
15559 // correct sequence.
15561 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
15562 SelectionDAG &DAG) const {
15563 MachineFunction &MF = DAG.getMachineFunction();
15564 bool SplitStack = MF.shouldSplitStack();
15565 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
15570 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15571 SDNode* Node = Op.getNode();
15573 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
15574 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
15575 " not tell us which reg is the stack pointer!");
15576 EVT VT = Node->getValueType(0);
15577 SDValue Tmp1 = SDValue(Node, 0);
15578 SDValue Tmp2 = SDValue(Node, 1);
15579 SDValue Tmp3 = Node->getOperand(2);
15580 SDValue Chain = Tmp1.getOperand(0);
15582 // Chain the dynamic stack allocation so that it doesn't modify the stack
15583 // pointer when other instructions are using the stack.
15584 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
15587 SDValue Size = Tmp2.getOperand(1);
15588 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
15589 Chain = SP.getValue(1);
15590 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
15591 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
15592 unsigned StackAlign = TFI.getStackAlignment();
15593 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
15594 if (Align > StackAlign)
15595 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
15596 DAG.getConstant(-(uint64_t)Align, dl, VT));
15597 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
15599 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
15600 DAG.getIntPtrConstant(0, dl, true), SDValue(),
15603 SDValue Ops[2] = { Tmp1, Tmp2 };
15604 return DAG.getMergeValues(Ops, dl);
15608 SDValue Chain = Op.getOperand(0);
15609 SDValue Size = Op.getOperand(1);
15610 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
15611 EVT VT = Op.getNode()->getValueType(0);
15613 bool Is64Bit = Subtarget->is64Bit();
15614 MVT SPTy = getPointerTy(DAG.getDataLayout());
15617 MachineRegisterInfo &MRI = MF.getRegInfo();
15620 // The 64 bit implementation of segmented stacks needs to clobber both r10
15621 // r11. This makes it impossible to use it along with nested parameters.
15622 const Function *F = MF.getFunction();
15624 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
15626 if (I->hasNestAttr())
15627 report_fatal_error("Cannot use segmented stacks with functions that "
15628 "have nested arguments.");
15631 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
15632 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
15633 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
15634 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
15635 DAG.getRegister(Vreg, SPTy));
15636 SDValue Ops1[2] = { Value, Chain };
15637 return DAG.getMergeValues(Ops1, dl);
15640 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
15642 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
15643 Flag = Chain.getValue(1);
15644 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
15646 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
15648 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15649 unsigned SPReg = RegInfo->getStackRegister();
15650 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
15651 Chain = SP.getValue(1);
15654 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
15655 DAG.getConstant(-(uint64_t)Align, dl, VT));
15656 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
15659 SDValue Ops1[2] = { SP, Chain };
15660 return DAG.getMergeValues(Ops1, dl);
15664 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
15665 MachineFunction &MF = DAG.getMachineFunction();
15666 auto PtrVT = getPointerTy(MF.getDataLayout());
15667 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15669 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15672 if (!Subtarget->is64Bit() ||
15673 Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv())) {
15674 // vastart just stores the address of the VarArgsFrameIndex slot into the
15675 // memory location argument.
15676 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15677 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
15678 MachinePointerInfo(SV), false, false, 0);
15682 // gp_offset (0 - 6 * 8)
15683 // fp_offset (48 - 48 + 8 * 16)
15684 // overflow_arg_area (point to parameters coming in memory).
15686 SmallVector<SDValue, 8> MemOps;
15687 SDValue FIN = Op.getOperand(1);
15689 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
15690 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
15692 FIN, MachinePointerInfo(SV), false, false, 0);
15693 MemOps.push_back(Store);
15696 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15697 Store = DAG.getStore(Op.getOperand(0), DL,
15698 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
15700 FIN, MachinePointerInfo(SV, 4), false, false, 0);
15701 MemOps.push_back(Store);
15703 // Store ptr to overflow_arg_area
15704 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4, DL));
15705 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
15706 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
15707 MachinePointerInfo(SV, 8),
15709 MemOps.push_back(Store);
15711 // Store ptr to reg_save_area.
15712 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(
15713 Subtarget->isTarget64BitLP64() ? 8 : 4, DL));
15714 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT);
15715 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, MachinePointerInfo(
15716 SV, Subtarget->isTarget64BitLP64() ? 16 : 12), false, false, 0);
15717 MemOps.push_back(Store);
15718 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
15721 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
15722 assert(Subtarget->is64Bit() &&
15723 "LowerVAARG only handles 64-bit va_arg!");
15724 assert(Op.getNode()->getNumOperands() == 4);
15726 MachineFunction &MF = DAG.getMachineFunction();
15727 if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
15728 // The Win64 ABI uses char* instead of a structure.
15729 return DAG.expandVAArg(Op.getNode());
15731 SDValue Chain = Op.getOperand(0);
15732 SDValue SrcPtr = Op.getOperand(1);
15733 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
15734 unsigned Align = Op.getConstantOperandVal(3);
15737 EVT ArgVT = Op.getNode()->getValueType(0);
15738 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
15739 uint32_t ArgSize = DAG.getDataLayout().getTypeAllocSize(ArgTy);
15742 // Decide which area this value should be read from.
15743 // TODO: Implement the AMD64 ABI in its entirety. This simple
15744 // selection mechanism works only for the basic types.
15745 if (ArgVT == MVT::f80) {
15746 llvm_unreachable("va_arg for f80 not yet implemented");
15747 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
15748 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
15749 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
15750 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
15752 llvm_unreachable("Unhandled argument type in LowerVAARG");
15755 if (ArgMode == 2) {
15756 // Sanity Check: Make sure using fp_offset makes sense.
15757 assert(!Subtarget->useSoftFloat() &&
15758 !(MF.getFunction()->hasFnAttribute(Attribute::NoImplicitFloat)) &&
15759 Subtarget->hasSSE1());
15762 // Insert VAARG_64 node into the DAG
15763 // VAARG_64 returns two values: Variable Argument Address, Chain
15764 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15765 DAG.getConstant(ArgMode, dl, MVT::i8),
15766 DAG.getConstant(Align, dl, MVT::i32)};
15767 SDVTList VTs = DAG.getVTList(getPointerTy(DAG.getDataLayout()), MVT::Other);
15768 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15769 VTs, InstOps, MVT::i64,
15770 MachinePointerInfo(SV),
15772 /*Volatile=*/false,
15774 /*WriteMem=*/true);
15775 Chain = VAARG.getValue(1);
15777 // Load the next argument and return it
15778 return DAG.getLoad(ArgVT, dl,
15781 MachinePointerInfo(),
15782 false, false, false, 0);
15785 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15786 SelectionDAG &DAG) {
15787 // X86-64 va_list is a struct { i32, i32, i8*, i8* }, except on Windows,
15788 // where a va_list is still an i8*.
15789 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15790 if (Subtarget->isCallingConvWin64(
15791 DAG.getMachineFunction().getFunction()->getCallingConv()))
15792 // Probably a Win64 va_copy.
15793 return DAG.expandVACopy(Op.getNode());
15795 SDValue Chain = Op.getOperand(0);
15796 SDValue DstPtr = Op.getOperand(1);
15797 SDValue SrcPtr = Op.getOperand(2);
15798 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15799 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15802 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15803 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15805 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15808 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15809 // amount is a constant. Takes immediate version of shift as input.
15810 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15811 SDValue SrcOp, uint64_t ShiftAmt,
15812 SelectionDAG &DAG) {
15813 MVT ElementType = VT.getVectorElementType();
15815 // Fold this packed shift into its first operand if ShiftAmt is 0.
15819 // Check for ShiftAmt >= element width
15820 if (ShiftAmt >= ElementType.getSizeInBits()) {
15821 if (Opc == X86ISD::VSRAI)
15822 ShiftAmt = ElementType.getSizeInBits() - 1;
15824 return DAG.getConstant(0, dl, VT);
15827 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15828 && "Unknown target vector shift-by-constant node");
15830 // Fold this packed vector shift into a build vector if SrcOp is a
15831 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15832 if (VT == SrcOp.getSimpleValueType() &&
15833 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15834 SmallVector<SDValue, 8> Elts;
15835 unsigned NumElts = SrcOp->getNumOperands();
15836 ConstantSDNode *ND;
15839 default: llvm_unreachable(nullptr);
15840 case X86ISD::VSHLI:
15841 for (unsigned i=0; i!=NumElts; ++i) {
15842 SDValue CurrentOp = SrcOp->getOperand(i);
15843 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15844 Elts.push_back(CurrentOp);
15847 ND = cast<ConstantSDNode>(CurrentOp);
15848 const APInt &C = ND->getAPIntValue();
15849 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15852 case X86ISD::VSRLI:
15853 for (unsigned i=0; i!=NumElts; ++i) {
15854 SDValue CurrentOp = SrcOp->getOperand(i);
15855 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15856 Elts.push_back(CurrentOp);
15859 ND = cast<ConstantSDNode>(CurrentOp);
15860 const APInt &C = ND->getAPIntValue();
15861 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15864 case X86ISD::VSRAI:
15865 for (unsigned i=0; i!=NumElts; ++i) {
15866 SDValue CurrentOp = SrcOp->getOperand(i);
15867 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15868 Elts.push_back(CurrentOp);
15871 ND = cast<ConstantSDNode>(CurrentOp);
15872 const APInt &C = ND->getAPIntValue();
15873 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15878 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15881 return DAG.getNode(Opc, dl, VT, SrcOp,
15882 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15885 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15886 // may or may not be a constant. Takes immediate version of shift as input.
15887 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15888 SDValue SrcOp, SDValue ShAmt,
15889 SelectionDAG &DAG) {
15890 MVT SVT = ShAmt.getSimpleValueType();
15891 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15893 // Catch shift-by-constant.
15894 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15895 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15896 CShAmt->getZExtValue(), DAG);
15898 // Change opcode to non-immediate version
15900 default: llvm_unreachable("Unknown target vector shift node");
15901 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15902 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15903 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15906 const X86Subtarget &Subtarget =
15907 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15908 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15909 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15910 // Let the shuffle legalizer expand this shift amount node.
15911 SDValue Op0 = ShAmt.getOperand(0);
15912 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15913 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15915 // Need to build a vector containing shift amount.
15916 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15917 SmallVector<SDValue, 4> ShOps;
15918 ShOps.push_back(ShAmt);
15919 if (SVT == MVT::i32) {
15920 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15921 ShOps.push_back(DAG.getUNDEF(SVT));
15923 ShOps.push_back(DAG.getUNDEF(SVT));
15925 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15926 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15929 // The return type has to be a 128-bit type with the same element
15930 // type as the input type.
15931 MVT EltVT = VT.getVectorElementType();
15932 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15934 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15935 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15938 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15939 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15940 /// necessary casting or extending for \p Mask when lowering masking intrinsics
15941 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15942 SDValue PreservedSrc,
15943 const X86Subtarget *Subtarget,
15944 SelectionDAG &DAG) {
15945 EVT VT = Op.getValueType();
15946 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15947 MVT::i1, VT.getVectorNumElements());
15948 SDValue VMask = SDValue();
15949 unsigned OpcodeSelect = ISD::VSELECT;
15952 assert(MaskVT.isSimple() && "invalid mask type");
15954 if (isAllOnes(Mask))
15957 if (MaskVT.bitsGT(Mask.getValueType())) {
15958 EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),
15959 MaskVT.getSizeInBits());
15960 VMask = DAG.getBitcast(MaskVT,
15961 DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));
15963 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15964 Mask.getValueType().getSizeInBits());
15965 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15966 // are extracted by EXTRACT_SUBVECTOR.
15967 VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15968 DAG.getBitcast(BitcastVT, Mask),
15969 DAG.getIntPtrConstant(0, dl));
15972 switch (Op.getOpcode()) {
15974 case X86ISD::PCMPEQM:
15975 case X86ISD::PCMPGTM:
15977 case X86ISD::CMPMU:
15978 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15979 case X86ISD::VFPCLASS:
15980 return DAG.getNode(ISD::OR, dl, VT, Op, VMask);
15981 case X86ISD::VTRUNC:
15982 case X86ISD::VTRUNCS:
15983 case X86ISD::VTRUNCUS:
15984 // We can't use ISD::VSELECT here because it is not always "Legal"
15985 // for the destination type. For example vpmovqb require only AVX512
15986 // and vselect that can operate on byte element type require BWI
15987 OpcodeSelect = X86ISD::SELECT;
15990 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15991 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15992 return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);
15995 /// \brief Creates an SDNode for a predicated scalar operation.
15996 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15997 /// The mask is coming as MVT::i8 and it should be truncated
15998 /// to MVT::i1 while lowering masking intrinsics.
15999 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
16000 /// "X86select" instead of "vselect". We just can't create the "vselect" node
16001 /// for a scalar instruction.
16002 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
16003 SDValue PreservedSrc,
16004 const X86Subtarget *Subtarget,
16005 SelectionDAG &DAG) {
16006 if (isAllOnes(Mask))
16009 EVT VT = Op.getValueType();
16011 // The mask should be of type MVT::i1
16012 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
16014 if (Op.getOpcode() == X86ISD::FSETCC)
16015 return DAG.getNode(ISD::AND, dl, VT, Op, IMask);
16016 if (Op.getOpcode() == X86ISD::VFPCLASS)
16017 return DAG.getNode(ISD::OR, dl, VT, Op, IMask);
16019 if (PreservedSrc.getOpcode() == ISD::UNDEF)
16020 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
16021 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
16024 static int getSEHRegistrationNodeSize(const Function *Fn) {
16025 if (!Fn->hasPersonalityFn())
16026 report_fatal_error(
16027 "querying registration node size for function without personality");
16028 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
16029 // WinEHStatePass for the full struct definition.
16030 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
16031 case EHPersonality::MSVC_X86SEH: return 24;
16032 case EHPersonality::MSVC_CXX: return 16;
16035 report_fatal_error("can only recover FP for MSVC EH personality functions");
16038 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
16039 /// function or when returning to a parent frame after catching an exception, we
16040 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
16041 /// Here's the math:
16042 /// RegNodeBase = EntryEBP - RegNodeSize
16043 /// ParentFP = RegNodeBase - RegNodeFrameOffset
16044 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
16045 /// subtracting the offset (negative on x86) takes us back to the parent FP.
16046 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
16047 SDValue EntryEBP) {
16048 MachineFunction &MF = DAG.getMachineFunction();
16051 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16052 MVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
16054 // It's possible that the parent function no longer has a personality function
16055 // if the exceptional code was optimized away, in which case we just return
16056 // the incoming EBP.
16057 if (!Fn->hasPersonalityFn())
16060 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16062 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
16064 MCSymbol *OffsetSym =
16065 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
16066 GlobalValue::getRealLinkageName(Fn->getName()));
16067 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
16068 SDValue RegNodeFrameOffset =
16069 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
16071 // RegNodeBase = EntryEBP - RegNodeSize
16072 // ParentFP = RegNodeBase - RegNodeFrameOffset
16073 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
16074 DAG.getConstant(RegNodeSize, dl, PtrVT));
16075 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
16078 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
16079 SelectionDAG &DAG) {
16081 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16082 EVT VT = Op.getValueType();
16083 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
16085 switch(IntrData->Type) {
16086 case INTR_TYPE_1OP:
16087 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
16088 case INTR_TYPE_2OP:
16089 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16091 case INTR_TYPE_2OP_IMM8:
16092 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16093 DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(2)));
16094 case INTR_TYPE_3OP:
16095 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16096 Op.getOperand(2), Op.getOperand(3));
16097 case INTR_TYPE_4OP:
16098 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
16099 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
16100 case INTR_TYPE_1OP_MASK_RM: {
16101 SDValue Src = Op.getOperand(1);
16102 SDValue PassThru = Op.getOperand(2);
16103 SDValue Mask = Op.getOperand(3);
16104 SDValue RoundingMode;
16105 // We allways add rounding mode to the Node.
16106 // If the rounding mode is not specified, we add the
16107 // "current direction" mode.
16108 if (Op.getNumOperands() == 4)
16110 DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16112 RoundingMode = Op.getOperand(4);
16113 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16114 if (IntrWithRoundingModeOpcode != 0)
16115 if (cast<ConstantSDNode>(RoundingMode)->getZExtValue() !=
16116 X86::STATIC_ROUNDING::CUR_DIRECTION)
16117 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16118 dl, Op.getValueType(), Src, RoundingMode),
16119 Mask, PassThru, Subtarget, DAG);
16120 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
16122 Mask, PassThru, Subtarget, DAG);
16124 case INTR_TYPE_1OP_MASK: {
16125 SDValue Src = Op.getOperand(1);
16126 SDValue PassThru = Op.getOperand(2);
16127 SDValue Mask = Op.getOperand(3);
16128 // We add rounding mode to the Node when
16129 // - RM Opcode is specified and
16130 // - RM is not "current direction".
16131 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16132 if (IntrWithRoundingModeOpcode != 0) {
16133 SDValue Rnd = Op.getOperand(4);
16134 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16135 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16136 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16137 dl, Op.getValueType(),
16139 Mask, PassThru, Subtarget, DAG);
16142 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
16143 Mask, PassThru, Subtarget, DAG);
16145 case INTR_TYPE_SCALAR_MASK: {
16146 SDValue Src1 = Op.getOperand(1);
16147 SDValue Src2 = Op.getOperand(2);
16148 SDValue passThru = Op.getOperand(3);
16149 SDValue Mask = Op.getOperand(4);
16150 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2),
16151 Mask, passThru, Subtarget, DAG);
16153 case INTR_TYPE_SCALAR_MASK_RM: {
16154 SDValue Src1 = Op.getOperand(1);
16155 SDValue Src2 = Op.getOperand(2);
16156 SDValue Src0 = Op.getOperand(3);
16157 SDValue Mask = Op.getOperand(4);
16158 // There are 2 kinds of intrinsics in this group:
16159 // (1) With suppress-all-exceptions (sae) or rounding mode- 6 operands
16160 // (2) With rounding mode and sae - 7 operands.
16161 if (Op.getNumOperands() == 6) {
16162 SDValue Sae = Op.getOperand(5);
16163 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
16164 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
16166 Mask, Src0, Subtarget, DAG);
16168 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
16169 SDValue RoundingMode = Op.getOperand(5);
16170 SDValue Sae = Op.getOperand(6);
16171 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
16172 RoundingMode, Sae),
16173 Mask, Src0, Subtarget, DAG);
16175 case INTR_TYPE_2OP_MASK:
16176 case INTR_TYPE_2OP_IMM8_MASK: {
16177 SDValue Src1 = Op.getOperand(1);
16178 SDValue Src2 = Op.getOperand(2);
16179 SDValue PassThru = Op.getOperand(3);
16180 SDValue Mask = Op.getOperand(4);
16182 if (IntrData->Type == INTR_TYPE_2OP_IMM8_MASK)
16183 Src2 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src2);
16185 // We specify 2 possible opcodes for intrinsics with rounding modes.
16186 // First, we check if the intrinsic may have non-default rounding mode,
16187 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16188 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16189 if (IntrWithRoundingModeOpcode != 0) {
16190 SDValue Rnd = Op.getOperand(5);
16191 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16192 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16193 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16194 dl, Op.getValueType(),
16196 Mask, PassThru, Subtarget, DAG);
16199 // TODO: Intrinsics should have fast-math-flags to propagate.
16200 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,Src1,Src2),
16201 Mask, PassThru, Subtarget, DAG);
16203 case INTR_TYPE_2OP_MASK_RM: {
16204 SDValue Src1 = Op.getOperand(1);
16205 SDValue Src2 = Op.getOperand(2);
16206 SDValue PassThru = Op.getOperand(3);
16207 SDValue Mask = Op.getOperand(4);
16208 // We specify 2 possible modes for intrinsics, with/without rounding
16210 // First, we check if the intrinsic have rounding mode (6 operands),
16211 // if not, we set rounding mode to "current".
16213 if (Op.getNumOperands() == 6)
16214 Rnd = Op.getOperand(5);
16216 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16217 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16219 Mask, PassThru, Subtarget, DAG);
16221 case INTR_TYPE_3OP_SCALAR_MASK_RM: {
16222 SDValue Src1 = Op.getOperand(1);
16223 SDValue Src2 = Op.getOperand(2);
16224 SDValue Src3 = Op.getOperand(3);
16225 SDValue PassThru = Op.getOperand(4);
16226 SDValue Mask = Op.getOperand(5);
16227 SDValue Sae = Op.getOperand(6);
16229 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1,
16231 Mask, PassThru, Subtarget, DAG);
16233 case INTR_TYPE_3OP_MASK_RM: {
16234 SDValue Src1 = Op.getOperand(1);
16235 SDValue Src2 = Op.getOperand(2);
16236 SDValue Imm = Op.getOperand(3);
16237 SDValue PassThru = Op.getOperand(4);
16238 SDValue Mask = Op.getOperand(5);
16239 // We specify 2 possible modes for intrinsics, with/without rounding
16241 // First, we check if the intrinsic have rounding mode (7 operands),
16242 // if not, we set rounding mode to "current".
16244 if (Op.getNumOperands() == 7)
16245 Rnd = Op.getOperand(6);
16247 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
16248 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16249 Src1, Src2, Imm, Rnd),
16250 Mask, PassThru, Subtarget, DAG);
16252 case INTR_TYPE_3OP_IMM8_MASK:
16253 case INTR_TYPE_3OP_MASK:
16254 case INSERT_SUBVEC: {
16255 SDValue Src1 = Op.getOperand(1);
16256 SDValue Src2 = Op.getOperand(2);
16257 SDValue Src3 = Op.getOperand(3);
16258 SDValue PassThru = Op.getOperand(4);
16259 SDValue Mask = Op.getOperand(5);
16261 if (IntrData->Type == INTR_TYPE_3OP_IMM8_MASK)
16262 Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
16263 else if (IntrData->Type == INSERT_SUBVEC) {
16264 // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
16265 assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
16266 unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
16267 Imm *= Src2.getValueType().getVectorNumElements();
16268 Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
16271 // We specify 2 possible opcodes for intrinsics with rounding modes.
16272 // First, we check if the intrinsic may have non-default rounding mode,
16273 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16274 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16275 if (IntrWithRoundingModeOpcode != 0) {
16276 SDValue Rnd = Op.getOperand(6);
16277 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
16278 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
16279 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16280 dl, Op.getValueType(),
16281 Src1, Src2, Src3, Rnd),
16282 Mask, PassThru, Subtarget, DAG);
16285 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16287 Mask, PassThru, Subtarget, DAG);
16289 case VPERM_3OP_MASKZ:
16290 case VPERM_3OP_MASK:
16293 case FMA_OP_MASK: {
16294 SDValue Src1 = Op.getOperand(1);
16295 SDValue Src2 = Op.getOperand(2);
16296 SDValue Src3 = Op.getOperand(3);
16297 SDValue Mask = Op.getOperand(4);
16298 EVT VT = Op.getValueType();
16299 SDValue PassThru = SDValue();
16301 // set PassThru element
16302 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
16303 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16304 else if (IntrData->Type == FMA_OP_MASK3)
16309 // We specify 2 possible opcodes for intrinsics with rounding modes.
16310 // First, we check if the intrinsic may have non-default rounding mode,
16311 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16312 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
16313 if (IntrWithRoundingModeOpcode != 0) {
16314 SDValue Rnd = Op.getOperand(5);
16315 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16316 X86::STATIC_ROUNDING::CUR_DIRECTION)
16317 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
16318 dl, Op.getValueType(),
16319 Src1, Src2, Src3, Rnd),
16320 Mask, PassThru, Subtarget, DAG);
16322 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
16323 dl, Op.getValueType(),
16325 Mask, PassThru, Subtarget, DAG);
16327 case TERLOG_OP_MASK:
16328 case TERLOG_OP_MASKZ: {
16329 SDValue Src1 = Op.getOperand(1);
16330 SDValue Src2 = Op.getOperand(2);
16331 SDValue Src3 = Op.getOperand(3);
16332 SDValue Src4 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(4));
16333 SDValue Mask = Op.getOperand(5);
16334 EVT VT = Op.getValueType();
16335 SDValue PassThru = Src1;
16336 // Set PassThru element.
16337 if (IntrData->Type == TERLOG_OP_MASKZ)
16338 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
16340 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16341 Src1, Src2, Src3, Src4),
16342 Mask, PassThru, Subtarget, DAG);
16345 // FPclass intrinsics with mask
16346 SDValue Src1 = Op.getOperand(1);
16347 EVT VT = Src1.getValueType();
16348 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16349 VT.getVectorNumElements());
16350 SDValue Imm = Op.getOperand(2);
16351 SDValue Mask = Op.getOperand(3);
16352 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16353 Mask.getValueType().getSizeInBits());
16354 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MaskVT, Src1, Imm);
16355 SDValue FPclassMask = getVectorMaskingNode(FPclass, Mask,
16356 DAG.getTargetConstant(0, dl, MaskVT),
16358 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16359 DAG.getUNDEF(BitcastVT), FPclassMask,
16360 DAG.getIntPtrConstant(0, dl));
16361 return DAG.getBitcast(Op.getValueType(), Res);
16364 SDValue Src1 = Op.getOperand(1);
16365 SDValue Imm = Op.getOperand(2);
16366 SDValue Mask = Op.getOperand(3);
16367 SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Imm);
16368 SDValue FPclassMask = getScalarMaskingNode(FPclass, Mask,
16369 DAG.getTargetConstant(0, dl, MVT::i1), Subtarget, DAG);
16370 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i8, FPclassMask);
16373 case CMP_MASK_CC: {
16374 // Comparison intrinsics with masks.
16375 // Example of transformation:
16376 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
16377 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
16379 // (v8i1 (insert_subvector undef,
16380 // (v2i1 (and (PCMPEQM %a, %b),
16381 // (extract_subvector
16382 // (v8i1 (bitcast %mask)), 0))), 0))))
16383 EVT VT = Op.getOperand(1).getValueType();
16384 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16385 VT.getVectorNumElements());
16386 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
16387 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16388 Mask.getValueType().getSizeInBits());
16390 if (IntrData->Type == CMP_MASK_CC) {
16391 SDValue CC = Op.getOperand(3);
16392 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
16393 // We specify 2 possible opcodes for intrinsics with rounding modes.
16394 // First, we check if the intrinsic may have non-default rounding mode,
16395 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
16396 if (IntrData->Opc1 != 0) {
16397 SDValue Rnd = Op.getOperand(5);
16398 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16399 X86::STATIC_ROUNDING::CUR_DIRECTION)
16400 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
16401 Op.getOperand(2), CC, Rnd);
16403 //default rounding mode
16405 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16406 Op.getOperand(2), CC);
16409 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
16410 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
16413 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
16414 DAG.getTargetConstant(0, dl,
16417 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
16418 DAG.getUNDEF(BitcastVT), CmpMask,
16419 DAG.getIntPtrConstant(0, dl));
16420 return DAG.getBitcast(Op.getValueType(), Res);
16422 case CMP_MASK_SCALAR_CC: {
16423 SDValue Src1 = Op.getOperand(1);
16424 SDValue Src2 = Op.getOperand(2);
16425 SDValue CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op.getOperand(3));
16426 SDValue Mask = Op.getOperand(4);
16429 if (IntrData->Opc1 != 0) {
16430 SDValue Rnd = Op.getOperand(5);
16431 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
16432 X86::STATIC_ROUNDING::CUR_DIRECTION)
16433 Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
16435 //default rounding mode
16437 Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::i1, Src1, Src2, CC);
16439 SDValue CmpMask = getScalarMaskingNode(Cmp, Mask,
16440 DAG.getTargetConstant(0, dl,
16444 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::i8,
16445 DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i8, CmpMask),
16446 DAG.getValueType(MVT::i1));
16448 case COMI: { // Comparison intrinsics
16449 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
16450 SDValue LHS = Op.getOperand(1);
16451 SDValue RHS = Op.getOperand(2);
16452 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
16453 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
16454 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
16455 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16456 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
16457 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16460 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
16461 Op.getOperand(1), Op.getOperand(2), DAG);
16463 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
16464 Op.getSimpleValueType(),
16466 Op.getOperand(2), DAG),
16467 Op.getOperand(4), Op.getOperand(3), Subtarget,
16469 case COMPRESS_EXPAND_IN_REG: {
16470 SDValue Mask = Op.getOperand(3);
16471 SDValue DataToCompress = Op.getOperand(1);
16472 SDValue PassThru = Op.getOperand(2);
16473 if (isAllOnes(Mask)) // return data as is
16474 return Op.getOperand(1);
16476 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
16478 Mask, PassThru, Subtarget, DAG);
16481 SDValue Mask = Op.getOperand(3);
16482 EVT VT = Op.getValueType();
16483 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16484 VT.getVectorNumElements());
16485 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16486 Mask.getValueType().getSizeInBits());
16488 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16489 DAG.getBitcast(BitcastVT, Mask),
16490 DAG.getIntPtrConstant(0, dl));
16491 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
16500 default: return SDValue(); // Don't custom lower most intrinsics.
16502 case Intrinsic::x86_avx2_permd:
16503 case Intrinsic::x86_avx2_permps:
16504 // Operands intentionally swapped. Mask is last operand to intrinsic,
16505 // but second operand for node/instruction.
16506 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
16507 Op.getOperand(2), Op.getOperand(1));
16509 // ptest and testp intrinsics. The intrinsic these come from are designed to
16510 // return an integer value, not just an instruction so lower it to the ptest
16511 // or testp pattern and a setcc for the result.
16512 case Intrinsic::x86_sse41_ptestz:
16513 case Intrinsic::x86_sse41_ptestc:
16514 case Intrinsic::x86_sse41_ptestnzc:
16515 case Intrinsic::x86_avx_ptestz_256:
16516 case Intrinsic::x86_avx_ptestc_256:
16517 case Intrinsic::x86_avx_ptestnzc_256:
16518 case Intrinsic::x86_avx_vtestz_ps:
16519 case Intrinsic::x86_avx_vtestc_ps:
16520 case Intrinsic::x86_avx_vtestnzc_ps:
16521 case Intrinsic::x86_avx_vtestz_pd:
16522 case Intrinsic::x86_avx_vtestc_pd:
16523 case Intrinsic::x86_avx_vtestnzc_pd:
16524 case Intrinsic::x86_avx_vtestz_ps_256:
16525 case Intrinsic::x86_avx_vtestc_ps_256:
16526 case Intrinsic::x86_avx_vtestnzc_ps_256:
16527 case Intrinsic::x86_avx_vtestz_pd_256:
16528 case Intrinsic::x86_avx_vtestc_pd_256:
16529 case Intrinsic::x86_avx_vtestnzc_pd_256: {
16530 bool IsTestPacked = false;
16533 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
16534 case Intrinsic::x86_avx_vtestz_ps:
16535 case Intrinsic::x86_avx_vtestz_pd:
16536 case Intrinsic::x86_avx_vtestz_ps_256:
16537 case Intrinsic::x86_avx_vtestz_pd_256:
16538 IsTestPacked = true; // Fallthrough
16539 case Intrinsic::x86_sse41_ptestz:
16540 case Intrinsic::x86_avx_ptestz_256:
16542 X86CC = X86::COND_E;
16544 case Intrinsic::x86_avx_vtestc_ps:
16545 case Intrinsic::x86_avx_vtestc_pd:
16546 case Intrinsic::x86_avx_vtestc_ps_256:
16547 case Intrinsic::x86_avx_vtestc_pd_256:
16548 IsTestPacked = true; // Fallthrough
16549 case Intrinsic::x86_sse41_ptestc:
16550 case Intrinsic::x86_avx_ptestc_256:
16552 X86CC = X86::COND_B;
16554 case Intrinsic::x86_avx_vtestnzc_ps:
16555 case Intrinsic::x86_avx_vtestnzc_pd:
16556 case Intrinsic::x86_avx_vtestnzc_ps_256:
16557 case Intrinsic::x86_avx_vtestnzc_pd_256:
16558 IsTestPacked = true; // Fallthrough
16559 case Intrinsic::x86_sse41_ptestnzc:
16560 case Intrinsic::x86_avx_ptestnzc_256:
16562 X86CC = X86::COND_A;
16566 SDValue LHS = Op.getOperand(1);
16567 SDValue RHS = Op.getOperand(2);
16568 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
16569 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
16570 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16571 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
16572 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16574 case Intrinsic::x86_avx512_kortestz_w:
16575 case Intrinsic::x86_avx512_kortestc_w: {
16576 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
16577 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
16578 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
16579 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
16580 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
16581 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
16582 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16585 case Intrinsic::x86_sse42_pcmpistria128:
16586 case Intrinsic::x86_sse42_pcmpestria128:
16587 case Intrinsic::x86_sse42_pcmpistric128:
16588 case Intrinsic::x86_sse42_pcmpestric128:
16589 case Intrinsic::x86_sse42_pcmpistrio128:
16590 case Intrinsic::x86_sse42_pcmpestrio128:
16591 case Intrinsic::x86_sse42_pcmpistris128:
16592 case Intrinsic::x86_sse42_pcmpestris128:
16593 case Intrinsic::x86_sse42_pcmpistriz128:
16594 case Intrinsic::x86_sse42_pcmpestriz128: {
16598 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
16599 case Intrinsic::x86_sse42_pcmpistria128:
16600 Opcode = X86ISD::PCMPISTRI;
16601 X86CC = X86::COND_A;
16603 case Intrinsic::x86_sse42_pcmpestria128:
16604 Opcode = X86ISD::PCMPESTRI;
16605 X86CC = X86::COND_A;
16607 case Intrinsic::x86_sse42_pcmpistric128:
16608 Opcode = X86ISD::PCMPISTRI;
16609 X86CC = X86::COND_B;
16611 case Intrinsic::x86_sse42_pcmpestric128:
16612 Opcode = X86ISD::PCMPESTRI;
16613 X86CC = X86::COND_B;
16615 case Intrinsic::x86_sse42_pcmpistrio128:
16616 Opcode = X86ISD::PCMPISTRI;
16617 X86CC = X86::COND_O;
16619 case Intrinsic::x86_sse42_pcmpestrio128:
16620 Opcode = X86ISD::PCMPESTRI;
16621 X86CC = X86::COND_O;
16623 case Intrinsic::x86_sse42_pcmpistris128:
16624 Opcode = X86ISD::PCMPISTRI;
16625 X86CC = X86::COND_S;
16627 case Intrinsic::x86_sse42_pcmpestris128:
16628 Opcode = X86ISD::PCMPESTRI;
16629 X86CC = X86::COND_S;
16631 case Intrinsic::x86_sse42_pcmpistriz128:
16632 Opcode = X86ISD::PCMPISTRI;
16633 X86CC = X86::COND_E;
16635 case Intrinsic::x86_sse42_pcmpestriz128:
16636 Opcode = X86ISD::PCMPESTRI;
16637 X86CC = X86::COND_E;
16640 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16641 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16642 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
16643 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16644 DAG.getConstant(X86CC, dl, MVT::i8),
16645 SDValue(PCMP.getNode(), 1));
16646 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
16649 case Intrinsic::x86_sse42_pcmpistri128:
16650 case Intrinsic::x86_sse42_pcmpestri128: {
16652 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
16653 Opcode = X86ISD::PCMPISTRI;
16655 Opcode = X86ISD::PCMPESTRI;
16657 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
16658 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
16659 return DAG.getNode(Opcode, dl, VTs, NewOps);
16662 case Intrinsic::x86_seh_lsda: {
16663 // Compute the symbol for the LSDA. We know it'll get emitted later.
16664 MachineFunction &MF = DAG.getMachineFunction();
16665 SDValue Op1 = Op.getOperand(1);
16666 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
16667 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
16668 GlobalValue::getRealLinkageName(Fn->getName()));
16670 // Generate a simple absolute symbol reference. This intrinsic is only
16671 // supported on 32-bit Windows, which isn't PIC.
16672 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
16673 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
16676 case Intrinsic::x86_seh_recoverfp: {
16677 SDValue FnOp = Op.getOperand(1);
16678 SDValue IncomingFPOp = Op.getOperand(2);
16679 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
16680 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
16682 report_fatal_error(
16683 "llvm.x86.seh.recoverfp must take a function as the first argument");
16684 return recoverFramePointer(DAG, Fn, IncomingFPOp);
16687 case Intrinsic::localaddress: {
16688 // Returns one of the stack, base, or frame pointer registers, depending on
16689 // which is used to reference local variables.
16690 MachineFunction &MF = DAG.getMachineFunction();
16691 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16693 if (RegInfo->hasBasePointer(MF))
16694 Reg = RegInfo->getBaseRegister();
16695 else // This function handles the SP or FP case.
16696 Reg = RegInfo->getPtrSizedFrameRegister(MF);
16697 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
16702 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16703 SDValue Src, SDValue Mask, SDValue Base,
16704 SDValue Index, SDValue ScaleOp, SDValue Chain,
16705 const X86Subtarget * Subtarget) {
16707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16709 llvm_unreachable("Invalid scale type");
16710 unsigned ScaleVal = C->getZExtValue();
16711 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16712 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16714 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16715 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16716 Index.getSimpleValueType().getVectorNumElements());
16718 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16720 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16722 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16723 Mask.getValueType().getSizeInBits());
16725 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16726 // are extracted by EXTRACT_SUBVECTOR.
16727 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16728 DAG.getBitcast(BitcastVT, Mask),
16729 DAG.getIntPtrConstant(0, dl));
16731 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
16732 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16733 SDValue Segment = DAG.getRegister(0, MVT::i32);
16734 if (Src.getOpcode() == ISD::UNDEF)
16735 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
16736 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16737 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16738 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
16739 return DAG.getMergeValues(RetOps, dl);
16742 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16743 SDValue Src, SDValue Mask, SDValue Base,
16744 SDValue Index, SDValue ScaleOp, SDValue Chain) {
16746 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16748 llvm_unreachable("Invalid scale type");
16749 unsigned ScaleVal = C->getZExtValue();
16750 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
16751 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
16753 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16754 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16755 SDValue Segment = DAG.getRegister(0, MVT::i32);
16756 EVT MaskVT = MVT::getVectorVT(MVT::i1,
16757 Index.getSimpleValueType().getVectorNumElements());
16759 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16761 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16763 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16764 Mask.getValueType().getSizeInBits());
16766 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16767 // are extracted by EXTRACT_SUBVECTOR.
16768 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16769 DAG.getBitcast(BitcastVT, Mask),
16770 DAG.getIntPtrConstant(0, dl));
16772 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
16773 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
16774 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
16775 return SDValue(Res, 1);
16778 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
16779 SDValue Mask, SDValue Base, SDValue Index,
16780 SDValue ScaleOp, SDValue Chain) {
16782 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
16783 assert(C && "Invalid scale type");
16784 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
16785 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
16786 SDValue Segment = DAG.getRegister(0, MVT::i32);
16788 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
16790 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
16792 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
16794 MaskInReg = DAG.getBitcast(MaskVT, Mask);
16795 //SDVTList VTs = DAG.getVTList(MVT::Other);
16796 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
16797 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
16798 return SDValue(Res, 0);
16801 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
16802 // read performance monitor counters (x86_rdpmc).
16803 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
16804 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16805 SmallVectorImpl<SDValue> &Results) {
16806 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16807 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16810 // The ECX register is used to select the index of the performance counter
16812 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
16814 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
16816 // Reads the content of a 64-bit performance counter and returns it in the
16817 // registers EDX:EAX.
16818 if (Subtarget->is64Bit()) {
16819 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16820 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16823 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16824 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16827 Chain = HI.getValue(1);
16829 if (Subtarget->is64Bit()) {
16830 // The EAX register is loaded with the low-order 32 bits. The EDX register
16831 // is loaded with the supported high-order bits of the counter.
16832 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16833 DAG.getConstant(32, DL, MVT::i8));
16834 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16835 Results.push_back(Chain);
16839 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16840 SDValue Ops[] = { LO, HI };
16841 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16842 Results.push_back(Pair);
16843 Results.push_back(Chain);
16846 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
16847 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
16848 // also used to custom lower READCYCLECOUNTER nodes.
16849 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
16850 SelectionDAG &DAG, const X86Subtarget *Subtarget,
16851 SmallVectorImpl<SDValue> &Results) {
16852 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
16853 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
16856 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
16857 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
16858 // and the EAX register is loaded with the low-order 32 bits.
16859 if (Subtarget->is64Bit()) {
16860 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
16861 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
16864 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
16865 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
16868 SDValue Chain = HI.getValue(1);
16870 if (Opcode == X86ISD::RDTSCP_DAG) {
16871 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
16873 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
16874 // the ECX register. Add 'ecx' explicitly to the chain.
16875 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
16877 // Explicitly store the content of ECX at the location passed in input
16878 // to the 'rdtscp' intrinsic.
16879 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
16880 MachinePointerInfo(), false, false, 0);
16883 if (Subtarget->is64Bit()) {
16884 // The EDX register is loaded with the high-order 32 bits of the MSR, and
16885 // the EAX register is loaded with the low-order 32 bits.
16886 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
16887 DAG.getConstant(32, DL, MVT::i8));
16888 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
16889 Results.push_back(Chain);
16893 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
16894 SDValue Ops[] = { LO, HI };
16895 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
16896 Results.push_back(Pair);
16897 Results.push_back(Chain);
16900 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
16901 SelectionDAG &DAG) {
16902 SmallVector<SDValue, 2> Results;
16904 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
16906 return DAG.getMergeValues(Results, DL);
16909 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
16910 SelectionDAG &DAG) {
16911 MachineFunction &MF = DAG.getMachineFunction();
16912 const Function *Fn = MF.getFunction();
16914 SDValue Chain = Op.getOperand(0);
16916 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
16917 "using llvm.x86.seh.restoreframe requires a frame pointer");
16919 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16920 MVT VT = TLI.getPointerTy(DAG.getDataLayout());
16922 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16923 unsigned FrameReg =
16924 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16925 unsigned SPReg = RegInfo->getStackRegister();
16926 unsigned SlotSize = RegInfo->getSlotSize();
16928 // Get incoming EBP.
16929 SDValue IncomingEBP =
16930 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
16932 // SP is saved in the first field of every registration node, so load
16933 // [EBP-RegNodeSize] into SP.
16934 int RegNodeSize = getSEHRegistrationNodeSize(Fn);
16935 SDValue SPAddr = DAG.getNode(ISD::ADD, dl, VT, IncomingEBP,
16936 DAG.getConstant(-RegNodeSize, dl, VT));
16938 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
16939 false, VT.getScalarSizeInBits() / 8);
16940 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
16942 if (!RegInfo->needsStackRealignment(MF)) {
16943 // Adjust EBP to point back to the original frame position.
16944 SDValue NewFP = recoverFramePointer(DAG, Fn, IncomingEBP);
16945 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
16947 assert(RegInfo->hasBasePointer(MF) &&
16948 "functions with Win32 EH must use frame or base pointer register");
16950 // Reload the base pointer (ESI) with the adjusted incoming EBP.
16951 SDValue NewBP = recoverFramePointer(DAG, Fn, IncomingEBP);
16952 Chain = DAG.getCopyToReg(Chain, dl, RegInfo->getBaseRegister(), NewBP);
16954 // Reload the spilled EBP value, now that the stack and base pointers are
16956 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
16957 X86FI->setHasSEHFramePtrSave(true);
16958 int FI = MF.getFrameInfo()->CreateSpillStackObject(SlotSize, SlotSize);
16959 X86FI->setSEHFramePtrSaveIndex(FI);
16960 SDValue NewFP = DAG.getLoad(VT, dl, Chain, DAG.getFrameIndex(FI, VT),
16961 MachinePointerInfo(), false, false, false,
16962 VT.getScalarSizeInBits() / 8);
16963 Chain = DAG.getCopyToReg(NewFP, dl, FrameReg, NewFP);
16969 /// \brief Lower intrinsics for TRUNCATE_TO_MEM case
16970 /// return truncate Store/MaskedStore Node
16971 static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,
16975 SDValue Mask = Op.getOperand(4);
16976 SDValue DataToTruncate = Op.getOperand(3);
16977 SDValue Addr = Op.getOperand(2);
16978 SDValue Chain = Op.getOperand(0);
16980 EVT VT = DataToTruncate.getValueType();
16981 EVT SVT = EVT::getVectorVT(*DAG.getContext(),
16982 ElementType, VT.getVectorNumElements());
16984 if (isAllOnes(Mask)) // return just a truncate store
16985 return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,
16986 MachinePointerInfo(), SVT, false, false,
16987 SVT.getScalarSizeInBits()/8);
16989 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
16990 MVT::i1, VT.getVectorNumElements());
16991 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
16992 Mask.getValueType().getSizeInBits());
16993 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
16994 // are extracted by EXTRACT_SUBVECTOR.
16995 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
16996 DAG.getBitcast(BitcastVT, Mask),
16997 DAG.getIntPtrConstant(0, dl));
16999 MachineMemOperand *MMO = DAG.getMachineFunction().
17000 getMachineMemOperand(MachinePointerInfo(),
17001 MachineMemOperand::MOStore, SVT.getStoreSize(),
17002 SVT.getScalarSizeInBits()/8);
17004 return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,
17005 VMask, SVT, MMO, true);
17008 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
17009 SelectionDAG &DAG) {
17010 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
17012 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
17014 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
17015 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
17020 switch(IntrData->Type) {
17022 llvm_unreachable("Unknown Intrinsic Type");
17026 // Emit the node with the right value type.
17027 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
17028 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17030 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
17031 // Otherwise return the value from Rand, which is always 0, casted to i32.
17032 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
17033 DAG.getConstant(1, dl, Op->getValueType(1)),
17034 DAG.getConstant(X86::COND_B, dl, MVT::i32),
17035 SDValue(Result.getNode(), 1) };
17036 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
17037 DAG.getVTList(Op->getValueType(1), MVT::Glue),
17040 // Return { result, isValid, chain }.
17041 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
17042 SDValue(Result.getNode(), 2));
17045 //gather(v1, mask, index, base, scale);
17046 SDValue Chain = Op.getOperand(0);
17047 SDValue Src = Op.getOperand(2);
17048 SDValue Base = Op.getOperand(3);
17049 SDValue Index = Op.getOperand(4);
17050 SDValue Mask = Op.getOperand(5);
17051 SDValue Scale = Op.getOperand(6);
17052 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
17056 //scatter(base, mask, index, v1, scale);
17057 SDValue Chain = Op.getOperand(0);
17058 SDValue Base = Op.getOperand(2);
17059 SDValue Mask = Op.getOperand(3);
17060 SDValue Index = Op.getOperand(4);
17061 SDValue Src = Op.getOperand(5);
17062 SDValue Scale = Op.getOperand(6);
17063 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
17067 SDValue Hint = Op.getOperand(6);
17068 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
17069 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
17070 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
17071 SDValue Chain = Op.getOperand(0);
17072 SDValue Mask = Op.getOperand(2);
17073 SDValue Index = Op.getOperand(3);
17074 SDValue Base = Op.getOperand(4);
17075 SDValue Scale = Op.getOperand(5);
17076 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
17078 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
17080 SmallVector<SDValue, 2> Results;
17081 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
17083 return DAG.getMergeValues(Results, dl);
17085 // Read Performance Monitoring Counters.
17087 SmallVector<SDValue, 2> Results;
17088 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
17089 return DAG.getMergeValues(Results, dl);
17091 // XTEST intrinsics.
17093 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17094 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
17095 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17096 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
17098 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
17099 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
17100 Ret, SDValue(InTrans.getNode(), 1));
17104 SmallVector<SDValue, 2> Results;
17105 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
17106 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
17107 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
17108 DAG.getConstant(-1, dl, MVT::i8));
17109 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
17110 Op.getOperand(4), GenCF.getValue(1));
17111 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
17112 Op.getOperand(5), MachinePointerInfo(),
17114 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
17115 DAG.getConstant(X86::COND_B, dl, MVT::i8),
17117 Results.push_back(SetCC);
17118 Results.push_back(Store);
17119 return DAG.getMergeValues(Results, dl);
17121 case COMPRESS_TO_MEM: {
17123 SDValue Mask = Op.getOperand(4);
17124 SDValue DataToCompress = Op.getOperand(3);
17125 SDValue Addr = Op.getOperand(2);
17126 SDValue Chain = Op.getOperand(0);
17128 EVT VT = DataToCompress.getValueType();
17129 if (isAllOnes(Mask)) // return just a store
17130 return DAG.getStore(Chain, dl, DataToCompress, Addr,
17131 MachinePointerInfo(), false, false,
17132 VT.getScalarSizeInBits()/8);
17134 SDValue Compressed =
17135 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
17136 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
17137 return DAG.getStore(Chain, dl, Compressed, Addr,
17138 MachinePointerInfo(), false, false,
17139 VT.getScalarSizeInBits()/8);
17141 case TRUNCATE_TO_MEM_VI8:
17142 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);
17143 case TRUNCATE_TO_MEM_VI16:
17144 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);
17145 case TRUNCATE_TO_MEM_VI32:
17146 return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);
17147 case EXPAND_FROM_MEM: {
17149 SDValue Mask = Op.getOperand(4);
17150 SDValue PassThru = Op.getOperand(3);
17151 SDValue Addr = Op.getOperand(2);
17152 SDValue Chain = Op.getOperand(0);
17153 EVT VT = Op.getValueType();
17155 if (isAllOnes(Mask)) // return just a load
17156 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
17157 false, VT.getScalarSizeInBits()/8);
17159 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
17160 false, false, false,
17161 VT.getScalarSizeInBits()/8);
17163 SDValue Results[] = {
17164 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
17165 Mask, PassThru, Subtarget, DAG), Chain};
17166 return DAG.getMergeValues(Results, dl);
17171 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
17172 SelectionDAG &DAG) const {
17173 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
17174 MFI->setReturnAddressIsTaken(true);
17176 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
17179 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17181 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17184 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
17185 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17186 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
17187 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17188 DAG.getNode(ISD::ADD, dl, PtrVT,
17189 FrameAddr, Offset),
17190 MachinePointerInfo(), false, false, false, 0);
17193 // Just load the return address.
17194 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
17195 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
17196 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
17199 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
17200 MachineFunction &MF = DAG.getMachineFunction();
17201 MachineFrameInfo *MFI = MF.getFrameInfo();
17202 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
17203 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17204 EVT VT = Op.getValueType();
17206 MFI->setFrameAddressIsTaken(true);
17208 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
17209 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
17210 // is not possible to crawl up the stack without looking at the unwind codes
17212 int FrameAddrIndex = FuncInfo->getFAIndex();
17213 if (!FrameAddrIndex) {
17214 // Set up a frame object for the return address.
17215 unsigned SlotSize = RegInfo->getSlotSize();
17216 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
17217 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
17218 FuncInfo->setFAIndex(FrameAddrIndex);
17220 return DAG.getFrameIndex(FrameAddrIndex, VT);
17223 unsigned FrameReg =
17224 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17225 SDLoc dl(Op); // FIXME probably not meaningful
17226 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
17227 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
17228 (FrameReg == X86::EBP && VT == MVT::i32)) &&
17229 "Invalid Frame Register!");
17230 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
17232 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
17233 MachinePointerInfo(),
17234 false, false, false, 0);
17238 // FIXME? Maybe this could be a TableGen attribute on some registers and
17239 // this table could be generated automatically from RegInfo.
17240 unsigned X86TargetLowering::getRegisterByName(const char* RegName, EVT VT,
17241 SelectionDAG &DAG) const {
17242 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17243 const MachineFunction &MF = DAG.getMachineFunction();
17245 unsigned Reg = StringSwitch<unsigned>(RegName)
17246 .Case("esp", X86::ESP)
17247 .Case("rsp", X86::RSP)
17248 .Case("ebp", X86::EBP)
17249 .Case("rbp", X86::RBP)
17252 if (Reg == X86::EBP || Reg == X86::RBP) {
17253 if (!TFI.hasFP(MF))
17254 report_fatal_error("register " + StringRef(RegName) +
17255 " is allocatable: function has no frame pointer");
17258 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17259 unsigned FrameReg =
17260 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
17261 assert((FrameReg == X86::EBP || FrameReg == X86::RBP) &&
17262 "Invalid Frame Register!");
17270 report_fatal_error("Invalid register name global variable");
17273 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
17274 SelectionDAG &DAG) const {
17275 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17276 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
17279 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
17280 SDValue Chain = Op.getOperand(0);
17281 SDValue Offset = Op.getOperand(1);
17282 SDValue Handler = Op.getOperand(2);
17285 EVT PtrVT = getPointerTy(DAG.getDataLayout());
17286 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
17287 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
17288 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
17289 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
17290 "Invalid Frame Register!");
17291 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
17292 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
17294 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
17295 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
17297 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
17298 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
17300 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
17302 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
17303 DAG.getRegister(StoreAddrReg, PtrVT));
17306 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
17307 SelectionDAG &DAG) const {
17309 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
17310 DAG.getVTList(MVT::i32, MVT::Other),
17311 Op.getOperand(0), Op.getOperand(1));
17314 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
17315 SelectionDAG &DAG) const {
17317 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
17318 Op.getOperand(0), Op.getOperand(1));
17321 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
17322 return Op.getOperand(0);
17325 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
17326 SelectionDAG &DAG) const {
17327 SDValue Root = Op.getOperand(0);
17328 SDValue Trmp = Op.getOperand(1); // trampoline
17329 SDValue FPtr = Op.getOperand(2); // nested function
17330 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
17333 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
17334 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
17336 if (Subtarget->is64Bit()) {
17337 SDValue OutChains[6];
17339 // Large code-model.
17340 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
17341 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
17343 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
17344 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
17346 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
17348 // Load the pointer to the nested function into R11.
17349 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
17350 SDValue Addr = Trmp;
17351 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17352 Addr, MachinePointerInfo(TrmpAddr),
17355 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17356 DAG.getConstant(2, dl, MVT::i64));
17357 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
17358 MachinePointerInfo(TrmpAddr, 2),
17361 // Load the 'nest' parameter value into R10.
17362 // R10 is specified in X86CallingConv.td
17363 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
17364 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17365 DAG.getConstant(10, dl, MVT::i64));
17366 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17367 Addr, MachinePointerInfo(TrmpAddr, 10),
17370 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17371 DAG.getConstant(12, dl, MVT::i64));
17372 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
17373 MachinePointerInfo(TrmpAddr, 12),
17376 // Jump to the nested function.
17377 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
17378 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17379 DAG.getConstant(20, dl, MVT::i64));
17380 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
17381 Addr, MachinePointerInfo(TrmpAddr, 20),
17384 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
17385 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
17386 DAG.getConstant(22, dl, MVT::i64));
17387 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
17388 Addr, MachinePointerInfo(TrmpAddr, 22),
17391 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17393 const Function *Func =
17394 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
17395 CallingConv::ID CC = Func->getCallingConv();
17400 llvm_unreachable("Unsupported calling convention");
17401 case CallingConv::C:
17402 case CallingConv::X86_StdCall: {
17403 // Pass 'nest' parameter in ECX.
17404 // Must be kept in sync with X86CallingConv.td
17405 NestReg = X86::ECX;
17407 // Check that ECX wasn't needed by an 'inreg' parameter.
17408 FunctionType *FTy = Func->getFunctionType();
17409 const AttributeSet &Attrs = Func->getAttributes();
17411 if (!Attrs.isEmpty() && !Func->isVarArg()) {
17412 unsigned InRegCount = 0;
17415 for (FunctionType::param_iterator I = FTy->param_begin(),
17416 E = FTy->param_end(); I != E; ++I, ++Idx)
17417 if (Attrs.hasAttribute(Idx, Attribute::InReg)) {
17418 auto &DL = DAG.getDataLayout();
17419 // FIXME: should only count parameters that are lowered to integers.
17420 InRegCount += (DL.getTypeSizeInBits(*I) + 31) / 32;
17423 if (InRegCount > 2) {
17424 report_fatal_error("Nest register in use - reduce number of inreg"
17430 case CallingConv::X86_FastCall:
17431 case CallingConv::X86_ThisCall:
17432 case CallingConv::Fast:
17433 // Pass 'nest' parameter in EAX.
17434 // Must be kept in sync with X86CallingConv.td
17435 NestReg = X86::EAX;
17439 SDValue OutChains[4];
17440 SDValue Addr, Disp;
17442 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17443 DAG.getConstant(10, dl, MVT::i32));
17444 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
17446 // This is storing the opcode for MOV32ri.
17447 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
17448 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
17449 OutChains[0] = DAG.getStore(Root, dl,
17450 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
17451 Trmp, MachinePointerInfo(TrmpAddr),
17454 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17455 DAG.getConstant(1, dl, MVT::i32));
17456 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
17457 MachinePointerInfo(TrmpAddr, 1),
17460 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
17461 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17462 DAG.getConstant(5, dl, MVT::i32));
17463 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
17464 Addr, MachinePointerInfo(TrmpAddr, 5),
17467 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
17468 DAG.getConstant(6, dl, MVT::i32));
17469 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
17470 MachinePointerInfo(TrmpAddr, 6),
17473 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
17477 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
17478 SelectionDAG &DAG) const {
17480 The rounding mode is in bits 11:10 of FPSR, and has the following
17482 00 Round to nearest
17487 FLT_ROUNDS, on the other hand, expects the following:
17494 To perform the conversion, we do:
17495 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
17498 MachineFunction &MF = DAG.getMachineFunction();
17499 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
17500 unsigned StackAlignment = TFI.getStackAlignment();
17501 MVT VT = Op.getSimpleValueType();
17504 // Save FP Control Word to stack slot
17505 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
17506 SDValue StackSlot =
17507 DAG.getFrameIndex(SSFI, getPointerTy(DAG.getDataLayout()));
17509 MachineMemOperand *MMO =
17510 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, SSFI),
17511 MachineMemOperand::MOStore, 2, 2);
17513 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
17514 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
17515 DAG.getVTList(MVT::Other),
17516 Ops, MVT::i16, MMO);
17518 // Load FP Control Word from stack slot
17519 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
17520 MachinePointerInfo(), false, false, false, 0);
17522 // Transform as necessary
17524 DAG.getNode(ISD::SRL, DL, MVT::i16,
17525 DAG.getNode(ISD::AND, DL, MVT::i16,
17526 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
17527 DAG.getConstant(11, DL, MVT::i8));
17529 DAG.getNode(ISD::SRL, DL, MVT::i16,
17530 DAG.getNode(ISD::AND, DL, MVT::i16,
17531 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
17532 DAG.getConstant(9, DL, MVT::i8));
17535 DAG.getNode(ISD::AND, DL, MVT::i16,
17536 DAG.getNode(ISD::ADD, DL, MVT::i16,
17537 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
17538 DAG.getConstant(1, DL, MVT::i16)),
17539 DAG.getConstant(3, DL, MVT::i16));
17541 return DAG.getNode((VT.getSizeInBits() < 16 ?
17542 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
17545 /// \brief Lower a vector CTLZ using native supported vector CTLZ instruction.
17547 // 1. i32/i64 128/256-bit vector (native support require VLX) are expended
17548 // to 512-bit vector.
17549 // 2. i8/i16 vector implemented using dword LZCNT vector instruction
17550 // ( sub(trunc(lzcnt(zext32(x)))) ). In case zext32(x) is illegal,
17551 // split the vector, perform operation on it's Lo a Hi part and
17552 // concatenate the results.
17553 static SDValue LowerVectorCTLZ_AVX512(SDValue Op, SelectionDAG &DAG) {
17555 MVT VT = Op.getSimpleValueType();
17556 MVT EltVT = VT.getVectorElementType();
17557 unsigned NumElems = VT.getVectorNumElements();
17559 if (EltVT == MVT::i64 || EltVT == MVT::i32) {
17560 // Extend to 512 bit vector.
17561 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17562 "Unsupported value type for operation");
17564 MVT NewVT = MVT::getVectorVT(EltVT, 512 / VT.getScalarSizeInBits());
17565 SDValue Vec512 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, NewVT,
17566 DAG.getUNDEF(NewVT),
17568 DAG.getIntPtrConstant(0, dl));
17569 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Vec512);
17571 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, CtlzNode,
17572 DAG.getIntPtrConstant(0, dl));
17575 assert((EltVT == MVT::i8 || EltVT == MVT::i16) &&
17576 "Unsupported element type");
17578 if (16 < NumElems) {
17579 // Split vector, it's Lo and Hi parts will be handled in next iteration.
17581 std::tie(Lo, Hi) = DAG.SplitVector(Op.getOperand(0), dl);
17582 MVT OutVT = MVT::getVectorVT(EltVT, NumElems/2);
17584 Lo = DAG.getNode(Op.getOpcode(), dl, OutVT, Lo);
17585 Hi = DAG.getNode(Op.getOpcode(), dl, OutVT, Hi);
17587 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Lo, Hi);
17590 MVT NewVT = MVT::getVectorVT(MVT::i32, NumElems);
17592 assert((NewVT.is256BitVector() || NewVT.is512BitVector()) &&
17593 "Unsupported value type for operation");
17595 // Use native supported vector instruction vplzcntd.
17596 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, NewVT, Op.getOperand(0));
17597 SDValue CtlzNode = DAG.getNode(ISD::CTLZ, dl, NewVT, Op);
17598 SDValue TruncNode = DAG.getNode(ISD::TRUNCATE, dl, VT, CtlzNode);
17599 SDValue Delta = DAG.getConstant(32 - EltVT.getSizeInBits(), dl, VT);
17601 return DAG.getNode(ISD::SUB, dl, VT, TruncNode, Delta);
17604 static SDValue LowerCTLZ(SDValue Op, const X86Subtarget *Subtarget,
17605 SelectionDAG &DAG) {
17606 MVT VT = Op.getSimpleValueType();
17608 unsigned NumBits = VT.getSizeInBits();
17611 if (VT.isVector() && Subtarget->hasAVX512())
17612 return LowerVectorCTLZ_AVX512(Op, DAG);
17614 Op = Op.getOperand(0);
17615 if (VT == MVT::i8) {
17616 // Zero extend to i32 since there is not an i8 bsr.
17618 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17621 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
17622 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17623 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17625 // If src is zero (i.e. bsr sets ZF), returns NumBits.
17628 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
17629 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17632 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
17634 // Finally xor with NumBits-1.
17635 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17636 DAG.getConstant(NumBits - 1, dl, OpVT));
17639 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17643 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, const X86Subtarget *Subtarget,
17644 SelectionDAG &DAG) {
17645 MVT VT = Op.getSimpleValueType();
17647 unsigned NumBits = VT.getSizeInBits();
17650 if (VT.isVector() && Subtarget->hasAVX512())
17651 return LowerVectorCTLZ_AVX512(Op, DAG);
17653 Op = Op.getOperand(0);
17654 if (VT == MVT::i8) {
17655 // Zero extend to i32 since there is not an i8 bsr.
17657 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
17660 // Issue a bsr (scan bits in reverse).
17661 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
17662 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
17664 // And xor with NumBits-1.
17665 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
17666 DAG.getConstant(NumBits - 1, dl, OpVT));
17669 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
17673 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
17674 MVT VT = Op.getSimpleValueType();
17675 unsigned NumBits = VT.getScalarSizeInBits();
17678 if (VT.isVector()) {
17679 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17681 SDValue N0 = Op.getOperand(0);
17682 SDValue Zero = DAG.getConstant(0, dl, VT);
17684 // lsb(x) = (x & -x)
17685 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, N0,
17686 DAG.getNode(ISD::SUB, dl, VT, Zero, N0));
17688 // cttz_undef(x) = (width - 1) - ctlz(lsb)
17689 if (Op.getOpcode() == ISD::CTTZ_ZERO_UNDEF &&
17690 TLI.isOperationLegal(ISD::CTLZ, VT)) {
17691 SDValue WidthMinusOne = DAG.getConstant(NumBits - 1, dl, VT);
17692 return DAG.getNode(ISD::SUB, dl, VT, WidthMinusOne,
17693 DAG.getNode(ISD::CTLZ, dl, VT, LSB));
17696 // cttz(x) = ctpop(lsb - 1)
17697 SDValue One = DAG.getConstant(1, dl, VT);
17698 return DAG.getNode(ISD::CTPOP, dl, VT,
17699 DAG.getNode(ISD::SUB, dl, VT, LSB, One));
17702 assert(Op.getOpcode() == ISD::CTTZ &&
17703 "Only scalar CTTZ requires custom lowering");
17705 // Issue a bsf (scan bits forward) which also sets EFLAGS.
17706 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17707 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op.getOperand(0));
17709 // If src is zero (i.e. bsf sets ZF), returns NumBits.
17712 DAG.getConstant(NumBits, dl, VT),
17713 DAG.getConstant(X86::COND_E, dl, MVT::i8),
17716 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
17719 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
17720 // ones, and then concatenate the result back.
17721 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
17722 MVT VT = Op.getSimpleValueType();
17724 assert(VT.is256BitVector() && VT.isInteger() &&
17725 "Unsupported value type for operation");
17727 unsigned NumElems = VT.getVectorNumElements();
17730 // Extract the LHS vectors
17731 SDValue LHS = Op.getOperand(0);
17732 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
17733 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
17735 // Extract the RHS vectors
17736 SDValue RHS = Op.getOperand(1);
17737 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
17738 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
17740 MVT EltVT = VT.getVectorElementType();
17741 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17743 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17744 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
17745 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
17748 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
17749 if (Op.getValueType() == MVT::i1)
17750 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17751 Op.getOperand(0), Op.getOperand(1));
17752 assert(Op.getSimpleValueType().is256BitVector() &&
17753 Op.getSimpleValueType().isInteger() &&
17754 "Only handle AVX 256-bit vector integer operation");
17755 return Lower256IntArith(Op, DAG);
17758 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
17759 if (Op.getValueType() == MVT::i1)
17760 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
17761 Op.getOperand(0), Op.getOperand(1));
17762 assert(Op.getSimpleValueType().is256BitVector() &&
17763 Op.getSimpleValueType().isInteger() &&
17764 "Only handle AVX 256-bit vector integer operation");
17765 return Lower256IntArith(Op, DAG);
17768 static SDValue LowerMINMAX(SDValue Op, SelectionDAG &DAG) {
17769 assert(Op.getSimpleValueType().is256BitVector() &&
17770 Op.getSimpleValueType().isInteger() &&
17771 "Only handle AVX 256-bit vector integer operation");
17772 return Lower256IntArith(Op, DAG);
17775 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
17776 SelectionDAG &DAG) {
17778 MVT VT = Op.getSimpleValueType();
17781 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
17783 // Decompose 256-bit ops into smaller 128-bit ops.
17784 if (VT.is256BitVector() && !Subtarget->hasInt256())
17785 return Lower256IntArith(Op, DAG);
17787 SDValue A = Op.getOperand(0);
17788 SDValue B = Op.getOperand(1);
17790 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
17791 // pairs, multiply and truncate.
17792 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
17793 if (Subtarget->hasInt256()) {
17794 if (VT == MVT::v32i8) {
17795 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
17796 SDValue Lo = DAG.getIntPtrConstant(0, dl);
17797 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
17798 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
17799 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
17800 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
17801 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
17802 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
17803 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
17804 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
17807 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
17808 return DAG.getNode(
17809 ISD::TRUNCATE, dl, VT,
17810 DAG.getNode(ISD::MUL, dl, ExVT,
17811 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
17812 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
17815 assert(VT == MVT::v16i8 &&
17816 "Pre-AVX2 support only supports v16i8 multiplication");
17817 MVT ExVT = MVT::v8i16;
17819 // Extract the lo parts and sign extend to i16
17821 if (Subtarget->hasSSE41()) {
17822 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
17823 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
17825 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
17826 -1, 4, -1, 5, -1, 6, -1, 7};
17827 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17828 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17829 ALo = DAG.getBitcast(ExVT, ALo);
17830 BLo = DAG.getBitcast(ExVT, BLo);
17831 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
17832 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
17835 // Extract the hi parts and sign extend to i16
17837 if (Subtarget->hasSSE41()) {
17838 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
17839 -1, -1, -1, -1, -1, -1, -1, -1};
17840 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17841 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17842 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
17843 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
17845 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
17846 -1, 12, -1, 13, -1, 14, -1, 15};
17847 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
17848 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
17849 AHi = DAG.getBitcast(ExVT, AHi);
17850 BHi = DAG.getBitcast(ExVT, BHi);
17851 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
17852 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
17855 // Multiply, mask the lower 8bits of the lo/hi results and pack
17856 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
17857 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
17858 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
17859 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
17860 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17863 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
17864 if (VT == MVT::v4i32) {
17865 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
17866 "Should not custom lower when pmuldq is available!");
17868 // Extract the odd parts.
17869 static const int UnpackMask[] = { 1, -1, 3, -1 };
17870 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
17871 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
17873 // Multiply the even parts.
17874 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
17875 // Now multiply odd parts.
17876 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
17878 Evens = DAG.getBitcast(VT, Evens);
17879 Odds = DAG.getBitcast(VT, Odds);
17881 // Merge the two vectors back together with a shuffle. This expands into 2
17883 static const int ShufMask[] = { 0, 4, 2, 6 };
17884 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
17887 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
17888 "Only know how to lower V2I64/V4I64/V8I64 multiply");
17890 // Ahi = psrlqi(a, 32);
17891 // Bhi = psrlqi(b, 32);
17893 // AloBlo = pmuludq(a, b);
17894 // AloBhi = pmuludq(a, Bhi);
17895 // AhiBlo = pmuludq(Ahi, b);
17897 // AloBhi = psllqi(AloBhi, 32);
17898 // AhiBlo = psllqi(AhiBlo, 32);
17899 // return AloBlo + AloBhi + AhiBlo;
17901 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
17902 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
17904 SDValue AhiBlo = Ahi;
17905 SDValue AloBhi = Bhi;
17906 // Bit cast to 32-bit vectors for MULUDQ
17907 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
17908 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
17909 A = DAG.getBitcast(MulVT, A);
17910 B = DAG.getBitcast(MulVT, B);
17911 Ahi = DAG.getBitcast(MulVT, Ahi);
17912 Bhi = DAG.getBitcast(MulVT, Bhi);
17914 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
17915 // After shifting right const values the result may be all-zero.
17916 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
17917 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
17918 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
17920 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
17921 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
17922 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
17925 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
17926 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
17929 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
17930 assert(Subtarget->isTargetWin64() && "Unexpected target");
17931 EVT VT = Op.getValueType();
17932 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
17933 "Unexpected return type for lowering");
17937 switch (Op->getOpcode()) {
17938 default: llvm_unreachable("Unexpected request for libcall!");
17939 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
17940 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
17941 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
17942 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
17943 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
17944 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
17948 SDValue InChain = DAG.getEntryNode();
17950 TargetLowering::ArgListTy Args;
17951 TargetLowering::ArgListEntry Entry;
17952 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
17953 EVT ArgVT = Op->getOperand(i).getValueType();
17954 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
17955 "Unexpected argument type for lowering");
17956 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
17957 Entry.Node = StackPtr;
17958 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
17960 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17961 Entry.Ty = PointerType::get(ArgTy,0);
17962 Entry.isSExt = false;
17963 Entry.isZExt = false;
17964 Args.push_back(Entry);
17967 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
17968 getPointerTy(DAG.getDataLayout()));
17970 TargetLowering::CallLoweringInfo CLI(DAG);
17971 CLI.setDebugLoc(dl).setChain(InChain)
17972 .setCallee(getLibcallCallingConv(LC),
17973 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
17974 Callee, std::move(Args), 0)
17975 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
17977 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
17978 return DAG.getBitcast(VT, CallInfo.first);
17981 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
17982 SelectionDAG &DAG) {
17983 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
17984 EVT VT = Op0.getValueType();
17987 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
17988 (VT == MVT::v8i32 && Subtarget->hasInt256()));
17990 // PMULxD operations multiply each even value (starting at 0) of LHS with
17991 // the related value of RHS and produce a widen result.
17992 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
17993 // => <2 x i64> <ae|cg>
17995 // In other word, to have all the results, we need to perform two PMULxD:
17996 // 1. one with the even values.
17997 // 2. one with the odd values.
17998 // To achieve #2, with need to place the odd values at an even position.
18000 // Place the odd value at an even position (basically, shift all values 1
18001 // step to the left):
18002 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
18003 // <a|b|c|d> => <b|undef|d|undef>
18004 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
18005 // <e|f|g|h> => <f|undef|h|undef>
18006 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
18008 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
18010 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
18011 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
18013 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
18014 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
18015 // => <2 x i64> <ae|cg>
18016 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
18017 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
18018 // => <2 x i64> <bf|dh>
18019 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
18021 // Shuffle it back into the right order.
18022 SDValue Highs, Lows;
18023 if (VT == MVT::v8i32) {
18024 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
18025 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18026 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
18027 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18029 const int HighMask[] = {1, 5, 3, 7};
18030 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
18031 const int LowMask[] = {0, 4, 2, 6};
18032 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
18035 // If we have a signed multiply but no PMULDQ fix up the high parts of a
18036 // unsigned multiply.
18037 if (IsSigned && !Subtarget->hasSSE41()) {
18038 SDValue ShAmt = DAG.getConstant(
18040 DAG.getTargetLoweringInfo().getShiftAmountTy(VT, DAG.getDataLayout()));
18041 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
18042 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
18043 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
18044 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
18046 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
18047 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
18050 // The first result of MUL_LOHI is actually the low value, followed by the
18052 SDValue Ops[] = {Lows, Highs};
18053 return DAG.getMergeValues(Ops, dl);
18056 // Return true if the required (according to Opcode) shift-imm form is natively
18057 // supported by the Subtarget
18058 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
18060 if (VT.getScalarSizeInBits() < 16)
18063 if (VT.is512BitVector() &&
18064 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
18067 bool LShift = VT.is128BitVector() ||
18068 (VT.is256BitVector() && Subtarget->hasInt256());
18070 bool AShift = LShift && (Subtarget->hasVLX() ||
18071 (VT != MVT::v2i64 && VT != MVT::v4i64));
18072 return (Opcode == ISD::SRA) ? AShift : LShift;
18075 // The shift amount is a variable, but it is the same for all vector lanes.
18076 // These instructions are defined together with shift-immediate.
18078 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
18080 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
18083 // Return true if the required (according to Opcode) variable-shift form is
18084 // natively supported by the Subtarget
18085 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
18088 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
18091 // vXi16 supported only on AVX-512, BWI
18092 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
18095 if (VT.is512BitVector() || Subtarget->hasVLX())
18098 bool LShift = VT.is128BitVector() || VT.is256BitVector();
18099 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
18100 return (Opcode == ISD::SRA) ? AShift : LShift;
18103 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
18104 const X86Subtarget *Subtarget) {
18105 MVT VT = Op.getSimpleValueType();
18107 SDValue R = Op.getOperand(0);
18108 SDValue Amt = Op.getOperand(1);
18110 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18111 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18113 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
18114 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
18115 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
18116 SDValue Ex = DAG.getBitcast(ExVT, R);
18118 if (ShiftAmt >= 32) {
18119 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
18121 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
18122 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18123 ShiftAmt - 32, DAG);
18124 if (VT == MVT::v2i64)
18125 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
18126 if (VT == MVT::v4i64)
18127 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18128 {9, 1, 11, 3, 13, 5, 15, 7});
18130 // SRA upper i32, SHL whole i64 and select lower i32.
18131 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
18134 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
18135 Lower = DAG.getBitcast(ExVT, Lower);
18136 if (VT == MVT::v2i64)
18137 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
18138 if (VT == MVT::v4i64)
18139 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
18140 {8, 1, 10, 3, 12, 5, 14, 7});
18142 return DAG.getBitcast(VT, Ex);
18145 // Optimize shl/srl/sra with constant shift amount.
18146 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
18147 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
18148 uint64_t ShiftAmt = ShiftConst->getZExtValue();
18150 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18151 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18153 // i64 SRA needs to be performed as partial shifts.
18154 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
18155 Op.getOpcode() == ISD::SRA && !Subtarget->hasXOP())
18156 return ArithmeticShiftRight64(ShiftAmt);
18158 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
18159 unsigned NumElts = VT.getVectorNumElements();
18160 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
18162 // Simple i8 add case
18163 if (Op.getOpcode() == ISD::SHL && ShiftAmt == 1)
18164 return DAG.getNode(ISD::ADD, dl, VT, R, R);
18166 // ashr(R, 7) === cmp_slt(R, 0)
18167 if (Op.getOpcode() == ISD::SRA && ShiftAmt == 7) {
18168 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
18169 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
18172 // XOP can shift v16i8 directly instead of as shift v8i16 + mask.
18173 if (VT == MVT::v16i8 && Subtarget->hasXOP())
18176 if (Op.getOpcode() == ISD::SHL) {
18177 // Make a large shift.
18178 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
18180 SHL = DAG.getBitcast(VT, SHL);
18181 // Zero out the rightmost bits.
18182 SmallVector<SDValue, 32> V(
18183 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
18184 return DAG.getNode(ISD::AND, dl, VT, SHL,
18185 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18187 if (Op.getOpcode() == ISD::SRL) {
18188 // Make a large shift.
18189 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
18191 SRL = DAG.getBitcast(VT, SRL);
18192 // Zero out the leftmost bits.
18193 SmallVector<SDValue, 32> V(
18194 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
18195 return DAG.getNode(ISD::AND, dl, VT, SRL,
18196 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
18198 if (Op.getOpcode() == ISD::SRA) {
18199 // ashr(R, Amt) === sub(xor(lshr(R, Amt), Mask), Mask)
18200 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18201 SmallVector<SDValue, 32> V(NumElts,
18202 DAG.getConstant(128 >> ShiftAmt, dl,
18204 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
18205 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
18206 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
18209 llvm_unreachable("Unknown shift opcode.");
18214 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18215 if (!Subtarget->is64Bit() && !Subtarget->hasXOP() &&
18216 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64))) {
18218 // Peek through any splat that was introduced for i64 shift vectorization.
18219 int SplatIndex = -1;
18220 if (ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt.getNode()))
18221 if (SVN->isSplat()) {
18222 SplatIndex = SVN->getSplatIndex();
18223 Amt = Amt.getOperand(0);
18224 assert(SplatIndex < (int)VT.getVectorNumElements() &&
18225 "Splat shuffle referencing second operand");
18228 if (Amt.getOpcode() != ISD::BITCAST ||
18229 Amt.getOperand(0).getOpcode() != ISD::BUILD_VECTOR)
18232 Amt = Amt.getOperand(0);
18233 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18234 VT.getVectorNumElements();
18235 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
18236 uint64_t ShiftAmt = 0;
18237 unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
18238 for (unsigned i = 0; i != Ratio; ++i) {
18239 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
18243 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
18246 // Check remaining shift amounts (if not a splat).
18247 if (SplatIndex < 0) {
18248 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18249 uint64_t ShAmt = 0;
18250 for (unsigned j = 0; j != Ratio; ++j) {
18251 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
18255 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
18257 if (ShAmt != ShiftAmt)
18262 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
18263 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
18265 if (Op.getOpcode() == ISD::SRA)
18266 return ArithmeticShiftRight64(ShiftAmt);
18272 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
18273 const X86Subtarget* Subtarget) {
18274 MVT VT = Op.getSimpleValueType();
18276 SDValue R = Op.getOperand(0);
18277 SDValue Amt = Op.getOperand(1);
18279 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
18280 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
18282 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
18283 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
18285 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
18287 EVT EltVT = VT.getVectorElementType();
18289 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
18290 // Check if this build_vector node is doing a splat.
18291 // If so, then set BaseShAmt equal to the splat value.
18292 BaseShAmt = BV->getSplatValue();
18293 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
18294 BaseShAmt = SDValue();
18296 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
18297 Amt = Amt.getOperand(0);
18299 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
18300 if (SVN && SVN->isSplat()) {
18301 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
18302 SDValue InVec = Amt.getOperand(0);
18303 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
18304 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
18305 "Unexpected shuffle index found!");
18306 BaseShAmt = InVec.getOperand(SplatIdx);
18307 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
18308 if (ConstantSDNode *C =
18309 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
18310 if (C->getZExtValue() == SplatIdx)
18311 BaseShAmt = InVec.getOperand(1);
18316 // Avoid introducing an extract element from a shuffle.
18317 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
18318 DAG.getIntPtrConstant(SplatIdx, dl));
18322 if (BaseShAmt.getNode()) {
18323 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
18324 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
18325 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
18326 else if (EltVT.bitsLT(MVT::i32))
18327 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
18329 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
18333 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
18334 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
18335 Amt.getOpcode() == ISD::BITCAST &&
18336 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
18337 Amt = Amt.getOperand(0);
18338 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
18339 VT.getVectorNumElements();
18340 std::vector<SDValue> Vals(Ratio);
18341 for (unsigned i = 0; i != Ratio; ++i)
18342 Vals[i] = Amt.getOperand(i);
18343 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
18344 for (unsigned j = 0; j != Ratio; ++j)
18345 if (Vals[j] != Amt.getOperand(i + j))
18349 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
18350 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
18355 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
18356 SelectionDAG &DAG) {
18357 MVT VT = Op.getSimpleValueType();
18359 SDValue R = Op.getOperand(0);
18360 SDValue Amt = Op.getOperand(1);
18362 assert(VT.isVector() && "Custom lowering only for vector shifts!");
18363 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
18365 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
18368 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
18371 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
18374 // XOP has 128-bit variable logical/arithmetic shifts.
18375 // +ve/-ve Amt = shift left/right.
18376 if (Subtarget->hasXOP() &&
18377 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
18378 VT == MVT::v8i16 || VT == MVT::v16i8)) {
18379 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) {
18380 SDValue Zero = getZeroVector(VT, Subtarget, DAG, dl);
18381 Amt = DAG.getNode(ISD::SUB, dl, VT, Zero, Amt);
18383 if (Op.getOpcode() == ISD::SHL || Op.getOpcode() == ISD::SRL)
18384 return DAG.getNode(X86ISD::VPSHL, dl, VT, R, Amt);
18385 if (Op.getOpcode() == ISD::SRA)
18386 return DAG.getNode(X86ISD::VPSHA, dl, VT, R, Amt);
18389 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
18390 // shifts per-lane and then shuffle the partial results back together.
18391 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
18392 // Splat the shift amounts so the scalar shifts above will catch it.
18393 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
18394 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
18395 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
18396 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
18397 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
18400 // i64 vector arithmetic shift can be emulated with the transform:
18401 // M = lshr(SIGN_BIT, Amt)
18402 // ashr(R, Amt) === sub(xor(lshr(R, Amt), M), M)
18403 if ((VT == MVT::v2i64 || (VT == MVT::v4i64 && Subtarget->hasInt256())) &&
18404 Op.getOpcode() == ISD::SRA) {
18405 SDValue S = DAG.getConstant(APInt::getSignBit(64), dl, VT);
18406 SDValue M = DAG.getNode(ISD::SRL, dl, VT, S, Amt);
18407 R = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
18408 R = DAG.getNode(ISD::XOR, dl, VT, R, M);
18409 R = DAG.getNode(ISD::SUB, dl, VT, R, M);
18413 // If possible, lower this packed shift into a vector multiply instead of
18414 // expanding it into a sequence of scalar shifts.
18415 // Do this only if the vector shift count is a constant build_vector.
18416 if (Op.getOpcode() == ISD::SHL &&
18417 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
18418 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
18419 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18420 SmallVector<SDValue, 8> Elts;
18421 EVT SVT = VT.getScalarType();
18422 unsigned SVTBits = SVT.getSizeInBits();
18423 const APInt &One = APInt(SVTBits, 1);
18424 unsigned NumElems = VT.getVectorNumElements();
18426 for (unsigned i=0; i !=NumElems; ++i) {
18427 SDValue Op = Amt->getOperand(i);
18428 if (Op->getOpcode() == ISD::UNDEF) {
18429 Elts.push_back(Op);
18433 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
18434 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
18435 uint64_t ShAmt = C.getZExtValue();
18436 if (ShAmt >= SVTBits) {
18437 Elts.push_back(DAG.getUNDEF(SVT));
18440 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
18442 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
18443 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
18446 // Lower SHL with variable shift amount.
18447 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
18448 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
18450 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
18451 DAG.getConstant(0x3f800000U, dl, VT));
18452 Op = DAG.getBitcast(MVT::v4f32, Op);
18453 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
18454 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
18457 // If possible, lower this shift as a sequence of two shifts by
18458 // constant plus a MOVSS/MOVSD instead of scalarizing it.
18460 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
18462 // Could be rewritten as:
18463 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
18465 // The advantage is that the two shifts from the example would be
18466 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
18467 // the vector shift into four scalar shifts plus four pairs of vector
18469 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
18470 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18471 unsigned TargetOpcode = X86ISD::MOVSS;
18472 bool CanBeSimplified;
18473 // The splat value for the first packed shift (the 'X' from the example).
18474 SDValue Amt1 = Amt->getOperand(0);
18475 // The splat value for the second packed shift (the 'Y' from the example).
18476 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
18477 Amt->getOperand(2);
18479 // See if it is possible to replace this node with a sequence of
18480 // two shifts followed by a MOVSS/MOVSD
18481 if (VT == MVT::v4i32) {
18482 // Check if it is legal to use a MOVSS.
18483 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
18484 Amt2 == Amt->getOperand(3);
18485 if (!CanBeSimplified) {
18486 // Otherwise, check if we can still simplify this node using a MOVSD.
18487 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
18488 Amt->getOperand(2) == Amt->getOperand(3);
18489 TargetOpcode = X86ISD::MOVSD;
18490 Amt2 = Amt->getOperand(2);
18493 // Do similar checks for the case where the machine value type
18495 CanBeSimplified = Amt1 == Amt->getOperand(1);
18496 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
18497 CanBeSimplified = Amt2 == Amt->getOperand(i);
18499 if (!CanBeSimplified) {
18500 TargetOpcode = X86ISD::MOVSD;
18501 CanBeSimplified = true;
18502 Amt2 = Amt->getOperand(4);
18503 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
18504 CanBeSimplified = Amt1 == Amt->getOperand(i);
18505 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
18506 CanBeSimplified = Amt2 == Amt->getOperand(j);
18510 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
18511 isa<ConstantSDNode>(Amt2)) {
18512 // Replace this node with two shifts followed by a MOVSS/MOVSD.
18513 EVT CastVT = MVT::v4i32;
18515 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
18516 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
18518 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
18519 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
18520 if (TargetOpcode == X86ISD::MOVSD)
18521 CastVT = MVT::v2i64;
18522 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
18523 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
18524 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
18526 return DAG.getBitcast(VT, Result);
18530 // v4i32 Non Uniform Shifts.
18531 // If the shift amount is constant we can shift each lane using the SSE2
18532 // immediate shifts, else we need to zero-extend each lane to the lower i64
18533 // and shift using the SSE2 variable shifts.
18534 // The separate results can then be blended together.
18535 if (VT == MVT::v4i32) {
18536 unsigned Opc = Op.getOpcode();
18537 SDValue Amt0, Amt1, Amt2, Amt3;
18538 if (ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
18539 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {0, 0, 0, 0});
18540 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {1, 1, 1, 1});
18541 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {2, 2, 2, 2});
18542 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, DAG.getUNDEF(VT), {3, 3, 3, 3});
18544 // ISD::SHL is handled above but we include it here for completeness.
18547 llvm_unreachable("Unknown target vector shift node");
18549 Opc = X86ISD::VSHL;
18552 Opc = X86ISD::VSRL;
18555 Opc = X86ISD::VSRA;
18558 // The SSE2 shifts use the lower i64 as the same shift amount for
18559 // all lanes and the upper i64 is ignored. These shuffle masks
18560 // optimally zero-extend each lanes on SSE2/SSE41/AVX targets.
18561 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18562 Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Z, {0, 4, -1, -1});
18563 Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Z, {1, 5, -1, -1});
18564 Amt2 = DAG.getVectorShuffle(VT, dl, Amt, Z, {2, 6, -1, -1});
18565 Amt3 = DAG.getVectorShuffle(VT, dl, Amt, Z, {3, 7, -1, -1});
18568 SDValue R0 = DAG.getNode(Opc, dl, VT, R, Amt0);
18569 SDValue R1 = DAG.getNode(Opc, dl, VT, R, Amt1);
18570 SDValue R2 = DAG.getNode(Opc, dl, VT, R, Amt2);
18571 SDValue R3 = DAG.getNode(Opc, dl, VT, R, Amt3);
18572 SDValue R02 = DAG.getVectorShuffle(VT, dl, R0, R2, {0, -1, 6, -1});
18573 SDValue R13 = DAG.getVectorShuffle(VT, dl, R1, R3, {-1, 1, -1, 7});
18574 return DAG.getVectorShuffle(VT, dl, R02, R13, {0, 5, 2, 7});
18577 if (VT == MVT::v16i8 ||
18578 (VT == MVT::v32i8 && Subtarget->hasInt256() && !Subtarget->hasXOP())) {
18579 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
18580 unsigned ShiftOpcode = Op->getOpcode();
18582 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
18583 // On SSE41 targets we make use of the fact that VSELECT lowers
18584 // to PBLENDVB which selects bytes based just on the sign bit.
18585 if (Subtarget->hasSSE41()) {
18586 V0 = DAG.getBitcast(VT, V0);
18587 V1 = DAG.getBitcast(VT, V1);
18588 Sel = DAG.getBitcast(VT, Sel);
18589 return DAG.getBitcast(SelVT,
18590 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
18592 // On pre-SSE41 targets we test for the sign bit by comparing to
18593 // zero - a negative value will set all bits of the lanes to true
18594 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
18595 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
18596 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
18597 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
18600 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
18601 // We can safely do this using i16 shifts as we're only interested in
18602 // the 3 lower bits of each byte.
18603 Amt = DAG.getBitcast(ExtVT, Amt);
18604 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
18605 Amt = DAG.getBitcast(VT, Amt);
18607 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
18608 // r = VSELECT(r, shift(r, 4), a);
18610 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18611 R = SignBitSelect(VT, Amt, M, R);
18614 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18616 // r = VSELECT(r, shift(r, 2), a);
18617 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18618 R = SignBitSelect(VT, Amt, M, R);
18621 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18623 // return VSELECT(r, shift(r, 1), a);
18624 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18625 R = SignBitSelect(VT, Amt, M, R);
18629 if (Op->getOpcode() == ISD::SRA) {
18630 // For SRA we need to unpack each byte to the higher byte of a i16 vector
18631 // so we can correctly sign extend. We don't care what happens to the
18633 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
18634 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
18635 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
18636 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
18637 ALo = DAG.getBitcast(ExtVT, ALo);
18638 AHi = DAG.getBitcast(ExtVT, AHi);
18639 RLo = DAG.getBitcast(ExtVT, RLo);
18640 RHi = DAG.getBitcast(ExtVT, RHi);
18642 // r = VSELECT(r, shift(r, 4), a);
18643 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18644 DAG.getConstant(4, dl, ExtVT));
18645 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18646 DAG.getConstant(4, dl, ExtVT));
18647 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18648 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18651 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18652 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18654 // r = VSELECT(r, shift(r, 2), a);
18655 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18656 DAG.getConstant(2, dl, ExtVT));
18657 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18658 DAG.getConstant(2, dl, ExtVT));
18659 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18660 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18663 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
18664 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
18666 // r = VSELECT(r, shift(r, 1), a);
18667 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
18668 DAG.getConstant(1, dl, ExtVT));
18669 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
18670 DAG.getConstant(1, dl, ExtVT));
18671 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
18672 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
18674 // Logical shift the result back to the lower byte, leaving a zero upper
18676 // meaning that we can safely pack with PACKUSWB.
18678 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
18680 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
18681 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
18685 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
18686 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
18687 // solution better.
18688 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
18689 MVT ExtVT = MVT::v8i32;
18691 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
18692 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
18693 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
18694 return DAG.getNode(ISD::TRUNCATE, dl, VT,
18695 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
18698 if (Subtarget->hasInt256() && !Subtarget->hasXOP() && VT == MVT::v16i16) {
18699 MVT ExtVT = MVT::v8i32;
18700 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
18701 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
18702 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
18703 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
18704 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
18705 ALo = DAG.getBitcast(ExtVT, ALo);
18706 AHi = DAG.getBitcast(ExtVT, AHi);
18707 RLo = DAG.getBitcast(ExtVT, RLo);
18708 RHi = DAG.getBitcast(ExtVT, RHi);
18709 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
18710 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
18711 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
18712 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
18713 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
18716 if (VT == MVT::v8i16) {
18717 unsigned ShiftOpcode = Op->getOpcode();
18719 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
18720 // On SSE41 targets we make use of the fact that VSELECT lowers
18721 // to PBLENDVB which selects bytes based just on the sign bit.
18722 if (Subtarget->hasSSE41()) {
18723 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
18724 V0 = DAG.getBitcast(ExtVT, V0);
18725 V1 = DAG.getBitcast(ExtVT, V1);
18726 Sel = DAG.getBitcast(ExtVT, Sel);
18727 return DAG.getBitcast(
18728 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
18730 // On pre-SSE41 targets we splat the sign bit - a negative value will
18731 // set all bits of the lanes to true and VSELECT uses that in
18732 // its OR(AND(V0,C),AND(V1,~C)) lowering.
18734 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
18735 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
18738 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
18739 if (Subtarget->hasSSE41()) {
18740 // On SSE41 targets we need to replicate the shift mask in both
18741 // bytes for PBLENDVB.
18744 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
18745 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
18747 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
18750 // r = VSELECT(r, shift(r, 8), a);
18751 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
18752 R = SignBitSelect(Amt, M, R);
18755 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18757 // r = VSELECT(r, shift(r, 4), a);
18758 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
18759 R = SignBitSelect(Amt, M, R);
18762 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18764 // r = VSELECT(r, shift(r, 2), a);
18765 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
18766 R = SignBitSelect(Amt, M, R);
18769 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
18771 // return VSELECT(r, shift(r, 1), a);
18772 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
18773 R = SignBitSelect(Amt, M, R);
18777 // Decompose 256-bit shifts into smaller 128-bit shifts.
18778 if (VT.is256BitVector()) {
18779 unsigned NumElems = VT.getVectorNumElements();
18780 MVT EltVT = VT.getVectorElementType();
18781 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
18783 // Extract the two vectors
18784 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
18785 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
18787 // Recreate the shift amount vectors
18788 SDValue Amt1, Amt2;
18789 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
18790 // Constant shift amount
18791 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
18792 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
18793 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
18795 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
18796 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
18798 // Variable shift amount
18799 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
18800 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
18803 // Issue new vector shifts for the smaller types
18804 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
18805 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
18807 // Concatenate the result back
18808 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
18814 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
18815 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
18816 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
18817 // looks for this combo and may remove the "setcc" instruction if the "setcc"
18818 // has only one use.
18819 SDNode *N = Op.getNode();
18820 SDValue LHS = N->getOperand(0);
18821 SDValue RHS = N->getOperand(1);
18822 unsigned BaseOp = 0;
18825 switch (Op.getOpcode()) {
18826 default: llvm_unreachable("Unknown ovf instruction!");
18828 // A subtract of one will be selected as a INC. Note that INC doesn't
18829 // set CF, so we can't do this for UADDO.
18830 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18832 BaseOp = X86ISD::INC;
18833 Cond = X86::COND_O;
18836 BaseOp = X86ISD::ADD;
18837 Cond = X86::COND_O;
18840 BaseOp = X86ISD::ADD;
18841 Cond = X86::COND_B;
18844 // A subtract of one will be selected as a DEC. Note that DEC doesn't
18845 // set CF, so we can't do this for USUBO.
18846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
18848 BaseOp = X86ISD::DEC;
18849 Cond = X86::COND_O;
18852 BaseOp = X86ISD::SUB;
18853 Cond = X86::COND_O;
18856 BaseOp = X86ISD::SUB;
18857 Cond = X86::COND_B;
18860 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
18861 Cond = X86::COND_O;
18863 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
18864 if (N->getValueType(0) == MVT::i8) {
18865 BaseOp = X86ISD::UMUL8;
18866 Cond = X86::COND_O;
18869 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
18871 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
18874 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
18875 DAG.getConstant(X86::COND_O, DL, MVT::i32),
18876 SDValue(Sum.getNode(), 2));
18878 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18882 // Also sets EFLAGS.
18883 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
18884 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
18887 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
18888 DAG.getConstant(Cond, DL, MVT::i32),
18889 SDValue(Sum.getNode(), 1));
18891 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
18894 /// Returns true if the operand type is exactly twice the native width, and
18895 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
18896 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
18897 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
18898 bool X86TargetLowering::needsCmpXchgNb(Type *MemType) const {
18899 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
18902 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
18903 else if (OpWidth == 128)
18904 return Subtarget->hasCmpxchg16b();
18909 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
18910 return needsCmpXchgNb(SI->getValueOperand()->getType());
18913 // Note: this turns large loads into lock cmpxchg8b/16b.
18914 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
18915 TargetLowering::AtomicExpansionKind
18916 X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
18917 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
18918 return needsCmpXchgNb(PTy->getElementType()) ? AtomicExpansionKind::CmpXChg
18919 : AtomicExpansionKind::None;
18922 TargetLowering::AtomicExpansionKind
18923 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
18924 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18925 Type *MemType = AI->getType();
18927 // If the operand is too big, we must see if cmpxchg8/16b is available
18928 // and default to library calls otherwise.
18929 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
18930 return needsCmpXchgNb(MemType) ? AtomicExpansionKind::CmpXChg
18931 : AtomicExpansionKind::None;
18934 AtomicRMWInst::BinOp Op = AI->getOperation();
18937 llvm_unreachable("Unknown atomic operation");
18938 case AtomicRMWInst::Xchg:
18939 case AtomicRMWInst::Add:
18940 case AtomicRMWInst::Sub:
18941 // It's better to use xadd, xsub or xchg for these in all cases.
18942 return AtomicExpansionKind::None;
18943 case AtomicRMWInst::Or:
18944 case AtomicRMWInst::And:
18945 case AtomicRMWInst::Xor:
18946 // If the atomicrmw's result isn't actually used, we can just add a "lock"
18947 // prefix to a normal instruction for these operations.
18948 return !AI->use_empty() ? AtomicExpansionKind::CmpXChg
18949 : AtomicExpansionKind::None;
18950 case AtomicRMWInst::Nand:
18951 case AtomicRMWInst::Max:
18952 case AtomicRMWInst::Min:
18953 case AtomicRMWInst::UMax:
18954 case AtomicRMWInst::UMin:
18955 // These always require a non-trivial set of data operations on x86. We must
18956 // use a cmpxchg loop.
18957 return AtomicExpansionKind::CmpXChg;
18961 static bool hasMFENCE(const X86Subtarget& Subtarget) {
18962 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
18963 // no-sse2). There isn't any reason to disable it if the target processor
18965 return Subtarget.hasSSE2() || Subtarget.is64Bit();
18969 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
18970 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
18971 Type *MemType = AI->getType();
18972 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
18973 // there is no benefit in turning such RMWs into loads, and it is actually
18974 // harmful as it introduces a mfence.
18975 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
18978 auto Builder = IRBuilder<>(AI);
18979 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
18980 auto SynchScope = AI->getSynchScope();
18981 // We must restrict the ordering to avoid generating loads with Release or
18982 // ReleaseAcquire orderings.
18983 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
18984 auto Ptr = AI->getPointerOperand();
18986 // Before the load we need a fence. Here is an example lifted from
18987 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
18990 // x.store(1, relaxed);
18991 // r1 = y.fetch_add(0, release);
18993 // y.fetch_add(42, acquire);
18994 // r2 = x.load(relaxed);
18995 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
18996 // lowered to just a load without a fence. A mfence flushes the store buffer,
18997 // making the optimization clearly correct.
18998 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
18999 // otherwise, we might be able to be more aggressive on relaxed idempotent
19000 // rmw. In practice, they do not look useful, so we don't try to be
19001 // especially clever.
19002 if (SynchScope == SingleThread)
19003 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
19004 // the IR level, so we must wrap it in an intrinsic.
19007 if (!hasMFENCE(*Subtarget))
19008 // FIXME: it might make sense to use a locked operation here but on a
19009 // different cache-line to prevent cache-line bouncing. In practice it
19010 // is probably a small win, and x86 processors without mfence are rare
19011 // enough that we do not bother.
19015 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
19016 Builder.CreateCall(MFence, {});
19018 // Finally we can emit the atomic load.
19019 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
19020 AI->getType()->getPrimitiveSizeInBits());
19021 Loaded->setAtomic(Order, SynchScope);
19022 AI->replaceAllUsesWith(Loaded);
19023 AI->eraseFromParent();
19027 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
19028 SelectionDAG &DAG) {
19030 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
19031 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
19032 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
19033 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
19035 // The only fence that needs an instruction is a sequentially-consistent
19036 // cross-thread fence.
19037 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
19038 if (hasMFENCE(*Subtarget))
19039 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
19041 SDValue Chain = Op.getOperand(0);
19042 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
19044 DAG.getRegister(X86::ESP, MVT::i32), // Base
19045 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
19046 DAG.getRegister(0, MVT::i32), // Index
19047 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
19048 DAG.getRegister(0, MVT::i32), // Segment.
19052 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
19053 return SDValue(Res, 0);
19056 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
19057 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
19060 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
19061 SelectionDAG &DAG) {
19062 MVT T = Op.getSimpleValueType();
19066 switch(T.SimpleTy) {
19067 default: llvm_unreachable("Invalid value type!");
19068 case MVT::i8: Reg = X86::AL; size = 1; break;
19069 case MVT::i16: Reg = X86::AX; size = 2; break;
19070 case MVT::i32: Reg = X86::EAX; size = 4; break;
19072 assert(Subtarget->is64Bit() && "Node not type legal!");
19073 Reg = X86::RAX; size = 8;
19076 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
19077 Op.getOperand(2), SDValue());
19078 SDValue Ops[] = { cpIn.getValue(0),
19081 DAG.getTargetConstant(size, DL, MVT::i8),
19082 cpIn.getValue(1) };
19083 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19084 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
19085 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
19089 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
19090 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
19091 MVT::i32, cpOut.getValue(2));
19092 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
19093 DAG.getConstant(X86::COND_E, DL, MVT::i8),
19096 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
19097 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
19098 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
19102 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
19103 SelectionDAG &DAG) {
19104 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
19105 MVT DstVT = Op.getSimpleValueType();
19107 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
19108 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19109 if (DstVT != MVT::f64)
19110 // This conversion needs to be expanded.
19113 SDValue InVec = Op->getOperand(0);
19115 unsigned NumElts = SrcVT.getVectorNumElements();
19116 EVT SVT = SrcVT.getVectorElementType();
19118 // Widen the vector in input in the case of MVT::v2i32.
19119 // Example: from MVT::v2i32 to MVT::v4i32.
19120 SmallVector<SDValue, 16> Elts;
19121 for (unsigned i = 0, e = NumElts; i != e; ++i)
19122 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
19123 DAG.getIntPtrConstant(i, dl)));
19125 // Explicitly mark the extra elements as Undef.
19126 Elts.append(NumElts, DAG.getUNDEF(SVT));
19128 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19129 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
19130 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
19131 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
19132 DAG.getIntPtrConstant(0, dl));
19135 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
19136 Subtarget->hasMMX() && "Unexpected custom BITCAST");
19137 assert((DstVT == MVT::i64 ||
19138 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
19139 "Unexpected custom BITCAST");
19140 // i64 <=> MMX conversions are Legal.
19141 if (SrcVT==MVT::i64 && DstVT.isVector())
19143 if (DstVT==MVT::i64 && SrcVT.isVector())
19145 // MMX <=> MMX conversions are Legal.
19146 if (SrcVT.isVector() && DstVT.isVector())
19148 // All other conversions need to be expanded.
19152 /// Compute the horizontal sum of bytes in V for the elements of VT.
19154 /// Requires V to be a byte vector and VT to be an integer vector type with
19155 /// wider elements than V's type. The width of the elements of VT determines
19156 /// how many bytes of V are summed horizontally to produce each element of the
19158 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
19159 const X86Subtarget *Subtarget,
19160 SelectionDAG &DAG) {
19162 MVT ByteVecVT = V.getSimpleValueType();
19163 MVT EltVT = VT.getVectorElementType();
19164 int NumElts = VT.getVectorNumElements();
19165 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
19166 "Expected value to have byte element type.");
19167 assert(EltVT != MVT::i8 &&
19168 "Horizontal byte sum only makes sense for wider elements!");
19169 unsigned VecSize = VT.getSizeInBits();
19170 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
19172 // PSADBW instruction horizontally add all bytes and leave the result in i64
19173 // chunks, thus directly computes the pop count for v2i64 and v4i64.
19174 if (EltVT == MVT::i64) {
19175 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19176 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
19177 return DAG.getBitcast(VT, V);
19180 if (EltVT == MVT::i32) {
19181 // We unpack the low half and high half into i32s interleaved with zeros so
19182 // that we can use PSADBW to horizontally sum them. The most useful part of
19183 // this is that it lines up the results of two PSADBW instructions to be
19184 // two v2i64 vectors which concatenated are the 4 population counts. We can
19185 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
19186 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
19187 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
19188 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
19190 // Do the horizontal sums into two v2i64s.
19191 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
19192 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19193 DAG.getBitcast(ByteVecVT, Low), Zeros);
19194 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
19195 DAG.getBitcast(ByteVecVT, High), Zeros);
19197 // Merge them together.
19198 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
19199 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
19200 DAG.getBitcast(ShortVecVT, Low),
19201 DAG.getBitcast(ShortVecVT, High));
19203 return DAG.getBitcast(VT, V);
19206 // The only element type left is i16.
19207 assert(EltVT == MVT::i16 && "Unknown how to handle type");
19209 // To obtain pop count for each i16 element starting from the pop count for
19210 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
19211 // right by 8. It is important to shift as i16s as i8 vector shift isn't
19212 // directly supported.
19213 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
19214 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
19215 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19216 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
19217 DAG.getBitcast(ByteVecVT, V));
19218 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
19221 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
19222 const X86Subtarget *Subtarget,
19223 SelectionDAG &DAG) {
19224 MVT VT = Op.getSimpleValueType();
19225 MVT EltVT = VT.getVectorElementType();
19226 unsigned VecSize = VT.getSizeInBits();
19228 // Implement a lookup table in register by using an algorithm based on:
19229 // http://wm.ite.pl/articles/sse-popcount.html
19231 // The general idea is that every lower byte nibble in the input vector is an
19232 // index into a in-register pre-computed pop count table. We then split up the
19233 // input vector in two new ones: (1) a vector with only the shifted-right
19234 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
19235 // masked out higher ones) for each byte. PSHUB is used separately with both
19236 // to index the in-register table. Next, both are added and the result is a
19237 // i8 vector where each element contains the pop count for input byte.
19239 // To obtain the pop count for elements != i8, we follow up with the same
19240 // approach and use additional tricks as described below.
19242 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
19243 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
19244 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
19245 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
19247 int NumByteElts = VecSize / 8;
19248 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
19249 SDValue In = DAG.getBitcast(ByteVecVT, Op);
19250 SmallVector<SDValue, 16> LUTVec;
19251 for (int i = 0; i < NumByteElts; ++i)
19252 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
19253 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
19254 SmallVector<SDValue, 16> Mask0F(NumByteElts,
19255 DAG.getConstant(0x0F, DL, MVT::i8));
19256 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
19259 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
19260 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
19261 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
19264 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
19266 // The input vector is used as the shuffle mask that index elements into the
19267 // LUT. After counting low and high nibbles, add the vector to obtain the
19268 // final pop count per i8 element.
19269 SDValue HighPopCnt =
19270 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
19271 SDValue LowPopCnt =
19272 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
19273 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
19275 if (EltVT == MVT::i8)
19278 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
19281 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
19282 const X86Subtarget *Subtarget,
19283 SelectionDAG &DAG) {
19284 MVT VT = Op.getSimpleValueType();
19285 assert(VT.is128BitVector() &&
19286 "Only 128-bit vector bitmath lowering supported.");
19288 int VecSize = VT.getSizeInBits();
19289 MVT EltVT = VT.getVectorElementType();
19290 int Len = EltVT.getSizeInBits();
19292 // This is the vectorized version of the "best" algorithm from
19293 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
19294 // with a minor tweak to use a series of adds + shifts instead of vector
19295 // multiplications. Implemented for all integer vector types. We only use
19296 // this when we don't have SSSE3 which allows a LUT-based lowering that is
19297 // much faster, even faster than using native popcnt instructions.
19299 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
19300 MVT VT = V.getSimpleValueType();
19301 SmallVector<SDValue, 32> Shifters(
19302 VT.getVectorNumElements(),
19303 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
19304 return DAG.getNode(OpCode, DL, VT, V,
19305 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
19307 auto GetMask = [&](SDValue V, APInt Mask) {
19308 MVT VT = V.getSimpleValueType();
19309 SmallVector<SDValue, 32> Masks(
19310 VT.getVectorNumElements(),
19311 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
19312 return DAG.getNode(ISD::AND, DL, VT, V,
19313 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
19316 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
19317 // x86, so set the SRL type to have elements at least i16 wide. This is
19318 // correct because all of our SRLs are followed immediately by a mask anyways
19319 // that handles any bits that sneak into the high bits of the byte elements.
19320 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
19324 // v = v - ((v >> 1) & 0x55555555...)
19326 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
19327 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
19328 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
19330 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
19331 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
19332 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
19333 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
19334 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
19336 // v = (v + (v >> 4)) & 0x0F0F0F0F...
19337 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
19338 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
19339 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
19341 // At this point, V contains the byte-wise population count, and we are
19342 // merely doing a horizontal sum if necessary to get the wider element
19344 if (EltVT == MVT::i8)
19347 return LowerHorizontalByteSum(
19348 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
19352 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19353 SelectionDAG &DAG) {
19354 MVT VT = Op.getSimpleValueType();
19355 // FIXME: Need to add AVX-512 support here!
19356 assert((VT.is256BitVector() || VT.is128BitVector()) &&
19357 "Unknown CTPOP type to handle");
19358 SDLoc DL(Op.getNode());
19359 SDValue Op0 = Op.getOperand(0);
19361 if (!Subtarget->hasSSSE3()) {
19362 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
19363 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
19364 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
19367 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
19368 unsigned NumElems = VT.getVectorNumElements();
19370 // Extract each 128-bit vector, compute pop count and concat the result.
19371 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
19372 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
19374 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
19375 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
19376 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
19379 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
19382 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
19383 SelectionDAG &DAG) {
19384 assert(Op.getValueType().isVector() &&
19385 "We only do custom lowering for vector population count.");
19386 return LowerVectorCTPOP(Op, Subtarget, DAG);
19389 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
19390 SDNode *Node = Op.getNode();
19392 EVT T = Node->getValueType(0);
19393 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
19394 DAG.getConstant(0, dl, T), Node->getOperand(2));
19395 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
19396 cast<AtomicSDNode>(Node)->getMemoryVT(),
19397 Node->getOperand(0),
19398 Node->getOperand(1), negOp,
19399 cast<AtomicSDNode>(Node)->getMemOperand(),
19400 cast<AtomicSDNode>(Node)->getOrdering(),
19401 cast<AtomicSDNode>(Node)->getSynchScope());
19404 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
19405 SDNode *Node = Op.getNode();
19407 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
19409 // Convert seq_cst store -> xchg
19410 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
19411 // FIXME: On 32-bit, store -> fist or movq would be more efficient
19412 // (The only way to get a 16-byte store is cmpxchg16b)
19413 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
19414 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
19415 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
19416 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
19417 cast<AtomicSDNode>(Node)->getMemoryVT(),
19418 Node->getOperand(0),
19419 Node->getOperand(1), Node->getOperand(2),
19420 cast<AtomicSDNode>(Node)->getMemOperand(),
19421 cast<AtomicSDNode>(Node)->getOrdering(),
19422 cast<AtomicSDNode>(Node)->getSynchScope());
19423 return Swap.getValue(1);
19425 // Other atomic stores have a simple pattern.
19429 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
19430 EVT VT = Op.getNode()->getSimpleValueType(0);
19432 // Let legalize expand this if it isn't a legal type yet.
19433 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
19436 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
19439 bool ExtraOp = false;
19440 switch (Op.getOpcode()) {
19441 default: llvm_unreachable("Invalid code");
19442 case ISD::ADDC: Opc = X86ISD::ADD; break;
19443 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
19444 case ISD::SUBC: Opc = X86ISD::SUB; break;
19445 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
19449 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19451 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
19452 Op.getOperand(1), Op.getOperand(2));
19455 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
19456 SelectionDAG &DAG) {
19457 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
19459 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
19460 // which returns the values as { float, float } (in XMM0) or
19461 // { double, double } (which is returned in XMM0, XMM1).
19463 SDValue Arg = Op.getOperand(0);
19464 EVT ArgVT = Arg.getValueType();
19465 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
19467 TargetLowering::ArgListTy Args;
19468 TargetLowering::ArgListEntry Entry;
19472 Entry.isSExt = false;
19473 Entry.isZExt = false;
19474 Args.push_back(Entry);
19476 bool isF64 = ArgVT == MVT::f64;
19477 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
19478 // the small struct {f32, f32} is returned in (eax, edx). For f64,
19479 // the results are returned via SRet in memory.
19480 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
19481 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19483 DAG.getExternalSymbol(LibcallName, TLI.getPointerTy(DAG.getDataLayout()));
19485 Type *RetTy = isF64
19486 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
19487 : (Type*)VectorType::get(ArgTy, 4);
19489 TargetLowering::CallLoweringInfo CLI(DAG);
19490 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
19491 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
19493 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
19496 // Returned in xmm0 and xmm1.
19497 return CallResult.first;
19499 // Returned in bits 0:31 and 32:64 xmm0.
19500 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19501 CallResult.first, DAG.getIntPtrConstant(0, dl));
19502 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
19503 CallResult.first, DAG.getIntPtrConstant(1, dl));
19504 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
19505 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
19508 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
19509 SelectionDAG &DAG) {
19510 assert(Subtarget->hasAVX512() &&
19511 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19513 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
19514 EVT VT = N->getValue().getValueType();
19515 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
19518 // X86 scatter kills mask register, so its type should be added to
19519 // the list of return values
19520 if (N->getNumValues() == 1) {
19521 SDValue Index = N->getIndex();
19522 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19523 !Index.getValueType().is512BitVector())
19524 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19526 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
19527 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19528 N->getOperand(3), Index };
19530 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
19531 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
19532 return SDValue(NewScatter.getNode(), 0);
19537 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
19538 SelectionDAG &DAG) {
19539 assert(Subtarget->hasAVX512() &&
19540 "MGATHER/MSCATTER are supported on AVX-512 arch only");
19542 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
19543 EVT VT = Op.getValueType();
19544 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
19547 SDValue Index = N->getIndex();
19548 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
19549 !Index.getValueType().is512BitVector()) {
19550 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19551 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
19552 N->getOperand(3), Index };
19553 DAG.UpdateNodeOperands(N, Ops);
19558 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
19559 SelectionDAG &DAG) const {
19560 // TODO: Eventually, the lowering of these nodes should be informed by or
19561 // deferred to the GC strategy for the function in which they appear. For
19562 // now, however, they must be lowered to something. Since they are logically
19563 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19564 // require special handling for these nodes), lower them as literal NOOPs for
19566 SmallVector<SDValue, 2> Ops;
19568 Ops.push_back(Op.getOperand(0));
19569 if (Op->getGluedNode())
19570 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19573 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19574 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19579 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
19580 SelectionDAG &DAG) const {
19581 // TODO: Eventually, the lowering of these nodes should be informed by or
19582 // deferred to the GC strategy for the function in which they appear. For
19583 // now, however, they must be lowered to something. Since they are logically
19584 // no-ops in the case of a null GC strategy (or a GC strategy which does not
19585 // require special handling for these nodes), lower them as literal NOOPs for
19587 SmallVector<SDValue, 2> Ops;
19589 Ops.push_back(Op.getOperand(0));
19590 if (Op->getGluedNode())
19591 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
19594 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
19595 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
19600 /// LowerOperation - Provide custom lowering hooks for some operations.
19602 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
19603 switch (Op.getOpcode()) {
19604 default: llvm_unreachable("Should not custom lower this!");
19605 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
19606 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
19607 return LowerCMP_SWAP(Op, Subtarget, DAG);
19608 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
19609 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
19610 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
19611 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
19612 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
19613 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
19614 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
19615 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
19616 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
19617 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
19618 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
19619 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
19620 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
19621 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
19622 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
19623 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
19624 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
19625 case ISD::SHL_PARTS:
19626 case ISD::SRA_PARTS:
19627 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
19628 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
19629 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
19630 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
19631 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
19632 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
19633 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
19634 case ISD::SIGN_EXTEND_VECTOR_INREG:
19635 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
19636 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
19637 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
19638 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
19639 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
19641 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
19642 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
19643 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
19644 case ISD::SETCC: return LowerSETCC(Op, DAG);
19645 case ISD::SELECT: return LowerSELECT(Op, DAG);
19646 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
19647 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
19648 case ISD::VASTART: return LowerVASTART(Op, DAG);
19649 case ISD::VAARG: return LowerVAARG(Op, DAG);
19650 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
19651 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
19652 case ISD::INTRINSIC_VOID:
19653 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
19654 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
19655 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
19656 case ISD::FRAME_TO_ARGS_OFFSET:
19657 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
19658 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
19659 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
19660 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
19661 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
19662 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
19663 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
19664 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
19665 case ISD::CTLZ: return LowerCTLZ(Op, Subtarget, DAG);
19666 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, Subtarget, DAG);
19668 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op, DAG);
19669 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
19670 case ISD::UMUL_LOHI:
19671 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
19674 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
19680 case ISD::UMULO: return LowerXALUO(Op, DAG);
19681 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
19682 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
19686 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
19687 case ISD::ADD: return LowerADD(Op, DAG);
19688 case ISD::SUB: return LowerSUB(Op, DAG);
19692 case ISD::UMIN: return LowerMINMAX(Op, DAG);
19693 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
19694 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
19695 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
19696 case ISD::GC_TRANSITION_START:
19697 return LowerGC_TRANSITION_START(Op, DAG);
19698 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
19702 /// ReplaceNodeResults - Replace a node with an illegal result type
19703 /// with a new node built out of custom code.
19704 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
19705 SmallVectorImpl<SDValue>&Results,
19706 SelectionDAG &DAG) const {
19708 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
19709 switch (N->getOpcode()) {
19711 llvm_unreachable("Do not know how to custom type legalize this operation!");
19712 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
19713 case X86ISD::FMINC:
19715 case X86ISD::FMAXC:
19716 case X86ISD::FMAX: {
19717 EVT VT = N->getValueType(0);
19718 if (VT != MVT::v2f32)
19719 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
19720 SDValue UNDEF = DAG.getUNDEF(VT);
19721 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19722 N->getOperand(0), UNDEF);
19723 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
19724 N->getOperand(1), UNDEF);
19725 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
19728 case ISD::SIGN_EXTEND_INREG:
19733 // We don't want to expand or promote these.
19740 case ISD::UDIVREM: {
19741 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
19742 Results.push_back(V);
19745 case ISD::FP_TO_SINT:
19746 case ISD::FP_TO_UINT: {
19747 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
19749 std::pair<SDValue,SDValue> Vals =
19750 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
19751 SDValue FIST = Vals.first, StackSlot = Vals.second;
19752 if (FIST.getNode()) {
19753 EVT VT = N->getValueType(0);
19754 // Return a load from the stack slot.
19755 if (StackSlot.getNode())
19756 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
19757 MachinePointerInfo(),
19758 false, false, false, 0));
19760 Results.push_back(FIST);
19764 case ISD::UINT_TO_FP: {
19765 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19766 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
19767 N->getValueType(0) != MVT::v2f32)
19769 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
19771 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
19773 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
19774 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
19775 DAG.getBitcast(MVT::v2i64, VBias));
19776 Or = DAG.getBitcast(MVT::v2f64, Or);
19777 // TODO: Are there any fast-math-flags to propagate here?
19778 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
19779 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
19782 case ISD::FP_ROUND: {
19783 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
19785 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
19786 Results.push_back(V);
19789 case ISD::FP_EXTEND: {
19790 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
19791 // No other ValueType for FP_EXTEND should reach this point.
19792 assert(N->getValueType(0) == MVT::v2f32 &&
19793 "Do not know how to legalize this Node");
19796 case ISD::INTRINSIC_W_CHAIN: {
19797 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
19799 default : llvm_unreachable("Do not know how to custom type "
19800 "legalize this intrinsic operation!");
19801 case Intrinsic::x86_rdtsc:
19802 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19804 case Intrinsic::x86_rdtscp:
19805 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
19807 case Intrinsic::x86_rdpmc:
19808 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
19811 case ISD::READCYCLECOUNTER: {
19812 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
19815 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
19816 EVT T = N->getValueType(0);
19817 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
19818 bool Regs64bit = T == MVT::i128;
19819 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
19820 SDValue cpInL, cpInH;
19821 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19822 DAG.getConstant(0, dl, HalfT));
19823 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
19824 DAG.getConstant(1, dl, HalfT));
19825 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
19826 Regs64bit ? X86::RAX : X86::EAX,
19828 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
19829 Regs64bit ? X86::RDX : X86::EDX,
19830 cpInH, cpInL.getValue(1));
19831 SDValue swapInL, swapInH;
19832 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19833 DAG.getConstant(0, dl, HalfT));
19834 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
19835 DAG.getConstant(1, dl, HalfT));
19836 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
19837 Regs64bit ? X86::RBX : X86::EBX,
19838 swapInL, cpInH.getValue(1));
19839 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
19840 Regs64bit ? X86::RCX : X86::ECX,
19841 swapInH, swapInL.getValue(1));
19842 SDValue Ops[] = { swapInH.getValue(0),
19844 swapInH.getValue(1) };
19845 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
19846 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
19847 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
19848 X86ISD::LCMPXCHG8_DAG;
19849 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
19850 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
19851 Regs64bit ? X86::RAX : X86::EAX,
19852 HalfT, Result.getValue(1));
19853 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
19854 Regs64bit ? X86::RDX : X86::EDX,
19855 HalfT, cpOutL.getValue(2));
19856 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
19858 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
19859 MVT::i32, cpOutH.getValue(2));
19861 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
19862 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
19863 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
19865 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
19866 Results.push_back(Success);
19867 Results.push_back(EFLAGS.getValue(1));
19870 case ISD::ATOMIC_SWAP:
19871 case ISD::ATOMIC_LOAD_ADD:
19872 case ISD::ATOMIC_LOAD_SUB:
19873 case ISD::ATOMIC_LOAD_AND:
19874 case ISD::ATOMIC_LOAD_OR:
19875 case ISD::ATOMIC_LOAD_XOR:
19876 case ISD::ATOMIC_LOAD_NAND:
19877 case ISD::ATOMIC_LOAD_MIN:
19878 case ISD::ATOMIC_LOAD_MAX:
19879 case ISD::ATOMIC_LOAD_UMIN:
19880 case ISD::ATOMIC_LOAD_UMAX:
19881 case ISD::ATOMIC_LOAD: {
19882 // Delegate to generic TypeLegalization. Situations we can really handle
19883 // should have already been dealt with by AtomicExpandPass.cpp.
19886 case ISD::BITCAST: {
19887 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
19888 EVT DstVT = N->getValueType(0);
19889 EVT SrcVT = N->getOperand(0)->getValueType(0);
19891 if (SrcVT != MVT::f64 ||
19892 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
19895 unsigned NumElts = DstVT.getVectorNumElements();
19896 EVT SVT = DstVT.getVectorElementType();
19897 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
19898 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
19899 MVT::v2f64, N->getOperand(0));
19900 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
19902 if (ExperimentalVectorWideningLegalization) {
19903 // If we are legalizing vectors by widening, we already have the desired
19904 // legal vector type, just return it.
19905 Results.push_back(ToVecInt);
19909 SmallVector<SDValue, 8> Elts;
19910 for (unsigned i = 0, e = NumElts; i != e; ++i)
19911 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
19912 ToVecInt, DAG.getIntPtrConstant(i, dl)));
19914 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
19919 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
19920 switch ((X86ISD::NodeType)Opcode) {
19921 case X86ISD::FIRST_NUMBER: break;
19922 case X86ISD::BSF: return "X86ISD::BSF";
19923 case X86ISD::BSR: return "X86ISD::BSR";
19924 case X86ISD::SHLD: return "X86ISD::SHLD";
19925 case X86ISD::SHRD: return "X86ISD::SHRD";
19926 case X86ISD::FAND: return "X86ISD::FAND";
19927 case X86ISD::FANDN: return "X86ISD::FANDN";
19928 case X86ISD::FOR: return "X86ISD::FOR";
19929 case X86ISD::FXOR: return "X86ISD::FXOR";
19930 case X86ISD::FILD: return "X86ISD::FILD";
19931 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
19932 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
19933 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
19934 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
19935 case X86ISD::FLD: return "X86ISD::FLD";
19936 case X86ISD::FST: return "X86ISD::FST";
19937 case X86ISD::CALL: return "X86ISD::CALL";
19938 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
19939 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
19940 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
19941 case X86ISD::BT: return "X86ISD::BT";
19942 case X86ISD::CMP: return "X86ISD::CMP";
19943 case X86ISD::COMI: return "X86ISD::COMI";
19944 case X86ISD::UCOMI: return "X86ISD::UCOMI";
19945 case X86ISD::CMPM: return "X86ISD::CMPM";
19946 case X86ISD::CMPMU: return "X86ISD::CMPMU";
19947 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
19948 case X86ISD::SETCC: return "X86ISD::SETCC";
19949 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
19950 case X86ISD::FSETCC: return "X86ISD::FSETCC";
19951 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
19952 case X86ISD::CMOV: return "X86ISD::CMOV";
19953 case X86ISD::BRCOND: return "X86ISD::BRCOND";
19954 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
19955 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
19956 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
19957 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
19958 case X86ISD::Wrapper: return "X86ISD::Wrapper";
19959 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
19960 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
19961 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
19962 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
19963 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
19964 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
19965 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
19966 case X86ISD::PINSRB: return "X86ISD::PINSRB";
19967 case X86ISD::PINSRW: return "X86ISD::PINSRW";
19968 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
19969 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
19970 case X86ISD::ANDNP: return "X86ISD::ANDNP";
19971 case X86ISD::PSIGN: return "X86ISD::PSIGN";
19972 case X86ISD::BLENDI: return "X86ISD::BLENDI";
19973 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
19974 case X86ISD::ADDUS: return "X86ISD::ADDUS";
19975 case X86ISD::SUBUS: return "X86ISD::SUBUS";
19976 case X86ISD::HADD: return "X86ISD::HADD";
19977 case X86ISD::HSUB: return "X86ISD::HSUB";
19978 case X86ISD::FHADD: return "X86ISD::FHADD";
19979 case X86ISD::FHSUB: return "X86ISD::FHSUB";
19980 case X86ISD::ABS: return "X86ISD::ABS";
19981 case X86ISD::CONFLICT: return "X86ISD::CONFLICT";
19982 case X86ISD::FMAX: return "X86ISD::FMAX";
19983 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
19984 case X86ISD::FMIN: return "X86ISD::FMIN";
19985 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
19986 case X86ISD::FMAXC: return "X86ISD::FMAXC";
19987 case X86ISD::FMINC: return "X86ISD::FMINC";
19988 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
19989 case X86ISD::FRCP: return "X86ISD::FRCP";
19990 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
19991 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
19992 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
19993 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
19994 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
19995 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
19996 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
19997 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
19998 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
19999 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
20000 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
20001 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
20002 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
20003 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
20004 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
20005 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
20006 case X86ISD::VZEXT: return "X86ISD::VZEXT";
20007 case X86ISD::VSEXT: return "X86ISD::VSEXT";
20008 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
20009 case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";
20010 case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";
20011 case X86ISD::VINSERT: return "X86ISD::VINSERT";
20012 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
20013 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
20014 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
20015 case X86ISD::CVTUDQ2PD: return "X86ISD::CVTUDQ2PD";
20016 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
20017 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
20018 case X86ISD::VSHL: return "X86ISD::VSHL";
20019 case X86ISD::VSRL: return "X86ISD::VSRL";
20020 case X86ISD::VSRA: return "X86ISD::VSRA";
20021 case X86ISD::VSHLI: return "X86ISD::VSHLI";
20022 case X86ISD::VSRLI: return "X86ISD::VSRLI";
20023 case X86ISD::VSRAI: return "X86ISD::VSRAI";
20024 case X86ISD::CMPP: return "X86ISD::CMPP";
20025 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
20026 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
20027 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
20028 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
20029 case X86ISD::ADD: return "X86ISD::ADD";
20030 case X86ISD::SUB: return "X86ISD::SUB";
20031 case X86ISD::ADC: return "X86ISD::ADC";
20032 case X86ISD::SBB: return "X86ISD::SBB";
20033 case X86ISD::SMUL: return "X86ISD::SMUL";
20034 case X86ISD::UMUL: return "X86ISD::UMUL";
20035 case X86ISD::SMUL8: return "X86ISD::SMUL8";
20036 case X86ISD::UMUL8: return "X86ISD::UMUL8";
20037 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
20038 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
20039 case X86ISD::INC: return "X86ISD::INC";
20040 case X86ISD::DEC: return "X86ISD::DEC";
20041 case X86ISD::OR: return "X86ISD::OR";
20042 case X86ISD::XOR: return "X86ISD::XOR";
20043 case X86ISD::AND: return "X86ISD::AND";
20044 case X86ISD::BEXTR: return "X86ISD::BEXTR";
20045 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
20046 case X86ISD::PTEST: return "X86ISD::PTEST";
20047 case X86ISD::TESTP: return "X86ISD::TESTP";
20048 case X86ISD::TESTM: return "X86ISD::TESTM";
20049 case X86ISD::TESTNM: return "X86ISD::TESTNM";
20050 case X86ISD::KORTEST: return "X86ISD::KORTEST";
20051 case X86ISD::KTEST: return "X86ISD::KTEST";
20052 case X86ISD::PACKSS: return "X86ISD::PACKSS";
20053 case X86ISD::PACKUS: return "X86ISD::PACKUS";
20054 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
20055 case X86ISD::VALIGN: return "X86ISD::VALIGN";
20056 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
20057 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
20058 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
20059 case X86ISD::SHUFP: return "X86ISD::SHUFP";
20060 case X86ISD::SHUF128: return "X86ISD::SHUF128";
20061 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
20062 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
20063 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
20064 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
20065 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
20066 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
20067 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
20068 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
20069 case X86ISD::MOVSD: return "X86ISD::MOVSD";
20070 case X86ISD::MOVSS: return "X86ISD::MOVSS";
20071 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
20072 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
20073 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
20074 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
20075 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
20076 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
20077 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
20078 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
20079 case X86ISD::VPERMV: return "X86ISD::VPERMV";
20080 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
20081 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
20082 case X86ISD::VPERMI: return "X86ISD::VPERMI";
20083 case X86ISD::VPTERNLOG: return "X86ISD::VPTERNLOG";
20084 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
20085 case X86ISD::VRANGE: return "X86ISD::VRANGE";
20086 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
20087 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
20088 case X86ISD::PSADBW: return "X86ISD::PSADBW";
20089 case X86ISD::DBPSADBW: return "X86ISD::DBPSADBW";
20090 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
20091 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
20092 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
20093 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
20094 case X86ISD::MFENCE: return "X86ISD::MFENCE";
20095 case X86ISD::SFENCE: return "X86ISD::SFENCE";
20096 case X86ISD::LFENCE: return "X86ISD::LFENCE";
20097 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
20098 case X86ISD::SAHF: return "X86ISD::SAHF";
20099 case X86ISD::RDRAND: return "X86ISD::RDRAND";
20100 case X86ISD::RDSEED: return "X86ISD::RDSEED";
20101 case X86ISD::VPMADDUBSW: return "X86ISD::VPMADDUBSW";
20102 case X86ISD::VPMADDWD: return "X86ISD::VPMADDWD";
20103 case X86ISD::VPROT: return "X86ISD::VPROT";
20104 case X86ISD::VPROTI: return "X86ISD::VPROTI";
20105 case X86ISD::VPSHA: return "X86ISD::VPSHA";
20106 case X86ISD::VPSHL: return "X86ISD::VPSHL";
20107 case X86ISD::VPCOM: return "X86ISD::VPCOM";
20108 case X86ISD::VPCOMU: return "X86ISD::VPCOMU";
20109 case X86ISD::FMADD: return "X86ISD::FMADD";
20110 case X86ISD::FMSUB: return "X86ISD::FMSUB";
20111 case X86ISD::FNMADD: return "X86ISD::FNMADD";
20112 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
20113 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
20114 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
20115 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
20116 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
20117 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
20118 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
20119 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
20120 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
20121 case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
20122 case X86ISD::VREDUCE: return "X86ISD::VREDUCE";
20123 case X86ISD::VGETMANT: return "X86ISD::VGETMANT";
20124 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
20125 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
20126 case X86ISD::XTEST: return "X86ISD::XTEST";
20127 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
20128 case X86ISD::EXPAND: return "X86ISD::EXPAND";
20129 case X86ISD::SELECT: return "X86ISD::SELECT";
20130 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
20131 case X86ISD::RCP28: return "X86ISD::RCP28";
20132 case X86ISD::EXP2: return "X86ISD::EXP2";
20133 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
20134 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
20135 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
20136 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
20137 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
20138 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
20139 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
20140 case X86ISD::SCALEF: return "X86ISD::SCALEF";
20141 case X86ISD::ADDS: return "X86ISD::ADDS";
20142 case X86ISD::SUBS: return "X86ISD::SUBS";
20143 case X86ISD::AVG: return "X86ISD::AVG";
20144 case X86ISD::MULHRS: return "X86ISD::MULHRS";
20145 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
20146 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
20147 case X86ISD::FP_TO_SINT_RND: return "X86ISD::FP_TO_SINT_RND";
20148 case X86ISD::FP_TO_UINT_RND: return "X86ISD::FP_TO_UINT_RND";
20149 case X86ISD::VFPCLASS: return "X86ISD::VFPCLASS";
20154 // isLegalAddressingMode - Return true if the addressing mode represented
20155 // by AM is legal for this target, for a load/store of the specified type.
20156 bool X86TargetLowering::isLegalAddressingMode(const DataLayout &DL,
20157 const AddrMode &AM, Type *Ty,
20158 unsigned AS) const {
20159 // X86 supports extremely general addressing modes.
20160 CodeModel::Model M = getTargetMachine().getCodeModel();
20161 Reloc::Model R = getTargetMachine().getRelocationModel();
20163 // X86 allows a sign-extended 32-bit immediate field as a displacement.
20164 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
20169 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
20171 // If a reference to this global requires an extra load, we can't fold it.
20172 if (isGlobalStubReference(GVFlags))
20175 // If BaseGV requires a register for the PIC base, we cannot also have a
20176 // BaseReg specified.
20177 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
20180 // If lower 4G is not available, then we must use rip-relative addressing.
20181 if ((M != CodeModel::Small || R != Reloc::Static) &&
20182 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
20186 switch (AM.Scale) {
20192 // These scales always work.
20197 // These scales are formed with basereg+scalereg. Only accept if there is
20202 default: // Other stuff never works.
20209 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
20210 unsigned Bits = Ty->getScalarSizeInBits();
20212 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
20213 // particularly cheaper than those without.
20217 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
20218 // variable shifts just as cheap as scalar ones.
20219 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
20222 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
20223 // fully general vector.
20227 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
20228 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20230 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
20231 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
20232 return NumBits1 > NumBits2;
20235 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
20236 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
20239 if (!isTypeLegal(EVT::getEVT(Ty1)))
20242 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
20244 // Assuming the caller doesn't have a zeroext or signext return parameter,
20245 // truncation all the way down to i1 is valid.
20249 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
20250 return isInt<32>(Imm);
20253 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
20254 // Can also use sub to handle negated immediates.
20255 return isInt<32>(Imm);
20258 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
20259 if (!VT1.isInteger() || !VT2.isInteger())
20261 unsigned NumBits1 = VT1.getSizeInBits();
20262 unsigned NumBits2 = VT2.getSizeInBits();
20263 return NumBits1 > NumBits2;
20266 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
20267 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20268 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
20271 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
20272 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
20273 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
20276 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
20277 EVT VT1 = Val.getValueType();
20278 if (isZExtFree(VT1, VT2))
20281 if (Val.getOpcode() != ISD::LOAD)
20284 if (!VT1.isSimple() || !VT1.isInteger() ||
20285 !VT2.isSimple() || !VT2.isInteger())
20288 switch (VT1.getSimpleVT().SimpleTy) {
20293 // X86 has 8, 16, and 32-bit zero-extending loads.
20300 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
20303 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
20304 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
20307 VT = VT.getScalarType();
20309 if (!VT.isSimple())
20312 switch (VT.getSimpleVT().SimpleTy) {
20323 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
20324 // i16 instructions are longer (0x66 prefix) and potentially slower.
20325 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
20328 /// isShuffleMaskLegal - Targets can use this to indicate that they only
20329 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
20330 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
20331 /// are assumed to be legal.
20333 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
20335 if (!VT.isSimple())
20338 // Not for i1 vectors
20339 if (VT.getScalarType() == MVT::i1)
20342 // Very little shuffling can be done for 64-bit vectors right now.
20343 if (VT.getSizeInBits() == 64)
20346 // We only care that the types being shuffled are legal. The lowering can
20347 // handle any possible shuffle mask that results.
20348 return isTypeLegal(VT.getSimpleVT());
20352 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
20354 // Just delegate to the generic legality, clear masks aren't special.
20355 return isShuffleMaskLegal(Mask, VT);
20358 //===----------------------------------------------------------------------===//
20359 // X86 Scheduler Hooks
20360 //===----------------------------------------------------------------------===//
20362 /// Utility function to emit xbegin specifying the start of an RTM region.
20363 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
20364 const TargetInstrInfo *TII) {
20365 DebugLoc DL = MI->getDebugLoc();
20367 const BasicBlock *BB = MBB->getBasicBlock();
20368 MachineFunction::iterator I = ++MBB->getIterator();
20370 // For the v = xbegin(), we generate
20381 MachineBasicBlock *thisMBB = MBB;
20382 MachineFunction *MF = MBB->getParent();
20383 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20384 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20385 MF->insert(I, mainMBB);
20386 MF->insert(I, sinkMBB);
20388 // Transfer the remainder of BB and its successor edges to sinkMBB.
20389 sinkMBB->splice(sinkMBB->begin(), MBB,
20390 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20391 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20395 // # fallthrough to mainMBB
20396 // # abortion to sinkMBB
20397 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
20398 thisMBB->addSuccessor(mainMBB);
20399 thisMBB->addSuccessor(sinkMBB);
20403 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
20404 mainMBB->addSuccessor(sinkMBB);
20407 // EAX is live into the sinkMBB
20408 sinkMBB->addLiveIn(X86::EAX);
20409 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20410 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20413 MI->eraseFromParent();
20417 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
20418 // or XMM0_V32I8 in AVX all of this code can be replaced with that
20419 // in the .td file.
20420 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
20421 const TargetInstrInfo *TII) {
20423 switch (MI->getOpcode()) {
20424 default: llvm_unreachable("illegal opcode!");
20425 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
20426 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
20427 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
20428 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
20429 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
20430 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
20431 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
20432 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
20435 DebugLoc dl = MI->getDebugLoc();
20436 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20438 unsigned NumArgs = MI->getNumOperands();
20439 for (unsigned i = 1; i < NumArgs; ++i) {
20440 MachineOperand &Op = MI->getOperand(i);
20441 if (!(Op.isReg() && Op.isImplicit()))
20442 MIB.addOperand(Op);
20444 if (MI->hasOneMemOperand())
20445 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20447 BuildMI(*BB, MI, dl,
20448 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20449 .addReg(X86::XMM0);
20451 MI->eraseFromParent();
20455 // FIXME: Custom handling because TableGen doesn't support multiple implicit
20456 // defs in an instruction pattern
20457 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
20458 const TargetInstrInfo *TII) {
20460 switch (MI->getOpcode()) {
20461 default: llvm_unreachable("illegal opcode!");
20462 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
20463 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
20464 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
20465 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
20466 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
20467 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
20468 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
20469 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
20472 DebugLoc dl = MI->getDebugLoc();
20473 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
20475 unsigned NumArgs = MI->getNumOperands(); // remove the results
20476 for (unsigned i = 1; i < NumArgs; ++i) {
20477 MachineOperand &Op = MI->getOperand(i);
20478 if (!(Op.isReg() && Op.isImplicit()))
20479 MIB.addOperand(Op);
20481 if (MI->hasOneMemOperand())
20482 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
20484 BuildMI(*BB, MI, dl,
20485 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
20488 MI->eraseFromParent();
20492 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
20493 const X86Subtarget *Subtarget) {
20494 DebugLoc dl = MI->getDebugLoc();
20495 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20496 // Address into RAX/EAX, other two args into ECX, EDX.
20497 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
20498 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
20499 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
20500 for (int i = 0; i < X86::AddrNumOperands; ++i)
20501 MIB.addOperand(MI->getOperand(i));
20503 unsigned ValOps = X86::AddrNumOperands;
20504 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
20505 .addReg(MI->getOperand(ValOps).getReg());
20506 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
20507 .addReg(MI->getOperand(ValOps+1).getReg());
20509 // The instruction doesn't actually take any operands though.
20510 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
20512 MI->eraseFromParent(); // The pseudo is gone now.
20516 MachineBasicBlock *
20517 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
20518 MachineBasicBlock *MBB) const {
20519 // Emit va_arg instruction on X86-64.
20521 // Operands to this pseudo-instruction:
20522 // 0 ) Output : destination address (reg)
20523 // 1-5) Input : va_list address (addr, i64mem)
20524 // 6 ) ArgSize : Size (in bytes) of vararg type
20525 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
20526 // 8 ) Align : Alignment of type
20527 // 9 ) EFLAGS (implicit-def)
20529 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
20530 static_assert(X86::AddrNumOperands == 5,
20531 "VAARG_64 assumes 5 address operands");
20533 unsigned DestReg = MI->getOperand(0).getReg();
20534 MachineOperand &Base = MI->getOperand(1);
20535 MachineOperand &Scale = MI->getOperand(2);
20536 MachineOperand &Index = MI->getOperand(3);
20537 MachineOperand &Disp = MI->getOperand(4);
20538 MachineOperand &Segment = MI->getOperand(5);
20539 unsigned ArgSize = MI->getOperand(6).getImm();
20540 unsigned ArgMode = MI->getOperand(7).getImm();
20541 unsigned Align = MI->getOperand(8).getImm();
20543 // Memory Reference
20544 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
20545 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20546 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20548 // Machine Information
20549 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20550 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
20551 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
20552 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
20553 DebugLoc DL = MI->getDebugLoc();
20555 // struct va_list {
20558 // i64 overflow_area (address)
20559 // i64 reg_save_area (address)
20561 // sizeof(va_list) = 24
20562 // alignment(va_list) = 8
20564 unsigned TotalNumIntRegs = 6;
20565 unsigned TotalNumXMMRegs = 8;
20566 bool UseGPOffset = (ArgMode == 1);
20567 bool UseFPOffset = (ArgMode == 2);
20568 unsigned MaxOffset = TotalNumIntRegs * 8 +
20569 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
20571 /* Align ArgSize to a multiple of 8 */
20572 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
20573 bool NeedsAlign = (Align > 8);
20575 MachineBasicBlock *thisMBB = MBB;
20576 MachineBasicBlock *overflowMBB;
20577 MachineBasicBlock *offsetMBB;
20578 MachineBasicBlock *endMBB;
20580 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
20581 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
20582 unsigned OffsetReg = 0;
20584 if (!UseGPOffset && !UseFPOffset) {
20585 // If we only pull from the overflow region, we don't create a branch.
20586 // We don't need to alter control flow.
20587 OffsetDestReg = 0; // unused
20588 OverflowDestReg = DestReg;
20590 offsetMBB = nullptr;
20591 overflowMBB = thisMBB;
20594 // First emit code to check if gp_offset (or fp_offset) is below the bound.
20595 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
20596 // If not, pull from overflow_area. (branch to overflowMBB)
20601 // offsetMBB overflowMBB
20606 // Registers for the PHI in endMBB
20607 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
20608 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
20610 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20611 MachineFunction *MF = MBB->getParent();
20612 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20613 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20614 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
20616 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20618 // Insert the new basic blocks
20619 MF->insert(MBBIter, offsetMBB);
20620 MF->insert(MBBIter, overflowMBB);
20621 MF->insert(MBBIter, endMBB);
20623 // Transfer the remainder of MBB and its successor edges to endMBB.
20624 endMBB->splice(endMBB->begin(), thisMBB,
20625 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
20626 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
20628 // Make offsetMBB and overflowMBB successors of thisMBB
20629 thisMBB->addSuccessor(offsetMBB);
20630 thisMBB->addSuccessor(overflowMBB);
20632 // endMBB is a successor of both offsetMBB and overflowMBB
20633 offsetMBB->addSuccessor(endMBB);
20634 overflowMBB->addSuccessor(endMBB);
20636 // Load the offset value into a register
20637 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20638 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
20642 .addDisp(Disp, UseFPOffset ? 4 : 0)
20643 .addOperand(Segment)
20644 .setMemRefs(MMOBegin, MMOEnd);
20646 // Check if there is enough room left to pull this argument.
20647 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
20649 .addImm(MaxOffset + 8 - ArgSizeA8);
20651 // Branch to "overflowMBB" if offset >= max
20652 // Fall through to "offsetMBB" otherwise
20653 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
20654 .addMBB(overflowMBB);
20657 // In offsetMBB, emit code to use the reg_save_area.
20659 assert(OffsetReg != 0);
20661 // Read the reg_save_area address.
20662 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
20663 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
20668 .addOperand(Segment)
20669 .setMemRefs(MMOBegin, MMOEnd);
20671 // Zero-extend the offset
20672 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
20673 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
20676 .addImm(X86::sub_32bit);
20678 // Add the offset to the reg_save_area to get the final address.
20679 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
20680 .addReg(OffsetReg64)
20681 .addReg(RegSaveReg);
20683 // Compute the offset for the next argument
20684 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
20685 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
20687 .addImm(UseFPOffset ? 16 : 8);
20689 // Store it back into the va_list.
20690 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
20694 .addDisp(Disp, UseFPOffset ? 4 : 0)
20695 .addOperand(Segment)
20696 .addReg(NextOffsetReg)
20697 .setMemRefs(MMOBegin, MMOEnd);
20700 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
20705 // Emit code to use overflow area
20708 // Load the overflow_area address into a register.
20709 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
20710 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
20715 .addOperand(Segment)
20716 .setMemRefs(MMOBegin, MMOEnd);
20718 // If we need to align it, do so. Otherwise, just copy the address
20719 // to OverflowDestReg.
20721 // Align the overflow address
20722 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
20723 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
20725 // aligned_addr = (addr + (align-1)) & ~(align-1)
20726 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
20727 .addReg(OverflowAddrReg)
20730 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
20732 .addImm(~(uint64_t)(Align-1));
20734 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
20735 .addReg(OverflowAddrReg);
20738 // Compute the next overflow address after this argument.
20739 // (the overflow address should be kept 8-byte aligned)
20740 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
20741 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
20742 .addReg(OverflowDestReg)
20743 .addImm(ArgSizeA8);
20745 // Store the new overflow address.
20746 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
20751 .addOperand(Segment)
20752 .addReg(NextAddrReg)
20753 .setMemRefs(MMOBegin, MMOEnd);
20755 // If we branched, emit the PHI to the front of endMBB.
20757 BuildMI(*endMBB, endMBB->begin(), DL,
20758 TII->get(X86::PHI), DestReg)
20759 .addReg(OffsetDestReg).addMBB(offsetMBB)
20760 .addReg(OverflowDestReg).addMBB(overflowMBB);
20763 // Erase the pseudo instruction
20764 MI->eraseFromParent();
20769 MachineBasicBlock *
20770 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
20772 MachineBasicBlock *MBB) const {
20773 // Emit code to save XMM registers to the stack. The ABI says that the
20774 // number of registers to save is given in %al, so it's theoretically
20775 // possible to do an indirect jump trick to avoid saving all of them,
20776 // however this code takes a simpler approach and just executes all
20777 // of the stores if %al is non-zero. It's less code, and it's probably
20778 // easier on the hardware branch predictor, and stores aren't all that
20779 // expensive anyway.
20781 // Create the new basic blocks. One block contains all the XMM stores,
20782 // and one block is the final destination regardless of whether any
20783 // stores were performed.
20784 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
20785 MachineFunction *F = MBB->getParent();
20786 MachineFunction::iterator MBBIter = ++MBB->getIterator();
20787 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
20788 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
20789 F->insert(MBBIter, XMMSaveMBB);
20790 F->insert(MBBIter, EndMBB);
20792 // Transfer the remainder of MBB and its successor edges to EndMBB.
20793 EndMBB->splice(EndMBB->begin(), MBB,
20794 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20795 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
20797 // The original block will now fall through to the XMM save block.
20798 MBB->addSuccessor(XMMSaveMBB);
20799 // The XMMSaveMBB will fall through to the end block.
20800 XMMSaveMBB->addSuccessor(EndMBB);
20802 // Now add the instructions.
20803 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20804 DebugLoc DL = MI->getDebugLoc();
20806 unsigned CountReg = MI->getOperand(0).getReg();
20807 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
20808 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
20810 if (!Subtarget->isCallingConvWin64(F->getFunction()->getCallingConv())) {
20811 // If %al is 0, branch around the XMM save block.
20812 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
20813 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
20814 MBB->addSuccessor(EndMBB);
20817 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
20818 // that was just emitted, but clearly shouldn't be "saved".
20819 assert((MI->getNumOperands() <= 3 ||
20820 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
20821 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
20822 && "Expected last argument to be EFLAGS");
20823 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
20824 // In the XMM save block, save all the XMM argument registers.
20825 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
20826 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
20827 MachineMemOperand *MMO = F->getMachineMemOperand(
20828 MachinePointerInfo::getFixedStack(*F, RegSaveFrameIndex, Offset),
20829 MachineMemOperand::MOStore,
20830 /*Size=*/16, /*Align=*/16);
20831 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
20832 .addFrameIndex(RegSaveFrameIndex)
20833 .addImm(/*Scale=*/1)
20834 .addReg(/*IndexReg=*/0)
20835 .addImm(/*Disp=*/Offset)
20836 .addReg(/*Segment=*/0)
20837 .addReg(MI->getOperand(i).getReg())
20838 .addMemOperand(MMO);
20841 MI->eraseFromParent(); // The pseudo instruction is gone now.
20846 // The EFLAGS operand of SelectItr might be missing a kill marker
20847 // because there were multiple uses of EFLAGS, and ISel didn't know
20848 // which to mark. Figure out whether SelectItr should have had a
20849 // kill marker, and set it if it should. Returns the correct kill
20851 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
20852 MachineBasicBlock* BB,
20853 const TargetRegisterInfo* TRI) {
20854 // Scan forward through BB for a use/def of EFLAGS.
20855 MachineBasicBlock::iterator miI(std::next(SelectItr));
20856 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
20857 const MachineInstr& mi = *miI;
20858 if (mi.readsRegister(X86::EFLAGS))
20860 if (mi.definesRegister(X86::EFLAGS))
20861 break; // Should have kill-flag - update below.
20864 // If we hit the end of the block, check whether EFLAGS is live into a
20866 if (miI == BB->end()) {
20867 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
20868 sEnd = BB->succ_end();
20869 sItr != sEnd; ++sItr) {
20870 MachineBasicBlock* succ = *sItr;
20871 if (succ->isLiveIn(X86::EFLAGS))
20876 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
20877 // out. SelectMI should have a kill flag on EFLAGS.
20878 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
20882 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
20883 // together with other CMOV pseudo-opcodes into a single basic-block with
20884 // conditional jump around it.
20885 static bool isCMOVPseudo(MachineInstr *MI) {
20886 switch (MI->getOpcode()) {
20887 case X86::CMOV_FR32:
20888 case X86::CMOV_FR64:
20889 case X86::CMOV_GR8:
20890 case X86::CMOV_GR16:
20891 case X86::CMOV_GR32:
20892 case X86::CMOV_RFP32:
20893 case X86::CMOV_RFP64:
20894 case X86::CMOV_RFP80:
20895 case X86::CMOV_V2F64:
20896 case X86::CMOV_V2I64:
20897 case X86::CMOV_V4F32:
20898 case X86::CMOV_V4F64:
20899 case X86::CMOV_V4I64:
20900 case X86::CMOV_V16F32:
20901 case X86::CMOV_V8F32:
20902 case X86::CMOV_V8F64:
20903 case X86::CMOV_V8I64:
20904 case X86::CMOV_V8I1:
20905 case X86::CMOV_V16I1:
20906 case X86::CMOV_V32I1:
20907 case X86::CMOV_V64I1:
20915 MachineBasicBlock *
20916 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
20917 MachineBasicBlock *BB) const {
20918 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20919 DebugLoc DL = MI->getDebugLoc();
20921 // To "insert" a SELECT_CC instruction, we actually have to insert the
20922 // diamond control-flow pattern. The incoming instruction knows the
20923 // destination vreg to set, the condition code register to branch on, the
20924 // true/false values to select between, and a branch opcode to use.
20925 const BasicBlock *LLVM_BB = BB->getBasicBlock();
20926 MachineFunction::iterator It = ++BB->getIterator();
20931 // cmpTY ccX, r1, r2
20933 // fallthrough --> copy0MBB
20934 MachineBasicBlock *thisMBB = BB;
20935 MachineFunction *F = BB->getParent();
20937 // This code lowers all pseudo-CMOV instructions. Generally it lowers these
20938 // as described above, by inserting a BB, and then making a PHI at the join
20939 // point to select the true and false operands of the CMOV in the PHI.
20941 // The code also handles two different cases of multiple CMOV opcodes
20945 // In this case, there are multiple CMOVs in a row, all which are based on
20946 // the same condition setting (or the exact opposite condition setting).
20947 // In this case we can lower all the CMOVs using a single inserted BB, and
20948 // then make a number of PHIs at the join point to model the CMOVs. The only
20949 // trickiness here, is that in a case like:
20951 // t2 = CMOV cond1 t1, f1
20952 // t3 = CMOV cond1 t2, f2
20954 // when rewriting this into PHIs, we have to perform some renaming on the
20955 // temps since you cannot have a PHI operand refer to a PHI result earlier
20956 // in the same block. The "simple" but wrong lowering would be:
20958 // t2 = PHI t1(BB1), f1(BB2)
20959 // t3 = PHI t2(BB1), f2(BB2)
20961 // but clearly t2 is not defined in BB1, so that is incorrect. The proper
20962 // renaming is to note that on the path through BB1, t2 is really just a
20963 // copy of t1, and do that renaming, properly generating:
20965 // t2 = PHI t1(BB1), f1(BB2)
20966 // t3 = PHI t1(BB1), f2(BB2)
20968 // Case 2, we lower cascaded CMOVs such as
20970 // (CMOV (CMOV F, T, cc1), T, cc2)
20972 // to two successives branches. For that, we look for another CMOV as the
20973 // following instruction.
20975 // Without this, we would add a PHI between the two jumps, which ends up
20976 // creating a few copies all around. For instance, for
20978 // (sitofp (zext (fcmp une)))
20980 // we would generate:
20982 // ucomiss %xmm1, %xmm0
20983 // movss <1.0f>, %xmm0
20984 // movaps %xmm0, %xmm1
20986 // xorps %xmm1, %xmm1
20989 // movaps %xmm1, %xmm0
20993 // because this custom-inserter would have generated:
21005 // A: X = ...; Y = ...
21007 // C: Z = PHI [X, A], [Y, B]
21009 // E: PHI [X, C], [Z, D]
21011 // If we lower both CMOVs in a single step, we can instead generate:
21023 // A: X = ...; Y = ...
21025 // E: PHI [X, A], [X, C], [Y, D]
21027 // Which, in our sitofp/fcmp example, gives us something like:
21029 // ucomiss %xmm1, %xmm0
21030 // movss <1.0f>, %xmm0
21033 // xorps %xmm0, %xmm0
21037 MachineInstr *CascadedCMOV = nullptr;
21038 MachineInstr *LastCMOV = MI;
21039 X86::CondCode CC = X86::CondCode(MI->getOperand(3).getImm());
21040 X86::CondCode OppCC = X86::GetOppositeBranchCondition(CC);
21041 MachineBasicBlock::iterator NextMIIt =
21042 std::next(MachineBasicBlock::iterator(MI));
21044 // Check for case 1, where there are multiple CMOVs with the same condition
21045 // first. Of the two cases of multiple CMOV lowerings, case 1 reduces the
21046 // number of jumps the most.
21048 if (isCMOVPseudo(MI)) {
21049 // See if we have a string of CMOVS with the same condition.
21050 while (NextMIIt != BB->end() &&
21051 isCMOVPseudo(NextMIIt) &&
21052 (NextMIIt->getOperand(3).getImm() == CC ||
21053 NextMIIt->getOperand(3).getImm() == OppCC)) {
21054 LastCMOV = &*NextMIIt;
21059 // This checks for case 2, but only do this if we didn't already find
21060 // case 1, as indicated by LastCMOV == MI.
21061 if (LastCMOV == MI &&
21062 NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
21063 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
21064 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg()) {
21065 CascadedCMOV = &*NextMIIt;
21068 MachineBasicBlock *jcc1MBB = nullptr;
21070 // If we have a cascaded CMOV, we lower it to two successive branches to
21071 // the same block. EFLAGS is used by both, so mark it as live in the second.
21072 if (CascadedCMOV) {
21073 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
21074 F->insert(It, jcc1MBB);
21075 jcc1MBB->addLiveIn(X86::EFLAGS);
21078 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
21079 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
21080 F->insert(It, copy0MBB);
21081 F->insert(It, sinkMBB);
21083 // If the EFLAGS register isn't dead in the terminator, then claim that it's
21084 // live into the sink and copy blocks.
21085 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
21087 MachineInstr *LastEFLAGSUser = CascadedCMOV ? CascadedCMOV : LastCMOV;
21088 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
21089 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
21090 copy0MBB->addLiveIn(X86::EFLAGS);
21091 sinkMBB->addLiveIn(X86::EFLAGS);
21094 // Transfer the remainder of BB and its successor edges to sinkMBB.
21095 sinkMBB->splice(sinkMBB->begin(), BB,
21096 std::next(MachineBasicBlock::iterator(LastCMOV)), BB->end());
21097 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
21099 // Add the true and fallthrough blocks as its successors.
21100 if (CascadedCMOV) {
21101 // The fallthrough block may be jcc1MBB, if we have a cascaded CMOV.
21102 BB->addSuccessor(jcc1MBB);
21104 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
21105 // jump to the sinkMBB.
21106 jcc1MBB->addSuccessor(copy0MBB);
21107 jcc1MBB->addSuccessor(sinkMBB);
21109 BB->addSuccessor(copy0MBB);
21112 // The true block target of the first (or only) branch is always sinkMBB.
21113 BB->addSuccessor(sinkMBB);
21115 // Create the conditional branch instruction.
21116 unsigned Opc = X86::GetCondBranchFromCond(CC);
21117 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
21119 if (CascadedCMOV) {
21120 unsigned Opc2 = X86::GetCondBranchFromCond(
21121 (X86::CondCode)CascadedCMOV->getOperand(3).getImm());
21122 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
21126 // %FalseValue = ...
21127 // # fallthrough to sinkMBB
21128 copy0MBB->addSuccessor(sinkMBB);
21131 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
21133 MachineBasicBlock::iterator MIItBegin = MachineBasicBlock::iterator(MI);
21134 MachineBasicBlock::iterator MIItEnd =
21135 std::next(MachineBasicBlock::iterator(LastCMOV));
21136 MachineBasicBlock::iterator SinkInsertionPoint = sinkMBB->begin();
21137 DenseMap<unsigned, std::pair<unsigned, unsigned>> RegRewriteTable;
21138 MachineInstrBuilder MIB;
21140 // As we are creating the PHIs, we have to be careful if there is more than
21141 // one. Later CMOVs may reference the results of earlier CMOVs, but later
21142 // PHIs have to reference the individual true/false inputs from earlier PHIs.
21143 // That also means that PHI construction must work forward from earlier to
21144 // later, and that the code must maintain a mapping from earlier PHI's
21145 // destination registers, and the registers that went into the PHI.
21147 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; ++MIIt) {
21148 unsigned DestReg = MIIt->getOperand(0).getReg();
21149 unsigned Op1Reg = MIIt->getOperand(1).getReg();
21150 unsigned Op2Reg = MIIt->getOperand(2).getReg();
21152 // If this CMOV we are generating is the opposite condition from
21153 // the jump we generated, then we have to swap the operands for the
21154 // PHI that is going to be generated.
21155 if (MIIt->getOperand(3).getImm() == OppCC)
21156 std::swap(Op1Reg, Op2Reg);
21158 if (RegRewriteTable.find(Op1Reg) != RegRewriteTable.end())
21159 Op1Reg = RegRewriteTable[Op1Reg].first;
21161 if (RegRewriteTable.find(Op2Reg) != RegRewriteTable.end())
21162 Op2Reg = RegRewriteTable[Op2Reg].second;
21164 MIB = BuildMI(*sinkMBB, SinkInsertionPoint, DL,
21165 TII->get(X86::PHI), DestReg)
21166 .addReg(Op1Reg).addMBB(copy0MBB)
21167 .addReg(Op2Reg).addMBB(thisMBB);
21169 // Add this PHI to the rewrite table.
21170 RegRewriteTable[DestReg] = std::make_pair(Op1Reg, Op2Reg);
21173 // If we have a cascaded CMOV, the second Jcc provides the same incoming
21174 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
21175 if (CascadedCMOV) {
21176 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
21177 // Copy the PHI result to the register defined by the second CMOV.
21178 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
21179 DL, TII->get(TargetOpcode::COPY),
21180 CascadedCMOV->getOperand(0).getReg())
21181 .addReg(MI->getOperand(0).getReg());
21182 CascadedCMOV->eraseFromParent();
21185 // Now remove the CMOV(s).
21186 for (MachineBasicBlock::iterator MIIt = MIItBegin; MIIt != MIItEnd; )
21187 (MIIt++)->eraseFromParent();
21192 MachineBasicBlock *
21193 X86TargetLowering::EmitLoweredAtomicFP(MachineInstr *MI,
21194 MachineBasicBlock *BB) const {
21195 // Combine the following atomic floating-point modification pattern:
21196 // a.store(reg OP a.load(acquire), release)
21197 // Transform them into:
21198 // OPss (%gpr), %xmm
21199 // movss %xmm, (%gpr)
21200 // Or sd equivalent for 64-bit operations.
21202 switch (MI->getOpcode()) {
21203 default: llvm_unreachable("unexpected instr type for EmitLoweredAtomicFP");
21204 case X86::RELEASE_FADD32mr: MOp = X86::MOVSSmr; FOp = X86::ADDSSrm; break;
21205 case X86::RELEASE_FADD64mr: MOp = X86::MOVSDmr; FOp = X86::ADDSDrm; break;
21207 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21208 DebugLoc DL = MI->getDebugLoc();
21209 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
21210 MachineOperand MSrc = MI->getOperand(0);
21211 unsigned VSrc = MI->getOperand(5).getReg();
21212 const MachineOperand &Disp = MI->getOperand(3);
21213 MachineOperand ZeroDisp = MachineOperand::CreateImm(0);
21214 bool hasDisp = Disp.isGlobal() || Disp.isImm();
21215 if (hasDisp && MSrc.isReg())
21216 MSrc.setIsKill(false);
21217 MachineInstrBuilder MIM = BuildMI(*BB, MI, DL, TII->get(MOp))
21218 .addOperand(/*Base=*/MSrc)
21219 .addImm(/*Scale=*/1)
21220 .addReg(/*Index=*/0)
21221 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21223 MachineInstr *MIO = BuildMI(*BB, (MachineInstr *)MIM, DL, TII->get(FOp),
21224 MRI.createVirtualRegister(MRI.getRegClass(VSrc)))
21226 .addOperand(/*Base=*/MSrc)
21227 .addImm(/*Scale=*/1)
21228 .addReg(/*Index=*/0)
21229 .addDisp(hasDisp ? Disp : ZeroDisp, /*off=*/0)
21230 .addReg(/*Segment=*/0);
21231 MIM.addReg(MIO->getOperand(0).getReg(), RegState::Kill);
21232 MI->eraseFromParent(); // The pseudo instruction is gone now.
21236 MachineBasicBlock *
21237 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
21238 MachineBasicBlock *BB) const {
21239 MachineFunction *MF = BB->getParent();
21240 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21241 DebugLoc DL = MI->getDebugLoc();
21242 const BasicBlock *LLVM_BB = BB->getBasicBlock();
21244 assert(MF->shouldSplitStack());
21246 const bool Is64Bit = Subtarget->is64Bit();
21247 const bool IsLP64 = Subtarget->isTarget64BitLP64();
21249 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
21250 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
21253 // ... [Till the alloca]
21254 // If stacklet is not large enough, jump to mallocMBB
21257 // Allocate by subtracting from RSP
21258 // Jump to continueMBB
21261 // Allocate by call to runtime
21265 // [rest of original BB]
21268 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21269 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21270 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
21272 MachineRegisterInfo &MRI = MF->getRegInfo();
21273 const TargetRegisterClass *AddrRegClass =
21274 getRegClassFor(getPointerTy(MF->getDataLayout()));
21276 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21277 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
21278 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
21279 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
21280 sizeVReg = MI->getOperand(1).getReg(),
21281 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
21283 MachineFunction::iterator MBBIter = ++BB->getIterator();
21285 MF->insert(MBBIter, bumpMBB);
21286 MF->insert(MBBIter, mallocMBB);
21287 MF->insert(MBBIter, continueMBB);
21289 continueMBB->splice(continueMBB->begin(), BB,
21290 std::next(MachineBasicBlock::iterator(MI)), BB->end());
21291 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
21293 // Add code to the main basic block to check if the stack limit has been hit,
21294 // and if so, jump to mallocMBB otherwise to bumpMBB.
21295 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
21296 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
21297 .addReg(tmpSPVReg).addReg(sizeVReg);
21298 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
21299 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
21300 .addReg(SPLimitVReg);
21301 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
21303 // bumpMBB simply decreases the stack pointer, since we know the current
21304 // stacklet has enough space.
21305 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
21306 .addReg(SPLimitVReg);
21307 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
21308 .addReg(SPLimitVReg);
21309 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21311 // Calls into a routine in libgcc to allocate more space from the heap.
21312 const uint32_t *RegMask =
21313 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
21315 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
21317 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21318 .addExternalSymbol("__morestack_allocate_stack_space")
21319 .addRegMask(RegMask)
21320 .addReg(X86::RDI, RegState::Implicit)
21321 .addReg(X86::RAX, RegState::ImplicitDefine);
21322 } else if (Is64Bit) {
21323 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
21325 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
21326 .addExternalSymbol("__morestack_allocate_stack_space")
21327 .addRegMask(RegMask)
21328 .addReg(X86::EDI, RegState::Implicit)
21329 .addReg(X86::EAX, RegState::ImplicitDefine);
21331 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
21333 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
21334 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
21335 .addExternalSymbol("__morestack_allocate_stack_space")
21336 .addRegMask(RegMask)
21337 .addReg(X86::EAX, RegState::ImplicitDefine);
21341 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
21344 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
21345 .addReg(IsLP64 ? X86::RAX : X86::EAX);
21346 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
21348 // Set up the CFG correctly.
21349 BB->addSuccessor(bumpMBB);
21350 BB->addSuccessor(mallocMBB);
21351 mallocMBB->addSuccessor(continueMBB);
21352 bumpMBB->addSuccessor(continueMBB);
21354 // Take care of the PHI nodes.
21355 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
21356 MI->getOperand(0).getReg())
21357 .addReg(mallocPtrVReg).addMBB(mallocMBB)
21358 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
21360 // Delete the original pseudo instruction.
21361 MI->eraseFromParent();
21364 return continueMBB;
21367 MachineBasicBlock *
21368 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
21369 MachineBasicBlock *BB) const {
21370 DebugLoc DL = MI->getDebugLoc();
21372 assert(!Subtarget->isTargetMachO());
21374 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
21377 MI->eraseFromParent(); // The pseudo instruction is gone now.
21381 MachineBasicBlock *
21382 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
21383 MachineBasicBlock *BB) const {
21384 // This is pretty easy. We're taking the value that we received from
21385 // our load from the relocation, sticking it in either RDI (x86-64)
21386 // or EAX and doing an indirect call. The return value will then
21387 // be in the normal return register.
21388 MachineFunction *F = BB->getParent();
21389 const X86InstrInfo *TII = Subtarget->getInstrInfo();
21390 DebugLoc DL = MI->getDebugLoc();
21392 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
21393 assert(MI->getOperand(3).isGlobal() && "This should be a global");
21395 // Get a register mask for the lowered call.
21396 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
21397 // proper register mask.
21398 const uint32_t *RegMask =
21399 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
21400 if (Subtarget->is64Bit()) {
21401 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21402 TII->get(X86::MOV64rm), X86::RDI)
21404 .addImm(0).addReg(0)
21405 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21406 MI->getOperand(3).getTargetFlags())
21408 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
21409 addDirectMem(MIB, X86::RDI);
21410 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
21411 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
21412 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21413 TII->get(X86::MOV32rm), X86::EAX)
21415 .addImm(0).addReg(0)
21416 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21417 MI->getOperand(3).getTargetFlags())
21419 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21420 addDirectMem(MIB, X86::EAX);
21421 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21423 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
21424 TII->get(X86::MOV32rm), X86::EAX)
21425 .addReg(TII->getGlobalBaseReg(F))
21426 .addImm(0).addReg(0)
21427 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
21428 MI->getOperand(3).getTargetFlags())
21430 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
21431 addDirectMem(MIB, X86::EAX);
21432 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
21435 MI->eraseFromParent(); // The pseudo instruction is gone now.
21439 MachineBasicBlock *
21440 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
21441 MachineBasicBlock *MBB) const {
21442 DebugLoc DL = MI->getDebugLoc();
21443 MachineFunction *MF = MBB->getParent();
21444 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21445 MachineRegisterInfo &MRI = MF->getRegInfo();
21447 const BasicBlock *BB = MBB->getBasicBlock();
21448 MachineFunction::iterator I = ++MBB->getIterator();
21450 // Memory Reference
21451 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21452 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21455 unsigned MemOpndSlot = 0;
21457 unsigned CurOp = 0;
21459 DstReg = MI->getOperand(CurOp++).getReg();
21460 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
21461 assert(RC->hasType(MVT::i32) && "Invalid destination!");
21462 unsigned mainDstReg = MRI.createVirtualRegister(RC);
21463 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
21465 MemOpndSlot = CurOp;
21467 MVT PVT = getPointerTy(MF->getDataLayout());
21468 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21469 "Invalid Pointer Size!");
21471 // For v = setjmp(buf), we generate
21474 // buf[LabelOffset] = restoreMBB <-- takes address of restoreMBB
21475 // SjLjSetup restoreMBB
21481 // v = phi(main, restore)
21484 // if base pointer being used, load it from frame
21487 MachineBasicBlock *thisMBB = MBB;
21488 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
21489 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
21490 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
21491 MF->insert(I, mainMBB);
21492 MF->insert(I, sinkMBB);
21493 MF->push_back(restoreMBB);
21494 restoreMBB->setHasAddressTaken();
21496 MachineInstrBuilder MIB;
21498 // Transfer the remainder of BB and its successor edges to sinkMBB.
21499 sinkMBB->splice(sinkMBB->begin(), MBB,
21500 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
21501 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
21504 unsigned PtrStoreOpc = 0;
21505 unsigned LabelReg = 0;
21506 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21507 Reloc::Model RM = MF->getTarget().getRelocationModel();
21508 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
21509 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
21511 // Prepare IP either in reg or imm.
21512 if (!UseImmLabel) {
21513 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
21514 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
21515 LabelReg = MRI.createVirtualRegister(PtrRC);
21516 if (Subtarget->is64Bit()) {
21517 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
21521 .addMBB(restoreMBB)
21524 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
21525 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
21526 .addReg(XII->getGlobalBaseReg(MF))
21529 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
21533 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
21535 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
21536 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21537 if (i == X86::AddrDisp)
21538 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
21540 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
21543 MIB.addReg(LabelReg);
21545 MIB.addMBB(restoreMBB);
21546 MIB.setMemRefs(MMOBegin, MMOEnd);
21548 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
21549 .addMBB(restoreMBB);
21551 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21552 MIB.addRegMask(RegInfo->getNoPreservedMask());
21553 thisMBB->addSuccessor(mainMBB);
21554 thisMBB->addSuccessor(restoreMBB);
21558 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
21559 mainMBB->addSuccessor(sinkMBB);
21562 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
21563 TII->get(X86::PHI), DstReg)
21564 .addReg(mainDstReg).addMBB(mainMBB)
21565 .addReg(restoreDstReg).addMBB(restoreMBB);
21568 if (RegInfo->hasBasePointer(*MF)) {
21569 const bool Uses64BitFramePtr =
21570 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
21571 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
21572 X86FI->setRestoreBasePointer(MF);
21573 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
21574 unsigned BasePtr = RegInfo->getBaseRegister();
21575 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
21576 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
21577 FramePtr, true, X86FI->getRestoreBasePointerOffset())
21578 .setMIFlag(MachineInstr::FrameSetup);
21580 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
21581 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
21582 restoreMBB->addSuccessor(sinkMBB);
21584 MI->eraseFromParent();
21588 MachineBasicBlock *
21589 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
21590 MachineBasicBlock *MBB) const {
21591 DebugLoc DL = MI->getDebugLoc();
21592 MachineFunction *MF = MBB->getParent();
21593 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21594 MachineRegisterInfo &MRI = MF->getRegInfo();
21596 // Memory Reference
21597 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
21598 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
21600 MVT PVT = getPointerTy(MF->getDataLayout());
21601 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
21602 "Invalid Pointer Size!");
21604 const TargetRegisterClass *RC =
21605 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
21606 unsigned Tmp = MRI.createVirtualRegister(RC);
21607 // Since FP is only updated here but NOT referenced, it's treated as GPR.
21608 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
21609 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
21610 unsigned SP = RegInfo->getStackRegister();
21612 MachineInstrBuilder MIB;
21614 const int64_t LabelOffset = 1 * PVT.getStoreSize();
21615 const int64_t SPOffset = 2 * PVT.getStoreSize();
21617 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
21618 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
21621 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
21622 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
21623 MIB.addOperand(MI->getOperand(i));
21624 MIB.setMemRefs(MMOBegin, MMOEnd);
21626 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
21627 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21628 if (i == X86::AddrDisp)
21629 MIB.addDisp(MI->getOperand(i), LabelOffset);
21631 MIB.addOperand(MI->getOperand(i));
21633 MIB.setMemRefs(MMOBegin, MMOEnd);
21635 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
21636 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
21637 if (i == X86::AddrDisp)
21638 MIB.addDisp(MI->getOperand(i), SPOffset);
21640 MIB.addOperand(MI->getOperand(i));
21642 MIB.setMemRefs(MMOBegin, MMOEnd);
21644 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
21646 MI->eraseFromParent();
21650 // Replace 213-type (isel default) FMA3 instructions with 231-type for
21651 // accumulator loops. Writing back to the accumulator allows the coalescer
21652 // to remove extra copies in the loop.
21653 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
21654 MachineBasicBlock *
21655 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
21656 MachineBasicBlock *MBB) const {
21657 MachineOperand &AddendOp = MI->getOperand(3);
21659 // Bail out early if the addend isn't a register - we can't switch these.
21660 if (!AddendOp.isReg())
21663 MachineFunction &MF = *MBB->getParent();
21664 MachineRegisterInfo &MRI = MF.getRegInfo();
21666 // Check whether the addend is defined by a PHI:
21667 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
21668 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
21669 if (!AddendDef.isPHI())
21672 // Look for the following pattern:
21674 // %addend = phi [%entry, 0], [%loop, %result]
21676 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
21680 // %addend = phi [%entry, 0], [%loop, %result]
21682 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
21684 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
21685 assert(AddendDef.getOperand(i).isReg());
21686 MachineOperand PHISrcOp = AddendDef.getOperand(i);
21687 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
21688 if (&PHISrcInst == MI) {
21689 // Found a matching instruction.
21690 unsigned NewFMAOpc = 0;
21691 switch (MI->getOpcode()) {
21692 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
21693 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
21694 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
21695 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
21696 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
21697 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
21698 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
21699 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
21700 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
21701 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
21702 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
21703 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
21704 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
21705 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
21706 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
21707 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
21708 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
21709 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
21710 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
21711 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
21713 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
21714 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
21715 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
21716 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
21717 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
21718 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
21719 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
21720 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
21721 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
21722 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
21723 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
21724 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
21725 default: llvm_unreachable("Unrecognized FMA variant.");
21728 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
21729 MachineInstrBuilder MIB =
21730 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
21731 .addOperand(MI->getOperand(0))
21732 .addOperand(MI->getOperand(3))
21733 .addOperand(MI->getOperand(2))
21734 .addOperand(MI->getOperand(1));
21735 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
21736 MI->eraseFromParent();
21743 MachineBasicBlock *
21744 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
21745 MachineBasicBlock *BB) const {
21746 switch (MI->getOpcode()) {
21747 default: llvm_unreachable("Unexpected instr type to insert");
21748 case X86::TAILJMPd64:
21749 case X86::TAILJMPr64:
21750 case X86::TAILJMPm64:
21751 case X86::TAILJMPd64_REX:
21752 case X86::TAILJMPr64_REX:
21753 case X86::TAILJMPm64_REX:
21754 llvm_unreachable("TAILJMP64 would not be touched here.");
21755 case X86::TCRETURNdi64:
21756 case X86::TCRETURNri64:
21757 case X86::TCRETURNmi64:
21759 case X86::WIN_ALLOCA:
21760 return EmitLoweredWinAlloca(MI, BB);
21761 case X86::SEG_ALLOCA_32:
21762 case X86::SEG_ALLOCA_64:
21763 return EmitLoweredSegAlloca(MI, BB);
21764 case X86::TLSCall_32:
21765 case X86::TLSCall_64:
21766 return EmitLoweredTLSCall(MI, BB);
21767 case X86::CMOV_FR32:
21768 case X86::CMOV_FR64:
21769 case X86::CMOV_GR8:
21770 case X86::CMOV_GR16:
21771 case X86::CMOV_GR32:
21772 case X86::CMOV_RFP32:
21773 case X86::CMOV_RFP64:
21774 case X86::CMOV_RFP80:
21775 case X86::CMOV_V2F64:
21776 case X86::CMOV_V2I64:
21777 case X86::CMOV_V4F32:
21778 case X86::CMOV_V4F64:
21779 case X86::CMOV_V4I64:
21780 case X86::CMOV_V16F32:
21781 case X86::CMOV_V8F32:
21782 case X86::CMOV_V8F64:
21783 case X86::CMOV_V8I64:
21784 case X86::CMOV_V8I1:
21785 case X86::CMOV_V16I1:
21786 case X86::CMOV_V32I1:
21787 case X86::CMOV_V64I1:
21788 return EmitLoweredSelect(MI, BB);
21790 case X86::RELEASE_FADD32mr:
21791 case X86::RELEASE_FADD64mr:
21792 return EmitLoweredAtomicFP(MI, BB);
21794 case X86::FP32_TO_INT16_IN_MEM:
21795 case X86::FP32_TO_INT32_IN_MEM:
21796 case X86::FP32_TO_INT64_IN_MEM:
21797 case X86::FP64_TO_INT16_IN_MEM:
21798 case X86::FP64_TO_INT32_IN_MEM:
21799 case X86::FP64_TO_INT64_IN_MEM:
21800 case X86::FP80_TO_INT16_IN_MEM:
21801 case X86::FP80_TO_INT32_IN_MEM:
21802 case X86::FP80_TO_INT64_IN_MEM: {
21803 MachineFunction *F = BB->getParent();
21804 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
21805 DebugLoc DL = MI->getDebugLoc();
21807 // Change the floating point control register to use "round towards zero"
21808 // mode when truncating to an integer value.
21809 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
21810 addFrameReference(BuildMI(*BB, MI, DL,
21811 TII->get(X86::FNSTCW16m)), CWFrameIdx);
21813 // Load the old value of the high byte of the control word...
21815 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
21816 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
21819 // Set the high part to be round to zero...
21820 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
21823 // Reload the modified control word now...
21824 addFrameReference(BuildMI(*BB, MI, DL,
21825 TII->get(X86::FLDCW16m)), CWFrameIdx);
21827 // Restore the memory image of control word to original value
21828 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
21831 // Get the X86 opcode to use.
21833 switch (MI->getOpcode()) {
21834 default: llvm_unreachable("illegal opcode!");
21835 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
21836 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
21837 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
21838 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
21839 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
21840 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
21841 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
21842 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
21843 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
21847 MachineOperand &Op = MI->getOperand(0);
21849 AM.BaseType = X86AddressMode::RegBase;
21850 AM.Base.Reg = Op.getReg();
21852 AM.BaseType = X86AddressMode::FrameIndexBase;
21853 AM.Base.FrameIndex = Op.getIndex();
21855 Op = MI->getOperand(1);
21857 AM.Scale = Op.getImm();
21858 Op = MI->getOperand(2);
21860 AM.IndexReg = Op.getImm();
21861 Op = MI->getOperand(3);
21862 if (Op.isGlobal()) {
21863 AM.GV = Op.getGlobal();
21865 AM.Disp = Op.getImm();
21867 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
21868 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
21870 // Reload the original control word now.
21871 addFrameReference(BuildMI(*BB, MI, DL,
21872 TII->get(X86::FLDCW16m)), CWFrameIdx);
21874 MI->eraseFromParent(); // The pseudo instruction is gone now.
21877 // String/text processing lowering.
21878 case X86::PCMPISTRM128REG:
21879 case X86::VPCMPISTRM128REG:
21880 case X86::PCMPISTRM128MEM:
21881 case X86::VPCMPISTRM128MEM:
21882 case X86::PCMPESTRM128REG:
21883 case X86::VPCMPESTRM128REG:
21884 case X86::PCMPESTRM128MEM:
21885 case X86::VPCMPESTRM128MEM:
21886 assert(Subtarget->hasSSE42() &&
21887 "Target must have SSE4.2 or AVX features enabled");
21888 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
21890 // String/text processing lowering.
21891 case X86::PCMPISTRIREG:
21892 case X86::VPCMPISTRIREG:
21893 case X86::PCMPISTRIMEM:
21894 case X86::VPCMPISTRIMEM:
21895 case X86::PCMPESTRIREG:
21896 case X86::VPCMPESTRIREG:
21897 case X86::PCMPESTRIMEM:
21898 case X86::VPCMPESTRIMEM:
21899 assert(Subtarget->hasSSE42() &&
21900 "Target must have SSE4.2 or AVX features enabled");
21901 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
21903 // Thread synchronization.
21905 return EmitMonitor(MI, BB, Subtarget);
21909 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
21911 case X86::VASTART_SAVE_XMM_REGS:
21912 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
21914 case X86::VAARG_64:
21915 return EmitVAARG64WithCustomInserter(MI, BB);
21917 case X86::EH_SjLj_SetJmp32:
21918 case X86::EH_SjLj_SetJmp64:
21919 return emitEHSjLjSetJmp(MI, BB);
21921 case X86::EH_SjLj_LongJmp32:
21922 case X86::EH_SjLj_LongJmp64:
21923 return emitEHSjLjLongJmp(MI, BB);
21925 case TargetOpcode::STATEPOINT:
21926 // As an implementation detail, STATEPOINT shares the STACKMAP format at
21927 // this point in the process. We diverge later.
21928 return emitPatchPoint(MI, BB);
21930 case TargetOpcode::STACKMAP:
21931 case TargetOpcode::PATCHPOINT:
21932 return emitPatchPoint(MI, BB);
21934 case X86::VFMADDPDr213r:
21935 case X86::VFMADDPSr213r:
21936 case X86::VFMADDSDr213r:
21937 case X86::VFMADDSSr213r:
21938 case X86::VFMSUBPDr213r:
21939 case X86::VFMSUBPSr213r:
21940 case X86::VFMSUBSDr213r:
21941 case X86::VFMSUBSSr213r:
21942 case X86::VFNMADDPDr213r:
21943 case X86::VFNMADDPSr213r:
21944 case X86::VFNMADDSDr213r:
21945 case X86::VFNMADDSSr213r:
21946 case X86::VFNMSUBPDr213r:
21947 case X86::VFNMSUBPSr213r:
21948 case X86::VFNMSUBSDr213r:
21949 case X86::VFNMSUBSSr213r:
21950 case X86::VFMADDSUBPDr213r:
21951 case X86::VFMADDSUBPSr213r:
21952 case X86::VFMSUBADDPDr213r:
21953 case X86::VFMSUBADDPSr213r:
21954 case X86::VFMADDPDr213rY:
21955 case X86::VFMADDPSr213rY:
21956 case X86::VFMSUBPDr213rY:
21957 case X86::VFMSUBPSr213rY:
21958 case X86::VFNMADDPDr213rY:
21959 case X86::VFNMADDPSr213rY:
21960 case X86::VFNMSUBPDr213rY:
21961 case X86::VFNMSUBPSr213rY:
21962 case X86::VFMADDSUBPDr213rY:
21963 case X86::VFMADDSUBPSr213rY:
21964 case X86::VFMSUBADDPDr213rY:
21965 case X86::VFMSUBADDPSr213rY:
21966 return emitFMA3Instr(MI, BB);
21970 //===----------------------------------------------------------------------===//
21971 // X86 Optimization Hooks
21972 //===----------------------------------------------------------------------===//
21974 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
21977 const SelectionDAG &DAG,
21978 unsigned Depth) const {
21979 unsigned BitWidth = KnownZero.getBitWidth();
21980 unsigned Opc = Op.getOpcode();
21981 assert((Opc >= ISD::BUILTIN_OP_END ||
21982 Opc == ISD::INTRINSIC_WO_CHAIN ||
21983 Opc == ISD::INTRINSIC_W_CHAIN ||
21984 Opc == ISD::INTRINSIC_VOID) &&
21985 "Should use MaskedValueIsZero if you don't know whether Op"
21986 " is a target node!");
21988 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
22002 // These nodes' second result is a boolean.
22003 if (Op.getResNo() == 0)
22006 case X86ISD::SETCC:
22007 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
22009 case ISD::INTRINSIC_WO_CHAIN: {
22010 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
22011 unsigned NumLoBits = 0;
22014 case Intrinsic::x86_sse_movmsk_ps:
22015 case Intrinsic::x86_avx_movmsk_ps_256:
22016 case Intrinsic::x86_sse2_movmsk_pd:
22017 case Intrinsic::x86_avx_movmsk_pd_256:
22018 case Intrinsic::x86_mmx_pmovmskb:
22019 case Intrinsic::x86_sse2_pmovmskb_128:
22020 case Intrinsic::x86_avx2_pmovmskb: {
22021 // High bits of movmskp{s|d}, pmovmskb are known zero.
22023 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
22024 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
22025 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
22026 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
22027 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
22028 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
22029 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
22030 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
22032 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
22041 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
22043 const SelectionDAG &,
22044 unsigned Depth) const {
22045 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
22046 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
22047 return Op.getValueType().getScalarType().getSizeInBits();
22053 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
22054 /// node is a GlobalAddress + offset.
22055 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
22056 const GlobalValue* &GA,
22057 int64_t &Offset) const {
22058 if (N->getOpcode() == X86ISD::Wrapper) {
22059 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
22060 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
22061 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
22065 return TargetLowering::isGAPlusOffset(N, GA, Offset);
22068 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
22069 /// same as extracting the high 128-bit part of 256-bit vector and then
22070 /// inserting the result into the low part of a new 256-bit vector
22071 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
22072 EVT VT = SVOp->getValueType(0);
22073 unsigned NumElems = VT.getVectorNumElements();
22075 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22076 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
22077 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22078 SVOp->getMaskElt(j) >= 0)
22084 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
22085 /// same as extracting the low 128-bit part of 256-bit vector and then
22086 /// inserting the result into the high part of a new 256-bit vector
22087 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
22088 EVT VT = SVOp->getValueType(0);
22089 unsigned NumElems = VT.getVectorNumElements();
22091 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22092 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
22093 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
22094 SVOp->getMaskElt(j) >= 0)
22100 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
22101 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
22102 TargetLowering::DAGCombinerInfo &DCI,
22103 const X86Subtarget* Subtarget) {
22105 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22106 SDValue V1 = SVOp->getOperand(0);
22107 SDValue V2 = SVOp->getOperand(1);
22108 EVT VT = SVOp->getValueType(0);
22109 unsigned NumElems = VT.getVectorNumElements();
22111 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
22112 V2.getOpcode() == ISD::CONCAT_VECTORS) {
22116 // V UNDEF BUILD_VECTOR UNDEF
22118 // CONCAT_VECTOR CONCAT_VECTOR
22121 // RESULT: V + zero extended
22123 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
22124 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
22125 V1.getOperand(1).getOpcode() != ISD::UNDEF)
22128 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
22131 // To match the shuffle mask, the first half of the mask should
22132 // be exactly the first vector, and all the rest a splat with the
22133 // first element of the second one.
22134 for (unsigned i = 0; i != NumElems/2; ++i)
22135 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
22136 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
22139 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
22140 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
22141 if (Ld->hasNUsesOfValue(1, 0)) {
22142 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
22143 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
22145 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
22147 Ld->getPointerInfo(),
22148 Ld->getAlignment(),
22149 false/*isVolatile*/, true/*ReadMem*/,
22150 false/*WriteMem*/);
22152 // Make sure the newly-created LOAD is in the same position as Ld in
22153 // terms of dependency. We create a TokenFactor for Ld and ResNode,
22154 // and update uses of Ld's output chain to use the TokenFactor.
22155 if (Ld->hasAnyUseOfValue(1)) {
22156 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
22157 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
22158 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
22159 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
22160 SDValue(ResNode.getNode(), 1));
22163 return DAG.getBitcast(VT, ResNode);
22167 // Emit a zeroed vector and insert the desired subvector on its
22169 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
22170 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
22171 return DCI.CombineTo(N, InsV);
22174 //===--------------------------------------------------------------------===//
22175 // Combine some shuffles into subvector extracts and inserts:
22178 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
22179 if (isShuffleHigh128VectorInsertLow(SVOp)) {
22180 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
22181 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
22182 return DCI.CombineTo(N, InsV);
22185 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
22186 if (isShuffleLow128VectorInsertHigh(SVOp)) {
22187 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
22188 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
22189 return DCI.CombineTo(N, InsV);
22195 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
22198 /// This is the leaf of the recursive combinine below. When we have found some
22199 /// chain of single-use x86 shuffle instructions and accumulated the combined
22200 /// shuffle mask represented by them, this will try to pattern match that mask
22201 /// into either a single instruction if there is a special purpose instruction
22202 /// for this operation, or into a PSHUFB instruction which is a fully general
22203 /// instruction but should only be used to replace chains over a certain depth.
22204 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
22205 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
22206 TargetLowering::DAGCombinerInfo &DCI,
22207 const X86Subtarget *Subtarget) {
22208 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
22210 // Find the operand that enters the chain. Note that multiple uses are OK
22211 // here, we're not going to remove the operand we find.
22212 SDValue Input = Op.getOperand(0);
22213 while (Input.getOpcode() == ISD::BITCAST)
22214 Input = Input.getOperand(0);
22216 MVT VT = Input.getSimpleValueType();
22217 MVT RootVT = Root.getSimpleValueType();
22220 if (Mask.size() == 1) {
22221 int Index = Mask[0];
22222 assert((Index >= 0 || Index == SM_SentinelUndef ||
22223 Index == SM_SentinelZero) &&
22224 "Invalid shuffle index found!");
22226 // We may end up with an accumulated mask of size 1 as a result of
22227 // widening of shuffle operands (see function canWidenShuffleElements).
22228 // If the only shuffle index is equal to SM_SentinelZero then propagate
22229 // a zero vector. Otherwise, the combine shuffle mask is a no-op shuffle
22230 // mask, and therefore the entire chain of shuffles can be folded away.
22231 if (Index == SM_SentinelZero)
22232 DCI.CombineTo(Root.getNode(), getZeroVector(RootVT, Subtarget, DAG, DL));
22234 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
22239 // Use the float domain if the operand type is a floating point type.
22240 bool FloatDomain = VT.isFloatingPoint();
22242 // For floating point shuffles, we don't have free copies in the shuffle
22243 // instructions or the ability to load as part of the instruction, so
22244 // canonicalize their shuffles to UNPCK or MOV variants.
22246 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
22247 // vectors because it can have a load folded into it that UNPCK cannot. This
22248 // doesn't preclude something switching to the shorter encoding post-RA.
22250 // FIXME: Should teach these routines about AVX vector widths.
22251 if (FloatDomain && VT.getSizeInBits() == 128) {
22252 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
22253 bool Lo = Mask.equals({0, 0});
22256 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
22257 // is no slower than UNPCKLPD but has the option to fold the input operand
22258 // into even an unaligned memory load.
22259 if (Lo && Subtarget->hasSSE3()) {
22260 Shuffle = X86ISD::MOVDDUP;
22261 ShuffleVT = MVT::v2f64;
22263 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
22264 // than the UNPCK variants.
22265 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
22266 ShuffleVT = MVT::v4f32;
22268 if (Depth == 1 && Root->getOpcode() == Shuffle)
22269 return false; // Nothing to do!
22270 Op = DAG.getBitcast(ShuffleVT, Input);
22271 DCI.AddToWorklist(Op.getNode());
22272 if (Shuffle == X86ISD::MOVDDUP)
22273 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22275 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22276 DCI.AddToWorklist(Op.getNode());
22277 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22281 if (Subtarget->hasSSE3() &&
22282 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
22283 bool Lo = Mask.equals({0, 0, 2, 2});
22284 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
22285 MVT ShuffleVT = MVT::v4f32;
22286 if (Depth == 1 && Root->getOpcode() == Shuffle)
22287 return false; // Nothing to do!
22288 Op = DAG.getBitcast(ShuffleVT, Input);
22289 DCI.AddToWorklist(Op.getNode());
22290 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
22291 DCI.AddToWorklist(Op.getNode());
22292 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22296 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
22297 bool Lo = Mask.equals({0, 0, 1, 1});
22298 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22299 MVT ShuffleVT = MVT::v4f32;
22300 if (Depth == 1 && Root->getOpcode() == Shuffle)
22301 return false; // Nothing to do!
22302 Op = DAG.getBitcast(ShuffleVT, Input);
22303 DCI.AddToWorklist(Op.getNode());
22304 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22305 DCI.AddToWorklist(Op.getNode());
22306 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22312 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
22313 // variants as none of these have single-instruction variants that are
22314 // superior to the UNPCK formulation.
22315 if (!FloatDomain && VT.getSizeInBits() == 128 &&
22316 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22317 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
22318 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
22320 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
22321 bool Lo = Mask[0] == 0;
22322 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
22323 if (Depth == 1 && Root->getOpcode() == Shuffle)
22324 return false; // Nothing to do!
22326 switch (Mask.size()) {
22328 ShuffleVT = MVT::v8i16;
22331 ShuffleVT = MVT::v16i8;
22334 llvm_unreachable("Impossible mask size!");
22336 Op = DAG.getBitcast(ShuffleVT, Input);
22337 DCI.AddToWorklist(Op.getNode());
22338 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
22339 DCI.AddToWorklist(Op.getNode());
22340 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22345 // Don't try to re-form single instruction chains under any circumstances now
22346 // that we've done encoding canonicalization for them.
22350 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
22351 // can replace them with a single PSHUFB instruction profitably. Intel's
22352 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
22353 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
22354 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
22355 SmallVector<SDValue, 16> PSHUFBMask;
22356 int NumBytes = VT.getSizeInBits() / 8;
22357 int Ratio = NumBytes / Mask.size();
22358 for (int i = 0; i < NumBytes; ++i) {
22359 if (Mask[i / Ratio] == SM_SentinelUndef) {
22360 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
22363 int M = Mask[i / Ratio] != SM_SentinelZero
22364 ? Ratio * Mask[i / Ratio] + i % Ratio
22366 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
22368 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
22369 Op = DAG.getBitcast(ByteVT, Input);
22370 DCI.AddToWorklist(Op.getNode());
22371 SDValue PSHUFBMaskOp =
22372 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
22373 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
22374 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
22375 DCI.AddToWorklist(Op.getNode());
22376 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
22381 // Failed to find any combines.
22385 /// \brief Fully generic combining of x86 shuffle instructions.
22387 /// This should be the last combine run over the x86 shuffle instructions. Once
22388 /// they have been fully optimized, this will recursively consider all chains
22389 /// of single-use shuffle instructions, build a generic model of the cumulative
22390 /// shuffle operation, and check for simpler instructions which implement this
22391 /// operation. We use this primarily for two purposes:
22393 /// 1) Collapse generic shuffles to specialized single instructions when
22394 /// equivalent. In most cases, this is just an encoding size win, but
22395 /// sometimes we will collapse multiple generic shuffles into a single
22396 /// special-purpose shuffle.
22397 /// 2) Look for sequences of shuffle instructions with 3 or more total
22398 /// instructions, and replace them with the slightly more expensive SSSE3
22399 /// PSHUFB instruction if available. We do this as the last combining step
22400 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
22401 /// a suitable short sequence of other instructions. The PHUFB will either
22402 /// use a register or have to read from memory and so is slightly (but only
22403 /// slightly) more expensive than the other shuffle instructions.
22405 /// Because this is inherently a quadratic operation (for each shuffle in
22406 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
22407 /// This should never be an issue in practice as the shuffle lowering doesn't
22408 /// produce sequences of more than 8 instructions.
22410 /// FIXME: We will currently miss some cases where the redundant shuffling
22411 /// would simplify under the threshold for PSHUFB formation because of
22412 /// combine-ordering. To fix this, we should do the redundant instruction
22413 /// combining in this recursive walk.
22414 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
22415 ArrayRef<int> RootMask,
22416 int Depth, bool HasPSHUFB,
22418 TargetLowering::DAGCombinerInfo &DCI,
22419 const X86Subtarget *Subtarget) {
22420 // Bound the depth of our recursive combine because this is ultimately
22421 // quadratic in nature.
22425 // Directly rip through bitcasts to find the underlying operand.
22426 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
22427 Op = Op.getOperand(0);
22429 MVT VT = Op.getSimpleValueType();
22430 if (!VT.isVector())
22431 return false; // Bail if we hit a non-vector.
22433 assert(Root.getSimpleValueType().isVector() &&
22434 "Shuffles operate on vector types!");
22435 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
22436 "Can only combine shuffles of the same vector register size.");
22438 if (!isTargetShuffle(Op.getOpcode()))
22440 SmallVector<int, 16> OpMask;
22442 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
22443 // We only can combine unary shuffles which we can decode the mask for.
22444 if (!HaveMask || !IsUnary)
22447 assert(VT.getVectorNumElements() == OpMask.size() &&
22448 "Different mask size from vector size!");
22449 assert(((RootMask.size() > OpMask.size() &&
22450 RootMask.size() % OpMask.size() == 0) ||
22451 (OpMask.size() > RootMask.size() &&
22452 OpMask.size() % RootMask.size() == 0) ||
22453 OpMask.size() == RootMask.size()) &&
22454 "The smaller number of elements must divide the larger.");
22455 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
22456 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
22457 assert(((RootRatio == 1 && OpRatio == 1) ||
22458 (RootRatio == 1) != (OpRatio == 1)) &&
22459 "Must not have a ratio for both incoming and op masks!");
22461 SmallVector<int, 16> Mask;
22462 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
22464 // Merge this shuffle operation's mask into our accumulated mask. Note that
22465 // this shuffle's mask will be the first applied to the input, followed by the
22466 // root mask to get us all the way to the root value arrangement. The reason
22467 // for this order is that we are recursing up the operation chain.
22468 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
22469 int RootIdx = i / RootRatio;
22470 if (RootMask[RootIdx] < 0) {
22471 // This is a zero or undef lane, we're done.
22472 Mask.push_back(RootMask[RootIdx]);
22476 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
22477 int OpIdx = RootMaskedIdx / OpRatio;
22478 if (OpMask[OpIdx] < 0) {
22479 // The incoming lanes are zero or undef, it doesn't matter which ones we
22481 Mask.push_back(OpMask[OpIdx]);
22485 // Ok, we have non-zero lanes, map them through.
22486 Mask.push_back(OpMask[OpIdx] * OpRatio +
22487 RootMaskedIdx % OpRatio);
22490 // See if we can recurse into the operand to combine more things.
22491 switch (Op.getOpcode()) {
22492 case X86ISD::PSHUFB:
22494 case X86ISD::PSHUFD:
22495 case X86ISD::PSHUFHW:
22496 case X86ISD::PSHUFLW:
22497 if (Op.getOperand(0).hasOneUse() &&
22498 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22499 HasPSHUFB, DAG, DCI, Subtarget))
22503 case X86ISD::UNPCKL:
22504 case X86ISD::UNPCKH:
22505 assert(Op.getOperand(0) == Op.getOperand(1) &&
22506 "We only combine unary shuffles!");
22507 // We can't check for single use, we have to check that this shuffle is the
22509 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
22510 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
22511 HasPSHUFB, DAG, DCI, Subtarget))
22516 // Minor canonicalization of the accumulated shuffle mask to make it easier
22517 // to match below. All this does is detect masks with squential pairs of
22518 // elements, and shrink them to the half-width mask. It does this in a loop
22519 // so it will reduce the size of the mask to the minimal width mask which
22520 // performs an equivalent shuffle.
22521 SmallVector<int, 16> WidenedMask;
22522 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
22523 Mask = std::move(WidenedMask);
22524 WidenedMask.clear();
22527 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
22531 /// \brief Get the PSHUF-style mask from PSHUF node.
22533 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
22534 /// PSHUF-style masks that can be reused with such instructions.
22535 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
22536 MVT VT = N.getSimpleValueType();
22537 SmallVector<int, 4> Mask;
22539 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
22543 // If we have more than 128-bits, only the low 128-bits of shuffle mask
22544 // matter. Check that the upper masks are repeats and remove them.
22545 if (VT.getSizeInBits() > 128) {
22546 int LaneElts = 128 / VT.getScalarSizeInBits();
22548 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
22549 for (int j = 0; j < LaneElts; ++j)
22550 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
22551 "Mask doesn't repeat in high 128-bit lanes!");
22553 Mask.resize(LaneElts);
22556 switch (N.getOpcode()) {
22557 case X86ISD::PSHUFD:
22559 case X86ISD::PSHUFLW:
22562 case X86ISD::PSHUFHW:
22563 Mask.erase(Mask.begin(), Mask.begin() + 4);
22564 for (int &M : Mask)
22568 llvm_unreachable("No valid shuffle instruction found!");
22572 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
22574 /// We walk up the chain and look for a combinable shuffle, skipping over
22575 /// shuffles that we could hoist this shuffle's transformation past without
22576 /// altering anything.
22578 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
22580 TargetLowering::DAGCombinerInfo &DCI) {
22581 assert(N.getOpcode() == X86ISD::PSHUFD &&
22582 "Called with something other than an x86 128-bit half shuffle!");
22585 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
22586 // of the shuffles in the chain so that we can form a fresh chain to replace
22588 SmallVector<SDValue, 8> Chain;
22589 SDValue V = N.getOperand(0);
22590 for (; V.hasOneUse(); V = V.getOperand(0)) {
22591 switch (V.getOpcode()) {
22593 return SDValue(); // Nothing combined!
22596 // Skip bitcasts as we always know the type for the target specific
22600 case X86ISD::PSHUFD:
22601 // Found another dword shuffle.
22604 case X86ISD::PSHUFLW:
22605 // Check that the low words (being shuffled) are the identity in the
22606 // dword shuffle, and the high words are self-contained.
22607 if (Mask[0] != 0 || Mask[1] != 1 ||
22608 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
22611 Chain.push_back(V);
22614 case X86ISD::PSHUFHW:
22615 // Check that the high words (being shuffled) are the identity in the
22616 // dword shuffle, and the low words are self-contained.
22617 if (Mask[2] != 2 || Mask[3] != 3 ||
22618 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
22621 Chain.push_back(V);
22624 case X86ISD::UNPCKL:
22625 case X86ISD::UNPCKH:
22626 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
22627 // shuffle into a preceding word shuffle.
22628 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
22629 V.getSimpleValueType().getScalarType() != MVT::i16)
22632 // Search for a half-shuffle which we can combine with.
22633 unsigned CombineOp =
22634 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
22635 if (V.getOperand(0) != V.getOperand(1) ||
22636 !V->isOnlyUserOf(V.getOperand(0).getNode()))
22638 Chain.push_back(V);
22639 V = V.getOperand(0);
22641 switch (V.getOpcode()) {
22643 return SDValue(); // Nothing to combine.
22645 case X86ISD::PSHUFLW:
22646 case X86ISD::PSHUFHW:
22647 if (V.getOpcode() == CombineOp)
22650 Chain.push_back(V);
22654 V = V.getOperand(0);
22658 } while (V.hasOneUse());
22661 // Break out of the loop if we break out of the switch.
22665 if (!V.hasOneUse())
22666 // We fell out of the loop without finding a viable combining instruction.
22669 // Merge this node's mask and our incoming mask.
22670 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22671 for (int &M : Mask)
22673 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
22674 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22676 // Rebuild the chain around this new shuffle.
22677 while (!Chain.empty()) {
22678 SDValue W = Chain.pop_back_val();
22680 if (V.getValueType() != W.getOperand(0).getValueType())
22681 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
22683 switch (W.getOpcode()) {
22685 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
22687 case X86ISD::UNPCKL:
22688 case X86ISD::UNPCKH:
22689 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
22692 case X86ISD::PSHUFD:
22693 case X86ISD::PSHUFLW:
22694 case X86ISD::PSHUFHW:
22695 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
22699 if (V.getValueType() != N.getValueType())
22700 V = DAG.getBitcast(N.getValueType(), V);
22702 // Return the new chain to replace N.
22706 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or
22709 /// We walk up the chain, skipping shuffles of the other half and looking
22710 /// through shuffles which switch halves trying to find a shuffle of the same
22711 /// pair of dwords.
22712 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
22714 TargetLowering::DAGCombinerInfo &DCI) {
22716 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
22717 "Called with something other than an x86 128-bit half shuffle!");
22719 unsigned CombineOpcode = N.getOpcode();
22721 // Walk up a single-use chain looking for a combinable shuffle.
22722 SDValue V = N.getOperand(0);
22723 for (; V.hasOneUse(); V = V.getOperand(0)) {
22724 switch (V.getOpcode()) {
22726 return false; // Nothing combined!
22729 // Skip bitcasts as we always know the type for the target specific
22733 case X86ISD::PSHUFLW:
22734 case X86ISD::PSHUFHW:
22735 if (V.getOpcode() == CombineOpcode)
22738 // Other-half shuffles are no-ops.
22741 // Break out of the loop if we break out of the switch.
22745 if (!V.hasOneUse())
22746 // We fell out of the loop without finding a viable combining instruction.
22749 // Combine away the bottom node as its shuffle will be accumulated into
22750 // a preceding shuffle.
22751 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22753 // Record the old value.
22756 // Merge this node's mask and our incoming mask (adjusted to account for all
22757 // the pshufd instructions encountered).
22758 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22759 for (int &M : Mask)
22761 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
22762 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
22764 // Check that the shuffles didn't cancel each other out. If not, we need to
22765 // combine to the new one.
22767 // Replace the combinable shuffle with the combined one, updating all users
22768 // so that we re-evaluate the chain here.
22769 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
22774 /// \brief Try to combine x86 target specific shuffles.
22775 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
22776 TargetLowering::DAGCombinerInfo &DCI,
22777 const X86Subtarget *Subtarget) {
22779 MVT VT = N.getSimpleValueType();
22780 SmallVector<int, 4> Mask;
22782 switch (N.getOpcode()) {
22783 case X86ISD::PSHUFD:
22784 case X86ISD::PSHUFLW:
22785 case X86ISD::PSHUFHW:
22786 Mask = getPSHUFShuffleMask(N);
22787 assert(Mask.size() == 4);
22793 // Nuke no-op shuffles that show up after combining.
22794 if (isNoopShuffleMask(Mask))
22795 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
22797 // Look for simplifications involving one or two shuffle instructions.
22798 SDValue V = N.getOperand(0);
22799 switch (N.getOpcode()) {
22802 case X86ISD::PSHUFLW:
22803 case X86ISD::PSHUFHW:
22804 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
22806 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
22807 return SDValue(); // We combined away this shuffle, so we're done.
22809 // See if this reduces to a PSHUFD which is no more expensive and can
22810 // combine with more operations. Note that it has to at least flip the
22811 // dwords as otherwise it would have been removed as a no-op.
22812 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
22813 int DMask[] = {0, 1, 2, 3};
22814 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
22815 DMask[DOffset + 0] = DOffset + 1;
22816 DMask[DOffset + 1] = DOffset + 0;
22817 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
22818 V = DAG.getBitcast(DVT, V);
22819 DCI.AddToWorklist(V.getNode());
22820 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
22821 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
22822 DCI.AddToWorklist(V.getNode());
22823 return DAG.getBitcast(VT, V);
22826 // Look for shuffle patterns which can be implemented as a single unpack.
22827 // FIXME: This doesn't handle the location of the PSHUFD generically, and
22828 // only works when we have a PSHUFD followed by two half-shuffles.
22829 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
22830 (V.getOpcode() == X86ISD::PSHUFLW ||
22831 V.getOpcode() == X86ISD::PSHUFHW) &&
22832 V.getOpcode() != N.getOpcode() &&
22834 SDValue D = V.getOperand(0);
22835 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
22836 D = D.getOperand(0);
22837 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
22838 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
22839 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
22840 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22841 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
22843 for (int i = 0; i < 4; ++i) {
22844 WordMask[i + NOffset] = Mask[i] + NOffset;
22845 WordMask[i + VOffset] = VMask[i] + VOffset;
22847 // Map the word mask through the DWord mask.
22849 for (int i = 0; i < 8; ++i)
22850 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
22851 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
22852 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
22853 // We can replace all three shuffles with an unpack.
22854 V = DAG.getBitcast(VT, D.getOperand(0));
22855 DCI.AddToWorklist(V.getNode());
22856 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
22865 case X86ISD::PSHUFD:
22866 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
22875 /// \brief Try to combine a shuffle into a target-specific add-sub node.
22877 /// We combine this directly on the abstract vector shuffle nodes so it is
22878 /// easier to generically match. We also insert dummy vector shuffle nodes for
22879 /// the operands which explicitly discard the lanes which are unused by this
22880 /// operation to try to flow through the rest of the combiner the fact that
22881 /// they're unused.
22882 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
22884 EVT VT = N->getValueType(0);
22886 // We only handle target-independent shuffles.
22887 // FIXME: It would be easy and harmless to use the target shuffle mask
22888 // extraction tool to support more.
22889 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
22892 auto *SVN = cast<ShuffleVectorSDNode>(N);
22893 ArrayRef<int> Mask = SVN->getMask();
22894 SDValue V1 = N->getOperand(0);
22895 SDValue V2 = N->getOperand(1);
22897 // We require the first shuffle operand to be the SUB node, and the second to
22898 // be the ADD node.
22899 // FIXME: We should support the commuted patterns.
22900 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
22903 // If there are other uses of these operations we can't fold them.
22904 if (!V1->hasOneUse() || !V2->hasOneUse())
22907 // Ensure that both operations have the same operands. Note that we can
22908 // commute the FADD operands.
22909 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
22910 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
22911 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
22914 // We're looking for blends between FADD and FSUB nodes. We insist on these
22915 // nodes being lined up in a specific expected pattern.
22916 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
22917 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
22918 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
22921 // Only specific types are legal at this point, assert so we notice if and
22922 // when these change.
22923 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
22924 VT == MVT::v4f64) &&
22925 "Unknown vector type encountered!");
22927 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
22930 /// PerformShuffleCombine - Performs several different shuffle combines.
22931 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
22932 TargetLowering::DAGCombinerInfo &DCI,
22933 const X86Subtarget *Subtarget) {
22935 SDValue N0 = N->getOperand(0);
22936 SDValue N1 = N->getOperand(1);
22937 EVT VT = N->getValueType(0);
22939 // Don't create instructions with illegal types after legalize types has run.
22940 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22941 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
22944 // If we have legalized the vector types, look for blends of FADD and FSUB
22945 // nodes that we can fuse into an ADDSUB node.
22946 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
22947 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
22950 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
22951 if (Subtarget->hasFp256() && VT.is256BitVector() &&
22952 N->getOpcode() == ISD::VECTOR_SHUFFLE)
22953 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
22955 // During Type Legalization, when promoting illegal vector types,
22956 // the backend might introduce new shuffle dag nodes and bitcasts.
22958 // This code performs the following transformation:
22959 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
22960 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
22962 // We do this only if both the bitcast and the BINOP dag nodes have
22963 // one use. Also, perform this transformation only if the new binary
22964 // operation is legal. This is to avoid introducing dag nodes that
22965 // potentially need to be further expanded (or custom lowered) into a
22966 // less optimal sequence of dag nodes.
22967 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
22968 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
22969 N0.getOpcode() == ISD::BITCAST) {
22970 SDValue BC0 = N0.getOperand(0);
22971 EVT SVT = BC0.getValueType();
22972 unsigned Opcode = BC0.getOpcode();
22973 unsigned NumElts = VT.getVectorNumElements();
22975 if (BC0.hasOneUse() && SVT.isVector() &&
22976 SVT.getVectorNumElements() * 2 == NumElts &&
22977 TLI.isOperationLegal(Opcode, VT)) {
22978 bool CanFold = false;
22990 unsigned SVTNumElts = SVT.getVectorNumElements();
22991 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
22992 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
22993 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
22994 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
22995 CanFold = SVOp->getMaskElt(i) < 0;
22998 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
22999 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
23000 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
23001 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
23006 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
23007 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
23008 // consecutive, non-overlapping, and in the right order.
23009 SmallVector<SDValue, 16> Elts;
23010 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
23011 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
23013 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
23016 if (isTargetShuffle(N->getOpcode())) {
23018 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
23019 if (Shuffle.getNode())
23022 // Try recursively combining arbitrary sequences of x86 shuffle
23023 // instructions into higher-order shuffles. We do this after combining
23024 // specific PSHUF instruction sequences into their minimal form so that we
23025 // can evaluate how many specialized shuffle instructions are involved in
23026 // a particular chain.
23027 SmallVector<int, 1> NonceMask; // Just a placeholder.
23028 NonceMask.push_back(0);
23029 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
23030 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
23032 return SDValue(); // This routine will use CombineTo to replace N.
23038 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
23039 /// specific shuffle of a load can be folded into a single element load.
23040 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
23041 /// shuffles have been custom lowered so we need to handle those here.
23042 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
23043 TargetLowering::DAGCombinerInfo &DCI) {
23044 if (DCI.isBeforeLegalizeOps())
23047 SDValue InVec = N->getOperand(0);
23048 SDValue EltNo = N->getOperand(1);
23050 if (!isa<ConstantSDNode>(EltNo))
23053 EVT OriginalVT = InVec.getValueType();
23055 if (InVec.getOpcode() == ISD::BITCAST) {
23056 // Don't duplicate a load with other uses.
23057 if (!InVec.hasOneUse())
23059 EVT BCVT = InVec.getOperand(0).getValueType();
23060 if (!BCVT.isVector() ||
23061 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
23063 InVec = InVec.getOperand(0);
23066 EVT CurrentVT = InVec.getValueType();
23068 if (!isTargetShuffle(InVec.getOpcode()))
23071 // Don't duplicate a load with other uses.
23072 if (!InVec.hasOneUse())
23075 SmallVector<int, 16> ShuffleMask;
23077 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
23078 ShuffleMask, UnaryShuffle))
23081 // Select the input vector, guarding against out of range extract vector.
23082 unsigned NumElems = CurrentVT.getVectorNumElements();
23083 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
23084 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
23085 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
23086 : InVec.getOperand(1);
23088 // If inputs to shuffle are the same for both ops, then allow 2 uses
23089 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
23090 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
23092 if (LdNode.getOpcode() == ISD::BITCAST) {
23093 // Don't duplicate a load with other uses.
23094 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
23097 AllowedUses = 1; // only allow 1 load use if we have a bitcast
23098 LdNode = LdNode.getOperand(0);
23101 if (!ISD::isNormalLoad(LdNode.getNode()))
23104 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
23106 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
23109 EVT EltVT = N->getValueType(0);
23110 // If there's a bitcast before the shuffle, check if the load type and
23111 // alignment is valid.
23112 unsigned Align = LN0->getAlignment();
23113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23114 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
23115 EltVT.getTypeForEVT(*DAG.getContext()));
23117 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
23120 // All checks match so transform back to vector_shuffle so that DAG combiner
23121 // can finish the job
23124 // Create shuffle node taking into account the case that its a unary shuffle
23125 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
23126 : InVec.getOperand(1);
23127 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
23128 InVec.getOperand(0), Shuffle,
23130 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
23131 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
23135 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
23136 /// special and don't usually play with other vector types, it's better to
23137 /// handle them early to be sure we emit efficient code by avoiding
23138 /// store-load conversions.
23139 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
23140 if (N->getValueType(0) != MVT::x86mmx ||
23141 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
23142 N->getOperand(0)->getValueType(0) != MVT::v2i32)
23145 SDValue V = N->getOperand(0);
23146 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
23147 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
23148 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
23149 N->getValueType(0), V.getOperand(0));
23154 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
23155 /// generation and convert it from being a bunch of shuffles and extracts
23156 /// into a somewhat faster sequence. For i686, the best sequence is apparently
23157 /// storing the value and loading scalars back, while for x64 we should
23158 /// use 64-bit extracts and shifts.
23159 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
23160 TargetLowering::DAGCombinerInfo &DCI) {
23161 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
23164 SDValue InputVector = N->getOperand(0);
23165 SDLoc dl(InputVector);
23166 // Detect mmx to i32 conversion through a v2i32 elt extract.
23167 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
23168 N->getValueType(0) == MVT::i32 &&
23169 InputVector.getValueType() == MVT::v2i32) {
23171 // The bitcast source is a direct mmx result.
23172 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
23173 if (MMXSrc.getValueType() == MVT::x86mmx)
23174 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23175 N->getValueType(0),
23176 InputVector.getNode()->getOperand(0));
23178 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
23179 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
23180 MMXSrc.getValueType() == MVT::i64) {
23181 SDValue MMXSrcOp = MMXSrc.getOperand(0);
23182 if (MMXSrcOp.hasOneUse() && MMXSrcOp.getOpcode() == ISD::BITCAST &&
23183 MMXSrcOp.getValueType() == MVT::v1i64 &&
23184 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
23185 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
23186 N->getValueType(0), MMXSrcOp.getOperand(0));
23190 EVT VT = N->getValueType(0);
23192 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
23193 InputVector.getOpcode() == ISD::BITCAST &&
23194 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
23195 uint64_t ExtractedElt =
23196 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
23197 uint64_t InputValue =
23198 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
23199 uint64_t Res = (InputValue >> ExtractedElt) & 1;
23200 return DAG.getConstant(Res, dl, MVT::i1);
23202 // Only operate on vectors of 4 elements, where the alternative shuffling
23203 // gets to be more expensive.
23204 if (InputVector.getValueType() != MVT::v4i32)
23207 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
23208 // single use which is a sign-extend or zero-extend, and all elements are
23210 SmallVector<SDNode *, 4> Uses;
23211 unsigned ExtractedElements = 0;
23212 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
23213 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
23214 if (UI.getUse().getResNo() != InputVector.getResNo())
23217 SDNode *Extract = *UI;
23218 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
23221 if (Extract->getValueType(0) != MVT::i32)
23223 if (!Extract->hasOneUse())
23225 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
23226 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
23228 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
23231 // Record which element was extracted.
23232 ExtractedElements |=
23233 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
23235 Uses.push_back(Extract);
23238 // If not all the elements were used, this may not be worthwhile.
23239 if (ExtractedElements != 15)
23242 // Ok, we've now decided to do the transformation.
23243 // If 64-bit shifts are legal, use the extract-shift sequence,
23244 // otherwise bounce the vector off the cache.
23245 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23248 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
23249 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
23250 auto &DL = DAG.getDataLayout();
23251 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy(DL);
23252 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23253 DAG.getConstant(0, dl, VecIdxTy));
23254 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
23255 DAG.getConstant(1, dl, VecIdxTy));
23257 SDValue ShAmt = DAG.getConstant(
23258 32, dl, DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64, DL));
23259 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
23260 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23261 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
23262 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
23263 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
23264 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
23266 // Store the value to a temporary stack slot.
23267 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
23268 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
23269 MachinePointerInfo(), false, false, 0);
23271 EVT ElementType = InputVector.getValueType().getVectorElementType();
23272 unsigned EltSize = ElementType.getSizeInBits() / 8;
23274 // Replace each use (extract) with a load of the appropriate element.
23275 for (unsigned i = 0; i < 4; ++i) {
23276 uint64_t Offset = EltSize * i;
23277 auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());
23278 SDValue OffsetVal = DAG.getConstant(Offset, dl, PtrVT);
23280 SDValue ScalarAddr =
23281 DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, OffsetVal);
23283 // Load the scalar.
23284 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
23285 ScalarAddr, MachinePointerInfo(),
23286 false, false, false, 0);
23291 // Replace the extracts
23292 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
23293 UE = Uses.end(); UI != UE; ++UI) {
23294 SDNode *Extract = *UI;
23296 SDValue Idx = Extract->getOperand(1);
23297 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
23298 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
23301 // The replacement was made in place; don't return anything.
23306 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
23307 const X86Subtarget *Subtarget) {
23309 SDValue Cond = N->getOperand(0);
23310 SDValue LHS = N->getOperand(1);
23311 SDValue RHS = N->getOperand(2);
23313 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
23314 SDValue CondSrc = Cond->getOperand(0);
23315 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
23316 Cond = CondSrc->getOperand(0);
23319 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
23322 // A vselect where all conditions and data are constants can be optimized into
23323 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
23324 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
23325 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
23328 unsigned MaskValue = 0;
23329 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
23332 MVT VT = N->getSimpleValueType(0);
23333 unsigned NumElems = VT.getVectorNumElements();
23334 SmallVector<int, 8> ShuffleMask(NumElems, -1);
23335 for (unsigned i = 0; i < NumElems; ++i) {
23336 // Be sure we emit undef where we can.
23337 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
23338 ShuffleMask[i] = -1;
23340 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
23343 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23344 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
23346 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
23349 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
23351 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
23352 TargetLowering::DAGCombinerInfo &DCI,
23353 const X86Subtarget *Subtarget) {
23355 SDValue Cond = N->getOperand(0);
23356 // Get the LHS/RHS of the select.
23357 SDValue LHS = N->getOperand(1);
23358 SDValue RHS = N->getOperand(2);
23359 EVT VT = LHS.getValueType();
23360 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23362 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
23363 // instructions match the semantics of the common C idiom x<y?x:y but not
23364 // x<=y?x:y, because of how they handle negative zero (which can be
23365 // ignored in unsafe-math mode).
23366 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
23367 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
23368 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
23369 (Subtarget->hasSSE2() ||
23370 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
23371 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23373 unsigned Opcode = 0;
23374 // Check for x CC y ? x : y.
23375 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23376 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23380 // Converting this to a min would handle NaNs incorrectly, and swapping
23381 // the operands would cause it to handle comparisons between positive
23382 // and negative zero incorrectly.
23383 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23384 if (!DAG.getTarget().Options.UnsafeFPMath &&
23385 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23387 std::swap(LHS, RHS);
23389 Opcode = X86ISD::FMIN;
23392 // Converting this to a min would handle comparisons between positive
23393 // and negative zero incorrectly.
23394 if (!DAG.getTarget().Options.UnsafeFPMath &&
23395 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23397 Opcode = X86ISD::FMIN;
23400 // Converting this to a min would handle both negative zeros and NaNs
23401 // incorrectly, but we can swap the operands to fix both.
23402 std::swap(LHS, RHS);
23406 Opcode = X86ISD::FMIN;
23410 // Converting this to a max would handle comparisons between positive
23411 // and negative zero incorrectly.
23412 if (!DAG.getTarget().Options.UnsafeFPMath &&
23413 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
23415 Opcode = X86ISD::FMAX;
23418 // Converting this to a max would handle NaNs incorrectly, and swapping
23419 // the operands would cause it to handle comparisons between positive
23420 // and negative zero incorrectly.
23421 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
23422 if (!DAG.getTarget().Options.UnsafeFPMath &&
23423 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
23425 std::swap(LHS, RHS);
23427 Opcode = X86ISD::FMAX;
23430 // Converting this to a max would handle both negative zeros and NaNs
23431 // incorrectly, but we can swap the operands to fix both.
23432 std::swap(LHS, RHS);
23436 Opcode = X86ISD::FMAX;
23439 // Check for x CC y ? y : x -- a min/max with reversed arms.
23440 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
23441 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
23445 // Converting this to a min would handle comparisons between positive
23446 // and negative zero incorrectly, and swapping the operands would
23447 // cause it to handle NaNs incorrectly.
23448 if (!DAG.getTarget().Options.UnsafeFPMath &&
23449 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
23450 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23452 std::swap(LHS, RHS);
23454 Opcode = X86ISD::FMIN;
23457 // Converting this to a min would handle NaNs incorrectly.
23458 if (!DAG.getTarget().Options.UnsafeFPMath &&
23459 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
23461 Opcode = X86ISD::FMIN;
23464 // Converting this to a min would handle both negative zeros and NaNs
23465 // incorrectly, but we can swap the operands to fix both.
23466 std::swap(LHS, RHS);
23470 Opcode = X86ISD::FMIN;
23474 // Converting this to a max would handle NaNs incorrectly.
23475 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23477 Opcode = X86ISD::FMAX;
23480 // Converting this to a max would handle comparisons between positive
23481 // and negative zero incorrectly, and swapping the operands would
23482 // cause it to handle NaNs incorrectly.
23483 if (!DAG.getTarget().Options.UnsafeFPMath &&
23484 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
23485 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
23487 std::swap(LHS, RHS);
23489 Opcode = X86ISD::FMAX;
23492 // Converting this to a max would handle both negative zeros and NaNs
23493 // incorrectly, but we can swap the operands to fix both.
23494 std::swap(LHS, RHS);
23498 Opcode = X86ISD::FMAX;
23504 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
23507 EVT CondVT = Cond.getValueType();
23508 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
23509 CondVT.getVectorElementType() == MVT::i1) {
23510 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
23511 // lowering on KNL. In this case we convert it to
23512 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
23513 // The same situation for all 128 and 256-bit vectors of i8 and i16.
23514 // Since SKX these selects have a proper lowering.
23515 EVT OpVT = LHS.getValueType();
23516 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
23517 (OpVT.getVectorElementType() == MVT::i8 ||
23518 OpVT.getVectorElementType() == MVT::i16) &&
23519 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
23520 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
23521 DCI.AddToWorklist(Cond.getNode());
23522 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
23525 // If this is a select between two integer constants, try to do some
23527 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
23528 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
23529 // Don't do this for crazy integer types.
23530 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
23531 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
23532 // so that TrueC (the true value) is larger than FalseC.
23533 bool NeedsCondInvert = false;
23535 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
23536 // Efficiently invertible.
23537 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
23538 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
23539 isa<ConstantSDNode>(Cond.getOperand(1))))) {
23540 NeedsCondInvert = true;
23541 std::swap(TrueC, FalseC);
23544 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
23545 if (FalseC->getAPIntValue() == 0 &&
23546 TrueC->getAPIntValue().isPowerOf2()) {
23547 if (NeedsCondInvert) // Invert the condition if needed.
23548 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23549 DAG.getConstant(1, DL, Cond.getValueType()));
23551 // Zero extend the condition if needed.
23552 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
23554 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
23555 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
23556 DAG.getConstant(ShAmt, DL, MVT::i8));
23559 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
23560 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
23561 if (NeedsCondInvert) // Invert the condition if needed.
23562 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23563 DAG.getConstant(1, DL, Cond.getValueType()));
23565 // Zero extend the condition if needed.
23566 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
23567 FalseC->getValueType(0), Cond);
23568 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23569 SDValue(FalseC, 0));
23572 // Optimize cases that will turn into an LEA instruction. This requires
23573 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
23574 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
23575 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
23576 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
23578 bool isFastMultiplier = false;
23580 switch ((unsigned char)Diff) {
23582 case 1: // result = add base, cond
23583 case 2: // result = lea base( , cond*2)
23584 case 3: // result = lea base(cond, cond*2)
23585 case 4: // result = lea base( , cond*4)
23586 case 5: // result = lea base(cond, cond*4)
23587 case 8: // result = lea base( , cond*8)
23588 case 9: // result = lea base(cond, cond*8)
23589 isFastMultiplier = true;
23594 if (isFastMultiplier) {
23595 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
23596 if (NeedsCondInvert) // Invert the condition if needed.
23597 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
23598 DAG.getConstant(1, DL, Cond.getValueType()));
23600 // Zero extend the condition if needed.
23601 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
23603 // Scale the condition by the difference.
23605 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
23606 DAG.getConstant(Diff, DL,
23607 Cond.getValueType()));
23609 // Add the base if non-zero.
23610 if (FalseC->getAPIntValue() != 0)
23611 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
23612 SDValue(FalseC, 0));
23619 // Canonicalize max and min:
23620 // (x > y) ? x : y -> (x >= y) ? x : y
23621 // (x < y) ? x : y -> (x <= y) ? x : y
23622 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
23623 // the need for an extra compare
23624 // against zero. e.g.
23625 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
23627 // testl %edi, %edi
23629 // cmovgl %edi, %eax
23633 // cmovsl %eax, %edi
23634 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
23635 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
23636 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
23637 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23642 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
23643 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
23644 Cond.getOperand(0), Cond.getOperand(1), NewCC);
23645 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
23650 // Early exit check
23651 if (!TLI.isTypeLegal(VT))
23654 // Match VSELECTs into subs with unsigned saturation.
23655 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
23656 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
23657 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
23658 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
23659 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
23661 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
23662 // left side invert the predicate to simplify logic below.
23664 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
23666 CC = ISD::getSetCCInverse(CC, true);
23667 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
23671 if (Other.getNode() && Other->getNumOperands() == 2 &&
23672 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
23673 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
23674 SDValue CondRHS = Cond->getOperand(1);
23676 // Look for a general sub with unsigned saturation first.
23677 // x >= y ? x-y : 0 --> subus x, y
23678 // x > y ? x-y : 0 --> subus x, y
23679 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
23680 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
23681 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
23683 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
23684 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
23685 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
23686 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
23687 // If the RHS is a constant we have to reverse the const
23688 // canonicalization.
23689 // x > C-1 ? x+-C : 0 --> subus x, C
23690 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
23691 CondRHSConst->getAPIntValue() ==
23692 (-OpRHSConst->getAPIntValue() - 1))
23693 return DAG.getNode(
23694 X86ISD::SUBUS, DL, VT, OpLHS,
23695 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
23697 // Another special case: If C was a sign bit, the sub has been
23698 // canonicalized into a xor.
23699 // FIXME: Would it be better to use computeKnownBits to determine
23700 // whether it's safe to decanonicalize the xor?
23701 // x s< 0 ? x^C : 0 --> subus x, C
23702 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
23703 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
23704 OpRHSConst->getAPIntValue().isSignBit())
23705 // Note that we have to rebuild the RHS constant here to ensure we
23706 // don't rely on particular values of undef lanes.
23707 return DAG.getNode(
23708 X86ISD::SUBUS, DL, VT, OpLHS,
23709 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
23714 // Simplify vector selection if condition value type matches vselect
23716 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
23717 assert(Cond.getValueType().isVector() &&
23718 "vector select expects a vector selector!");
23720 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
23721 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
23723 // Try invert the condition if true value is not all 1s and false value
23725 if (!TValIsAllOnes && !FValIsAllZeros &&
23726 // Check if the selector will be produced by CMPP*/PCMP*
23727 Cond.getOpcode() == ISD::SETCC &&
23728 // Check if SETCC has already been promoted
23729 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
23731 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
23732 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
23734 if (TValIsAllZeros || FValIsAllOnes) {
23735 SDValue CC = Cond.getOperand(2);
23736 ISD::CondCode NewCC =
23737 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
23738 Cond.getOperand(0).getValueType().isInteger());
23739 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
23740 std::swap(LHS, RHS);
23741 TValIsAllOnes = FValIsAllOnes;
23742 FValIsAllZeros = TValIsAllZeros;
23746 if (TValIsAllOnes || FValIsAllZeros) {
23749 if (TValIsAllOnes && FValIsAllZeros)
23751 else if (TValIsAllOnes)
23753 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
23754 else if (FValIsAllZeros)
23755 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
23756 DAG.getBitcast(CondVT, LHS));
23758 return DAG.getBitcast(VT, Ret);
23762 // We should generate an X86ISD::BLENDI from a vselect if its argument
23763 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
23764 // constants. This specific pattern gets generated when we split a
23765 // selector for a 512 bit vector in a machine without AVX512 (but with
23766 // 256-bit vectors), during legalization:
23768 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
23770 // Iff we find this pattern and the build_vectors are built from
23771 // constants, we translate the vselect into a shuffle_vector that we
23772 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
23773 if ((N->getOpcode() == ISD::VSELECT ||
23774 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
23775 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
23776 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
23777 if (Shuffle.getNode())
23781 // If this is a *dynamic* select (non-constant condition) and we can match
23782 // this node with one of the variable blend instructions, restructure the
23783 // condition so that the blends can use the high bit of each element and use
23784 // SimplifyDemandedBits to simplify the condition operand.
23785 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
23786 !DCI.isBeforeLegalize() &&
23787 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
23788 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
23790 // Don't optimize vector selects that map to mask-registers.
23794 // We can only handle the cases where VSELECT is directly legal on the
23795 // subtarget. We custom lower VSELECT nodes with constant conditions and
23796 // this makes it hard to see whether a dynamic VSELECT will correctly
23797 // lower, so we both check the operation's status and explicitly handle the
23798 // cases where a *dynamic* blend will fail even though a constant-condition
23799 // blend could be custom lowered.
23800 // FIXME: We should find a better way to handle this class of problems.
23801 // Potentially, we should combine constant-condition vselect nodes
23802 // pre-legalization into shuffles and not mark as many types as custom
23804 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
23806 // FIXME: We don't support i16-element blends currently. We could and
23807 // should support them by making *all* the bits in the condition be set
23808 // rather than just the high bit and using an i8-element blend.
23809 if (VT.getScalarType() == MVT::i16)
23811 // Dynamic blending was only available from SSE4.1 onward.
23812 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
23814 // Byte blends are only available in AVX2
23815 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
23816 !Subtarget->hasAVX2())
23819 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
23820 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
23822 APInt KnownZero, KnownOne;
23823 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
23824 DCI.isBeforeLegalizeOps());
23825 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
23826 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
23828 // If we changed the computation somewhere in the DAG, this change
23829 // will affect all users of Cond.
23830 // Make sure it is fine and update all the nodes so that we do not
23831 // use the generic VSELECT anymore. Otherwise, we may perform
23832 // wrong optimizations as we messed up with the actual expectation
23833 // for the vector boolean values.
23834 if (Cond != TLO.Old) {
23835 // Check all uses of that condition operand to check whether it will be
23836 // consumed by non-BLEND instructions, which may depend on all bits are
23838 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23840 if (I->getOpcode() != ISD::VSELECT)
23841 // TODO: Add other opcodes eventually lowered into BLEND.
23844 // Update all the users of the condition, before committing the change,
23845 // so that the VSELECT optimizations that expect the correct vector
23846 // boolean value will not be triggered.
23847 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
23849 DAG.ReplaceAllUsesOfValueWith(
23851 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
23852 Cond, I->getOperand(1), I->getOperand(2)));
23853 DCI.CommitTargetLoweringOpt(TLO);
23856 // At this point, only Cond is changed. Change the condition
23857 // just for N to keep the opportunity to optimize all other
23858 // users their own way.
23859 DAG.ReplaceAllUsesOfValueWith(
23861 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
23862 TLO.New, N->getOperand(1), N->getOperand(2)));
23870 // Check whether a boolean test is testing a boolean value generated by
23871 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
23874 // Simplify the following patterns:
23875 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
23876 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
23877 // to (Op EFLAGS Cond)
23879 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
23880 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
23881 // to (Op EFLAGS !Cond)
23883 // where Op could be BRCOND or CMOV.
23885 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
23886 // Quit if not CMP and SUB with its value result used.
23887 if (Cmp.getOpcode() != X86ISD::CMP &&
23888 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
23891 // Quit if not used as a boolean value.
23892 if (CC != X86::COND_E && CC != X86::COND_NE)
23895 // Check CMP operands. One of them should be 0 or 1 and the other should be
23896 // an SetCC or extended from it.
23897 SDValue Op1 = Cmp.getOperand(0);
23898 SDValue Op2 = Cmp.getOperand(1);
23901 const ConstantSDNode* C = nullptr;
23902 bool needOppositeCond = (CC == X86::COND_E);
23903 bool checkAgainstTrue = false; // Is it a comparison against 1?
23905 if ((C = dyn_cast<ConstantSDNode>(Op1)))
23907 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
23909 else // Quit if all operands are not constants.
23912 if (C->getZExtValue() == 1) {
23913 needOppositeCond = !needOppositeCond;
23914 checkAgainstTrue = true;
23915 } else if (C->getZExtValue() != 0)
23916 // Quit if the constant is neither 0 or 1.
23919 bool truncatedToBoolWithAnd = false;
23920 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
23921 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
23922 SetCC.getOpcode() == ISD::TRUNCATE ||
23923 SetCC.getOpcode() == ISD::AND) {
23924 if (SetCC.getOpcode() == ISD::AND) {
23926 ConstantSDNode *CS;
23927 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
23928 CS->getZExtValue() == 1)
23930 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
23931 CS->getZExtValue() == 1)
23935 SetCC = SetCC.getOperand(OpIdx);
23936 truncatedToBoolWithAnd = true;
23938 SetCC = SetCC.getOperand(0);
23941 switch (SetCC.getOpcode()) {
23942 case X86ISD::SETCC_CARRY:
23943 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
23944 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
23945 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
23946 // truncated to i1 using 'and'.
23947 if (checkAgainstTrue && !truncatedToBoolWithAnd)
23949 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
23950 "Invalid use of SETCC_CARRY!");
23952 case X86ISD::SETCC:
23953 // Set the condition code or opposite one if necessary.
23954 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
23955 if (needOppositeCond)
23956 CC = X86::GetOppositeBranchCondition(CC);
23957 return SetCC.getOperand(1);
23958 case X86ISD::CMOV: {
23959 // Check whether false/true value has canonical one, i.e. 0 or 1.
23960 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
23961 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
23962 // Quit if true value is not a constant.
23965 // Quit if false value is not a constant.
23967 SDValue Op = SetCC.getOperand(0);
23968 // Skip 'zext' or 'trunc' node.
23969 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
23970 Op.getOpcode() == ISD::TRUNCATE)
23971 Op = Op.getOperand(0);
23972 // A special case for rdrand/rdseed, where 0 is set if false cond is
23974 if ((Op.getOpcode() != X86ISD::RDRAND &&
23975 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
23978 // Quit if false value is not the constant 0 or 1.
23979 bool FValIsFalse = true;
23980 if (FVal && FVal->getZExtValue() != 0) {
23981 if (FVal->getZExtValue() != 1)
23983 // If FVal is 1, opposite cond is needed.
23984 needOppositeCond = !needOppositeCond;
23985 FValIsFalse = false;
23987 // Quit if TVal is not the constant opposite of FVal.
23988 if (FValIsFalse && TVal->getZExtValue() != 1)
23990 if (!FValIsFalse && TVal->getZExtValue() != 0)
23992 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
23993 if (needOppositeCond)
23994 CC = X86::GetOppositeBranchCondition(CC);
23995 return SetCC.getOperand(3);
24002 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
24004 /// (X86or (X86setcc) (X86setcc))
24005 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
24006 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
24007 X86::CondCode &CC1, SDValue &Flags,
24009 if (Cond->getOpcode() == X86ISD::CMP) {
24010 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
24011 if (!CondOp1C || !CondOp1C->isNullValue())
24014 Cond = Cond->getOperand(0);
24019 SDValue SetCC0, SetCC1;
24020 switch (Cond->getOpcode()) {
24021 default: return false;
24028 SetCC0 = Cond->getOperand(0);
24029 SetCC1 = Cond->getOperand(1);
24033 // Make sure we have SETCC nodes, using the same flags value.
24034 if (SetCC0.getOpcode() != X86ISD::SETCC ||
24035 SetCC1.getOpcode() != X86ISD::SETCC ||
24036 SetCC0->getOperand(1) != SetCC1->getOperand(1))
24039 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
24040 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
24041 Flags = SetCC0->getOperand(1);
24045 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
24046 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
24047 TargetLowering::DAGCombinerInfo &DCI,
24048 const X86Subtarget *Subtarget) {
24051 // If the flag operand isn't dead, don't touch this CMOV.
24052 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
24055 SDValue FalseOp = N->getOperand(0);
24056 SDValue TrueOp = N->getOperand(1);
24057 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
24058 SDValue Cond = N->getOperand(3);
24060 if (CC == X86::COND_E || CC == X86::COND_NE) {
24061 switch (Cond.getOpcode()) {
24065 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
24066 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
24067 return (CC == X86::COND_E) ? FalseOp : TrueOp;
24073 Flags = checkBoolTestSetCCCombine(Cond, CC);
24074 if (Flags.getNode() &&
24075 // Extra check as FCMOV only supports a subset of X86 cond.
24076 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
24077 SDValue Ops[] = { FalseOp, TrueOp,
24078 DAG.getConstant(CC, DL, MVT::i8), Flags };
24079 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24082 // If this is a select between two integer constants, try to do some
24083 // optimizations. Note that the operands are ordered the opposite of SELECT
24085 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
24086 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
24087 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
24088 // larger than FalseC (the false value).
24089 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
24090 CC = X86::GetOppositeBranchCondition(CC);
24091 std::swap(TrueC, FalseC);
24092 std::swap(TrueOp, FalseOp);
24095 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
24096 // This is efficient for any integer data type (including i8/i16) and
24098 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
24099 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24100 DAG.getConstant(CC, DL, MVT::i8), Cond);
24102 // Zero extend the condition if needed.
24103 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
24105 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
24106 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
24107 DAG.getConstant(ShAmt, DL, MVT::i8));
24108 if (N->getNumValues() == 2) // Dead flag value?
24109 return DCI.CombineTo(N, Cond, SDValue());
24113 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
24114 // for any integer data type, including i8/i16.
24115 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
24116 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24117 DAG.getConstant(CC, DL, MVT::i8), Cond);
24119 // Zero extend the condition if needed.
24120 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
24121 FalseC->getValueType(0), Cond);
24122 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24123 SDValue(FalseC, 0));
24125 if (N->getNumValues() == 2) // Dead flag value?
24126 return DCI.CombineTo(N, Cond, SDValue());
24130 // Optimize cases that will turn into an LEA instruction. This requires
24131 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
24132 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
24133 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
24134 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
24136 bool isFastMultiplier = false;
24138 switch ((unsigned char)Diff) {
24140 case 1: // result = add base, cond
24141 case 2: // result = lea base( , cond*2)
24142 case 3: // result = lea base(cond, cond*2)
24143 case 4: // result = lea base( , cond*4)
24144 case 5: // result = lea base(cond, cond*4)
24145 case 8: // result = lea base( , cond*8)
24146 case 9: // result = lea base(cond, cond*8)
24147 isFastMultiplier = true;
24152 if (isFastMultiplier) {
24153 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
24154 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
24155 DAG.getConstant(CC, DL, MVT::i8), Cond);
24156 // Zero extend the condition if needed.
24157 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
24159 // Scale the condition by the difference.
24161 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
24162 DAG.getConstant(Diff, DL, Cond.getValueType()));
24164 // Add the base if non-zero.
24165 if (FalseC->getAPIntValue() != 0)
24166 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
24167 SDValue(FalseC, 0));
24168 if (N->getNumValues() == 2) // Dead flag value?
24169 return DCI.CombineTo(N, Cond, SDValue());
24176 // Handle these cases:
24177 // (select (x != c), e, c) -> select (x != c), e, x),
24178 // (select (x == c), c, e) -> select (x == c), x, e)
24179 // where the c is an integer constant, and the "select" is the combination
24180 // of CMOV and CMP.
24182 // The rationale for this change is that the conditional-move from a constant
24183 // needs two instructions, however, conditional-move from a register needs
24184 // only one instruction.
24186 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
24187 // some instruction-combining opportunities. This opt needs to be
24188 // postponed as late as possible.
24190 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
24191 // the DCI.xxxx conditions are provided to postpone the optimization as
24192 // late as possible.
24194 ConstantSDNode *CmpAgainst = nullptr;
24195 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
24196 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
24197 !isa<ConstantSDNode>(Cond.getOperand(0))) {
24199 if (CC == X86::COND_NE &&
24200 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
24201 CC = X86::GetOppositeBranchCondition(CC);
24202 std::swap(TrueOp, FalseOp);
24205 if (CC == X86::COND_E &&
24206 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
24207 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
24208 DAG.getConstant(CC, DL, MVT::i8), Cond };
24209 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
24214 // Fold and/or of setcc's to double CMOV:
24215 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
24216 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
24218 // This combine lets us generate:
24219 // cmovcc1 (jcc1 if we don't have CMOV)
24225 // cmovne (jne if we don't have CMOV)
24226 // When we can't use the CMOV instruction, it might increase branch
24228 // When we can use CMOV, or when there is no mispredict, this improves
24229 // throughput and reduces register pressure.
24231 if (CC == X86::COND_NE) {
24233 X86::CondCode CC0, CC1;
24235 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
24237 std::swap(FalseOp, TrueOp);
24238 CC0 = X86::GetOppositeBranchCondition(CC0);
24239 CC1 = X86::GetOppositeBranchCondition(CC1);
24242 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
24244 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
24245 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
24246 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
24247 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
24255 /// PerformMulCombine - Optimize a single multiply with constant into two
24256 /// in order to implement it with two cheaper instructions, e.g.
24257 /// LEA + SHL, LEA + LEA.
24258 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
24259 TargetLowering::DAGCombinerInfo &DCI) {
24260 // An imul is usually smaller than the alternative sequence.
24261 if (DAG.getMachineFunction().getFunction()->optForMinSize())
24264 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
24267 EVT VT = N->getValueType(0);
24268 if (VT != MVT::i64 && VT != MVT::i32)
24271 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
24274 uint64_t MulAmt = C->getZExtValue();
24275 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
24278 uint64_t MulAmt1 = 0;
24279 uint64_t MulAmt2 = 0;
24280 if ((MulAmt % 9) == 0) {
24282 MulAmt2 = MulAmt / 9;
24283 } else if ((MulAmt % 5) == 0) {
24285 MulAmt2 = MulAmt / 5;
24286 } else if ((MulAmt % 3) == 0) {
24288 MulAmt2 = MulAmt / 3;
24291 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
24294 if (isPowerOf2_64(MulAmt2) &&
24295 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
24296 // If second multiplifer is pow2, issue it first. We want the multiply by
24297 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
24299 std::swap(MulAmt1, MulAmt2);
24302 if (isPowerOf2_64(MulAmt1))
24303 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
24304 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
24306 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
24307 DAG.getConstant(MulAmt1, DL, VT));
24309 if (isPowerOf2_64(MulAmt2))
24310 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
24311 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
24313 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
24314 DAG.getConstant(MulAmt2, DL, VT));
24316 // Do not add new nodes to DAG combiner worklist.
24317 DCI.CombineTo(N, NewMul, false);
24322 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
24323 SDValue N0 = N->getOperand(0);
24324 SDValue N1 = N->getOperand(1);
24325 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
24326 EVT VT = N0.getValueType();
24328 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
24329 // since the result of setcc_c is all zero's or all ones.
24330 if (VT.isInteger() && !VT.isVector() &&
24331 N1C && N0.getOpcode() == ISD::AND &&
24332 N0.getOperand(1).getOpcode() == ISD::Constant) {
24333 SDValue N00 = N0.getOperand(0);
24334 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
24335 APInt ShAmt = N1C->getAPIntValue();
24336 Mask = Mask.shl(ShAmt);
24337 bool MaskOK = false;
24338 // We can handle cases concerning bit-widening nodes containing setcc_c if
24339 // we carefully interrogate the mask to make sure we are semantics
24341 // The transform is not safe if the result of C1 << C2 exceeds the bitwidth
24342 // of the underlying setcc_c operation if the setcc_c was zero extended.
24343 // Consider the following example:
24344 // zext(setcc_c) -> i32 0x0000FFFF
24345 // c1 -> i32 0x0000FFFF
24346 // c2 -> i32 0x00000001
24347 // (shl (and (setcc_c), c1), c2) -> i32 0x0001FFFE
24348 // (and setcc_c, (c1 << c2)) -> i32 0x0000FFFE
24349 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24351 } else if (N00.getOpcode() == ISD::SIGN_EXTEND &&
24352 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24354 } else if ((N00.getOpcode() == ISD::ZERO_EXTEND ||
24355 N00.getOpcode() == ISD::ANY_EXTEND) &&
24356 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
24357 MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
24359 if (MaskOK && Mask != 0) {
24361 return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
24365 // Hardware support for vector shifts is sparse which makes us scalarize the
24366 // vector operations in many cases. Also, on sandybridge ADD is faster than
24368 // (shl V, 1) -> add V,V
24369 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
24370 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
24371 assert(N0.getValueType().isVector() && "Invalid vector shift type");
24372 // We shift all of the values by one. In many cases we do not have
24373 // hardware support for this operation. This is better expressed as an ADD
24375 if (N1SplatC->getAPIntValue() == 1)
24376 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
24382 /// \brief Returns a vector of 0s if the node in input is a vector logical
24383 /// shift by a constant amount which is known to be bigger than or equal
24384 /// to the vector element size in bits.
24385 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
24386 const X86Subtarget *Subtarget) {
24387 EVT VT = N->getValueType(0);
24389 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
24390 (!Subtarget->hasInt256() ||
24391 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
24394 SDValue Amt = N->getOperand(1);
24396 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
24397 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
24398 APInt ShiftAmt = AmtSplat->getAPIntValue();
24399 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
24401 // SSE2/AVX2 logical shifts always return a vector of 0s
24402 // if the shift amount is bigger than or equal to
24403 // the element size. The constant shift amount will be
24404 // encoded as a 8-bit immediate.
24405 if (ShiftAmt.trunc(8).uge(MaxAmount))
24406 return getZeroVector(VT, Subtarget, DAG, DL);
24412 /// PerformShiftCombine - Combine shifts.
24413 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
24414 TargetLowering::DAGCombinerInfo &DCI,
24415 const X86Subtarget *Subtarget) {
24416 if (N->getOpcode() == ISD::SHL)
24417 if (SDValue V = PerformSHLCombine(N, DAG))
24420 // Try to fold this logical shift into a zero vector.
24421 if (N->getOpcode() != ISD::SRA)
24422 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
24428 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
24429 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
24430 // and friends. Likewise for OR -> CMPNEQSS.
24431 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
24432 TargetLowering::DAGCombinerInfo &DCI,
24433 const X86Subtarget *Subtarget) {
24436 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
24437 // we're requiring SSE2 for both.
24438 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
24439 SDValue N0 = N->getOperand(0);
24440 SDValue N1 = N->getOperand(1);
24441 SDValue CMP0 = N0->getOperand(1);
24442 SDValue CMP1 = N1->getOperand(1);
24445 // The SETCCs should both refer to the same CMP.
24446 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
24449 SDValue CMP00 = CMP0->getOperand(0);
24450 SDValue CMP01 = CMP0->getOperand(1);
24451 EVT VT = CMP00.getValueType();
24453 if (VT == MVT::f32 || VT == MVT::f64) {
24454 bool ExpectingFlags = false;
24455 // Check for any users that want flags:
24456 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
24457 !ExpectingFlags && UI != UE; ++UI)
24458 switch (UI->getOpcode()) {
24463 ExpectingFlags = true;
24465 case ISD::CopyToReg:
24466 case ISD::SIGN_EXTEND:
24467 case ISD::ZERO_EXTEND:
24468 case ISD::ANY_EXTEND:
24472 if (!ExpectingFlags) {
24473 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
24474 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
24476 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
24477 X86::CondCode tmp = cc0;
24482 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
24483 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
24484 // FIXME: need symbolic constants for these magic numbers.
24485 // See X86ATTInstPrinter.cpp:printSSECC().
24486 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
24487 if (Subtarget->hasAVX512()) {
24488 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
24490 DAG.getConstant(x86cc, DL, MVT::i8));
24491 if (N->getValueType(0) != MVT::i1)
24492 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
24496 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
24497 CMP00.getValueType(), CMP00, CMP01,
24498 DAG.getConstant(x86cc, DL,
24501 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
24502 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
24504 if (is64BitFP && !Subtarget->is64Bit()) {
24505 // On a 32-bit target, we cannot bitcast the 64-bit float to a
24506 // 64-bit integer, since that's not a legal type. Since
24507 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
24508 // bits, but can do this little dance to extract the lowest 32 bits
24509 // and work with those going forward.
24510 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
24512 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
24513 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
24514 Vector32, DAG.getIntPtrConstant(0, DL));
24518 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
24519 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
24520 DAG.getConstant(1, DL, IntVT));
24521 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
24523 return OneBitOfTruth;
24531 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
24532 /// so it can be folded inside ANDNP.
24533 static bool CanFoldXORWithAllOnes(const SDNode *N) {
24534 EVT VT = N->getValueType(0);
24536 // Match direct AllOnes for 128 and 256-bit vectors
24537 if (ISD::isBuildVectorAllOnes(N))
24540 // Look through a bit convert.
24541 if (N->getOpcode() == ISD::BITCAST)
24542 N = N->getOperand(0).getNode();
24544 // Sometimes the operand may come from a insert_subvector building a 256-bit
24546 if (VT.is256BitVector() &&
24547 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
24548 SDValue V1 = N->getOperand(0);
24549 SDValue V2 = N->getOperand(1);
24551 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
24552 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
24553 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
24554 ISD::isBuildVectorAllOnes(V2.getNode()))
24561 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
24562 // register. In most cases we actually compare or select YMM-sized registers
24563 // and mixing the two types creates horrible code. This method optimizes
24564 // some of the transition sequences.
24565 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
24566 TargetLowering::DAGCombinerInfo &DCI,
24567 const X86Subtarget *Subtarget) {
24568 EVT VT = N->getValueType(0);
24569 if (!VT.is256BitVector())
24572 assert((N->getOpcode() == ISD::ANY_EXTEND ||
24573 N->getOpcode() == ISD::ZERO_EXTEND ||
24574 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
24576 SDValue Narrow = N->getOperand(0);
24577 EVT NarrowVT = Narrow->getValueType(0);
24578 if (!NarrowVT.is128BitVector())
24581 if (Narrow->getOpcode() != ISD::XOR &&
24582 Narrow->getOpcode() != ISD::AND &&
24583 Narrow->getOpcode() != ISD::OR)
24586 SDValue N0 = Narrow->getOperand(0);
24587 SDValue N1 = Narrow->getOperand(1);
24590 // The Left side has to be a trunc.
24591 if (N0.getOpcode() != ISD::TRUNCATE)
24594 // The type of the truncated inputs.
24595 EVT WideVT = N0->getOperand(0)->getValueType(0);
24599 // The right side has to be a 'trunc' or a constant vector.
24600 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
24601 ConstantSDNode *RHSConstSplat = nullptr;
24602 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
24603 RHSConstSplat = RHSBV->getConstantSplatNode();
24604 if (!RHSTrunc && !RHSConstSplat)
24607 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24609 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
24612 // Set N0 and N1 to hold the inputs to the new wide operation.
24613 N0 = N0->getOperand(0);
24614 if (RHSConstSplat) {
24615 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
24616 SDValue(RHSConstSplat, 0));
24617 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
24618 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
24619 } else if (RHSTrunc) {
24620 N1 = N1->getOperand(0);
24623 // Generate the wide operation.
24624 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
24625 unsigned Opcode = N->getOpcode();
24627 case ISD::ANY_EXTEND:
24629 case ISD::ZERO_EXTEND: {
24630 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
24631 APInt Mask = APInt::getAllOnesValue(InBits);
24632 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
24633 return DAG.getNode(ISD::AND, DL, VT,
24634 Op, DAG.getConstant(Mask, DL, VT));
24636 case ISD::SIGN_EXTEND:
24637 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
24638 Op, DAG.getValueType(NarrowVT));
24640 llvm_unreachable("Unexpected opcode");
24644 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
24645 TargetLowering::DAGCombinerInfo &DCI,
24646 const X86Subtarget *Subtarget) {
24647 SDValue N0 = N->getOperand(0);
24648 SDValue N1 = N->getOperand(1);
24651 // A vector zext_in_reg may be represented as a shuffle,
24652 // feeding into a bitcast (this represents anyext) feeding into
24653 // an and with a mask.
24654 // We'd like to try to combine that into a shuffle with zero
24655 // plus a bitcast, removing the and.
24656 if (N0.getOpcode() != ISD::BITCAST ||
24657 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
24660 // The other side of the AND should be a splat of 2^C, where C
24661 // is the number of bits in the source type.
24662 if (N1.getOpcode() == ISD::BITCAST)
24663 N1 = N1.getOperand(0);
24664 if (N1.getOpcode() != ISD::BUILD_VECTOR)
24666 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
24668 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
24669 EVT SrcType = Shuffle->getValueType(0);
24671 // We expect a single-source shuffle
24672 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
24675 unsigned SrcSize = SrcType.getScalarSizeInBits();
24677 APInt SplatValue, SplatUndef;
24678 unsigned SplatBitSize;
24680 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
24681 SplatBitSize, HasAnyUndefs))
24684 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
24685 // Make sure the splat matches the mask we expect
24686 if (SplatBitSize > ResSize ||
24687 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
24690 // Make sure the input and output size make sense
24691 if (SrcSize >= ResSize || ResSize % SrcSize)
24694 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
24695 // The number of u's between each two values depends on the ratio between
24696 // the source and dest type.
24697 unsigned ZextRatio = ResSize / SrcSize;
24698 bool IsZext = true;
24699 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
24700 if (i % ZextRatio) {
24701 if (Shuffle->getMaskElt(i) > 0) {
24707 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
24708 // Expected element number
24718 // Ok, perform the transformation - replace the shuffle with
24719 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
24720 // (instead of undef) where the k elements come from the zero vector.
24721 SmallVector<int, 8> Mask;
24722 unsigned NumElems = SrcType.getVectorNumElements();
24723 for (unsigned i = 0; i < NumElems; ++i)
24725 Mask.push_back(NumElems);
24727 Mask.push_back(i / ZextRatio);
24729 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
24730 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
24731 return DAG.getBitcast(N0.getValueType(), NewShuffle);
24734 /// If both input operands of a logic op are being cast from floating point
24735 /// types, try to convert this into a floating point logic node to avoid
24736 /// unnecessary moves from SSE to integer registers.
24737 static SDValue convertIntLogicToFPLogic(SDNode *N, SelectionDAG &DAG,
24738 const X86Subtarget *Subtarget) {
24739 unsigned FPOpcode = ISD::DELETED_NODE;
24740 if (N->getOpcode() == ISD::AND)
24741 FPOpcode = X86ISD::FAND;
24742 else if (N->getOpcode() == ISD::OR)
24743 FPOpcode = X86ISD::FOR;
24744 else if (N->getOpcode() == ISD::XOR)
24745 FPOpcode = X86ISD::FXOR;
24747 assert(FPOpcode != ISD::DELETED_NODE &&
24748 "Unexpected input node for FP logic conversion");
24750 EVT VT = N->getValueType(0);
24751 SDValue N0 = N->getOperand(0);
24752 SDValue N1 = N->getOperand(1);
24754 if (N0.getOpcode() == ISD::BITCAST && N1.getOpcode() == ISD::BITCAST &&
24755 ((Subtarget->hasSSE1() && VT == MVT::i32) ||
24756 (Subtarget->hasSSE2() && VT == MVT::i64))) {
24757 SDValue N00 = N0.getOperand(0);
24758 SDValue N10 = N1.getOperand(0);
24759 EVT N00Type = N00.getValueType();
24760 EVT N10Type = N10.getValueType();
24761 if (N00Type.isFloatingPoint() && N10Type.isFloatingPoint()) {
24762 SDValue FPLogic = DAG.getNode(FPOpcode, DL, N00Type, N00, N10);
24763 return DAG.getBitcast(VT, FPLogic);
24769 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
24770 TargetLowering::DAGCombinerInfo &DCI,
24771 const X86Subtarget *Subtarget) {
24772 if (DCI.isBeforeLegalizeOps())
24775 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
24778 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24781 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24784 EVT VT = N->getValueType(0);
24785 SDValue N0 = N->getOperand(0);
24786 SDValue N1 = N->getOperand(1);
24789 // Create BEXTR instructions
24790 // BEXTR is ((X >> imm) & (2**size-1))
24791 if (VT == MVT::i32 || VT == MVT::i64) {
24792 // Check for BEXTR.
24793 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
24794 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
24795 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
24796 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24797 if (MaskNode && ShiftNode) {
24798 uint64_t Mask = MaskNode->getZExtValue();
24799 uint64_t Shift = ShiftNode->getZExtValue();
24800 if (isMask_64(Mask)) {
24801 uint64_t MaskSize = countPopulation(Mask);
24802 if (Shift + MaskSize <= VT.getSizeInBits())
24803 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
24804 DAG.getConstant(Shift | (MaskSize << 8), DL,
24813 // Want to form ANDNP nodes:
24814 // 1) In the hopes of then easily combining them with OR and AND nodes
24815 // to form PBLEND/PSIGN.
24816 // 2) To match ANDN packed intrinsics
24817 if (VT != MVT::v2i64 && VT != MVT::v4i64)
24820 // Check LHS for vnot
24821 if (N0.getOpcode() == ISD::XOR &&
24822 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
24823 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
24824 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
24826 // Check RHS for vnot
24827 if (N1.getOpcode() == ISD::XOR &&
24828 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
24829 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
24830 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
24835 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
24836 TargetLowering::DAGCombinerInfo &DCI,
24837 const X86Subtarget *Subtarget) {
24838 if (DCI.isBeforeLegalizeOps())
24841 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
24844 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
24847 SDValue N0 = N->getOperand(0);
24848 SDValue N1 = N->getOperand(1);
24849 EVT VT = N->getValueType(0);
24851 // look for psign/blend
24852 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
24853 if (!Subtarget->hasSSSE3() ||
24854 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
24857 // Canonicalize pandn to RHS
24858 if (N0.getOpcode() == X86ISD::ANDNP)
24860 // or (and (m, y), (pandn m, x))
24861 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
24862 SDValue Mask = N1.getOperand(0);
24863 SDValue X = N1.getOperand(1);
24865 if (N0.getOperand(0) == Mask)
24866 Y = N0.getOperand(1);
24867 if (N0.getOperand(1) == Mask)
24868 Y = N0.getOperand(0);
24870 // Check to see if the mask appeared in both the AND and ANDNP and
24874 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
24875 // Look through mask bitcast.
24876 if (Mask.getOpcode() == ISD::BITCAST)
24877 Mask = Mask.getOperand(0);
24878 if (X.getOpcode() == ISD::BITCAST)
24879 X = X.getOperand(0);
24880 if (Y.getOpcode() == ISD::BITCAST)
24881 Y = Y.getOperand(0);
24883 EVT MaskVT = Mask.getValueType();
24885 // Validate that the Mask operand is a vector sra node.
24886 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
24887 // there is no psrai.b
24888 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
24889 unsigned SraAmt = ~0;
24890 if (Mask.getOpcode() == ISD::SRA) {
24891 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
24892 if (auto *AmtConst = AmtBV->getConstantSplatNode())
24893 SraAmt = AmtConst->getZExtValue();
24894 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
24895 SDValue SraC = Mask.getOperand(1);
24896 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
24898 if ((SraAmt + 1) != EltBits)
24903 // Now we know we at least have a plendvb with the mask val. See if
24904 // we can form a psignb/w/d.
24905 // psign = x.type == y.type == mask.type && y = sub(0, x);
24906 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
24907 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
24908 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
24909 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
24910 "Unsupported VT for PSIGN");
24911 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
24912 return DAG.getBitcast(VT, Mask);
24914 // PBLENDVB only available on SSE 4.1
24915 if (!Subtarget->hasSSE41())
24918 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
24920 X = DAG.getBitcast(BlendVT, X);
24921 Y = DAG.getBitcast(BlendVT, Y);
24922 Mask = DAG.getBitcast(BlendVT, Mask);
24923 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
24924 return DAG.getBitcast(VT, Mask);
24928 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
24931 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
24932 bool OptForSize = DAG.getMachineFunction().getFunction()->optForSize();
24934 // SHLD/SHRD instructions have lower register pressure, but on some
24935 // platforms they have higher latency than the equivalent
24936 // series of shifts/or that would otherwise be generated.
24937 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
24938 // have higher latencies and we are not optimizing for size.
24939 if (!OptForSize && Subtarget->isSHLDSlow())
24942 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
24944 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
24946 if (!N0.hasOneUse() || !N1.hasOneUse())
24949 SDValue ShAmt0 = N0.getOperand(1);
24950 if (ShAmt0.getValueType() != MVT::i8)
24952 SDValue ShAmt1 = N1.getOperand(1);
24953 if (ShAmt1.getValueType() != MVT::i8)
24955 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
24956 ShAmt0 = ShAmt0.getOperand(0);
24957 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
24958 ShAmt1 = ShAmt1.getOperand(0);
24961 unsigned Opc = X86ISD::SHLD;
24962 SDValue Op0 = N0.getOperand(0);
24963 SDValue Op1 = N1.getOperand(0);
24964 if (ShAmt0.getOpcode() == ISD::SUB) {
24965 Opc = X86ISD::SHRD;
24966 std::swap(Op0, Op1);
24967 std::swap(ShAmt0, ShAmt1);
24970 unsigned Bits = VT.getSizeInBits();
24971 if (ShAmt1.getOpcode() == ISD::SUB) {
24972 SDValue Sum = ShAmt1.getOperand(0);
24973 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
24974 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
24975 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
24976 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
24977 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
24978 return DAG.getNode(Opc, DL, VT,
24980 DAG.getNode(ISD::TRUNCATE, DL,
24983 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
24984 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
24986 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
24987 return DAG.getNode(Opc, DL, VT,
24988 N0.getOperand(0), N1.getOperand(0),
24989 DAG.getNode(ISD::TRUNCATE, DL,
24996 // Generate NEG and CMOV for integer abs.
24997 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
24998 EVT VT = N->getValueType(0);
25000 // Since X86 does not have CMOV for 8-bit integer, we don't convert
25001 // 8-bit integer abs to NEG and CMOV.
25002 if (VT.isInteger() && VT.getSizeInBits() == 8)
25005 SDValue N0 = N->getOperand(0);
25006 SDValue N1 = N->getOperand(1);
25009 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
25010 // and change it to SUB and CMOV.
25011 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
25012 N0.getOpcode() == ISD::ADD &&
25013 N0.getOperand(1) == N1 &&
25014 N1.getOpcode() == ISD::SRA &&
25015 N1.getOperand(0) == N0.getOperand(0))
25016 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
25017 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
25018 // Generate SUB & CMOV.
25019 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
25020 DAG.getConstant(0, DL, VT), N0.getOperand(0));
25022 SDValue Ops[] = { N0.getOperand(0), Neg,
25023 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
25024 SDValue(Neg.getNode(), 1) };
25025 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
25030 // Try to turn tests against the signbit in the form of:
25031 // XOR(TRUNCATE(SRL(X, size(X)-1)), 1)
25034 static SDValue foldXorTruncShiftIntoCmp(SDNode *N, SelectionDAG &DAG) {
25035 // This is only worth doing if the output type is i8.
25036 if (N->getValueType(0) != MVT::i8)
25039 SDValue N0 = N->getOperand(0);
25040 SDValue N1 = N->getOperand(1);
25042 // We should be performing an xor against a truncated shift.
25043 if (N0.getOpcode() != ISD::TRUNCATE || !N0.hasOneUse())
25046 // Make sure we are performing an xor against one.
25047 if (!isa<ConstantSDNode>(N1) || !cast<ConstantSDNode>(N1)->isOne())
25050 // SetCC on x86 zero extends so only act on this if it's a logical shift.
25051 SDValue Shift = N0.getOperand(0);
25052 if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse())
25055 // Make sure we are truncating from one of i16, i32 or i64.
25056 EVT ShiftTy = Shift.getValueType();
25057 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64)
25060 // Make sure the shift amount extracts the sign bit.
25061 if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
25062 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
25065 // Create a greater-than comparison against -1.
25066 // N.B. Using SETGE against 0 works but we want a canonical looking
25067 // comparison, using SETGT matches up with what TranslateX86CC.
25069 SDValue ShiftOp = Shift.getOperand(0);
25070 EVT ShiftOpTy = ShiftOp.getValueType();
25071 SDValue Cond = DAG.getSetCC(DL, MVT::i8, ShiftOp,
25072 DAG.getConstant(-1, DL, ShiftOpTy), ISD::SETGT);
25076 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
25077 TargetLowering::DAGCombinerInfo &DCI,
25078 const X86Subtarget *Subtarget) {
25079 if (DCI.isBeforeLegalizeOps())
25082 if (SDValue RV = foldXorTruncShiftIntoCmp(N, DAG))
25085 if (Subtarget->hasCMov())
25086 if (SDValue RV = performIntegerAbsCombine(N, DAG))
25089 if (SDValue FPLogic = convertIntLogicToFPLogic(N, DAG, Subtarget))
25095 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
25096 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
25097 TargetLowering::DAGCombinerInfo &DCI,
25098 const X86Subtarget *Subtarget) {
25099 LoadSDNode *Ld = cast<LoadSDNode>(N);
25100 EVT RegVT = Ld->getValueType(0);
25101 EVT MemVT = Ld->getMemoryVT();
25103 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25105 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
25106 // into two 16-byte operations.
25107 ISD::LoadExtType Ext = Ld->getExtensionType();
25109 unsigned AddressSpace = Ld->getAddressSpace();
25110 unsigned Alignment = Ld->getAlignment();
25111 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() &&
25112 Ext == ISD::NON_EXTLOAD &&
25113 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), RegVT,
25114 AddressSpace, Alignment, &Fast) && !Fast) {
25115 unsigned NumElems = RegVT.getVectorNumElements();
25119 SDValue Ptr = Ld->getBasePtr();
25120 SDValue Increment =
25121 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25123 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
25125 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25126 Ld->getPointerInfo(), Ld->isVolatile(),
25127 Ld->isNonTemporal(), Ld->isInvariant(),
25129 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25130 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
25131 Ld->getPointerInfo(), Ld->isVolatile(),
25132 Ld->isNonTemporal(), Ld->isInvariant(),
25133 std::min(16U, Alignment));
25134 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
25136 Load2.getValue(1));
25138 SDValue NewVec = DAG.getUNDEF(RegVT);
25139 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
25140 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
25141 return DCI.CombineTo(N, NewVec, TF, true);
25147 /// PerformMLOADCombine - Resolve extending loads
25148 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
25149 TargetLowering::DAGCombinerInfo &DCI,
25150 const X86Subtarget *Subtarget) {
25151 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
25152 if (Mld->getExtensionType() != ISD::SEXTLOAD)
25155 EVT VT = Mld->getValueType(0);
25156 unsigned NumElems = VT.getVectorNumElements();
25157 EVT LdVT = Mld->getMemoryVT();
25160 assert(LdVT != VT && "Cannot extend to the same type");
25161 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
25162 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
25163 // From, To sizes and ElemCount must be pow of two
25164 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25165 "Unexpected size for extending masked load");
25167 unsigned SizeRatio = ToSz / FromSz;
25168 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
25170 // Create a type on which we perform the shuffle
25171 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25172 LdVT.getScalarType(), NumElems*SizeRatio);
25173 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25175 // Convert Src0 value
25176 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
25177 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
25178 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25179 for (unsigned i = 0; i != NumElems; ++i)
25180 ShuffleVec[i] = i * SizeRatio;
25182 // Can't shuffle using an illegal type.
25183 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25184 "WideVecVT should be legal");
25185 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
25186 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
25188 // Prepare the new mask
25190 SDValue Mask = Mld->getMask();
25191 if (Mask.getValueType() == VT) {
25192 // Mask and original value have the same type
25193 NewMask = DAG.getBitcast(WideVecVT, Mask);
25194 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25195 for (unsigned i = 0; i != NumElems; ++i)
25196 ShuffleVec[i] = i * SizeRatio;
25197 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25198 ShuffleVec[i] = NumElems*SizeRatio;
25199 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25200 DAG.getConstant(0, dl, WideVecVT),
25204 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25205 unsigned WidenNumElts = NumElems*SizeRatio;
25206 unsigned MaskNumElts = VT.getVectorNumElements();
25207 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25210 unsigned NumConcat = WidenNumElts / MaskNumElts;
25211 SmallVector<SDValue, 16> Ops(NumConcat);
25212 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25214 for (unsigned i = 1; i != NumConcat; ++i)
25217 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25220 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
25221 Mld->getBasePtr(), NewMask, WideSrc0,
25222 Mld->getMemoryVT(), Mld->getMemOperand(),
25224 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
25225 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
25227 /// PerformMSTORECombine - Resolve truncating stores
25228 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
25229 const X86Subtarget *Subtarget) {
25230 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
25231 if (!Mst->isTruncatingStore())
25234 EVT VT = Mst->getValue().getValueType();
25235 unsigned NumElems = VT.getVectorNumElements();
25236 EVT StVT = Mst->getMemoryVT();
25239 assert(StVT != VT && "Cannot truncate to the same type");
25240 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25241 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25243 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25245 // The truncating store is legal in some cases. For example
25246 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25247 // are designated for truncate store.
25248 // In this case we don't need any further transformations.
25249 if (TLI.isTruncStoreLegal(VT, StVT))
25252 // From, To sizes and ElemCount must be pow of two
25253 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
25254 "Unexpected size for truncating masked store");
25255 // We are going to use the original vector elt for storing.
25256 // Accumulated smaller vector elements must be a multiple of the store size.
25257 assert (((NumElems * FromSz) % ToSz) == 0 &&
25258 "Unexpected ratio for truncating masked store");
25260 unsigned SizeRatio = FromSz / ToSz;
25261 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25263 // Create a type on which we perform the shuffle
25264 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25265 StVT.getScalarType(), NumElems*SizeRatio);
25267 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25269 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
25270 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
25271 for (unsigned i = 0; i != NumElems; ++i)
25272 ShuffleVec[i] = i * SizeRatio;
25274 // Can't shuffle using an illegal type.
25275 assert(DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT) &&
25276 "WideVecVT should be legal");
25278 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25279 DAG.getUNDEF(WideVecVT),
25283 SDValue Mask = Mst->getMask();
25284 if (Mask.getValueType() == VT) {
25285 // Mask and original value have the same type
25286 NewMask = DAG.getBitcast(WideVecVT, Mask);
25287 for (unsigned i = 0; i != NumElems; ++i)
25288 ShuffleVec[i] = i * SizeRatio;
25289 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
25290 ShuffleVec[i] = NumElems*SizeRatio;
25291 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
25292 DAG.getConstant(0, dl, WideVecVT),
25296 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
25297 unsigned WidenNumElts = NumElems*SizeRatio;
25298 unsigned MaskNumElts = VT.getVectorNumElements();
25299 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
25302 unsigned NumConcat = WidenNumElts / MaskNumElts;
25303 SmallVector<SDValue, 16> Ops(NumConcat);
25304 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
25306 for (unsigned i = 1; i != NumConcat; ++i)
25309 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
25312 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
25313 NewMask, StVT, Mst->getMemOperand(), false);
25315 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
25316 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
25317 const X86Subtarget *Subtarget) {
25318 StoreSDNode *St = cast<StoreSDNode>(N);
25319 EVT VT = St->getValue().getValueType();
25320 EVT StVT = St->getMemoryVT();
25322 SDValue StoredVal = St->getOperand(1);
25323 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25325 // If we are saving a concatenation of two XMM registers and 32-byte stores
25326 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
25328 unsigned AddressSpace = St->getAddressSpace();
25329 unsigned Alignment = St->getAlignment();
25330 if (VT.is256BitVector() && StVT == VT &&
25331 TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
25332 AddressSpace, Alignment, &Fast) && !Fast) {
25333 unsigned NumElems = VT.getVectorNumElements();
25337 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
25338 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
25341 DAG.getConstant(16, dl, TLI.getPointerTy(DAG.getDataLayout()));
25342 SDValue Ptr0 = St->getBasePtr();
25343 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
25345 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
25346 St->getPointerInfo(), St->isVolatile(),
25347 St->isNonTemporal(), Alignment);
25348 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
25349 St->getPointerInfo(), St->isVolatile(),
25350 St->isNonTemporal(),
25351 std::min(16U, Alignment));
25352 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
25355 // Optimize trunc store (of multiple scalars) to shuffle and store.
25356 // First, pack all of the elements in one place. Next, store to memory
25357 // in fewer chunks.
25358 if (St->isTruncatingStore() && VT.isVector()) {
25359 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25360 unsigned NumElems = VT.getVectorNumElements();
25361 assert(StVT != VT && "Cannot truncate to the same type");
25362 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
25363 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
25365 // The truncating store is legal in some cases. For example
25366 // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw
25367 // are designated for truncate store.
25368 // In this case we don't need any further transformations.
25369 if (TLI.isTruncStoreLegal(VT, StVT))
25372 // From, To sizes and ElemCount must be pow of two
25373 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
25374 // We are going to use the original vector elt for storing.
25375 // Accumulated smaller vector elements must be a multiple of the store size.
25376 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
25378 unsigned SizeRatio = FromSz / ToSz;
25380 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
25382 // Create a type on which we perform the shuffle
25383 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
25384 StVT.getScalarType(), NumElems*SizeRatio);
25386 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
25388 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
25389 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
25390 for (unsigned i = 0; i != NumElems; ++i)
25391 ShuffleVec[i] = i * SizeRatio;
25393 // Can't shuffle using an illegal type.
25394 if (!TLI.isTypeLegal(WideVecVT))
25397 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
25398 DAG.getUNDEF(WideVecVT),
25400 // At this point all of the data is stored at the bottom of the
25401 // register. We now need to save it to mem.
25403 // Find the largest store unit
25404 MVT StoreType = MVT::i8;
25405 for (MVT Tp : MVT::integer_valuetypes()) {
25406 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
25410 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
25411 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
25412 (64 <= NumElems * ToSz))
25413 StoreType = MVT::f64;
25415 // Bitcast the original vector into a vector of store-size units
25416 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
25417 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
25418 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
25419 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
25420 SmallVector<SDValue, 8> Chains;
25421 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, dl,
25422 TLI.getPointerTy(DAG.getDataLayout()));
25423 SDValue Ptr = St->getBasePtr();
25425 // Perform one or more big stores into memory.
25426 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
25427 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
25428 StoreType, ShuffWide,
25429 DAG.getIntPtrConstant(i, dl));
25430 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
25431 St->getPointerInfo(), St->isVolatile(),
25432 St->isNonTemporal(), St->getAlignment());
25433 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
25434 Chains.push_back(Ch);
25437 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
25440 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
25441 // the FP state in cases where an emms may be missing.
25442 // A preferable solution to the general problem is to figure out the right
25443 // places to insert EMMS. This qualifies as a quick hack.
25445 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
25446 if (VT.getSizeInBits() != 64)
25449 const Function *F = DAG.getMachineFunction().getFunction();
25450 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
25452 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
25453 if ((VT.isVector() ||
25454 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
25455 isa<LoadSDNode>(St->getValue()) &&
25456 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
25457 St->getChain().hasOneUse() && !St->isVolatile()) {
25458 SDNode* LdVal = St->getValue().getNode();
25459 LoadSDNode *Ld = nullptr;
25460 int TokenFactorIndex = -1;
25461 SmallVector<SDValue, 8> Ops;
25462 SDNode* ChainVal = St->getChain().getNode();
25463 // Must be a store of a load. We currently handle two cases: the load
25464 // is a direct child, and it's under an intervening TokenFactor. It is
25465 // possible to dig deeper under nested TokenFactors.
25466 if (ChainVal == LdVal)
25467 Ld = cast<LoadSDNode>(St->getChain());
25468 else if (St->getValue().hasOneUse() &&
25469 ChainVal->getOpcode() == ISD::TokenFactor) {
25470 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
25471 if (ChainVal->getOperand(i).getNode() == LdVal) {
25472 TokenFactorIndex = i;
25473 Ld = cast<LoadSDNode>(St->getValue());
25475 Ops.push_back(ChainVal->getOperand(i));
25479 if (!Ld || !ISD::isNormalLoad(Ld))
25482 // If this is not the MMX case, i.e. we are just turning i64 load/store
25483 // into f64 load/store, avoid the transformation if there are multiple
25484 // uses of the loaded value.
25485 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
25490 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
25491 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
25493 if (Subtarget->is64Bit() || F64IsLegal) {
25494 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
25495 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
25496 Ld->getPointerInfo(), Ld->isVolatile(),
25497 Ld->isNonTemporal(), Ld->isInvariant(),
25498 Ld->getAlignment());
25499 SDValue NewChain = NewLd.getValue(1);
25500 if (TokenFactorIndex != -1) {
25501 Ops.push_back(NewChain);
25502 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25504 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
25505 St->getPointerInfo(),
25506 St->isVolatile(), St->isNonTemporal(),
25507 St->getAlignment());
25510 // Otherwise, lower to two pairs of 32-bit loads / stores.
25511 SDValue LoAddr = Ld->getBasePtr();
25512 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
25513 DAG.getConstant(4, LdDL, MVT::i32));
25515 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
25516 Ld->getPointerInfo(),
25517 Ld->isVolatile(), Ld->isNonTemporal(),
25518 Ld->isInvariant(), Ld->getAlignment());
25519 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
25520 Ld->getPointerInfo().getWithOffset(4),
25521 Ld->isVolatile(), Ld->isNonTemporal(),
25523 MinAlign(Ld->getAlignment(), 4));
25525 SDValue NewChain = LoLd.getValue(1);
25526 if (TokenFactorIndex != -1) {
25527 Ops.push_back(LoLd);
25528 Ops.push_back(HiLd);
25529 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
25532 LoAddr = St->getBasePtr();
25533 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
25534 DAG.getConstant(4, StDL, MVT::i32));
25536 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
25537 St->getPointerInfo(),
25538 St->isVolatile(), St->isNonTemporal(),
25539 St->getAlignment());
25540 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
25541 St->getPointerInfo().getWithOffset(4),
25543 St->isNonTemporal(),
25544 MinAlign(St->getAlignment(), 4));
25545 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
25548 // This is similar to the above case, but here we handle a scalar 64-bit
25549 // integer store that is extracted from a vector on a 32-bit target.
25550 // If we have SSE2, then we can treat it like a floating-point double
25551 // to get past legalization. The execution dependencies fixup pass will
25552 // choose the optimal machine instruction for the store if this really is
25553 // an integer or v2f32 rather than an f64.
25554 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
25555 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
25556 SDValue OldExtract = St->getOperand(1);
25557 SDValue ExtOp0 = OldExtract.getOperand(0);
25558 unsigned VecSize = ExtOp0.getValueSizeInBits();
25559 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
25560 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
25561 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
25562 BitCast, OldExtract.getOperand(1));
25563 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
25564 St->getPointerInfo(), St->isVolatile(),
25565 St->isNonTemporal(), St->getAlignment());
25571 /// Return 'true' if this vector operation is "horizontal"
25572 /// and return the operands for the horizontal operation in LHS and RHS. A
25573 /// horizontal operation performs the binary operation on successive elements
25574 /// of its first operand, then on successive elements of its second operand,
25575 /// returning the resulting values in a vector. For example, if
25576 /// A = < float a0, float a1, float a2, float a3 >
25578 /// B = < float b0, float b1, float b2, float b3 >
25579 /// then the result of doing a horizontal operation on A and B is
25580 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
25581 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
25582 /// A horizontal-op B, for some already available A and B, and if so then LHS is
25583 /// set to A, RHS to B, and the routine returns 'true'.
25584 /// Note that the binary operation should have the property that if one of the
25585 /// operands is UNDEF then the result is UNDEF.
25586 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
25587 // Look for the following pattern: if
25588 // A = < float a0, float a1, float a2, float a3 >
25589 // B = < float b0, float b1, float b2, float b3 >
25591 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
25592 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
25593 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
25594 // which is A horizontal-op B.
25596 // At least one of the operands should be a vector shuffle.
25597 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
25598 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
25601 MVT VT = LHS.getSimpleValueType();
25603 assert((VT.is128BitVector() || VT.is256BitVector()) &&
25604 "Unsupported vector type for horizontal add/sub");
25606 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
25607 // operate independently on 128-bit lanes.
25608 unsigned NumElts = VT.getVectorNumElements();
25609 unsigned NumLanes = VT.getSizeInBits()/128;
25610 unsigned NumLaneElts = NumElts / NumLanes;
25611 assert((NumLaneElts % 2 == 0) &&
25612 "Vector type should have an even number of elements in each lane");
25613 unsigned HalfLaneElts = NumLaneElts/2;
25615 // View LHS in the form
25616 // LHS = VECTOR_SHUFFLE A, B, LMask
25617 // If LHS is not a shuffle then pretend it is the shuffle
25618 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
25619 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
25622 SmallVector<int, 16> LMask(NumElts);
25623 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25624 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
25625 A = LHS.getOperand(0);
25626 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
25627 B = LHS.getOperand(1);
25628 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
25629 std::copy(Mask.begin(), Mask.end(), LMask.begin());
25631 if (LHS.getOpcode() != ISD::UNDEF)
25633 for (unsigned i = 0; i != NumElts; ++i)
25637 // Likewise, view RHS in the form
25638 // RHS = VECTOR_SHUFFLE C, D, RMask
25640 SmallVector<int, 16> RMask(NumElts);
25641 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
25642 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
25643 C = RHS.getOperand(0);
25644 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
25645 D = RHS.getOperand(1);
25646 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
25647 std::copy(Mask.begin(), Mask.end(), RMask.begin());
25649 if (RHS.getOpcode() != ISD::UNDEF)
25651 for (unsigned i = 0; i != NumElts; ++i)
25655 // Check that the shuffles are both shuffling the same vectors.
25656 if (!(A == C && B == D) && !(A == D && B == C))
25659 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
25660 if (!A.getNode() && !B.getNode())
25663 // If A and B occur in reverse order in RHS, then "swap" them (which means
25664 // rewriting the mask).
25666 ShuffleVectorSDNode::commuteMask(RMask);
25668 // At this point LHS and RHS are equivalent to
25669 // LHS = VECTOR_SHUFFLE A, B, LMask
25670 // RHS = VECTOR_SHUFFLE A, B, RMask
25671 // Check that the masks correspond to performing a horizontal operation.
25672 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
25673 for (unsigned i = 0; i != NumLaneElts; ++i) {
25674 int LIdx = LMask[i+l], RIdx = RMask[i+l];
25676 // Ignore any UNDEF components.
25677 if (LIdx < 0 || RIdx < 0 ||
25678 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
25679 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
25682 // Check that successive elements are being operated on. If not, this is
25683 // not a horizontal operation.
25684 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
25685 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
25686 if (!(LIdx == Index && RIdx == Index + 1) &&
25687 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
25692 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
25693 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
25697 /// Do target-specific dag combines on floating point adds.
25698 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
25699 const X86Subtarget *Subtarget) {
25700 EVT VT = N->getValueType(0);
25701 SDValue LHS = N->getOperand(0);
25702 SDValue RHS = N->getOperand(1);
25704 // Try to synthesize horizontal adds from adds of shuffles.
25705 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25706 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25707 isHorizontalBinOp(LHS, RHS, true))
25708 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
25712 /// Do target-specific dag combines on floating point subs.
25713 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
25714 const X86Subtarget *Subtarget) {
25715 EVT VT = N->getValueType(0);
25716 SDValue LHS = N->getOperand(0);
25717 SDValue RHS = N->getOperand(1);
25719 // Try to synthesize horizontal subs from subs of shuffles.
25720 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
25721 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
25722 isHorizontalBinOp(LHS, RHS, false))
25723 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
25727 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
25728 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG,
25729 const X86Subtarget *Subtarget) {
25730 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
25732 // F[X]OR(0.0, x) -> x
25733 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25734 if (C->getValueAPF().isPosZero())
25735 return N->getOperand(1);
25737 // F[X]OR(x, 0.0) -> x
25738 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25739 if (C->getValueAPF().isPosZero())
25740 return N->getOperand(0);
25742 EVT VT = N->getValueType(0);
25743 if (VT.is512BitVector() && !Subtarget->hasDQI()) {
25745 MVT IntScalar = MVT::getIntegerVT(VT.getScalarSizeInBits());
25746 MVT IntVT = MVT::getVectorVT(IntScalar, VT.getVectorNumElements());
25748 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(0));
25749 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, IntVT, N->getOperand(1));
25750 unsigned IntOpcode = (N->getOpcode() == X86ISD::FOR) ? ISD::OR : ISD::XOR;
25751 SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
25752 return DAG.getNode(ISD::BITCAST, dl, VT, IntOp);
25757 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
25758 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
25759 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
25761 // Only perform optimizations if UnsafeMath is used.
25762 if (!DAG.getTarget().Options.UnsafeFPMath)
25765 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
25766 // into FMINC and FMAXC, which are Commutative operations.
25767 unsigned NewOp = 0;
25768 switch (N->getOpcode()) {
25769 default: llvm_unreachable("unknown opcode");
25770 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
25771 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
25774 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
25775 N->getOperand(0), N->getOperand(1));
25778 /// Do target-specific dag combines on X86ISD::FAND nodes.
25779 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
25780 // FAND(0.0, x) -> 0.0
25781 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25782 if (C->getValueAPF().isPosZero())
25783 return N->getOperand(0);
25785 // FAND(x, 0.0) -> 0.0
25786 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25787 if (C->getValueAPF().isPosZero())
25788 return N->getOperand(1);
25793 /// Do target-specific dag combines on X86ISD::FANDN nodes
25794 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
25795 // FANDN(0.0, x) -> x
25796 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
25797 if (C->getValueAPF().isPosZero())
25798 return N->getOperand(1);
25800 // FANDN(x, 0.0) -> 0.0
25801 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
25802 if (C->getValueAPF().isPosZero())
25803 return N->getOperand(1);
25808 static SDValue PerformBTCombine(SDNode *N,
25810 TargetLowering::DAGCombinerInfo &DCI) {
25811 // BT ignores high bits in the bit index operand.
25812 SDValue Op1 = N->getOperand(1);
25813 if (Op1.hasOneUse()) {
25814 unsigned BitWidth = Op1.getValueSizeInBits();
25815 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
25816 APInt KnownZero, KnownOne;
25817 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
25818 !DCI.isBeforeLegalizeOps());
25819 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
25820 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
25821 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
25822 DCI.CommitTargetLoweringOpt(TLO);
25827 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
25828 SDValue Op = N->getOperand(0);
25829 if (Op.getOpcode() == ISD::BITCAST)
25830 Op = Op.getOperand(0);
25831 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
25832 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
25833 VT.getVectorElementType().getSizeInBits() ==
25834 OpVT.getVectorElementType().getSizeInBits()) {
25835 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
25840 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
25841 const X86Subtarget *Subtarget) {
25842 EVT VT = N->getValueType(0);
25843 if (!VT.isVector())
25846 SDValue N0 = N->getOperand(0);
25847 SDValue N1 = N->getOperand(1);
25848 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
25851 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
25852 // both SSE and AVX2 since there is no sign-extended shift right
25853 // operation on a vector with 64-bit elements.
25854 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
25855 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
25856 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
25857 N0.getOpcode() == ISD::SIGN_EXTEND)) {
25858 SDValue N00 = N0.getOperand(0);
25860 // EXTLOAD has a better solution on AVX2,
25861 // it may be replaced with X86ISD::VSEXT node.
25862 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
25863 if (!ISD::isNormalLoad(N00.getNode()))
25866 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
25867 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
25869 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
25875 /// sext(add_nsw(x, C)) --> add(sext(x), C_sext)
25876 /// Promoting a sign extension ahead of an 'add nsw' exposes opportunities
25877 /// to combine math ops, use an LEA, or use a complex addressing mode. This can
25878 /// eliminate extend, add, and shift instructions.
25879 static SDValue promoteSextBeforeAddNSW(SDNode *Sext, SelectionDAG &DAG,
25880 const X86Subtarget *Subtarget) {
25881 // TODO: This should be valid for other integer types.
25882 EVT VT = Sext->getValueType(0);
25883 if (VT != MVT::i64)
25886 // We need an 'add nsw' feeding into the 'sext'.
25887 SDValue Add = Sext->getOperand(0);
25888 if (Add.getOpcode() != ISD::ADD || !Add->getFlags()->hasNoSignedWrap())
25891 // Having a constant operand to the 'add' ensures that we are not increasing
25892 // the instruction count because the constant is extended for free below.
25893 // A constant operand can also become the displacement field of an LEA.
25894 auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
25898 // Don't make the 'add' bigger if there's no hope of combining it with some
25899 // other 'add' or 'shl' instruction.
25900 // TODO: It may be profitable to generate simpler LEA instructions in place
25901 // of single 'add' instructions, but the cost model for selecting an LEA
25902 // currently has a high threshold.
25903 bool HasLEAPotential = false;
25904 for (auto *User : Sext->uses()) {
25905 if (User->getOpcode() == ISD::ADD || User->getOpcode() == ISD::SHL) {
25906 HasLEAPotential = true;
25910 if (!HasLEAPotential)
25913 // Everything looks good, so pull the 'sext' ahead of the 'add'.
25914 int64_t AddConstant = AddOp1->getSExtValue();
25915 SDValue AddOp0 = Add.getOperand(0);
25916 SDValue NewSext = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(Sext), VT, AddOp0);
25917 SDValue NewConstant = DAG.getConstant(AddConstant, SDLoc(Add), VT);
25919 // The wider add is guaranteed to not wrap because both operands are
25922 Flags.setNoSignedWrap(true);
25923 return DAG.getNode(ISD::ADD, SDLoc(Add), VT, NewSext, NewConstant, &Flags);
25926 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
25927 TargetLowering::DAGCombinerInfo &DCI,
25928 const X86Subtarget *Subtarget) {
25929 SDValue N0 = N->getOperand(0);
25930 EVT VT = N->getValueType(0);
25931 EVT SVT = VT.getScalarType();
25932 EVT InVT = N0.getValueType();
25933 EVT InSVT = InVT.getScalarType();
25936 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
25937 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
25938 // This exposes the sext to the sdivrem lowering, so that it directly extends
25939 // from AH (which we otherwise need to do contortions to access).
25940 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
25941 InVT == MVT::i8 && VT == MVT::i32) {
25942 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
25943 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
25944 N0.getOperand(0), N0.getOperand(1));
25945 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
25946 return R.getValue(1);
25949 if (!DCI.isBeforeLegalizeOps()) {
25950 if (InVT == MVT::i1) {
25951 SDValue Zero = DAG.getConstant(0, DL, VT);
25953 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
25954 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
25959 if (VT.isVector() && Subtarget->hasSSE2()) {
25960 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
25961 EVT InVT = N.getValueType();
25962 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
25963 Size / InVT.getScalarSizeInBits());
25964 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
25965 DAG.getUNDEF(InVT));
25967 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
25970 // If target-size is less than 128-bits, extend to a type that would extend
25971 // to 128 bits, extend that and extract the original target vector.
25972 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
25973 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25974 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25975 unsigned Scale = 128 / VT.getSizeInBits();
25977 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
25978 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
25979 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
25980 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
25981 DAG.getIntPtrConstant(0, DL));
25984 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
25985 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
25986 if (VT.getSizeInBits() == 128 &&
25987 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25988 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25989 SDValue ExOp = ExtendVecSize(DL, N0, 128);
25990 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
25993 // On pre-AVX2 targets, split into 128-bit nodes of
25994 // ISD::SIGN_EXTEND_VECTOR_INREG.
25995 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
25996 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
25997 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
25998 unsigned NumVecs = VT.getSizeInBits() / 128;
25999 unsigned NumSubElts = 128 / SVT.getSizeInBits();
26000 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
26001 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
26003 SmallVector<SDValue, 8> Opnds;
26004 for (unsigned i = 0, Offset = 0; i != NumVecs;
26005 ++i, Offset += NumSubElts) {
26006 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
26007 DAG.getIntPtrConstant(Offset, DL));
26008 SrcVec = ExtendVecSize(DL, SrcVec, 128);
26009 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
26010 Opnds.push_back(SrcVec);
26012 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
26016 if (Subtarget->hasAVX() && VT.isVector() && VT.getSizeInBits() == 256)
26017 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26020 if (SDValue NewAdd = promoteSextBeforeAddNSW(N, DAG, Subtarget))
26026 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
26027 const X86Subtarget* Subtarget) {
26029 EVT VT = N->getValueType(0);
26031 // Let legalize expand this if it isn't a legal type yet.
26032 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
26035 EVT ScalarVT = VT.getScalarType();
26036 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
26037 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
26038 !Subtarget->hasAVX512()))
26041 SDValue A = N->getOperand(0);
26042 SDValue B = N->getOperand(1);
26043 SDValue C = N->getOperand(2);
26045 bool NegA = (A.getOpcode() == ISD::FNEG);
26046 bool NegB = (B.getOpcode() == ISD::FNEG);
26047 bool NegC = (C.getOpcode() == ISD::FNEG);
26049 // Negative multiplication when NegA xor NegB
26050 bool NegMul = (NegA != NegB);
26052 A = A.getOperand(0);
26054 B = B.getOperand(0);
26056 C = C.getOperand(0);
26060 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
26062 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
26064 return DAG.getNode(Opcode, dl, VT, A, B, C);
26067 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
26068 TargetLowering::DAGCombinerInfo &DCI,
26069 const X86Subtarget *Subtarget) {
26070 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
26071 // (and (i32 x86isd::setcc_carry), 1)
26072 // This eliminates the zext. This transformation is necessary because
26073 // ISD::SETCC is always legalized to i8.
26075 SDValue N0 = N->getOperand(0);
26076 EVT VT = N->getValueType(0);
26078 if (N0.getOpcode() == ISD::AND &&
26080 N0.getOperand(0).hasOneUse()) {
26081 SDValue N00 = N0.getOperand(0);
26082 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26083 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
26084 if (!C || C->getZExtValue() != 1)
26086 return DAG.getNode(ISD::AND, dl, VT,
26087 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26088 N00.getOperand(0), N00.getOperand(1)),
26089 DAG.getConstant(1, dl, VT));
26093 if (N0.getOpcode() == ISD::TRUNCATE &&
26095 N0.getOperand(0).hasOneUse()) {
26096 SDValue N00 = N0.getOperand(0);
26097 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
26098 return DAG.getNode(ISD::AND, dl, VT,
26099 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
26100 N00.getOperand(0), N00.getOperand(1)),
26101 DAG.getConstant(1, dl, VT));
26105 if (VT.is256BitVector())
26106 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
26109 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
26110 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
26111 // This exposes the zext to the udivrem lowering, so that it directly extends
26112 // from AH (which we otherwise need to do contortions to access).
26113 if (N0.getOpcode() == ISD::UDIVREM &&
26114 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
26115 (VT == MVT::i32 || VT == MVT::i64)) {
26116 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
26117 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
26118 N0.getOperand(0), N0.getOperand(1));
26119 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
26120 return R.getValue(1);
26126 // Optimize x == -y --> x+y == 0
26127 // x != -y --> x+y != 0
26128 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
26129 const X86Subtarget* Subtarget) {
26130 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
26131 SDValue LHS = N->getOperand(0);
26132 SDValue RHS = N->getOperand(1);
26133 EVT VT = N->getValueType(0);
26136 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
26137 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
26138 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
26139 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
26140 LHS.getOperand(1));
26141 return DAG.getSetCC(DL, N->getValueType(0), addV,
26142 DAG.getConstant(0, DL, addV.getValueType()), CC);
26144 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
26145 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
26146 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
26147 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
26148 RHS.getOperand(1));
26149 return DAG.getSetCC(DL, N->getValueType(0), addV,
26150 DAG.getConstant(0, DL, addV.getValueType()), CC);
26153 if (VT.getScalarType() == MVT::i1 &&
26154 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
26156 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26157 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26158 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26160 if (!IsSEXT0 || !IsVZero1) {
26161 // Swap the operands and update the condition code.
26162 std::swap(LHS, RHS);
26163 CC = ISD::getSetCCSwappedOperands(CC);
26165 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
26166 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
26167 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
26170 if (IsSEXT0 && IsVZero1) {
26171 assert(VT == LHS.getOperand(0).getValueType() &&
26172 "Uexpected operand type");
26173 if (CC == ISD::SETGT)
26174 return DAG.getConstant(0, DL, VT);
26175 if (CC == ISD::SETLE)
26176 return DAG.getConstant(1, DL, VT);
26177 if (CC == ISD::SETEQ || CC == ISD::SETGE)
26178 return DAG.getNOT(DL, LHS.getOperand(0), VT);
26180 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
26181 "Unexpected condition code!");
26182 return LHS.getOperand(0);
26189 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
26190 SelectionDAG &DAG) {
26192 MVT VT = Load->getSimpleValueType(0);
26193 MVT EVT = VT.getVectorElementType();
26194 SDValue Addr = Load->getOperand(1);
26195 SDValue NewAddr = DAG.getNode(
26196 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
26197 DAG.getConstant(Index * EVT.getStoreSize(), dl,
26198 Addr.getSimpleValueType()));
26201 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
26202 DAG.getMachineFunction().getMachineMemOperand(
26203 Load->getMemOperand(), 0, EVT.getStoreSize()));
26207 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
26208 const X86Subtarget *Subtarget) {
26210 MVT VT = N->getOperand(1)->getSimpleValueType(0);
26211 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
26212 "X86insertps is only defined for v4x32");
26214 SDValue Ld = N->getOperand(1);
26215 if (MayFoldLoad(Ld)) {
26216 // Extract the countS bits from the immediate so we can get the proper
26217 // address when narrowing the vector load to a specific element.
26218 // When the second source op is a memory address, insertps doesn't use
26219 // countS and just gets an f32 from that address.
26220 unsigned DestIndex =
26221 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
26223 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
26225 // Create this as a scalar to vector to match the instruction pattern.
26226 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
26227 // countS bits are ignored when loading from memory on insertps, which
26228 // means we don't need to explicitly set them to 0.
26229 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
26230 LoadScalarToVector, N->getOperand(2));
26235 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
26236 SDValue V0 = N->getOperand(0);
26237 SDValue V1 = N->getOperand(1);
26239 EVT VT = N->getValueType(0);
26241 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
26242 // operands and changing the mask to 1. This saves us a bunch of
26243 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
26244 // x86InstrInfo knows how to commute this back after instruction selection
26245 // if it would help register allocation.
26247 // TODO: If optimizing for size or a processor that doesn't suffer from
26248 // partial register update stalls, this should be transformed into a MOVSD
26249 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
26251 if (VT == MVT::v2f64)
26252 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
26253 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
26254 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
26255 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
26261 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
26262 // as "sbb reg,reg", since it can be extended without zext and produces
26263 // an all-ones bit which is more useful than 0/1 in some cases.
26264 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
26267 return DAG.getNode(ISD::AND, DL, VT,
26268 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26269 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26271 DAG.getConstant(1, DL, VT));
26272 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
26273 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
26274 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
26275 DAG.getConstant(X86::COND_B, DL, MVT::i8),
26279 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
26280 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
26281 TargetLowering::DAGCombinerInfo &DCI,
26282 const X86Subtarget *Subtarget) {
26284 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
26285 SDValue EFLAGS = N->getOperand(1);
26287 if (CC == X86::COND_A) {
26288 // Try to convert COND_A into COND_B in an attempt to facilitate
26289 // materializing "setb reg".
26291 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
26292 // cannot take an immediate as its first operand.
26294 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
26295 EFLAGS.getValueType().isInteger() &&
26296 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
26297 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
26298 EFLAGS.getNode()->getVTList(),
26299 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
26300 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
26301 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
26305 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
26306 // a zext and produces an all-ones bit which is more useful than 0/1 in some
26308 if (CC == X86::COND_B)
26309 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
26311 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26312 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26313 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
26319 // Optimize branch condition evaluation.
26321 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
26322 TargetLowering::DAGCombinerInfo &DCI,
26323 const X86Subtarget *Subtarget) {
26325 SDValue Chain = N->getOperand(0);
26326 SDValue Dest = N->getOperand(1);
26327 SDValue EFLAGS = N->getOperand(3);
26328 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
26330 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
26331 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
26332 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
26339 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
26340 SelectionDAG &DAG) {
26341 // Take advantage of vector comparisons producing 0 or -1 in each lane to
26342 // optimize away operation when it's from a constant.
26344 // The general transformation is:
26345 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
26346 // AND(VECTOR_CMP(x,y), constant2)
26347 // constant2 = UNARYOP(constant)
26349 // Early exit if this isn't a vector operation, the operand of the
26350 // unary operation isn't a bitwise AND, or if the sizes of the operations
26351 // aren't the same.
26352 EVT VT = N->getValueType(0);
26353 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
26354 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
26355 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
26358 // Now check that the other operand of the AND is a constant. We could
26359 // make the transformation for non-constant splats as well, but it's unclear
26360 // that would be a benefit as it would not eliminate any operations, just
26361 // perform one more step in scalar code before moving to the vector unit.
26362 if (BuildVectorSDNode *BV =
26363 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
26364 // Bail out if the vector isn't a constant.
26365 if (!BV->isConstant())
26368 // Everything checks out. Build up the new and improved node.
26370 EVT IntVT = BV->getValueType(0);
26371 // Create a new constant of the appropriate type for the transformed
26373 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
26374 // The AND node needs bitcasts to/from an integer vector type around it.
26375 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
26376 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
26377 N->getOperand(0)->getOperand(0), MaskConst);
26378 SDValue Res = DAG.getBitcast(VT, NewAnd);
26385 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26386 const X86Subtarget *Subtarget) {
26387 SDValue Op0 = N->getOperand(0);
26388 EVT VT = N->getValueType(0);
26389 EVT InVT = Op0.getValueType();
26390 EVT InSVT = InVT.getScalarType();
26391 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
26393 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
26394 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
26395 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26397 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26398 InVT.getVectorNumElements());
26399 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
26401 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
26402 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
26404 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26410 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
26411 const X86Subtarget *Subtarget) {
26412 // First try to optimize away the conversion entirely when it's
26413 // conditionally from a constant. Vectors only.
26414 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
26417 // Now move on to more general possibilities.
26418 SDValue Op0 = N->getOperand(0);
26419 EVT VT = N->getValueType(0);
26420 EVT InVT = Op0.getValueType();
26421 EVT InSVT = InVT.getScalarType();
26423 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
26424 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
26425 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
26427 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
26428 InVT.getVectorNumElements());
26429 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
26430 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
26433 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
26434 // a 32-bit target where SSE doesn't support i64->FP operations.
26435 if (Op0.getOpcode() == ISD::LOAD) {
26436 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
26437 EVT LdVT = Ld->getValueType(0);
26439 // This transformation is not supported if the result type is f16
26440 if (VT == MVT::f16)
26443 if (!Ld->isVolatile() && !VT.isVector() &&
26444 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
26445 !Subtarget->is64Bit() && LdVT == MVT::i64) {
26446 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
26447 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
26448 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
26455 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
26456 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
26457 X86TargetLowering::DAGCombinerInfo &DCI) {
26458 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
26459 // the result is either zero or one (depending on the input carry bit).
26460 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
26461 if (X86::isZeroNode(N->getOperand(0)) &&
26462 X86::isZeroNode(N->getOperand(1)) &&
26463 // We don't have a good way to replace an EFLAGS use, so only do this when
26465 SDValue(N, 1).use_empty()) {
26467 EVT VT = N->getValueType(0);
26468 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
26469 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
26470 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
26471 DAG.getConstant(X86::COND_B, DL,
26474 DAG.getConstant(1, DL, VT));
26475 return DCI.CombineTo(N, Res1, CarryOut);
26481 // fold (add Y, (sete X, 0)) -> adc 0, Y
26482 // (add Y, (setne X, 0)) -> sbb -1, Y
26483 // (sub (sete X, 0), Y) -> sbb 0, Y
26484 // (sub (setne X, 0), Y) -> adc -1, Y
26485 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
26488 // Look through ZExts.
26489 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
26490 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
26493 SDValue SetCC = Ext.getOperand(0);
26494 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
26497 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
26498 if (CC != X86::COND_E && CC != X86::COND_NE)
26501 SDValue Cmp = SetCC.getOperand(1);
26502 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
26503 !X86::isZeroNode(Cmp.getOperand(1)) ||
26504 !Cmp.getOperand(0).getValueType().isInteger())
26507 SDValue CmpOp0 = Cmp.getOperand(0);
26508 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
26509 DAG.getConstant(1, DL, CmpOp0.getValueType()));
26511 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
26512 if (CC == X86::COND_NE)
26513 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
26514 DL, OtherVal.getValueType(), OtherVal,
26515 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
26517 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
26518 DL, OtherVal.getValueType(), OtherVal,
26519 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
26522 /// PerformADDCombine - Do target-specific dag combines on integer adds.
26523 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
26524 const X86Subtarget *Subtarget) {
26525 EVT VT = N->getValueType(0);
26526 SDValue Op0 = N->getOperand(0);
26527 SDValue Op1 = N->getOperand(1);
26529 // Try to synthesize horizontal adds from adds of shuffles.
26530 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26531 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26532 isHorizontalBinOp(Op0, Op1, true))
26533 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
26535 return OptimizeConditionalInDecrement(N, DAG);
26538 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
26539 const X86Subtarget *Subtarget) {
26540 SDValue Op0 = N->getOperand(0);
26541 SDValue Op1 = N->getOperand(1);
26543 // X86 can't encode an immediate LHS of a sub. See if we can push the
26544 // negation into a preceding instruction.
26545 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
26546 // If the RHS of the sub is a XOR with one use and a constant, invert the
26547 // immediate. Then add one to the LHS of the sub so we can turn
26548 // X-Y -> X+~Y+1, saving one register.
26549 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
26550 isa<ConstantSDNode>(Op1.getOperand(1))) {
26551 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
26552 EVT VT = Op0.getValueType();
26553 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
26555 DAG.getConstant(~XorC, SDLoc(Op1), VT));
26556 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
26557 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
26561 // Try to synthesize horizontal adds from adds of shuffles.
26562 EVT VT = N->getValueType(0);
26563 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
26564 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
26565 isHorizontalBinOp(Op0, Op1, true))
26566 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
26568 return OptimizeConditionalInDecrement(N, DAG);
26571 /// performVZEXTCombine - Performs build vector combines
26572 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
26573 TargetLowering::DAGCombinerInfo &DCI,
26574 const X86Subtarget *Subtarget) {
26576 MVT VT = N->getSimpleValueType(0);
26577 SDValue Op = N->getOperand(0);
26578 MVT OpVT = Op.getSimpleValueType();
26579 MVT OpEltVT = OpVT.getVectorElementType();
26580 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
26582 // (vzext (bitcast (vzext (x)) -> (vzext x)
26584 while (V.getOpcode() == ISD::BITCAST)
26585 V = V.getOperand(0);
26587 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
26588 MVT InnerVT = V.getSimpleValueType();
26589 MVT InnerEltVT = InnerVT.getVectorElementType();
26591 // If the element sizes match exactly, we can just do one larger vzext. This
26592 // is always an exact type match as vzext operates on integer types.
26593 if (OpEltVT == InnerEltVT) {
26594 assert(OpVT == InnerVT && "Types must match for vzext!");
26595 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
26598 // The only other way we can combine them is if only a single element of the
26599 // inner vzext is used in the input to the outer vzext.
26600 if (InnerEltVT.getSizeInBits() < InputBits)
26603 // In this case, the inner vzext is completely dead because we're going to
26604 // only look at bits inside of the low element. Just do the outer vzext on
26605 // a bitcast of the input to the inner.
26606 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
26609 // Check if we can bypass extracting and re-inserting an element of an input
26610 // vector. Essentially:
26611 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
26612 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
26613 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
26614 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
26615 SDValue ExtractedV = V.getOperand(0);
26616 SDValue OrigV = ExtractedV.getOperand(0);
26617 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
26618 if (ExtractIdx->getZExtValue() == 0) {
26619 MVT OrigVT = OrigV.getSimpleValueType();
26620 // Extract a subvector if necessary...
26621 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
26622 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
26623 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
26624 OrigVT.getVectorNumElements() / Ratio);
26625 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
26626 DAG.getIntPtrConstant(0, DL));
26628 Op = DAG.getBitcast(OpVT, OrigV);
26629 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
26636 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
26637 DAGCombinerInfo &DCI) const {
26638 SelectionDAG &DAG = DCI.DAG;
26639 switch (N->getOpcode()) {
26641 case ISD::EXTRACT_VECTOR_ELT:
26642 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
26645 case X86ISD::SHRUNKBLEND:
26646 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
26647 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
26648 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
26649 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
26650 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
26651 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
26652 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
26655 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
26656 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
26657 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
26658 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
26659 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
26660 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
26661 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
26662 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
26663 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
26664 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
26665 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
26666 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
26668 case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
26670 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
26671 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
26672 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
26673 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
26674 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
26675 case ISD::ANY_EXTEND:
26676 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
26677 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
26678 case ISD::SIGN_EXTEND_INREG:
26679 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
26680 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
26681 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
26682 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
26683 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
26684 case X86ISD::SHUFP: // Handle all target specific shuffles
26685 case X86ISD::PALIGNR:
26686 case X86ISD::UNPCKH:
26687 case X86ISD::UNPCKL:
26688 case X86ISD::MOVHLPS:
26689 case X86ISD::MOVLHPS:
26690 case X86ISD::PSHUFB:
26691 case X86ISD::PSHUFD:
26692 case X86ISD::PSHUFHW:
26693 case X86ISD::PSHUFLW:
26694 case X86ISD::MOVSS:
26695 case X86ISD::MOVSD:
26696 case X86ISD::VPERMILPI:
26697 case X86ISD::VPERM2X128:
26698 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
26699 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
26700 case X86ISD::INSERTPS: {
26701 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
26702 return PerformINSERTPSCombine(N, DAG, Subtarget);
26705 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
26711 /// isTypeDesirableForOp - Return true if the target has native support for
26712 /// the specified value type and it is 'desirable' to use the type for the
26713 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
26714 /// instruction encodings are longer and some i16 instructions are slow.
26715 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
26716 if (!isTypeLegal(VT))
26718 if (VT != MVT::i16)
26725 case ISD::SIGN_EXTEND:
26726 case ISD::ZERO_EXTEND:
26727 case ISD::ANY_EXTEND:
26740 /// IsDesirableToPromoteOp - This method query the target whether it is
26741 /// beneficial for dag combiner to promote the specified node. If true, it
26742 /// should return the desired promotion type by reference.
26743 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
26744 EVT VT = Op.getValueType();
26745 if (VT != MVT::i16)
26748 bool Promote = false;
26749 bool Commute = false;
26750 switch (Op.getOpcode()) {
26753 LoadSDNode *LD = cast<LoadSDNode>(Op);
26754 // If the non-extending load has a single use and it's not live out, then it
26755 // might be folded.
26756 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
26757 Op.hasOneUse()*/) {
26758 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
26759 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
26760 // The only case where we'd want to promote LOAD (rather then it being
26761 // promoted as an operand is when it's only use is liveout.
26762 if (UI->getOpcode() != ISD::CopyToReg)
26769 case ISD::SIGN_EXTEND:
26770 case ISD::ZERO_EXTEND:
26771 case ISD::ANY_EXTEND:
26776 SDValue N0 = Op.getOperand(0);
26777 // Look out for (store (shl (load), x)).
26778 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
26791 SDValue N0 = Op.getOperand(0);
26792 SDValue N1 = Op.getOperand(1);
26793 if (!Commute && MayFoldLoad(N1))
26795 // Avoid disabling potential load folding opportunities.
26796 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
26798 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
26808 //===----------------------------------------------------------------------===//
26809 // X86 Inline Assembly Support
26810 //===----------------------------------------------------------------------===//
26812 // Helper to match a string separated by whitespace.
26813 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
26814 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
26816 for (StringRef Piece : Pieces) {
26817 if (!S.startswith(Piece)) // Check if the piece matches.
26820 S = S.substr(Piece.size());
26821 StringRef::size_type Pos = S.find_first_not_of(" \t");
26822 if (Pos == 0) // We matched a prefix.
26831 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
26833 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
26834 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
26835 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
26836 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
26838 if (AsmPieces.size() == 3)
26840 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
26847 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
26848 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
26850 std::string AsmStr = IA->getAsmString();
26852 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
26853 if (!Ty || Ty->getBitWidth() % 16 != 0)
26856 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
26857 SmallVector<StringRef, 4> AsmPieces;
26858 SplitString(AsmStr, AsmPieces, ";\n");
26860 switch (AsmPieces.size()) {
26861 default: return false;
26863 // FIXME: this should verify that we are targeting a 486 or better. If not,
26864 // we will turn this bswap into something that will be lowered to logical
26865 // ops instead of emitting the bswap asm. For now, we don't support 486 or
26866 // lower so don't worry about this.
26868 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
26869 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
26870 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
26871 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
26872 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
26873 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
26874 // No need to check constraints, nothing other than the equivalent of
26875 // "=r,0" would be valid here.
26876 return IntrinsicLowering::LowerToByteSwap(CI);
26879 // rorw $$8, ${0:w} --> llvm.bswap.i16
26880 if (CI->getType()->isIntegerTy(16) &&
26881 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26882 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
26883 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
26885 StringRef ConstraintsStr = IA->getConstraintString();
26886 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26887 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26888 if (clobbersFlagRegisters(AsmPieces))
26889 return IntrinsicLowering::LowerToByteSwap(CI);
26893 if (CI->getType()->isIntegerTy(32) &&
26894 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
26895 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
26896 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
26897 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
26899 StringRef ConstraintsStr = IA->getConstraintString();
26900 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
26901 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
26902 if (clobbersFlagRegisters(AsmPieces))
26903 return IntrinsicLowering::LowerToByteSwap(CI);
26906 if (CI->getType()->isIntegerTy(64)) {
26907 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
26908 if (Constraints.size() >= 2 &&
26909 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
26910 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
26911 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
26912 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
26913 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
26914 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
26915 return IntrinsicLowering::LowerToByteSwap(CI);
26923 /// getConstraintType - Given a constraint letter, return the type of
26924 /// constraint it is for this target.
26925 X86TargetLowering::ConstraintType
26926 X86TargetLowering::getConstraintType(StringRef Constraint) const {
26927 if (Constraint.size() == 1) {
26928 switch (Constraint[0]) {
26939 return C_RegisterClass;
26963 return TargetLowering::getConstraintType(Constraint);
26966 /// Examine constraint type and operand type and determine a weight value.
26967 /// This object must already have been set up with the operand type
26968 /// and the current alternative constraint selected.
26969 TargetLowering::ConstraintWeight
26970 X86TargetLowering::getSingleConstraintMatchWeight(
26971 AsmOperandInfo &info, const char *constraint) const {
26972 ConstraintWeight weight = CW_Invalid;
26973 Value *CallOperandVal = info.CallOperandVal;
26974 // If we don't have a value, we can't do a match,
26975 // but allow it at the lowest weight.
26976 if (!CallOperandVal)
26978 Type *type = CallOperandVal->getType();
26979 // Look at the constraint type.
26980 switch (*constraint) {
26982 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
26993 if (CallOperandVal->getType()->isIntegerTy())
26994 weight = CW_SpecificReg;
26999 if (type->isFloatingPointTy())
27000 weight = CW_SpecificReg;
27003 if (type->isX86_MMXTy() && Subtarget->hasMMX())
27004 weight = CW_SpecificReg;
27008 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
27009 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
27010 weight = CW_Register;
27013 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
27014 if (C->getZExtValue() <= 31)
27015 weight = CW_Constant;
27019 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27020 if (C->getZExtValue() <= 63)
27021 weight = CW_Constant;
27025 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27026 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
27027 weight = CW_Constant;
27031 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27032 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
27033 weight = CW_Constant;
27037 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27038 if (C->getZExtValue() <= 3)
27039 weight = CW_Constant;
27043 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27044 if (C->getZExtValue() <= 0xff)
27045 weight = CW_Constant;
27050 if (isa<ConstantFP>(CallOperandVal)) {
27051 weight = CW_Constant;
27055 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27056 if ((C->getSExtValue() >= -0x80000000LL) &&
27057 (C->getSExtValue() <= 0x7fffffffLL))
27058 weight = CW_Constant;
27062 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
27063 if (C->getZExtValue() <= 0xffffffff)
27064 weight = CW_Constant;
27071 /// LowerXConstraint - try to replace an X constraint, which matches anything,
27072 /// with another that has more specific requirements based on the type of the
27073 /// corresponding operand.
27074 const char *X86TargetLowering::
27075 LowerXConstraint(EVT ConstraintVT) const {
27076 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
27077 // 'f' like normal targets.
27078 if (ConstraintVT.isFloatingPoint()) {
27079 if (Subtarget->hasSSE2())
27081 if (Subtarget->hasSSE1())
27085 return TargetLowering::LowerXConstraint(ConstraintVT);
27088 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
27089 /// vector. If it is invalid, don't add anything to Ops.
27090 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
27091 std::string &Constraint,
27092 std::vector<SDValue>&Ops,
27093 SelectionDAG &DAG) const {
27096 // Only support length 1 constraints for now.
27097 if (Constraint.length() > 1) return;
27099 char ConstraintLetter = Constraint[0];
27100 switch (ConstraintLetter) {
27103 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27104 if (C->getZExtValue() <= 31) {
27105 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27106 Op.getValueType());
27112 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27113 if (C->getZExtValue() <= 63) {
27114 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27115 Op.getValueType());
27121 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27122 if (isInt<8>(C->getSExtValue())) {
27123 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27124 Op.getValueType());
27130 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27131 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
27132 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
27133 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
27134 Op.getValueType());
27140 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27141 if (C->getZExtValue() <= 3) {
27142 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27143 Op.getValueType());
27149 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27150 if (C->getZExtValue() <= 255) {
27151 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27152 Op.getValueType());
27158 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27159 if (C->getZExtValue() <= 127) {
27160 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27161 Op.getValueType());
27167 // 32-bit signed value
27168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27169 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27170 C->getSExtValue())) {
27171 // Widen to 64 bits here to get it sign extended.
27172 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
27175 // FIXME gcc accepts some relocatable values here too, but only in certain
27176 // memory models; it's complicated.
27181 // 32-bit unsigned value
27182 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
27183 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
27184 C->getZExtValue())) {
27185 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
27186 Op.getValueType());
27190 // FIXME gcc accepts some relocatable values here too, but only in certain
27191 // memory models; it's complicated.
27195 // Literal immediates are always ok.
27196 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
27197 // Widen to 64 bits here to get it sign extended.
27198 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
27202 // In any sort of PIC mode addresses need to be computed at runtime by
27203 // adding in a register or some sort of table lookup. These can't
27204 // be used as immediates.
27205 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
27208 // If we are in non-pic codegen mode, we allow the address of a global (with
27209 // an optional displacement) to be used with 'i'.
27210 GlobalAddressSDNode *GA = nullptr;
27211 int64_t Offset = 0;
27213 // Match either (GA), (GA+C), (GA+C1+C2), etc.
27215 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
27216 Offset += GA->getOffset();
27218 } else if (Op.getOpcode() == ISD::ADD) {
27219 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27220 Offset += C->getZExtValue();
27221 Op = Op.getOperand(0);
27224 } else if (Op.getOpcode() == ISD::SUB) {
27225 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
27226 Offset += -C->getZExtValue();
27227 Op = Op.getOperand(0);
27232 // Otherwise, this isn't something we can handle, reject it.
27236 const GlobalValue *GV = GA->getGlobal();
27237 // If we require an extra load to get this address, as in PIC mode, we
27238 // can't accept it.
27239 if (isGlobalStubReference(
27240 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
27243 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
27244 GA->getValueType(0), Offset);
27249 if (Result.getNode()) {
27250 Ops.push_back(Result);
27253 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
27256 std::pair<unsigned, const TargetRegisterClass *>
27257 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
27258 StringRef Constraint,
27260 // First, see if this is a constraint that directly corresponds to an LLVM
27262 if (Constraint.size() == 1) {
27263 // GCC Constraint Letters
27264 switch (Constraint[0]) {
27266 // TODO: Slight differences here in allocation order and leaving
27267 // RIP in the class. Do they matter any more here than they do
27268 // in the normal allocation?
27269 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
27270 if (Subtarget->is64Bit()) {
27271 if (VT == MVT::i32 || VT == MVT::f32)
27272 return std::make_pair(0U, &X86::GR32RegClass);
27273 if (VT == MVT::i16)
27274 return std::make_pair(0U, &X86::GR16RegClass);
27275 if (VT == MVT::i8 || VT == MVT::i1)
27276 return std::make_pair(0U, &X86::GR8RegClass);
27277 if (VT == MVT::i64 || VT == MVT::f64)
27278 return std::make_pair(0U, &X86::GR64RegClass);
27281 // 32-bit fallthrough
27282 case 'Q': // Q_REGS
27283 if (VT == MVT::i32 || VT == MVT::f32)
27284 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
27285 if (VT == MVT::i16)
27286 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
27287 if (VT == MVT::i8 || VT == MVT::i1)
27288 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
27289 if (VT == MVT::i64)
27290 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
27292 case 'r': // GENERAL_REGS
27293 case 'l': // INDEX_REGS
27294 if (VT == MVT::i8 || VT == MVT::i1)
27295 return std::make_pair(0U, &X86::GR8RegClass);
27296 if (VT == MVT::i16)
27297 return std::make_pair(0U, &X86::GR16RegClass);
27298 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
27299 return std::make_pair(0U, &X86::GR32RegClass);
27300 return std::make_pair(0U, &X86::GR64RegClass);
27301 case 'R': // LEGACY_REGS
27302 if (VT == MVT::i8 || VT == MVT::i1)
27303 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
27304 if (VT == MVT::i16)
27305 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
27306 if (VT == MVT::i32 || !Subtarget->is64Bit())
27307 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
27308 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
27309 case 'f': // FP Stack registers.
27310 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
27311 // value to the correct fpstack register class.
27312 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
27313 return std::make_pair(0U, &X86::RFP32RegClass);
27314 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
27315 return std::make_pair(0U, &X86::RFP64RegClass);
27316 return std::make_pair(0U, &X86::RFP80RegClass);
27317 case 'y': // MMX_REGS if MMX allowed.
27318 if (!Subtarget->hasMMX()) break;
27319 return std::make_pair(0U, &X86::VR64RegClass);
27320 case 'Y': // SSE_REGS if SSE2 allowed
27321 if (!Subtarget->hasSSE2()) break;
27323 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
27324 if (!Subtarget->hasSSE1()) break;
27326 switch (VT.SimpleTy) {
27328 // Scalar SSE types.
27331 return std::make_pair(0U, &X86::FR32RegClass);
27334 return std::make_pair(0U, &X86::FR64RegClass);
27342 return std::make_pair(0U, &X86::VR128RegClass);
27350 return std::make_pair(0U, &X86::VR256RegClass);
27355 return std::make_pair(0U, &X86::VR512RegClass);
27361 // Use the default implementation in TargetLowering to convert the register
27362 // constraint into a member of a register class.
27363 std::pair<unsigned, const TargetRegisterClass*> Res;
27364 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
27366 // Not found as a standard register?
27368 // Map st(0) -> st(7) -> ST0
27369 if (Constraint.size() == 7 && Constraint[0] == '{' &&
27370 tolower(Constraint[1]) == 's' &&
27371 tolower(Constraint[2]) == 't' &&
27372 Constraint[3] == '(' &&
27373 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
27374 Constraint[5] == ')' &&
27375 Constraint[6] == '}') {
27377 Res.first = X86::FP0+Constraint[4]-'0';
27378 Res.second = &X86::RFP80RegClass;
27382 // GCC allows "st(0)" to be called just plain "st".
27383 if (StringRef("{st}").equals_lower(Constraint)) {
27384 Res.first = X86::FP0;
27385 Res.second = &X86::RFP80RegClass;
27390 if (StringRef("{flags}").equals_lower(Constraint)) {
27391 Res.first = X86::EFLAGS;
27392 Res.second = &X86::CCRRegClass;
27396 // 'A' means EAX + EDX.
27397 if (Constraint == "A") {
27398 Res.first = X86::EAX;
27399 Res.second = &X86::GR32_ADRegClass;
27405 // Otherwise, check to see if this is a register class of the wrong value
27406 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
27407 // turn into {ax},{dx}.
27408 // MVT::Other is used to specify clobber names.
27409 if (Res.second->hasType(VT) || VT == MVT::Other)
27410 return Res; // Correct type already, nothing to do.
27412 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
27413 // return "eax". This should even work for things like getting 64bit integer
27414 // registers when given an f64 type.
27415 const TargetRegisterClass *Class = Res.second;
27416 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
27417 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
27418 unsigned Size = VT.getSizeInBits();
27419 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
27420 : Size == 16 ? MVT::i16
27421 : Size == 32 ? MVT::i32
27422 : Size == 64 ? MVT::i64
27424 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
27426 Res.first = DestReg;
27427 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
27428 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
27429 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
27430 : &X86::GR64RegClass;
27431 assert(Res.second->contains(Res.first) && "Register in register class");
27433 // No register found/type mismatch.
27435 Res.second = nullptr;
27437 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
27438 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
27439 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
27440 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
27441 Class == &X86::VR512RegClass) {
27442 // Handle references to XMM physical registers that got mapped into the
27443 // wrong class. This can happen with constraints like {xmm0} where the
27444 // target independent register mapper will just pick the first match it can
27445 // find, ignoring the required type.
27447 if (VT == MVT::f32 || VT == MVT::i32)
27448 Res.second = &X86::FR32RegClass;
27449 else if (VT == MVT::f64 || VT == MVT::i64)
27450 Res.second = &X86::FR64RegClass;
27451 else if (X86::VR128RegClass.hasType(VT))
27452 Res.second = &X86::VR128RegClass;
27453 else if (X86::VR256RegClass.hasType(VT))
27454 Res.second = &X86::VR256RegClass;
27455 else if (X86::VR512RegClass.hasType(VT))
27456 Res.second = &X86::VR512RegClass;
27458 // Type mismatch and not a clobber: Return an error;
27460 Res.second = nullptr;
27467 int X86TargetLowering::getScalingFactorCost(const DataLayout &DL,
27468 const AddrMode &AM, Type *Ty,
27469 unsigned AS) const {
27470 // Scaling factors are not free at all.
27471 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
27472 // will take 2 allocations in the out of order engine instead of 1
27473 // for plain addressing mode, i.e. inst (reg1).
27475 // vaddps (%rsi,%drx), %ymm0, %ymm1
27476 // Requires two allocations (one for the load, one for the computation)
27478 // vaddps (%rsi), %ymm0, %ymm1
27479 // Requires just 1 allocation, i.e., freeing allocations for other operations
27480 // and having less micro operations to execute.
27482 // For some X86 architectures, this is even worse because for instance for
27483 // stores, the complex addressing mode forces the instruction to use the
27484 // "load" ports instead of the dedicated "store" port.
27485 // E.g., on Haswell:
27486 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
27487 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
27488 if (isLegalAddressingMode(DL, AM, Ty, AS))
27489 // Scale represents reg2 * scale, thus account for 1
27490 // as soon as we use a second register.
27491 return AM.Scale != 0;
27495 bool X86TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
27496 // Integer division on x86 is expensive. However, when aggressively optimizing
27497 // for code size, we prefer to use a div instruction, as it is usually smaller
27498 // than the alternative sequence.
27499 // The exception to this is vector division. Since x86 doesn't have vector
27500 // integer division, leaving the division as-is is a loss even in terms of
27501 // size, because it will have to be scalarized, while the alternative code
27502 // sequence can be performed in vector form.
27503 bool OptSize = Attr.hasAttribute(AttributeSet::FunctionIndex,
27504 Attribute::MinSize);
27505 return OptSize && !VT.isVector();