1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 // Forward declarations.
71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
74 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
75 const X86Subtarget &STI)
76 : TargetLowering(TM), Subtarget(&STI) {
77 X86ScalarSSEf64 = Subtarget->hasSSE2();
78 X86ScalarSSEf32 = Subtarget->hasSSE1();
81 // Set up the TargetLowering object.
82 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
84 // X86 is weird. It always uses i8 for shift amounts and setcc results.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // For 64-bit, since we have so many registers, use the ILP scheduler.
90 // For 32-bit, use the register pressure specific scheduling.
91 // For Atom, always use ILP scheduling.
92 if (Subtarget->isAtom())
93 setSchedulingPreference(Sched::ILP);
94 else if (Subtarget->is64Bit())
95 setSchedulingPreference(Sched::ILP);
97 setSchedulingPreference(Sched::RegPressure);
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
99 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
101 // Bypass expensive divides on Atom when compiling with O2.
102 if (TM.getOptLevel() >= CodeGenOpt::Default) {
103 if (Subtarget->hasSlowDivide32())
104 addBypassSlowDiv(32, 8);
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
106 addBypassSlowDiv(64, 16);
109 if (Subtarget->isTargetKnownWindowsMSVC()) {
110 // Setup Windows compiler runtime calls.
111 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
112 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
113 setLibcallName(RTLIB::SREM_I64, "_allrem");
114 setLibcallName(RTLIB::UREM_I64, "_aullrem");
115 setLibcallName(RTLIB::MUL_I64, "_allmul");
116 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
118 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
119 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
120 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
122 // The _ftol2 runtime function has an unusual calling conv, which
123 // is modeled by a special pseudo-instruction.
124 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
125 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
126 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
127 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
130 if (Subtarget->isTargetDarwin()) {
131 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(false);
133 setUseUnderscoreLongJmp(false);
134 } else if (Subtarget->isTargetWindowsGNU()) {
135 // MS runtime is weird: it exports _setjmp, but longjmp!
136 setUseUnderscoreSetJmp(true);
137 setUseUnderscoreLongJmp(false);
139 setUseUnderscoreSetJmp(true);
140 setUseUnderscoreLongJmp(true);
143 // Set up the register classes.
144 addRegisterClass(MVT::i8, &X86::GR8RegClass);
145 addRegisterClass(MVT::i16, &X86::GR16RegClass);
146 addRegisterClass(MVT::i32, &X86::GR32RegClass);
147 if (Subtarget->is64Bit())
148 addRegisterClass(MVT::i64, &X86::GR64RegClass);
150 for (MVT VT : MVT::integer_valuetypes())
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
153 // We don't accept any truncstore of integer registers.
154 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
155 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
156 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
157 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
159 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163 // SETOEQ and SETUNE require checking two conditions.
164 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
165 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
166 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
171 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
177 if (Subtarget->is64Bit()) {
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 } else if (!Subtarget->useSoftFloat()) {
181 // We have an algorithm for SSE2->double, and we turn this into a
182 // 64-bit FILD followed by conditional FADD for other targets.
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
184 // We have an algorithm for SSE2, and we turn this into a 64-bit
185 // FILD for other targets.
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
189 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
191 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
194 if (!Subtarget->useSoftFloat()) {
195 // SSE has no i16 to fp conversion, only i32
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
206 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
216 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
219 if (X86ScalarSSEf32) {
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
221 // f32 and f64 cases are Legal, f80 case is not
222 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
237 } else if (!Subtarget->useSoftFloat()) {
238 // Since AVX is a superset of SSE3, only check for SSE here.
239 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
240 // Expand FP_TO_UINT into a select.
241 // FIXME: We would like to use a Custom expander here eventually to do
242 // the optimal thing for SSE vs. the default expansion in the legalizer.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
250 if (isTargetFTOL()) {
251 // Use the _ftol2 runtime function, which has a pseudo-instruction
252 // to handle its weird calling convention.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
256 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
257 if (!X86ScalarSSEf64) {
258 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
259 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
262 // Without SSE, i64->f64 goes through memory.
263 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
267 // Scalar integer divide and remainder are lowered to use operations that
268 // produce two results, to match the available instructions. This exposes
269 // the two-result form to trivial CSE, which is able to combine x/y and x%y
270 // into a single instruction.
272 // Scalar integer multiply-high is also lowered to use two-result
273 // operations, to match the available instructions. However, plain multiply
274 // (low) operations are left as Legal, as there are single-result
275 // instructions for this in x86. Using the two-result multiply instructions
276 // when both high and low results are needed must be arranged by dagcombine.
277 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
279 setOperationAction(ISD::MULHS, VT, Expand);
280 setOperationAction(ISD::MULHU, VT, Expand);
281 setOperationAction(ISD::SDIV, VT, Expand);
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SREM, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
286 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
287 setOperationAction(ISD::ADDC, VT, Custom);
288 setOperationAction(ISD::ADDE, VT, Custom);
289 setOperationAction(ISD::SUBC, VT, Custom);
290 setOperationAction(ISD::SUBE, VT, Custom);
293 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
294 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
295 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
309 if (Subtarget->is64Bit())
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
314 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
316 setOperationAction(ISD::FREM , MVT::f64 , Expand);
317 setOperationAction(ISD::FREM , MVT::f80 , Expand);
318 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
320 // Promote the i8 variants and force them on up to i32 which has a shorter
322 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
323 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
326 if (Subtarget->hasBMI()) {
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
332 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
333 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
334 if (Subtarget->is64Bit())
335 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
338 if (Subtarget->hasLZCNT()) {
339 // When promoting the i8 variants, force them to i32 for a shorter
341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
356 if (Subtarget->is64Bit()) {
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
362 // Special handling for half-precision floating point conversions.
363 // If we don't have F16C support, then lower half float conversions
364 // into library calls.
365 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
366 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
370 // There's never any support for operations beyond MVT::f32.
371 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
372 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
379 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
380 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
383 if (Subtarget->hasPOPCNT()) {
384 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
386 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
387 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
388 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
393 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
395 if (!Subtarget->hasMOVBE())
396 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
398 // These should be promoted to a larger select which is supported.
399 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
400 // X86 wants to expand cmov itself.
401 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
402 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
403 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
404 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
405 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
407 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
408 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
410 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
411 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
417 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
418 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
419 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
420 // support continuation, user-level threading, and etc.. As a result, no
421 // other SjLj exception interfaces are implemented and please don't build
422 // your own exception handling based on them.
423 // LLVM/Clang supports zero-cost DWARF exception handling.
424 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
425 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasSSE1())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // Expand certain atomics
459 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
461 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
462 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
463 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
466 if (Subtarget->hasCmpxchg16b()) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
470 // FIXME - use subtarget debug flags
471 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
472 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
473 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
476 if (Subtarget->is64Bit()) {
477 setExceptionPointerRegister(X86::RAX);
478 setExceptionSelectorRegister(X86::RDX);
480 setExceptionPointerRegister(X86::EAX);
481 setExceptionSelectorRegister(X86::EDX);
483 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
484 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
486 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
487 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::TRAP, MVT::Other, Legal);
490 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
492 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
493 setOperationAction(ISD::VASTART , MVT::Other, Custom);
494 setOperationAction(ISD::VAEND , MVT::Other, Expand);
495 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
496 // TargetInfo::X86_64ABIBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Custom);
498 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
500 // TargetInfo::CharPtrBuiltinVaList
501 setOperationAction(ISD::VAARG , MVT::Other, Expand);
502 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
505 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
506 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
508 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
510 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
511 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
512 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
514 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
515 // f32 and f64 use SSE.
516 // Set up the FP register classes.
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::FR64RegClass);
520 // Use ANDPD to simulate FABS.
521 setOperationAction(ISD::FABS , MVT::f64, Custom);
522 setOperationAction(ISD::FABS , MVT::f32, Custom);
524 // Use XORP to simulate FNEG.
525 setOperationAction(ISD::FNEG , MVT::f64, Custom);
526 setOperationAction(ISD::FNEG , MVT::f32, Custom);
528 // Use ANDPD and ORPD to simulate FCOPYSIGN.
529 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
530 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
532 // Lower this to FGETSIGNx86 plus an AND.
533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
536 // We don't support sin/cos/fmod
537 setOperationAction(ISD::FSIN , MVT::f64, Expand);
538 setOperationAction(ISD::FCOS , MVT::f64, Expand);
539 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
540 setOperationAction(ISD::FSIN , MVT::f32, Expand);
541 setOperationAction(ISD::FCOS , MVT::f32, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
544 // Expand FP immediates into loads from the stack, except for the special
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578 if (!TM.Options.UnsafeFPMath) {
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (!Subtarget->useSoftFloat()) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
589 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
590 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
594 if (!TM.Options.UnsafeFPMath) {
595 setOperationAction(ISD::FSIN , MVT::f64, Expand);
596 setOperationAction(ISD::FSIN , MVT::f32, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FCOS , MVT::f32, Expand);
599 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
602 addLegalFPImmediate(APFloat(+0.0)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
612 // We don't support FMA.
613 setOperationAction(ISD::FMA, MVT::f64, Expand);
614 setOperationAction(ISD::FMA, MVT::f32, Expand);
616 // Long double always uses X87.
617 if (!Subtarget->useSoftFloat()) {
618 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
619 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
622 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
623 addLegalFPImmediate(TmpFlt); // FLD0
625 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
628 APFloat TmpFlt2(+1.0);
629 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
631 addLegalFPImmediate(TmpFlt2); // FLD1
632 TmpFlt2.changeSign();
633 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
636 if (!TM.Options.UnsafeFPMath) {
637 setOperationAction(ISD::FSIN , MVT::f80, Expand);
638 setOperationAction(ISD::FCOS , MVT::f80, Expand);
639 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
642 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
643 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
644 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
645 setOperationAction(ISD::FRINT, MVT::f80, Expand);
646 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
647 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 // Always use a library call for pow.
651 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
652 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
655 setOperationAction(ISD::FLOG, MVT::f80, Expand);
656 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
658 setOperationAction(ISD::FEXP, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
661 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
663 // First set operation action for all vector types to either promote
664 // (for widening) or expand (for scalarization). Then we will selectively
665 // turn on ones that can be effectively codegen'd.
666 for (MVT VT : MVT::vector_valuetypes()) {
667 setOperationAction(ISD::ADD , VT, Expand);
668 setOperationAction(ISD::SUB , VT, Expand);
669 setOperationAction(ISD::FADD, VT, Expand);
670 setOperationAction(ISD::FNEG, VT, Expand);
671 setOperationAction(ISD::FSUB, VT, Expand);
672 setOperationAction(ISD::MUL , VT, Expand);
673 setOperationAction(ISD::FMUL, VT, Expand);
674 setOperationAction(ISD::SDIV, VT, Expand);
675 setOperationAction(ISD::UDIV, VT, Expand);
676 setOperationAction(ISD::FDIV, VT, Expand);
677 setOperationAction(ISD::SREM, VT, Expand);
678 setOperationAction(ISD::UREM, VT, Expand);
679 setOperationAction(ISD::LOAD, VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::FABS, VT, Expand);
686 setOperationAction(ISD::FSIN, VT, Expand);
687 setOperationAction(ISD::FSINCOS, VT, Expand);
688 setOperationAction(ISD::FCOS, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FREM, VT, Expand);
691 setOperationAction(ISD::FMA, VT, Expand);
692 setOperationAction(ISD::FPOWI, VT, Expand);
693 setOperationAction(ISD::FSQRT, VT, Expand);
694 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::FPOW, VT, Expand);
707 setOperationAction(ISD::CTPOP, VT, Expand);
708 setOperationAction(ISD::CTTZ, VT, Expand);
709 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
710 setOperationAction(ISD::CTLZ, VT, Expand);
711 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::SHL, VT, Expand);
713 setOperationAction(ISD::SRA, VT, Expand);
714 setOperationAction(ISD::SRL, VT, Expand);
715 setOperationAction(ISD::ROTL, VT, Expand);
716 setOperationAction(ISD::ROTR, VT, Expand);
717 setOperationAction(ISD::BSWAP, VT, Expand);
718 setOperationAction(ISD::SETCC, VT, Expand);
719 setOperationAction(ISD::FLOG, VT, Expand);
720 setOperationAction(ISD::FLOG2, VT, Expand);
721 setOperationAction(ISD::FLOG10, VT, Expand);
722 setOperationAction(ISD::FEXP, VT, Expand);
723 setOperationAction(ISD::FEXP2, VT, Expand);
724 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
725 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
727 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
729 setOperationAction(ISD::TRUNCATE, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
731 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
732 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
733 setOperationAction(ISD::VSELECT, VT, Expand);
734 setOperationAction(ISD::SELECT_CC, VT, Expand);
735 for (MVT InnerVT : MVT::vector_valuetypes()) {
736 setTruncStoreAction(InnerVT, VT, Expand);
738 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
741 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
742 // types, we have to deal with them whether we ask for Expansion or not.
743 // Setting Expand causes its own optimisation problems though, so leave
745 if (VT.getVectorElementType() == MVT::i1)
746 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
748 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
749 // split/scalarized right now.
750 if (VT.getVectorElementType() == MVT::f16)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
756 // with -msoft-float, disable use of MMX as well.
757 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
758 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
759 // No operations on x86mmx supported, everything uses intrinsics.
762 // MMX-sized vectors (other than x86mmx) are expected to be expanded
763 // into smaller operations.
764 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
765 setOperationAction(ISD::MULHS, MMXTy, Expand);
766 setOperationAction(ISD::AND, MMXTy, Expand);
767 setOperationAction(ISD::OR, MMXTy, Expand);
768 setOperationAction(ISD::XOR, MMXTy, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
770 setOperationAction(ISD::SELECT, MMXTy, Expand);
771 setOperationAction(ISD::BITCAST, MMXTy, Expand);
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
775 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
776 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
788 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
795 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
797 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
798 // registers cannot be used even for integer operations.
799 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
800 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
801 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
802 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
804 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
805 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
806 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
807 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
808 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
809 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
812 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
814 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
816 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
818 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
819 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
826 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
828 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
829 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
830 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
831 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
833 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
834 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
835 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
836 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
837 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
839 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
840 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
841 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
842 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
844 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
845 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
846 MVT VT = (MVT::SimpleValueType)i;
847 // Do not attempt to custom lower non-power-of-2 vectors
848 if (!isPowerOf2_32(VT.getVectorNumElements()))
850 // Do not attempt to custom lower non-128-bit vectors
851 if (!VT.is128BitVector())
853 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
854 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
855 setOperationAction(ISD::VSELECT, VT, Custom);
856 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
859 // We support custom legalizing of sext and anyext loads for specific
860 // memory vector types which we can load as a scalar (or sequence of
861 // scalars) and extend in-register to a legal 128-bit vector type. For sext
862 // loads these must work with a single scalar load.
863 for (MVT VT : MVT::integer_vector_valuetypes()) {
864 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
865 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
866 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
867 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
868 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
869 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
870 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
871 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
875 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
876 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
878 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
879 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
880 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
881 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
882 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
884 if (Subtarget->is64Bit()) {
885 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
886 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
889 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
890 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
891 MVT VT = (MVT::SimpleValueType)i;
893 // Do not attempt to promote non-128-bit vectors
894 if (!VT.is128BitVector())
897 setOperationAction(ISD::AND, VT, Promote);
898 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
899 setOperationAction(ISD::OR, VT, Promote);
900 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
901 setOperationAction(ISD::XOR, VT, Promote);
902 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
903 setOperationAction(ISD::LOAD, VT, Promote);
904 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
905 setOperationAction(ISD::SELECT, VT, Promote);
906 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
909 // Custom lower v2i64 and v2f64 selects.
910 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
911 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
912 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
913 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
915 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
916 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
918 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
920 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
921 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
922 // As there is no 64-bit GPR available, we need build a special custom
923 // sequence to convert from v2i32 to v2f32.
924 if (!Subtarget->is64Bit())
925 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
927 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
928 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
930 for (MVT VT : MVT::fp_vector_valuetypes())
931 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
933 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
934 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
935 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
938 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
939 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
940 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
941 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
942 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
943 setOperationAction(ISD::FRINT, RoundedTy, Legal);
944 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
947 // FIXME: Do we need to handle scalar-to-vector here?
948 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
950 // We directly match byte blends in the backend as they match the VSELECT
952 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
954 // SSE41 brings specific instructions for doing vector sign extend even in
955 // cases where we don't have SRA.
956 for (MVT VT : MVT::integer_vector_valuetypes()) {
957 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
958 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
959 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
962 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
963 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
964 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
965 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
966 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
967 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
968 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
970 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
971 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
972 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
973 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
974 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
975 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
977 // i8 and i16 vectors are custom because the source register and source
978 // source memory operand types are not the same width. f32 vectors are
979 // custom since the immediate controlling the insert encodes additional
981 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
982 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
983 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
984 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
986 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
987 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
988 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
989 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
991 // FIXME: these should be Legal, but that's only for the case where
992 // the index is constant. For now custom expand to deal with that.
993 if (Subtarget->is64Bit()) {
994 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
995 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
999 if (Subtarget->hasSSE2()) {
1000 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1001 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1002 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1004 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1005 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1007 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1008 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1010 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1011 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1013 // In the customized shift lowering, the legal cases in AVX2 will be
1015 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1016 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1018 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1019 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1021 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1024 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1025 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1026 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1027 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1028 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1029 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1030 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1032 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1033 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1034 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1036 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1037 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1038 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1039 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1040 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1041 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1042 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1043 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1044 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1045 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1046 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1047 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1049 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1050 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1051 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1052 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1053 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1054 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1055 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1056 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1057 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1058 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1059 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1060 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1062 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1063 // even though v8i16 is a legal type.
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1065 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1066 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1068 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1069 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1070 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1072 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1073 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1075 for (MVT VT : MVT::fp_vector_valuetypes())
1076 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1078 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1079 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1081 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1082 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1084 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1085 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1087 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1088 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1089 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1090 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1092 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1093 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1094 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1096 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1097 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1098 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1099 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1100 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1101 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1102 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1103 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1104 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1105 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1106 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1107 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1109 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1110 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1111 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1112 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1114 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1115 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1116 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1117 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1118 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1119 setOperationAction(ISD::FMA, MVT::f32, Legal);
1120 setOperationAction(ISD::FMA, MVT::f64, Legal);
1123 if (Subtarget->hasInt256()) {
1124 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1125 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1126 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1127 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1129 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1130 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1131 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1132 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1134 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1135 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1136 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1137 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1139 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1140 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1141 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1142 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1144 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1145 // when we have a 256bit-wide blend with immediate.
1146 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1148 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1149 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1150 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1151 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1152 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1153 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1154 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1156 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1157 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1158 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1159 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1160 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1161 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1163 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1164 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1165 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1166 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1168 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1169 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1170 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1171 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1173 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1174 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1175 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1176 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1179 // In the customized shift lowering, the legal cases in AVX2 will be
1181 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1182 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1184 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1185 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1187 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1189 // Custom lower several nodes for 256-bit types.
1190 for (MVT VT : MVT::vector_valuetypes()) {
1191 if (VT.getScalarSizeInBits() >= 32) {
1192 setOperationAction(ISD::MLOAD, VT, Legal);
1193 setOperationAction(ISD::MSTORE, VT, Legal);
1195 // Extract subvector is special because the value type
1196 // (result) is 128-bit but the source is 256-bit wide.
1197 if (VT.is128BitVector()) {
1198 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1200 // Do not attempt to custom lower other non-256-bit vectors
1201 if (!VT.is256BitVector())
1204 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1205 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1206 setOperationAction(ISD::VSELECT, VT, Custom);
1207 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1208 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1209 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1210 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1211 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1214 if (Subtarget->hasInt256())
1215 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1218 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1219 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1220 MVT VT = (MVT::SimpleValueType)i;
1222 // Do not attempt to promote non-256-bit vectors
1223 if (!VT.is256BitVector())
1226 setOperationAction(ISD::AND, VT, Promote);
1227 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1228 setOperationAction(ISD::OR, VT, Promote);
1229 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1230 setOperationAction(ISD::XOR, VT, Promote);
1231 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1232 setOperationAction(ISD::LOAD, VT, Promote);
1233 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1234 setOperationAction(ISD::SELECT, VT, Promote);
1235 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1239 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1240 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1241 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1242 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1243 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1245 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1246 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1247 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1249 for (MVT VT : MVT::fp_vector_valuetypes())
1250 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1252 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1253 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1254 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1255 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1256 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1257 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1258 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1259 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1260 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1261 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1262 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1263 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1265 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1266 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1267 setOperationAction(ISD::XOR, MVT::i1, Legal);
1268 setOperationAction(ISD::OR, MVT::i1, Legal);
1269 setOperationAction(ISD::AND, MVT::i1, Legal);
1270 setOperationAction(ISD::SUB, MVT::i1, Custom);
1271 setOperationAction(ISD::ADD, MVT::i1, Custom);
1272 setOperationAction(ISD::MUL, MVT::i1, Custom);
1273 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1274 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1275 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1276 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1277 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1279 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1280 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1281 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1282 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1283 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1284 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1286 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1287 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1288 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1289 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1290 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1291 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1292 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1293 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1295 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1296 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1297 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1298 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1299 if (Subtarget->is64Bit()) {
1300 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1301 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1302 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1303 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1305 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1306 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1307 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1308 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1309 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1310 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1311 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1312 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1313 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1314 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1315 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1316 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1317 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1318 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1319 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1320 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1322 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1323 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1324 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1325 if (Subtarget->hasDQI()) {
1326 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1327 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1329 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1330 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1331 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1332 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1333 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1334 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1335 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1336 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1337 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1338 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1339 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1340 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1341 if (Subtarget->hasDQI()) {
1342 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1343 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1345 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1346 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1347 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1348 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1349 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1350 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1351 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1352 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1353 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1354 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1356 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1357 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1358 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1359 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1360 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1362 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1363 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1365 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1367 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1368 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1369 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1370 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1371 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1372 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1373 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1374 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1375 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1376 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1377 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1379 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1380 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1382 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1383 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1385 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1387 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1388 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1390 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1391 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1393 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1394 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1396 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1397 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1398 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1399 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1400 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1401 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1403 if (Subtarget->hasCDI()) {
1404 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1405 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1407 if (Subtarget->hasDQI()) {
1408 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1409 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1410 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1412 // Custom lower several nodes.
1413 for (MVT VT : MVT::vector_valuetypes()) {
1414 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1416 setOperationAction(ISD::AND, VT, Legal);
1417 setOperationAction(ISD::OR, VT, Legal);
1418 setOperationAction(ISD::XOR, VT, Legal);
1420 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1421 setOperationAction(ISD::MGATHER, VT, Custom);
1422 setOperationAction(ISD::MSCATTER, VT, Custom);
1424 // Extract subvector is special because the value type
1425 // (result) is 256/128-bit but the source is 512-bit wide.
1426 if (VT.is128BitVector() || VT.is256BitVector()) {
1427 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1429 if (VT.getVectorElementType() == MVT::i1)
1430 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1432 // Do not attempt to custom lower other non-512-bit vectors
1433 if (!VT.is512BitVector())
1436 if (EltSize >= 32) {
1437 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1438 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1439 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1440 setOperationAction(ISD::VSELECT, VT, Legal);
1441 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1442 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1443 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1444 setOperationAction(ISD::MLOAD, VT, Legal);
1445 setOperationAction(ISD::MSTORE, VT, Legal);
1448 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1449 MVT VT = (MVT::SimpleValueType)i;
1451 // Do not attempt to promote non-512-bit vectors.
1452 if (!VT.is512BitVector())
1455 setOperationAction(ISD::SELECT, VT, Promote);
1456 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1460 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1461 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1462 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1464 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1465 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1467 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1468 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1469 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1470 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1471 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1472 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1473 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1474 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1475 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1476 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1477 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1478 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1479 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1480 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1481 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1482 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1483 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1484 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1485 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1486 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1487 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1488 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1489 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1490 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1491 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1492 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1493 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1495 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1496 const MVT VT = (MVT::SimpleValueType)i;
1498 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1500 // Do not attempt to promote non-512-bit vectors.
1501 if (!VT.is512BitVector())
1505 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1506 setOperationAction(ISD::VSELECT, VT, Legal);
1511 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1512 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1513 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1515 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1516 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1517 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1518 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1519 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1520 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1521 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1522 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1524 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1526 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1527 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1528 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1529 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1530 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1531 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1532 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1533 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1536 // We want to custom lower some of our intrinsics.
1537 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1538 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1539 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1540 if (!Subtarget->is64Bit())
1541 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1543 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1544 // handle type legalization for these operations here.
1546 // FIXME: We really should do custom legalization for addition and
1547 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1548 // than generic legalization for 64-bit multiplication-with-overflow, though.
1549 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1550 // Add/Sub/Mul with overflow operations are custom lowered.
1552 setOperationAction(ISD::SADDO, VT, Custom);
1553 setOperationAction(ISD::UADDO, VT, Custom);
1554 setOperationAction(ISD::SSUBO, VT, Custom);
1555 setOperationAction(ISD::USUBO, VT, Custom);
1556 setOperationAction(ISD::SMULO, VT, Custom);
1557 setOperationAction(ISD::UMULO, VT, Custom);
1561 if (!Subtarget->is64Bit()) {
1562 // These libcalls are not available in 32-bit.
1563 setLibcallName(RTLIB::SHL_I128, nullptr);
1564 setLibcallName(RTLIB::SRL_I128, nullptr);
1565 setLibcallName(RTLIB::SRA_I128, nullptr);
1568 // Combine sin / cos into one node or libcall if possible.
1569 if (Subtarget->hasSinCos()) {
1570 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1571 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1572 if (Subtarget->isTargetDarwin()) {
1573 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1574 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1575 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1576 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1580 if (Subtarget->isTargetWin64()) {
1581 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1582 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1583 setOperationAction(ISD::SREM, MVT::i128, Custom);
1584 setOperationAction(ISD::UREM, MVT::i128, Custom);
1585 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1586 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1589 // We have target-specific dag combine patterns for the following nodes:
1590 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1591 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1592 setTargetDAGCombine(ISD::BITCAST);
1593 setTargetDAGCombine(ISD::VSELECT);
1594 setTargetDAGCombine(ISD::SELECT);
1595 setTargetDAGCombine(ISD::SHL);
1596 setTargetDAGCombine(ISD::SRA);
1597 setTargetDAGCombine(ISD::SRL);
1598 setTargetDAGCombine(ISD::OR);
1599 setTargetDAGCombine(ISD::AND);
1600 setTargetDAGCombine(ISD::ADD);
1601 setTargetDAGCombine(ISD::FADD);
1602 setTargetDAGCombine(ISD::FSUB);
1603 setTargetDAGCombine(ISD::FMA);
1604 setTargetDAGCombine(ISD::SUB);
1605 setTargetDAGCombine(ISD::LOAD);
1606 setTargetDAGCombine(ISD::MLOAD);
1607 setTargetDAGCombine(ISD::STORE);
1608 setTargetDAGCombine(ISD::MSTORE);
1609 setTargetDAGCombine(ISD::ZERO_EXTEND);
1610 setTargetDAGCombine(ISD::ANY_EXTEND);
1611 setTargetDAGCombine(ISD::SIGN_EXTEND);
1612 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1613 setTargetDAGCombine(ISD::SINT_TO_FP);
1614 setTargetDAGCombine(ISD::SETCC);
1615 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1616 setTargetDAGCombine(ISD::BUILD_VECTOR);
1617 setTargetDAGCombine(ISD::MUL);
1618 setTargetDAGCombine(ISD::XOR);
1620 computeRegisterProperties(Subtarget->getRegisterInfo());
1622 // On Darwin, -Os means optimize for size without hurting performance,
1623 // do not reduce the limit.
1624 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1625 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1626 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1627 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1628 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1629 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1630 setPrefLoopAlignment(4); // 2^4 bytes.
1632 // Predictable cmov don't hurt on atom because it's in-order.
1633 PredictableSelectIsExpensive = !Subtarget->isAtom();
1634 EnableExtLdPromotion = true;
1635 setPrefFunctionAlignment(4); // 2^4 bytes.
1637 verifyIntrinsicTables();
1640 // This has so far only been implemented for 64-bit MachO.
1641 bool X86TargetLowering::useLoadStackGuardNode() const {
1642 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1645 TargetLoweringBase::LegalizeTypeAction
1646 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1647 if (ExperimentalVectorWideningLegalization &&
1648 VT.getVectorNumElements() != 1 &&
1649 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1650 return TypeWidenVector;
1652 return TargetLoweringBase::getPreferredVectorAction(VT);
1655 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1657 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1659 const unsigned NumElts = VT.getVectorNumElements();
1660 const EVT EltVT = VT.getVectorElementType();
1661 if (VT.is512BitVector()) {
1662 if (Subtarget->hasAVX512())
1663 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1664 EltVT == MVT::f32 || EltVT == MVT::f64)
1666 case 8: return MVT::v8i1;
1667 case 16: return MVT::v16i1;
1669 if (Subtarget->hasBWI())
1670 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1672 case 32: return MVT::v32i1;
1673 case 64: return MVT::v64i1;
1677 if (VT.is256BitVector() || VT.is128BitVector()) {
1678 if (Subtarget->hasVLX())
1679 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1680 EltVT == MVT::f32 || EltVT == MVT::f64)
1682 case 2: return MVT::v2i1;
1683 case 4: return MVT::v4i1;
1684 case 8: return MVT::v8i1;
1686 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1687 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1689 case 8: return MVT::v8i1;
1690 case 16: return MVT::v16i1;
1691 case 32: return MVT::v32i1;
1695 return VT.changeVectorElementTypeToInteger();
1698 /// Helper for getByValTypeAlignment to determine
1699 /// the desired ByVal argument alignment.
1700 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1703 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1704 if (VTy->getBitWidth() == 128)
1706 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1707 unsigned EltAlign = 0;
1708 getMaxByValAlign(ATy->getElementType(), EltAlign);
1709 if (EltAlign > MaxAlign)
1710 MaxAlign = EltAlign;
1711 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1712 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1713 unsigned EltAlign = 0;
1714 getMaxByValAlign(STy->getElementType(i), EltAlign);
1715 if (EltAlign > MaxAlign)
1716 MaxAlign = EltAlign;
1723 /// Return the desired alignment for ByVal aggregate
1724 /// function arguments in the caller parameter area. For X86, aggregates
1725 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1726 /// are at 4-byte boundaries.
1727 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1728 if (Subtarget->is64Bit()) {
1729 // Max of 8 and alignment of type.
1730 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1737 if (Subtarget->hasSSE1())
1738 getMaxByValAlign(Ty, Align);
1742 /// Returns the target specific optimal type for load
1743 /// and store operations as a result of memset, memcpy, and memmove
1744 /// lowering. If DstAlign is zero that means it's safe to destination
1745 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1746 /// means there isn't a need to check it against alignment requirement,
1747 /// probably because the source does not need to be loaded. If 'IsMemset' is
1748 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1749 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1750 /// source is constant so it does not need to be loaded.
1751 /// It returns EVT::Other if the type should be determined using generic
1752 /// target-independent logic.
1754 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1755 unsigned DstAlign, unsigned SrcAlign,
1756 bool IsMemset, bool ZeroMemset,
1758 MachineFunction &MF) const {
1759 const Function *F = MF.getFunction();
1760 if ((!IsMemset || ZeroMemset) &&
1761 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1763 (Subtarget->isUnalignedMemAccessFast() ||
1764 ((DstAlign == 0 || DstAlign >= 16) &&
1765 (SrcAlign == 0 || SrcAlign >= 16)))) {
1767 if (Subtarget->hasInt256())
1769 if (Subtarget->hasFp256())
1772 if (Subtarget->hasSSE2())
1774 if (Subtarget->hasSSE1())
1776 } else if (!MemcpyStrSrc && Size >= 8 &&
1777 !Subtarget->is64Bit() &&
1778 Subtarget->hasSSE2()) {
1779 // Do not use f64 to lower memcpy if source is string constant. It's
1780 // better to use i32 to avoid the loads.
1784 if (Subtarget->is64Bit() && Size >= 8)
1789 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1791 return X86ScalarSSEf32;
1792 else if (VT == MVT::f64)
1793 return X86ScalarSSEf64;
1798 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1803 *Fast = Subtarget->isUnalignedMemAccessFast();
1807 /// Return the entry encoding for a jump table in the
1808 /// current function. The returned value is a member of the
1809 /// MachineJumpTableInfo::JTEntryKind enum.
1810 unsigned X86TargetLowering::getJumpTableEncoding() const {
1811 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1813 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1814 Subtarget->isPICStyleGOT())
1815 return MachineJumpTableInfo::EK_Custom32;
1817 // Otherwise, use the normal jump table encoding heuristics.
1818 return TargetLowering::getJumpTableEncoding();
1821 bool X86TargetLowering::useSoftFloat() const {
1822 return Subtarget->useSoftFloat();
1826 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1827 const MachineBasicBlock *MBB,
1828 unsigned uid,MCContext &Ctx) const{
1829 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1830 Subtarget->isPICStyleGOT());
1831 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1833 return MCSymbolRefExpr::create(MBB->getSymbol(),
1834 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1837 /// Returns relocation base for the given PIC jumptable.
1838 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1839 SelectionDAG &DAG) const {
1840 if (!Subtarget->is64Bit())
1841 // This doesn't have SDLoc associated with it, but is not really the
1842 // same as a Register.
1843 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1847 /// This returns the relocation base for the given PIC jumptable,
1848 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1849 const MCExpr *X86TargetLowering::
1850 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1851 MCContext &Ctx) const {
1852 // X86-64 uses RIP relative addressing based on the jump table label.
1853 if (Subtarget->isPICStyleRIPRel())
1854 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1856 // Otherwise, the reference is relative to the PIC base.
1857 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1860 std::pair<const TargetRegisterClass *, uint8_t>
1861 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1863 const TargetRegisterClass *RRC = nullptr;
1865 switch (VT.SimpleTy) {
1867 return TargetLowering::findRepresentativeClass(TRI, VT);
1868 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1869 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1872 RRC = &X86::VR64RegClass;
1874 case MVT::f32: case MVT::f64:
1875 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1876 case MVT::v4f32: case MVT::v2f64:
1877 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1879 RRC = &X86::VR128RegClass;
1882 return std::make_pair(RRC, Cost);
1885 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1886 unsigned &Offset) const {
1887 if (!Subtarget->isTargetLinux())
1890 if (Subtarget->is64Bit()) {
1891 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1893 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1905 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1906 unsigned DestAS) const {
1907 assert(SrcAS != DestAS && "Expected different address spaces!");
1909 return SrcAS < 256 && DestAS < 256;
1912 //===----------------------------------------------------------------------===//
1913 // Return Value Calling Convention Implementation
1914 //===----------------------------------------------------------------------===//
1916 #include "X86GenCallingConv.inc"
1919 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1920 MachineFunction &MF, bool isVarArg,
1921 const SmallVectorImpl<ISD::OutputArg> &Outs,
1922 LLVMContext &Context) const {
1923 SmallVector<CCValAssign, 16> RVLocs;
1924 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1925 return CCInfo.CheckReturn(Outs, RetCC_X86);
1928 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1929 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1934 X86TargetLowering::LowerReturn(SDValue Chain,
1935 CallingConv::ID CallConv, bool isVarArg,
1936 const SmallVectorImpl<ISD::OutputArg> &Outs,
1937 const SmallVectorImpl<SDValue> &OutVals,
1938 SDLoc dl, SelectionDAG &DAG) const {
1939 MachineFunction &MF = DAG.getMachineFunction();
1940 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1942 SmallVector<CCValAssign, 16> RVLocs;
1943 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
1944 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1947 SmallVector<SDValue, 6> RetOps;
1948 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1949 // Operand #1 = Bytes To Pop
1950 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
1953 // Copy the result values into the output registers.
1954 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1955 CCValAssign &VA = RVLocs[i];
1956 assert(VA.isRegLoc() && "Can only return in registers!");
1957 SDValue ValToCopy = OutVals[i];
1958 EVT ValVT = ValToCopy.getValueType();
1960 // Promote values to the appropriate types.
1961 if (VA.getLocInfo() == CCValAssign::SExt)
1962 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1963 else if (VA.getLocInfo() == CCValAssign::ZExt)
1964 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1965 else if (VA.getLocInfo() == CCValAssign::AExt) {
1966 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
1967 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1969 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1971 else if (VA.getLocInfo() == CCValAssign::BCvt)
1972 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
1974 assert(VA.getLocInfo() != CCValAssign::FPExt &&
1975 "Unexpected FP-extend for return value.");
1977 // If this is x86-64, and we disabled SSE, we can't return FP values,
1978 // or SSE or MMX vectors.
1979 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1980 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1981 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1982 report_fatal_error("SSE register return with SSE disabled");
1984 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1985 // llvm-gcc has never done it right and no one has noticed, so this
1986 // should be OK for now.
1987 if (ValVT == MVT::f64 &&
1988 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1989 report_fatal_error("SSE2 register return with SSE2 disabled");
1991 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1992 // the RET instruction and handled by the FP Stackifier.
1993 if (VA.getLocReg() == X86::FP0 ||
1994 VA.getLocReg() == X86::FP1) {
1995 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1996 // change the value to the FP stack register class.
1997 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1998 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1999 RetOps.push_back(ValToCopy);
2000 // Don't emit a copytoreg.
2004 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2005 // which is returned in RAX / RDX.
2006 if (Subtarget->is64Bit()) {
2007 if (ValVT == MVT::x86mmx) {
2008 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2009 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2010 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2012 // If we don't have SSE2 available, convert to v4f32 so the generated
2013 // register is legal.
2014 if (!Subtarget->hasSSE2())
2015 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2020 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2021 Flag = Chain.getValue(1);
2022 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2025 // All x86 ABIs require that for returning structs by value we copy
2026 // the sret argument into %rax/%eax (depending on ABI) for the return.
2027 // We saved the argument into a virtual register in the entry block,
2028 // so now we copy the value out and into %rax/%eax.
2030 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2031 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2032 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2033 // either case FuncInfo->setSRetReturnReg() will have been called.
2034 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2035 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2038 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2039 X86::RAX : X86::EAX;
2040 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2041 Flag = Chain.getValue(1);
2043 // RAX/EAX now acts like a return value.
2044 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2047 RetOps[0] = Chain; // Update chain.
2049 // Add the flag if we have it.
2051 RetOps.push_back(Flag);
2053 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2056 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2057 if (N->getNumValues() != 1)
2059 if (!N->hasNUsesOfValue(1, 0))
2062 SDValue TCChain = Chain;
2063 SDNode *Copy = *N->use_begin();
2064 if (Copy->getOpcode() == ISD::CopyToReg) {
2065 // If the copy has a glue operand, we conservatively assume it isn't safe to
2066 // perform a tail call.
2067 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2069 TCChain = Copy->getOperand(0);
2070 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2073 bool HasRet = false;
2074 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2076 if (UI->getOpcode() != X86ISD::RET_FLAG)
2078 // If we are returning more than one value, we can definitely
2079 // not make a tail call see PR19530
2080 if (UI->getNumOperands() > 4)
2082 if (UI->getNumOperands() == 4 &&
2083 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2096 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2097 ISD::NodeType ExtendKind) const {
2099 // TODO: Is this also valid on 32-bit?
2100 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2101 ReturnMVT = MVT::i8;
2103 ReturnMVT = MVT::i32;
2105 EVT MinVT = getRegisterType(Context, ReturnMVT);
2106 return VT.bitsLT(MinVT) ? MinVT : VT;
2109 /// Lower the result values of a call into the
2110 /// appropriate copies out of appropriate physical registers.
2113 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2114 CallingConv::ID CallConv, bool isVarArg,
2115 const SmallVectorImpl<ISD::InputArg> &Ins,
2116 SDLoc dl, SelectionDAG &DAG,
2117 SmallVectorImpl<SDValue> &InVals) const {
2119 // Assign locations to each value returned by this call.
2120 SmallVector<CCValAssign, 16> RVLocs;
2121 bool Is64Bit = Subtarget->is64Bit();
2122 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2124 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2126 // Copy all of the result registers out of their specified physreg.
2127 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2128 CCValAssign &VA = RVLocs[i];
2129 EVT CopyVT = VA.getLocVT();
2131 // If this is x86-64, and we disabled SSE, we can't return FP values
2132 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2133 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2134 report_fatal_error("SSE register return with SSE disabled");
2137 // If we prefer to use the value in xmm registers, copy it out as f80 and
2138 // use a truncate to move it from fp stack reg to xmm reg.
2139 bool RoundAfterCopy = false;
2140 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2141 isScalarFPTypeInSSEReg(VA.getValVT())) {
2143 RoundAfterCopy = (CopyVT != VA.getLocVT());
2146 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2147 CopyVT, InFlag).getValue(1);
2148 SDValue Val = Chain.getValue(0);
2151 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2152 // This truncation won't change the value.
2153 DAG.getIntPtrConstant(1, dl));
2155 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2156 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2158 InFlag = Chain.getValue(2);
2159 InVals.push_back(Val);
2165 //===----------------------------------------------------------------------===//
2166 // C & StdCall & Fast Calling Convention implementation
2167 //===----------------------------------------------------------------------===//
2168 // StdCall calling convention seems to be standard for many Windows' API
2169 // routines and around. It differs from C calling convention just a little:
2170 // callee should clean up the stack, not caller. Symbols should be also
2171 // decorated in some fancy way :) It doesn't support any vector arguments.
2172 // For info on fast calling convention see Fast Calling Convention (tail call)
2173 // implementation LowerX86_32FastCCCallTo.
2175 /// CallIsStructReturn - Determines whether a call uses struct return
2177 enum StructReturnType {
2182 static StructReturnType
2183 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2185 return NotStructReturn;
2187 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2188 if (!Flags.isSRet())
2189 return NotStructReturn;
2190 if (Flags.isInReg())
2191 return RegStructReturn;
2192 return StackStructReturn;
2195 /// Determines whether a function uses struct return semantics.
2196 static StructReturnType
2197 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2199 return NotStructReturn;
2201 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2202 if (!Flags.isSRet())
2203 return NotStructReturn;
2204 if (Flags.isInReg())
2205 return RegStructReturn;
2206 return StackStructReturn;
2209 /// Make a copy of an aggregate at address specified by "Src" to address
2210 /// "Dst" with size and alignment information specified by the specific
2211 /// parameter attribute. The copy will be passed as a byval function parameter.
2213 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2214 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2216 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2218 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2219 /*isVolatile*/false, /*AlwaysInline=*/true,
2220 /*isTailCall*/false,
2221 MachinePointerInfo(), MachinePointerInfo());
2224 /// Return true if the calling convention is one that
2225 /// supports tail call optimization.
2226 static bool IsTailCallConvention(CallingConv::ID CC) {
2227 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2228 CC == CallingConv::HiPE);
2231 /// \brief Return true if the calling convention is a C calling convention.
2232 static bool IsCCallConvention(CallingConv::ID CC) {
2233 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2234 CC == CallingConv::X86_64_SysV);
2237 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2239 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2240 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2244 CallingConv::ID CalleeCC = CS.getCallingConv();
2245 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2251 /// Return true if the function is being made into
2252 /// a tailcall target by changing its ABI.
2253 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2254 bool GuaranteedTailCallOpt) {
2255 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2259 X86TargetLowering::LowerMemArgument(SDValue Chain,
2260 CallingConv::ID CallConv,
2261 const SmallVectorImpl<ISD::InputArg> &Ins,
2262 SDLoc dl, SelectionDAG &DAG,
2263 const CCValAssign &VA,
2264 MachineFrameInfo *MFI,
2266 // Create the nodes corresponding to a load from this parameter slot.
2267 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2268 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2269 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2270 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2273 // If value is passed by pointer we have address passed instead of the value
2275 bool ExtendedInMem = VA.isExtInLoc() &&
2276 VA.getValVT().getScalarType() == MVT::i1;
2278 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2279 ValVT = VA.getLocVT();
2281 ValVT = VA.getValVT();
2283 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2284 // changed with more analysis.
2285 // In case of tail call optimization mark all arguments mutable. Since they
2286 // could be overwritten by lowering of arguments in case of a tail call.
2287 if (Flags.isByVal()) {
2288 unsigned Bytes = Flags.getByValSize();
2289 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2290 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2291 return DAG.getFrameIndex(FI, getPointerTy());
2293 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2294 VA.getLocMemOffset(), isImmutable);
2295 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2296 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2297 MachinePointerInfo::getFixedStack(FI),
2298 false, false, false, 0);
2299 return ExtendedInMem ?
2300 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2304 // FIXME: Get this from tablegen.
2305 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2306 const X86Subtarget *Subtarget) {
2307 assert(Subtarget->is64Bit());
2309 if (Subtarget->isCallingConvWin64(CallConv)) {
2310 static const MCPhysReg GPR64ArgRegsWin64[] = {
2311 X86::RCX, X86::RDX, X86::R8, X86::R9
2313 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2316 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2317 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2319 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2322 // FIXME: Get this from tablegen.
2323 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2324 CallingConv::ID CallConv,
2325 const X86Subtarget *Subtarget) {
2326 assert(Subtarget->is64Bit());
2327 if (Subtarget->isCallingConvWin64(CallConv)) {
2328 // The XMM registers which might contain var arg parameters are shadowed
2329 // in their paired GPR. So we only need to save the GPR to their home
2331 // TODO: __vectorcall will change this.
2335 const Function *Fn = MF.getFunction();
2336 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2337 bool isSoftFloat = Subtarget->useSoftFloat();
2338 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2339 "SSE register cannot be used when SSE is disabled!");
2340 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2341 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2345 static const MCPhysReg XMMArgRegs64Bit[] = {
2346 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2347 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2349 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2353 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2354 CallingConv::ID CallConv,
2356 const SmallVectorImpl<ISD::InputArg> &Ins,
2359 SmallVectorImpl<SDValue> &InVals)
2361 MachineFunction &MF = DAG.getMachineFunction();
2362 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2363 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2365 const Function* Fn = MF.getFunction();
2366 if (Fn->hasExternalLinkage() &&
2367 Subtarget->isTargetCygMing() &&
2368 Fn->getName() == "main")
2369 FuncInfo->setForceFramePointer(true);
2371 MachineFrameInfo *MFI = MF.getFrameInfo();
2372 bool Is64Bit = Subtarget->is64Bit();
2373 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2375 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2376 "Var args not supported with calling convention fastcc, ghc or hipe");
2378 // Assign locations to all of the incoming arguments.
2379 SmallVector<CCValAssign, 16> ArgLocs;
2380 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2382 // Allocate shadow area for Win64
2384 CCInfo.AllocateStack(32, 8);
2386 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2388 unsigned LastVal = ~0U;
2390 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2391 CCValAssign &VA = ArgLocs[i];
2392 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2394 assert(VA.getValNo() != LastVal &&
2395 "Don't support value assigned to multiple locs yet");
2397 LastVal = VA.getValNo();
2399 if (VA.isRegLoc()) {
2400 EVT RegVT = VA.getLocVT();
2401 const TargetRegisterClass *RC;
2402 if (RegVT == MVT::i32)
2403 RC = &X86::GR32RegClass;
2404 else if (Is64Bit && RegVT == MVT::i64)
2405 RC = &X86::GR64RegClass;
2406 else if (RegVT == MVT::f32)
2407 RC = &X86::FR32RegClass;
2408 else if (RegVT == MVT::f64)
2409 RC = &X86::FR64RegClass;
2410 else if (RegVT.is512BitVector())
2411 RC = &X86::VR512RegClass;
2412 else if (RegVT.is256BitVector())
2413 RC = &X86::VR256RegClass;
2414 else if (RegVT.is128BitVector())
2415 RC = &X86::VR128RegClass;
2416 else if (RegVT == MVT::x86mmx)
2417 RC = &X86::VR64RegClass;
2418 else if (RegVT == MVT::i1)
2419 RC = &X86::VK1RegClass;
2420 else if (RegVT == MVT::v8i1)
2421 RC = &X86::VK8RegClass;
2422 else if (RegVT == MVT::v16i1)
2423 RC = &X86::VK16RegClass;
2424 else if (RegVT == MVT::v32i1)
2425 RC = &X86::VK32RegClass;
2426 else if (RegVT == MVT::v64i1)
2427 RC = &X86::VK64RegClass;
2429 llvm_unreachable("Unknown argument type!");
2431 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2432 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2434 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2435 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2437 if (VA.getLocInfo() == CCValAssign::SExt)
2438 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2439 DAG.getValueType(VA.getValVT()));
2440 else if (VA.getLocInfo() == CCValAssign::ZExt)
2441 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2442 DAG.getValueType(VA.getValVT()));
2443 else if (VA.getLocInfo() == CCValAssign::BCvt)
2444 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2446 if (VA.isExtInLoc()) {
2447 // Handle MMX values passed in XMM regs.
2448 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2449 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2451 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2454 assert(VA.isMemLoc());
2455 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2458 // If value is passed via pointer - do a load.
2459 if (VA.getLocInfo() == CCValAssign::Indirect)
2460 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2461 MachinePointerInfo(), false, false, false, 0);
2463 InVals.push_back(ArgValue);
2466 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2467 // All x86 ABIs require that for returning structs by value we copy the
2468 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2469 // the argument into a virtual register so that we can access it from the
2471 if (Ins[i].Flags.isSRet()) {
2472 unsigned Reg = FuncInfo->getSRetReturnReg();
2474 MVT PtrTy = getPointerTy();
2475 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2476 FuncInfo->setSRetReturnReg(Reg);
2478 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2479 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2484 unsigned StackSize = CCInfo.getNextStackOffset();
2485 // Align stack specially for tail calls.
2486 if (FuncIsMadeTailCallSafe(CallConv,
2487 MF.getTarget().Options.GuaranteedTailCallOpt))
2488 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2490 // If the function takes variable number of arguments, make a frame index for
2491 // the start of the first vararg value... for expansion of llvm.va_start. We
2492 // can skip this if there are no va_start calls.
2493 if (MFI->hasVAStart() &&
2494 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2495 CallConv != CallingConv::X86_ThisCall))) {
2496 FuncInfo->setVarArgsFrameIndex(
2497 MFI->CreateFixedObject(1, StackSize, true));
2500 MachineModuleInfo &MMI = MF.getMMI();
2501 const Function *WinEHParent = nullptr;
2502 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2503 WinEHParent = MMI.getWinEHParent(Fn);
2504 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2505 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2507 // Figure out if XMM registers are in use.
2508 assert(!(Subtarget->useSoftFloat() &&
2509 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2510 "SSE register cannot be used when SSE is disabled!");
2512 // 64-bit calling conventions support varargs and register parameters, so we
2513 // have to do extra work to spill them in the prologue.
2514 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2515 // Find the first unallocated argument registers.
2516 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2517 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2518 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2519 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2520 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2521 "SSE register cannot be used when SSE is disabled!");
2523 // Gather all the live in physical registers.
2524 SmallVector<SDValue, 6> LiveGPRs;
2525 SmallVector<SDValue, 8> LiveXMMRegs;
2527 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2528 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2530 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2532 if (!ArgXMMs.empty()) {
2533 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2534 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2535 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2536 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2537 LiveXMMRegs.push_back(
2538 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2543 // Get to the caller-allocated home save location. Add 8 to account
2544 // for the return address.
2545 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2546 FuncInfo->setRegSaveFrameIndex(
2547 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2548 // Fixup to set vararg frame on shadow area (4 x i64).
2550 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2552 // For X86-64, if there are vararg parameters that are passed via
2553 // registers, then we must store them to their spots on the stack so
2554 // they may be loaded by deferencing the result of va_next.
2555 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2556 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2557 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2558 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2561 // Store the integer parameter registers.
2562 SmallVector<SDValue, 8> MemOps;
2563 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2565 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2566 for (SDValue Val : LiveGPRs) {
2567 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2568 DAG.getIntPtrConstant(Offset, dl));
2570 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2571 MachinePointerInfo::getFixedStack(
2572 FuncInfo->getRegSaveFrameIndex(), Offset),
2574 MemOps.push_back(Store);
2578 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2579 // Now store the XMM (fp + vector) parameter registers.
2580 SmallVector<SDValue, 12> SaveXMMOps;
2581 SaveXMMOps.push_back(Chain);
2582 SaveXMMOps.push_back(ALVal);
2583 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2584 FuncInfo->getRegSaveFrameIndex(), dl));
2585 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2586 FuncInfo->getVarArgsFPOffset(), dl));
2587 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2589 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2590 MVT::Other, SaveXMMOps));
2593 if (!MemOps.empty())
2594 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2595 } else if (IsWinEHOutlined) {
2596 // Get to the caller-allocated home save location. Add 8 to account
2597 // for the return address.
2598 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2599 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2600 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2602 MMI.getWinEHFuncInfo(Fn)
2603 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2604 FuncInfo->getRegSaveFrameIndex();
2606 // Store the second integer parameter (rdx) into rsp+16 relative to the
2607 // stack pointer at the entry of the function.
2609 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2610 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2611 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2612 Chain = DAG.getStore(
2613 Val.getValue(1), dl, Val, RSFIN,
2614 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2615 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2618 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2619 // Find the largest legal vector type.
2620 MVT VecVT = MVT::Other;
2621 // FIXME: Only some x86_32 calling conventions support AVX512.
2622 if (Subtarget->hasAVX512() &&
2623 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2624 CallConv == CallingConv::Intel_OCL_BI)))
2625 VecVT = MVT::v16f32;
2626 else if (Subtarget->hasAVX())
2628 else if (Subtarget->hasSSE2())
2631 // We forward some GPRs and some vector types.
2632 SmallVector<MVT, 2> RegParmTypes;
2633 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2634 RegParmTypes.push_back(IntVT);
2635 if (VecVT != MVT::Other)
2636 RegParmTypes.push_back(VecVT);
2638 // Compute the set of forwarded registers. The rest are scratch.
2639 SmallVectorImpl<ForwardedRegister> &Forwards =
2640 FuncInfo->getForwardedMustTailRegParms();
2641 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2643 // Conservatively forward AL on x86_64, since it might be used for varargs.
2644 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2645 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2646 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2649 // Copy all forwards from physical to virtual registers.
2650 for (ForwardedRegister &F : Forwards) {
2651 // FIXME: Can we use a less constrained schedule?
2652 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2653 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2654 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2658 // Some CCs need callee pop.
2659 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2660 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2661 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2663 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2664 // If this is an sret function, the return should pop the hidden pointer.
2665 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2666 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2667 argsAreStructReturn(Ins) == StackStructReturn)
2668 FuncInfo->setBytesToPopOnReturn(4);
2672 // RegSaveFrameIndex is X86-64 only.
2673 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2674 if (CallConv == CallingConv::X86_FastCall ||
2675 CallConv == CallingConv::X86_ThisCall)
2676 // fastcc functions can't have varargs.
2677 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2680 FuncInfo->setArgumentStackSize(StackSize);
2682 if (IsWinEHParent) {
2683 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2684 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2685 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2686 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2687 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2688 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2689 /*isVolatile=*/true,
2690 /*isNonTemporal=*/false, /*Alignment=*/0);
2697 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2698 SDValue StackPtr, SDValue Arg,
2699 SDLoc dl, SelectionDAG &DAG,
2700 const CCValAssign &VA,
2701 ISD::ArgFlagsTy Flags) const {
2702 unsigned LocMemOffset = VA.getLocMemOffset();
2703 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2704 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2705 if (Flags.isByVal())
2706 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2708 return DAG.getStore(Chain, dl, Arg, PtrOff,
2709 MachinePointerInfo::getStack(LocMemOffset),
2713 /// Emit a load of return address if tail call
2714 /// optimization is performed and it is required.
2716 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2717 SDValue &OutRetAddr, SDValue Chain,
2718 bool IsTailCall, bool Is64Bit,
2719 int FPDiff, SDLoc dl) const {
2720 // Adjust the Return address stack slot.
2721 EVT VT = getPointerTy();
2722 OutRetAddr = getReturnAddressFrameIndex(DAG);
2724 // Load the "old" Return address.
2725 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2726 false, false, false, 0);
2727 return SDValue(OutRetAddr.getNode(), 1);
2730 /// Emit a store of the return address if tail call
2731 /// optimization is performed and it is required (FPDiff!=0).
2732 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2733 SDValue Chain, SDValue RetAddrFrIdx,
2734 EVT PtrVT, unsigned SlotSize,
2735 int FPDiff, SDLoc dl) {
2736 // Store the return address to the appropriate stack slot.
2737 if (!FPDiff) return Chain;
2738 // Calculate the new stack slot for the return address.
2739 int NewReturnAddrFI =
2740 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2742 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2743 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2744 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2750 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2751 SmallVectorImpl<SDValue> &InVals) const {
2752 SelectionDAG &DAG = CLI.DAG;
2754 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2755 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2756 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2757 SDValue Chain = CLI.Chain;
2758 SDValue Callee = CLI.Callee;
2759 CallingConv::ID CallConv = CLI.CallConv;
2760 bool &isTailCall = CLI.IsTailCall;
2761 bool isVarArg = CLI.IsVarArg;
2763 MachineFunction &MF = DAG.getMachineFunction();
2764 bool Is64Bit = Subtarget->is64Bit();
2765 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2766 StructReturnType SR = callIsStructReturn(Outs);
2767 bool IsSibcall = false;
2768 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2769 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2771 if (Attr.getValueAsString() == "true")
2774 if (Subtarget->isPICStyleGOT() &&
2775 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2776 // If we are using a GOT, disable tail calls to external symbols with
2777 // default visibility. Tail calling such a symbol requires using a GOT
2778 // relocation, which forces early binding of the symbol. This breaks code
2779 // that require lazy function symbol resolution. Using musttail or
2780 // GuaranteedTailCallOpt will override this.
2781 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2782 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2783 G->getGlobal()->hasDefaultVisibility()))
2787 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2789 // Force this to be a tail call. The verifier rules are enough to ensure
2790 // that we can lower this successfully without moving the return address
2793 } else if (isTailCall) {
2794 // Check if it's really possible to do a tail call.
2795 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2796 isVarArg, SR != NotStructReturn,
2797 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2798 Outs, OutVals, Ins, DAG);
2800 // Sibcalls are automatically detected tailcalls which do not require
2802 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2809 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2810 "Var args not supported with calling convention fastcc, ghc or hipe");
2812 // Analyze operands of the call, assigning locations to each operand.
2813 SmallVector<CCValAssign, 16> ArgLocs;
2814 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2816 // Allocate shadow area for Win64
2818 CCInfo.AllocateStack(32, 8);
2820 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2822 // Get a count of how many bytes are to be pushed on the stack.
2823 unsigned NumBytes = CCInfo.getNextStackOffset();
2825 // This is a sibcall. The memory operands are available in caller's
2826 // own caller's stack.
2828 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2829 IsTailCallConvention(CallConv))
2830 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2833 if (isTailCall && !IsSibcall && !IsMustTail) {
2834 // Lower arguments at fp - stackoffset + fpdiff.
2835 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2837 FPDiff = NumBytesCallerPushed - NumBytes;
2839 // Set the delta of movement of the returnaddr stackslot.
2840 // But only set if delta is greater than previous delta.
2841 if (FPDiff < X86Info->getTCReturnAddrDelta())
2842 X86Info->setTCReturnAddrDelta(FPDiff);
2845 unsigned NumBytesToPush = NumBytes;
2846 unsigned NumBytesToPop = NumBytes;
2848 // If we have an inalloca argument, all stack space has already been allocated
2849 // for us and be right at the top of the stack. We don't support multiple
2850 // arguments passed in memory when using inalloca.
2851 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2853 if (!ArgLocs.back().isMemLoc())
2854 report_fatal_error("cannot use inalloca attribute on a register "
2856 if (ArgLocs.back().getLocMemOffset() != 0)
2857 report_fatal_error("any parameter with the inalloca attribute must be "
2858 "the only memory argument");
2862 Chain = DAG.getCALLSEQ_START(
2863 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2865 SDValue RetAddrFrIdx;
2866 // Load return address for tail calls.
2867 if (isTailCall && FPDiff)
2868 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2869 Is64Bit, FPDiff, dl);
2871 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2872 SmallVector<SDValue, 8> MemOpChains;
2875 // Walk the register/memloc assignments, inserting copies/loads. In the case
2876 // of tail call optimization arguments are handle later.
2877 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2878 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2879 // Skip inalloca arguments, they have already been written.
2880 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2881 if (Flags.isInAlloca())
2884 CCValAssign &VA = ArgLocs[i];
2885 EVT RegVT = VA.getLocVT();
2886 SDValue Arg = OutVals[i];
2887 bool isByVal = Flags.isByVal();
2889 // Promote the value if needed.
2890 switch (VA.getLocInfo()) {
2891 default: llvm_unreachable("Unknown loc info!");
2892 case CCValAssign::Full: break;
2893 case CCValAssign::SExt:
2894 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2896 case CCValAssign::ZExt:
2897 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2899 case CCValAssign::AExt:
2900 if (Arg.getValueType().isVector() &&
2901 Arg.getValueType().getScalarType() == MVT::i1)
2902 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2903 else if (RegVT.is128BitVector()) {
2904 // Special case: passing MMX values in XMM registers.
2905 Arg = DAG.getBitcast(MVT::i64, Arg);
2906 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2907 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2909 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2911 case CCValAssign::BCvt:
2912 Arg = DAG.getBitcast(RegVT, Arg);
2914 case CCValAssign::Indirect: {
2915 // Store the argument.
2916 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2917 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2918 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2919 MachinePointerInfo::getFixedStack(FI),
2926 if (VA.isRegLoc()) {
2927 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2928 if (isVarArg && IsWin64) {
2929 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2930 // shadow reg if callee is a varargs function.
2931 unsigned ShadowReg = 0;
2932 switch (VA.getLocReg()) {
2933 case X86::XMM0: ShadowReg = X86::RCX; break;
2934 case X86::XMM1: ShadowReg = X86::RDX; break;
2935 case X86::XMM2: ShadowReg = X86::R8; break;
2936 case X86::XMM3: ShadowReg = X86::R9; break;
2939 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2941 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2942 assert(VA.isMemLoc());
2943 if (!StackPtr.getNode())
2944 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2946 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2947 dl, DAG, VA, Flags));
2951 if (!MemOpChains.empty())
2952 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
2954 if (Subtarget->isPICStyleGOT()) {
2955 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2958 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2959 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
2961 // If we are tail calling and generating PIC/GOT style code load the
2962 // address of the callee into ECX. The value in ecx is used as target of
2963 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2964 // for tail calls on PIC/GOT architectures. Normally we would just put the
2965 // address of GOT into ebx and then call target@PLT. But for tail calls
2966 // ebx would be restored (since ebx is callee saved) before jumping to the
2969 // Note: The actual moving to ECX is done further down.
2970 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2971 if (G && !G->getGlobal()->hasLocalLinkage() &&
2972 G->getGlobal()->hasDefaultVisibility())
2973 Callee = LowerGlobalAddress(Callee, DAG);
2974 else if (isa<ExternalSymbolSDNode>(Callee))
2975 Callee = LowerExternalSymbol(Callee, DAG);
2979 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
2980 // From AMD64 ABI document:
2981 // For calls that may call functions that use varargs or stdargs
2982 // (prototype-less calls or calls to functions containing ellipsis (...) in
2983 // the declaration) %al is used as hidden argument to specify the number
2984 // of SSE registers used. The contents of %al do not need to match exactly
2985 // the number of registers, but must be an ubound on the number of SSE
2986 // registers used and is in the range 0 - 8 inclusive.
2988 // Count the number of XMM registers allocated.
2989 static const MCPhysReg XMMArgRegs[] = {
2990 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2991 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2993 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
2994 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2995 && "SSE registers cannot be used when SSE is disabled");
2997 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2998 DAG.getConstant(NumXMMRegs, dl,
3002 if (isVarArg && IsMustTail) {
3003 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3004 for (const auto &F : Forwards) {
3005 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3006 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3010 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3011 // don't need this because the eligibility check rejects calls that require
3012 // shuffling arguments passed in memory.
3013 if (!IsSibcall && isTailCall) {
3014 // Force all the incoming stack arguments to be loaded from the stack
3015 // before any new outgoing arguments are stored to the stack, because the
3016 // outgoing stack slots may alias the incoming argument stack slots, and
3017 // the alias isn't otherwise explicit. This is slightly more conservative
3018 // than necessary, because it means that each store effectively depends
3019 // on every argument instead of just those arguments it would clobber.
3020 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3022 SmallVector<SDValue, 8> MemOpChains2;
3025 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3026 CCValAssign &VA = ArgLocs[i];
3029 assert(VA.isMemLoc());
3030 SDValue Arg = OutVals[i];
3031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3032 // Skip inalloca arguments. They don't require any work.
3033 if (Flags.isInAlloca())
3035 // Create frame index.
3036 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3037 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3038 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3039 FIN = DAG.getFrameIndex(FI, getPointerTy());
3041 if (Flags.isByVal()) {
3042 // Copy relative to framepointer.
3043 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3044 if (!StackPtr.getNode())
3045 StackPtr = DAG.getCopyFromReg(Chain, dl,
3046 RegInfo->getStackRegister(),
3048 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3050 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3054 // Store relative to framepointer.
3055 MemOpChains2.push_back(
3056 DAG.getStore(ArgChain, dl, Arg, FIN,
3057 MachinePointerInfo::getFixedStack(FI),
3062 if (!MemOpChains2.empty())
3063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3065 // Store the return address to the appropriate stack slot.
3066 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3067 getPointerTy(), RegInfo->getSlotSize(),
3071 // Build a sequence of copy-to-reg nodes chained together with token chain
3072 // and flag operands which copy the outgoing args into registers.
3074 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3075 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3076 RegsToPass[i].second, InFlag);
3077 InFlag = Chain.getValue(1);
3080 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3081 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3082 // In the 64-bit large code model, we have to make all calls
3083 // through a register, since the call instruction's 32-bit
3084 // pc-relative offset may not be large enough to hold the whole
3086 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3087 // If the callee is a GlobalAddress node (quite common, every direct call
3088 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3090 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3092 // We should use extra load for direct calls to dllimported functions in
3094 const GlobalValue *GV = G->getGlobal();
3095 if (!GV->hasDLLImportStorageClass()) {
3096 unsigned char OpFlags = 0;
3097 bool ExtraLoad = false;
3098 unsigned WrapperKind = ISD::DELETED_NODE;
3100 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3101 // external symbols most go through the PLT in PIC mode. If the symbol
3102 // has hidden or protected visibility, or if it is static or local, then
3103 // we don't need to use the PLT - we can directly call it.
3104 if (Subtarget->isTargetELF() &&
3105 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3106 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3107 OpFlags = X86II::MO_PLT;
3108 } else if (Subtarget->isPICStyleStubAny() &&
3109 (GV->isDeclaration() || GV->isWeakForLinker()) &&
3110 (!Subtarget->getTargetTriple().isMacOSX() ||
3111 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3112 // PC-relative references to external symbols should go through $stub,
3113 // unless we're building with the leopard linker or later, which
3114 // automatically synthesizes these stubs.
3115 OpFlags = X86II::MO_DARWIN_STUB;
3116 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3117 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3118 // If the function is marked as non-lazy, generate an indirect call
3119 // which loads from the GOT directly. This avoids runtime overhead
3120 // at the cost of eager binding (and one extra byte of encoding).
3121 OpFlags = X86II::MO_GOTPCREL;
3122 WrapperKind = X86ISD::WrapperRIP;
3126 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3127 G->getOffset(), OpFlags);
3129 // Add a wrapper if needed.
3130 if (WrapperKind != ISD::DELETED_NODE)
3131 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3132 // Add extra indirection if needed.
3134 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3135 MachinePointerInfo::getGOT(),
3136 false, false, false, 0);
3138 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3139 unsigned char OpFlags = 0;
3141 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3142 // external symbols should go through the PLT.
3143 if (Subtarget->isTargetELF() &&
3144 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3145 OpFlags = X86II::MO_PLT;
3146 } else if (Subtarget->isPICStyleStubAny() &&
3147 (!Subtarget->getTargetTriple().isMacOSX() ||
3148 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3149 // PC-relative references to external symbols should go through $stub,
3150 // unless we're building with the leopard linker or later, which
3151 // automatically synthesizes these stubs.
3152 OpFlags = X86II::MO_DARWIN_STUB;
3155 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3157 } else if (Subtarget->isTarget64BitILP32() &&
3158 Callee->getValueType(0) == MVT::i32) {
3159 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3160 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3163 // Returns a chain & a flag for retval copy to use.
3164 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3165 SmallVector<SDValue, 8> Ops;
3167 if (!IsSibcall && isTailCall) {
3168 Chain = DAG.getCALLSEQ_END(Chain,
3169 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3170 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3171 InFlag = Chain.getValue(1);
3174 Ops.push_back(Chain);
3175 Ops.push_back(Callee);
3178 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3180 // Add argument registers to the end of the list so that they are known live
3182 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3183 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3184 RegsToPass[i].second.getValueType()));
3186 // Add a register mask operand representing the call-preserved registers.
3187 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3188 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3189 assert(Mask && "Missing call preserved mask for calling convention");
3190 Ops.push_back(DAG.getRegisterMask(Mask));
3192 if (InFlag.getNode())
3193 Ops.push_back(InFlag);
3197 //// If this is the first return lowered for this function, add the regs
3198 //// to the liveout set for the function.
3199 // This isn't right, although it's probably harmless on x86; liveouts
3200 // should be computed from returns not tail calls. Consider a void
3201 // function making a tail call to a function returning int.
3202 MF.getFrameInfo()->setHasTailCall();
3203 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3206 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3207 InFlag = Chain.getValue(1);
3209 // Create the CALLSEQ_END node.
3210 unsigned NumBytesForCalleeToPop;
3211 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3212 DAG.getTarget().Options.GuaranteedTailCallOpt))
3213 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3214 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3215 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3216 SR == StackStructReturn)
3217 // If this is a call to a struct-return function, the callee
3218 // pops the hidden struct pointer, so we have to push it back.
3219 // This is common for Darwin/X86, Linux & Mingw32 targets.
3220 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3221 NumBytesForCalleeToPop = 4;
3223 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3225 // Returns a flag for retval copy to use.
3227 Chain = DAG.getCALLSEQ_END(Chain,
3228 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3229 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3232 InFlag = Chain.getValue(1);
3235 // Handle result values, copying them out of physregs into vregs that we
3237 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3238 Ins, dl, DAG, InVals);
3241 //===----------------------------------------------------------------------===//
3242 // Fast Calling Convention (tail call) implementation
3243 //===----------------------------------------------------------------------===//
3245 // Like std call, callee cleans arguments, convention except that ECX is
3246 // reserved for storing the tail called function address. Only 2 registers are
3247 // free for argument passing (inreg). Tail call optimization is performed
3249 // * tailcallopt is enabled
3250 // * caller/callee are fastcc
3251 // On X86_64 architecture with GOT-style position independent code only local
3252 // (within module) calls are supported at the moment.
3253 // To keep the stack aligned according to platform abi the function
3254 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3255 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3256 // If a tail called function callee has more arguments than the caller the
3257 // caller needs to make sure that there is room to move the RETADDR to. This is
3258 // achieved by reserving an area the size of the argument delta right after the
3259 // original RETADDR, but before the saved framepointer or the spilled registers
3260 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3272 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3273 /// for a 16 byte align requirement.
3275 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3276 SelectionDAG& DAG) const {
3277 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3278 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3279 unsigned StackAlignment = TFI.getStackAlignment();
3280 uint64_t AlignMask = StackAlignment - 1;
3281 int64_t Offset = StackSize;
3282 unsigned SlotSize = RegInfo->getSlotSize();
3283 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3284 // Number smaller than 12 so just add the difference.
3285 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3287 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3288 Offset = ((~AlignMask) & Offset) + StackAlignment +
3289 (StackAlignment-SlotSize);
3294 /// MatchingStackOffset - Return true if the given stack call argument is
3295 /// already available in the same position (relatively) of the caller's
3296 /// incoming argument stack.
3298 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3299 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3300 const X86InstrInfo *TII) {
3301 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3303 if (Arg.getOpcode() == ISD::CopyFromReg) {
3304 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3305 if (!TargetRegisterInfo::isVirtualRegister(VR))
3307 MachineInstr *Def = MRI->getVRegDef(VR);
3310 if (!Flags.isByVal()) {
3311 if (!TII->isLoadFromStackSlot(Def, FI))
3314 unsigned Opcode = Def->getOpcode();
3315 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3316 Opcode == X86::LEA64_32r) &&
3317 Def->getOperand(1).isFI()) {
3318 FI = Def->getOperand(1).getIndex();
3319 Bytes = Flags.getByValSize();
3323 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3324 if (Flags.isByVal())
3325 // ByVal argument is passed in as a pointer but it's now being
3326 // dereferenced. e.g.
3327 // define @foo(%struct.X* %A) {
3328 // tail call @bar(%struct.X* byval %A)
3331 SDValue Ptr = Ld->getBasePtr();
3332 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3335 FI = FINode->getIndex();
3336 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3337 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3338 FI = FINode->getIndex();
3339 Bytes = Flags.getByValSize();
3343 assert(FI != INT_MAX);
3344 if (!MFI->isFixedObjectIndex(FI))
3346 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3349 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3350 /// for tail call optimization. Targets which want to do tail call
3351 /// optimization should implement this function.
3353 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3354 CallingConv::ID CalleeCC,
3356 bool isCalleeStructRet,
3357 bool isCallerStructRet,
3359 const SmallVectorImpl<ISD::OutputArg> &Outs,
3360 const SmallVectorImpl<SDValue> &OutVals,
3361 const SmallVectorImpl<ISD::InputArg> &Ins,
3362 SelectionDAG &DAG) const {
3363 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3366 // If -tailcallopt is specified, make fastcc functions tail-callable.
3367 const MachineFunction &MF = DAG.getMachineFunction();
3368 const Function *CallerF = MF.getFunction();
3370 // If the function return type is x86_fp80 and the callee return type is not,
3371 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3372 // perform a tailcall optimization here.
3373 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3376 CallingConv::ID CallerCC = CallerF->getCallingConv();
3377 bool CCMatch = CallerCC == CalleeCC;
3378 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3379 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3381 // Win64 functions have extra shadow space for argument homing. Don't do the
3382 // sibcall if the caller and callee have mismatched expectations for this
3384 if (IsCalleeWin64 != IsCallerWin64)
3387 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3388 if (IsTailCallConvention(CalleeCC) && CCMatch)
3393 // Look for obvious safe cases to perform tail call optimization that do not
3394 // require ABI changes. This is what gcc calls sibcall.
3396 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3397 // emit a special epilogue.
3398 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3399 if (RegInfo->needsStackRealignment(MF))
3402 // Also avoid sibcall optimization if either caller or callee uses struct
3403 // return semantics.
3404 if (isCalleeStructRet || isCallerStructRet)
3407 // An stdcall/thiscall caller is expected to clean up its arguments; the
3408 // callee isn't going to do that.
3409 // FIXME: this is more restrictive than needed. We could produce a tailcall
3410 // when the stack adjustment matches. For example, with a thiscall that takes
3411 // only one argument.
3412 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3413 CallerCC == CallingConv::X86_ThisCall))
3416 // Do not sibcall optimize vararg calls unless all arguments are passed via
3418 if (isVarArg && !Outs.empty()) {
3420 // Optimizing for varargs on Win64 is unlikely to be safe without
3421 // additional testing.
3422 if (IsCalleeWin64 || IsCallerWin64)
3425 SmallVector<CCValAssign, 16> ArgLocs;
3426 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3429 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3430 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3431 if (!ArgLocs[i].isRegLoc())
3435 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3436 // stack. Therefore, if it's not used by the call it is not safe to optimize
3437 // this into a sibcall.
3438 bool Unused = false;
3439 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3446 SmallVector<CCValAssign, 16> RVLocs;
3447 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3449 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3450 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3451 CCValAssign &VA = RVLocs[i];
3452 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3457 // If the calling conventions do not match, then we'd better make sure the
3458 // results are returned in the same way as what the caller expects.
3460 SmallVector<CCValAssign, 16> RVLocs1;
3461 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3463 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3465 SmallVector<CCValAssign, 16> RVLocs2;
3466 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3468 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3470 if (RVLocs1.size() != RVLocs2.size())
3472 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3473 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3475 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3477 if (RVLocs1[i].isRegLoc()) {
3478 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3481 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3487 // If the callee takes no arguments then go on to check the results of the
3489 if (!Outs.empty()) {
3490 // Check if stack adjustment is needed. For now, do not do this if any
3491 // argument is passed on the stack.
3492 SmallVector<CCValAssign, 16> ArgLocs;
3493 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3496 // Allocate shadow area for Win64
3498 CCInfo.AllocateStack(32, 8);
3500 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3501 if (CCInfo.getNextStackOffset()) {
3502 MachineFunction &MF = DAG.getMachineFunction();
3503 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3506 // Check if the arguments are already laid out in the right way as
3507 // the caller's fixed stack objects.
3508 MachineFrameInfo *MFI = MF.getFrameInfo();
3509 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3510 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3511 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3512 CCValAssign &VA = ArgLocs[i];
3513 SDValue Arg = OutVals[i];
3514 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3515 if (VA.getLocInfo() == CCValAssign::Indirect)
3517 if (!VA.isRegLoc()) {
3518 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3525 // If the tailcall address may be in a register, then make sure it's
3526 // possible to register allocate for it. In 32-bit, the call address can
3527 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3528 // callee-saved registers are restored. These happen to be the same
3529 // registers used to pass 'inreg' arguments so watch out for those.
3530 if (!Subtarget->is64Bit() &&
3531 ((!isa<GlobalAddressSDNode>(Callee) &&
3532 !isa<ExternalSymbolSDNode>(Callee)) ||
3533 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3534 unsigned NumInRegs = 0;
3535 // In PIC we need an extra register to formulate the address computation
3537 unsigned MaxInRegs =
3538 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3540 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3541 CCValAssign &VA = ArgLocs[i];
3544 unsigned Reg = VA.getLocReg();
3547 case X86::EAX: case X86::EDX: case X86::ECX:
3548 if (++NumInRegs == MaxInRegs)
3560 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3561 const TargetLibraryInfo *libInfo) const {
3562 return X86::createFastISel(funcInfo, libInfo);
3565 //===----------------------------------------------------------------------===//
3566 // Other Lowering Hooks
3567 //===----------------------------------------------------------------------===//
3569 static bool MayFoldLoad(SDValue Op) {
3570 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3573 static bool MayFoldIntoStore(SDValue Op) {
3574 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3577 static bool isTargetShuffle(unsigned Opcode) {
3579 default: return false;
3580 case X86ISD::BLENDI:
3581 case X86ISD::PSHUFB:
3582 case X86ISD::PSHUFD:
3583 case X86ISD::PSHUFHW:
3584 case X86ISD::PSHUFLW:
3586 case X86ISD::PALIGNR:
3587 case X86ISD::MOVLHPS:
3588 case X86ISD::MOVLHPD:
3589 case X86ISD::MOVHLPS:
3590 case X86ISD::MOVLPS:
3591 case X86ISD::MOVLPD:
3592 case X86ISD::MOVSHDUP:
3593 case X86ISD::MOVSLDUP:
3594 case X86ISD::MOVDDUP:
3597 case X86ISD::UNPCKL:
3598 case X86ISD::UNPCKH:
3599 case X86ISD::VPERMILPI:
3600 case X86ISD::VPERM2X128:
3601 case X86ISD::VPERMI:
3606 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3607 SDValue V1, unsigned TargetMask,
3608 SelectionDAG &DAG) {
3610 default: llvm_unreachable("Unknown x86 shuffle node");
3611 case X86ISD::PSHUFD:
3612 case X86ISD::PSHUFHW:
3613 case X86ISD::PSHUFLW:
3614 case X86ISD::VPERMILPI:
3615 case X86ISD::VPERMI:
3616 return DAG.getNode(Opc, dl, VT, V1,
3617 DAG.getConstant(TargetMask, dl, MVT::i8));
3621 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3622 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3624 default: llvm_unreachable("Unknown x86 shuffle node");
3625 case X86ISD::MOVLHPS:
3626 case X86ISD::MOVLHPD:
3627 case X86ISD::MOVHLPS:
3628 case X86ISD::MOVLPS:
3629 case X86ISD::MOVLPD:
3632 case X86ISD::UNPCKL:
3633 case X86ISD::UNPCKH:
3634 return DAG.getNode(Opc, dl, VT, V1, V2);
3638 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3639 MachineFunction &MF = DAG.getMachineFunction();
3640 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3641 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3642 int ReturnAddrIndex = FuncInfo->getRAIndex();
3644 if (ReturnAddrIndex == 0) {
3645 // Set up a frame object for the return address.
3646 unsigned SlotSize = RegInfo->getSlotSize();
3647 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3650 FuncInfo->setRAIndex(ReturnAddrIndex);
3653 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3656 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3657 bool hasSymbolicDisplacement) {
3658 // Offset should fit into 32 bit immediate field.
3659 if (!isInt<32>(Offset))
3662 // If we don't have a symbolic displacement - we don't have any extra
3664 if (!hasSymbolicDisplacement)
3667 // FIXME: Some tweaks might be needed for medium code model.
3668 if (M != CodeModel::Small && M != CodeModel::Kernel)
3671 // For small code model we assume that latest object is 16MB before end of 31
3672 // bits boundary. We may also accept pretty large negative constants knowing
3673 // that all objects are in the positive half of address space.
3674 if (M == CodeModel::Small && Offset < 16*1024*1024)
3677 // For kernel code model we know that all object resist in the negative half
3678 // of 32bits address space. We may not accept negative offsets, since they may
3679 // be just off and we may accept pretty large positive ones.
3680 if (M == CodeModel::Kernel && Offset >= 0)
3686 /// isCalleePop - Determines whether the callee is required to pop its
3687 /// own arguments. Callee pop is necessary to support tail calls.
3688 bool X86::isCalleePop(CallingConv::ID CallingConv,
3689 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3690 switch (CallingConv) {
3693 case CallingConv::X86_StdCall:
3694 case CallingConv::X86_FastCall:
3695 case CallingConv::X86_ThisCall:
3697 case CallingConv::Fast:
3698 case CallingConv::GHC:
3699 case CallingConv::HiPE:
3706 /// \brief Return true if the condition is an unsigned comparison operation.
3707 static bool isX86CCUnsigned(unsigned X86CC) {
3709 default: llvm_unreachable("Invalid integer condition!");
3710 case X86::COND_E: return true;
3711 case X86::COND_G: return false;
3712 case X86::COND_GE: return false;
3713 case X86::COND_L: return false;
3714 case X86::COND_LE: return false;
3715 case X86::COND_NE: return true;
3716 case X86::COND_B: return true;
3717 case X86::COND_A: return true;
3718 case X86::COND_BE: return true;
3719 case X86::COND_AE: return true;
3721 llvm_unreachable("covered switch fell through?!");
3724 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3725 /// specific condition code, returning the condition code and the LHS/RHS of the
3726 /// comparison to make.
3727 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3728 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3730 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3731 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3732 // X > -1 -> X == 0, jump !sign.
3733 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3734 return X86::COND_NS;
3736 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3737 // X < 0 -> X == 0, jump on sign.
3740 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3742 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3743 return X86::COND_LE;
3747 switch (SetCCOpcode) {
3748 default: llvm_unreachable("Invalid integer condition!");
3749 case ISD::SETEQ: return X86::COND_E;
3750 case ISD::SETGT: return X86::COND_G;
3751 case ISD::SETGE: return X86::COND_GE;
3752 case ISD::SETLT: return X86::COND_L;
3753 case ISD::SETLE: return X86::COND_LE;
3754 case ISD::SETNE: return X86::COND_NE;
3755 case ISD::SETULT: return X86::COND_B;
3756 case ISD::SETUGT: return X86::COND_A;
3757 case ISD::SETULE: return X86::COND_BE;
3758 case ISD::SETUGE: return X86::COND_AE;
3762 // First determine if it is required or is profitable to flip the operands.
3764 // If LHS is a foldable load, but RHS is not, flip the condition.
3765 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3766 !ISD::isNON_EXTLoad(RHS.getNode())) {
3767 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3768 std::swap(LHS, RHS);
3771 switch (SetCCOpcode) {
3777 std::swap(LHS, RHS);
3781 // On a floating point condition, the flags are set as follows:
3783 // 0 | 0 | 0 | X > Y
3784 // 0 | 0 | 1 | X < Y
3785 // 1 | 0 | 0 | X == Y
3786 // 1 | 1 | 1 | unordered
3787 switch (SetCCOpcode) {
3788 default: llvm_unreachable("Condcode should be pre-legalized away");
3790 case ISD::SETEQ: return X86::COND_E;
3791 case ISD::SETOLT: // flipped
3793 case ISD::SETGT: return X86::COND_A;
3794 case ISD::SETOLE: // flipped
3796 case ISD::SETGE: return X86::COND_AE;
3797 case ISD::SETUGT: // flipped
3799 case ISD::SETLT: return X86::COND_B;
3800 case ISD::SETUGE: // flipped
3802 case ISD::SETLE: return X86::COND_BE;
3804 case ISD::SETNE: return X86::COND_NE;
3805 case ISD::SETUO: return X86::COND_P;
3806 case ISD::SETO: return X86::COND_NP;
3808 case ISD::SETUNE: return X86::COND_INVALID;
3812 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3813 /// code. Current x86 isa includes the following FP cmov instructions:
3814 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3815 static bool hasFPCMov(unsigned X86CC) {
3831 /// isFPImmLegal - Returns true if the target can instruction select the
3832 /// specified FP immediate natively. If false, the legalizer will
3833 /// materialize the FP immediate as a load from a constant pool.
3834 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3835 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3836 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3842 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3843 ISD::LoadExtType ExtTy,
3845 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3846 // relocation target a movq or addq instruction: don't let the load shrink.
3847 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3848 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3849 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3850 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3854 /// \brief Returns true if it is beneficial to convert a load of a constant
3855 /// to just the constant itself.
3856 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3858 assert(Ty->isIntegerTy());
3860 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3861 if (BitSize == 0 || BitSize > 64)
3866 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3867 unsigned Index) const {
3868 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3871 return (Index == 0 || Index == ResVT.getVectorNumElements());
3874 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3875 // Speculate cttz only if we can directly use TZCNT.
3876 return Subtarget->hasBMI();
3879 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3880 // Speculate ctlz only if we can directly use LZCNT.
3881 return Subtarget->hasLZCNT();
3884 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3885 /// the specified range (L, H].
3886 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3887 return (Val < 0) || (Val >= Low && Val < Hi);
3890 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3891 /// specified value.
3892 static bool isUndefOrEqual(int Val, int CmpVal) {
3893 return (Val < 0 || Val == CmpVal);
3896 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3897 /// from position Pos and ending in Pos+Size, falls within the specified
3898 /// sequential range (Low, Low+Size]. or is undef.
3899 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3900 unsigned Pos, unsigned Size, int Low) {
3901 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3902 if (!isUndefOrEqual(Mask[i], Low))
3907 /// isVEXTRACTIndex - Return true if the specified
3908 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3909 /// suitable for instruction that extract 128 or 256 bit vectors
3910 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3911 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3912 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3915 // The index should be aligned on a vecWidth-bit boundary.
3917 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3919 MVT VT = N->getSimpleValueType(0);
3920 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3921 bool Result = (Index * ElSize) % vecWidth == 0;
3926 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3927 /// operand specifies a subvector insert that is suitable for input to
3928 /// insertion of 128 or 256-bit subvectors
3929 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3930 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3931 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3933 // The index should be aligned on a vecWidth-bit boundary.
3935 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3937 MVT VT = N->getSimpleValueType(0);
3938 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3939 bool Result = (Index * ElSize) % vecWidth == 0;
3944 bool X86::isVINSERT128Index(SDNode *N) {
3945 return isVINSERTIndex(N, 128);
3948 bool X86::isVINSERT256Index(SDNode *N) {
3949 return isVINSERTIndex(N, 256);
3952 bool X86::isVEXTRACT128Index(SDNode *N) {
3953 return isVEXTRACTIndex(N, 128);
3956 bool X86::isVEXTRACT256Index(SDNode *N) {
3957 return isVEXTRACTIndex(N, 256);
3960 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
3961 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3962 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3963 llvm_unreachable("Illegal extract subvector for VEXTRACT");
3966 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3968 MVT VecVT = N->getOperand(0).getSimpleValueType();
3969 MVT ElVT = VecVT.getVectorElementType();
3971 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3972 return Index / NumElemsPerChunk;
3975 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
3976 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
3977 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
3978 llvm_unreachable("Illegal insert subvector for VINSERT");
3981 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
3983 MVT VecVT = N->getSimpleValueType(0);
3984 MVT ElVT = VecVT.getVectorElementType();
3986 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
3987 return Index / NumElemsPerChunk;
3990 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
3991 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
3992 /// and VINSERTI128 instructions.
3993 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
3994 return getExtractVEXTRACTImmediate(N, 128);
3997 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
3998 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
3999 /// and VINSERTI64x4 instructions.
4000 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4001 return getExtractVEXTRACTImmediate(N, 256);
4004 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4005 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4006 /// and VINSERTI128 instructions.
4007 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4008 return getInsertVINSERTImmediate(N, 128);
4011 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4012 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4013 /// and VINSERTI64x4 instructions.
4014 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4015 return getInsertVINSERTImmediate(N, 256);
4018 /// isZero - Returns true if Elt is a constant integer zero
4019 static bool isZero(SDValue V) {
4020 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4021 return C && C->isNullValue();
4024 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4026 bool X86::isZeroNode(SDValue Elt) {
4029 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4030 return CFP->getValueAPF().isPosZero();
4034 /// getZeroVector - Returns a vector of specified type with all zero elements.
4036 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4037 SelectionDAG &DAG, SDLoc dl) {
4038 assert(VT.isVector() && "Expected a vector type");
4040 // Always build SSE zero vectors as <4 x i32> bitcasted
4041 // to their dest type. This ensures they get CSE'd.
4043 if (VT.is128BitVector()) { // SSE
4044 if (Subtarget->hasSSE2()) { // SSE2
4045 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4046 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4048 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4049 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4051 } else if (VT.is256BitVector()) { // AVX
4052 if (Subtarget->hasInt256()) { // AVX2
4053 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4054 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4055 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4057 // 256-bit logic and arithmetic instructions in AVX are all
4058 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4059 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4060 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4061 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4063 } else if (VT.is512BitVector()) { // AVX-512
4064 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4065 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4066 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4067 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4068 } else if (VT.getScalarType() == MVT::i1) {
4070 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4071 && "Unexpected vector type");
4072 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4073 && "Unexpected vector type");
4074 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4075 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4076 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4078 llvm_unreachable("Unexpected vector type");
4080 return DAG.getBitcast(VT, Vec);
4083 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4084 SelectionDAG &DAG, SDLoc dl,
4085 unsigned vectorWidth) {
4086 assert((vectorWidth == 128 || vectorWidth == 256) &&
4087 "Unsupported vector width");
4088 EVT VT = Vec.getValueType();
4089 EVT ElVT = VT.getVectorElementType();
4090 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4091 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4092 VT.getVectorNumElements()/Factor);
4094 // Extract from UNDEF is UNDEF.
4095 if (Vec.getOpcode() == ISD::UNDEF)
4096 return DAG.getUNDEF(ResultVT);
4098 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4099 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4101 // This is the index of the first element of the vectorWidth-bit chunk
4103 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4106 // If the input is a buildvector just emit a smaller one.
4107 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4108 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4109 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4112 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4113 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4116 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4117 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4118 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4119 /// instructions or a simple subregister reference. Idx is an index in the
4120 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4121 /// lowering EXTRACT_VECTOR_ELT operations easier.
4122 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4123 SelectionDAG &DAG, SDLoc dl) {
4124 assert((Vec.getValueType().is256BitVector() ||
4125 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4126 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4129 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4130 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4131 SelectionDAG &DAG, SDLoc dl) {
4132 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4133 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4136 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4137 unsigned IdxVal, SelectionDAG &DAG,
4138 SDLoc dl, unsigned vectorWidth) {
4139 assert((vectorWidth == 128 || vectorWidth == 256) &&
4140 "Unsupported vector width");
4141 // Inserting UNDEF is Result
4142 if (Vec.getOpcode() == ISD::UNDEF)
4144 EVT VT = Vec.getValueType();
4145 EVT ElVT = VT.getVectorElementType();
4146 EVT ResultVT = Result.getValueType();
4148 // Insert the relevant vectorWidth bits.
4149 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4151 // This is the index of the first element of the vectorWidth-bit chunk
4153 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4156 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4157 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4160 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4161 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4162 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4163 /// simple superregister reference. Idx is an index in the 128 bits
4164 /// we want. It need not be aligned to a 128-bit boundary. That makes
4165 /// lowering INSERT_VECTOR_ELT operations easier.
4166 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4167 SelectionDAG &DAG, SDLoc dl) {
4168 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4170 // For insertion into the zero index (low half) of a 256-bit vector, it is
4171 // more efficient to generate a blend with immediate instead of an insert*128.
4172 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4173 // extend the subvector to the size of the result vector. Make sure that
4174 // we are not recursing on that node by checking for undef here.
4175 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4176 Result.getOpcode() != ISD::UNDEF) {
4177 EVT ResultVT = Result.getValueType();
4178 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4179 SDValue Undef = DAG.getUNDEF(ResultVT);
4180 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4183 // The blend instruction, and therefore its mask, depend on the data type.
4184 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4185 if (ScalarType.isFloatingPoint()) {
4186 // Choose either vblendps (float) or vblendpd (double).
4187 unsigned ScalarSize = ScalarType.getSizeInBits();
4188 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4189 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4190 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4191 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4194 const X86Subtarget &Subtarget =
4195 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4197 // AVX2 is needed for 256-bit integer blend support.
4198 // Integers must be cast to 32-bit because there is only vpblendd;
4199 // vpblendw can't be used for this because it has a handicapped mask.
4201 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4202 // is still more efficient than using the wrong domain vinsertf128 that
4203 // will be created by InsertSubVector().
4204 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4206 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4207 Vec256 = DAG.getBitcast(CastVT, Vec256);
4208 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4209 return DAG.getBitcast(ResultVT, Vec256);
4212 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4215 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4216 SelectionDAG &DAG, SDLoc dl) {
4217 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4218 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4221 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4222 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4223 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4224 /// large BUILD_VECTORS.
4225 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4226 unsigned NumElems, SelectionDAG &DAG,
4228 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4229 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4232 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4233 unsigned NumElems, SelectionDAG &DAG,
4235 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4236 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4239 /// getOnesVector - Returns a vector of specified type with all bits set.
4240 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4241 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4242 /// Then bitcast to their original type, ensuring they get CSE'd.
4243 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4245 assert(VT.isVector() && "Expected a vector type");
4247 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4249 if (VT.is256BitVector()) {
4250 if (HasInt256) { // AVX2
4251 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4252 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4254 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4255 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4257 } else if (VT.is128BitVector()) {
4258 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4260 llvm_unreachable("Unexpected vector type");
4262 return DAG.getBitcast(VT, Vec);
4265 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4266 /// operation of specified width.
4267 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4269 unsigned NumElems = VT.getVectorNumElements();
4270 SmallVector<int, 8> Mask;
4271 Mask.push_back(NumElems);
4272 for (unsigned i = 1; i != NumElems; ++i)
4274 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4277 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4278 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4280 unsigned NumElems = VT.getVectorNumElements();
4281 SmallVector<int, 8> Mask;
4282 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4284 Mask.push_back(i + NumElems);
4286 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4289 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4290 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4292 unsigned NumElems = VT.getVectorNumElements();
4293 SmallVector<int, 8> Mask;
4294 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4295 Mask.push_back(i + Half);
4296 Mask.push_back(i + NumElems + Half);
4298 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4301 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4302 /// vector of zero or undef vector. This produces a shuffle where the low
4303 /// element of V2 is swizzled into the zero/undef vector, landing at element
4304 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4305 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4307 const X86Subtarget *Subtarget,
4308 SelectionDAG &DAG) {
4309 MVT VT = V2.getSimpleValueType();
4311 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4312 unsigned NumElems = VT.getVectorNumElements();
4313 SmallVector<int, 16> MaskVec;
4314 for (unsigned i = 0; i != NumElems; ++i)
4315 // If this is the insertion idx, put the low elt of V2 here.
4316 MaskVec.push_back(i == Idx ? NumElems : i);
4317 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4320 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4321 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4322 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4323 /// shuffles which use a single input multiple times, and in those cases it will
4324 /// adjust the mask to only have indices within that single input.
4325 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4326 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4327 unsigned NumElems = VT.getVectorNumElements();
4331 bool IsFakeUnary = false;
4332 switch(N->getOpcode()) {
4333 case X86ISD::BLENDI:
4334 ImmN = N->getOperand(N->getNumOperands()-1);
4335 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4338 ImmN = N->getOperand(N->getNumOperands()-1);
4339 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4340 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4342 case X86ISD::UNPCKH:
4343 DecodeUNPCKHMask(VT, Mask);
4344 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4346 case X86ISD::UNPCKL:
4347 DecodeUNPCKLMask(VT, Mask);
4348 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4350 case X86ISD::MOVHLPS:
4351 DecodeMOVHLPSMask(NumElems, Mask);
4352 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4354 case X86ISD::MOVLHPS:
4355 DecodeMOVLHPSMask(NumElems, Mask);
4356 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4358 case X86ISD::PALIGNR:
4359 ImmN = N->getOperand(N->getNumOperands()-1);
4360 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4362 case X86ISD::PSHUFD:
4363 case X86ISD::VPERMILPI:
4364 ImmN = N->getOperand(N->getNumOperands()-1);
4365 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4368 case X86ISD::PSHUFHW:
4369 ImmN = N->getOperand(N->getNumOperands()-1);
4370 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4373 case X86ISD::PSHUFLW:
4374 ImmN = N->getOperand(N->getNumOperands()-1);
4375 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4378 case X86ISD::PSHUFB: {
4380 SDValue MaskNode = N->getOperand(1);
4381 while (MaskNode->getOpcode() == ISD::BITCAST)
4382 MaskNode = MaskNode->getOperand(0);
4384 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4385 // If we have a build-vector, then things are easy.
4386 EVT VT = MaskNode.getValueType();
4387 assert(VT.isVector() &&
4388 "Can't produce a non-vector with a build_vector!");
4389 if (!VT.isInteger())
4392 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4394 SmallVector<uint64_t, 32> RawMask;
4395 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4396 SDValue Op = MaskNode->getOperand(i);
4397 if (Op->getOpcode() == ISD::UNDEF) {
4398 RawMask.push_back((uint64_t)SM_SentinelUndef);
4401 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4404 APInt MaskElement = CN->getAPIntValue();
4406 // We now have to decode the element which could be any integer size and
4407 // extract each byte of it.
4408 for (int j = 0; j < NumBytesPerElement; ++j) {
4409 // Note that this is x86 and so always little endian: the low byte is
4410 // the first byte of the mask.
4411 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4412 MaskElement = MaskElement.lshr(8);
4415 DecodePSHUFBMask(RawMask, Mask);
4419 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4423 SDValue Ptr = MaskLoad->getBasePtr();
4424 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4425 Ptr->getOpcode() == X86ISD::WrapperRIP)
4426 Ptr = Ptr->getOperand(0);
4428 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4429 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4432 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4433 DecodePSHUFBMask(C, Mask);
4441 case X86ISD::VPERMI:
4442 ImmN = N->getOperand(N->getNumOperands()-1);
4443 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4448 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4450 case X86ISD::VPERM2X128:
4451 ImmN = N->getOperand(N->getNumOperands()-1);
4452 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4453 if (Mask.empty()) return false;
4455 case X86ISD::MOVSLDUP:
4456 DecodeMOVSLDUPMask(VT, Mask);
4459 case X86ISD::MOVSHDUP:
4460 DecodeMOVSHDUPMask(VT, Mask);
4463 case X86ISD::MOVDDUP:
4464 DecodeMOVDDUPMask(VT, Mask);
4467 case X86ISD::MOVLHPD:
4468 case X86ISD::MOVLPD:
4469 case X86ISD::MOVLPS:
4470 // Not yet implemented
4472 default: llvm_unreachable("unknown target shuffle node");
4475 // If we have a fake unary shuffle, the shuffle mask is spread across two
4476 // inputs that are actually the same node. Re-map the mask to always point
4477 // into the first input.
4480 if (M >= (int)Mask.size())
4486 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4487 /// element of the result of the vector shuffle.
4488 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4491 return SDValue(); // Limit search depth.
4493 SDValue V = SDValue(N, 0);
4494 EVT VT = V.getValueType();
4495 unsigned Opcode = V.getOpcode();
4497 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4498 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4499 int Elt = SV->getMaskElt(Index);
4502 return DAG.getUNDEF(VT.getVectorElementType());
4504 unsigned NumElems = VT.getVectorNumElements();
4505 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4506 : SV->getOperand(1);
4507 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4510 // Recurse into target specific vector shuffles to find scalars.
4511 if (isTargetShuffle(Opcode)) {
4512 MVT ShufVT = V.getSimpleValueType();
4513 unsigned NumElems = ShufVT.getVectorNumElements();
4514 SmallVector<int, 16> ShuffleMask;
4517 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4520 int Elt = ShuffleMask[Index];
4522 return DAG.getUNDEF(ShufVT.getVectorElementType());
4524 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4526 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4530 // Actual nodes that may contain scalar elements
4531 if (Opcode == ISD::BITCAST) {
4532 V = V.getOperand(0);
4533 EVT SrcVT = V.getValueType();
4534 unsigned NumElems = VT.getVectorNumElements();
4536 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4540 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4541 return (Index == 0) ? V.getOperand(0)
4542 : DAG.getUNDEF(VT.getVectorElementType());
4544 if (V.getOpcode() == ISD::BUILD_VECTOR)
4545 return V.getOperand(Index);
4550 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4552 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4553 unsigned NumNonZero, unsigned NumZero,
4555 const X86Subtarget* Subtarget,
4556 const TargetLowering &TLI) {
4564 // SSE4.1 - use PINSRB to insert each byte directly.
4565 if (Subtarget->hasSSE41()) {
4566 for (unsigned i = 0; i < 16; ++i) {
4567 bool isNonZero = (NonZeros & (1 << i)) != 0;
4571 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4573 V = DAG.getUNDEF(MVT::v16i8);
4576 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4577 MVT::v16i8, V, Op.getOperand(i),
4578 DAG.getIntPtrConstant(i, dl));
4585 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4586 for (unsigned i = 0; i < 16; ++i) {
4587 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4588 if (ThisIsNonZero && First) {
4590 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4592 V = DAG.getUNDEF(MVT::v8i16);
4597 SDValue ThisElt, LastElt;
4598 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4599 if (LastIsNonZero) {
4600 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4601 MVT::i16, Op.getOperand(i-1));
4603 if (ThisIsNonZero) {
4604 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4605 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4606 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4608 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4612 if (ThisElt.getNode())
4613 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4614 DAG.getIntPtrConstant(i/2, dl));
4618 return DAG.getBitcast(MVT::v16i8, V);
4621 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4623 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4624 unsigned NumNonZero, unsigned NumZero,
4626 const X86Subtarget* Subtarget,
4627 const TargetLowering &TLI) {
4634 for (unsigned i = 0; i < 8; ++i) {
4635 bool isNonZero = (NonZeros & (1 << i)) != 0;
4639 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4641 V = DAG.getUNDEF(MVT::v8i16);
4644 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4645 MVT::v8i16, V, Op.getOperand(i),
4646 DAG.getIntPtrConstant(i, dl));
4653 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4654 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4655 const X86Subtarget *Subtarget,
4656 const TargetLowering &TLI) {
4657 // Find all zeroable elements.
4658 std::bitset<4> Zeroable;
4659 for (int i=0; i < 4; ++i) {
4660 SDValue Elt = Op->getOperand(i);
4661 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4663 assert(Zeroable.size() - Zeroable.count() > 1 &&
4664 "We expect at least two non-zero elements!");
4666 // We only know how to deal with build_vector nodes where elements are either
4667 // zeroable or extract_vector_elt with constant index.
4668 SDValue FirstNonZero;
4669 unsigned FirstNonZeroIdx;
4670 for (unsigned i=0; i < 4; ++i) {
4673 SDValue Elt = Op->getOperand(i);
4674 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4675 !isa<ConstantSDNode>(Elt.getOperand(1)))
4677 // Make sure that this node is extracting from a 128-bit vector.
4678 MVT VT = Elt.getOperand(0).getSimpleValueType();
4679 if (!VT.is128BitVector())
4681 if (!FirstNonZero.getNode()) {
4683 FirstNonZeroIdx = i;
4687 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4688 SDValue V1 = FirstNonZero.getOperand(0);
4689 MVT VT = V1.getSimpleValueType();
4691 // See if this build_vector can be lowered as a blend with zero.
4693 unsigned EltMaskIdx, EltIdx;
4695 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4696 if (Zeroable[EltIdx]) {
4697 // The zero vector will be on the right hand side.
4698 Mask[EltIdx] = EltIdx+4;
4702 Elt = Op->getOperand(EltIdx);
4703 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4704 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4705 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4707 Mask[EltIdx] = EltIdx;
4711 // Let the shuffle legalizer deal with blend operations.
4712 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4713 if (V1.getSimpleValueType() != VT)
4714 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4715 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4718 // See if we can lower this build_vector to a INSERTPS.
4719 if (!Subtarget->hasSSE41())
4722 SDValue V2 = Elt.getOperand(0);
4723 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4726 bool CanFold = true;
4727 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4731 SDValue Current = Op->getOperand(i);
4732 SDValue SrcVector = Current->getOperand(0);
4735 CanFold = SrcVector == V1 &&
4736 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4742 assert(V1.getNode() && "Expected at least two non-zero elements!");
4743 if (V1.getSimpleValueType() != MVT::v4f32)
4744 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4745 if (V2.getSimpleValueType() != MVT::v4f32)
4746 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4748 // Ok, we can emit an INSERTPS instruction.
4749 unsigned ZMask = Zeroable.to_ulong();
4751 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4752 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4754 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4755 DAG.getIntPtrConstant(InsertPSMask, DL));
4756 return DAG.getBitcast(VT, Result);
4759 /// Return a vector logical shift node.
4760 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4761 unsigned NumBits, SelectionDAG &DAG,
4762 const TargetLowering &TLI, SDLoc dl) {
4763 assert(VT.is128BitVector() && "Unknown type for VShift");
4764 MVT ShVT = MVT::v2i64;
4765 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4766 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4767 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4768 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4769 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4770 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4774 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4776 // Check if the scalar load can be widened into a vector load. And if
4777 // the address is "base + cst" see if the cst can be "absorbed" into
4778 // the shuffle mask.
4779 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4780 SDValue Ptr = LD->getBasePtr();
4781 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4783 EVT PVT = LD->getValueType(0);
4784 if (PVT != MVT::i32 && PVT != MVT::f32)
4789 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4790 FI = FINode->getIndex();
4792 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4793 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4794 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4795 Offset = Ptr.getConstantOperandVal(1);
4796 Ptr = Ptr.getOperand(0);
4801 // FIXME: 256-bit vector instructions don't require a strict alignment,
4802 // improve this code to support it better.
4803 unsigned RequiredAlign = VT.getSizeInBits()/8;
4804 SDValue Chain = LD->getChain();
4805 // Make sure the stack object alignment is at least 16 or 32.
4806 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4807 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4808 if (MFI->isFixedObjectIndex(FI)) {
4809 // Can't change the alignment. FIXME: It's possible to compute
4810 // the exact stack offset and reference FI + adjust offset instead.
4811 // If someone *really* cares about this. That's the way to implement it.
4814 MFI->setObjectAlignment(FI, RequiredAlign);
4818 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4819 // Ptr + (Offset & ~15).
4822 if ((Offset % RequiredAlign) & 3)
4824 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4827 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4828 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4831 int EltNo = (Offset - StartOffset) >> 2;
4832 unsigned NumElems = VT.getVectorNumElements();
4834 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4835 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4836 LD->getPointerInfo().getWithOffset(StartOffset),
4837 false, false, false, 0);
4839 SmallVector<int, 8> Mask(NumElems, EltNo);
4841 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4847 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4848 /// elements can be replaced by a single large load which has the same value as
4849 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4851 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4853 /// FIXME: we'd also like to handle the case where the last elements are zero
4854 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4855 /// There's even a handy isZeroNode for that purpose.
4856 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4857 SDLoc &DL, SelectionDAG &DAG,
4858 bool isAfterLegalize) {
4859 unsigned NumElems = Elts.size();
4861 LoadSDNode *LDBase = nullptr;
4862 unsigned LastLoadedElt = -1U;
4864 // For each element in the initializer, see if we've found a load or an undef.
4865 // If we don't find an initial load element, or later load elements are
4866 // non-consecutive, bail out.
4867 for (unsigned i = 0; i < NumElems; ++i) {
4868 SDValue Elt = Elts[i];
4869 // Look through a bitcast.
4870 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4871 Elt = Elt.getOperand(0);
4872 if (!Elt.getNode() ||
4873 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4876 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4878 LDBase = cast<LoadSDNode>(Elt.getNode());
4882 if (Elt.getOpcode() == ISD::UNDEF)
4885 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4886 EVT LdVT = Elt.getValueType();
4887 // Each loaded element must be the correct fractional portion of the
4888 // requested vector load.
4889 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4891 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4896 // If we have found an entire vector of loads and undefs, then return a large
4897 // load of the entire vector width starting at the base pointer. If we found
4898 // consecutive loads for the low half, generate a vzext_load node.
4899 if (LastLoadedElt == NumElems - 1) {
4900 assert(LDBase && "Did not find base load for merging consecutive loads");
4901 EVT EltVT = LDBase->getValueType(0);
4902 // Ensure that the input vector size for the merged loads matches the
4903 // cumulative size of the input elements.
4904 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4907 if (isAfterLegalize &&
4908 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4911 SDValue NewLd = SDValue();
4913 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4914 LDBase->getPointerInfo(), LDBase->isVolatile(),
4915 LDBase->isNonTemporal(), LDBase->isInvariant(),
4916 LDBase->getAlignment());
4918 if (LDBase->hasAnyUseOfValue(1)) {
4919 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4921 SDValue(NewLd.getNode(), 1));
4922 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4923 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4924 SDValue(NewLd.getNode(), 1));
4930 //TODO: The code below fires only for for loading the low v2i32 / v2f32
4931 //of a v4i32 / v4f32. It's probably worth generalizing.
4932 EVT EltVT = VT.getVectorElementType();
4933 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
4934 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
4935 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
4936 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
4938 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
4939 LDBase->getPointerInfo(),
4940 LDBase->getAlignment(),
4941 false/*isVolatile*/, true/*ReadMem*/,
4944 // Make sure the newly-created LOAD is in the same position as LDBase in
4945 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
4946 // update uses of LDBase's output chain to use the TokenFactor.
4947 if (LDBase->hasAnyUseOfValue(1)) {
4948 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4949 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
4950 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4951 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4952 SDValue(ResNode.getNode(), 1));
4955 return DAG.getBitcast(VT, ResNode);
4960 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
4961 /// to generate a splat value for the following cases:
4962 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
4963 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
4964 /// a scalar load, or a constant.
4965 /// The VBROADCAST node is returned when a pattern is found,
4966 /// or SDValue() otherwise.
4967 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
4968 SelectionDAG &DAG) {
4969 // VBROADCAST requires AVX.
4970 // TODO: Splats could be generated for non-AVX CPUs using SSE
4971 // instructions, but there's less potential gain for only 128-bit vectors.
4972 if (!Subtarget->hasAVX())
4975 MVT VT = Op.getSimpleValueType();
4978 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
4979 "Unsupported vector type for broadcast.");
4984 switch (Op.getOpcode()) {
4986 // Unknown pattern found.
4989 case ISD::BUILD_VECTOR: {
4990 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
4991 BitVector UndefElements;
4992 SDValue Splat = BVOp->getSplatValue(&UndefElements);
4994 // We need a splat of a single value to use broadcast, and it doesn't
4995 // make any sense if the value is only in one element of the vector.
4996 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5000 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5001 Ld.getOpcode() == ISD::ConstantFP);
5003 // Make sure that all of the users of a non-constant load are from the
5004 // BUILD_VECTOR node.
5005 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5010 case ISD::VECTOR_SHUFFLE: {
5011 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5013 // Shuffles must have a splat mask where the first element is
5015 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5018 SDValue Sc = Op.getOperand(0);
5019 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5020 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5022 if (!Subtarget->hasInt256())
5025 // Use the register form of the broadcast instruction available on AVX2.
5026 if (VT.getSizeInBits() >= 256)
5027 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5028 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5031 Ld = Sc.getOperand(0);
5032 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5033 Ld.getOpcode() == ISD::ConstantFP);
5035 // The scalar_to_vector node and the suspected
5036 // load node must have exactly one user.
5037 // Constants may have multiple users.
5039 // AVX-512 has register version of the broadcast
5040 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5041 Ld.getValueType().getSizeInBits() >= 32;
5042 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5049 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5050 bool IsGE256 = (VT.getSizeInBits() >= 256);
5052 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5053 // instruction to save 8 or more bytes of constant pool data.
5054 // TODO: If multiple splats are generated to load the same constant,
5055 // it may be detrimental to overall size. There needs to be a way to detect
5056 // that condition to know if this is truly a size win.
5057 const Function *F = DAG.getMachineFunction().getFunction();
5058 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5060 // Handle broadcasting a single constant scalar from the constant pool
5062 // On Sandybridge (no AVX2), it is still better to load a constant vector
5063 // from the constant pool and not to broadcast it from a scalar.
5064 // But override that restriction when optimizing for size.
5065 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5066 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5067 EVT CVT = Ld.getValueType();
5068 assert(!CVT.isVector() && "Must not broadcast a vector type");
5070 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5071 // For size optimization, also splat v2f64 and v2i64, and for size opt
5072 // with AVX2, also splat i8 and i16.
5073 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5074 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5075 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5076 const Constant *C = nullptr;
5077 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5078 C = CI->getConstantIntValue();
5079 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5080 C = CF->getConstantFPValue();
5082 assert(C && "Invalid constant type");
5084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5085 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5086 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5087 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5088 MachinePointerInfo::getConstantPool(),
5089 false, false, false, Alignment);
5091 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5095 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5097 // Handle AVX2 in-register broadcasts.
5098 if (!IsLoad && Subtarget->hasInt256() &&
5099 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5100 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5102 // The scalar source must be a normal load.
5106 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5107 (Subtarget->hasVLX() && ScalarSize == 64))
5108 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5110 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5111 // double since there is no vbroadcastsd xmm
5112 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5113 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5114 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5117 // Unsupported broadcast.
5121 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5122 /// underlying vector and index.
5124 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5126 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5128 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5129 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5132 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5134 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5136 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5137 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5140 // In this case the vector is the extract_subvector expression and the index
5141 // is 2, as specified by the shuffle.
5142 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5143 SDValue ShuffleVec = SVOp->getOperand(0);
5144 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5145 assert(ShuffleVecVT.getVectorElementType() ==
5146 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5148 int ShuffleIdx = SVOp->getMaskElt(Idx);
5149 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5150 ExtractedFromVec = ShuffleVec;
5156 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5157 MVT VT = Op.getSimpleValueType();
5159 // Skip if insert_vec_elt is not supported.
5160 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5161 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5165 unsigned NumElems = Op.getNumOperands();
5169 SmallVector<unsigned, 4> InsertIndices;
5170 SmallVector<int, 8> Mask(NumElems, -1);
5172 for (unsigned i = 0; i != NumElems; ++i) {
5173 unsigned Opc = Op.getOperand(i).getOpcode();
5175 if (Opc == ISD::UNDEF)
5178 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5179 // Quit if more than 1 elements need inserting.
5180 if (InsertIndices.size() > 1)
5183 InsertIndices.push_back(i);
5187 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5188 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5189 // Quit if non-constant index.
5190 if (!isa<ConstantSDNode>(ExtIdx))
5192 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5194 // Quit if extracted from vector of different type.
5195 if (ExtractedFromVec.getValueType() != VT)
5198 if (!VecIn1.getNode())
5199 VecIn1 = ExtractedFromVec;
5200 else if (VecIn1 != ExtractedFromVec) {
5201 if (!VecIn2.getNode())
5202 VecIn2 = ExtractedFromVec;
5203 else if (VecIn2 != ExtractedFromVec)
5204 // Quit if more than 2 vectors to shuffle
5208 if (ExtractedFromVec == VecIn1)
5210 else if (ExtractedFromVec == VecIn2)
5211 Mask[i] = Idx + NumElems;
5214 if (!VecIn1.getNode())
5217 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5218 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5219 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5220 unsigned Idx = InsertIndices[i];
5221 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5222 DAG.getIntPtrConstant(Idx, DL));
5228 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5229 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5230 Op.getScalarValueSizeInBits() == 1 &&
5231 "Can not convert non-constant vector");
5232 uint64_t Immediate = 0;
5233 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5234 SDValue In = Op.getOperand(idx);
5235 if (In.getOpcode() != ISD::UNDEF)
5236 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5240 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5241 return DAG.getConstant(Immediate, dl, VT);
5243 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5245 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5247 MVT VT = Op.getSimpleValueType();
5248 assert((VT.getVectorElementType() == MVT::i1) &&
5249 "Unexpected type in LowerBUILD_VECTORvXi1!");
5252 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5253 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5254 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5255 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5258 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5259 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5260 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5261 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5264 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5265 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5266 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5267 return DAG.getBitcast(VT, Imm);
5268 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5269 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5270 DAG.getIntPtrConstant(0, dl));
5273 // Vector has one or more non-const elements
5274 uint64_t Immediate = 0;
5275 SmallVector<unsigned, 16> NonConstIdx;
5276 bool IsSplat = true;
5277 bool HasConstElts = false;
5279 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5280 SDValue In = Op.getOperand(idx);
5281 if (In.getOpcode() == ISD::UNDEF)
5283 if (!isa<ConstantSDNode>(In))
5284 NonConstIdx.push_back(idx);
5286 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5287 HasConstElts = true;
5291 else if (In != Op.getOperand(SplatIdx))
5295 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5297 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5298 DAG.getConstant(1, dl, VT),
5299 DAG.getConstant(0, dl, VT));
5301 // insert elements one by one
5305 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5306 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5308 else if (HasConstElts)
5309 Imm = DAG.getConstant(0, dl, VT);
5311 Imm = DAG.getUNDEF(VT);
5312 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5313 DstVec = DAG.getBitcast(VT, Imm);
5315 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5316 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5317 DAG.getIntPtrConstant(0, dl));
5320 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5321 unsigned InsertIdx = NonConstIdx[i];
5322 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5323 Op.getOperand(InsertIdx),
5324 DAG.getIntPtrConstant(InsertIdx, dl));
5329 /// \brief Return true if \p N implements a horizontal binop and return the
5330 /// operands for the horizontal binop into V0 and V1.
5332 /// This is a helper function of LowerToHorizontalOp().
5333 /// This function checks that the build_vector \p N in input implements a
5334 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5335 /// operation to match.
5336 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5337 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5338 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5341 /// This function only analyzes elements of \p N whose indices are
5342 /// in range [BaseIdx, LastIdx).
5343 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5345 unsigned BaseIdx, unsigned LastIdx,
5346 SDValue &V0, SDValue &V1) {
5347 EVT VT = N->getValueType(0);
5349 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5350 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5351 "Invalid Vector in input!");
5353 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5354 bool CanFold = true;
5355 unsigned ExpectedVExtractIdx = BaseIdx;
5356 unsigned NumElts = LastIdx - BaseIdx;
5357 V0 = DAG.getUNDEF(VT);
5358 V1 = DAG.getUNDEF(VT);
5360 // Check if N implements a horizontal binop.
5361 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5362 SDValue Op = N->getOperand(i + BaseIdx);
5365 if (Op->getOpcode() == ISD::UNDEF) {
5366 // Update the expected vector extract index.
5367 if (i * 2 == NumElts)
5368 ExpectedVExtractIdx = BaseIdx;
5369 ExpectedVExtractIdx += 2;
5373 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5378 SDValue Op0 = Op.getOperand(0);
5379 SDValue Op1 = Op.getOperand(1);
5381 // Try to match the following pattern:
5382 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5383 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5384 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5385 Op0.getOperand(0) == Op1.getOperand(0) &&
5386 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5387 isa<ConstantSDNode>(Op1.getOperand(1)));
5391 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5392 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5394 if (i * 2 < NumElts) {
5395 if (V0.getOpcode() == ISD::UNDEF) {
5396 V0 = Op0.getOperand(0);
5397 if (V0.getValueType() != VT)
5401 if (V1.getOpcode() == ISD::UNDEF) {
5402 V1 = Op0.getOperand(0);
5403 if (V1.getValueType() != VT)
5406 if (i * 2 == NumElts)
5407 ExpectedVExtractIdx = BaseIdx;
5410 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5411 if (I0 == ExpectedVExtractIdx)
5412 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5413 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5414 // Try to match the following dag sequence:
5415 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5416 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5420 ExpectedVExtractIdx += 2;
5426 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5427 /// a concat_vector.
5429 /// This is a helper function of LowerToHorizontalOp().
5430 /// This function expects two 256-bit vectors called V0 and V1.
5431 /// At first, each vector is split into two separate 128-bit vectors.
5432 /// Then, the resulting 128-bit vectors are used to implement two
5433 /// horizontal binary operations.
5435 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5437 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5438 /// the two new horizontal binop.
5439 /// When Mode is set, the first horizontal binop dag node would take as input
5440 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5441 /// horizontal binop dag node would take as input the lower 128-bit of V1
5442 /// and the upper 128-bit of V1.
5444 /// HADD V0_LO, V0_HI
5445 /// HADD V1_LO, V1_HI
5447 /// Otherwise, the first horizontal binop dag node takes as input the lower
5448 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5449 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5451 /// HADD V0_LO, V1_LO
5452 /// HADD V0_HI, V1_HI
5454 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5455 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5456 /// the upper 128-bits of the result.
5457 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5458 SDLoc DL, SelectionDAG &DAG,
5459 unsigned X86Opcode, bool Mode,
5460 bool isUndefLO, bool isUndefHI) {
5461 EVT VT = V0.getValueType();
5462 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5463 "Invalid nodes in input!");
5465 unsigned NumElts = VT.getVectorNumElements();
5466 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5467 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5468 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5469 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5470 EVT NewVT = V0_LO.getValueType();
5472 SDValue LO = DAG.getUNDEF(NewVT);
5473 SDValue HI = DAG.getUNDEF(NewVT);
5476 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5477 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5478 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5479 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5480 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5482 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5483 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5484 V1_LO->getOpcode() != ISD::UNDEF))
5485 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5487 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5488 V1_HI->getOpcode() != ISD::UNDEF))
5489 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5492 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5495 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5497 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5498 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5499 EVT VT = BV->getValueType(0);
5500 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5501 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5505 unsigned NumElts = VT.getVectorNumElements();
5506 SDValue InVec0 = DAG.getUNDEF(VT);
5507 SDValue InVec1 = DAG.getUNDEF(VT);
5509 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5510 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5512 // Odd-numbered elements in the input build vector are obtained from
5513 // adding two integer/float elements.
5514 // Even-numbered elements in the input build vector are obtained from
5515 // subtracting two integer/float elements.
5516 unsigned ExpectedOpcode = ISD::FSUB;
5517 unsigned NextExpectedOpcode = ISD::FADD;
5518 bool AddFound = false;
5519 bool SubFound = false;
5521 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5522 SDValue Op = BV->getOperand(i);
5524 // Skip 'undef' values.
5525 unsigned Opcode = Op.getOpcode();
5526 if (Opcode == ISD::UNDEF) {
5527 std::swap(ExpectedOpcode, NextExpectedOpcode);
5531 // Early exit if we found an unexpected opcode.
5532 if (Opcode != ExpectedOpcode)
5535 SDValue Op0 = Op.getOperand(0);
5536 SDValue Op1 = Op.getOperand(1);
5538 // Try to match the following pattern:
5539 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5540 // Early exit if we cannot match that sequence.
5541 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5542 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5543 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5544 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5545 Op0.getOperand(1) != Op1.getOperand(1))
5548 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5552 // We found a valid add/sub node. Update the information accordingly.
5558 // Update InVec0 and InVec1.
5559 if (InVec0.getOpcode() == ISD::UNDEF) {
5560 InVec0 = Op0.getOperand(0);
5561 if (InVec0.getValueType() != VT)
5564 if (InVec1.getOpcode() == ISD::UNDEF) {
5565 InVec1 = Op1.getOperand(0);
5566 if (InVec1.getValueType() != VT)
5570 // Make sure that operands in input to each add/sub node always
5571 // come from a same pair of vectors.
5572 if (InVec0 != Op0.getOperand(0)) {
5573 if (ExpectedOpcode == ISD::FSUB)
5576 // FADD is commutable. Try to commute the operands
5577 // and then test again.
5578 std::swap(Op0, Op1);
5579 if (InVec0 != Op0.getOperand(0))
5583 if (InVec1 != Op1.getOperand(0))
5586 // Update the pair of expected opcodes.
5587 std::swap(ExpectedOpcode, NextExpectedOpcode);
5590 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5591 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5592 InVec1.getOpcode() != ISD::UNDEF)
5593 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5598 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5599 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5600 const X86Subtarget *Subtarget,
5601 SelectionDAG &DAG) {
5602 EVT VT = BV->getValueType(0);
5603 unsigned NumElts = VT.getVectorNumElements();
5604 unsigned NumUndefsLO = 0;
5605 unsigned NumUndefsHI = 0;
5606 unsigned Half = NumElts/2;
5608 // Count the number of UNDEF operands in the build_vector in input.
5609 for (unsigned i = 0, e = Half; i != e; ++i)
5610 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5613 for (unsigned i = Half, e = NumElts; i != e; ++i)
5614 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5617 // Early exit if this is either a build_vector of all UNDEFs or all the
5618 // operands but one are UNDEF.
5619 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5623 SDValue InVec0, InVec1;
5624 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5625 // Try to match an SSE3 float HADD/HSUB.
5626 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5627 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5629 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5630 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5631 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5632 // Try to match an SSSE3 integer HADD/HSUB.
5633 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5634 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5636 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5637 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5640 if (!Subtarget->hasAVX())
5643 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5644 // Try to match an AVX horizontal add/sub of packed single/double
5645 // precision floating point values from 256-bit vectors.
5646 SDValue InVec2, InVec3;
5647 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5648 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5649 ((InVec0.getOpcode() == ISD::UNDEF ||
5650 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5651 ((InVec1.getOpcode() == ISD::UNDEF ||
5652 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5653 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5655 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5656 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5657 ((InVec0.getOpcode() == ISD::UNDEF ||
5658 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5659 ((InVec1.getOpcode() == ISD::UNDEF ||
5660 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5661 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5662 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5663 // Try to match an AVX2 horizontal add/sub of signed integers.
5664 SDValue InVec2, InVec3;
5666 bool CanFold = true;
5668 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5669 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5670 ((InVec0.getOpcode() == ISD::UNDEF ||
5671 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5672 ((InVec1.getOpcode() == ISD::UNDEF ||
5673 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5674 X86Opcode = X86ISD::HADD;
5675 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5676 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5677 ((InVec0.getOpcode() == ISD::UNDEF ||
5678 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5679 ((InVec1.getOpcode() == ISD::UNDEF ||
5680 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5681 X86Opcode = X86ISD::HSUB;
5686 // Fold this build_vector into a single horizontal add/sub.
5687 // Do this only if the target has AVX2.
5688 if (Subtarget->hasAVX2())
5689 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5691 // Do not try to expand this build_vector into a pair of horizontal
5692 // add/sub if we can emit a pair of scalar add/sub.
5693 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5696 // Convert this build_vector into a pair of horizontal binop followed by
5698 bool isUndefLO = NumUndefsLO == Half;
5699 bool isUndefHI = NumUndefsHI == Half;
5700 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5701 isUndefLO, isUndefHI);
5705 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5706 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5708 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5709 X86Opcode = X86ISD::HADD;
5710 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5711 X86Opcode = X86ISD::HSUB;
5712 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5713 X86Opcode = X86ISD::FHADD;
5714 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5715 X86Opcode = X86ISD::FHSUB;
5719 // Don't try to expand this build_vector into a pair of horizontal add/sub
5720 // if we can simply emit a pair of scalar add/sub.
5721 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5724 // Convert this build_vector into two horizontal add/sub followed by
5726 bool isUndefLO = NumUndefsLO == Half;
5727 bool isUndefHI = NumUndefsHI == Half;
5728 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5729 isUndefLO, isUndefHI);
5736 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5739 MVT VT = Op.getSimpleValueType();
5740 MVT ExtVT = VT.getVectorElementType();
5741 unsigned NumElems = Op.getNumOperands();
5743 // Generate vectors for predicate vectors.
5744 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5745 return LowerBUILD_VECTORvXi1(Op, DAG);
5747 // Vectors containing all zeros can be matched by pxor and xorps later
5748 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5749 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5750 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5751 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5754 return getZeroVector(VT, Subtarget, DAG, dl);
5757 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5758 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5759 // vpcmpeqd on 256-bit vectors.
5760 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5761 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5764 if (!VT.is512BitVector())
5765 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5768 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5769 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5771 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5772 return HorizontalOp;
5773 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5776 unsigned EVTBits = ExtVT.getSizeInBits();
5778 unsigned NumZero = 0;
5779 unsigned NumNonZero = 0;
5780 unsigned NonZeros = 0;
5781 bool IsAllConstants = true;
5782 SmallSet<SDValue, 8> Values;
5783 for (unsigned i = 0; i < NumElems; ++i) {
5784 SDValue Elt = Op.getOperand(i);
5785 if (Elt.getOpcode() == ISD::UNDEF)
5788 if (Elt.getOpcode() != ISD::Constant &&
5789 Elt.getOpcode() != ISD::ConstantFP)
5790 IsAllConstants = false;
5791 if (X86::isZeroNode(Elt))
5794 NonZeros |= (1 << i);
5799 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5800 if (NumNonZero == 0)
5801 return DAG.getUNDEF(VT);
5803 // Special case for single non-zero, non-undef, element.
5804 if (NumNonZero == 1) {
5805 unsigned Idx = countTrailingZeros(NonZeros);
5806 SDValue Item = Op.getOperand(Idx);
5808 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5809 // the value are obviously zero, truncate the value to i32 and do the
5810 // insertion that way. Only do this if the value is non-constant or if the
5811 // value is a constant being inserted into element 0. It is cheaper to do
5812 // a constant pool load than it is to do a movd + shuffle.
5813 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5814 (!IsAllConstants || Idx == 0)) {
5815 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5817 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5818 EVT VecVT = MVT::v4i32;
5820 // Truncate the value (which may itself be a constant) to i32, and
5821 // convert it to a vector with movd (S2V+shuffle to zero extend).
5822 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5823 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5824 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5825 Item, Idx * 2, true, Subtarget, DAG));
5829 // If we have a constant or non-constant insertion into the low element of
5830 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5831 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5832 // depending on what the source datatype is.
5835 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5837 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5838 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5839 if (VT.is512BitVector()) {
5840 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5841 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5842 Item, DAG.getIntPtrConstant(0, dl));
5844 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5845 "Expected an SSE value type!");
5846 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5847 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5848 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5851 // We can't directly insert an i8 or i16 into a vector, so zero extend
5853 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5854 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5855 if (VT.is256BitVector()) {
5856 if (Subtarget->hasAVX()) {
5857 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5858 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5860 // Without AVX, we need to extend to a 128-bit vector and then
5861 // insert into the 256-bit vector.
5862 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5863 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5864 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5867 assert(VT.is128BitVector() && "Expected an SSE value type!");
5868 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5869 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5871 return DAG.getBitcast(VT, Item);
5875 // Is it a vector logical left shift?
5876 if (NumElems == 2 && Idx == 1 &&
5877 X86::isZeroNode(Op.getOperand(0)) &&
5878 !X86::isZeroNode(Op.getOperand(1))) {
5879 unsigned NumBits = VT.getSizeInBits();
5880 return getVShift(true, VT,
5881 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5882 VT, Op.getOperand(1)),
5883 NumBits/2, DAG, *this, dl);
5886 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5889 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5890 // is a non-constant being inserted into an element other than the low one,
5891 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5892 // movd/movss) to move this into the low element, then shuffle it into
5894 if (EVTBits == 32) {
5895 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5896 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5900 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5901 if (Values.size() == 1) {
5902 if (EVTBits == 32) {
5903 // Instead of a shuffle like this:
5904 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5905 // Check if it's possible to issue this instead.
5906 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5907 unsigned Idx = countTrailingZeros(NonZeros);
5908 SDValue Item = Op.getOperand(Idx);
5909 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5910 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5915 // A vector full of immediates; various special cases are already
5916 // handled, so this is best done with a single constant-pool load.
5920 // For AVX-length vectors, see if we can use a vector load to get all of the
5921 // elements, otherwise build the individual 128-bit pieces and use
5922 // shuffles to put them in place.
5923 if (VT.is256BitVector() || VT.is512BitVector()) {
5924 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5926 // Check for a build vector of consecutive loads.
5927 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
5930 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5932 // Build both the lower and upper subvector.
5933 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5934 makeArrayRef(&V[0], NumElems/2));
5935 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
5936 makeArrayRef(&V[NumElems / 2], NumElems/2));
5938 // Recreate the wider vector with the lower and upper part.
5939 if (VT.is256BitVector())
5940 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5941 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5944 // Let legalizer expand 2-wide build_vectors.
5945 if (EVTBits == 64) {
5946 if (NumNonZero == 1) {
5947 // One half is zero or undef.
5948 unsigned Idx = countTrailingZeros(NonZeros);
5949 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5950 Op.getOperand(Idx));
5951 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5956 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5957 if (EVTBits == 8 && NumElems == 16)
5958 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5962 if (EVTBits == 16 && NumElems == 8)
5963 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5967 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
5968 if (EVTBits == 32 && NumElems == 4)
5969 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
5972 // If element VT is == 32 bits, turn it into a number of shuffles.
5973 SmallVector<SDValue, 8> V(NumElems);
5974 if (NumElems == 4 && NumZero > 0) {
5975 for (unsigned i = 0; i < 4; ++i) {
5976 bool isZero = !(NonZeros & (1 << i));
5978 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5980 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5983 for (unsigned i = 0; i < 2; ++i) {
5984 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5987 V[i] = V[i*2]; // Must be a zero vector.
5990 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5993 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5996 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6001 bool Reverse1 = (NonZeros & 0x3) == 2;
6002 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6006 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6007 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6009 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6012 if (Values.size() > 1 && VT.is128BitVector()) {
6013 // Check for a build vector of consecutive loads.
6014 for (unsigned i = 0; i < NumElems; ++i)
6015 V[i] = Op.getOperand(i);
6017 // Check for elements which are consecutive loads.
6018 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6021 // Check for a build vector from mostly shuffle plus few inserting.
6022 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6025 // For SSE 4.1, use insertps to put the high elements into the low element.
6026 if (Subtarget->hasSSE41()) {
6028 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6029 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6031 Result = DAG.getUNDEF(VT);
6033 for (unsigned i = 1; i < NumElems; ++i) {
6034 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6035 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6036 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6041 // Otherwise, expand into a number of unpckl*, start by extending each of
6042 // our (non-undef) elements to the full vector width with the element in the
6043 // bottom slot of the vector (which generates no code for SSE).
6044 for (unsigned i = 0; i < NumElems; ++i) {
6045 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6046 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6048 V[i] = DAG.getUNDEF(VT);
6051 // Next, we iteratively mix elements, e.g. for v4f32:
6052 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6053 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6054 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6055 unsigned EltStride = NumElems >> 1;
6056 while (EltStride != 0) {
6057 for (unsigned i = 0; i < EltStride; ++i) {
6058 // If V[i+EltStride] is undef and this is the first round of mixing,
6059 // then it is safe to just drop this shuffle: V[i] is already in the
6060 // right place, the one element (since it's the first round) being
6061 // inserted as undef can be dropped. This isn't safe for successive
6062 // rounds because they will permute elements within both vectors.
6063 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6064 EltStride == NumElems/2)
6067 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6076 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6077 // to create 256-bit vectors from two other 128-bit ones.
6078 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6080 MVT ResVT = Op.getSimpleValueType();
6082 assert((ResVT.is256BitVector() ||
6083 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6085 SDValue V1 = Op.getOperand(0);
6086 SDValue V2 = Op.getOperand(1);
6087 unsigned NumElems = ResVT.getVectorNumElements();
6088 if (ResVT.is256BitVector())
6089 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6091 if (Op.getNumOperands() == 4) {
6092 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6093 ResVT.getVectorNumElements()/2);
6094 SDValue V3 = Op.getOperand(2);
6095 SDValue V4 = Op.getOperand(3);
6096 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6097 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6099 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6102 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6103 const X86Subtarget *Subtarget,
6104 SelectionDAG & DAG) {
6106 MVT ResVT = Op.getSimpleValueType();
6107 unsigned NumOfOperands = Op.getNumOperands();
6109 assert(isPowerOf2_32(NumOfOperands) &&
6110 "Unexpected number of operands in CONCAT_VECTORS");
6112 if (NumOfOperands > 2) {
6113 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6114 ResVT.getVectorNumElements()/2);
6115 SmallVector<SDValue, 2> Ops;
6116 for (unsigned i = 0; i < NumOfOperands/2; i++)
6117 Ops.push_back(Op.getOperand(i));
6118 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6120 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6121 Ops.push_back(Op.getOperand(i));
6122 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6123 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6126 SDValue V1 = Op.getOperand(0);
6127 SDValue V2 = Op.getOperand(1);
6128 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6129 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6131 if (IsZeroV1 && IsZeroV2)
6132 return getZeroVector(ResVT, Subtarget, DAG, dl);
6134 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6135 SDValue Undef = DAG.getUNDEF(ResVT);
6136 unsigned NumElems = ResVT.getVectorNumElements();
6137 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6139 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6140 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6144 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6145 // Zero the upper bits of V1
6146 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6147 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6150 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6153 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6154 const X86Subtarget *Subtarget,
6155 SelectionDAG &DAG) {
6156 MVT VT = Op.getSimpleValueType();
6157 if (VT.getVectorElementType() == MVT::i1)
6158 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6160 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6161 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6162 Op.getNumOperands() == 4)));
6164 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6165 // from two other 128-bit ones.
6167 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6168 return LowerAVXCONCAT_VECTORS(Op, DAG);
6172 //===----------------------------------------------------------------------===//
6173 // Vector shuffle lowering
6175 // This is an experimental code path for lowering vector shuffles on x86. It is
6176 // designed to handle arbitrary vector shuffles and blends, gracefully
6177 // degrading performance as necessary. It works hard to recognize idiomatic
6178 // shuffles and lower them to optimal instruction patterns without leaving
6179 // a framework that allows reasonably efficient handling of all vector shuffle
6181 //===----------------------------------------------------------------------===//
6183 /// \brief Tiny helper function to identify a no-op mask.
6185 /// This is a somewhat boring predicate function. It checks whether the mask
6186 /// array input, which is assumed to be a single-input shuffle mask of the kind
6187 /// used by the X86 shuffle instructions (not a fully general
6188 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6189 /// in-place shuffle are 'no-op's.
6190 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6191 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6192 if (Mask[i] != -1 && Mask[i] != i)
6197 /// \brief Helper function to classify a mask as a single-input mask.
6199 /// This isn't a generic single-input test because in the vector shuffle
6200 /// lowering we canonicalize single inputs to be the first input operand. This
6201 /// means we can more quickly test for a single input by only checking whether
6202 /// an input from the second operand exists. We also assume that the size of
6203 /// mask corresponds to the size of the input vectors which isn't true in the
6204 /// fully general case.
6205 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6207 if (M >= (int)Mask.size())
6212 /// \brief Test whether there are elements crossing 128-bit lanes in this
6215 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6216 /// and we routinely test for these.
6217 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6218 int LaneSize = 128 / VT.getScalarSizeInBits();
6219 int Size = Mask.size();
6220 for (int i = 0; i < Size; ++i)
6221 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6226 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6228 /// This checks a shuffle mask to see if it is performing the same
6229 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6230 /// that it is also not lane-crossing. It may however involve a blend from the
6231 /// same lane of a second vector.
6233 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6234 /// non-trivial to compute in the face of undef lanes. The representation is
6235 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6236 /// entries from both V1 and V2 inputs to the wider mask.
6238 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6239 SmallVectorImpl<int> &RepeatedMask) {
6240 int LaneSize = 128 / VT.getScalarSizeInBits();
6241 RepeatedMask.resize(LaneSize, -1);
6242 int Size = Mask.size();
6243 for (int i = 0; i < Size; ++i) {
6246 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6247 // This entry crosses lanes, so there is no way to model this shuffle.
6250 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6251 if (RepeatedMask[i % LaneSize] == -1)
6252 // This is the first non-undef entry in this slot of a 128-bit lane.
6253 RepeatedMask[i % LaneSize] =
6254 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6255 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6256 // Found a mismatch with the repeated mask.
6262 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6265 /// This is a fast way to test a shuffle mask against a fixed pattern:
6267 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6269 /// It returns true if the mask is exactly as wide as the argument list, and
6270 /// each element of the mask is either -1 (signifying undef) or the value given
6271 /// in the argument.
6272 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6273 ArrayRef<int> ExpectedMask) {
6274 if (Mask.size() != ExpectedMask.size())
6277 int Size = Mask.size();
6279 // If the values are build vectors, we can look through them to find
6280 // equivalent inputs that make the shuffles equivalent.
6281 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6282 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6284 for (int i = 0; i < Size; ++i)
6285 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6286 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6287 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6288 if (!MaskBV || !ExpectedBV ||
6289 MaskBV->getOperand(Mask[i] % Size) !=
6290 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6297 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6299 /// This helper function produces an 8-bit shuffle immediate corresponding to
6300 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6301 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6304 /// NB: We rely heavily on "undef" masks preserving the input lane.
6305 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6306 SelectionDAG &DAG) {
6307 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6308 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6309 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6310 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6311 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6314 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6315 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6316 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6317 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6318 return DAG.getConstant(Imm, DL, MVT::i8);
6321 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6323 /// This is used as a fallback approach when first class blend instructions are
6324 /// unavailable. Currently it is only suitable for integer vectors, but could
6325 /// be generalized for floating point vectors if desirable.
6326 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6327 SDValue V2, ArrayRef<int> Mask,
6328 SelectionDAG &DAG) {
6329 assert(VT.isInteger() && "Only supports integer vector types!");
6330 MVT EltVT = VT.getScalarType();
6331 int NumEltBits = EltVT.getSizeInBits();
6332 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6333 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6335 SmallVector<SDValue, 16> MaskOps;
6336 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6337 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6338 return SDValue(); // Shuffled input!
6339 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6342 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6343 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6344 // We have to cast V2 around.
6345 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6346 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6347 DAG.getBitcast(MaskVT, V1Mask),
6348 DAG.getBitcast(MaskVT, V2)));
6349 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6352 /// \brief Try to emit a blend instruction for a shuffle.
6354 /// This doesn't do any checks for the availability of instructions for blending
6355 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6356 /// be matched in the backend with the type given. What it does check for is
6357 /// that the shuffle mask is in fact a blend.
6358 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6359 SDValue V2, ArrayRef<int> Mask,
6360 const X86Subtarget *Subtarget,
6361 SelectionDAG &DAG) {
6362 unsigned BlendMask = 0;
6363 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6364 if (Mask[i] >= Size) {
6365 if (Mask[i] != i + Size)
6366 return SDValue(); // Shuffled V2 input!
6367 BlendMask |= 1u << i;
6370 if (Mask[i] >= 0 && Mask[i] != i)
6371 return SDValue(); // Shuffled V1 input!
6373 switch (VT.SimpleTy) {
6378 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6379 DAG.getConstant(BlendMask, DL, MVT::i8));
6383 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6387 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6388 // that instruction.
6389 if (Subtarget->hasAVX2()) {
6390 // Scale the blend by the number of 32-bit dwords per element.
6391 int Scale = VT.getScalarSizeInBits() / 32;
6393 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6394 if (Mask[i] >= Size)
6395 for (int j = 0; j < Scale; ++j)
6396 BlendMask |= 1u << (i * Scale + j);
6398 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6399 V1 = DAG.getBitcast(BlendVT, V1);
6400 V2 = DAG.getBitcast(BlendVT, V2);
6401 return DAG.getBitcast(
6402 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6403 DAG.getConstant(BlendMask, DL, MVT::i8)));
6407 // For integer shuffles we need to expand the mask and cast the inputs to
6408 // v8i16s prior to blending.
6409 int Scale = 8 / VT.getVectorNumElements();
6411 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6412 if (Mask[i] >= Size)
6413 for (int j = 0; j < Scale; ++j)
6414 BlendMask |= 1u << (i * Scale + j);
6416 V1 = DAG.getBitcast(MVT::v8i16, V1);
6417 V2 = DAG.getBitcast(MVT::v8i16, V2);
6418 return DAG.getBitcast(VT,
6419 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6420 DAG.getConstant(BlendMask, DL, MVT::i8)));
6424 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6425 SmallVector<int, 8> RepeatedMask;
6426 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6427 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6428 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6430 for (int i = 0; i < 8; ++i)
6431 if (RepeatedMask[i] >= 16)
6432 BlendMask |= 1u << i;
6433 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6434 DAG.getConstant(BlendMask, DL, MVT::i8));
6440 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6441 "256-bit byte-blends require AVX2 support!");
6443 // Scale the blend by the number of bytes per element.
6444 int Scale = VT.getScalarSizeInBits() / 8;
6446 // This form of blend is always done on bytes. Compute the byte vector
6448 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6450 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6451 // mix of LLVM's code generator and the x86 backend. We tell the code
6452 // generator that boolean values in the elements of an x86 vector register
6453 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6454 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6455 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6456 // of the element (the remaining are ignored) and 0 in that high bit would
6457 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6458 // the LLVM model for boolean values in vector elements gets the relevant
6459 // bit set, it is set backwards and over constrained relative to x86's
6461 SmallVector<SDValue, 32> VSELECTMask;
6462 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6463 for (int j = 0; j < Scale; ++j)
6464 VSELECTMask.push_back(
6465 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6466 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6469 V1 = DAG.getBitcast(BlendVT, V1);
6470 V2 = DAG.getBitcast(BlendVT, V2);
6471 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6472 DAG.getNode(ISD::BUILD_VECTOR, DL,
6473 BlendVT, VSELECTMask),
6478 llvm_unreachable("Not a supported integer vector type!");
6482 /// \brief Try to lower as a blend of elements from two inputs followed by
6483 /// a single-input permutation.
6485 /// This matches the pattern where we can blend elements from two inputs and
6486 /// then reduce the shuffle to a single-input permutation.
6487 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6490 SelectionDAG &DAG) {
6491 // We build up the blend mask while checking whether a blend is a viable way
6492 // to reduce the shuffle.
6493 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6494 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6496 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6500 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6502 if (BlendMask[Mask[i] % Size] == -1)
6503 BlendMask[Mask[i] % Size] = Mask[i];
6504 else if (BlendMask[Mask[i] % Size] != Mask[i])
6505 return SDValue(); // Can't blend in the needed input!
6507 PermuteMask[i] = Mask[i] % Size;
6510 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6511 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6514 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6515 /// blends and permutes.
6517 /// This matches the extremely common pattern for handling combined
6518 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6519 /// operations. It will try to pick the best arrangement of shuffles and
6521 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6525 SelectionDAG &DAG) {
6526 // Shuffle the input elements into the desired positions in V1 and V2 and
6527 // blend them together.
6528 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6529 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6530 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6531 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6532 if (Mask[i] >= 0 && Mask[i] < Size) {
6533 V1Mask[i] = Mask[i];
6535 } else if (Mask[i] >= Size) {
6536 V2Mask[i] = Mask[i] - Size;
6537 BlendMask[i] = i + Size;
6540 // Try to lower with the simpler initial blend strategy unless one of the
6541 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6542 // shuffle may be able to fold with a load or other benefit. However, when
6543 // we'll have to do 2x as many shuffles in order to achieve this, blending
6544 // first is a better strategy.
6545 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6546 if (SDValue BlendPerm =
6547 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6550 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6551 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6552 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6555 /// \brief Try to lower a vector shuffle as a byte rotation.
6557 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6558 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6559 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6560 /// try to generically lower a vector shuffle through such an pattern. It
6561 /// does not check for the profitability of lowering either as PALIGNR or
6562 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6563 /// This matches shuffle vectors that look like:
6565 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6567 /// Essentially it concatenates V1 and V2, shifts right by some number of
6568 /// elements, and takes the low elements as the result. Note that while this is
6569 /// specified as a *right shift* because x86 is little-endian, it is a *left
6570 /// rotate* of the vector lanes.
6571 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6574 const X86Subtarget *Subtarget,
6575 SelectionDAG &DAG) {
6576 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6578 int NumElts = Mask.size();
6579 int NumLanes = VT.getSizeInBits() / 128;
6580 int NumLaneElts = NumElts / NumLanes;
6582 // We need to detect various ways of spelling a rotation:
6583 // [11, 12, 13, 14, 15, 0, 1, 2]
6584 // [-1, 12, 13, 14, -1, -1, 1, -1]
6585 // [-1, -1, -1, -1, -1, -1, 1, 2]
6586 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6587 // [-1, 4, 5, 6, -1, -1, 9, -1]
6588 // [-1, 4, 5, 6, -1, -1, -1, -1]
6591 for (int l = 0; l < NumElts; l += NumLaneElts) {
6592 for (int i = 0; i < NumLaneElts; ++i) {
6593 if (Mask[l + i] == -1)
6595 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6597 // Get the mod-Size index and lane correct it.
6598 int LaneIdx = (Mask[l + i] % NumElts) - l;
6599 // Make sure it was in this lane.
6600 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6603 // Determine where a rotated vector would have started.
6604 int StartIdx = i - LaneIdx;
6606 // The identity rotation isn't interesting, stop.
6609 // If we found the tail of a vector the rotation must be the missing
6610 // front. If we found the head of a vector, it must be how much of the
6612 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6615 Rotation = CandidateRotation;
6616 else if (Rotation != CandidateRotation)
6617 // The rotations don't match, so we can't match this mask.
6620 // Compute which value this mask is pointing at.
6621 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6623 // Compute which of the two target values this index should be assigned
6624 // to. This reflects whether the high elements are remaining or the low
6625 // elements are remaining.
6626 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6628 // Either set up this value if we've not encountered it before, or check
6629 // that it remains consistent.
6632 else if (TargetV != MaskV)
6633 // This may be a rotation, but it pulls from the inputs in some
6634 // unsupported interleaving.
6639 // Check that we successfully analyzed the mask, and normalize the results.
6640 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6641 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6647 // The actual rotate instruction rotates bytes, so we need to scale the
6648 // rotation based on how many bytes are in the vector lane.
6649 int Scale = 16 / NumLaneElts;
6651 // SSSE3 targets can use the palignr instruction.
6652 if (Subtarget->hasSSSE3()) {
6653 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6654 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6655 Lo = DAG.getBitcast(AlignVT, Lo);
6656 Hi = DAG.getBitcast(AlignVT, Hi);
6658 return DAG.getBitcast(
6659 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6660 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6663 assert(VT.getSizeInBits() == 128 &&
6664 "Rotate-based lowering only supports 128-bit lowering!");
6665 assert(Mask.size() <= 16 &&
6666 "Can shuffle at most 16 bytes in a 128-bit vector!");
6668 // Default SSE2 implementation
6669 int LoByteShift = 16 - Rotation * Scale;
6670 int HiByteShift = Rotation * Scale;
6672 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6673 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6674 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6676 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6677 DAG.getConstant(LoByteShift, DL, MVT::i8));
6678 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6679 DAG.getConstant(HiByteShift, DL, MVT::i8));
6680 return DAG.getBitcast(VT,
6681 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6684 /// \brief Compute whether each element of a shuffle is zeroable.
6686 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6687 /// Either it is an undef element in the shuffle mask, the element of the input
6688 /// referenced is undef, or the element of the input referenced is known to be
6689 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6690 /// as many lanes with this technique as possible to simplify the remaining
6692 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6693 SDValue V1, SDValue V2) {
6694 SmallBitVector Zeroable(Mask.size(), false);
6696 while (V1.getOpcode() == ISD::BITCAST)
6697 V1 = V1->getOperand(0);
6698 while (V2.getOpcode() == ISD::BITCAST)
6699 V2 = V2->getOperand(0);
6701 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6702 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6704 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6706 // Handle the easy cases.
6707 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6712 // If this is an index into a build_vector node (which has the same number
6713 // of elements), dig out the input value and use it.
6714 SDValue V = M < Size ? V1 : V2;
6715 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6718 SDValue Input = V.getOperand(M % Size);
6719 // The UNDEF opcode check really should be dead code here, but not quite
6720 // worth asserting on (it isn't invalid, just unexpected).
6721 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6728 /// \brief Try to emit a bitmask instruction for a shuffle.
6730 /// This handles cases where we can model a blend exactly as a bitmask due to
6731 /// one of the inputs being zeroable.
6732 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6733 SDValue V2, ArrayRef<int> Mask,
6734 SelectionDAG &DAG) {
6735 MVT EltVT = VT.getScalarType();
6736 int NumEltBits = EltVT.getSizeInBits();
6737 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6738 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6739 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6741 if (EltVT.isFloatingPoint()) {
6742 Zero = DAG.getBitcast(EltVT, Zero);
6743 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6745 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6746 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6748 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6751 if (Mask[i] % Size != i)
6752 return SDValue(); // Not a blend.
6754 V = Mask[i] < Size ? V1 : V2;
6755 else if (V != (Mask[i] < Size ? V1 : V2))
6756 return SDValue(); // Can only let one input through the mask.
6758 VMaskOps[i] = AllOnes;
6761 return SDValue(); // No non-zeroable elements!
6763 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6764 V = DAG.getNode(VT.isFloatingPoint()
6765 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6770 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6772 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6773 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6774 /// matches elements from one of the input vectors shuffled to the left or
6775 /// right with zeroable elements 'shifted in'. It handles both the strictly
6776 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6779 /// PSHL : (little-endian) left bit shift.
6780 /// [ zz, 0, zz, 2 ]
6781 /// [ -1, 4, zz, -1 ]
6782 /// PSRL : (little-endian) right bit shift.
6784 /// [ -1, -1, 7, zz]
6785 /// PSLLDQ : (little-endian) left byte shift
6786 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6787 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6788 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6789 /// PSRLDQ : (little-endian) right byte shift
6790 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6791 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6792 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6793 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6794 SDValue V2, ArrayRef<int> Mask,
6795 SelectionDAG &DAG) {
6796 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6798 int Size = Mask.size();
6799 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6801 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6802 for (int i = 0; i < Size; i += Scale)
6803 for (int j = 0; j < Shift; ++j)
6804 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6810 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6811 for (int i = 0; i != Size; i += Scale) {
6812 unsigned Pos = Left ? i + Shift : i;
6813 unsigned Low = Left ? i : i + Shift;
6814 unsigned Len = Scale - Shift;
6815 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6816 Low + (V == V1 ? 0 : Size)))
6820 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6821 bool ByteShift = ShiftEltBits > 64;
6822 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6823 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6824 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6826 // Normalize the scale for byte shifts to still produce an i64 element
6828 Scale = ByteShift ? Scale / 2 : Scale;
6830 // We need to round trip through the appropriate type for the shift.
6831 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6832 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6833 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6834 "Illegal integer vector type");
6835 V = DAG.getBitcast(ShiftVT, V);
6837 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6838 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6839 return DAG.getBitcast(VT, V);
6842 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6843 // keep doubling the size of the integer elements up to that. We can
6844 // then shift the elements of the integer vector by whole multiples of
6845 // their width within the elements of the larger integer vector. Test each
6846 // multiple to see if we can find a match with the moved element indices
6847 // and that the shifted in elements are all zeroable.
6848 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6849 for (int Shift = 1; Shift != Scale; ++Shift)
6850 for (bool Left : {true, false})
6851 if (CheckZeros(Shift, Scale, Left))
6852 for (SDValue V : {V1, V2})
6853 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6860 /// \brief Lower a vector shuffle as a zero or any extension.
6862 /// Given a specific number of elements, element bit width, and extension
6863 /// stride, produce either a zero or any extension based on the available
6864 /// features of the subtarget.
6865 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6866 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
6867 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6868 assert(Scale > 1 && "Need a scale to extend.");
6869 int NumElements = VT.getVectorNumElements();
6870 int EltBits = VT.getScalarSizeInBits();
6871 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
6872 "Only 8, 16, and 32 bit elements can be extended.");
6873 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
6875 // Found a valid zext mask! Try various lowering strategies based on the
6876 // input type and available ISA extensions.
6877 if (Subtarget->hasSSE41()) {
6878 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
6879 NumElements / Scale);
6880 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
6883 // For any extends we can cheat for larger element sizes and use shuffle
6884 // instructions that can fold with a load and/or copy.
6885 if (AnyExt && EltBits == 32) {
6886 int PSHUFDMask[4] = {0, -1, 1, -1};
6887 return DAG.getBitcast(
6888 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6889 DAG.getBitcast(MVT::v4i32, InputV),
6890 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
6892 if (AnyExt && EltBits == 16 && Scale > 2) {
6893 int PSHUFDMask[4] = {0, -1, 0, -1};
6894 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
6895 DAG.getBitcast(MVT::v4i32, InputV),
6896 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
6897 int PSHUFHWMask[4] = {1, -1, -1, -1};
6898 return DAG.getBitcast(
6899 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
6900 DAG.getBitcast(MVT::v8i16, InputV),
6901 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
6904 // If this would require more than 2 unpack instructions to expand, use
6905 // pshufb when available. We can only use more than 2 unpack instructions
6906 // when zero extending i8 elements which also makes it easier to use pshufb.
6907 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
6908 assert(NumElements == 16 && "Unexpected byte vector width!");
6909 SDValue PSHUFBMask[16];
6910 for (int i = 0; i < 16; ++i)
6912 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
6913 InputV = DAG.getBitcast(MVT::v16i8, InputV);
6914 return DAG.getBitcast(VT,
6915 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
6916 DAG.getNode(ISD::BUILD_VECTOR, DL,
6917 MVT::v16i8, PSHUFBMask)));
6920 // Otherwise emit a sequence of unpacks.
6922 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
6923 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
6924 : getZeroVector(InputVT, Subtarget, DAG, DL);
6925 InputV = DAG.getBitcast(InputVT, InputV);
6926 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
6930 } while (Scale > 1);
6931 return DAG.getBitcast(VT, InputV);
6934 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
6936 /// This routine will try to do everything in its power to cleverly lower
6937 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
6938 /// check for the profitability of this lowering, it tries to aggressively
6939 /// match this pattern. It will use all of the micro-architectural details it
6940 /// can to emit an efficient lowering. It handles both blends with all-zero
6941 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
6942 /// masking out later).
6944 /// The reason we have dedicated lowering for zext-style shuffles is that they
6945 /// are both incredibly common and often quite performance sensitive.
6946 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
6947 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
6948 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
6949 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6951 int Bits = VT.getSizeInBits();
6952 int NumElements = VT.getVectorNumElements();
6953 assert(VT.getScalarSizeInBits() <= 32 &&
6954 "Exceeds 32-bit integer zero extension limit");
6955 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
6957 // Define a helper function to check a particular ext-scale and lower to it if
6959 auto Lower = [&](int Scale) -> SDValue {
6962 for (int i = 0; i < NumElements; ++i) {
6964 continue; // Valid anywhere but doesn't tell us anything.
6965 if (i % Scale != 0) {
6966 // Each of the extended elements need to be zeroable.
6970 // We no longer are in the anyext case.
6975 // Each of the base elements needs to be consecutive indices into the
6976 // same input vector.
6977 SDValue V = Mask[i] < NumElements ? V1 : V2;
6980 else if (InputV != V)
6981 return SDValue(); // Flip-flopping inputs.
6983 if (Mask[i] % NumElements != i / Scale)
6984 return SDValue(); // Non-consecutive strided elements.
6987 // If we fail to find an input, we have a zero-shuffle which should always
6988 // have already been handled.
6989 // FIXME: Maybe handle this here in case during blending we end up with one?
6993 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
6994 DL, VT, Scale, AnyExt, InputV, Subtarget, DAG);
6997 // The widest scale possible for extending is to a 64-bit integer.
6998 assert(Bits % 64 == 0 &&
6999 "The number of bits in a vector must be divisible by 64 on x86!");
7000 int NumExtElements = Bits / 64;
7002 // Each iteration, try extending the elements half as much, but into twice as
7004 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7005 assert(NumElements % NumExtElements == 0 &&
7006 "The input vector size must be divisible by the extended size.");
7007 if (SDValue V = Lower(NumElements / NumExtElements))
7011 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7015 // Returns one of the source operands if the shuffle can be reduced to a
7016 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7017 auto CanZExtLowHalf = [&]() {
7018 for (int i = NumElements / 2; i != NumElements; ++i)
7021 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7023 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7028 if (SDValue V = CanZExtLowHalf()) {
7029 V = DAG.getBitcast(MVT::v2i64, V);
7030 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7031 return DAG.getBitcast(VT, V);
7034 // No viable ext lowering found.
7038 /// \brief Try to get a scalar value for a specific element of a vector.
7040 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7041 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7042 SelectionDAG &DAG) {
7043 MVT VT = V.getSimpleValueType();
7044 MVT EltVT = VT.getVectorElementType();
7045 while (V.getOpcode() == ISD::BITCAST)
7046 V = V.getOperand(0);
7047 // If the bitcasts shift the element size, we can't extract an equivalent
7049 MVT NewVT = V.getSimpleValueType();
7050 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7053 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7054 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7055 // Ensure the scalar operand is the same size as the destination.
7056 // FIXME: Add support for scalar truncation where possible.
7057 SDValue S = V.getOperand(Idx);
7058 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7059 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7065 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7067 /// This is particularly important because the set of instructions varies
7068 /// significantly based on whether the operand is a load or not.
7069 static bool isShuffleFoldableLoad(SDValue V) {
7070 while (V.getOpcode() == ISD::BITCAST)
7071 V = V.getOperand(0);
7073 return ISD::isNON_EXTLoad(V.getNode());
7076 /// \brief Try to lower insertion of a single element into a zero vector.
7078 /// This is a common pattern that we have especially efficient patterns to lower
7079 /// across all subtarget feature sets.
7080 static SDValue lowerVectorShuffleAsElementInsertion(
7081 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7082 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7083 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7085 MVT EltVT = VT.getVectorElementType();
7087 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7088 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7090 bool IsV1Zeroable = true;
7091 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7092 if (i != V2Index && !Zeroable[i]) {
7093 IsV1Zeroable = false;
7097 // Check for a single input from a SCALAR_TO_VECTOR node.
7098 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7099 // all the smarts here sunk into that routine. However, the current
7100 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7101 // vector shuffle lowering is dead.
7102 if (SDValue V2S = getScalarValueForVectorElement(
7103 V2, Mask[V2Index] - Mask.size(), DAG)) {
7104 // We need to zext the scalar if it is smaller than an i32.
7105 V2S = DAG.getBitcast(EltVT, V2S);
7106 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7107 // Using zext to expand a narrow element won't work for non-zero
7112 // Zero-extend directly to i32.
7114 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7116 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7117 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7118 EltVT == MVT::i16) {
7119 // Either not inserting from the low element of the input or the input
7120 // element size is too small to use VZEXT_MOVL to clear the high bits.
7124 if (!IsV1Zeroable) {
7125 // If V1 can't be treated as a zero vector we have fewer options to lower
7126 // this. We can't support integer vectors or non-zero targets cheaply, and
7127 // the V1 elements can't be permuted in any way.
7128 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7129 if (!VT.isFloatingPoint() || V2Index != 0)
7131 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7132 V1Mask[V2Index] = -1;
7133 if (!isNoopShuffleMask(V1Mask))
7135 // This is essentially a special case blend operation, but if we have
7136 // general purpose blend operations, they are always faster. Bail and let
7137 // the rest of the lowering handle these as blends.
7138 if (Subtarget->hasSSE41())
7141 // Otherwise, use MOVSD or MOVSS.
7142 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7143 "Only two types of floating point element types to handle!");
7144 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7148 // This lowering only works for the low element with floating point vectors.
7149 if (VT.isFloatingPoint() && V2Index != 0)
7152 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7154 V2 = DAG.getBitcast(VT, V2);
7157 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7158 // the desired position. Otherwise it is more efficient to do a vector
7159 // shift left. We know that we can do a vector shift left because all
7160 // the inputs are zero.
7161 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7162 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7163 V2Shuffle[V2Index] = 0;
7164 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7166 V2 = DAG.getBitcast(MVT::v2i64, V2);
7168 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7170 V2Index * EltVT.getSizeInBits()/8, DL,
7171 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7172 V2 = DAG.getBitcast(VT, V2);
7178 /// \brief Try to lower broadcast of a single element.
7180 /// For convenience, this code also bundles all of the subtarget feature set
7181 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7182 /// a convenient way to factor it out.
7183 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7185 const X86Subtarget *Subtarget,
7186 SelectionDAG &DAG) {
7187 if (!Subtarget->hasAVX())
7189 if (VT.isInteger() && !Subtarget->hasAVX2())
7192 // Check that the mask is a broadcast.
7193 int BroadcastIdx = -1;
7195 if (M >= 0 && BroadcastIdx == -1)
7197 else if (M >= 0 && M != BroadcastIdx)
7200 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7201 "a sorted mask where the broadcast "
7204 // Go up the chain of (vector) values to find a scalar load that we can
7205 // combine with the broadcast.
7207 switch (V.getOpcode()) {
7208 case ISD::CONCAT_VECTORS: {
7209 int OperandSize = Mask.size() / V.getNumOperands();
7210 V = V.getOperand(BroadcastIdx / OperandSize);
7211 BroadcastIdx %= OperandSize;
7215 case ISD::INSERT_SUBVECTOR: {
7216 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7217 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7221 int BeginIdx = (int)ConstantIdx->getZExtValue();
7223 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7224 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7225 BroadcastIdx -= BeginIdx;
7236 // Check if this is a broadcast of a scalar. We special case lowering
7237 // for scalars so that we can more effectively fold with loads.
7238 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7239 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7240 V = V.getOperand(BroadcastIdx);
7242 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7243 // Only AVX2 has register broadcasts.
7244 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7246 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7247 // We can't broadcast from a vector register without AVX2, and we can only
7248 // broadcast from the zero-element of a vector register.
7252 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7255 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7256 // INSERTPS when the V1 elements are already in the correct locations
7257 // because otherwise we can just always use two SHUFPS instructions which
7258 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7259 // perform INSERTPS if a single V1 element is out of place and all V2
7260 // elements are zeroable.
7261 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7263 SelectionDAG &DAG) {
7264 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7265 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7266 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7267 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7269 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7272 int V1DstIndex = -1;
7273 int V2DstIndex = -1;
7274 bool V1UsedInPlace = false;
7276 for (int i = 0; i < 4; ++i) {
7277 // Synthesize a zero mask from the zeroable elements (includes undefs).
7283 // Flag if we use any V1 inputs in place.
7285 V1UsedInPlace = true;
7289 // We can only insert a single non-zeroable element.
7290 if (V1DstIndex != -1 || V2DstIndex != -1)
7294 // V1 input out of place for insertion.
7297 // V2 input for insertion.
7302 // Don't bother if we have no (non-zeroable) element for insertion.
7303 if (V1DstIndex == -1 && V2DstIndex == -1)
7306 // Determine element insertion src/dst indices. The src index is from the
7307 // start of the inserted vector, not the start of the concatenated vector.
7308 unsigned V2SrcIndex = 0;
7309 if (V1DstIndex != -1) {
7310 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7311 // and don't use the original V2 at all.
7312 V2SrcIndex = Mask[V1DstIndex];
7313 V2DstIndex = V1DstIndex;
7316 V2SrcIndex = Mask[V2DstIndex] - 4;
7319 // If no V1 inputs are used in place, then the result is created only from
7320 // the zero mask and the V2 insertion - so remove V1 dependency.
7322 V1 = DAG.getUNDEF(MVT::v4f32);
7324 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7325 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7327 // Insert the V2 element into the desired position.
7329 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7330 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7333 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7334 /// UNPCK instruction.
7336 /// This specifically targets cases where we end up with alternating between
7337 /// the two inputs, and so can permute them into something that feeds a single
7338 /// UNPCK instruction. Note that this routine only targets integer vectors
7339 /// because for floating point vectors we have a generalized SHUFPS lowering
7340 /// strategy that handles everything that doesn't *exactly* match an unpack,
7341 /// making this clever lowering unnecessary.
7342 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7343 SDValue V2, ArrayRef<int> Mask,
7344 SelectionDAG &DAG) {
7345 assert(!VT.isFloatingPoint() &&
7346 "This routine only supports integer vectors.");
7347 assert(!isSingleInputShuffleMask(Mask) &&
7348 "This routine should only be used when blending two inputs.");
7349 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7351 int Size = Mask.size();
7353 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7354 return M >= 0 && M % Size < Size / 2;
7356 int NumHiInputs = std::count_if(
7357 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7359 bool UnpackLo = NumLoInputs >= NumHiInputs;
7361 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7362 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7363 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7365 for (int i = 0; i < Size; ++i) {
7369 // Each element of the unpack contains Scale elements from this mask.
7370 int UnpackIdx = i / Scale;
7372 // We only handle the case where V1 feeds the first slots of the unpack.
7373 // We rely on canonicalization to ensure this is the case.
7374 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7377 // Setup the mask for this input. The indexing is tricky as we have to
7378 // handle the unpack stride.
7379 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7380 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7384 // If we will have to shuffle both inputs to use the unpack, check whether
7385 // we can just unpack first and shuffle the result. If so, skip this unpack.
7386 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7387 !isNoopShuffleMask(V2Mask))
7390 // Shuffle the inputs into place.
7391 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7392 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7394 // Cast the inputs to the type we will use to unpack them.
7395 V1 = DAG.getBitcast(UnpackVT, V1);
7396 V2 = DAG.getBitcast(UnpackVT, V2);
7398 // Unpack the inputs and cast the result back to the desired type.
7399 return DAG.getBitcast(
7400 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7404 // We try each unpack from the largest to the smallest to try and find one
7405 // that fits this mask.
7406 int OrigNumElements = VT.getVectorNumElements();
7407 int OrigScalarSize = VT.getScalarSizeInBits();
7408 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7409 int Scale = ScalarSize / OrigScalarSize;
7410 int NumElements = OrigNumElements / Scale;
7411 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7412 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7416 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7418 if (NumLoInputs == 0 || NumHiInputs == 0) {
7419 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7420 "We have to have *some* inputs!");
7421 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7423 // FIXME: We could consider the total complexity of the permute of each
7424 // possible unpacking. Or at the least we should consider how many
7425 // half-crossings are created.
7426 // FIXME: We could consider commuting the unpacks.
7428 SmallVector<int, 32> PermMask;
7429 PermMask.assign(Size, -1);
7430 for (int i = 0; i < Size; ++i) {
7434 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7437 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7439 return DAG.getVectorShuffle(
7440 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7442 DAG.getUNDEF(VT), PermMask);
7448 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7450 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7451 /// support for floating point shuffles but not integer shuffles. These
7452 /// instructions will incur a domain crossing penalty on some chips though so
7453 /// it is better to avoid lowering through this for integer vectors where
7455 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7456 const X86Subtarget *Subtarget,
7457 SelectionDAG &DAG) {
7459 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7460 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7461 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7462 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7463 ArrayRef<int> Mask = SVOp->getMask();
7464 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7466 if (isSingleInputShuffleMask(Mask)) {
7467 // Use low duplicate instructions for masks that match their pattern.
7468 if (Subtarget->hasSSE3())
7469 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7470 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7472 // Straight shuffle of a single input vector. Simulate this by using the
7473 // single input as both of the "inputs" to this instruction..
7474 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7476 if (Subtarget->hasAVX()) {
7477 // If we have AVX, we can use VPERMILPS which will allow folding a load
7478 // into the shuffle.
7479 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7480 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7483 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7484 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7486 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7487 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7489 // If we have a single input, insert that into V1 if we can do so cheaply.
7490 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7491 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7492 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7494 // Try inverting the insertion since for v2 masks it is easy to do and we
7495 // can't reliably sort the mask one way or the other.
7496 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7497 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7498 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7499 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7503 // Try to use one of the special instruction patterns to handle two common
7504 // blend patterns if a zero-blend above didn't work.
7505 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7506 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7507 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7508 // We can either use a special instruction to load over the low double or
7509 // to move just the low double.
7511 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7513 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7515 if (Subtarget->hasSSE41())
7516 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7520 // Use dedicated unpack instructions for masks that match their pattern.
7521 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7522 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7523 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7524 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7526 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7527 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7528 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7531 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7533 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7534 /// the integer unit to minimize domain crossing penalties. However, for blends
7535 /// it falls back to the floating point shuffle operation with appropriate bit
7537 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7538 const X86Subtarget *Subtarget,
7539 SelectionDAG &DAG) {
7541 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7542 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7543 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7544 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7545 ArrayRef<int> Mask = SVOp->getMask();
7546 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7548 if (isSingleInputShuffleMask(Mask)) {
7549 // Check for being able to broadcast a single element.
7550 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7551 Mask, Subtarget, DAG))
7554 // Straight shuffle of a single input vector. For everything from SSE2
7555 // onward this has a single fast instruction with no scary immediates.
7556 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7557 V1 = DAG.getBitcast(MVT::v4i32, V1);
7558 int WidenedMask[4] = {
7559 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7560 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7561 return DAG.getBitcast(
7563 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7564 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7566 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7567 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7568 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7569 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7571 // If we have a blend of two PACKUS operations an the blend aligns with the
7572 // low and half halves, we can just merge the PACKUS operations. This is
7573 // particularly important as it lets us merge shuffles that this routine itself
7575 auto GetPackNode = [](SDValue V) {
7576 while (V.getOpcode() == ISD::BITCAST)
7577 V = V.getOperand(0);
7579 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7581 if (SDValue V1Pack = GetPackNode(V1))
7582 if (SDValue V2Pack = GetPackNode(V2))
7583 return DAG.getBitcast(MVT::v2i64,
7584 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7585 Mask[0] == 0 ? V1Pack.getOperand(0)
7586 : V1Pack.getOperand(1),
7587 Mask[1] == 2 ? V2Pack.getOperand(0)
7588 : V2Pack.getOperand(1)));
7590 // Try to use shift instructions.
7592 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7595 // When loading a scalar and then shuffling it into a vector we can often do
7596 // the insertion cheaply.
7597 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7598 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7600 // Try inverting the insertion since for v2 masks it is easy to do and we
7601 // can't reliably sort the mask one way or the other.
7602 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7603 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7604 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7607 // We have different paths for blend lowering, but they all must use the
7608 // *exact* same predicate.
7609 bool IsBlendSupported = Subtarget->hasSSE41();
7610 if (IsBlendSupported)
7611 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7615 // Use dedicated unpack instructions for masks that match their pattern.
7616 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7617 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7618 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7619 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7621 // Try to use byte rotation instructions.
7622 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7623 if (Subtarget->hasSSSE3())
7624 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7625 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7628 // If we have direct support for blends, we should lower by decomposing into
7629 // a permute. That will be faster than the domain cross.
7630 if (IsBlendSupported)
7631 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7634 // We implement this with SHUFPD which is pretty lame because it will likely
7635 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7636 // However, all the alternatives are still more cycles and newer chips don't
7637 // have this problem. It would be really nice if x86 had better shuffles here.
7638 V1 = DAG.getBitcast(MVT::v2f64, V1);
7639 V2 = DAG.getBitcast(MVT::v2f64, V2);
7640 return DAG.getBitcast(MVT::v2i64,
7641 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7644 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7646 /// This is used to disable more specialized lowerings when the shufps lowering
7647 /// will happen to be efficient.
7648 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7649 // This routine only handles 128-bit shufps.
7650 assert(Mask.size() == 4 && "Unsupported mask size!");
7652 // To lower with a single SHUFPS we need to have the low half and high half
7653 // each requiring a single input.
7654 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7656 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7662 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7664 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7665 /// It makes no assumptions about whether this is the *best* lowering, it simply
7667 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7668 ArrayRef<int> Mask, SDValue V1,
7669 SDValue V2, SelectionDAG &DAG) {
7670 SDValue LowV = V1, HighV = V2;
7671 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7674 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7676 if (NumV2Elements == 1) {
7678 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7681 // Compute the index adjacent to V2Index and in the same half by toggling
7683 int V2AdjIndex = V2Index ^ 1;
7685 if (Mask[V2AdjIndex] == -1) {
7686 // Handles all the cases where we have a single V2 element and an undef.
7687 // This will only ever happen in the high lanes because we commute the
7688 // vector otherwise.
7690 std::swap(LowV, HighV);
7691 NewMask[V2Index] -= 4;
7693 // Handle the case where the V2 element ends up adjacent to a V1 element.
7694 // To make this work, blend them together as the first step.
7695 int V1Index = V2AdjIndex;
7696 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7697 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7698 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7700 // Now proceed to reconstruct the final blend as we have the necessary
7701 // high or low half formed.
7708 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7709 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7711 } else if (NumV2Elements == 2) {
7712 if (Mask[0] < 4 && Mask[1] < 4) {
7713 // Handle the easy case where we have V1 in the low lanes and V2 in the
7717 } else if (Mask[2] < 4 && Mask[3] < 4) {
7718 // We also handle the reversed case because this utility may get called
7719 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7720 // arrange things in the right direction.
7726 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7727 // trying to place elements directly, just blend them and set up the final
7728 // shuffle to place them.
7730 // The first two blend mask elements are for V1, the second two are for
7732 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7733 Mask[2] < 4 ? Mask[2] : Mask[3],
7734 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7735 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7736 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7737 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7739 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7742 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7743 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7744 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7745 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7748 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7749 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7752 /// \brief Lower 4-lane 32-bit floating point shuffles.
7754 /// Uses instructions exclusively from the floating point unit to minimize
7755 /// domain crossing penalties, as these are sufficient to implement all v4f32
7757 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7758 const X86Subtarget *Subtarget,
7759 SelectionDAG &DAG) {
7761 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7762 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7763 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7764 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7765 ArrayRef<int> Mask = SVOp->getMask();
7766 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7769 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7771 if (NumV2Elements == 0) {
7772 // Check for being able to broadcast a single element.
7773 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7774 Mask, Subtarget, DAG))
7777 // Use even/odd duplicate instructions for masks that match their pattern.
7778 if (Subtarget->hasSSE3()) {
7779 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
7780 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
7781 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
7782 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
7785 if (Subtarget->hasAVX()) {
7786 // If we have AVX, we can use VPERMILPS which will allow folding a load
7787 // into the shuffle.
7788 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
7789 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7792 // Otherwise, use a straight shuffle of a single input vector. We pass the
7793 // input vector to both operands to simulate this with a SHUFPS.
7794 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
7795 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7798 // There are special ways we can lower some single-element blends. However, we
7799 // have custom ways we can lower more complex single-element blends below that
7800 // we defer to if both this and BLENDPS fail to match, so restrict this to
7801 // when the V2 input is targeting element 0 of the mask -- that is the fast
7803 if (NumV2Elements == 1 && Mask[0] >= 4)
7804 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
7805 Mask, Subtarget, DAG))
7808 if (Subtarget->hasSSE41()) {
7809 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
7813 // Use INSERTPS if we can complete the shuffle efficiently.
7814 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
7817 if (!isSingleSHUFPSMask(Mask))
7818 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
7819 DL, MVT::v4f32, V1, V2, Mask, DAG))
7823 // Use dedicated unpack instructions for masks that match their pattern.
7824 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7825 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
7826 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7827 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
7828 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7829 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
7830 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7831 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
7833 // Otherwise fall back to a SHUFPS lowering strategy.
7834 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
7837 /// \brief Lower 4-lane i32 vector shuffles.
7839 /// We try to handle these with integer-domain shuffles where we can, but for
7840 /// blends we use the floating point domain blend instructions.
7841 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7842 const X86Subtarget *Subtarget,
7843 SelectionDAG &DAG) {
7845 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
7846 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7847 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
7848 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7849 ArrayRef<int> Mask = SVOp->getMask();
7850 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7852 // Whenever we can lower this as a zext, that instruction is strictly faster
7853 // than any alternative. It also allows us to fold memory operands into the
7854 // shuffle in many cases.
7855 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
7856 Mask, Subtarget, DAG))
7860 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7862 if (NumV2Elements == 0) {
7863 // Check for being able to broadcast a single element.
7864 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
7865 Mask, Subtarget, DAG))
7868 // Straight shuffle of a single input vector. For everything from SSE2
7869 // onward this has a single fast instruction with no scary immediates.
7870 // We coerce the shuffle pattern to be compatible with UNPCK instructions
7871 // but we aren't actually going to use the UNPCK instruction because doing
7872 // so prevents folding a load into this instruction or making a copy.
7873 const int UnpackLoMask[] = {0, 0, 1, 1};
7874 const int UnpackHiMask[] = {2, 2, 3, 3};
7875 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
7876 Mask = UnpackLoMask;
7877 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
7878 Mask = UnpackHiMask;
7880 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7881 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
7884 // Try to use shift instructions.
7886 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
7889 // There are special ways we can lower some single-element blends.
7890 if (NumV2Elements == 1)
7891 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
7892 Mask, Subtarget, DAG))
7895 // We have different paths for blend lowering, but they all must use the
7896 // *exact* same predicate.
7897 bool IsBlendSupported = Subtarget->hasSSE41();
7898 if (IsBlendSupported)
7899 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
7903 if (SDValue Masked =
7904 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
7907 // Use dedicated unpack instructions for masks that match their pattern.
7908 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
7909 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
7910 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
7911 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
7912 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
7913 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
7914 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
7915 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
7917 // Try to use byte rotation instructions.
7918 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7919 if (Subtarget->hasSSSE3())
7920 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7921 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
7924 // If we have direct support for blends, we should lower by decomposing into
7925 // a permute. That will be faster than the domain cross.
7926 if (IsBlendSupported)
7927 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
7930 // Try to lower by permuting the inputs into an unpack instruction.
7931 if (SDValue Unpack =
7932 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
7935 // We implement this with SHUFPS because it can blend from two vectors.
7936 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
7937 // up the inputs, bypassing domain shift penalties that we would encur if we
7938 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
7940 return DAG.getBitcast(
7942 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
7943 DAG.getBitcast(MVT::v4f32, V2), Mask));
7946 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
7947 /// shuffle lowering, and the most complex part.
7949 /// The lowering strategy is to try to form pairs of input lanes which are
7950 /// targeted at the same half of the final vector, and then use a dword shuffle
7951 /// to place them onto the right half, and finally unpack the paired lanes into
7952 /// their final position.
7954 /// The exact breakdown of how to form these dword pairs and align them on the
7955 /// correct sides is really tricky. See the comments within the function for
7956 /// more of the details.
7958 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
7959 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
7960 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
7961 /// vector, form the analogous 128-bit 8-element Mask.
7962 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
7963 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
7964 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7965 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
7966 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
7968 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
7969 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
7970 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
7972 SmallVector<int, 4> LoInputs;
7973 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
7974 [](int M) { return M >= 0; });
7975 std::sort(LoInputs.begin(), LoInputs.end());
7976 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
7977 SmallVector<int, 4> HiInputs;
7978 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
7979 [](int M) { return M >= 0; });
7980 std::sort(HiInputs.begin(), HiInputs.end());
7981 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
7983 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
7984 int NumHToL = LoInputs.size() - NumLToL;
7986 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
7987 int NumHToH = HiInputs.size() - NumLToH;
7988 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
7989 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
7990 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
7991 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
7993 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
7994 // such inputs we can swap two of the dwords across the half mark and end up
7995 // with <=2 inputs to each half in each half. Once there, we can fall through
7996 // to the generic code below. For example:
7998 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
7999 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8001 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8002 // and an existing 2-into-2 on the other half. In this case we may have to
8003 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8004 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8005 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8006 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8007 // half than the one we target for fixing) will be fixed when we re-enter this
8008 // path. We will also combine away any sequence of PSHUFD instructions that
8009 // result into a single instruction. Here is an example of the tricky case:
8011 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8012 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8014 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8016 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8017 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8019 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8020 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8022 // The result is fine to be handled by the generic logic.
8023 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8024 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8025 int AOffset, int BOffset) {
8026 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8027 "Must call this with A having 3 or 1 inputs from the A half.");
8028 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8029 "Must call this with B having 1 or 3 inputs from the B half.");
8030 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8031 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8033 // Compute the index of dword with only one word among the three inputs in
8034 // a half by taking the sum of the half with three inputs and subtracting
8035 // the sum of the actual three inputs. The difference is the remaining
8038 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8039 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8040 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8041 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8042 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8043 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8044 int TripleNonInputIdx =
8045 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8046 TripleDWord = TripleNonInputIdx / 2;
8048 // We use xor with one to compute the adjacent DWord to whichever one the
8050 OneInputDWord = (OneInput / 2) ^ 1;
8052 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8053 // and BToA inputs. If there is also such a problem with the BToB and AToB
8054 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8055 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8056 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8057 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8058 // Compute how many inputs will be flipped by swapping these DWords. We
8060 // to balance this to ensure we don't form a 3-1 shuffle in the other
8062 int NumFlippedAToBInputs =
8063 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8064 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8065 int NumFlippedBToBInputs =
8066 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8067 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8068 if ((NumFlippedAToBInputs == 1 &&
8069 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8070 (NumFlippedBToBInputs == 1 &&
8071 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8072 // We choose whether to fix the A half or B half based on whether that
8073 // half has zero flipped inputs. At zero, we may not be able to fix it
8074 // with that half. We also bias towards fixing the B half because that
8075 // will more commonly be the high half, and we have to bias one way.
8076 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8077 ArrayRef<int> Inputs) {
8078 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8079 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8080 PinnedIdx ^ 1) != Inputs.end();
8081 // Determine whether the free index is in the flipped dword or the
8082 // unflipped dword based on where the pinned index is. We use this bit
8083 // in an xor to conditionally select the adjacent dword.
8084 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8085 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8086 FixFreeIdx) != Inputs.end();
8087 if (IsFixIdxInput == IsFixFreeIdxInput)
8089 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8090 FixFreeIdx) != Inputs.end();
8091 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8092 "We need to be changing the number of flipped inputs!");
8093 int PSHUFHalfMask[] = {0, 1, 2, 3};
8094 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8095 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8097 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8100 if (M != -1 && M == FixIdx)
8102 else if (M != -1 && M == FixFreeIdx)
8105 if (NumFlippedBToBInputs != 0) {
8107 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8108 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8110 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8112 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8113 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8118 int PSHUFDMask[] = {0, 1, 2, 3};
8119 PSHUFDMask[ADWord] = BDWord;
8120 PSHUFDMask[BDWord] = ADWord;
8123 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8124 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8126 // Adjust the mask to match the new locations of A and B.
8128 if (M != -1 && M/2 == ADWord)
8129 M = 2 * BDWord + M % 2;
8130 else if (M != -1 && M/2 == BDWord)
8131 M = 2 * ADWord + M % 2;
8133 // Recurse back into this routine to re-compute state now that this isn't
8134 // a 3 and 1 problem.
8135 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8138 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8139 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8140 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8141 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8143 // At this point there are at most two inputs to the low and high halves from
8144 // each half. That means the inputs can always be grouped into dwords and
8145 // those dwords can then be moved to the correct half with a dword shuffle.
8146 // We use at most one low and one high word shuffle to collect these paired
8147 // inputs into dwords, and finally a dword shuffle to place them.
8148 int PSHUFLMask[4] = {-1, -1, -1, -1};
8149 int PSHUFHMask[4] = {-1, -1, -1, -1};
8150 int PSHUFDMask[4] = {-1, -1, -1, -1};
8152 // First fix the masks for all the inputs that are staying in their
8153 // original halves. This will then dictate the targets of the cross-half
8155 auto fixInPlaceInputs =
8156 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8157 MutableArrayRef<int> SourceHalfMask,
8158 MutableArrayRef<int> HalfMask, int HalfOffset) {
8159 if (InPlaceInputs.empty())
8161 if (InPlaceInputs.size() == 1) {
8162 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8163 InPlaceInputs[0] - HalfOffset;
8164 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8167 if (IncomingInputs.empty()) {
8168 // Just fix all of the in place inputs.
8169 for (int Input : InPlaceInputs) {
8170 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8171 PSHUFDMask[Input / 2] = Input / 2;
8176 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8177 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8178 InPlaceInputs[0] - HalfOffset;
8179 // Put the second input next to the first so that they are packed into
8180 // a dword. We find the adjacent index by toggling the low bit.
8181 int AdjIndex = InPlaceInputs[0] ^ 1;
8182 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8183 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8184 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8186 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8187 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8189 // Now gather the cross-half inputs and place them into a free dword of
8190 // their target half.
8191 // FIXME: This operation could almost certainly be simplified dramatically to
8192 // look more like the 3-1 fixing operation.
8193 auto moveInputsToRightHalf = [&PSHUFDMask](
8194 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8195 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8196 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8198 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8199 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8201 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8203 int LowWord = Word & ~1;
8204 int HighWord = Word | 1;
8205 return isWordClobbered(SourceHalfMask, LowWord) ||
8206 isWordClobbered(SourceHalfMask, HighWord);
8209 if (IncomingInputs.empty())
8212 if (ExistingInputs.empty()) {
8213 // Map any dwords with inputs from them into the right half.
8214 for (int Input : IncomingInputs) {
8215 // If the source half mask maps over the inputs, turn those into
8216 // swaps and use the swapped lane.
8217 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8218 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8219 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8220 Input - SourceOffset;
8221 // We have to swap the uses in our half mask in one sweep.
8222 for (int &M : HalfMask)
8223 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8225 else if (M == Input)
8226 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8228 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8229 Input - SourceOffset &&
8230 "Previous placement doesn't match!");
8232 // Note that this correctly re-maps both when we do a swap and when
8233 // we observe the other side of the swap above. We rely on that to
8234 // avoid swapping the members of the input list directly.
8235 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8238 // Map the input's dword into the correct half.
8239 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8240 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8242 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8244 "Previous placement doesn't match!");
8247 // And just directly shift any other-half mask elements to be same-half
8248 // as we will have mirrored the dword containing the element into the
8249 // same position within that half.
8250 for (int &M : HalfMask)
8251 if (M >= SourceOffset && M < SourceOffset + 4) {
8252 M = M - SourceOffset + DestOffset;
8253 assert(M >= 0 && "This should never wrap below zero!");
8258 // Ensure we have the input in a viable dword of its current half. This
8259 // is particularly tricky because the original position may be clobbered
8260 // by inputs being moved and *staying* in that half.
8261 if (IncomingInputs.size() == 1) {
8262 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8263 int InputFixed = std::find(std::begin(SourceHalfMask),
8264 std::end(SourceHalfMask), -1) -
8265 std::begin(SourceHalfMask) + SourceOffset;
8266 SourceHalfMask[InputFixed - SourceOffset] =
8267 IncomingInputs[0] - SourceOffset;
8268 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8270 IncomingInputs[0] = InputFixed;
8272 } else if (IncomingInputs.size() == 2) {
8273 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8274 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8275 // We have two non-adjacent or clobbered inputs we need to extract from
8276 // the source half. To do this, we need to map them into some adjacent
8277 // dword slot in the source mask.
8278 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8279 IncomingInputs[1] - SourceOffset};
8281 // If there is a free slot in the source half mask adjacent to one of
8282 // the inputs, place the other input in it. We use (Index XOR 1) to
8283 // compute an adjacent index.
8284 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8285 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8286 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8287 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8288 InputsFixed[1] = InputsFixed[0] ^ 1;
8289 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8290 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8291 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8292 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8293 InputsFixed[0] = InputsFixed[1] ^ 1;
8294 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8295 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8296 // The two inputs are in the same DWord but it is clobbered and the
8297 // adjacent DWord isn't used at all. Move both inputs to the free
8299 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8300 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8301 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8302 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8304 // The only way we hit this point is if there is no clobbering
8305 // (because there are no off-half inputs to this half) and there is no
8306 // free slot adjacent to one of the inputs. In this case, we have to
8307 // swap an input with a non-input.
8308 for (int i = 0; i < 4; ++i)
8309 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8310 "We can't handle any clobbers here!");
8311 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8312 "Cannot have adjacent inputs here!");
8314 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8315 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8317 // We also have to update the final source mask in this case because
8318 // it may need to undo the above swap.
8319 for (int &M : FinalSourceHalfMask)
8320 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8321 M = InputsFixed[1] + SourceOffset;
8322 else if (M == InputsFixed[1] + SourceOffset)
8323 M = (InputsFixed[0] ^ 1) + SourceOffset;
8325 InputsFixed[1] = InputsFixed[0] ^ 1;
8328 // Point everything at the fixed inputs.
8329 for (int &M : HalfMask)
8330 if (M == IncomingInputs[0])
8331 M = InputsFixed[0] + SourceOffset;
8332 else if (M == IncomingInputs[1])
8333 M = InputsFixed[1] + SourceOffset;
8335 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8336 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8339 llvm_unreachable("Unhandled input size!");
8342 // Now hoist the DWord down to the right half.
8343 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8344 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8345 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8346 for (int &M : HalfMask)
8347 for (int Input : IncomingInputs)
8349 M = FreeDWord * 2 + Input % 2;
8351 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8352 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8353 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8354 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8356 // Now enact all the shuffles we've computed to move the inputs into their
8358 if (!isNoopShuffleMask(PSHUFLMask))
8359 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8360 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8361 if (!isNoopShuffleMask(PSHUFHMask))
8362 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8363 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8364 if (!isNoopShuffleMask(PSHUFDMask))
8367 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8368 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8370 // At this point, each half should contain all its inputs, and we can then
8371 // just shuffle them into their final position.
8372 assert(std::count_if(LoMask.begin(), LoMask.end(),
8373 [](int M) { return M >= 4; }) == 0 &&
8374 "Failed to lift all the high half inputs to the low mask!");
8375 assert(std::count_if(HiMask.begin(), HiMask.end(),
8376 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8377 "Failed to lift all the low half inputs to the high mask!");
8379 // Do a half shuffle for the low mask.
8380 if (!isNoopShuffleMask(LoMask))
8381 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8382 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8384 // Do a half shuffle with the high mask after shifting its values down.
8385 for (int &M : HiMask)
8388 if (!isNoopShuffleMask(HiMask))
8389 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8390 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8395 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8396 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8397 SDValue V2, ArrayRef<int> Mask,
8398 SelectionDAG &DAG, bool &V1InUse,
8400 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8406 int Size = Mask.size();
8407 int Scale = 16 / Size;
8408 for (int i = 0; i < 16; ++i) {
8409 if (Mask[i / Scale] == -1) {
8410 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8412 const int ZeroMask = 0x80;
8413 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8415 int V2Idx = Mask[i / Scale] < Size
8417 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8418 if (Zeroable[i / Scale])
8419 V1Idx = V2Idx = ZeroMask;
8420 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8421 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8422 V1InUse |= (ZeroMask != V1Idx);
8423 V2InUse |= (ZeroMask != V2Idx);
8428 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8429 DAG.getBitcast(MVT::v16i8, V1),
8430 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8432 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8433 DAG.getBitcast(MVT::v16i8, V2),
8434 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8436 // If we need shuffled inputs from both, blend the two.
8438 if (V1InUse && V2InUse)
8439 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8441 V = V1InUse ? V1 : V2;
8443 // Cast the result back to the correct type.
8444 return DAG.getBitcast(VT, V);
8447 /// \brief Generic lowering of 8-lane i16 shuffles.
8449 /// This handles both single-input shuffles and combined shuffle/blends with
8450 /// two inputs. The single input shuffles are immediately delegated to
8451 /// a dedicated lowering routine.
8453 /// The blends are lowered in one of three fundamental ways. If there are few
8454 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8455 /// of the input is significantly cheaper when lowered as an interleaving of
8456 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8457 /// halves of the inputs separately (making them have relatively few inputs)
8458 /// and then concatenate them.
8459 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8460 const X86Subtarget *Subtarget,
8461 SelectionDAG &DAG) {
8463 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8464 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8465 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8466 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8467 ArrayRef<int> OrigMask = SVOp->getMask();
8468 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8469 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8470 MutableArrayRef<int> Mask(MaskStorage);
8472 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8474 // Whenever we can lower this as a zext, that instruction is strictly faster
8475 // than any alternative.
8476 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8477 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8480 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8482 auto isV2 = [](int M) { return M >= 8; };
8484 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8486 if (NumV2Inputs == 0) {
8487 // Check for being able to broadcast a single element.
8488 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8489 Mask, Subtarget, DAG))
8492 // Try to use shift instructions.
8494 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8497 // Use dedicated unpack instructions for masks that match their pattern.
8498 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8499 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8500 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8501 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8503 // Try to use byte rotation instructions.
8504 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8505 Mask, Subtarget, DAG))
8508 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8512 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8513 "All single-input shuffles should be canonicalized to be V1-input "
8516 // Try to use shift instructions.
8518 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8521 // There are special ways we can lower some single-element blends.
8522 if (NumV2Inputs == 1)
8523 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8524 Mask, Subtarget, DAG))
8527 // We have different paths for blend lowering, but they all must use the
8528 // *exact* same predicate.
8529 bool IsBlendSupported = Subtarget->hasSSE41();
8530 if (IsBlendSupported)
8531 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8535 if (SDValue Masked =
8536 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8539 // Use dedicated unpack instructions for masks that match their pattern.
8540 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8541 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8542 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8543 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8545 // Try to use byte rotation instructions.
8546 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8547 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8550 if (SDValue BitBlend =
8551 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8554 if (SDValue Unpack =
8555 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8558 // If we can't directly blend but can use PSHUFB, that will be better as it
8559 // can both shuffle and set up the inefficient blend.
8560 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8561 bool V1InUse, V2InUse;
8562 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8566 // We can always bit-blend if we have to so the fallback strategy is to
8567 // decompose into single-input permutes and blends.
8568 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8572 /// \brief Check whether a compaction lowering can be done by dropping even
8573 /// elements and compute how many times even elements must be dropped.
8575 /// This handles shuffles which take every Nth element where N is a power of
8576 /// two. Example shuffle masks:
8578 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8579 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8580 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8581 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8582 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8583 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8585 /// Any of these lanes can of course be undef.
8587 /// This routine only supports N <= 3.
8588 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8591 /// \returns N above, or the number of times even elements must be dropped if
8592 /// there is such a number. Otherwise returns zero.
8593 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8594 // Figure out whether we're looping over two inputs or just one.
8595 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8597 // The modulus for the shuffle vector entries is based on whether this is
8598 // a single input or not.
8599 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8600 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8601 "We should only be called with masks with a power-of-2 size!");
8603 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8605 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8606 // and 2^3 simultaneously. This is because we may have ambiguity with
8607 // partially undef inputs.
8608 bool ViableForN[3] = {true, true, true};
8610 for (int i = 0, e = Mask.size(); i < e; ++i) {
8611 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8616 bool IsAnyViable = false;
8617 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8618 if (ViableForN[j]) {
8621 // The shuffle mask must be equal to (i * 2^N) % M.
8622 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8625 ViableForN[j] = false;
8627 // Early exit if we exhaust the possible powers of two.
8632 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8636 // Return 0 as there is no viable power of two.
8640 /// \brief Generic lowering of v16i8 shuffles.
8642 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8643 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8644 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8645 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8647 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8648 const X86Subtarget *Subtarget,
8649 SelectionDAG &DAG) {
8651 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8652 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8653 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8654 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8655 ArrayRef<int> Mask = SVOp->getMask();
8656 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8658 // Try to use shift instructions.
8660 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8663 // Try to use byte rotation instructions.
8664 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8665 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8668 // Try to use a zext lowering.
8669 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8670 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8674 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8676 // For single-input shuffles, there are some nicer lowering tricks we can use.
8677 if (NumV2Elements == 0) {
8678 // Check for being able to broadcast a single element.
8679 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8680 Mask, Subtarget, DAG))
8683 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8684 // Notably, this handles splat and partial-splat shuffles more efficiently.
8685 // However, it only makes sense if the pre-duplication shuffle simplifies
8686 // things significantly. Currently, this means we need to be able to
8687 // express the pre-duplication shuffle as an i16 shuffle.
8689 // FIXME: We should check for other patterns which can be widened into an
8690 // i16 shuffle as well.
8691 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8692 for (int i = 0; i < 16; i += 2)
8693 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8698 auto tryToWidenViaDuplication = [&]() -> SDValue {
8699 if (!canWidenViaDuplication(Mask))
8701 SmallVector<int, 4> LoInputs;
8702 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8703 [](int M) { return M >= 0 && M < 8; });
8704 std::sort(LoInputs.begin(), LoInputs.end());
8705 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8707 SmallVector<int, 4> HiInputs;
8708 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8709 [](int M) { return M >= 8; });
8710 std::sort(HiInputs.begin(), HiInputs.end());
8711 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8714 bool TargetLo = LoInputs.size() >= HiInputs.size();
8715 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8716 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8718 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8719 SmallDenseMap<int, int, 8> LaneMap;
8720 for (int I : InPlaceInputs) {
8721 PreDupI16Shuffle[I/2] = I/2;
8724 int j = TargetLo ? 0 : 4, je = j + 4;
8725 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8726 // Check if j is already a shuffle of this input. This happens when
8727 // there are two adjacent bytes after we move the low one.
8728 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8729 // If we haven't yet mapped the input, search for a slot into which
8731 while (j < je && PreDupI16Shuffle[j] != -1)
8735 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8738 // Map this input with the i16 shuffle.
8739 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8742 // Update the lane map based on the mapping we ended up with.
8743 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8745 V1 = DAG.getBitcast(
8747 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8748 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8750 // Unpack the bytes to form the i16s that will be shuffled into place.
8751 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8752 MVT::v16i8, V1, V1);
8754 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8755 for (int i = 0; i < 16; ++i)
8756 if (Mask[i] != -1) {
8757 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8758 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8759 if (PostDupI16Shuffle[i / 2] == -1)
8760 PostDupI16Shuffle[i / 2] = MappedMask;
8762 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8763 "Conflicting entrties in the original shuffle!");
8765 return DAG.getBitcast(
8767 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8768 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
8770 if (SDValue V = tryToWidenViaDuplication())
8774 // Use dedicated unpack instructions for masks that match their pattern.
8775 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8776 0, 16, 1, 17, 2, 18, 3, 19,
8778 4, 20, 5, 21, 6, 22, 7, 23}))
8779 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
8780 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
8781 8, 24, 9, 25, 10, 26, 11, 27,
8783 12, 28, 13, 29, 14, 30, 15, 31}))
8784 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
8786 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
8787 // with PSHUFB. It is important to do this before we attempt to generate any
8788 // blends but after all of the single-input lowerings. If the single input
8789 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
8790 // want to preserve that and we can DAG combine any longer sequences into
8791 // a PSHUFB in the end. But once we start blending from multiple inputs,
8792 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
8793 // and there are *very* few patterns that would actually be faster than the
8794 // PSHUFB approach because of its ability to zero lanes.
8796 // FIXME: The only exceptions to the above are blends which are exact
8797 // interleavings with direct instructions supporting them. We currently don't
8798 // handle those well here.
8799 if (Subtarget->hasSSSE3()) {
8800 bool V1InUse = false;
8801 bool V2InUse = false;
8803 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
8804 DAG, V1InUse, V2InUse);
8806 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
8807 // do so. This avoids using them to handle blends-with-zero which is
8808 // important as a single pshufb is significantly faster for that.
8809 if (V1InUse && V2InUse) {
8810 if (Subtarget->hasSSE41())
8811 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
8812 Mask, Subtarget, DAG))
8815 // We can use an unpack to do the blending rather than an or in some
8816 // cases. Even though the or may be (very minorly) more efficient, we
8817 // preference this lowering because there are common cases where part of
8818 // the complexity of the shuffles goes away when we do the final blend as
8820 // FIXME: It might be worth trying to detect if the unpack-feeding
8821 // shuffles will both be pshufb, in which case we shouldn't bother with
8823 if (SDValue Unpack =
8824 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
8831 // There are special ways we can lower some single-element blends.
8832 if (NumV2Elements == 1)
8833 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
8834 Mask, Subtarget, DAG))
8837 if (SDValue BitBlend =
8838 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
8841 // Check whether a compaction lowering can be done. This handles shuffles
8842 // which take every Nth element for some even N. See the helper function for
8845 // We special case these as they can be particularly efficiently handled with
8846 // the PACKUSB instruction on x86 and they show up in common patterns of
8847 // rearranging bytes to truncate wide elements.
8848 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
8849 // NumEvenDrops is the power of two stride of the elements. Another way of
8850 // thinking about it is that we need to drop the even elements this many
8851 // times to get the original input.
8852 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8854 // First we need to zero all the dropped bytes.
8855 assert(NumEvenDrops <= 3 &&
8856 "No support for dropping even elements more than 3 times.");
8857 // We use the mask type to pick which bytes are preserved based on how many
8858 // elements are dropped.
8859 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
8860 SDValue ByteClearMask = DAG.getBitcast(
8861 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
8862 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
8864 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
8866 // Now pack things back together.
8867 V1 = DAG.getBitcast(MVT::v8i16, V1);
8868 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
8869 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
8870 for (int i = 1; i < NumEvenDrops; ++i) {
8871 Result = DAG.getBitcast(MVT::v8i16, Result);
8872 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
8878 // Handle multi-input cases by blending single-input shuffles.
8879 if (NumV2Elements > 0)
8880 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
8883 // The fallback path for single-input shuffles widens this into two v8i16
8884 // vectors with unpacks, shuffles those, and then pulls them back together
8888 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8889 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8890 for (int i = 0; i < 16; ++i)
8892 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
8894 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
8896 SDValue VLoHalf, VHiHalf;
8897 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
8898 // them out and avoid using UNPCK{L,H} to extract the elements of V as
8900 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
8901 [](int M) { return M >= 0 && M % 2 == 1; }) &&
8902 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
8903 [](int M) { return M >= 0 && M % 2 == 1; })) {
8904 // Use a mask to drop the high bytes.
8905 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
8906 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
8907 DAG.getConstant(0x00FF, DL, MVT::v8i16));
8909 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
8910 VHiHalf = DAG.getUNDEF(MVT::v8i16);
8912 // Squash the masks to point directly into VLoHalf.
8913 for (int &M : LoBlendMask)
8916 for (int &M : HiBlendMask)
8920 // Otherwise just unpack the low half of V into VLoHalf and the high half into
8921 // VHiHalf so that we can blend them as i16s.
8922 VLoHalf = DAG.getBitcast(
8923 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
8924 VHiHalf = DAG.getBitcast(
8925 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
8928 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
8929 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
8931 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
8934 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
8936 /// This routine breaks down the specific type of 128-bit shuffle and
8937 /// dispatches to the lowering routines accordingly.
8938 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8939 MVT VT, const X86Subtarget *Subtarget,
8940 SelectionDAG &DAG) {
8941 switch (VT.SimpleTy) {
8943 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8945 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
8947 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8949 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
8951 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
8953 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
8956 llvm_unreachable("Unimplemented!");
8960 /// \brief Helper function to test whether a shuffle mask could be
8961 /// simplified by widening the elements being shuffled.
8963 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
8964 /// leaves it in an unspecified state.
8966 /// NOTE: This must handle normal vector shuffle masks and *target* vector
8967 /// shuffle masks. The latter have the special property of a '-2' representing
8968 /// a zero-ed lane of a vector.
8969 static bool canWidenShuffleElements(ArrayRef<int> Mask,
8970 SmallVectorImpl<int> &WidenedMask) {
8971 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
8972 // If both elements are undef, its trivial.
8973 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
8974 WidenedMask.push_back(SM_SentinelUndef);
8978 // Check for an undef mask and a mask value properly aligned to fit with
8979 // a pair of values. If we find such a case, use the non-undef mask's value.
8980 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
8981 WidenedMask.push_back(Mask[i + 1] / 2);
8984 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
8985 WidenedMask.push_back(Mask[i] / 2);
8989 // When zeroing, we need to spread the zeroing across both lanes to widen.
8990 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
8991 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
8992 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
8993 WidenedMask.push_back(SM_SentinelZero);
8999 // Finally check if the two mask values are adjacent and aligned with
9001 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9002 WidenedMask.push_back(Mask[i] / 2);
9006 // Otherwise we can't safely widen the elements used in this shuffle.
9009 assert(WidenedMask.size() == Mask.size() / 2 &&
9010 "Incorrect size of mask after widening the elements!");
9015 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9017 /// This routine just extracts two subvectors, shuffles them independently, and
9018 /// then concatenates them back together. This should work effectively with all
9019 /// AVX vector shuffle types.
9020 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9021 SDValue V2, ArrayRef<int> Mask,
9022 SelectionDAG &DAG) {
9023 assert(VT.getSizeInBits() >= 256 &&
9024 "Only for 256-bit or wider vector shuffles!");
9025 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9026 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9028 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9029 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9031 int NumElements = VT.getVectorNumElements();
9032 int SplitNumElements = NumElements / 2;
9033 MVT ScalarVT = VT.getScalarType();
9034 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9036 // Rather than splitting build-vectors, just build two narrower build
9037 // vectors. This helps shuffling with splats and zeros.
9038 auto SplitVector = [&](SDValue V) {
9039 while (V.getOpcode() == ISD::BITCAST)
9040 V = V->getOperand(0);
9042 MVT OrigVT = V.getSimpleValueType();
9043 int OrigNumElements = OrigVT.getVectorNumElements();
9044 int OrigSplitNumElements = OrigNumElements / 2;
9045 MVT OrigScalarVT = OrigVT.getScalarType();
9046 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9050 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9052 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9053 DAG.getIntPtrConstant(0, DL));
9054 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9055 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9058 SmallVector<SDValue, 16> LoOps, HiOps;
9059 for (int i = 0; i < OrigSplitNumElements; ++i) {
9060 LoOps.push_back(BV->getOperand(i));
9061 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9063 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9064 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9066 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9067 DAG.getBitcast(SplitVT, HiV));
9070 SDValue LoV1, HiV1, LoV2, HiV2;
9071 std::tie(LoV1, HiV1) = SplitVector(V1);
9072 std::tie(LoV2, HiV2) = SplitVector(V2);
9074 // Now create two 4-way blends of these half-width vectors.
9075 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9076 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9077 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9078 for (int i = 0; i < SplitNumElements; ++i) {
9079 int M = HalfMask[i];
9080 if (M >= NumElements) {
9081 if (M >= NumElements + SplitNumElements)
9085 V2BlendMask.push_back(M - NumElements);
9086 V1BlendMask.push_back(-1);
9087 BlendMask.push_back(SplitNumElements + i);
9088 } else if (M >= 0) {
9089 if (M >= SplitNumElements)
9093 V2BlendMask.push_back(-1);
9094 V1BlendMask.push_back(M);
9095 BlendMask.push_back(i);
9097 V2BlendMask.push_back(-1);
9098 V1BlendMask.push_back(-1);
9099 BlendMask.push_back(-1);
9103 // Because the lowering happens after all combining takes place, we need to
9104 // manually combine these blend masks as much as possible so that we create
9105 // a minimal number of high-level vector shuffle nodes.
9107 // First try just blending the halves of V1 or V2.
9108 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9109 return DAG.getUNDEF(SplitVT);
9110 if (!UseLoV2 && !UseHiV2)
9111 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9112 if (!UseLoV1 && !UseHiV1)
9113 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9115 SDValue V1Blend, V2Blend;
9116 if (UseLoV1 && UseHiV1) {
9118 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9120 // We only use half of V1 so map the usage down into the final blend mask.
9121 V1Blend = UseLoV1 ? LoV1 : HiV1;
9122 for (int i = 0; i < SplitNumElements; ++i)
9123 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9124 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9126 if (UseLoV2 && UseHiV2) {
9128 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9130 // We only use half of V2 so map the usage down into the final blend mask.
9131 V2Blend = UseLoV2 ? LoV2 : HiV2;
9132 for (int i = 0; i < SplitNumElements; ++i)
9133 if (BlendMask[i] >= SplitNumElements)
9134 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9136 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9138 SDValue Lo = HalfBlend(LoMask);
9139 SDValue Hi = HalfBlend(HiMask);
9140 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9143 /// \brief Either split a vector in halves or decompose the shuffles and the
9146 /// This is provided as a good fallback for many lowerings of non-single-input
9147 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9148 /// between splitting the shuffle into 128-bit components and stitching those
9149 /// back together vs. extracting the single-input shuffles and blending those
9151 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9152 SDValue V2, ArrayRef<int> Mask,
9153 SelectionDAG &DAG) {
9154 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9155 "lower single-input shuffles as it "
9156 "could then recurse on itself.");
9157 int Size = Mask.size();
9159 // If this can be modeled as a broadcast of two elements followed by a blend,
9160 // prefer that lowering. This is especially important because broadcasts can
9161 // often fold with memory operands.
9162 auto DoBothBroadcast = [&] {
9163 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9166 if (V2BroadcastIdx == -1)
9167 V2BroadcastIdx = M - Size;
9168 else if (M - Size != V2BroadcastIdx)
9170 } else if (M >= 0) {
9171 if (V1BroadcastIdx == -1)
9173 else if (M != V1BroadcastIdx)
9178 if (DoBothBroadcast())
9179 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9182 // If the inputs all stem from a single 128-bit lane of each input, then we
9183 // split them rather than blending because the split will decompose to
9184 // unusually few instructions.
9185 int LaneCount = VT.getSizeInBits() / 128;
9186 int LaneSize = Size / LaneCount;
9187 SmallBitVector LaneInputs[2];
9188 LaneInputs[0].resize(LaneCount, false);
9189 LaneInputs[1].resize(LaneCount, false);
9190 for (int i = 0; i < Size; ++i)
9192 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9193 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9194 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9196 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9197 // that the decomposed single-input shuffles don't end up here.
9198 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9201 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9202 /// a permutation and blend of those lanes.
9204 /// This essentially blends the out-of-lane inputs to each lane into the lane
9205 /// from a permuted copy of the vector. This lowering strategy results in four
9206 /// instructions in the worst case for a single-input cross lane shuffle which
9207 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9208 /// of. Special cases for each particular shuffle pattern should be handled
9209 /// prior to trying this lowering.
9210 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9211 SDValue V1, SDValue V2,
9213 SelectionDAG &DAG) {
9214 // FIXME: This should probably be generalized for 512-bit vectors as well.
9215 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9216 int LaneSize = Mask.size() / 2;
9218 // If there are only inputs from one 128-bit lane, splitting will in fact be
9219 // less expensive. The flags track whether the given lane contains an element
9220 // that crosses to another lane.
9221 bool LaneCrossing[2] = {false, false};
9222 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9223 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9224 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9225 if (!LaneCrossing[0] || !LaneCrossing[1])
9226 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9228 if (isSingleInputShuffleMask(Mask)) {
9229 SmallVector<int, 32> FlippedBlendMask;
9230 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9231 FlippedBlendMask.push_back(
9232 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9234 : Mask[i] % LaneSize +
9235 (i / LaneSize) * LaneSize + Size));
9237 // Flip the vector, and blend the results which should now be in-lane. The
9238 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9239 // 5 for the high source. The value 3 selects the high half of source 2 and
9240 // the value 2 selects the low half of source 2. We only use source 2 to
9241 // allow folding it into a memory operand.
9242 unsigned PERMMask = 3 | 2 << 4;
9243 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9244 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9245 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9248 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9249 // will be handled by the above logic and a blend of the results, much like
9250 // other patterns in AVX.
9251 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9254 /// \brief Handle lowering 2-lane 128-bit shuffles.
9255 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9256 SDValue V2, ArrayRef<int> Mask,
9257 const X86Subtarget *Subtarget,
9258 SelectionDAG &DAG) {
9259 // TODO: If minimizing size and one of the inputs is a zero vector and the
9260 // the zero vector has only one use, we could use a VPERM2X128 to save the
9261 // instruction bytes needed to explicitly generate the zero vector.
9263 // Blends are faster and handle all the non-lane-crossing cases.
9264 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9268 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9269 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9271 // If either input operand is a zero vector, use VPERM2X128 because its mask
9272 // allows us to replace the zero input with an implicit zero.
9273 if (!IsV1Zero && !IsV2Zero) {
9274 // Check for patterns which can be matched with a single insert of a 128-bit
9276 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9277 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9278 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9279 VT.getVectorNumElements() / 2);
9280 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9281 DAG.getIntPtrConstant(0, DL));
9282 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9283 OnlyUsesV1 ? V1 : V2,
9284 DAG.getIntPtrConstant(0, DL));
9285 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9289 // Otherwise form a 128-bit permutation. After accounting for undefs,
9290 // convert the 64-bit shuffle mask selection values into 128-bit
9291 // selection bits by dividing the indexes by 2 and shifting into positions
9292 // defined by a vperm2*128 instruction's immediate control byte.
9294 // The immediate permute control byte looks like this:
9295 // [1:0] - select 128 bits from sources for low half of destination
9297 // [3] - zero low half of destination
9298 // [5:4] - select 128 bits from sources for high half of destination
9300 // [7] - zero high half of destination
9302 int MaskLO = Mask[0];
9303 if (MaskLO == SM_SentinelUndef)
9304 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9306 int MaskHI = Mask[2];
9307 if (MaskHI == SM_SentinelUndef)
9308 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9310 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9312 // If either input is a zero vector, replace it with an undef input.
9313 // Shuffle mask values < 4 are selecting elements of V1.
9314 // Shuffle mask values >= 4 are selecting elements of V2.
9315 // Adjust each half of the permute mask by clearing the half that was
9316 // selecting the zero vector and setting the zero mask bit.
9318 V1 = DAG.getUNDEF(VT);
9320 PermMask = (PermMask & 0xf0) | 0x08;
9322 PermMask = (PermMask & 0x0f) | 0x80;
9325 V2 = DAG.getUNDEF(VT);
9327 PermMask = (PermMask & 0xf0) | 0x08;
9329 PermMask = (PermMask & 0x0f) | 0x80;
9332 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9333 DAG.getConstant(PermMask, DL, MVT::i8));
9336 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9337 /// shuffling each lane.
9339 /// This will only succeed when the result of fixing the 128-bit lanes results
9340 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9341 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9342 /// the lane crosses early and then use simpler shuffles within each lane.
9344 /// FIXME: It might be worthwhile at some point to support this without
9345 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9346 /// in x86 only floating point has interesting non-repeating shuffles, and even
9347 /// those are still *marginally* more expensive.
9348 static SDValue lowerVectorShuffleByMerging128BitLanes(
9349 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9350 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9351 assert(!isSingleInputShuffleMask(Mask) &&
9352 "This is only useful with multiple inputs.");
9354 int Size = Mask.size();
9355 int LaneSize = 128 / VT.getScalarSizeInBits();
9356 int NumLanes = Size / LaneSize;
9357 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9359 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9360 // check whether the in-128-bit lane shuffles share a repeating pattern.
9361 SmallVector<int, 4> Lanes;
9362 Lanes.resize(NumLanes, -1);
9363 SmallVector<int, 4> InLaneMask;
9364 InLaneMask.resize(LaneSize, -1);
9365 for (int i = 0; i < Size; ++i) {
9369 int j = i / LaneSize;
9372 // First entry we've seen for this lane.
9373 Lanes[j] = Mask[i] / LaneSize;
9374 } else if (Lanes[j] != Mask[i] / LaneSize) {
9375 // This doesn't match the lane selected previously!
9379 // Check that within each lane we have a consistent shuffle mask.
9380 int k = i % LaneSize;
9381 if (InLaneMask[k] < 0) {
9382 InLaneMask[k] = Mask[i] % LaneSize;
9383 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9384 // This doesn't fit a repeating in-lane mask.
9389 // First shuffle the lanes into place.
9390 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9391 VT.getSizeInBits() / 64);
9392 SmallVector<int, 8> LaneMask;
9393 LaneMask.resize(NumLanes * 2, -1);
9394 for (int i = 0; i < NumLanes; ++i)
9395 if (Lanes[i] >= 0) {
9396 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9397 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9400 V1 = DAG.getBitcast(LaneVT, V1);
9401 V2 = DAG.getBitcast(LaneVT, V2);
9402 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9404 // Cast it back to the type we actually want.
9405 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9407 // Now do a simple shuffle that isn't lane crossing.
9408 SmallVector<int, 8> NewMask;
9409 NewMask.resize(Size, -1);
9410 for (int i = 0; i < Size; ++i)
9412 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9413 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9414 "Must not introduce lane crosses at this point!");
9416 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9419 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9422 /// This returns true if the elements from a particular input are already in the
9423 /// slot required by the given mask and require no permutation.
9424 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9425 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9426 int Size = Mask.size();
9427 for (int i = 0; i < Size; ++i)
9428 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9434 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9435 ArrayRef<int> Mask, SDValue V1,
9436 SDValue V2, SelectionDAG &DAG) {
9438 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9439 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9440 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9441 int NumElts = VT.getVectorNumElements();
9442 bool ShufpdMask = true;
9443 bool CommutableMask = true;
9444 unsigned Immediate = 0;
9445 for (int i = 0; i < NumElts; ++i) {
9448 int Val = (i & 6) + NumElts * (i & 1);
9449 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9450 if (Mask[i] < Val || Mask[i] > Val + 1)
9452 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9453 CommutableMask = false;
9454 Immediate |= (Mask[i] % 2) << i;
9457 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9458 DAG.getConstant(Immediate, DL, MVT::i8));
9460 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9461 DAG.getConstant(Immediate, DL, MVT::i8));
9465 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9467 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9468 /// isn't available.
9469 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9470 const X86Subtarget *Subtarget,
9471 SelectionDAG &DAG) {
9473 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9474 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9476 ArrayRef<int> Mask = SVOp->getMask();
9477 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9479 SmallVector<int, 4> WidenedMask;
9480 if (canWidenShuffleElements(Mask, WidenedMask))
9481 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9484 if (isSingleInputShuffleMask(Mask)) {
9485 // Check for being able to broadcast a single element.
9486 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9487 Mask, Subtarget, DAG))
9490 // Use low duplicate instructions for masks that match their pattern.
9491 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9492 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9494 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9495 // Non-half-crossing single input shuffles can be lowerid with an
9496 // interleaved permutation.
9497 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9498 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9499 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9500 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9503 // With AVX2 we have direct support for this permutation.
9504 if (Subtarget->hasAVX2())
9505 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9506 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9508 // Otherwise, fall back.
9509 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9513 // X86 has dedicated unpack instructions that can handle specific blend
9514 // operations: UNPCKH and UNPCKL.
9515 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9516 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9517 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9518 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9519 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9520 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9521 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9522 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9524 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9528 // Check if the blend happens to exactly fit that of SHUFPD.
9530 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9533 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9534 // shuffle. However, if we have AVX2 and either inputs are already in place,
9535 // we will be able to shuffle even across lanes the other input in a single
9536 // instruction so skip this pattern.
9537 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9538 isShuffleMaskInputInPlace(1, Mask))))
9539 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9540 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9543 // If we have AVX2 then we always want to lower with a blend because an v4 we
9544 // can fully permute the elements.
9545 if (Subtarget->hasAVX2())
9546 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9549 // Otherwise fall back on generic lowering.
9550 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9553 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9555 /// This routine is only called when we have AVX2 and thus a reasonable
9556 /// instruction set for v4i64 shuffling..
9557 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9558 const X86Subtarget *Subtarget,
9559 SelectionDAG &DAG) {
9561 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9562 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9563 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9564 ArrayRef<int> Mask = SVOp->getMask();
9565 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9566 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9568 SmallVector<int, 4> WidenedMask;
9569 if (canWidenShuffleElements(Mask, WidenedMask))
9570 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9573 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9577 // Check for being able to broadcast a single element.
9578 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9579 Mask, Subtarget, DAG))
9582 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9583 // use lower latency instructions that will operate on both 128-bit lanes.
9584 SmallVector<int, 2> RepeatedMask;
9585 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9586 if (isSingleInputShuffleMask(Mask)) {
9587 int PSHUFDMask[] = {-1, -1, -1, -1};
9588 for (int i = 0; i < 2; ++i)
9589 if (RepeatedMask[i] >= 0) {
9590 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9591 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9593 return DAG.getBitcast(
9595 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9596 DAG.getBitcast(MVT::v8i32, V1),
9597 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9601 // AVX2 provides a direct instruction for permuting a single input across
9603 if (isSingleInputShuffleMask(Mask))
9604 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9605 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9607 // Try to use shift instructions.
9609 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9612 // Use dedicated unpack instructions for masks that match their pattern.
9613 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9614 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9615 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9616 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9617 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9618 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9619 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9620 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9622 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9623 // shuffle. However, if we have AVX2 and either inputs are already in place,
9624 // we will be able to shuffle even across lanes the other input in a single
9625 // instruction so skip this pattern.
9626 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9627 isShuffleMaskInputInPlace(1, Mask))))
9628 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9629 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9632 // Otherwise fall back on generic blend lowering.
9633 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9637 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9639 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9640 /// isn't available.
9641 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9642 const X86Subtarget *Subtarget,
9643 SelectionDAG &DAG) {
9645 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9646 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9647 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9648 ArrayRef<int> Mask = SVOp->getMask();
9649 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9651 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9655 // Check for being able to broadcast a single element.
9656 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9657 Mask, Subtarget, DAG))
9660 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9661 // options to efficiently lower the shuffle.
9662 SmallVector<int, 4> RepeatedMask;
9663 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9664 assert(RepeatedMask.size() == 4 &&
9665 "Repeated masks must be half the mask width!");
9667 // Use even/odd duplicate instructions for masks that match their pattern.
9668 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9669 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9670 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9671 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9673 if (isSingleInputShuffleMask(Mask))
9674 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9675 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9677 // Use dedicated unpack instructions for masks that match their pattern.
9678 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9679 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9680 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9681 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9682 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9683 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9684 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9685 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9687 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9688 // have already handled any direct blends. We also need to squash the
9689 // repeated mask into a simulated v4f32 mask.
9690 for (int i = 0; i < 4; ++i)
9691 if (RepeatedMask[i] >= 8)
9692 RepeatedMask[i] -= 4;
9693 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9696 // If we have a single input shuffle with different shuffle patterns in the
9697 // two 128-bit lanes use the variable mask to VPERMILPS.
9698 if (isSingleInputShuffleMask(Mask)) {
9699 SDValue VPermMask[8];
9700 for (int i = 0; i < 8; ++i)
9701 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9702 : DAG.getConstant(Mask[i], DL, MVT::i32);
9703 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9705 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9706 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9708 if (Subtarget->hasAVX2())
9710 X86ISD::VPERMV, DL, MVT::v8f32,
9711 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
9712 MVT::v8i32, VPermMask)),
9715 // Otherwise, fall back.
9716 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9720 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9722 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9723 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9726 // If we have AVX2 then we always want to lower with a blend because at v8 we
9727 // can fully permute the elements.
9728 if (Subtarget->hasAVX2())
9729 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9732 // Otherwise fall back on generic lowering.
9733 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9736 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9738 /// This routine is only called when we have AVX2 and thus a reasonable
9739 /// instruction set for v8i32 shuffling..
9740 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9741 const X86Subtarget *Subtarget,
9742 SelectionDAG &DAG) {
9744 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9745 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9746 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9747 ArrayRef<int> Mask = SVOp->getMask();
9748 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9749 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9751 // Whenever we can lower this as a zext, that instruction is strictly faster
9752 // than any alternative. It also allows us to fold memory operands into the
9753 // shuffle in many cases.
9754 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9755 Mask, Subtarget, DAG))
9758 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9762 // Check for being able to broadcast a single element.
9763 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9764 Mask, Subtarget, DAG))
9767 // If the shuffle mask is repeated in each 128-bit lane we can use more
9768 // efficient instructions that mirror the shuffles across the two 128-bit
9770 SmallVector<int, 4> RepeatedMask;
9771 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
9772 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
9773 if (isSingleInputShuffleMask(Mask))
9774 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
9775 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9777 // Use dedicated unpack instructions for masks that match their pattern.
9778 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9779 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
9780 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9781 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
9782 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9783 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
9784 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9785 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
9788 // Try to use shift instructions.
9790 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
9793 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9794 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9797 // If the shuffle patterns aren't repeated but it is a single input, directly
9798 // generate a cross-lane VPERMD instruction.
9799 if (isSingleInputShuffleMask(Mask)) {
9800 SDValue VPermMask[8];
9801 for (int i = 0; i < 8; ++i)
9802 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9803 : DAG.getConstant(Mask[i], DL, MVT::i32);
9805 X86ISD::VPERMV, DL, MVT::v8i32,
9806 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
9809 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9811 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9812 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
9815 // Otherwise fall back on generic blend lowering.
9816 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
9820 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
9822 /// This routine is only called when we have AVX2 and thus a reasonable
9823 /// instruction set for v16i16 shuffling..
9824 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9825 const X86Subtarget *Subtarget,
9826 SelectionDAG &DAG) {
9828 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9829 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
9830 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9831 ArrayRef<int> Mask = SVOp->getMask();
9832 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
9833 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
9835 // Whenever we can lower this as a zext, that instruction is strictly faster
9836 // than any alternative. It also allows us to fold memory operands into the
9837 // shuffle in many cases.
9838 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
9839 Mask, Subtarget, DAG))
9842 // Check for being able to broadcast a single element.
9843 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
9844 Mask, Subtarget, DAG))
9847 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
9851 // Use dedicated unpack instructions for masks that match their pattern.
9852 if (isShuffleEquivalent(V1, V2, Mask,
9853 {// First 128-bit lane:
9854 0, 16, 1, 17, 2, 18, 3, 19,
9855 // Second 128-bit lane:
9856 8, 24, 9, 25, 10, 26, 11, 27}))
9857 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
9858 if (isShuffleEquivalent(V1, V2, Mask,
9859 {// First 128-bit lane:
9860 4, 20, 5, 21, 6, 22, 7, 23,
9861 // Second 128-bit lane:
9862 12, 28, 13, 29, 14, 30, 15, 31}))
9863 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
9865 // Try to use shift instructions.
9867 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
9870 // Try to use byte rotation instructions.
9871 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9872 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9875 if (isSingleInputShuffleMask(Mask)) {
9876 // There are no generalized cross-lane shuffle operations available on i16
9878 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
9879 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
9882 SmallVector<int, 8> RepeatedMask;
9883 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
9884 // As this is a single-input shuffle, the repeated mask should be
9885 // a strictly valid v8i16 mask that we can pass through to the v8i16
9886 // lowering to handle even the v16 case.
9887 return lowerV8I16GeneralSingleInputVectorShuffle(
9888 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
9891 SDValue PSHUFBMask[32];
9892 for (int i = 0; i < 16; ++i) {
9893 if (Mask[i] == -1) {
9894 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
9898 int M = i < 8 ? Mask[i] : Mask[i] - 8;
9899 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
9900 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
9901 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
9903 return DAG.getBitcast(MVT::v16i16,
9904 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
9905 DAG.getBitcast(MVT::v32i8, V1),
9906 DAG.getNode(ISD::BUILD_VECTOR, DL,
9907 MVT::v32i8, PSHUFBMask)));
9910 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9912 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9913 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
9916 // Otherwise fall back on generic lowering.
9917 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
9920 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
9922 /// This routine is only called when we have AVX2 and thus a reasonable
9923 /// instruction set for v32i8 shuffling..
9924 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9925 const X86Subtarget *Subtarget,
9926 SelectionDAG &DAG) {
9928 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9929 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
9930 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9931 ArrayRef<int> Mask = SVOp->getMask();
9932 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
9933 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
9935 // Whenever we can lower this as a zext, that instruction is strictly faster
9936 // than any alternative. It also allows us to fold memory operands into the
9937 // shuffle in many cases.
9938 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
9939 Mask, Subtarget, DAG))
9942 // Check for being able to broadcast a single element.
9943 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
9944 Mask, Subtarget, DAG))
9947 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
9951 // Use dedicated unpack instructions for masks that match their pattern.
9952 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
9954 if (isShuffleEquivalent(
9956 {// First 128-bit lane:
9957 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
9958 // Second 128-bit lane:
9959 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
9960 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
9961 if (isShuffleEquivalent(
9963 {// First 128-bit lane:
9964 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
9965 // Second 128-bit lane:
9966 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
9967 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
9969 // Try to use shift instructions.
9971 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
9974 // Try to use byte rotation instructions.
9975 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
9976 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
9979 if (isSingleInputShuffleMask(Mask)) {
9980 // There are no generalized cross-lane shuffle operations available on i8
9982 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
9983 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
9986 SDValue PSHUFBMask[32];
9987 for (int i = 0; i < 32; ++i)
9990 ? DAG.getUNDEF(MVT::i8)
9991 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
9995 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
9996 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
9999 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10001 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10002 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10005 // Otherwise fall back on generic lowering.
10006 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10009 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10011 /// This routine either breaks down the specific type of a 256-bit x86 vector
10012 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10013 /// together based on the available instructions.
10014 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10015 MVT VT, const X86Subtarget *Subtarget,
10016 SelectionDAG &DAG) {
10018 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10019 ArrayRef<int> Mask = SVOp->getMask();
10021 // If we have a single input to the zero element, insert that into V1 if we
10022 // can do so cheaply.
10023 int NumElts = VT.getVectorNumElements();
10024 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10025 return M >= NumElts;
10028 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10029 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10030 DL, VT, V1, V2, Mask, Subtarget, DAG))
10033 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10034 // check for those subtargets here and avoid much of the subtarget querying in
10035 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10036 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10037 // floating point types there eventually, just immediately cast everything to
10038 // a float and operate entirely in that domain.
10039 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10040 int ElementBits = VT.getScalarSizeInBits();
10041 if (ElementBits < 32)
10042 // No floating point type available, decompose into 128-bit vectors.
10043 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10045 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10046 VT.getVectorNumElements());
10047 V1 = DAG.getBitcast(FpVT, V1);
10048 V2 = DAG.getBitcast(FpVT, V2);
10049 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10052 switch (VT.SimpleTy) {
10054 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10056 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10058 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10060 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10062 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10064 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10067 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10071 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10072 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10073 const X86Subtarget *Subtarget,
10074 SelectionDAG &DAG) {
10076 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10077 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10079 ArrayRef<int> Mask = SVOp->getMask();
10080 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10082 // X86 has dedicated unpack instructions that can handle specific blend
10083 // operations: UNPCKH and UNPCKL.
10084 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10085 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10086 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10087 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10089 // FIXME: Implement direct support for this type!
10090 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10093 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10094 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10095 const X86Subtarget *Subtarget,
10096 SelectionDAG &DAG) {
10098 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10099 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10100 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10101 ArrayRef<int> Mask = SVOp->getMask();
10102 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10104 // Use dedicated unpack instructions for masks that match their pattern.
10105 if (isShuffleEquivalent(V1, V2, Mask,
10106 {// First 128-bit lane.
10107 0, 16, 1, 17, 4, 20, 5, 21,
10108 // Second 128-bit lane.
10109 8, 24, 9, 25, 12, 28, 13, 29}))
10110 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10111 if (isShuffleEquivalent(V1, V2, Mask,
10112 {// First 128-bit lane.
10113 2, 18, 3, 19, 6, 22, 7, 23,
10114 // Second 128-bit lane.
10115 10, 26, 11, 27, 14, 30, 15, 31}))
10116 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10118 // FIXME: Implement direct support for this type!
10119 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10122 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10123 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10124 const X86Subtarget *Subtarget,
10125 SelectionDAG &DAG) {
10127 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10128 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10129 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10130 ArrayRef<int> Mask = SVOp->getMask();
10131 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10133 // X86 has dedicated unpack instructions that can handle specific blend
10134 // operations: UNPCKH and UNPCKL.
10135 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10136 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10137 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10138 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10140 // FIXME: Implement direct support for this type!
10141 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10144 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10145 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10146 const X86Subtarget *Subtarget,
10147 SelectionDAG &DAG) {
10149 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10150 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10151 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10152 ArrayRef<int> Mask = SVOp->getMask();
10153 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10155 // Use dedicated unpack instructions for masks that match their pattern.
10156 if (isShuffleEquivalent(V1, V2, Mask,
10157 {// First 128-bit lane.
10158 0, 16, 1, 17, 4, 20, 5, 21,
10159 // Second 128-bit lane.
10160 8, 24, 9, 25, 12, 28, 13, 29}))
10161 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10162 if (isShuffleEquivalent(V1, V2, Mask,
10163 {// First 128-bit lane.
10164 2, 18, 3, 19, 6, 22, 7, 23,
10165 // Second 128-bit lane.
10166 10, 26, 11, 27, 14, 30, 15, 31}))
10167 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10169 // FIXME: Implement direct support for this type!
10170 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10173 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10174 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10175 const X86Subtarget *Subtarget,
10176 SelectionDAG &DAG) {
10178 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10179 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10180 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10181 ArrayRef<int> Mask = SVOp->getMask();
10182 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10183 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10185 // FIXME: Implement direct support for this type!
10186 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10189 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10190 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10191 const X86Subtarget *Subtarget,
10192 SelectionDAG &DAG) {
10194 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10195 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10196 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10197 ArrayRef<int> Mask = SVOp->getMask();
10198 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10199 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10201 // FIXME: Implement direct support for this type!
10202 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10205 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10207 /// This routine either breaks down the specific type of a 512-bit x86 vector
10208 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10209 /// together based on the available instructions.
10210 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10211 MVT VT, const X86Subtarget *Subtarget,
10212 SelectionDAG &DAG) {
10214 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10215 ArrayRef<int> Mask = SVOp->getMask();
10216 assert(Subtarget->hasAVX512() &&
10217 "Cannot lower 512-bit vectors w/ basic ISA!");
10219 // Check for being able to broadcast a single element.
10220 if (SDValue Broadcast =
10221 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10224 // Dispatch to each element type for lowering. If we don't have supprot for
10225 // specific element type shuffles at 512 bits, immediately split them and
10226 // lower them. Each lowering routine of a given type is allowed to assume that
10227 // the requisite ISA extensions for that element type are available.
10228 switch (VT.SimpleTy) {
10230 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10232 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10234 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10236 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10238 if (Subtarget->hasBWI())
10239 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10242 if (Subtarget->hasBWI())
10243 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10247 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10250 // Otherwise fall back on splitting.
10251 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10254 /// \brief Top-level lowering for x86 vector shuffles.
10256 /// This handles decomposition, canonicalization, and lowering of all x86
10257 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10258 /// above in helper routines. The canonicalization attempts to widen shuffles
10259 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10260 /// s.t. only one of the two inputs needs to be tested, etc.
10261 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10262 SelectionDAG &DAG) {
10263 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10264 ArrayRef<int> Mask = SVOp->getMask();
10265 SDValue V1 = Op.getOperand(0);
10266 SDValue V2 = Op.getOperand(1);
10267 MVT VT = Op.getSimpleValueType();
10268 int NumElements = VT.getVectorNumElements();
10271 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10273 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10274 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10275 if (V1IsUndef && V2IsUndef)
10276 return DAG.getUNDEF(VT);
10278 // When we create a shuffle node we put the UNDEF node to second operand,
10279 // but in some cases the first operand may be transformed to UNDEF.
10280 // In this case we should just commute the node.
10282 return DAG.getCommutedVectorShuffle(*SVOp);
10284 // Check for non-undef masks pointing at an undef vector and make the masks
10285 // undef as well. This makes it easier to match the shuffle based solely on
10289 if (M >= NumElements) {
10290 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10291 for (int &M : NewMask)
10292 if (M >= NumElements)
10294 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10297 // We actually see shuffles that are entirely re-arrangements of a set of
10298 // zero inputs. This mostly happens while decomposing complex shuffles into
10299 // simple ones. Directly lower these as a buildvector of zeros.
10300 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10301 if (Zeroable.all())
10302 return getZeroVector(VT, Subtarget, DAG, dl);
10304 // Try to collapse shuffles into using a vector type with fewer elements but
10305 // wider element types. We cap this to not form integers or floating point
10306 // elements wider than 64 bits, but it might be interesting to form i128
10307 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10308 SmallVector<int, 16> WidenedMask;
10309 if (VT.getScalarSizeInBits() < 64 &&
10310 canWidenShuffleElements(Mask, WidenedMask)) {
10311 MVT NewEltVT = VT.isFloatingPoint()
10312 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10313 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10314 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10315 // Make sure that the new vector type is legal. For example, v2f64 isn't
10317 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10318 V1 = DAG.getBitcast(NewVT, V1);
10319 V2 = DAG.getBitcast(NewVT, V2);
10320 return DAG.getBitcast(
10321 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10325 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10326 for (int M : SVOp->getMask())
10328 ++NumUndefElements;
10329 else if (M < NumElements)
10334 // Commute the shuffle as needed such that more elements come from V1 than
10335 // V2. This allows us to match the shuffle pattern strictly on how many
10336 // elements come from V1 without handling the symmetric cases.
10337 if (NumV2Elements > NumV1Elements)
10338 return DAG.getCommutedVectorShuffle(*SVOp);
10340 // When the number of V1 and V2 elements are the same, try to minimize the
10341 // number of uses of V2 in the low half of the vector. When that is tied,
10342 // ensure that the sum of indices for V1 is equal to or lower than the sum
10343 // indices for V2. When those are equal, try to ensure that the number of odd
10344 // indices for V1 is lower than the number of odd indices for V2.
10345 if (NumV1Elements == NumV2Elements) {
10346 int LowV1Elements = 0, LowV2Elements = 0;
10347 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10348 if (M >= NumElements)
10352 if (LowV2Elements > LowV1Elements) {
10353 return DAG.getCommutedVectorShuffle(*SVOp);
10354 } else if (LowV2Elements == LowV1Elements) {
10355 int SumV1Indices = 0, SumV2Indices = 0;
10356 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10357 if (SVOp->getMask()[i] >= NumElements)
10359 else if (SVOp->getMask()[i] >= 0)
10361 if (SumV2Indices < SumV1Indices) {
10362 return DAG.getCommutedVectorShuffle(*SVOp);
10363 } else if (SumV2Indices == SumV1Indices) {
10364 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10365 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10366 if (SVOp->getMask()[i] >= NumElements)
10367 NumV2OddIndices += i % 2;
10368 else if (SVOp->getMask()[i] >= 0)
10369 NumV1OddIndices += i % 2;
10370 if (NumV2OddIndices < NumV1OddIndices)
10371 return DAG.getCommutedVectorShuffle(*SVOp);
10376 // For each vector width, delegate to a specialized lowering routine.
10377 if (VT.getSizeInBits() == 128)
10378 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10380 if (VT.getSizeInBits() == 256)
10381 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10383 // Force AVX-512 vectors to be scalarized for now.
10384 // FIXME: Implement AVX-512 support!
10385 if (VT.getSizeInBits() == 512)
10386 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10388 llvm_unreachable("Unimplemented!");
10391 // This function assumes its argument is a BUILD_VECTOR of constants or
10392 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10394 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10395 unsigned &MaskValue) {
10397 unsigned NumElems = BuildVector->getNumOperands();
10398 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10399 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10400 unsigned NumElemsInLane = NumElems / NumLanes;
10402 // Blend for v16i16 should be symetric for the both lanes.
10403 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10404 SDValue EltCond = BuildVector->getOperand(i);
10405 SDValue SndLaneEltCond =
10406 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10408 int Lane1Cond = -1, Lane2Cond = -1;
10409 if (isa<ConstantSDNode>(EltCond))
10410 Lane1Cond = !isZero(EltCond);
10411 if (isa<ConstantSDNode>(SndLaneEltCond))
10412 Lane2Cond = !isZero(SndLaneEltCond);
10414 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10415 // Lane1Cond != 0, means we want the first argument.
10416 // Lane1Cond == 0, means we want the second argument.
10417 // The encoding of this argument is 0 for the first argument, 1
10418 // for the second. Therefore, invert the condition.
10419 MaskValue |= !Lane1Cond << i;
10420 else if (Lane1Cond < 0)
10421 MaskValue |= !Lane2Cond << i;
10428 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10429 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10430 const X86Subtarget *Subtarget,
10431 SelectionDAG &DAG) {
10432 SDValue Cond = Op.getOperand(0);
10433 SDValue LHS = Op.getOperand(1);
10434 SDValue RHS = Op.getOperand(2);
10436 MVT VT = Op.getSimpleValueType();
10438 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10440 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10442 // Only non-legal VSELECTs reach this lowering, convert those into generic
10443 // shuffles and re-use the shuffle lowering path for blends.
10444 SmallVector<int, 32> Mask;
10445 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10446 SDValue CondElt = CondBV->getOperand(i);
10448 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10450 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10453 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10454 // A vselect where all conditions and data are constants can be optimized into
10455 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10456 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10457 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10458 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10461 // Try to lower this to a blend-style vector shuffle. This can handle all
10462 // constant condition cases.
10463 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10466 // Variable blends are only legal from SSE4.1 onward.
10467 if (!Subtarget->hasSSE41())
10470 // Only some types will be legal on some subtargets. If we can emit a legal
10471 // VSELECT-matching blend, return Op, and but if we need to expand, return
10473 switch (Op.getSimpleValueType().SimpleTy) {
10475 // Most of the vector types have blends past SSE4.1.
10479 // The byte blends for AVX vectors were introduced only in AVX2.
10480 if (Subtarget->hasAVX2())
10487 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10488 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10491 // FIXME: We should custom lower this by fixing the condition and using i8
10497 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10498 MVT VT = Op.getSimpleValueType();
10501 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10504 if (VT.getSizeInBits() == 8) {
10505 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10506 Op.getOperand(0), Op.getOperand(1));
10507 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10508 DAG.getValueType(VT));
10509 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10512 if (VT.getSizeInBits() == 16) {
10513 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10514 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10516 return DAG.getNode(
10517 ISD::TRUNCATE, dl, MVT::i16,
10518 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10519 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10520 Op.getOperand(1)));
10521 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10522 Op.getOperand(0), Op.getOperand(1));
10523 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10524 DAG.getValueType(VT));
10525 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10528 if (VT == MVT::f32) {
10529 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10530 // the result back to FR32 register. It's only worth matching if the
10531 // result has a single use which is a store or a bitcast to i32. And in
10532 // the case of a store, it's not worth it if the index is a constant 0,
10533 // because a MOVSSmr can be used instead, which is smaller and faster.
10534 if (!Op.hasOneUse())
10536 SDNode *User = *Op.getNode()->use_begin();
10537 if ((User->getOpcode() != ISD::STORE ||
10538 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10539 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10540 (User->getOpcode() != ISD::BITCAST ||
10541 User->getValueType(0) != MVT::i32))
10543 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10544 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10546 return DAG.getBitcast(MVT::f32, Extract);
10549 if (VT == MVT::i32 || VT == MVT::i64) {
10550 // ExtractPS/pextrq works with constant index.
10551 if (isa<ConstantSDNode>(Op.getOperand(1)))
10557 /// Extract one bit from mask vector, like v16i1 or v8i1.
10558 /// AVX-512 feature.
10560 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10561 SDValue Vec = Op.getOperand(0);
10563 MVT VecVT = Vec.getSimpleValueType();
10564 SDValue Idx = Op.getOperand(1);
10565 MVT EltVT = Op.getSimpleValueType();
10567 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10568 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10569 "Unexpected vector type in ExtractBitFromMaskVector");
10571 // variable index can't be handled in mask registers,
10572 // extend vector to VR512
10573 if (!isa<ConstantSDNode>(Idx)) {
10574 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10575 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10576 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10577 ExtVT.getVectorElementType(), Ext, Idx);
10578 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10581 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10582 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10583 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10584 rc = getRegClassFor(MVT::v16i1);
10585 unsigned MaxSift = rc->getSize()*8 - 1;
10586 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10587 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10588 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10589 DAG.getConstant(MaxSift, dl, MVT::i8));
10590 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10591 DAG.getIntPtrConstant(0, dl));
10595 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10596 SelectionDAG &DAG) const {
10598 SDValue Vec = Op.getOperand(0);
10599 MVT VecVT = Vec.getSimpleValueType();
10600 SDValue Idx = Op.getOperand(1);
10602 if (Op.getSimpleValueType() == MVT::i1)
10603 return ExtractBitFromMaskVector(Op, DAG);
10605 if (!isa<ConstantSDNode>(Idx)) {
10606 if (VecVT.is512BitVector() ||
10607 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10608 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10611 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10612 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10613 MaskEltVT.getSizeInBits());
10615 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10616 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10617 getZeroVector(MaskVT, Subtarget, DAG, dl),
10618 Idx, DAG.getConstant(0, dl, getPointerTy()));
10619 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10620 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10621 Perm, DAG.getConstant(0, dl, getPointerTy()));
10626 // If this is a 256-bit vector result, first extract the 128-bit vector and
10627 // then extract the element from the 128-bit vector.
10628 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10630 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10631 // Get the 128-bit vector.
10632 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10633 MVT EltVT = VecVT.getVectorElementType();
10635 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10637 //if (IdxVal >= NumElems/2)
10638 // IdxVal -= NumElems/2;
10639 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10640 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10641 DAG.getConstant(IdxVal, dl, MVT::i32));
10644 assert(VecVT.is128BitVector() && "Unexpected vector length");
10646 if (Subtarget->hasSSE41())
10647 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
10650 MVT VT = Op.getSimpleValueType();
10651 // TODO: handle v16i8.
10652 if (VT.getSizeInBits() == 16) {
10653 SDValue Vec = Op.getOperand(0);
10654 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10656 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10657 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10658 DAG.getBitcast(MVT::v4i32, Vec),
10659 Op.getOperand(1)));
10660 // Transform it so it match pextrw which produces a 32-bit result.
10661 MVT EltVT = MVT::i32;
10662 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10663 Op.getOperand(0), Op.getOperand(1));
10664 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10665 DAG.getValueType(VT));
10666 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10669 if (VT.getSizeInBits() == 32) {
10670 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10674 // SHUFPS the element to the lowest double word, then movss.
10675 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10676 MVT VVT = Op.getOperand(0).getSimpleValueType();
10677 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10678 DAG.getUNDEF(VVT), Mask);
10679 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10680 DAG.getIntPtrConstant(0, dl));
10683 if (VT.getSizeInBits() == 64) {
10684 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10685 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10686 // to match extract_elt for f64.
10687 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10691 // UNPCKHPD the element to the lowest double word, then movsd.
10692 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10693 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10694 int Mask[2] = { 1, -1 };
10695 MVT VVT = Op.getOperand(0).getSimpleValueType();
10696 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10697 DAG.getUNDEF(VVT), Mask);
10698 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10699 DAG.getIntPtrConstant(0, dl));
10705 /// Insert one bit to mask vector, like v16i1 or v8i1.
10706 /// AVX-512 feature.
10708 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10710 SDValue Vec = Op.getOperand(0);
10711 SDValue Elt = Op.getOperand(1);
10712 SDValue Idx = Op.getOperand(2);
10713 MVT VecVT = Vec.getSimpleValueType();
10715 if (!isa<ConstantSDNode>(Idx)) {
10716 // Non constant index. Extend source and destination,
10717 // insert element and then truncate the result.
10718 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10719 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10720 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10721 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10722 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10723 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10726 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10727 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10729 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10730 DAG.getConstant(IdxVal, dl, MVT::i8));
10731 if (Vec.getOpcode() == ISD::UNDEF)
10733 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10736 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10737 SelectionDAG &DAG) const {
10738 MVT VT = Op.getSimpleValueType();
10739 MVT EltVT = VT.getVectorElementType();
10741 if (EltVT == MVT::i1)
10742 return InsertBitToMaskVector(Op, DAG);
10745 SDValue N0 = Op.getOperand(0);
10746 SDValue N1 = Op.getOperand(1);
10747 SDValue N2 = Op.getOperand(2);
10748 if (!isa<ConstantSDNode>(N2))
10750 auto *N2C = cast<ConstantSDNode>(N2);
10751 unsigned IdxVal = N2C->getZExtValue();
10753 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10754 // into that, and then insert the subvector back into the result.
10755 if (VT.is256BitVector() || VT.is512BitVector()) {
10756 // With a 256-bit vector, we can insert into the zero element efficiently
10757 // using a blend if we have AVX or AVX2 and the right data type.
10758 if (VT.is256BitVector() && IdxVal == 0) {
10759 // TODO: It is worthwhile to cast integer to floating point and back
10760 // and incur a domain crossing penalty if that's what we'll end up
10761 // doing anyway after extracting to a 128-bit vector.
10762 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10763 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10764 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
10765 N2 = DAG.getIntPtrConstant(1, dl);
10766 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
10770 // Get the desired 128-bit vector chunk.
10771 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
10773 // Insert the element into the desired chunk.
10774 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
10775 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
10777 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
10778 DAG.getConstant(IdxIn128, dl, MVT::i32));
10780 // Insert the changed part back into the bigger vector
10781 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
10783 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
10785 if (Subtarget->hasSSE41()) {
10786 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
10788 if (VT == MVT::v8i16) {
10789 Opc = X86ISD::PINSRW;
10791 assert(VT == MVT::v16i8);
10792 Opc = X86ISD::PINSRB;
10795 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
10797 if (N1.getValueType() != MVT::i32)
10798 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10799 if (N2.getValueType() != MVT::i32)
10800 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10801 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
10804 if (EltVT == MVT::f32) {
10805 // Bits [7:6] of the constant are the source select. This will always be
10806 // zero here. The DAG Combiner may combine an extract_elt index into
10807 // these bits. For example (insert (extract, 3), 2) could be matched by
10808 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
10809 // Bits [5:4] of the constant are the destination select. This is the
10810 // value of the incoming immediate.
10811 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
10812 // combine either bitwise AND or insert of float 0.0 to set these bits.
10814 const Function *F = DAG.getMachineFunction().getFunction();
10815 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
10816 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
10817 // If this is an insertion of 32-bits into the low 32-bits of
10818 // a vector, we prefer to generate a blend with immediate rather
10819 // than an insertps. Blends are simpler operations in hardware and so
10820 // will always have equal or better performance than insertps.
10821 // But if optimizing for size and there's a load folding opportunity,
10822 // generate insertps because blendps does not have a 32-bit memory
10824 N2 = DAG.getIntPtrConstant(1, dl);
10825 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10826 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
10828 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
10829 // Create this as a scalar to vector..
10830 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
10831 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
10834 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
10835 // PINSR* works with constant index.
10840 if (EltVT == MVT::i8)
10843 if (EltVT.getSizeInBits() == 16) {
10844 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
10845 // as its second argument.
10846 if (N1.getValueType() != MVT::i32)
10847 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
10848 if (N2.getValueType() != MVT::i32)
10849 N2 = DAG.getIntPtrConstant(IdxVal, dl);
10850 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
10855 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
10857 MVT OpVT = Op.getSimpleValueType();
10859 // If this is a 256-bit vector result, first insert into a 128-bit
10860 // vector and then insert into the 256-bit vector.
10861 if (!OpVT.is128BitVector()) {
10862 // Insert into a 128-bit vector.
10863 unsigned SizeFactor = OpVT.getSizeInBits()/128;
10864 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
10865 OpVT.getVectorNumElements() / SizeFactor);
10867 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
10869 // Insert the 128-bit vector.
10870 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
10873 if (OpVT == MVT::v1i64 &&
10874 Op.getOperand(0).getValueType() == MVT::i64)
10875 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
10877 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
10878 assert(OpVT.is128BitVector() && "Expected an SSE type!");
10879 return DAG.getBitcast(
10880 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
10883 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
10884 // a simple subregister reference or explicit instructions to grab
10885 // upper bits of a vector.
10886 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10887 SelectionDAG &DAG) {
10889 SDValue In = Op.getOperand(0);
10890 SDValue Idx = Op.getOperand(1);
10891 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10892 MVT ResVT = Op.getSimpleValueType();
10893 MVT InVT = In.getSimpleValueType();
10895 if (Subtarget->hasFp256()) {
10896 if (ResVT.is128BitVector() &&
10897 (InVT.is256BitVector() || InVT.is512BitVector()) &&
10898 isa<ConstantSDNode>(Idx)) {
10899 return Extract128BitVector(In, IdxVal, DAG, dl);
10901 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
10902 isa<ConstantSDNode>(Idx)) {
10903 return Extract256BitVector(In, IdxVal, DAG, dl);
10909 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
10910 // simple superregister reference or explicit instructions to insert
10911 // the upper bits of a vector.
10912 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
10913 SelectionDAG &DAG) {
10914 if (!Subtarget->hasAVX())
10918 SDValue Vec = Op.getOperand(0);
10919 SDValue SubVec = Op.getOperand(1);
10920 SDValue Idx = Op.getOperand(2);
10922 if (!isa<ConstantSDNode>(Idx))
10925 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10926 MVT OpVT = Op.getSimpleValueType();
10927 MVT SubVecVT = SubVec.getSimpleValueType();
10929 // Fold two 16-byte subvector loads into one 32-byte load:
10930 // (insert_subvector (insert_subvector undef, (load addr), 0),
10931 // (load addr + 16), Elts/2)
10933 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
10934 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
10935 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
10936 !Subtarget->isUnalignedMem32Slow()) {
10937 SDValue SubVec2 = Vec.getOperand(1);
10938 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
10939 if (Idx2->getZExtValue() == 0) {
10940 SDValue Ops[] = { SubVec2, SubVec };
10941 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
10947 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
10948 SubVecVT.is128BitVector())
10949 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
10951 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
10952 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
10954 if (OpVT.getVectorElementType() == MVT::i1) {
10955 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
10957 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
10958 SDValue Undef = DAG.getUNDEF(OpVT);
10959 unsigned NumElems = OpVT.getVectorNumElements();
10960 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
10962 if (IdxVal == OpVT.getVectorNumElements() / 2) {
10963 // Zero upper bits of the Vec
10964 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10965 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10967 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10969 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10970 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10973 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
10975 // Zero upper bits of the Vec2
10976 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
10977 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
10978 // Zero lower bits of the Vec
10979 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
10980 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
10981 // Merge them together
10982 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
10988 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
10989 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
10990 // one of the above mentioned nodes. It has to be wrapped because otherwise
10991 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
10992 // be used to form addressing mode. These wrapped nodes will be selected
10995 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
10996 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
10998 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
10999 // global base reg.
11000 unsigned char OpFlag = 0;
11001 unsigned WrapperKind = X86ISD::Wrapper;
11002 CodeModel::Model M = DAG.getTarget().getCodeModel();
11004 if (Subtarget->isPICStyleRIPRel() &&
11005 (M == CodeModel::Small || M == CodeModel::Kernel))
11006 WrapperKind = X86ISD::WrapperRIP;
11007 else if (Subtarget->isPICStyleGOT())
11008 OpFlag = X86II::MO_GOTOFF;
11009 else if (Subtarget->isPICStyleStubPIC())
11010 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11012 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11013 CP->getAlignment(),
11014 CP->getOffset(), OpFlag);
11016 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11017 // With PIC, the address is actually $g + Offset.
11019 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11020 DAG.getNode(X86ISD::GlobalBaseReg,
11021 SDLoc(), getPointerTy()),
11028 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11029 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11031 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11032 // global base reg.
11033 unsigned char OpFlag = 0;
11034 unsigned WrapperKind = X86ISD::Wrapper;
11035 CodeModel::Model M = DAG.getTarget().getCodeModel();
11037 if (Subtarget->isPICStyleRIPRel() &&
11038 (M == CodeModel::Small || M == CodeModel::Kernel))
11039 WrapperKind = X86ISD::WrapperRIP;
11040 else if (Subtarget->isPICStyleGOT())
11041 OpFlag = X86II::MO_GOTOFF;
11042 else if (Subtarget->isPICStyleStubPIC())
11043 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11045 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11048 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11050 // With PIC, the address is actually $g + Offset.
11052 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11053 DAG.getNode(X86ISD::GlobalBaseReg,
11054 SDLoc(), getPointerTy()),
11061 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11062 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11064 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11065 // global base reg.
11066 unsigned char OpFlag = 0;
11067 unsigned WrapperKind = X86ISD::Wrapper;
11068 CodeModel::Model M = DAG.getTarget().getCodeModel();
11070 if (Subtarget->isPICStyleRIPRel() &&
11071 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11072 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11073 OpFlag = X86II::MO_GOTPCREL;
11074 WrapperKind = X86ISD::WrapperRIP;
11075 } else if (Subtarget->isPICStyleGOT()) {
11076 OpFlag = X86II::MO_GOT;
11077 } else if (Subtarget->isPICStyleStubPIC()) {
11078 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11079 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11080 OpFlag = X86II::MO_DARWIN_NONLAZY;
11083 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11086 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11088 // With PIC, the address is actually $g + Offset.
11089 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11090 !Subtarget->is64Bit()) {
11091 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11092 DAG.getNode(X86ISD::GlobalBaseReg,
11093 SDLoc(), getPointerTy()),
11097 // For symbols that require a load from a stub to get the address, emit the
11099 if (isGlobalStubReference(OpFlag))
11100 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11101 MachinePointerInfo::getGOT(), false, false, false, 0);
11107 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11108 // Create the TargetBlockAddressAddress node.
11109 unsigned char OpFlags =
11110 Subtarget->ClassifyBlockAddressReference();
11111 CodeModel::Model M = DAG.getTarget().getCodeModel();
11112 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11113 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11115 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11118 if (Subtarget->isPICStyleRIPRel() &&
11119 (M == CodeModel::Small || M == CodeModel::Kernel))
11120 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11122 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11124 // With PIC, the address is actually $g + Offset.
11125 if (isGlobalRelativeToPICBase(OpFlags)) {
11126 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11127 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11135 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11136 int64_t Offset, SelectionDAG &DAG) const {
11137 // Create the TargetGlobalAddress node, folding in the constant
11138 // offset if it is legal.
11139 unsigned char OpFlags =
11140 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11141 CodeModel::Model M = DAG.getTarget().getCodeModel();
11143 if (OpFlags == X86II::MO_NO_FLAG &&
11144 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11145 // A direct static reference to a global.
11146 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11149 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11152 if (Subtarget->isPICStyleRIPRel() &&
11153 (M == CodeModel::Small || M == CodeModel::Kernel))
11154 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11156 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11158 // With PIC, the address is actually $g + Offset.
11159 if (isGlobalRelativeToPICBase(OpFlags)) {
11160 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11161 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11165 // For globals that require a load from a stub to get the address, emit the
11167 if (isGlobalStubReference(OpFlags))
11168 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11169 MachinePointerInfo::getGOT(), false, false, false, 0);
11171 // If there was a non-zero offset that we didn't fold, create an explicit
11172 // addition for it.
11174 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11175 DAG.getConstant(Offset, dl, getPointerTy()));
11181 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11182 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11183 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11184 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11188 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11189 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11190 unsigned char OperandFlags, bool LocalDynamic = false) {
11191 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11192 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11194 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11195 GA->getValueType(0),
11199 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11203 SDValue Ops[] = { Chain, TGA, *InFlag };
11204 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11206 SDValue Ops[] = { Chain, TGA };
11207 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11210 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11211 MFI->setAdjustsStack(true);
11212 MFI->setHasCalls(true);
11214 SDValue Flag = Chain.getValue(1);
11215 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11218 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11220 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11223 SDLoc dl(GA); // ? function entry point might be better
11224 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11225 DAG.getNode(X86ISD::GlobalBaseReg,
11226 SDLoc(), PtrVT), InFlag);
11227 InFlag = Chain.getValue(1);
11229 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11232 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11234 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11236 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11237 X86::RAX, X86II::MO_TLSGD);
11240 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11246 // Get the start address of the TLS block for this module.
11247 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11248 .getInfo<X86MachineFunctionInfo>();
11249 MFI->incNumLocalDynamicTLSAccesses();
11253 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11254 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11257 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11258 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11259 InFlag = Chain.getValue(1);
11260 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11261 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11264 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11268 unsigned char OperandFlags = X86II::MO_DTPOFF;
11269 unsigned WrapperKind = X86ISD::Wrapper;
11270 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11271 GA->getValueType(0),
11272 GA->getOffset(), OperandFlags);
11273 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11275 // Add x@dtpoff with the base.
11276 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11279 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11280 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11281 const EVT PtrVT, TLSModel::Model model,
11282 bool is64Bit, bool isPIC) {
11285 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11286 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11287 is64Bit ? 257 : 256));
11289 SDValue ThreadPointer =
11290 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11291 MachinePointerInfo(Ptr), false, false, false, 0);
11293 unsigned char OperandFlags = 0;
11294 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11296 unsigned WrapperKind = X86ISD::Wrapper;
11297 if (model == TLSModel::LocalExec) {
11298 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11299 } else if (model == TLSModel::InitialExec) {
11301 OperandFlags = X86II::MO_GOTTPOFF;
11302 WrapperKind = X86ISD::WrapperRIP;
11304 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11307 llvm_unreachable("Unexpected model");
11310 // emit "addl x@ntpoff,%eax" (local exec)
11311 // or "addl x@indntpoff,%eax" (initial exec)
11312 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11314 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11315 GA->getOffset(), OperandFlags);
11316 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11318 if (model == TLSModel::InitialExec) {
11319 if (isPIC && !is64Bit) {
11320 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11321 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11325 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11326 MachinePointerInfo::getGOT(), false, false, false, 0);
11329 // The address of the thread local variable is the add of the thread
11330 // pointer with the offset of the variable.
11331 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11335 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11337 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11338 const GlobalValue *GV = GA->getGlobal();
11340 if (Subtarget->isTargetELF()) {
11341 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11343 case TLSModel::GeneralDynamic:
11344 if (Subtarget->is64Bit())
11345 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11346 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11347 case TLSModel::LocalDynamic:
11348 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11349 Subtarget->is64Bit());
11350 case TLSModel::InitialExec:
11351 case TLSModel::LocalExec:
11352 return LowerToTLSExecModel(
11353 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11354 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11356 llvm_unreachable("Unknown TLS model.");
11359 if (Subtarget->isTargetDarwin()) {
11360 // Darwin only has one model of TLS. Lower to that.
11361 unsigned char OpFlag = 0;
11362 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11363 X86ISD::WrapperRIP : X86ISD::Wrapper;
11365 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11366 // global base reg.
11367 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11368 !Subtarget->is64Bit();
11370 OpFlag = X86II::MO_TLVP_PIC_BASE;
11372 OpFlag = X86II::MO_TLVP;
11374 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11375 GA->getValueType(0),
11376 GA->getOffset(), OpFlag);
11377 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11379 // With PIC32, the address is actually $g + Offset.
11381 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11382 DAG.getNode(X86ISD::GlobalBaseReg,
11383 SDLoc(), getPointerTy()),
11386 // Lowering the machine isd will make sure everything is in the right
11388 SDValue Chain = DAG.getEntryNode();
11389 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11390 SDValue Args[] = { Chain, Offset };
11391 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11393 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11394 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11395 MFI->setAdjustsStack(true);
11397 // And our return value (tls address) is in the standard call return value
11399 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11400 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11401 Chain.getValue(1));
11404 if (Subtarget->isTargetKnownWindowsMSVC() ||
11405 Subtarget->isTargetWindowsGNU()) {
11406 // Just use the implicit TLS architecture
11407 // Need to generate someting similar to:
11408 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11410 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11411 // mov rcx, qword [rdx+rcx*8]
11412 // mov eax, .tls$:tlsvar
11413 // [rax+rcx] contains the address
11414 // Windows 64bit: gs:0x58
11415 // Windows 32bit: fs:__tls_array
11418 SDValue Chain = DAG.getEntryNode();
11420 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11421 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11422 // use its literal value of 0x2C.
11423 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11424 ? Type::getInt8PtrTy(*DAG.getContext(),
11426 : Type::getInt32PtrTy(*DAG.getContext(),
11430 Subtarget->is64Bit()
11431 ? DAG.getIntPtrConstant(0x58, dl)
11432 : (Subtarget->isTargetWindowsGNU()
11433 ? DAG.getIntPtrConstant(0x2C, dl)
11434 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11436 SDValue ThreadPointer =
11437 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11438 MachinePointerInfo(Ptr), false, false, false, 0);
11441 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11442 res = ThreadPointer;
11444 // Load the _tls_index variable
11445 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11446 if (Subtarget->is64Bit())
11447 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11448 MachinePointerInfo(), MVT::i32, false, false,
11451 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11452 false, false, false, 0);
11454 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11456 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11458 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11461 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11462 false, false, false, 0);
11464 // Get the offset of start of .tls section
11465 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11466 GA->getValueType(0),
11467 GA->getOffset(), X86II::MO_SECREL);
11468 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11470 // The address of the thread local variable is the add of the thread
11471 // pointer with the offset of the variable.
11472 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11475 llvm_unreachable("TLS not implemented for this target.");
11478 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11479 /// and take a 2 x i32 value to shift plus a shift amount.
11480 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11481 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11482 MVT VT = Op.getSimpleValueType();
11483 unsigned VTBits = VT.getSizeInBits();
11485 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11486 SDValue ShOpLo = Op.getOperand(0);
11487 SDValue ShOpHi = Op.getOperand(1);
11488 SDValue ShAmt = Op.getOperand(2);
11489 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11490 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11492 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11493 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11494 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11495 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11496 : DAG.getConstant(0, dl, VT);
11498 SDValue Tmp2, Tmp3;
11499 if (Op.getOpcode() == ISD::SHL_PARTS) {
11500 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11501 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11503 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11504 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11507 // If the shift amount is larger or equal than the width of a part we can't
11508 // rely on the results of shld/shrd. Insert a test and select the appropriate
11509 // values for large shift amounts.
11510 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11511 DAG.getConstant(VTBits, dl, MVT::i8));
11512 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11513 AndNode, DAG.getConstant(0, dl, MVT::i8));
11516 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11517 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11518 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11520 if (Op.getOpcode() == ISD::SHL_PARTS) {
11521 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11522 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11524 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11525 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11528 SDValue Ops[2] = { Lo, Hi };
11529 return DAG.getMergeValues(Ops, dl);
11532 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11533 SelectionDAG &DAG) const {
11534 SDValue Src = Op.getOperand(0);
11535 MVT SrcVT = Src.getSimpleValueType();
11536 MVT VT = Op.getSimpleValueType();
11539 if (SrcVT.isVector()) {
11540 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
11541 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
11542 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
11543 DAG.getUNDEF(SrcVT)));
11545 if (SrcVT.getVectorElementType() == MVT::i1) {
11546 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11547 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11548 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
11553 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11554 "Unknown SINT_TO_FP to lower!");
11556 // These are really Legal; return the operand so the caller accepts it as
11558 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11560 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11561 Subtarget->is64Bit()) {
11565 unsigned Size = SrcVT.getSizeInBits()/8;
11566 MachineFunction &MF = DAG.getMachineFunction();
11567 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11568 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11569 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11571 MachinePointerInfo::getFixedStack(SSFI),
11573 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11576 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11578 SelectionDAG &DAG) const {
11582 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11584 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11586 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11588 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11590 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11591 MachineMemOperand *MMO;
11593 int SSFI = FI->getIndex();
11595 DAG.getMachineFunction()
11596 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11597 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11599 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11600 StackSlot = StackSlot.getOperand(1);
11602 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11603 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11605 Tys, Ops, SrcVT, MMO);
11608 Chain = Result.getValue(1);
11609 SDValue InFlag = Result.getValue(2);
11611 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11612 // shouldn't be necessary except that RFP cannot be live across
11613 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11614 MachineFunction &MF = DAG.getMachineFunction();
11615 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11616 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11617 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11618 Tys = DAG.getVTList(MVT::Other);
11620 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11622 MachineMemOperand *MMO =
11623 DAG.getMachineFunction()
11624 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11625 MachineMemOperand::MOStore, SSFISize, SSFISize);
11627 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11628 Ops, Op.getValueType(), MMO);
11629 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11630 MachinePointerInfo::getFixedStack(SSFI),
11631 false, false, false, 0);
11637 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11638 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11639 SelectionDAG &DAG) const {
11640 // This algorithm is not obvious. Here it is what we're trying to output:
11643 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11644 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11646 haddpd %xmm0, %xmm0
11648 pshufd $0x4e, %xmm0, %xmm1
11654 LLVMContext *Context = DAG.getContext();
11656 // Build some magic constants.
11657 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11658 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11659 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11661 SmallVector<Constant*,2> CV1;
11663 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11664 APInt(64, 0x4330000000000000ULL))));
11666 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11667 APInt(64, 0x4530000000000000ULL))));
11668 Constant *C1 = ConstantVector::get(CV1);
11669 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11671 // Load the 64-bit value into an XMM register.
11672 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11674 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11675 MachinePointerInfo::getConstantPool(),
11676 false, false, false, 16);
11678 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
11680 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11681 MachinePointerInfo::getConstantPool(),
11682 false, false, false, 16);
11683 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
11684 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11687 if (Subtarget->hasSSE3()) {
11688 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11689 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11691 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
11692 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11694 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11695 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
11698 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11699 DAG.getIntPtrConstant(0, dl));
11702 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11703 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11704 SelectionDAG &DAG) const {
11706 // FP constant to bias correct the final result.
11707 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11710 // Load the 32-bit value into an XMM register.
11711 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11714 // Zero out the upper parts of the register.
11715 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11717 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11718 DAG.getBitcast(MVT::v2f64, Load),
11719 DAG.getIntPtrConstant(0, dl));
11721 // Or the load with the bias.
11722 SDValue Or = DAG.getNode(
11723 ISD::OR, dl, MVT::v2i64,
11724 DAG.getBitcast(MVT::v2i64,
11725 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
11726 DAG.getBitcast(MVT::v2i64,
11727 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
11729 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11730 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
11732 // Subtract the bias.
11733 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11735 // Handle final rounding.
11736 EVT DestVT = Op.getValueType();
11738 if (DestVT.bitsLT(MVT::f64))
11739 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11740 DAG.getIntPtrConstant(0, dl));
11741 if (DestVT.bitsGT(MVT::f64))
11742 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11744 // Handle final rounding.
11748 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11749 const X86Subtarget &Subtarget) {
11750 // The algorithm is the following:
11751 // #ifdef __SSE4_1__
11752 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11753 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11754 // (uint4) 0x53000000, 0xaa);
11756 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11757 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11759 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11760 // return (float4) lo + fhi;
11763 SDValue V = Op->getOperand(0);
11764 EVT VecIntVT = V.getValueType();
11765 bool Is128 = VecIntVT == MVT::v4i32;
11766 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
11767 // If we convert to something else than the supported type, e.g., to v4f64,
11769 if (VecFloatVT != Op->getValueType(0))
11772 unsigned NumElts = VecIntVT.getVectorNumElements();
11773 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
11774 "Unsupported custom type");
11775 assert(NumElts <= 8 && "The size of the constant array must be fixed");
11777 // In the #idef/#else code, we have in common:
11778 // - The vector of constants:
11784 // Create the splat vector for 0x4b000000.
11785 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
11786 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
11787 CstLow, CstLow, CstLow, CstLow};
11788 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11789 makeArrayRef(&CstLowArray[0], NumElts));
11790 // Create the splat vector for 0x53000000.
11791 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
11792 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
11793 CstHigh, CstHigh, CstHigh, CstHigh};
11794 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11795 makeArrayRef(&CstHighArray[0], NumElts));
11797 // Create the right shift.
11798 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
11799 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
11800 CstShift, CstShift, CstShift, CstShift};
11801 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
11802 makeArrayRef(&CstShiftArray[0], NumElts));
11803 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
11806 if (Subtarget.hasSSE41()) {
11807 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
11808 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11809 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
11810 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
11811 // Low will be bitcasted right away, so do not bother bitcasting back to its
11813 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
11814 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11815 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11816 // (uint4) 0x53000000, 0xaa);
11817 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
11818 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
11819 // High will be bitcasted right away, so do not bother bitcasting back to
11820 // its original type.
11821 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
11822 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
11824 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
11825 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
11826 CstMask, CstMask, CstMask);
11827 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11828 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
11829 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
11831 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11832 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
11835 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
11836 SDValue CstFAdd = DAG.getConstantFP(
11837 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
11838 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
11839 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
11840 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
11841 makeArrayRef(&CstFAddArray[0], NumElts));
11843 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11844 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
11846 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
11847 // return (float4) lo + fhi;
11848 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
11849 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
11852 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
11853 SelectionDAG &DAG) const {
11854 SDValue N0 = Op.getOperand(0);
11855 MVT SVT = N0.getSimpleValueType();
11858 switch (SVT.SimpleTy) {
11860 llvm_unreachable("Custom UINT_TO_FP is not supported!");
11865 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
11866 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11867 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
11871 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
11874 if (Subtarget->hasAVX512())
11875 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
11876 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
11878 llvm_unreachable(nullptr);
11881 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
11882 SelectionDAG &DAG) const {
11883 SDValue N0 = Op.getOperand(0);
11886 if (Op.getValueType().isVector())
11887 return lowerUINT_TO_FP_vec(Op, DAG);
11889 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
11890 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
11891 // the optimization here.
11892 if (DAG.SignBitIsZero(N0))
11893 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
11895 MVT SrcVT = N0.getSimpleValueType();
11896 MVT DstVT = Op.getSimpleValueType();
11897 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
11898 return LowerUINT_TO_FP_i64(Op, DAG);
11899 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
11900 return LowerUINT_TO_FP_i32(Op, DAG);
11901 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
11904 // Make a 64-bit buffer, and use it to build an FILD.
11905 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
11906 if (SrcVT == MVT::i32) {
11907 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
11908 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
11909 getPointerTy(), StackSlot, WordOff);
11910 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11911 StackSlot, MachinePointerInfo(),
11913 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
11914 OffsetSlot, MachinePointerInfo(),
11916 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
11920 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
11921 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11922 StackSlot, MachinePointerInfo(),
11924 // For i64 source, we need to add the appropriate power of 2 if the input
11925 // was negative. This is the same as the optimization in
11926 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
11927 // we must be careful to do the computation in x87 extended precision, not
11928 // in SSE. (The generic code can't know it's OK to do this, or how to.)
11929 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
11930 MachineMemOperand *MMO =
11931 DAG.getMachineFunction()
11932 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11933 MachineMemOperand::MOLoad, 8, 8);
11935 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
11936 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
11937 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
11940 APInt FF(32, 0x5F800000ULL);
11942 // Check whether the sign bit is set.
11943 SDValue SignSet = DAG.getSetCC(dl,
11944 getSetCCResultType(*DAG.getContext(), MVT::i64),
11946 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
11948 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
11949 SDValue FudgePtr = DAG.getConstantPool(
11950 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
11953 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
11954 SDValue Zero = DAG.getIntPtrConstant(0, dl);
11955 SDValue Four = DAG.getIntPtrConstant(4, dl);
11956 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
11958 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
11960 // Load the value out, extending it from f32 to f80.
11961 // FIXME: Avoid the extend by constructing the right constant pool?
11962 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
11963 FudgePtr, MachinePointerInfo::getConstantPool(),
11964 MVT::f32, false, false, false, 4);
11965 // Extend everything to 80 bits to force it to be done on x87.
11966 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
11967 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
11968 DAG.getIntPtrConstant(0, dl));
11971 std::pair<SDValue,SDValue>
11972 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
11973 bool IsSigned, bool IsReplace) const {
11976 EVT DstTy = Op.getValueType();
11978 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
11979 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
11983 assert(DstTy.getSimpleVT() <= MVT::i64 &&
11984 DstTy.getSimpleVT() >= MVT::i16 &&
11985 "Unknown FP_TO_INT to lower!");
11987 // These are really Legal.
11988 if (DstTy == MVT::i32 &&
11989 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11990 return std::make_pair(SDValue(), SDValue());
11991 if (Subtarget->is64Bit() &&
11992 DstTy == MVT::i64 &&
11993 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
11994 return std::make_pair(SDValue(), SDValue());
11996 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
11997 // stack slot, or into the FTOL runtime function.
11998 MachineFunction &MF = DAG.getMachineFunction();
11999 unsigned MemSize = DstTy.getSizeInBits()/8;
12000 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12001 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12004 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12005 Opc = X86ISD::WIN_FTOL;
12007 switch (DstTy.getSimpleVT().SimpleTy) {
12008 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12009 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12010 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12011 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12014 SDValue Chain = DAG.getEntryNode();
12015 SDValue Value = Op.getOperand(0);
12016 EVT TheVT = Op.getOperand(0).getValueType();
12017 // FIXME This causes a redundant load/store if the SSE-class value is already
12018 // in memory, such as if it is on the callstack.
12019 if (isScalarFPTypeInSSEReg(TheVT)) {
12020 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12021 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12022 MachinePointerInfo::getFixedStack(SSFI),
12024 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12026 Chain, StackSlot, DAG.getValueType(TheVT)
12029 MachineMemOperand *MMO =
12030 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12031 MachineMemOperand::MOLoad, MemSize, MemSize);
12032 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12033 Chain = Value.getValue(1);
12034 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12035 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12038 MachineMemOperand *MMO =
12039 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12040 MachineMemOperand::MOStore, MemSize, MemSize);
12042 if (Opc != X86ISD::WIN_FTOL) {
12043 // Build the FP_TO_INT*_IN_MEM
12044 SDValue Ops[] = { Chain, Value, StackSlot };
12045 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12047 return std::make_pair(FIST, StackSlot);
12049 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12050 DAG.getVTList(MVT::Other, MVT::Glue),
12052 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12053 MVT::i32, ftol.getValue(1));
12054 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12055 MVT::i32, eax.getValue(2));
12056 SDValue Ops[] = { eax, edx };
12057 SDValue pair = IsReplace
12058 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12059 : DAG.getMergeValues(Ops, DL);
12060 return std::make_pair(pair, SDValue());
12064 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12065 const X86Subtarget *Subtarget) {
12066 MVT VT = Op->getSimpleValueType(0);
12067 SDValue In = Op->getOperand(0);
12068 MVT InVT = In.getSimpleValueType();
12071 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12072 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12074 // Optimize vectors in AVX mode:
12077 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12078 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12079 // Concat upper and lower parts.
12082 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12083 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12084 // Concat upper and lower parts.
12087 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12088 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12089 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12092 if (Subtarget->hasInt256())
12093 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12095 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12096 SDValue Undef = DAG.getUNDEF(InVT);
12097 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12098 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12099 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12101 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12102 VT.getVectorNumElements()/2);
12104 OpLo = DAG.getBitcast(HVT, OpLo);
12105 OpHi = DAG.getBitcast(HVT, OpHi);
12107 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12110 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12111 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12112 MVT VT = Op->getSimpleValueType(0);
12113 SDValue In = Op->getOperand(0);
12114 MVT InVT = In.getSimpleValueType();
12116 unsigned int NumElts = VT.getVectorNumElements();
12117 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12120 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12121 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12123 assert(InVT.getVectorElementType() == MVT::i1);
12124 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12126 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12128 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12130 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12131 if (VT.is512BitVector())
12133 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12136 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12137 SelectionDAG &DAG) {
12138 if (Subtarget->hasFp256())
12139 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12145 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12146 SelectionDAG &DAG) {
12148 MVT VT = Op.getSimpleValueType();
12149 SDValue In = Op.getOperand(0);
12150 MVT SVT = In.getSimpleValueType();
12152 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12153 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12155 if (Subtarget->hasFp256())
12156 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12159 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12160 VT.getVectorNumElements() != SVT.getVectorNumElements());
12164 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12166 MVT VT = Op.getSimpleValueType();
12167 SDValue In = Op.getOperand(0);
12168 MVT InVT = In.getSimpleValueType();
12170 if (VT == MVT::i1) {
12171 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12172 "Invalid scalar TRUNCATE operation");
12173 if (InVT.getSizeInBits() >= 32)
12175 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12176 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12178 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12179 "Invalid TRUNCATE operation");
12181 // move vector to mask - truncate solution for SKX
12182 if (VT.getVectorElementType() == MVT::i1) {
12183 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12184 Subtarget->hasBWI())
12185 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12186 if ((InVT.is256BitVector() || InVT.is128BitVector())
12187 && InVT.getScalarSizeInBits() <= 16 &&
12188 Subtarget->hasBWI() && Subtarget->hasVLX())
12189 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12190 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12191 Subtarget->hasDQI())
12192 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12193 if ((InVT.is256BitVector() || InVT.is128BitVector())
12194 && InVT.getScalarSizeInBits() >= 32 &&
12195 Subtarget->hasDQI() && Subtarget->hasVLX())
12196 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12198 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12199 if (VT.getVectorElementType().getSizeInBits() >=8)
12200 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12202 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12203 unsigned NumElts = InVT.getVectorNumElements();
12204 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12205 if (InVT.getSizeInBits() < 512) {
12206 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12207 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12212 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12213 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12214 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12217 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12218 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12219 if (Subtarget->hasInt256()) {
12220 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12221 In = DAG.getBitcast(MVT::v8i32, In);
12222 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12224 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12225 DAG.getIntPtrConstant(0, DL));
12228 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12229 DAG.getIntPtrConstant(0, DL));
12230 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12231 DAG.getIntPtrConstant(2, DL));
12232 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12233 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12234 static const int ShufMask[] = {0, 2, 4, 6};
12235 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12238 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12239 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12240 if (Subtarget->hasInt256()) {
12241 In = DAG.getBitcast(MVT::v32i8, In);
12243 SmallVector<SDValue,32> pshufbMask;
12244 for (unsigned i = 0; i < 2; ++i) {
12245 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12246 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12247 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12248 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12249 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12250 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12251 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12252 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12253 for (unsigned j = 0; j < 8; ++j)
12254 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12256 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12257 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12258 In = DAG.getBitcast(MVT::v4i64, In);
12260 static const int ShufMask[] = {0, 2, -1, -1};
12261 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12263 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12264 DAG.getIntPtrConstant(0, DL));
12265 return DAG.getBitcast(VT, In);
12268 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12269 DAG.getIntPtrConstant(0, DL));
12271 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12272 DAG.getIntPtrConstant(4, DL));
12274 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12275 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12277 // The PSHUFB mask:
12278 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12279 -1, -1, -1, -1, -1, -1, -1, -1};
12281 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12282 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12283 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12285 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12286 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12288 // The MOVLHPS Mask:
12289 static const int ShufMask2[] = {0, 1, 4, 5};
12290 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12291 return DAG.getBitcast(MVT::v8i16, res);
12294 // Handle truncation of V256 to V128 using shuffles.
12295 if (!VT.is128BitVector() || !InVT.is256BitVector())
12298 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12300 unsigned NumElems = VT.getVectorNumElements();
12301 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12303 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12304 // Prepare truncation shuffle mask
12305 for (unsigned i = 0; i != NumElems; ++i)
12306 MaskVec[i] = i * 2;
12307 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12308 DAG.getUNDEF(NVT), &MaskVec[0]);
12309 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12310 DAG.getIntPtrConstant(0, DL));
12313 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12314 SelectionDAG &DAG) const {
12315 assert(!Op.getSimpleValueType().isVector());
12317 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12318 /*IsSigned=*/ true, /*IsReplace=*/ false);
12319 SDValue FIST = Vals.first, StackSlot = Vals.second;
12320 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12321 if (!FIST.getNode()) return Op;
12323 if (StackSlot.getNode())
12324 // Load the result.
12325 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12326 FIST, StackSlot, MachinePointerInfo(),
12327 false, false, false, 0);
12329 // The node is the result.
12333 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12334 SelectionDAG &DAG) const {
12335 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12336 /*IsSigned=*/ false, /*IsReplace=*/ false);
12337 SDValue FIST = Vals.first, StackSlot = Vals.second;
12338 assert(FIST.getNode() && "Unexpected failure");
12340 if (StackSlot.getNode())
12341 // Load the result.
12342 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12343 FIST, StackSlot, MachinePointerInfo(),
12344 false, false, false, 0);
12346 // The node is the result.
12350 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12352 MVT VT = Op.getSimpleValueType();
12353 SDValue In = Op.getOperand(0);
12354 MVT SVT = In.getSimpleValueType();
12356 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12358 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12359 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12360 In, DAG.getUNDEF(SVT)));
12363 /// The only differences between FABS and FNEG are the mask and the logic op.
12364 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12365 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12366 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12367 "Wrong opcode for lowering FABS or FNEG.");
12369 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12371 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12372 // into an FNABS. We'll lower the FABS after that if it is still in use.
12374 for (SDNode *User : Op->uses())
12375 if (User->getOpcode() == ISD::FNEG)
12378 SDValue Op0 = Op.getOperand(0);
12379 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12382 MVT VT = Op.getSimpleValueType();
12383 // Assume scalar op for initialization; update for vector if needed.
12384 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12385 // generate a 16-byte vector constant and logic op even for the scalar case.
12386 // Using a 16-byte mask allows folding the load of the mask with
12387 // the logic op, so it can save (~4 bytes) on code size.
12389 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12390 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12391 // decide if we should generate a 16-byte constant mask when we only need 4 or
12392 // 8 bytes for the scalar case.
12393 if (VT.isVector()) {
12394 EltVT = VT.getVectorElementType();
12395 NumElts = VT.getVectorNumElements();
12398 unsigned EltBits = EltVT.getSizeInBits();
12399 LLVMContext *Context = DAG.getContext();
12400 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12402 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12403 Constant *C = ConstantInt::get(*Context, MaskElt);
12404 C = ConstantVector::getSplat(NumElts, C);
12405 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12406 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12407 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12408 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12409 MachinePointerInfo::getConstantPool(),
12410 false, false, false, Alignment);
12412 if (VT.isVector()) {
12413 // For a vector, cast operands to a vector type, perform the logic op,
12414 // and cast the result back to the original value type.
12415 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12416 SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);
12417 SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))
12418 : DAG.getBitcast(VecVT, Op0);
12419 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12420 return DAG.getBitcast(VT,
12421 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12424 // If not vector, then scalar.
12425 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12426 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12427 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12430 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12431 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12432 LLVMContext *Context = DAG.getContext();
12433 SDValue Op0 = Op.getOperand(0);
12434 SDValue Op1 = Op.getOperand(1);
12436 MVT VT = Op.getSimpleValueType();
12437 MVT SrcVT = Op1.getSimpleValueType();
12439 // If second operand is smaller, extend it first.
12440 if (SrcVT.bitsLT(VT)) {
12441 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12444 // And if it is bigger, shrink it first.
12445 if (SrcVT.bitsGT(VT)) {
12446 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12450 // At this point the operands and the result should have the same
12451 // type, and that won't be f80 since that is not custom lowered.
12453 const fltSemantics &Sem =
12454 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12455 const unsigned SizeInBits = VT.getSizeInBits();
12457 SmallVector<Constant *, 4> CV(
12458 VT == MVT::f64 ? 2 : 4,
12459 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12461 // First, clear all bits but the sign bit from the second operand (sign).
12462 CV[0] = ConstantFP::get(*Context,
12463 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12464 Constant *C = ConstantVector::get(CV);
12465 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12466 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12467 MachinePointerInfo::getConstantPool(),
12468 false, false, false, 16);
12469 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12471 // Next, clear the sign bit from the first operand (magnitude).
12472 // If it's a constant, we can clear it here.
12473 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12474 APFloat APF = Op0CN->getValueAPF();
12475 // If the magnitude is a positive zero, the sign bit alone is enough.
12476 if (APF.isPosZero())
12479 CV[0] = ConstantFP::get(*Context, APF);
12481 CV[0] = ConstantFP::get(
12483 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12485 C = ConstantVector::get(CV);
12486 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12487 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12488 MachinePointerInfo::getConstantPool(),
12489 false, false, false, 16);
12490 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12491 if (!isa<ConstantFPSDNode>(Op0))
12492 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12494 // OR the magnitude value with the sign bit.
12495 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12498 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12499 SDValue N0 = Op.getOperand(0);
12501 MVT VT = Op.getSimpleValueType();
12503 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12504 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12505 DAG.getConstant(1, dl, VT));
12506 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12509 // Check whether an OR'd tree is PTEST-able.
12510 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12511 SelectionDAG &DAG) {
12512 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12514 if (!Subtarget->hasSSE41())
12517 if (!Op->hasOneUse())
12520 SDNode *N = Op.getNode();
12523 SmallVector<SDValue, 8> Opnds;
12524 DenseMap<SDValue, unsigned> VecInMap;
12525 SmallVector<SDValue, 8> VecIns;
12526 EVT VT = MVT::Other;
12528 // Recognize a special case where a vector is casted into wide integer to
12530 Opnds.push_back(N->getOperand(0));
12531 Opnds.push_back(N->getOperand(1));
12533 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12534 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12535 // BFS traverse all OR'd operands.
12536 if (I->getOpcode() == ISD::OR) {
12537 Opnds.push_back(I->getOperand(0));
12538 Opnds.push_back(I->getOperand(1));
12539 // Re-evaluate the number of nodes to be traversed.
12540 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12544 // Quit if a non-EXTRACT_VECTOR_ELT
12545 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12548 // Quit if without a constant index.
12549 SDValue Idx = I->getOperand(1);
12550 if (!isa<ConstantSDNode>(Idx))
12553 SDValue ExtractedFromVec = I->getOperand(0);
12554 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12555 if (M == VecInMap.end()) {
12556 VT = ExtractedFromVec.getValueType();
12557 // Quit if not 128/256-bit vector.
12558 if (!VT.is128BitVector() && !VT.is256BitVector())
12560 // Quit if not the same type.
12561 if (VecInMap.begin() != VecInMap.end() &&
12562 VT != VecInMap.begin()->first.getValueType())
12564 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12565 VecIns.push_back(ExtractedFromVec);
12567 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12570 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12571 "Not extracted from 128-/256-bit vector.");
12573 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12575 for (DenseMap<SDValue, unsigned>::const_iterator
12576 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12577 // Quit if not all elements are used.
12578 if (I->second != FullMask)
12582 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12584 // Cast all vectors into TestVT for PTEST.
12585 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12586 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12588 // If more than one full vectors are evaluated, OR them first before PTEST.
12589 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12590 // Each iteration will OR 2 nodes and append the result until there is only
12591 // 1 node left, i.e. the final OR'd value of all vectors.
12592 SDValue LHS = VecIns[Slot];
12593 SDValue RHS = VecIns[Slot + 1];
12594 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12597 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12598 VecIns.back(), VecIns.back());
12601 /// \brief return true if \c Op has a use that doesn't just read flags.
12602 static bool hasNonFlagsUse(SDValue Op) {
12603 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12605 SDNode *User = *UI;
12606 unsigned UOpNo = UI.getOperandNo();
12607 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12608 // Look pass truncate.
12609 UOpNo = User->use_begin().getOperandNo();
12610 User = *User->use_begin();
12613 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12614 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12620 /// Emit nodes that will be selected as "test Op0,Op0", or something
12622 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12623 SelectionDAG &DAG) const {
12624 if (Op.getValueType() == MVT::i1) {
12625 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12626 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12627 DAG.getConstant(0, dl, MVT::i8));
12629 // CF and OF aren't always set the way we want. Determine which
12630 // of these we need.
12631 bool NeedCF = false;
12632 bool NeedOF = false;
12635 case X86::COND_A: case X86::COND_AE:
12636 case X86::COND_B: case X86::COND_BE:
12639 case X86::COND_G: case X86::COND_GE:
12640 case X86::COND_L: case X86::COND_LE:
12641 case X86::COND_O: case X86::COND_NO: {
12642 // Check if we really need to set the
12643 // Overflow flag. If NoSignedWrap is present
12644 // that is not actually needed.
12645 switch (Op->getOpcode()) {
12650 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12651 if (BinNode->Flags.hasNoSignedWrap())
12661 // See if we can use the EFLAGS value from the operand instead of
12662 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12663 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12664 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12665 // Emit a CMP with 0, which is the TEST pattern.
12666 //if (Op.getValueType() == MVT::i1)
12667 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12668 // DAG.getConstant(0, MVT::i1));
12669 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12670 DAG.getConstant(0, dl, Op.getValueType()));
12672 unsigned Opcode = 0;
12673 unsigned NumOperands = 0;
12675 // Truncate operations may prevent the merge of the SETCC instruction
12676 // and the arithmetic instruction before it. Attempt to truncate the operands
12677 // of the arithmetic instruction and use a reduced bit-width instruction.
12678 bool NeedTruncation = false;
12679 SDValue ArithOp = Op;
12680 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12681 SDValue Arith = Op->getOperand(0);
12682 // Both the trunc and the arithmetic op need to have one user each.
12683 if (Arith->hasOneUse())
12684 switch (Arith.getOpcode()) {
12691 NeedTruncation = true;
12697 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12698 // which may be the result of a CAST. We use the variable 'Op', which is the
12699 // non-casted variable when we check for possible users.
12700 switch (ArithOp.getOpcode()) {
12702 // Due to an isel shortcoming, be conservative if this add is likely to be
12703 // selected as part of a load-modify-store instruction. When the root node
12704 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12705 // uses of other nodes in the match, such as the ADD in this case. This
12706 // leads to the ADD being left around and reselected, with the result being
12707 // two adds in the output. Alas, even if none our users are stores, that
12708 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12709 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12710 // climbing the DAG back to the root, and it doesn't seem to be worth the
12712 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12713 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12714 if (UI->getOpcode() != ISD::CopyToReg &&
12715 UI->getOpcode() != ISD::SETCC &&
12716 UI->getOpcode() != ISD::STORE)
12719 if (ConstantSDNode *C =
12720 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12721 // An add of one will be selected as an INC.
12722 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12723 Opcode = X86ISD::INC;
12728 // An add of negative one (subtract of one) will be selected as a DEC.
12729 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12730 Opcode = X86ISD::DEC;
12736 // Otherwise use a regular EFLAGS-setting add.
12737 Opcode = X86ISD::ADD;
12742 // If we have a constant logical shift that's only used in a comparison
12743 // against zero turn it into an equivalent AND. This allows turning it into
12744 // a TEST instruction later.
12745 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12746 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12747 EVT VT = Op.getValueType();
12748 unsigned BitWidth = VT.getSizeInBits();
12749 unsigned ShAmt = Op->getConstantOperandVal(1);
12750 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12752 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12753 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12754 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12755 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12757 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12758 DAG.getConstant(Mask, dl, VT));
12759 DAG.ReplaceAllUsesWith(Op, New);
12765 // If the primary and result isn't used, don't bother using X86ISD::AND,
12766 // because a TEST instruction will be better.
12767 if (!hasNonFlagsUse(Op))
12773 // Due to the ISEL shortcoming noted above, be conservative if this op is
12774 // likely to be selected as part of a load-modify-store instruction.
12775 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12776 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12777 if (UI->getOpcode() == ISD::STORE)
12780 // Otherwise use a regular EFLAGS-setting instruction.
12781 switch (ArithOp.getOpcode()) {
12782 default: llvm_unreachable("unexpected operator!");
12783 case ISD::SUB: Opcode = X86ISD::SUB; break;
12784 case ISD::XOR: Opcode = X86ISD::XOR; break;
12785 case ISD::AND: Opcode = X86ISD::AND; break;
12787 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
12788 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
12789 if (EFLAGS.getNode())
12792 Opcode = X86ISD::OR;
12806 return SDValue(Op.getNode(), 1);
12812 // If we found that truncation is beneficial, perform the truncation and
12814 if (NeedTruncation) {
12815 EVT VT = Op.getValueType();
12816 SDValue WideVal = Op->getOperand(0);
12817 EVT WideVT = WideVal.getValueType();
12818 unsigned ConvertedOp = 0;
12819 // Use a target machine opcode to prevent further DAGCombine
12820 // optimizations that may separate the arithmetic operations
12821 // from the setcc node.
12822 switch (WideVal.getOpcode()) {
12824 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
12825 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
12826 case ISD::AND: ConvertedOp = X86ISD::AND; break;
12827 case ISD::OR: ConvertedOp = X86ISD::OR; break;
12828 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
12832 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12833 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
12834 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
12835 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
12836 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
12842 // Emit a CMP with 0, which is the TEST pattern.
12843 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12844 DAG.getConstant(0, dl, Op.getValueType()));
12846 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
12847 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
12849 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
12850 DAG.ReplaceAllUsesWith(Op, New);
12851 return SDValue(New.getNode(), 1);
12854 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
12856 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
12857 SDLoc dl, SelectionDAG &DAG) const {
12858 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
12859 if (C->getAPIntValue() == 0)
12860 return EmitTest(Op0, X86CC, dl, DAG);
12862 if (Op0.getValueType() == MVT::i1)
12863 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
12866 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
12867 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
12868 // Do the comparison at i32 if it's smaller, besides the Atom case.
12869 // This avoids subregister aliasing issues. Keep the smaller reference
12870 // if we're optimizing for size, however, as that'll allow better folding
12871 // of memory operations.
12872 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
12873 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
12874 Attribute::MinSize) &&
12875 !Subtarget->isAtom()) {
12876 unsigned ExtendOp =
12877 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
12878 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
12879 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
12881 // Use SUB instead of CMP to enable CSE between SUB and CMP.
12882 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
12883 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
12885 return SDValue(Sub.getNode(), 1);
12887 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
12890 /// Convert a comparison if required by the subtarget.
12891 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
12892 SelectionDAG &DAG) const {
12893 // If the subtarget does not support the FUCOMI instruction, floating-point
12894 // comparisons have to be converted.
12895 if (Subtarget->hasCMov() ||
12896 Cmp.getOpcode() != X86ISD::CMP ||
12897 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
12898 !Cmp.getOperand(1).getValueType().isFloatingPoint())
12901 // The instruction selector will select an FUCOM instruction instead of
12902 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
12903 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
12904 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
12906 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
12907 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
12908 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
12909 DAG.getConstant(8, dl, MVT::i8));
12910 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
12911 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
12914 /// The minimum architected relative accuracy is 2^-12. We need one
12915 /// Newton-Raphson step to have a good float result (24 bits of precision).
12916 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
12917 DAGCombinerInfo &DCI,
12918 unsigned &RefinementSteps,
12919 bool &UseOneConstNR) const {
12920 EVT VT = Op.getValueType();
12921 const char *RecipOp;
12923 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
12924 // TODO: Add support for AVX512 (v16f32).
12925 // It is likely not profitable to do this for f64 because a double-precision
12926 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
12927 // instructions: convert to single, rsqrtss, convert back to double, refine
12928 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
12929 // along with FMA, this could be a throughput win.
12930 if (VT == MVT::f32 && Subtarget->hasSSE1())
12932 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
12933 (VT == MVT::v8f32 && Subtarget->hasAVX()))
12934 RecipOp = "vec-sqrtf";
12938 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
12939 if (!Recips.isEnabled(RecipOp))
12942 RefinementSteps = Recips.getRefinementSteps(RecipOp);
12943 UseOneConstNR = false;
12944 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
12947 /// The minimum architected relative accuracy is 2^-12. We need one
12948 /// Newton-Raphson step to have a good float result (24 bits of precision).
12949 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
12950 DAGCombinerInfo &DCI,
12951 unsigned &RefinementSteps) const {
12952 EVT VT = Op.getValueType();
12953 const char *RecipOp;
12955 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
12956 // TODO: Add support for AVX512 (v16f32).
12957 // It is likely not profitable to do this for f64 because a double-precision
12958 // reciprocal estimate with refinement on x86 prior to FMA requires
12959 // 15 instructions: convert to single, rcpss, convert back to double, refine
12960 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
12961 // along with FMA, this could be a throughput win.
12962 if (VT == MVT::f32 && Subtarget->hasSSE1())
12964 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
12965 (VT == MVT::v8f32 && Subtarget->hasAVX()))
12966 RecipOp = "vec-divf";
12970 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
12971 if (!Recips.isEnabled(RecipOp))
12974 RefinementSteps = Recips.getRefinementSteps(RecipOp);
12975 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
12978 /// If we have at least two divisions that use the same divisor, convert to
12979 /// multplication by a reciprocal. This may need to be adjusted for a given
12980 /// CPU if a division's cost is not at least twice the cost of a multiplication.
12981 /// This is because we still need one division to calculate the reciprocal and
12982 /// then we need two multiplies by that reciprocal as replacements for the
12983 /// original divisions.
12984 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
12985 return NumUsers > 1;
12988 static bool isAllOnes(SDValue V) {
12989 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
12990 return C && C->isAllOnesValue();
12993 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
12994 /// if it's possible.
12995 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
12996 SDLoc dl, SelectionDAG &DAG) const {
12997 SDValue Op0 = And.getOperand(0);
12998 SDValue Op1 = And.getOperand(1);
12999 if (Op0.getOpcode() == ISD::TRUNCATE)
13000 Op0 = Op0.getOperand(0);
13001 if (Op1.getOpcode() == ISD::TRUNCATE)
13002 Op1 = Op1.getOperand(0);
13005 if (Op1.getOpcode() == ISD::SHL)
13006 std::swap(Op0, Op1);
13007 if (Op0.getOpcode() == ISD::SHL) {
13008 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13009 if (And00C->getZExtValue() == 1) {
13010 // If we looked past a truncate, check that it's only truncating away
13012 unsigned BitWidth = Op0.getValueSizeInBits();
13013 unsigned AndBitWidth = And.getValueSizeInBits();
13014 if (BitWidth > AndBitWidth) {
13016 DAG.computeKnownBits(Op0, Zeros, Ones);
13017 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13021 RHS = Op0.getOperand(1);
13023 } else if (Op1.getOpcode() == ISD::Constant) {
13024 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13025 uint64_t AndRHSVal = AndRHS->getZExtValue();
13026 SDValue AndLHS = Op0;
13028 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13029 LHS = AndLHS.getOperand(0);
13030 RHS = AndLHS.getOperand(1);
13033 // Use BT if the immediate can't be encoded in a TEST instruction.
13034 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13036 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13040 if (LHS.getNode()) {
13041 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13042 // instruction. Since the shift amount is in-range-or-undefined, we know
13043 // that doing a bittest on the i32 value is ok. We extend to i32 because
13044 // the encoding for the i16 version is larger than the i32 version.
13045 // Also promote i16 to i32 for performance / code size reason.
13046 if (LHS.getValueType() == MVT::i8 ||
13047 LHS.getValueType() == MVT::i16)
13048 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13050 // If the operand types disagree, extend the shift amount to match. Since
13051 // BT ignores high bits (like shifts) we can use anyextend.
13052 if (LHS.getValueType() != RHS.getValueType())
13053 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13055 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13056 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13057 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13058 DAG.getConstant(Cond, dl, MVT::i8), BT);
13064 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13066 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13071 // SSE Condition code mapping:
13080 switch (SetCCOpcode) {
13081 default: llvm_unreachable("Unexpected SETCC condition");
13083 case ISD::SETEQ: SSECC = 0; break;
13085 case ISD::SETGT: Swap = true; // Fallthrough
13087 case ISD::SETOLT: SSECC = 1; break;
13089 case ISD::SETGE: Swap = true; // Fallthrough
13091 case ISD::SETOLE: SSECC = 2; break;
13092 case ISD::SETUO: SSECC = 3; break;
13094 case ISD::SETNE: SSECC = 4; break;
13095 case ISD::SETULE: Swap = true; // Fallthrough
13096 case ISD::SETUGE: SSECC = 5; break;
13097 case ISD::SETULT: Swap = true; // Fallthrough
13098 case ISD::SETUGT: SSECC = 6; break;
13099 case ISD::SETO: SSECC = 7; break;
13101 case ISD::SETONE: SSECC = 8; break;
13104 std::swap(Op0, Op1);
13109 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13110 // ones, and then concatenate the result back.
13111 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13112 MVT VT = Op.getSimpleValueType();
13114 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13115 "Unsupported value type for operation");
13117 unsigned NumElems = VT.getVectorNumElements();
13119 SDValue CC = Op.getOperand(2);
13121 // Extract the LHS vectors
13122 SDValue LHS = Op.getOperand(0);
13123 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13124 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13126 // Extract the RHS vectors
13127 SDValue RHS = Op.getOperand(1);
13128 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13129 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13131 // Issue the operation on the smaller types and concatenate the result back
13132 MVT EltVT = VT.getVectorElementType();
13133 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13134 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13135 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13136 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13139 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13140 SDValue Op0 = Op.getOperand(0);
13141 SDValue Op1 = Op.getOperand(1);
13142 SDValue CC = Op.getOperand(2);
13143 MVT VT = Op.getSimpleValueType();
13146 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13147 "Unexpected type for boolean compare operation");
13148 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13149 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13150 DAG.getConstant(-1, dl, VT));
13151 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13152 DAG.getConstant(-1, dl, VT));
13153 switch (SetCCOpcode) {
13154 default: llvm_unreachable("Unexpected SETCC condition");
13156 // (x == y) -> ~(x ^ y)
13157 return DAG.getNode(ISD::XOR, dl, VT,
13158 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13159 DAG.getConstant(-1, dl, VT));
13161 // (x != y) -> (x ^ y)
13162 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13165 // (x > y) -> (x & ~y)
13166 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13169 // (x < y) -> (~x & y)
13170 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13173 // (x <= y) -> (~x | y)
13174 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13177 // (x >=y) -> (x | ~y)
13178 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13182 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13183 const X86Subtarget *Subtarget) {
13184 SDValue Op0 = Op.getOperand(0);
13185 SDValue Op1 = Op.getOperand(1);
13186 SDValue CC = Op.getOperand(2);
13187 MVT VT = Op.getSimpleValueType();
13190 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13191 Op.getValueType().getScalarType() == MVT::i1 &&
13192 "Cannot set masked compare for this operation");
13194 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13196 bool Unsigned = false;
13199 switch (SetCCOpcode) {
13200 default: llvm_unreachable("Unexpected SETCC condition");
13201 case ISD::SETNE: SSECC = 4; break;
13202 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13203 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13204 case ISD::SETLT: Swap = true; //fall-through
13205 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13206 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13207 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13208 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13209 case ISD::SETULE: Unsigned = true; //fall-through
13210 case ISD::SETLE: SSECC = 2; break;
13214 std::swap(Op0, Op1);
13216 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13217 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13218 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13219 DAG.getConstant(SSECC, dl, MVT::i8));
13222 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13223 /// operand \p Op1. If non-trivial (for example because it's not constant)
13224 /// return an empty value.
13225 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13227 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13231 MVT VT = Op1.getSimpleValueType();
13232 MVT EVT = VT.getVectorElementType();
13233 unsigned n = VT.getVectorNumElements();
13234 SmallVector<SDValue, 8> ULTOp1;
13236 for (unsigned i = 0; i < n; ++i) {
13237 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13238 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13241 // Avoid underflow.
13242 APInt Val = Elt->getAPIntValue();
13246 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13249 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13252 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13253 SelectionDAG &DAG) {
13254 SDValue Op0 = Op.getOperand(0);
13255 SDValue Op1 = Op.getOperand(1);
13256 SDValue CC = Op.getOperand(2);
13257 MVT VT = Op.getSimpleValueType();
13258 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13259 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13264 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13265 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13268 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13269 unsigned Opc = X86ISD::CMPP;
13270 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13271 assert(VT.getVectorNumElements() <= 16);
13272 Opc = X86ISD::CMPM;
13274 // In the two special cases we can't handle, emit two comparisons.
13277 unsigned CombineOpc;
13278 if (SetCCOpcode == ISD::SETUEQ) {
13279 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13281 assert(SetCCOpcode == ISD::SETONE);
13282 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13285 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13286 DAG.getConstant(CC0, dl, MVT::i8));
13287 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13288 DAG.getConstant(CC1, dl, MVT::i8));
13289 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13291 // Handle all other FP comparisons here.
13292 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13293 DAG.getConstant(SSECC, dl, MVT::i8));
13296 // Break 256-bit integer vector compare into smaller ones.
13297 if (VT.is256BitVector() && !Subtarget->hasInt256())
13298 return Lower256IntVSETCC(Op, DAG);
13300 EVT OpVT = Op1.getValueType();
13301 if (OpVT.getVectorElementType() == MVT::i1)
13302 return LowerBoolVSETCC_AVX512(Op, DAG);
13304 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13305 if (Subtarget->hasAVX512()) {
13306 if (Op1.getValueType().is512BitVector() ||
13307 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13308 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13309 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13311 // In AVX-512 architecture setcc returns mask with i1 elements,
13312 // But there is no compare instruction for i8 and i16 elements in KNL.
13313 // We are not talking about 512-bit operands in this case, these
13314 // types are illegal.
13316 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13317 OpVT.getVectorElementType().getSizeInBits() >= 8))
13318 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13319 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13322 // We are handling one of the integer comparisons here. Since SSE only has
13323 // GT and EQ comparisons for integer, swapping operands and multiple
13324 // operations may be required for some comparisons.
13326 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13327 bool Subus = false;
13329 switch (SetCCOpcode) {
13330 default: llvm_unreachable("Unexpected SETCC condition");
13331 case ISD::SETNE: Invert = true;
13332 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13333 case ISD::SETLT: Swap = true;
13334 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13335 case ISD::SETGE: Swap = true;
13336 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13337 Invert = true; break;
13338 case ISD::SETULT: Swap = true;
13339 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13340 FlipSigns = true; break;
13341 case ISD::SETUGE: Swap = true;
13342 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13343 FlipSigns = true; Invert = true; break;
13346 // Special case: Use min/max operations for SETULE/SETUGE
13347 MVT VET = VT.getVectorElementType();
13349 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13350 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13353 switch (SetCCOpcode) {
13355 case ISD::SETULE: Opc = X86ISD::UMIN; MinMax = true; break;
13356 case ISD::SETUGE: Opc = X86ISD::UMAX; MinMax = true; break;
13359 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13362 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13363 if (!MinMax && hasSubus) {
13364 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13366 // t = psubus Op0, Op1
13367 // pcmpeq t, <0..0>
13368 switch (SetCCOpcode) {
13370 case ISD::SETULT: {
13371 // If the comparison is against a constant we can turn this into a
13372 // setule. With psubus, setule does not require a swap. This is
13373 // beneficial because the constant in the register is no longer
13374 // destructed as the destination so it can be hoisted out of a loop.
13375 // Only do this pre-AVX since vpcmp* is no longer destructive.
13376 if (Subtarget->hasAVX())
13378 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13379 if (ULEOp1.getNode()) {
13381 Subus = true; Invert = false; Swap = false;
13385 // Psubus is better than flip-sign because it requires no inversion.
13386 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13387 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13391 Opc = X86ISD::SUBUS;
13397 std::swap(Op0, Op1);
13399 // Check that the operation in question is available (most are plain SSE2,
13400 // but PCMPGTQ and PCMPEQQ have different requirements).
13401 if (VT == MVT::v2i64) {
13402 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13403 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13405 // First cast everything to the right type.
13406 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13407 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13409 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13410 // bits of the inputs before performing those operations. The lower
13411 // compare is always unsigned.
13414 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13416 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13417 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13418 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13419 Sign, Zero, Sign, Zero);
13421 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13422 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13424 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13425 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13426 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13428 // Create masks for only the low parts/high parts of the 64 bit integers.
13429 static const int MaskHi[] = { 1, 1, 3, 3 };
13430 static const int MaskLo[] = { 0, 0, 2, 2 };
13431 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13432 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13433 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13435 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13436 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13439 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13441 return DAG.getBitcast(VT, Result);
13444 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13445 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13446 // pcmpeqd + pshufd + pand.
13447 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13449 // First cast everything to the right type.
13450 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13451 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13454 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13456 // Make sure the lower and upper halves are both all-ones.
13457 static const int Mask[] = { 1, 0, 3, 2 };
13458 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13459 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13462 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13464 return DAG.getBitcast(VT, Result);
13468 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13469 // bits of the inputs before performing those operations.
13471 EVT EltVT = VT.getVectorElementType();
13472 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13474 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13475 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13478 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13480 // If the logical-not of the result is required, perform that now.
13482 Result = DAG.getNOT(dl, Result, VT);
13485 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13488 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13489 getZeroVector(VT, Subtarget, DAG, dl));
13494 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13496 MVT VT = Op.getSimpleValueType();
13498 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13500 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13501 && "SetCC type must be 8-bit or 1-bit integer");
13502 SDValue Op0 = Op.getOperand(0);
13503 SDValue Op1 = Op.getOperand(1);
13505 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13507 // Optimize to BT if possible.
13508 // Lower (X & (1 << N)) == 0 to BT(X, N).
13509 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13510 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13511 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13512 Op1.getOpcode() == ISD::Constant &&
13513 cast<ConstantSDNode>(Op1)->isNullValue() &&
13514 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13515 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13516 if (NewSetCC.getNode()) {
13518 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13523 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13525 if (Op1.getOpcode() == ISD::Constant &&
13526 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13527 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13528 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13530 // If the input is a setcc, then reuse the input setcc or use a new one with
13531 // the inverted condition.
13532 if (Op0.getOpcode() == X86ISD::SETCC) {
13533 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13534 bool Invert = (CC == ISD::SETNE) ^
13535 cast<ConstantSDNode>(Op1)->isNullValue();
13539 CCode = X86::GetOppositeBranchCondition(CCode);
13540 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13541 DAG.getConstant(CCode, dl, MVT::i8),
13542 Op0.getOperand(1));
13544 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13548 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13549 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13550 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13552 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13553 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13556 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13557 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13558 if (X86CC == X86::COND_INVALID)
13561 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13562 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13563 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13564 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13566 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13570 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13571 static bool isX86LogicalCmp(SDValue Op) {
13572 unsigned Opc = Op.getNode()->getOpcode();
13573 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13574 Opc == X86ISD::SAHF)
13576 if (Op.getResNo() == 1 &&
13577 (Opc == X86ISD::ADD ||
13578 Opc == X86ISD::SUB ||
13579 Opc == X86ISD::ADC ||
13580 Opc == X86ISD::SBB ||
13581 Opc == X86ISD::SMUL ||
13582 Opc == X86ISD::UMUL ||
13583 Opc == X86ISD::INC ||
13584 Opc == X86ISD::DEC ||
13585 Opc == X86ISD::OR ||
13586 Opc == X86ISD::XOR ||
13587 Opc == X86ISD::AND))
13590 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13596 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13597 if (V.getOpcode() != ISD::TRUNCATE)
13600 SDValue VOp0 = V.getOperand(0);
13601 unsigned InBits = VOp0.getValueSizeInBits();
13602 unsigned Bits = V.getValueSizeInBits();
13603 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13606 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13607 bool addTest = true;
13608 SDValue Cond = Op.getOperand(0);
13609 SDValue Op1 = Op.getOperand(1);
13610 SDValue Op2 = Op.getOperand(2);
13612 EVT VT = Op1.getValueType();
13615 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13616 // are available or VBLENDV if AVX is available.
13617 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13618 if (Cond.getOpcode() == ISD::SETCC &&
13619 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13620 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13621 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13622 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13623 int SSECC = translateX86FSETCC(
13624 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13627 if (Subtarget->hasAVX512()) {
13628 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13629 DAG.getConstant(SSECC, DL, MVT::i8));
13630 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13633 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13634 DAG.getConstant(SSECC, DL, MVT::i8));
13636 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13637 // of 3 logic instructions for size savings and potentially speed.
13638 // Unfortunately, there is no scalar form of VBLENDV.
13640 // If either operand is a constant, don't try this. We can expect to
13641 // optimize away at least one of the logic instructions later in that
13642 // case, so that sequence would be faster than a variable blend.
13644 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13645 // uses XMM0 as the selection register. That may need just as many
13646 // instructions as the AND/ANDN/OR sequence due to register moves, so
13649 if (Subtarget->hasAVX() &&
13650 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13652 // Convert to vectors, do a VSELECT, and convert back to scalar.
13653 // All of the conversions should be optimized away.
13655 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13656 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13657 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13658 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13660 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13661 VCmp = DAG.getBitcast(VCmpVT, VCmp);
13663 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13665 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13666 VSel, DAG.getIntPtrConstant(0, DL));
13668 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13669 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13670 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13674 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13676 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13677 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13678 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13679 Op1Scalar = Op1.getOperand(0);
13681 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13682 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13683 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13684 Op2Scalar = Op2.getOperand(0);
13685 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13686 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13687 Op1Scalar.getValueType(),
13688 Cond, Op1Scalar, Op2Scalar);
13689 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13690 return DAG.getBitcast(VT, newSelect);
13691 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
13692 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13693 DAG.getIntPtrConstant(0, DL));
13697 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13698 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13699 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13700 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13701 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13702 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13703 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13705 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13708 if (Cond.getOpcode() == ISD::SETCC) {
13709 SDValue NewCond = LowerSETCC(Cond, DAG);
13710 if (NewCond.getNode())
13714 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13715 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13716 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13717 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13718 if (Cond.getOpcode() == X86ISD::SETCC &&
13719 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13720 isZero(Cond.getOperand(1).getOperand(1))) {
13721 SDValue Cmp = Cond.getOperand(1);
13723 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13725 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13726 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13727 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13729 SDValue CmpOp0 = Cmp.getOperand(0);
13730 // Apply further optimizations for special cases
13731 // (select (x != 0), -1, 0) -> neg & sbb
13732 // (select (x == 0), 0, -1) -> neg & sbb
13733 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13734 if (YC->isNullValue() &&
13735 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13736 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13737 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13738 DAG.getConstant(0, DL,
13739 CmpOp0.getValueType()),
13741 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13742 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13743 SDValue(Neg.getNode(), 1));
13747 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13748 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13749 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13751 SDValue Res = // Res = 0 or -1.
13752 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13753 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13755 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13756 Res = DAG.getNOT(DL, Res, Res.getValueType());
13758 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13759 if (!N2C || !N2C->isNullValue())
13760 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
13765 // Look past (and (setcc_carry (cmp ...)), 1).
13766 if (Cond.getOpcode() == ISD::AND &&
13767 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
13768 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
13769 if (C && C->getAPIntValue() == 1)
13770 Cond = Cond.getOperand(0);
13773 // If condition flag is set by a X86ISD::CMP, then use it as the condition
13774 // setting operand in place of the X86ISD::SETCC.
13775 unsigned CondOpcode = Cond.getOpcode();
13776 if (CondOpcode == X86ISD::SETCC ||
13777 CondOpcode == X86ISD::SETCC_CARRY) {
13778 CC = Cond.getOperand(0);
13780 SDValue Cmp = Cond.getOperand(1);
13781 unsigned Opc = Cmp.getOpcode();
13782 MVT VT = Op.getSimpleValueType();
13784 bool IllegalFPCMov = false;
13785 if (VT.isFloatingPoint() && !VT.isVector() &&
13786 !isScalarFPTypeInSSEReg(VT)) // FPStack?
13787 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
13789 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
13790 Opc == X86ISD::BT) { // FIXME
13794 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
13795 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
13796 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
13797 Cond.getOperand(0).getValueType() != MVT::i8)) {
13798 SDValue LHS = Cond.getOperand(0);
13799 SDValue RHS = Cond.getOperand(1);
13800 unsigned X86Opcode;
13803 switch (CondOpcode) {
13804 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
13805 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
13806 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
13807 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
13808 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
13809 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
13810 default: llvm_unreachable("unexpected overflowing operator");
13812 if (CondOpcode == ISD::UMULO)
13813 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
13816 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
13818 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
13820 if (CondOpcode == ISD::UMULO)
13821 Cond = X86Op.getValue(2);
13823 Cond = X86Op.getValue(1);
13825 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
13830 // Look pass the truncate if the high bits are known zero.
13831 if (isTruncWithZeroHighBitsInput(Cond, DAG))
13832 Cond = Cond.getOperand(0);
13834 // We know the result of AND is compared against zero. Try to match
13836 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
13837 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
13838 if (NewSetCC.getNode()) {
13839 CC = NewSetCC.getOperand(0);
13840 Cond = NewSetCC.getOperand(1);
13847 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
13848 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
13851 // a < b ? -1 : 0 -> RES = ~setcc_carry
13852 // a < b ? 0 : -1 -> RES = setcc_carry
13853 // a >= b ? -1 : 0 -> RES = setcc_carry
13854 // a >= b ? 0 : -1 -> RES = ~setcc_carry
13855 if (Cond.getOpcode() == X86ISD::SUB) {
13856 Cond = ConvertCmpIfNecessary(Cond, DAG);
13857 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
13859 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
13860 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
13861 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13862 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13864 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
13865 return DAG.getNOT(DL, Res, Res.getValueType());
13870 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
13871 // widen the cmov and push the truncate through. This avoids introducing a new
13872 // branch during isel and doesn't add any extensions.
13873 if (Op.getValueType() == MVT::i8 &&
13874 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
13875 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
13876 if (T1.getValueType() == T2.getValueType() &&
13877 // Blacklist CopyFromReg to avoid partial register stalls.
13878 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
13879 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
13880 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
13881 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
13885 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
13886 // condition is true.
13887 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
13888 SDValue Ops[] = { Op2, Op1, CC, Cond };
13889 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
13892 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
13893 const X86Subtarget *Subtarget,
13894 SelectionDAG &DAG) {
13895 MVT VT = Op->getSimpleValueType(0);
13896 SDValue In = Op->getOperand(0);
13897 MVT InVT = In.getSimpleValueType();
13898 MVT VTElt = VT.getVectorElementType();
13899 MVT InVTElt = InVT.getVectorElementType();
13903 if ((InVTElt == MVT::i1) &&
13904 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
13905 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
13907 ((Subtarget->hasBWI() && VT.is512BitVector() &&
13908 VTElt.getSizeInBits() <= 16)) ||
13910 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
13911 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
13913 ((Subtarget->hasDQI() && VT.is512BitVector() &&
13914 VTElt.getSizeInBits() >= 32))))
13915 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13917 unsigned int NumElts = VT.getVectorNumElements();
13919 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
13922 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
13923 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
13924 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
13925 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13928 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
13929 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13931 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
13934 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
13936 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
13937 if (VT.is512BitVector())
13939 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
13942 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
13943 const X86Subtarget *Subtarget,
13944 SelectionDAG &DAG) {
13945 SDValue In = Op->getOperand(0);
13946 MVT VT = Op->getSimpleValueType(0);
13947 MVT InVT = In.getSimpleValueType();
13948 assert(VT.getSizeInBits() == InVT.getSizeInBits());
13950 MVT InSVT = InVT.getScalarType();
13951 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
13953 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
13955 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
13960 // SSE41 targets can use the pmovsx* instructions directly.
13961 if (Subtarget->hasSSE41())
13962 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
13964 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
13968 // As SRAI is only available on i16/i32 types, we expand only up to i32
13969 // and handle i64 separately.
13970 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
13971 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
13972 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
13973 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
13974 Curr = DAG.getBitcast(CurrVT, Curr);
13977 SDValue SignExt = Curr;
13978 if (CurrVT != InVT) {
13979 unsigned SignExtShift =
13980 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
13981 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
13982 DAG.getConstant(SignExtShift, dl, MVT::i8));
13988 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
13989 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
13990 DAG.getConstant(31, dl, MVT::i8));
13991 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
13992 return DAG.getBitcast(VT, Ext);
13998 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
13999 SelectionDAG &DAG) {
14000 MVT VT = Op->getSimpleValueType(0);
14001 SDValue In = Op->getOperand(0);
14002 MVT InVT = In.getSimpleValueType();
14005 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14006 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14008 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14009 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14010 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14013 if (Subtarget->hasInt256())
14014 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14016 // Optimize vectors in AVX mode
14017 // Sign extend v8i16 to v8i32 and
14020 // Divide input vector into two parts
14021 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14022 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14023 // concat the vectors to original VT
14025 unsigned NumElems = InVT.getVectorNumElements();
14026 SDValue Undef = DAG.getUNDEF(InVT);
14028 SmallVector<int,8> ShufMask1(NumElems, -1);
14029 for (unsigned i = 0; i != NumElems/2; ++i)
14032 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14034 SmallVector<int,8> ShufMask2(NumElems, -1);
14035 for (unsigned i = 0; i != NumElems/2; ++i)
14036 ShufMask2[i] = i + NumElems/2;
14038 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14040 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14041 VT.getVectorNumElements()/2);
14043 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14044 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14046 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14049 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14050 // may emit an illegal shuffle but the expansion is still better than scalar
14051 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14052 // we'll emit a shuffle and a arithmetic shift.
14053 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14054 // TODO: It is possible to support ZExt by zeroing the undef values during
14055 // the shuffle phase or after the shuffle.
14056 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14057 SelectionDAG &DAG) {
14058 MVT RegVT = Op.getSimpleValueType();
14059 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14060 assert(RegVT.isInteger() &&
14061 "We only custom lower integer vector sext loads.");
14063 // Nothing useful we can do without SSE2 shuffles.
14064 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14066 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14068 EVT MemVT = Ld->getMemoryVT();
14069 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14070 unsigned RegSz = RegVT.getSizeInBits();
14072 ISD::LoadExtType Ext = Ld->getExtensionType();
14074 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14075 && "Only anyext and sext are currently implemented.");
14076 assert(MemVT != RegVT && "Cannot extend to the same type");
14077 assert(MemVT.isVector() && "Must load a vector from memory");
14079 unsigned NumElems = RegVT.getVectorNumElements();
14080 unsigned MemSz = MemVT.getSizeInBits();
14081 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14083 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14084 // The only way in which we have a legal 256-bit vector result but not the
14085 // integer 256-bit operations needed to directly lower a sextload is if we
14086 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14087 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14088 // correctly legalized. We do this late to allow the canonical form of
14089 // sextload to persist throughout the rest of the DAG combiner -- it wants
14090 // to fold together any extensions it can, and so will fuse a sign_extend
14091 // of an sextload into a sextload targeting a wider value.
14093 if (MemSz == 128) {
14094 // Just switch this to a normal load.
14095 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14096 "it must be a legal 128-bit vector "
14098 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14099 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14100 Ld->isInvariant(), Ld->getAlignment());
14102 assert(MemSz < 128 &&
14103 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14104 // Do an sext load to a 128-bit vector type. We want to use the same
14105 // number of elements, but elements half as wide. This will end up being
14106 // recursively lowered by this routine, but will succeed as we definitely
14107 // have all the necessary features if we're using AVX1.
14109 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14110 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14112 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14113 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14114 Ld->isNonTemporal(), Ld->isInvariant(),
14115 Ld->getAlignment());
14118 // Replace chain users with the new chain.
14119 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14120 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14122 // Finally, do a normal sign-extend to the desired register.
14123 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14126 // All sizes must be a power of two.
14127 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14128 "Non-power-of-two elements are not custom lowered!");
14130 // Attempt to load the original value using scalar loads.
14131 // Find the largest scalar type that divides the total loaded size.
14132 MVT SclrLoadTy = MVT::i8;
14133 for (MVT Tp : MVT::integer_valuetypes()) {
14134 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14139 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14140 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14142 SclrLoadTy = MVT::f64;
14144 // Calculate the number of scalar loads that we need to perform
14145 // in order to load our vector from memory.
14146 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14148 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14149 "Can only lower sext loads with a single scalar load!");
14151 unsigned loadRegZize = RegSz;
14152 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14155 // Represent our vector as a sequence of elements which are the
14156 // largest scalar that we can load.
14157 EVT LoadUnitVecVT = EVT::getVectorVT(
14158 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14160 // Represent the data using the same element type that is stored in
14161 // memory. In practice, we ''widen'' MemVT.
14163 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14164 loadRegZize / MemVT.getScalarType().getSizeInBits());
14166 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14167 "Invalid vector type");
14169 // We can't shuffle using an illegal type.
14170 assert(TLI.isTypeLegal(WideVecVT) &&
14171 "We only lower types that form legal widened vector types");
14173 SmallVector<SDValue, 8> Chains;
14174 SDValue Ptr = Ld->getBasePtr();
14175 SDValue Increment =
14176 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14177 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14179 for (unsigned i = 0; i < NumLoads; ++i) {
14180 // Perform a single load.
14181 SDValue ScalarLoad =
14182 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14183 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14184 Ld->getAlignment());
14185 Chains.push_back(ScalarLoad.getValue(1));
14186 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14187 // another round of DAGCombining.
14189 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14191 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14192 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14194 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14197 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14199 // Bitcast the loaded value to a vector of the original element type, in
14200 // the size of the target vector type.
14201 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14202 unsigned SizeRatio = RegSz / MemSz;
14204 if (Ext == ISD::SEXTLOAD) {
14205 // If we have SSE4.1, we can directly emit a VSEXT node.
14206 if (Subtarget->hasSSE41()) {
14207 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14208 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14212 // Otherwise we'll shuffle the small elements in the high bits of the
14213 // larger type and perform an arithmetic shift. If the shift is not legal
14214 // it's better to scalarize.
14215 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14216 "We can't implement a sext load without an arithmetic right shift!");
14218 // Redistribute the loaded elements into the different locations.
14219 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14220 for (unsigned i = 0; i != NumElems; ++i)
14221 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14223 SDValue Shuff = DAG.getVectorShuffle(
14224 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14226 Shuff = DAG.getBitcast(RegVT, Shuff);
14228 // Build the arithmetic shift.
14229 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14230 MemVT.getVectorElementType().getSizeInBits();
14232 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14233 DAG.getConstant(Amt, dl, RegVT));
14235 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14239 // Redistribute the loaded elements into the different locations.
14240 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14241 for (unsigned i = 0; i != NumElems; ++i)
14242 ShuffleVec[i * SizeRatio] = i;
14244 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14245 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14247 // Bitcast to the requested type.
14248 Shuff = DAG.getBitcast(RegVT, Shuff);
14249 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14253 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14254 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14255 // from the AND / OR.
14256 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14257 Opc = Op.getOpcode();
14258 if (Opc != ISD::OR && Opc != ISD::AND)
14260 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14261 Op.getOperand(0).hasOneUse() &&
14262 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14263 Op.getOperand(1).hasOneUse());
14266 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14267 // 1 and that the SETCC node has a single use.
14268 static bool isXor1OfSetCC(SDValue Op) {
14269 if (Op.getOpcode() != ISD::XOR)
14271 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14272 if (N1C && N1C->getAPIntValue() == 1) {
14273 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14274 Op.getOperand(0).hasOneUse();
14279 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14280 bool addTest = true;
14281 SDValue Chain = Op.getOperand(0);
14282 SDValue Cond = Op.getOperand(1);
14283 SDValue Dest = Op.getOperand(2);
14286 bool Inverted = false;
14288 if (Cond.getOpcode() == ISD::SETCC) {
14289 // Check for setcc([su]{add,sub,mul}o == 0).
14290 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14291 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14292 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14293 Cond.getOperand(0).getResNo() == 1 &&
14294 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14295 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14296 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14297 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14298 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14299 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14301 Cond = Cond.getOperand(0);
14303 SDValue NewCond = LowerSETCC(Cond, DAG);
14304 if (NewCond.getNode())
14309 // FIXME: LowerXALUO doesn't handle these!!
14310 else if (Cond.getOpcode() == X86ISD::ADD ||
14311 Cond.getOpcode() == X86ISD::SUB ||
14312 Cond.getOpcode() == X86ISD::SMUL ||
14313 Cond.getOpcode() == X86ISD::UMUL)
14314 Cond = LowerXALUO(Cond, DAG);
14317 // Look pass (and (setcc_carry (cmp ...)), 1).
14318 if (Cond.getOpcode() == ISD::AND &&
14319 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14320 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14321 if (C && C->getAPIntValue() == 1)
14322 Cond = Cond.getOperand(0);
14325 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14326 // setting operand in place of the X86ISD::SETCC.
14327 unsigned CondOpcode = Cond.getOpcode();
14328 if (CondOpcode == X86ISD::SETCC ||
14329 CondOpcode == X86ISD::SETCC_CARRY) {
14330 CC = Cond.getOperand(0);
14332 SDValue Cmp = Cond.getOperand(1);
14333 unsigned Opc = Cmp.getOpcode();
14334 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14335 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14339 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14343 // These can only come from an arithmetic instruction with overflow,
14344 // e.g. SADDO, UADDO.
14345 Cond = Cond.getNode()->getOperand(1);
14351 CondOpcode = Cond.getOpcode();
14352 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14353 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14354 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14355 Cond.getOperand(0).getValueType() != MVT::i8)) {
14356 SDValue LHS = Cond.getOperand(0);
14357 SDValue RHS = Cond.getOperand(1);
14358 unsigned X86Opcode;
14361 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14362 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14364 switch (CondOpcode) {
14365 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14367 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14369 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14372 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14373 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14375 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14377 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14380 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14381 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14382 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14383 default: llvm_unreachable("unexpected overflowing operator");
14386 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14387 if (CondOpcode == ISD::UMULO)
14388 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14391 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14393 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14395 if (CondOpcode == ISD::UMULO)
14396 Cond = X86Op.getValue(2);
14398 Cond = X86Op.getValue(1);
14400 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14404 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14405 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14406 if (CondOpc == ISD::OR) {
14407 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14408 // two branches instead of an explicit OR instruction with a
14410 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14411 isX86LogicalCmp(Cmp)) {
14412 CC = Cond.getOperand(0).getOperand(0);
14413 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14414 Chain, Dest, CC, Cmp);
14415 CC = Cond.getOperand(1).getOperand(0);
14419 } else { // ISD::AND
14420 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14421 // two branches instead of an explicit AND instruction with a
14422 // separate test. However, we only do this if this block doesn't
14423 // have a fall-through edge, because this requires an explicit
14424 // jmp when the condition is false.
14425 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14426 isX86LogicalCmp(Cmp) &&
14427 Op.getNode()->hasOneUse()) {
14428 X86::CondCode CCode =
14429 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14430 CCode = X86::GetOppositeBranchCondition(CCode);
14431 CC = DAG.getConstant(CCode, dl, MVT::i8);
14432 SDNode *User = *Op.getNode()->use_begin();
14433 // Look for an unconditional branch following this conditional branch.
14434 // We need this because we need to reverse the successors in order
14435 // to implement FCMP_OEQ.
14436 if (User->getOpcode() == ISD::BR) {
14437 SDValue FalseBB = User->getOperand(1);
14439 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14440 assert(NewBR == User);
14444 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14445 Chain, Dest, CC, Cmp);
14446 X86::CondCode CCode =
14447 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14448 CCode = X86::GetOppositeBranchCondition(CCode);
14449 CC = DAG.getConstant(CCode, dl, MVT::i8);
14455 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14456 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14457 // It should be transformed during dag combiner except when the condition
14458 // is set by a arithmetics with overflow node.
14459 X86::CondCode CCode =
14460 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14461 CCode = X86::GetOppositeBranchCondition(CCode);
14462 CC = DAG.getConstant(CCode, dl, MVT::i8);
14463 Cond = Cond.getOperand(0).getOperand(1);
14465 } else if (Cond.getOpcode() == ISD::SETCC &&
14466 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14467 // For FCMP_OEQ, we can emit
14468 // two branches instead of an explicit AND instruction with a
14469 // separate test. However, we only do this if this block doesn't
14470 // have a fall-through edge, because this requires an explicit
14471 // jmp when the condition is false.
14472 if (Op.getNode()->hasOneUse()) {
14473 SDNode *User = *Op.getNode()->use_begin();
14474 // Look for an unconditional branch following this conditional branch.
14475 // We need this because we need to reverse the successors in order
14476 // to implement FCMP_OEQ.
14477 if (User->getOpcode() == ISD::BR) {
14478 SDValue FalseBB = User->getOperand(1);
14480 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14481 assert(NewBR == User);
14485 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14486 Cond.getOperand(0), Cond.getOperand(1));
14487 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14488 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14489 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14490 Chain, Dest, CC, Cmp);
14491 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14496 } else if (Cond.getOpcode() == ISD::SETCC &&
14497 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14498 // For FCMP_UNE, we can emit
14499 // two branches instead of an explicit AND instruction with a
14500 // separate test. However, we only do this if this block doesn't
14501 // have a fall-through edge, because this requires an explicit
14502 // jmp when the condition is false.
14503 if (Op.getNode()->hasOneUse()) {
14504 SDNode *User = *Op.getNode()->use_begin();
14505 // Look for an unconditional branch following this conditional branch.
14506 // We need this because we need to reverse the successors in order
14507 // to implement FCMP_UNE.
14508 if (User->getOpcode() == ISD::BR) {
14509 SDValue FalseBB = User->getOperand(1);
14511 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14512 assert(NewBR == User);
14515 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14516 Cond.getOperand(0), Cond.getOperand(1));
14517 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14518 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14519 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14520 Chain, Dest, CC, Cmp);
14521 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14531 // Look pass the truncate if the high bits are known zero.
14532 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14533 Cond = Cond.getOperand(0);
14535 // We know the result of AND is compared against zero. Try to match
14537 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14538 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14539 if (NewSetCC.getNode()) {
14540 CC = NewSetCC.getOperand(0);
14541 Cond = NewSetCC.getOperand(1);
14548 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14549 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14550 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14552 Cond = ConvertCmpIfNecessary(Cond, DAG);
14553 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14554 Chain, Dest, CC, Cond);
14557 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14558 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14559 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14560 // that the guard pages used by the OS virtual memory manager are allocated in
14561 // correct sequence.
14563 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14564 SelectionDAG &DAG) const {
14565 MachineFunction &MF = DAG.getMachineFunction();
14566 bool SplitStack = MF.shouldSplitStack();
14567 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14572 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14573 SDNode* Node = Op.getNode();
14575 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14576 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14577 " not tell us which reg is the stack pointer!");
14578 EVT VT = Node->getValueType(0);
14579 SDValue Tmp1 = SDValue(Node, 0);
14580 SDValue Tmp2 = SDValue(Node, 1);
14581 SDValue Tmp3 = Node->getOperand(2);
14582 SDValue Chain = Tmp1.getOperand(0);
14584 // Chain the dynamic stack allocation so that it doesn't modify the stack
14585 // pointer when other instructions are using the stack.
14586 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14589 SDValue Size = Tmp2.getOperand(1);
14590 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14591 Chain = SP.getValue(1);
14592 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14593 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14594 unsigned StackAlign = TFI.getStackAlignment();
14595 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14596 if (Align > StackAlign)
14597 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14598 DAG.getConstant(-(uint64_t)Align, dl, VT));
14599 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14601 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14602 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14605 SDValue Ops[2] = { Tmp1, Tmp2 };
14606 return DAG.getMergeValues(Ops, dl);
14610 SDValue Chain = Op.getOperand(0);
14611 SDValue Size = Op.getOperand(1);
14612 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14613 EVT VT = Op.getNode()->getValueType(0);
14615 bool Is64Bit = Subtarget->is64Bit();
14616 EVT SPTy = getPointerTy();
14619 MachineRegisterInfo &MRI = MF.getRegInfo();
14622 // The 64 bit implementation of segmented stacks needs to clobber both r10
14623 // r11. This makes it impossible to use it along with nested parameters.
14624 const Function *F = MF.getFunction();
14626 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14628 if (I->hasNestAttr())
14629 report_fatal_error("Cannot use segmented stacks with functions that "
14630 "have nested arguments.");
14633 const TargetRegisterClass *AddrRegClass =
14634 getRegClassFor(getPointerTy());
14635 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14636 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14637 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14638 DAG.getRegister(Vreg, SPTy));
14639 SDValue Ops1[2] = { Value, Chain };
14640 return DAG.getMergeValues(Ops1, dl);
14643 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14645 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14646 Flag = Chain.getValue(1);
14647 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14649 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14651 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14652 unsigned SPReg = RegInfo->getStackRegister();
14653 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14654 Chain = SP.getValue(1);
14657 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14658 DAG.getConstant(-(uint64_t)Align, dl, VT));
14659 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14662 SDValue Ops1[2] = { SP, Chain };
14663 return DAG.getMergeValues(Ops1, dl);
14667 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14668 MachineFunction &MF = DAG.getMachineFunction();
14669 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14671 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14674 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14675 // vastart just stores the address of the VarArgsFrameIndex slot into the
14676 // memory location argument.
14677 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14679 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14680 MachinePointerInfo(SV), false, false, 0);
14684 // gp_offset (0 - 6 * 8)
14685 // fp_offset (48 - 48 + 8 * 16)
14686 // overflow_arg_area (point to parameters coming in memory).
14688 SmallVector<SDValue, 8> MemOps;
14689 SDValue FIN = Op.getOperand(1);
14691 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14692 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14694 FIN, MachinePointerInfo(SV), false, false, 0);
14695 MemOps.push_back(Store);
14698 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14699 FIN, DAG.getIntPtrConstant(4, DL));
14700 Store = DAG.getStore(Op.getOperand(0), DL,
14701 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14703 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14704 MemOps.push_back(Store);
14706 // Store ptr to overflow_arg_area
14707 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14708 FIN, DAG.getIntPtrConstant(4, DL));
14709 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14711 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14712 MachinePointerInfo(SV, 8),
14714 MemOps.push_back(Store);
14716 // Store ptr to reg_save_area.
14717 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14718 FIN, DAG.getIntPtrConstant(8, DL));
14719 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14721 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14722 MachinePointerInfo(SV, 16), false, false, 0);
14723 MemOps.push_back(Store);
14724 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14727 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14728 assert(Subtarget->is64Bit() &&
14729 "LowerVAARG only handles 64-bit va_arg!");
14730 assert((Subtarget->isTargetLinux() ||
14731 Subtarget->isTargetDarwin()) &&
14732 "Unhandled target in LowerVAARG");
14733 assert(Op.getNode()->getNumOperands() == 4);
14734 SDValue Chain = Op.getOperand(0);
14735 SDValue SrcPtr = Op.getOperand(1);
14736 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14737 unsigned Align = Op.getConstantOperandVal(3);
14740 EVT ArgVT = Op.getNode()->getValueType(0);
14741 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14742 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14745 // Decide which area this value should be read from.
14746 // TODO: Implement the AMD64 ABI in its entirety. This simple
14747 // selection mechanism works only for the basic types.
14748 if (ArgVT == MVT::f80) {
14749 llvm_unreachable("va_arg for f80 not yet implemented");
14750 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14751 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14752 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14753 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14755 llvm_unreachable("Unhandled argument type in LowerVAARG");
14758 if (ArgMode == 2) {
14759 // Sanity Check: Make sure using fp_offset makes sense.
14760 assert(!Subtarget->useSoftFloat() &&
14761 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14762 Attribute::NoImplicitFloat)) &&
14763 Subtarget->hasSSE1());
14766 // Insert VAARG_64 node into the DAG
14767 // VAARG_64 returns two values: Variable Argument Address, Chain
14768 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
14769 DAG.getConstant(ArgMode, dl, MVT::i8),
14770 DAG.getConstant(Align, dl, MVT::i32)};
14771 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
14772 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
14773 VTs, InstOps, MVT::i64,
14774 MachinePointerInfo(SV),
14776 /*Volatile=*/false,
14778 /*WriteMem=*/true);
14779 Chain = VAARG.getValue(1);
14781 // Load the next argument and return it
14782 return DAG.getLoad(ArgVT, dl,
14785 MachinePointerInfo(),
14786 false, false, false, 0);
14789 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
14790 SelectionDAG &DAG) {
14791 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
14792 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
14793 SDValue Chain = Op.getOperand(0);
14794 SDValue DstPtr = Op.getOperand(1);
14795 SDValue SrcPtr = Op.getOperand(2);
14796 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
14797 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
14800 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
14801 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
14803 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
14806 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
14807 // amount is a constant. Takes immediate version of shift as input.
14808 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
14809 SDValue SrcOp, uint64_t ShiftAmt,
14810 SelectionDAG &DAG) {
14811 MVT ElementType = VT.getVectorElementType();
14813 // Fold this packed shift into its first operand if ShiftAmt is 0.
14817 // Check for ShiftAmt >= element width
14818 if (ShiftAmt >= ElementType.getSizeInBits()) {
14819 if (Opc == X86ISD::VSRAI)
14820 ShiftAmt = ElementType.getSizeInBits() - 1;
14822 return DAG.getConstant(0, dl, VT);
14825 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
14826 && "Unknown target vector shift-by-constant node");
14828 // Fold this packed vector shift into a build vector if SrcOp is a
14829 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
14830 if (VT == SrcOp.getSimpleValueType() &&
14831 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
14832 SmallVector<SDValue, 8> Elts;
14833 unsigned NumElts = SrcOp->getNumOperands();
14834 ConstantSDNode *ND;
14837 default: llvm_unreachable(nullptr);
14838 case X86ISD::VSHLI:
14839 for (unsigned i=0; i!=NumElts; ++i) {
14840 SDValue CurrentOp = SrcOp->getOperand(i);
14841 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14842 Elts.push_back(CurrentOp);
14845 ND = cast<ConstantSDNode>(CurrentOp);
14846 const APInt &C = ND->getAPIntValue();
14847 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
14850 case X86ISD::VSRLI:
14851 for (unsigned i=0; i!=NumElts; ++i) {
14852 SDValue CurrentOp = SrcOp->getOperand(i);
14853 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14854 Elts.push_back(CurrentOp);
14857 ND = cast<ConstantSDNode>(CurrentOp);
14858 const APInt &C = ND->getAPIntValue();
14859 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
14862 case X86ISD::VSRAI:
14863 for (unsigned i=0; i!=NumElts; ++i) {
14864 SDValue CurrentOp = SrcOp->getOperand(i);
14865 if (CurrentOp->getOpcode() == ISD::UNDEF) {
14866 Elts.push_back(CurrentOp);
14869 ND = cast<ConstantSDNode>(CurrentOp);
14870 const APInt &C = ND->getAPIntValue();
14871 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
14876 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
14879 return DAG.getNode(Opc, dl, VT, SrcOp,
14880 DAG.getConstant(ShiftAmt, dl, MVT::i8));
14883 // getTargetVShiftNode - Handle vector element shifts where the shift amount
14884 // may or may not be a constant. Takes immediate version of shift as input.
14885 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
14886 SDValue SrcOp, SDValue ShAmt,
14887 SelectionDAG &DAG) {
14888 MVT SVT = ShAmt.getSimpleValueType();
14889 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
14891 // Catch shift-by-constant.
14892 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
14893 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
14894 CShAmt->getZExtValue(), DAG);
14896 // Change opcode to non-immediate version
14898 default: llvm_unreachable("Unknown target vector shift node");
14899 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
14900 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
14901 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
14904 const X86Subtarget &Subtarget =
14905 static_cast<const X86Subtarget &>(DAG.getSubtarget());
14906 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
14907 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
14908 // Let the shuffle legalizer expand this shift amount node.
14909 SDValue Op0 = ShAmt.getOperand(0);
14910 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
14911 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
14913 // Need to build a vector containing shift amount.
14914 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
14915 SmallVector<SDValue, 4> ShOps;
14916 ShOps.push_back(ShAmt);
14917 if (SVT == MVT::i32) {
14918 ShOps.push_back(DAG.getConstant(0, dl, SVT));
14919 ShOps.push_back(DAG.getUNDEF(SVT));
14921 ShOps.push_back(DAG.getUNDEF(SVT));
14923 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
14924 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
14927 // The return type has to be a 128-bit type with the same element
14928 // type as the input type.
14929 MVT EltVT = VT.getVectorElementType();
14930 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
14932 ShAmt = DAG.getBitcast(ShVT, ShAmt);
14933 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
14936 /// \brief Return (and \p Op, \p Mask) for compare instructions or
14937 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
14938 /// necessary casting for \p Mask when lowering masking intrinsics.
14939 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
14940 SDValue PreservedSrc,
14941 const X86Subtarget *Subtarget,
14942 SelectionDAG &DAG) {
14943 EVT VT = Op.getValueType();
14944 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
14945 MVT::i1, VT.getVectorNumElements());
14946 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
14947 Mask.getValueType().getSizeInBits());
14950 assert(MaskVT.isSimple() && "invalid mask type");
14952 if (isAllOnes(Mask))
14955 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
14956 // are extracted by EXTRACT_SUBVECTOR.
14957 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
14958 DAG.getBitcast(BitcastVT, Mask),
14959 DAG.getIntPtrConstant(0, dl));
14961 switch (Op.getOpcode()) {
14963 case X86ISD::PCMPEQM:
14964 case X86ISD::PCMPGTM:
14966 case X86ISD::CMPMU:
14967 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
14969 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14970 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14971 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
14974 /// \brief Creates an SDNode for a predicated scalar operation.
14975 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
14976 /// The mask is comming as MVT::i8 and it should be truncated
14977 /// to MVT::i1 while lowering masking intrinsics.
14978 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
14979 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
14980 /// a scalar instruction.
14981 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
14982 SDValue PreservedSrc,
14983 const X86Subtarget *Subtarget,
14984 SelectionDAG &DAG) {
14985 if (isAllOnes(Mask))
14988 EVT VT = Op.getValueType();
14990 // The mask should be of type MVT::i1
14991 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
14993 if (PreservedSrc.getOpcode() == ISD::UNDEF)
14994 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
14995 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
14998 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
14999 SelectionDAG &DAG) {
15001 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15002 EVT VT = Op.getValueType();
15003 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15005 switch(IntrData->Type) {
15006 case INTR_TYPE_1OP:
15007 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15008 case INTR_TYPE_2OP:
15009 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15011 case INTR_TYPE_3OP:
15012 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15013 Op.getOperand(2), Op.getOperand(3));
15014 case INTR_TYPE_1OP_MASK_RM: {
15015 SDValue Src = Op.getOperand(1);
15016 SDValue PassThru = Op.getOperand(2);
15017 SDValue Mask = Op.getOperand(3);
15018 SDValue RoundingMode;
15019 if (Op.getNumOperands() == 4)
15020 RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15022 RoundingMode = Op.getOperand(4);
15023 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15024 if (IntrWithRoundingModeOpcode != 0) {
15025 unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
15026 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
15027 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15028 dl, Op.getValueType(), Src, RoundingMode),
15029 Mask, PassThru, Subtarget, DAG);
15031 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15033 Mask, PassThru, Subtarget, DAG);
15035 case INTR_TYPE_1OP_MASK: {
15036 SDValue Src = Op.getOperand(1);
15037 SDValue Passthru = Op.getOperand(2);
15038 SDValue Mask = Op.getOperand(3);
15039 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15040 Mask, Passthru, Subtarget, DAG);
15042 case INTR_TYPE_SCALAR_MASK_RM: {
15043 SDValue Src1 = Op.getOperand(1);
15044 SDValue Src2 = Op.getOperand(2);
15045 SDValue Src0 = Op.getOperand(3);
15046 SDValue Mask = Op.getOperand(4);
15047 // There are 2 kinds of intrinsics in this group:
15048 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15049 // (2) With rounding mode and sae - 7 operands.
15050 if (Op.getNumOperands() == 6) {
15051 SDValue Sae = Op.getOperand(5);
15052 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15053 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15055 Mask, Src0, Subtarget, DAG);
15057 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15058 SDValue RoundingMode = Op.getOperand(5);
15059 SDValue Sae = Op.getOperand(6);
15060 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15061 RoundingMode, Sae),
15062 Mask, Src0, Subtarget, DAG);
15064 case INTR_TYPE_2OP_MASK: {
15065 SDValue Src1 = Op.getOperand(1);
15066 SDValue Src2 = Op.getOperand(2);
15067 SDValue PassThru = Op.getOperand(3);
15068 SDValue Mask = Op.getOperand(4);
15069 // We specify 2 possible opcodes for intrinsics with rounding modes.
15070 // First, we check if the intrinsic may have non-default rounding mode,
15071 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15072 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15073 if (IntrWithRoundingModeOpcode != 0) {
15074 SDValue Rnd = Op.getOperand(5);
15075 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15076 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15077 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15078 dl, Op.getValueType(),
15080 Mask, PassThru, Subtarget, DAG);
15083 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15085 Mask, PassThru, Subtarget, DAG);
15087 case INTR_TYPE_3OP_MASK: {
15088 SDValue Src1 = Op.getOperand(1);
15089 SDValue Src2 = Op.getOperand(2);
15090 SDValue Src3 = Op.getOperand(3);
15091 SDValue PassThru = Op.getOperand(4);
15092 SDValue Mask = Op.getOperand(5);
15093 // We specify 2 possible opcodes for intrinsics with rounding modes.
15094 // First, we check if the intrinsic may have non-default rounding mode,
15095 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15096 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15097 if (IntrWithRoundingModeOpcode != 0) {
15098 SDValue Rnd = Op.getOperand(6);
15099 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15100 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15101 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15102 dl, Op.getValueType(),
15103 Src1, Src2, Src3, Rnd),
15104 Mask, PassThru, Subtarget, DAG);
15107 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15109 Mask, PassThru, Subtarget, DAG);
15111 case VPERM_3OP_MASKZ:
15112 case VPERM_3OP_MASK:
15114 case FMA_OP_MASK: {
15115 SDValue Src1 = Op.getOperand(1);
15116 SDValue Src2 = Op.getOperand(2);
15117 SDValue Src3 = Op.getOperand(3);
15118 SDValue Mask = Op.getOperand(4);
15119 EVT VT = Op.getValueType();
15121 (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ) ?
15122 getZeroVector(VT, Subtarget, DAG, dl) : Src1;
15123 // We specify 2 possible opcodes for intrinsics with rounding modes.
15124 // First, we check if the intrinsic may have non-default rounding mode,
15125 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15126 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15127 if (IntrWithRoundingModeOpcode != 0) {
15128 SDValue Rnd = Op.getOperand(5);
15129 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15130 X86::STATIC_ROUNDING::CUR_DIRECTION)
15131 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15132 dl, Op.getValueType(),
15133 Src1, Src2, Src3, Rnd),
15134 Mask, PassThru, Subtarget, DAG);
15136 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15137 dl, Op.getValueType(),
15139 Mask, PassThru, Subtarget, DAG);
15142 case CMP_MASK_CC: {
15143 // Comparison intrinsics with masks.
15144 // Example of transformation:
15145 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15146 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15148 // (v8i1 (insert_subvector undef,
15149 // (v2i1 (and (PCMPEQM %a, %b),
15150 // (extract_subvector
15151 // (v8i1 (bitcast %mask)), 0))), 0))))
15152 EVT VT = Op.getOperand(1).getValueType();
15153 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15154 VT.getVectorNumElements());
15155 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15156 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15157 Mask.getValueType().getSizeInBits());
15159 if (IntrData->Type == CMP_MASK_CC) {
15160 SDValue CC = Op.getOperand(3);
15161 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15162 // We specify 2 possible opcodes for intrinsics with rounding modes.
15163 // First, we check if the intrinsic may have non-default rounding mode,
15164 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15165 if (IntrData->Opc1 != 0) {
15166 SDValue Rnd = Op.getOperand(5);
15167 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15168 X86::STATIC_ROUNDING::CUR_DIRECTION)
15169 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15170 Op.getOperand(2), CC, Rnd);
15172 //default rounding mode
15174 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15175 Op.getOperand(2), CC);
15178 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15179 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15182 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15183 DAG.getTargetConstant(0, dl,
15186 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15187 DAG.getUNDEF(BitcastVT), CmpMask,
15188 DAG.getIntPtrConstant(0, dl));
15189 return DAG.getBitcast(Op.getValueType(), Res);
15191 case COMI: { // Comparison intrinsics
15192 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15193 SDValue LHS = Op.getOperand(1);
15194 SDValue RHS = Op.getOperand(2);
15195 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15196 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15197 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15198 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15199 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15200 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15203 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15204 Op.getOperand(1), Op.getOperand(2), DAG);
15206 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15207 Op.getSimpleValueType(),
15209 Op.getOperand(2), DAG),
15210 Op.getOperand(4), Op.getOperand(3), Subtarget,
15212 case COMPRESS_EXPAND_IN_REG: {
15213 SDValue Mask = Op.getOperand(3);
15214 SDValue DataToCompress = Op.getOperand(1);
15215 SDValue PassThru = Op.getOperand(2);
15216 if (isAllOnes(Mask)) // return data as is
15217 return Op.getOperand(1);
15219 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15221 Mask, PassThru, Subtarget, DAG);
15224 SDValue Mask = Op.getOperand(3);
15225 EVT VT = Op.getValueType();
15226 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15227 VT.getVectorNumElements());
15228 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15229 Mask.getValueType().getSizeInBits());
15231 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15232 DAG.getBitcast(BitcastVT, Mask),
15233 DAG.getIntPtrConstant(0, dl));
15234 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15243 default: return SDValue(); // Don't custom lower most intrinsics.
15245 case Intrinsic::x86_avx2_permd:
15246 case Intrinsic::x86_avx2_permps:
15247 // Operands intentionally swapped. Mask is last operand to intrinsic,
15248 // but second operand for node/instruction.
15249 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15250 Op.getOperand(2), Op.getOperand(1));
15252 // ptest and testp intrinsics. The intrinsic these come from are designed to
15253 // return an integer value, not just an instruction so lower it to the ptest
15254 // or testp pattern and a setcc for the result.
15255 case Intrinsic::x86_sse41_ptestz:
15256 case Intrinsic::x86_sse41_ptestc:
15257 case Intrinsic::x86_sse41_ptestnzc:
15258 case Intrinsic::x86_avx_ptestz_256:
15259 case Intrinsic::x86_avx_ptestc_256:
15260 case Intrinsic::x86_avx_ptestnzc_256:
15261 case Intrinsic::x86_avx_vtestz_ps:
15262 case Intrinsic::x86_avx_vtestc_ps:
15263 case Intrinsic::x86_avx_vtestnzc_ps:
15264 case Intrinsic::x86_avx_vtestz_pd:
15265 case Intrinsic::x86_avx_vtestc_pd:
15266 case Intrinsic::x86_avx_vtestnzc_pd:
15267 case Intrinsic::x86_avx_vtestz_ps_256:
15268 case Intrinsic::x86_avx_vtestc_ps_256:
15269 case Intrinsic::x86_avx_vtestnzc_ps_256:
15270 case Intrinsic::x86_avx_vtestz_pd_256:
15271 case Intrinsic::x86_avx_vtestc_pd_256:
15272 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15273 bool IsTestPacked = false;
15276 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15277 case Intrinsic::x86_avx_vtestz_ps:
15278 case Intrinsic::x86_avx_vtestz_pd:
15279 case Intrinsic::x86_avx_vtestz_ps_256:
15280 case Intrinsic::x86_avx_vtestz_pd_256:
15281 IsTestPacked = true; // Fallthrough
15282 case Intrinsic::x86_sse41_ptestz:
15283 case Intrinsic::x86_avx_ptestz_256:
15285 X86CC = X86::COND_E;
15287 case Intrinsic::x86_avx_vtestc_ps:
15288 case Intrinsic::x86_avx_vtestc_pd:
15289 case Intrinsic::x86_avx_vtestc_ps_256:
15290 case Intrinsic::x86_avx_vtestc_pd_256:
15291 IsTestPacked = true; // Fallthrough
15292 case Intrinsic::x86_sse41_ptestc:
15293 case Intrinsic::x86_avx_ptestc_256:
15295 X86CC = X86::COND_B;
15297 case Intrinsic::x86_avx_vtestnzc_ps:
15298 case Intrinsic::x86_avx_vtestnzc_pd:
15299 case Intrinsic::x86_avx_vtestnzc_ps_256:
15300 case Intrinsic::x86_avx_vtestnzc_pd_256:
15301 IsTestPacked = true; // Fallthrough
15302 case Intrinsic::x86_sse41_ptestnzc:
15303 case Intrinsic::x86_avx_ptestnzc_256:
15305 X86CC = X86::COND_A;
15309 SDValue LHS = Op.getOperand(1);
15310 SDValue RHS = Op.getOperand(2);
15311 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15312 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15313 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15314 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15315 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15317 case Intrinsic::x86_avx512_kortestz_w:
15318 case Intrinsic::x86_avx512_kortestc_w: {
15319 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15320 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15321 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15322 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15323 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15324 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15325 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15328 case Intrinsic::x86_sse42_pcmpistria128:
15329 case Intrinsic::x86_sse42_pcmpestria128:
15330 case Intrinsic::x86_sse42_pcmpistric128:
15331 case Intrinsic::x86_sse42_pcmpestric128:
15332 case Intrinsic::x86_sse42_pcmpistrio128:
15333 case Intrinsic::x86_sse42_pcmpestrio128:
15334 case Intrinsic::x86_sse42_pcmpistris128:
15335 case Intrinsic::x86_sse42_pcmpestris128:
15336 case Intrinsic::x86_sse42_pcmpistriz128:
15337 case Intrinsic::x86_sse42_pcmpestriz128: {
15341 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15342 case Intrinsic::x86_sse42_pcmpistria128:
15343 Opcode = X86ISD::PCMPISTRI;
15344 X86CC = X86::COND_A;
15346 case Intrinsic::x86_sse42_pcmpestria128:
15347 Opcode = X86ISD::PCMPESTRI;
15348 X86CC = X86::COND_A;
15350 case Intrinsic::x86_sse42_pcmpistric128:
15351 Opcode = X86ISD::PCMPISTRI;
15352 X86CC = X86::COND_B;
15354 case Intrinsic::x86_sse42_pcmpestric128:
15355 Opcode = X86ISD::PCMPESTRI;
15356 X86CC = X86::COND_B;
15358 case Intrinsic::x86_sse42_pcmpistrio128:
15359 Opcode = X86ISD::PCMPISTRI;
15360 X86CC = X86::COND_O;
15362 case Intrinsic::x86_sse42_pcmpestrio128:
15363 Opcode = X86ISD::PCMPESTRI;
15364 X86CC = X86::COND_O;
15366 case Intrinsic::x86_sse42_pcmpistris128:
15367 Opcode = X86ISD::PCMPISTRI;
15368 X86CC = X86::COND_S;
15370 case Intrinsic::x86_sse42_pcmpestris128:
15371 Opcode = X86ISD::PCMPESTRI;
15372 X86CC = X86::COND_S;
15374 case Intrinsic::x86_sse42_pcmpistriz128:
15375 Opcode = X86ISD::PCMPISTRI;
15376 X86CC = X86::COND_E;
15378 case Intrinsic::x86_sse42_pcmpestriz128:
15379 Opcode = X86ISD::PCMPESTRI;
15380 X86CC = X86::COND_E;
15383 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15384 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15385 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15386 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15387 DAG.getConstant(X86CC, dl, MVT::i8),
15388 SDValue(PCMP.getNode(), 1));
15389 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15392 case Intrinsic::x86_sse42_pcmpistri128:
15393 case Intrinsic::x86_sse42_pcmpestri128: {
15395 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15396 Opcode = X86ISD::PCMPISTRI;
15398 Opcode = X86ISD::PCMPESTRI;
15400 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15401 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15402 return DAG.getNode(Opcode, dl, VTs, NewOps);
15405 case Intrinsic::x86_seh_lsda: {
15406 // Compute the symbol for the LSDA. We know it'll get emitted later.
15407 MachineFunction &MF = DAG.getMachineFunction();
15408 SDValue Op1 = Op.getOperand(1);
15409 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15410 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15411 GlobalValue::getRealLinkageName(Fn->getName()));
15413 // Generate a simple absolute symbol reference. This intrinsic is only
15414 // supported on 32-bit Windows, which isn't PIC.
15415 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
15416 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15421 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15422 SDValue Src, SDValue Mask, SDValue Base,
15423 SDValue Index, SDValue ScaleOp, SDValue Chain,
15424 const X86Subtarget * Subtarget) {
15426 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15427 assert(C && "Invalid scale type");
15428 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15429 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15430 Index.getSimpleValueType().getVectorNumElements());
15432 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15434 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15436 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15437 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15438 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15439 SDValue Segment = DAG.getRegister(0, MVT::i32);
15440 if (Src.getOpcode() == ISD::UNDEF)
15441 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15442 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15443 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15444 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15445 return DAG.getMergeValues(RetOps, dl);
15448 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15449 SDValue Src, SDValue Mask, SDValue Base,
15450 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15452 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15453 assert(C && "Invalid scale type");
15454 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15455 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15456 SDValue Segment = DAG.getRegister(0, MVT::i32);
15457 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15458 Index.getSimpleValueType().getVectorNumElements());
15460 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15462 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15464 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15465 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15466 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15467 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15468 return SDValue(Res, 1);
15471 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15472 SDValue Mask, SDValue Base, SDValue Index,
15473 SDValue ScaleOp, SDValue Chain) {
15475 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15476 assert(C && "Invalid scale type");
15477 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15478 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15479 SDValue Segment = DAG.getRegister(0, MVT::i32);
15481 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15483 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15485 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15487 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15488 //SDVTList VTs = DAG.getVTList(MVT::Other);
15489 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15490 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15491 return SDValue(Res, 0);
15494 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15495 // read performance monitor counters (x86_rdpmc).
15496 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15497 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15498 SmallVectorImpl<SDValue> &Results) {
15499 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15500 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15503 // The ECX register is used to select the index of the performance counter
15505 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15507 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15509 // Reads the content of a 64-bit performance counter and returns it in the
15510 // registers EDX:EAX.
15511 if (Subtarget->is64Bit()) {
15512 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15513 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15516 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15517 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15520 Chain = HI.getValue(1);
15522 if (Subtarget->is64Bit()) {
15523 // The EAX register is loaded with the low-order 32 bits. The EDX register
15524 // is loaded with the supported high-order bits of the counter.
15525 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15526 DAG.getConstant(32, DL, MVT::i8));
15527 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15528 Results.push_back(Chain);
15532 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15533 SDValue Ops[] = { LO, HI };
15534 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15535 Results.push_back(Pair);
15536 Results.push_back(Chain);
15539 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15540 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15541 // also used to custom lower READCYCLECOUNTER nodes.
15542 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15543 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15544 SmallVectorImpl<SDValue> &Results) {
15545 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15546 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15549 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15550 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15551 // and the EAX register is loaded with the low-order 32 bits.
15552 if (Subtarget->is64Bit()) {
15553 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15554 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15557 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15558 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15561 SDValue Chain = HI.getValue(1);
15563 if (Opcode == X86ISD::RDTSCP_DAG) {
15564 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15566 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15567 // the ECX register. Add 'ecx' explicitly to the chain.
15568 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15570 // Explicitly store the content of ECX at the location passed in input
15571 // to the 'rdtscp' intrinsic.
15572 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15573 MachinePointerInfo(), false, false, 0);
15576 if (Subtarget->is64Bit()) {
15577 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15578 // the EAX register is loaded with the low-order 32 bits.
15579 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15580 DAG.getConstant(32, DL, MVT::i8));
15581 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15582 Results.push_back(Chain);
15586 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15587 SDValue Ops[] = { LO, HI };
15588 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15589 Results.push_back(Pair);
15590 Results.push_back(Chain);
15593 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15594 SelectionDAG &DAG) {
15595 SmallVector<SDValue, 2> Results;
15597 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15599 return DAG.getMergeValues(Results, DL);
15602 static SDValue LowerEXCEPTIONINFO(SDValue Op, const X86Subtarget *Subtarget,
15603 SelectionDAG &DAG) {
15604 MachineFunction &MF = DAG.getMachineFunction();
15606 SDValue FnOp = Op.getOperand(2);
15607 SDValue FPOp = Op.getOperand(3);
15609 // Compute the symbol for the parent EH registration. We know it'll get
15611 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(FnOp)->getGlobal());
15612 MCSymbol *ParentFrameSym =
15613 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15614 GlobalValue::getRealLinkageName(Fn->getName()));
15616 // Create a TargetExternalSymbol for the label to avoid any target lowering
15617 // that would make this PC relative.
15618 MVT PtrVT = Op.getSimpleValueType();
15619 SDValue OffsetSym = DAG.getMCSymbol(ParentFrameSym, PtrVT);
15620 SDValue OffsetVal =
15621 DAG.getNode(ISD::FRAME_ALLOC_RECOVER, dl, PtrVT, OffsetSym);
15623 // Add the offset to the FP.
15624 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, FPOp, OffsetVal);
15626 // Load the second field of the struct, which is 4 bytes in. See
15627 // WinEHStatePass for more info.
15628 Add = DAG.getNode(ISD::ADD, dl, PtrVT, Add, DAG.getConstant(4, dl, PtrVT));
15629 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Add, MachinePointerInfo(),
15630 false, false, false, 0);
15633 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15634 SelectionDAG &DAG) {
15635 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15637 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15639 if (IntNo == Intrinsic::x86_seh_exceptioninfo)
15640 return LowerEXCEPTIONINFO(Op, Subtarget, DAG);
15645 switch(IntrData->Type) {
15647 llvm_unreachable("Unknown Intrinsic Type");
15651 // Emit the node with the right value type.
15652 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
15653 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15655 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
15656 // Otherwise return the value from Rand, which is always 0, casted to i32.
15657 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
15658 DAG.getConstant(1, dl, Op->getValueType(1)),
15659 DAG.getConstant(X86::COND_B, dl, MVT::i32),
15660 SDValue(Result.getNode(), 1) };
15661 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
15662 DAG.getVTList(Op->getValueType(1), MVT::Glue),
15665 // Return { result, isValid, chain }.
15666 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
15667 SDValue(Result.getNode(), 2));
15670 //gather(v1, mask, index, base, scale);
15671 SDValue Chain = Op.getOperand(0);
15672 SDValue Src = Op.getOperand(2);
15673 SDValue Base = Op.getOperand(3);
15674 SDValue Index = Op.getOperand(4);
15675 SDValue Mask = Op.getOperand(5);
15676 SDValue Scale = Op.getOperand(6);
15677 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
15681 //scatter(base, mask, index, v1, scale);
15682 SDValue Chain = Op.getOperand(0);
15683 SDValue Base = Op.getOperand(2);
15684 SDValue Mask = Op.getOperand(3);
15685 SDValue Index = Op.getOperand(4);
15686 SDValue Src = Op.getOperand(5);
15687 SDValue Scale = Op.getOperand(6);
15688 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
15692 SDValue Hint = Op.getOperand(6);
15693 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
15694 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
15695 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
15696 SDValue Chain = Op.getOperand(0);
15697 SDValue Mask = Op.getOperand(2);
15698 SDValue Index = Op.getOperand(3);
15699 SDValue Base = Op.getOperand(4);
15700 SDValue Scale = Op.getOperand(5);
15701 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
15703 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
15705 SmallVector<SDValue, 2> Results;
15706 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
15708 return DAG.getMergeValues(Results, dl);
15710 // Read Performance Monitoring Counters.
15712 SmallVector<SDValue, 2> Results;
15713 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
15714 return DAG.getMergeValues(Results, dl);
15716 // XTEST intrinsics.
15718 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15719 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
15720 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15721 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
15723 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
15724 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
15725 Ret, SDValue(InTrans.getNode(), 1));
15729 SmallVector<SDValue, 2> Results;
15730 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
15731 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
15732 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
15733 DAG.getConstant(-1, dl, MVT::i8));
15734 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
15735 Op.getOperand(4), GenCF.getValue(1));
15736 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
15737 Op.getOperand(5), MachinePointerInfo(),
15739 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15740 DAG.getConstant(X86::COND_B, dl, MVT::i8),
15742 Results.push_back(SetCC);
15743 Results.push_back(Store);
15744 return DAG.getMergeValues(Results, dl);
15746 case COMPRESS_TO_MEM: {
15748 SDValue Mask = Op.getOperand(4);
15749 SDValue DataToCompress = Op.getOperand(3);
15750 SDValue Addr = Op.getOperand(2);
15751 SDValue Chain = Op.getOperand(0);
15753 EVT VT = DataToCompress.getValueType();
15754 if (isAllOnes(Mask)) // return just a store
15755 return DAG.getStore(Chain, dl, DataToCompress, Addr,
15756 MachinePointerInfo(), false, false,
15757 VT.getScalarSizeInBits()/8);
15759 SDValue Compressed =
15760 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
15761 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
15762 return DAG.getStore(Chain, dl, Compressed, Addr,
15763 MachinePointerInfo(), false, false,
15764 VT.getScalarSizeInBits()/8);
15766 case EXPAND_FROM_MEM: {
15768 SDValue Mask = Op.getOperand(4);
15769 SDValue PassThru = Op.getOperand(3);
15770 SDValue Addr = Op.getOperand(2);
15771 SDValue Chain = Op.getOperand(0);
15772 EVT VT = Op.getValueType();
15774 if (isAllOnes(Mask)) // return just a load
15775 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
15776 false, VT.getScalarSizeInBits()/8);
15778 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
15779 false, false, false,
15780 VT.getScalarSizeInBits()/8);
15782 SDValue Results[] = {
15783 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
15784 Mask, PassThru, Subtarget, DAG), Chain};
15785 return DAG.getMergeValues(Results, dl);
15790 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
15791 SelectionDAG &DAG) const {
15792 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
15793 MFI->setReturnAddressIsTaken(true);
15795 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
15798 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15800 EVT PtrVT = getPointerTy();
15803 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
15804 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15805 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
15806 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15807 DAG.getNode(ISD::ADD, dl, PtrVT,
15808 FrameAddr, Offset),
15809 MachinePointerInfo(), false, false, false, 0);
15812 // Just load the return address.
15813 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
15814 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
15815 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
15818 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
15819 MachineFunction &MF = DAG.getMachineFunction();
15820 MachineFrameInfo *MFI = MF.getFrameInfo();
15821 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
15822 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15823 EVT VT = Op.getValueType();
15825 MFI->setFrameAddressIsTaken(true);
15827 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
15828 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
15829 // is not possible to crawl up the stack without looking at the unwind codes
15831 int FrameAddrIndex = FuncInfo->getFAIndex();
15832 if (!FrameAddrIndex) {
15833 // Set up a frame object for the return address.
15834 unsigned SlotSize = RegInfo->getSlotSize();
15835 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
15836 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
15837 FuncInfo->setFAIndex(FrameAddrIndex);
15839 return DAG.getFrameIndex(FrameAddrIndex, VT);
15842 unsigned FrameReg =
15843 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15844 SDLoc dl(Op); // FIXME probably not meaningful
15845 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15846 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
15847 (FrameReg == X86::EBP && VT == MVT::i32)) &&
15848 "Invalid Frame Register!");
15849 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
15851 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
15852 MachinePointerInfo(),
15853 false, false, false, 0);
15857 // FIXME? Maybe this could be a TableGen attribute on some registers and
15858 // this table could be generated automatically from RegInfo.
15859 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
15861 unsigned Reg = StringSwitch<unsigned>(RegName)
15862 .Case("esp", X86::ESP)
15863 .Case("rsp", X86::RSP)
15867 report_fatal_error("Invalid register name global variable");
15870 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
15871 SelectionDAG &DAG) const {
15872 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15873 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
15876 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
15877 SDValue Chain = Op.getOperand(0);
15878 SDValue Offset = Op.getOperand(1);
15879 SDValue Handler = Op.getOperand(2);
15882 EVT PtrVT = getPointerTy();
15883 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15884 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
15885 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
15886 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
15887 "Invalid Frame Register!");
15888 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
15889 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
15891 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
15892 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
15894 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
15895 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
15897 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
15899 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
15900 DAG.getRegister(StoreAddrReg, PtrVT));
15903 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
15904 SelectionDAG &DAG) const {
15906 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
15907 DAG.getVTList(MVT::i32, MVT::Other),
15908 Op.getOperand(0), Op.getOperand(1));
15911 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
15912 SelectionDAG &DAG) const {
15914 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
15915 Op.getOperand(0), Op.getOperand(1));
15918 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
15919 return Op.getOperand(0);
15922 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
15923 SelectionDAG &DAG) const {
15924 SDValue Root = Op.getOperand(0);
15925 SDValue Trmp = Op.getOperand(1); // trampoline
15926 SDValue FPtr = Op.getOperand(2); // nested function
15927 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
15930 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15931 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15933 if (Subtarget->is64Bit()) {
15934 SDValue OutChains[6];
15936 // Large code-model.
15937 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
15938 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
15940 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
15941 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
15943 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
15945 // Load the pointer to the nested function into R11.
15946 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
15947 SDValue Addr = Trmp;
15948 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15949 Addr, MachinePointerInfo(TrmpAddr),
15952 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15953 DAG.getConstant(2, dl, MVT::i64));
15954 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
15955 MachinePointerInfo(TrmpAddr, 2),
15958 // Load the 'nest' parameter value into R10.
15959 // R10 is specified in X86CallingConv.td
15960 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
15961 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15962 DAG.getConstant(10, dl, MVT::i64));
15963 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15964 Addr, MachinePointerInfo(TrmpAddr, 10),
15967 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15968 DAG.getConstant(12, dl, MVT::i64));
15969 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
15970 MachinePointerInfo(TrmpAddr, 12),
15973 // Jump to the nested function.
15974 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
15975 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15976 DAG.getConstant(20, dl, MVT::i64));
15977 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
15978 Addr, MachinePointerInfo(TrmpAddr, 20),
15981 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
15982 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
15983 DAG.getConstant(22, dl, MVT::i64));
15984 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
15985 Addr, MachinePointerInfo(TrmpAddr, 22),
15988 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
15990 const Function *Func =
15991 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
15992 CallingConv::ID CC = Func->getCallingConv();
15997 llvm_unreachable("Unsupported calling convention");
15998 case CallingConv::C:
15999 case CallingConv::X86_StdCall: {
16000 // Pass 'nest' parameter in ECX.
16001 // Must be kept in sync with X86CallingConv.td
16002 NestReg = X86::ECX;
16004 // Check that ECX wasn't needed by an 'inreg' parameter.
16005 FunctionType *FTy = Func->getFunctionType();
16006 const AttributeSet &Attrs = Func->getAttributes();
16008 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16009 unsigned InRegCount = 0;
16012 for (FunctionType::param_iterator I = FTy->param_begin(),
16013 E = FTy->param_end(); I != E; ++I, ++Idx)
16014 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16015 // FIXME: should only count parameters that are lowered to integers.
16016 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16018 if (InRegCount > 2) {
16019 report_fatal_error("Nest register in use - reduce number of inreg"
16025 case CallingConv::X86_FastCall:
16026 case CallingConv::X86_ThisCall:
16027 case CallingConv::Fast:
16028 // Pass 'nest' parameter in EAX.
16029 // Must be kept in sync with X86CallingConv.td
16030 NestReg = X86::EAX;
16034 SDValue OutChains[4];
16035 SDValue Addr, Disp;
16037 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16038 DAG.getConstant(10, dl, MVT::i32));
16039 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16041 // This is storing the opcode for MOV32ri.
16042 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16043 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16044 OutChains[0] = DAG.getStore(Root, dl,
16045 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16046 Trmp, MachinePointerInfo(TrmpAddr),
16049 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16050 DAG.getConstant(1, dl, MVT::i32));
16051 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16052 MachinePointerInfo(TrmpAddr, 1),
16055 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16056 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16057 DAG.getConstant(5, dl, MVT::i32));
16058 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16059 Addr, MachinePointerInfo(TrmpAddr, 5),
16062 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16063 DAG.getConstant(6, dl, MVT::i32));
16064 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16065 MachinePointerInfo(TrmpAddr, 6),
16068 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16072 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16073 SelectionDAG &DAG) const {
16075 The rounding mode is in bits 11:10 of FPSR, and has the following
16077 00 Round to nearest
16082 FLT_ROUNDS, on the other hand, expects the following:
16089 To perform the conversion, we do:
16090 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16093 MachineFunction &MF = DAG.getMachineFunction();
16094 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16095 unsigned StackAlignment = TFI.getStackAlignment();
16096 MVT VT = Op.getSimpleValueType();
16099 // Save FP Control Word to stack slot
16100 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16101 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16103 MachineMemOperand *MMO =
16104 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16105 MachineMemOperand::MOStore, 2, 2);
16107 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16108 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16109 DAG.getVTList(MVT::Other),
16110 Ops, MVT::i16, MMO);
16112 // Load FP Control Word from stack slot
16113 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16114 MachinePointerInfo(), false, false, false, 0);
16116 // Transform as necessary
16118 DAG.getNode(ISD::SRL, DL, MVT::i16,
16119 DAG.getNode(ISD::AND, DL, MVT::i16,
16120 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16121 DAG.getConstant(11, DL, MVT::i8));
16123 DAG.getNode(ISD::SRL, DL, MVT::i16,
16124 DAG.getNode(ISD::AND, DL, MVT::i16,
16125 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16126 DAG.getConstant(9, DL, MVT::i8));
16129 DAG.getNode(ISD::AND, DL, MVT::i16,
16130 DAG.getNode(ISD::ADD, DL, MVT::i16,
16131 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16132 DAG.getConstant(1, DL, MVT::i16)),
16133 DAG.getConstant(3, DL, MVT::i16));
16135 return DAG.getNode((VT.getSizeInBits() < 16 ?
16136 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16139 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16140 MVT VT = Op.getSimpleValueType();
16142 unsigned NumBits = VT.getSizeInBits();
16145 Op = Op.getOperand(0);
16146 if (VT == MVT::i8) {
16147 // Zero extend to i32 since there is not an i8 bsr.
16149 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16152 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16153 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16154 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16156 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16159 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16160 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16163 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16165 // Finally xor with NumBits-1.
16166 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16167 DAG.getConstant(NumBits - 1, dl, OpVT));
16170 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16174 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16175 MVT VT = Op.getSimpleValueType();
16177 unsigned NumBits = VT.getSizeInBits();
16180 Op = Op.getOperand(0);
16181 if (VT == MVT::i8) {
16182 // Zero extend to i32 since there is not an i8 bsr.
16184 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16187 // Issue a bsr (scan bits in reverse).
16188 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16189 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16191 // And xor with NumBits-1.
16192 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16193 DAG.getConstant(NumBits - 1, dl, OpVT));
16196 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16200 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16201 MVT VT = Op.getSimpleValueType();
16202 unsigned NumBits = VT.getSizeInBits();
16204 Op = Op.getOperand(0);
16206 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16207 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16208 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16210 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16213 DAG.getConstant(NumBits, dl, VT),
16214 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16217 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16220 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16221 // ones, and then concatenate the result back.
16222 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16223 MVT VT = Op.getSimpleValueType();
16225 assert(VT.is256BitVector() && VT.isInteger() &&
16226 "Unsupported value type for operation");
16228 unsigned NumElems = VT.getVectorNumElements();
16231 // Extract the LHS vectors
16232 SDValue LHS = Op.getOperand(0);
16233 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16234 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16236 // Extract the RHS vectors
16237 SDValue RHS = Op.getOperand(1);
16238 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16239 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16241 MVT EltVT = VT.getVectorElementType();
16242 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16244 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16245 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16246 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16249 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16250 if (Op.getValueType() == MVT::i1)
16251 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16252 Op.getOperand(0), Op.getOperand(1));
16253 assert(Op.getSimpleValueType().is256BitVector() &&
16254 Op.getSimpleValueType().isInteger() &&
16255 "Only handle AVX 256-bit vector integer operation");
16256 return Lower256IntArith(Op, DAG);
16259 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16260 if (Op.getValueType() == MVT::i1)
16261 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16262 Op.getOperand(0), Op.getOperand(1));
16263 assert(Op.getSimpleValueType().is256BitVector() &&
16264 Op.getSimpleValueType().isInteger() &&
16265 "Only handle AVX 256-bit vector integer operation");
16266 return Lower256IntArith(Op, DAG);
16269 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16270 SelectionDAG &DAG) {
16272 MVT VT = Op.getSimpleValueType();
16275 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16277 // Decompose 256-bit ops into smaller 128-bit ops.
16278 if (VT.is256BitVector() && !Subtarget->hasInt256())
16279 return Lower256IntArith(Op, DAG);
16281 SDValue A = Op.getOperand(0);
16282 SDValue B = Op.getOperand(1);
16284 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16285 // pairs, multiply and truncate.
16286 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16287 if (Subtarget->hasInt256()) {
16288 if (VT == MVT::v32i8) {
16289 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16290 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16291 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16292 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16293 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16294 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16295 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16296 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16297 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16298 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16301 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16302 return DAG.getNode(
16303 ISD::TRUNCATE, dl, VT,
16304 DAG.getNode(ISD::MUL, dl, ExVT,
16305 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16306 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16309 assert(VT == MVT::v16i8 &&
16310 "Pre-AVX2 support only supports v16i8 multiplication");
16311 MVT ExVT = MVT::v8i16;
16313 // Extract the lo parts and sign extend to i16
16315 if (Subtarget->hasSSE41()) {
16316 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16317 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16319 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16320 -1, 4, -1, 5, -1, 6, -1, 7};
16321 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16322 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16323 ALo = DAG.getBitcast(ExVT, ALo);
16324 BLo = DAG.getBitcast(ExVT, BLo);
16325 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16326 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16329 // Extract the hi parts and sign extend to i16
16331 if (Subtarget->hasSSE41()) {
16332 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16333 -1, -1, -1, -1, -1, -1, -1, -1};
16334 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16335 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16336 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16337 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16339 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16340 -1, 12, -1, 13, -1, 14, -1, 15};
16341 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16342 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16343 AHi = DAG.getBitcast(ExVT, AHi);
16344 BHi = DAG.getBitcast(ExVT, BHi);
16345 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16346 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16349 // Multiply, mask the lower 8bits of the lo/hi results and pack
16350 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16351 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16352 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16353 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16354 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16357 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16358 if (VT == MVT::v4i32) {
16359 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16360 "Should not custom lower when pmuldq is available!");
16362 // Extract the odd parts.
16363 static const int UnpackMask[] = { 1, -1, 3, -1 };
16364 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16365 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16367 // Multiply the even parts.
16368 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16369 // Now multiply odd parts.
16370 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16372 Evens = DAG.getBitcast(VT, Evens);
16373 Odds = DAG.getBitcast(VT, Odds);
16375 // Merge the two vectors back together with a shuffle. This expands into 2
16377 static const int ShufMask[] = { 0, 4, 2, 6 };
16378 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16381 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16382 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16384 // Ahi = psrlqi(a, 32);
16385 // Bhi = psrlqi(b, 32);
16387 // AloBlo = pmuludq(a, b);
16388 // AloBhi = pmuludq(a, Bhi);
16389 // AhiBlo = pmuludq(Ahi, b);
16391 // AloBhi = psllqi(AloBhi, 32);
16392 // AhiBlo = psllqi(AhiBlo, 32);
16393 // return AloBlo + AloBhi + AhiBlo;
16395 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16396 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16398 SDValue AhiBlo = Ahi;
16399 SDValue AloBhi = Bhi;
16400 // Bit cast to 32-bit vectors for MULUDQ
16401 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16402 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16403 A = DAG.getBitcast(MulVT, A);
16404 B = DAG.getBitcast(MulVT, B);
16405 Ahi = DAG.getBitcast(MulVT, Ahi);
16406 Bhi = DAG.getBitcast(MulVT, Bhi);
16408 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16409 // After shifting right const values the result may be all-zero.
16410 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
16411 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16412 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16414 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
16415 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16416 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16419 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16420 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16423 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16424 assert(Subtarget->isTargetWin64() && "Unexpected target");
16425 EVT VT = Op.getValueType();
16426 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16427 "Unexpected return type for lowering");
16431 switch (Op->getOpcode()) {
16432 default: llvm_unreachable("Unexpected request for libcall!");
16433 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16434 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16435 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16436 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16437 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16438 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16442 SDValue InChain = DAG.getEntryNode();
16444 TargetLowering::ArgListTy Args;
16445 TargetLowering::ArgListEntry Entry;
16446 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16447 EVT ArgVT = Op->getOperand(i).getValueType();
16448 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16449 "Unexpected argument type for lowering");
16450 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16451 Entry.Node = StackPtr;
16452 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16454 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16455 Entry.Ty = PointerType::get(ArgTy,0);
16456 Entry.isSExt = false;
16457 Entry.isZExt = false;
16458 Args.push_back(Entry);
16461 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16464 TargetLowering::CallLoweringInfo CLI(DAG);
16465 CLI.setDebugLoc(dl).setChain(InChain)
16466 .setCallee(getLibcallCallingConv(LC),
16467 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16468 Callee, std::move(Args), 0)
16469 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16471 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16472 return DAG.getBitcast(VT, CallInfo.first);
16475 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16476 SelectionDAG &DAG) {
16477 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16478 EVT VT = Op0.getValueType();
16481 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16482 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16484 // PMULxD operations multiply each even value (starting at 0) of LHS with
16485 // the related value of RHS and produce a widen result.
16486 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16487 // => <2 x i64> <ae|cg>
16489 // In other word, to have all the results, we need to perform two PMULxD:
16490 // 1. one with the even values.
16491 // 2. one with the odd values.
16492 // To achieve #2, with need to place the odd values at an even position.
16494 // Place the odd value at an even position (basically, shift all values 1
16495 // step to the left):
16496 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16497 // <a|b|c|d> => <b|undef|d|undef>
16498 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16499 // <e|f|g|h> => <f|undef|h|undef>
16500 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16502 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16504 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16505 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16507 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16508 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16509 // => <2 x i64> <ae|cg>
16510 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16511 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16512 // => <2 x i64> <bf|dh>
16513 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16515 // Shuffle it back into the right order.
16516 SDValue Highs, Lows;
16517 if (VT == MVT::v8i32) {
16518 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16519 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16520 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16521 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16523 const int HighMask[] = {1, 5, 3, 7};
16524 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16525 const int LowMask[] = {0, 4, 2, 6};
16526 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16529 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16530 // unsigned multiply.
16531 if (IsSigned && !Subtarget->hasSSE41()) {
16533 DAG.getConstant(31, dl,
16534 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16535 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16536 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16537 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16538 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16540 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16541 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16544 // The first result of MUL_LOHI is actually the low value, followed by the
16546 SDValue Ops[] = {Lows, Highs};
16547 return DAG.getMergeValues(Ops, dl);
16550 // Return true if the requred (according to Opcode) shift-imm form is natively
16551 // supported by the Subtarget
16552 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16554 if (VT.getScalarSizeInBits() < 16)
16557 if (VT.is512BitVector() &&
16558 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16561 bool LShift = VT.is128BitVector() ||
16562 (VT.is256BitVector() && Subtarget->hasInt256());
16564 bool AShift = LShift && (Subtarget->hasVLX() ||
16565 (VT != MVT::v2i64 && VT != MVT::v4i64));
16566 return (Opcode == ISD::SRA) ? AShift : LShift;
16569 // The shift amount is a variable, but it is the same for all vector lanes.
16570 // These instrcutions are defined together with shift-immediate.
16572 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16574 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16577 // Return true if the requred (according to Opcode) variable-shift form is
16578 // natively supported by the Subtarget
16579 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16582 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16585 // vXi16 supported only on AVX-512, BWI
16586 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16589 if (VT.is512BitVector() || Subtarget->hasVLX())
16592 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16593 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16594 return (Opcode == ISD::SRA) ? AShift : LShift;
16597 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16598 const X86Subtarget *Subtarget) {
16599 MVT VT = Op.getSimpleValueType();
16601 SDValue R = Op.getOperand(0);
16602 SDValue Amt = Op.getOperand(1);
16604 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16605 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16607 // Optimize shl/srl/sra with constant shift amount.
16608 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16609 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16610 uint64_t ShiftAmt = ShiftConst->getZExtValue();
16612 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
16613 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16615 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
16616 unsigned NumElts = VT.getVectorNumElements();
16617 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
16619 if (Op.getOpcode() == ISD::SHL) {
16620 // Simple i8 add case
16622 return DAG.getNode(ISD::ADD, dl, VT, R, R);
16624 // Make a large shift.
16625 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
16627 SHL = DAG.getBitcast(VT, SHL);
16628 // Zero out the rightmost bits.
16629 SmallVector<SDValue, 32> V(
16630 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
16631 return DAG.getNode(ISD::AND, dl, VT, SHL,
16632 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16634 if (Op.getOpcode() == ISD::SRL) {
16635 // Make a large shift.
16636 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
16638 SRL = DAG.getBitcast(VT, SRL);
16639 // Zero out the leftmost bits.
16640 SmallVector<SDValue, 32> V(
16641 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
16642 return DAG.getNode(ISD::AND, dl, VT, SRL,
16643 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
16645 if (Op.getOpcode() == ISD::SRA) {
16646 if (ShiftAmt == 7) {
16647 // R s>> 7 === R s< 0
16648 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
16649 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
16652 // R s>> a === ((R u>> a) ^ m) - m
16653 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
16654 SmallVector<SDValue, 32> V(NumElts,
16655 DAG.getConstant(128 >> ShiftAmt, dl,
16657 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
16658 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
16659 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
16662 llvm_unreachable("Unknown shift opcode.");
16667 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16668 if (!Subtarget->is64Bit() &&
16669 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
16670 Amt.getOpcode() == ISD::BITCAST &&
16671 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16672 Amt = Amt.getOperand(0);
16673 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16674 VT.getVectorNumElements();
16675 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
16676 uint64_t ShiftAmt = 0;
16677 for (unsigned i = 0; i != Ratio; ++i) {
16678 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
16682 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
16684 // Check remaining shift amounts.
16685 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16686 uint64_t ShAmt = 0;
16687 for (unsigned j = 0; j != Ratio; ++j) {
16688 ConstantSDNode *C =
16689 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
16693 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
16695 if (ShAmt != ShiftAmt)
16698 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
16704 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
16705 const X86Subtarget* Subtarget) {
16706 MVT VT = Op.getSimpleValueType();
16708 SDValue R = Op.getOperand(0);
16709 SDValue Amt = Op.getOperand(1);
16711 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16712 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16714 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
16715 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
16717 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
16719 EVT EltVT = VT.getVectorElementType();
16721 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
16722 // Check if this build_vector node is doing a splat.
16723 // If so, then set BaseShAmt equal to the splat value.
16724 BaseShAmt = BV->getSplatValue();
16725 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
16726 BaseShAmt = SDValue();
16728 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
16729 Amt = Amt.getOperand(0);
16731 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
16732 if (SVN && SVN->isSplat()) {
16733 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
16734 SDValue InVec = Amt.getOperand(0);
16735 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
16736 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
16737 "Unexpected shuffle index found!");
16738 BaseShAmt = InVec.getOperand(SplatIdx);
16739 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
16740 if (ConstantSDNode *C =
16741 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
16742 if (C->getZExtValue() == SplatIdx)
16743 BaseShAmt = InVec.getOperand(1);
16748 // Avoid introducing an extract element from a shuffle.
16749 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
16750 DAG.getIntPtrConstant(SplatIdx, dl));
16754 if (BaseShAmt.getNode()) {
16755 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
16756 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
16757 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
16758 else if (EltVT.bitsLT(MVT::i32))
16759 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
16761 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
16765 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
16766 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
16767 Amt.getOpcode() == ISD::BITCAST &&
16768 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
16769 Amt = Amt.getOperand(0);
16770 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
16771 VT.getVectorNumElements();
16772 std::vector<SDValue> Vals(Ratio);
16773 for (unsigned i = 0; i != Ratio; ++i)
16774 Vals[i] = Amt.getOperand(i);
16775 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
16776 for (unsigned j = 0; j != Ratio; ++j)
16777 if (Vals[j] != Amt.getOperand(i + j))
16780 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
16785 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
16786 SelectionDAG &DAG) {
16787 MVT VT = Op.getSimpleValueType();
16789 SDValue R = Op.getOperand(0);
16790 SDValue Amt = Op.getOperand(1);
16792 assert(VT.isVector() && "Custom lowering only for vector shifts!");
16793 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
16795 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
16798 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
16801 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
16804 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
16805 // shifts per-lane and then shuffle the partial results back together.
16806 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
16807 // Splat the shift amounts so the scalar shifts above will catch it.
16808 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
16809 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
16810 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
16811 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
16812 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
16815 // If possible, lower this packed shift into a vector multiply instead of
16816 // expanding it into a sequence of scalar shifts.
16817 // Do this only if the vector shift count is a constant build_vector.
16818 if (Op.getOpcode() == ISD::SHL &&
16819 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
16820 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
16821 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16822 SmallVector<SDValue, 8> Elts;
16823 EVT SVT = VT.getScalarType();
16824 unsigned SVTBits = SVT.getSizeInBits();
16825 const APInt &One = APInt(SVTBits, 1);
16826 unsigned NumElems = VT.getVectorNumElements();
16828 for (unsigned i=0; i !=NumElems; ++i) {
16829 SDValue Op = Amt->getOperand(i);
16830 if (Op->getOpcode() == ISD::UNDEF) {
16831 Elts.push_back(Op);
16835 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
16836 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
16837 uint64_t ShAmt = C.getZExtValue();
16838 if (ShAmt >= SVTBits) {
16839 Elts.push_back(DAG.getUNDEF(SVT));
16842 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
16844 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
16845 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
16848 // Lower SHL with variable shift amount.
16849 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
16850 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
16852 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
16853 DAG.getConstant(0x3f800000U, dl, VT));
16854 Op = DAG.getBitcast(MVT::v4f32, Op);
16855 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
16856 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
16859 // If possible, lower this shift as a sequence of two shifts by
16860 // constant plus a MOVSS/MOVSD instead of scalarizing it.
16862 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
16864 // Could be rewritten as:
16865 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
16867 // The advantage is that the two shifts from the example would be
16868 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
16869 // the vector shift into four scalar shifts plus four pairs of vector
16871 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
16872 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
16873 unsigned TargetOpcode = X86ISD::MOVSS;
16874 bool CanBeSimplified;
16875 // The splat value for the first packed shift (the 'X' from the example).
16876 SDValue Amt1 = Amt->getOperand(0);
16877 // The splat value for the second packed shift (the 'Y' from the example).
16878 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
16879 Amt->getOperand(2);
16881 // See if it is possible to replace this node with a sequence of
16882 // two shifts followed by a MOVSS/MOVSD
16883 if (VT == MVT::v4i32) {
16884 // Check if it is legal to use a MOVSS.
16885 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
16886 Amt2 == Amt->getOperand(3);
16887 if (!CanBeSimplified) {
16888 // Otherwise, check if we can still simplify this node using a MOVSD.
16889 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
16890 Amt->getOperand(2) == Amt->getOperand(3);
16891 TargetOpcode = X86ISD::MOVSD;
16892 Amt2 = Amt->getOperand(2);
16895 // Do similar checks for the case where the machine value type
16897 CanBeSimplified = Amt1 == Amt->getOperand(1);
16898 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
16899 CanBeSimplified = Amt2 == Amt->getOperand(i);
16901 if (!CanBeSimplified) {
16902 TargetOpcode = X86ISD::MOVSD;
16903 CanBeSimplified = true;
16904 Amt2 = Amt->getOperand(4);
16905 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
16906 CanBeSimplified = Amt1 == Amt->getOperand(i);
16907 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
16908 CanBeSimplified = Amt2 == Amt->getOperand(j);
16912 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
16913 isa<ConstantSDNode>(Amt2)) {
16914 // Replace this node with two shifts followed by a MOVSS/MOVSD.
16915 EVT CastVT = MVT::v4i32;
16917 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
16918 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
16920 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
16921 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
16922 if (TargetOpcode == X86ISD::MOVSD)
16923 CastVT = MVT::v2i64;
16924 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
16925 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
16926 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
16928 return DAG.getBitcast(VT, Result);
16932 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
16933 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
16934 unsigned ShiftOpcode = Op->getOpcode();
16936 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
16937 // On SSE41 targets we make use of the fact that VSELECT lowers
16938 // to PBLENDVB which selects bytes based just on the sign bit.
16939 if (Subtarget->hasSSE41()) {
16940 V0 = DAG.getBitcast(VT, V0);
16941 V1 = DAG.getBitcast(VT, V1);
16942 Sel = DAG.getBitcast(VT, Sel);
16943 return DAG.getBitcast(SelVT,
16944 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
16946 // On pre-SSE41 targets we test for the sign bit by comparing to
16947 // zero - a negative value will set all bits of the lanes to true
16948 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
16949 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
16950 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
16951 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
16954 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
16955 // We can safely do this using i16 shifts as we're only interested in
16956 // the 3 lower bits of each byte.
16957 Amt = DAG.getBitcast(ExtVT, Amt);
16958 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
16959 Amt = DAG.getBitcast(VT, Amt);
16961 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
16962 // r = VSELECT(r, shift(r, 4), a);
16964 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
16965 R = SignBitSelect(VT, Amt, M, R);
16968 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
16970 // r = VSELECT(r, shift(r, 2), a);
16971 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
16972 R = SignBitSelect(VT, Amt, M, R);
16975 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
16977 // return VSELECT(r, shift(r, 1), a);
16978 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
16979 R = SignBitSelect(VT, Amt, M, R);
16983 if (Op->getOpcode() == ISD::SRA) {
16984 // For SRA we need to unpack each byte to the higher byte of a i16 vector
16985 // so we can correctly sign extend. We don't care what happens to the
16987 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
16988 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
16989 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
16990 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
16991 ALo = DAG.getBitcast(ExtVT, ALo);
16992 AHi = DAG.getBitcast(ExtVT, AHi);
16993 RLo = DAG.getBitcast(ExtVT, RLo);
16994 RHi = DAG.getBitcast(ExtVT, RHi);
16996 // r = VSELECT(r, shift(r, 4), a);
16997 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
16998 DAG.getConstant(4, dl, ExtVT));
16999 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17000 DAG.getConstant(4, dl, ExtVT));
17001 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17002 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17005 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17006 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17008 // r = VSELECT(r, shift(r, 2), a);
17009 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17010 DAG.getConstant(2, dl, ExtVT));
17011 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17012 DAG.getConstant(2, dl, ExtVT));
17013 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17014 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17017 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17018 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17020 // r = VSELECT(r, shift(r, 1), a);
17021 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17022 DAG.getConstant(1, dl, ExtVT));
17023 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17024 DAG.getConstant(1, dl, ExtVT));
17025 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17026 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17028 // Logical shift the result back to the lower byte, leaving a zero upper
17030 // meaning that we can safely pack with PACKUSWB.
17032 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
17034 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
17035 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17039 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17040 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17041 // solution better.
17042 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17043 MVT ExtVT = MVT::v8i32;
17045 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17046 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17047 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17048 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17049 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17052 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17053 MVT ExtVT = MVT::v8i32;
17054 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17055 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17056 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17057 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17058 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17059 ALo = DAG.getBitcast(ExtVT, ALo);
17060 AHi = DAG.getBitcast(ExtVT, AHi);
17061 RLo = DAG.getBitcast(ExtVT, RLo);
17062 RHi = DAG.getBitcast(ExtVT, RHi);
17063 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17064 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17065 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17066 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17067 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17070 if (VT == MVT::v8i16) {
17071 unsigned ShiftOpcode = Op->getOpcode();
17073 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
17074 // On SSE41 targets we make use of the fact that VSELECT lowers
17075 // to PBLENDVB which selects bytes based just on the sign bit.
17076 if (Subtarget->hasSSE41()) {
17077 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
17078 V0 = DAG.getBitcast(ExtVT, V0);
17079 V1 = DAG.getBitcast(ExtVT, V1);
17080 Sel = DAG.getBitcast(ExtVT, Sel);
17081 return DAG.getBitcast(
17082 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
17084 // On pre-SSE41 targets we splat the sign bit - a negative value will
17085 // set all bits of the lanes to true and VSELECT uses that in
17086 // its OR(AND(V0,C),AND(V1,~C)) lowering.
17088 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
17089 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
17092 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
17093 if (Subtarget->hasSSE41()) {
17094 // On SSE41 targets we need to replicate the shift mask in both
17095 // bytes for PBLENDVB.
17098 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
17099 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
17101 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
17104 // r = VSELECT(r, shift(r, 8), a);
17105 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
17106 R = SignBitSelect(Amt, M, R);
17109 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17111 // r = VSELECT(r, shift(r, 4), a);
17112 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17113 R = SignBitSelect(Amt, M, R);
17116 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17118 // r = VSELECT(r, shift(r, 2), a);
17119 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17120 R = SignBitSelect(Amt, M, R);
17123 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17125 // return VSELECT(r, shift(r, 1), a);
17126 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17127 R = SignBitSelect(Amt, M, R);
17131 // Decompose 256-bit shifts into smaller 128-bit shifts.
17132 if (VT.is256BitVector()) {
17133 unsigned NumElems = VT.getVectorNumElements();
17134 MVT EltVT = VT.getVectorElementType();
17135 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17137 // Extract the two vectors
17138 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17139 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17141 // Recreate the shift amount vectors
17142 SDValue Amt1, Amt2;
17143 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17144 // Constant shift amount
17145 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17146 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17147 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17149 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17150 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17152 // Variable shift amount
17153 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17154 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17157 // Issue new vector shifts for the smaller types
17158 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17159 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17161 // Concatenate the result back
17162 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17168 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17169 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17170 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17171 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17172 // has only one use.
17173 SDNode *N = Op.getNode();
17174 SDValue LHS = N->getOperand(0);
17175 SDValue RHS = N->getOperand(1);
17176 unsigned BaseOp = 0;
17179 switch (Op.getOpcode()) {
17180 default: llvm_unreachable("Unknown ovf instruction!");
17182 // A subtract of one will be selected as a INC. Note that INC doesn't
17183 // set CF, so we can't do this for UADDO.
17184 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17186 BaseOp = X86ISD::INC;
17187 Cond = X86::COND_O;
17190 BaseOp = X86ISD::ADD;
17191 Cond = X86::COND_O;
17194 BaseOp = X86ISD::ADD;
17195 Cond = X86::COND_B;
17198 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17199 // set CF, so we can't do this for USUBO.
17200 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17202 BaseOp = X86ISD::DEC;
17203 Cond = X86::COND_O;
17206 BaseOp = X86ISD::SUB;
17207 Cond = X86::COND_O;
17210 BaseOp = X86ISD::SUB;
17211 Cond = X86::COND_B;
17214 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17215 Cond = X86::COND_O;
17217 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17218 if (N->getValueType(0) == MVT::i8) {
17219 BaseOp = X86ISD::UMUL8;
17220 Cond = X86::COND_O;
17223 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17225 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17228 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17229 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17230 SDValue(Sum.getNode(), 2));
17232 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17236 // Also sets EFLAGS.
17237 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17238 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17241 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17242 DAG.getConstant(Cond, DL, MVT::i32),
17243 SDValue(Sum.getNode(), 1));
17245 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17248 /// Returns true if the operand type is exactly twice the native width, and
17249 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17250 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17251 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17252 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17253 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17256 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17257 else if (OpWidth == 128)
17258 return Subtarget->hasCmpxchg16b();
17263 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17264 return needsCmpXchgNb(SI->getValueOperand()->getType());
17267 // Note: this turns large loads into lock cmpxchg8b/16b.
17268 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17269 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17270 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17271 return needsCmpXchgNb(PTy->getElementType());
17274 TargetLoweringBase::AtomicRMWExpansionKind
17275 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17276 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17277 const Type *MemType = AI->getType();
17279 // If the operand is too big, we must see if cmpxchg8/16b is available
17280 // and default to library calls otherwise.
17281 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17282 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17283 : AtomicRMWExpansionKind::None;
17286 AtomicRMWInst::BinOp Op = AI->getOperation();
17289 llvm_unreachable("Unknown atomic operation");
17290 case AtomicRMWInst::Xchg:
17291 case AtomicRMWInst::Add:
17292 case AtomicRMWInst::Sub:
17293 // It's better to use xadd, xsub or xchg for these in all cases.
17294 return AtomicRMWExpansionKind::None;
17295 case AtomicRMWInst::Or:
17296 case AtomicRMWInst::And:
17297 case AtomicRMWInst::Xor:
17298 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17299 // prefix to a normal instruction for these operations.
17300 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17301 : AtomicRMWExpansionKind::None;
17302 case AtomicRMWInst::Nand:
17303 case AtomicRMWInst::Max:
17304 case AtomicRMWInst::Min:
17305 case AtomicRMWInst::UMax:
17306 case AtomicRMWInst::UMin:
17307 // These always require a non-trivial set of data operations on x86. We must
17308 // use a cmpxchg loop.
17309 return AtomicRMWExpansionKind::CmpXChg;
17313 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17314 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17315 // no-sse2). There isn't any reason to disable it if the target processor
17317 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17321 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17322 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17323 const Type *MemType = AI->getType();
17324 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17325 // there is no benefit in turning such RMWs into loads, and it is actually
17326 // harmful as it introduces a mfence.
17327 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17330 auto Builder = IRBuilder<>(AI);
17331 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17332 auto SynchScope = AI->getSynchScope();
17333 // We must restrict the ordering to avoid generating loads with Release or
17334 // ReleaseAcquire orderings.
17335 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17336 auto Ptr = AI->getPointerOperand();
17338 // Before the load we need a fence. Here is an example lifted from
17339 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17342 // x.store(1, relaxed);
17343 // r1 = y.fetch_add(0, release);
17345 // y.fetch_add(42, acquire);
17346 // r2 = x.load(relaxed);
17347 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17348 // lowered to just a load without a fence. A mfence flushes the store buffer,
17349 // making the optimization clearly correct.
17350 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17351 // otherwise, we might be able to be more agressive on relaxed idempotent
17352 // rmw. In practice, they do not look useful, so we don't try to be
17353 // especially clever.
17354 if (SynchScope == SingleThread)
17355 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17356 // the IR level, so we must wrap it in an intrinsic.
17359 if (!hasMFENCE(*Subtarget))
17360 // FIXME: it might make sense to use a locked operation here but on a
17361 // different cache-line to prevent cache-line bouncing. In practice it
17362 // is probably a small win, and x86 processors without mfence are rare
17363 // enough that we do not bother.
17367 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17368 Builder.CreateCall(MFence, {});
17370 // Finally we can emit the atomic load.
17371 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17372 AI->getType()->getPrimitiveSizeInBits());
17373 Loaded->setAtomic(Order, SynchScope);
17374 AI->replaceAllUsesWith(Loaded);
17375 AI->eraseFromParent();
17379 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17380 SelectionDAG &DAG) {
17382 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17383 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17384 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17385 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17387 // The only fence that needs an instruction is a sequentially-consistent
17388 // cross-thread fence.
17389 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17390 if (hasMFENCE(*Subtarget))
17391 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17393 SDValue Chain = Op.getOperand(0);
17394 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17396 DAG.getRegister(X86::ESP, MVT::i32), // Base
17397 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17398 DAG.getRegister(0, MVT::i32), // Index
17399 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17400 DAG.getRegister(0, MVT::i32), // Segment.
17404 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17405 return SDValue(Res, 0);
17408 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17409 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17412 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17413 SelectionDAG &DAG) {
17414 MVT T = Op.getSimpleValueType();
17418 switch(T.SimpleTy) {
17419 default: llvm_unreachable("Invalid value type!");
17420 case MVT::i8: Reg = X86::AL; size = 1; break;
17421 case MVT::i16: Reg = X86::AX; size = 2; break;
17422 case MVT::i32: Reg = X86::EAX; size = 4; break;
17424 assert(Subtarget->is64Bit() && "Node not type legal!");
17425 Reg = X86::RAX; size = 8;
17428 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17429 Op.getOperand(2), SDValue());
17430 SDValue Ops[] = { cpIn.getValue(0),
17433 DAG.getTargetConstant(size, DL, MVT::i8),
17434 cpIn.getValue(1) };
17435 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17436 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17437 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17441 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17442 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17443 MVT::i32, cpOut.getValue(2));
17444 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17445 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17448 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17449 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17450 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17454 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17455 SelectionDAG &DAG) {
17456 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17457 MVT DstVT = Op.getSimpleValueType();
17459 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17460 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17461 if (DstVT != MVT::f64)
17462 // This conversion needs to be expanded.
17465 SDValue InVec = Op->getOperand(0);
17467 unsigned NumElts = SrcVT.getVectorNumElements();
17468 EVT SVT = SrcVT.getVectorElementType();
17470 // Widen the vector in input in the case of MVT::v2i32.
17471 // Example: from MVT::v2i32 to MVT::v4i32.
17472 SmallVector<SDValue, 16> Elts;
17473 for (unsigned i = 0, e = NumElts; i != e; ++i)
17474 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17475 DAG.getIntPtrConstant(i, dl)));
17477 // Explicitly mark the extra elements as Undef.
17478 Elts.append(NumElts, DAG.getUNDEF(SVT));
17480 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17481 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17482 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
17483 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17484 DAG.getIntPtrConstant(0, dl));
17487 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17488 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17489 assert((DstVT == MVT::i64 ||
17490 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17491 "Unexpected custom BITCAST");
17492 // i64 <=> MMX conversions are Legal.
17493 if (SrcVT==MVT::i64 && DstVT.isVector())
17495 if (DstVT==MVT::i64 && SrcVT.isVector())
17497 // MMX <=> MMX conversions are Legal.
17498 if (SrcVT.isVector() && DstVT.isVector())
17500 // All other conversions need to be expanded.
17504 /// Compute the horizontal sum of bytes in V for the elements of VT.
17506 /// Requires V to be a byte vector and VT to be an integer vector type with
17507 /// wider elements than V's type. The width of the elements of VT determines
17508 /// how many bytes of V are summed horizontally to produce each element of the
17510 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
17511 const X86Subtarget *Subtarget,
17512 SelectionDAG &DAG) {
17514 MVT ByteVecVT = V.getSimpleValueType();
17515 MVT EltVT = VT.getVectorElementType();
17516 int NumElts = VT.getVectorNumElements();
17517 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
17518 "Expected value to have byte element type.");
17519 assert(EltVT != MVT::i8 &&
17520 "Horizontal byte sum only makes sense for wider elements!");
17521 unsigned VecSize = VT.getSizeInBits();
17522 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
17524 // PSADBW instruction horizontally add all bytes and leave the result in i64
17525 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17526 if (EltVT == MVT::i64) {
17527 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17528 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
17529 return DAG.getBitcast(VT, V);
17532 if (EltVT == MVT::i32) {
17533 // We unpack the low half and high half into i32s interleaved with zeros so
17534 // that we can use PSADBW to horizontally sum them. The most useful part of
17535 // this is that it lines up the results of two PSADBW instructions to be
17536 // two v2i64 vectors which concatenated are the 4 population counts. We can
17537 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17538 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17539 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
17540 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
17542 // Do the horizontal sums into two v2i64s.
17543 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17544 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17545 DAG.getBitcast(ByteVecVT, Low), Zeros);
17546 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17547 DAG.getBitcast(ByteVecVT, High), Zeros);
17549 // Merge them together.
17550 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
17551 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
17552 DAG.getBitcast(ShortVecVT, Low),
17553 DAG.getBitcast(ShortVecVT, High));
17555 return DAG.getBitcast(VT, V);
17558 // The only element type left is i16.
17559 assert(EltVT == MVT::i16 && "Unknown how to handle type");
17561 // To obtain pop count for each i16 element starting from the pop count for
17562 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
17563 // right by 8. It is important to shift as i16s as i8 vector shift isn't
17564 // directly supported.
17565 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
17566 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
17567 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17568 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
17569 DAG.getBitcast(ByteVecVT, V));
17570 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17573 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
17574 const X86Subtarget *Subtarget,
17575 SelectionDAG &DAG) {
17576 MVT VT = Op.getSimpleValueType();
17577 MVT EltVT = VT.getVectorElementType();
17578 unsigned VecSize = VT.getSizeInBits();
17580 // Implement a lookup table in register by using an algorithm based on:
17581 // http://wm.ite.pl/articles/sse-popcount.html
17583 // The general idea is that every lower byte nibble in the input vector is an
17584 // index into a in-register pre-computed pop count table. We then split up the
17585 // input vector in two new ones: (1) a vector with only the shifted-right
17586 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
17587 // masked out higher ones) for each byte. PSHUB is used separately with both
17588 // to index the in-register table. Next, both are added and the result is a
17589 // i8 vector where each element contains the pop count for input byte.
17591 // To obtain the pop count for elements != i8, we follow up with the same
17592 // approach and use additional tricks as described below.
17594 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
17595 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
17596 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
17597 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
17599 int NumByteElts = VecSize / 8;
17600 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
17601 SDValue In = DAG.getBitcast(ByteVecVT, Op);
17602 SmallVector<SDValue, 16> LUTVec;
17603 for (int i = 0; i < NumByteElts; ++i)
17604 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
17605 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
17606 SmallVector<SDValue, 16> Mask0F(NumByteElts,
17607 DAG.getConstant(0x0F, DL, MVT::i8));
17608 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
17611 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
17612 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
17613 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
17616 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
17618 // The input vector is used as the shuffle mask that index elements into the
17619 // LUT. After counting low and high nibbles, add the vector to obtain the
17620 // final pop count per i8 element.
17621 SDValue HighPopCnt =
17622 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
17623 SDValue LowPopCnt =
17624 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
17625 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
17627 if (EltVT == MVT::i8)
17630 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
17633 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
17634 const X86Subtarget *Subtarget,
17635 SelectionDAG &DAG) {
17636 MVT VT = Op.getSimpleValueType();
17637 assert(VT.is128BitVector() &&
17638 "Only 128-bit vector bitmath lowering supported.");
17640 int VecSize = VT.getSizeInBits();
17641 MVT EltVT = VT.getVectorElementType();
17642 int Len = EltVT.getSizeInBits();
17644 // This is the vectorized version of the "best" algorithm from
17645 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
17646 // with a minor tweak to use a series of adds + shifts instead of vector
17647 // multiplications. Implemented for all integer vector types. We only use
17648 // this when we don't have SSSE3 which allows a LUT-based lowering that is
17649 // much faster, even faster than using native popcnt instructions.
17651 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
17652 MVT VT = V.getSimpleValueType();
17653 SmallVector<SDValue, 32> Shifters(
17654 VT.getVectorNumElements(),
17655 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
17656 return DAG.getNode(OpCode, DL, VT, V,
17657 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
17659 auto GetMask = [&](SDValue V, APInt Mask) {
17660 MVT VT = V.getSimpleValueType();
17661 SmallVector<SDValue, 32> Masks(
17662 VT.getVectorNumElements(),
17663 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
17664 return DAG.getNode(ISD::AND, DL, VT, V,
17665 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
17668 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
17669 // x86, so set the SRL type to have elements at least i16 wide. This is
17670 // correct because all of our SRLs are followed immediately by a mask anyways
17671 // that handles any bits that sneak into the high bits of the byte elements.
17672 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
17676 // v = v - ((v >> 1) & 0x55555555...)
17678 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
17679 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
17680 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
17682 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
17683 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
17684 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
17685 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
17686 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
17688 // v = (v + (v >> 4)) & 0x0F0F0F0F...
17689 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
17690 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
17691 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
17693 // At this point, V contains the byte-wise population count, and we are
17694 // merely doing a horizontal sum if necessary to get the wider element
17696 if (EltVT == MVT::i8)
17699 return LowerHorizontalByteSum(
17700 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
17704 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17705 SelectionDAG &DAG) {
17706 MVT VT = Op.getSimpleValueType();
17707 // FIXME: Need to add AVX-512 support here!
17708 assert((VT.is256BitVector() || VT.is128BitVector()) &&
17709 "Unknown CTPOP type to handle");
17710 SDLoc DL(Op.getNode());
17711 SDValue Op0 = Op.getOperand(0);
17713 if (!Subtarget->hasSSSE3()) {
17714 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
17715 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
17716 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
17719 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
17720 unsigned NumElems = VT.getVectorNumElements();
17722 // Extract each 128-bit vector, compute pop count and concat the result.
17723 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
17724 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
17726 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
17727 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
17728 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
17731 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
17734 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
17735 SelectionDAG &DAG) {
17736 assert(Op.getValueType().isVector() &&
17737 "We only do custom lowering for vector population count.");
17738 return LowerVectorCTPOP(Op, Subtarget, DAG);
17741 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
17742 SDNode *Node = Op.getNode();
17744 EVT T = Node->getValueType(0);
17745 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
17746 DAG.getConstant(0, dl, T), Node->getOperand(2));
17747 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
17748 cast<AtomicSDNode>(Node)->getMemoryVT(),
17749 Node->getOperand(0),
17750 Node->getOperand(1), negOp,
17751 cast<AtomicSDNode>(Node)->getMemOperand(),
17752 cast<AtomicSDNode>(Node)->getOrdering(),
17753 cast<AtomicSDNode>(Node)->getSynchScope());
17756 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
17757 SDNode *Node = Op.getNode();
17759 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
17761 // Convert seq_cst store -> xchg
17762 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
17763 // FIXME: On 32-bit, store -> fist or movq would be more efficient
17764 // (The only way to get a 16-byte store is cmpxchg16b)
17765 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
17766 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
17767 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17768 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
17769 cast<AtomicSDNode>(Node)->getMemoryVT(),
17770 Node->getOperand(0),
17771 Node->getOperand(1), Node->getOperand(2),
17772 cast<AtomicSDNode>(Node)->getMemOperand(),
17773 cast<AtomicSDNode>(Node)->getOrdering(),
17774 cast<AtomicSDNode>(Node)->getSynchScope());
17775 return Swap.getValue(1);
17777 // Other atomic stores have a simple pattern.
17781 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
17782 EVT VT = Op.getNode()->getSimpleValueType(0);
17784 // Let legalize expand this if it isn't a legal type yet.
17785 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17788 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
17791 bool ExtraOp = false;
17792 switch (Op.getOpcode()) {
17793 default: llvm_unreachable("Invalid code");
17794 case ISD::ADDC: Opc = X86ISD::ADD; break;
17795 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
17796 case ISD::SUBC: Opc = X86ISD::SUB; break;
17797 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17801 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17803 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
17804 Op.getOperand(1), Op.getOperand(2));
17807 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
17808 SelectionDAG &DAG) {
17809 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
17811 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
17812 // which returns the values as { float, float } (in XMM0) or
17813 // { double, double } (which is returned in XMM0, XMM1).
17815 SDValue Arg = Op.getOperand(0);
17816 EVT ArgVT = Arg.getValueType();
17817 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
17819 TargetLowering::ArgListTy Args;
17820 TargetLowering::ArgListEntry Entry;
17824 Entry.isSExt = false;
17825 Entry.isZExt = false;
17826 Args.push_back(Entry);
17828 bool isF64 = ArgVT == MVT::f64;
17829 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
17830 // the small struct {f32, f32} is returned in (eax, edx). For f64,
17831 // the results are returned via SRet in memory.
17832 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
17833 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17834 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
17836 Type *RetTy = isF64
17837 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
17838 : (Type*)VectorType::get(ArgTy, 4);
17840 TargetLowering::CallLoweringInfo CLI(DAG);
17841 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
17842 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
17844 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
17847 // Returned in xmm0 and xmm1.
17848 return CallResult.first;
17850 // Returned in bits 0:31 and 32:64 xmm0.
17851 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17852 CallResult.first, DAG.getIntPtrConstant(0, dl));
17853 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
17854 CallResult.first, DAG.getIntPtrConstant(1, dl));
17855 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
17856 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
17859 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
17860 SelectionDAG &DAG) {
17861 assert(Subtarget->hasAVX512() &&
17862 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17864 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
17865 EVT VT = N->getValue().getValueType();
17866 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
17869 // X86 scatter kills mask register, so its type should be added to
17870 // the list of return values
17871 if (N->getNumValues() == 1) {
17872 SDValue Index = N->getIndex();
17873 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17874 !Index.getValueType().is512BitVector())
17875 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17877 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
17878 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17879 N->getOperand(3), Index };
17881 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
17882 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
17883 return SDValue(NewScatter.getNode(), 0);
17888 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
17889 SelectionDAG &DAG) {
17890 assert(Subtarget->hasAVX512() &&
17891 "MGATHER/MSCATTER are supported on AVX-512 arch only");
17893 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
17894 EVT VT = Op.getValueType();
17895 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
17898 SDValue Index = N->getIndex();
17899 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
17900 !Index.getValueType().is512BitVector()) {
17901 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
17902 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
17903 N->getOperand(3), Index };
17904 DAG.UpdateNodeOperands(N, Ops);
17909 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
17910 SelectionDAG &DAG) const {
17911 // TODO: Eventually, the lowering of these nodes should be informed by or
17912 // deferred to the GC strategy for the function in which they appear. For
17913 // now, however, they must be lowered to something. Since they are logically
17914 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17915 // require special handling for these nodes), lower them as literal NOOPs for
17917 SmallVector<SDValue, 2> Ops;
17919 Ops.push_back(Op.getOperand(0));
17920 if (Op->getGluedNode())
17921 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17924 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17925 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17930 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
17931 SelectionDAG &DAG) const {
17932 // TODO: Eventually, the lowering of these nodes should be informed by or
17933 // deferred to the GC strategy for the function in which they appear. For
17934 // now, however, they must be lowered to something. Since they are logically
17935 // no-ops in the case of a null GC strategy (or a GC strategy which does not
17936 // require special handling for these nodes), lower them as literal NOOPs for
17938 SmallVector<SDValue, 2> Ops;
17940 Ops.push_back(Op.getOperand(0));
17941 if (Op->getGluedNode())
17942 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
17945 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
17946 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
17951 /// LowerOperation - Provide custom lowering hooks for some operations.
17953 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
17954 switch (Op.getOpcode()) {
17955 default: llvm_unreachable("Should not custom lower this!");
17956 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
17957 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
17958 return LowerCMP_SWAP(Op, Subtarget, DAG);
17959 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
17960 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
17961 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
17962 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
17963 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
17964 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
17965 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
17966 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
17967 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
17968 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
17969 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
17970 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
17971 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
17972 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
17973 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
17974 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
17975 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
17976 case ISD::SHL_PARTS:
17977 case ISD::SRA_PARTS:
17978 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
17979 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
17980 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
17981 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
17982 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
17983 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
17984 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
17985 case ISD::SIGN_EXTEND_VECTOR_INREG:
17986 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
17987 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
17988 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
17989 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
17990 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
17992 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
17993 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
17994 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
17995 case ISD::SETCC: return LowerSETCC(Op, DAG);
17996 case ISD::SELECT: return LowerSELECT(Op, DAG);
17997 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
17998 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
17999 case ISD::VASTART: return LowerVASTART(Op, DAG);
18000 case ISD::VAARG: return LowerVAARG(Op, DAG);
18001 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18002 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18003 case ISD::INTRINSIC_VOID:
18004 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18005 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18006 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18007 case ISD::FRAME_TO_ARGS_OFFSET:
18008 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18009 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18010 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18011 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18012 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18013 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18014 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18015 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18016 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18017 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18018 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18019 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18020 case ISD::UMUL_LOHI:
18021 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18024 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18030 case ISD::UMULO: return LowerXALUO(Op, DAG);
18031 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18032 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18036 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18037 case ISD::ADD: return LowerADD(Op, DAG);
18038 case ISD::SUB: return LowerSUB(Op, DAG);
18039 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18040 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
18041 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
18042 case ISD::GC_TRANSITION_START:
18043 return LowerGC_TRANSITION_START(Op, DAG);
18044 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
18048 /// ReplaceNodeResults - Replace a node with an illegal result type
18049 /// with a new node built out of custom code.
18050 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18051 SmallVectorImpl<SDValue>&Results,
18052 SelectionDAG &DAG) const {
18054 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18055 switch (N->getOpcode()) {
18057 llvm_unreachable("Do not know how to custom type legalize this operation!");
18058 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
18059 case X86ISD::FMINC:
18061 case X86ISD::FMAXC:
18062 case X86ISD::FMAX: {
18063 EVT VT = N->getValueType(0);
18064 if (VT != MVT::v2f32)
18065 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
18066 SDValue UNDEF = DAG.getUNDEF(VT);
18067 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18068 N->getOperand(0), UNDEF);
18069 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18070 N->getOperand(1), UNDEF);
18071 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
18074 case ISD::SIGN_EXTEND_INREG:
18079 // We don't want to expand or promote these.
18086 case ISD::UDIVREM: {
18087 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18088 Results.push_back(V);
18091 case ISD::FP_TO_SINT:
18092 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18093 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18094 if (N->getOperand(0).getValueType() == MVT::f16)
18097 case ISD::FP_TO_UINT: {
18098 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18100 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18103 std::pair<SDValue,SDValue> Vals =
18104 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18105 SDValue FIST = Vals.first, StackSlot = Vals.second;
18106 if (FIST.getNode()) {
18107 EVT VT = N->getValueType(0);
18108 // Return a load from the stack slot.
18109 if (StackSlot.getNode())
18110 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18111 MachinePointerInfo(),
18112 false, false, false, 0));
18114 Results.push_back(FIST);
18118 case ISD::UINT_TO_FP: {
18119 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18120 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18121 N->getValueType(0) != MVT::v2f32)
18123 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18125 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18127 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18128 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18129 DAG.getBitcast(MVT::v2i64, VBias));
18130 Or = DAG.getBitcast(MVT::v2f64, Or);
18131 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18132 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18135 case ISD::FP_ROUND: {
18136 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18138 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18139 Results.push_back(V);
18142 case ISD::FP_EXTEND: {
18143 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18144 // No other ValueType for FP_EXTEND should reach this point.
18145 assert(N->getValueType(0) == MVT::v2f32 &&
18146 "Do not know how to legalize this Node");
18149 case ISD::INTRINSIC_W_CHAIN: {
18150 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18152 default : llvm_unreachable("Do not know how to custom type "
18153 "legalize this intrinsic operation!");
18154 case Intrinsic::x86_rdtsc:
18155 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18157 case Intrinsic::x86_rdtscp:
18158 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18160 case Intrinsic::x86_rdpmc:
18161 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18164 case ISD::READCYCLECOUNTER: {
18165 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18168 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18169 EVT T = N->getValueType(0);
18170 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18171 bool Regs64bit = T == MVT::i128;
18172 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18173 SDValue cpInL, cpInH;
18174 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18175 DAG.getConstant(0, dl, HalfT));
18176 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18177 DAG.getConstant(1, dl, HalfT));
18178 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18179 Regs64bit ? X86::RAX : X86::EAX,
18181 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18182 Regs64bit ? X86::RDX : X86::EDX,
18183 cpInH, cpInL.getValue(1));
18184 SDValue swapInL, swapInH;
18185 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18186 DAG.getConstant(0, dl, HalfT));
18187 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18188 DAG.getConstant(1, dl, HalfT));
18189 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18190 Regs64bit ? X86::RBX : X86::EBX,
18191 swapInL, cpInH.getValue(1));
18192 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18193 Regs64bit ? X86::RCX : X86::ECX,
18194 swapInH, swapInL.getValue(1));
18195 SDValue Ops[] = { swapInH.getValue(0),
18197 swapInH.getValue(1) };
18198 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18199 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18200 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18201 X86ISD::LCMPXCHG8_DAG;
18202 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18203 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18204 Regs64bit ? X86::RAX : X86::EAX,
18205 HalfT, Result.getValue(1));
18206 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18207 Regs64bit ? X86::RDX : X86::EDX,
18208 HalfT, cpOutL.getValue(2));
18209 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18211 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18212 MVT::i32, cpOutH.getValue(2));
18214 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18215 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18216 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18218 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18219 Results.push_back(Success);
18220 Results.push_back(EFLAGS.getValue(1));
18223 case ISD::ATOMIC_SWAP:
18224 case ISD::ATOMIC_LOAD_ADD:
18225 case ISD::ATOMIC_LOAD_SUB:
18226 case ISD::ATOMIC_LOAD_AND:
18227 case ISD::ATOMIC_LOAD_OR:
18228 case ISD::ATOMIC_LOAD_XOR:
18229 case ISD::ATOMIC_LOAD_NAND:
18230 case ISD::ATOMIC_LOAD_MIN:
18231 case ISD::ATOMIC_LOAD_MAX:
18232 case ISD::ATOMIC_LOAD_UMIN:
18233 case ISD::ATOMIC_LOAD_UMAX:
18234 case ISD::ATOMIC_LOAD: {
18235 // Delegate to generic TypeLegalization. Situations we can really handle
18236 // should have already been dealt with by AtomicExpandPass.cpp.
18239 case ISD::BITCAST: {
18240 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18241 EVT DstVT = N->getValueType(0);
18242 EVT SrcVT = N->getOperand(0)->getValueType(0);
18244 if (SrcVT != MVT::f64 ||
18245 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18248 unsigned NumElts = DstVT.getVectorNumElements();
18249 EVT SVT = DstVT.getVectorElementType();
18250 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18251 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18252 MVT::v2f64, N->getOperand(0));
18253 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
18255 if (ExperimentalVectorWideningLegalization) {
18256 // If we are legalizing vectors by widening, we already have the desired
18257 // legal vector type, just return it.
18258 Results.push_back(ToVecInt);
18262 SmallVector<SDValue, 8> Elts;
18263 for (unsigned i = 0, e = NumElts; i != e; ++i)
18264 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18265 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18267 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18272 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18273 switch ((X86ISD::NodeType)Opcode) {
18274 case X86ISD::FIRST_NUMBER: break;
18275 case X86ISD::BSF: return "X86ISD::BSF";
18276 case X86ISD::BSR: return "X86ISD::BSR";
18277 case X86ISD::SHLD: return "X86ISD::SHLD";
18278 case X86ISD::SHRD: return "X86ISD::SHRD";
18279 case X86ISD::FAND: return "X86ISD::FAND";
18280 case X86ISD::FANDN: return "X86ISD::FANDN";
18281 case X86ISD::FOR: return "X86ISD::FOR";
18282 case X86ISD::FXOR: return "X86ISD::FXOR";
18283 case X86ISD::FILD: return "X86ISD::FILD";
18284 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18285 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18286 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18287 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18288 case X86ISD::FLD: return "X86ISD::FLD";
18289 case X86ISD::FST: return "X86ISD::FST";
18290 case X86ISD::CALL: return "X86ISD::CALL";
18291 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18292 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18293 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18294 case X86ISD::BT: return "X86ISD::BT";
18295 case X86ISD::CMP: return "X86ISD::CMP";
18296 case X86ISD::COMI: return "X86ISD::COMI";
18297 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18298 case X86ISD::CMPM: return "X86ISD::CMPM";
18299 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18300 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18301 case X86ISD::SETCC: return "X86ISD::SETCC";
18302 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18303 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18304 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18305 case X86ISD::CMOV: return "X86ISD::CMOV";
18306 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18307 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18308 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18309 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18310 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18311 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18312 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18313 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18314 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18315 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18316 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18317 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18318 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18319 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18320 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18321 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18322 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18323 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18324 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18325 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18326 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18327 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18328 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18329 case X86ISD::HADD: return "X86ISD::HADD";
18330 case X86ISD::HSUB: return "X86ISD::HSUB";
18331 case X86ISD::FHADD: return "X86ISD::FHADD";
18332 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18333 case X86ISD::UMAX: return "X86ISD::UMAX";
18334 case X86ISD::UMIN: return "X86ISD::UMIN";
18335 case X86ISD::SMAX: return "X86ISD::SMAX";
18336 case X86ISD::SMIN: return "X86ISD::SMIN";
18337 case X86ISD::ABS: return "X86ISD::ABS";
18338 case X86ISD::FMAX: return "X86ISD::FMAX";
18339 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18340 case X86ISD::FMIN: return "X86ISD::FMIN";
18341 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18342 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18343 case X86ISD::FMINC: return "X86ISD::FMINC";
18344 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18345 case X86ISD::FRCP: return "X86ISD::FRCP";
18346 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18347 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18348 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18349 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18350 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18351 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18352 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18353 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18354 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18355 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18356 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18357 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18358 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18359 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18360 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18361 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18362 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18363 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18364 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18365 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18366 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18367 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
18368 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18369 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18370 case X86ISD::VSHL: return "X86ISD::VSHL";
18371 case X86ISD::VSRL: return "X86ISD::VSRL";
18372 case X86ISD::VSRA: return "X86ISD::VSRA";
18373 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18374 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18375 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18376 case X86ISD::CMPP: return "X86ISD::CMPP";
18377 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18378 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18379 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18380 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18381 case X86ISD::ADD: return "X86ISD::ADD";
18382 case X86ISD::SUB: return "X86ISD::SUB";
18383 case X86ISD::ADC: return "X86ISD::ADC";
18384 case X86ISD::SBB: return "X86ISD::SBB";
18385 case X86ISD::SMUL: return "X86ISD::SMUL";
18386 case X86ISD::UMUL: return "X86ISD::UMUL";
18387 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18388 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18389 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18390 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18391 case X86ISD::INC: return "X86ISD::INC";
18392 case X86ISD::DEC: return "X86ISD::DEC";
18393 case X86ISD::OR: return "X86ISD::OR";
18394 case X86ISD::XOR: return "X86ISD::XOR";
18395 case X86ISD::AND: return "X86ISD::AND";
18396 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18397 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18398 case X86ISD::PTEST: return "X86ISD::PTEST";
18399 case X86ISD::TESTP: return "X86ISD::TESTP";
18400 case X86ISD::TESTM: return "X86ISD::TESTM";
18401 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18402 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18403 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18404 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18405 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18406 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18407 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18408 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18409 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18410 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18411 case X86ISD::SHUF128: return "X86ISD::SHUF128";
18412 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18413 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18414 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18415 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18416 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18417 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18418 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18419 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18420 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18421 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18422 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18423 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18424 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18425 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18426 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18427 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18428 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18429 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18430 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18431 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18432 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18433 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18434 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
18435 case X86ISD::VRANGE: return "X86ISD::VRANGE";
18436 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18437 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18438 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18439 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18440 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18441 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18442 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18443 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18444 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18445 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18446 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18447 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18448 case X86ISD::SAHF: return "X86ISD::SAHF";
18449 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18450 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18451 case X86ISD::FMADD: return "X86ISD::FMADD";
18452 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18453 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18454 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18455 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18456 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18457 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18458 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18459 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18460 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18461 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18462 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18463 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18464 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18465 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18466 case X86ISD::XTEST: return "X86ISD::XTEST";
18467 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18468 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18469 case X86ISD::SELECT: return "X86ISD::SELECT";
18470 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18471 case X86ISD::RCP28: return "X86ISD::RCP28";
18472 case X86ISD::EXP2: return "X86ISD::EXP2";
18473 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18474 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18475 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18476 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18477 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18478 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
18479 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
18480 case X86ISD::ADDS: return "X86ISD::ADDS";
18481 case X86ISD::SUBS: return "X86ISD::SUBS";
18482 case X86ISD::AVG: return "X86ISD::AVG";
18483 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
18484 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
18489 // isLegalAddressingMode - Return true if the addressing mode represented
18490 // by AM is legal for this target, for a load/store of the specified type.
18491 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18493 unsigned AS) const {
18494 // X86 supports extremely general addressing modes.
18495 CodeModel::Model M = getTargetMachine().getCodeModel();
18496 Reloc::Model R = getTargetMachine().getRelocationModel();
18498 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18499 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18504 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18506 // If a reference to this global requires an extra load, we can't fold it.
18507 if (isGlobalStubReference(GVFlags))
18510 // If BaseGV requires a register for the PIC base, we cannot also have a
18511 // BaseReg specified.
18512 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18515 // If lower 4G is not available, then we must use rip-relative addressing.
18516 if ((M != CodeModel::Small || R != Reloc::Static) &&
18517 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18521 switch (AM.Scale) {
18527 // These scales always work.
18532 // These scales are formed with basereg+scalereg. Only accept if there is
18537 default: // Other stuff never works.
18544 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18545 unsigned Bits = Ty->getScalarSizeInBits();
18547 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18548 // particularly cheaper than those without.
18552 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18553 // variable shifts just as cheap as scalar ones.
18554 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18557 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18558 // fully general vector.
18562 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18563 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18565 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18566 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18567 return NumBits1 > NumBits2;
18570 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18571 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18574 if (!isTypeLegal(EVT::getEVT(Ty1)))
18577 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18579 // Assuming the caller doesn't have a zeroext or signext return parameter,
18580 // truncation all the way down to i1 is valid.
18584 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18585 return isInt<32>(Imm);
18588 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18589 // Can also use sub to handle negated immediates.
18590 return isInt<32>(Imm);
18593 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18594 if (!VT1.isInteger() || !VT2.isInteger())
18596 unsigned NumBits1 = VT1.getSizeInBits();
18597 unsigned NumBits2 = VT2.getSizeInBits();
18598 return NumBits1 > NumBits2;
18601 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
18602 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18603 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
18606 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
18607 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
18608 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
18611 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
18612 EVT VT1 = Val.getValueType();
18613 if (isZExtFree(VT1, VT2))
18616 if (Val.getOpcode() != ISD::LOAD)
18619 if (!VT1.isSimple() || !VT1.isInteger() ||
18620 !VT2.isSimple() || !VT2.isInteger())
18623 switch (VT1.getSimpleVT().SimpleTy) {
18628 // X86 has 8, 16, and 32-bit zero-extending loads.
18635 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
18638 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
18639 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
18642 VT = VT.getScalarType();
18644 if (!VT.isSimple())
18647 switch (VT.getSimpleVT().SimpleTy) {
18658 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
18659 // i16 instructions are longer (0x66 prefix) and potentially slower.
18660 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
18663 /// isShuffleMaskLegal - Targets can use this to indicate that they only
18664 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
18665 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
18666 /// are assumed to be legal.
18668 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
18670 if (!VT.isSimple())
18673 // Not for i1 vectors
18674 if (VT.getScalarType() == MVT::i1)
18677 // Very little shuffling can be done for 64-bit vectors right now.
18678 if (VT.getSizeInBits() == 64)
18681 // We only care that the types being shuffled are legal. The lowering can
18682 // handle any possible shuffle mask that results.
18683 return isTypeLegal(VT.getSimpleVT());
18687 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
18689 // Just delegate to the generic legality, clear masks aren't special.
18690 return isShuffleMaskLegal(Mask, VT);
18693 //===----------------------------------------------------------------------===//
18694 // X86 Scheduler Hooks
18695 //===----------------------------------------------------------------------===//
18697 /// Utility function to emit xbegin specifying the start of an RTM region.
18698 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
18699 const TargetInstrInfo *TII) {
18700 DebugLoc DL = MI->getDebugLoc();
18702 const BasicBlock *BB = MBB->getBasicBlock();
18703 MachineFunction::iterator I = MBB;
18706 // For the v = xbegin(), we generate
18717 MachineBasicBlock *thisMBB = MBB;
18718 MachineFunction *MF = MBB->getParent();
18719 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
18720 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
18721 MF->insert(I, mainMBB);
18722 MF->insert(I, sinkMBB);
18724 // Transfer the remainder of BB and its successor edges to sinkMBB.
18725 sinkMBB->splice(sinkMBB->begin(), MBB,
18726 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
18727 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
18731 // # fallthrough to mainMBB
18732 // # abortion to sinkMBB
18733 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
18734 thisMBB->addSuccessor(mainMBB);
18735 thisMBB->addSuccessor(sinkMBB);
18739 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
18740 mainMBB->addSuccessor(sinkMBB);
18743 // EAX is live into the sinkMBB
18744 sinkMBB->addLiveIn(X86::EAX);
18745 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
18746 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18749 MI->eraseFromParent();
18753 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
18754 // or XMM0_V32I8 in AVX all of this code can be replaced with that
18755 // in the .td file.
18756 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
18757 const TargetInstrInfo *TII) {
18759 switch (MI->getOpcode()) {
18760 default: llvm_unreachable("illegal opcode!");
18761 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
18762 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
18763 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
18764 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
18765 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
18766 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
18767 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
18768 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
18771 DebugLoc dl = MI->getDebugLoc();
18772 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18774 unsigned NumArgs = MI->getNumOperands();
18775 for (unsigned i = 1; i < NumArgs; ++i) {
18776 MachineOperand &Op = MI->getOperand(i);
18777 if (!(Op.isReg() && Op.isImplicit()))
18778 MIB.addOperand(Op);
18780 if (MI->hasOneMemOperand())
18781 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18783 BuildMI(*BB, MI, dl,
18784 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18785 .addReg(X86::XMM0);
18787 MI->eraseFromParent();
18791 // FIXME: Custom handling because TableGen doesn't support multiple implicit
18792 // defs in an instruction pattern
18793 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
18794 const TargetInstrInfo *TII) {
18796 switch (MI->getOpcode()) {
18797 default: llvm_unreachable("illegal opcode!");
18798 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
18799 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
18800 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
18801 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
18802 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
18803 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
18804 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
18805 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
18808 DebugLoc dl = MI->getDebugLoc();
18809 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
18811 unsigned NumArgs = MI->getNumOperands(); // remove the results
18812 for (unsigned i = 1; i < NumArgs; ++i) {
18813 MachineOperand &Op = MI->getOperand(i);
18814 if (!(Op.isReg() && Op.isImplicit()))
18815 MIB.addOperand(Op);
18817 if (MI->hasOneMemOperand())
18818 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
18820 BuildMI(*BB, MI, dl,
18821 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
18824 MI->eraseFromParent();
18828 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
18829 const X86Subtarget *Subtarget) {
18830 DebugLoc dl = MI->getDebugLoc();
18831 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18832 // Address into RAX/EAX, other two args into ECX, EDX.
18833 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
18834 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
18835 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
18836 for (int i = 0; i < X86::AddrNumOperands; ++i)
18837 MIB.addOperand(MI->getOperand(i));
18839 unsigned ValOps = X86::AddrNumOperands;
18840 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
18841 .addReg(MI->getOperand(ValOps).getReg());
18842 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
18843 .addReg(MI->getOperand(ValOps+1).getReg());
18845 // The instruction doesn't actually take any operands though.
18846 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
18848 MI->eraseFromParent(); // The pseudo is gone now.
18852 MachineBasicBlock *
18853 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
18854 MachineBasicBlock *MBB) const {
18855 // Emit va_arg instruction on X86-64.
18857 // Operands to this pseudo-instruction:
18858 // 0 ) Output : destination address (reg)
18859 // 1-5) Input : va_list address (addr, i64mem)
18860 // 6 ) ArgSize : Size (in bytes) of vararg type
18861 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
18862 // 8 ) Align : Alignment of type
18863 // 9 ) EFLAGS (implicit-def)
18865 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
18866 static_assert(X86::AddrNumOperands == 5,
18867 "VAARG_64 assumes 5 address operands");
18869 unsigned DestReg = MI->getOperand(0).getReg();
18870 MachineOperand &Base = MI->getOperand(1);
18871 MachineOperand &Scale = MI->getOperand(2);
18872 MachineOperand &Index = MI->getOperand(3);
18873 MachineOperand &Disp = MI->getOperand(4);
18874 MachineOperand &Segment = MI->getOperand(5);
18875 unsigned ArgSize = MI->getOperand(6).getImm();
18876 unsigned ArgMode = MI->getOperand(7).getImm();
18877 unsigned Align = MI->getOperand(8).getImm();
18879 // Memory Reference
18880 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
18881 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
18882 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
18884 // Machine Information
18885 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
18886 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
18887 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
18888 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
18889 DebugLoc DL = MI->getDebugLoc();
18891 // struct va_list {
18894 // i64 overflow_area (address)
18895 // i64 reg_save_area (address)
18897 // sizeof(va_list) = 24
18898 // alignment(va_list) = 8
18900 unsigned TotalNumIntRegs = 6;
18901 unsigned TotalNumXMMRegs = 8;
18902 bool UseGPOffset = (ArgMode == 1);
18903 bool UseFPOffset = (ArgMode == 2);
18904 unsigned MaxOffset = TotalNumIntRegs * 8 +
18905 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
18907 /* Align ArgSize to a multiple of 8 */
18908 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
18909 bool NeedsAlign = (Align > 8);
18911 MachineBasicBlock *thisMBB = MBB;
18912 MachineBasicBlock *overflowMBB;
18913 MachineBasicBlock *offsetMBB;
18914 MachineBasicBlock *endMBB;
18916 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
18917 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
18918 unsigned OffsetReg = 0;
18920 if (!UseGPOffset && !UseFPOffset) {
18921 // If we only pull from the overflow region, we don't create a branch.
18922 // We don't need to alter control flow.
18923 OffsetDestReg = 0; // unused
18924 OverflowDestReg = DestReg;
18926 offsetMBB = nullptr;
18927 overflowMBB = thisMBB;
18930 // First emit code to check if gp_offset (or fp_offset) is below the bound.
18931 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
18932 // If not, pull from overflow_area. (branch to overflowMBB)
18937 // offsetMBB overflowMBB
18942 // Registers for the PHI in endMBB
18943 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
18944 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
18946 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
18947 MachineFunction *MF = MBB->getParent();
18948 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18949 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18950 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
18952 MachineFunction::iterator MBBIter = MBB;
18955 // Insert the new basic blocks
18956 MF->insert(MBBIter, offsetMBB);
18957 MF->insert(MBBIter, overflowMBB);
18958 MF->insert(MBBIter, endMBB);
18960 // Transfer the remainder of MBB and its successor edges to endMBB.
18961 endMBB->splice(endMBB->begin(), thisMBB,
18962 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
18963 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
18965 // Make offsetMBB and overflowMBB successors of thisMBB
18966 thisMBB->addSuccessor(offsetMBB);
18967 thisMBB->addSuccessor(overflowMBB);
18969 // endMBB is a successor of both offsetMBB and overflowMBB
18970 offsetMBB->addSuccessor(endMBB);
18971 overflowMBB->addSuccessor(endMBB);
18973 // Load the offset value into a register
18974 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
18975 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
18979 .addDisp(Disp, UseFPOffset ? 4 : 0)
18980 .addOperand(Segment)
18981 .setMemRefs(MMOBegin, MMOEnd);
18983 // Check if there is enough room left to pull this argument.
18984 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
18986 .addImm(MaxOffset + 8 - ArgSizeA8);
18988 // Branch to "overflowMBB" if offset >= max
18989 // Fall through to "offsetMBB" otherwise
18990 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
18991 .addMBB(overflowMBB);
18994 // In offsetMBB, emit code to use the reg_save_area.
18996 assert(OffsetReg != 0);
18998 // Read the reg_save_area address.
18999 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19000 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19005 .addOperand(Segment)
19006 .setMemRefs(MMOBegin, MMOEnd);
19008 // Zero-extend the offset
19009 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19010 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19013 .addImm(X86::sub_32bit);
19015 // Add the offset to the reg_save_area to get the final address.
19016 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19017 .addReg(OffsetReg64)
19018 .addReg(RegSaveReg);
19020 // Compute the offset for the next argument
19021 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19022 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19024 .addImm(UseFPOffset ? 16 : 8);
19026 // Store it back into the va_list.
19027 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19031 .addDisp(Disp, UseFPOffset ? 4 : 0)
19032 .addOperand(Segment)
19033 .addReg(NextOffsetReg)
19034 .setMemRefs(MMOBegin, MMOEnd);
19037 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
19042 // Emit code to use overflow area
19045 // Load the overflow_area address into a register.
19046 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19047 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19052 .addOperand(Segment)
19053 .setMemRefs(MMOBegin, MMOEnd);
19055 // If we need to align it, do so. Otherwise, just copy the address
19056 // to OverflowDestReg.
19058 // Align the overflow address
19059 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19060 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19062 // aligned_addr = (addr + (align-1)) & ~(align-1)
19063 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19064 .addReg(OverflowAddrReg)
19067 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19069 .addImm(~(uint64_t)(Align-1));
19071 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19072 .addReg(OverflowAddrReg);
19075 // Compute the next overflow address after this argument.
19076 // (the overflow address should be kept 8-byte aligned)
19077 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19078 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19079 .addReg(OverflowDestReg)
19080 .addImm(ArgSizeA8);
19082 // Store the new overflow address.
19083 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19088 .addOperand(Segment)
19089 .addReg(NextAddrReg)
19090 .setMemRefs(MMOBegin, MMOEnd);
19092 // If we branched, emit the PHI to the front of endMBB.
19094 BuildMI(*endMBB, endMBB->begin(), DL,
19095 TII->get(X86::PHI), DestReg)
19096 .addReg(OffsetDestReg).addMBB(offsetMBB)
19097 .addReg(OverflowDestReg).addMBB(overflowMBB);
19100 // Erase the pseudo instruction
19101 MI->eraseFromParent();
19106 MachineBasicBlock *
19107 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19109 MachineBasicBlock *MBB) const {
19110 // Emit code to save XMM registers to the stack. The ABI says that the
19111 // number of registers to save is given in %al, so it's theoretically
19112 // possible to do an indirect jump trick to avoid saving all of them,
19113 // however this code takes a simpler approach and just executes all
19114 // of the stores if %al is non-zero. It's less code, and it's probably
19115 // easier on the hardware branch predictor, and stores aren't all that
19116 // expensive anyway.
19118 // Create the new basic blocks. One block contains all the XMM stores,
19119 // and one block is the final destination regardless of whether any
19120 // stores were performed.
19121 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19122 MachineFunction *F = MBB->getParent();
19123 MachineFunction::iterator MBBIter = MBB;
19125 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19126 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19127 F->insert(MBBIter, XMMSaveMBB);
19128 F->insert(MBBIter, EndMBB);
19130 // Transfer the remainder of MBB and its successor edges to EndMBB.
19131 EndMBB->splice(EndMBB->begin(), MBB,
19132 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19133 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19135 // The original block will now fall through to the XMM save block.
19136 MBB->addSuccessor(XMMSaveMBB);
19137 // The XMMSaveMBB will fall through to the end block.
19138 XMMSaveMBB->addSuccessor(EndMBB);
19140 // Now add the instructions.
19141 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19142 DebugLoc DL = MI->getDebugLoc();
19144 unsigned CountReg = MI->getOperand(0).getReg();
19145 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19146 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19148 if (!Subtarget->isTargetWin64()) {
19149 // If %al is 0, branch around the XMM save block.
19150 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19151 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19152 MBB->addSuccessor(EndMBB);
19155 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19156 // that was just emitted, but clearly shouldn't be "saved".
19157 assert((MI->getNumOperands() <= 3 ||
19158 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19159 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19160 && "Expected last argument to be EFLAGS");
19161 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19162 // In the XMM save block, save all the XMM argument registers.
19163 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19164 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19165 MachineMemOperand *MMO =
19166 F->getMachineMemOperand(
19167 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19168 MachineMemOperand::MOStore,
19169 /*Size=*/16, /*Align=*/16);
19170 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19171 .addFrameIndex(RegSaveFrameIndex)
19172 .addImm(/*Scale=*/1)
19173 .addReg(/*IndexReg=*/0)
19174 .addImm(/*Disp=*/Offset)
19175 .addReg(/*Segment=*/0)
19176 .addReg(MI->getOperand(i).getReg())
19177 .addMemOperand(MMO);
19180 MI->eraseFromParent(); // The pseudo instruction is gone now.
19185 // The EFLAGS operand of SelectItr might be missing a kill marker
19186 // because there were multiple uses of EFLAGS, and ISel didn't know
19187 // which to mark. Figure out whether SelectItr should have had a
19188 // kill marker, and set it if it should. Returns the correct kill
19190 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19191 MachineBasicBlock* BB,
19192 const TargetRegisterInfo* TRI) {
19193 // Scan forward through BB for a use/def of EFLAGS.
19194 MachineBasicBlock::iterator miI(std::next(SelectItr));
19195 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19196 const MachineInstr& mi = *miI;
19197 if (mi.readsRegister(X86::EFLAGS))
19199 if (mi.definesRegister(X86::EFLAGS))
19200 break; // Should have kill-flag - update below.
19203 // If we hit the end of the block, check whether EFLAGS is live into a
19205 if (miI == BB->end()) {
19206 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19207 sEnd = BB->succ_end();
19208 sItr != sEnd; ++sItr) {
19209 MachineBasicBlock* succ = *sItr;
19210 if (succ->isLiveIn(X86::EFLAGS))
19215 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19216 // out. SelectMI should have a kill flag on EFLAGS.
19217 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19221 MachineBasicBlock *
19222 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19223 MachineBasicBlock *BB) const {
19224 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19225 DebugLoc DL = MI->getDebugLoc();
19227 // To "insert" a SELECT_CC instruction, we actually have to insert the
19228 // diamond control-flow pattern. The incoming instruction knows the
19229 // destination vreg to set, the condition code register to branch on, the
19230 // true/false values to select between, and a branch opcode to use.
19231 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19232 MachineFunction::iterator It = BB;
19238 // cmpTY ccX, r1, r2
19240 // fallthrough --> copy0MBB
19241 MachineBasicBlock *thisMBB = BB;
19242 MachineFunction *F = BB->getParent();
19244 // We also lower double CMOVs:
19245 // (CMOV (CMOV F, T, cc1), T, cc2)
19246 // to two successives branches. For that, we look for another CMOV as the
19247 // following instruction.
19249 // Without this, we would add a PHI between the two jumps, which ends up
19250 // creating a few copies all around. For instance, for
19252 // (sitofp (zext (fcmp une)))
19254 // we would generate:
19256 // ucomiss %xmm1, %xmm0
19257 // movss <1.0f>, %xmm0
19258 // movaps %xmm0, %xmm1
19260 // xorps %xmm1, %xmm1
19263 // movaps %xmm1, %xmm0
19267 // because this custom-inserter would have generated:
19279 // A: X = ...; Y = ...
19281 // C: Z = PHI [X, A], [Y, B]
19283 // E: PHI [X, C], [Z, D]
19285 // If we lower both CMOVs in a single step, we can instead generate:
19297 // A: X = ...; Y = ...
19299 // E: PHI [X, A], [X, C], [Y, D]
19301 // Which, in our sitofp/fcmp example, gives us something like:
19303 // ucomiss %xmm1, %xmm0
19304 // movss <1.0f>, %xmm0
19307 // xorps %xmm0, %xmm0
19311 MachineInstr *NextCMOV = nullptr;
19312 MachineBasicBlock::iterator NextMIIt =
19313 std::next(MachineBasicBlock::iterator(MI));
19314 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19315 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19316 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19317 NextCMOV = &*NextMIIt;
19319 MachineBasicBlock *jcc1MBB = nullptr;
19321 // If we have a double CMOV, we lower it to two successive branches to
19322 // the same block. EFLAGS is used by both, so mark it as live in the second.
19324 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19325 F->insert(It, jcc1MBB);
19326 jcc1MBB->addLiveIn(X86::EFLAGS);
19329 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19330 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19331 F->insert(It, copy0MBB);
19332 F->insert(It, sinkMBB);
19334 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19335 // live into the sink and copy blocks.
19336 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19338 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19339 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19340 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19341 copy0MBB->addLiveIn(X86::EFLAGS);
19342 sinkMBB->addLiveIn(X86::EFLAGS);
19345 // Transfer the remainder of BB and its successor edges to sinkMBB.
19346 sinkMBB->splice(sinkMBB->begin(), BB,
19347 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19348 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19350 // Add the true and fallthrough blocks as its successors.
19352 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19353 BB->addSuccessor(jcc1MBB);
19355 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19356 // jump to the sinkMBB.
19357 jcc1MBB->addSuccessor(copy0MBB);
19358 jcc1MBB->addSuccessor(sinkMBB);
19360 BB->addSuccessor(copy0MBB);
19363 // The true block target of the first (or only) branch is always sinkMBB.
19364 BB->addSuccessor(sinkMBB);
19366 // Create the conditional branch instruction.
19368 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19369 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19372 unsigned Opc2 = X86::GetCondBranchFromCond(
19373 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19374 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19378 // %FalseValue = ...
19379 // # fallthrough to sinkMBB
19380 copy0MBB->addSuccessor(sinkMBB);
19383 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19385 MachineInstrBuilder MIB =
19386 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19387 MI->getOperand(0).getReg())
19388 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19389 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19391 // If we have a double CMOV, the second Jcc provides the same incoming
19392 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19394 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19395 // Copy the PHI result to the register defined by the second CMOV.
19396 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19397 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19398 .addReg(MI->getOperand(0).getReg());
19399 NextCMOV->eraseFromParent();
19402 MI->eraseFromParent(); // The pseudo instruction is gone now.
19406 MachineBasicBlock *
19407 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19408 MachineBasicBlock *BB) const {
19409 MachineFunction *MF = BB->getParent();
19410 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19411 DebugLoc DL = MI->getDebugLoc();
19412 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19414 assert(MF->shouldSplitStack());
19416 const bool Is64Bit = Subtarget->is64Bit();
19417 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19419 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19420 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19423 // ... [Till the alloca]
19424 // If stacklet is not large enough, jump to mallocMBB
19427 // Allocate by subtracting from RSP
19428 // Jump to continueMBB
19431 // Allocate by call to runtime
19435 // [rest of original BB]
19438 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19439 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19440 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19442 MachineRegisterInfo &MRI = MF->getRegInfo();
19443 const TargetRegisterClass *AddrRegClass =
19444 getRegClassFor(getPointerTy());
19446 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19447 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19448 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19449 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19450 sizeVReg = MI->getOperand(1).getReg(),
19451 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19453 MachineFunction::iterator MBBIter = BB;
19456 MF->insert(MBBIter, bumpMBB);
19457 MF->insert(MBBIter, mallocMBB);
19458 MF->insert(MBBIter, continueMBB);
19460 continueMBB->splice(continueMBB->begin(), BB,
19461 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19462 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19464 // Add code to the main basic block to check if the stack limit has been hit,
19465 // and if so, jump to mallocMBB otherwise to bumpMBB.
19466 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19467 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19468 .addReg(tmpSPVReg).addReg(sizeVReg);
19469 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19470 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19471 .addReg(SPLimitVReg);
19472 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19474 // bumpMBB simply decreases the stack pointer, since we know the current
19475 // stacklet has enough space.
19476 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19477 .addReg(SPLimitVReg);
19478 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19479 .addReg(SPLimitVReg);
19480 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19482 // Calls into a routine in libgcc to allocate more space from the heap.
19483 const uint32_t *RegMask =
19484 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19486 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19488 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19489 .addExternalSymbol("__morestack_allocate_stack_space")
19490 .addRegMask(RegMask)
19491 .addReg(X86::RDI, RegState::Implicit)
19492 .addReg(X86::RAX, RegState::ImplicitDefine);
19493 } else if (Is64Bit) {
19494 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19496 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19497 .addExternalSymbol("__morestack_allocate_stack_space")
19498 .addRegMask(RegMask)
19499 .addReg(X86::EDI, RegState::Implicit)
19500 .addReg(X86::EAX, RegState::ImplicitDefine);
19502 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19504 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19505 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19506 .addExternalSymbol("__morestack_allocate_stack_space")
19507 .addRegMask(RegMask)
19508 .addReg(X86::EAX, RegState::ImplicitDefine);
19512 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19515 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19516 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19517 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19519 // Set up the CFG correctly.
19520 BB->addSuccessor(bumpMBB);
19521 BB->addSuccessor(mallocMBB);
19522 mallocMBB->addSuccessor(continueMBB);
19523 bumpMBB->addSuccessor(continueMBB);
19525 // Take care of the PHI nodes.
19526 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19527 MI->getOperand(0).getReg())
19528 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19529 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19531 // Delete the original pseudo instruction.
19532 MI->eraseFromParent();
19535 return continueMBB;
19538 MachineBasicBlock *
19539 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19540 MachineBasicBlock *BB) const {
19541 DebugLoc DL = MI->getDebugLoc();
19543 assert(!Subtarget->isTargetMachO());
19545 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
19548 MI->eraseFromParent(); // The pseudo instruction is gone now.
19552 MachineBasicBlock *
19553 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19554 MachineBasicBlock *BB) const {
19555 // This is pretty easy. We're taking the value that we received from
19556 // our load from the relocation, sticking it in either RDI (x86-64)
19557 // or EAX and doing an indirect call. The return value will then
19558 // be in the normal return register.
19559 MachineFunction *F = BB->getParent();
19560 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19561 DebugLoc DL = MI->getDebugLoc();
19563 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19564 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19566 // Get a register mask for the lowered call.
19567 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19568 // proper register mask.
19569 const uint32_t *RegMask =
19570 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19571 if (Subtarget->is64Bit()) {
19572 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19573 TII->get(X86::MOV64rm), X86::RDI)
19575 .addImm(0).addReg(0)
19576 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19577 MI->getOperand(3).getTargetFlags())
19579 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19580 addDirectMem(MIB, X86::RDI);
19581 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19582 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19583 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19584 TII->get(X86::MOV32rm), X86::EAX)
19586 .addImm(0).addReg(0)
19587 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19588 MI->getOperand(3).getTargetFlags())
19590 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19591 addDirectMem(MIB, X86::EAX);
19592 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19594 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19595 TII->get(X86::MOV32rm), X86::EAX)
19596 .addReg(TII->getGlobalBaseReg(F))
19597 .addImm(0).addReg(0)
19598 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19599 MI->getOperand(3).getTargetFlags())
19601 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19602 addDirectMem(MIB, X86::EAX);
19603 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19606 MI->eraseFromParent(); // The pseudo instruction is gone now.
19610 MachineBasicBlock *
19611 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
19612 MachineBasicBlock *MBB) const {
19613 DebugLoc DL = MI->getDebugLoc();
19614 MachineFunction *MF = MBB->getParent();
19615 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19616 MachineRegisterInfo &MRI = MF->getRegInfo();
19618 const BasicBlock *BB = MBB->getBasicBlock();
19619 MachineFunction::iterator I = MBB;
19622 // Memory Reference
19623 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19624 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19627 unsigned MemOpndSlot = 0;
19629 unsigned CurOp = 0;
19631 DstReg = MI->getOperand(CurOp++).getReg();
19632 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
19633 assert(RC->hasType(MVT::i32) && "Invalid destination!");
19634 unsigned mainDstReg = MRI.createVirtualRegister(RC);
19635 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
19637 MemOpndSlot = CurOp;
19639 MVT PVT = getPointerTy();
19640 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19641 "Invalid Pointer Size!");
19643 // For v = setjmp(buf), we generate
19646 // buf[LabelOffset] = restoreMBB
19647 // SjLjSetup restoreMBB
19653 // v = phi(main, restore)
19656 // if base pointer being used, load it from frame
19659 MachineBasicBlock *thisMBB = MBB;
19660 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19661 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19662 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
19663 MF->insert(I, mainMBB);
19664 MF->insert(I, sinkMBB);
19665 MF->push_back(restoreMBB);
19667 MachineInstrBuilder MIB;
19669 // Transfer the remainder of BB and its successor edges to sinkMBB.
19670 sinkMBB->splice(sinkMBB->begin(), MBB,
19671 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19672 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19675 unsigned PtrStoreOpc = 0;
19676 unsigned LabelReg = 0;
19677 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19678 Reloc::Model RM = MF->getTarget().getRelocationModel();
19679 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
19680 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
19682 // Prepare IP either in reg or imm.
19683 if (!UseImmLabel) {
19684 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
19685 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
19686 LabelReg = MRI.createVirtualRegister(PtrRC);
19687 if (Subtarget->is64Bit()) {
19688 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
19692 .addMBB(restoreMBB)
19695 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
19696 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
19697 .addReg(XII->getGlobalBaseReg(MF))
19700 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
19704 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
19706 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
19707 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19708 if (i == X86::AddrDisp)
19709 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
19711 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
19714 MIB.addReg(LabelReg);
19716 MIB.addMBB(restoreMBB);
19717 MIB.setMemRefs(MMOBegin, MMOEnd);
19719 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
19720 .addMBB(restoreMBB);
19722 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19723 MIB.addRegMask(RegInfo->getNoPreservedMask());
19724 thisMBB->addSuccessor(mainMBB);
19725 thisMBB->addSuccessor(restoreMBB);
19729 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
19730 mainMBB->addSuccessor(sinkMBB);
19733 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19734 TII->get(X86::PHI), DstReg)
19735 .addReg(mainDstReg).addMBB(mainMBB)
19736 .addReg(restoreDstReg).addMBB(restoreMBB);
19739 if (RegInfo->hasBasePointer(*MF)) {
19740 const bool Uses64BitFramePtr =
19741 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
19742 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
19743 X86FI->setRestoreBasePointer(MF);
19744 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
19745 unsigned BasePtr = RegInfo->getBaseRegister();
19746 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
19747 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
19748 FramePtr, true, X86FI->getRestoreBasePointerOffset())
19749 .setMIFlag(MachineInstr::FrameSetup);
19751 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
19752 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
19753 restoreMBB->addSuccessor(sinkMBB);
19755 MI->eraseFromParent();
19759 MachineBasicBlock *
19760 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
19761 MachineBasicBlock *MBB) const {
19762 DebugLoc DL = MI->getDebugLoc();
19763 MachineFunction *MF = MBB->getParent();
19764 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19765 MachineRegisterInfo &MRI = MF->getRegInfo();
19767 // Memory Reference
19768 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19769 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19771 MVT PVT = getPointerTy();
19772 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
19773 "Invalid Pointer Size!");
19775 const TargetRegisterClass *RC =
19776 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
19777 unsigned Tmp = MRI.createVirtualRegister(RC);
19778 // Since FP is only updated here but NOT referenced, it's treated as GPR.
19779 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
19780 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
19781 unsigned SP = RegInfo->getStackRegister();
19783 MachineInstrBuilder MIB;
19785 const int64_t LabelOffset = 1 * PVT.getStoreSize();
19786 const int64_t SPOffset = 2 * PVT.getStoreSize();
19788 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
19789 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
19792 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
19793 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
19794 MIB.addOperand(MI->getOperand(i));
19795 MIB.setMemRefs(MMOBegin, MMOEnd);
19797 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
19798 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19799 if (i == X86::AddrDisp)
19800 MIB.addDisp(MI->getOperand(i), LabelOffset);
19802 MIB.addOperand(MI->getOperand(i));
19804 MIB.setMemRefs(MMOBegin, MMOEnd);
19806 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
19807 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
19808 if (i == X86::AddrDisp)
19809 MIB.addDisp(MI->getOperand(i), SPOffset);
19811 MIB.addOperand(MI->getOperand(i));
19813 MIB.setMemRefs(MMOBegin, MMOEnd);
19815 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
19817 MI->eraseFromParent();
19821 // Replace 213-type (isel default) FMA3 instructions with 231-type for
19822 // accumulator loops. Writing back to the accumulator allows the coalescer
19823 // to remove extra copies in the loop.
19824 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
19825 MachineBasicBlock *
19826 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
19827 MachineBasicBlock *MBB) const {
19828 MachineOperand &AddendOp = MI->getOperand(3);
19830 // Bail out early if the addend isn't a register - we can't switch these.
19831 if (!AddendOp.isReg())
19834 MachineFunction &MF = *MBB->getParent();
19835 MachineRegisterInfo &MRI = MF.getRegInfo();
19837 // Check whether the addend is defined by a PHI:
19838 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
19839 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
19840 if (!AddendDef.isPHI())
19843 // Look for the following pattern:
19845 // %addend = phi [%entry, 0], [%loop, %result]
19847 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
19851 // %addend = phi [%entry, 0], [%loop, %result]
19853 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
19855 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
19856 assert(AddendDef.getOperand(i).isReg());
19857 MachineOperand PHISrcOp = AddendDef.getOperand(i);
19858 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
19859 if (&PHISrcInst == MI) {
19860 // Found a matching instruction.
19861 unsigned NewFMAOpc = 0;
19862 switch (MI->getOpcode()) {
19863 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
19864 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
19865 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
19866 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
19867 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
19868 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
19869 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
19870 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
19871 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
19872 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
19873 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
19874 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
19875 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
19876 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
19877 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
19878 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
19879 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
19880 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
19881 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
19882 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
19884 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
19885 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
19886 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
19887 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
19888 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
19889 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
19890 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
19891 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
19892 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
19893 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
19894 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
19895 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
19896 default: llvm_unreachable("Unrecognized FMA variant.");
19899 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
19900 MachineInstrBuilder MIB =
19901 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
19902 .addOperand(MI->getOperand(0))
19903 .addOperand(MI->getOperand(3))
19904 .addOperand(MI->getOperand(2))
19905 .addOperand(MI->getOperand(1));
19906 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
19907 MI->eraseFromParent();
19914 MachineBasicBlock *
19915 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
19916 MachineBasicBlock *BB) const {
19917 switch (MI->getOpcode()) {
19918 default: llvm_unreachable("Unexpected instr type to insert");
19919 case X86::TAILJMPd64:
19920 case X86::TAILJMPr64:
19921 case X86::TAILJMPm64:
19922 case X86::TAILJMPd64_REX:
19923 case X86::TAILJMPr64_REX:
19924 case X86::TAILJMPm64_REX:
19925 llvm_unreachable("TAILJMP64 would not be touched here.");
19926 case X86::TCRETURNdi64:
19927 case X86::TCRETURNri64:
19928 case X86::TCRETURNmi64:
19930 case X86::WIN_ALLOCA:
19931 return EmitLoweredWinAlloca(MI, BB);
19932 case X86::SEG_ALLOCA_32:
19933 case X86::SEG_ALLOCA_64:
19934 return EmitLoweredSegAlloca(MI, BB);
19935 case X86::TLSCall_32:
19936 case X86::TLSCall_64:
19937 return EmitLoweredTLSCall(MI, BB);
19938 case X86::CMOV_GR8:
19939 case X86::CMOV_FR32:
19940 case X86::CMOV_FR64:
19941 case X86::CMOV_V4F32:
19942 case X86::CMOV_V2F64:
19943 case X86::CMOV_V2I64:
19944 case X86::CMOV_V8F32:
19945 case X86::CMOV_V4F64:
19946 case X86::CMOV_V4I64:
19947 case X86::CMOV_V16F32:
19948 case X86::CMOV_V8F64:
19949 case X86::CMOV_V8I64:
19950 case X86::CMOV_GR16:
19951 case X86::CMOV_GR32:
19952 case X86::CMOV_RFP32:
19953 case X86::CMOV_RFP64:
19954 case X86::CMOV_RFP80:
19955 case X86::CMOV_V8I1:
19956 case X86::CMOV_V16I1:
19957 case X86::CMOV_V32I1:
19958 case X86::CMOV_V64I1:
19959 return EmitLoweredSelect(MI, BB);
19961 case X86::FP32_TO_INT16_IN_MEM:
19962 case X86::FP32_TO_INT32_IN_MEM:
19963 case X86::FP32_TO_INT64_IN_MEM:
19964 case X86::FP64_TO_INT16_IN_MEM:
19965 case X86::FP64_TO_INT32_IN_MEM:
19966 case X86::FP64_TO_INT64_IN_MEM:
19967 case X86::FP80_TO_INT16_IN_MEM:
19968 case X86::FP80_TO_INT32_IN_MEM:
19969 case X86::FP80_TO_INT64_IN_MEM: {
19970 MachineFunction *F = BB->getParent();
19971 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19972 DebugLoc DL = MI->getDebugLoc();
19974 // Change the floating point control register to use "round towards zero"
19975 // mode when truncating to an integer value.
19976 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
19977 addFrameReference(BuildMI(*BB, MI, DL,
19978 TII->get(X86::FNSTCW16m)), CWFrameIdx);
19980 // Load the old value of the high byte of the control word...
19982 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
19983 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
19986 // Set the high part to be round to zero...
19987 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
19990 // Reload the modified control word now...
19991 addFrameReference(BuildMI(*BB, MI, DL,
19992 TII->get(X86::FLDCW16m)), CWFrameIdx);
19994 // Restore the memory image of control word to original value
19995 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
19998 // Get the X86 opcode to use.
20000 switch (MI->getOpcode()) {
20001 default: llvm_unreachable("illegal opcode!");
20002 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20003 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20004 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20005 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20006 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20007 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20008 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20009 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20010 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20014 MachineOperand &Op = MI->getOperand(0);
20016 AM.BaseType = X86AddressMode::RegBase;
20017 AM.Base.Reg = Op.getReg();
20019 AM.BaseType = X86AddressMode::FrameIndexBase;
20020 AM.Base.FrameIndex = Op.getIndex();
20022 Op = MI->getOperand(1);
20024 AM.Scale = Op.getImm();
20025 Op = MI->getOperand(2);
20027 AM.IndexReg = Op.getImm();
20028 Op = MI->getOperand(3);
20029 if (Op.isGlobal()) {
20030 AM.GV = Op.getGlobal();
20032 AM.Disp = Op.getImm();
20034 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20035 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20037 // Reload the original control word now.
20038 addFrameReference(BuildMI(*BB, MI, DL,
20039 TII->get(X86::FLDCW16m)), CWFrameIdx);
20041 MI->eraseFromParent(); // The pseudo instruction is gone now.
20044 // String/text processing lowering.
20045 case X86::PCMPISTRM128REG:
20046 case X86::VPCMPISTRM128REG:
20047 case X86::PCMPISTRM128MEM:
20048 case X86::VPCMPISTRM128MEM:
20049 case X86::PCMPESTRM128REG:
20050 case X86::VPCMPESTRM128REG:
20051 case X86::PCMPESTRM128MEM:
20052 case X86::VPCMPESTRM128MEM:
20053 assert(Subtarget->hasSSE42() &&
20054 "Target must have SSE4.2 or AVX features enabled");
20055 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
20057 // String/text processing lowering.
20058 case X86::PCMPISTRIREG:
20059 case X86::VPCMPISTRIREG:
20060 case X86::PCMPISTRIMEM:
20061 case X86::VPCMPISTRIMEM:
20062 case X86::PCMPESTRIREG:
20063 case X86::VPCMPESTRIREG:
20064 case X86::PCMPESTRIMEM:
20065 case X86::VPCMPESTRIMEM:
20066 assert(Subtarget->hasSSE42() &&
20067 "Target must have SSE4.2 or AVX features enabled");
20068 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
20070 // Thread synchronization.
20072 return EmitMonitor(MI, BB, Subtarget);
20076 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
20078 case X86::VASTART_SAVE_XMM_REGS:
20079 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20081 case X86::VAARG_64:
20082 return EmitVAARG64WithCustomInserter(MI, BB);
20084 case X86::EH_SjLj_SetJmp32:
20085 case X86::EH_SjLj_SetJmp64:
20086 return emitEHSjLjSetJmp(MI, BB);
20088 case X86::EH_SjLj_LongJmp32:
20089 case X86::EH_SjLj_LongJmp64:
20090 return emitEHSjLjLongJmp(MI, BB);
20092 case TargetOpcode::STATEPOINT:
20093 // As an implementation detail, STATEPOINT shares the STACKMAP format at
20094 // this point in the process. We diverge later.
20095 return emitPatchPoint(MI, BB);
20097 case TargetOpcode::STACKMAP:
20098 case TargetOpcode::PATCHPOINT:
20099 return emitPatchPoint(MI, BB);
20101 case X86::VFMADDPDr213r:
20102 case X86::VFMADDPSr213r:
20103 case X86::VFMADDSDr213r:
20104 case X86::VFMADDSSr213r:
20105 case X86::VFMSUBPDr213r:
20106 case X86::VFMSUBPSr213r:
20107 case X86::VFMSUBSDr213r:
20108 case X86::VFMSUBSSr213r:
20109 case X86::VFNMADDPDr213r:
20110 case X86::VFNMADDPSr213r:
20111 case X86::VFNMADDSDr213r:
20112 case X86::VFNMADDSSr213r:
20113 case X86::VFNMSUBPDr213r:
20114 case X86::VFNMSUBPSr213r:
20115 case X86::VFNMSUBSDr213r:
20116 case X86::VFNMSUBSSr213r:
20117 case X86::VFMADDSUBPDr213r:
20118 case X86::VFMADDSUBPSr213r:
20119 case X86::VFMSUBADDPDr213r:
20120 case X86::VFMSUBADDPSr213r:
20121 case X86::VFMADDPDr213rY:
20122 case X86::VFMADDPSr213rY:
20123 case X86::VFMSUBPDr213rY:
20124 case X86::VFMSUBPSr213rY:
20125 case X86::VFNMADDPDr213rY:
20126 case X86::VFNMADDPSr213rY:
20127 case X86::VFNMSUBPDr213rY:
20128 case X86::VFNMSUBPSr213rY:
20129 case X86::VFMADDSUBPDr213rY:
20130 case X86::VFMADDSUBPSr213rY:
20131 case X86::VFMSUBADDPDr213rY:
20132 case X86::VFMSUBADDPSr213rY:
20133 return emitFMA3Instr(MI, BB);
20137 //===----------------------------------------------------------------------===//
20138 // X86 Optimization Hooks
20139 //===----------------------------------------------------------------------===//
20141 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20144 const SelectionDAG &DAG,
20145 unsigned Depth) const {
20146 unsigned BitWidth = KnownZero.getBitWidth();
20147 unsigned Opc = Op.getOpcode();
20148 assert((Opc >= ISD::BUILTIN_OP_END ||
20149 Opc == ISD::INTRINSIC_WO_CHAIN ||
20150 Opc == ISD::INTRINSIC_W_CHAIN ||
20151 Opc == ISD::INTRINSIC_VOID) &&
20152 "Should use MaskedValueIsZero if you don't know whether Op"
20153 " is a target node!");
20155 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20169 // These nodes' second result is a boolean.
20170 if (Op.getResNo() == 0)
20173 case X86ISD::SETCC:
20174 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20176 case ISD::INTRINSIC_WO_CHAIN: {
20177 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20178 unsigned NumLoBits = 0;
20181 case Intrinsic::x86_sse_movmsk_ps:
20182 case Intrinsic::x86_avx_movmsk_ps_256:
20183 case Intrinsic::x86_sse2_movmsk_pd:
20184 case Intrinsic::x86_avx_movmsk_pd_256:
20185 case Intrinsic::x86_mmx_pmovmskb:
20186 case Intrinsic::x86_sse2_pmovmskb_128:
20187 case Intrinsic::x86_avx2_pmovmskb: {
20188 // High bits of movmskp{s|d}, pmovmskb are known zero.
20190 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20191 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20192 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20193 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20194 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20195 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20196 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20197 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20199 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20208 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20210 const SelectionDAG &,
20211 unsigned Depth) const {
20212 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20213 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20214 return Op.getValueType().getScalarType().getSizeInBits();
20220 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20221 /// node is a GlobalAddress + offset.
20222 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20223 const GlobalValue* &GA,
20224 int64_t &Offset) const {
20225 if (N->getOpcode() == X86ISD::Wrapper) {
20226 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20227 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20228 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20232 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20235 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20236 /// same as extracting the high 128-bit part of 256-bit vector and then
20237 /// inserting the result into the low part of a new 256-bit vector
20238 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20239 EVT VT = SVOp->getValueType(0);
20240 unsigned NumElems = VT.getVectorNumElements();
20242 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20243 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20244 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20245 SVOp->getMaskElt(j) >= 0)
20251 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20252 /// same as extracting the low 128-bit part of 256-bit vector and then
20253 /// inserting the result into the high part of a new 256-bit vector
20254 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20255 EVT VT = SVOp->getValueType(0);
20256 unsigned NumElems = VT.getVectorNumElements();
20258 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20259 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20260 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20261 SVOp->getMaskElt(j) >= 0)
20267 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20268 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20269 TargetLowering::DAGCombinerInfo &DCI,
20270 const X86Subtarget* Subtarget) {
20272 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20273 SDValue V1 = SVOp->getOperand(0);
20274 SDValue V2 = SVOp->getOperand(1);
20275 EVT VT = SVOp->getValueType(0);
20276 unsigned NumElems = VT.getVectorNumElements();
20278 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20279 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20283 // V UNDEF BUILD_VECTOR UNDEF
20285 // CONCAT_VECTOR CONCAT_VECTOR
20288 // RESULT: V + zero extended
20290 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20291 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20292 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20295 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20298 // To match the shuffle mask, the first half of the mask should
20299 // be exactly the first vector, and all the rest a splat with the
20300 // first element of the second one.
20301 for (unsigned i = 0; i != NumElems/2; ++i)
20302 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20303 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20306 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20307 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20308 if (Ld->hasNUsesOfValue(1, 0)) {
20309 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20310 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20312 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20314 Ld->getPointerInfo(),
20315 Ld->getAlignment(),
20316 false/*isVolatile*/, true/*ReadMem*/,
20317 false/*WriteMem*/);
20319 // Make sure the newly-created LOAD is in the same position as Ld in
20320 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20321 // and update uses of Ld's output chain to use the TokenFactor.
20322 if (Ld->hasAnyUseOfValue(1)) {
20323 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20324 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20325 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20326 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20327 SDValue(ResNode.getNode(), 1));
20330 return DAG.getBitcast(VT, ResNode);
20334 // Emit a zeroed vector and insert the desired subvector on its
20336 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20337 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20338 return DCI.CombineTo(N, InsV);
20341 //===--------------------------------------------------------------------===//
20342 // Combine some shuffles into subvector extracts and inserts:
20345 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20346 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20347 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20348 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20349 return DCI.CombineTo(N, InsV);
20352 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20353 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20354 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20355 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20356 return DCI.CombineTo(N, InsV);
20362 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20365 /// This is the leaf of the recursive combinine below. When we have found some
20366 /// chain of single-use x86 shuffle instructions and accumulated the combined
20367 /// shuffle mask represented by them, this will try to pattern match that mask
20368 /// into either a single instruction if there is a special purpose instruction
20369 /// for this operation, or into a PSHUFB instruction which is a fully general
20370 /// instruction but should only be used to replace chains over a certain depth.
20371 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20372 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20373 TargetLowering::DAGCombinerInfo &DCI,
20374 const X86Subtarget *Subtarget) {
20375 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20377 // Find the operand that enters the chain. Note that multiple uses are OK
20378 // here, we're not going to remove the operand we find.
20379 SDValue Input = Op.getOperand(0);
20380 while (Input.getOpcode() == ISD::BITCAST)
20381 Input = Input.getOperand(0);
20383 MVT VT = Input.getSimpleValueType();
20384 MVT RootVT = Root.getSimpleValueType();
20387 // Just remove no-op shuffle masks.
20388 if (Mask.size() == 1) {
20389 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
20394 // Use the float domain if the operand type is a floating point type.
20395 bool FloatDomain = VT.isFloatingPoint();
20397 // For floating point shuffles, we don't have free copies in the shuffle
20398 // instructions or the ability to load as part of the instruction, so
20399 // canonicalize their shuffles to UNPCK or MOV variants.
20401 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20402 // vectors because it can have a load folded into it that UNPCK cannot. This
20403 // doesn't preclude something switching to the shorter encoding post-RA.
20405 // FIXME: Should teach these routines about AVX vector widths.
20406 if (FloatDomain && VT.getSizeInBits() == 128) {
20407 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20408 bool Lo = Mask.equals({0, 0});
20411 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20412 // is no slower than UNPCKLPD but has the option to fold the input operand
20413 // into even an unaligned memory load.
20414 if (Lo && Subtarget->hasSSE3()) {
20415 Shuffle = X86ISD::MOVDDUP;
20416 ShuffleVT = MVT::v2f64;
20418 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20419 // than the UNPCK variants.
20420 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20421 ShuffleVT = MVT::v4f32;
20423 if (Depth == 1 && Root->getOpcode() == Shuffle)
20424 return false; // Nothing to do!
20425 Op = DAG.getBitcast(ShuffleVT, Input);
20426 DCI.AddToWorklist(Op.getNode());
20427 if (Shuffle == X86ISD::MOVDDUP)
20428 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20430 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20431 DCI.AddToWorklist(Op.getNode());
20432 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20436 if (Subtarget->hasSSE3() &&
20437 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20438 bool Lo = Mask.equals({0, 0, 2, 2});
20439 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20440 MVT ShuffleVT = MVT::v4f32;
20441 if (Depth == 1 && Root->getOpcode() == Shuffle)
20442 return false; // Nothing to do!
20443 Op = DAG.getBitcast(ShuffleVT, Input);
20444 DCI.AddToWorklist(Op.getNode());
20445 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20446 DCI.AddToWorklist(Op.getNode());
20447 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20451 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20452 bool Lo = Mask.equals({0, 0, 1, 1});
20453 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20454 MVT ShuffleVT = MVT::v4f32;
20455 if (Depth == 1 && Root->getOpcode() == Shuffle)
20456 return false; // Nothing to do!
20457 Op = DAG.getBitcast(ShuffleVT, Input);
20458 DCI.AddToWorklist(Op.getNode());
20459 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20460 DCI.AddToWorklist(Op.getNode());
20461 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20467 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20468 // variants as none of these have single-instruction variants that are
20469 // superior to the UNPCK formulation.
20470 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20471 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20472 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20473 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20475 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20476 bool Lo = Mask[0] == 0;
20477 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20478 if (Depth == 1 && Root->getOpcode() == Shuffle)
20479 return false; // Nothing to do!
20481 switch (Mask.size()) {
20483 ShuffleVT = MVT::v8i16;
20486 ShuffleVT = MVT::v16i8;
20489 llvm_unreachable("Impossible mask size!");
20491 Op = DAG.getBitcast(ShuffleVT, Input);
20492 DCI.AddToWorklist(Op.getNode());
20493 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20494 DCI.AddToWorklist(Op.getNode());
20495 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20500 // Don't try to re-form single instruction chains under any circumstances now
20501 // that we've done encoding canonicalization for them.
20505 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20506 // can replace them with a single PSHUFB instruction profitably. Intel's
20507 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20508 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20509 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20510 SmallVector<SDValue, 16> PSHUFBMask;
20511 int NumBytes = VT.getSizeInBits() / 8;
20512 int Ratio = NumBytes / Mask.size();
20513 for (int i = 0; i < NumBytes; ++i) {
20514 if (Mask[i / Ratio] == SM_SentinelUndef) {
20515 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20518 int M = Mask[i / Ratio] != SM_SentinelZero
20519 ? Ratio * Mask[i / Ratio] + i % Ratio
20521 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20523 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20524 Op = DAG.getBitcast(ByteVT, Input);
20525 DCI.AddToWorklist(Op.getNode());
20526 SDValue PSHUFBMaskOp =
20527 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20528 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20529 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20530 DCI.AddToWorklist(Op.getNode());
20531 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20536 // Failed to find any combines.
20540 /// \brief Fully generic combining of x86 shuffle instructions.
20542 /// This should be the last combine run over the x86 shuffle instructions. Once
20543 /// they have been fully optimized, this will recursively consider all chains
20544 /// of single-use shuffle instructions, build a generic model of the cumulative
20545 /// shuffle operation, and check for simpler instructions which implement this
20546 /// operation. We use this primarily for two purposes:
20548 /// 1) Collapse generic shuffles to specialized single instructions when
20549 /// equivalent. In most cases, this is just an encoding size win, but
20550 /// sometimes we will collapse multiple generic shuffles into a single
20551 /// special-purpose shuffle.
20552 /// 2) Look for sequences of shuffle instructions with 3 or more total
20553 /// instructions, and replace them with the slightly more expensive SSSE3
20554 /// PSHUFB instruction if available. We do this as the last combining step
20555 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20556 /// a suitable short sequence of other instructions. The PHUFB will either
20557 /// use a register or have to read from memory and so is slightly (but only
20558 /// slightly) more expensive than the other shuffle instructions.
20560 /// Because this is inherently a quadratic operation (for each shuffle in
20561 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20562 /// This should never be an issue in practice as the shuffle lowering doesn't
20563 /// produce sequences of more than 8 instructions.
20565 /// FIXME: We will currently miss some cases where the redundant shuffling
20566 /// would simplify under the threshold for PSHUFB formation because of
20567 /// combine-ordering. To fix this, we should do the redundant instruction
20568 /// combining in this recursive walk.
20569 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20570 ArrayRef<int> RootMask,
20571 int Depth, bool HasPSHUFB,
20573 TargetLowering::DAGCombinerInfo &DCI,
20574 const X86Subtarget *Subtarget) {
20575 // Bound the depth of our recursive combine because this is ultimately
20576 // quadratic in nature.
20580 // Directly rip through bitcasts to find the underlying operand.
20581 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20582 Op = Op.getOperand(0);
20584 MVT VT = Op.getSimpleValueType();
20585 if (!VT.isVector())
20586 return false; // Bail if we hit a non-vector.
20588 assert(Root.getSimpleValueType().isVector() &&
20589 "Shuffles operate on vector types!");
20590 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20591 "Can only combine shuffles of the same vector register size.");
20593 if (!isTargetShuffle(Op.getOpcode()))
20595 SmallVector<int, 16> OpMask;
20597 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20598 // We only can combine unary shuffles which we can decode the mask for.
20599 if (!HaveMask || !IsUnary)
20602 assert(VT.getVectorNumElements() == OpMask.size() &&
20603 "Different mask size from vector size!");
20604 assert(((RootMask.size() > OpMask.size() &&
20605 RootMask.size() % OpMask.size() == 0) ||
20606 (OpMask.size() > RootMask.size() &&
20607 OpMask.size() % RootMask.size() == 0) ||
20608 OpMask.size() == RootMask.size()) &&
20609 "The smaller number of elements must divide the larger.");
20610 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
20611 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
20612 assert(((RootRatio == 1 && OpRatio == 1) ||
20613 (RootRatio == 1) != (OpRatio == 1)) &&
20614 "Must not have a ratio for both incoming and op masks!");
20616 SmallVector<int, 16> Mask;
20617 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
20619 // Merge this shuffle operation's mask into our accumulated mask. Note that
20620 // this shuffle's mask will be the first applied to the input, followed by the
20621 // root mask to get us all the way to the root value arrangement. The reason
20622 // for this order is that we are recursing up the operation chain.
20623 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
20624 int RootIdx = i / RootRatio;
20625 if (RootMask[RootIdx] < 0) {
20626 // This is a zero or undef lane, we're done.
20627 Mask.push_back(RootMask[RootIdx]);
20631 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
20632 int OpIdx = RootMaskedIdx / OpRatio;
20633 if (OpMask[OpIdx] < 0) {
20634 // The incoming lanes are zero or undef, it doesn't matter which ones we
20636 Mask.push_back(OpMask[OpIdx]);
20640 // Ok, we have non-zero lanes, map them through.
20641 Mask.push_back(OpMask[OpIdx] * OpRatio +
20642 RootMaskedIdx % OpRatio);
20645 // See if we can recurse into the operand to combine more things.
20646 switch (Op.getOpcode()) {
20647 case X86ISD::PSHUFB:
20649 case X86ISD::PSHUFD:
20650 case X86ISD::PSHUFHW:
20651 case X86ISD::PSHUFLW:
20652 if (Op.getOperand(0).hasOneUse() &&
20653 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20654 HasPSHUFB, DAG, DCI, Subtarget))
20658 case X86ISD::UNPCKL:
20659 case X86ISD::UNPCKH:
20660 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
20661 // We can't check for single use, we have to check that this shuffle is the only user.
20662 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
20663 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
20664 HasPSHUFB, DAG, DCI, Subtarget))
20669 // Minor canonicalization of the accumulated shuffle mask to make it easier
20670 // to match below. All this does is detect masks with squential pairs of
20671 // elements, and shrink them to the half-width mask. It does this in a loop
20672 // so it will reduce the size of the mask to the minimal width mask which
20673 // performs an equivalent shuffle.
20674 SmallVector<int, 16> WidenedMask;
20675 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
20676 Mask = std::move(WidenedMask);
20677 WidenedMask.clear();
20680 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
20684 /// \brief Get the PSHUF-style mask from PSHUF node.
20686 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
20687 /// PSHUF-style masks that can be reused with such instructions.
20688 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
20689 MVT VT = N.getSimpleValueType();
20690 SmallVector<int, 4> Mask;
20692 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
20696 // If we have more than 128-bits, only the low 128-bits of shuffle mask
20697 // matter. Check that the upper masks are repeats and remove them.
20698 if (VT.getSizeInBits() > 128) {
20699 int LaneElts = 128 / VT.getScalarSizeInBits();
20701 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
20702 for (int j = 0; j < LaneElts; ++j)
20703 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
20704 "Mask doesn't repeat in high 128-bit lanes!");
20706 Mask.resize(LaneElts);
20709 switch (N.getOpcode()) {
20710 case X86ISD::PSHUFD:
20712 case X86ISD::PSHUFLW:
20715 case X86ISD::PSHUFHW:
20716 Mask.erase(Mask.begin(), Mask.begin() + 4);
20717 for (int &M : Mask)
20721 llvm_unreachable("No valid shuffle instruction found!");
20725 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
20727 /// We walk up the chain and look for a combinable shuffle, skipping over
20728 /// shuffles that we could hoist this shuffle's transformation past without
20729 /// altering anything.
20731 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
20733 TargetLowering::DAGCombinerInfo &DCI) {
20734 assert(N.getOpcode() == X86ISD::PSHUFD &&
20735 "Called with something other than an x86 128-bit half shuffle!");
20738 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
20739 // of the shuffles in the chain so that we can form a fresh chain to replace
20741 SmallVector<SDValue, 8> Chain;
20742 SDValue V = N.getOperand(0);
20743 for (; V.hasOneUse(); V = V.getOperand(0)) {
20744 switch (V.getOpcode()) {
20746 return SDValue(); // Nothing combined!
20749 // Skip bitcasts as we always know the type for the target specific
20753 case X86ISD::PSHUFD:
20754 // Found another dword shuffle.
20757 case X86ISD::PSHUFLW:
20758 // Check that the low words (being shuffled) are the identity in the
20759 // dword shuffle, and the high words are self-contained.
20760 if (Mask[0] != 0 || Mask[1] != 1 ||
20761 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
20764 Chain.push_back(V);
20767 case X86ISD::PSHUFHW:
20768 // Check that the high words (being shuffled) are the identity in the
20769 // dword shuffle, and the low words are self-contained.
20770 if (Mask[2] != 2 || Mask[3] != 3 ||
20771 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
20774 Chain.push_back(V);
20777 case X86ISD::UNPCKL:
20778 case X86ISD::UNPCKH:
20779 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
20780 // shuffle into a preceding word shuffle.
20781 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
20782 V.getSimpleValueType().getScalarType() != MVT::i16)
20785 // Search for a half-shuffle which we can combine with.
20786 unsigned CombineOp =
20787 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
20788 if (V.getOperand(0) != V.getOperand(1) ||
20789 !V->isOnlyUserOf(V.getOperand(0).getNode()))
20791 Chain.push_back(V);
20792 V = V.getOperand(0);
20794 switch (V.getOpcode()) {
20796 return SDValue(); // Nothing to combine.
20798 case X86ISD::PSHUFLW:
20799 case X86ISD::PSHUFHW:
20800 if (V.getOpcode() == CombineOp)
20803 Chain.push_back(V);
20807 V = V.getOperand(0);
20811 } while (V.hasOneUse());
20814 // Break out of the loop if we break out of the switch.
20818 if (!V.hasOneUse())
20819 // We fell out of the loop without finding a viable combining instruction.
20822 // Merge this node's mask and our incoming mask.
20823 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20824 for (int &M : Mask)
20826 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
20827 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20829 // Rebuild the chain around this new shuffle.
20830 while (!Chain.empty()) {
20831 SDValue W = Chain.pop_back_val();
20833 if (V.getValueType() != W.getOperand(0).getValueType())
20834 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
20836 switch (W.getOpcode()) {
20838 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
20840 case X86ISD::UNPCKL:
20841 case X86ISD::UNPCKH:
20842 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
20845 case X86ISD::PSHUFD:
20846 case X86ISD::PSHUFLW:
20847 case X86ISD::PSHUFHW:
20848 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
20852 if (V.getValueType() != N.getValueType())
20853 V = DAG.getBitcast(N.getValueType(), V);
20855 // Return the new chain to replace N.
20859 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
20861 /// We walk up the chain, skipping shuffles of the other half and looking
20862 /// through shuffles which switch halves trying to find a shuffle of the same
20863 /// pair of dwords.
20864 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
20866 TargetLowering::DAGCombinerInfo &DCI) {
20868 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
20869 "Called with something other than an x86 128-bit half shuffle!");
20871 unsigned CombineOpcode = N.getOpcode();
20873 // Walk up a single-use chain looking for a combinable shuffle.
20874 SDValue V = N.getOperand(0);
20875 for (; V.hasOneUse(); V = V.getOperand(0)) {
20876 switch (V.getOpcode()) {
20878 return false; // Nothing combined!
20881 // Skip bitcasts as we always know the type for the target specific
20885 case X86ISD::PSHUFLW:
20886 case X86ISD::PSHUFHW:
20887 if (V.getOpcode() == CombineOpcode)
20890 // Other-half shuffles are no-ops.
20893 // Break out of the loop if we break out of the switch.
20897 if (!V.hasOneUse())
20898 // We fell out of the loop without finding a viable combining instruction.
20901 // Combine away the bottom node as its shuffle will be accumulated into
20902 // a preceding shuffle.
20903 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20905 // Record the old value.
20908 // Merge this node's mask and our incoming mask (adjusted to account for all
20909 // the pshufd instructions encountered).
20910 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20911 for (int &M : Mask)
20913 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
20914 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
20916 // Check that the shuffles didn't cancel each other out. If not, we need to
20917 // combine to the new one.
20919 // Replace the combinable shuffle with the combined one, updating all users
20920 // so that we re-evaluate the chain here.
20921 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
20926 /// \brief Try to combine x86 target specific shuffles.
20927 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
20928 TargetLowering::DAGCombinerInfo &DCI,
20929 const X86Subtarget *Subtarget) {
20931 MVT VT = N.getSimpleValueType();
20932 SmallVector<int, 4> Mask;
20934 switch (N.getOpcode()) {
20935 case X86ISD::PSHUFD:
20936 case X86ISD::PSHUFLW:
20937 case X86ISD::PSHUFHW:
20938 Mask = getPSHUFShuffleMask(N);
20939 assert(Mask.size() == 4);
20945 // Nuke no-op shuffles that show up after combining.
20946 if (isNoopShuffleMask(Mask))
20947 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
20949 // Look for simplifications involving one or two shuffle instructions.
20950 SDValue V = N.getOperand(0);
20951 switch (N.getOpcode()) {
20954 case X86ISD::PSHUFLW:
20955 case X86ISD::PSHUFHW:
20956 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
20958 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
20959 return SDValue(); // We combined away this shuffle, so we're done.
20961 // See if this reduces to a PSHUFD which is no more expensive and can
20962 // combine with more operations. Note that it has to at least flip the
20963 // dwords as otherwise it would have been removed as a no-op.
20964 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
20965 int DMask[] = {0, 1, 2, 3};
20966 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
20967 DMask[DOffset + 0] = DOffset + 1;
20968 DMask[DOffset + 1] = DOffset + 0;
20969 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
20970 V = DAG.getBitcast(DVT, V);
20971 DCI.AddToWorklist(V.getNode());
20972 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
20973 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
20974 DCI.AddToWorklist(V.getNode());
20975 return DAG.getBitcast(VT, V);
20978 // Look for shuffle patterns which can be implemented as a single unpack.
20979 // FIXME: This doesn't handle the location of the PSHUFD generically, and
20980 // only works when we have a PSHUFD followed by two half-shuffles.
20981 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
20982 (V.getOpcode() == X86ISD::PSHUFLW ||
20983 V.getOpcode() == X86ISD::PSHUFHW) &&
20984 V.getOpcode() != N.getOpcode() &&
20986 SDValue D = V.getOperand(0);
20987 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
20988 D = D.getOperand(0);
20989 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
20990 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
20991 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
20992 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20993 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
20995 for (int i = 0; i < 4; ++i) {
20996 WordMask[i + NOffset] = Mask[i] + NOffset;
20997 WordMask[i + VOffset] = VMask[i] + VOffset;
20999 // Map the word mask through the DWord mask.
21001 for (int i = 0; i < 8; ++i)
21002 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21003 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21004 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
21005 // We can replace all three shuffles with an unpack.
21006 V = DAG.getBitcast(VT, D.getOperand(0));
21007 DCI.AddToWorklist(V.getNode());
21008 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21017 case X86ISD::PSHUFD:
21018 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21027 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21029 /// We combine this directly on the abstract vector shuffle nodes so it is
21030 /// easier to generically match. We also insert dummy vector shuffle nodes for
21031 /// the operands which explicitly discard the lanes which are unused by this
21032 /// operation to try to flow through the rest of the combiner the fact that
21033 /// they're unused.
21034 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21036 EVT VT = N->getValueType(0);
21038 // We only handle target-independent shuffles.
21039 // FIXME: It would be easy and harmless to use the target shuffle mask
21040 // extraction tool to support more.
21041 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21044 auto *SVN = cast<ShuffleVectorSDNode>(N);
21045 ArrayRef<int> Mask = SVN->getMask();
21046 SDValue V1 = N->getOperand(0);
21047 SDValue V2 = N->getOperand(1);
21049 // We require the first shuffle operand to be the SUB node, and the second to
21050 // be the ADD node.
21051 // FIXME: We should support the commuted patterns.
21052 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21055 // If there are other uses of these operations we can't fold them.
21056 if (!V1->hasOneUse() || !V2->hasOneUse())
21059 // Ensure that both operations have the same operands. Note that we can
21060 // commute the FADD operands.
21061 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21062 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21063 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21066 // We're looking for blends between FADD and FSUB nodes. We insist on these
21067 // nodes being lined up in a specific expected pattern.
21068 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
21069 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
21070 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
21073 // Only specific types are legal at this point, assert so we notice if and
21074 // when these change.
21075 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21076 VT == MVT::v4f64) &&
21077 "Unknown vector type encountered!");
21079 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21082 /// PerformShuffleCombine - Performs several different shuffle combines.
21083 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21084 TargetLowering::DAGCombinerInfo &DCI,
21085 const X86Subtarget *Subtarget) {
21087 SDValue N0 = N->getOperand(0);
21088 SDValue N1 = N->getOperand(1);
21089 EVT VT = N->getValueType(0);
21091 // Don't create instructions with illegal types after legalize types has run.
21092 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21093 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21096 // If we have legalized the vector types, look for blends of FADD and FSUB
21097 // nodes that we can fuse into an ADDSUB node.
21098 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21099 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21102 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21103 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21104 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21105 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21107 // During Type Legalization, when promoting illegal vector types,
21108 // the backend might introduce new shuffle dag nodes and bitcasts.
21110 // This code performs the following transformation:
21111 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21112 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21114 // We do this only if both the bitcast and the BINOP dag nodes have
21115 // one use. Also, perform this transformation only if the new binary
21116 // operation is legal. This is to avoid introducing dag nodes that
21117 // potentially need to be further expanded (or custom lowered) into a
21118 // less optimal sequence of dag nodes.
21119 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21120 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21121 N0.getOpcode() == ISD::BITCAST) {
21122 SDValue BC0 = N0.getOperand(0);
21123 EVT SVT = BC0.getValueType();
21124 unsigned Opcode = BC0.getOpcode();
21125 unsigned NumElts = VT.getVectorNumElements();
21127 if (BC0.hasOneUse() && SVT.isVector() &&
21128 SVT.getVectorNumElements() * 2 == NumElts &&
21129 TLI.isOperationLegal(Opcode, VT)) {
21130 bool CanFold = false;
21142 unsigned SVTNumElts = SVT.getVectorNumElements();
21143 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21144 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21145 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21146 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21147 CanFold = SVOp->getMaskElt(i) < 0;
21150 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
21151 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
21152 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21153 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21158 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21159 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21160 // consecutive, non-overlapping, and in the right order.
21161 SmallVector<SDValue, 16> Elts;
21162 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21163 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21165 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
21168 if (isTargetShuffle(N->getOpcode())) {
21170 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21171 if (Shuffle.getNode())
21174 // Try recursively combining arbitrary sequences of x86 shuffle
21175 // instructions into higher-order shuffles. We do this after combining
21176 // specific PSHUF instruction sequences into their minimal form so that we
21177 // can evaluate how many specialized shuffle instructions are involved in
21178 // a particular chain.
21179 SmallVector<int, 1> NonceMask; // Just a placeholder.
21180 NonceMask.push_back(0);
21181 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21182 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21184 return SDValue(); // This routine will use CombineTo to replace N.
21190 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21191 /// specific shuffle of a load can be folded into a single element load.
21192 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21193 /// shuffles have been custom lowered so we need to handle those here.
21194 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21195 TargetLowering::DAGCombinerInfo &DCI) {
21196 if (DCI.isBeforeLegalizeOps())
21199 SDValue InVec = N->getOperand(0);
21200 SDValue EltNo = N->getOperand(1);
21202 if (!isa<ConstantSDNode>(EltNo))
21205 EVT OriginalVT = InVec.getValueType();
21207 if (InVec.getOpcode() == ISD::BITCAST) {
21208 // Don't duplicate a load with other uses.
21209 if (!InVec.hasOneUse())
21211 EVT BCVT = InVec.getOperand(0).getValueType();
21212 if (!BCVT.isVector() ||
21213 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21215 InVec = InVec.getOperand(0);
21218 EVT CurrentVT = InVec.getValueType();
21220 if (!isTargetShuffle(InVec.getOpcode()))
21223 // Don't duplicate a load with other uses.
21224 if (!InVec.hasOneUse())
21227 SmallVector<int, 16> ShuffleMask;
21229 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21230 ShuffleMask, UnaryShuffle))
21233 // Select the input vector, guarding against out of range extract vector.
21234 unsigned NumElems = CurrentVT.getVectorNumElements();
21235 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21236 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21237 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21238 : InVec.getOperand(1);
21240 // If inputs to shuffle are the same for both ops, then allow 2 uses
21241 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21242 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21244 if (LdNode.getOpcode() == ISD::BITCAST) {
21245 // Don't duplicate a load with other uses.
21246 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21249 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21250 LdNode = LdNode.getOperand(0);
21253 if (!ISD::isNormalLoad(LdNode.getNode()))
21256 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21258 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21261 EVT EltVT = N->getValueType(0);
21262 // If there's a bitcast before the shuffle, check if the load type and
21263 // alignment is valid.
21264 unsigned Align = LN0->getAlignment();
21265 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21266 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21267 EltVT.getTypeForEVT(*DAG.getContext()));
21269 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21272 // All checks match so transform back to vector_shuffle so that DAG combiner
21273 // can finish the job
21276 // Create shuffle node taking into account the case that its a unary shuffle
21277 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21278 : InVec.getOperand(1);
21279 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21280 InVec.getOperand(0), Shuffle,
21282 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
21283 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21287 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21288 /// special and don't usually play with other vector types, it's better to
21289 /// handle them early to be sure we emit efficient code by avoiding
21290 /// store-load conversions.
21291 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21292 if (N->getValueType(0) != MVT::x86mmx ||
21293 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21294 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21297 SDValue V = N->getOperand(0);
21298 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21299 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21300 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21301 N->getValueType(0), V.getOperand(0));
21306 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21307 /// generation and convert it from being a bunch of shuffles and extracts
21308 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21309 /// storing the value and loading scalars back, while for x64 we should
21310 /// use 64-bit extracts and shifts.
21311 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21312 TargetLowering::DAGCombinerInfo &DCI) {
21313 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
21316 SDValue InputVector = N->getOperand(0);
21317 SDLoc dl(InputVector);
21318 // Detect mmx to i32 conversion through a v2i32 elt extract.
21319 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21320 N->getValueType(0) == MVT::i32 &&
21321 InputVector.getValueType() == MVT::v2i32) {
21323 // The bitcast source is a direct mmx result.
21324 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21325 if (MMXSrc.getValueType() == MVT::x86mmx)
21326 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21327 N->getValueType(0),
21328 InputVector.getNode()->getOperand(0));
21330 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21331 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21332 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21333 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21334 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21335 MMXSrcOp.getValueType() == MVT::v1i64 &&
21336 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21337 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21338 N->getValueType(0),
21339 MMXSrcOp.getOperand(0));
21342 EVT VT = N->getValueType(0);
21344 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21345 InputVector.getOpcode() == ISD::BITCAST &&
21346 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21347 uint64_t ExtractedElt =
21348 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21349 uint64_t InputValue =
21350 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21351 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21352 return DAG.getConstant(Res, dl, MVT::i1);
21354 // Only operate on vectors of 4 elements, where the alternative shuffling
21355 // gets to be more expensive.
21356 if (InputVector.getValueType() != MVT::v4i32)
21359 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21360 // single use which is a sign-extend or zero-extend, and all elements are
21362 SmallVector<SDNode *, 4> Uses;
21363 unsigned ExtractedElements = 0;
21364 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21365 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21366 if (UI.getUse().getResNo() != InputVector.getResNo())
21369 SDNode *Extract = *UI;
21370 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21373 if (Extract->getValueType(0) != MVT::i32)
21375 if (!Extract->hasOneUse())
21377 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21378 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21380 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21383 // Record which element was extracted.
21384 ExtractedElements |=
21385 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21387 Uses.push_back(Extract);
21390 // If not all the elements were used, this may not be worthwhile.
21391 if (ExtractedElements != 15)
21394 // Ok, we've now decided to do the transformation.
21395 // If 64-bit shifts are legal, use the extract-shift sequence,
21396 // otherwise bounce the vector off the cache.
21397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21400 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21401 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
21402 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21403 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21404 DAG.getConstant(0, dl, VecIdxTy));
21405 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21406 DAG.getConstant(1, dl, VecIdxTy));
21408 SDValue ShAmt = DAG.getConstant(32, dl,
21409 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21410 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21411 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21412 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21413 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21414 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21415 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21417 // Store the value to a temporary stack slot.
21418 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21419 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21420 MachinePointerInfo(), false, false, 0);
21422 EVT ElementType = InputVector.getValueType().getVectorElementType();
21423 unsigned EltSize = ElementType.getSizeInBits() / 8;
21425 // Replace each use (extract) with a load of the appropriate element.
21426 for (unsigned i = 0; i < 4; ++i) {
21427 uint64_t Offset = EltSize * i;
21428 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21430 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21431 StackPtr, OffsetVal);
21433 // Load the scalar.
21434 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21435 ScalarAddr, MachinePointerInfo(),
21436 false, false, false, 0);
21441 // Replace the extracts
21442 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21443 UE = Uses.end(); UI != UE; ++UI) {
21444 SDNode *Extract = *UI;
21446 SDValue Idx = Extract->getOperand(1);
21447 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21448 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21451 // The replacement was made in place; don't return anything.
21455 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21456 static std::pair<unsigned, bool>
21457 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21458 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21459 if (!VT.isVector())
21460 return std::make_pair(0, false);
21462 bool NeedSplit = false;
21463 switch (VT.getSimpleVT().SimpleTy) {
21464 default: return std::make_pair(0, false);
21467 if (!Subtarget->hasVLX())
21468 return std::make_pair(0, false);
21472 if (!Subtarget->hasBWI())
21473 return std::make_pair(0, false);
21477 if (!Subtarget->hasAVX512())
21478 return std::make_pair(0, false);
21483 if (!Subtarget->hasAVX2())
21485 if (!Subtarget->hasAVX())
21486 return std::make_pair(0, false);
21491 if (!Subtarget->hasSSE2())
21492 return std::make_pair(0, false);
21495 // SSE2 has only a small subset of the operations.
21496 bool hasUnsigned = Subtarget->hasSSE41() ||
21497 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21498 bool hasSigned = Subtarget->hasSSE41() ||
21499 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21501 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21504 // Check for x CC y ? x : y.
21505 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21506 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21511 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21514 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21517 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21520 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21522 // Check for x CC y ? y : x -- a min/max with reversed arms.
21523 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21524 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21529 Opc = hasUnsigned ? X86ISD::UMAX : 0u; break;
21532 Opc = hasUnsigned ? X86ISD::UMIN : 0u; break;
21535 Opc = hasSigned ? X86ISD::SMAX : 0u; break;
21538 Opc = hasSigned ? X86ISD::SMIN : 0u; break;
21542 return std::make_pair(Opc, NeedSplit);
21546 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21547 const X86Subtarget *Subtarget) {
21549 SDValue Cond = N->getOperand(0);
21550 SDValue LHS = N->getOperand(1);
21551 SDValue RHS = N->getOperand(2);
21553 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21554 SDValue CondSrc = Cond->getOperand(0);
21555 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21556 Cond = CondSrc->getOperand(0);
21559 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21562 // A vselect where all conditions and data are constants can be optimized into
21563 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21564 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21565 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21568 unsigned MaskValue = 0;
21569 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21572 MVT VT = N->getSimpleValueType(0);
21573 unsigned NumElems = VT.getVectorNumElements();
21574 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21575 for (unsigned i = 0; i < NumElems; ++i) {
21576 // Be sure we emit undef where we can.
21577 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21578 ShuffleMask[i] = -1;
21580 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21583 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21584 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21586 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21589 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21591 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21592 TargetLowering::DAGCombinerInfo &DCI,
21593 const X86Subtarget *Subtarget) {
21595 SDValue Cond = N->getOperand(0);
21596 // Get the LHS/RHS of the select.
21597 SDValue LHS = N->getOperand(1);
21598 SDValue RHS = N->getOperand(2);
21599 EVT VT = LHS.getValueType();
21600 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21602 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
21603 // instructions match the semantics of the common C idiom x<y?x:y but not
21604 // x<=y?x:y, because of how they handle negative zero (which can be
21605 // ignored in unsafe-math mode).
21606 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
21607 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
21608 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
21609 (Subtarget->hasSSE2() ||
21610 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
21611 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21613 unsigned Opcode = 0;
21614 // Check for x CC y ? x : y.
21615 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21616 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21620 // Converting this to a min would handle NaNs incorrectly, and swapping
21621 // the operands would cause it to handle comparisons between positive
21622 // and negative zero incorrectly.
21623 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21624 if (!DAG.getTarget().Options.UnsafeFPMath &&
21625 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21627 std::swap(LHS, RHS);
21629 Opcode = X86ISD::FMIN;
21632 // Converting this to a min would handle comparisons between positive
21633 // and negative zero incorrectly.
21634 if (!DAG.getTarget().Options.UnsafeFPMath &&
21635 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21637 Opcode = X86ISD::FMIN;
21640 // Converting this to a min would handle both negative zeros and NaNs
21641 // incorrectly, but we can swap the operands to fix both.
21642 std::swap(LHS, RHS);
21646 Opcode = X86ISD::FMIN;
21650 // Converting this to a max would handle comparisons between positive
21651 // and negative zero incorrectly.
21652 if (!DAG.getTarget().Options.UnsafeFPMath &&
21653 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
21655 Opcode = X86ISD::FMAX;
21658 // Converting this to a max would handle NaNs incorrectly, and swapping
21659 // the operands would cause it to handle comparisons between positive
21660 // and negative zero incorrectly.
21661 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
21662 if (!DAG.getTarget().Options.UnsafeFPMath &&
21663 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
21665 std::swap(LHS, RHS);
21667 Opcode = X86ISD::FMAX;
21670 // Converting this to a max would handle both negative zeros and NaNs
21671 // incorrectly, but we can swap the operands to fix both.
21672 std::swap(LHS, RHS);
21676 Opcode = X86ISD::FMAX;
21679 // Check for x CC y ? y : x -- a min/max with reversed arms.
21680 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21681 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21685 // Converting this to a min would handle comparisons between positive
21686 // and negative zero incorrectly, and swapping the operands would
21687 // cause it to handle NaNs incorrectly.
21688 if (!DAG.getTarget().Options.UnsafeFPMath &&
21689 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
21690 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21692 std::swap(LHS, RHS);
21694 Opcode = X86ISD::FMIN;
21697 // Converting this to a min would handle NaNs incorrectly.
21698 if (!DAG.getTarget().Options.UnsafeFPMath &&
21699 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
21701 Opcode = X86ISD::FMIN;
21704 // Converting this to a min would handle both negative zeros and NaNs
21705 // incorrectly, but we can swap the operands to fix both.
21706 std::swap(LHS, RHS);
21710 Opcode = X86ISD::FMIN;
21714 // Converting this to a max would handle NaNs incorrectly.
21715 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21717 Opcode = X86ISD::FMAX;
21720 // Converting this to a max would handle comparisons between positive
21721 // and negative zero incorrectly, and swapping the operands would
21722 // cause it to handle NaNs incorrectly.
21723 if (!DAG.getTarget().Options.UnsafeFPMath &&
21724 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
21725 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
21727 std::swap(LHS, RHS);
21729 Opcode = X86ISD::FMAX;
21732 // Converting this to a max would handle both negative zeros and NaNs
21733 // incorrectly, but we can swap the operands to fix both.
21734 std::swap(LHS, RHS);
21738 Opcode = X86ISD::FMAX;
21744 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
21747 EVT CondVT = Cond.getValueType();
21748 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
21749 CondVT.getVectorElementType() == MVT::i1) {
21750 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
21751 // lowering on KNL. In this case we convert it to
21752 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
21753 // The same situation for all 128 and 256-bit vectors of i8 and i16.
21754 // Since SKX these selects have a proper lowering.
21755 EVT OpVT = LHS.getValueType();
21756 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
21757 (OpVT.getVectorElementType() == MVT::i8 ||
21758 OpVT.getVectorElementType() == MVT::i16) &&
21759 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
21760 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
21761 DCI.AddToWorklist(Cond.getNode());
21762 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
21765 // If this is a select between two integer constants, try to do some
21767 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
21768 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
21769 // Don't do this for crazy integer types.
21770 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
21771 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
21772 // so that TrueC (the true value) is larger than FalseC.
21773 bool NeedsCondInvert = false;
21775 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
21776 // Efficiently invertible.
21777 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
21778 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
21779 isa<ConstantSDNode>(Cond.getOperand(1))))) {
21780 NeedsCondInvert = true;
21781 std::swap(TrueC, FalseC);
21784 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
21785 if (FalseC->getAPIntValue() == 0 &&
21786 TrueC->getAPIntValue().isPowerOf2()) {
21787 if (NeedsCondInvert) // Invert the condition if needed.
21788 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21789 DAG.getConstant(1, DL, Cond.getValueType()));
21791 // Zero extend the condition if needed.
21792 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
21794 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
21795 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
21796 DAG.getConstant(ShAmt, DL, MVT::i8));
21799 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
21800 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
21801 if (NeedsCondInvert) // Invert the condition if needed.
21802 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21803 DAG.getConstant(1, DL, Cond.getValueType()));
21805 // Zero extend the condition if needed.
21806 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
21807 FalseC->getValueType(0), Cond);
21808 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21809 SDValue(FalseC, 0));
21812 // Optimize cases that will turn into an LEA instruction. This requires
21813 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
21814 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
21815 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
21816 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
21818 bool isFastMultiplier = false;
21820 switch ((unsigned char)Diff) {
21822 case 1: // result = add base, cond
21823 case 2: // result = lea base( , cond*2)
21824 case 3: // result = lea base(cond, cond*2)
21825 case 4: // result = lea base( , cond*4)
21826 case 5: // result = lea base(cond, cond*4)
21827 case 8: // result = lea base( , cond*8)
21828 case 9: // result = lea base(cond, cond*8)
21829 isFastMultiplier = true;
21834 if (isFastMultiplier) {
21835 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
21836 if (NeedsCondInvert) // Invert the condition if needed.
21837 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
21838 DAG.getConstant(1, DL, Cond.getValueType()));
21840 // Zero extend the condition if needed.
21841 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
21843 // Scale the condition by the difference.
21845 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
21846 DAG.getConstant(Diff, DL,
21847 Cond.getValueType()));
21849 // Add the base if non-zero.
21850 if (FalseC->getAPIntValue() != 0)
21851 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
21852 SDValue(FalseC, 0));
21859 // Canonicalize max and min:
21860 // (x > y) ? x : y -> (x >= y) ? x : y
21861 // (x < y) ? x : y -> (x <= y) ? x : y
21862 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
21863 // the need for an extra compare
21864 // against zero. e.g.
21865 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
21867 // testl %edi, %edi
21869 // cmovgl %edi, %eax
21873 // cmovsl %eax, %edi
21874 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
21875 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21876 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21877 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21882 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
21883 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
21884 Cond.getOperand(0), Cond.getOperand(1), NewCC);
21885 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
21890 // Early exit check
21891 if (!TLI.isTypeLegal(VT))
21894 // Match VSELECTs into subs with unsigned saturation.
21895 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
21896 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
21897 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
21898 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
21899 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21901 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
21902 // left side invert the predicate to simplify logic below.
21904 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
21906 CC = ISD::getSetCCInverse(CC, true);
21907 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
21911 if (Other.getNode() && Other->getNumOperands() == 2 &&
21912 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
21913 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
21914 SDValue CondRHS = Cond->getOperand(1);
21916 // Look for a general sub with unsigned saturation first.
21917 // x >= y ? x-y : 0 --> subus x, y
21918 // x > y ? x-y : 0 --> subus x, y
21919 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
21920 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
21921 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
21923 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
21924 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
21925 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
21926 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
21927 // If the RHS is a constant we have to reverse the const
21928 // canonicalization.
21929 // x > C-1 ? x+-C : 0 --> subus x, C
21930 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
21931 CondRHSConst->getAPIntValue() ==
21932 (-OpRHSConst->getAPIntValue() - 1))
21933 return DAG.getNode(
21934 X86ISD::SUBUS, DL, VT, OpLHS,
21935 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
21937 // Another special case: If C was a sign bit, the sub has been
21938 // canonicalized into a xor.
21939 // FIXME: Would it be better to use computeKnownBits to determine
21940 // whether it's safe to decanonicalize the xor?
21941 // x s< 0 ? x^C : 0 --> subus x, C
21942 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
21943 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
21944 OpRHSConst->getAPIntValue().isSignBit())
21945 // Note that we have to rebuild the RHS constant here to ensure we
21946 // don't rely on particular values of undef lanes.
21947 return DAG.getNode(
21948 X86ISD::SUBUS, DL, VT, OpLHS,
21949 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
21954 // Try to match a min/max vector operation.
21955 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
21956 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
21957 unsigned Opc = ret.first;
21958 bool NeedSplit = ret.second;
21960 if (Opc && NeedSplit) {
21961 unsigned NumElems = VT.getVectorNumElements();
21962 // Extract the LHS vectors
21963 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
21964 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
21966 // Extract the RHS vectors
21967 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
21968 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
21970 // Create min/max for each subvector
21971 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
21972 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
21974 // Merge the result
21975 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
21977 return DAG.getNode(Opc, DL, VT, LHS, RHS);
21980 // Simplify vector selection if condition value type matches vselect
21982 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
21983 assert(Cond.getValueType().isVector() &&
21984 "vector select expects a vector selector!");
21986 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
21987 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
21989 // Try invert the condition if true value is not all 1s and false value
21991 if (!TValIsAllOnes && !FValIsAllZeros &&
21992 // Check if the selector will be produced by CMPP*/PCMP*
21993 Cond.getOpcode() == ISD::SETCC &&
21994 // Check if SETCC has already been promoted
21995 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
21996 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
21997 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
21999 if (TValIsAllZeros || FValIsAllOnes) {
22000 SDValue CC = Cond.getOperand(2);
22001 ISD::CondCode NewCC =
22002 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22003 Cond.getOperand(0).getValueType().isInteger());
22004 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22005 std::swap(LHS, RHS);
22006 TValIsAllOnes = FValIsAllOnes;
22007 FValIsAllZeros = TValIsAllZeros;
22011 if (TValIsAllOnes || FValIsAllZeros) {
22014 if (TValIsAllOnes && FValIsAllZeros)
22016 else if (TValIsAllOnes)
22018 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
22019 else if (FValIsAllZeros)
22020 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22021 DAG.getBitcast(CondVT, LHS));
22023 return DAG.getBitcast(VT, Ret);
22027 // We should generate an X86ISD::BLENDI from a vselect if its argument
22028 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22029 // constants. This specific pattern gets generated when we split a
22030 // selector for a 512 bit vector in a machine without AVX512 (but with
22031 // 256-bit vectors), during legalization:
22033 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22035 // Iff we find this pattern and the build_vectors are built from
22036 // constants, we translate the vselect into a shuffle_vector that we
22037 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22038 if ((N->getOpcode() == ISD::VSELECT ||
22039 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22040 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
22041 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22042 if (Shuffle.getNode())
22046 // If this is a *dynamic* select (non-constant condition) and we can match
22047 // this node with one of the variable blend instructions, restructure the
22048 // condition so that the blends can use the high bit of each element and use
22049 // SimplifyDemandedBits to simplify the condition operand.
22050 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22051 !DCI.isBeforeLegalize() &&
22052 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22053 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22055 // Don't optimize vector selects that map to mask-registers.
22059 // We can only handle the cases where VSELECT is directly legal on the
22060 // subtarget. We custom lower VSELECT nodes with constant conditions and
22061 // this makes it hard to see whether a dynamic VSELECT will correctly
22062 // lower, so we both check the operation's status and explicitly handle the
22063 // cases where a *dynamic* blend will fail even though a constant-condition
22064 // blend could be custom lowered.
22065 // FIXME: We should find a better way to handle this class of problems.
22066 // Potentially, we should combine constant-condition vselect nodes
22067 // pre-legalization into shuffles and not mark as many types as custom
22069 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
22071 // FIXME: We don't support i16-element blends currently. We could and
22072 // should support them by making *all* the bits in the condition be set
22073 // rather than just the high bit and using an i8-element blend.
22074 if (VT.getScalarType() == MVT::i16)
22076 // Dynamic blending was only available from SSE4.1 onward.
22077 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
22079 // Byte blends are only available in AVX2
22080 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
22081 !Subtarget->hasAVX2())
22084 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22085 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22087 APInt KnownZero, KnownOne;
22088 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22089 DCI.isBeforeLegalizeOps());
22090 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22091 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22093 // If we changed the computation somewhere in the DAG, this change
22094 // will affect all users of Cond.
22095 // Make sure it is fine and update all the nodes so that we do not
22096 // use the generic VSELECT anymore. Otherwise, we may perform
22097 // wrong optimizations as we messed up with the actual expectation
22098 // for the vector boolean values.
22099 if (Cond != TLO.Old) {
22100 // Check all uses of that condition operand to check whether it will be
22101 // consumed by non-BLEND instructions, which may depend on all bits are
22103 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22105 if (I->getOpcode() != ISD::VSELECT)
22106 // TODO: Add other opcodes eventually lowered into BLEND.
22109 // Update all the users of the condition, before committing the change,
22110 // so that the VSELECT optimizations that expect the correct vector
22111 // boolean value will not be triggered.
22112 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22114 DAG.ReplaceAllUsesOfValueWith(
22116 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22117 Cond, I->getOperand(1), I->getOperand(2)));
22118 DCI.CommitTargetLoweringOpt(TLO);
22121 // At this point, only Cond is changed. Change the condition
22122 // just for N to keep the opportunity to optimize all other
22123 // users their own way.
22124 DAG.ReplaceAllUsesOfValueWith(
22126 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22127 TLO.New, N->getOperand(1), N->getOperand(2)));
22135 // Check whether a boolean test is testing a boolean value generated by
22136 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22139 // Simplify the following patterns:
22140 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22141 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22142 // to (Op EFLAGS Cond)
22144 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22145 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22146 // to (Op EFLAGS !Cond)
22148 // where Op could be BRCOND or CMOV.
22150 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22151 // Quit if not CMP and SUB with its value result used.
22152 if (Cmp.getOpcode() != X86ISD::CMP &&
22153 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22156 // Quit if not used as a boolean value.
22157 if (CC != X86::COND_E && CC != X86::COND_NE)
22160 // Check CMP operands. One of them should be 0 or 1 and the other should be
22161 // an SetCC or extended from it.
22162 SDValue Op1 = Cmp.getOperand(0);
22163 SDValue Op2 = Cmp.getOperand(1);
22166 const ConstantSDNode* C = nullptr;
22167 bool needOppositeCond = (CC == X86::COND_E);
22168 bool checkAgainstTrue = false; // Is it a comparison against 1?
22170 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22172 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22174 else // Quit if all operands are not constants.
22177 if (C->getZExtValue() == 1) {
22178 needOppositeCond = !needOppositeCond;
22179 checkAgainstTrue = true;
22180 } else if (C->getZExtValue() != 0)
22181 // Quit if the constant is neither 0 or 1.
22184 bool truncatedToBoolWithAnd = false;
22185 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22186 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22187 SetCC.getOpcode() == ISD::TRUNCATE ||
22188 SetCC.getOpcode() == ISD::AND) {
22189 if (SetCC.getOpcode() == ISD::AND) {
22191 ConstantSDNode *CS;
22192 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22193 CS->getZExtValue() == 1)
22195 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22196 CS->getZExtValue() == 1)
22200 SetCC = SetCC.getOperand(OpIdx);
22201 truncatedToBoolWithAnd = true;
22203 SetCC = SetCC.getOperand(0);
22206 switch (SetCC.getOpcode()) {
22207 case X86ISD::SETCC_CARRY:
22208 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22209 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22210 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22211 // truncated to i1 using 'and'.
22212 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22214 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22215 "Invalid use of SETCC_CARRY!");
22217 case X86ISD::SETCC:
22218 // Set the condition code or opposite one if necessary.
22219 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22220 if (needOppositeCond)
22221 CC = X86::GetOppositeBranchCondition(CC);
22222 return SetCC.getOperand(1);
22223 case X86ISD::CMOV: {
22224 // Check whether false/true value has canonical one, i.e. 0 or 1.
22225 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22226 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22227 // Quit if true value is not a constant.
22230 // Quit if false value is not a constant.
22232 SDValue Op = SetCC.getOperand(0);
22233 // Skip 'zext' or 'trunc' node.
22234 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22235 Op.getOpcode() == ISD::TRUNCATE)
22236 Op = Op.getOperand(0);
22237 // A special case for rdrand/rdseed, where 0 is set if false cond is
22239 if ((Op.getOpcode() != X86ISD::RDRAND &&
22240 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22243 // Quit if false value is not the constant 0 or 1.
22244 bool FValIsFalse = true;
22245 if (FVal && FVal->getZExtValue() != 0) {
22246 if (FVal->getZExtValue() != 1)
22248 // If FVal is 1, opposite cond is needed.
22249 needOppositeCond = !needOppositeCond;
22250 FValIsFalse = false;
22252 // Quit if TVal is not the constant opposite of FVal.
22253 if (FValIsFalse && TVal->getZExtValue() != 1)
22255 if (!FValIsFalse && TVal->getZExtValue() != 0)
22257 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22258 if (needOppositeCond)
22259 CC = X86::GetOppositeBranchCondition(CC);
22260 return SetCC.getOperand(3);
22267 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22269 /// (X86or (X86setcc) (X86setcc))
22270 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22271 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22272 X86::CondCode &CC1, SDValue &Flags,
22274 if (Cond->getOpcode() == X86ISD::CMP) {
22275 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22276 if (!CondOp1C || !CondOp1C->isNullValue())
22279 Cond = Cond->getOperand(0);
22284 SDValue SetCC0, SetCC1;
22285 switch (Cond->getOpcode()) {
22286 default: return false;
22293 SetCC0 = Cond->getOperand(0);
22294 SetCC1 = Cond->getOperand(1);
22298 // Make sure we have SETCC nodes, using the same flags value.
22299 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22300 SetCC1.getOpcode() != X86ISD::SETCC ||
22301 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22304 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22305 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22306 Flags = SetCC0->getOperand(1);
22310 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22311 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22312 TargetLowering::DAGCombinerInfo &DCI,
22313 const X86Subtarget *Subtarget) {
22316 // If the flag operand isn't dead, don't touch this CMOV.
22317 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22320 SDValue FalseOp = N->getOperand(0);
22321 SDValue TrueOp = N->getOperand(1);
22322 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22323 SDValue Cond = N->getOperand(3);
22325 if (CC == X86::COND_E || CC == X86::COND_NE) {
22326 switch (Cond.getOpcode()) {
22330 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22331 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22332 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22338 Flags = checkBoolTestSetCCCombine(Cond, CC);
22339 if (Flags.getNode() &&
22340 // Extra check as FCMOV only supports a subset of X86 cond.
22341 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22342 SDValue Ops[] = { FalseOp, TrueOp,
22343 DAG.getConstant(CC, DL, MVT::i8), Flags };
22344 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22347 // If this is a select between two integer constants, try to do some
22348 // optimizations. Note that the operands are ordered the opposite of SELECT
22350 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22351 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22352 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22353 // larger than FalseC (the false value).
22354 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22355 CC = X86::GetOppositeBranchCondition(CC);
22356 std::swap(TrueC, FalseC);
22357 std::swap(TrueOp, FalseOp);
22360 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22361 // This is efficient for any integer data type (including i8/i16) and
22363 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22364 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22365 DAG.getConstant(CC, DL, MVT::i8), Cond);
22367 // Zero extend the condition if needed.
22368 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22370 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22371 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22372 DAG.getConstant(ShAmt, DL, MVT::i8));
22373 if (N->getNumValues() == 2) // Dead flag value?
22374 return DCI.CombineTo(N, Cond, SDValue());
22378 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22379 // for any integer data type, including i8/i16.
22380 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22381 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22382 DAG.getConstant(CC, DL, MVT::i8), Cond);
22384 // Zero extend the condition if needed.
22385 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22386 FalseC->getValueType(0), Cond);
22387 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22388 SDValue(FalseC, 0));
22390 if (N->getNumValues() == 2) // Dead flag value?
22391 return DCI.CombineTo(N, Cond, SDValue());
22395 // Optimize cases that will turn into an LEA instruction. This requires
22396 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22397 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22398 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22399 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22401 bool isFastMultiplier = false;
22403 switch ((unsigned char)Diff) {
22405 case 1: // result = add base, cond
22406 case 2: // result = lea base( , cond*2)
22407 case 3: // result = lea base(cond, cond*2)
22408 case 4: // result = lea base( , cond*4)
22409 case 5: // result = lea base(cond, cond*4)
22410 case 8: // result = lea base( , cond*8)
22411 case 9: // result = lea base(cond, cond*8)
22412 isFastMultiplier = true;
22417 if (isFastMultiplier) {
22418 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22419 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22420 DAG.getConstant(CC, DL, MVT::i8), Cond);
22421 // Zero extend the condition if needed.
22422 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22424 // Scale the condition by the difference.
22426 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22427 DAG.getConstant(Diff, DL, Cond.getValueType()));
22429 // Add the base if non-zero.
22430 if (FalseC->getAPIntValue() != 0)
22431 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22432 SDValue(FalseC, 0));
22433 if (N->getNumValues() == 2) // Dead flag value?
22434 return DCI.CombineTo(N, Cond, SDValue());
22441 // Handle these cases:
22442 // (select (x != c), e, c) -> select (x != c), e, x),
22443 // (select (x == c), c, e) -> select (x == c), x, e)
22444 // where the c is an integer constant, and the "select" is the combination
22445 // of CMOV and CMP.
22447 // The rationale for this change is that the conditional-move from a constant
22448 // needs two instructions, however, conditional-move from a register needs
22449 // only one instruction.
22451 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22452 // some instruction-combining opportunities. This opt needs to be
22453 // postponed as late as possible.
22455 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22456 // the DCI.xxxx conditions are provided to postpone the optimization as
22457 // late as possible.
22459 ConstantSDNode *CmpAgainst = nullptr;
22460 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22461 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22462 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22464 if (CC == X86::COND_NE &&
22465 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22466 CC = X86::GetOppositeBranchCondition(CC);
22467 std::swap(TrueOp, FalseOp);
22470 if (CC == X86::COND_E &&
22471 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22472 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22473 DAG.getConstant(CC, DL, MVT::i8), Cond };
22474 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22479 // Fold and/or of setcc's to double CMOV:
22480 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22481 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22483 // This combine lets us generate:
22484 // cmovcc1 (jcc1 if we don't have CMOV)
22490 // cmovne (jne if we don't have CMOV)
22491 // When we can't use the CMOV instruction, it might increase branch
22493 // When we can use CMOV, or when there is no mispredict, this improves
22494 // throughput and reduces register pressure.
22496 if (CC == X86::COND_NE) {
22498 X86::CondCode CC0, CC1;
22500 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22502 std::swap(FalseOp, TrueOp);
22503 CC0 = X86::GetOppositeBranchCondition(CC0);
22504 CC1 = X86::GetOppositeBranchCondition(CC1);
22507 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22509 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22510 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22511 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22512 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22520 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22521 const X86Subtarget *Subtarget) {
22522 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22524 default: return SDValue();
22525 // SSE/AVX/AVX2 blend intrinsics.
22526 case Intrinsic::x86_avx2_pblendvb:
22527 // Don't try to simplify this intrinsic if we don't have AVX2.
22528 if (!Subtarget->hasAVX2())
22531 case Intrinsic::x86_avx_blendv_pd_256:
22532 case Intrinsic::x86_avx_blendv_ps_256:
22533 // Don't try to simplify this intrinsic if we don't have AVX.
22534 if (!Subtarget->hasAVX())
22537 case Intrinsic::x86_sse41_blendvps:
22538 case Intrinsic::x86_sse41_blendvpd:
22539 case Intrinsic::x86_sse41_pblendvb: {
22540 SDValue Op0 = N->getOperand(1);
22541 SDValue Op1 = N->getOperand(2);
22542 SDValue Mask = N->getOperand(3);
22544 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22545 if (!Subtarget->hasSSE41())
22548 // fold (blend A, A, Mask) -> A
22551 // fold (blend A, B, allZeros) -> A
22552 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22554 // fold (blend A, B, allOnes) -> B
22555 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22558 // Simplify the case where the mask is a constant i32 value.
22559 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22560 if (C->isNullValue())
22562 if (C->isAllOnesValue())
22569 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22570 case Intrinsic::x86_sse2_psrai_w:
22571 case Intrinsic::x86_sse2_psrai_d:
22572 case Intrinsic::x86_avx2_psrai_w:
22573 case Intrinsic::x86_avx2_psrai_d:
22574 case Intrinsic::x86_sse2_psra_w:
22575 case Intrinsic::x86_sse2_psra_d:
22576 case Intrinsic::x86_avx2_psra_w:
22577 case Intrinsic::x86_avx2_psra_d: {
22578 SDValue Op0 = N->getOperand(1);
22579 SDValue Op1 = N->getOperand(2);
22580 EVT VT = Op0.getValueType();
22581 assert(VT.isVector() && "Expected a vector type!");
22583 if (isa<BuildVectorSDNode>(Op1))
22584 Op1 = Op1.getOperand(0);
22586 if (!isa<ConstantSDNode>(Op1))
22589 EVT SVT = VT.getVectorElementType();
22590 unsigned SVTBits = SVT.getSizeInBits();
22592 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22593 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22594 uint64_t ShAmt = C.getZExtValue();
22596 // Don't try to convert this shift into a ISD::SRA if the shift
22597 // count is bigger than or equal to the element size.
22598 if (ShAmt >= SVTBits)
22601 // Trivial case: if the shift count is zero, then fold this
22602 // into the first operand.
22606 // Replace this packed shift intrinsic with a target independent
22609 SDValue Splat = DAG.getConstant(C, DL, VT);
22610 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
22615 /// PerformMulCombine - Optimize a single multiply with constant into two
22616 /// in order to implement it with two cheaper instructions, e.g.
22617 /// LEA + SHL, LEA + LEA.
22618 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
22619 TargetLowering::DAGCombinerInfo &DCI) {
22620 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
22623 EVT VT = N->getValueType(0);
22624 if (VT != MVT::i64 && VT != MVT::i32)
22627 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
22630 uint64_t MulAmt = C->getZExtValue();
22631 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
22634 uint64_t MulAmt1 = 0;
22635 uint64_t MulAmt2 = 0;
22636 if ((MulAmt % 9) == 0) {
22638 MulAmt2 = MulAmt / 9;
22639 } else if ((MulAmt % 5) == 0) {
22641 MulAmt2 = MulAmt / 5;
22642 } else if ((MulAmt % 3) == 0) {
22644 MulAmt2 = MulAmt / 3;
22647 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
22650 if (isPowerOf2_64(MulAmt2) &&
22651 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
22652 // If second multiplifer is pow2, issue it first. We want the multiply by
22653 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
22655 std::swap(MulAmt1, MulAmt2);
22658 if (isPowerOf2_64(MulAmt1))
22659 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
22660 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
22662 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
22663 DAG.getConstant(MulAmt1, DL, VT));
22665 if (isPowerOf2_64(MulAmt2))
22666 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
22667 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
22669 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
22670 DAG.getConstant(MulAmt2, DL, VT));
22672 // Do not add new nodes to DAG combiner worklist.
22673 DCI.CombineTo(N, NewMul, false);
22678 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
22679 SDValue N0 = N->getOperand(0);
22680 SDValue N1 = N->getOperand(1);
22681 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
22682 EVT VT = N0.getValueType();
22684 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
22685 // since the result of setcc_c is all zero's or all ones.
22686 if (VT.isInteger() && !VT.isVector() &&
22687 N1C && N0.getOpcode() == ISD::AND &&
22688 N0.getOperand(1).getOpcode() == ISD::Constant) {
22689 SDValue N00 = N0.getOperand(0);
22690 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
22691 ((N00.getOpcode() == ISD::ANY_EXTEND ||
22692 N00.getOpcode() == ISD::ZERO_EXTEND) &&
22693 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
22694 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
22695 APInt ShAmt = N1C->getAPIntValue();
22696 Mask = Mask.shl(ShAmt);
22699 return DAG.getNode(ISD::AND, DL, VT,
22700 N00, DAG.getConstant(Mask, DL, VT));
22705 // Hardware support for vector shifts is sparse which makes us scalarize the
22706 // vector operations in many cases. Also, on sandybridge ADD is faster than
22708 // (shl V, 1) -> add V,V
22709 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
22710 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
22711 assert(N0.getValueType().isVector() && "Invalid vector shift type");
22712 // We shift all of the values by one. In many cases we do not have
22713 // hardware support for this operation. This is better expressed as an ADD
22715 if (N1SplatC->getZExtValue() == 1)
22716 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
22722 /// \brief Returns a vector of 0s if the node in input is a vector logical
22723 /// shift by a constant amount which is known to be bigger than or equal
22724 /// to the vector element size in bits.
22725 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
22726 const X86Subtarget *Subtarget) {
22727 EVT VT = N->getValueType(0);
22729 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
22730 (!Subtarget->hasInt256() ||
22731 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
22734 SDValue Amt = N->getOperand(1);
22736 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
22737 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
22738 APInt ShiftAmt = AmtSplat->getAPIntValue();
22739 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
22741 // SSE2/AVX2 logical shifts always return a vector of 0s
22742 // if the shift amount is bigger than or equal to
22743 // the element size. The constant shift amount will be
22744 // encoded as a 8-bit immediate.
22745 if (ShiftAmt.trunc(8).uge(MaxAmount))
22746 return getZeroVector(VT, Subtarget, DAG, DL);
22752 /// PerformShiftCombine - Combine shifts.
22753 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
22754 TargetLowering::DAGCombinerInfo &DCI,
22755 const X86Subtarget *Subtarget) {
22756 if (N->getOpcode() == ISD::SHL)
22757 if (SDValue V = PerformSHLCombine(N, DAG))
22760 // Try to fold this logical shift into a zero vector.
22761 if (N->getOpcode() != ISD::SRA)
22762 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
22768 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
22769 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
22770 // and friends. Likewise for OR -> CMPNEQSS.
22771 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
22772 TargetLowering::DAGCombinerInfo &DCI,
22773 const X86Subtarget *Subtarget) {
22776 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
22777 // we're requiring SSE2 for both.
22778 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
22779 SDValue N0 = N->getOperand(0);
22780 SDValue N1 = N->getOperand(1);
22781 SDValue CMP0 = N0->getOperand(1);
22782 SDValue CMP1 = N1->getOperand(1);
22785 // The SETCCs should both refer to the same CMP.
22786 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
22789 SDValue CMP00 = CMP0->getOperand(0);
22790 SDValue CMP01 = CMP0->getOperand(1);
22791 EVT VT = CMP00.getValueType();
22793 if (VT == MVT::f32 || VT == MVT::f64) {
22794 bool ExpectingFlags = false;
22795 // Check for any users that want flags:
22796 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
22797 !ExpectingFlags && UI != UE; ++UI)
22798 switch (UI->getOpcode()) {
22803 ExpectingFlags = true;
22805 case ISD::CopyToReg:
22806 case ISD::SIGN_EXTEND:
22807 case ISD::ZERO_EXTEND:
22808 case ISD::ANY_EXTEND:
22812 if (!ExpectingFlags) {
22813 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
22814 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
22816 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
22817 X86::CondCode tmp = cc0;
22822 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
22823 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
22824 // FIXME: need symbolic constants for these magic numbers.
22825 // See X86ATTInstPrinter.cpp:printSSECC().
22826 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
22827 if (Subtarget->hasAVX512()) {
22828 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
22830 DAG.getConstant(x86cc, DL, MVT::i8));
22831 if (N->getValueType(0) != MVT::i1)
22832 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
22836 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
22837 CMP00.getValueType(), CMP00, CMP01,
22838 DAG.getConstant(x86cc, DL,
22841 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
22842 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
22844 if (is64BitFP && !Subtarget->is64Bit()) {
22845 // On a 32-bit target, we cannot bitcast the 64-bit float to a
22846 // 64-bit integer, since that's not a legal type. Since
22847 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
22848 // bits, but can do this little dance to extract the lowest 32 bits
22849 // and work with those going forward.
22850 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
22852 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
22853 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
22854 Vector32, DAG.getIntPtrConstant(0, DL));
22858 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
22859 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
22860 DAG.getConstant(1, DL, IntVT));
22861 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
22863 return OneBitOfTruth;
22871 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
22872 /// so it can be folded inside ANDNP.
22873 static bool CanFoldXORWithAllOnes(const SDNode *N) {
22874 EVT VT = N->getValueType(0);
22876 // Match direct AllOnes for 128 and 256-bit vectors
22877 if (ISD::isBuildVectorAllOnes(N))
22880 // Look through a bit convert.
22881 if (N->getOpcode() == ISD::BITCAST)
22882 N = N->getOperand(0).getNode();
22884 // Sometimes the operand may come from a insert_subvector building a 256-bit
22886 if (VT.is256BitVector() &&
22887 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
22888 SDValue V1 = N->getOperand(0);
22889 SDValue V2 = N->getOperand(1);
22891 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
22892 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
22893 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
22894 ISD::isBuildVectorAllOnes(V2.getNode()))
22901 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
22902 // register. In most cases we actually compare or select YMM-sized registers
22903 // and mixing the two types creates horrible code. This method optimizes
22904 // some of the transition sequences.
22905 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
22906 TargetLowering::DAGCombinerInfo &DCI,
22907 const X86Subtarget *Subtarget) {
22908 EVT VT = N->getValueType(0);
22909 if (!VT.is256BitVector())
22912 assert((N->getOpcode() == ISD::ANY_EXTEND ||
22913 N->getOpcode() == ISD::ZERO_EXTEND ||
22914 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
22916 SDValue Narrow = N->getOperand(0);
22917 EVT NarrowVT = Narrow->getValueType(0);
22918 if (!NarrowVT.is128BitVector())
22921 if (Narrow->getOpcode() != ISD::XOR &&
22922 Narrow->getOpcode() != ISD::AND &&
22923 Narrow->getOpcode() != ISD::OR)
22926 SDValue N0 = Narrow->getOperand(0);
22927 SDValue N1 = Narrow->getOperand(1);
22930 // The Left side has to be a trunc.
22931 if (N0.getOpcode() != ISD::TRUNCATE)
22934 // The type of the truncated inputs.
22935 EVT WideVT = N0->getOperand(0)->getValueType(0);
22939 // The right side has to be a 'trunc' or a constant vector.
22940 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
22941 ConstantSDNode *RHSConstSplat = nullptr;
22942 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
22943 RHSConstSplat = RHSBV->getConstantSplatNode();
22944 if (!RHSTrunc && !RHSConstSplat)
22947 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22949 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
22952 // Set N0 and N1 to hold the inputs to the new wide operation.
22953 N0 = N0->getOperand(0);
22954 if (RHSConstSplat) {
22955 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
22956 SDValue(RHSConstSplat, 0));
22957 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
22958 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
22959 } else if (RHSTrunc) {
22960 N1 = N1->getOperand(0);
22963 // Generate the wide operation.
22964 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
22965 unsigned Opcode = N->getOpcode();
22967 case ISD::ANY_EXTEND:
22969 case ISD::ZERO_EXTEND: {
22970 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
22971 APInt Mask = APInt::getAllOnesValue(InBits);
22972 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
22973 return DAG.getNode(ISD::AND, DL, VT,
22974 Op, DAG.getConstant(Mask, DL, VT));
22976 case ISD::SIGN_EXTEND:
22977 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
22978 Op, DAG.getValueType(NarrowVT));
22980 llvm_unreachable("Unexpected opcode");
22984 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
22985 TargetLowering::DAGCombinerInfo &DCI,
22986 const X86Subtarget *Subtarget) {
22987 SDValue N0 = N->getOperand(0);
22988 SDValue N1 = N->getOperand(1);
22991 // A vector zext_in_reg may be represented as a shuffle,
22992 // feeding into a bitcast (this represents anyext) feeding into
22993 // an and with a mask.
22994 // We'd like to try to combine that into a shuffle with zero
22995 // plus a bitcast, removing the and.
22996 if (N0.getOpcode() != ISD::BITCAST ||
22997 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
23000 // The other side of the AND should be a splat of 2^C, where C
23001 // is the number of bits in the source type.
23002 if (N1.getOpcode() == ISD::BITCAST)
23003 N1 = N1.getOperand(0);
23004 if (N1.getOpcode() != ISD::BUILD_VECTOR)
23006 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
23008 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
23009 EVT SrcType = Shuffle->getValueType(0);
23011 // We expect a single-source shuffle
23012 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
23015 unsigned SrcSize = SrcType.getScalarSizeInBits();
23017 APInt SplatValue, SplatUndef;
23018 unsigned SplatBitSize;
23020 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
23021 SplatBitSize, HasAnyUndefs))
23024 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
23025 // Make sure the splat matches the mask we expect
23026 if (SplatBitSize > ResSize ||
23027 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
23030 // Make sure the input and output size make sense
23031 if (SrcSize >= ResSize || ResSize % SrcSize)
23034 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
23035 // The number of u's between each two values depends on the ratio between
23036 // the source and dest type.
23037 unsigned ZextRatio = ResSize / SrcSize;
23038 bool IsZext = true;
23039 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
23040 if (i % ZextRatio) {
23041 if (Shuffle->getMaskElt(i) > 0) {
23047 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
23048 // Expected element number
23058 // Ok, perform the transformation - replace the shuffle with
23059 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
23060 // (instead of undef) where the k elements come from the zero vector.
23061 SmallVector<int, 8> Mask;
23062 unsigned NumElems = SrcType.getVectorNumElements();
23063 for (unsigned i = 0; i < NumElems; ++i)
23065 Mask.push_back(NumElems);
23067 Mask.push_back(i / ZextRatio);
23069 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
23070 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
23071 return DAG.getBitcast(N0.getValueType(), NewShuffle);
23074 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23075 TargetLowering::DAGCombinerInfo &DCI,
23076 const X86Subtarget *Subtarget) {
23077 if (DCI.isBeforeLegalizeOps())
23080 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
23083 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23086 EVT VT = N->getValueType(0);
23087 SDValue N0 = N->getOperand(0);
23088 SDValue N1 = N->getOperand(1);
23091 // Create BEXTR instructions
23092 // BEXTR is ((X >> imm) & (2**size-1))
23093 if (VT == MVT::i32 || VT == MVT::i64) {
23094 // Check for BEXTR.
23095 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23096 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23097 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23098 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23099 if (MaskNode && ShiftNode) {
23100 uint64_t Mask = MaskNode->getZExtValue();
23101 uint64_t Shift = ShiftNode->getZExtValue();
23102 if (isMask_64(Mask)) {
23103 uint64_t MaskSize = countPopulation(Mask);
23104 if (Shift + MaskSize <= VT.getSizeInBits())
23105 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23106 DAG.getConstant(Shift | (MaskSize << 8), DL,
23115 // Want to form ANDNP nodes:
23116 // 1) In the hopes of then easily combining them with OR and AND nodes
23117 // to form PBLEND/PSIGN.
23118 // 2) To match ANDN packed intrinsics
23119 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23122 // Check LHS for vnot
23123 if (N0.getOpcode() == ISD::XOR &&
23124 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23125 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23126 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23128 // Check RHS for vnot
23129 if (N1.getOpcode() == ISD::XOR &&
23130 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23131 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23132 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23137 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23138 TargetLowering::DAGCombinerInfo &DCI,
23139 const X86Subtarget *Subtarget) {
23140 if (DCI.isBeforeLegalizeOps())
23143 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23146 SDValue N0 = N->getOperand(0);
23147 SDValue N1 = N->getOperand(1);
23148 EVT VT = N->getValueType(0);
23150 // look for psign/blend
23151 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23152 if (!Subtarget->hasSSSE3() ||
23153 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23156 // Canonicalize pandn to RHS
23157 if (N0.getOpcode() == X86ISD::ANDNP)
23159 // or (and (m, y), (pandn m, x))
23160 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23161 SDValue Mask = N1.getOperand(0);
23162 SDValue X = N1.getOperand(1);
23164 if (N0.getOperand(0) == Mask)
23165 Y = N0.getOperand(1);
23166 if (N0.getOperand(1) == Mask)
23167 Y = N0.getOperand(0);
23169 // Check to see if the mask appeared in both the AND and ANDNP and
23173 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23174 // Look through mask bitcast.
23175 if (Mask.getOpcode() == ISD::BITCAST)
23176 Mask = Mask.getOperand(0);
23177 if (X.getOpcode() == ISD::BITCAST)
23178 X = X.getOperand(0);
23179 if (Y.getOpcode() == ISD::BITCAST)
23180 Y = Y.getOperand(0);
23182 EVT MaskVT = Mask.getValueType();
23184 // Validate that the Mask operand is a vector sra node.
23185 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23186 // there is no psrai.b
23187 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23188 unsigned SraAmt = ~0;
23189 if (Mask.getOpcode() == ISD::SRA) {
23190 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23191 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23192 SraAmt = AmtConst->getZExtValue();
23193 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23194 SDValue SraC = Mask.getOperand(1);
23195 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23197 if ((SraAmt + 1) != EltBits)
23202 // Now we know we at least have a plendvb with the mask val. See if
23203 // we can form a psignb/w/d.
23204 // psign = x.type == y.type == mask.type && y = sub(0, x);
23205 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23206 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23207 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23208 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23209 "Unsupported VT for PSIGN");
23210 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23211 return DAG.getBitcast(VT, Mask);
23213 // PBLENDVB only available on SSE 4.1
23214 if (!Subtarget->hasSSE41())
23217 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23219 X = DAG.getBitcast(BlendVT, X);
23220 Y = DAG.getBitcast(BlendVT, Y);
23221 Mask = DAG.getBitcast(BlendVT, Mask);
23222 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23223 return DAG.getBitcast(VT, Mask);
23227 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23230 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23231 MachineFunction &MF = DAG.getMachineFunction();
23233 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23235 // SHLD/SHRD instructions have lower register pressure, but on some
23236 // platforms they have higher latency than the equivalent
23237 // series of shifts/or that would otherwise be generated.
23238 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23239 // have higher latencies and we are not optimizing for size.
23240 if (!OptForSize && Subtarget->isSHLDSlow())
23243 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23245 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23247 if (!N0.hasOneUse() || !N1.hasOneUse())
23250 SDValue ShAmt0 = N0.getOperand(1);
23251 if (ShAmt0.getValueType() != MVT::i8)
23253 SDValue ShAmt1 = N1.getOperand(1);
23254 if (ShAmt1.getValueType() != MVT::i8)
23256 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23257 ShAmt0 = ShAmt0.getOperand(0);
23258 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23259 ShAmt1 = ShAmt1.getOperand(0);
23262 unsigned Opc = X86ISD::SHLD;
23263 SDValue Op0 = N0.getOperand(0);
23264 SDValue Op1 = N1.getOperand(0);
23265 if (ShAmt0.getOpcode() == ISD::SUB) {
23266 Opc = X86ISD::SHRD;
23267 std::swap(Op0, Op1);
23268 std::swap(ShAmt0, ShAmt1);
23271 unsigned Bits = VT.getSizeInBits();
23272 if (ShAmt1.getOpcode() == ISD::SUB) {
23273 SDValue Sum = ShAmt1.getOperand(0);
23274 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23275 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23276 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23277 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23278 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23279 return DAG.getNode(Opc, DL, VT,
23281 DAG.getNode(ISD::TRUNCATE, DL,
23284 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23285 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23287 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23288 return DAG.getNode(Opc, DL, VT,
23289 N0.getOperand(0), N1.getOperand(0),
23290 DAG.getNode(ISD::TRUNCATE, DL,
23297 // Generate NEG and CMOV for integer abs.
23298 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23299 EVT VT = N->getValueType(0);
23301 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23302 // 8-bit integer abs to NEG and CMOV.
23303 if (VT.isInteger() && VT.getSizeInBits() == 8)
23306 SDValue N0 = N->getOperand(0);
23307 SDValue N1 = N->getOperand(1);
23310 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23311 // and change it to SUB and CMOV.
23312 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23313 N0.getOpcode() == ISD::ADD &&
23314 N0.getOperand(1) == N1 &&
23315 N1.getOpcode() == ISD::SRA &&
23316 N1.getOperand(0) == N0.getOperand(0))
23317 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23318 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23319 // Generate SUB & CMOV.
23320 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23321 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23323 SDValue Ops[] = { N0.getOperand(0), Neg,
23324 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23325 SDValue(Neg.getNode(), 1) };
23326 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23331 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23332 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23333 TargetLowering::DAGCombinerInfo &DCI,
23334 const X86Subtarget *Subtarget) {
23335 if (DCI.isBeforeLegalizeOps())
23338 if (Subtarget->hasCMov())
23339 if (SDValue RV = performIntegerAbsCombine(N, DAG))
23345 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23346 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23347 TargetLowering::DAGCombinerInfo &DCI,
23348 const X86Subtarget *Subtarget) {
23349 LoadSDNode *Ld = cast<LoadSDNode>(N);
23350 EVT RegVT = Ld->getValueType(0);
23351 EVT MemVT = Ld->getMemoryVT();
23353 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23355 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23356 // into two 16-byte operations.
23357 ISD::LoadExtType Ext = Ld->getExtensionType();
23358 unsigned Alignment = Ld->getAlignment();
23359 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23360 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23361 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23362 unsigned NumElems = RegVT.getVectorNumElements();
23366 SDValue Ptr = Ld->getBasePtr();
23367 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23369 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23371 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23372 Ld->getPointerInfo(), Ld->isVolatile(),
23373 Ld->isNonTemporal(), Ld->isInvariant(),
23375 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23376 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23377 Ld->getPointerInfo(), Ld->isVolatile(),
23378 Ld->isNonTemporal(), Ld->isInvariant(),
23379 std::min(16U, Alignment));
23380 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23382 Load2.getValue(1));
23384 SDValue NewVec = DAG.getUNDEF(RegVT);
23385 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23386 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23387 return DCI.CombineTo(N, NewVec, TF, true);
23393 /// PerformMLOADCombine - Resolve extending loads
23394 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23395 TargetLowering::DAGCombinerInfo &DCI,
23396 const X86Subtarget *Subtarget) {
23397 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23398 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23401 EVT VT = Mld->getValueType(0);
23402 unsigned NumElems = VT.getVectorNumElements();
23403 EVT LdVT = Mld->getMemoryVT();
23406 assert(LdVT != VT && "Cannot extend to the same type");
23407 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23408 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23409 // From, To sizes and ElemCount must be pow of two
23410 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23411 "Unexpected size for extending masked load");
23413 unsigned SizeRatio = ToSz / FromSz;
23414 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23416 // Create a type on which we perform the shuffle
23417 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23418 LdVT.getScalarType(), NumElems*SizeRatio);
23419 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23421 // Convert Src0 value
23422 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
23423 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23424 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23425 for (unsigned i = 0; i != NumElems; ++i)
23426 ShuffleVec[i] = i * SizeRatio;
23428 // Can't shuffle using an illegal type.
23429 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23430 && "WideVecVT should be legal");
23431 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23432 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23434 // Prepare the new mask
23436 SDValue Mask = Mld->getMask();
23437 if (Mask.getValueType() == VT) {
23438 // Mask and original value have the same type
23439 NewMask = DAG.getBitcast(WideVecVT, Mask);
23440 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23441 for (unsigned i = 0; i != NumElems; ++i)
23442 ShuffleVec[i] = i * SizeRatio;
23443 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23444 ShuffleVec[i] = NumElems*SizeRatio;
23445 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23446 DAG.getConstant(0, dl, WideVecVT),
23450 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23451 unsigned WidenNumElts = NumElems*SizeRatio;
23452 unsigned MaskNumElts = VT.getVectorNumElements();
23453 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23456 unsigned NumConcat = WidenNumElts / MaskNumElts;
23457 SmallVector<SDValue, 16> Ops(NumConcat);
23458 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23460 for (unsigned i = 1; i != NumConcat; ++i)
23463 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23466 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23467 Mld->getBasePtr(), NewMask, WideSrc0,
23468 Mld->getMemoryVT(), Mld->getMemOperand(),
23470 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23471 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23474 /// PerformMSTORECombine - Resolve truncating stores
23475 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23476 const X86Subtarget *Subtarget) {
23477 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23478 if (!Mst->isTruncatingStore())
23481 EVT VT = Mst->getValue().getValueType();
23482 unsigned NumElems = VT.getVectorNumElements();
23483 EVT StVT = Mst->getMemoryVT();
23486 assert(StVT != VT && "Cannot truncate to the same type");
23487 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23488 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23490 // From, To sizes and ElemCount must be pow of two
23491 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23492 "Unexpected size for truncating masked store");
23493 // We are going to use the original vector elt for storing.
23494 // Accumulated smaller vector elements must be a multiple of the store size.
23495 assert (((NumElems * FromSz) % ToSz) == 0 &&
23496 "Unexpected ratio for truncating masked store");
23498 unsigned SizeRatio = FromSz / ToSz;
23499 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23501 // Create a type on which we perform the shuffle
23502 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23503 StVT.getScalarType(), NumElems*SizeRatio);
23505 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23507 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
23508 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23509 for (unsigned i = 0; i != NumElems; ++i)
23510 ShuffleVec[i] = i * SizeRatio;
23512 // Can't shuffle using an illegal type.
23513 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23514 && "WideVecVT should be legal");
23516 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23517 DAG.getUNDEF(WideVecVT),
23521 SDValue Mask = Mst->getMask();
23522 if (Mask.getValueType() == VT) {
23523 // Mask and original value have the same type
23524 NewMask = DAG.getBitcast(WideVecVT, Mask);
23525 for (unsigned i = 0; i != NumElems; ++i)
23526 ShuffleVec[i] = i * SizeRatio;
23527 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23528 ShuffleVec[i] = NumElems*SizeRatio;
23529 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23530 DAG.getConstant(0, dl, WideVecVT),
23534 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23535 unsigned WidenNumElts = NumElems*SizeRatio;
23536 unsigned MaskNumElts = VT.getVectorNumElements();
23537 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23540 unsigned NumConcat = WidenNumElts / MaskNumElts;
23541 SmallVector<SDValue, 16> Ops(NumConcat);
23542 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23544 for (unsigned i = 1; i != NumConcat; ++i)
23547 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23550 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23551 NewMask, StVT, Mst->getMemOperand(), false);
23553 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23554 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23555 const X86Subtarget *Subtarget) {
23556 StoreSDNode *St = cast<StoreSDNode>(N);
23557 EVT VT = St->getValue().getValueType();
23558 EVT StVT = St->getMemoryVT();
23560 SDValue StoredVal = St->getOperand(1);
23561 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23563 // If we are saving a concatenation of two XMM registers and 32-byte stores
23564 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23565 unsigned Alignment = St->getAlignment();
23566 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23567 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23568 StVT == VT && !IsAligned) {
23569 unsigned NumElems = VT.getVectorNumElements();
23573 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23574 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23576 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23577 SDValue Ptr0 = St->getBasePtr();
23578 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23580 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23581 St->getPointerInfo(), St->isVolatile(),
23582 St->isNonTemporal(), Alignment);
23583 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23584 St->getPointerInfo(), St->isVolatile(),
23585 St->isNonTemporal(),
23586 std::min(16U, Alignment));
23587 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23590 // Optimize trunc store (of multiple scalars) to shuffle and store.
23591 // First, pack all of the elements in one place. Next, store to memory
23592 // in fewer chunks.
23593 if (St->isTruncatingStore() && VT.isVector()) {
23594 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23595 unsigned NumElems = VT.getVectorNumElements();
23596 assert(StVT != VT && "Cannot truncate to the same type");
23597 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23598 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23600 // From, To sizes and ElemCount must be pow of two
23601 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
23602 // We are going to use the original vector elt for storing.
23603 // Accumulated smaller vector elements must be a multiple of the store size.
23604 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
23606 unsigned SizeRatio = FromSz / ToSz;
23608 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23610 // Create a type on which we perform the shuffle
23611 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23612 StVT.getScalarType(), NumElems*SizeRatio);
23614 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23616 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
23617 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
23618 for (unsigned i = 0; i != NumElems; ++i)
23619 ShuffleVec[i] = i * SizeRatio;
23621 // Can't shuffle using an illegal type.
23622 if (!TLI.isTypeLegal(WideVecVT))
23625 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23626 DAG.getUNDEF(WideVecVT),
23628 // At this point all of the data is stored at the bottom of the
23629 // register. We now need to save it to mem.
23631 // Find the largest store unit
23632 MVT StoreType = MVT::i8;
23633 for (MVT Tp : MVT::integer_valuetypes()) {
23634 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
23638 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
23639 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
23640 (64 <= NumElems * ToSz))
23641 StoreType = MVT::f64;
23643 // Bitcast the original vector into a vector of store-size units
23644 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
23645 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
23646 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
23647 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
23648 SmallVector<SDValue, 8> Chains;
23649 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
23650 TLI.getPointerTy());
23651 SDValue Ptr = St->getBasePtr();
23653 // Perform one or more big stores into memory.
23654 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
23655 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
23656 StoreType, ShuffWide,
23657 DAG.getIntPtrConstant(i, dl));
23658 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
23659 St->getPointerInfo(), St->isVolatile(),
23660 St->isNonTemporal(), St->getAlignment());
23661 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23662 Chains.push_back(Ch);
23665 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
23668 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
23669 // the FP state in cases where an emms may be missing.
23670 // A preferable solution to the general problem is to figure out the right
23671 // places to insert EMMS. This qualifies as a quick hack.
23673 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
23674 if (VT.getSizeInBits() != 64)
23677 const Function *F = DAG.getMachineFunction().getFunction();
23678 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
23680 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
23681 if ((VT.isVector() ||
23682 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
23683 isa<LoadSDNode>(St->getValue()) &&
23684 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
23685 St->getChain().hasOneUse() && !St->isVolatile()) {
23686 SDNode* LdVal = St->getValue().getNode();
23687 LoadSDNode *Ld = nullptr;
23688 int TokenFactorIndex = -1;
23689 SmallVector<SDValue, 8> Ops;
23690 SDNode* ChainVal = St->getChain().getNode();
23691 // Must be a store of a load. We currently handle two cases: the load
23692 // is a direct child, and it's under an intervening TokenFactor. It is
23693 // possible to dig deeper under nested TokenFactors.
23694 if (ChainVal == LdVal)
23695 Ld = cast<LoadSDNode>(St->getChain());
23696 else if (St->getValue().hasOneUse() &&
23697 ChainVal->getOpcode() == ISD::TokenFactor) {
23698 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
23699 if (ChainVal->getOperand(i).getNode() == LdVal) {
23700 TokenFactorIndex = i;
23701 Ld = cast<LoadSDNode>(St->getValue());
23703 Ops.push_back(ChainVal->getOperand(i));
23707 if (!Ld || !ISD::isNormalLoad(Ld))
23710 // If this is not the MMX case, i.e. we are just turning i64 load/store
23711 // into f64 load/store, avoid the transformation if there are multiple
23712 // uses of the loaded value.
23713 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
23718 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
23719 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
23721 if (Subtarget->is64Bit() || F64IsLegal) {
23722 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
23723 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
23724 Ld->getPointerInfo(), Ld->isVolatile(),
23725 Ld->isNonTemporal(), Ld->isInvariant(),
23726 Ld->getAlignment());
23727 SDValue NewChain = NewLd.getValue(1);
23728 if (TokenFactorIndex != -1) {
23729 Ops.push_back(NewChain);
23730 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23732 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
23733 St->getPointerInfo(),
23734 St->isVolatile(), St->isNonTemporal(),
23735 St->getAlignment());
23738 // Otherwise, lower to two pairs of 32-bit loads / stores.
23739 SDValue LoAddr = Ld->getBasePtr();
23740 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
23741 DAG.getConstant(4, LdDL, MVT::i32));
23743 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
23744 Ld->getPointerInfo(),
23745 Ld->isVolatile(), Ld->isNonTemporal(),
23746 Ld->isInvariant(), Ld->getAlignment());
23747 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
23748 Ld->getPointerInfo().getWithOffset(4),
23749 Ld->isVolatile(), Ld->isNonTemporal(),
23751 MinAlign(Ld->getAlignment(), 4));
23753 SDValue NewChain = LoLd.getValue(1);
23754 if (TokenFactorIndex != -1) {
23755 Ops.push_back(LoLd);
23756 Ops.push_back(HiLd);
23757 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
23760 LoAddr = St->getBasePtr();
23761 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
23762 DAG.getConstant(4, StDL, MVT::i32));
23764 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
23765 St->getPointerInfo(),
23766 St->isVolatile(), St->isNonTemporal(),
23767 St->getAlignment());
23768 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
23769 St->getPointerInfo().getWithOffset(4),
23771 St->isNonTemporal(),
23772 MinAlign(St->getAlignment(), 4));
23773 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
23776 // This is similar to the above case, but here we handle a scalar 64-bit
23777 // integer store that is extracted from a vector on a 32-bit target.
23778 // If we have SSE2, then we can treat it like a floating-point double
23779 // to get past legalization. The execution dependencies fixup pass will
23780 // choose the optimal machine instruction for the store if this really is
23781 // an integer or v2f32 rather than an f64.
23782 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
23783 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
23784 SDValue OldExtract = St->getOperand(1);
23785 SDValue ExtOp0 = OldExtract.getOperand(0);
23786 unsigned VecSize = ExtOp0.getValueSizeInBits();
23787 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
23788 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
23789 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
23790 BitCast, OldExtract.getOperand(1));
23791 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
23792 St->getPointerInfo(), St->isVolatile(),
23793 St->isNonTemporal(), St->getAlignment());
23799 /// Return 'true' if this vector operation is "horizontal"
23800 /// and return the operands for the horizontal operation in LHS and RHS. A
23801 /// horizontal operation performs the binary operation on successive elements
23802 /// of its first operand, then on successive elements of its second operand,
23803 /// returning the resulting values in a vector. For example, if
23804 /// A = < float a0, float a1, float a2, float a3 >
23806 /// B = < float b0, float b1, float b2, float b3 >
23807 /// then the result of doing a horizontal operation on A and B is
23808 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
23809 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
23810 /// A horizontal-op B, for some already available A and B, and if so then LHS is
23811 /// set to A, RHS to B, and the routine returns 'true'.
23812 /// Note that the binary operation should have the property that if one of the
23813 /// operands is UNDEF then the result is UNDEF.
23814 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
23815 // Look for the following pattern: if
23816 // A = < float a0, float a1, float a2, float a3 >
23817 // B = < float b0, float b1, float b2, float b3 >
23819 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
23820 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
23821 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
23822 // which is A horizontal-op B.
23824 // At least one of the operands should be a vector shuffle.
23825 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
23826 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
23829 MVT VT = LHS.getSimpleValueType();
23831 assert((VT.is128BitVector() || VT.is256BitVector()) &&
23832 "Unsupported vector type for horizontal add/sub");
23834 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
23835 // operate independently on 128-bit lanes.
23836 unsigned NumElts = VT.getVectorNumElements();
23837 unsigned NumLanes = VT.getSizeInBits()/128;
23838 unsigned NumLaneElts = NumElts / NumLanes;
23839 assert((NumLaneElts % 2 == 0) &&
23840 "Vector type should have an even number of elements in each lane");
23841 unsigned HalfLaneElts = NumLaneElts/2;
23843 // View LHS in the form
23844 // LHS = VECTOR_SHUFFLE A, B, LMask
23845 // If LHS is not a shuffle then pretend it is the shuffle
23846 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
23847 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
23850 SmallVector<int, 16> LMask(NumElts);
23851 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23852 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
23853 A = LHS.getOperand(0);
23854 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
23855 B = LHS.getOperand(1);
23856 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
23857 std::copy(Mask.begin(), Mask.end(), LMask.begin());
23859 if (LHS.getOpcode() != ISD::UNDEF)
23861 for (unsigned i = 0; i != NumElts; ++i)
23865 // Likewise, view RHS in the form
23866 // RHS = VECTOR_SHUFFLE C, D, RMask
23868 SmallVector<int, 16> RMask(NumElts);
23869 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
23870 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
23871 C = RHS.getOperand(0);
23872 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
23873 D = RHS.getOperand(1);
23874 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
23875 std::copy(Mask.begin(), Mask.end(), RMask.begin());
23877 if (RHS.getOpcode() != ISD::UNDEF)
23879 for (unsigned i = 0; i != NumElts; ++i)
23883 // Check that the shuffles are both shuffling the same vectors.
23884 if (!(A == C && B == D) && !(A == D && B == C))
23887 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
23888 if (!A.getNode() && !B.getNode())
23891 // If A and B occur in reverse order in RHS, then "swap" them (which means
23892 // rewriting the mask).
23894 ShuffleVectorSDNode::commuteMask(RMask);
23896 // At this point LHS and RHS are equivalent to
23897 // LHS = VECTOR_SHUFFLE A, B, LMask
23898 // RHS = VECTOR_SHUFFLE A, B, RMask
23899 // Check that the masks correspond to performing a horizontal operation.
23900 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
23901 for (unsigned i = 0; i != NumLaneElts; ++i) {
23902 int LIdx = LMask[i+l], RIdx = RMask[i+l];
23904 // Ignore any UNDEF components.
23905 if (LIdx < 0 || RIdx < 0 ||
23906 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
23907 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
23910 // Check that successive elements are being operated on. If not, this is
23911 // not a horizontal operation.
23912 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
23913 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
23914 if (!(LIdx == Index && RIdx == Index + 1) &&
23915 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
23920 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
23921 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
23925 /// Do target-specific dag combines on floating point adds.
23926 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
23927 const X86Subtarget *Subtarget) {
23928 EVT VT = N->getValueType(0);
23929 SDValue LHS = N->getOperand(0);
23930 SDValue RHS = N->getOperand(1);
23932 // Try to synthesize horizontal adds from adds of shuffles.
23933 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23934 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23935 isHorizontalBinOp(LHS, RHS, true))
23936 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
23940 /// Do target-specific dag combines on floating point subs.
23941 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
23942 const X86Subtarget *Subtarget) {
23943 EVT VT = N->getValueType(0);
23944 SDValue LHS = N->getOperand(0);
23945 SDValue RHS = N->getOperand(1);
23947 // Try to synthesize horizontal subs from subs of shuffles.
23948 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
23949 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
23950 isHorizontalBinOp(LHS, RHS, false))
23951 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
23955 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
23956 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
23957 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
23959 // F[X]OR(0.0, x) -> x
23960 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23961 if (C->getValueAPF().isPosZero())
23962 return N->getOperand(1);
23964 // F[X]OR(x, 0.0) -> x
23965 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
23966 if (C->getValueAPF().isPosZero())
23967 return N->getOperand(0);
23971 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
23972 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
23973 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
23975 // Only perform optimizations if UnsafeMath is used.
23976 if (!DAG.getTarget().Options.UnsafeFPMath)
23979 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
23980 // into FMINC and FMAXC, which are Commutative operations.
23981 unsigned NewOp = 0;
23982 switch (N->getOpcode()) {
23983 default: llvm_unreachable("unknown opcode");
23984 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
23985 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
23988 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
23989 N->getOperand(0), N->getOperand(1));
23992 /// Do target-specific dag combines on X86ISD::FAND nodes.
23993 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
23994 // FAND(0.0, x) -> 0.0
23995 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
23996 if (C->getValueAPF().isPosZero())
23997 return N->getOperand(0);
23999 // FAND(x, 0.0) -> 0.0
24000 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24001 if (C->getValueAPF().isPosZero())
24002 return N->getOperand(1);
24007 /// Do target-specific dag combines on X86ISD::FANDN nodes
24008 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24009 // FANDN(0.0, x) -> x
24010 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24011 if (C->getValueAPF().isPosZero())
24012 return N->getOperand(1);
24014 // FANDN(x, 0.0) -> 0.0
24015 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24016 if (C->getValueAPF().isPosZero())
24017 return N->getOperand(1);
24022 static SDValue PerformBTCombine(SDNode *N,
24024 TargetLowering::DAGCombinerInfo &DCI) {
24025 // BT ignores high bits in the bit index operand.
24026 SDValue Op1 = N->getOperand(1);
24027 if (Op1.hasOneUse()) {
24028 unsigned BitWidth = Op1.getValueSizeInBits();
24029 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24030 APInt KnownZero, KnownOne;
24031 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24032 !DCI.isBeforeLegalizeOps());
24033 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24034 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24035 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24036 DCI.CommitTargetLoweringOpt(TLO);
24041 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24042 SDValue Op = N->getOperand(0);
24043 if (Op.getOpcode() == ISD::BITCAST)
24044 Op = Op.getOperand(0);
24045 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24046 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24047 VT.getVectorElementType().getSizeInBits() ==
24048 OpVT.getVectorElementType().getSizeInBits()) {
24049 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24054 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24055 const X86Subtarget *Subtarget) {
24056 EVT VT = N->getValueType(0);
24057 if (!VT.isVector())
24060 SDValue N0 = N->getOperand(0);
24061 SDValue N1 = N->getOperand(1);
24062 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24065 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24066 // both SSE and AVX2 since there is no sign-extended shift right
24067 // operation on a vector with 64-bit elements.
24068 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24069 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24070 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24071 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24072 SDValue N00 = N0.getOperand(0);
24074 // EXTLOAD has a better solution on AVX2,
24075 // it may be replaced with X86ISD::VSEXT node.
24076 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24077 if (!ISD::isNormalLoad(N00.getNode()))
24080 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24081 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24083 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24089 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24090 TargetLowering::DAGCombinerInfo &DCI,
24091 const X86Subtarget *Subtarget) {
24092 SDValue N0 = N->getOperand(0);
24093 EVT VT = N->getValueType(0);
24094 EVT SVT = VT.getScalarType();
24095 EVT InVT = N0.getValueType();
24096 EVT InSVT = InVT.getScalarType();
24099 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24100 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24101 // This exposes the sext to the sdivrem lowering, so that it directly extends
24102 // from AH (which we otherwise need to do contortions to access).
24103 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24104 InVT == MVT::i8 && VT == MVT::i32) {
24105 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24106 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24107 N0.getOperand(0), N0.getOperand(1));
24108 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24109 return R.getValue(1);
24112 if (!DCI.isBeforeLegalizeOps()) {
24113 if (InVT == MVT::i1) {
24114 SDValue Zero = DAG.getConstant(0, DL, VT);
24116 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24117 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24122 if (VT.isVector()) {
24123 auto ExtendToVec128 = [&DAG](SDLoc DL, SDValue N) {
24124 EVT InVT = N.getValueType();
24125 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24126 128 / InVT.getScalarSizeInBits());
24127 SmallVector<SDValue, 8> Opnds(128 / InVT.getSizeInBits(),
24128 DAG.getUNDEF(InVT));
24130 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24133 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24134 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24135 if (VT.getSizeInBits() == 128 &&
24136 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24137 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24138 SDValue ExOp = ExtendToVec128(DL, N0);
24139 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
24142 // On pre-AVX2 targets, split into 128-bit nodes of
24143 // ISD::SIGN_EXTEND_VECTOR_INREG.
24144 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
24145 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24146 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24147 unsigned NumVecs = VT.getSizeInBits() / 128;
24148 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24149 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24150 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24152 SmallVector<SDValue, 8> Opnds;
24153 for (unsigned i = 0, Offset = 0; i != NumVecs;
24154 ++i, Offset += NumSubElts) {
24155 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24156 DAG.getIntPtrConstant(Offset, DL));
24157 SrcVec = ExtendToVec128(DL, SrcVec);
24158 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24159 Opnds.push_back(SrcVec);
24161 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24165 if (!Subtarget->hasFp256())
24168 if (VT.isVector() && VT.getSizeInBits() == 256)
24169 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24175 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24176 const X86Subtarget* Subtarget) {
24178 EVT VT = N->getValueType(0);
24180 // Let legalize expand this if it isn't a legal type yet.
24181 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24184 EVT ScalarVT = VT.getScalarType();
24185 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24186 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
24187 !Subtarget->hasAVX512()))
24190 SDValue A = N->getOperand(0);
24191 SDValue B = N->getOperand(1);
24192 SDValue C = N->getOperand(2);
24194 bool NegA = (A.getOpcode() == ISD::FNEG);
24195 bool NegB = (B.getOpcode() == ISD::FNEG);
24196 bool NegC = (C.getOpcode() == ISD::FNEG);
24198 // Negative multiplication when NegA xor NegB
24199 bool NegMul = (NegA != NegB);
24201 A = A.getOperand(0);
24203 B = B.getOperand(0);
24205 C = C.getOperand(0);
24209 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24211 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24213 return DAG.getNode(Opcode, dl, VT, A, B, C);
24216 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24217 TargetLowering::DAGCombinerInfo &DCI,
24218 const X86Subtarget *Subtarget) {
24219 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24220 // (and (i32 x86isd::setcc_carry), 1)
24221 // This eliminates the zext. This transformation is necessary because
24222 // ISD::SETCC is always legalized to i8.
24224 SDValue N0 = N->getOperand(0);
24225 EVT VT = N->getValueType(0);
24227 if (N0.getOpcode() == ISD::AND &&
24229 N0.getOperand(0).hasOneUse()) {
24230 SDValue N00 = N0.getOperand(0);
24231 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24232 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24233 if (!C || C->getZExtValue() != 1)
24235 return DAG.getNode(ISD::AND, dl, VT,
24236 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24237 N00.getOperand(0), N00.getOperand(1)),
24238 DAG.getConstant(1, dl, VT));
24242 if (N0.getOpcode() == ISD::TRUNCATE &&
24244 N0.getOperand(0).hasOneUse()) {
24245 SDValue N00 = N0.getOperand(0);
24246 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24247 return DAG.getNode(ISD::AND, dl, VT,
24248 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24249 N00.getOperand(0), N00.getOperand(1)),
24250 DAG.getConstant(1, dl, VT));
24254 if (VT.is256BitVector())
24255 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24258 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24259 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24260 // This exposes the zext to the udivrem lowering, so that it directly extends
24261 // from AH (which we otherwise need to do contortions to access).
24262 if (N0.getOpcode() == ISD::UDIVREM &&
24263 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24264 (VT == MVT::i32 || VT == MVT::i64)) {
24265 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24266 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24267 N0.getOperand(0), N0.getOperand(1));
24268 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24269 return R.getValue(1);
24275 // Optimize x == -y --> x+y == 0
24276 // x != -y --> x+y != 0
24277 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24278 const X86Subtarget* Subtarget) {
24279 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24280 SDValue LHS = N->getOperand(0);
24281 SDValue RHS = N->getOperand(1);
24282 EVT VT = N->getValueType(0);
24285 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24287 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24288 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24289 LHS.getOperand(1));
24290 return DAG.getSetCC(DL, N->getValueType(0), addV,
24291 DAG.getConstant(0, DL, addV.getValueType()), CC);
24293 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24295 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24296 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24297 RHS.getOperand(1));
24298 return DAG.getSetCC(DL, N->getValueType(0), addV,
24299 DAG.getConstant(0, DL, addV.getValueType()), CC);
24302 if (VT.getScalarType() == MVT::i1 &&
24303 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24305 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24306 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24307 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24309 if (!IsSEXT0 || !IsVZero1) {
24310 // Swap the operands and update the condition code.
24311 std::swap(LHS, RHS);
24312 CC = ISD::getSetCCSwappedOperands(CC);
24314 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24315 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24316 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24319 if (IsSEXT0 && IsVZero1) {
24320 assert(VT == LHS.getOperand(0).getValueType() &&
24321 "Uexpected operand type");
24322 if (CC == ISD::SETGT)
24323 return DAG.getConstant(0, DL, VT);
24324 if (CC == ISD::SETLE)
24325 return DAG.getConstant(1, DL, VT);
24326 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24327 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24329 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24330 "Unexpected condition code!");
24331 return LHS.getOperand(0);
24338 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24339 SelectionDAG &DAG) {
24341 MVT VT = Load->getSimpleValueType(0);
24342 MVT EVT = VT.getVectorElementType();
24343 SDValue Addr = Load->getOperand(1);
24344 SDValue NewAddr = DAG.getNode(
24345 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24346 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24347 Addr.getSimpleValueType()));
24350 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24351 DAG.getMachineFunction().getMachineMemOperand(
24352 Load->getMemOperand(), 0, EVT.getStoreSize()));
24356 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24357 const X86Subtarget *Subtarget) {
24359 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24360 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24361 "X86insertps is only defined for v4x32");
24363 SDValue Ld = N->getOperand(1);
24364 if (MayFoldLoad(Ld)) {
24365 // Extract the countS bits from the immediate so we can get the proper
24366 // address when narrowing the vector load to a specific element.
24367 // When the second source op is a memory address, insertps doesn't use
24368 // countS and just gets an f32 from that address.
24369 unsigned DestIndex =
24370 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24372 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24374 // Create this as a scalar to vector to match the instruction pattern.
24375 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24376 // countS bits are ignored when loading from memory on insertps, which
24377 // means we don't need to explicitly set them to 0.
24378 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24379 LoadScalarToVector, N->getOperand(2));
24384 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24385 SDValue V0 = N->getOperand(0);
24386 SDValue V1 = N->getOperand(1);
24388 EVT VT = N->getValueType(0);
24390 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24391 // operands and changing the mask to 1. This saves us a bunch of
24392 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24393 // x86InstrInfo knows how to commute this back after instruction selection
24394 // if it would help register allocation.
24396 // TODO: If optimizing for size or a processor that doesn't suffer from
24397 // partial register update stalls, this should be transformed into a MOVSD
24398 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24400 if (VT == MVT::v2f64)
24401 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24402 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24403 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24404 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24410 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24411 // as "sbb reg,reg", since it can be extended without zext and produces
24412 // an all-ones bit which is more useful than 0/1 in some cases.
24413 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24416 return DAG.getNode(ISD::AND, DL, VT,
24417 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24418 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24420 DAG.getConstant(1, DL, VT));
24421 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24422 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24423 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24424 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24428 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24429 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24430 TargetLowering::DAGCombinerInfo &DCI,
24431 const X86Subtarget *Subtarget) {
24433 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24434 SDValue EFLAGS = N->getOperand(1);
24436 if (CC == X86::COND_A) {
24437 // Try to convert COND_A into COND_B in an attempt to facilitate
24438 // materializing "setb reg".
24440 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24441 // cannot take an immediate as its first operand.
24443 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24444 EFLAGS.getValueType().isInteger() &&
24445 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24446 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24447 EFLAGS.getNode()->getVTList(),
24448 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24449 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24450 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24454 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24455 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24457 if (CC == X86::COND_B)
24458 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24460 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24461 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24462 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24468 // Optimize branch condition evaluation.
24470 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24471 TargetLowering::DAGCombinerInfo &DCI,
24472 const X86Subtarget *Subtarget) {
24474 SDValue Chain = N->getOperand(0);
24475 SDValue Dest = N->getOperand(1);
24476 SDValue EFLAGS = N->getOperand(3);
24477 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24479 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24480 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24481 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24488 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24489 SelectionDAG &DAG) {
24490 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24491 // optimize away operation when it's from a constant.
24493 // The general transformation is:
24494 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24495 // AND(VECTOR_CMP(x,y), constant2)
24496 // constant2 = UNARYOP(constant)
24498 // Early exit if this isn't a vector operation, the operand of the
24499 // unary operation isn't a bitwise AND, or if the sizes of the operations
24500 // aren't the same.
24501 EVT VT = N->getValueType(0);
24502 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24503 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24504 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24507 // Now check that the other operand of the AND is a constant. We could
24508 // make the transformation for non-constant splats as well, but it's unclear
24509 // that would be a benefit as it would not eliminate any operations, just
24510 // perform one more step in scalar code before moving to the vector unit.
24511 if (BuildVectorSDNode *BV =
24512 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24513 // Bail out if the vector isn't a constant.
24514 if (!BV->isConstant())
24517 // Everything checks out. Build up the new and improved node.
24519 EVT IntVT = BV->getValueType(0);
24520 // Create a new constant of the appropriate type for the transformed
24522 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24523 // The AND node needs bitcasts to/from an integer vector type around it.
24524 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
24525 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24526 N->getOperand(0)->getOperand(0), MaskConst);
24527 SDValue Res = DAG.getBitcast(VT, NewAnd);
24534 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24535 const X86Subtarget *Subtarget) {
24536 // First try to optimize away the conversion entirely when it's
24537 // conditionally from a constant. Vectors only.
24538 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
24541 // Now move on to more general possibilities.
24542 SDValue Op0 = N->getOperand(0);
24543 EVT InVT = Op0->getValueType(0);
24545 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
24546 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
24547 if (InVT == MVT::v8i8 || InVT == MVT::v4i8 ||
24548 InVT == MVT::v8i16 || InVT == MVT::v4i16) {
24550 MVT DstVT = MVT::getVectorVT(MVT::i32, InVT.getVectorNumElements());
24551 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24552 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
24555 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24556 // a 32-bit target where SSE doesn't support i64->FP operations.
24557 if (Op0.getOpcode() == ISD::LOAD) {
24558 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
24559 EVT LdVT = Ld->getValueType(0);
24561 // This transformation is not supported if the result type is f16
24562 if (N->getValueType(0) == MVT::f16)
24565 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
24566 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
24567 !Subtarget->is64Bit() && LdVT == MVT::i64) {
24568 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
24569 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
24570 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
24577 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
24578 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
24579 X86TargetLowering::DAGCombinerInfo &DCI) {
24580 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
24581 // the result is either zero or one (depending on the input carry bit).
24582 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
24583 if (X86::isZeroNode(N->getOperand(0)) &&
24584 X86::isZeroNode(N->getOperand(1)) &&
24585 // We don't have a good way to replace an EFLAGS use, so only do this when
24587 SDValue(N, 1).use_empty()) {
24589 EVT VT = N->getValueType(0);
24590 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
24591 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
24592 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
24593 DAG.getConstant(X86::COND_B, DL,
24596 DAG.getConstant(1, DL, VT));
24597 return DCI.CombineTo(N, Res1, CarryOut);
24603 // fold (add Y, (sete X, 0)) -> adc 0, Y
24604 // (add Y, (setne X, 0)) -> sbb -1, Y
24605 // (sub (sete X, 0), Y) -> sbb 0, Y
24606 // (sub (setne X, 0), Y) -> adc -1, Y
24607 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
24610 // Look through ZExts.
24611 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
24612 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
24615 SDValue SetCC = Ext.getOperand(0);
24616 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
24619 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
24620 if (CC != X86::COND_E && CC != X86::COND_NE)
24623 SDValue Cmp = SetCC.getOperand(1);
24624 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
24625 !X86::isZeroNode(Cmp.getOperand(1)) ||
24626 !Cmp.getOperand(0).getValueType().isInteger())
24629 SDValue CmpOp0 = Cmp.getOperand(0);
24630 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
24631 DAG.getConstant(1, DL, CmpOp0.getValueType()));
24633 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
24634 if (CC == X86::COND_NE)
24635 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
24636 DL, OtherVal.getValueType(), OtherVal,
24637 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
24639 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
24640 DL, OtherVal.getValueType(), OtherVal,
24641 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
24644 /// PerformADDCombine - Do target-specific dag combines on integer adds.
24645 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
24646 const X86Subtarget *Subtarget) {
24647 EVT VT = N->getValueType(0);
24648 SDValue Op0 = N->getOperand(0);
24649 SDValue Op1 = N->getOperand(1);
24651 // Try to synthesize horizontal adds from adds of shuffles.
24652 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24653 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24654 isHorizontalBinOp(Op0, Op1, true))
24655 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
24657 return OptimizeConditionalInDecrement(N, DAG);
24660 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
24661 const X86Subtarget *Subtarget) {
24662 SDValue Op0 = N->getOperand(0);
24663 SDValue Op1 = N->getOperand(1);
24665 // X86 can't encode an immediate LHS of a sub. See if we can push the
24666 // negation into a preceding instruction.
24667 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
24668 // If the RHS of the sub is a XOR with one use and a constant, invert the
24669 // immediate. Then add one to the LHS of the sub so we can turn
24670 // X-Y -> X+~Y+1, saving one register.
24671 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
24672 isa<ConstantSDNode>(Op1.getOperand(1))) {
24673 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
24674 EVT VT = Op0.getValueType();
24675 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
24677 DAG.getConstant(~XorC, SDLoc(Op1), VT));
24678 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
24679 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
24683 // Try to synthesize horizontal adds from adds of shuffles.
24684 EVT VT = N->getValueType(0);
24685 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
24686 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
24687 isHorizontalBinOp(Op0, Op1, true))
24688 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
24690 return OptimizeConditionalInDecrement(N, DAG);
24693 /// performVZEXTCombine - Performs build vector combines
24694 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
24695 TargetLowering::DAGCombinerInfo &DCI,
24696 const X86Subtarget *Subtarget) {
24698 MVT VT = N->getSimpleValueType(0);
24699 SDValue Op = N->getOperand(0);
24700 MVT OpVT = Op.getSimpleValueType();
24701 MVT OpEltVT = OpVT.getVectorElementType();
24702 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
24704 // (vzext (bitcast (vzext (x)) -> (vzext x)
24706 while (V.getOpcode() == ISD::BITCAST)
24707 V = V.getOperand(0);
24709 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
24710 MVT InnerVT = V.getSimpleValueType();
24711 MVT InnerEltVT = InnerVT.getVectorElementType();
24713 // If the element sizes match exactly, we can just do one larger vzext. This
24714 // is always an exact type match as vzext operates on integer types.
24715 if (OpEltVT == InnerEltVT) {
24716 assert(OpVT == InnerVT && "Types must match for vzext!");
24717 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
24720 // The only other way we can combine them is if only a single element of the
24721 // inner vzext is used in the input to the outer vzext.
24722 if (InnerEltVT.getSizeInBits() < InputBits)
24725 // In this case, the inner vzext is completely dead because we're going to
24726 // only look at bits inside of the low element. Just do the outer vzext on
24727 // a bitcast of the input to the inner.
24728 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
24731 // Check if we can bypass extracting and re-inserting an element of an input
24732 // vector. Essentialy:
24733 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
24734 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
24735 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
24736 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
24737 SDValue ExtractedV = V.getOperand(0);
24738 SDValue OrigV = ExtractedV.getOperand(0);
24739 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
24740 if (ExtractIdx->getZExtValue() == 0) {
24741 MVT OrigVT = OrigV.getSimpleValueType();
24742 // Extract a subvector if necessary...
24743 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
24744 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
24745 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
24746 OrigVT.getVectorNumElements() / Ratio);
24747 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
24748 DAG.getIntPtrConstant(0, DL));
24750 Op = DAG.getBitcast(OpVT, OrigV);
24751 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
24758 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
24759 DAGCombinerInfo &DCI) const {
24760 SelectionDAG &DAG = DCI.DAG;
24761 switch (N->getOpcode()) {
24763 case ISD::EXTRACT_VECTOR_ELT:
24764 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
24767 case X86ISD::SHRUNKBLEND:
24768 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
24769 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
24770 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
24771 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
24772 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
24773 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
24774 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
24777 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
24778 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
24779 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
24780 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
24781 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
24782 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
24783 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
24784 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
24785 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
24786 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
24787 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
24789 case X86ISD::FOR: return PerformFORCombine(N, DAG);
24791 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
24792 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
24793 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
24794 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
24795 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
24796 case ISD::ANY_EXTEND:
24797 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
24798 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
24799 case ISD::SIGN_EXTEND_INREG:
24800 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
24801 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
24802 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
24803 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
24804 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
24805 case X86ISD::SHUFP: // Handle all target specific shuffles
24806 case X86ISD::PALIGNR:
24807 case X86ISD::UNPCKH:
24808 case X86ISD::UNPCKL:
24809 case X86ISD::MOVHLPS:
24810 case X86ISD::MOVLHPS:
24811 case X86ISD::PSHUFB:
24812 case X86ISD::PSHUFD:
24813 case X86ISD::PSHUFHW:
24814 case X86ISD::PSHUFLW:
24815 case X86ISD::MOVSS:
24816 case X86ISD::MOVSD:
24817 case X86ISD::VPERMILPI:
24818 case X86ISD::VPERM2X128:
24819 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
24820 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
24821 case ISD::INTRINSIC_WO_CHAIN:
24822 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
24823 case X86ISD::INSERTPS: {
24824 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
24825 return PerformINSERTPSCombine(N, DAG, Subtarget);
24828 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
24834 /// isTypeDesirableForOp - Return true if the target has native support for
24835 /// the specified value type and it is 'desirable' to use the type for the
24836 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
24837 /// instruction encodings are longer and some i16 instructions are slow.
24838 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
24839 if (!isTypeLegal(VT))
24841 if (VT != MVT::i16)
24848 case ISD::SIGN_EXTEND:
24849 case ISD::ZERO_EXTEND:
24850 case ISD::ANY_EXTEND:
24863 /// IsDesirableToPromoteOp - This method query the target whether it is
24864 /// beneficial for dag combiner to promote the specified node. If true, it
24865 /// should return the desired promotion type by reference.
24866 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
24867 EVT VT = Op.getValueType();
24868 if (VT != MVT::i16)
24871 bool Promote = false;
24872 bool Commute = false;
24873 switch (Op.getOpcode()) {
24876 LoadSDNode *LD = cast<LoadSDNode>(Op);
24877 // If the non-extending load has a single use and it's not live out, then it
24878 // might be folded.
24879 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
24880 Op.hasOneUse()*/) {
24881 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
24882 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
24883 // The only case where we'd want to promote LOAD (rather then it being
24884 // promoted as an operand is when it's only use is liveout.
24885 if (UI->getOpcode() != ISD::CopyToReg)
24892 case ISD::SIGN_EXTEND:
24893 case ISD::ZERO_EXTEND:
24894 case ISD::ANY_EXTEND:
24899 SDValue N0 = Op.getOperand(0);
24900 // Look out for (store (shl (load), x)).
24901 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
24914 SDValue N0 = Op.getOperand(0);
24915 SDValue N1 = Op.getOperand(1);
24916 if (!Commute && MayFoldLoad(N1))
24918 // Avoid disabling potential load folding opportunities.
24919 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
24921 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
24931 //===----------------------------------------------------------------------===//
24932 // X86 Inline Assembly Support
24933 //===----------------------------------------------------------------------===//
24935 // Helper to match a string separated by whitespace.
24936 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
24937 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
24939 for (StringRef Piece : Pieces) {
24940 if (!S.startswith(Piece)) // Check if the piece matches.
24943 S = S.substr(Piece.size());
24944 StringRef::size_type Pos = S.find_first_not_of(" \t");
24945 if (Pos == 0) // We matched a prefix.
24954 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
24956 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
24957 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
24958 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
24959 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
24961 if (AsmPieces.size() == 3)
24963 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
24970 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
24971 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
24973 std::string AsmStr = IA->getAsmString();
24975 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
24976 if (!Ty || Ty->getBitWidth() % 16 != 0)
24979 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
24980 SmallVector<StringRef, 4> AsmPieces;
24981 SplitString(AsmStr, AsmPieces, ";\n");
24983 switch (AsmPieces.size()) {
24984 default: return false;
24986 // FIXME: this should verify that we are targeting a 486 or better. If not,
24987 // we will turn this bswap into something that will be lowered to logical
24988 // ops instead of emitting the bswap asm. For now, we don't support 486 or
24989 // lower so don't worry about this.
24991 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
24992 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
24993 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
24994 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
24995 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
24996 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
24997 // No need to check constraints, nothing other than the equivalent of
24998 // "=r,0" would be valid here.
24999 return IntrinsicLowering::LowerToByteSwap(CI);
25002 // rorw $$8, ${0:w} --> llvm.bswap.i16
25003 if (CI->getType()->isIntegerTy(16) &&
25004 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25005 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
25006 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
25008 const std::string &ConstraintsStr = IA->getConstraintString();
25009 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25010 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25011 if (clobbersFlagRegisters(AsmPieces))
25012 return IntrinsicLowering::LowerToByteSwap(CI);
25016 if (CI->getType()->isIntegerTy(32) &&
25017 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25018 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
25019 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
25020 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
25022 const std::string &ConstraintsStr = IA->getConstraintString();
25023 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25024 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25025 if (clobbersFlagRegisters(AsmPieces))
25026 return IntrinsicLowering::LowerToByteSwap(CI);
25029 if (CI->getType()->isIntegerTy(64)) {
25030 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25031 if (Constraints.size() >= 2 &&
25032 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25033 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25034 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25035 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
25036 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
25037 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
25038 return IntrinsicLowering::LowerToByteSwap(CI);
25046 /// getConstraintType - Given a constraint letter, return the type of
25047 /// constraint it is for this target.
25048 X86TargetLowering::ConstraintType
25049 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
25050 if (Constraint.size() == 1) {
25051 switch (Constraint[0]) {
25062 return C_RegisterClass;
25086 return TargetLowering::getConstraintType(Constraint);
25089 /// Examine constraint type and operand type and determine a weight value.
25090 /// This object must already have been set up with the operand type
25091 /// and the current alternative constraint selected.
25092 TargetLowering::ConstraintWeight
25093 X86TargetLowering::getSingleConstraintMatchWeight(
25094 AsmOperandInfo &info, const char *constraint) const {
25095 ConstraintWeight weight = CW_Invalid;
25096 Value *CallOperandVal = info.CallOperandVal;
25097 // If we don't have a value, we can't do a match,
25098 // but allow it at the lowest weight.
25099 if (!CallOperandVal)
25101 Type *type = CallOperandVal->getType();
25102 // Look at the constraint type.
25103 switch (*constraint) {
25105 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25116 if (CallOperandVal->getType()->isIntegerTy())
25117 weight = CW_SpecificReg;
25122 if (type->isFloatingPointTy())
25123 weight = CW_SpecificReg;
25126 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25127 weight = CW_SpecificReg;
25131 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25132 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25133 weight = CW_Register;
25136 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25137 if (C->getZExtValue() <= 31)
25138 weight = CW_Constant;
25142 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25143 if (C->getZExtValue() <= 63)
25144 weight = CW_Constant;
25148 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25149 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25150 weight = CW_Constant;
25154 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25155 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25156 weight = CW_Constant;
25160 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25161 if (C->getZExtValue() <= 3)
25162 weight = CW_Constant;
25166 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25167 if (C->getZExtValue() <= 0xff)
25168 weight = CW_Constant;
25173 if (isa<ConstantFP>(CallOperandVal)) {
25174 weight = CW_Constant;
25178 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25179 if ((C->getSExtValue() >= -0x80000000LL) &&
25180 (C->getSExtValue() <= 0x7fffffffLL))
25181 weight = CW_Constant;
25185 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25186 if (C->getZExtValue() <= 0xffffffff)
25187 weight = CW_Constant;
25194 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25195 /// with another that has more specific requirements based on the type of the
25196 /// corresponding operand.
25197 const char *X86TargetLowering::
25198 LowerXConstraint(EVT ConstraintVT) const {
25199 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25200 // 'f' like normal targets.
25201 if (ConstraintVT.isFloatingPoint()) {
25202 if (Subtarget->hasSSE2())
25204 if (Subtarget->hasSSE1())
25208 return TargetLowering::LowerXConstraint(ConstraintVT);
25211 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25212 /// vector. If it is invalid, don't add anything to Ops.
25213 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25214 std::string &Constraint,
25215 std::vector<SDValue>&Ops,
25216 SelectionDAG &DAG) const {
25219 // Only support length 1 constraints for now.
25220 if (Constraint.length() > 1) return;
25222 char ConstraintLetter = Constraint[0];
25223 switch (ConstraintLetter) {
25226 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25227 if (C->getZExtValue() <= 31) {
25228 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25229 Op.getValueType());
25235 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25236 if (C->getZExtValue() <= 63) {
25237 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25238 Op.getValueType());
25244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25245 if (isInt<8>(C->getSExtValue())) {
25246 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25247 Op.getValueType());
25253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25254 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25255 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25256 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25257 Op.getValueType());
25263 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25264 if (C->getZExtValue() <= 3) {
25265 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25266 Op.getValueType());
25272 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25273 if (C->getZExtValue() <= 255) {
25274 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25275 Op.getValueType());
25281 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25282 if (C->getZExtValue() <= 127) {
25283 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25284 Op.getValueType());
25290 // 32-bit signed value
25291 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25292 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25293 C->getSExtValue())) {
25294 // Widen to 64 bits here to get it sign extended.
25295 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25298 // FIXME gcc accepts some relocatable values here too, but only in certain
25299 // memory models; it's complicated.
25304 // 32-bit unsigned value
25305 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25306 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25307 C->getZExtValue())) {
25308 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25309 Op.getValueType());
25313 // FIXME gcc accepts some relocatable values here too, but only in certain
25314 // memory models; it's complicated.
25318 // Literal immediates are always ok.
25319 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25320 // Widen to 64 bits here to get it sign extended.
25321 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25325 // In any sort of PIC mode addresses need to be computed at runtime by
25326 // adding in a register or some sort of table lookup. These can't
25327 // be used as immediates.
25328 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25331 // If we are in non-pic codegen mode, we allow the address of a global (with
25332 // an optional displacement) to be used with 'i'.
25333 GlobalAddressSDNode *GA = nullptr;
25334 int64_t Offset = 0;
25336 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25338 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25339 Offset += GA->getOffset();
25341 } else if (Op.getOpcode() == ISD::ADD) {
25342 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25343 Offset += C->getZExtValue();
25344 Op = Op.getOperand(0);
25347 } else if (Op.getOpcode() == ISD::SUB) {
25348 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25349 Offset += -C->getZExtValue();
25350 Op = Op.getOperand(0);
25355 // Otherwise, this isn't something we can handle, reject it.
25359 const GlobalValue *GV = GA->getGlobal();
25360 // If we require an extra load to get this address, as in PIC mode, we
25361 // can't accept it.
25362 if (isGlobalStubReference(
25363 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25366 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25367 GA->getValueType(0), Offset);
25372 if (Result.getNode()) {
25373 Ops.push_back(Result);
25376 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25379 std::pair<unsigned, const TargetRegisterClass *>
25380 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25381 const std::string &Constraint,
25383 // First, see if this is a constraint that directly corresponds to an LLVM
25385 if (Constraint.size() == 1) {
25386 // GCC Constraint Letters
25387 switch (Constraint[0]) {
25389 // TODO: Slight differences here in allocation order and leaving
25390 // RIP in the class. Do they matter any more here than they do
25391 // in the normal allocation?
25392 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25393 if (Subtarget->is64Bit()) {
25394 if (VT == MVT::i32 || VT == MVT::f32)
25395 return std::make_pair(0U, &X86::GR32RegClass);
25396 if (VT == MVT::i16)
25397 return std::make_pair(0U, &X86::GR16RegClass);
25398 if (VT == MVT::i8 || VT == MVT::i1)
25399 return std::make_pair(0U, &X86::GR8RegClass);
25400 if (VT == MVT::i64 || VT == MVT::f64)
25401 return std::make_pair(0U, &X86::GR64RegClass);
25404 // 32-bit fallthrough
25405 case 'Q': // Q_REGS
25406 if (VT == MVT::i32 || VT == MVT::f32)
25407 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25408 if (VT == MVT::i16)
25409 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25410 if (VT == MVT::i8 || VT == MVT::i1)
25411 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25412 if (VT == MVT::i64)
25413 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25415 case 'r': // GENERAL_REGS
25416 case 'l': // INDEX_REGS
25417 if (VT == MVT::i8 || VT == MVT::i1)
25418 return std::make_pair(0U, &X86::GR8RegClass);
25419 if (VT == MVT::i16)
25420 return std::make_pair(0U, &X86::GR16RegClass);
25421 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25422 return std::make_pair(0U, &X86::GR32RegClass);
25423 return std::make_pair(0U, &X86::GR64RegClass);
25424 case 'R': // LEGACY_REGS
25425 if (VT == MVT::i8 || VT == MVT::i1)
25426 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25427 if (VT == MVT::i16)
25428 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25429 if (VT == MVT::i32 || !Subtarget->is64Bit())
25430 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25431 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25432 case 'f': // FP Stack registers.
25433 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25434 // value to the correct fpstack register class.
25435 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25436 return std::make_pair(0U, &X86::RFP32RegClass);
25437 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25438 return std::make_pair(0U, &X86::RFP64RegClass);
25439 return std::make_pair(0U, &X86::RFP80RegClass);
25440 case 'y': // MMX_REGS if MMX allowed.
25441 if (!Subtarget->hasMMX()) break;
25442 return std::make_pair(0U, &X86::VR64RegClass);
25443 case 'Y': // SSE_REGS if SSE2 allowed
25444 if (!Subtarget->hasSSE2()) break;
25446 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25447 if (!Subtarget->hasSSE1()) break;
25449 switch (VT.SimpleTy) {
25451 // Scalar SSE types.
25454 return std::make_pair(0U, &X86::FR32RegClass);
25457 return std::make_pair(0U, &X86::FR64RegClass);
25465 return std::make_pair(0U, &X86::VR128RegClass);
25473 return std::make_pair(0U, &X86::VR256RegClass);
25478 return std::make_pair(0U, &X86::VR512RegClass);
25484 // Use the default implementation in TargetLowering to convert the register
25485 // constraint into a member of a register class.
25486 std::pair<unsigned, const TargetRegisterClass*> Res;
25487 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25489 // Not found as a standard register?
25491 // Map st(0) -> st(7) -> ST0
25492 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25493 tolower(Constraint[1]) == 's' &&
25494 tolower(Constraint[2]) == 't' &&
25495 Constraint[3] == '(' &&
25496 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25497 Constraint[5] == ')' &&
25498 Constraint[6] == '}') {
25500 Res.first = X86::FP0+Constraint[4]-'0';
25501 Res.second = &X86::RFP80RegClass;
25505 // GCC allows "st(0)" to be called just plain "st".
25506 if (StringRef("{st}").equals_lower(Constraint)) {
25507 Res.first = X86::FP0;
25508 Res.second = &X86::RFP80RegClass;
25513 if (StringRef("{flags}").equals_lower(Constraint)) {
25514 Res.first = X86::EFLAGS;
25515 Res.second = &X86::CCRRegClass;
25519 // 'A' means EAX + EDX.
25520 if (Constraint == "A") {
25521 Res.first = X86::EAX;
25522 Res.second = &X86::GR32_ADRegClass;
25528 // Otherwise, check to see if this is a register class of the wrong value
25529 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25530 // turn into {ax},{dx}.
25531 if (Res.second->hasType(VT))
25532 return Res; // Correct type already, nothing to do.
25534 // All of the single-register GCC register classes map their values onto
25535 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
25536 // really want an 8-bit or 32-bit register, map to the appropriate register
25537 // class and return the appropriate register.
25538 if (Res.second == &X86::GR16RegClass) {
25539 if (VT == MVT::i8 || VT == MVT::i1) {
25540 unsigned DestReg = 0;
25541 switch (Res.first) {
25543 case X86::AX: DestReg = X86::AL; break;
25544 case X86::DX: DestReg = X86::DL; break;
25545 case X86::CX: DestReg = X86::CL; break;
25546 case X86::BX: DestReg = X86::BL; break;
25549 Res.first = DestReg;
25550 Res.second = &X86::GR8RegClass;
25552 } else if (VT == MVT::i32 || VT == MVT::f32) {
25553 unsigned DestReg = 0;
25554 switch (Res.first) {
25556 case X86::AX: DestReg = X86::EAX; break;
25557 case X86::DX: DestReg = X86::EDX; break;
25558 case X86::CX: DestReg = X86::ECX; break;
25559 case X86::BX: DestReg = X86::EBX; break;
25560 case X86::SI: DestReg = X86::ESI; break;
25561 case X86::DI: DestReg = X86::EDI; break;
25562 case X86::BP: DestReg = X86::EBP; break;
25563 case X86::SP: DestReg = X86::ESP; break;
25566 Res.first = DestReg;
25567 Res.second = &X86::GR32RegClass;
25569 } else if (VT == MVT::i64 || VT == MVT::f64) {
25570 unsigned DestReg = 0;
25571 switch (Res.first) {
25573 case X86::AX: DestReg = X86::RAX; break;
25574 case X86::DX: DestReg = X86::RDX; break;
25575 case X86::CX: DestReg = X86::RCX; break;
25576 case X86::BX: DestReg = X86::RBX; break;
25577 case X86::SI: DestReg = X86::RSI; break;
25578 case X86::DI: DestReg = X86::RDI; break;
25579 case X86::BP: DestReg = X86::RBP; break;
25580 case X86::SP: DestReg = X86::RSP; break;
25583 Res.first = DestReg;
25584 Res.second = &X86::GR64RegClass;
25586 } else if (VT != MVT::Other) {
25587 // Type mismatch and not a clobber: Return an error;
25589 Res.second = nullptr;
25591 } else if (Res.second == &X86::FR32RegClass ||
25592 Res.second == &X86::FR64RegClass ||
25593 Res.second == &X86::VR128RegClass ||
25594 Res.second == &X86::VR256RegClass ||
25595 Res.second == &X86::FR32XRegClass ||
25596 Res.second == &X86::FR64XRegClass ||
25597 Res.second == &X86::VR128XRegClass ||
25598 Res.second == &X86::VR256XRegClass ||
25599 Res.second == &X86::VR512RegClass) {
25600 // Handle references to XMM physical registers that got mapped into the
25601 // wrong class. This can happen with constraints like {xmm0} where the
25602 // target independent register mapper will just pick the first match it can
25603 // find, ignoring the required type.
25605 if (VT == MVT::f32 || VT == MVT::i32)
25606 Res.second = &X86::FR32RegClass;
25607 else if (VT == MVT::f64 || VT == MVT::i64)
25608 Res.second = &X86::FR64RegClass;
25609 else if (X86::VR128RegClass.hasType(VT))
25610 Res.second = &X86::VR128RegClass;
25611 else if (X86::VR256RegClass.hasType(VT))
25612 Res.second = &X86::VR256RegClass;
25613 else if (X86::VR512RegClass.hasType(VT))
25614 Res.second = &X86::VR512RegClass;
25615 else if (VT != MVT::Other) {
25616 // Type mismatch and not a clobber: Return an error;
25618 Res.second = nullptr;
25620 } else if (VT != MVT::Other) {
25621 // Type mismatch and not a clobber: Return an error;
25623 Res.second = nullptr;
25629 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
25631 unsigned AS) const {
25632 // Scaling factors are not free at all.
25633 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
25634 // will take 2 allocations in the out of order engine instead of 1
25635 // for plain addressing mode, i.e. inst (reg1).
25637 // vaddps (%rsi,%drx), %ymm0, %ymm1
25638 // Requires two allocations (one for the load, one for the computation)
25640 // vaddps (%rsi), %ymm0, %ymm1
25641 // Requires just 1 allocation, i.e., freeing allocations for other operations
25642 // and having less micro operations to execute.
25644 // For some X86 architectures, this is even worse because for instance for
25645 // stores, the complex addressing mode forces the instruction to use the
25646 // "load" ports instead of the dedicated "store" port.
25647 // E.g., on Haswell:
25648 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
25649 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
25650 if (isLegalAddressingMode(AM, Ty, AS))
25651 // Scale represents reg2 * scale, thus account for 1
25652 // as soon as we use a second register.
25653 return AM.Scale != 0;
25657 bool X86TargetLowering::isTargetFTOL() const {
25658 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();