1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SSARegMap.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
29 #include "llvm/ADT/VectorExtras.h"
33 #include "llvm/Support/CommandLine.h"
34 static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
35 cl::desc("Enable fastcc on X86"));
37 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
38 : TargetLowering(TM) {
39 Subtarget = &TM.getSubtarget<X86Subtarget>();
40 X86ScalarSSE = Subtarget->hasSSE2();
42 // Set up the TargetLowering object.
44 // X86 is weird, it always uses i8 for shift amounts and setcc results.
45 setShiftAmountType(MVT::i8);
46 setSetCCResultType(MVT::i8);
47 setSetCCResultContents(ZeroOrOneSetCCResult);
48 setSchedulingPreference(SchedulingForRegPressure);
49 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
50 setStackPointerRegisterToSaveRestore(X86::ESP);
52 // Set up the register classes.
53 addRegisterClass(MVT::i8, X86::R8RegisterClass);
54 addRegisterClass(MVT::i16, X86::R16RegisterClass);
55 addRegisterClass(MVT::i32, X86::R32RegisterClass);
57 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
59 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
60 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
61 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
64 // No SSE i64 SINT_TO_FP, so expand i32 UINT_TO_FP instead.
65 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Expand);
67 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
69 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
71 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
72 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
73 // SSE has no i16 to fp conversion, only i32
75 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
77 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
78 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
81 // We can handle SINT_TO_FP and FP_TO_SINT from/to i64 even though i64
83 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
84 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
86 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
88 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
89 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
92 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
94 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
95 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
98 // Handle FP_TO_UINT by promoting the destination to a larger signed
100 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
101 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
102 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
104 if (X86ScalarSSE && !Subtarget->hasSSE3())
105 // Expand FP_TO_UINT into a select.
106 // FIXME: We would like to use a Custom expander here eventually to do
107 // the optimal thing for SSE vs. the default expansion in the legalizer.
108 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
110 // With SSE3 we can use fisttpll to convert to a signed i64.
111 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
113 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
114 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
116 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
117 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
118 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
119 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
120 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
121 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
125 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
126 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
127 setOperationAction(ISD::FREM , MVT::f64 , Expand);
128 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
129 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
130 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
131 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
132 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
133 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
134 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
135 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
136 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
137 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
138 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
140 setOperationAction(ISD::READIO , MVT::i1 , Expand);
141 setOperationAction(ISD::READIO , MVT::i8 , Expand);
142 setOperationAction(ISD::READIO , MVT::i16 , Expand);
143 setOperationAction(ISD::READIO , MVT::i32 , Expand);
144 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
145 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
146 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
147 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
149 // These should be promoted to a larger select which is supported.
150 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
151 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
153 // X86 wants to expand cmov itself.
154 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
155 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
156 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
157 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
158 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
159 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
160 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
161 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
162 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
163 // X86 ret instruction may pop stack.
164 setOperationAction(ISD::RET , MVT::Other, Custom);
166 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
167 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
168 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
169 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
170 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
171 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
172 // X86 wants to expand memset / memcpy itself.
173 setOperationAction(ISD::MEMSET , MVT::Other, Custom);
174 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
176 // We don't have line number support yet.
177 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
178 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
179 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
181 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
182 setOperationAction(ISD::VASTART , MVT::Other, Custom);
184 // Use the default implementation.
185 setOperationAction(ISD::VAARG , MVT::Other, Expand);
186 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
187 setOperationAction(ISD::VAEND , MVT::Other, Expand);
188 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
189 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
190 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
193 // Set up the FP register classes.
194 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
195 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
197 // SSE has no load+extend ops
198 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
199 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
201 // Use ANDPD to simulate FABS.
202 setOperationAction(ISD::FABS , MVT::f64, Custom);
203 setOperationAction(ISD::FABS , MVT::f32, Custom);
205 // Use XORP to simulate FNEG.
206 setOperationAction(ISD::FNEG , MVT::f64, Custom);
207 setOperationAction(ISD::FNEG , MVT::f32, Custom);
209 // We don't support sin/cos/fmod
210 setOperationAction(ISD::FSIN , MVT::f64, Expand);
211 setOperationAction(ISD::FCOS , MVT::f64, Expand);
212 setOperationAction(ISD::FREM , MVT::f64, Expand);
213 setOperationAction(ISD::FSIN , MVT::f32, Expand);
214 setOperationAction(ISD::FCOS , MVT::f32, Expand);
215 setOperationAction(ISD::FREM , MVT::f32, Expand);
217 // Expand FP immediates into loads from the stack, except for the special
219 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
220 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
221 addLegalFPImmediate(+0.0); // xorps / xorpd
223 // Set up the FP register classes.
224 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
226 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
229 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
230 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
233 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
234 addLegalFPImmediate(+0.0); // FLD0
235 addLegalFPImmediate(+1.0); // FLD1
236 addLegalFPImmediate(-0.0); // FLD0/FCHS
237 addLegalFPImmediate(-1.0); // FLD1/FCHS
240 if (TM.getSubtarget<X86Subtarget>().hasMMX()) {
241 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
242 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
243 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
245 // FIXME: We don't support any ConstantVec's yet. We should custom expand
247 setOperationAction(ISD::ConstantVec, MVT::v8i8, Expand);
248 setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand);
249 setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand);
252 if (TM.getSubtarget<X86Subtarget>().hasSSE1()) {
253 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
255 // FIXME: We don't support any ConstantVec's yet. We should custom expand
257 setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
260 if (TM.getSubtarget<X86Subtarget>().hasSSE2()) {
261 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
262 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
263 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
264 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
265 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
268 // FIXME: We don't support any ConstantVec's yet. We should custom expand
270 setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand);
271 setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand);
272 setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand);
273 setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
274 setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand);
277 computeRegisterProperties();
279 // FIXME: These should be based on subtarget info. Plus, the values should
280 // be smaller when we are in optimizing for size mode.
281 maxStoresPerMemset = 16; // For %llvm.memset -> sequence of stores
282 maxStoresPerMemcpy = 16; // For %llvm.memcpy -> sequence of stores
283 maxStoresPerMemmove = 16; // For %llvm.memmove -> sequence of stores
284 allowUnalignedMemoryAccesses = true; // x86 supports it!
287 std::vector<SDOperand>
288 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
289 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
290 return LowerFastCCArguments(F, DAG);
291 return LowerCCCArguments(F, DAG);
294 std::pair<SDOperand, SDOperand>
295 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
296 bool isVarArg, unsigned CallingConv,
298 SDOperand Callee, ArgListTy &Args,
300 assert((!isVarArg || CallingConv == CallingConv::C) &&
301 "Only C takes varargs!");
303 // If the callee is a GlobalAddress node (quite common, every direct call is)
304 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
305 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
306 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
307 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
308 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
310 if (CallingConv == CallingConv::Fast && EnableFastCC)
311 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
312 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
315 //===----------------------------------------------------------------------===//
316 // C Calling Convention implementation
317 //===----------------------------------------------------------------------===//
319 std::vector<SDOperand>
320 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
321 std::vector<SDOperand> ArgValues;
323 MachineFunction &MF = DAG.getMachineFunction();
324 MachineFrameInfo *MFI = MF.getFrameInfo();
326 // Add DAG nodes to load the arguments... On entry to a function on the X86,
327 // the stack frame looks like this:
329 // [ESP] -- return address
330 // [ESP + 4] -- first argument (leftmost lexically)
331 // [ESP + 8] -- second argument, if first argument is four bytes in size
334 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
335 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
336 MVT::ValueType ObjectVT = getValueType(I->getType());
337 unsigned ArgIncrement = 4;
340 default: assert(0 && "Unhandled argument type!");
342 case MVT::i8: ObjSize = 1; break;
343 case MVT::i16: ObjSize = 2; break;
344 case MVT::i32: ObjSize = 4; break;
345 case MVT::i64: ObjSize = ArgIncrement = 8; break;
346 case MVT::f32: ObjSize = 4; break;
347 case MVT::f64: ObjSize = ArgIncrement = 8; break;
349 // Create the frame index object for this incoming parameter...
350 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
352 // Create the SelectionDAG nodes corresponding to a load from this parameter
353 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
355 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
359 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
360 DAG.getSrcValue(NULL));
362 if (MVT::isInteger(ObjectVT))
363 ArgValue = DAG.getConstant(0, ObjectVT);
365 ArgValue = DAG.getConstantFP(0, ObjectVT);
367 ArgValues.push_back(ArgValue);
369 ArgOffset += ArgIncrement; // Move on to the next argument...
372 // If the function takes variable number of arguments, make a frame index for
373 // the start of the first vararg value... for expansion of llvm.va_start.
375 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
376 ReturnAddrIndex = 0; // No return address slot generated yet.
377 BytesToPopOnReturn = 0; // Callee pops nothing.
378 BytesCallerReserves = ArgOffset;
380 // Finally, inform the code generator which regs we return values in.
381 switch (getValueType(F.getReturnType())) {
382 default: assert(0 && "Unknown type!");
383 case MVT::isVoid: break;
388 MF.addLiveOut(X86::EAX);
391 MF.addLiveOut(X86::EAX);
392 MF.addLiveOut(X86::EDX);
396 MF.addLiveOut(X86::ST0);
402 std::pair<SDOperand, SDOperand>
403 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
404 bool isVarArg, bool isTailCall,
405 SDOperand Callee, ArgListTy &Args,
407 // Count how many bytes are to be pushed on the stack.
408 unsigned NumBytes = 0;
412 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(0, getPointerTy()));
414 for (unsigned i = 0, e = Args.size(); i != e; ++i)
415 switch (getValueType(Args[i].second)) {
416 default: assert(0 && "Unknown value type!");
430 Chain = DAG.getCALLSEQ_START(Chain,
431 DAG.getConstant(NumBytes, getPointerTy()));
433 // Arguments go on the stack in reverse order, as specified by the ABI.
434 unsigned ArgOffset = 0;
435 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
436 std::vector<SDOperand> Stores;
438 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
439 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
440 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
442 switch (getValueType(Args[i].second)) {
443 default: assert(0 && "Unexpected ValueType for argument!");
447 // Promote the integer to 32 bits. If the input type is signed use a
448 // sign extend, otherwise use a zero extend.
449 if (Args[i].second->isSigned())
450 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
452 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
457 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
458 Args[i].first, PtrOff,
459 DAG.getSrcValue(NULL)));
464 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
465 Args[i].first, PtrOff,
466 DAG.getSrcValue(NULL)));
471 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
474 std::vector<MVT::ValueType> RetVals;
475 MVT::ValueType RetTyVT = getValueType(RetTy);
476 RetVals.push_back(MVT::Other);
478 // The result values produced have to be legal. Promote the result.
480 case MVT::isVoid: break;
482 RetVals.push_back(RetTyVT);
487 RetVals.push_back(MVT::i32);
491 RetVals.push_back(MVT::f32);
493 RetVals.push_back(MVT::f64);
496 RetVals.push_back(MVT::i32);
497 RetVals.push_back(MVT::i32);
501 std::vector<MVT::ValueType> NodeTys;
502 NodeTys.push_back(MVT::Other); // Returns a chain
503 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
504 std::vector<SDOperand> Ops;
505 Ops.push_back(Chain);
506 Ops.push_back(Callee);
508 // FIXME: Do not generate X86ISD::TAILCALL for now.
509 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
510 SDOperand InFlag = Chain.getValue(1);
513 NodeTys.push_back(MVT::Other); // Returns a chain
514 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
516 Ops.push_back(Chain);
517 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
518 Ops.push_back(DAG.getConstant(0, getPointerTy()));
519 Ops.push_back(InFlag);
520 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
521 InFlag = Chain.getValue(1);
524 if (RetTyVT != MVT::isVoid) {
526 default: assert(0 && "Unknown value type to return!");
529 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
530 Chain = RetVal.getValue(1);
531 if (RetTyVT == MVT::i1)
532 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
535 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
536 Chain = RetVal.getValue(1);
539 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
540 Chain = RetVal.getValue(1);
543 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
544 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
546 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
547 Chain = Hi.getValue(1);
552 std::vector<MVT::ValueType> Tys;
553 Tys.push_back(MVT::f64);
554 Tys.push_back(MVT::Other);
555 Tys.push_back(MVT::Flag);
556 std::vector<SDOperand> Ops;
557 Ops.push_back(Chain);
558 Ops.push_back(InFlag);
559 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
560 Chain = RetVal.getValue(1);
561 InFlag = RetVal.getValue(2);
563 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
564 // shouldn't be necessary except that RFP cannot be live across
565 // multiple blocks. When stackifier is fixed, they can be uncoupled.
566 MachineFunction &MF = DAG.getMachineFunction();
567 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
568 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
570 Tys.push_back(MVT::Other);
572 Ops.push_back(Chain);
573 Ops.push_back(RetVal);
574 Ops.push_back(StackSlot);
575 Ops.push_back(DAG.getValueType(RetTyVT));
576 Ops.push_back(InFlag);
577 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
578 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
579 DAG.getSrcValue(NULL));
580 Chain = RetVal.getValue(1);
583 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
584 // FIXME: we would really like to remember that this FP_ROUND
585 // operation is okay to eliminate if we allow excess FP precision.
586 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
592 return std::make_pair(RetVal, Chain);
595 //===----------------------------------------------------------------------===//
596 // Fast Calling Convention implementation
597 //===----------------------------------------------------------------------===//
599 // The X86 'fast' calling convention passes up to two integer arguments in
600 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
601 // and requires that the callee pop its arguments off the stack (allowing proper
602 // tail calls), and has the same return value conventions as C calling convs.
604 // This calling convention always arranges for the callee pop value to be 8n+4
605 // bytes, which is needed for tail recursion elimination and stack alignment
608 // Note that this can be enhanced in the future to pass fp vals in registers
609 // (when we have a global fp allocator) and do other tricks.
612 /// AddLiveIn - This helper function adds the specified physical register to the
613 /// MachineFunction as a live in value. It also creates a corresponding virtual
615 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
616 TargetRegisterClass *RC) {
617 assert(RC->contains(PReg) && "Not the correct regclass!");
618 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
619 MF.addLiveIn(PReg, VReg);
624 std::vector<SDOperand>
625 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
626 std::vector<SDOperand> ArgValues;
628 MachineFunction &MF = DAG.getMachineFunction();
629 MachineFrameInfo *MFI = MF.getFrameInfo();
631 // Add DAG nodes to load the arguments... On entry to a function the stack
632 // frame looks like this:
634 // [ESP] -- return address
635 // [ESP + 4] -- first nonreg argument (leftmost lexically)
636 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
638 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
640 // Keep track of the number of integer regs passed so far. This can be either
641 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
643 unsigned NumIntRegs = 0;
645 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
646 MVT::ValueType ObjectVT = getValueType(I->getType());
647 unsigned ArgIncrement = 4;
648 unsigned ObjSize = 0;
652 default: assert(0 && "Unhandled argument type!");
655 if (NumIntRegs < 2) {
656 if (!I->use_empty()) {
657 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
658 X86::R8RegisterClass);
659 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
660 DAG.setRoot(ArgValue.getValue(1));
661 if (ObjectVT == MVT::i1)
662 // FIXME: Should insert a assertzext here.
663 ArgValue = DAG.getNode(ISD::TRUNCATE, MVT::i1, ArgValue);
672 if (NumIntRegs < 2) {
673 if (!I->use_empty()) {
674 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
675 X86::R16RegisterClass);
676 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
677 DAG.setRoot(ArgValue.getValue(1));
685 if (NumIntRegs < 2) {
686 if (!I->use_empty()) {
687 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
688 X86::R32RegisterClass);
689 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
690 DAG.setRoot(ArgValue.getValue(1));
698 if (NumIntRegs == 0) {
699 if (!I->use_empty()) {
700 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
701 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
703 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
704 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
705 DAG.setRoot(Hi.getValue(1));
707 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
711 } else if (NumIntRegs == 1) {
712 if (!I->use_empty()) {
713 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
714 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
715 DAG.setRoot(Low.getValue(1));
717 // Load the high part from memory.
718 // Create the frame index object for this incoming parameter...
719 int FI = MFI->CreateFixedObject(4, ArgOffset);
720 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
721 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
722 DAG.getSrcValue(NULL));
723 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
729 ObjSize = ArgIncrement = 8;
731 case MVT::f32: ObjSize = 4; break;
732 case MVT::f64: ObjSize = ArgIncrement = 8; break;
735 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
737 if (ObjSize && !I->use_empty()) {
738 // Create the frame index object for this incoming parameter...
739 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
741 // Create the SelectionDAG nodes corresponding to a load from this
743 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
745 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
746 DAG.getSrcValue(NULL));
747 } else if (ArgValue.Val == 0) {
748 if (MVT::isInteger(ObjectVT))
749 ArgValue = DAG.getConstant(0, ObjectVT);
751 ArgValue = DAG.getConstantFP(0, ObjectVT);
753 ArgValues.push_back(ArgValue);
756 ArgOffset += ArgIncrement; // Move on to the next argument.
759 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
760 // arguments and the arguments after the retaddr has been pushed are aligned.
761 if ((ArgOffset & 7) == 0)
764 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
765 ReturnAddrIndex = 0; // No return address slot generated yet.
766 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
767 BytesCallerReserves = 0;
769 // Finally, inform the code generator which regs we return values in.
770 switch (getValueType(F.getReturnType())) {
771 default: assert(0 && "Unknown type!");
772 case MVT::isVoid: break;
777 MF.addLiveOut(X86::EAX);
780 MF.addLiveOut(X86::EAX);
781 MF.addLiveOut(X86::EDX);
785 MF.addLiveOut(X86::ST0);
791 std::pair<SDOperand, SDOperand>
792 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
793 bool isTailCall, SDOperand Callee,
794 ArgListTy &Args, SelectionDAG &DAG) {
795 // Count how many bytes are to be pushed on the stack.
796 unsigned NumBytes = 0;
798 // Keep track of the number of integer regs passed so far. This can be either
799 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
801 unsigned NumIntRegs = 0;
803 for (unsigned i = 0, e = Args.size(); i != e; ++i)
804 switch (getValueType(Args[i].second)) {
805 default: assert(0 && "Unknown value type!");
810 if (NumIntRegs < 2) {
819 if (NumIntRegs == 0) {
822 } else if (NumIntRegs == 1) {
834 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
835 // arguments and the arguments after the retaddr has been pushed are aligned.
836 if ((NumBytes & 7) == 0)
839 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
841 // Arguments go on the stack in reverse order, as specified by the ABI.
842 unsigned ArgOffset = 0;
843 SDOperand StackPtr = DAG.getRegister(X86::ESP, MVT::i32);
845 std::vector<SDOperand> Stores;
846 std::vector<SDOperand> RegValuesToPass;
847 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
848 switch (getValueType(Args[i].second)) {
849 default: assert(0 && "Unexpected ValueType for argument!");
851 Args[i].first = DAG.getNode(ISD::ANY_EXTEND, MVT::i8, Args[i].first);
856 if (NumIntRegs < 2) {
857 RegValuesToPass.push_back(Args[i].first);
863 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
864 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
865 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
866 Args[i].first, PtrOff,
867 DAG.getSrcValue(NULL)));
872 if (NumIntRegs < 2) { // Can pass part of it in regs?
873 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
874 Args[i].first, DAG.getConstant(1, MVT::i32));
875 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
876 Args[i].first, DAG.getConstant(0, MVT::i32));
877 RegValuesToPass.push_back(Lo);
879 if (NumIntRegs < 2) { // Pass both parts in regs?
880 RegValuesToPass.push_back(Hi);
883 // Pass the high part in memory.
884 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
885 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
886 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
887 Hi, PtrOff, DAG.getSrcValue(NULL)));
894 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
895 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
896 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
897 Args[i].first, PtrOff,
898 DAG.getSrcValue(NULL)));
904 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
906 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
907 // arguments and the arguments after the retaddr has been pushed are aligned.
908 if ((ArgOffset & 7) == 0)
911 std::vector<MVT::ValueType> RetVals;
912 MVT::ValueType RetTyVT = getValueType(RetTy);
914 RetVals.push_back(MVT::Other);
916 // The result values produced have to be legal. Promote the result.
918 case MVT::isVoid: break;
920 RetVals.push_back(RetTyVT);
925 RetVals.push_back(MVT::i32);
929 RetVals.push_back(MVT::f32);
931 RetVals.push_back(MVT::f64);
934 RetVals.push_back(MVT::i32);
935 RetVals.push_back(MVT::i32);
939 // Build a sequence of copy-to-reg nodes chained together with token chain
940 // and flag operands which copy the outgoing args into registers.
942 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
944 SDOperand RegToPass = RegValuesToPass[i];
945 switch (RegToPass.getValueType()) {
946 default: assert(0 && "Bad thing to pass in regs");
948 CCReg = (i == 0) ? X86::AL : X86::DL;
951 CCReg = (i == 0) ? X86::AX : X86::DX;
954 CCReg = (i == 0) ? X86::EAX : X86::EDX;
958 Chain = DAG.getCopyToReg(Chain, CCReg, RegToPass, InFlag);
959 InFlag = Chain.getValue(1);
962 std::vector<MVT::ValueType> NodeTys;
963 NodeTys.push_back(MVT::Other); // Returns a chain
964 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
965 std::vector<SDOperand> Ops;
966 Ops.push_back(Chain);
967 Ops.push_back(Callee);
969 Ops.push_back(InFlag);
971 // FIXME: Do not generate X86ISD::TAILCALL for now.
972 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops);
973 InFlag = Chain.getValue(1);
976 NodeTys.push_back(MVT::Other); // Returns a chain
977 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
979 Ops.push_back(Chain);
980 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
981 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
982 Ops.push_back(InFlag);
983 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, Ops);
984 InFlag = Chain.getValue(1);
987 if (RetTyVT != MVT::isVoid) {
989 default: assert(0 && "Unknown value type to return!");
992 RetVal = DAG.getCopyFromReg(Chain, X86::AL, MVT::i8, InFlag);
993 Chain = RetVal.getValue(1);
994 if (RetTyVT == MVT::i1)
995 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::i1, RetVal);
998 RetVal = DAG.getCopyFromReg(Chain, X86::AX, MVT::i16, InFlag);
999 Chain = RetVal.getValue(1);
1002 RetVal = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1003 Chain = RetVal.getValue(1);
1006 SDOperand Lo = DAG.getCopyFromReg(Chain, X86::EAX, MVT::i32, InFlag);
1007 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), X86::EDX, MVT::i32,
1009 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1010 Chain = Hi.getValue(1);
1015 std::vector<MVT::ValueType> Tys;
1016 Tys.push_back(MVT::f64);
1017 Tys.push_back(MVT::Other);
1018 Tys.push_back(MVT::Flag);
1019 std::vector<SDOperand> Ops;
1020 Ops.push_back(Chain);
1021 Ops.push_back(InFlag);
1022 RetVal = DAG.getNode(X86ISD::FP_GET_RESULT, Tys, Ops);
1023 Chain = RetVal.getValue(1);
1024 InFlag = RetVal.getValue(2);
1026 // FIXME: Currently the FST is flagged to the FP_GET_RESULT. This
1027 // shouldn't be necessary except that RFP cannot be live across
1028 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1029 MachineFunction &MF = DAG.getMachineFunction();
1030 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1031 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1033 Tys.push_back(MVT::Other);
1035 Ops.push_back(Chain);
1036 Ops.push_back(RetVal);
1037 Ops.push_back(StackSlot);
1038 Ops.push_back(DAG.getValueType(RetTyVT));
1039 Ops.push_back(InFlag);
1040 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1041 RetVal = DAG.getLoad(RetTyVT, Chain, StackSlot,
1042 DAG.getSrcValue(NULL));
1043 Chain = RetVal.getValue(1);
1046 if (RetTyVT == MVT::f32 && !X86ScalarSSE)
1047 // FIXME: we would really like to remember that this FP_ROUND
1048 // operation is okay to eliminate if we allow excess FP precision.
1049 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal);
1055 return std::make_pair(RetVal, Chain);
1058 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1059 if (ReturnAddrIndex == 0) {
1060 // Set up a frame object for the return address.
1061 MachineFunction &MF = DAG.getMachineFunction();
1062 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
1065 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
1070 std::pair<SDOperand, SDOperand> X86TargetLowering::
1071 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
1072 SelectionDAG &DAG) {
1074 if (Depth) // Depths > 0 not supported yet!
1075 Result = DAG.getConstant(0, getPointerTy());
1077 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
1078 if (!isFrameAddress)
1079 // Just load the return address
1080 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
1081 DAG.getSrcValue(NULL));
1083 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
1084 DAG.getConstant(4, MVT::i32));
1086 return std::make_pair(Result, Chain);
1089 /// getCondBrOpcodeForX86CC - Returns the X86 conditional branch opcode
1090 /// which corresponds to the condition code.
1091 static unsigned getCondBrOpcodeForX86CC(unsigned X86CC) {
1093 default: assert(0 && "Unknown X86 conditional code!");
1094 case X86ISD::COND_A: return X86::JA;
1095 case X86ISD::COND_AE: return X86::JAE;
1096 case X86ISD::COND_B: return X86::JB;
1097 case X86ISD::COND_BE: return X86::JBE;
1098 case X86ISD::COND_E: return X86::JE;
1099 case X86ISD::COND_G: return X86::JG;
1100 case X86ISD::COND_GE: return X86::JGE;
1101 case X86ISD::COND_L: return X86::JL;
1102 case X86ISD::COND_LE: return X86::JLE;
1103 case X86ISD::COND_NE: return X86::JNE;
1104 case X86ISD::COND_NO: return X86::JNO;
1105 case X86ISD::COND_NP: return X86::JNP;
1106 case X86ISD::COND_NS: return X86::JNS;
1107 case X86ISD::COND_O: return X86::JO;
1108 case X86ISD::COND_P: return X86::JP;
1109 case X86ISD::COND_S: return X86::JS;
1113 /// translateX86CC - do a one to one translation of a ISD::CondCode to the X86
1114 /// specific condition code. It returns a false if it cannot do a direct
1115 /// translation. X86CC is the translated CondCode. Flip is set to true if the
1116 /// the order of comparison operands should be flipped.
1117 static bool translateX86CC(SDOperand CC, bool isFP, unsigned &X86CC,
1119 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1121 X86CC = X86ISD::COND_INVALID;
1123 switch (SetCCOpcode) {
1125 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1126 case ISD::SETGT: X86CC = X86ISD::COND_G; break;
1127 case ISD::SETGE: X86CC = X86ISD::COND_GE; break;
1128 case ISD::SETLT: X86CC = X86ISD::COND_L; break;
1129 case ISD::SETLE: X86CC = X86ISD::COND_LE; break;
1130 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1131 case ISD::SETULT: X86CC = X86ISD::COND_B; break;
1132 case ISD::SETUGT: X86CC = X86ISD::COND_A; break;
1133 case ISD::SETULE: X86CC = X86ISD::COND_BE; break;
1134 case ISD::SETUGE: X86CC = X86ISD::COND_AE; break;
1137 // On a floating point condition, the flags are set as follows:
1139 // 0 | 0 | 0 | X > Y
1140 // 0 | 0 | 1 | X < Y
1141 // 1 | 0 | 0 | X == Y
1142 // 1 | 1 | 1 | unordered
1143 switch (SetCCOpcode) {
1146 case ISD::SETEQ: X86CC = X86ISD::COND_E; break;
1147 case ISD::SETOLE: Flip = true; // Fallthrough
1149 case ISD::SETGT: X86CC = X86ISD::COND_A; break;
1150 case ISD::SETOLT: Flip = true; // Fallthrough
1152 case ISD::SETGE: X86CC = X86ISD::COND_AE; break;
1153 case ISD::SETUGE: Flip = true; // Fallthrough
1155 case ISD::SETLT: X86CC = X86ISD::COND_B; break;
1156 case ISD::SETUGT: Flip = true; // Fallthrough
1158 case ISD::SETLE: X86CC = X86ISD::COND_BE; break;
1160 case ISD::SETNE: X86CC = X86ISD::COND_NE; break;
1161 case ISD::SETUO: X86CC = X86ISD::COND_P; break;
1162 case ISD::SETO: X86CC = X86ISD::COND_NP; break;
1166 return X86CC != X86ISD::COND_INVALID;
1169 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
1170 /// code. Current x86 isa includes the following FP cmov instructions:
1171 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
1172 static bool hasFPCMov(unsigned X86CC) {
1176 case X86ISD::COND_B:
1177 case X86ISD::COND_BE:
1178 case X86ISD::COND_E:
1179 case X86ISD::COND_P:
1180 case X86ISD::COND_A:
1181 case X86ISD::COND_AE:
1182 case X86ISD::COND_NE:
1183 case X86ISD::COND_NP:
1189 X86TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1190 MachineBasicBlock *BB) {
1191 switch (MI->getOpcode()) {
1192 default: assert(false && "Unexpected instr type to insert");
1193 case X86::CMOV_FR32:
1194 case X86::CMOV_FR64: {
1195 // To "insert" a SELECT_CC instruction, we actually have to insert the
1196 // diamond control-flow pattern. The incoming instruction knows the
1197 // destination vreg to set, the condition code register to branch on, the
1198 // true/false values to select between, and a branch opcode to use.
1199 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1200 ilist<MachineBasicBlock>::iterator It = BB;
1206 // cmpTY ccX, r1, r2
1208 // fallthrough --> copy0MBB
1209 MachineBasicBlock *thisMBB = BB;
1210 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1211 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1212 unsigned Opc = getCondBrOpcodeForX86CC(MI->getOperand(3).getImmedValue());
1213 BuildMI(BB, Opc, 1).addMBB(sinkMBB);
1214 MachineFunction *F = BB->getParent();
1215 F->getBasicBlockList().insert(It, copy0MBB);
1216 F->getBasicBlockList().insert(It, sinkMBB);
1217 // Update machine-CFG edges
1218 BB->addSuccessor(copy0MBB);
1219 BB->addSuccessor(sinkMBB);
1222 // %FalseValue = ...
1223 // # fallthrough to sinkMBB
1226 // Update machine-CFG edges
1227 BB->addSuccessor(sinkMBB);
1230 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1233 BuildMI(BB, X86::PHI, 4, MI->getOperand(0).getReg())
1234 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1235 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1237 delete MI; // The pseudo instruction is gone now.
1241 case X86::FP_TO_INT16_IN_MEM:
1242 case X86::FP_TO_INT32_IN_MEM:
1243 case X86::FP_TO_INT64_IN_MEM: {
1244 // Change the floating point control register to use "round towards zero"
1245 // mode when truncating to an integer value.
1246 MachineFunction *F = BB->getParent();
1247 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
1248 addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
1250 // Load the old value of the high byte of the control word...
1252 F->getSSARegMap()->createVirtualRegister(X86::R16RegisterClass);
1253 addFrameReference(BuildMI(BB, X86::MOV16rm, 4, OldCW), CWFrameIdx);
1255 // Set the high part to be round to zero...
1256 addFrameReference(BuildMI(BB, X86::MOV16mi, 5), CWFrameIdx).addImm(0xC7F);
1258 // Reload the modified control word now...
1259 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1261 // Restore the memory image of control word to original value
1262 addFrameReference(BuildMI(BB, X86::MOV16mr, 5), CWFrameIdx).addReg(OldCW);
1264 // Get the X86 opcode to use.
1266 switch (MI->getOpcode()) {
1267 default: assert(0 && "illegal opcode!");
1268 case X86::FP_TO_INT16_IN_MEM: Opc = X86::FpIST16m; break;
1269 case X86::FP_TO_INT32_IN_MEM: Opc = X86::FpIST32m; break;
1270 case X86::FP_TO_INT64_IN_MEM: Opc = X86::FpIST64m; break;
1274 MachineOperand &Op = MI->getOperand(0);
1275 if (Op.isRegister()) {
1276 AM.BaseType = X86AddressMode::RegBase;
1277 AM.Base.Reg = Op.getReg();
1279 AM.BaseType = X86AddressMode::FrameIndexBase;
1280 AM.Base.FrameIndex = Op.getFrameIndex();
1282 Op = MI->getOperand(1);
1283 if (Op.isImmediate())
1284 AM.Scale = Op.getImmedValue();
1285 Op = MI->getOperand(2);
1286 if (Op.isImmediate())
1287 AM.IndexReg = Op.getImmedValue();
1288 Op = MI->getOperand(3);
1289 if (Op.isGlobalAddress()) {
1290 AM.GV = Op.getGlobal();
1292 AM.Disp = Op.getImmedValue();
1294 addFullAddress(BuildMI(BB, Opc, 5), AM).addReg(MI->getOperand(4).getReg());
1296 // Reload the original control word now.
1297 addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
1299 delete MI; // The pseudo instruction is gone now.
1306 //===----------------------------------------------------------------------===//
1307 // X86 Custom Lowering Hooks
1308 //===----------------------------------------------------------------------===//
1310 /// LowerOperation - Provide custom lowering hooks for some operations.
1312 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1313 switch (Op.getOpcode()) {
1314 default: assert(0 && "Should not custom lower this!");
1315 case ISD::SHL_PARTS:
1316 case ISD::SRA_PARTS:
1317 case ISD::SRL_PARTS: {
1318 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1319 "Not an i64 shift!");
1320 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
1321 SDOperand ShOpLo = Op.getOperand(0);
1322 SDOperand ShOpHi = Op.getOperand(1);
1323 SDOperand ShAmt = Op.getOperand(2);
1324 SDOperand Tmp1 = isSRA ? DAG.getNode(ISD::SRA, MVT::i32, ShOpHi,
1325 DAG.getConstant(31, MVT::i8))
1326 : DAG.getConstant(0, MVT::i32);
1328 SDOperand Tmp2, Tmp3;
1329 if (Op.getOpcode() == ISD::SHL_PARTS) {
1330 Tmp2 = DAG.getNode(X86ISD::SHLD, MVT::i32, ShOpHi, ShOpLo, ShAmt);
1331 Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, ShOpLo, ShAmt);
1333 Tmp2 = DAG.getNode(X86ISD::SHRD, MVT::i32, ShOpLo, ShOpHi, ShAmt);
1334 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
1337 SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
1338 ShAmt, DAG.getConstant(32, MVT::i8));
1341 SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1343 std::vector<MVT::ValueType> Tys;
1344 Tys.push_back(MVT::i32);
1345 Tys.push_back(MVT::Flag);
1346 std::vector<SDOperand> Ops;
1347 if (Op.getOpcode() == ISD::SHL_PARTS) {
1348 Ops.push_back(Tmp2);
1349 Ops.push_back(Tmp3);
1351 Ops.push_back(InFlag);
1352 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1353 InFlag = Hi.getValue(1);
1356 Ops.push_back(Tmp3);
1357 Ops.push_back(Tmp1);
1359 Ops.push_back(InFlag);
1360 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1362 Ops.push_back(Tmp2);
1363 Ops.push_back(Tmp3);
1365 Ops.push_back(InFlag);
1366 Lo = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1367 InFlag = Lo.getValue(1);
1370 Ops.push_back(Tmp3);
1371 Ops.push_back(Tmp1);
1373 Ops.push_back(InFlag);
1374 Hi = DAG.getNode(X86ISD::CMOV, Tys, Ops);
1378 Tys.push_back(MVT::i32);
1379 Tys.push_back(MVT::i32);
1383 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1385 case ISD::SINT_TO_FP: {
1386 assert(Op.getOperand(0).getValueType() <= MVT::i64 &&
1387 Op.getOperand(0).getValueType() >= MVT::i16 &&
1388 "Unknown SINT_TO_FP to lower!");
1391 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
1392 unsigned Size = MVT::getSizeInBits(SrcVT)/8;
1393 MachineFunction &MF = DAG.getMachineFunction();
1394 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1395 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1396 SDOperand Chain = DAG.getNode(ISD::STORE, MVT::Other,
1397 DAG.getEntryNode(), Op.getOperand(0),
1398 StackSlot, DAG.getSrcValue(NULL));
1401 std::vector<MVT::ValueType> Tys;
1402 Tys.push_back(MVT::f64);
1403 Tys.push_back(MVT::Other);
1404 if (X86ScalarSSE) Tys.push_back(MVT::Flag);
1405 std::vector<SDOperand> Ops;
1406 Ops.push_back(Chain);
1407 Ops.push_back(StackSlot);
1408 Ops.push_back(DAG.getValueType(SrcVT));
1409 Result = DAG.getNode(X86ScalarSSE ? X86ISD::FILD_FLAG :X86ISD::FILD,
1413 Chain = Result.getValue(1);
1414 SDOperand InFlag = Result.getValue(2);
1416 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
1417 // shouldn't be necessary except that RFP cannot be live across
1418 // multiple blocks. When stackifier is fixed, they can be uncoupled.
1419 MachineFunction &MF = DAG.getMachineFunction();
1420 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
1421 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1422 std::vector<MVT::ValueType> Tys;
1423 Tys.push_back(MVT::Other);
1424 std::vector<SDOperand> Ops;
1425 Ops.push_back(Chain);
1426 Ops.push_back(Result);
1427 Ops.push_back(StackSlot);
1428 Ops.push_back(DAG.getValueType(Op.getValueType()));
1429 Ops.push_back(InFlag);
1430 Chain = DAG.getNode(X86ISD::FST, Tys, Ops);
1431 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
1432 DAG.getSrcValue(NULL));
1437 case ISD::FP_TO_SINT: {
1438 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1439 "Unknown FP_TO_SINT to lower!");
1440 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1442 MachineFunction &MF = DAG.getMachineFunction();
1443 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1444 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1445 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1448 switch (Op.getValueType()) {
1449 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1450 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1451 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1452 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1455 SDOperand Chain = DAG.getEntryNode();
1456 SDOperand Value = Op.getOperand(0);
1458 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
1459 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Value, StackSlot,
1460 DAG.getSrcValue(0));
1461 std::vector<MVT::ValueType> Tys;
1462 Tys.push_back(MVT::f64);
1463 Tys.push_back(MVT::Other);
1464 std::vector<SDOperand> Ops;
1465 Ops.push_back(Chain);
1466 Ops.push_back(StackSlot);
1467 Ops.push_back(DAG.getValueType(Op.getOperand(0).getValueType()));
1468 Value = DAG.getNode(X86ISD::FLD, Tys, Ops);
1469 Chain = Value.getValue(1);
1470 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1471 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1474 // Build the FP_TO_INT*_IN_MEM
1475 std::vector<SDOperand> Ops;
1476 Ops.push_back(Chain);
1477 Ops.push_back(Value);
1478 Ops.push_back(StackSlot);
1479 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1482 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1483 DAG.getSrcValue(NULL));
1485 case ISD::READCYCLECOUNTER: {
1486 std::vector<MVT::ValueType> Tys;
1487 Tys.push_back(MVT::Other);
1488 Tys.push_back(MVT::Flag);
1489 std::vector<SDOperand> Ops;
1490 Ops.push_back(Op.getOperand(0));
1491 SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
1493 Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
1494 Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
1495 MVT::i32, Ops[0].getValue(2)));
1496 Ops.push_back(Ops[1].getValue(1));
1497 Tys[0] = Tys[1] = MVT::i32;
1498 Tys.push_back(MVT::Other);
1499 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
1502 MVT::ValueType VT = Op.getValueType();
1503 const Type *OpNTy = MVT::getTypeForValueType(VT);
1504 std::vector<Constant*> CV;
1505 if (VT == MVT::f64) {
1506 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(~(1ULL << 63))));
1507 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1509 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(~(1U << 31))));
1510 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1511 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1512 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1514 Constant *CS = ConstantStruct::get(CV);
1515 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
1517 = DAG.getNode(X86ISD::LOAD_PACK,
1518 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
1519 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
1522 MVT::ValueType VT = Op.getValueType();
1523 const Type *OpNTy = MVT::getTypeForValueType(VT);
1524 std::vector<Constant*> CV;
1525 if (VT == MVT::f64) {
1526 CV.push_back(ConstantFP::get(OpNTy, BitsToDouble(1ULL << 63)));
1527 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1529 CV.push_back(ConstantFP::get(OpNTy, BitsToFloat(1U << 31)));
1530 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1531 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1532 CV.push_back(ConstantFP::get(OpNTy, 0.0));
1534 Constant *CS = ConstantStruct::get(CV);
1535 SDOperand CPIdx = DAG.getConstantPool(CS, getPointerTy(), 4);
1537 = DAG.getNode(X86ISD::LOAD_PACK,
1538 VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
1539 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
1542 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
1544 SDOperand CC = Op.getOperand(2);
1545 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
1546 bool isFP = MVT::isFloatingPoint(Op.getOperand(1).getValueType());
1549 if (translateX86CC(CC, isFP, X86CC, Flip)) {
1551 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1552 Op.getOperand(1), Op.getOperand(0));
1554 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1555 Op.getOperand(0), Op.getOperand(1));
1556 return DAG.getNode(X86ISD::SETCC, MVT::i8,
1557 DAG.getConstant(X86CC, MVT::i8), Cond);
1559 assert(isFP && "Illegal integer SetCC!");
1561 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1562 Op.getOperand(0), Op.getOperand(1));
1563 std::vector<MVT::ValueType> Tys;
1564 std::vector<SDOperand> Ops;
1565 switch (SetCCOpcode) {
1566 default: assert(false && "Illegal floating point SetCC!");
1567 case ISD::SETOEQ: { // !PF & ZF
1568 Tys.push_back(MVT::i8);
1569 Tys.push_back(MVT::Flag);
1570 Ops.push_back(DAG.getConstant(X86ISD::COND_NP, MVT::i8));
1571 Ops.push_back(Cond);
1572 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1573 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1574 DAG.getConstant(X86ISD::COND_E, MVT::i8),
1576 return DAG.getNode(ISD::AND, MVT::i8, Tmp1, Tmp2);
1578 case ISD::SETUNE: { // PF | !ZF
1579 Tys.push_back(MVT::i8);
1580 Tys.push_back(MVT::Flag);
1581 Ops.push_back(DAG.getConstant(X86ISD::COND_P, MVT::i8));
1582 Ops.push_back(Cond);
1583 SDOperand Tmp1 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1584 SDOperand Tmp2 = DAG.getNode(X86ISD::SETCC, MVT::i8,
1585 DAG.getConstant(X86ISD::COND_NE, MVT::i8),
1587 return DAG.getNode(ISD::OR, MVT::i8, Tmp1, Tmp2);
1593 MVT::ValueType VT = Op.getValueType();
1594 bool isFP = MVT::isFloatingPoint(VT);
1595 bool isFPStack = isFP && !X86ScalarSSE;
1596 bool isFPSSE = isFP && X86ScalarSSE;
1597 bool addTest = false;
1598 SDOperand Op0 = Op.getOperand(0);
1600 if (Op0.getOpcode() == ISD::SETCC)
1601 Op0 = LowerOperation(Op0, DAG);
1603 if (Op0.getOpcode() == X86ISD::SETCC) {
1604 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1605 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1606 // have another use it will be eliminated.
1607 // If the X86ISD::SETCC has more than one use, then it's probably better
1608 // to use a test instead of duplicating the X86ISD::CMP (for register
1609 // pressure reason).
1610 if (Op0.getOperand(1).getOpcode() == X86ISD::CMP) {
1611 if (!Op0.hasOneUse()) {
1612 std::vector<MVT::ValueType> Tys;
1613 for (unsigned i = 0; i < Op0.Val->getNumValues(); ++i)
1614 Tys.push_back(Op0.Val->getValueType(i));
1615 std::vector<SDOperand> Ops;
1616 for (unsigned i = 0; i < Op0.getNumOperands(); ++i)
1617 Ops.push_back(Op0.getOperand(i));
1618 Op0 = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1621 CC = Op0.getOperand(0);
1622 Cond = Op0.getOperand(1);
1623 // Make a copy as flag result cannot be used by more than one.
1624 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1625 Cond.getOperand(0), Cond.getOperand(1));
1627 isFPStack && !hasFPCMov(cast<ConstantSDNode>(CC)->getSignExtended());
1634 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1635 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
1638 std::vector<MVT::ValueType> Tys;
1639 Tys.push_back(Op.getValueType());
1640 Tys.push_back(MVT::Flag);
1641 std::vector<SDOperand> Ops;
1642 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
1643 // condition is true.
1644 Ops.push_back(Op.getOperand(2));
1645 Ops.push_back(Op.getOperand(1));
1647 Ops.push_back(Cond);
1648 return DAG.getNode(X86ISD::CMOV, Tys, Ops);
1651 bool addTest = false;
1652 SDOperand Cond = Op.getOperand(1);
1653 SDOperand Dest = Op.getOperand(2);
1655 if (Cond.getOpcode() == ISD::SETCC)
1656 Cond = LowerOperation(Cond, DAG);
1658 if (Cond.getOpcode() == X86ISD::SETCC) {
1659 // If condition flag is set by a X86ISD::CMP, then make a copy of it
1660 // (since flag operand cannot be shared). If the X86ISD::SETCC does not
1661 // have another use it will be eliminated.
1662 // If the X86ISD::SETCC has more than one use, then it's probably better
1663 // to use a test instead of duplicating the X86ISD::CMP (for register
1664 // pressure reason).
1665 if (Cond.getOperand(1).getOpcode() == X86ISD::CMP) {
1666 if (!Cond.hasOneUse()) {
1667 std::vector<MVT::ValueType> Tys;
1668 for (unsigned i = 0; i < Cond.Val->getNumValues(); ++i)
1669 Tys.push_back(Cond.Val->getValueType(i));
1670 std::vector<SDOperand> Ops;
1671 for (unsigned i = 0; i < Cond.getNumOperands(); ++i)
1672 Ops.push_back(Cond.getOperand(i));
1673 Cond = DAG.getNode(X86ISD::SETCC, Tys, Ops);
1676 CC = Cond.getOperand(0);
1677 Cond = Cond.getOperand(1);
1678 // Make a copy as flag result cannot be used by more than one.
1679 Cond = DAG.getNode(X86ISD::CMP, MVT::Flag,
1680 Cond.getOperand(0), Cond.getOperand(1));
1687 CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
1688 Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
1690 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
1691 Op.getOperand(0), Op.getOperand(2), CC, Cond);
1695 SDOperand Chain = Op.getOperand(0);
1697 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1698 if (Align == 0) Align = 1;
1700 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
1701 // If not DWORD aligned, call memset if size is less than the threshold.
1702 // It knows how to align to the right boundary first.
1703 if ((Align & 3) != 0 &&
1704 !(I && I->getValue() >= Subtarget->getMinRepStrSizeThreshold())) {
1705 MVT::ValueType IntPtr = getPointerTy();
1706 const Type *IntPtrTy = getTargetData().getIntPtrType();
1707 std::vector<std::pair<SDOperand, const Type*> > Args;
1708 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
1709 // Extend the ubyte argument to be an int value for the call.
1710 SDOperand Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Op.getOperand(2));
1711 Args.push_back(std::make_pair(Val, IntPtrTy));
1712 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
1713 std::pair<SDOperand,SDOperand> CallResult =
1714 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
1715 DAG.getExternalSymbol("memset", IntPtr), Args, DAG);
1716 return CallResult.second;
1721 if (ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Op.getOperand(2))) {
1723 unsigned Val = ValC->getValue() & 255;
1725 // If the value is a constant, then we can potentially use larger sets.
1726 switch (Align & 3) {
1727 case 2: // WORD aligned
1730 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1732 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1733 DAG.getConstant(1, MVT::i8));
1734 Val = (Val << 8) | Val;
1737 case 0: // DWORD aligned
1740 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1742 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1743 DAG.getConstant(2, MVT::i8));
1744 Val = (Val << 8) | Val;
1745 Val = (Val << 16) | Val;
1748 default: // Byte aligned
1750 Count = Op.getOperand(3);
1755 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
1757 InFlag = Chain.getValue(1);
1760 Count = Op.getOperand(3);
1761 Chain = DAG.getCopyToReg(Chain, X86::AL, Op.getOperand(2), InFlag);
1762 InFlag = Chain.getValue(1);
1765 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1766 InFlag = Chain.getValue(1);
1767 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1768 InFlag = Chain.getValue(1);
1770 return DAG.getNode(X86ISD::REP_STOS, MVT::Other, Chain,
1771 DAG.getValueType(AVT), InFlag);
1774 SDOperand Chain = Op.getOperand(0);
1776 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue();
1777 if (Align == 0) Align = 1;
1779 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Op.getOperand(3));
1780 // If not DWORD aligned, call memcpy if size is less than the threshold.
1781 // It knows how to align to the right boundary first.
1782 if ((Align & 3) != 0 &&
1783 !(I && I->getValue() >= Subtarget->getMinRepStrSizeThreshold())) {
1784 MVT::ValueType IntPtr = getPointerTy();
1785 const Type *IntPtrTy = getTargetData().getIntPtrType();
1786 std::vector<std::pair<SDOperand, const Type*> > Args;
1787 Args.push_back(std::make_pair(Op.getOperand(1), IntPtrTy));
1788 Args.push_back(std::make_pair(Op.getOperand(2), IntPtrTy));
1789 Args.push_back(std::make_pair(Op.getOperand(3), IntPtrTy));
1790 std::pair<SDOperand,SDOperand> CallResult =
1791 LowerCallTo(Chain, Type::VoidTy, false, CallingConv::C, false,
1792 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG);
1793 return CallResult.second;
1798 switch (Align & 3) {
1799 case 2: // WORD aligned
1802 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1804 Count = DAG.getConstant(I->getValue() / 2, MVT::i32);
1806 case 0: // DWORD aligned
1809 Count = DAG.getConstant(I->getValue() / 4, MVT::i32);
1811 Count = DAG.getNode(ISD::SRL, MVT::i32, Op.getOperand(3),
1812 DAG.getConstant(2, MVT::i8));
1814 default: // Byte aligned
1816 Count = Op.getOperand(3);
1821 Chain = DAG.getCopyToReg(Chain, X86::ECX, Count, InFlag);
1822 InFlag = Chain.getValue(1);
1823 Chain = DAG.getCopyToReg(Chain, X86::EDI, Op.getOperand(1), InFlag);
1824 InFlag = Chain.getValue(1);
1825 Chain = DAG.getCopyToReg(Chain, X86::ESI, Op.getOperand(2), InFlag);
1826 InFlag = Chain.getValue(1);
1828 return DAG.getNode(X86ISD::REP_MOVS, MVT::Other, Chain,
1829 DAG.getValueType(AVT), InFlag);
1831 case ISD::ConstantPool: {
1832 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1834 DAG.getTargetConstantPool(CP->get(), getPointerTy(), CP->getAlignment());
1835 // Only lower ConstantPool on Darwin.
1836 if (getTargetMachine().
1837 getSubtarget<X86Subtarget>().isTargetDarwin()) {
1838 // With PIC, the address is actually $g + Offset.
1839 if (getTargetMachine().getRelocationModel() == Reloc::PIC)
1840 Result = DAG.getNode(ISD::ADD, getPointerTy(),
1841 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Result);
1846 case ISD::GlobalAddress: {
1848 // Only lower GlobalAddress on Darwin.
1849 if (getTargetMachine().
1850 getSubtarget<X86Subtarget>().isTargetDarwin()) {
1851 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1852 SDOperand Addr = DAG.getTargetGlobalAddress(GV, getPointerTy());
1853 // With PIC, the address is actually $g + Offset.
1854 if (getTargetMachine().getRelocationModel() == Reloc::PIC)
1855 Addr = DAG.getNode(ISD::ADD, getPointerTy(),
1856 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()), Addr);
1858 // For Darwin, external and weak symbols are indirect, so we want to load
1859 // the value at address GV, not the value of GV itself. This means that
1860 // the GlobalAddress must be in the base or index register of the address,
1861 // not the GV offset field.
1862 if (getTargetMachine().getRelocationModel() != Reloc::Static &&
1863 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
1864 (GV->isExternal() && !GV->hasNotBeenReadFromBytecode())))
1865 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(),
1866 Addr, DAG.getSrcValue(NULL));
1871 case ISD::VASTART: {
1872 // vastart just stores the address of the VarArgsFrameIndex slot into the
1873 // memory location argument.
1874 // FIXME: Replace MVT::i32 with PointerTy
1875 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
1876 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
1877 Op.getOperand(1), Op.getOperand(2));
1882 switch(Op.getNumOperands()) {
1884 assert(0 && "Do not know how to return this many arguments!");
1887 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, Op.getOperand(0),
1888 DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1890 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1891 if (MVT::isInteger(ArgVT))
1892 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EAX, Op.getOperand(1),
1894 else if (!X86ScalarSSE) {
1895 std::vector<MVT::ValueType> Tys;
1896 Tys.push_back(MVT::Other);
1897 Tys.push_back(MVT::Flag);
1898 std::vector<SDOperand> Ops;
1899 Ops.push_back(Op.getOperand(0));
1900 Ops.push_back(Op.getOperand(1));
1901 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
1904 SDOperand Chain = Op.getOperand(0);
1905 SDOperand Value = Op.getOperand(1);
1907 if (Value.getOpcode() == ISD::LOAD &&
1908 (Chain == Value.getValue(1) || Chain == Value.getOperand(0))) {
1909 Chain = Value.getOperand(0);
1910 MemLoc = Value.getOperand(1);
1912 // Spill the value to memory and reload it into top of stack.
1913 unsigned Size = MVT::getSizeInBits(ArgVT)/8;
1914 MachineFunction &MF = DAG.getMachineFunction();
1915 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
1916 MemLoc = DAG.getFrameIndex(SSFI, getPointerTy());
1917 Chain = DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0),
1918 Value, MemLoc, DAG.getSrcValue(0));
1920 std::vector<MVT::ValueType> Tys;
1921 Tys.push_back(MVT::f64);
1922 Tys.push_back(MVT::Other);
1923 std::vector<SDOperand> Ops;
1924 Ops.push_back(Chain);
1925 Ops.push_back(MemLoc);
1926 Ops.push_back(DAG.getValueType(ArgVT));
1927 Copy = DAG.getNode(X86ISD::FLD, Tys, Ops);
1929 Tys.push_back(MVT::Other);
1930 Tys.push_back(MVT::Flag);
1932 Ops.push_back(Copy.getValue(1));
1933 Ops.push_back(Copy);
1934 Copy = DAG.getNode(X86ISD::FP_SET_RESULT, Tys, Ops);
1939 Copy = DAG.getCopyToReg(Op.getOperand(0), X86::EDX, Op.getOperand(2),
1941 Copy = DAG.getCopyToReg(Copy, X86::EAX,Op.getOperand(1),Copy.getValue(1));
1944 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other,
1945 Copy, DAG.getConstant(getBytesToPopOnReturn(), MVT::i16),
1951 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
1953 default: return NULL;
1954 case X86ISD::SHLD: return "X86ISD::SHLD";
1955 case X86ISD::SHRD: return "X86ISD::SHRD";
1956 case X86ISD::FAND: return "X86ISD::FAND";
1957 case X86ISD::FXOR: return "X86ISD::FXOR";
1958 case X86ISD::FILD: return "X86ISD::FILD";
1959 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
1960 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
1961 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
1962 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
1963 case X86ISD::FLD: return "X86ISD::FLD";
1964 case X86ISD::FST: return "X86ISD::FST";
1965 case X86ISD::FP_GET_RESULT: return "X86ISD::FP_GET_RESULT";
1966 case X86ISD::FP_SET_RESULT: return "X86ISD::FP_SET_RESULT";
1967 case X86ISD::CALL: return "X86ISD::CALL";
1968 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
1969 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
1970 case X86ISD::CMP: return "X86ISD::CMP";
1971 case X86ISD::TEST: return "X86ISD::TEST";
1972 case X86ISD::SETCC: return "X86ISD::SETCC";
1973 case X86ISD::CMOV: return "X86ISD::CMOV";
1974 case X86ISD::BRCOND: return "X86ISD::BRCOND";
1975 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
1976 case X86ISD::REP_STOS: return "X86ISD::RET_STOS";
1977 case X86ISD::REP_MOVS: return "X86ISD::RET_MOVS";
1978 case X86ISD::LOAD_PACK: return "X86ISD::LOAD_PACK";
1979 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
1983 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1985 uint64_t &KnownZero,
1987 unsigned Depth) const {
1989 unsigned Opc = Op.getOpcode();
1990 KnownZero = KnownOne = 0; // Don't know anything.
1994 assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
1997 KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
2002 std::vector<unsigned> X86TargetLowering::
2003 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2004 MVT::ValueType VT) const {
2005 if (Constraint.size() == 1) {
2006 // FIXME: not handling fp-stack yet!
2007 // FIXME: not handling MMX registers yet ('y' constraint).
2008 switch (Constraint[0]) { // GCC X86 Constraint Letters
2009 default: break; // Unknown constriant letter
2010 case 'r': // GENERAL_REGS
2011 case 'R': // LEGACY_REGS
2012 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
2013 X86::ESI, X86::EDI, X86::EBP, X86::ESP, 0);
2014 case 'l': // INDEX_REGS
2015 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX,
2016 X86::ESI, X86::EDI, X86::EBP, 0);
2017 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
2019 return make_vector<unsigned>(X86::EAX, X86::EBX, X86::ECX, X86::EDX, 0);
2020 case 'x': // SSE_REGS if SSE1 allowed
2021 if (Subtarget->hasSSE1())
2022 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2023 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
2025 return std::vector<unsigned>();
2026 case 'Y': // SSE_REGS if SSE2 allowed
2027 if (Subtarget->hasSSE2())
2028 return make_vector<unsigned>(X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2029 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7,
2031 return std::vector<unsigned>();
2035 return std::vector<unsigned>();