1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86MachineFunctionInfo.h"
19 #include "X86TargetMachine.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/ADT/BitVector.h"
27 #include "llvm/ADT/VectorExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/PseudoSourceValue.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/SmallSet.h"
40 #include "llvm/ADT/StringExtras.h"
41 #include "llvm/Support/CommandLine.h"
45 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
47 // Forward declarations.
48 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG);
50 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
51 : TargetLowering(TM) {
52 Subtarget = &TM.getSubtarget<X86Subtarget>();
53 X86ScalarSSEf64 = Subtarget->hasSSE2();
54 X86ScalarSSEf32 = Subtarget->hasSSE1();
55 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
59 RegInfo = TM.getRegisterInfo();
62 // Set up the TargetLowering object.
64 // X86 is weird, it always uses i8 for shift amounts and setcc results.
65 setShiftAmountType(MVT::i8);
66 setBooleanContents(ZeroOrOneBooleanContent);
67 setSchedulingPreference(SchedulingForRegPressure);
68 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
69 setStackPointerRegisterToSaveRestore(X86StackPtr);
71 if (Subtarget->isTargetDarwin()) {
72 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(false);
74 setUseUnderscoreLongJmp(false);
75 } else if (Subtarget->isTargetMingw()) {
76 // MS runtime is weird: it exports _setjmp, but longjmp!
77 setUseUnderscoreSetJmp(true);
78 setUseUnderscoreLongJmp(false);
80 setUseUnderscoreSetJmp(true);
81 setUseUnderscoreLongJmp(true);
84 // Set up the register classes.
85 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
86 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
87 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
88 if (Subtarget->is64Bit())
89 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
91 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 // We don't accept any truncstore of integer registers.
94 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
95 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
96 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
97 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
98 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
99 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
101 // SETOEQ and SETUNE require checking two conditions.
102 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
103 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
104 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
105 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
106 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
107 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
109 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
111 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
112 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
113 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
115 if (Subtarget->is64Bit()) {
116 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
117 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
119 if (X86ScalarSSEf64) {
120 // We have an impenetrably clever algorithm for ui64->double only.
121 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
123 // We have faster algorithm for ui32->single only.
124 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
126 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
129 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
131 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
132 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
133 // SSE has no i16 to fp conversion, only i32
134 if (X86ScalarSSEf32) {
135 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
136 // f32 and f64 cases are Legal, f80 case is not
137 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
139 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
140 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
143 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
144 // are Legal, f80 is custom lowered.
145 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
146 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
148 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
150 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
151 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
153 if (X86ScalarSSEf32) {
154 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
155 // f32 and f64 cases are Legal, f80 case is not
156 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
158 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
159 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
162 // Handle FP_TO_UINT by promoting the destination to a larger signed
164 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
165 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
166 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
168 if (Subtarget->is64Bit()) {
169 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
170 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
172 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
173 // Expand FP_TO_UINT into a select.
174 // FIXME: We would like to use a Custom expander here eventually to do
175 // the optimal thing for SSE vs. the default expansion in the legalizer.
176 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
178 // With SSE3 we can use fisttpll to convert to a signed i64.
179 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
182 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
183 if (!X86ScalarSSEf64) {
184 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
185 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
188 // Scalar integer divide and remainder are lowered to use operations that
189 // produce two results, to match the available instructions. This exposes
190 // the two-result form to trivial CSE, which is able to combine x/y and x%y
191 // into a single instruction.
193 // Scalar integer multiply-high is also lowered to use two-result
194 // operations, to match the available instructions. However, plain multiply
195 // (low) operations are left as Legal, as there are single-result
196 // instructions for this in x86. Using the two-result multiply instructions
197 // when both high and low results are needed must be arranged by dagcombine.
198 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
199 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
200 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
201 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
202 setOperationAction(ISD::SREM , MVT::i8 , Expand);
203 setOperationAction(ISD::UREM , MVT::i8 , Expand);
204 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
205 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
206 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
207 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
208 setOperationAction(ISD::SREM , MVT::i16 , Expand);
209 setOperationAction(ISD::UREM , MVT::i16 , Expand);
210 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
211 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
212 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
213 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
214 setOperationAction(ISD::SREM , MVT::i32 , Expand);
215 setOperationAction(ISD::UREM , MVT::i32 , Expand);
216 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
217 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
218 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
219 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
220 setOperationAction(ISD::SREM , MVT::i64 , Expand);
221 setOperationAction(ISD::UREM , MVT::i64 , Expand);
223 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
224 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
225 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
226 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
227 if (Subtarget->is64Bit())
228 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
230 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
231 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
232 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
233 setOperationAction(ISD::FREM , MVT::f32 , Expand);
234 setOperationAction(ISD::FREM , MVT::f64 , Expand);
235 setOperationAction(ISD::FREM , MVT::f80 , Expand);
236 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
238 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
239 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
240 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
241 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
242 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
243 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
244 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
245 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
246 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
247 if (Subtarget->is64Bit()) {
248 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
249 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
250 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
253 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
254 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
256 // These should be promoted to a larger select which is supported.
257 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
258 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
259 // X86 wants to expand cmov itself.
260 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
261 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
262 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
263 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
264 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
265 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
266 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
267 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
268 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
269 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
270 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
271 if (Subtarget->is64Bit()) {
272 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
273 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
275 // X86 ret instruction may pop stack.
276 setOperationAction(ISD::RET , MVT::Other, Custom);
277 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
280 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
281 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
282 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
283 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
284 if (Subtarget->is64Bit())
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
287 if (Subtarget->is64Bit()) {
288 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
289 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
290 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
291 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
293 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
294 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
295 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
296 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
297 if (Subtarget->is64Bit()) {
298 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
299 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
300 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
303 if (Subtarget->hasSSE1())
304 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
306 if (!Subtarget->hasSSE2())
307 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
309 // Expand certain atomics
310 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
311 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
312 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
313 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
315 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
316 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
317 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
318 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
320 if (!Subtarget->is64Bit()) {
321 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
322 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
323 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
324 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
325 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
326 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
327 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
330 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
331 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
332 // FIXME - use subtarget debug flags
333 if (!Subtarget->isTargetDarwin() &&
334 !Subtarget->isTargetELF() &&
335 !Subtarget->isTargetCygMing()) {
336 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
337 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
340 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
341 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
342 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
343 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
344 if (Subtarget->is64Bit()) {
345 setExceptionPointerRegister(X86::RAX);
346 setExceptionSelectorRegister(X86::RDX);
348 setExceptionPointerRegister(X86::EAX);
349 setExceptionSelectorRegister(X86::EDX);
351 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
352 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
354 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
356 setOperationAction(ISD::TRAP, MVT::Other, Legal);
358 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
359 setOperationAction(ISD::VASTART , MVT::Other, Custom);
360 setOperationAction(ISD::VAEND , MVT::Other, Expand);
361 if (Subtarget->is64Bit()) {
362 setOperationAction(ISD::VAARG , MVT::Other, Custom);
363 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
365 setOperationAction(ISD::VAARG , MVT::Other, Expand);
366 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
369 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
370 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
371 if (Subtarget->is64Bit())
372 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
373 if (Subtarget->isTargetCygMing())
374 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
376 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
378 if (X86ScalarSSEf64) {
379 // f32 and f64 use SSE.
380 // Set up the FP register classes.
381 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
382 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
384 // Use ANDPD to simulate FABS.
385 setOperationAction(ISD::FABS , MVT::f64, Custom);
386 setOperationAction(ISD::FABS , MVT::f32, Custom);
388 // Use XORP to simulate FNEG.
389 setOperationAction(ISD::FNEG , MVT::f64, Custom);
390 setOperationAction(ISD::FNEG , MVT::f32, Custom);
392 // Use ANDPD and ORPD to simulate FCOPYSIGN.
393 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
394 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
396 // We don't support sin/cos/fmod
397 setOperationAction(ISD::FSIN , MVT::f64, Expand);
398 setOperationAction(ISD::FCOS , MVT::f64, Expand);
399 setOperationAction(ISD::FSIN , MVT::f32, Expand);
400 setOperationAction(ISD::FCOS , MVT::f32, Expand);
402 // Expand FP immediates into loads from the stack, except for the special
404 addLegalFPImmediate(APFloat(+0.0)); // xorpd
405 addLegalFPImmediate(APFloat(+0.0f)); // xorps
407 // Floating truncations from f80 and extensions to f80 go through memory.
408 // If optimizing, we lie about this though and handle it in
409 // InstructionSelectPreprocess so that dagcombine2 can hack on these.
411 setConvertAction(MVT::f32, MVT::f80, Expand);
412 setConvertAction(MVT::f64, MVT::f80, Expand);
413 setConvertAction(MVT::f80, MVT::f32, Expand);
414 setConvertAction(MVT::f80, MVT::f64, Expand);
416 } else if (X86ScalarSSEf32) {
417 // Use SSE for f32, x87 for f64.
418 // Set up the FP register classes.
419 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
420 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
422 // Use ANDPS to simulate FABS.
423 setOperationAction(ISD::FABS , MVT::f32, Custom);
425 // Use XORP to simulate FNEG.
426 setOperationAction(ISD::FNEG , MVT::f32, Custom);
428 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
430 // Use ANDPS and ORPS to simulate FCOPYSIGN.
431 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
432 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
434 // We don't support sin/cos/fmod
435 setOperationAction(ISD::FSIN , MVT::f32, Expand);
436 setOperationAction(ISD::FCOS , MVT::f32, Expand);
438 // Special cases we handle for FP constants.
439 addLegalFPImmediate(APFloat(+0.0f)); // xorps
440 addLegalFPImmediate(APFloat(+0.0)); // FLD0
441 addLegalFPImmediate(APFloat(+1.0)); // FLD1
442 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
443 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
445 // SSE <-> X87 conversions go through memory. If optimizing, we lie about
446 // this though and handle it in InstructionSelectPreprocess so that
447 // dagcombine2 can hack on these.
449 setConvertAction(MVT::f32, MVT::f64, Expand);
450 setConvertAction(MVT::f32, MVT::f80, Expand);
451 setConvertAction(MVT::f80, MVT::f32, Expand);
452 setConvertAction(MVT::f64, MVT::f32, Expand);
453 // And x87->x87 truncations also.
454 setConvertAction(MVT::f80, MVT::f64, Expand);
458 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
459 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
462 // f32 and f64 in x87.
463 // Set up the FP register classes.
464 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
465 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
467 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
468 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
469 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
470 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
472 // Floating truncations go through memory. If optimizing, we lie about
473 // this though and handle it in InstructionSelectPreprocess so that
474 // dagcombine2 can hack on these.
476 setConvertAction(MVT::f80, MVT::f32, Expand);
477 setConvertAction(MVT::f64, MVT::f32, Expand);
478 setConvertAction(MVT::f80, MVT::f64, Expand);
482 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
483 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
485 addLegalFPImmediate(APFloat(+0.0)); // FLD0
486 addLegalFPImmediate(APFloat(+1.0)); // FLD1
487 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
488 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
489 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
490 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
491 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
492 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
495 // Long double always uses X87.
496 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
497 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
498 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
501 APFloat TmpFlt(+0.0);
502 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
504 addLegalFPImmediate(TmpFlt); // FLD0
506 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
507 APFloat TmpFlt2(+1.0);
508 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
510 addLegalFPImmediate(TmpFlt2); // FLD1
511 TmpFlt2.changeSign();
512 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
516 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
517 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
520 // Always use a library call for pow.
521 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
522 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
523 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
525 setOperationAction(ISD::FLOG, MVT::f80, Expand);
526 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
527 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
528 setOperationAction(ISD::FEXP, MVT::f80, Expand);
529 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
531 // First set operation action for all vector types to either promote
532 // (for widening) or expand (for scalarization). Then we will selectively
533 // turn on ones that can be effectively codegen'd.
534 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
535 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
536 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
542 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
543 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
551 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
575 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
576 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
577 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
578 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
581 if (!DisableMMX && Subtarget->hasMMX()) {
582 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
583 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
584 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
585 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
586 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
588 // FIXME: add MMX packed arithmetics
590 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
591 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
592 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
593 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
595 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
596 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
597 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
598 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
600 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
601 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
603 setOperationAction(ISD::AND, MVT::v8i8, Promote);
604 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
605 setOperationAction(ISD::AND, MVT::v4i16, Promote);
606 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
607 setOperationAction(ISD::AND, MVT::v2i32, Promote);
608 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
609 setOperationAction(ISD::AND, MVT::v1i64, Legal);
611 setOperationAction(ISD::OR, MVT::v8i8, Promote);
612 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
613 setOperationAction(ISD::OR, MVT::v4i16, Promote);
614 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
615 setOperationAction(ISD::OR, MVT::v2i32, Promote);
616 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
617 setOperationAction(ISD::OR, MVT::v1i64, Legal);
619 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
620 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
621 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
622 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
623 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
624 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
625 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
627 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
628 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
629 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
630 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
631 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
632 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
633 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
634 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
635 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
638 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
639 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
640 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
641 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
643 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
644 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
645 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
646 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
648 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
649 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
650 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
651 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
653 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
655 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
656 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
657 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
658 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
659 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
660 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
663 if (Subtarget->hasSSE1()) {
664 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
666 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
667 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
668 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
669 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
670 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
671 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
672 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
673 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
674 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
675 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
676 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
677 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
680 if (Subtarget->hasSSE2()) {
681 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
682 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
683 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
684 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
685 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
687 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
688 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
689 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
690 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
691 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
692 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
693 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
694 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
695 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
696 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
697 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
698 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
699 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
700 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
701 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
702 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
704 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
705 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
706 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
707 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
709 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
710 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
711 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
712 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
715 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
716 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
717 MVT VT = (MVT::SimpleValueType)i;
718 // Do not attempt to custom lower non-power-of-2 vectors
719 if (!isPowerOf2_32(VT.getVectorNumElements()))
721 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
722 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
723 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
725 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
726 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
727 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
728 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
729 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
730 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
731 if (Subtarget->is64Bit()) {
732 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
733 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
736 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
737 for (unsigned VT = (unsigned)MVT::v16i8; VT != (unsigned)MVT::v2i64; VT++) {
738 setOperationAction(ISD::AND, (MVT::SimpleValueType)VT, Promote);
739 AddPromotedToType (ISD::AND, (MVT::SimpleValueType)VT, MVT::v2i64);
740 setOperationAction(ISD::OR, (MVT::SimpleValueType)VT, Promote);
741 AddPromotedToType (ISD::OR, (MVT::SimpleValueType)VT, MVT::v2i64);
742 setOperationAction(ISD::XOR, (MVT::SimpleValueType)VT, Promote);
743 AddPromotedToType (ISD::XOR, (MVT::SimpleValueType)VT, MVT::v2i64);
744 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Promote);
745 AddPromotedToType (ISD::LOAD, (MVT::SimpleValueType)VT, MVT::v2i64);
746 setOperationAction(ISD::SELECT, (MVT::SimpleValueType)VT, Promote);
747 AddPromotedToType (ISD::SELECT, (MVT::SimpleValueType)VT, MVT::v2i64);
750 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
752 // Custom lower v2i64 and v2f64 selects.
753 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
754 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
755 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
756 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
760 if (Subtarget->hasSSE41()) {
761 // FIXME: Do we need to handle scalar-to-vector here?
762 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
764 // i8 and i16 vectors are custom , because the source register and source
765 // source memory operand types are not the same width. f32 vectors are
766 // custom since the immediate controlling the insert encodes additional
768 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
769 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
770 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
771 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
773 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
774 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
775 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
778 if (Subtarget->is64Bit()) {
779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
780 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
784 if (Subtarget->hasSSE42()) {
785 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
788 // We want to custom lower some of our intrinsics.
789 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
791 // Add/Sub/Mul with overflow operations are custom lowered.
792 setOperationAction(ISD::SADDO, MVT::i32, Custom);
793 setOperationAction(ISD::SADDO, MVT::i64, Custom);
794 setOperationAction(ISD::UADDO, MVT::i32, Custom);
795 setOperationAction(ISD::UADDO, MVT::i64, Custom);
796 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
797 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
798 setOperationAction(ISD::USUBO, MVT::i32, Custom);
799 setOperationAction(ISD::USUBO, MVT::i64, Custom);
800 setOperationAction(ISD::SMULO, MVT::i32, Custom);
801 setOperationAction(ISD::SMULO, MVT::i64, Custom);
802 setOperationAction(ISD::UMULO, MVT::i32, Custom);
803 setOperationAction(ISD::UMULO, MVT::i64, Custom);
805 // We have target-specific dag combine patterns for the following nodes:
806 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
807 setTargetDAGCombine(ISD::BUILD_VECTOR);
808 setTargetDAGCombine(ISD::SELECT);
809 setTargetDAGCombine(ISD::SHL);
810 setTargetDAGCombine(ISD::SRA);
811 setTargetDAGCombine(ISD::SRL);
812 setTargetDAGCombine(ISD::STORE);
814 computeRegisterProperties();
816 // FIXME: These should be based on subtarget info. Plus, the values should
817 // be smaller when we are in optimizing for size mode.
818 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
819 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
820 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
821 allowUnalignedMemoryAccesses = true; // x86 supports it!
822 setPrefLoopAlignment(16);
826 MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
831 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
832 /// the desired ByVal argument alignment.
833 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
836 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
837 if (VTy->getBitWidth() == 128)
839 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
840 unsigned EltAlign = 0;
841 getMaxByValAlign(ATy->getElementType(), EltAlign);
842 if (EltAlign > MaxAlign)
844 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
845 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
846 unsigned EltAlign = 0;
847 getMaxByValAlign(STy->getElementType(i), EltAlign);
848 if (EltAlign > MaxAlign)
857 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
858 /// function arguments in the caller parameter area. For X86, aggregates
859 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
860 /// are at 4-byte boundaries.
861 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
862 if (Subtarget->is64Bit()) {
863 // Max of 8 and alignment of type.
864 unsigned TyAlign = TD->getABITypeAlignment(Ty);
871 if (Subtarget->hasSSE1())
872 getMaxByValAlign(Ty, Align);
876 /// getOptimalMemOpType - Returns the target specific optimal type for load
877 /// and store operations as a result of memset, memcpy, and memmove
878 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
881 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
882 bool isSrcConst, bool isSrcStr) const {
883 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
884 // linux. This is because the stack realignment code can't handle certain
885 // cases like PR2962. This should be removed when PR2962 is fixed.
886 if (Subtarget->getStackAlignment() >= 16) {
887 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
889 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
892 if (Subtarget->is64Bit() && Size >= 8)
898 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
900 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
901 SelectionDAG &DAG) const {
902 if (usesGlobalOffsetTable())
903 return DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, getPointerTy());
904 if (!Subtarget->isPICStyleRIPRel())
905 return DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy());
909 //===----------------------------------------------------------------------===//
910 // Return Value Calling Convention Implementation
911 //===----------------------------------------------------------------------===//
913 #include "X86GenCallingConv.inc"
915 /// LowerRET - Lower an ISD::RET node.
916 SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
917 assert((Op.getNumOperands() & 1) == 1 && "ISD::RET should have odd # args");
919 SmallVector<CCValAssign, 16> RVLocs;
920 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
921 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
922 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
923 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
925 // If this is the first return lowered for this function, add the regs to the
926 // liveout set for the function.
927 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
928 for (unsigned i = 0; i != RVLocs.size(); ++i)
929 if (RVLocs[i].isRegLoc())
930 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
932 SDValue Chain = Op.getOperand(0);
934 // Handle tail call return.
935 Chain = GetPossiblePreceedingTailCall(Chain, X86ISD::TAILCALL);
936 if (Chain.getOpcode() == X86ISD::TAILCALL) {
937 SDValue TailCall = Chain;
938 SDValue TargetAddress = TailCall.getOperand(1);
939 SDValue StackAdjustment = TailCall.getOperand(2);
940 assert(((TargetAddress.getOpcode() == ISD::Register &&
941 (cast<RegisterSDNode>(TargetAddress)->getReg() == X86::EAX ||
942 cast<RegisterSDNode>(TargetAddress)->getReg() == X86::R9)) ||
943 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
944 TargetAddress.getOpcode() == ISD::TargetGlobalAddress) &&
945 "Expecting an global address, external symbol, or register");
946 assert(StackAdjustment.getOpcode() == ISD::Constant &&
947 "Expecting a const value");
949 SmallVector<SDValue,8> Operands;
950 Operands.push_back(Chain.getOperand(0));
951 Operands.push_back(TargetAddress);
952 Operands.push_back(StackAdjustment);
953 // Copy registers used by the call. Last operand is a flag so it is not
955 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
956 Operands.push_back(Chain.getOperand(i));
958 return DAG.getNode(X86ISD::TC_RETURN, MVT::Other, &Operands[0],
965 SmallVector<SDValue, 6> RetOps;
966 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
967 // Operand #1 = Bytes To Pop
968 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
970 // Copy the result values into the output registers.
971 for (unsigned i = 0; i != RVLocs.size(); ++i) {
972 CCValAssign &VA = RVLocs[i];
973 assert(VA.isRegLoc() && "Can only return in registers!");
974 SDValue ValToCopy = Op.getOperand(i*2+1);
976 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
977 // the RET instruction and handled by the FP Stackifier.
978 if (RVLocs[i].getLocReg() == X86::ST0 ||
979 RVLocs[i].getLocReg() == X86::ST1) {
980 // If this is a copy from an xmm register to ST(0), use an FPExtend to
981 // change the value to the FP stack register class.
982 if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
983 ValToCopy = DAG.getNode(ISD::FP_EXTEND, MVT::f80, ValToCopy);
984 RetOps.push_back(ValToCopy);
985 // Don't emit a copytoreg.
989 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), ValToCopy, Flag);
990 Flag = Chain.getValue(1);
993 // The x86-64 ABI for returning structs by value requires that we copy
994 // the sret argument into %rax for the return. We saved the argument into
995 // a virtual register in the entry block, so now we copy the value out
997 if (Subtarget->is64Bit() &&
998 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
999 MachineFunction &MF = DAG.getMachineFunction();
1000 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1001 unsigned Reg = FuncInfo->getSRetReturnReg();
1003 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1004 FuncInfo->setSRetReturnReg(Reg);
1006 SDValue Val = DAG.getCopyFromReg(Chain, Reg, getPointerTy());
1008 Chain = DAG.getCopyToReg(Chain, X86::RAX, Val, Flag);
1009 Flag = Chain.getValue(1);
1012 RetOps[0] = Chain; // Update chain.
1014 // Add the flag if we have it.
1016 RetOps.push_back(Flag);
1018 return DAG.getNode(X86ISD::RET_FLAG, MVT::Other, &RetOps[0], RetOps.size());
1022 /// LowerCallResult - Lower the result values of an ISD::CALL into the
1023 /// appropriate copies out of appropriate physical registers. This assumes that
1024 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
1025 /// being lowered. The returns a SDNode with the same number of values as the
1027 SDNode *X86TargetLowering::
1028 LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
1029 unsigned CallingConv, SelectionDAG &DAG) {
1031 // Assign locations to each value returned by this call.
1032 SmallVector<CCValAssign, 16> RVLocs;
1033 bool isVarArg = TheCall->isVarArg();
1034 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
1035 CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
1037 SmallVector<SDValue, 8> ResultVals;
1039 // Copy all of the result registers out of their specified physreg.
1040 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1041 MVT CopyVT = RVLocs[i].getValVT();
1043 // If this is a call to a function that returns an fp value on the floating
1044 // point stack, but where we prefer to use the value in xmm registers, copy
1045 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1046 if ((RVLocs[i].getLocReg() == X86::ST0 ||
1047 RVLocs[i].getLocReg() == X86::ST1) &&
1048 isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
1052 Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
1053 CopyVT, InFlag).getValue(1);
1054 SDValue Val = Chain.getValue(0);
1055 InFlag = Chain.getValue(2);
1057 if (CopyVT != RVLocs[i].getValVT()) {
1058 // Round the F80 the right size, which also moves to the appropriate xmm
1060 Val = DAG.getNode(ISD::FP_ROUND, RVLocs[i].getValVT(), Val,
1061 // This truncation won't change the value.
1062 DAG.getIntPtrConstant(1));
1065 ResultVals.push_back(Val);
1068 // Merge everything together with a MERGE_VALUES node.
1069 ResultVals.push_back(Chain);
1070 return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0],
1071 ResultVals.size()).getNode();
1075 //===----------------------------------------------------------------------===//
1076 // C & StdCall & Fast Calling Convention implementation
1077 //===----------------------------------------------------------------------===//
1078 // StdCall calling convention seems to be standard for many Windows' API
1079 // routines and around. It differs from C calling convention just a little:
1080 // callee should clean up the stack, not caller. Symbols should be also
1081 // decorated in some fancy way :) It doesn't support any vector arguments.
1082 // For info on fast calling convention see Fast Calling Convention (tail call)
1083 // implementation LowerX86_32FastCCCallTo.
1085 /// AddLiveIn - This helper function adds the specified physical register to the
1086 /// MachineFunction as a live in value. It also creates a corresponding virtual
1087 /// register for it.
1088 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
1089 const TargetRegisterClass *RC) {
1090 assert(RC->contains(PReg) && "Not the correct regclass!");
1091 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1092 MF.getRegInfo().addLiveIn(PReg, VReg);
1096 /// CallIsStructReturn - Determines whether a CALL node uses struct return
1098 static bool CallIsStructReturn(CallSDNode *TheCall) {
1099 unsigned NumOps = TheCall->getNumArgs();
1103 return TheCall->getArgFlags(0).isSRet();
1106 /// ArgsAreStructReturn - Determines whether a FORMAL_ARGUMENTS node uses struct
1107 /// return semantics.
1108 static bool ArgsAreStructReturn(SDValue Op) {
1109 unsigned NumArgs = Op.getNode()->getNumValues() - 1;
1113 return cast<ARG_FLAGSSDNode>(Op.getOperand(3))->getArgFlags().isSRet();
1116 /// IsCalleePop - Determines whether a CALL or FORMAL_ARGUMENTS node requires
1117 /// the callee to pop its own arguments. Callee pop is necessary to support tail
1119 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1123 switch (CallingConv) {
1126 case CallingConv::X86_StdCall:
1127 return !Subtarget->is64Bit();
1128 case CallingConv::X86_FastCall:
1129 return !Subtarget->is64Bit();
1130 case CallingConv::Fast:
1131 return PerformTailCallOpt;
1135 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1136 /// given CallingConvention value.
1137 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1138 if (Subtarget->is64Bit()) {
1139 if (Subtarget->isTargetWin64())
1140 return CC_X86_Win64_C;
1141 else if (CC == CallingConv::Fast && PerformTailCallOpt)
1142 return CC_X86_64_TailCall;
1147 if (CC == CallingConv::X86_FastCall)
1148 return CC_X86_32_FastCall;
1149 else if (CC == CallingConv::Fast)
1150 return CC_X86_32_FastCC;
1155 /// NameDecorationForFORMAL_ARGUMENTS - Selects the appropriate decoration to
1156 /// apply to a MachineFunction containing a given FORMAL_ARGUMENTS node.
1158 X86TargetLowering::NameDecorationForFORMAL_ARGUMENTS(SDValue Op) {
1159 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1160 if (CC == CallingConv::X86_FastCall)
1162 else if (CC == CallingConv::X86_StdCall)
1168 /// CallRequiresGOTInRegister - Check whether the call requires the GOT pointer
1169 /// in a register before calling.
1170 bool X86TargetLowering::CallRequiresGOTPtrInReg(bool Is64Bit, bool IsTailCall) {
1171 return !IsTailCall && !Is64Bit &&
1172 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1173 Subtarget->isPICStyleGOT();
1176 /// CallRequiresFnAddressInReg - Check whether the call requires the function
1177 /// address to be loaded in a register.
1179 X86TargetLowering::CallRequiresFnAddressInReg(bool Is64Bit, bool IsTailCall) {
1180 return !Is64Bit && IsTailCall &&
1181 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1182 Subtarget->isPICStyleGOT();
1185 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1186 /// by "Src" to address "Dst" with size and alignment information specified by
1187 /// the specific parameter attribute. The copy will be passed as a byval
1188 /// function parameter.
1190 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1191 ISD::ArgFlagsTy Flags, SelectionDAG &DAG) {
1192 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1193 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(),
1194 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1197 SDValue X86TargetLowering::LowerMemArgument(SDValue Op, SelectionDAG &DAG,
1198 const CCValAssign &VA,
1199 MachineFrameInfo *MFI,
1201 SDValue Root, unsigned i) {
1202 // Create the nodes corresponding to a load from this parameter slot.
1203 ISD::ArgFlagsTy Flags =
1204 cast<ARG_FLAGSSDNode>(Op.getOperand(3 + i))->getArgFlags();
1205 bool AlwaysUseMutable = (CC==CallingConv::Fast) && PerformTailCallOpt;
1206 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1208 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1209 // changed with more analysis.
1210 // In case of tail call optimization mark all arguments mutable. Since they
1211 // could be overwritten by lowering of arguments in case of a tail call.
1212 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1213 VA.getLocMemOffset(), isImmutable);
1214 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1215 if (Flags.isByVal())
1217 return DAG.getLoad(VA.getValVT(), Root, FIN,
1218 PseudoSourceValue::getFixedStack(FI), 0);
1222 X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
1223 MachineFunction &MF = DAG.getMachineFunction();
1224 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1226 const Function* Fn = MF.getFunction();
1227 if (Fn->hasExternalLinkage() &&
1228 Subtarget->isTargetCygMing() &&
1229 Fn->getName() == "main")
1230 FuncInfo->setForceFramePointer(true);
1232 // Decorate the function name.
1233 FuncInfo->setDecorationStyle(NameDecorationForFORMAL_ARGUMENTS(Op));
1235 MachineFrameInfo *MFI = MF.getFrameInfo();
1236 SDValue Root = Op.getOperand(0);
1237 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1238 unsigned CC = MF.getFunction()->getCallingConv();
1239 bool Is64Bit = Subtarget->is64Bit();
1240 bool IsWin64 = Subtarget->isTargetWin64();
1242 assert(!(isVarArg && CC == CallingConv::Fast) &&
1243 "Var args not supported with calling convention fastcc");
1245 // Assign locations to all of the incoming arguments.
1246 SmallVector<CCValAssign, 16> ArgLocs;
1247 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1248 CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
1250 SmallVector<SDValue, 8> ArgValues;
1251 unsigned LastVal = ~0U;
1252 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1253 CCValAssign &VA = ArgLocs[i];
1254 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1256 assert(VA.getValNo() != LastVal &&
1257 "Don't support value assigned to multiple locs yet");
1258 LastVal = VA.getValNo();
1260 if (VA.isRegLoc()) {
1261 MVT RegVT = VA.getLocVT();
1262 TargetRegisterClass *RC = NULL;
1263 if (RegVT == MVT::i32)
1264 RC = X86::GR32RegisterClass;
1265 else if (Is64Bit && RegVT == MVT::i64)
1266 RC = X86::GR64RegisterClass;
1267 else if (RegVT == MVT::f32)
1268 RC = X86::FR32RegisterClass;
1269 else if (RegVT == MVT::f64)
1270 RC = X86::FR64RegisterClass;
1271 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1272 RC = X86::VR128RegisterClass;
1273 else if (RegVT.isVector()) {
1274 assert(RegVT.getSizeInBits() == 64);
1276 RC = X86::VR64RegisterClass; // MMX values are passed in MMXs.
1278 // Darwin calling convention passes MMX values in either GPRs or
1279 // XMMs in x86-64. Other targets pass them in memory.
1280 if (RegVT != MVT::v1i64 && Subtarget->hasSSE2()) {
1281 RC = X86::VR128RegisterClass; // MMX values are passed in XMMs.
1284 RC = X86::GR64RegisterClass; // v1i64 values are passed in GPRs.
1289 assert(0 && "Unknown argument type!");
1292 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
1293 SDValue ArgValue = DAG.getCopyFromReg(Root, Reg, RegVT);
1295 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1296 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1298 if (VA.getLocInfo() == CCValAssign::SExt)
1299 ArgValue = DAG.getNode(ISD::AssertSext, RegVT, ArgValue,
1300 DAG.getValueType(VA.getValVT()));
1301 else if (VA.getLocInfo() == CCValAssign::ZExt)
1302 ArgValue = DAG.getNode(ISD::AssertZext, RegVT, ArgValue,
1303 DAG.getValueType(VA.getValVT()));
1305 if (VA.getLocInfo() != CCValAssign::Full)
1306 ArgValue = DAG.getNode(ISD::TRUNCATE, VA.getValVT(), ArgValue);
1308 // Handle MMX values passed in GPRs.
1309 if (Is64Bit && RegVT != VA.getLocVT()) {
1310 if (RegVT.getSizeInBits() == 64 && RC == X86::GR64RegisterClass)
1311 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1312 else if (RC == X86::VR128RegisterClass) {
1313 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i64, ArgValue,
1314 DAG.getConstant(0, MVT::i64));
1315 ArgValue = DAG.getNode(ISD::BIT_CONVERT, VA.getLocVT(), ArgValue);
1319 ArgValues.push_back(ArgValue);
1321 assert(VA.isMemLoc());
1322 ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, CC, Root, i));
1326 // The x86-64 ABI for returning structs by value requires that we copy
1327 // the sret argument into %rax for the return. Save the argument into
1328 // a virtual register so that we can access it from the return points.
1329 if (Is64Bit && DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1330 MachineFunction &MF = DAG.getMachineFunction();
1331 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1332 unsigned Reg = FuncInfo->getSRetReturnReg();
1334 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1335 FuncInfo->setSRetReturnReg(Reg);
1337 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), Reg, ArgValues[0]);
1338 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, Copy, Root);
1341 unsigned StackSize = CCInfo.getNextStackOffset();
1342 // align stack specially for tail calls
1343 if (PerformTailCallOpt && CC == CallingConv::Fast)
1344 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1346 // If the function takes variable number of arguments, make a frame index for
1347 // the start of the first vararg value... for expansion of llvm.va_start.
1349 if (Is64Bit || CC != CallingConv::X86_FastCall) {
1350 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1353 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1355 // FIXME: We should really autogenerate these arrays
1356 static const unsigned GPR64ArgRegsWin64[] = {
1357 X86::RCX, X86::RDX, X86::R8, X86::R9
1359 static const unsigned XMMArgRegsWin64[] = {
1360 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1362 static const unsigned GPR64ArgRegs64Bit[] = {
1363 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1365 static const unsigned XMMArgRegs64Bit[] = {
1366 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1367 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1369 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1372 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1373 GPR64ArgRegs = GPR64ArgRegsWin64;
1374 XMMArgRegs = XMMArgRegsWin64;
1376 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1377 GPR64ArgRegs = GPR64ArgRegs64Bit;
1378 XMMArgRegs = XMMArgRegs64Bit;
1380 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1382 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1385 // For X86-64, if there are vararg parameters that are passed via
1386 // registers, then we must store them to their spots on the stack so they
1387 // may be loaded by deferencing the result of va_next.
1388 VarArgsGPOffset = NumIntRegs * 8;
1389 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1390 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1391 TotalNumXMMRegs * 16, 16);
1393 // Store the integer parameter registers.
1394 SmallVector<SDValue, 8> MemOps;
1395 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1396 SDValue FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1397 DAG.getIntPtrConstant(VarArgsGPOffset));
1398 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1399 unsigned VReg = AddLiveIn(MF, GPR64ArgRegs[NumIntRegs],
1400 X86::GR64RegisterClass);
1401 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1403 DAG.getStore(Val.getValue(1), Val, FIN,
1404 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1405 MemOps.push_back(Store);
1406 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1407 DAG.getIntPtrConstant(8));
1410 // Now store the XMM (fp + vector) parameter registers.
1411 FIN = DAG.getNode(ISD::ADD, getPointerTy(), RSFIN,
1412 DAG.getIntPtrConstant(VarArgsFPOffset));
1413 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1414 unsigned VReg = AddLiveIn(MF, XMMArgRegs[NumXMMRegs],
1415 X86::VR128RegisterClass);
1416 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::v4f32);
1418 DAG.getStore(Val.getValue(1), Val, FIN,
1419 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1420 MemOps.push_back(Store);
1421 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1422 DAG.getIntPtrConstant(16));
1424 if (!MemOps.empty())
1425 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1426 &MemOps[0], MemOps.size());
1430 ArgValues.push_back(Root);
1432 // Some CCs need callee pop.
1433 if (IsCalleePop(isVarArg, CC)) {
1434 BytesToPopOnReturn = StackSize; // Callee pops everything.
1435 BytesCallerReserves = 0;
1437 BytesToPopOnReturn = 0; // Callee pops nothing.
1438 // If this is an sret function, the return should pop the hidden pointer.
1439 if (!Is64Bit && CC != CallingConv::Fast && ArgsAreStructReturn(Op))
1440 BytesToPopOnReturn = 4;
1441 BytesCallerReserves = StackSize;
1445 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1446 if (CC == CallingConv::X86_FastCall)
1447 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1450 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1452 // Return the new list of results.
1453 return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
1454 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
1458 X86TargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
1459 const SDValue &StackPtr,
1460 const CCValAssign &VA,
1462 SDValue Arg, ISD::ArgFlagsTy Flags) {
1463 unsigned LocMemOffset = VA.getLocMemOffset();
1464 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1465 PtrOff = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, PtrOff);
1466 if (Flags.isByVal()) {
1467 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG);
1469 return DAG.getStore(Chain, Arg, PtrOff,
1470 PseudoSourceValue::getStack(), LocMemOffset);
1473 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1474 /// optimization is performed and it is required.
1476 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1477 SDValue &OutRetAddr,
1482 if (!IsTailCall || FPDiff==0) return Chain;
1484 // Adjust the Return address stack slot.
1485 MVT VT = getPointerTy();
1486 OutRetAddr = getReturnAddressFrameIndex(DAG);
1488 // Load the "old" Return address.
1489 OutRetAddr = DAG.getLoad(VT, Chain, OutRetAddr, NULL, 0);
1490 return SDValue(OutRetAddr.getNode(), 1);
1493 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1494 /// optimization is performed and it is required (FPDiff!=0).
1496 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1497 SDValue Chain, SDValue RetAddrFrIdx,
1498 bool Is64Bit, int FPDiff) {
1499 // Store the return address to the appropriate stack slot.
1500 if (!FPDiff) return Chain;
1501 // Calculate the new stack slot for the return address.
1502 int SlotSize = Is64Bit ? 8 : 4;
1503 int NewReturnAddrFI =
1504 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1505 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1506 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1507 Chain = DAG.getStore(Chain, RetAddrFrIdx, NewRetAddrFrIdx,
1508 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1512 SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
1513 MachineFunction &MF = DAG.getMachineFunction();
1514 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
1515 SDValue Chain = TheCall->getChain();
1516 unsigned CC = TheCall->getCallingConv();
1517 bool isVarArg = TheCall->isVarArg();
1518 bool IsTailCall = TheCall->isTailCall() &&
1519 CC == CallingConv::Fast && PerformTailCallOpt;
1520 SDValue Callee = TheCall->getCallee();
1521 bool Is64Bit = Subtarget->is64Bit();
1522 bool IsStructRet = CallIsStructReturn(TheCall);
1524 assert(!(isVarArg && CC == CallingConv::Fast) &&
1525 "Var args not supported with calling convention fastcc");
1527 // Analyze operands of the call, assigning locations to each operand.
1528 SmallVector<CCValAssign, 16> ArgLocs;
1529 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
1530 CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
1532 // Get a count of how many bytes are to be pushed on the stack.
1533 unsigned NumBytes = CCInfo.getNextStackOffset();
1534 if (PerformTailCallOpt && CC == CallingConv::Fast)
1535 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1539 // Lower arguments at fp - stackoffset + fpdiff.
1540 unsigned NumBytesCallerPushed =
1541 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1542 FPDiff = NumBytesCallerPushed - NumBytes;
1544 // Set the delta of movement of the returnaddr stackslot.
1545 // But only set if delta is greater than previous delta.
1546 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1547 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1550 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1552 SDValue RetAddrFrIdx;
1553 // Load return adress for tail calls.
1554 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, IsTailCall, Is64Bit,
1557 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1558 SmallVector<SDValue, 8> MemOpChains;
1561 // Walk the register/memloc assignments, inserting copies/loads. In the case
1562 // of tail call optimization arguments are handle later.
1563 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1564 CCValAssign &VA = ArgLocs[i];
1565 SDValue Arg = TheCall->getArg(i);
1566 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1567 bool isByVal = Flags.isByVal();
1569 // Promote the value if needed.
1570 switch (VA.getLocInfo()) {
1571 default: assert(0 && "Unknown loc info!");
1572 case CCValAssign::Full: break;
1573 case CCValAssign::SExt:
1574 Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
1576 case CCValAssign::ZExt:
1577 Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
1579 case CCValAssign::AExt:
1580 Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
1584 if (VA.isRegLoc()) {
1586 MVT RegVT = VA.getLocVT();
1587 if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1588 switch (VA.getLocReg()) {
1591 case X86::RDI: case X86::RSI: case X86::RDX: case X86::RCX:
1593 // Special case: passing MMX values in GPR registers.
1594 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1597 case X86::XMM0: case X86::XMM1: case X86::XMM2: case X86::XMM3:
1598 case X86::XMM4: case X86::XMM5: case X86::XMM6: case X86::XMM7: {
1599 // Special case: passing MMX values in XMM registers.
1600 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Arg);
1601 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Arg);
1602 Arg = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
1603 DAG.getNode(ISD::UNDEF, MVT::v2i64), Arg,
1604 getMOVLMask(2, DAG));
1609 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1611 if (!IsTailCall || (IsTailCall && isByVal)) {
1612 assert(VA.isMemLoc());
1613 if (StackPtr.getNode() == 0)
1614 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1616 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA,
1617 Chain, Arg, Flags));
1622 if (!MemOpChains.empty())
1623 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1624 &MemOpChains[0], MemOpChains.size());
1626 // Build a sequence of copy-to-reg nodes chained together with token chain
1627 // and flag operands which copy the outgoing args into registers.
1629 // Tail call byval lowering might overwrite argument registers so in case of
1630 // tail call optimization the copies to registers are lowered later.
1632 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1633 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1635 InFlag = Chain.getValue(1);
1638 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1640 if (CallRequiresGOTPtrInReg(Is64Bit, IsTailCall)) {
1641 Chain = DAG.getCopyToReg(Chain, X86::EBX,
1642 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
1644 InFlag = Chain.getValue(1);
1646 // If we are tail calling and generating PIC/GOT style code load the address
1647 // of the callee into ecx. The value in ecx is used as target of the tail
1648 // jump. This is done to circumvent the ebx/callee-saved problem for tail
1649 // calls on PIC/GOT architectures. Normally we would just put the address of
1650 // GOT into ebx and then call target@PLT. But for tail callss ebx would be
1651 // restored (since ebx is callee saved) before jumping to the target@PLT.
1652 if (CallRequiresFnAddressInReg(Is64Bit, IsTailCall)) {
1653 // Note: The actual moving to ecx is done further down.
1654 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1655 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1656 !G->getGlobal()->hasProtectedVisibility())
1657 Callee = LowerGlobalAddress(Callee, DAG);
1658 else if (isa<ExternalSymbolSDNode>(Callee))
1659 Callee = LowerExternalSymbol(Callee,DAG);
1662 if (Is64Bit && isVarArg) {
1663 // From AMD64 ABI document:
1664 // For calls that may call functions that use varargs or stdargs
1665 // (prototype-less calls or calls to functions containing ellipsis (...) in
1666 // the declaration) %al is used as hidden argument to specify the number
1667 // of SSE registers used. The contents of %al do not need to match exactly
1668 // the number of registers, but must be an ubound on the number of SSE
1669 // registers used and is in the range 0 - 8 inclusive.
1671 // FIXME: Verify this on Win64
1672 // Count the number of XMM registers allocated.
1673 static const unsigned XMMArgRegs[] = {
1674 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1675 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1677 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1679 Chain = DAG.getCopyToReg(Chain, X86::AL,
1680 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1681 InFlag = Chain.getValue(1);
1685 // For tail calls lower the arguments to the 'real' stack slot.
1687 SmallVector<SDValue, 8> MemOpChains2;
1690 // Do not flag preceeding copytoreg stuff together with the following stuff.
1692 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1693 CCValAssign &VA = ArgLocs[i];
1694 if (!VA.isRegLoc()) {
1695 assert(VA.isMemLoc());
1696 SDValue Arg = TheCall->getArg(i);
1697 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1698 // Create frame index.
1699 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1700 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1701 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1702 FIN = DAG.getFrameIndex(FI, getPointerTy());
1704 if (Flags.isByVal()) {
1705 // Copy relative to framepointer.
1706 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1707 if (StackPtr.getNode() == 0)
1708 StackPtr = DAG.getCopyFromReg(Chain, X86StackPtr, getPointerTy());
1709 Source = DAG.getNode(ISD::ADD, getPointerTy(), StackPtr, Source);
1711 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, Chain,
1714 // Store relative to framepointer.
1715 MemOpChains2.push_back(
1716 DAG.getStore(Chain, Arg, FIN,
1717 PseudoSourceValue::getFixedStack(FI), 0));
1722 if (!MemOpChains2.empty())
1723 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1724 &MemOpChains2[0], MemOpChains2.size());
1726 // Copy arguments to their registers.
1727 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1728 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1730 InFlag = Chain.getValue(1);
1734 // Store the return address to the appropriate stack slot.
1735 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1739 // If the callee is a GlobalAddress node (quite common, every direct call is)
1740 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1741 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1742 // We should use extra load for direct calls to dllimported functions in
1744 if (!Subtarget->GVRequiresExtraLoad(G->getGlobal(),
1745 getTargetMachine(), true))
1746 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy(),
1748 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1749 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy());
1750 } else if (IsTailCall) {
1751 unsigned Opc = Is64Bit ? X86::R9 : X86::EAX;
1753 Chain = DAG.getCopyToReg(Chain,
1754 DAG.getRegister(Opc, getPointerTy()),
1756 Callee = DAG.getRegister(Opc, getPointerTy());
1757 // Add register as live out.
1758 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
1761 // Returns a chain & a flag for retval copy to use.
1762 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1763 SmallVector<SDValue, 8> Ops;
1766 Ops.push_back(Chain);
1767 Ops.push_back(DAG.getIntPtrConstant(NumBytes, true));
1768 Ops.push_back(DAG.getIntPtrConstant(0, true));
1769 if (InFlag.getNode())
1770 Ops.push_back(InFlag);
1771 Chain = DAG.getNode(ISD::CALLSEQ_END, NodeTys, &Ops[0], Ops.size());
1772 InFlag = Chain.getValue(1);
1774 // Returns a chain & a flag for retval copy to use.
1775 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1779 Ops.push_back(Chain);
1780 Ops.push_back(Callee);
1783 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1785 // Add argument registers to the end of the list so that they are known live
1787 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1788 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1789 RegsToPass[i].second.getValueType()));
1791 // Add an implicit use GOT pointer in EBX.
1792 if (!IsTailCall && !Is64Bit &&
1793 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1794 Subtarget->isPICStyleGOT())
1795 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1797 // Add an implicit use of AL for x86 vararg functions.
1798 if (Is64Bit && isVarArg)
1799 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1801 if (InFlag.getNode())
1802 Ops.push_back(InFlag);
1805 assert(InFlag.getNode() &&
1806 "Flag must be set. Depend on flag being set in LowerRET");
1807 Chain = DAG.getNode(X86ISD::TAILCALL,
1808 TheCall->getVTList(), &Ops[0], Ops.size());
1810 return SDValue(Chain.getNode(), Op.getResNo());
1813 Chain = DAG.getNode(X86ISD::CALL, NodeTys, &Ops[0], Ops.size());
1814 InFlag = Chain.getValue(1);
1816 // Create the CALLSEQ_END node.
1817 unsigned NumBytesForCalleeToPush;
1818 if (IsCalleePop(isVarArg, CC))
1819 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1820 else if (!Is64Bit && CC != CallingConv::Fast && IsStructRet)
1821 // If this is is a call to a struct-return function, the callee
1822 // pops the hidden struct pointer, so we have to push it back.
1823 // This is common for Darwin/X86, Linux & Mingw32 targets.
1824 NumBytesForCalleeToPush = 4;
1826 NumBytesForCalleeToPush = 0; // Callee pops nothing.
1828 // Returns a flag for retval copy to use.
1829 Chain = DAG.getCALLSEQ_END(Chain,
1830 DAG.getIntPtrConstant(NumBytes, true),
1831 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
1834 InFlag = Chain.getValue(1);
1836 // Handle result values, copying them out of physregs into vregs that we
1838 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
1843 //===----------------------------------------------------------------------===//
1844 // Fast Calling Convention (tail call) implementation
1845 //===----------------------------------------------------------------------===//
1847 // Like std call, callee cleans arguments, convention except that ECX is
1848 // reserved for storing the tail called function address. Only 2 registers are
1849 // free for argument passing (inreg). Tail call optimization is performed
1851 // * tailcallopt is enabled
1852 // * caller/callee are fastcc
1853 // On X86_64 architecture with GOT-style position independent code only local
1854 // (within module) calls are supported at the moment.
1855 // To keep the stack aligned according to platform abi the function
1856 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
1857 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
1858 // If a tail called function callee has more arguments than the caller the
1859 // caller needs to make sure that there is room to move the RETADDR to. This is
1860 // achieved by reserving an area the size of the argument delta right after the
1861 // original REtADDR, but before the saved framepointer or the spilled registers
1862 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
1874 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
1875 /// for a 16 byte align requirement.
1876 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
1877 SelectionDAG& DAG) {
1878 MachineFunction &MF = DAG.getMachineFunction();
1879 const TargetMachine &TM = MF.getTarget();
1880 const TargetFrameInfo &TFI = *TM.getFrameInfo();
1881 unsigned StackAlignment = TFI.getStackAlignment();
1882 uint64_t AlignMask = StackAlignment - 1;
1883 int64_t Offset = StackSize;
1884 uint64_t SlotSize = TD->getPointerSize();
1885 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
1886 // Number smaller than 12 so just add the difference.
1887 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
1889 // Mask out lower bits, add stackalignment once plus the 12 bytes.
1890 Offset = ((~AlignMask) & Offset) + StackAlignment +
1891 (StackAlignment-SlotSize);
1896 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1897 /// following the call is a return. A function is eligible if caller/callee
1898 /// calling conventions match, currently only fastcc supports tail calls, and
1899 /// the function CALL is immediatly followed by a RET.
1900 bool X86TargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1902 SelectionDAG& DAG) const {
1903 if (!PerformTailCallOpt)
1906 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1907 MachineFunction &MF = DAG.getMachineFunction();
1908 unsigned CallerCC = MF.getFunction()->getCallingConv();
1909 unsigned CalleeCC= TheCall->getCallingConv();
1910 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1911 SDValue Callee = TheCall->getCallee();
1912 // On x86/32Bit PIC/GOT tail calls are supported.
1913 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ ||
1914 !Subtarget->isPICStyleGOT()|| !Subtarget->is64Bit())
1917 // Can only do local tail calls (in same module, hidden or protected) on
1918 // x86_64 PIC/GOT at the moment.
1919 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1920 return G->getGlobal()->hasHiddenVisibility()
1921 || G->getGlobal()->hasProtectedVisibility();
1929 X86TargetLowering::createFastISel(MachineFunction &mf,
1930 MachineModuleInfo *mmo,
1932 DenseMap<const Value *, unsigned> &vm,
1933 DenseMap<const BasicBlock *,
1934 MachineBasicBlock *> &bm,
1935 DenseMap<const AllocaInst *, int> &am
1937 , SmallSet<Instruction*, 8> &cil
1940 return X86::createFastISel(mf, mmo, dw, vm, bm, am
1948 //===----------------------------------------------------------------------===//
1949 // Other Lowering Hooks
1950 //===----------------------------------------------------------------------===//
1953 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
1954 MachineFunction &MF = DAG.getMachineFunction();
1955 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1956 int ReturnAddrIndex = FuncInfo->getRAIndex();
1958 if (ReturnAddrIndex == 0) {
1959 // Set up a frame object for the return address.
1960 uint64_t SlotSize = TD->getPointerSize();
1961 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
1962 FuncInfo->setRAIndex(ReturnAddrIndex);
1965 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
1969 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
1970 /// specific condition code, returning the condition code and the LHS/RHS of the
1971 /// comparison to make.
1972 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
1973 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
1975 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
1976 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
1977 // X > -1 -> X == 0, jump !sign.
1978 RHS = DAG.getConstant(0, RHS.getValueType());
1979 return X86::COND_NS;
1980 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
1981 // X < 0 -> X == 0, jump on sign.
1983 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
1985 RHS = DAG.getConstant(0, RHS.getValueType());
1986 return X86::COND_LE;
1990 switch (SetCCOpcode) {
1991 default: assert(0 && "Invalid integer condition!");
1992 case ISD::SETEQ: return X86::COND_E;
1993 case ISD::SETGT: return X86::COND_G;
1994 case ISD::SETGE: return X86::COND_GE;
1995 case ISD::SETLT: return X86::COND_L;
1996 case ISD::SETLE: return X86::COND_LE;
1997 case ISD::SETNE: return X86::COND_NE;
1998 case ISD::SETULT: return X86::COND_B;
1999 case ISD::SETUGT: return X86::COND_A;
2000 case ISD::SETULE: return X86::COND_BE;
2001 case ISD::SETUGE: return X86::COND_AE;
2005 // First determine if it is required or is profitable to flip the operands.
2007 // If LHS is a foldable load, but RHS is not, flip the condition.
2008 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2009 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2010 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2011 std::swap(LHS, RHS);
2014 switch (SetCCOpcode) {
2020 std::swap(LHS, RHS);
2024 // On a floating point condition, the flags are set as follows:
2026 // 0 | 0 | 0 | X > Y
2027 // 0 | 0 | 1 | X < Y
2028 // 1 | 0 | 0 | X == Y
2029 // 1 | 1 | 1 | unordered
2030 switch (SetCCOpcode) {
2031 default: assert(0 && "Condcode should be pre-legalized away");
2033 case ISD::SETEQ: return X86::COND_E;
2034 case ISD::SETOLT: // flipped
2036 case ISD::SETGT: return X86::COND_A;
2037 case ISD::SETOLE: // flipped
2039 case ISD::SETGE: return X86::COND_AE;
2040 case ISD::SETUGT: // flipped
2042 case ISD::SETLT: return X86::COND_B;
2043 case ISD::SETUGE: // flipped
2045 case ISD::SETLE: return X86::COND_BE;
2047 case ISD::SETNE: return X86::COND_NE;
2048 case ISD::SETUO: return X86::COND_P;
2049 case ISD::SETO: return X86::COND_NP;
2053 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2054 /// code. Current x86 isa includes the following FP cmov instructions:
2055 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2056 static bool hasFPCMov(unsigned X86CC) {
2072 /// isUndefOrInRange - Op is either an undef node or a ConstantSDNode. Return
2073 /// true if Op is undef or if its value falls within the specified range (L, H].
2074 static bool isUndefOrInRange(SDValue Op, unsigned Low, unsigned Hi) {
2075 if (Op.getOpcode() == ISD::UNDEF)
2078 unsigned Val = cast<ConstantSDNode>(Op)->getZExtValue();
2079 return (Val >= Low && Val < Hi);
2082 /// isUndefOrEqual - Op is either an undef node or a ConstantSDNode. Return
2083 /// true if Op is undef or if its value equal to the specified value.
2084 static bool isUndefOrEqual(SDValue Op, unsigned Val) {
2085 if (Op.getOpcode() == ISD::UNDEF)
2087 return cast<ConstantSDNode>(Op)->getZExtValue() == Val;
2090 /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
2091 /// specifies a shuffle of elements that is suitable for input to PSHUFD.
2092 bool X86::isPSHUFDMask(SDNode *N) {
2093 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2095 if (N->getNumOperands() != 2 && N->getNumOperands() != 4)
2098 // Check if the value doesn't reference the second vector.
2099 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2100 SDValue Arg = N->getOperand(i);
2101 if (Arg.getOpcode() == ISD::UNDEF) continue;
2102 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2103 if (cast<ConstantSDNode>(Arg)->getZExtValue() >= e)
2110 /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
2111 /// specifies a shuffle of elements that is suitable for input to PSHUFHW.
2112 bool X86::isPSHUFHWMask(SDNode *N) {
2113 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2115 if (N->getNumOperands() != 8)
2118 // Lower quadword copied in order.
2119 for (unsigned i = 0; i != 4; ++i) {
2120 SDValue Arg = N->getOperand(i);
2121 if (Arg.getOpcode() == ISD::UNDEF) continue;
2122 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2123 if (cast<ConstantSDNode>(Arg)->getZExtValue() != i)
2127 // Upper quadword shuffled.
2128 for (unsigned i = 4; i != 8; ++i) {
2129 SDValue Arg = N->getOperand(i);
2130 if (Arg.getOpcode() == ISD::UNDEF) continue;
2131 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2132 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2133 if (Val < 4 || Val > 7)
2140 /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
2141 /// specifies a shuffle of elements that is suitable for input to PSHUFLW.
2142 bool X86::isPSHUFLWMask(SDNode *N) {
2143 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2145 if (N->getNumOperands() != 8)
2148 // Upper quadword copied in order.
2149 for (unsigned i = 4; i != 8; ++i)
2150 if (!isUndefOrEqual(N->getOperand(i), i))
2153 // Lower quadword shuffled.
2154 for (unsigned i = 0; i != 4; ++i)
2155 if (!isUndefOrInRange(N->getOperand(i), 0, 4))
2161 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2162 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2163 template<class SDOperand>
2164 static bool isSHUFPMask(SDOperand *Elems, unsigned NumElems) {
2165 if (NumElems != 2 && NumElems != 4) return false;
2167 unsigned Half = NumElems / 2;
2168 for (unsigned i = 0; i < Half; ++i)
2169 if (!isUndefOrInRange(Elems[i], 0, NumElems))
2171 for (unsigned i = Half; i < NumElems; ++i)
2172 if (!isUndefOrInRange(Elems[i], NumElems, NumElems*2))
2178 bool X86::isSHUFPMask(SDNode *N) {
2179 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2180 return ::isSHUFPMask(N->op_begin(), N->getNumOperands());
2183 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2184 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2185 /// half elements to come from vector 1 (which would equal the dest.) and
2186 /// the upper half to come from vector 2.
2187 template<class SDOperand>
2188 static bool isCommutedSHUFP(SDOperand *Ops, unsigned NumOps) {
2189 if (NumOps != 2 && NumOps != 4) return false;
2191 unsigned Half = NumOps / 2;
2192 for (unsigned i = 0; i < Half; ++i)
2193 if (!isUndefOrInRange(Ops[i], NumOps, NumOps*2))
2195 for (unsigned i = Half; i < NumOps; ++i)
2196 if (!isUndefOrInRange(Ops[i], 0, NumOps))
2201 static bool isCommutedSHUFP(SDNode *N) {
2202 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2203 return isCommutedSHUFP(N->op_begin(), N->getNumOperands());
2206 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2207 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2208 bool X86::isMOVHLPSMask(SDNode *N) {
2209 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2211 if (N->getNumOperands() != 4)
2214 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2215 return isUndefOrEqual(N->getOperand(0), 6) &&
2216 isUndefOrEqual(N->getOperand(1), 7) &&
2217 isUndefOrEqual(N->getOperand(2), 2) &&
2218 isUndefOrEqual(N->getOperand(3), 3);
2221 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2222 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2224 bool X86::isMOVHLPS_v_undef_Mask(SDNode *N) {
2225 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2227 if (N->getNumOperands() != 4)
2230 // Expect bit0 == 2, bit1 == 3, bit2 == 2, bit3 == 3
2231 return isUndefOrEqual(N->getOperand(0), 2) &&
2232 isUndefOrEqual(N->getOperand(1), 3) &&
2233 isUndefOrEqual(N->getOperand(2), 2) &&
2234 isUndefOrEqual(N->getOperand(3), 3);
2237 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2238 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2239 bool X86::isMOVLPMask(SDNode *N) {
2240 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2242 unsigned NumElems = N->getNumOperands();
2243 if (NumElems != 2 && NumElems != 4)
2246 for (unsigned i = 0; i < NumElems/2; ++i)
2247 if (!isUndefOrEqual(N->getOperand(i), i + NumElems))
2250 for (unsigned i = NumElems/2; i < NumElems; ++i)
2251 if (!isUndefOrEqual(N->getOperand(i), i))
2257 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2258 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2260 bool X86::isMOVHPMask(SDNode *N) {
2261 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2263 unsigned NumElems = N->getNumOperands();
2264 if (NumElems != 2 && NumElems != 4)
2267 for (unsigned i = 0; i < NumElems/2; ++i)
2268 if (!isUndefOrEqual(N->getOperand(i), i))
2271 for (unsigned i = 0; i < NumElems/2; ++i) {
2272 SDValue Arg = N->getOperand(i + NumElems/2);
2273 if (!isUndefOrEqual(Arg, i + NumElems))
2280 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2281 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2282 template<class SDOperand>
2283 bool static isUNPCKLMask(SDOperand *Elts, unsigned NumElts,
2284 bool V2IsSplat = false) {
2285 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2288 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2289 SDValue BitI = Elts[i];
2290 SDValue BitI1 = Elts[i+1];
2291 if (!isUndefOrEqual(BitI, j))
2294 if (isUndefOrEqual(BitI1, NumElts))
2297 if (!isUndefOrEqual(BitI1, j + NumElts))
2305 bool X86::isUNPCKLMask(SDNode *N, bool V2IsSplat) {
2306 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2307 return ::isUNPCKLMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2310 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2311 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2312 template<class SDOperand>
2313 bool static isUNPCKHMask(SDOperand *Elts, unsigned NumElts,
2314 bool V2IsSplat = false) {
2315 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2318 for (unsigned i = 0, j = 0; i != NumElts; i += 2, ++j) {
2319 SDValue BitI = Elts[i];
2320 SDValue BitI1 = Elts[i+1];
2321 if (!isUndefOrEqual(BitI, j + NumElts/2))
2324 if (isUndefOrEqual(BitI1, NumElts))
2327 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2335 bool X86::isUNPCKHMask(SDNode *N, bool V2IsSplat) {
2336 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2337 return ::isUNPCKHMask(N->op_begin(), N->getNumOperands(), V2IsSplat);
2340 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2341 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2343 bool X86::isUNPCKL_v_undef_Mask(SDNode *N) {
2344 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2346 unsigned NumElems = N->getNumOperands();
2347 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2350 for (unsigned i = 0, j = 0; i != NumElems; i += 2, ++j) {
2351 SDValue BitI = N->getOperand(i);
2352 SDValue BitI1 = N->getOperand(i+1);
2354 if (!isUndefOrEqual(BitI, j))
2356 if (!isUndefOrEqual(BitI1, j))
2363 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2364 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2366 bool X86::isUNPCKH_v_undef_Mask(SDNode *N) {
2367 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2369 unsigned NumElems = N->getNumOperands();
2370 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2373 for (unsigned i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2374 SDValue BitI = N->getOperand(i);
2375 SDValue BitI1 = N->getOperand(i + 1);
2377 if (!isUndefOrEqual(BitI, j))
2379 if (!isUndefOrEqual(BitI1, j))
2386 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2387 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2388 /// MOVSD, and MOVD, i.e. setting the lowest element.
2389 template<class SDOperand>
2390 static bool isMOVLMask(SDOperand *Elts, unsigned NumElts) {
2391 if (NumElts != 2 && NumElts != 4)
2394 if (!isUndefOrEqual(Elts[0], NumElts))
2397 for (unsigned i = 1; i < NumElts; ++i) {
2398 if (!isUndefOrEqual(Elts[i], i))
2405 bool X86::isMOVLMask(SDNode *N) {
2406 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2407 return ::isMOVLMask(N->op_begin(), N->getNumOperands());
2410 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2411 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2412 /// element of vector 2 and the other elements to come from vector 1 in order.
2413 template<class SDOperand>
2414 static bool isCommutedMOVL(SDOperand *Ops, unsigned NumOps,
2415 bool V2IsSplat = false,
2416 bool V2IsUndef = false) {
2417 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2420 if (!isUndefOrEqual(Ops[0], 0))
2423 for (unsigned i = 1; i < NumOps; ++i) {
2424 SDValue Arg = Ops[i];
2425 if (!(isUndefOrEqual(Arg, i+NumOps) ||
2426 (V2IsUndef && isUndefOrInRange(Arg, NumOps, NumOps*2)) ||
2427 (V2IsSplat && isUndefOrEqual(Arg, NumOps))))
2434 static bool isCommutedMOVL(SDNode *N, bool V2IsSplat = false,
2435 bool V2IsUndef = false) {
2436 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2437 return isCommutedMOVL(N->op_begin(), N->getNumOperands(),
2438 V2IsSplat, V2IsUndef);
2441 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2442 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2443 bool X86::isMOVSHDUPMask(SDNode *N) {
2444 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2446 if (N->getNumOperands() != 4)
2449 // Expect 1, 1, 3, 3
2450 for (unsigned i = 0; i < 2; ++i) {
2451 SDValue Arg = N->getOperand(i);
2452 if (Arg.getOpcode() == ISD::UNDEF) continue;
2453 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2454 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2455 if (Val != 1) return false;
2459 for (unsigned i = 2; i < 4; ++i) {
2460 SDValue Arg = N->getOperand(i);
2461 if (Arg.getOpcode() == ISD::UNDEF) continue;
2462 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2463 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2464 if (Val != 3) return false;
2468 // Don't use movshdup if it can be done with a shufps.
2472 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2473 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2474 bool X86::isMOVSLDUPMask(SDNode *N) {
2475 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2477 if (N->getNumOperands() != 4)
2480 // Expect 0, 0, 2, 2
2481 for (unsigned i = 0; i < 2; ++i) {
2482 SDValue Arg = N->getOperand(i);
2483 if (Arg.getOpcode() == ISD::UNDEF) continue;
2484 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2485 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2486 if (Val != 0) return false;
2490 for (unsigned i = 2; i < 4; ++i) {
2491 SDValue Arg = N->getOperand(i);
2492 if (Arg.getOpcode() == ISD::UNDEF) continue;
2493 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2494 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2495 if (Val != 2) return false;
2499 // Don't use movshdup if it can be done with a shufps.
2503 /// isIdentityMask - Return true if the specified VECTOR_SHUFFLE operand
2504 /// specifies a identity operation on the LHS or RHS.
2505 static bool isIdentityMask(SDNode *N, bool RHS = false) {
2506 unsigned NumElems = N->getNumOperands();
2507 for (unsigned i = 0; i < NumElems; ++i)
2508 if (!isUndefOrEqual(N->getOperand(i), i + (RHS ? NumElems : 0)))
2513 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2514 /// a splat of a single element.
2515 static bool isSplatMask(SDNode *N) {
2516 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2518 // This is a splat operation if each element of the permute is the same, and
2519 // if the value doesn't reference the second vector.
2520 unsigned NumElems = N->getNumOperands();
2521 SDValue ElementBase;
2523 for (; i != NumElems; ++i) {
2524 SDValue Elt = N->getOperand(i);
2525 if (isa<ConstantSDNode>(Elt)) {
2531 if (!ElementBase.getNode())
2534 for (; i != NumElems; ++i) {
2535 SDValue Arg = N->getOperand(i);
2536 if (Arg.getOpcode() == ISD::UNDEF) continue;
2537 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2538 if (Arg != ElementBase) return false;
2541 // Make sure it is a splat of the first vector operand.
2542 return cast<ConstantSDNode>(ElementBase)->getZExtValue() < NumElems;
2545 /// getSplatMaskEltNo - Given a splat mask, return the index to the element
2546 /// we want to splat.
2547 static SDValue getSplatMaskEltNo(SDNode *N) {
2548 assert(isSplatMask(N) && "Not a splat mask");
2549 unsigned NumElems = N->getNumOperands();
2550 SDValue ElementBase;
2552 for (; i != NumElems; ++i) {
2553 SDValue Elt = N->getOperand(i);
2554 if (isa<ConstantSDNode>(Elt))
2557 assert(0 && " No splat value found!");
2562 /// isSplatMask - Return true if the specified VECTOR_SHUFFLE operand specifies
2563 /// a splat of a single element and it's a 2 or 4 element mask.
2564 bool X86::isSplatMask(SDNode *N) {
2565 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2567 // We can only splat 64-bit, and 32-bit quantities with a single instruction.
2568 if (N->getNumOperands() != 4 && N->getNumOperands() != 2)
2570 return ::isSplatMask(N);
2573 /// isSplatLoMask - Return true if the specified VECTOR_SHUFFLE operand
2574 /// specifies a splat of zero element.
2575 bool X86::isSplatLoMask(SDNode *N) {
2576 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2578 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
2579 if (!isUndefOrEqual(N->getOperand(i), 0))
2584 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2585 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2586 bool X86::isMOVDDUPMask(SDNode *N) {
2587 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2589 unsigned e = N->getNumOperands() / 2;
2590 for (unsigned i = 0; i < e; ++i)
2591 if (!isUndefOrEqual(N->getOperand(i), i))
2593 for (unsigned i = 0; i < e; ++i)
2594 if (!isUndefOrEqual(N->getOperand(e+i), i))
2599 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2600 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2602 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2603 unsigned NumOperands = N->getNumOperands();
2604 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2606 for (unsigned i = 0; i < NumOperands; ++i) {
2608 SDValue Arg = N->getOperand(NumOperands-i-1);
2609 if (Arg.getOpcode() != ISD::UNDEF)
2610 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2611 if (Val >= NumOperands) Val -= NumOperands;
2613 if (i != NumOperands - 1)
2620 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2621 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2623 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2625 // 8 nodes, but we only care about the last 4.
2626 for (unsigned i = 7; i >= 4; --i) {
2628 SDValue Arg = N->getOperand(i);
2629 if (Arg.getOpcode() != ISD::UNDEF)
2630 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2639 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2640 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2642 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2644 // 8 nodes, but we only care about the first 4.
2645 for (int i = 3; i >= 0; --i) {
2647 SDValue Arg = N->getOperand(i);
2648 if (Arg.getOpcode() != ISD::UNDEF)
2649 Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2658 /// isPSHUFHW_PSHUFLWMask - true if the specified VECTOR_SHUFFLE operand
2659 /// specifies a 8 element shuffle that can be broken into a pair of
2660 /// PSHUFHW and PSHUFLW.
2661 static bool isPSHUFHW_PSHUFLWMask(SDNode *N) {
2662 assert(N->getOpcode() == ISD::BUILD_VECTOR);
2664 if (N->getNumOperands() != 8)
2667 // Lower quadword shuffled.
2668 for (unsigned i = 0; i != 4; ++i) {
2669 SDValue Arg = N->getOperand(i);
2670 if (Arg.getOpcode() == ISD::UNDEF) continue;
2671 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2672 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2677 // Upper quadword shuffled.
2678 for (unsigned i = 4; i != 8; ++i) {
2679 SDValue Arg = N->getOperand(i);
2680 if (Arg.getOpcode() == ISD::UNDEF) continue;
2681 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2682 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2683 if (Val < 4 || Val > 7)
2690 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as
2691 /// values in ther permute mask.
2692 static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
2693 SDValue &V2, SDValue &Mask,
2694 SelectionDAG &DAG) {
2695 MVT VT = Op.getValueType();
2696 MVT MaskVT = Mask.getValueType();
2697 MVT EltVT = MaskVT.getVectorElementType();
2698 unsigned NumElems = Mask.getNumOperands();
2699 SmallVector<SDValue, 8> MaskVec;
2701 for (unsigned i = 0; i != NumElems; ++i) {
2702 SDValue Arg = Mask.getOperand(i);
2703 if (Arg.getOpcode() == ISD::UNDEF) {
2704 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2707 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2708 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2710 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2712 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2716 Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2717 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
2720 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2721 /// the two vector operands have swapped position.
2723 SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG) {
2724 MVT MaskVT = Mask.getValueType();
2725 MVT EltVT = MaskVT.getVectorElementType();
2726 unsigned NumElems = Mask.getNumOperands();
2727 SmallVector<SDValue, 8> MaskVec;
2728 for (unsigned i = 0; i != NumElems; ++i) {
2729 SDValue Arg = Mask.getOperand(i);
2730 if (Arg.getOpcode() == ISD::UNDEF) {
2731 MaskVec.push_back(DAG.getNode(ISD::UNDEF, EltVT));
2734 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
2735 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2737 MaskVec.push_back(DAG.getConstant(Val + NumElems, EltVT));
2739 MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
2741 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], NumElems);
2745 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2746 /// match movhlps. The lower half elements should come from upper half of
2747 /// V1 (and in order), and the upper half elements should come from the upper
2748 /// half of V2 (and in order).
2749 static bool ShouldXformToMOVHLPS(SDNode *Mask) {
2750 unsigned NumElems = Mask->getNumOperands();
2753 for (unsigned i = 0, e = 2; i != e; ++i)
2754 if (!isUndefOrEqual(Mask->getOperand(i), i+2))
2756 for (unsigned i = 2; i != 4; ++i)
2757 if (!isUndefOrEqual(Mask->getOperand(i), i+4))
2762 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2763 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2765 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2766 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2768 N = N->getOperand(0).getNode();
2769 if (!ISD::isNON_EXTLoad(N))
2772 *LD = cast<LoadSDNode>(N);
2776 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2777 /// match movlp{s|d}. The lower half elements should come from lower half of
2778 /// V1 (and in order), and the upper half elements should come from the upper
2779 /// half of V2 (and in order). And since V1 will become the source of the
2780 /// MOVLP, it must be either a vector load or a scalar load to vector.
2781 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, SDNode *Mask) {
2782 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2784 // Is V2 is a vector load, don't do this transformation. We will try to use
2785 // load folding shufps op.
2786 if (ISD::isNON_EXTLoad(V2))
2789 unsigned NumElems = Mask->getNumOperands();
2790 if (NumElems != 2 && NumElems != 4)
2792 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2793 if (!isUndefOrEqual(Mask->getOperand(i), i))
2795 for (unsigned i = NumElems/2; i != NumElems; ++i)
2796 if (!isUndefOrEqual(Mask->getOperand(i), i+NumElems))
2801 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2803 static bool isSplatVector(SDNode *N) {
2804 if (N->getOpcode() != ISD::BUILD_VECTOR)
2807 SDValue SplatValue = N->getOperand(0);
2808 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2809 if (N->getOperand(i) != SplatValue)
2814 /// isUndefShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2816 static bool isUndefShuffle(SDNode *N) {
2817 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2820 SDValue V1 = N->getOperand(0);
2821 SDValue V2 = N->getOperand(1);
2822 SDValue Mask = N->getOperand(2);
2823 unsigned NumElems = Mask.getNumOperands();
2824 for (unsigned i = 0; i != NumElems; ++i) {
2825 SDValue Arg = Mask.getOperand(i);
2826 if (Arg.getOpcode() != ISD::UNDEF) {
2827 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2828 if (Val < NumElems && V1.getOpcode() != ISD::UNDEF)
2830 else if (Val >= NumElems && V2.getOpcode() != ISD::UNDEF)
2837 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2839 static inline bool isZeroNode(SDValue Elt) {
2840 return ((isa<ConstantSDNode>(Elt) &&
2841 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2842 (isa<ConstantFPSDNode>(Elt) &&
2843 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2846 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2847 /// to an zero vector.
2848 static bool isZeroShuffle(SDNode *N) {
2849 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
2852 SDValue V1 = N->getOperand(0);
2853 SDValue V2 = N->getOperand(1);
2854 SDValue Mask = N->getOperand(2);
2855 unsigned NumElems = Mask.getNumOperands();
2856 for (unsigned i = 0; i != NumElems; ++i) {
2857 SDValue Arg = Mask.getOperand(i);
2858 if (Arg.getOpcode() == ISD::UNDEF)
2861 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
2862 if (Idx < NumElems) {
2863 unsigned Opc = V1.getNode()->getOpcode();
2864 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2866 if (Opc != ISD::BUILD_VECTOR ||
2867 !isZeroNode(V1.getNode()->getOperand(Idx)))
2869 } else if (Idx >= NumElems) {
2870 unsigned Opc = V2.getNode()->getOpcode();
2871 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2873 if (Opc != ISD::BUILD_VECTOR ||
2874 !isZeroNode(V2.getNode()->getOperand(Idx - NumElems)))
2881 /// getZeroVector - Returns a vector of specified type with all zero elements.
2883 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG) {
2884 assert(VT.isVector() && "Expected a vector type");
2886 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2887 // type. This ensures they get CSE'd.
2889 if (VT.getSizeInBits() == 64) { // MMX
2890 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2891 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2892 } else if (HasSSE2) { // SSE2
2893 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2894 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2896 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2897 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4f32, Cst, Cst, Cst, Cst);
2899 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2902 /// getOnesVector - Returns a vector of specified type with all bits set.
2904 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG) {
2905 assert(VT.isVector() && "Expected a vector type");
2907 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2908 // type. This ensures they get CSE'd.
2909 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2911 if (VT.getSizeInBits() == 64) // MMX
2912 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
2914 Vec = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
2915 return DAG.getNode(ISD::BIT_CONVERT, VT, Vec);
2919 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2920 /// that point to V2 points to its first element.
2921 static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
2922 assert(Mask.getOpcode() == ISD::BUILD_VECTOR);
2924 bool Changed = false;
2925 SmallVector<SDValue, 8> MaskVec;
2926 unsigned NumElems = Mask.getNumOperands();
2927 for (unsigned i = 0; i != NumElems; ++i) {
2928 SDValue Arg = Mask.getOperand(i);
2929 if (Arg.getOpcode() != ISD::UNDEF) {
2930 unsigned Val = cast<ConstantSDNode>(Arg)->getZExtValue();
2931 if (Val > NumElems) {
2932 Arg = DAG.getConstant(NumElems, Arg.getValueType());
2936 MaskVec.push_back(Arg);
2940 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getValueType(),
2941 &MaskVec[0], MaskVec.size());
2945 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2946 /// operation of specified width.
2947 static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG) {
2948 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2949 MVT BaseVT = MaskVT.getVectorElementType();
2951 SmallVector<SDValue, 8> MaskVec;
2952 MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
2953 for (unsigned i = 1; i != NumElems; ++i)
2954 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2955 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2958 /// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
2959 /// of specified width.
2960 static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG) {
2961 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2962 MVT BaseVT = MaskVT.getVectorElementType();
2963 SmallVector<SDValue, 8> MaskVec;
2964 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2965 MaskVec.push_back(DAG.getConstant(i, BaseVT));
2966 MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
2968 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2971 /// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
2972 /// of specified width.
2973 static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG) {
2974 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2975 MVT BaseVT = MaskVT.getVectorElementType();
2976 unsigned Half = NumElems/2;
2977 SmallVector<SDValue, 8> MaskVec;
2978 for (unsigned i = 0; i != Half; ++i) {
2979 MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
2980 MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
2982 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
2985 /// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
2986 /// element #0 of a vector with the specified index, leaving the rest of the
2987 /// elements in place.
2988 static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
2989 SelectionDAG &DAG) {
2990 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
2991 MVT BaseVT = MaskVT.getVectorElementType();
2992 SmallVector<SDValue, 8> MaskVec;
2993 // Element #0 of the result gets the elt we are replacing.
2994 MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
2995 for (unsigned i = 1; i != NumElems; ++i)
2996 MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
2997 return DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], MaskVec.size());
3000 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
3001 static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
3002 MVT PVT = HasSSE2 ? MVT::v4i32 : MVT::v4f32;
3003 MVT VT = Op.getValueType();
3006 SDValue V1 = Op.getOperand(0);
3007 SDValue Mask = Op.getOperand(2);
3008 unsigned MaskNumElems = Mask.getNumOperands();
3009 unsigned NumElems = MaskNumElems;
3010 // Special handling of v4f32 -> v4i32.
3011 if (VT != MVT::v4f32) {
3012 // Find which element we want to splat.
3013 SDNode* EltNoNode = getSplatMaskEltNo(Mask.getNode()).getNode();
3014 unsigned EltNo = cast<ConstantSDNode>(EltNoNode)->getZExtValue();
3015 // unpack elements to the correct location
3016 while (NumElems > 4) {
3017 if (EltNo < NumElems/2) {
3018 Mask = getUnpacklMask(MaskNumElems, DAG);
3020 Mask = getUnpackhMask(MaskNumElems, DAG);
3021 EltNo -= NumElems/2;
3023 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1, Mask);
3026 SDValue Cst = DAG.getConstant(EltNo, MVT::i32);
3027 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst, Cst, Cst, Cst);
3030 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3031 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3032 DAG.getNode(ISD::UNDEF, PVT), Mask);
3033 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3036 /// isVectorLoad - Returns true if the node is a vector load, a scalar
3037 /// load that's promoted to vector, or a load bitcasted.
3038 static bool isVectorLoad(SDValue Op) {
3039 assert(Op.getValueType().isVector() && "Expected a vector type");
3040 if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
3041 Op.getOpcode() == ISD::BIT_CONVERT) {
3042 return isa<LoadSDNode>(Op.getOperand(0));
3044 return isa<LoadSDNode>(Op);
3048 /// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
3050 static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
3051 SelectionDAG &DAG, bool HasSSE3) {
3052 // If we have sse3 and shuffle has more than one use or input is a load, then
3053 // use movddup. Otherwise, use movlhps.
3054 bool UseMovddup = HasSSE3 && (!Op.hasOneUse() || isVectorLoad(V1));
3055 MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
3056 MVT VT = Op.getValueType();
3059 unsigned NumElems = PVT.getVectorNumElements();
3060 if (NumElems == 2) {
3061 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
3062 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, Cst, Cst);
3064 assert(NumElems == 4);
3065 SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
3066 SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
3067 Mask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Cst0, Cst1, Cst0, Cst1);
3070 V1 = DAG.getNode(ISD::BIT_CONVERT, PVT, V1);
3071 SDValue Shuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, PVT, V1,
3072 DAG.getNode(ISD::UNDEF, PVT), Mask);
3073 return DAG.getNode(ISD::BIT_CONVERT, VT, Shuffle);
3076 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3077 /// vector of zero or undef vector. This produces a shuffle where the low
3078 /// element of V2 is swizzled into the zero/undef vector, landing at element
3079 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3080 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3081 bool isZero, bool HasSSE2,
3082 SelectionDAG &DAG) {
3083 MVT VT = V2.getValueType();
3085 ? getZeroVector(VT, HasSSE2, DAG) : DAG.getNode(ISD::UNDEF, VT);
3086 unsigned NumElems = V2.getValueType().getVectorNumElements();
3087 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3088 MVT EVT = MaskVT.getVectorElementType();
3089 SmallVector<SDValue, 16> MaskVec;
3090 for (unsigned i = 0; i != NumElems; ++i)
3091 if (i == Idx) // If this is the insertion idx, put the low elt of V2 here.
3092 MaskVec.push_back(DAG.getConstant(NumElems, EVT));
3094 MaskVec.push_back(DAG.getConstant(i, EVT));
3095 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3096 &MaskVec[0], MaskVec.size());
3097 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
3100 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3101 /// a shuffle that is zero.
3103 unsigned getNumOfConsecutiveZeros(SDValue Op, SDValue Mask,
3104 unsigned NumElems, bool Low,
3105 SelectionDAG &DAG) {
3106 unsigned NumZeros = 0;
3107 for (unsigned i = 0; i < NumElems; ++i) {
3108 unsigned Index = Low ? i : NumElems-i-1;
3109 SDValue Idx = Mask.getOperand(Index);
3110 if (Idx.getOpcode() == ISD::UNDEF) {
3114 SDValue Elt = DAG.getShuffleScalarElt(Op.getNode(), Index);
3115 if (Elt.getNode() && isZeroNode(Elt))
3123 /// isVectorShift - Returns true if the shuffle can be implemented as a
3124 /// logical left or right shift of a vector.
3125 static bool isVectorShift(SDValue Op, SDValue Mask, SelectionDAG &DAG,
3126 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3127 unsigned NumElems = Mask.getNumOperands();
3130 unsigned NumZeros= getNumOfConsecutiveZeros(Op, Mask, NumElems, true, DAG);
3133 NumZeros = getNumOfConsecutiveZeros(Op, Mask, NumElems, false, DAG);
3138 bool SeenV1 = false;
3139 bool SeenV2 = false;
3140 for (unsigned i = NumZeros; i < NumElems; ++i) {
3141 unsigned Val = isLeft ? (i - NumZeros) : i;
3142 SDValue Idx = Mask.getOperand(isLeft ? i : (i - NumZeros));
3143 if (Idx.getOpcode() == ISD::UNDEF)
3145 unsigned Index = cast<ConstantSDNode>(Idx)->getZExtValue();
3146 if (Index < NumElems)
3155 if (SeenV1 && SeenV2)
3158 ShVal = SeenV1 ? Op.getOperand(0) : Op.getOperand(1);
3164 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3166 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3167 unsigned NumNonZero, unsigned NumZero,
3168 SelectionDAG &DAG, TargetLowering &TLI) {
3174 for (unsigned i = 0; i < 16; ++i) {
3175 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3176 if (ThisIsNonZero && First) {
3178 V = getZeroVector(MVT::v8i16, true, DAG);
3180 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3185 SDValue ThisElt(0, 0), LastElt(0, 0);
3186 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3187 if (LastIsNonZero) {
3188 LastElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i-1));
3190 if (ThisIsNonZero) {
3191 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, MVT::i16, Op.getOperand(i));
3192 ThisElt = DAG.getNode(ISD::SHL, MVT::i16,
3193 ThisElt, DAG.getConstant(8, MVT::i8));
3195 ThisElt = DAG.getNode(ISD::OR, MVT::i16, ThisElt, LastElt);
3199 if (ThisElt.getNode())
3200 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, ThisElt,
3201 DAG.getIntPtrConstant(i/2));
3205 return DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, V);
3208 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3210 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3211 unsigned NumNonZero, unsigned NumZero,
3212 SelectionDAG &DAG, TargetLowering &TLI) {
3218 for (unsigned i = 0; i < 8; ++i) {
3219 bool isNonZero = (NonZeros & (1 << i)) != 0;
3223 V = getZeroVector(MVT::v8i16, true, DAG);
3225 V = DAG.getNode(ISD::UNDEF, MVT::v8i16);
3228 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, V, Op.getOperand(i),
3229 DAG.getIntPtrConstant(i));
3236 /// getVShift - Return a vector logical shift node.
3238 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3239 unsigned NumBits, SelectionDAG &DAG,
3240 const TargetLowering &TLI) {
3241 bool isMMX = VT.getSizeInBits() == 64;
3242 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3243 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3244 SrcOp = DAG.getNode(ISD::BIT_CONVERT, ShVT, SrcOp);
3245 return DAG.getNode(ISD::BIT_CONVERT, VT,
3246 DAG.getNode(Opc, ShVT, SrcOp,
3247 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3251 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3252 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3253 if (ISD::isBuildVectorAllZeros(Op.getNode())
3254 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3255 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3256 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3257 // eliminated on x86-32 hosts.
3258 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3261 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3262 return getOnesVector(Op.getValueType(), DAG);
3263 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG);
3266 MVT VT = Op.getValueType();
3267 MVT EVT = VT.getVectorElementType();
3268 unsigned EVTBits = EVT.getSizeInBits();
3270 unsigned NumElems = Op.getNumOperands();
3271 unsigned NumZero = 0;
3272 unsigned NumNonZero = 0;
3273 unsigned NonZeros = 0;
3274 bool IsAllConstants = true;
3275 SmallSet<SDValue, 8> Values;
3276 for (unsigned i = 0; i < NumElems; ++i) {
3277 SDValue Elt = Op.getOperand(i);
3278 if (Elt.getOpcode() == ISD::UNDEF)
3281 if (Elt.getOpcode() != ISD::Constant &&
3282 Elt.getOpcode() != ISD::ConstantFP)
3283 IsAllConstants = false;
3284 if (isZeroNode(Elt))
3287 NonZeros |= (1 << i);
3292 if (NumNonZero == 0) {
3293 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3294 return DAG.getNode(ISD::UNDEF, VT);
3297 // Special case for single non-zero, non-undef, element.
3298 if (NumNonZero == 1 && NumElems <= 4) {
3299 unsigned Idx = CountTrailingZeros_32(NonZeros);
3300 SDValue Item = Op.getOperand(Idx);
3302 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3303 // the value are obviously zero, truncate the value to i32 and do the
3304 // insertion that way. Only do this if the value is non-constant or if the
3305 // value is a constant being inserted into element 0. It is cheaper to do
3306 // a constant pool load than it is to do a movd + shuffle.
3307 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3308 (!IsAllConstants || Idx == 0)) {
3309 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3310 // Handle MMX and SSE both.
3311 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3312 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3314 // Truncate the value (which may itself be a constant) to i32, and
3315 // convert it to a vector with movd (S2V+shuffle to zero extend).
3316 Item = DAG.getNode(ISD::TRUNCATE, MVT::i32, Item);
3317 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecVT, Item);
3318 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3319 Subtarget->hasSSE2(), DAG);
3321 // Now we have our 32-bit value zero extended in the low element of
3322 // a vector. If Idx != 0, swizzle it into place.
3325 Item, DAG.getNode(ISD::UNDEF, Item.getValueType()),
3326 getSwapEltZeroMask(VecElts, Idx, DAG)
3328 Item = DAG.getNode(ISD::VECTOR_SHUFFLE, VecVT, Ops, 3);
3330 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Item);
3334 // If we have a constant or non-constant insertion into the low element of
3335 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3336 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3337 // depending on what the source datatype is. Because we can only get here
3338 // when NumElems <= 4, this only needs to handle i32/f32/i64/f64.
3340 // Don't do this for i64 values on x86-32.
3341 (EVT != MVT::i64 || Subtarget->is64Bit())) {
3342 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3343 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3344 return getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3345 Subtarget->hasSSE2(), DAG);
3348 // Is it a vector logical left shift?
3349 if (NumElems == 2 && Idx == 1 &&
3350 isZeroNode(Op.getOperand(0)) && !isZeroNode(Op.getOperand(1))) {
3351 unsigned NumBits = VT.getSizeInBits();
3352 return getVShift(true, VT,
3353 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(1)),
3354 NumBits/2, DAG, *this);
3357 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3360 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3361 // is a non-constant being inserted into an element other than the low one,
3362 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3363 // movd/movss) to move this into the low element, then shuffle it into
3365 if (EVTBits == 32) {
3366 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Item);
3368 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3369 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3370 Subtarget->hasSSE2(), DAG);
3371 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3372 MVT MaskEVT = MaskVT.getVectorElementType();
3373 SmallVector<SDValue, 8> MaskVec;
3374 for (unsigned i = 0; i < NumElems; i++)
3375 MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
3376 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3377 &MaskVec[0], MaskVec.size());
3378 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Item,
3379 DAG.getNode(ISD::UNDEF, VT), Mask);
3383 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3384 if (Values.size() == 1)
3387 // A vector full of immediates; various special cases are already
3388 // handled, so this is best done with a single constant-pool load.
3392 // Let legalizer expand 2-wide build_vectors.
3393 if (EVTBits == 64) {
3394 if (NumNonZero == 1) {
3395 // One half is zero or undef.
3396 unsigned Idx = CountTrailingZeros_32(NonZeros);
3397 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT,
3398 Op.getOperand(Idx));
3399 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3400 Subtarget->hasSSE2(), DAG);
3405 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3406 if (EVTBits == 8 && NumElems == 16) {
3407 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3409 if (V.getNode()) return V;
3412 if (EVTBits == 16 && NumElems == 8) {
3413 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3415 if (V.getNode()) return V;
3418 // If element VT is == 32 bits, turn it into a number of shuffles.
3419 SmallVector<SDValue, 8> V;
3421 if (NumElems == 4 && NumZero > 0) {
3422 for (unsigned i = 0; i < 4; ++i) {
3423 bool isZero = !(NonZeros & (1 << i));
3425 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG);
3427 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3430 for (unsigned i = 0; i < 2; ++i) {
3431 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3434 V[i] = V[i*2]; // Must be a zero vector.
3437 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2+1], V[i*2],
3438 getMOVLMask(NumElems, DAG));
3441 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3442 getMOVLMask(NumElems, DAG));
3445 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i*2], V[i*2+1],
3446 getUnpacklMask(NumElems, DAG));
3451 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
3452 MVT EVT = MaskVT.getVectorElementType();
3453 SmallVector<SDValue, 8> MaskVec;
3454 bool Reverse = (NonZeros & 0x3) == 2;
3455 for (unsigned i = 0; i < 2; ++i)
3457 MaskVec.push_back(DAG.getConstant(1-i, EVT));
3459 MaskVec.push_back(DAG.getConstant(i, EVT));
3460 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3461 for (unsigned i = 0; i < 2; ++i)
3463 MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
3465 MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
3466 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3467 &MaskVec[0], MaskVec.size());
3468 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
3471 if (Values.size() > 2) {
3472 // Expand into a number of unpckl*.
3474 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3475 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3476 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3477 SDValue UnpckMask = getUnpacklMask(NumElems, DAG);
3478 for (unsigned i = 0; i < NumElems; ++i)
3479 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Op.getOperand(i));
3481 while (NumElems != 0) {
3482 for (unsigned i = 0; i < NumElems; ++i)
3483 V[i] = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[i], V[i + NumElems],
3494 SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
3495 SDValue PermMask, SelectionDAG &DAG,
3496 TargetLowering &TLI) {
3498 MVT MaskVT = MVT::getIntVectorWithNumElements(8);
3499 MVT MaskEVT = MaskVT.getVectorElementType();
3500 MVT PtrVT = TLI.getPointerTy();
3501 SmallVector<SDValue, 8> MaskElts(PermMask.getNode()->op_begin(),
3502 PermMask.getNode()->op_end());
3504 // First record which half of which vector the low elements come from.
3505 SmallVector<unsigned, 4> LowQuad(4);
3506 for (unsigned i = 0; i < 4; ++i) {
3507 SDValue Elt = MaskElts[i];
3508 if (Elt.getOpcode() == ISD::UNDEF)
3510 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3511 int QuadIdx = EltIdx / 4;
3515 int BestLowQuad = -1;
3516 unsigned MaxQuad = 1;
3517 for (unsigned i = 0; i < 4; ++i) {
3518 if (LowQuad[i] > MaxQuad) {
3520 MaxQuad = LowQuad[i];
3524 // Record which half of which vector the high elements come from.
3525 SmallVector<unsigned, 4> HighQuad(4);
3526 for (unsigned i = 4; i < 8; ++i) {
3527 SDValue Elt = MaskElts[i];
3528 if (Elt.getOpcode() == ISD::UNDEF)
3530 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3531 int QuadIdx = EltIdx / 4;
3532 ++HighQuad[QuadIdx];
3535 int BestHighQuad = -1;
3537 for (unsigned i = 0; i < 4; ++i) {
3538 if (HighQuad[i] > MaxQuad) {
3540 MaxQuad = HighQuad[i];
3544 // If it's possible to sort parts of either half with PSHUF{H|L}W, then do it.
3545 if (BestLowQuad != -1 || BestHighQuad != -1) {
3546 // First sort the 4 chunks in order using shufpd.
3547 SmallVector<SDValue, 8> MaskVec;
3549 if (BestLowQuad != -1)
3550 MaskVec.push_back(DAG.getConstant(BestLowQuad, MVT::i32));
3552 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
3554 if (BestHighQuad != -1)
3555 MaskVec.push_back(DAG.getConstant(BestHighQuad, MVT::i32));
3557 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
3559 SDValue Mask= DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec[0],2);
3560 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2i64,
3561 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V1),
3562 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, V2), Mask);
3563 NewV = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, NewV);
3565 // Now sort high and low parts separately.
3566 BitVector InOrder(8);
3567 if (BestLowQuad != -1) {
3568 // Sort lower half in order using PSHUFLW.
3570 bool AnyOutOrder = false;
3572 for (unsigned i = 0; i != 4; ++i) {
3573 SDValue Elt = MaskElts[i];
3574 if (Elt.getOpcode() == ISD::UNDEF) {
3575 MaskVec.push_back(Elt);
3578 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3582 MaskVec.push_back(DAG.getConstant(EltIdx % 4, MaskEVT));
3584 // If this element is in the right place after this shuffle, then
3586 if ((int)(EltIdx / 4) == BestLowQuad)
3591 for (unsigned i = 4; i != 8; ++i)
3592 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3593 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3594 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3598 if (BestHighQuad != -1) {
3599 // Sort high half in order using PSHUFHW if possible.
3602 for (unsigned i = 0; i != 4; ++i)
3603 MaskVec.push_back(DAG.getConstant(i, MaskEVT));
3605 bool AnyOutOrder = false;
3606 for (unsigned i = 4; i != 8; ++i) {
3607 SDValue Elt = MaskElts[i];
3608 if (Elt.getOpcode() == ISD::UNDEF) {
3609 MaskVec.push_back(Elt);
3612 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3616 MaskVec.push_back(DAG.getConstant((EltIdx % 4) + 4, MaskEVT));
3618 // If this element is in the right place after this shuffle, then
3620 if ((int)(EltIdx / 4) == BestHighQuad)
3626 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3627 NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, NewV, NewV, Mask);
3631 // The other elements are put in the right place using pextrw and pinsrw.
3632 for (unsigned i = 0; i != 8; ++i) {
3635 SDValue Elt = MaskElts[i];
3636 if (Elt.getOpcode() == ISD::UNDEF)
3638 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3639 SDValue ExtOp = (EltIdx < 8)
3640 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3641 DAG.getConstant(EltIdx, PtrVT))
3642 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3643 DAG.getConstant(EltIdx - 8, PtrVT));
3644 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3645 DAG.getConstant(i, PtrVT));
3651 // PSHUF{H|L}W are not used. Lower into extracts and inserts but try to use as
3652 // few as possible. First, let's find out how many elements are already in the
3654 unsigned V1InOrder = 0;
3655 unsigned V1FromV1 = 0;
3656 unsigned V2InOrder = 0;
3657 unsigned V2FromV2 = 0;
3658 SmallVector<SDValue, 8> V1Elts;
3659 SmallVector<SDValue, 8> V2Elts;
3660 for (unsigned i = 0; i < 8; ++i) {
3661 SDValue Elt = MaskElts[i];
3662 if (Elt.getOpcode() == ISD::UNDEF) {
3663 V1Elts.push_back(Elt);
3664 V2Elts.push_back(Elt);
3669 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3671 V1Elts.push_back(Elt);
3672 V2Elts.push_back(DAG.getConstant(i+8, MaskEVT));
3674 } else if (EltIdx == i+8) {
3675 V1Elts.push_back(Elt);
3676 V2Elts.push_back(DAG.getConstant(i, MaskEVT));
3678 } else if (EltIdx < 8) {
3679 V1Elts.push_back(Elt);
3680 V2Elts.push_back(DAG.getConstant(EltIdx+8, MaskEVT));
3683 V1Elts.push_back(Elt);
3684 V2Elts.push_back(DAG.getConstant(EltIdx-8, MaskEVT));
3689 if (V2InOrder > V1InOrder) {
3690 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3692 std::swap(V1Elts, V2Elts);
3693 std::swap(V1FromV1, V2FromV2);
3696 if ((V1FromV1 + V1InOrder) != 8) {
3697 // Some elements are from V2.
3699 // If there are elements that are from V1 but out of place,
3700 // then first sort them in place
3701 SmallVector<SDValue, 8> MaskVec;
3702 for (unsigned i = 0; i < 8; ++i) {
3703 SDValue Elt = V1Elts[i];
3704 if (Elt.getOpcode() == ISD::UNDEF) {
3705 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3708 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3710 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3712 MaskVec.push_back(DAG.getConstant(EltIdx, MaskEVT));
3714 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0], 8);
3715 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v8i16, V1, V1, Mask);
3719 for (unsigned i = 0; i < 8; ++i) {
3720 SDValue Elt = V1Elts[i];
3721 if (Elt.getOpcode() == ISD::UNDEF)
3723 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3726 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V2,
3727 DAG.getConstant(EltIdx - 8, PtrVT));
3728 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3729 DAG.getConstant(i, PtrVT));
3733 // All elements are from V1.
3735 for (unsigned i = 0; i < 8; ++i) {
3736 SDValue Elt = V1Elts[i];
3737 if (Elt.getOpcode() == ISD::UNDEF)
3739 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3740 SDValue ExtOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i16, V1,
3741 DAG.getConstant(EltIdx, PtrVT));
3742 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, MVT::v8i16, NewV, ExtOp,
3743 DAG.getConstant(i, PtrVT));
3749 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3750 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3751 /// done when every pair / quad of shuffle mask elements point to elements in
3752 /// the right sequence. e.g.
3753 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3755 SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
3757 SDValue PermMask, SelectionDAG &DAG,
3758 TargetLowering &TLI) {
3759 unsigned NumElems = PermMask.getNumOperands();
3760 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3761 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3762 MVT MaskEltVT = MaskVT.getVectorElementType();
3764 switch (VT.getSimpleVT()) {
3765 default: assert(false && "Unexpected!");
3766 case MVT::v4f32: NewVT = MVT::v2f64; break;
3767 case MVT::v4i32: NewVT = MVT::v2i64; break;
3768 case MVT::v8i16: NewVT = MVT::v4i32; break;
3769 case MVT::v16i8: NewVT = MVT::v4i32; break;
3772 if (NewWidth == 2) {
3778 unsigned Scale = NumElems / NewWidth;
3779 SmallVector<SDValue, 8> MaskVec;
3780 for (unsigned i = 0; i < NumElems; i += Scale) {
3781 unsigned StartIdx = ~0U;
3782 for (unsigned j = 0; j < Scale; ++j) {
3783 SDValue Elt = PermMask.getOperand(i+j);
3784 if (Elt.getOpcode() == ISD::UNDEF)
3786 unsigned EltIdx = cast<ConstantSDNode>(Elt)->getZExtValue();
3787 if (StartIdx == ~0U)
3788 StartIdx = EltIdx - (EltIdx % Scale);
3789 if (EltIdx != StartIdx + j)
3792 if (StartIdx == ~0U)
3793 MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
3795 MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
3798 V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
3799 V2 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V2);
3800 return DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT, V1, V2,
3801 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3802 &MaskVec[0], MaskVec.size()));
3805 /// getVZextMovL - Return a zero-extending vector move low node.
3807 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3808 SDValue SrcOp, SelectionDAG &DAG,
3809 const X86Subtarget *Subtarget) {
3810 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3811 LoadSDNode *LD = NULL;
3812 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3813 LD = dyn_cast<LoadSDNode>(SrcOp);
3815 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3817 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3818 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3819 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3820 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3821 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3823 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3824 return DAG.getNode(ISD::BIT_CONVERT, VT,
3825 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3826 DAG.getNode(ISD::SCALAR_TO_VECTOR, OpVT,
3833 return DAG.getNode(ISD::BIT_CONVERT, VT,
3834 DAG.getNode(X86ISD::VZEXT_MOVL, OpVT,
3835 DAG.getNode(ISD::BIT_CONVERT, OpVT, SrcOp)));
3838 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3841 LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
3842 SDValue PermMask, MVT VT, SelectionDAG &DAG) {
3843 MVT MaskVT = PermMask.getValueType();
3844 MVT MaskEVT = MaskVT.getVectorElementType();
3845 SmallVector<std::pair<int, int>, 8> Locs;
3847 SmallVector<SDValue, 8> Mask1(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3850 for (unsigned i = 0; i != 4; ++i) {
3851 SDValue Elt = PermMask.getOperand(i);
3852 if (Elt.getOpcode() == ISD::UNDEF) {
3853 Locs[i] = std::make_pair(-1, -1);
3855 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3856 assert(Val < 8 && "Invalid VECTOR_SHUFFLE index!");
3858 Locs[i] = std::make_pair(0, NumLo);
3862 Locs[i] = std::make_pair(1, NumHi);
3864 Mask1[2+NumHi] = Elt;
3870 if (NumLo <= 2 && NumHi <= 2) {
3871 // If no more than two elements come from either vector. This can be
3872 // implemented with two shuffles. First shuffle gather the elements.
3873 // The second shuffle, which takes the first shuffle as both of its
3874 // vector operands, put the elements into the right order.
3875 V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3876 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3877 &Mask1[0], Mask1.size()));
3879 SmallVector<SDValue, 8> Mask2(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3880 for (unsigned i = 0; i != 4; ++i) {
3881 if (Locs[i].first == -1)
3884 unsigned Idx = (i < 2) ? 0 : 4;
3885 Idx += Locs[i].first * 2 + Locs[i].second;
3886 Mask2[i] = DAG.getConstant(Idx, MaskEVT);
3890 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
3891 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3892 &Mask2[0], Mask2.size()));
3893 } else if (NumLo == 3 || NumHi == 3) {
3894 // Otherwise, we must have three elements from one vector, call it X, and
3895 // one element from the other, call it Y. First, use a shufps to build an
3896 // intermediate vector with the one element from Y and the element from X
3897 // that will be in the same half in the final destination (the indexes don't
3898 // matter). Then, use a shufps to build the final vector, taking the half
3899 // containing the element from Y from the intermediate, and the other half
3902 // Normalize it so the 3 elements come from V1.
3903 PermMask = CommuteVectorShuffleMask(PermMask, DAG);
3907 // Find the element from V2.
3909 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3910 SDValue Elt = PermMask.getOperand(HiIndex);
3911 if (Elt.getOpcode() == ISD::UNDEF)
3913 unsigned Val = cast<ConstantSDNode>(Elt)->getZExtValue();
3918 Mask1[0] = PermMask.getOperand(HiIndex);
3919 Mask1[1] = DAG.getNode(ISD::UNDEF, MaskEVT);
3920 Mask1[2] = PermMask.getOperand(HiIndex^1);
3921 Mask1[3] = DAG.getNode(ISD::UNDEF, MaskEVT);
3922 V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3923 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3926 Mask1[0] = PermMask.getOperand(0);
3927 Mask1[1] = PermMask.getOperand(1);
3928 Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
3929 Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
3930 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3931 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3933 Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
3934 Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
3935 Mask1[2] = PermMask.getOperand(2);
3936 Mask1[3] = PermMask.getOperand(3);
3937 if (Mask1[2].getOpcode() != ISD::UNDEF)
3939 DAG.getConstant(cast<ConstantSDNode>(Mask1[2])->getZExtValue()+4,
3941 if (Mask1[3].getOpcode() != ISD::UNDEF)
3943 DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
3945 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V2, V1,
3946 DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &Mask1[0], 4));
3950 // Break it into (shuffle shuffle_hi, shuffle_lo).
3952 SmallVector<SDValue,8> LoMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3953 SmallVector<SDValue,8> HiMask(4, DAG.getNode(ISD::UNDEF, MaskEVT));
3954 SmallVector<SDValue,8> *MaskPtr = &LoMask;
3955 unsigned MaskIdx = 0;
3958 for (unsigned i = 0; i != 4; ++i) {
3965 SDValue Elt = PermMask.getOperand(i);
3966 if (Elt.getOpcode() == ISD::UNDEF) {
3967 Locs[i] = std::make_pair(-1, -1);
3968 } else if (cast<ConstantSDNode>(Elt)->getZExtValue() < 4) {
3969 Locs[i] = std::make_pair(MaskIdx, LoIdx);
3970 (*MaskPtr)[LoIdx] = Elt;
3973 Locs[i] = std::make_pair(MaskIdx, HiIdx);
3974 (*MaskPtr)[HiIdx] = Elt;
3979 SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3980 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3981 &LoMask[0], LoMask.size()));
3982 SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
3983 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3984 &HiMask[0], HiMask.size()));
3985 SmallVector<SDValue, 8> MaskOps;
3986 for (unsigned i = 0; i != 4; ++i) {
3987 if (Locs[i].first == -1) {
3988 MaskOps.push_back(DAG.getNode(ISD::UNDEF, MaskEVT));
3990 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
3991 MaskOps.push_back(DAG.getConstant(Idx, MaskEVT));
3994 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
3995 DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3996 &MaskOps[0], MaskOps.size()));
4000 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4001 SDValue V1 = Op.getOperand(0);
4002 SDValue V2 = Op.getOperand(1);
4003 SDValue PermMask = Op.getOperand(2);
4004 MVT VT = Op.getValueType();
4005 unsigned NumElems = PermMask.getNumOperands();
4006 bool isMMX = VT.getSizeInBits() == 64;
4007 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4008 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4009 bool V1IsSplat = false;
4010 bool V2IsSplat = false;
4012 if (isUndefShuffle(Op.getNode()))
4013 return DAG.getNode(ISD::UNDEF, VT);
4015 if (isZeroShuffle(Op.getNode()))
4016 return getZeroVector(VT, Subtarget->hasSSE2(), DAG);
4018 if (isIdentityMask(PermMask.getNode()))
4020 else if (isIdentityMask(PermMask.getNode(), true))
4023 // Canonicalize movddup shuffles.
4024 if (V2IsUndef && Subtarget->hasSSE2() &&
4025 VT.getSizeInBits() == 128 &&
4026 X86::isMOVDDUPMask(PermMask.getNode()))
4027 return CanonicalizeMovddup(Op, V1, PermMask, DAG, Subtarget->hasSSE3());
4029 if (isSplatMask(PermMask.getNode())) {
4030 if (isMMX || NumElems < 4) return Op;
4031 // Promote it to a v4{if}32 splat.
4032 return PromoteSplat(Op, DAG, Subtarget->hasSSE2());
4035 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4037 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4038 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask, DAG, *this);
4039 if (NewOp.getNode())
4040 return DAG.getNode(ISD::BIT_CONVERT, VT, LowerVECTOR_SHUFFLE(NewOp, DAG));
4041 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4042 // FIXME: Figure out a cleaner way to do this.
4043 // Try to make use of movq to zero out the top part.
4044 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4045 SDValue NewOp = RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4047 if (NewOp.getNode()) {
4048 SDValue NewV1 = NewOp.getOperand(0);
4049 SDValue NewV2 = NewOp.getOperand(1);
4050 SDValue NewMask = NewOp.getOperand(2);
4051 if (isCommutedMOVL(NewMask.getNode(), true, false)) {
4052 NewOp = CommuteVectorShuffle(NewOp, NewV1, NewV2, NewMask, DAG);
4053 return getVZextMovL(VT, NewOp.getValueType(), NewV2, DAG, Subtarget);
4056 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4057 SDValue NewOp= RewriteAsNarrowerShuffle(V1, V2, VT, PermMask,
4059 if (NewOp.getNode() && X86::isMOVLMask(NewOp.getOperand(2).getNode()))
4060 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4065 // Check if this can be converted into a logical shift.
4066 bool isLeft = false;
4069 bool isShift = isVectorShift(Op, PermMask, DAG, isLeft, ShVal, ShAmt);
4070 if (isShift && ShVal.hasOneUse()) {
4071 // If the shifted value has multiple uses, it may be cheaper to use
4072 // v_set0 + movlhps or movhlps, etc.
4073 MVT EVT = VT.getVectorElementType();
4074 ShAmt *= EVT.getSizeInBits();
4075 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4078 if (X86::isMOVLMask(PermMask.getNode())) {
4081 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4082 return getVZextMovL(VT, VT, V2, DAG, Subtarget);
4087 if (!isMMX && (X86::isMOVSHDUPMask(PermMask.getNode()) ||
4088 X86::isMOVSLDUPMask(PermMask.getNode()) ||
4089 X86::isMOVHLPSMask(PermMask.getNode()) ||
4090 X86::isMOVHPMask(PermMask.getNode()) ||
4091 X86::isMOVLPMask(PermMask.getNode())))
4094 if (ShouldXformToMOVHLPS(PermMask.getNode()) ||
4095 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), PermMask.getNode()))
4096 return CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4099 // No better options. Use a vshl / vsrl.
4100 MVT EVT = VT.getVectorElementType();
4101 ShAmt *= EVT.getSizeInBits();
4102 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this);
4105 bool Commuted = false;
4106 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4107 // 1,1,1,1 -> v8i16 though.
4108 V1IsSplat = isSplatVector(V1.getNode());
4109 V2IsSplat = isSplatVector(V2.getNode());
4111 // Canonicalize the splat or undef, if present, to be on the RHS.
4112 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4113 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4114 std::swap(V1IsSplat, V2IsSplat);
4115 std::swap(V1IsUndef, V2IsUndef);
4119 // FIXME: Figure out a cleaner way to do this.
4120 if (isCommutedMOVL(PermMask.getNode(), V2IsSplat, V2IsUndef)) {
4121 if (V2IsUndef) return V1;
4122 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4124 // V2 is a splat, so the mask may be malformed. That is, it may point
4125 // to any V2 element. The instruction selectior won't like this. Get
4126 // a corrected mask and commute to form a proper MOVS{S|D}.
4127 SDValue NewMask = getMOVLMask(NumElems, DAG);
4128 if (NewMask.getNode() != PermMask.getNode())
4129 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4134 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4135 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4136 X86::isUNPCKLMask(PermMask.getNode()) ||
4137 X86::isUNPCKHMask(PermMask.getNode()))
4141 // Normalize mask so all entries that point to V2 points to its first
4142 // element then try to match unpck{h|l} again. If match, return a
4143 // new vector_shuffle with the corrected mask.
4144 SDValue NewMask = NormalizeMask(PermMask, DAG);
4145 if (NewMask.getNode() != PermMask.getNode()) {
4146 if (X86::isUNPCKLMask(PermMask.getNode(), true)) {
4147 SDValue NewMask = getUnpacklMask(NumElems, DAG);
4148 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4149 } else if (X86::isUNPCKHMask(PermMask.getNode(), true)) {
4150 SDValue NewMask = getUnpackhMask(NumElems, DAG);
4151 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, NewMask);
4156 // Normalize the node to match x86 shuffle ops if needed
4157 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(PermMask.getNode()))
4158 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4161 // Commute is back and try unpck* again.
4162 Op = CommuteVectorShuffle(Op, V1, V2, PermMask, DAG);
4163 if (X86::isUNPCKL_v_undef_Mask(PermMask.getNode()) ||
4164 X86::isUNPCKH_v_undef_Mask(PermMask.getNode()) ||
4165 X86::isUNPCKLMask(PermMask.getNode()) ||
4166 X86::isUNPCKHMask(PermMask.getNode()))
4170 // Try PSHUF* first, then SHUFP*.
4171 // MMX doesn't have PSHUFD but it does have PSHUFW. While it's theoretically
4172 // possible to shuffle a v2i32 using PSHUFW, that's not yet implemented.
4173 if (isMMX && NumElems == 4 && X86::isPSHUFDMask(PermMask.getNode())) {
4174 if (V2.getOpcode() != ISD::UNDEF)
4175 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
4176 DAG.getNode(ISD::UNDEF, VT), PermMask);
4181 if (Subtarget->hasSSE2() &&
4182 (X86::isPSHUFDMask(PermMask.getNode()) ||
4183 X86::isPSHUFHWMask(PermMask.getNode()) ||
4184 X86::isPSHUFLWMask(PermMask.getNode()))) {
4186 if (VT == MVT::v4f32) {
4188 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT,
4189 DAG.getNode(ISD::BIT_CONVERT, RVT, V1),
4190 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4191 } else if (V2.getOpcode() != ISD::UNDEF)
4192 Op = DAG.getNode(ISD::VECTOR_SHUFFLE, RVT, V1,
4193 DAG.getNode(ISD::UNDEF, RVT), PermMask);
4195 Op = DAG.getNode(ISD::BIT_CONVERT, VT, Op);
4199 // Binary or unary shufps.
4200 if (X86::isSHUFPMask(PermMask.getNode()) ||
4201 (V2.getOpcode() == ISD::UNDEF && X86::isPSHUFDMask(PermMask.getNode())))
4205 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4206 if (VT == MVT::v8i16) {
4207 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(V1, V2, PermMask, DAG, *this);
4208 if (NewOp.getNode())
4212 // Handle all 4 wide cases with a number of shuffles except for MMX.
4213 if (NumElems == 4 && !isMMX)
4214 return LowerVECTOR_SHUFFLE_4wide(V1, V2, PermMask, VT, DAG);
4220 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4221 SelectionDAG &DAG) {
4222 MVT VT = Op.getValueType();
4223 if (VT.getSizeInBits() == 8) {
4224 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, MVT::i32,
4225 Op.getOperand(0), Op.getOperand(1));
4226 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4227 DAG.getValueType(VT));
4228 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4229 } else if (VT.getSizeInBits() == 16) {
4230 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4231 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4233 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4234 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4235 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32,
4238 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, MVT::i32,
4239 Op.getOperand(0), Op.getOperand(1));
4240 SDValue Assert = DAG.getNode(ISD::AssertZext, MVT::i32, Extract,
4241 DAG.getValueType(VT));
4242 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4243 } else if (VT == MVT::f32) {
4244 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4245 // the result back to FR32 register. It's only worth matching if the
4246 // result has a single use which is a store or a bitcast to i32. And in
4247 // the case of a store, it's not worth it if the index is a constant 0,
4248 // because a MOVSSmr can be used instead, which is smaller and faster.
4249 if (!Op.hasOneUse())
4251 SDNode *User = *Op.getNode()->use_begin();
4252 if ((User->getOpcode() != ISD::STORE ||
4253 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4254 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4255 (User->getOpcode() != ISD::BIT_CONVERT ||
4256 User->getValueType(0) != MVT::i32))
4258 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4259 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
4261 return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
4262 } else if (VT == MVT::i32) {
4263 // ExtractPS works with constant index.
4264 if (isa<ConstantSDNode>(Op.getOperand(1)))
4272 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4273 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4276 if (Subtarget->hasSSE41()) {
4277 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4282 MVT VT = Op.getValueType();
4283 // TODO: handle v16i8.
4284 if (VT.getSizeInBits() == 16) {
4285 SDValue Vec = Op.getOperand(0);
4286 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4288 return DAG.getNode(ISD::TRUNCATE, MVT::i16,
4289 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::i32,
4290 DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Vec),
4292 // Transform it so it match pextrw which produces a 32-bit result.
4293 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4294 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, EVT,
4295 Op.getOperand(0), Op.getOperand(1));
4296 SDValue Assert = DAG.getNode(ISD::AssertZext, EVT, Extract,
4297 DAG.getValueType(VT));
4298 return DAG.getNode(ISD::TRUNCATE, VT, Assert);
4299 } else if (VT.getSizeInBits() == 32) {
4300 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4303 // SHUFPS the element to the lowest double word, then movss.
4304 MVT MaskVT = MVT::getIntVectorWithNumElements(4);
4305 SmallVector<SDValue, 8> IdxVec;
4307 push_back(DAG.getConstant(Idx, MaskVT.getVectorElementType()));
4309 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4311 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4313 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4314 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4315 &IdxVec[0], IdxVec.size());
4316 SDValue Vec = Op.getOperand(0);
4317 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4318 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4319 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4320 DAG.getIntPtrConstant(0));
4321 } else if (VT.getSizeInBits() == 64) {
4322 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4323 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4324 // to match extract_elt for f64.
4325 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4329 // UNPCKHPD the element to the lowest double word, then movsd.
4330 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4331 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4332 MVT MaskVT = MVT::getIntVectorWithNumElements(2);
4333 SmallVector<SDValue, 8> IdxVec;
4334 IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
4336 push_back(DAG.getNode(ISD::UNDEF, MaskVT.getVectorElementType()));
4337 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4338 &IdxVec[0], IdxVec.size());
4339 SDValue Vec = Op.getOperand(0);
4340 Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
4341 Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
4342 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
4343 DAG.getIntPtrConstant(0));
4350 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4351 MVT VT = Op.getValueType();
4352 MVT EVT = VT.getVectorElementType();
4354 SDValue N0 = Op.getOperand(0);
4355 SDValue N1 = Op.getOperand(1);
4356 SDValue N2 = Op.getOperand(2);
4358 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4359 isa<ConstantSDNode>(N2)) {
4360 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4362 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4364 if (N1.getValueType() != MVT::i32)
4365 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4366 if (N2.getValueType() != MVT::i32)
4367 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4368 return DAG.getNode(Opc, VT, N0, N1, N2);
4369 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4370 // Bits [7:6] of the constant are the source select. This will always be
4371 // zero here. The DAG Combiner may combine an extract_elt index into these
4372 // bits. For example (insert (extract, 3), 2) could be matched by putting
4373 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4374 // Bits [5:4] of the constant are the destination select. This is the
4375 // value of the incoming immediate.
4376 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4377 // combine either bitwise AND or insert of float 0.0 to set these bits.
4378 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4379 return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
4380 } else if (EVT == MVT::i32) {
4381 // InsertPS works with constant index.
4382 if (isa<ConstantSDNode>(N2))
4389 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4390 MVT VT = Op.getValueType();
4391 MVT EVT = VT.getVectorElementType();
4393 if (Subtarget->hasSSE41())
4394 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4399 SDValue N0 = Op.getOperand(0);
4400 SDValue N1 = Op.getOperand(1);
4401 SDValue N2 = Op.getOperand(2);
4403 if (EVT.getSizeInBits() == 16) {
4404 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4405 // as its second argument.
4406 if (N1.getValueType() != MVT::i32)
4407 N1 = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, N1);
4408 if (N2.getValueType() != MVT::i32)
4409 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4410 return DAG.getNode(X86ISD::PINSRW, VT, N0, N1, N2);
4416 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4417 if (Op.getValueType() == MVT::v2f32)
4418 return DAG.getNode(ISD::BIT_CONVERT, MVT::v2f32,
4419 DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2i32,
4420 DAG.getNode(ISD::BIT_CONVERT, MVT::i32,
4421 Op.getOperand(0))));
4423 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, Op.getOperand(0));
4424 MVT VT = MVT::v2i32;
4425 switch (Op.getValueType().getSimpleVT()) {
4432 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(),
4433 DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, AnyExt));
4436 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4437 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4438 // one of the above mentioned nodes. It has to be wrapped because otherwise
4439 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4440 // be used to form addressing mode. These wrapped nodes will be selected
4443 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4444 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4445 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(),
4447 CP->getAlignment());
4448 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4449 // With PIC, the address is actually $g + Offset.
4450 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4451 !Subtarget->isPICStyleRIPRel()) {
4452 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4453 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4461 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV,
4463 SelectionDAG &DAG) const {
4464 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
4465 bool ExtraLoadRequired =
4466 Subtarget->GVRequiresExtraLoad(GV, getTargetMachine(), false);
4468 // Create the TargetGlobalAddress node, folding in the constant
4469 // offset if it is legal.
4471 if (!IsPic && !ExtraLoadRequired && isInt32(Offset)) {
4472 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4475 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0);
4476 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4478 // With PIC, the address is actually $g + Offset.
4479 if (IsPic && !Subtarget->isPICStyleRIPRel()) {
4480 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4481 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4485 // For Darwin & Mingw32, external and weak symbols are indirect, so we want to
4486 // load the value at address GV, not the value of GV itself. This means that
4487 // the GlobalAddress must be in the base or index register of the address, not
4488 // the GV offset field. Platform check is inside GVRequiresExtraLoad() call
4489 // The same applies for external symbols during PIC codegen
4490 if (ExtraLoadRequired)
4491 Result = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), Result,
4492 PseudoSourceValue::getGOT(), 0);
4494 // If there was a non-zero offset that we didn't fold, create an explicit
4497 Result = DAG.getNode(ISD::ADD, getPointerTy(), Result,
4498 DAG.getConstant(Offset, getPointerTy()));
4504 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4505 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4506 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4507 return LowerGlobalAddress(GV, Offset, DAG);
4510 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4512 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4515 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), X86::EBX,
4516 DAG.getNode(X86ISD::GlobalBaseReg,
4518 InFlag = Chain.getValue(1);
4520 // emit leal symbol@TLSGD(,%ebx,1), %eax
4521 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4522 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4523 GA->getValueType(0),
4525 SDValue Ops[] = { Chain, TGA, InFlag };
4526 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 3);
4527 InFlag = Result.getValue(2);
4528 Chain = Result.getValue(1);
4530 // call ___tls_get_addr. This function receives its argument in
4531 // the register EAX.
4532 Chain = DAG.getCopyToReg(Chain, X86::EAX, Result, InFlag);
4533 InFlag = Chain.getValue(1);
4535 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4536 SDValue Ops1[] = { Chain,
4537 DAG.getTargetExternalSymbol("___tls_get_addr",
4539 DAG.getRegister(X86::EAX, PtrVT),
4540 DAG.getRegister(X86::EBX, PtrVT),
4542 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 5);
4543 InFlag = Chain.getValue(1);
4545 return DAG.getCopyFromReg(Chain, X86::EAX, PtrVT, InFlag);
4548 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4550 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4552 SDValue InFlag, Chain;
4554 // emit leaq symbol@TLSGD(%rip), %rdi
4555 SDVTList NodeTys = DAG.getVTList(PtrVT, MVT::Other, MVT::Flag);
4556 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4557 GA->getValueType(0),
4559 SDValue Ops[] = { DAG.getEntryNode(), TGA};
4560 SDValue Result = DAG.getNode(X86ISD::TLSADDR, NodeTys, Ops, 2);
4561 Chain = Result.getValue(1);
4562 InFlag = Result.getValue(2);
4564 // call __tls_get_addr. This function receives its argument in
4565 // the register RDI.
4566 Chain = DAG.getCopyToReg(Chain, X86::RDI, Result, InFlag);
4567 InFlag = Chain.getValue(1);
4569 NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4570 SDValue Ops1[] = { Chain,
4571 DAG.getTargetExternalSymbol("__tls_get_addr",
4573 DAG.getRegister(X86::RDI, PtrVT),
4575 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops1, 4);
4576 InFlag = Chain.getValue(1);
4578 return DAG.getCopyFromReg(Chain, X86::RAX, PtrVT, InFlag);
4581 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4582 // "local exec" model.
4583 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4585 // Get the Thread Pointer
4586 SDValue ThreadPointer = DAG.getNode(X86ISD::THREAD_POINTER, PtrVT);
4587 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4589 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4590 GA->getValueType(0),
4592 SDValue Offset = DAG.getNode(X86ISD::Wrapper, PtrVT, TGA);
4594 if (GA->getGlobal()->isDeclaration()) // initial exec TLS model
4595 Offset = DAG.getLoad(PtrVT, DAG.getEntryNode(), Offset,
4596 PseudoSourceValue::getGOT(), 0);
4598 // The address of the thread local variable is the add of the thread
4599 // pointer with the offset of the variable.
4600 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
4604 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4605 // TODO: implement the "local dynamic" model
4606 // TODO: implement the "initial exec"model for pic executables
4607 assert(Subtarget->isTargetELF() &&
4608 "TLS not implemented for non-ELF targets");
4609 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4610 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
4611 // otherwise use the "Local Exec"TLS Model
4612 if (Subtarget->is64Bit()) {
4613 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4615 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
4616 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4618 return LowerToTLSExecModel(GA, DAG, getPointerTy());
4623 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4624 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4625 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy());
4626 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4627 // With PIC, the address is actually $g + Offset.
4628 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4629 !Subtarget->isPICStyleRIPRel()) {
4630 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4631 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4638 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4639 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4640 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
4641 Result = DAG.getNode(X86ISD::Wrapper, getPointerTy(), Result);
4642 // With PIC, the address is actually $g + Offset.
4643 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4644 !Subtarget->isPICStyleRIPRel()) {
4645 Result = DAG.getNode(ISD::ADD, getPointerTy(),
4646 DAG.getNode(X86ISD::GlobalBaseReg, getPointerTy()),
4653 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4654 /// take a 2 x i32 value to shift plus a shift amount.
4655 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4656 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4657 MVT VT = Op.getValueType();
4658 unsigned VTBits = VT.getSizeInBits();
4659 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4660 SDValue ShOpLo = Op.getOperand(0);
4661 SDValue ShOpHi = Op.getOperand(1);
4662 SDValue ShAmt = Op.getOperand(2);
4663 SDValue Tmp1 = isSRA ?
4664 DAG.getNode(ISD::SRA, VT, ShOpHi, DAG.getConstant(VTBits - 1, MVT::i8)) :
4665 DAG.getConstant(0, VT);
4668 if (Op.getOpcode() == ISD::SHL_PARTS) {
4669 Tmp2 = DAG.getNode(X86ISD::SHLD, VT, ShOpHi, ShOpLo, ShAmt);
4670 Tmp3 = DAG.getNode(ISD::SHL, VT, ShOpLo, ShAmt);
4672 Tmp2 = DAG.getNode(X86ISD::SHRD, VT, ShOpLo, ShOpHi, ShAmt);
4673 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, VT, ShOpHi, ShAmt);
4676 SDValue AndNode = DAG.getNode(ISD::AND, MVT::i8, ShAmt,
4677 DAG.getConstant(VTBits, MVT::i8));
4678 SDValue Cond = DAG.getNode(X86ISD::CMP, VT,
4679 AndNode, DAG.getConstant(0, MVT::i8));
4682 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4683 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4684 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4686 if (Op.getOpcode() == ISD::SHL_PARTS) {
4687 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4688 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4690 Lo = DAG.getNode(X86ISD::CMOV, VT, Ops0, 4);
4691 Hi = DAG.getNode(X86ISD::CMOV, VT, Ops1, 4);
4694 SDValue Ops[2] = { Lo, Hi };
4695 return DAG.getMergeValues(Ops, 2);
4698 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4699 MVT SrcVT = Op.getOperand(0).getValueType();
4700 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4701 "Unknown SINT_TO_FP to lower!");
4703 // These are really Legal; caller falls through into that case.
4704 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4706 if (SrcVT == MVT::i64 && Op.getValueType() != MVT::f80 &&
4707 Subtarget->is64Bit())
4710 unsigned Size = SrcVT.getSizeInBits()/8;
4711 MachineFunction &MF = DAG.getMachineFunction();
4712 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4713 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4714 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Op.getOperand(0),
4716 PseudoSourceValue::getFixedStack(SSFI), 0);
4720 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4722 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4724 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4725 SmallVector<SDValue, 8> Ops;
4726 Ops.push_back(Chain);
4727 Ops.push_back(StackSlot);
4728 Ops.push_back(DAG.getValueType(SrcVT));
4729 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD,
4730 Tys, &Ops[0], Ops.size());
4733 Chain = Result.getValue(1);
4734 SDValue InFlag = Result.getValue(2);
4736 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4737 // shouldn't be necessary except that RFP cannot be live across
4738 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4739 MachineFunction &MF = DAG.getMachineFunction();
4740 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4741 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4742 Tys = DAG.getVTList(MVT::Other);
4743 SmallVector<SDValue, 8> Ops;
4744 Ops.push_back(Chain);
4745 Ops.push_back(Result);
4746 Ops.push_back(StackSlot);
4747 Ops.push_back(DAG.getValueType(Op.getValueType()));
4748 Ops.push_back(InFlag);
4749 Chain = DAG.getNode(X86ISD::FST, Tys, &Ops[0], Ops.size());
4750 Result = DAG.getLoad(Op.getValueType(), Chain, StackSlot,
4751 PseudoSourceValue::getFixedStack(SSFI), 0);
4757 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4758 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4759 // This algorithm is not obvious. Here it is in C code, more or less:
4761 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4762 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4763 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4765 // Copy ints to xmm registers.
4766 __m128i xh = _mm_cvtsi32_si128( hi );
4767 __m128i xl = _mm_cvtsi32_si128( lo );
4769 // Combine into low half of a single xmm register.
4770 __m128i x = _mm_unpacklo_epi32( xh, xl );
4774 // Merge in appropriate exponents to give the integer bits the right
4776 x = _mm_unpacklo_epi32( x, exp );
4778 // Subtract away the biases to deal with the IEEE-754 double precision
4780 d = _mm_sub_pd( (__m128d) x, bias );
4782 // All conversions up to here are exact. The correctly rounded result is
4783 // calculated using the current rounding mode using the following
4785 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4786 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4787 // store doesn't really need to be here (except
4788 // maybe to zero the other double)
4793 // Build some magic constants.
4794 std::vector<Constant*> CV0;
4795 CV0.push_back(ConstantInt::get(APInt(32, 0x45300000)));
4796 CV0.push_back(ConstantInt::get(APInt(32, 0x43300000)));
4797 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4798 CV0.push_back(ConstantInt::get(APInt(32, 0)));
4799 Constant *C0 = ConstantVector::get(CV0);
4800 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 4);
4802 std::vector<Constant*> CV1;
4803 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4530000000000000ULL))));
4804 CV1.push_back(ConstantFP::get(APFloat(APInt(64, 0x4330000000000000ULL))));
4805 Constant *C1 = ConstantVector::get(CV1);
4806 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 4);
4808 SmallVector<SDValue, 4> MaskVec;
4809 MaskVec.push_back(DAG.getConstant(0, MVT::i32));
4810 MaskVec.push_back(DAG.getConstant(4, MVT::i32));
4811 MaskVec.push_back(DAG.getConstant(1, MVT::i32));
4812 MaskVec.push_back(DAG.getConstant(5, MVT::i32));
4813 SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, &MaskVec[0],
4815 SmallVector<SDValue, 4> MaskVec2;
4816 MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
4817 MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
4818 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v2i32, &MaskVec2[0],
4821 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4822 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4824 DAG.getIntPtrConstant(1)));
4825 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4826 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4828 DAG.getIntPtrConstant(0)));
4829 SDValue Unpck1 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4830 XR1, XR2, UnpcklMask);
4831 SDValue CLod0 = DAG.getLoad(MVT::v4i32, DAG.getEntryNode(), CPIdx0,
4832 PseudoSourceValue::getConstantPool(), 0,
4834 SDValue Unpck2 = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v4i32,
4835 Unpck1, CLod0, UnpcklMask);
4836 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Unpck2);
4837 SDValue CLod1 = DAG.getLoad(MVT::v2f64, CLod0.getValue(1), CPIdx1,
4838 PseudoSourceValue::getConstantPool(), 0,
4840 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::v2f64, XR2F, CLod1);
4842 // Add the halves; easiest way is to swap them into another reg first.
4843 SDValue Shuf = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v2f64,
4844 Sub, Sub, ShufMask);
4845 SDValue Add = DAG.getNode(ISD::FADD, MVT::v2f64, Shuf, Sub);
4846 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64, Add,
4847 DAG.getIntPtrConstant(0));
4850 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4851 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
4852 // FP constant to bias correct the final result.
4853 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
4856 // Load the 32-bit value into an XMM register.
4857 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v4i32,
4858 DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
4860 DAG.getIntPtrConstant(0)));
4862 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64,
4863 DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Load),
4864 DAG.getIntPtrConstant(0));
4866 // Or the load with the bias.
4867 SDValue Or = DAG.getNode(ISD::OR, MVT::v2i64,
4868 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
4869 DAG.getNode(ISD::SCALAR_TO_VECTOR,
4871 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64,
4872 DAG.getNode(ISD::SCALAR_TO_VECTOR,
4873 MVT::v2f64, Bias)));
4874 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f64,
4875 DAG.getNode(ISD::BIT_CONVERT, MVT::v2f64, Or),
4876 DAG.getIntPtrConstant(0));
4878 // Subtract the bias.
4879 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Or, Bias);
4881 // Handle final rounding.
4882 MVT DestVT = Op.getValueType();
4884 if (DestVT.bitsLT(MVT::f64)) {
4885 return DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
4886 DAG.getIntPtrConstant(0));
4887 } else if (DestVT.bitsGT(MVT::f64)) {
4888 return DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
4891 // Handle final rounding.
4895 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4896 SDValue N0 = Op.getOperand(0);
4898 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
4899 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
4900 // the optimization here.
4901 if (DAG.SignBitIsZero(N0))
4902 return DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), N0);
4904 MVT SrcVT = N0.getValueType();
4905 if (SrcVT == MVT::i64) {
4906 // We only handle SSE2 f64 target here; caller can handle the rest.
4907 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
4910 return LowerUINT_TO_FP_i64(Op, DAG);
4911 } else if (SrcVT == MVT::i32) {
4912 return LowerUINT_TO_FP_i32(Op, DAG);
4915 assert(0 && "Unknown UINT_TO_FP to lower!");
4919 std::pair<SDValue,SDValue> X86TargetLowering::
4920 FP_TO_SINTHelper(SDValue Op, SelectionDAG &DAG) {
4921 assert(Op.getValueType().getSimpleVT() <= MVT::i64 &&
4922 Op.getValueType().getSimpleVT() >= MVT::i16 &&
4923 "Unknown FP_TO_SINT to lower!");
4925 // These are really Legal.
4926 if (Op.getValueType() == MVT::i32 &&
4927 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
4928 return std::make_pair(SDValue(), SDValue());
4929 if (Subtarget->is64Bit() &&
4930 Op.getValueType() == MVT::i64 &&
4931 Op.getOperand(0).getValueType() != MVT::f80)
4932 return std::make_pair(SDValue(), SDValue());
4934 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
4936 MachineFunction &MF = DAG.getMachineFunction();
4937 unsigned MemSize = Op.getValueType().getSizeInBits()/8;
4938 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4939 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4941 switch (Op.getValueType().getSimpleVT()) {
4942 default: assert(0 && "Invalid FP_TO_SINT to lower!");
4943 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
4944 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
4945 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
4948 SDValue Chain = DAG.getEntryNode();
4949 SDValue Value = Op.getOperand(0);
4950 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
4951 assert(Op.getValueType() == MVT::i64 && "Invalid FP_TO_SINT to lower!");
4952 Chain = DAG.getStore(Chain, Value, StackSlot,
4953 PseudoSourceValue::getFixedStack(SSFI), 0);
4954 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
4956 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
4958 Value = DAG.getNode(X86ISD::FLD, Tys, Ops, 3);
4959 Chain = Value.getValue(1);
4960 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
4961 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4964 // Build the FP_TO_INT*_IN_MEM
4965 SDValue Ops[] = { Chain, Value, StackSlot };
4966 SDValue FIST = DAG.getNode(Opc, MVT::Other, Ops, 3);
4968 return std::make_pair(FIST, StackSlot);
4971 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
4972 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(Op, DAG);
4973 SDValue FIST = Vals.first, StackSlot = Vals.second;
4974 if (FIST.getNode() == 0) return SDValue();
4977 return DAG.getLoad(Op.getValueType(), FIST, StackSlot, NULL, 0);
4980 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
4981 MVT VT = Op.getValueType();
4984 EltVT = VT.getVectorElementType();
4985 std::vector<Constant*> CV;
4986 if (EltVT == MVT::f64) {
4987 Constant *C = ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63))));
4991 Constant *C = ConstantFP::get(APFloat(APInt(32, ~(1U << 31))));
4997 Constant *C = ConstantVector::get(CV);
4998 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
4999 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5000 PseudoSourceValue::getConstantPool(), 0,
5002 return DAG.getNode(X86ISD::FAND, VT, Op.getOperand(0), Mask);
5005 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5006 MVT VT = Op.getValueType();
5008 unsigned EltNum = 1;
5009 if (VT.isVector()) {
5010 EltVT = VT.getVectorElementType();
5011 EltNum = VT.getVectorNumElements();
5013 std::vector<Constant*> CV;
5014 if (EltVT == MVT::f64) {
5015 Constant *C = ConstantFP::get(APFloat(APInt(64, 1ULL << 63)));
5019 Constant *C = ConstantFP::get(APFloat(APInt(32, 1U << 31)));
5025 Constant *C = ConstantVector::get(CV);
5026 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5027 SDValue Mask = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5028 PseudoSourceValue::getConstantPool(), 0,
5030 if (VT.isVector()) {
5031 return DAG.getNode(ISD::BIT_CONVERT, VT,
5032 DAG.getNode(ISD::XOR, MVT::v2i64,
5033 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Op.getOperand(0)),
5034 DAG.getNode(ISD::BIT_CONVERT, MVT::v2i64, Mask)));
5036 return DAG.getNode(X86ISD::FXOR, VT, Op.getOperand(0), Mask);
5040 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5041 SDValue Op0 = Op.getOperand(0);
5042 SDValue Op1 = Op.getOperand(1);
5043 MVT VT = Op.getValueType();
5044 MVT SrcVT = Op1.getValueType();
5046 // If second operand is smaller, extend it first.
5047 if (SrcVT.bitsLT(VT)) {
5048 Op1 = DAG.getNode(ISD::FP_EXTEND, VT, Op1);
5051 // And if it is bigger, shrink it first.
5052 if (SrcVT.bitsGT(VT)) {
5053 Op1 = DAG.getNode(ISD::FP_ROUND, VT, Op1, DAG.getIntPtrConstant(1));
5057 // At this point the operands and the result should have the same
5058 // type, and that won't be f80 since that is not custom lowered.
5060 // First get the sign bit of second operand.
5061 std::vector<Constant*> CV;
5062 if (SrcVT == MVT::f64) {
5063 CV.push_back(ConstantFP::get(APFloat(APInt(64, 1ULL << 63))));
5064 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5066 CV.push_back(ConstantFP::get(APFloat(APInt(32, 1U << 31))));
5067 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5068 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5069 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5071 Constant *C = ConstantVector::get(CV);
5072 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5073 SDValue Mask1 = DAG.getLoad(SrcVT, DAG.getEntryNode(), CPIdx,
5074 PseudoSourceValue::getConstantPool(), 0,
5076 SDValue SignBit = DAG.getNode(X86ISD::FAND, SrcVT, Op1, Mask1);
5078 // Shift sign bit right or left if the two operands have different types.
5079 if (SrcVT.bitsGT(VT)) {
5080 // Op0 is MVT::f32, Op1 is MVT::f64.
5081 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, MVT::v2f64, SignBit);
5082 SignBit = DAG.getNode(X86ISD::FSRL, MVT::v2f64, SignBit,
5083 DAG.getConstant(32, MVT::i32));
5084 SignBit = DAG.getNode(ISD::BIT_CONVERT, MVT::v4f32, SignBit);
5085 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, MVT::f32, SignBit,
5086 DAG.getIntPtrConstant(0));
5089 // Clear first operand sign bit.
5091 if (VT == MVT::f64) {
5092 CV.push_back(ConstantFP::get(APFloat(APInt(64, ~(1ULL << 63)))));
5093 CV.push_back(ConstantFP::get(APFloat(APInt(64, 0))));
5095 CV.push_back(ConstantFP::get(APFloat(APInt(32, ~(1U << 31)))));
5096 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5097 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5098 CV.push_back(ConstantFP::get(APFloat(APInt(32, 0))));
5100 C = ConstantVector::get(CV);
5101 CPIdx = DAG.getConstantPool(C, getPointerTy(), 4);
5102 SDValue Mask2 = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5103 PseudoSourceValue::getConstantPool(), 0,
5105 SDValue Val = DAG.getNode(X86ISD::FAND, VT, Op0, Mask2);
5107 // Or the value with the sign bit.
5108 return DAG.getNode(X86ISD::FOR, VT, Val, SignBit);
5111 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5112 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5113 SDValue Op0 = Op.getOperand(0);
5114 SDValue Op1 = Op.getOperand(1);
5115 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5117 // Lower (X & (1 << N)) == 0 to BT(X, N).
5118 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5119 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5120 if (Op0.getOpcode() == ISD::AND &&
5122 Op1.getOpcode() == ISD::Constant &&
5123 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5124 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5126 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5127 if (ConstantSDNode *Op010C =
5128 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5129 if (Op010C->getZExtValue() == 1) {
5130 LHS = Op0.getOperand(0);
5131 RHS = Op0.getOperand(1).getOperand(1);
5133 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5134 if (ConstantSDNode *Op000C =
5135 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5136 if (Op000C->getZExtValue() == 1) {
5137 LHS = Op0.getOperand(1);
5138 RHS = Op0.getOperand(0).getOperand(1);
5140 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5141 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5142 SDValue AndLHS = Op0.getOperand(0);
5143 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5144 LHS = AndLHS.getOperand(0);
5145 RHS = AndLHS.getOperand(1);
5149 if (LHS.getNode()) {
5150 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5151 // instruction. Since the shift amount is in-range-or-undefined, we know
5152 // that doing a bittest on the i16 value is ok. We extend to i32 because
5153 // the encoding for the i16 version is larger than the i32 version.
5154 if (LHS.getValueType() == MVT::i8)
5155 LHS = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, LHS);
5157 // If the operand types disagree, extend the shift amount to match. Since
5158 // BT ignores high bits (like shifts) we can use anyextend.
5159 if (LHS.getValueType() != RHS.getValueType())
5160 RHS = DAG.getNode(ISD::ANY_EXTEND, LHS.getValueType(), RHS);
5162 SDValue BT = DAG.getNode(X86ISD::BT, MVT::i32, LHS, RHS);
5163 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5164 return DAG.getNode(X86ISD::SETCC, MVT::i8,
5165 DAG.getConstant(Cond, MVT::i8), BT);
5169 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5170 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5172 SDValue Cond = DAG.getNode(X86ISD::CMP, MVT::i32, Op0, Op1);
5173 return DAG.getNode(X86ISD::SETCC, MVT::i8,
5174 DAG.getConstant(X86CC, MVT::i8), Cond);
5177 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5179 SDValue Op0 = Op.getOperand(0);
5180 SDValue Op1 = Op.getOperand(1);
5181 SDValue CC = Op.getOperand(2);
5182 MVT VT = Op.getValueType();
5183 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5184 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5188 MVT VT0 = Op0.getValueType();
5189 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5190 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5193 switch (SetCCOpcode) {
5196 case ISD::SETEQ: SSECC = 0; break;
5198 case ISD::SETGT: Swap = true; // Fallthrough
5200 case ISD::SETOLT: SSECC = 1; break;
5202 case ISD::SETGE: Swap = true; // Fallthrough
5204 case ISD::SETOLE: SSECC = 2; break;
5205 case ISD::SETUO: SSECC = 3; break;
5207 case ISD::SETNE: SSECC = 4; break;
5208 case ISD::SETULE: Swap = true;
5209 case ISD::SETUGE: SSECC = 5; break;
5210 case ISD::SETULT: Swap = true;
5211 case ISD::SETUGT: SSECC = 6; break;
5212 case ISD::SETO: SSECC = 7; break;
5215 std::swap(Op0, Op1);
5217 // In the two special cases we can't handle, emit two comparisons.
5219 if (SetCCOpcode == ISD::SETUEQ) {
5221 UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5222 EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5223 return DAG.getNode(ISD::OR, VT, UNORD, EQ);
5225 else if (SetCCOpcode == ISD::SETONE) {
5227 ORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5228 NEQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5229 return DAG.getNode(ISD::AND, VT, ORD, NEQ);
5231 assert(0 && "Illegal FP comparison");
5233 // Handle all other FP comparisons here.
5234 return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5237 // We are handling one of the integer comparisons here. Since SSE only has
5238 // GT and EQ comparisons for integer, swapping operands and multiple
5239 // operations may be required for some comparisons.
5240 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5241 bool Swap = false, Invert = false, FlipSigns = false;
5243 switch (VT.getSimpleVT()) {
5245 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5246 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5247 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5248 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5251 switch (SetCCOpcode) {
5253 case ISD::SETNE: Invert = true;
5254 case ISD::SETEQ: Opc = EQOpc; break;
5255 case ISD::SETLT: Swap = true;
5256 case ISD::SETGT: Opc = GTOpc; break;
5257 case ISD::SETGE: Swap = true;
5258 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5259 case ISD::SETULT: Swap = true;
5260 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5261 case ISD::SETUGE: Swap = true;
5262 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5265 std::swap(Op0, Op1);
5267 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5268 // bits of the inputs before performing those operations.
5270 MVT EltVT = VT.getVectorElementType();
5271 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5273 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5274 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
5276 Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
5277 Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
5280 SDValue Result = DAG.getNode(Opc, VT, Op0, Op1);
5282 // If the logical-not of the result is required, perform that now.
5284 Result = DAG.getNOT(Op.getDebugLoc(), Result, VT);
5289 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5290 static bool isX86LogicalCmp(unsigned Opc) {
5291 return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI;
5294 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5295 bool addTest = true;
5296 SDValue Cond = Op.getOperand(0);
5299 if (Cond.getOpcode() == ISD::SETCC)
5300 Cond = LowerSETCC(Cond, DAG);
5302 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5303 // setting operand in place of the X86ISD::SETCC.
5304 if (Cond.getOpcode() == X86ISD::SETCC) {
5305 CC = Cond.getOperand(0);
5307 SDValue Cmp = Cond.getOperand(1);
5308 unsigned Opc = Cmp.getOpcode();
5309 MVT VT = Op.getValueType();
5311 bool IllegalFPCMov = false;
5312 if (VT.isFloatingPoint() && !VT.isVector() &&
5313 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5314 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5316 if ((isX86LogicalCmp(Opc) && !IllegalFPCMov) || Opc == X86ISD::BT) { // FIXME
5323 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5324 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5327 const MVT *VTs = DAG.getNodeValueTypes(Op.getValueType(),
5329 SmallVector<SDValue, 4> Ops;
5330 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5331 // condition is true.
5332 Ops.push_back(Op.getOperand(2));
5333 Ops.push_back(Op.getOperand(1));
5335 Ops.push_back(Cond);
5336 return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
5339 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5340 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5341 // from the AND / OR.
5342 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5343 Opc = Op.getOpcode();
5344 if (Opc != ISD::OR && Opc != ISD::AND)
5346 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5347 Op.getOperand(0).hasOneUse() &&
5348 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5349 Op.getOperand(1).hasOneUse());
5352 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5353 bool addTest = true;
5354 SDValue Chain = Op.getOperand(0);
5355 SDValue Cond = Op.getOperand(1);
5356 SDValue Dest = Op.getOperand(2);
5359 if (Cond.getOpcode() == ISD::SETCC)
5360 Cond = LowerSETCC(Cond, DAG);
5362 // FIXME: LowerXALUO doesn't handle these!!
5363 else if (Cond.getOpcode() == X86ISD::ADD ||
5364 Cond.getOpcode() == X86ISD::SUB ||
5365 Cond.getOpcode() == X86ISD::SMUL ||
5366 Cond.getOpcode() == X86ISD::UMUL)
5367 Cond = LowerXALUO(Cond, DAG);
5370 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5371 // setting operand in place of the X86ISD::SETCC.
5372 if (Cond.getOpcode() == X86ISD::SETCC) {
5373 CC = Cond.getOperand(0);
5375 SDValue Cmp = Cond.getOperand(1);
5376 unsigned Opc = Cmp.getOpcode();
5377 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5378 if (isX86LogicalCmp(Opc) || Opc == X86ISD::BT) {
5382 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5386 // These can only come from an arithmetic instruction with overflow,
5387 // e.g. SADDO, UADDO.
5388 Cond = Cond.getNode()->getOperand(1);
5395 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5396 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5397 unsigned Opc = Cmp.getOpcode();
5398 if (CondOpc == ISD::OR) {
5399 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5400 // two branches instead of an explicit OR instruction with a
5402 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5403 isX86LogicalCmp(Opc)) {
5404 CC = Cond.getOperand(0).getOperand(0);
5405 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5406 Chain, Dest, CC, Cmp);
5407 CC = Cond.getOperand(1).getOperand(0);
5411 } else { // ISD::AND
5412 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5413 // two branches instead of an explicit AND instruction with a
5414 // separate test. However, we only do this if this block doesn't
5415 // have a fall-through edge, because this requires an explicit
5416 // jmp when the condition is false.
5417 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5418 isX86LogicalCmp(Opc) &&
5419 Op.getNode()->hasOneUse()) {
5420 X86::CondCode CCode =
5421 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5422 CCode = X86::GetOppositeBranchCondition(CCode);
5423 CC = DAG.getConstant(CCode, MVT::i8);
5424 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5425 // Look for an unconditional branch following this conditional branch.
5426 // We need this because we need to reverse the successors in order
5427 // to implement FCMP_OEQ.
5428 if (User.getOpcode() == ISD::BR) {
5429 SDValue FalseBB = User.getOperand(1);
5431 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5432 assert(NewBR == User);
5435 Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5436 Chain, Dest, CC, Cmp);
5437 X86::CondCode CCode =
5438 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5439 CCode = X86::GetOppositeBranchCondition(CCode);
5440 CC = DAG.getConstant(CCode, MVT::i8);
5450 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5451 Cond= DAG.getNode(X86ISD::CMP, MVT::i32, Cond, DAG.getConstant(0, MVT::i8));
5453 return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
5454 Chain, Dest, CC, Cond);
5458 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5459 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5460 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5461 // that the guard pages used by the OS virtual memory manager are allocated in
5462 // correct sequence.
5464 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5465 SelectionDAG &DAG) {
5466 assert(Subtarget->isTargetCygMing() &&
5467 "This should be used only on Cygwin/Mingw targets");
5470 SDValue Chain = Op.getOperand(0);
5471 SDValue Size = Op.getOperand(1);
5472 // FIXME: Ensure alignment here
5476 MVT IntPtr = getPointerTy();
5477 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5479 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5481 Chain = DAG.getCopyToReg(Chain, X86::EAX, Size, Flag);
5482 Flag = Chain.getValue(1);
5484 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5485 SDValue Ops[] = { Chain,
5486 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5487 DAG.getRegister(X86::EAX, IntPtr),
5488 DAG.getRegister(X86StackPtr, SPTy),
5490 Chain = DAG.getNode(X86ISD::CALL, NodeTys, Ops, 5);
5491 Flag = Chain.getValue(1);
5493 Chain = DAG.getCALLSEQ_END(Chain,
5494 DAG.getIntPtrConstant(0, true),
5495 DAG.getIntPtrConstant(0, true),
5498 Chain = DAG.getCopyFromReg(Chain, X86StackPtr, SPTy).getValue(1);
5500 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5501 return DAG.getMergeValues(Ops1, 2);
5505 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG,
5507 SDValue Dst, SDValue Src,
5508 SDValue Size, unsigned Align,
5510 uint64_t DstSVOff) {
5511 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5513 // If not DWORD aligned or size is more than the threshold, call the library.
5514 // The libc version is likely to be faster for these cases. It can use the
5515 // address value and run time information about the CPU.
5516 if ((Align & 3) != 0 ||
5518 ConstantSize->getZExtValue() >
5519 getSubtarget()->getMaxInlineSizeThreshold()) {
5520 SDValue InFlag(0, 0);
5522 // Check to see if there is a specialized entry-point for memory zeroing.
5523 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5525 if (const char *bzeroEntry = V &&
5526 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5527 MVT IntPtr = getPointerTy();
5528 const Type *IntPtrTy = TD->getIntPtrType();
5529 TargetLowering::ArgListTy Args;
5530 TargetLowering::ArgListEntry Entry;
5532 Entry.Ty = IntPtrTy;
5533 Args.push_back(Entry);
5535 Args.push_back(Entry);
5536 // FIXME provide DebugLoc info
5537 std::pair<SDValue,SDValue> CallResult =
5538 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5539 CallingConv::C, false,
5540 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG,
5541 DebugLoc::getUnknownLoc());
5542 return CallResult.second;
5545 // Otherwise have the target-independent code call memset.
5549 uint64_t SizeVal = ConstantSize->getZExtValue();
5550 SDValue InFlag(0, 0);
5553 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5554 unsigned BytesLeft = 0;
5555 bool TwoRepStos = false;
5558 uint64_t Val = ValC->getZExtValue() & 255;
5560 // If the value is a constant, then we can potentially use larger sets.
5561 switch (Align & 3) {
5562 case 2: // WORD aligned
5565 Val = (Val << 8) | Val;
5567 case 0: // DWORD aligned
5570 Val = (Val << 8) | Val;
5571 Val = (Val << 16) | Val;
5572 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5575 Val = (Val << 32) | Val;
5578 default: // Byte aligned
5581 Count = DAG.getIntPtrConstant(SizeVal);
5585 if (AVT.bitsGT(MVT::i8)) {
5586 unsigned UBytes = AVT.getSizeInBits() / 8;
5587 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5588 BytesLeft = SizeVal % UBytes;
5591 Chain = DAG.getCopyToReg(Chain, ValReg, DAG.getConstant(Val, AVT),
5593 InFlag = Chain.getValue(1);
5596 Count = DAG.getIntPtrConstant(SizeVal);
5597 Chain = DAG.getCopyToReg(Chain, X86::AL, Src, InFlag);
5598 InFlag = Chain.getValue(1);
5601 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5603 InFlag = Chain.getValue(1);
5604 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5606 InFlag = Chain.getValue(1);
5608 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5609 SmallVector<SDValue, 8> Ops;
5610 Ops.push_back(Chain);
5611 Ops.push_back(DAG.getValueType(AVT));
5612 Ops.push_back(InFlag);
5613 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5616 InFlag = Chain.getValue(1);
5618 MVT CVT = Count.getValueType();
5619 SDValue Left = DAG.getNode(ISD::AND, CVT, Count,
5620 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5621 Chain = DAG.getCopyToReg(Chain, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
5623 InFlag = Chain.getValue(1);
5624 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5626 Ops.push_back(Chain);
5627 Ops.push_back(DAG.getValueType(MVT::i8));
5628 Ops.push_back(InFlag);
5629 Chain = DAG.getNode(X86ISD::REP_STOS, Tys, &Ops[0], Ops.size());
5630 } else if (BytesLeft) {
5631 // Handle the last 1 - 7 bytes.
5632 unsigned Offset = SizeVal - BytesLeft;
5633 MVT AddrVT = Dst.getValueType();
5634 MVT SizeVT = Size.getValueType();
5636 Chain = DAG.getMemset(Chain,
5637 DAG.getNode(ISD::ADD, AddrVT, Dst,
5638 DAG.getConstant(Offset, AddrVT)),
5640 DAG.getConstant(BytesLeft, SizeVT),
5641 Align, DstSV, DstSVOff + Offset);
5644 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5649 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
5650 SDValue Chain, SDValue Dst, SDValue Src,
5651 SDValue Size, unsigned Align,
5653 const Value *DstSV, uint64_t DstSVOff,
5654 const Value *SrcSV, uint64_t SrcSVOff) {
5655 // This requires the copy size to be a constant, preferrably
5656 // within a subtarget-specific limit.
5657 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5660 uint64_t SizeVal = ConstantSize->getZExtValue();
5661 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5664 /// If not DWORD aligned, call the library.
5665 if ((Align & 3) != 0)
5670 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5673 unsigned UBytes = AVT.getSizeInBits() / 8;
5674 unsigned CountVal = SizeVal / UBytes;
5675 SDValue Count = DAG.getIntPtrConstant(CountVal);
5676 unsigned BytesLeft = SizeVal % UBytes;
5678 SDValue InFlag(0, 0);
5679 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RCX : X86::ECX,
5681 InFlag = Chain.getValue(1);
5682 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RDI : X86::EDI,
5684 InFlag = Chain.getValue(1);
5685 Chain = DAG.getCopyToReg(Chain, Subtarget->is64Bit() ? X86::RSI : X86::ESI,
5687 InFlag = Chain.getValue(1);
5689 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5690 SmallVector<SDValue, 8> Ops;
5691 Ops.push_back(Chain);
5692 Ops.push_back(DAG.getValueType(AVT));
5693 Ops.push_back(InFlag);
5694 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, Tys, &Ops[0], Ops.size());
5696 SmallVector<SDValue, 4> Results;
5697 Results.push_back(RepMovs);
5699 // Handle the last 1 - 7 bytes.
5700 unsigned Offset = SizeVal - BytesLeft;
5701 MVT DstVT = Dst.getValueType();
5702 MVT SrcVT = Src.getValueType();
5703 MVT SizeVT = Size.getValueType();
5704 Results.push_back(DAG.getMemcpy(Chain,
5705 DAG.getNode(ISD::ADD, DstVT, Dst,
5706 DAG.getConstant(Offset, DstVT)),
5707 DAG.getNode(ISD::ADD, SrcVT, Src,
5708 DAG.getConstant(Offset, SrcVT)),
5709 DAG.getConstant(BytesLeft, SizeVT),
5710 Align, AlwaysInline,
5711 DstSV, DstSVOff + Offset,
5712 SrcSV, SrcSVOff + Offset));
5715 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Results[0], Results.size());
5718 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
5719 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
5721 if (!Subtarget->is64Bit()) {
5722 // vastart just stores the address of the VarArgsFrameIndex slot into the
5723 // memory location argument.
5724 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5725 return DAG.getStore(Op.getOperand(0), FR,Op.getOperand(1), SV, 0);
5729 // gp_offset (0 - 6 * 8)
5730 // fp_offset (48 - 48 + 8 * 16)
5731 // overflow_arg_area (point to parameters coming in memory).
5733 SmallVector<SDValue, 8> MemOps;
5734 SDValue FIN = Op.getOperand(1);
5736 SDValue Store = DAG.getStore(Op.getOperand(0),
5737 DAG.getConstant(VarArgsGPOffset, MVT::i32),
5739 MemOps.push_back(Store);
5742 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5743 Store = DAG.getStore(Op.getOperand(0),
5744 DAG.getConstant(VarArgsFPOffset, MVT::i32),
5746 MemOps.push_back(Store);
5748 // Store ptr to overflow_arg_area
5749 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(4));
5750 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
5751 Store = DAG.getStore(Op.getOperand(0), OVFIN, FIN, SV, 0);
5752 MemOps.push_back(Store);
5754 // Store ptr to reg_save_area.
5755 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, DAG.getIntPtrConstant(8));
5756 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
5757 Store = DAG.getStore(Op.getOperand(0), RSFIN, FIN, SV, 0);
5758 MemOps.push_back(Store);
5759 return DAG.getNode(ISD::TokenFactor, MVT::Other, &MemOps[0], MemOps.size());
5762 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
5763 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5764 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
5765 SDValue Chain = Op.getOperand(0);
5766 SDValue SrcPtr = Op.getOperand(1);
5767 SDValue SrcSV = Op.getOperand(2);
5769 assert(0 && "VAArgInst is not yet implemented for x86-64!");
5774 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
5775 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
5776 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
5777 SDValue Chain = Op.getOperand(0);
5778 SDValue DstPtr = Op.getOperand(1);
5779 SDValue SrcPtr = Op.getOperand(2);
5780 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
5781 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
5783 return DAG.getMemcpy(Chain, DstPtr, SrcPtr,
5784 DAG.getIntPtrConstant(24), 8, false,
5785 DstSV, 0, SrcSV, 0);
5789 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
5790 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5792 default: return SDValue(); // Don't custom lower most intrinsics.
5793 // Comparison intrinsics.
5794 case Intrinsic::x86_sse_comieq_ss:
5795 case Intrinsic::x86_sse_comilt_ss:
5796 case Intrinsic::x86_sse_comile_ss:
5797 case Intrinsic::x86_sse_comigt_ss:
5798 case Intrinsic::x86_sse_comige_ss:
5799 case Intrinsic::x86_sse_comineq_ss:
5800 case Intrinsic::x86_sse_ucomieq_ss:
5801 case Intrinsic::x86_sse_ucomilt_ss:
5802 case Intrinsic::x86_sse_ucomile_ss:
5803 case Intrinsic::x86_sse_ucomigt_ss:
5804 case Intrinsic::x86_sse_ucomige_ss:
5805 case Intrinsic::x86_sse_ucomineq_ss:
5806 case Intrinsic::x86_sse2_comieq_sd:
5807 case Intrinsic::x86_sse2_comilt_sd:
5808 case Intrinsic::x86_sse2_comile_sd:
5809 case Intrinsic::x86_sse2_comigt_sd:
5810 case Intrinsic::x86_sse2_comige_sd:
5811 case Intrinsic::x86_sse2_comineq_sd:
5812 case Intrinsic::x86_sse2_ucomieq_sd:
5813 case Intrinsic::x86_sse2_ucomilt_sd:
5814 case Intrinsic::x86_sse2_ucomile_sd:
5815 case Intrinsic::x86_sse2_ucomigt_sd:
5816 case Intrinsic::x86_sse2_ucomige_sd:
5817 case Intrinsic::x86_sse2_ucomineq_sd: {
5819 ISD::CondCode CC = ISD::SETCC_INVALID;
5822 case Intrinsic::x86_sse_comieq_ss:
5823 case Intrinsic::x86_sse2_comieq_sd:
5827 case Intrinsic::x86_sse_comilt_ss:
5828 case Intrinsic::x86_sse2_comilt_sd:
5832 case Intrinsic::x86_sse_comile_ss:
5833 case Intrinsic::x86_sse2_comile_sd:
5837 case Intrinsic::x86_sse_comigt_ss:
5838 case Intrinsic::x86_sse2_comigt_sd:
5842 case Intrinsic::x86_sse_comige_ss:
5843 case Intrinsic::x86_sse2_comige_sd:
5847 case Intrinsic::x86_sse_comineq_ss:
5848 case Intrinsic::x86_sse2_comineq_sd:
5852 case Intrinsic::x86_sse_ucomieq_ss:
5853 case Intrinsic::x86_sse2_ucomieq_sd:
5854 Opc = X86ISD::UCOMI;
5857 case Intrinsic::x86_sse_ucomilt_ss:
5858 case Intrinsic::x86_sse2_ucomilt_sd:
5859 Opc = X86ISD::UCOMI;
5862 case Intrinsic::x86_sse_ucomile_ss:
5863 case Intrinsic::x86_sse2_ucomile_sd:
5864 Opc = X86ISD::UCOMI;
5867 case Intrinsic::x86_sse_ucomigt_ss:
5868 case Intrinsic::x86_sse2_ucomigt_sd:
5869 Opc = X86ISD::UCOMI;
5872 case Intrinsic::x86_sse_ucomige_ss:
5873 case Intrinsic::x86_sse2_ucomige_sd:
5874 Opc = X86ISD::UCOMI;
5877 case Intrinsic::x86_sse_ucomineq_ss:
5878 case Intrinsic::x86_sse2_ucomineq_sd:
5879 Opc = X86ISD::UCOMI;
5884 SDValue LHS = Op.getOperand(1);
5885 SDValue RHS = Op.getOperand(2);
5886 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
5887 SDValue Cond = DAG.getNode(Opc, MVT::i32, LHS, RHS);
5888 SDValue SetCC = DAG.getNode(X86ISD::SETCC, MVT::i8,
5889 DAG.getConstant(X86CC, MVT::i8), Cond);
5890 return DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, SetCC);
5893 // Fix vector shift instructions where the last operand is a non-immediate
5895 case Intrinsic::x86_sse2_pslli_w:
5896 case Intrinsic::x86_sse2_pslli_d:
5897 case Intrinsic::x86_sse2_pslli_q:
5898 case Intrinsic::x86_sse2_psrli_w:
5899 case Intrinsic::x86_sse2_psrli_d:
5900 case Intrinsic::x86_sse2_psrli_q:
5901 case Intrinsic::x86_sse2_psrai_w:
5902 case Intrinsic::x86_sse2_psrai_d:
5903 case Intrinsic::x86_mmx_pslli_w:
5904 case Intrinsic::x86_mmx_pslli_d:
5905 case Intrinsic::x86_mmx_pslli_q:
5906 case Intrinsic::x86_mmx_psrli_w:
5907 case Intrinsic::x86_mmx_psrli_d:
5908 case Intrinsic::x86_mmx_psrli_q:
5909 case Intrinsic::x86_mmx_psrai_w:
5910 case Intrinsic::x86_mmx_psrai_d: {
5911 SDValue ShAmt = Op.getOperand(2);
5912 if (isa<ConstantSDNode>(ShAmt))
5915 unsigned NewIntNo = 0;
5916 MVT ShAmtVT = MVT::v4i32;
5918 case Intrinsic::x86_sse2_pslli_w:
5919 NewIntNo = Intrinsic::x86_sse2_psll_w;
5921 case Intrinsic::x86_sse2_pslli_d:
5922 NewIntNo = Intrinsic::x86_sse2_psll_d;
5924 case Intrinsic::x86_sse2_pslli_q:
5925 NewIntNo = Intrinsic::x86_sse2_psll_q;
5927 case Intrinsic::x86_sse2_psrli_w:
5928 NewIntNo = Intrinsic::x86_sse2_psrl_w;
5930 case Intrinsic::x86_sse2_psrli_d:
5931 NewIntNo = Intrinsic::x86_sse2_psrl_d;
5933 case Intrinsic::x86_sse2_psrli_q:
5934 NewIntNo = Intrinsic::x86_sse2_psrl_q;
5936 case Intrinsic::x86_sse2_psrai_w:
5937 NewIntNo = Intrinsic::x86_sse2_psra_w;
5939 case Intrinsic::x86_sse2_psrai_d:
5940 NewIntNo = Intrinsic::x86_sse2_psra_d;
5943 ShAmtVT = MVT::v2i32;
5945 case Intrinsic::x86_mmx_pslli_w:
5946 NewIntNo = Intrinsic::x86_mmx_psll_w;
5948 case Intrinsic::x86_mmx_pslli_d:
5949 NewIntNo = Intrinsic::x86_mmx_psll_d;
5951 case Intrinsic::x86_mmx_pslli_q:
5952 NewIntNo = Intrinsic::x86_mmx_psll_q;
5954 case Intrinsic::x86_mmx_psrli_w:
5955 NewIntNo = Intrinsic::x86_mmx_psrl_w;
5957 case Intrinsic::x86_mmx_psrli_d:
5958 NewIntNo = Intrinsic::x86_mmx_psrl_d;
5960 case Intrinsic::x86_mmx_psrli_q:
5961 NewIntNo = Intrinsic::x86_mmx_psrl_q;
5963 case Intrinsic::x86_mmx_psrai_w:
5964 NewIntNo = Intrinsic::x86_mmx_psra_w;
5966 case Intrinsic::x86_mmx_psrai_d:
5967 NewIntNo = Intrinsic::x86_mmx_psra_d;
5969 default: abort(); // Can't reach here.
5974 MVT VT = Op.getValueType();
5975 ShAmt = DAG.getNode(ISD::BIT_CONVERT, VT,
5976 DAG.getNode(ISD::SCALAR_TO_VECTOR, ShAmtVT, ShAmt));
5977 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
5978 DAG.getConstant(NewIntNo, MVT::i32),
5979 Op.getOperand(1), ShAmt);
5984 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5985 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5988 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5990 DAG.getConstant(TD->getPointerSize(),
5991 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
5992 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(),
5993 DAG.getNode(ISD::ADD, getPointerTy(), FrameAddr, Offset),
5997 // Just load the return address.
5998 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
5999 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
6002 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6003 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6004 MFI->setFrameAddressIsTaken(true);
6005 MVT VT = Op.getValueType();
6006 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6007 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6008 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), FrameReg, VT);
6010 FrameAddr = DAG.getLoad(VT, DAG.getEntryNode(), FrameAddr, NULL, 0);
6014 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6015 SelectionDAG &DAG) {
6016 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6019 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6021 MachineFunction &MF = DAG.getMachineFunction();
6022 SDValue Chain = Op.getOperand(0);
6023 SDValue Offset = Op.getOperand(1);
6024 SDValue Handler = Op.getOperand(2);
6026 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6028 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6030 SDValue StoreAddr = DAG.getNode(ISD::SUB, getPointerTy(), Frame,
6031 DAG.getIntPtrConstant(-TD->getPointerSize()));
6032 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
6033 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
6034 Chain = DAG.getCopyToReg(Chain, StoreAddrReg, StoreAddr);
6035 MF.getRegInfo().addLiveOut(StoreAddrReg);
6037 return DAG.getNode(X86ISD::EH_RETURN,
6039 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6042 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6043 SelectionDAG &DAG) {
6044 SDValue Root = Op.getOperand(0);
6045 SDValue Trmp = Op.getOperand(1); // trampoline
6046 SDValue FPtr = Op.getOperand(2); // nested function
6047 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6049 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6051 const X86InstrInfo *TII =
6052 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6054 if (Subtarget->is64Bit()) {
6055 SDValue OutChains[6];
6057 // Large code-model.
6059 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6060 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6062 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6063 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6065 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6067 // Load the pointer to the nested function into R11.
6068 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6069 SDValue Addr = Trmp;
6070 OutChains[0] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
6073 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(2, MVT::i64));
6074 OutChains[1] = DAG.getStore(Root, FPtr, Addr, TrmpAddr, 2, false, 2);
6076 // Load the 'nest' parameter value into R10.
6077 // R10 is specified in X86CallingConv.td
6078 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6079 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(10, MVT::i64));
6080 OutChains[2] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
6083 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(12, MVT::i64));
6084 OutChains[3] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 12, false, 2);
6086 // Jump to the nested function.
6087 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6088 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(20, MVT::i64));
6089 OutChains[4] = DAG.getStore(Root, DAG.getConstant(OpCode, MVT::i16), Addr,
6092 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6093 Addr = DAG.getNode(ISD::ADD, MVT::i64, Trmp, DAG.getConstant(22, MVT::i64));
6094 OutChains[5] = DAG.getStore(Root, DAG.getConstant(ModRM, MVT::i8), Addr,
6098 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 6) };
6099 return DAG.getMergeValues(Ops, 2);
6101 const Function *Func =
6102 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6103 unsigned CC = Func->getCallingConv();
6108 assert(0 && "Unsupported calling convention");
6109 case CallingConv::C:
6110 case CallingConv::X86_StdCall: {
6111 // Pass 'nest' parameter in ECX.
6112 // Must be kept in sync with X86CallingConv.td
6115 // Check that ECX wasn't needed by an 'inreg' parameter.
6116 const FunctionType *FTy = Func->getFunctionType();
6117 const AttrListPtr &Attrs = Func->getAttributes();
6119 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6120 unsigned InRegCount = 0;
6123 for (FunctionType::param_iterator I = FTy->param_begin(),
6124 E = FTy->param_end(); I != E; ++I, ++Idx)
6125 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6126 // FIXME: should only count parameters that are lowered to integers.
6127 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6129 if (InRegCount > 2) {
6130 cerr << "Nest register in use - reduce number of inreg parameters!\n";
6136 case CallingConv::X86_FastCall:
6137 case CallingConv::Fast:
6138 // Pass 'nest' parameter in EAX.
6139 // Must be kept in sync with X86CallingConv.td
6144 SDValue OutChains[4];
6147 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(10, MVT::i32));
6148 Disp = DAG.getNode(ISD::SUB, MVT::i32, FPtr, Addr);
6150 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6151 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6152 OutChains[0] = DAG.getStore(Root, DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6155 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(1, MVT::i32));
6156 OutChains[1] = DAG.getStore(Root, Nest, Addr, TrmpAddr, 1, false, 1);
6158 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6159 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(5, MVT::i32));
6160 OutChains[2] = DAG.getStore(Root, DAG.getConstant(JMP, MVT::i8), Addr,
6161 TrmpAddr, 5, false, 1);
6163 Addr = DAG.getNode(ISD::ADD, MVT::i32, Trmp, DAG.getConstant(6, MVT::i32));
6164 OutChains[3] = DAG.getStore(Root, Disp, Addr, TrmpAddr, 6, false, 1);
6167 { Trmp, DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains, 4) };
6168 return DAG.getMergeValues(Ops, 2);
6172 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6174 The rounding mode is in bits 11:10 of FPSR, and has the following
6181 FLT_ROUNDS, on the other hand, expects the following:
6188 To perform the conversion, we do:
6189 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6192 MachineFunction &MF = DAG.getMachineFunction();
6193 const TargetMachine &TM = MF.getTarget();
6194 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6195 unsigned StackAlignment = TFI.getStackAlignment();
6196 MVT VT = Op.getValueType();
6198 // Save FP Control Word to stack slot
6199 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6200 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6202 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, MVT::Other,
6203 DAG.getEntryNode(), StackSlot);
6205 // Load FP Control Word from stack slot
6206 SDValue CWD = DAG.getLoad(MVT::i16, Chain, StackSlot, NULL, 0);
6208 // Transform as necessary
6210 DAG.getNode(ISD::SRL, MVT::i16,
6211 DAG.getNode(ISD::AND, MVT::i16,
6212 CWD, DAG.getConstant(0x800, MVT::i16)),
6213 DAG.getConstant(11, MVT::i8));
6215 DAG.getNode(ISD::SRL, MVT::i16,
6216 DAG.getNode(ISD::AND, MVT::i16,
6217 CWD, DAG.getConstant(0x400, MVT::i16)),
6218 DAG.getConstant(9, MVT::i8));
6221 DAG.getNode(ISD::AND, MVT::i16,
6222 DAG.getNode(ISD::ADD, MVT::i16,
6223 DAG.getNode(ISD::OR, MVT::i16, CWD1, CWD2),
6224 DAG.getConstant(1, MVT::i16)),
6225 DAG.getConstant(3, MVT::i16));
6228 return DAG.getNode((VT.getSizeInBits() < 16 ?
6229 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
6232 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6233 MVT VT = Op.getValueType();
6235 unsigned NumBits = VT.getSizeInBits();
6237 Op = Op.getOperand(0);
6238 if (VT == MVT::i8) {
6239 // Zero extend to i32 since there is not an i8 bsr.
6241 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6244 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6245 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6246 Op = DAG.getNode(X86ISD::BSR, VTs, Op);
6248 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6249 SmallVector<SDValue, 4> Ops;
6251 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6252 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6253 Ops.push_back(Op.getValue(1));
6254 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6256 // Finally xor with NumBits-1.
6257 Op = DAG.getNode(ISD::XOR, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6260 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6264 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6265 MVT VT = Op.getValueType();
6267 unsigned NumBits = VT.getSizeInBits();
6269 Op = Op.getOperand(0);
6270 if (VT == MVT::i8) {
6272 Op = DAG.getNode(ISD::ZERO_EXTEND, OpVT, Op);
6275 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6276 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6277 Op = DAG.getNode(X86ISD::BSF, VTs, Op);
6279 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6280 SmallVector<SDValue, 4> Ops;
6282 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6283 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6284 Ops.push_back(Op.getValue(1));
6285 Op = DAG.getNode(X86ISD::CMOV, OpVT, &Ops[0], 4);
6288 Op = DAG.getNode(ISD::TRUNCATE, MVT::i8, Op);
6292 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6293 MVT VT = Op.getValueType();
6294 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6296 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6297 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6298 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6299 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6300 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6302 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6303 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6304 // return AloBlo + AloBhi + AhiBlo;
6306 SDValue A = Op.getOperand(0);
6307 SDValue B = Op.getOperand(1);
6309 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6310 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6311 A, DAG.getConstant(32, MVT::i32));
6312 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6313 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6314 B, DAG.getConstant(32, MVT::i32));
6315 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6316 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6318 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6319 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6321 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6322 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6324 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6325 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6326 AloBhi, DAG.getConstant(32, MVT::i32));
6327 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
6328 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6329 AhiBlo, DAG.getConstant(32, MVT::i32));
6330 SDValue Res = DAG.getNode(ISD::ADD, VT, AloBlo, AloBhi);
6331 Res = DAG.getNode(ISD::ADD, VT, Res, AhiBlo);
6336 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6337 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6338 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6339 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6340 // has only one use.
6341 SDNode *N = Op.getNode();
6342 SDValue LHS = N->getOperand(0);
6343 SDValue RHS = N->getOperand(1);
6344 unsigned BaseOp = 0;
6347 switch (Op.getOpcode()) {
6348 default: assert(0 && "Unknown ovf instruction!");
6350 BaseOp = X86ISD::ADD;
6354 BaseOp = X86ISD::ADD;
6358 BaseOp = X86ISD::SUB;
6362 BaseOp = X86ISD::SUB;
6366 BaseOp = X86ISD::SMUL;
6370 BaseOp = X86ISD::UMUL;
6375 // Also sets EFLAGS.
6376 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6377 SDValue Sum = DAG.getNode(BaseOp, VTs, LHS, RHS);
6380 DAG.getNode(X86ISD::SETCC, N->getValueType(1),
6381 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6383 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6387 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6388 MVT T = Op.getValueType();
6391 switch(T.getSimpleVT()) {
6393 assert(false && "Invalid value type!");
6394 case MVT::i8: Reg = X86::AL; size = 1; break;
6395 case MVT::i16: Reg = X86::AX; size = 2; break;
6396 case MVT::i32: Reg = X86::EAX; size = 4; break;
6398 assert(Subtarget->is64Bit() && "Node not type legal!");
6399 Reg = X86::RAX; size = 8;
6402 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), Reg,
6403 Op.getOperand(2), SDValue());
6404 SDValue Ops[] = { cpIn.getValue(0),
6407 DAG.getTargetConstant(size, MVT::i8),
6409 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6410 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, Tys, Ops, 5);
6412 DAG.getCopyFromReg(Result.getValue(0), Reg, T, Result.getValue(1));
6416 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6417 SelectionDAG &DAG) {
6418 assert(Subtarget->is64Bit() && "Result not type legalized?");
6419 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6420 SDValue TheChain = Op.getOperand(0);
6421 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
6422 SDValue rax = DAG.getCopyFromReg(rd, X86::RAX, MVT::i64, rd.getValue(1));
6423 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), X86::RDX, MVT::i64,
6425 SDValue Tmp = DAG.getNode(ISD::SHL, MVT::i64, rdx,
6426 DAG.getConstant(32, MVT::i8));
6428 DAG.getNode(ISD::OR, MVT::i64, rax, Tmp),
6431 return DAG.getMergeValues(Ops, 2);
6434 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6435 SDNode *Node = Op.getNode();
6436 MVT T = Node->getValueType(0);
6437 SDValue negOp = DAG.getNode(ISD::SUB, T,
6438 DAG.getConstant(0, T), Node->getOperand(2));
6439 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD,
6440 cast<AtomicSDNode>(Node)->getMemoryVT(),
6441 Node->getOperand(0),
6442 Node->getOperand(1), negOp,
6443 cast<AtomicSDNode>(Node)->getSrcValue(),
6444 cast<AtomicSDNode>(Node)->getAlignment());
6447 /// LowerOperation - Provide custom lowering hooks for some operations.
6449 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6450 switch (Op.getOpcode()) {
6451 default: assert(0 && "Should not custom lower this!");
6452 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6453 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6454 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6455 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6456 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6457 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6458 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6459 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6460 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6461 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6462 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6463 case ISD::SHL_PARTS:
6464 case ISD::SRA_PARTS:
6465 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6466 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6467 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6468 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6469 case ISD::FABS: return LowerFABS(Op, DAG);
6470 case ISD::FNEG: return LowerFNEG(Op, DAG);
6471 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6472 case ISD::SETCC: return LowerSETCC(Op, DAG);
6473 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6474 case ISD::SELECT: return LowerSELECT(Op, DAG);
6475 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6476 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6477 case ISD::CALL: return LowerCALL(Op, DAG);
6478 case ISD::RET: return LowerRET(Op, DAG);
6479 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
6480 case ISD::VASTART: return LowerVASTART(Op, DAG);
6481 case ISD::VAARG: return LowerVAARG(Op, DAG);
6482 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6483 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6484 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6485 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6486 case ISD::FRAME_TO_ARGS_OFFSET:
6487 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6488 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6489 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6490 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6491 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6492 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6493 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6494 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6500 case ISD::UMULO: return LowerXALUO(Op, DAG);
6501 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6505 void X86TargetLowering::
6506 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6507 SelectionDAG &DAG, unsigned NewOp) {
6508 MVT T = Node->getValueType(0);
6509 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6511 SDValue Chain = Node->getOperand(0);
6512 SDValue In1 = Node->getOperand(1);
6513 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6514 Node->getOperand(2), DAG.getIntPtrConstant(0));
6515 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
6516 Node->getOperand(2), DAG.getIntPtrConstant(1));
6517 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6518 // have a MemOperand. Pass the info through as a normal operand.
6519 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6520 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6521 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6522 SDValue Result = DAG.getNode(NewOp, Tys, Ops, 5);
6523 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6524 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
6525 Results.push_back(Result.getValue(2));
6528 /// ReplaceNodeResults - Replace a node with an illegal result type
6529 /// with a new node built out of custom code.
6530 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6531 SmallVectorImpl<SDValue>&Results,
6532 SelectionDAG &DAG) {
6533 switch (N->getOpcode()) {
6535 assert(false && "Do not know how to custom type legalize this operation!");
6537 case ISD::FP_TO_SINT: {
6538 std::pair<SDValue,SDValue> Vals = FP_TO_SINTHelper(SDValue(N, 0), DAG);
6539 SDValue FIST = Vals.first, StackSlot = Vals.second;
6540 if (FIST.getNode() != 0) {
6541 MVT VT = N->getValueType(0);
6542 // Return a load from the stack slot.
6543 Results.push_back(DAG.getLoad(VT, FIST, StackSlot, NULL, 0));
6547 case ISD::READCYCLECOUNTER: {
6548 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6549 SDValue TheChain = N->getOperand(0);
6550 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, &TheChain, 1);
6551 SDValue eax = DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1));
6552 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), X86::EDX, MVT::i32,
6554 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6555 SDValue Ops[] = { eax, edx };
6556 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Ops, 2));
6557 Results.push_back(edx.getValue(1));
6560 case ISD::ATOMIC_CMP_SWAP: {
6561 MVT T = N->getValueType(0);
6562 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6563 SDValue cpInL, cpInH;
6564 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
6565 DAG.getConstant(0, MVT::i32));
6566 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(2),
6567 DAG.getConstant(1, MVT::i32));
6568 cpInL = DAG.getCopyToReg(N->getOperand(0), X86::EAX, cpInL, SDValue());
6569 cpInH = DAG.getCopyToReg(cpInL.getValue(0), X86::EDX, cpInH,
6571 SDValue swapInL, swapInH;
6572 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
6573 DAG.getConstant(0, MVT::i32));
6574 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(3),
6575 DAG.getConstant(1, MVT::i32));
6576 swapInL = DAG.getCopyToReg(cpInH.getValue(0), X86::EBX, swapInL,
6578 swapInH = DAG.getCopyToReg(swapInL.getValue(0), X86::ECX, swapInH,
6579 swapInL.getValue(1));
6580 SDValue Ops[] = { swapInH.getValue(0),
6582 swapInH.getValue(1) };
6583 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6584 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, Tys, Ops, 3);
6585 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), X86::EAX, MVT::i32,
6586 Result.getValue(1));
6587 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), X86::EDX, MVT::i32,
6588 cpOutL.getValue(2));
6589 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6590 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OpsF, 2));
6591 Results.push_back(cpOutH.getValue(1));
6594 case ISD::ATOMIC_LOAD_ADD:
6595 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6597 case ISD::ATOMIC_LOAD_AND:
6598 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6600 case ISD::ATOMIC_LOAD_NAND:
6601 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6603 case ISD::ATOMIC_LOAD_OR:
6604 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6606 case ISD::ATOMIC_LOAD_SUB:
6607 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6609 case ISD::ATOMIC_LOAD_XOR:
6610 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6612 case ISD::ATOMIC_SWAP:
6613 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
6618 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
6620 default: return NULL;
6621 case X86ISD::BSF: return "X86ISD::BSF";
6622 case X86ISD::BSR: return "X86ISD::BSR";
6623 case X86ISD::SHLD: return "X86ISD::SHLD";
6624 case X86ISD::SHRD: return "X86ISD::SHRD";
6625 case X86ISD::FAND: return "X86ISD::FAND";
6626 case X86ISD::FOR: return "X86ISD::FOR";
6627 case X86ISD::FXOR: return "X86ISD::FXOR";
6628 case X86ISD::FSRL: return "X86ISD::FSRL";
6629 case X86ISD::FILD: return "X86ISD::FILD";
6630 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
6631 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
6632 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
6633 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
6634 case X86ISD::FLD: return "X86ISD::FLD";
6635 case X86ISD::FST: return "X86ISD::FST";
6636 case X86ISD::CALL: return "X86ISD::CALL";
6637 case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
6638 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
6639 case X86ISD::BT: return "X86ISD::BT";
6640 case X86ISD::CMP: return "X86ISD::CMP";
6641 case X86ISD::COMI: return "X86ISD::COMI";
6642 case X86ISD::UCOMI: return "X86ISD::UCOMI";
6643 case X86ISD::SETCC: return "X86ISD::SETCC";
6644 case X86ISD::CMOV: return "X86ISD::CMOV";
6645 case X86ISD::BRCOND: return "X86ISD::BRCOND";
6646 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
6647 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
6648 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
6649 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
6650 case X86ISD::Wrapper: return "X86ISD::Wrapper";
6651 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
6652 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
6653 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
6654 case X86ISD::PINSRB: return "X86ISD::PINSRB";
6655 case X86ISD::PINSRW: return "X86ISD::PINSRW";
6656 case X86ISD::FMAX: return "X86ISD::FMAX";
6657 case X86ISD::FMIN: return "X86ISD::FMIN";
6658 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
6659 case X86ISD::FRCP: return "X86ISD::FRCP";
6660 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
6661 case X86ISD::THREAD_POINTER: return "X86ISD::THREAD_POINTER";
6662 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
6663 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
6664 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
6665 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
6666 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
6667 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
6668 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
6669 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
6670 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
6671 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
6672 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
6673 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
6674 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
6675 case X86ISD::VSHL: return "X86ISD::VSHL";
6676 case X86ISD::VSRL: return "X86ISD::VSRL";
6677 case X86ISD::CMPPD: return "X86ISD::CMPPD";
6678 case X86ISD::CMPPS: return "X86ISD::CMPPS";
6679 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
6680 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
6681 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
6682 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
6683 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
6684 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
6685 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
6686 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
6687 case X86ISD::ADD: return "X86ISD::ADD";
6688 case X86ISD::SUB: return "X86ISD::SUB";
6689 case X86ISD::SMUL: return "X86ISD::SMUL";
6690 case X86ISD::UMUL: return "X86ISD::UMUL";
6694 // isLegalAddressingMode - Return true if the addressing mode represented
6695 // by AM is legal for this target, for a load/store of the specified type.
6696 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
6697 const Type *Ty) const {
6698 // X86 supports extremely general addressing modes.
6700 // X86 allows a sign-extended 32-bit immediate field as a displacement.
6701 if (AM.BaseOffs <= -(1LL << 32) || AM.BaseOffs >= (1LL << 32)-1)
6705 // We can only fold this if we don't need an extra load.
6706 if (Subtarget->GVRequiresExtraLoad(AM.BaseGV, getTargetMachine(), false))
6708 // If BaseGV requires a register, we cannot also have a BaseReg.
6709 if (Subtarget->GVRequiresRegister(AM.BaseGV, getTargetMachine(), false) &&
6713 // X86-64 only supports addr of globals in small code model.
6714 if (Subtarget->is64Bit()) {
6715 if (getTargetMachine().getCodeModel() != CodeModel::Small)
6717 // If lower 4G is not available, then we must use rip-relative addressing.
6718 if (AM.BaseOffs || AM.Scale > 1)
6729 // These scales always work.
6734 // These scales are formed with basereg+scalereg. Only accept if there is
6739 default: // Other stuff never works.
6747 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
6748 if (!Ty1->isInteger() || !Ty2->isInteger())
6750 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
6751 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
6752 if (NumBits1 <= NumBits2)
6754 return Subtarget->is64Bit() || NumBits1 < 64;
6757 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
6758 if (!VT1.isInteger() || !VT2.isInteger())
6760 unsigned NumBits1 = VT1.getSizeInBits();
6761 unsigned NumBits2 = VT2.getSizeInBits();
6762 if (NumBits1 <= NumBits2)
6764 return Subtarget->is64Bit() || NumBits1 < 64;
6767 /// isShuffleMaskLegal - Targets can use this to indicate that they only
6768 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
6769 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
6770 /// are assumed to be legal.
6772 X86TargetLowering::isShuffleMaskLegal(SDValue Mask, MVT VT) const {
6773 // Only do shuffles on 128-bit vector types for now.
6774 if (VT.getSizeInBits() == 64) return false;
6775 return (Mask.getNode()->getNumOperands() <= 4 ||
6776 isIdentityMask(Mask.getNode()) ||
6777 isIdentityMask(Mask.getNode(), true) ||
6778 isSplatMask(Mask.getNode()) ||
6779 isPSHUFHW_PSHUFLWMask(Mask.getNode()) ||
6780 X86::isUNPCKLMask(Mask.getNode()) ||
6781 X86::isUNPCKHMask(Mask.getNode()) ||
6782 X86::isUNPCKL_v_undef_Mask(Mask.getNode()) ||
6783 X86::isUNPCKH_v_undef_Mask(Mask.getNode()));
6787 X86TargetLowering::isVectorClearMaskLegal(const std::vector<SDValue> &BVOps,
6788 MVT EVT, SelectionDAG &DAG) const {
6789 unsigned NumElts = BVOps.size();
6790 // Only do shuffles on 128-bit vector types for now.
6791 if (EVT.getSizeInBits() * NumElts == 64) return false;
6792 if (NumElts == 2) return true;
6794 return (isMOVLMask(&BVOps[0], 4) ||
6795 isCommutedMOVL(&BVOps[0], 4, true) ||
6796 isSHUFPMask(&BVOps[0], 4) ||
6797 isCommutedSHUFP(&BVOps[0], 4));
6802 //===----------------------------------------------------------------------===//
6803 // X86 Scheduler Hooks
6804 //===----------------------------------------------------------------------===//
6806 // private utility function
6808 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
6809 MachineBasicBlock *MBB,
6817 TargetRegisterClass *RC,
6819 // For the atomic bitwise operator, we generate
6822 // ld t1 = [bitinstr.addr]
6823 // op t2 = t1, [bitinstr.val]
6825 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
6827 // fallthrough -->nextMBB
6828 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6829 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6830 MachineFunction::iterator MBBIter = MBB;
6833 /// First build the CFG
6834 MachineFunction *F = MBB->getParent();
6835 MachineBasicBlock *thisMBB = MBB;
6836 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6837 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6838 F->insert(MBBIter, newMBB);
6839 F->insert(MBBIter, nextMBB);
6841 // Move all successors to thisMBB to nextMBB
6842 nextMBB->transferSuccessors(thisMBB);
6844 // Update thisMBB to fall through to newMBB
6845 thisMBB->addSuccessor(newMBB);
6847 // newMBB jumps to itself and fall through to nextMBB
6848 newMBB->addSuccessor(nextMBB);
6849 newMBB->addSuccessor(newMBB);
6851 // Insert instructions into newMBB based on incoming instruction
6852 assert(bInstr->getNumOperands() < 8 && "unexpected number of operands");
6853 MachineOperand& destOper = bInstr->getOperand(0);
6854 MachineOperand* argOpers[6];
6855 int numArgs = bInstr->getNumOperands() - 1;
6856 for (int i=0; i < numArgs; ++i)
6857 argOpers[i] = &bInstr->getOperand(i+1);
6859 // x86 address has 4 operands: base, index, scale, and displacement
6860 int lastAddrIndx = 3; // [0,3]
6863 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6864 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(LoadOpc), t1);
6865 for (int i=0; i <= lastAddrIndx; ++i)
6866 (*MIB).addOperand(*argOpers[i]);
6868 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
6870 MIB = BuildMI(newMBB, TII->get(notOpc), tt).addReg(t1);
6875 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6876 assert((argOpers[valArgIndx]->isReg() ||
6877 argOpers[valArgIndx]->isImm()) &&
6879 if (argOpers[valArgIndx]->isReg())
6880 MIB = BuildMI(newMBB, TII->get(regOpc), t2);
6882 MIB = BuildMI(newMBB, TII->get(immOpc), t2);
6884 (*MIB).addOperand(*argOpers[valArgIndx]);
6886 MIB = BuildMI(newMBB, TII->get(copyOpc), EAXreg);
6889 MIB = BuildMI(newMBB, TII->get(CXchgOpc));
6890 for (int i=0; i <= lastAddrIndx; ++i)
6891 (*MIB).addOperand(*argOpers[i]);
6893 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
6894 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
6896 MIB = BuildMI(newMBB, TII->get(copyOpc), destOper.getReg());
6900 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
6902 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
6906 // private utility function: 64 bit atomics on 32 bit host.
6908 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
6909 MachineBasicBlock *MBB,
6915 // For the atomic bitwise operator, we generate
6916 // thisMBB (instructions are in pairs, except cmpxchg8b)
6917 // ld t1,t2 = [bitinstr.addr]
6919 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
6920 // op t5, t6 <- out1, out2, [bitinstr.val]
6921 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
6922 // mov ECX, EBX <- t5, t6
6923 // mov EAX, EDX <- t1, t2
6924 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
6925 // mov t3, t4 <- EAX, EDX
6927 // result in out1, out2
6928 // fallthrough -->nextMBB
6930 const TargetRegisterClass *RC = X86::GR32RegisterClass;
6931 const unsigned LoadOpc = X86::MOV32rm;
6932 const unsigned copyOpc = X86::MOV32rr;
6933 const unsigned NotOpc = X86::NOT32r;
6934 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6935 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
6936 MachineFunction::iterator MBBIter = MBB;
6939 /// First build the CFG
6940 MachineFunction *F = MBB->getParent();
6941 MachineBasicBlock *thisMBB = MBB;
6942 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
6943 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
6944 F->insert(MBBIter, newMBB);
6945 F->insert(MBBIter, nextMBB);
6947 // Move all successors to thisMBB to nextMBB
6948 nextMBB->transferSuccessors(thisMBB);
6950 // Update thisMBB to fall through to newMBB
6951 thisMBB->addSuccessor(newMBB);
6953 // newMBB jumps to itself and fall through to nextMBB
6954 newMBB->addSuccessor(nextMBB);
6955 newMBB->addSuccessor(newMBB);
6957 // Insert instructions into newMBB based on incoming instruction
6958 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
6959 assert(bInstr->getNumOperands() < 18 && "unexpected number of operands");
6960 MachineOperand& dest1Oper = bInstr->getOperand(0);
6961 MachineOperand& dest2Oper = bInstr->getOperand(1);
6962 MachineOperand* argOpers[6];
6963 for (int i=0; i < 6; ++i)
6964 argOpers[i] = &bInstr->getOperand(i+2);
6966 // x86 address has 4 operands: base, index, scale, and displacement
6967 int lastAddrIndx = 3; // [0,3]
6969 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
6970 MachineInstrBuilder MIB = BuildMI(thisMBB, TII->get(LoadOpc), t1);
6971 for (int i=0; i <= lastAddrIndx; ++i)
6972 (*MIB).addOperand(*argOpers[i]);
6973 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
6974 MIB = BuildMI(thisMBB, TII->get(LoadOpc), t2);
6975 // add 4 to displacement.
6976 for (int i=0; i <= lastAddrIndx-1; ++i)
6977 (*MIB).addOperand(*argOpers[i]);
6978 MachineOperand newOp3 = *(argOpers[3]);
6980 newOp3.setImm(newOp3.getImm()+4);
6982 newOp3.setOffset(newOp3.getOffset()+4);
6983 (*MIB).addOperand(newOp3);
6985 // t3/4 are defined later, at the bottom of the loop
6986 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
6987 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
6988 BuildMI(newMBB, TII->get(X86::PHI), dest1Oper.getReg())
6989 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
6990 BuildMI(newMBB, TII->get(X86::PHI), dest2Oper.getReg())
6991 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
6993 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
6994 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
6996 MIB = BuildMI(newMBB, TII->get(NotOpc), tt1).addReg(t1);
6997 MIB = BuildMI(newMBB, TII->get(NotOpc), tt2).addReg(t2);
7003 assert((argOpers[4]->isReg() || argOpers[4]->isImm()) &&
7005 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7006 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7007 if (argOpers[4]->isReg())
7008 MIB = BuildMI(newMBB, TII->get(regOpcL), t5);
7010 MIB = BuildMI(newMBB, TII->get(immOpcL), t5);
7011 if (regOpcL != X86::MOV32rr)
7013 (*MIB).addOperand(*argOpers[4]);
7014 assert(argOpers[5]->isReg() == argOpers[4]->isReg());
7015 assert(argOpers[5]->isImm() == argOpers[4]->isImm());
7016 if (argOpers[5]->isReg())
7017 MIB = BuildMI(newMBB, TII->get(regOpcH), t6);
7019 MIB = BuildMI(newMBB, TII->get(immOpcH), t6);
7020 if (regOpcH != X86::MOV32rr)
7022 (*MIB).addOperand(*argOpers[5]);
7024 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EAX);
7026 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EDX);
7029 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::EBX);
7031 MIB = BuildMI(newMBB, TII->get(copyOpc), X86::ECX);
7034 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG8B));
7035 for (int i=0; i <= lastAddrIndx; ++i)
7036 (*MIB).addOperand(*argOpers[i]);
7038 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7039 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7041 MIB = BuildMI(newMBB, TII->get(copyOpc), t3);
7042 MIB.addReg(X86::EAX);
7043 MIB = BuildMI(newMBB, TII->get(copyOpc), t4);
7044 MIB.addReg(X86::EDX);
7047 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
7049 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7053 // private utility function
7055 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7056 MachineBasicBlock *MBB,
7058 // For the atomic min/max operator, we generate
7061 // ld t1 = [min/max.addr]
7062 // mov t2 = [min/max.val]
7064 // cmov[cond] t2 = t1
7066 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7068 // fallthrough -->nextMBB
7070 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7071 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7072 MachineFunction::iterator MBBIter = MBB;
7075 /// First build the CFG
7076 MachineFunction *F = MBB->getParent();
7077 MachineBasicBlock *thisMBB = MBB;
7078 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7079 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7080 F->insert(MBBIter, newMBB);
7081 F->insert(MBBIter, nextMBB);
7083 // Move all successors to thisMBB to nextMBB
7084 nextMBB->transferSuccessors(thisMBB);
7086 // Update thisMBB to fall through to newMBB
7087 thisMBB->addSuccessor(newMBB);
7089 // newMBB jumps to newMBB and fall through to nextMBB
7090 newMBB->addSuccessor(nextMBB);
7091 newMBB->addSuccessor(newMBB);
7093 // Insert instructions into newMBB based on incoming instruction
7094 assert(mInstr->getNumOperands() < 8 && "unexpected number of operands");
7095 MachineOperand& destOper = mInstr->getOperand(0);
7096 MachineOperand* argOpers[6];
7097 int numArgs = mInstr->getNumOperands() - 1;
7098 for (int i=0; i < numArgs; ++i)
7099 argOpers[i] = &mInstr->getOperand(i+1);
7101 // x86 address has 4 operands: base, index, scale, and displacement
7102 int lastAddrIndx = 3; // [0,3]
7105 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7106 MachineInstrBuilder MIB = BuildMI(newMBB, TII->get(X86::MOV32rm), t1);
7107 for (int i=0; i <= lastAddrIndx; ++i)
7108 (*MIB).addOperand(*argOpers[i]);
7110 // We only support register and immediate values
7111 assert((argOpers[valArgIndx]->isReg() ||
7112 argOpers[valArgIndx]->isImm()) &&
7115 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7116 if (argOpers[valArgIndx]->isReg())
7117 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
7119 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), t2);
7120 (*MIB).addOperand(*argOpers[valArgIndx]);
7122 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), X86::EAX);
7125 MIB = BuildMI(newMBB, TII->get(X86::CMP32rr));
7130 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7131 MIB = BuildMI(newMBB, TII->get(cmovOpc),t3);
7135 // Cmp and exchange if none has modified the memory location
7136 MIB = BuildMI(newMBB, TII->get(X86::LCMPXCHG32));
7137 for (int i=0; i <= lastAddrIndx; ++i)
7138 (*MIB).addOperand(*argOpers[i]);
7140 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7141 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7143 MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
7144 MIB.addReg(X86::EAX);
7147 BuildMI(newMBB, TII->get(X86::JNE)).addMBB(newMBB);
7149 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7155 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7156 MachineBasicBlock *BB) {
7157 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7158 switch (MI->getOpcode()) {
7159 default: assert(false && "Unexpected instr type to insert");
7160 case X86::CMOV_V1I64:
7161 case X86::CMOV_FR32:
7162 case X86::CMOV_FR64:
7163 case X86::CMOV_V4F32:
7164 case X86::CMOV_V2F64:
7165 case X86::CMOV_V2I64: {
7166 // To "insert" a SELECT_CC instruction, we actually have to insert the
7167 // diamond control-flow pattern. The incoming instruction knows the
7168 // destination vreg to set, the condition code register to branch on, the
7169 // true/false values to select between, and a branch opcode to use.
7170 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7171 MachineFunction::iterator It = BB;
7177 // cmpTY ccX, r1, r2
7179 // fallthrough --> copy0MBB
7180 MachineBasicBlock *thisMBB = BB;
7181 MachineFunction *F = BB->getParent();
7182 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7183 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7185 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7186 BuildMI(BB, TII->get(Opc)).addMBB(sinkMBB);
7187 F->insert(It, copy0MBB);
7188 F->insert(It, sinkMBB);
7189 // Update machine-CFG edges by transferring all successors of the current
7190 // block to the new block which will contain the Phi node for the select.
7191 sinkMBB->transferSuccessors(BB);
7193 // Add the true and fallthrough blocks as its successors.
7194 BB->addSuccessor(copy0MBB);
7195 BB->addSuccessor(sinkMBB);
7198 // %FalseValue = ...
7199 // # fallthrough to sinkMBB
7202 // Update machine-CFG edges
7203 BB->addSuccessor(sinkMBB);
7206 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7209 BuildMI(BB, TII->get(X86::PHI), MI->getOperand(0).getReg())
7210 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7211 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7213 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7217 case X86::FP32_TO_INT16_IN_MEM:
7218 case X86::FP32_TO_INT32_IN_MEM:
7219 case X86::FP32_TO_INT64_IN_MEM:
7220 case X86::FP64_TO_INT16_IN_MEM:
7221 case X86::FP64_TO_INT32_IN_MEM:
7222 case X86::FP64_TO_INT64_IN_MEM:
7223 case X86::FP80_TO_INT16_IN_MEM:
7224 case X86::FP80_TO_INT32_IN_MEM:
7225 case X86::FP80_TO_INT64_IN_MEM: {
7226 // Change the floating point control register to use "round towards zero"
7227 // mode when truncating to an integer value.
7228 MachineFunction *F = BB->getParent();
7229 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7230 addFrameReference(BuildMI(BB, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7232 // Load the old value of the high byte of the control word...
7234 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7235 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
7237 // Set the high part to be round to zero...
7238 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mi)), CWFrameIdx)
7241 // Reload the modified control word now...
7242 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
7244 // Restore the memory image of control word to original value
7245 addFrameReference(BuildMI(BB, TII->get(X86::MOV16mr)), CWFrameIdx)
7248 // Get the X86 opcode to use.
7250 switch (MI->getOpcode()) {
7251 default: assert(0 && "illegal opcode!");
7252 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7253 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7254 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7255 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7256 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7257 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7258 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7259 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7260 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7264 MachineOperand &Op = MI->getOperand(0);
7266 AM.BaseType = X86AddressMode::RegBase;
7267 AM.Base.Reg = Op.getReg();
7269 AM.BaseType = X86AddressMode::FrameIndexBase;
7270 AM.Base.FrameIndex = Op.getIndex();
7272 Op = MI->getOperand(1);
7274 AM.Scale = Op.getImm();
7275 Op = MI->getOperand(2);
7277 AM.IndexReg = Op.getImm();
7278 Op = MI->getOperand(3);
7279 if (Op.isGlobal()) {
7280 AM.GV = Op.getGlobal();
7282 AM.Disp = Op.getImm();
7284 addFullAddress(BuildMI(BB, TII->get(Opc)), AM)
7285 .addReg(MI->getOperand(4).getReg());
7287 // Reload the original control word now.
7288 addFrameReference(BuildMI(BB, TII->get(X86::FLDCW16m)), CWFrameIdx);
7290 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7293 case X86::ATOMAND32:
7294 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7295 X86::AND32ri, X86::MOV32rm,
7296 X86::LCMPXCHG32, X86::MOV32rr,
7297 X86::NOT32r, X86::EAX,
7298 X86::GR32RegisterClass);
7300 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7301 X86::OR32ri, X86::MOV32rm,
7302 X86::LCMPXCHG32, X86::MOV32rr,
7303 X86::NOT32r, X86::EAX,
7304 X86::GR32RegisterClass);
7305 case X86::ATOMXOR32:
7306 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7307 X86::XOR32ri, X86::MOV32rm,
7308 X86::LCMPXCHG32, X86::MOV32rr,
7309 X86::NOT32r, X86::EAX,
7310 X86::GR32RegisterClass);
7311 case X86::ATOMNAND32:
7312 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7313 X86::AND32ri, X86::MOV32rm,
7314 X86::LCMPXCHG32, X86::MOV32rr,
7315 X86::NOT32r, X86::EAX,
7316 X86::GR32RegisterClass, true);
7317 case X86::ATOMMIN32:
7318 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7319 case X86::ATOMMAX32:
7320 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7321 case X86::ATOMUMIN32:
7322 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7323 case X86::ATOMUMAX32:
7324 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7326 case X86::ATOMAND16:
7327 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7328 X86::AND16ri, X86::MOV16rm,
7329 X86::LCMPXCHG16, X86::MOV16rr,
7330 X86::NOT16r, X86::AX,
7331 X86::GR16RegisterClass);
7333 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7334 X86::OR16ri, X86::MOV16rm,
7335 X86::LCMPXCHG16, X86::MOV16rr,
7336 X86::NOT16r, X86::AX,
7337 X86::GR16RegisterClass);
7338 case X86::ATOMXOR16:
7339 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7340 X86::XOR16ri, X86::MOV16rm,
7341 X86::LCMPXCHG16, X86::MOV16rr,
7342 X86::NOT16r, X86::AX,
7343 X86::GR16RegisterClass);
7344 case X86::ATOMNAND16:
7345 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7346 X86::AND16ri, X86::MOV16rm,
7347 X86::LCMPXCHG16, X86::MOV16rr,
7348 X86::NOT16r, X86::AX,
7349 X86::GR16RegisterClass, true);
7350 case X86::ATOMMIN16:
7351 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7352 case X86::ATOMMAX16:
7353 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7354 case X86::ATOMUMIN16:
7355 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7356 case X86::ATOMUMAX16:
7357 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7360 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7361 X86::AND8ri, X86::MOV8rm,
7362 X86::LCMPXCHG8, X86::MOV8rr,
7363 X86::NOT8r, X86::AL,
7364 X86::GR8RegisterClass);
7366 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7367 X86::OR8ri, X86::MOV8rm,
7368 X86::LCMPXCHG8, X86::MOV8rr,
7369 X86::NOT8r, X86::AL,
7370 X86::GR8RegisterClass);
7372 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7373 X86::XOR8ri, X86::MOV8rm,
7374 X86::LCMPXCHG8, X86::MOV8rr,
7375 X86::NOT8r, X86::AL,
7376 X86::GR8RegisterClass);
7377 case X86::ATOMNAND8:
7378 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7379 X86::AND8ri, X86::MOV8rm,
7380 X86::LCMPXCHG8, X86::MOV8rr,
7381 X86::NOT8r, X86::AL,
7382 X86::GR8RegisterClass, true);
7383 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7384 // This group is for 64-bit host.
7385 case X86::ATOMAND64:
7386 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7387 X86::AND64ri32, X86::MOV64rm,
7388 X86::LCMPXCHG64, X86::MOV64rr,
7389 X86::NOT64r, X86::RAX,
7390 X86::GR64RegisterClass);
7392 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7393 X86::OR64ri32, X86::MOV64rm,
7394 X86::LCMPXCHG64, X86::MOV64rr,
7395 X86::NOT64r, X86::RAX,
7396 X86::GR64RegisterClass);
7397 case X86::ATOMXOR64:
7398 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7399 X86::XOR64ri32, X86::MOV64rm,
7400 X86::LCMPXCHG64, X86::MOV64rr,
7401 X86::NOT64r, X86::RAX,
7402 X86::GR64RegisterClass);
7403 case X86::ATOMNAND64:
7404 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7405 X86::AND64ri32, X86::MOV64rm,
7406 X86::LCMPXCHG64, X86::MOV64rr,
7407 X86::NOT64r, X86::RAX,
7408 X86::GR64RegisterClass, true);
7409 case X86::ATOMMIN64:
7410 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7411 case X86::ATOMMAX64:
7412 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7413 case X86::ATOMUMIN64:
7414 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7415 case X86::ATOMUMAX64:
7416 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7418 // This group does 64-bit operations on a 32-bit host.
7419 case X86::ATOMAND6432:
7420 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7421 X86::AND32rr, X86::AND32rr,
7422 X86::AND32ri, X86::AND32ri,
7424 case X86::ATOMOR6432:
7425 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7426 X86::OR32rr, X86::OR32rr,
7427 X86::OR32ri, X86::OR32ri,
7429 case X86::ATOMXOR6432:
7430 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7431 X86::XOR32rr, X86::XOR32rr,
7432 X86::XOR32ri, X86::XOR32ri,
7434 case X86::ATOMNAND6432:
7435 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7436 X86::AND32rr, X86::AND32rr,
7437 X86::AND32ri, X86::AND32ri,
7439 case X86::ATOMADD6432:
7440 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7441 X86::ADD32rr, X86::ADC32rr,
7442 X86::ADD32ri, X86::ADC32ri,
7444 case X86::ATOMSUB6432:
7445 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7446 X86::SUB32rr, X86::SBB32rr,
7447 X86::SUB32ri, X86::SBB32ri,
7449 case X86::ATOMSWAP6432:
7450 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7451 X86::MOV32rr, X86::MOV32rr,
7452 X86::MOV32ri, X86::MOV32ri,
7457 //===----------------------------------------------------------------------===//
7458 // X86 Optimization Hooks
7459 //===----------------------------------------------------------------------===//
7461 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7465 const SelectionDAG &DAG,
7466 unsigned Depth) const {
7467 unsigned Opc = Op.getOpcode();
7468 assert((Opc >= ISD::BUILTIN_OP_END ||
7469 Opc == ISD::INTRINSIC_WO_CHAIN ||
7470 Opc == ISD::INTRINSIC_W_CHAIN ||
7471 Opc == ISD::INTRINSIC_VOID) &&
7472 "Should use MaskedValueIsZero if you don't know whether Op"
7473 " is a target node!");
7475 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7479 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7480 Mask.getBitWidth() - 1);
7485 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7486 /// node is a GlobalAddress + offset.
7487 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7488 GlobalValue* &GA, int64_t &Offset) const{
7489 if (N->getOpcode() == X86ISD::Wrapper) {
7490 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7491 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7492 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7496 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7499 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7500 const TargetLowering &TLI) {
7503 if (TLI.isGAPlusOffset(Base, GV, Offset))
7504 return (GV->getAlignment() >= N && (Offset % N) == 0);
7505 // DAG combine handles the stack object case.
7509 static bool EltsFromConsecutiveLoads(SDNode *N, SDValue PermMask,
7510 unsigned NumElems, MVT EVT,
7512 SelectionDAG &DAG, MachineFrameInfo *MFI,
7513 const TargetLowering &TLI) {
7515 for (unsigned i = 0; i < NumElems; ++i) {
7516 SDValue Idx = PermMask.getOperand(i);
7517 if (Idx.getOpcode() == ISD::UNDEF) {
7523 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7524 if (!Elt.getNode() ||
7525 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7528 Base = Elt.getNode();
7529 if (Base->getOpcode() == ISD::UNDEF)
7533 if (Elt.getOpcode() == ISD::UNDEF)
7536 if (!TLI.isConsecutiveLoad(Elt.getNode(), Base,
7537 EVT.getSizeInBits()/8, i, MFI))
7543 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7544 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7545 /// if the load addresses are consecutive, non-overlapping, and in the right
7547 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7548 const TargetLowering &TLI) {
7549 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7550 MVT VT = N->getValueType(0);
7551 MVT EVT = VT.getVectorElementType();
7552 SDValue PermMask = N->getOperand(2);
7553 unsigned NumElems = PermMask.getNumOperands();
7554 SDNode *Base = NULL;
7555 if (!EltsFromConsecutiveLoads(N, PermMask, NumElems, EVT, Base,
7559 LoadSDNode *LD = cast<LoadSDNode>(Base);
7560 if (isBaseAlignmentOfN(16, Base->getOperand(1).getNode(), TLI))
7561 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7562 LD->getSrcValueOffset(), LD->isVolatile());
7563 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), LD->getSrcValue(),
7564 LD->getSrcValueOffset(), LD->isVolatile(),
7565 LD->getAlignment());
7568 /// PerformBuildVectorCombine - build_vector 0,(load i64 / f64) -> movq / movsd.
7569 static SDValue PerformBuildVectorCombine(SDNode *N, SelectionDAG &DAG,
7570 TargetLowering::DAGCombinerInfo &DCI,
7571 const X86Subtarget *Subtarget,
7572 const TargetLowering &TLI) {
7573 unsigned NumOps = N->getNumOperands();
7575 // Ignore single operand BUILD_VECTOR.
7579 MVT VT = N->getValueType(0);
7580 MVT EVT = VT.getVectorElementType();
7581 if ((EVT != MVT::i64 && EVT != MVT::f64) || Subtarget->is64Bit())
7582 // We are looking for load i64 and zero extend. We want to transform
7583 // it before legalizer has a chance to expand it. Also look for i64
7584 // BUILD_PAIR bit casted to f64.
7586 // This must be an insertion into a zero vector.
7587 SDValue HighElt = N->getOperand(1);
7588 if (!isZeroNode(HighElt))
7591 // Value must be a load.
7592 SDNode *Base = N->getOperand(0).getNode();
7593 if (!isa<LoadSDNode>(Base)) {
7594 if (Base->getOpcode() != ISD::BIT_CONVERT)
7596 Base = Base->getOperand(0).getNode();
7597 if (!isa<LoadSDNode>(Base))
7601 // Transform it into VZEXT_LOAD addr.
7602 LoadSDNode *LD = cast<LoadSDNode>(Base);
7604 // Load must not be an extload.
7605 if (LD->getExtensionType() != ISD::NON_EXTLOAD)
7608 // Load type should legal type so we don't have to legalize it.
7609 if (!TLI.isTypeLegal(VT))
7612 SDVTList Tys = DAG.getVTList(VT, MVT::Other);
7613 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
7614 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, Tys, Ops, 2);
7615 TargetLowering::TargetLoweringOpt TLO(DAG);
7616 TLO.CombineTo(SDValue(Base, 1), ResNode.getValue(1));
7617 DCI.CommitTargetLoweringOpt(TLO);
7621 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
7622 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
7623 const X86Subtarget *Subtarget) {
7624 SDValue Cond = N->getOperand(0);
7626 // If we have SSE[12] support, try to form min/max nodes.
7627 if (Subtarget->hasSSE2() &&
7628 (N->getValueType(0) == MVT::f32 || N->getValueType(0) == MVT::f64)) {
7629 if (Cond.getOpcode() == ISD::SETCC) {
7630 // Get the LHS/RHS of the select.
7631 SDValue LHS = N->getOperand(1);
7632 SDValue RHS = N->getOperand(2);
7633 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
7635 unsigned Opcode = 0;
7636 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
7639 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
7642 if (!UnsafeFPMath) break;
7644 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
7646 Opcode = X86ISD::FMIN;
7649 case ISD::SETOGT: // (X > Y) ? X : Y -> max
7652 if (!UnsafeFPMath) break;
7654 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
7656 Opcode = X86ISD::FMAX;
7659 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
7662 case ISD::SETOGT: // (X > Y) ? Y : X -> min
7665 if (!UnsafeFPMath) break;
7667 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
7669 Opcode = X86ISD::FMIN;
7672 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
7675 if (!UnsafeFPMath) break;
7677 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
7679 Opcode = X86ISD::FMAX;
7685 return DAG.getNode(Opcode, N->getValueType(0), LHS, RHS);
7693 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
7695 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
7696 const X86Subtarget *Subtarget) {
7697 // On X86 with SSE2 support, we can transform this to a vector shift if
7698 // all elements are shifted by the same amount. We can't do this in legalize
7699 // because the a constant vector is typically transformed to a constant pool
7700 // so we have no knowledge of the shift amount.
7701 if (!Subtarget->hasSSE2())
7704 MVT VT = N->getValueType(0);
7705 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
7708 SDValue ShAmtOp = N->getOperand(1);
7709 MVT EltVT = VT.getVectorElementType();
7711 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
7712 unsigned NumElts = VT.getVectorNumElements();
7714 for (; i != NumElts; ++i) {
7715 SDValue Arg = ShAmtOp.getOperand(i);
7716 if (Arg.getOpcode() == ISD::UNDEF) continue;
7720 for (; i != NumElts; ++i) {
7721 SDValue Arg = ShAmtOp.getOperand(i);
7722 if (Arg.getOpcode() == ISD::UNDEF) continue;
7723 if (Arg != BaseShAmt) {
7727 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
7728 isSplatMask(ShAmtOp.getOperand(2).getNode())) {
7729 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, ShAmtOp,
7730 DAG.getIntPtrConstant(0));
7734 if (EltVT.bitsGT(MVT::i32))
7735 BaseShAmt = DAG.getNode(ISD::TRUNCATE, MVT::i32, BaseShAmt);
7736 else if (EltVT.bitsLT(MVT::i32))
7737 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BaseShAmt);
7739 // The shift amount is identical so we can do a vector shift.
7740 SDValue ValOp = N->getOperand(0);
7741 switch (N->getOpcode()) {
7743 assert(0 && "Unknown shift opcode!");
7746 if (VT == MVT::v2i64)
7747 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7748 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
7750 if (VT == MVT::v4i32)
7751 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7752 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
7754 if (VT == MVT::v8i16)
7755 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7756 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
7760 if (VT == MVT::v4i32)
7761 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7762 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
7764 if (VT == MVT::v8i16)
7765 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7766 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
7770 if (VT == MVT::v2i64)
7771 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7772 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
7774 if (VT == MVT::v4i32)
7775 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7776 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
7778 if (VT == MVT::v8i16)
7779 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, VT,
7780 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
7787 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
7788 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
7789 const X86Subtarget *Subtarget) {
7790 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
7791 // the FP state in cases where an emms may be missing.
7792 // A preferable solution to the general problem is to figure out the right
7793 // places to insert EMMS. This qualifies as a quick hack.
7794 StoreSDNode *St = cast<StoreSDNode>(N);
7795 if (St->getValue().getValueType().isVector() &&
7796 St->getValue().getValueType().getSizeInBits() == 64 &&
7797 isa<LoadSDNode>(St->getValue()) &&
7798 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
7799 St->getChain().hasOneUse() && !St->isVolatile()) {
7800 SDNode* LdVal = St->getValue().getNode();
7802 int TokenFactorIndex = -1;
7803 SmallVector<SDValue, 8> Ops;
7804 SDNode* ChainVal = St->getChain().getNode();
7805 // Must be a store of a load. We currently handle two cases: the load
7806 // is a direct child, and it's under an intervening TokenFactor. It is
7807 // possible to dig deeper under nested TokenFactors.
7808 if (ChainVal == LdVal)
7809 Ld = cast<LoadSDNode>(St->getChain());
7810 else if (St->getValue().hasOneUse() &&
7811 ChainVal->getOpcode() == ISD::TokenFactor) {
7812 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
7813 if (ChainVal->getOperand(i).getNode() == LdVal) {
7814 TokenFactorIndex = i;
7815 Ld = cast<LoadSDNode>(St->getValue());
7817 Ops.push_back(ChainVal->getOperand(i));
7821 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
7822 if (Subtarget->is64Bit()) {
7823 SDValue NewLd = DAG.getLoad(MVT::i64, Ld->getChain(),
7824 Ld->getBasePtr(), Ld->getSrcValue(),
7825 Ld->getSrcValueOffset(), Ld->isVolatile(),
7826 Ld->getAlignment());
7827 SDValue NewChain = NewLd.getValue(1);
7828 if (TokenFactorIndex != -1) {
7829 Ops.push_back(NewChain);
7830 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7833 return DAG.getStore(NewChain, NewLd, St->getBasePtr(),
7834 St->getSrcValue(), St->getSrcValueOffset(),
7835 St->isVolatile(), St->getAlignment());
7838 // Otherwise, lower to two 32-bit copies.
7839 SDValue LoAddr = Ld->getBasePtr();
7840 SDValue HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7841 DAG.getConstant(4, MVT::i32));
7843 SDValue LoLd = DAG.getLoad(MVT::i32, Ld->getChain(), LoAddr,
7844 Ld->getSrcValue(), Ld->getSrcValueOffset(),
7845 Ld->isVolatile(), Ld->getAlignment());
7846 SDValue HiLd = DAG.getLoad(MVT::i32, Ld->getChain(), HiAddr,
7847 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
7849 MinAlign(Ld->getAlignment(), 4));
7851 SDValue NewChain = LoLd.getValue(1);
7852 if (TokenFactorIndex != -1) {
7853 Ops.push_back(LoLd);
7854 Ops.push_back(HiLd);
7855 NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0],
7859 LoAddr = St->getBasePtr();
7860 HiAddr = DAG.getNode(ISD::ADD, MVT::i32, LoAddr,
7861 DAG.getConstant(4, MVT::i32));
7863 SDValue LoSt = DAG.getStore(NewChain, LoLd, LoAddr,
7864 St->getSrcValue(), St->getSrcValueOffset(),
7865 St->isVolatile(), St->getAlignment());
7866 SDValue HiSt = DAG.getStore(NewChain, HiLd, HiAddr,
7868 St->getSrcValueOffset() + 4,
7870 MinAlign(St->getAlignment(), 4));
7871 return DAG.getNode(ISD::TokenFactor, MVT::Other, LoSt, HiSt);
7877 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
7878 /// X86ISD::FXOR nodes.
7879 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
7880 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
7881 // F[X]OR(0.0, x) -> x
7882 // F[X]OR(x, 0.0) -> x
7883 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7884 if (C->getValueAPF().isPosZero())
7885 return N->getOperand(1);
7886 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7887 if (C->getValueAPF().isPosZero())
7888 return N->getOperand(0);
7892 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
7893 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
7894 // FAND(0.0, x) -> 0.0
7895 // FAND(x, 0.0) -> 0.0
7896 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
7897 if (C->getValueAPF().isPosZero())
7898 return N->getOperand(0);
7899 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
7900 if (C->getValueAPF().isPosZero())
7901 return N->getOperand(1);
7905 static SDValue PerformBTCombine(SDNode *N,
7907 TargetLowering::DAGCombinerInfo &DCI) {
7908 // BT ignores high bits in the bit index operand.
7909 SDValue Op1 = N->getOperand(1);
7910 if (Op1.hasOneUse()) {
7911 unsigned BitWidth = Op1.getValueSizeInBits();
7912 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
7913 APInt KnownZero, KnownOne;
7914 TargetLowering::TargetLoweringOpt TLO(DAG);
7915 TargetLowering &TLI = DAG.getTargetLoweringInfo();
7916 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
7917 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
7918 DCI.CommitTargetLoweringOpt(TLO);
7923 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
7924 DAGCombinerInfo &DCI) const {
7925 SelectionDAG &DAG = DCI.DAG;
7926 switch (N->getOpcode()) {
7928 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
7929 case ISD::BUILD_VECTOR:
7930 return PerformBuildVectorCombine(N, DAG, DCI, Subtarget, *this);
7931 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
7934 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
7935 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
7937 case X86ISD::FOR: return PerformFORCombine(N, DAG);
7938 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
7939 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
7945 //===----------------------------------------------------------------------===//
7946 // X86 Inline Assembly Support
7947 //===----------------------------------------------------------------------===//
7949 /// getConstraintType - Given a constraint letter, return the type of
7950 /// constraint it is for this target.
7951 X86TargetLowering::ConstraintType
7952 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
7953 if (Constraint.size() == 1) {
7954 switch (Constraint[0]) {
7966 return C_RegisterClass;
7971 return TargetLowering::getConstraintType(Constraint);
7974 /// LowerXConstraint - try to replace an X constraint, which matches anything,
7975 /// with another that has more specific requirements based on the type of the
7976 /// corresponding operand.
7977 const char *X86TargetLowering::
7978 LowerXConstraint(MVT ConstraintVT) const {
7979 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
7980 // 'f' like normal targets.
7981 if (ConstraintVT.isFloatingPoint()) {
7982 if (Subtarget->hasSSE2())
7984 if (Subtarget->hasSSE1())
7988 return TargetLowering::LowerXConstraint(ConstraintVT);
7991 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7992 /// vector. If it is invalid, don't add anything to Ops.
7993 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7996 std::vector<SDValue>&Ops,
7997 SelectionDAG &DAG) const {
7998 SDValue Result(0, 0);
8000 switch (Constraint) {
8003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8004 if (C->getZExtValue() <= 31) {
8005 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8011 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8012 if (C->getZExtValue() <= 63) {
8013 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8019 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8020 if (C->getZExtValue() <= 255) {
8021 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8027 // Literal immediates are always ok.
8028 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
8029 Result = DAG.getTargetConstant(CST->getZExtValue(), Op.getValueType());
8033 // If we are in non-pic codegen mode, we allow the address of a global (with
8034 // an optional displacement) to be used with 'i'.
8035 GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
8038 // Match either (GA) or (GA+C)
8040 Offset = GA->getOffset();
8041 } else if (Op.getOpcode() == ISD::ADD) {
8042 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8043 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
8045 Offset = GA->getOffset()+C->getZExtValue();
8047 C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
8048 GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
8050 Offset = GA->getOffset()+C->getZExtValue();
8058 Op = LowerGlobalAddress(GA->getGlobal(), Offset, DAG);
8060 Op = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
8066 // Otherwise, not valid for this mode.
8071 if (Result.getNode()) {
8072 Ops.push_back(Result);
8075 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8079 std::vector<unsigned> X86TargetLowering::
8080 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8082 if (Constraint.size() == 1) {
8083 // FIXME: not handling fp-stack yet!
8084 switch (Constraint[0]) { // GCC X86 Constraint Letters
8085 default: break; // Unknown constraint letter
8086 case 'q': // Q_REGS (GENERAL_REGS in 64-bit mode)
8089 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
8090 else if (VT == MVT::i16)
8091 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
8092 else if (VT == MVT::i8)
8093 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
8094 else if (VT == MVT::i64)
8095 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
8100 return std::vector<unsigned>();
8103 std::pair<unsigned, const TargetRegisterClass*>
8104 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8106 // First, see if this is a constraint that directly corresponds to an LLVM
8108 if (Constraint.size() == 1) {
8109 // GCC Constraint Letters
8110 switch (Constraint[0]) {
8112 case 'r': // GENERAL_REGS
8113 case 'R': // LEGACY_REGS
8114 case 'l': // INDEX_REGS
8116 return std::make_pair(0U, X86::GR8RegisterClass);
8118 return std::make_pair(0U, X86::GR16RegisterClass);
8119 if (VT == MVT::i32 || !Subtarget->is64Bit())
8120 return std::make_pair(0U, X86::GR32RegisterClass);
8121 return std::make_pair(0U, X86::GR64RegisterClass);
8122 case 'f': // FP Stack registers.
8123 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
8124 // value to the correct fpstack register class.
8125 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
8126 return std::make_pair(0U, X86::RFP32RegisterClass);
8127 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
8128 return std::make_pair(0U, X86::RFP64RegisterClass);
8129 return std::make_pair(0U, X86::RFP80RegisterClass);
8130 case 'y': // MMX_REGS if MMX allowed.
8131 if (!Subtarget->hasMMX()) break;
8132 return std::make_pair(0U, X86::VR64RegisterClass);
8133 case 'Y': // SSE_REGS if SSE2 allowed
8134 if (!Subtarget->hasSSE2()) break;
8136 case 'x': // SSE_REGS if SSE1 allowed
8137 if (!Subtarget->hasSSE1()) break;
8139 switch (VT.getSimpleVT()) {
8141 // Scalar SSE types.
8144 return std::make_pair(0U, X86::FR32RegisterClass);
8147 return std::make_pair(0U, X86::FR64RegisterClass);
8155 return std::make_pair(0U, X86::VR128RegisterClass);
8161 // Use the default implementation in TargetLowering to convert the register
8162 // constraint into a member of a register class.
8163 std::pair<unsigned, const TargetRegisterClass*> Res;
8164 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8166 // Not found as a standard register?
8167 if (Res.second == 0) {
8168 // GCC calls "st(0)" just plain "st".
8169 if (StringsEqualNoCase("{st}", Constraint)) {
8170 Res.first = X86::ST0;
8171 Res.second = X86::RFP80RegisterClass;
8173 // 'A' means EAX + EDX.
8174 if (Constraint == "A") {
8175 Res.first = X86::EAX;
8176 Res.second = X86::GRADRegisterClass;
8181 // Otherwise, check to see if this is a register class of the wrong value
8182 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
8183 // turn into {ax},{dx}.
8184 if (Res.second->hasType(VT))
8185 return Res; // Correct type already, nothing to do.
8187 // All of the single-register GCC register classes map their values onto
8188 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
8189 // really want an 8-bit or 32-bit register, map to the appropriate register
8190 // class and return the appropriate register.
8191 if (Res.second == X86::GR16RegisterClass) {
8192 if (VT == MVT::i8) {
8193 unsigned DestReg = 0;
8194 switch (Res.first) {
8196 case X86::AX: DestReg = X86::AL; break;
8197 case X86::DX: DestReg = X86::DL; break;
8198 case X86::CX: DestReg = X86::CL; break;
8199 case X86::BX: DestReg = X86::BL; break;
8202 Res.first = DestReg;
8203 Res.second = Res.second = X86::GR8RegisterClass;
8205 } else if (VT == MVT::i32) {
8206 unsigned DestReg = 0;
8207 switch (Res.first) {
8209 case X86::AX: DestReg = X86::EAX; break;
8210 case X86::DX: DestReg = X86::EDX; break;
8211 case X86::CX: DestReg = X86::ECX; break;
8212 case X86::BX: DestReg = X86::EBX; break;
8213 case X86::SI: DestReg = X86::ESI; break;
8214 case X86::DI: DestReg = X86::EDI; break;
8215 case X86::BP: DestReg = X86::EBP; break;
8216 case X86::SP: DestReg = X86::ESP; break;
8219 Res.first = DestReg;
8220 Res.second = Res.second = X86::GR32RegisterClass;
8222 } else if (VT == MVT::i64) {
8223 unsigned DestReg = 0;
8224 switch (Res.first) {
8226 case X86::AX: DestReg = X86::RAX; break;
8227 case X86::DX: DestReg = X86::RDX; break;
8228 case X86::CX: DestReg = X86::RCX; break;
8229 case X86::BX: DestReg = X86::RBX; break;
8230 case X86::SI: DestReg = X86::RSI; break;
8231 case X86::DI: DestReg = X86::RDI; break;
8232 case X86::BP: DestReg = X86::RBP; break;
8233 case X86::SP: DestReg = X86::RSP; break;
8236 Res.first = DestReg;
8237 Res.second = Res.second = X86::GR64RegisterClass;
8240 } else if (Res.second == X86::FR32RegisterClass ||
8241 Res.second == X86::FR64RegisterClass ||
8242 Res.second == X86::VR128RegisterClass) {
8243 // Handle references to XMM physical registers that got mapped into the
8244 // wrong class. This can happen with constraints like {xmm0} where the
8245 // target independent register mapper will just pick the first match it can
8246 // find, ignoring the required type.
8248 Res.second = X86::FR32RegisterClass;
8249 else if (VT == MVT::f64)
8250 Res.second = X86::FR64RegisterClass;
8251 else if (X86::VR128RegisterClass->hasType(VT))
8252 Res.second = X86::VR128RegisterClass;
8258 //===----------------------------------------------------------------------===//
8259 // X86 Widen vector type
8260 //===----------------------------------------------------------------------===//
8262 /// getWidenVectorType: given a vector type, returns the type to widen
8263 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
8264 /// If there is no vector type that we want to widen to, returns MVT::Other
8265 /// When and where to widen is target dependent based on the cost of
8266 /// scalarizing vs using the wider vector type.
8268 MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
8269 assert(VT.isVector());
8270 if (isTypeLegal(VT))
8273 // TODO: In computeRegisterProperty, we can compute the list of legal vector
8274 // type based on element type. This would speed up our search (though
8275 // it may not be worth it since the size of the list is relatively
8277 MVT EltVT = VT.getVectorElementType();
8278 unsigned NElts = VT.getVectorNumElements();
8280 // On X86, it make sense to widen any vector wider than 1
8284 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
8285 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
8286 MVT SVT = (MVT::SimpleValueType)nVT;
8288 if (isTypeLegal(SVT) &&
8289 SVT.getVectorElementType() == EltVT &&
8290 SVT.getVectorNumElements() > NElts)