1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "X86InstrBuilder.h"
17 #include "X86ISelLowering.h"
18 #include "X86TargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/GlobalAlias.h"
23 #include "llvm/GlobalVariable.h"
24 #include "llvm/Function.h"
25 #include "llvm/Instructions.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/LLVMContext.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/VectorExtras.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/PseudoSourceValue.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Target/TargetLoweringObjectFile.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/SmallSet.h"
42 #include "llvm/ADT/StringExtras.h"
43 #include "llvm/Support/CommandLine.h"
44 #include "llvm/Support/raw_ostream.h"
48 DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX"));
50 // Forward declarations.
51 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
54 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
55 switch (TM.getSubtarget<X86Subtarget>().TargetType) {
56 default: llvm_unreachable("unknown subtarget type");
57 case X86Subtarget::isDarwin:
58 return new TargetLoweringObjectFileMachO();
59 case X86Subtarget::isELF:
60 return new TargetLoweringObjectFileELF();
61 case X86Subtarget::isMingw:
62 case X86Subtarget::isCygwin:
63 case X86Subtarget::isWindows:
64 return new TargetLoweringObjectFileCOFF();
69 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
70 : TargetLowering(TM, createTLOF(TM)) {
71 Subtarget = &TM.getSubtarget<X86Subtarget>();
72 X86ScalarSSEf64 = Subtarget->hasSSE2();
73 X86ScalarSSEf32 = Subtarget->hasSSE1();
74 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
76 RegInfo = TM.getRegisterInfo();
79 // Set up the TargetLowering object.
81 // X86 is weird, it always uses i8 for shift amounts and setcc results.
82 setShiftAmountType(MVT::i8);
83 setBooleanContents(ZeroOrOneBooleanContent);
84 setSchedulingPreference(SchedulingForRegPressure);
85 setStackPointerRegisterToSaveRestore(X86StackPtr);
87 if (Subtarget->isTargetDarwin()) {
88 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
89 setUseUnderscoreSetJmp(false);
90 setUseUnderscoreLongJmp(false);
91 } else if (Subtarget->isTargetMingw()) {
92 // MS runtime is weird: it exports _setjmp, but longjmp!
93 setUseUnderscoreSetJmp(true);
94 setUseUnderscoreLongJmp(false);
96 setUseUnderscoreSetJmp(true);
97 setUseUnderscoreLongJmp(true);
100 // Set up the register classes.
101 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
102 addRegisterClass(MVT::i16, X86::GR16RegisterClass);
103 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
104 if (Subtarget->is64Bit())
105 addRegisterClass(MVT::i64, X86::GR64RegisterClass);
107 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
109 // We don't accept any truncstore of integer registers.
110 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
111 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
112 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
113 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
114 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
115 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
117 // SETOEQ and SETUNE require checking two conditions.
118 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
119 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
120 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
121 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
122 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
123 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
125 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
127 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
128 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
129 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
131 if (Subtarget->is64Bit()) {
132 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
133 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
134 } else if (!UseSoftFloat) {
135 if (X86ScalarSSEf64) {
136 // We have an impenetrably clever algorithm for ui64->double only.
137 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
139 // We have an algorithm for SSE2, and we turn this into a 64-bit
140 // FILD for other targets.
141 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
144 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
146 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
147 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
150 // SSE has no i16 to fp conversion, only i32
151 if (X86ScalarSSEf32) {
152 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
153 // f32 and f64 cases are Legal, f80 case is not
154 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
156 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
157 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
160 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
161 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
164 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
165 // are Legal, f80 is custom lowered.
166 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
167 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
169 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
171 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
172 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
174 if (X86ScalarSSEf32) {
175 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
176 // f32 and f64 cases are Legal, f80 case is not
177 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
179 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
180 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
183 // Handle FP_TO_UINT by promoting the destination to a larger signed
185 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
186 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
187 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
189 if (Subtarget->is64Bit()) {
190 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
191 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
192 } else if (!UseSoftFloat) {
193 if (X86ScalarSSEf32 && !Subtarget->hasSSE3())
194 // Expand FP_TO_UINT into a select.
195 // FIXME: We would like to use a Custom expander here eventually to do
196 // the optimal thing for SSE vs. the default expansion in the legalizer.
197 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
199 // With SSE3 we can use fisttpll to convert to a signed i64; without
200 // SSE, we're stuck with a fistpll.
201 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
204 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
205 if (!X86ScalarSSEf64) {
206 setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
207 setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
210 // Scalar integer divide and remainder are lowered to use operations that
211 // produce two results, to match the available instructions. This exposes
212 // the two-result form to trivial CSE, which is able to combine x/y and x%y
213 // into a single instruction.
215 // Scalar integer multiply-high is also lowered to use two-result
216 // operations, to match the available instructions. However, plain multiply
217 // (low) operations are left as Legal, as there are single-result
218 // instructions for this in x86. Using the two-result multiply instructions
219 // when both high and low results are needed must be arranged by dagcombine.
220 setOperationAction(ISD::MULHS , MVT::i8 , Expand);
221 setOperationAction(ISD::MULHU , MVT::i8 , Expand);
222 setOperationAction(ISD::SDIV , MVT::i8 , Expand);
223 setOperationAction(ISD::UDIV , MVT::i8 , Expand);
224 setOperationAction(ISD::SREM , MVT::i8 , Expand);
225 setOperationAction(ISD::UREM , MVT::i8 , Expand);
226 setOperationAction(ISD::MULHS , MVT::i16 , Expand);
227 setOperationAction(ISD::MULHU , MVT::i16 , Expand);
228 setOperationAction(ISD::SDIV , MVT::i16 , Expand);
229 setOperationAction(ISD::UDIV , MVT::i16 , Expand);
230 setOperationAction(ISD::SREM , MVT::i16 , Expand);
231 setOperationAction(ISD::UREM , MVT::i16 , Expand);
232 setOperationAction(ISD::MULHS , MVT::i32 , Expand);
233 setOperationAction(ISD::MULHU , MVT::i32 , Expand);
234 setOperationAction(ISD::SDIV , MVT::i32 , Expand);
235 setOperationAction(ISD::UDIV , MVT::i32 , Expand);
236 setOperationAction(ISD::SREM , MVT::i32 , Expand);
237 setOperationAction(ISD::UREM , MVT::i32 , Expand);
238 setOperationAction(ISD::MULHS , MVT::i64 , Expand);
239 setOperationAction(ISD::MULHU , MVT::i64 , Expand);
240 setOperationAction(ISD::SDIV , MVT::i64 , Expand);
241 setOperationAction(ISD::UDIV , MVT::i64 , Expand);
242 setOperationAction(ISD::SREM , MVT::i64 , Expand);
243 setOperationAction(ISD::UREM , MVT::i64 , Expand);
245 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
246 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
247 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
248 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
249 if (Subtarget->is64Bit())
250 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
251 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
252 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
253 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
254 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
255 setOperationAction(ISD::FREM , MVT::f32 , Expand);
256 setOperationAction(ISD::FREM , MVT::f64 , Expand);
257 setOperationAction(ISD::FREM , MVT::f80 , Expand);
258 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
260 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
261 setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
262 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
263 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
264 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
265 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
266 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
267 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
268 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
269 if (Subtarget->is64Bit()) {
270 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
271 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
272 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
275 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
276 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
278 // These should be promoted to a larger select which is supported.
279 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
280 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
281 // X86 wants to expand cmov itself.
282 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
283 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
284 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
285 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
286 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
287 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
288 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
289 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
290 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
291 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
292 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
293 if (Subtarget->is64Bit()) {
294 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
295 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
297 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
300 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
301 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
302 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
303 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
304 if (Subtarget->is64Bit())
305 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
306 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
307 if (Subtarget->is64Bit()) {
308 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
309 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
310 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
311 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
313 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
314 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
315 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
316 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
317 if (Subtarget->is64Bit()) {
318 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
319 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
320 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
323 if (Subtarget->hasSSE1())
324 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
326 if (!Subtarget->hasSSE2())
327 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
329 // Expand certain atomics
330 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
331 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom);
332 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
333 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
335 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom);
336 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom);
337 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
338 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
340 if (!Subtarget->is64Bit()) {
341 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
342 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
343 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
344 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
345 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
346 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
347 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
350 // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion.
351 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
352 // FIXME - use subtarget debug flags
353 if (!Subtarget->isTargetDarwin() &&
354 !Subtarget->isTargetELF() &&
355 !Subtarget->isTargetCygMing()) {
356 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
357 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
360 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
361 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
362 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
363 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
364 if (Subtarget->is64Bit()) {
365 setExceptionPointerRegister(X86::RAX);
366 setExceptionSelectorRegister(X86::RDX);
368 setExceptionPointerRegister(X86::EAX);
369 setExceptionSelectorRegister(X86::EDX);
371 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
372 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
374 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
376 setOperationAction(ISD::TRAP, MVT::Other, Legal);
378 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
379 setOperationAction(ISD::VASTART , MVT::Other, Custom);
380 setOperationAction(ISD::VAEND , MVT::Other, Expand);
381 if (Subtarget->is64Bit()) {
382 setOperationAction(ISD::VAARG , MVT::Other, Custom);
383 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
385 setOperationAction(ISD::VAARG , MVT::Other, Expand);
386 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
389 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
390 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
391 if (Subtarget->is64Bit())
392 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
393 if (Subtarget->isTargetCygMing())
394 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
396 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
398 if (!UseSoftFloat && X86ScalarSSEf64) {
399 // f32 and f64 use SSE.
400 // Set up the FP register classes.
401 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
402 addRegisterClass(MVT::f64, X86::FR64RegisterClass);
404 // Use ANDPD to simulate FABS.
405 setOperationAction(ISD::FABS , MVT::f64, Custom);
406 setOperationAction(ISD::FABS , MVT::f32, Custom);
408 // Use XORP to simulate FNEG.
409 setOperationAction(ISD::FNEG , MVT::f64, Custom);
410 setOperationAction(ISD::FNEG , MVT::f32, Custom);
412 // Use ANDPD and ORPD to simulate FCOPYSIGN.
413 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
414 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
416 // We don't support sin/cos/fmod
417 setOperationAction(ISD::FSIN , MVT::f64, Expand);
418 setOperationAction(ISD::FCOS , MVT::f64, Expand);
419 setOperationAction(ISD::FSIN , MVT::f32, Expand);
420 setOperationAction(ISD::FCOS , MVT::f32, Expand);
422 // Expand FP immediates into loads from the stack, except for the special
424 addLegalFPImmediate(APFloat(+0.0)); // xorpd
425 addLegalFPImmediate(APFloat(+0.0f)); // xorps
426 } else if (!UseSoftFloat && X86ScalarSSEf32) {
427 // Use SSE for f32, x87 for f64.
428 // Set up the FP register classes.
429 addRegisterClass(MVT::f32, X86::FR32RegisterClass);
430 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
432 // Use ANDPS to simulate FABS.
433 setOperationAction(ISD::FABS , MVT::f32, Custom);
435 // Use XORP to simulate FNEG.
436 setOperationAction(ISD::FNEG , MVT::f32, Custom);
438 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
440 // Use ANDPS and ORPS to simulate FCOPYSIGN.
441 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
442 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
444 // We don't support sin/cos/fmod
445 setOperationAction(ISD::FSIN , MVT::f32, Expand);
446 setOperationAction(ISD::FCOS , MVT::f32, Expand);
448 // Special cases we handle for FP constants.
449 addLegalFPImmediate(APFloat(+0.0f)); // xorps
450 addLegalFPImmediate(APFloat(+0.0)); // FLD0
451 addLegalFPImmediate(APFloat(+1.0)); // FLD1
452 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
453 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
456 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
457 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
459 } else if (!UseSoftFloat) {
460 // f32 and f64 in x87.
461 // Set up the FP register classes.
462 addRegisterClass(MVT::f64, X86::RFP64RegisterClass);
463 addRegisterClass(MVT::f32, X86::RFP32RegisterClass);
465 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
466 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
467 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
468 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
471 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
472 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
474 addLegalFPImmediate(APFloat(+0.0)); // FLD0
475 addLegalFPImmediate(APFloat(+1.0)); // FLD1
476 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
477 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
478 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
479 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
480 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
481 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
484 // Long double always uses X87.
486 addRegisterClass(MVT::f80, X86::RFP80RegisterClass);
487 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
488 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
491 APFloat TmpFlt(+0.0);
492 TmpFlt.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
494 addLegalFPImmediate(TmpFlt); // FLD0
496 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
497 APFloat TmpFlt2(+1.0);
498 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
500 addLegalFPImmediate(TmpFlt2); // FLD1
501 TmpFlt2.changeSign();
502 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
506 setOperationAction(ISD::FSIN , MVT::f80 , Expand);
507 setOperationAction(ISD::FCOS , MVT::f80 , Expand);
511 // Always use a library call for pow.
512 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
513 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
514 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
516 setOperationAction(ISD::FLOG, MVT::f80, Expand);
517 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
518 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
519 setOperationAction(ISD::FEXP, MVT::f80, Expand);
520 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
522 // First set operation action for all vector types to either promote
523 // (for widening) or expand (for scalarization). Then we will selectively
524 // turn on ones that can be effectively codegen'd.
525 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
526 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
527 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand);
528 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand);
529 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand);
530 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand);
531 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand);
532 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand);
533 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand);
534 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand);
535 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand);
536 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand);
537 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand);
538 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand);
539 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand);
540 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand);
541 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand);
542 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand);
543 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand);
544 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand);
545 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand);
546 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand);
547 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand);
548 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand);
549 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand);
550 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand);
551 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
552 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand);
553 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand);
554 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand);
555 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand);
556 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand);
557 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand);
558 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand);
559 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand);
560 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand);
561 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand);
562 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand);
563 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand);
564 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand);
565 setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand);
566 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand);
567 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand);
568 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand);
569 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand);
570 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand);
571 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand);
572 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand);
573 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
574 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand);
577 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
578 // with -msoft-float, disable use of MMX as well.
579 if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) {
580 addRegisterClass(MVT::v8i8, X86::VR64RegisterClass);
581 addRegisterClass(MVT::v4i16, X86::VR64RegisterClass);
582 addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
583 addRegisterClass(MVT::v2f32, X86::VR64RegisterClass);
584 addRegisterClass(MVT::v1i64, X86::VR64RegisterClass);
586 setOperationAction(ISD::ADD, MVT::v8i8, Legal);
587 setOperationAction(ISD::ADD, MVT::v4i16, Legal);
588 setOperationAction(ISD::ADD, MVT::v2i32, Legal);
589 setOperationAction(ISD::ADD, MVT::v1i64, Legal);
591 setOperationAction(ISD::SUB, MVT::v8i8, Legal);
592 setOperationAction(ISD::SUB, MVT::v4i16, Legal);
593 setOperationAction(ISD::SUB, MVT::v2i32, Legal);
594 setOperationAction(ISD::SUB, MVT::v1i64, Legal);
596 setOperationAction(ISD::MULHS, MVT::v4i16, Legal);
597 setOperationAction(ISD::MUL, MVT::v4i16, Legal);
599 setOperationAction(ISD::AND, MVT::v8i8, Promote);
600 AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64);
601 setOperationAction(ISD::AND, MVT::v4i16, Promote);
602 AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64);
603 setOperationAction(ISD::AND, MVT::v2i32, Promote);
604 AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64);
605 setOperationAction(ISD::AND, MVT::v1i64, Legal);
607 setOperationAction(ISD::OR, MVT::v8i8, Promote);
608 AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64);
609 setOperationAction(ISD::OR, MVT::v4i16, Promote);
610 AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64);
611 setOperationAction(ISD::OR, MVT::v2i32, Promote);
612 AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64);
613 setOperationAction(ISD::OR, MVT::v1i64, Legal);
615 setOperationAction(ISD::XOR, MVT::v8i8, Promote);
616 AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64);
617 setOperationAction(ISD::XOR, MVT::v4i16, Promote);
618 AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64);
619 setOperationAction(ISD::XOR, MVT::v2i32, Promote);
620 AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64);
621 setOperationAction(ISD::XOR, MVT::v1i64, Legal);
623 setOperationAction(ISD::LOAD, MVT::v8i8, Promote);
624 AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64);
625 setOperationAction(ISD::LOAD, MVT::v4i16, Promote);
626 AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
627 setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
628 AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
629 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
630 AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
631 setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
633 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
634 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
635 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
636 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
637 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
639 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
640 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
641 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
642 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
644 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
645 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
646 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
647 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom);
649 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom);
651 setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand);
652 setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand);
653 setOperationAction(ISD::SELECT, MVT::v8i8, Promote);
654 setOperationAction(ISD::SELECT, MVT::v4i16, Promote);
655 setOperationAction(ISD::SELECT, MVT::v2i32, Promote);
656 setOperationAction(ISD::SELECT, MVT::v1i64, Custom);
657 setOperationAction(ISD::VSETCC, MVT::v8i8, Custom);
658 setOperationAction(ISD::VSETCC, MVT::v4i16, Custom);
659 setOperationAction(ISD::VSETCC, MVT::v2i32, Custom);
662 if (!UseSoftFloat && Subtarget->hasSSE1()) {
663 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass);
665 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
666 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
667 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
668 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
669 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
670 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
671 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
672 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
673 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
674 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
675 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
676 setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
679 if (!UseSoftFloat && Subtarget->hasSSE2()) {
680 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass);
682 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
683 // registers cannot be used even for integer operations.
684 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
685 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
686 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass);
687 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass);
689 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
690 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
691 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
692 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
693 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
694 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
695 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
696 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
697 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
698 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
699 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
700 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
701 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
702 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
703 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
704 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
706 setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
707 setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
708 setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
709 setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
711 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
712 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
713 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
714 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
715 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
717 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
718 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
719 MVT VT = (MVT::SimpleValueType)i;
720 // Do not attempt to custom lower non-power-of-2 vectors
721 if (!isPowerOf2_32(VT.getVectorNumElements()))
723 // Do not attempt to custom lower non-128-bit vectors
724 if (!VT.is128BitVector())
726 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
727 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
728 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
731 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
732 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
733 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
734 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
735 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
736 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
738 if (Subtarget->is64Bit()) {
739 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
740 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
743 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
744 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
745 MVT VT = (MVT::SimpleValueType)i;
747 // Do not attempt to promote non-128-bit vectors
748 if (!VT.is128BitVector()) {
751 setOperationAction(ISD::AND, VT, Promote);
752 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
753 setOperationAction(ISD::OR, VT, Promote);
754 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
755 setOperationAction(ISD::XOR, VT, Promote);
756 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
757 setOperationAction(ISD::LOAD, VT, Promote);
758 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
759 setOperationAction(ISD::SELECT, VT, Promote);
760 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
763 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
765 // Custom lower v2i64 and v2f64 selects.
766 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
767 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
768 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
769 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
771 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
772 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
773 if (!DisableMMX && Subtarget->hasMMX()) {
774 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
775 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
779 if (Subtarget->hasSSE41()) {
780 // FIXME: Do we need to handle scalar-to-vector here?
781 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
783 // i8 and i16 vectors are custom , because the source register and source
784 // source memory operand types are not the same width. f32 vectors are
785 // custom since the immediate controlling the insert encodes additional
787 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
788 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
789 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
790 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
792 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
793 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
794 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
795 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
797 if (Subtarget->is64Bit()) {
798 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal);
799 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
803 if (Subtarget->hasSSE42()) {
804 setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
807 if (!UseSoftFloat && Subtarget->hasAVX()) {
808 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass);
809 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass);
810 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass);
811 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass);
813 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
814 setOperationAction(ISD::LOAD, MVT::v8i32, Legal);
815 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
816 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
817 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
818 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
819 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
820 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
821 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
822 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
823 //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom);
824 //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom);
825 //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom);
826 //setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
827 //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom);
829 // Operations to consider commented out -v16i16 v32i8
830 //setOperationAction(ISD::ADD, MVT::v16i16, Legal);
831 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
832 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
833 //setOperationAction(ISD::SUB, MVT::v32i8, Legal);
834 //setOperationAction(ISD::SUB, MVT::v16i16, Legal);
835 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
836 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
837 //setOperationAction(ISD::MUL, MVT::v16i16, Legal);
838 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
839 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
840 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
841 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
842 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
843 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
845 setOperationAction(ISD::VSETCC, MVT::v4f64, Custom);
846 // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom);
847 // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom);
848 setOperationAction(ISD::VSETCC, MVT::v8i32, Custom);
850 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom);
851 // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom);
852 // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom);
853 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom);
854 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom);
856 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
857 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom);
858 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom);
859 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom);
860 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom);
861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom);
864 // Not sure we want to do this since there are no 256-bit integer
867 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
868 // This includes 256-bit vectors
869 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) {
870 MVT VT = (MVT::SimpleValueType)i;
872 // Do not attempt to custom lower non-power-of-2 vectors
873 if (!isPowerOf2_32(VT.getVectorNumElements()))
876 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
877 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
878 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
881 if (Subtarget->is64Bit()) {
882 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom);
883 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom);
888 // Not sure we want to do this since there are no 256-bit integer
891 // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64.
892 // Including 256-bit vectors
893 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) {
894 MVT VT = (MVT::SimpleValueType)i;
896 if (!VT.is256BitVector()) {
899 setOperationAction(ISD::AND, VT, Promote);
900 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
901 setOperationAction(ISD::OR, VT, Promote);
902 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
903 setOperationAction(ISD::XOR, VT, Promote);
904 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
905 setOperationAction(ISD::LOAD, VT, Promote);
906 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
907 setOperationAction(ISD::SELECT, VT, Promote);
908 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
911 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
915 // We want to custom lower some of our intrinsics.
916 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
918 // Add/Sub/Mul with overflow operations are custom lowered.
919 setOperationAction(ISD::SADDO, MVT::i32, Custom);
920 setOperationAction(ISD::SADDO, MVT::i64, Custom);
921 setOperationAction(ISD::UADDO, MVT::i32, Custom);
922 setOperationAction(ISD::UADDO, MVT::i64, Custom);
923 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
924 setOperationAction(ISD::SSUBO, MVT::i64, Custom);
925 setOperationAction(ISD::USUBO, MVT::i32, Custom);
926 setOperationAction(ISD::USUBO, MVT::i64, Custom);
927 setOperationAction(ISD::SMULO, MVT::i32, Custom);
928 setOperationAction(ISD::SMULO, MVT::i64, Custom);
930 if (!Subtarget->is64Bit()) {
931 // These libcalls are not available in 32-bit.
932 setLibcallName(RTLIB::SHL_I128, 0);
933 setLibcallName(RTLIB::SRL_I128, 0);
934 setLibcallName(RTLIB::SRA_I128, 0);
937 // We have target-specific dag combine patterns for the following nodes:
938 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
939 setTargetDAGCombine(ISD::BUILD_VECTOR);
940 setTargetDAGCombine(ISD::SELECT);
941 setTargetDAGCombine(ISD::SHL);
942 setTargetDAGCombine(ISD::SRA);
943 setTargetDAGCombine(ISD::SRL);
944 setTargetDAGCombine(ISD::STORE);
945 setTargetDAGCombine(ISD::MEMBARRIER);
946 if (Subtarget->is64Bit())
947 setTargetDAGCombine(ISD::MUL);
949 computeRegisterProperties();
951 // FIXME: These should be based on subtarget info. Plus, the values should
952 // be smaller when we are in optimizing for size mode.
953 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
954 maxStoresPerMemcpy = 16; // For @llvm.memcpy -> sequence of stores
955 maxStoresPerMemmove = 3; // For @llvm.memmove -> sequence of stores
956 allowUnalignedMemoryAccesses = true; // x86 supports it!
957 setPrefLoopAlignment(16);
958 benefitFromCodePlacementOpt = true;
962 MVT X86TargetLowering::getSetCCResultType(MVT VT) const {
967 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
968 /// the desired ByVal argument alignment.
969 static void getMaxByValAlign(const Type *Ty, unsigned &MaxAlign) {
972 if (const VectorType *VTy = dyn_cast<VectorType>(Ty)) {
973 if (VTy->getBitWidth() == 128)
975 } else if (const ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
976 unsigned EltAlign = 0;
977 getMaxByValAlign(ATy->getElementType(), EltAlign);
978 if (EltAlign > MaxAlign)
980 } else if (const StructType *STy = dyn_cast<StructType>(Ty)) {
981 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
982 unsigned EltAlign = 0;
983 getMaxByValAlign(STy->getElementType(i), EltAlign);
984 if (EltAlign > MaxAlign)
993 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
994 /// function arguments in the caller parameter area. For X86, aggregates
995 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
996 /// are at 4-byte boundaries.
997 unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const {
998 if (Subtarget->is64Bit()) {
999 // Max of 8 and alignment of type.
1000 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1007 if (Subtarget->hasSSE1())
1008 getMaxByValAlign(Ty, Align);
1012 /// getOptimalMemOpType - Returns the target specific optimal type for load
1013 /// and store operations as a result of memset, memcpy, and memmove
1014 /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for
1017 X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
1018 bool isSrcConst, bool isSrcStr,
1019 SelectionDAG &DAG) const {
1020 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like
1021 // linux. This is because the stack realignment code can't handle certain
1022 // cases like PR2962. This should be removed when PR2962 is fixed.
1023 const Function *F = DAG.getMachineFunction().getFunction();
1024 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
1025 if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) {
1026 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16)
1028 if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16)
1031 if (Subtarget->is64Bit() && Size >= 8)
1036 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1038 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1039 SelectionDAG &DAG) const {
1040 if (usesGlobalOffsetTable())
1041 return DAG.getGLOBAL_OFFSET_TABLE(getPointerTy());
1042 if (!Subtarget->is64Bit())
1043 // This doesn't have DebugLoc associated with it, but is not really the
1044 // same as a Register.
1045 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc::getUnknownLoc(),
1050 /// getFunctionAlignment - Return the Log2 alignment of this function.
1051 unsigned X86TargetLowering::getFunctionAlignment(const Function *F) const {
1052 return F->hasFnAttr(Attribute::OptimizeForSize) ? 1 : 4;
1055 //===----------------------------------------------------------------------===//
1056 // Return Value Calling Convention Implementation
1057 //===----------------------------------------------------------------------===//
1059 #include "X86GenCallingConv.inc"
1062 X86TargetLowering::LowerReturn(SDValue Chain,
1063 unsigned CallConv, bool isVarArg,
1064 const SmallVectorImpl<ISD::OutputArg> &Outs,
1065 DebugLoc dl, SelectionDAG &DAG) {
1067 SmallVector<CCValAssign, 16> RVLocs;
1068 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1069 RVLocs, *DAG.getContext());
1070 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1072 // If this is the first return lowered for this function, add the regs to the
1073 // liveout set for the function.
1074 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1075 for (unsigned i = 0; i != RVLocs.size(); ++i)
1076 if (RVLocs[i].isRegLoc())
1077 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1082 SmallVector<SDValue, 6> RetOps;
1083 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1084 // Operand #1 = Bytes To Pop
1085 RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16));
1087 // Copy the result values into the output registers.
1088 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1089 CCValAssign &VA = RVLocs[i];
1090 assert(VA.isRegLoc() && "Can only return in registers!");
1091 SDValue ValToCopy = Outs[i].Val;
1093 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1094 // the RET instruction and handled by the FP Stackifier.
1095 if (VA.getLocReg() == X86::ST0 ||
1096 VA.getLocReg() == X86::ST1) {
1097 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1098 // change the value to the FP stack register class.
1099 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1100 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1101 RetOps.push_back(ValToCopy);
1102 // Don't emit a copytoreg.
1106 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1107 // which is returned in RAX / RDX.
1108 if (Subtarget->is64Bit()) {
1109 MVT ValVT = ValToCopy.getValueType();
1110 if (ValVT.isVector() && ValVT.getSizeInBits() == 64) {
1111 ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy);
1112 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1)
1113 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy);
1117 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1118 Flag = Chain.getValue(1);
1121 // The x86-64 ABI for returning structs by value requires that we copy
1122 // the sret argument into %rax for the return. We saved the argument into
1123 // a virtual register in the entry block, so now we copy the value out
1125 if (Subtarget->is64Bit() &&
1126 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
1127 MachineFunction &MF = DAG.getMachineFunction();
1128 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1129 unsigned Reg = FuncInfo->getSRetReturnReg();
1131 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1132 FuncInfo->setSRetReturnReg(Reg);
1134 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1136 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag);
1137 Flag = Chain.getValue(1);
1140 RetOps[0] = Chain; // Update chain.
1142 // Add the flag if we have it.
1144 RetOps.push_back(Flag);
1146 return DAG.getNode(X86ISD::RET_FLAG, dl,
1147 MVT::Other, &RetOps[0], RetOps.size());
1150 /// LowerCallResult - Lower the result values of a call into the
1151 /// appropriate copies out of appropriate physical registers.
1154 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1155 unsigned CallConv, bool isVarArg,
1156 const SmallVectorImpl<ISD::InputArg> &Ins,
1157 DebugLoc dl, SelectionDAG &DAG,
1158 SmallVectorImpl<SDValue> &InVals) {
1160 // Assign locations to each value returned by this call.
1161 SmallVector<CCValAssign, 16> RVLocs;
1162 bool Is64Bit = Subtarget->is64Bit();
1163 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1164 RVLocs, *DAG.getContext());
1165 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1167 // Copy all of the result registers out of their specified physreg.
1168 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1169 CCValAssign &VA = RVLocs[i];
1170 MVT CopyVT = VA.getValVT();
1172 // If this is x86-64, and we disabled SSE, we can't return FP values
1173 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1174 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1175 llvm_report_error("SSE register return with SSE disabled");
1178 // If this is a call to a function that returns an fp value on the floating
1179 // point stack, but where we prefer to use the value in xmm registers, copy
1180 // it out as F80 and use a truncate to move it from fp stack reg to xmm reg.
1181 if ((VA.getLocReg() == X86::ST0 ||
1182 VA.getLocReg() == X86::ST1) &&
1183 isScalarFPTypeInSSEReg(VA.getValVT())) {
1188 if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) {
1189 // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64.
1190 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1191 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1192 MVT::v2i64, InFlag).getValue(1);
1193 Val = Chain.getValue(0);
1194 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1195 Val, DAG.getConstant(0, MVT::i64));
1197 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1198 MVT::i64, InFlag).getValue(1);
1199 Val = Chain.getValue(0);
1201 Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val);
1203 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1204 CopyVT, InFlag).getValue(1);
1205 Val = Chain.getValue(0);
1207 InFlag = Chain.getValue(2);
1209 if (CopyVT != VA.getValVT()) {
1210 // Round the F80 the right size, which also moves to the appropriate xmm
1212 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1213 // This truncation won't change the value.
1214 DAG.getIntPtrConstant(1));
1217 InVals.push_back(Val);
1224 //===----------------------------------------------------------------------===//
1225 // C & StdCall & Fast Calling Convention implementation
1226 //===----------------------------------------------------------------------===//
1227 // StdCall calling convention seems to be standard for many Windows' API
1228 // routines and around. It differs from C calling convention just a little:
1229 // callee should clean up the stack, not caller. Symbols should be also
1230 // decorated in some fancy way :) It doesn't support any vector arguments.
1231 // For info on fast calling convention see Fast Calling Convention (tail call)
1232 // implementation LowerX86_32FastCCCallTo.
1234 /// CallIsStructReturn - Determines whether a call uses struct return
1236 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1240 return Outs[0].Flags.isSRet();
1243 /// ArgsAreStructReturn - Determines whether a function uses struct
1244 /// return semantics.
1246 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1250 return Ins[0].Flags.isSRet();
1253 /// IsCalleePop - Determines whether the callee is required to pop its
1254 /// own arguments. Callee pop is necessary to support tail calls.
1255 bool X86TargetLowering::IsCalleePop(bool IsVarArg, unsigned CallingConv) {
1259 switch (CallingConv) {
1262 case CallingConv::X86_StdCall:
1263 return !Subtarget->is64Bit();
1264 case CallingConv::X86_FastCall:
1265 return !Subtarget->is64Bit();
1266 case CallingConv::Fast:
1267 return PerformTailCallOpt;
1271 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1272 /// given CallingConvention value.
1273 CCAssignFn *X86TargetLowering::CCAssignFnForNode(unsigned CC) const {
1274 if (Subtarget->is64Bit()) {
1275 if (Subtarget->isTargetWin64())
1276 return CC_X86_Win64_C;
1281 if (CC == CallingConv::X86_FastCall)
1282 return CC_X86_32_FastCall;
1283 else if (CC == CallingConv::Fast)
1284 return CC_X86_32_FastCC;
1289 /// NameDecorationForCallConv - Selects the appropriate decoration to
1290 /// apply to a MachineFunction containing a given calling convention.
1292 X86TargetLowering::NameDecorationForCallConv(unsigned CallConv) {
1293 if (CallConv == CallingConv::X86_FastCall)
1295 else if (CallConv == CallingConv::X86_StdCall)
1301 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1302 /// by "Src" to address "Dst" with size and alignment information specified by
1303 /// the specific parameter attribute. The copy will be passed as a byval
1304 /// function parameter.
1306 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1307 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1309 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1310 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1311 /*AlwaysInline=*/true, NULL, 0, NULL, 0);
1315 X86TargetLowering::LowerMemArgument(SDValue Chain,
1317 const SmallVectorImpl<ISD::InputArg> &Ins,
1318 DebugLoc dl, SelectionDAG &DAG,
1319 const CCValAssign &VA,
1320 MachineFrameInfo *MFI,
1323 // Create the nodes corresponding to a load from this parameter slot.
1324 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1325 bool AlwaysUseMutable = (CallConv==CallingConv::Fast) && PerformTailCallOpt;
1326 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1328 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1329 // changed with more analysis.
1330 // In case of tail call optimization mark all arguments mutable. Since they
1331 // could be overwritten by lowering of arguments in case of a tail call.
1332 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
1333 VA.getLocMemOffset(), isImmutable);
1334 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1335 if (Flags.isByVal())
1337 return DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1338 PseudoSourceValue::getFixedStack(FI), 0);
1342 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1345 const SmallVectorImpl<ISD::InputArg> &Ins,
1348 SmallVectorImpl<SDValue> &InVals) {
1350 MachineFunction &MF = DAG.getMachineFunction();
1351 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1353 const Function* Fn = MF.getFunction();
1354 if (Fn->hasExternalLinkage() &&
1355 Subtarget->isTargetCygMing() &&
1356 Fn->getName() == "main")
1357 FuncInfo->setForceFramePointer(true);
1359 // Decorate the function name.
1360 FuncInfo->setDecorationStyle(NameDecorationForCallConv(CallConv));
1362 MachineFrameInfo *MFI = MF.getFrameInfo();
1363 bool Is64Bit = Subtarget->is64Bit();
1364 bool IsWin64 = Subtarget->isTargetWin64();
1366 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1367 "Var args not supported with calling convention fastcc");
1369 // Assign locations to all of the incoming arguments.
1370 SmallVector<CCValAssign, 16> ArgLocs;
1371 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1372 ArgLocs, *DAG.getContext());
1373 CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForNode(CallConv));
1375 unsigned LastVal = ~0U;
1377 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1378 CCValAssign &VA = ArgLocs[i];
1379 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1381 assert(VA.getValNo() != LastVal &&
1382 "Don't support value assigned to multiple locs yet");
1383 LastVal = VA.getValNo();
1385 if (VA.isRegLoc()) {
1386 MVT RegVT = VA.getLocVT();
1387 TargetRegisterClass *RC = NULL;
1388 if (RegVT == MVT::i32)
1389 RC = X86::GR32RegisterClass;
1390 else if (Is64Bit && RegVT == MVT::i64)
1391 RC = X86::GR64RegisterClass;
1392 else if (RegVT == MVT::f32)
1393 RC = X86::FR32RegisterClass;
1394 else if (RegVT == MVT::f64)
1395 RC = X86::FR64RegisterClass;
1396 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128)
1397 RC = X86::VR128RegisterClass;
1398 else if (RegVT.isVector() && RegVT.getSizeInBits() == 64)
1399 RC = X86::VR64RegisterClass;
1401 llvm_unreachable("Unknown argument type!");
1403 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1404 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1406 // If this is an 8 or 16-bit value, it is really passed promoted to 32
1407 // bits. Insert an assert[sz]ext to capture this, then truncate to the
1409 if (VA.getLocInfo() == CCValAssign::SExt)
1410 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1411 DAG.getValueType(VA.getValVT()));
1412 else if (VA.getLocInfo() == CCValAssign::ZExt)
1413 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1414 DAG.getValueType(VA.getValVT()));
1415 else if (VA.getLocInfo() == CCValAssign::BCvt)
1416 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1418 if (VA.isExtInLoc()) {
1419 // Handle MMX values passed in XMM regs.
1420 if (RegVT.isVector()) {
1421 ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64,
1422 ArgValue, DAG.getConstant(0, MVT::i64));
1423 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1425 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1428 assert(VA.isMemLoc());
1429 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
1432 // If value is passed via pointer - do a load.
1433 if (VA.getLocInfo() == CCValAssign::Indirect)
1434 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, NULL, 0);
1436 InVals.push_back(ArgValue);
1439 // The x86-64 ABI for returning structs by value requires that we copy
1440 // the sret argument into %rax for the return. Save the argument into
1441 // a virtual register so that we can access it from the return points.
1442 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) {
1443 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1444 unsigned Reg = FuncInfo->getSRetReturnReg();
1446 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
1447 FuncInfo->setSRetReturnReg(Reg);
1449 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
1450 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
1453 unsigned StackSize = CCInfo.getNextStackOffset();
1454 // align stack specially for tail calls
1455 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1456 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
1458 // If the function takes variable number of arguments, make a frame index for
1459 // the start of the first vararg value... for expansion of llvm.va_start.
1461 if (Is64Bit || CallConv != CallingConv::X86_FastCall) {
1462 VarArgsFrameIndex = MFI->CreateFixedObject(1, StackSize);
1465 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
1467 // FIXME: We should really autogenerate these arrays
1468 static const unsigned GPR64ArgRegsWin64[] = {
1469 X86::RCX, X86::RDX, X86::R8, X86::R9
1471 static const unsigned XMMArgRegsWin64[] = {
1472 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3
1474 static const unsigned GPR64ArgRegs64Bit[] = {
1475 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
1477 static const unsigned XMMArgRegs64Bit[] = {
1478 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1479 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1481 const unsigned *GPR64ArgRegs, *XMMArgRegs;
1484 TotalNumIntRegs = 4; TotalNumXMMRegs = 4;
1485 GPR64ArgRegs = GPR64ArgRegsWin64;
1486 XMMArgRegs = XMMArgRegsWin64;
1488 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
1489 GPR64ArgRegs = GPR64ArgRegs64Bit;
1490 XMMArgRegs = XMMArgRegs64Bit;
1492 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
1494 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs,
1497 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat);
1498 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
1499 "SSE register cannot be used when SSE is disabled!");
1500 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) &&
1501 "SSE register cannot be used when SSE is disabled!");
1502 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
1503 // Kernel mode asks for SSE to be disabled, so don't push them
1505 TotalNumXMMRegs = 0;
1507 // For X86-64, if there are vararg parameters that are passed via
1508 // registers, then we must store them to their spots on the stack so they
1509 // may be loaded by deferencing the result of va_next.
1510 VarArgsGPOffset = NumIntRegs * 8;
1511 VarArgsFPOffset = TotalNumIntRegs * 8 + NumXMMRegs * 16;
1512 RegSaveFrameIndex = MFI->CreateStackObject(TotalNumIntRegs * 8 +
1513 TotalNumXMMRegs * 16, 16);
1515 // Store the integer parameter registers.
1516 SmallVector<SDValue, 8> MemOps;
1517 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
1518 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1519 DAG.getIntPtrConstant(VarArgsGPOffset));
1520 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
1521 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
1522 X86::GR64RegisterClass);
1523 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1525 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1526 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1527 MemOps.push_back(Store);
1528 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1529 DAG.getIntPtrConstant(8));
1532 // Now store the XMM (fp + vector) parameter registers.
1533 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
1534 DAG.getIntPtrConstant(VarArgsFPOffset));
1535 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
1536 unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs],
1537 X86::VR128RegisterClass);
1538 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
1540 DAG.getStore(Val.getValue(1), dl, Val, FIN,
1541 PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0);
1542 MemOps.push_back(Store);
1543 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1544 DAG.getIntPtrConstant(16));
1546 if (!MemOps.empty())
1547 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1548 &MemOps[0], MemOps.size());
1552 // Some CCs need callee pop.
1553 if (IsCalleePop(isVarArg, CallConv)) {
1554 BytesToPopOnReturn = StackSize; // Callee pops everything.
1555 BytesCallerReserves = 0;
1557 BytesToPopOnReturn = 0; // Callee pops nothing.
1558 // If this is an sret function, the return should pop the hidden pointer.
1559 if (!Is64Bit && CallConv != CallingConv::Fast && ArgsAreStructReturn(Ins))
1560 BytesToPopOnReturn = 4;
1561 BytesCallerReserves = StackSize;
1565 RegSaveFrameIndex = 0xAAAAAAA; // RegSaveFrameIndex is X86-64 only.
1566 if (CallConv == CallingConv::X86_FastCall)
1567 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
1570 FuncInfo->setBytesToPopOnReturn(BytesToPopOnReturn);
1576 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
1577 SDValue StackPtr, SDValue Arg,
1578 DebugLoc dl, SelectionDAG &DAG,
1579 const CCValAssign &VA,
1580 ISD::ArgFlagsTy Flags) {
1581 const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0);
1582 unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset();
1583 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1584 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1585 if (Flags.isByVal()) {
1586 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1588 return DAG.getStore(Chain, dl, Arg, PtrOff,
1589 PseudoSourceValue::getStack(), LocMemOffset);
1592 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
1593 /// optimization is performed and it is required.
1595 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
1596 SDValue &OutRetAddr,
1602 if (!IsTailCall || FPDiff==0) return Chain;
1604 // Adjust the Return address stack slot.
1605 MVT VT = getPointerTy();
1606 OutRetAddr = getReturnAddressFrameIndex(DAG);
1608 // Load the "old" Return address.
1609 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, NULL, 0);
1610 return SDValue(OutRetAddr.getNode(), 1);
1613 /// EmitTailCallStoreRetAddr - Emit a store of the return adress if tail call
1614 /// optimization is performed and it is required (FPDiff!=0).
1616 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
1617 SDValue Chain, SDValue RetAddrFrIdx,
1618 bool Is64Bit, int FPDiff, DebugLoc dl) {
1619 // Store the return address to the appropriate stack slot.
1620 if (!FPDiff) return Chain;
1621 // Calculate the new stack slot for the return address.
1622 int SlotSize = Is64Bit ? 8 : 4;
1623 int NewReturnAddrFI =
1624 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize);
1625 MVT VT = Is64Bit ? MVT::i64 : MVT::i32;
1626 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT);
1627 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
1628 PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0);
1633 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1634 unsigned CallConv, bool isVarArg, bool isTailCall,
1635 const SmallVectorImpl<ISD::OutputArg> &Outs,
1636 const SmallVectorImpl<ISD::InputArg> &Ins,
1637 DebugLoc dl, SelectionDAG &DAG,
1638 SmallVectorImpl<SDValue> &InVals) {
1640 MachineFunction &MF = DAG.getMachineFunction();
1641 bool Is64Bit = Subtarget->is64Bit();
1642 bool IsStructRet = CallIsStructReturn(Outs);
1644 assert((!isTailCall ||
1645 (CallConv == CallingConv::Fast && PerformTailCallOpt)) &&
1646 "IsEligibleForTailCallOptimization missed a case!");
1647 assert(!(isVarArg && CallConv == CallingConv::Fast) &&
1648 "Var args not supported with calling convention fastcc");
1650 // Analyze operands of the call, assigning locations to each operand.
1651 SmallVector<CCValAssign, 16> ArgLocs;
1652 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1653 ArgLocs, *DAG.getContext());
1654 CCInfo.AnalyzeCallOperands(Outs, CCAssignFnForNode(CallConv));
1656 // Get a count of how many bytes are to be pushed on the stack.
1657 unsigned NumBytes = CCInfo.getNextStackOffset();
1658 if (PerformTailCallOpt && CallConv == CallingConv::Fast)
1659 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
1663 // Lower arguments at fp - stackoffset + fpdiff.
1664 unsigned NumBytesCallerPushed =
1665 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn();
1666 FPDiff = NumBytesCallerPushed - NumBytes;
1668 // Set the delta of movement of the returnaddr stackslot.
1669 // But only set if delta is greater than previous delta.
1670 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta()))
1671 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff);
1674 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1676 SDValue RetAddrFrIdx;
1677 // Load return adress for tail calls.
1678 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, Is64Bit,
1681 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1682 SmallVector<SDValue, 8> MemOpChains;
1685 // Walk the register/memloc assignments, inserting copies/loads. In the case
1686 // of tail call optimization arguments are handle later.
1687 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1688 CCValAssign &VA = ArgLocs[i];
1689 MVT RegVT = VA.getLocVT();
1690 SDValue Arg = Outs[i].Val;
1691 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1692 bool isByVal = Flags.isByVal();
1694 // Promote the value if needed.
1695 switch (VA.getLocInfo()) {
1696 default: llvm_unreachable("Unknown loc info!");
1697 case CCValAssign::Full: break;
1698 case CCValAssign::SExt:
1699 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
1701 case CCValAssign::ZExt:
1702 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
1704 case CCValAssign::AExt:
1705 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) {
1706 // Special case: passing MMX values in XMM registers.
1707 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg);
1708 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
1709 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
1711 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
1713 case CCValAssign::BCvt:
1714 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
1716 case CCValAssign::Indirect: {
1717 // Store the argument.
1718 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1719 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1720 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
1721 PseudoSourceValue::getFixedStack(FI), 0);
1727 if (VA.isRegLoc()) {
1728 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1730 if (!isTailCall || (isTailCall && isByVal)) {
1731 assert(VA.isMemLoc());
1732 if (StackPtr.getNode() == 0)
1733 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy());
1735 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1736 dl, DAG, VA, Flags));
1741 if (!MemOpChains.empty())
1742 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1743 &MemOpChains[0], MemOpChains.size());
1745 // Build a sequence of copy-to-reg nodes chained together with token chain
1746 // and flag operands which copy the outgoing args into registers.
1748 // Tail call byval lowering might overwrite argument registers so in case of
1749 // tail call optimization the copies to registers are lowered later.
1751 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1752 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1753 RegsToPass[i].second, InFlag);
1754 InFlag = Chain.getValue(1);
1758 if (Subtarget->isPICStyleGOT()) {
1759 // ELF / PIC requires GOT in the EBX register before function calls via PLT
1762 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX,
1763 DAG.getNode(X86ISD::GlobalBaseReg,
1764 DebugLoc::getUnknownLoc(),
1767 InFlag = Chain.getValue(1);
1769 // If we are tail calling and generating PIC/GOT style code load the
1770 // address of the callee into ECX. The value in ecx is used as target of
1771 // the tail jump. This is done to circumvent the ebx/callee-saved problem
1772 // for tail calls on PIC/GOT architectures. Normally we would just put the
1773 // address of GOT into ebx and then call target@PLT. But for tail calls
1774 // ebx would be restored (since ebx is callee saved) before jumping to the
1777 // Note: The actual moving to ECX is done further down.
1778 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
1779 if (G && !G->getGlobal()->hasHiddenVisibility() &&
1780 !G->getGlobal()->hasProtectedVisibility())
1781 Callee = LowerGlobalAddress(Callee, DAG);
1782 else if (isa<ExternalSymbolSDNode>(Callee))
1783 Callee = LowerExternalSymbol(Callee, DAG);
1787 if (Is64Bit && isVarArg) {
1788 // From AMD64 ABI document:
1789 // For calls that may call functions that use varargs or stdargs
1790 // (prototype-less calls or calls to functions containing ellipsis (...) in
1791 // the declaration) %al is used as hidden argument to specify the number
1792 // of SSE registers used. The contents of %al do not need to match exactly
1793 // the number of registers, but must be an ubound on the number of SSE
1794 // registers used and is in the range 0 - 8 inclusive.
1796 // FIXME: Verify this on Win64
1797 // Count the number of XMM registers allocated.
1798 static const unsigned XMMArgRegs[] = {
1799 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
1800 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
1802 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
1803 assert((Subtarget->hasSSE1() || !NumXMMRegs)
1804 && "SSE registers cannot be used when SSE is disabled");
1806 Chain = DAG.getCopyToReg(Chain, dl, X86::AL,
1807 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag);
1808 InFlag = Chain.getValue(1);
1812 // For tail calls lower the arguments to the 'real' stack slot.
1814 // Force all the incoming stack arguments to be loaded from the stack
1815 // before any new outgoing arguments are stored to the stack, because the
1816 // outgoing stack slots may alias the incoming argument stack slots, and
1817 // the alias isn't otherwise explicit. This is slightly more conservative
1818 // than necessary, because it means that each store effectively depends
1819 // on every argument instead of just those arguments it would clobber.
1820 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
1822 SmallVector<SDValue, 8> MemOpChains2;
1825 // Do not flag preceeding copytoreg stuff together with the following stuff.
1827 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1828 CCValAssign &VA = ArgLocs[i];
1829 if (!VA.isRegLoc()) {
1830 assert(VA.isMemLoc());
1831 SDValue Arg = Outs[i].Val;
1832 ISD::ArgFlagsTy Flags = Outs[i].Flags;
1833 // Create frame index.
1834 int32_t Offset = VA.getLocMemOffset()+FPDiff;
1835 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
1836 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
1837 FIN = DAG.getFrameIndex(FI, getPointerTy());
1839 if (Flags.isByVal()) {
1840 // Copy relative to framepointer.
1841 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
1842 if (StackPtr.getNode() == 0)
1843 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr,
1845 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
1847 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
1851 // Store relative to framepointer.
1852 MemOpChains2.push_back(
1853 DAG.getStore(ArgChain, dl, Arg, FIN,
1854 PseudoSourceValue::getFixedStack(FI), 0));
1859 if (!MemOpChains2.empty())
1860 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1861 &MemOpChains2[0], MemOpChains2.size());
1863 // Copy arguments to their registers.
1864 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1865 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1866 RegsToPass[i].second, InFlag);
1867 InFlag = Chain.getValue(1);
1871 // Store the return address to the appropriate stack slot.
1872 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit,
1876 // If the callee is a GlobalAddress node (quite common, every direct call is)
1877 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1878 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1879 // We should use extra load for direct calls to dllimported functions in
1881 GlobalValue *GV = G->getGlobal();
1882 if (!GV->hasDLLImportLinkage()) {
1883 unsigned char OpFlags = 0;
1885 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
1886 // external symbols most go through the PLT in PIC mode. If the symbol
1887 // has hidden or protected visibility, or if it is static or local, then
1888 // we don't need to use the PLT - we can directly call it.
1889 if (Subtarget->isTargetELF() &&
1890 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1891 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
1892 OpFlags = X86II::MO_PLT;
1893 } else if (Subtarget->isPICStyleStubAny() &&
1894 (GV->isDeclaration() || GV->isWeakForLinker()) &&
1895 Subtarget->getDarwinVers() < 9) {
1896 // PC-relative references to external symbols should go through $stub,
1897 // unless we're building with the leopard linker or later, which
1898 // automatically synthesizes these stubs.
1899 OpFlags = X86II::MO_DARWIN_STUB;
1902 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy(),
1903 G->getOffset(), OpFlags);
1905 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1906 unsigned char OpFlags = 0;
1908 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to external
1909 // symbols should go through the PLT.
1910 if (Subtarget->isTargetELF() &&
1911 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1912 OpFlags = X86II::MO_PLT;
1913 } else if (Subtarget->isPICStyleStubAny() &&
1914 Subtarget->getDarwinVers() < 9) {
1915 // PC-relative references to external symbols should go through $stub,
1916 // unless we're building with the leopard linker or later, which
1917 // automatically synthesizes these stubs.
1918 OpFlags = X86II::MO_DARWIN_STUB;
1921 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
1923 } else if (isTailCall) {
1924 unsigned Opc = Is64Bit ? X86::R11 : X86::EAX;
1926 Chain = DAG.getCopyToReg(Chain, dl,
1927 DAG.getRegister(Opc, getPointerTy()),
1929 Callee = DAG.getRegister(Opc, getPointerTy());
1930 // Add register as live out.
1931 MF.getRegInfo().addLiveOut(Opc);
1934 // Returns a chain & a flag for retval copy to use.
1935 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1936 SmallVector<SDValue, 8> Ops;
1939 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1940 DAG.getIntPtrConstant(0, true), InFlag);
1941 InFlag = Chain.getValue(1);
1944 Ops.push_back(Chain);
1945 Ops.push_back(Callee);
1948 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
1950 // Add argument registers to the end of the list so that they are known live
1952 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1953 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1954 RegsToPass[i].second.getValueType()));
1956 // Add an implicit use GOT pointer in EBX.
1957 if (!isTailCall && Subtarget->isPICStyleGOT())
1958 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy()));
1960 // Add an implicit use of AL for x86 vararg functions.
1961 if (Is64Bit && isVarArg)
1962 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8));
1964 if (InFlag.getNode())
1965 Ops.push_back(InFlag);
1968 // If this is the first return lowered for this function, add the regs
1969 // to the liveout set for the function.
1970 if (MF.getRegInfo().liveout_empty()) {
1971 SmallVector<CCValAssign, 16> RVLocs;
1972 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1974 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1975 for (unsigned i = 0; i != RVLocs.size(); ++i)
1976 if (RVLocs[i].isRegLoc())
1977 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1980 assert(((Callee.getOpcode() == ISD::Register &&
1981 (cast<RegisterSDNode>(Callee)->getReg() == X86::EAX ||
1982 cast<RegisterSDNode>(Callee)->getReg() == X86::R9)) ||
1983 Callee.getOpcode() == ISD::TargetExternalSymbol ||
1984 Callee.getOpcode() == ISD::TargetGlobalAddress) &&
1985 "Expecting an global address, external symbol, or register");
1987 return DAG.getNode(X86ISD::TC_RETURN, dl,
1988 NodeTys, &Ops[0], Ops.size());
1991 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
1992 InFlag = Chain.getValue(1);
1994 // Create the CALLSEQ_END node.
1995 unsigned NumBytesForCalleeToPush;
1996 if (IsCalleePop(isVarArg, CallConv))
1997 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
1998 else if (!Is64Bit && CallConv != CallingConv::Fast && IsStructRet)
1999 // If this is is a call to a struct-return function, the callee
2000 // pops the hidden struct pointer, so we have to push it back.
2001 // This is common for Darwin/X86, Linux & Mingw32 targets.
2002 NumBytesForCalleeToPush = 4;
2004 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2006 // Returns a flag for retval copy to use.
2007 Chain = DAG.getCALLSEQ_END(Chain,
2008 DAG.getIntPtrConstant(NumBytes, true),
2009 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2012 InFlag = Chain.getValue(1);
2014 // Handle result values, copying them out of physregs into vregs that we
2016 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2017 Ins, dl, DAG, InVals);
2021 //===----------------------------------------------------------------------===//
2022 // Fast Calling Convention (tail call) implementation
2023 //===----------------------------------------------------------------------===//
2025 // Like std call, callee cleans arguments, convention except that ECX is
2026 // reserved for storing the tail called function address. Only 2 registers are
2027 // free for argument passing (inreg). Tail call optimization is performed
2029 // * tailcallopt is enabled
2030 // * caller/callee are fastcc
2031 // On X86_64 architecture with GOT-style position independent code only local
2032 // (within module) calls are supported at the moment.
2033 // To keep the stack aligned according to platform abi the function
2034 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2035 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2036 // If a tail called function callee has more arguments than the caller the
2037 // caller needs to make sure that there is room to move the RETADDR to. This is
2038 // achieved by reserving an area the size of the argument delta right after the
2039 // original REtADDR, but before the saved framepointer or the spilled registers
2040 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2052 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2053 /// for a 16 byte align requirement.
2054 unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2055 SelectionDAG& DAG) {
2056 MachineFunction &MF = DAG.getMachineFunction();
2057 const TargetMachine &TM = MF.getTarget();
2058 const TargetFrameInfo &TFI = *TM.getFrameInfo();
2059 unsigned StackAlignment = TFI.getStackAlignment();
2060 uint64_t AlignMask = StackAlignment - 1;
2061 int64_t Offset = StackSize;
2062 uint64_t SlotSize = TD->getPointerSize();
2063 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2064 // Number smaller than 12 so just add the difference.
2065 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2067 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2068 Offset = ((~AlignMask) & Offset) + StackAlignment +
2069 (StackAlignment-SlotSize);
2074 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2075 /// for tail call optimization. Targets which want to do tail call
2076 /// optimization should implement this function.
2078 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2081 const SmallVectorImpl<ISD::InputArg> &Ins,
2082 SelectionDAG& DAG) const {
2083 MachineFunction &MF = DAG.getMachineFunction();
2084 unsigned CallerCC = MF.getFunction()->getCallingConv();
2085 return CalleeCC == CallingConv::Fast && CallerCC == CalleeCC;
2089 X86TargetLowering::createFastISel(MachineFunction &mf,
2090 MachineModuleInfo *mmo,
2092 DenseMap<const Value *, unsigned> &vm,
2093 DenseMap<const BasicBlock *,
2094 MachineBasicBlock *> &bm,
2095 DenseMap<const AllocaInst *, int> &am
2097 , SmallSet<Instruction*, 8> &cil
2100 return X86::createFastISel(mf, mmo, dw, vm, bm, am
2108 //===----------------------------------------------------------------------===//
2109 // Other Lowering Hooks
2110 //===----------------------------------------------------------------------===//
2113 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
2114 MachineFunction &MF = DAG.getMachineFunction();
2115 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2116 int ReturnAddrIndex = FuncInfo->getRAIndex();
2118 if (ReturnAddrIndex == 0) {
2119 // Set up a frame object for the return address.
2120 uint64_t SlotSize = TD->getPointerSize();
2121 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize);
2122 FuncInfo->setRAIndex(ReturnAddrIndex);
2125 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
2129 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
2130 bool hasSymbolicDisplacement) {
2131 // Offset should fit into 32 bit immediate field.
2132 if (!isInt32(Offset))
2135 // If we don't have a symbolic displacement - we don't have any extra
2137 if (!hasSymbolicDisplacement)
2140 // FIXME: Some tweaks might be needed for medium code model.
2141 if (M != CodeModel::Small && M != CodeModel::Kernel)
2144 // For small code model we assume that latest object is 16MB before end of 31
2145 // bits boundary. We may also accept pretty large negative constants knowing
2146 // that all objects are in the positive half of address space.
2147 if (M == CodeModel::Small && Offset < 16*1024*1024)
2150 // For kernel code model we know that all object resist in the negative half
2151 // of 32bits address space. We may not accept negative offsets, since they may
2152 // be just off and we may accept pretty large positive ones.
2153 if (M == CodeModel::Kernel && Offset > 0)
2159 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
2160 /// specific condition code, returning the condition code and the LHS/RHS of the
2161 /// comparison to make.
2162 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
2163 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
2165 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
2166 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
2167 // X > -1 -> X == 0, jump !sign.
2168 RHS = DAG.getConstant(0, RHS.getValueType());
2169 return X86::COND_NS;
2170 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
2171 // X < 0 -> X == 0, jump on sign.
2173 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
2175 RHS = DAG.getConstant(0, RHS.getValueType());
2176 return X86::COND_LE;
2180 switch (SetCCOpcode) {
2181 default: llvm_unreachable("Invalid integer condition!");
2182 case ISD::SETEQ: return X86::COND_E;
2183 case ISD::SETGT: return X86::COND_G;
2184 case ISD::SETGE: return X86::COND_GE;
2185 case ISD::SETLT: return X86::COND_L;
2186 case ISD::SETLE: return X86::COND_LE;
2187 case ISD::SETNE: return X86::COND_NE;
2188 case ISD::SETULT: return X86::COND_B;
2189 case ISD::SETUGT: return X86::COND_A;
2190 case ISD::SETULE: return X86::COND_BE;
2191 case ISD::SETUGE: return X86::COND_AE;
2195 // First determine if it is required or is profitable to flip the operands.
2197 // If LHS is a foldable load, but RHS is not, flip the condition.
2198 if ((ISD::isNON_EXTLoad(LHS.getNode()) && LHS.hasOneUse()) &&
2199 !(ISD::isNON_EXTLoad(RHS.getNode()) && RHS.hasOneUse())) {
2200 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
2201 std::swap(LHS, RHS);
2204 switch (SetCCOpcode) {
2210 std::swap(LHS, RHS);
2214 // On a floating point condition, the flags are set as follows:
2216 // 0 | 0 | 0 | X > Y
2217 // 0 | 0 | 1 | X < Y
2218 // 1 | 0 | 0 | X == Y
2219 // 1 | 1 | 1 | unordered
2220 switch (SetCCOpcode) {
2221 default: llvm_unreachable("Condcode should be pre-legalized away");
2223 case ISD::SETEQ: return X86::COND_E;
2224 case ISD::SETOLT: // flipped
2226 case ISD::SETGT: return X86::COND_A;
2227 case ISD::SETOLE: // flipped
2229 case ISD::SETGE: return X86::COND_AE;
2230 case ISD::SETUGT: // flipped
2232 case ISD::SETLT: return X86::COND_B;
2233 case ISD::SETUGE: // flipped
2235 case ISD::SETLE: return X86::COND_BE;
2237 case ISD::SETNE: return X86::COND_NE;
2238 case ISD::SETUO: return X86::COND_P;
2239 case ISD::SETO: return X86::COND_NP;
2243 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
2244 /// code. Current x86 isa includes the following FP cmov instructions:
2245 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
2246 static bool hasFPCMov(unsigned X86CC) {
2262 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
2263 /// the specified range (L, H].
2264 static bool isUndefOrInRange(int Val, int Low, int Hi) {
2265 return (Val < 0) || (Val >= Low && Val < Hi);
2268 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
2269 /// specified value.
2270 static bool isUndefOrEqual(int Val, int CmpVal) {
2271 if (Val < 0 || Val == CmpVal)
2276 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
2277 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
2278 /// the second operand.
2279 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2280 if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16)
2281 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
2282 if (VT == MVT::v2f64 || VT == MVT::v2i64)
2283 return (Mask[0] < 2 && Mask[1] < 2);
2287 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) {
2288 SmallVector<int, 8> M;
2290 return ::isPSHUFDMask(M, N->getValueType(0));
2293 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
2294 /// is suitable for input to PSHUFHW.
2295 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2296 if (VT != MVT::v8i16)
2299 // Lower quadword copied in order or undef.
2300 for (int i = 0; i != 4; ++i)
2301 if (Mask[i] >= 0 && Mask[i] != i)
2304 // Upper quadword shuffled.
2305 for (int i = 4; i != 8; ++i)
2306 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7))
2312 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) {
2313 SmallVector<int, 8> M;
2315 return ::isPSHUFHWMask(M, N->getValueType(0));
2318 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
2319 /// is suitable for input to PSHUFLW.
2320 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2321 if (VT != MVT::v8i16)
2324 // Upper quadword copied in order.
2325 for (int i = 4; i != 8; ++i)
2326 if (Mask[i] >= 0 && Mask[i] != i)
2329 // Lower quadword shuffled.
2330 for (int i = 0; i != 4; ++i)
2337 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
2338 SmallVector<int, 8> M;
2340 return ::isPSHUFLWMask(M, N->getValueType(0));
2343 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
2344 /// specifies a shuffle of elements that is suitable for input to SHUFP*.
2345 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2346 int NumElems = VT.getVectorNumElements();
2347 if (NumElems != 2 && NumElems != 4)
2350 int Half = NumElems / 2;
2351 for (int i = 0; i < Half; ++i)
2352 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2354 for (int i = Half; i < NumElems; ++i)
2355 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2361 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) {
2362 SmallVector<int, 8> M;
2364 return ::isSHUFPMask(M, N->getValueType(0));
2367 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly
2368 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower
2369 /// half elements to come from vector 1 (which would equal the dest.) and
2370 /// the upper half to come from vector 2.
2371 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2372 int NumElems = VT.getVectorNumElements();
2374 if (NumElems != 2 && NumElems != 4)
2377 int Half = NumElems / 2;
2378 for (int i = 0; i < Half; ++i)
2379 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2))
2381 for (int i = Half; i < NumElems; ++i)
2382 if (!isUndefOrInRange(Mask[i], 0, NumElems))
2387 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) {
2388 SmallVector<int, 8> M;
2390 return isCommutedSHUFPMask(M, N->getValueType(0));
2393 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
2394 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
2395 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
2396 if (N->getValueType(0).getVectorNumElements() != 4)
2399 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
2400 return isUndefOrEqual(N->getMaskElt(0), 6) &&
2401 isUndefOrEqual(N->getMaskElt(1), 7) &&
2402 isUndefOrEqual(N->getMaskElt(2), 2) &&
2403 isUndefOrEqual(N->getMaskElt(3), 3);
2406 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
2407 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
2408 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) {
2409 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2411 if (NumElems != 2 && NumElems != 4)
2414 for (unsigned i = 0; i < NumElems/2; ++i)
2415 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems))
2418 for (unsigned i = NumElems/2; i < NumElems; ++i)
2419 if (!isUndefOrEqual(N->getMaskElt(i), i))
2425 /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
2426 /// specifies a shuffle of elements that is suitable for input to MOVHP{S|D}
2428 bool X86::isMOVHPMask(ShuffleVectorSDNode *N) {
2429 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2431 if (NumElems != 2 && NumElems != 4)
2434 for (unsigned i = 0; i < NumElems/2; ++i)
2435 if (!isUndefOrEqual(N->getMaskElt(i), i))
2438 for (unsigned i = 0; i < NumElems/2; ++i)
2439 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems))
2445 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
2446 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
2448 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
2449 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2454 return isUndefOrEqual(N->getMaskElt(0), 2) &&
2455 isUndefOrEqual(N->getMaskElt(1), 3) &&
2456 isUndefOrEqual(N->getMaskElt(2), 2) &&
2457 isUndefOrEqual(N->getMaskElt(3), 3);
2460 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
2461 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
2462 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT,
2463 bool V2IsSplat = false) {
2464 int NumElts = VT.getVectorNumElements();
2465 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2468 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2470 int BitI1 = Mask[i+1];
2471 if (!isUndefOrEqual(BitI, j))
2474 if (!isUndefOrEqual(BitI1, NumElts))
2477 if (!isUndefOrEqual(BitI1, j + NumElts))
2484 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2485 SmallVector<int, 8> M;
2487 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat);
2490 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
2491 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
2492 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT,
2493 bool V2IsSplat = false) {
2494 int NumElts = VT.getVectorNumElements();
2495 if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
2498 for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
2500 int BitI1 = Mask[i+1];
2501 if (!isUndefOrEqual(BitI, j + NumElts/2))
2504 if (isUndefOrEqual(BitI1, NumElts))
2507 if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
2514 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
2515 SmallVector<int, 8> M;
2517 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat);
2520 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
2521 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
2523 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
2524 int NumElems = VT.getVectorNumElements();
2525 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2528 for (int i = 0, j = 0; i != NumElems; i += 2, ++j) {
2530 int BitI1 = Mask[i+1];
2531 if (!isUndefOrEqual(BitI, j))
2533 if (!isUndefOrEqual(BitI1, j))
2539 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) {
2540 SmallVector<int, 8> M;
2542 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0));
2545 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
2546 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
2548 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) {
2549 int NumElems = VT.getVectorNumElements();
2550 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
2553 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) {
2555 int BitI1 = Mask[i+1];
2556 if (!isUndefOrEqual(BitI, j))
2558 if (!isUndefOrEqual(BitI1, j))
2564 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) {
2565 SmallVector<int, 8> M;
2567 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0));
2570 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
2571 /// specifies a shuffle of elements that is suitable for input to MOVSS,
2572 /// MOVSD, and MOVD, i.e. setting the lowest element.
2573 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) {
2574 if (VT.getVectorElementType().getSizeInBits() < 32)
2577 int NumElts = VT.getVectorNumElements();
2579 if (!isUndefOrEqual(Mask[0], NumElts))
2582 for (int i = 1; i < NumElts; ++i)
2583 if (!isUndefOrEqual(Mask[i], i))
2589 bool X86::isMOVLMask(ShuffleVectorSDNode *N) {
2590 SmallVector<int, 8> M;
2592 return ::isMOVLMask(M, N->getValueType(0));
2595 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse
2596 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
2597 /// element of vector 2 and the other elements to come from vector 1 in order.
2598 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT,
2599 bool V2IsSplat = false, bool V2IsUndef = false) {
2600 int NumOps = VT.getVectorNumElements();
2601 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
2604 if (!isUndefOrEqual(Mask[0], 0))
2607 for (int i = 1; i < NumOps; ++i)
2608 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
2609 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
2610 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
2616 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false,
2617 bool V2IsUndef = false) {
2618 SmallVector<int, 8> M;
2620 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef);
2623 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2624 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
2625 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N) {
2626 if (N->getValueType(0).getVectorNumElements() != 4)
2629 // Expect 1, 1, 3, 3
2630 for (unsigned i = 0; i < 2; ++i) {
2631 int Elt = N->getMaskElt(i);
2632 if (Elt >= 0 && Elt != 1)
2637 for (unsigned i = 2; i < 4; ++i) {
2638 int Elt = N->getMaskElt(i);
2639 if (Elt >= 0 && Elt != 3)
2644 // Don't use movshdup if it can be done with a shufps.
2645 // FIXME: verify that matching u, u, 3, 3 is what we want.
2649 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2650 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
2651 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N) {
2652 if (N->getValueType(0).getVectorNumElements() != 4)
2655 // Expect 0, 0, 2, 2
2656 for (unsigned i = 0; i < 2; ++i)
2657 if (N->getMaskElt(i) > 0)
2661 for (unsigned i = 2; i < 4; ++i) {
2662 int Elt = N->getMaskElt(i);
2663 if (Elt >= 0 && Elt != 2)
2668 // Don't use movsldup if it can be done with a shufps.
2672 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
2673 /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
2674 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) {
2675 int e = N->getValueType(0).getVectorNumElements() / 2;
2677 for (int i = 0; i < e; ++i)
2678 if (!isUndefOrEqual(N->getMaskElt(i), i))
2680 for (int i = 0; i < e; ++i)
2681 if (!isUndefOrEqual(N->getMaskElt(e+i), i))
2686 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
2687 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
2689 unsigned X86::getShuffleSHUFImmediate(SDNode *N) {
2690 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2691 int NumOperands = SVOp->getValueType(0).getVectorNumElements();
2693 unsigned Shift = (NumOperands == 4) ? 2 : 1;
2695 for (int i = 0; i < NumOperands; ++i) {
2696 int Val = SVOp->getMaskElt(NumOperands-i-1);
2697 if (Val < 0) Val = 0;
2698 if (Val >= NumOperands) Val -= NumOperands;
2700 if (i != NumOperands - 1)
2706 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
2707 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFHW
2709 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) {
2710 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2712 // 8 nodes, but we only care about the last 4.
2713 for (unsigned i = 7; i >= 4; --i) {
2714 int Val = SVOp->getMaskElt(i);
2723 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
2724 /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUFLW
2726 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
2727 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
2729 // 8 nodes, but we only care about the first 4.
2730 for (int i = 3; i >= 0; --i) {
2731 int Val = SVOp->getMaskElt(i);
2740 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
2742 bool X86::isZeroNode(SDValue Elt) {
2743 return ((isa<ConstantSDNode>(Elt) &&
2744 cast<ConstantSDNode>(Elt)->getZExtValue() == 0) ||
2745 (isa<ConstantFPSDNode>(Elt) &&
2746 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero()));
2749 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
2750 /// their permute mask.
2751 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
2752 SelectionDAG &DAG) {
2753 MVT VT = SVOp->getValueType(0);
2754 unsigned NumElems = VT.getVectorNumElements();
2755 SmallVector<int, 8> MaskVec;
2757 for (unsigned i = 0; i != NumElems; ++i) {
2758 int idx = SVOp->getMaskElt(i);
2760 MaskVec.push_back(idx);
2761 else if (idx < (int)NumElems)
2762 MaskVec.push_back(idx + NumElems);
2764 MaskVec.push_back(idx - NumElems);
2766 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
2767 SVOp->getOperand(0), &MaskVec[0]);
2770 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
2771 /// the two vector operands have swapped position.
2772 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) {
2773 unsigned NumElems = VT.getVectorNumElements();
2774 for (unsigned i = 0; i != NumElems; ++i) {
2778 else if (idx < (int)NumElems)
2779 Mask[i] = idx + NumElems;
2781 Mask[i] = idx - NumElems;
2785 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
2786 /// match movhlps. The lower half elements should come from upper half of
2787 /// V1 (and in order), and the upper half elements should come from the upper
2788 /// half of V2 (and in order).
2789 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) {
2790 if (Op->getValueType(0).getVectorNumElements() != 4)
2792 for (unsigned i = 0, e = 2; i != e; ++i)
2793 if (!isUndefOrEqual(Op->getMaskElt(i), i+2))
2795 for (unsigned i = 2; i != 4; ++i)
2796 if (!isUndefOrEqual(Op->getMaskElt(i), i+4))
2801 /// isScalarLoadToVector - Returns true if the node is a scalar load that
2802 /// is promoted to a vector. It also returns the LoadSDNode by reference if
2804 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
2805 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
2807 N = N->getOperand(0).getNode();
2808 if (!ISD::isNON_EXTLoad(N))
2811 *LD = cast<LoadSDNode>(N);
2815 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
2816 /// match movlp{s|d}. The lower half elements should come from lower half of
2817 /// V1 (and in order), and the upper half elements should come from the upper
2818 /// half of V2 (and in order). And since V1 will become the source of the
2819 /// MOVLP, it must be either a vector load or a scalar load to vector.
2820 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
2821 ShuffleVectorSDNode *Op) {
2822 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
2824 // Is V2 is a vector load, don't do this transformation. We will try to use
2825 // load folding shufps op.
2826 if (ISD::isNON_EXTLoad(V2))
2829 unsigned NumElems = Op->getValueType(0).getVectorNumElements();
2831 if (NumElems != 2 && NumElems != 4)
2833 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
2834 if (!isUndefOrEqual(Op->getMaskElt(i), i))
2836 for (unsigned i = NumElems/2; i != NumElems; ++i)
2837 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems))
2842 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
2844 static bool isSplatVector(SDNode *N) {
2845 if (N->getOpcode() != ISD::BUILD_VECTOR)
2848 SDValue SplatValue = N->getOperand(0);
2849 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
2850 if (N->getOperand(i) != SplatValue)
2855 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
2856 /// to an zero vector.
2857 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
2858 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
2859 SDValue V1 = N->getOperand(0);
2860 SDValue V2 = N->getOperand(1);
2861 unsigned NumElems = N->getValueType(0).getVectorNumElements();
2862 for (unsigned i = 0; i != NumElems; ++i) {
2863 int Idx = N->getMaskElt(i);
2864 if (Idx >= (int)NumElems) {
2865 unsigned Opc = V2.getOpcode();
2866 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
2868 if (Opc != ISD::BUILD_VECTOR ||
2869 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
2871 } else if (Idx >= 0) {
2872 unsigned Opc = V1.getOpcode();
2873 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
2875 if (Opc != ISD::BUILD_VECTOR ||
2876 !X86::isZeroNode(V1.getOperand(Idx)))
2883 /// getZeroVector - Returns a vector of specified type with all zero elements.
2885 static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
2887 assert(VT.isVector() && "Expected a vector type");
2889 // Always build zero vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2890 // type. This ensures they get CSE'd.
2892 if (VT.getSizeInBits() == 64) { // MMX
2893 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2894 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2895 } else if (HasSSE2) { // SSE2
2896 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2897 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2899 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
2900 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
2902 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2905 /// getOnesVector - Returns a vector of specified type with all bits set.
2907 static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
2908 assert(VT.isVector() && "Expected a vector type");
2910 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2911 // type. This ensures they get CSE'd.
2912 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2914 if (VT.getSizeInBits() == 64) // MMX
2915 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2917 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2918 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2922 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
2923 /// that point to V2 points to its first element.
2924 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
2925 MVT VT = SVOp->getValueType(0);
2926 unsigned NumElems = VT.getVectorNumElements();
2928 bool Changed = false;
2929 SmallVector<int, 8> MaskVec;
2930 SVOp->getMask(MaskVec);
2932 for (unsigned i = 0; i != NumElems; ++i) {
2933 if (MaskVec[i] > (int)NumElems) {
2934 MaskVec[i] = NumElems;
2939 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0),
2940 SVOp->getOperand(1), &MaskVec[0]);
2941 return SDValue(SVOp, 0);
2944 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
2945 /// operation of specified width.
2946 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2948 unsigned NumElems = VT.getVectorNumElements();
2949 SmallVector<int, 8> Mask;
2950 Mask.push_back(NumElems);
2951 for (unsigned i = 1; i != NumElems; ++i)
2953 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2956 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
2957 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2959 unsigned NumElems = VT.getVectorNumElements();
2960 SmallVector<int, 8> Mask;
2961 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
2963 Mask.push_back(i + NumElems);
2965 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2968 /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation.
2969 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1,
2971 unsigned NumElems = VT.getVectorNumElements();
2972 unsigned Half = NumElems/2;
2973 SmallVector<int, 8> Mask;
2974 for (unsigned i = 0; i != Half; ++i) {
2975 Mask.push_back(i + Half);
2976 Mask.push_back(i + NumElems + Half);
2978 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
2981 /// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
2982 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
2984 if (SV->getValueType(0).getVectorNumElements() <= 4)
2985 return SDValue(SV, 0);
2987 MVT PVT = MVT::v4f32;
2988 MVT VT = SV->getValueType(0);
2989 DebugLoc dl = SV->getDebugLoc();
2990 SDValue V1 = SV->getOperand(0);
2991 int NumElems = VT.getVectorNumElements();
2992 int EltNo = SV->getSplatIndex();
2994 // unpack elements to the correct location
2995 while (NumElems > 4) {
2996 if (EltNo < NumElems/2) {
2997 V1 = getUnpackl(DAG, dl, VT, V1, V1);
2999 V1 = getUnpackh(DAG, dl, VT, V1, V1);
3000 EltNo -= NumElems/2;
3005 // Perform the splat.
3006 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
3007 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
3008 V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), &SplatMask[0]);
3009 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
3012 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
3013 /// vector of zero or undef vector. This produces a shuffle where the low
3014 /// element of V2 is swizzled into the zero/undef vector, landing at element
3015 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
3016 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
3017 bool isZero, bool HasSSE2,
3018 SelectionDAG &DAG) {
3019 MVT VT = V2.getValueType();
3021 ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
3022 unsigned NumElems = VT.getVectorNumElements();
3023 SmallVector<int, 16> MaskVec;
3024 for (unsigned i = 0; i != NumElems; ++i)
3025 // If this is the insertion idx, put the low elt of V2 here.
3026 MaskVec.push_back(i == Idx ? NumElems : i);
3027 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
3030 /// getNumOfConsecutiveZeros - Return the number of elements in a result of
3031 /// a shuffle that is zero.
3033 unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp, int NumElems,
3034 bool Low, SelectionDAG &DAG) {
3035 unsigned NumZeros = 0;
3036 for (int i = 0; i < NumElems; ++i) {
3037 unsigned Index = Low ? i : NumElems-i-1;
3038 int Idx = SVOp->getMaskElt(Index);
3043 SDValue Elt = DAG.getShuffleScalarElt(SVOp, Index);
3044 if (Elt.getNode() && X86::isZeroNode(Elt))
3052 /// isVectorShift - Returns true if the shuffle can be implemented as a
3053 /// logical left or right shift of a vector.
3054 /// FIXME: split into pslldqi, psrldqi, palignr variants.
3055 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
3056 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
3057 int NumElems = SVOp->getValueType(0).getVectorNumElements();
3060 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, true, DAG);
3063 NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, false, DAG);
3067 bool SeenV1 = false;
3068 bool SeenV2 = false;
3069 for (int i = NumZeros; i < NumElems; ++i) {
3070 int Val = isLeft ? (i - NumZeros) : i;
3071 int Idx = SVOp->getMaskElt(isLeft ? i : (i - NumZeros));
3083 if (SeenV1 && SeenV2)
3086 ShVal = SeenV1 ? SVOp->getOperand(0) : SVOp->getOperand(1);
3092 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
3094 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
3095 unsigned NumNonZero, unsigned NumZero,
3096 SelectionDAG &DAG, TargetLowering &TLI) {
3100 DebugLoc dl = Op.getDebugLoc();
3103 for (unsigned i = 0; i < 16; ++i) {
3104 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
3105 if (ThisIsNonZero && First) {
3107 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3109 V = DAG.getUNDEF(MVT::v8i16);
3114 SDValue ThisElt(0, 0), LastElt(0, 0);
3115 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
3116 if (LastIsNonZero) {
3117 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
3118 MVT::i16, Op.getOperand(i-1));
3120 if (ThisIsNonZero) {
3121 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
3122 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
3123 ThisElt, DAG.getConstant(8, MVT::i8));
3125 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
3129 if (ThisElt.getNode())
3130 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
3131 DAG.getIntPtrConstant(i/2));
3135 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V);
3138 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
3140 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
3141 unsigned NumNonZero, unsigned NumZero,
3142 SelectionDAG &DAG, TargetLowering &TLI) {
3146 DebugLoc dl = Op.getDebugLoc();
3149 for (unsigned i = 0; i < 8; ++i) {
3150 bool isNonZero = (NonZeros & (1 << i)) != 0;
3154 V = getZeroVector(MVT::v8i16, true, DAG, dl);
3156 V = DAG.getUNDEF(MVT::v8i16);
3159 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
3160 MVT::v8i16, V, Op.getOperand(i),
3161 DAG.getIntPtrConstant(i));
3168 /// getVShift - Return a vector logical shift node.
3170 static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp,
3171 unsigned NumBits, SelectionDAG &DAG,
3172 const TargetLowering &TLI, DebugLoc dl) {
3173 bool isMMX = VT.getSizeInBits() == 64;
3174 MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64;
3175 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL;
3176 SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp);
3177 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3178 DAG.getNode(Opc, dl, ShVT, SrcOp,
3179 DAG.getConstant(NumBits, TLI.getShiftAmountTy())));
3183 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3184 DebugLoc dl = Op.getDebugLoc();
3185 // All zero's are handled with pxor, all one's are handled with pcmpeqd.
3186 if (ISD::isBuildVectorAllZeros(Op.getNode())
3187 || ISD::isBuildVectorAllOnes(Op.getNode())) {
3188 // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to
3189 // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are
3190 // eliminated on x86-32 hosts.
3191 if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32)
3194 if (ISD::isBuildVectorAllOnes(Op.getNode()))
3195 return getOnesVector(Op.getValueType(), DAG, dl);
3196 return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl);
3199 MVT VT = Op.getValueType();
3200 MVT EVT = VT.getVectorElementType();
3201 unsigned EVTBits = EVT.getSizeInBits();
3203 unsigned NumElems = Op.getNumOperands();
3204 unsigned NumZero = 0;
3205 unsigned NumNonZero = 0;
3206 unsigned NonZeros = 0;
3207 bool IsAllConstants = true;
3208 SmallSet<SDValue, 8> Values;
3209 for (unsigned i = 0; i < NumElems; ++i) {
3210 SDValue Elt = Op.getOperand(i);
3211 if (Elt.getOpcode() == ISD::UNDEF)
3214 if (Elt.getOpcode() != ISD::Constant &&
3215 Elt.getOpcode() != ISD::ConstantFP)
3216 IsAllConstants = false;
3217 if (X86::isZeroNode(Elt))
3220 NonZeros |= (1 << i);
3225 if (NumNonZero == 0) {
3226 // All undef vector. Return an UNDEF. All zero vectors were handled above.
3227 return DAG.getUNDEF(VT);
3230 // Special case for single non-zero, non-undef, element.
3231 if (NumNonZero == 1) {
3232 unsigned Idx = CountTrailingZeros_32(NonZeros);
3233 SDValue Item = Op.getOperand(Idx);
3235 // If this is an insertion of an i64 value on x86-32, and if the top bits of
3236 // the value are obviously zero, truncate the value to i32 and do the
3237 // insertion that way. Only do this if the value is non-constant or if the
3238 // value is a constant being inserted into element 0. It is cheaper to do
3239 // a constant pool load than it is to do a movd + shuffle.
3240 if (EVT == MVT::i64 && !Subtarget->is64Bit() &&
3241 (!IsAllConstants || Idx == 0)) {
3242 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
3243 // Handle MMX and SSE both.
3244 MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32;
3245 unsigned VecElts = VT == MVT::v2i64 ? 4 : 2;
3247 // Truncate the value (which may itself be a constant) to i32, and
3248 // convert it to a vector with movd (S2V+shuffle to zero extend).
3249 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
3250 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
3251 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3252 Subtarget->hasSSE2(), DAG);
3254 // Now we have our 32-bit value zero extended in the low element of
3255 // a vector. If Idx != 0, swizzle it into place.
3257 SmallVector<int, 4> Mask;
3258 Mask.push_back(Idx);
3259 for (unsigned i = 1; i != VecElts; ++i)
3261 Item = DAG.getVectorShuffle(VecVT, dl, Item,
3262 DAG.getUNDEF(Item.getValueType()),
3265 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Item);
3269 // If we have a constant or non-constant insertion into the low element of
3270 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
3271 // the rest of the elements. This will be matched as movd/movq/movss/movsd
3272 // depending on what the source datatype is.
3275 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3276 } else if (EVT == MVT::i32 || EVT == MVT::f32 || EVT == MVT::f64 ||
3277 (EVT == MVT::i64 && Subtarget->is64Bit())) {
3278 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3279 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
3280 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(),
3282 } else if (EVT == MVT::i16 || EVT == MVT::i8) {
3283 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
3284 MVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32;
3285 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item);
3286 Item = getShuffleVectorZeroOrUndef(Item, 0, true,
3287 Subtarget->hasSSE2(), DAG);
3288 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Item);
3292 // Is it a vector logical left shift?
3293 if (NumElems == 2 && Idx == 1 &&
3294 X86::isZeroNode(Op.getOperand(0)) &&
3295 !X86::isZeroNode(Op.getOperand(1))) {
3296 unsigned NumBits = VT.getSizeInBits();
3297 return getVShift(true, VT,
3298 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3299 VT, Op.getOperand(1)),
3300 NumBits/2, DAG, *this, dl);
3303 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
3306 // Otherwise, if this is a vector with i32 or f32 elements, and the element
3307 // is a non-constant being inserted into an element other than the low one,
3308 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
3309 // movd/movss) to move this into the low element, then shuffle it into
3311 if (EVTBits == 32) {
3312 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
3314 // Turn it into a shuffle of zero and zero-extended scalar to vector.
3315 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0,
3316 Subtarget->hasSSE2(), DAG);
3317 SmallVector<int, 8> MaskVec;
3318 for (unsigned i = 0; i < NumElems; i++)
3319 MaskVec.push_back(i == Idx ? 0 : 1);
3320 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
3324 // Splat is obviously ok. Let legalizer expand it to a shuffle.
3325 if (Values.size() == 1)
3328 // A vector full of immediates; various special cases are already
3329 // handled, so this is best done with a single constant-pool load.
3333 // Let legalizer expand 2-wide build_vectors.
3334 if (EVTBits == 64) {
3335 if (NumNonZero == 1) {
3336 // One half is zero or undef.
3337 unsigned Idx = CountTrailingZeros_32(NonZeros);
3338 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
3339 Op.getOperand(Idx));
3340 return getShuffleVectorZeroOrUndef(V2, Idx, true,
3341 Subtarget->hasSSE2(), DAG);
3346 // If element VT is < 32 bits, convert it to inserts into a zero vector.
3347 if (EVTBits == 8 && NumElems == 16) {
3348 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
3350 if (V.getNode()) return V;
3353 if (EVTBits == 16 && NumElems == 8) {
3354 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
3356 if (V.getNode()) return V;
3359 // If element VT is == 32 bits, turn it into a number of shuffles.
3360 SmallVector<SDValue, 8> V;
3362 if (NumElems == 4 && NumZero > 0) {
3363 for (unsigned i = 0; i < 4; ++i) {
3364 bool isZero = !(NonZeros & (1 << i));
3366 V[i] = getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
3368 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3371 for (unsigned i = 0; i < 2; ++i) {
3372 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
3375 V[i] = V[i*2]; // Must be a zero vector.
3378 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
3381 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
3384 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
3389 SmallVector<int, 8> MaskVec;
3390 bool Reverse = (NonZeros & 0x3) == 2;
3391 for (unsigned i = 0; i < 2; ++i)
3392 MaskVec.push_back(Reverse ? 1-i : i);
3393 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2;
3394 for (unsigned i = 0; i < 2; ++i)
3395 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems);
3396 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
3399 if (Values.size() > 2) {
3400 // If we have SSE 4.1, Expand into a number of inserts unless the number of
3401 // values to be inserted is equal to the number of elements, in which case
3402 // use the unpack code below in the hopes of matching the consecutive elts
3403 // load merge pattern for shuffles.
3404 // FIXME: We could probably just check that here directly.
3405 if (Values.size() < NumElems && VT.getSizeInBits() == 128 &&
3406 getSubtarget()->hasSSE41()) {
3407 V[0] = DAG.getUNDEF(VT);
3408 for (unsigned i = 0; i < NumElems; ++i)
3409 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
3410 V[0] = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, V[0],
3411 Op.getOperand(i), DAG.getIntPtrConstant(i));
3414 // Expand into a number of unpckl*.
3416 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
3417 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
3418 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
3419 for (unsigned i = 0; i < NumElems; ++i)
3420 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
3422 while (NumElems != 0) {
3423 for (unsigned i = 0; i < NumElems; ++i)
3424 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + NumElems]);
3433 // v8i16 shuffles - Prefer shuffles in the following order:
3434 // 1. [all] pshuflw, pshufhw, optional move
3435 // 2. [ssse3] 1 x pshufb
3436 // 3. [ssse3] 2 x pshufb + 1 x por
3437 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
3439 SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp,
3440 SelectionDAG &DAG, X86TargetLowering &TLI) {
3441 SDValue V1 = SVOp->getOperand(0);
3442 SDValue V2 = SVOp->getOperand(1);
3443 DebugLoc dl = SVOp->getDebugLoc();
3444 SmallVector<int, 8> MaskVals;
3446 // Determine if more than 1 of the words in each of the low and high quadwords
3447 // of the result come from the same quadword of one of the two inputs. Undef
3448 // mask values count as coming from any quadword, for better codegen.
3449 SmallVector<unsigned, 4> LoQuad(4);
3450 SmallVector<unsigned, 4> HiQuad(4);
3451 BitVector InputQuads(4);
3452 for (unsigned i = 0; i < 8; ++i) {
3453 SmallVectorImpl<unsigned> &Quad = i < 4 ? LoQuad : HiQuad;
3454 int EltIdx = SVOp->getMaskElt(i);
3455 MaskVals.push_back(EltIdx);
3464 InputQuads.set(EltIdx / 4);
3467 int BestLoQuad = -1;
3468 unsigned MaxQuad = 1;
3469 for (unsigned i = 0; i < 4; ++i) {
3470 if (LoQuad[i] > MaxQuad) {
3472 MaxQuad = LoQuad[i];
3476 int BestHiQuad = -1;
3478 for (unsigned i = 0; i < 4; ++i) {
3479 if (HiQuad[i] > MaxQuad) {
3481 MaxQuad = HiQuad[i];
3485 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
3486 // of the two input vectors, shuffle them into one input vector so only a
3487 // single pshufb instruction is necessary. If There are more than 2 input
3488 // quads, disable the next transformation since it does not help SSSE3.
3489 bool V1Used = InputQuads[0] || InputQuads[1];
3490 bool V2Used = InputQuads[2] || InputQuads[3];
3491 if (TLI.getSubtarget()->hasSSSE3()) {
3492 if (InputQuads.count() == 2 && V1Used && V2Used) {
3493 BestLoQuad = InputQuads.find_first();
3494 BestHiQuad = InputQuads.find_next(BestLoQuad);
3496 if (InputQuads.count() > 2) {
3502 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
3503 // the shuffle mask. If a quad is scored as -1, that means that it contains
3504 // words from all 4 input quadwords.
3506 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
3507 SmallVector<int, 8> MaskV;
3508 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad);
3509 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad);
3510 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
3511 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
3512 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]);
3513 NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV);
3515 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
3516 // source words for the shuffle, to aid later transformations.
3517 bool AllWordsInNewV = true;
3518 bool InOrder[2] = { true, true };
3519 for (unsigned i = 0; i != 8; ++i) {
3520 int idx = MaskVals[i];
3522 InOrder[i/4] = false;
3523 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
3525 AllWordsInNewV = false;
3529 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
3530 if (AllWordsInNewV) {
3531 for (int i = 0; i != 8; ++i) {
3532 int idx = MaskVals[i];
3535 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
3536 if ((idx != i) && idx < 4)
3538 if ((idx != i) && idx > 3)
3547 // If we've eliminated the use of V2, and the new mask is a pshuflw or
3548 // pshufhw, that's as cheap as it gets. Return the new shuffle.
3549 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
3550 return DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
3551 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
3555 // If we have SSSE3, and all words of the result are from 1 input vector,
3556 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
3557 // is present, fall back to case 4.
3558 if (TLI.getSubtarget()->hasSSSE3()) {
3559 SmallVector<SDValue,16> pshufbMask;
3561 // If we have elements from both input vectors, set the high bit of the
3562 // shuffle mask element to zero out elements that come from V2 in the V1
3563 // mask, and elements that come from V1 in the V2 mask, so that the two
3564 // results can be OR'd together.
3565 bool TwoInputs = V1Used && V2Used;
3566 for (unsigned i = 0; i != 8; ++i) {
3567 int EltIdx = MaskVals[i] * 2;
3568 if (TwoInputs && (EltIdx >= 16)) {
3569 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3570 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3573 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3574 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8));
3576 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
3577 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3578 DAG.getNode(ISD::BUILD_VECTOR, dl,
3579 MVT::v16i8, &pshufbMask[0], 16));
3581 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3583 // Calculate the shuffle mask for the second input, shuffle it, and
3584 // OR it with the first shuffled input.
3586 for (unsigned i = 0; i != 8; ++i) {
3587 int EltIdx = MaskVals[i] * 2;
3589 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3590 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3593 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3594 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8));
3596 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
3597 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3598 DAG.getNode(ISD::BUILD_VECTOR, dl,
3599 MVT::v16i8, &pshufbMask[0], 16));
3600 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3601 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3604 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
3605 // and update MaskVals with new element order.
3606 BitVector InOrder(8);
3607 if (BestLoQuad >= 0) {
3608 SmallVector<int, 8> MaskV;
3609 for (int i = 0; i != 4; ++i) {
3610 int idx = MaskVals[i];
3612 MaskV.push_back(-1);
3614 } else if ((idx / 4) == BestLoQuad) {
3615 MaskV.push_back(idx & 3);
3618 MaskV.push_back(-1);
3621 for (unsigned i = 4; i != 8; ++i)
3623 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3627 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
3628 // and update MaskVals with the new element order.
3629 if (BestHiQuad >= 0) {
3630 SmallVector<int, 8> MaskV;
3631 for (unsigned i = 0; i != 4; ++i)
3633 for (unsigned i = 4; i != 8; ++i) {
3634 int idx = MaskVals[i];
3636 MaskV.push_back(-1);
3638 } else if ((idx / 4) == BestHiQuad) {
3639 MaskV.push_back((idx & 3) + 4);
3642 MaskV.push_back(-1);
3645 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
3649 // In case BestHi & BestLo were both -1, which means each quadword has a word
3650 // from each of the four input quadwords, calculate the InOrder bitvector now
3651 // before falling through to the insert/extract cleanup.
3652 if (BestLoQuad == -1 && BestHiQuad == -1) {
3654 for (int i = 0; i != 8; ++i)
3655 if (MaskVals[i] < 0 || MaskVals[i] == i)
3659 // The other elements are put in the right place using pextrw and pinsrw.
3660 for (unsigned i = 0; i != 8; ++i) {
3663 int EltIdx = MaskVals[i];
3666 SDValue ExtOp = (EltIdx < 8)
3667 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
3668 DAG.getIntPtrConstant(EltIdx))
3669 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
3670 DAG.getIntPtrConstant(EltIdx - 8));
3671 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
3672 DAG.getIntPtrConstant(i));
3677 // v16i8 shuffles - Prefer shuffles in the following order:
3678 // 1. [ssse3] 1 x pshufb
3679 // 2. [ssse3] 2 x pshufb + 1 x por
3680 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
3682 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
3683 SelectionDAG &DAG, X86TargetLowering &TLI) {
3684 SDValue V1 = SVOp->getOperand(0);
3685 SDValue V2 = SVOp->getOperand(1);
3686 DebugLoc dl = SVOp->getDebugLoc();
3687 SmallVector<int, 16> MaskVals;
3688 SVOp->getMask(MaskVals);
3690 // If we have SSSE3, case 1 is generated when all result bytes come from
3691 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
3692 // present, fall back to case 3.
3693 // FIXME: kill V2Only once shuffles are canonizalized by getNode.
3696 for (unsigned i = 0; i < 16; ++i) {
3697 int EltIdx = MaskVals[i];
3706 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
3707 if (TLI.getSubtarget()->hasSSSE3()) {
3708 SmallVector<SDValue,16> pshufbMask;
3710 // If all result elements are from one input vector, then only translate
3711 // undef mask values to 0x80 (zero out result) in the pshufb mask.
3713 // Otherwise, we have elements from both input vectors, and must zero out
3714 // elements that come from V2 in the first mask, and V1 in the second mask
3715 // so that we can OR them together.
3716 bool TwoInputs = !(V1Only || V2Only);
3717 for (unsigned i = 0; i != 16; ++i) {
3718 int EltIdx = MaskVals[i];
3719 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) {
3720 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3723 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
3725 // If all the elements are from V2, assign it to V1 and return after
3726 // building the first pshufb.
3729 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
3730 DAG.getNode(ISD::BUILD_VECTOR, dl,
3731 MVT::v16i8, &pshufbMask[0], 16));
3735 // Calculate the shuffle mask for the second input, shuffle it, and
3736 // OR it with the first shuffled input.
3738 for (unsigned i = 0; i != 16; ++i) {
3739 int EltIdx = MaskVals[i];
3741 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
3744 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
3746 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
3747 DAG.getNode(ISD::BUILD_VECTOR, dl,
3748 MVT::v16i8, &pshufbMask[0], 16));
3749 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
3752 // No SSSE3 - Calculate in place words and then fix all out of place words
3753 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
3754 // the 16 different words that comprise the two doublequadword input vectors.
3755 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
3756 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2);
3757 SDValue NewV = V2Only ? V2 : V1;
3758 for (int i = 0; i != 8; ++i) {
3759 int Elt0 = MaskVals[i*2];
3760 int Elt1 = MaskVals[i*2+1];
3762 // This word of the result is all undef, skip it.
3763 if (Elt0 < 0 && Elt1 < 0)
3766 // This word of the result is already in the correct place, skip it.
3767 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1))
3769 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17))
3772 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
3773 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
3776 // If Elt0 and Elt1 are defined, are consecutive, and can be load
3777 // using a single extract together, load it and store it.
3778 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
3779 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3780 DAG.getIntPtrConstant(Elt1 / 2));
3781 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3782 DAG.getIntPtrConstant(i));
3786 // If Elt1 is defined, extract it from the appropriate source. If the
3787 // source byte is not also odd, shift the extracted word left 8 bits
3788 // otherwise clear the bottom 8 bits if we need to do an or.
3790 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
3791 DAG.getIntPtrConstant(Elt1 / 2));
3792 if ((Elt1 & 1) == 0)
3793 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
3794 DAG.getConstant(8, TLI.getShiftAmountTy()));
3796 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
3797 DAG.getConstant(0xFF00, MVT::i16));
3799 // If Elt0 is defined, extract it from the appropriate source. If the
3800 // source byte is not also even, shift the extracted word right 8 bits. If
3801 // Elt1 was also defined, OR the extracted values together before
3802 // inserting them in the result.
3804 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
3805 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
3806 if ((Elt0 & 1) != 0)
3807 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
3808 DAG.getConstant(8, TLI.getShiftAmountTy()));
3810 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
3811 DAG.getConstant(0x00FF, MVT::i16));
3812 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
3815 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
3816 DAG.getIntPtrConstant(i));
3818 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV);
3821 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
3822 /// ones, or rewriting v4i32 / v2f32 as 2 wide ones if possible. This can be
3823 /// done when every pair / quad of shuffle mask elements point to elements in
3824 /// the right sequence. e.g.
3825 /// vector_shuffle <>, <>, < 3, 4, | 10, 11, | 0, 1, | 14, 15>
3827 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
3829 TargetLowering &TLI, DebugLoc dl) {
3830 MVT VT = SVOp->getValueType(0);
3831 SDValue V1 = SVOp->getOperand(0);
3832 SDValue V2 = SVOp->getOperand(1);
3833 unsigned NumElems = VT.getVectorNumElements();
3834 unsigned NewWidth = (NumElems == 4) ? 2 : 4;
3835 MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
3836 MVT MaskEltVT = MaskVT.getVectorElementType();
3838 switch (VT.getSimpleVT()) {
3839 default: assert(false && "Unexpected!");
3840 case MVT::v4f32: NewVT = MVT::v2f64; break;
3841 case MVT::v4i32: NewVT = MVT::v2i64; break;
3842 case MVT::v8i16: NewVT = MVT::v4i32; break;
3843 case MVT::v16i8: NewVT = MVT::v4i32; break;
3846 if (NewWidth == 2) {
3852 int Scale = NumElems / NewWidth;
3853 SmallVector<int, 8> MaskVec;
3854 for (unsigned i = 0; i < NumElems; i += Scale) {
3856 for (int j = 0; j < Scale; ++j) {
3857 int EltIdx = SVOp->getMaskElt(i+j);
3861 StartIdx = EltIdx - (EltIdx % Scale);
3862 if (EltIdx != StartIdx + j)
3866 MaskVec.push_back(-1);
3868 MaskVec.push_back(StartIdx / Scale);
3871 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
3872 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
3873 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
3876 /// getVZextMovL - Return a zero-extending vector move low node.
3878 static SDValue getVZextMovL(MVT VT, MVT OpVT,
3879 SDValue SrcOp, SelectionDAG &DAG,
3880 const X86Subtarget *Subtarget, DebugLoc dl) {
3881 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
3882 LoadSDNode *LD = NULL;
3883 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
3884 LD = dyn_cast<LoadSDNode>(SrcOp);
3886 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
3888 MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
3889 if ((EVT != MVT::i64 || Subtarget->is64Bit()) &&
3890 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
3891 SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT &&
3892 SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) {
3894 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
3895 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3896 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3897 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
3905 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3906 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
3907 DAG.getNode(ISD::BIT_CONVERT, dl,
3911 /// LowerVECTOR_SHUFFLE_4wide - Handle all 4 wide cases with a number of
3914 LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
3915 SDValue V1 = SVOp->getOperand(0);
3916 SDValue V2 = SVOp->getOperand(1);
3917 DebugLoc dl = SVOp->getDebugLoc();
3918 MVT VT = SVOp->getValueType(0);
3920 SmallVector<std::pair<int, int>, 8> Locs;
3922 SmallVector<int, 8> Mask1(4U, -1);
3923 SmallVector<int, 8> PermMask;
3924 SVOp->getMask(PermMask);
3928 for (unsigned i = 0; i != 4; ++i) {
3929 int Idx = PermMask[i];
3931 Locs[i] = std::make_pair(-1, -1);
3933 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
3935 Locs[i] = std::make_pair(0, NumLo);
3939 Locs[i] = std::make_pair(1, NumHi);
3941 Mask1[2+NumHi] = Idx;
3947 if (NumLo <= 2 && NumHi <= 2) {
3948 // If no more than two elements come from either vector. This can be
3949 // implemented with two shuffles. First shuffle gather the elements.
3950 // The second shuffle, which takes the first shuffle as both of its
3951 // vector operands, put the elements into the right order.
3952 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3954 SmallVector<int, 8> Mask2(4U, -1);
3956 for (unsigned i = 0; i != 4; ++i) {
3957 if (Locs[i].first == -1)
3960 unsigned Idx = (i < 2) ? 0 : 4;
3961 Idx += Locs[i].first * 2 + Locs[i].second;
3966 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
3967 } else if (NumLo == 3 || NumHi == 3) {
3968 // Otherwise, we must have three elements from one vector, call it X, and
3969 // one element from the other, call it Y. First, use a shufps to build an
3970 // intermediate vector with the one element from Y and the element from X
3971 // that will be in the same half in the final destination (the indexes don't
3972 // matter). Then, use a shufps to build the final vector, taking the half
3973 // containing the element from Y from the intermediate, and the other half
3976 // Normalize it so the 3 elements come from V1.
3977 CommuteVectorShuffleMask(PermMask, VT);
3981 // Find the element from V2.
3983 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
3984 int Val = PermMask[HiIndex];
3991 Mask1[0] = PermMask[HiIndex];
3993 Mask1[2] = PermMask[HiIndex^1];
3995 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
3998 Mask1[0] = PermMask[0];
3999 Mask1[1] = PermMask[1];
4000 Mask1[2] = HiIndex & 1 ? 6 : 4;
4001 Mask1[3] = HiIndex & 1 ? 4 : 6;
4002 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
4004 Mask1[0] = HiIndex & 1 ? 2 : 0;
4005 Mask1[1] = HiIndex & 1 ? 0 : 2;
4006 Mask1[2] = PermMask[2];
4007 Mask1[3] = PermMask[3];
4012 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
4016 // Break it into (shuffle shuffle_hi, shuffle_lo).
4018 SmallVector<int,8> LoMask(4U, -1);
4019 SmallVector<int,8> HiMask(4U, -1);
4021 SmallVector<int,8> *MaskPtr = &LoMask;
4022 unsigned MaskIdx = 0;
4025 for (unsigned i = 0; i != 4; ++i) {
4032 int Idx = PermMask[i];
4034 Locs[i] = std::make_pair(-1, -1);
4035 } else if (Idx < 4) {
4036 Locs[i] = std::make_pair(MaskIdx, LoIdx);
4037 (*MaskPtr)[LoIdx] = Idx;
4040 Locs[i] = std::make_pair(MaskIdx, HiIdx);
4041 (*MaskPtr)[HiIdx] = Idx;
4046 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
4047 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
4048 SmallVector<int, 8> MaskOps;
4049 for (unsigned i = 0; i != 4; ++i) {
4050 if (Locs[i].first == -1) {
4051 MaskOps.push_back(-1);
4053 unsigned Idx = Locs[i].first * 4 + Locs[i].second;
4054 MaskOps.push_back(Idx);
4057 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
4061 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4063 SDValue V1 = Op.getOperand(0);
4064 SDValue V2 = Op.getOperand(1);
4065 MVT VT = Op.getValueType();
4066 DebugLoc dl = Op.getDebugLoc();
4067 unsigned NumElems = VT.getVectorNumElements();
4068 bool isMMX = VT.getSizeInBits() == 64;
4069 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
4070 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
4071 bool V1IsSplat = false;
4072 bool V2IsSplat = false;
4074 if (isZeroShuffle(SVOp))
4075 return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
4077 // Promote splats to v4f32.
4078 if (SVOp->isSplat()) {
4079 if (isMMX || NumElems < 4)
4081 return PromoteSplat(SVOp, DAG, Subtarget->hasSSE2());
4084 // If the shuffle can be profitably rewritten as a narrower shuffle, then
4086 if (VT == MVT::v8i16 || VT == MVT::v16i8) {
4087 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4088 if (NewOp.getNode())
4089 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
4090 LowerVECTOR_SHUFFLE(NewOp, DAG));
4091 } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
4092 // FIXME: Figure out a cleaner way to do this.
4093 // Try to make use of movq to zero out the top part.
4094 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
4095 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4096 if (NewOp.getNode()) {
4097 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false))
4098 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0),
4099 DAG, Subtarget, dl);
4101 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
4102 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl);
4103 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)))
4104 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1),
4105 DAG, Subtarget, dl);
4109 if (X86::isPSHUFDMask(SVOp))
4112 // Check if this can be converted into a logical shift.
4113 bool isLeft = false;
4116 bool isShift = getSubtarget()->hasSSE2() &&
4117 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
4118 if (isShift && ShVal.hasOneUse()) {
4119 // If the shifted value has multiple uses, it may be cheaper to use
4120 // v_set0 + movlhps or movhlps, etc.
4121 MVT EVT = VT.getVectorElementType();
4122 ShAmt *= EVT.getSizeInBits();
4123 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4126 if (X86::isMOVLMask(SVOp)) {
4129 if (ISD::isBuildVectorAllZeros(V1.getNode()))
4130 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
4135 // FIXME: fold these into legal mask.
4136 if (!isMMX && (X86::isMOVSHDUPMask(SVOp) ||
4137 X86::isMOVSLDUPMask(SVOp) ||
4138 X86::isMOVHLPSMask(SVOp) ||
4139 X86::isMOVHPMask(SVOp) ||
4140 X86::isMOVLPMask(SVOp)))
4143 if (ShouldXformToMOVHLPS(SVOp) ||
4144 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp))
4145 return CommuteVectorShuffle(SVOp, DAG);
4148 // No better options. Use a vshl / vsrl.
4149 MVT EVT = VT.getVectorElementType();
4150 ShAmt *= EVT.getSizeInBits();
4151 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
4154 bool Commuted = false;
4155 // FIXME: This should also accept a bitcast of a splat? Be careful, not
4156 // 1,1,1,1 -> v8i16 though.
4157 V1IsSplat = isSplatVector(V1.getNode());
4158 V2IsSplat = isSplatVector(V2.getNode());
4160 // Canonicalize the splat or undef, if present, to be on the RHS.
4161 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
4162 Op = CommuteVectorShuffle(SVOp, DAG);
4163 SVOp = cast<ShuffleVectorSDNode>(Op);
4164 V1 = SVOp->getOperand(0);
4165 V2 = SVOp->getOperand(1);
4166 std::swap(V1IsSplat, V2IsSplat);
4167 std::swap(V1IsUndef, V2IsUndef);
4171 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) {
4172 // Shuffling low element of v1 into undef, just return v1.
4175 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
4176 // the instruction selector will not match, so get a canonical MOVL with
4177 // swapped operands to undo the commute.
4178 return getMOVL(DAG, dl, VT, V2, V1);
4181 if (X86::isUNPCKL_v_undef_Mask(SVOp) ||
4182 X86::isUNPCKH_v_undef_Mask(SVOp) ||
4183 X86::isUNPCKLMask(SVOp) ||
4184 X86::isUNPCKHMask(SVOp))
4188 // Normalize mask so all entries that point to V2 points to its first
4189 // element then try to match unpck{h|l} again. If match, return a
4190 // new vector_shuffle with the corrected mask.
4191 SDValue NewMask = NormalizeMask(SVOp, DAG);
4192 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask);
4193 if (NSVOp != SVOp) {
4194 if (X86::isUNPCKLMask(NSVOp, true)) {
4196 } else if (X86::isUNPCKHMask(NSVOp, true)) {
4203 // Commute is back and try unpck* again.
4204 // FIXME: this seems wrong.
4205 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
4206 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
4207 if (X86::isUNPCKL_v_undef_Mask(NewSVOp) ||
4208 X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
4209 X86::isUNPCKLMask(NewSVOp) ||
4210 X86::isUNPCKHMask(NewSVOp))
4214 // FIXME: for mmx, bitcast v2i32 to v4i16 for shuffle.
4216 // Normalize the node to match x86 shuffle ops if needed
4217 if (!isMMX && V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp))
4218 return CommuteVectorShuffle(SVOp, DAG);
4220 // Check for legal shuffle and return?
4221 SmallVector<int, 16> PermMask;
4222 SVOp->getMask(PermMask);
4223 if (isShuffleMaskLegal(PermMask, VT))
4226 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
4227 if (VT == MVT::v8i16) {
4228 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this);
4229 if (NewOp.getNode())
4233 if (VT == MVT::v16i8) {
4234 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
4235 if (NewOp.getNode())
4239 // Handle all 4 wide cases with a number of shuffles except for MMX.
4240 if (NumElems == 4 && !isMMX)
4241 return LowerVECTOR_SHUFFLE_4wide(SVOp, DAG);
4247 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
4248 SelectionDAG &DAG) {
4249 MVT VT = Op.getValueType();
4250 DebugLoc dl = Op.getDebugLoc();
4251 if (VT.getSizeInBits() == 8) {
4252 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
4253 Op.getOperand(0), Op.getOperand(1));
4254 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4255 DAG.getValueType(VT));
4256 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4257 } else if (VT.getSizeInBits() == 16) {
4258 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4259 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
4261 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4262 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4263 DAG.getNode(ISD::BIT_CONVERT, dl,
4267 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
4268 Op.getOperand(0), Op.getOperand(1));
4269 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
4270 DAG.getValueType(VT));
4271 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4272 } else if (VT == MVT::f32) {
4273 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
4274 // the result back to FR32 register. It's only worth matching if the
4275 // result has a single use which is a store or a bitcast to i32. And in
4276 // the case of a store, it's not worth it if the index is a constant 0,
4277 // because a MOVSSmr can be used instead, which is smaller and faster.
4278 if (!Op.hasOneUse())
4280 SDNode *User = *Op.getNode()->use_begin();
4281 if ((User->getOpcode() != ISD::STORE ||
4282 (isa<ConstantSDNode>(Op.getOperand(1)) &&
4283 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
4284 (User->getOpcode() != ISD::BIT_CONVERT ||
4285 User->getValueType(0) != MVT::i32))
4287 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4288 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32,
4291 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract);
4292 } else if (VT == MVT::i32) {
4293 // ExtractPS works with constant index.
4294 if (isa<ConstantSDNode>(Op.getOperand(1)))
4302 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4303 if (!isa<ConstantSDNode>(Op.getOperand(1)))
4306 if (Subtarget->hasSSE41()) {
4307 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
4312 MVT VT = Op.getValueType();
4313 DebugLoc dl = Op.getDebugLoc();
4314 // TODO: handle v16i8.
4315 if (VT.getSizeInBits() == 16) {
4316 SDValue Vec = Op.getOperand(0);
4317 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4319 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
4320 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
4321 DAG.getNode(ISD::BIT_CONVERT, dl,
4324 // Transform it so it match pextrw which produces a 32-bit result.
4325 MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1);
4326 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT,
4327 Op.getOperand(0), Op.getOperand(1));
4328 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract,
4329 DAG.getValueType(VT));
4330 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
4331 } else if (VT.getSizeInBits() == 32) {
4332 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4336 // SHUFPS the element to the lowest double word, then movss.
4337 int Mask[4] = { Idx, -1, -1, -1 };
4338 MVT VVT = Op.getOperand(0).getValueType();
4339 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4340 DAG.getUNDEF(VVT), Mask);
4341 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4342 DAG.getIntPtrConstant(0));
4343 } else if (VT.getSizeInBits() == 64) {
4344 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
4345 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
4346 // to match extract_elt for f64.
4347 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
4351 // UNPCKHPD the element to the lowest double word, then movsd.
4352 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
4353 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
4354 int Mask[2] = { 1, -1 };
4355 MVT VVT = Op.getOperand(0).getValueType();
4356 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
4357 DAG.getUNDEF(VVT), Mask);
4358 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
4359 DAG.getIntPtrConstant(0));
4366 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
4367 MVT VT = Op.getValueType();
4368 MVT EVT = VT.getVectorElementType();
4369 DebugLoc dl = Op.getDebugLoc();
4371 SDValue N0 = Op.getOperand(0);
4372 SDValue N1 = Op.getOperand(1);
4373 SDValue N2 = Op.getOperand(2);
4375 if ((EVT.getSizeInBits() == 8 || EVT.getSizeInBits() == 16) &&
4376 isa<ConstantSDNode>(N2)) {
4377 unsigned Opc = (EVT.getSizeInBits() == 8) ? X86ISD::PINSRB
4379 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
4381 if (N1.getValueType() != MVT::i32)
4382 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4383 if (N2.getValueType() != MVT::i32)
4384 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4385 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
4386 } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
4387 // Bits [7:6] of the constant are the source select. This will always be
4388 // zero here. The DAG Combiner may combine an extract_elt index into these
4389 // bits. For example (insert (extract, 3), 2) could be matched by putting
4390 // the '3' into bits [7:6] of X86ISD::INSERTPS.
4391 // Bits [5:4] of the constant are the destination select. This is the
4392 // value of the incoming immediate.
4393 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
4394 // combine either bitwise AND or insert of float 0.0 to set these bits.
4395 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
4396 // Create this as a scalar to vector..
4397 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
4398 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
4399 } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) {
4400 // PINSR* works with constant index.
4407 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4408 MVT VT = Op.getValueType();
4409 MVT EVT = VT.getVectorElementType();
4411 if (Subtarget->hasSSE41())
4412 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
4417 DebugLoc dl = Op.getDebugLoc();
4418 SDValue N0 = Op.getOperand(0);
4419 SDValue N1 = Op.getOperand(1);
4420 SDValue N2 = Op.getOperand(2);
4422 if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
4423 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
4424 // as its second argument.
4425 if (N1.getValueType() != MVT::i32)
4426 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
4427 if (N2.getValueType() != MVT::i32)
4428 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
4429 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
4435 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
4436 DebugLoc dl = Op.getDebugLoc();
4437 if (Op.getValueType() == MVT::v2f32)
4438 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32,
4439 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32,
4440 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
4441 Op.getOperand(0))));
4443 if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
4444 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
4446 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
4447 MVT VT = MVT::v2i32;
4448 switch (Op.getValueType().getSimpleVT()) {
4455 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(),
4456 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, AnyExt));
4459 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
4460 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
4461 // one of the above mentioned nodes. It has to be wrapped because otherwise
4462 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
4463 // be used to form addressing mode. These wrapped nodes will be selected
4466 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
4467 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
4469 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4471 unsigned char OpFlag = 0;
4472 unsigned WrapperKind = X86ISD::Wrapper;
4473 CodeModel::Model M = getTargetMachine().getCodeModel();
4475 if (Subtarget->isPICStyleRIPRel() &&
4476 (M == CodeModel::Small || M == CodeModel::Kernel))
4477 WrapperKind = X86ISD::WrapperRIP;
4478 else if (Subtarget->isPICStyleGOT())
4479 OpFlag = X86II::MO_GOTOFF;
4480 else if (Subtarget->isPICStyleStubPIC())
4481 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4483 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
4485 CP->getOffset(), OpFlag);
4486 DebugLoc DL = CP->getDebugLoc();
4487 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4488 // With PIC, the address is actually $g + Offset.
4490 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4491 DAG.getNode(X86ISD::GlobalBaseReg,
4492 DebugLoc::getUnknownLoc(), getPointerTy()),
4499 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
4500 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
4502 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4504 unsigned char OpFlag = 0;
4505 unsigned WrapperKind = X86ISD::Wrapper;
4506 CodeModel::Model M = getTargetMachine().getCodeModel();
4508 if (Subtarget->isPICStyleRIPRel() &&
4509 (M == CodeModel::Small || M == CodeModel::Kernel))
4510 WrapperKind = X86ISD::WrapperRIP;
4511 else if (Subtarget->isPICStyleGOT())
4512 OpFlag = X86II::MO_GOTOFF;
4513 else if (Subtarget->isPICStyleStubPIC())
4514 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4516 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
4518 DebugLoc DL = JT->getDebugLoc();
4519 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4521 // With PIC, the address is actually $g + Offset.
4523 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4524 DAG.getNode(X86ISD::GlobalBaseReg,
4525 DebugLoc::getUnknownLoc(), getPointerTy()),
4533 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) {
4534 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
4536 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
4538 unsigned char OpFlag = 0;
4539 unsigned WrapperKind = X86ISD::Wrapper;
4540 CodeModel::Model M = getTargetMachine().getCodeModel();
4542 if (Subtarget->isPICStyleRIPRel() &&
4543 (M == CodeModel::Small || M == CodeModel::Kernel))
4544 WrapperKind = X86ISD::WrapperRIP;
4545 else if (Subtarget->isPICStyleGOT())
4546 OpFlag = X86II::MO_GOTOFF;
4547 else if (Subtarget->isPICStyleStubPIC())
4548 OpFlag = X86II::MO_PIC_BASE_OFFSET;
4550 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
4552 DebugLoc DL = Op.getDebugLoc();
4553 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
4556 // With PIC, the address is actually $g + Offset.
4557 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
4558 !Subtarget->is64Bit()) {
4559 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
4560 DAG.getNode(X86ISD::GlobalBaseReg,
4561 DebugLoc::getUnknownLoc(),
4570 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
4572 SelectionDAG &DAG) const {
4573 // Create the TargetGlobalAddress node, folding in the constant
4574 // offset if it is legal.
4575 unsigned char OpFlags =
4576 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
4577 CodeModel::Model M = getTargetMachine().getCodeModel();
4579 if (OpFlags == X86II::MO_NO_FLAG &&
4580 X86::isOffsetSuitableForCodeModel(Offset, M)) {
4581 // A direct static reference to a global.
4582 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
4585 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
4588 if (Subtarget->isPICStyleRIPRel() &&
4589 (M == CodeModel::Small || M == CodeModel::Kernel))
4590 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
4592 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
4594 // With PIC, the address is actually $g + Offset.
4595 if (isGlobalRelativeToPICBase(OpFlags)) {
4596 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
4597 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
4601 // For globals that require a load from a stub to get the address, emit the
4603 if (isGlobalStubReference(OpFlags))
4604 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
4605 PseudoSourceValue::getGOT(), 0);
4607 // If there was a non-zero offset that we didn't fold, create an explicit
4610 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
4611 DAG.getConstant(Offset, getPointerTy()));
4617 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) {
4618 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
4619 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
4620 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
4624 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
4625 SDValue *InFlag, const MVT PtrVT, unsigned ReturnReg,
4626 unsigned char OperandFlags) {
4627 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
4628 DebugLoc dl = GA->getDebugLoc();
4629 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(),
4630 GA->getValueType(0),
4634 SDValue Ops[] = { Chain, TGA, *InFlag };
4635 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3);
4637 SDValue Ops[] = { Chain, TGA };
4638 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2);
4640 SDValue Flag = Chain.getValue(1);
4641 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
4644 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
4646 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4649 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
4650 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
4651 DAG.getNode(X86ISD::GlobalBaseReg,
4652 DebugLoc::getUnknownLoc(),
4654 InFlag = Chain.getValue(1);
4656 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
4659 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
4661 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4663 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
4664 X86::RAX, X86II::MO_TLSGD);
4667 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or
4668 // "local exec" model.
4669 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
4670 const MVT PtrVT, TLSModel::Model model,
4672 DebugLoc dl = GA->getDebugLoc();
4673 // Get the Thread Pointer
4674 SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress,
4675 DebugLoc::getUnknownLoc(), PtrVT,
4676 DAG.getRegister(is64Bit? X86::FS : X86::GS,
4679 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base,
4682 unsigned char OperandFlags = 0;
4683 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
4685 unsigned WrapperKind = X86ISD::Wrapper;
4686 if (model == TLSModel::LocalExec) {
4687 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
4688 } else if (is64Bit) {
4689 assert(model == TLSModel::InitialExec);
4690 OperandFlags = X86II::MO_GOTTPOFF;
4691 WrapperKind = X86ISD::WrapperRIP;
4693 assert(model == TLSModel::InitialExec);
4694 OperandFlags = X86II::MO_INDNTPOFF;
4697 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
4699 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0),
4700 GA->getOffset(), OperandFlags);
4701 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
4703 if (model == TLSModel::InitialExec)
4704 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
4705 PseudoSourceValue::getGOT(), 0);
4707 // The address of the thread local variable is the add of the thread
4708 // pointer with the offset of the variable.
4709 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
4713 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
4714 // TODO: implement the "local dynamic" model
4715 // TODO: implement the "initial exec"model for pic executables
4716 assert(Subtarget->isTargetELF() &&
4717 "TLS not implemented for non-ELF targets");
4718 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
4719 const GlobalValue *GV = GA->getGlobal();
4721 // If GV is an alias then use the aliasee for determining
4722 // thread-localness.
4723 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
4724 GV = GA->resolveAliasedGlobal(false);
4726 TLSModel::Model model = getTLSModel(GV,
4727 getTargetMachine().getRelocationModel());
4730 case TLSModel::GeneralDynamic:
4731 case TLSModel::LocalDynamic: // not implemented
4732 if (Subtarget->is64Bit())
4733 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
4734 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
4736 case TLSModel::InitialExec:
4737 case TLSModel::LocalExec:
4738 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
4739 Subtarget->is64Bit());
4742 llvm_unreachable("Unreachable");
4747 /// LowerShift - Lower SRA_PARTS and friends, which return two i32 values and
4748 /// take a 2 x i32 value to shift plus a shift amount.
4749 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
4750 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4751 MVT VT = Op.getValueType();
4752 unsigned VTBits = VT.getSizeInBits();
4753 DebugLoc dl = Op.getDebugLoc();
4754 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
4755 SDValue ShOpLo = Op.getOperand(0);
4756 SDValue ShOpHi = Op.getOperand(1);
4757 SDValue ShAmt = Op.getOperand(2);
4758 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
4759 DAG.getConstant(VTBits - 1, MVT::i8))
4760 : DAG.getConstant(0, VT);
4763 if (Op.getOpcode() == ISD::SHL_PARTS) {
4764 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
4765 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4767 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
4768 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
4771 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
4772 DAG.getConstant(VTBits, MVT::i8));
4773 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT,
4774 AndNode, DAG.getConstant(0, MVT::i8));
4777 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
4778 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
4779 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
4781 if (Op.getOpcode() == ISD::SHL_PARTS) {
4782 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4783 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4785 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
4786 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
4789 SDValue Ops[2] = { Lo, Hi };
4790 return DAG.getMergeValues(Ops, 2, dl);
4793 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
4794 MVT SrcVT = Op.getOperand(0).getValueType();
4796 if (SrcVT.isVector()) {
4797 if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) {
4803 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
4804 "Unknown SINT_TO_FP to lower!");
4806 // These are really Legal; return the operand so the caller accepts it as
4808 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
4810 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
4811 Subtarget->is64Bit()) {
4815 DebugLoc dl = Op.getDebugLoc();
4816 unsigned Size = SrcVT.getSizeInBits()/8;
4817 MachineFunction &MF = DAG.getMachineFunction();
4818 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
4819 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4820 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
4822 PseudoSourceValue::getFixedStack(SSFI), 0);
4823 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
4826 SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain,
4828 SelectionDAG &DAG) {
4830 DebugLoc dl = Op.getDebugLoc();
4832 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
4834 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
4836 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
4837 SmallVector<SDValue, 8> Ops;
4838 Ops.push_back(Chain);
4839 Ops.push_back(StackSlot);
4840 Ops.push_back(DAG.getValueType(SrcVT));
4841 SDValue Result = DAG.getNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, dl,
4842 Tys, &Ops[0], Ops.size());
4845 Chain = Result.getValue(1);
4846 SDValue InFlag = Result.getValue(2);
4848 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
4849 // shouldn't be necessary except that RFP cannot be live across
4850 // multiple blocks. When stackifier is fixed, they can be uncoupled.
4851 MachineFunction &MF = DAG.getMachineFunction();
4852 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4853 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
4854 Tys = DAG.getVTList(MVT::Other);
4855 SmallVector<SDValue, 8> Ops;
4856 Ops.push_back(Chain);
4857 Ops.push_back(Result);
4858 Ops.push_back(StackSlot);
4859 Ops.push_back(DAG.getValueType(Op.getValueType()));
4860 Ops.push_back(InFlag);
4861 Chain = DAG.getNode(X86ISD::FST, dl, Tys, &Ops[0], Ops.size());
4862 Result = DAG.getLoad(Op.getValueType(), dl, Chain, StackSlot,
4863 PseudoSourceValue::getFixedStack(SSFI), 0);
4869 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
4870 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
4871 // This algorithm is not obvious. Here it is in C code, more or less:
4873 double uint64_to_double( uint32_t hi, uint32_t lo ) {
4874 static const __m128i exp = { 0x4330000045300000ULL, 0 };
4875 static const __m128d bias = { 0x1.0p84, 0x1.0p52 };
4877 // Copy ints to xmm registers.
4878 __m128i xh = _mm_cvtsi32_si128( hi );
4879 __m128i xl = _mm_cvtsi32_si128( lo );
4881 // Combine into low half of a single xmm register.
4882 __m128i x = _mm_unpacklo_epi32( xh, xl );
4886 // Merge in appropriate exponents to give the integer bits the right
4888 x = _mm_unpacklo_epi32( x, exp );
4890 // Subtract away the biases to deal with the IEEE-754 double precision
4892 d = _mm_sub_pd( (__m128d) x, bias );
4894 // All conversions up to here are exact. The correctly rounded result is
4895 // calculated using the current rounding mode using the following
4897 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) );
4898 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this
4899 // store doesn't really need to be here (except
4900 // maybe to zero the other double)
4905 DebugLoc dl = Op.getDebugLoc();
4906 LLVMContext *Context = DAG.getContext();
4908 // Build some magic constants.
4909 std::vector<Constant*> CV0;
4910 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000)));
4911 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000)));
4912 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4913 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0)));
4914 Constant *C0 = ConstantVector::get(CV0);
4915 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
4917 std::vector<Constant*> CV1;
4919 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL))));
4921 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL))));
4922 Constant *C1 = ConstantVector::get(CV1);
4923 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
4925 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4926 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4928 DAG.getIntPtrConstant(1)));
4929 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4930 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4932 DAG.getIntPtrConstant(0)));
4933 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2);
4934 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
4935 PseudoSourceValue::getConstantPool(), 0,
4937 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0);
4938 SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2);
4939 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
4940 PseudoSourceValue::getConstantPool(), 0,
4942 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
4944 // Add the halves; easiest way is to swap them into another reg first.
4945 int ShufMask[2] = { 1, -1 };
4946 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub,
4947 DAG.getUNDEF(MVT::v2f64), ShufMask);
4948 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub);
4949 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add,
4950 DAG.getIntPtrConstant(0));
4953 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
4954 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) {
4955 DebugLoc dl = Op.getDebugLoc();
4956 // FP constant to bias correct the final result.
4957 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
4960 // Load the 32-bit value into an XMM register.
4961 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
4962 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4964 DAG.getIntPtrConstant(0)));
4966 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4967 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load),
4968 DAG.getIntPtrConstant(0));
4970 // Or the load with the bias.
4971 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
4972 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4973 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4975 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
4976 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
4977 MVT::v2f64, Bias)));
4978 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4979 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or),
4980 DAG.getIntPtrConstant(0));
4982 // Subtract the bias.
4983 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
4985 // Handle final rounding.
4986 MVT DestVT = Op.getValueType();
4988 if (DestVT.bitsLT(MVT::f64)) {
4989 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
4990 DAG.getIntPtrConstant(0));
4991 } else if (DestVT.bitsGT(MVT::f64)) {
4992 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
4995 // Handle final rounding.
4999 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
5000 SDValue N0 = Op.getOperand(0);
5001 DebugLoc dl = Op.getDebugLoc();
5003 // Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't
5004 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
5005 // the optimization here.
5006 if (DAG.SignBitIsZero(N0))
5007 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
5009 MVT SrcVT = N0.getValueType();
5010 if (SrcVT == MVT::i64) {
5011 // We only handle SSE2 f64 target here; caller can expand the rest.
5012 if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64)
5015 return LowerUINT_TO_FP_i64(Op, DAG);
5016 } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) {
5017 return LowerUINT_TO_FP_i32(Op, DAG);
5020 assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!");
5022 // Make a 64-bit buffer, and use it to build an FILD.
5023 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
5024 SDValue WordOff = DAG.getConstant(4, getPointerTy());
5025 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
5026 getPointerTy(), StackSlot, WordOff);
5027 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
5028 StackSlot, NULL, 0);
5029 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
5030 OffsetSlot, NULL, 0);
5031 return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
5034 std::pair<SDValue,SDValue> X86TargetLowering::
5035 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) {
5036 DebugLoc dl = Op.getDebugLoc();
5038 MVT DstTy = Op.getValueType();
5041 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
5045 assert(DstTy.getSimpleVT() <= MVT::i64 &&
5046 DstTy.getSimpleVT() >= MVT::i16 &&
5047 "Unknown FP_TO_SINT to lower!");
5049 // These are really Legal.
5050 if (DstTy == MVT::i32 &&
5051 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5052 return std::make_pair(SDValue(), SDValue());
5053 if (Subtarget->is64Bit() &&
5054 DstTy == MVT::i64 &&
5055 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
5056 return std::make_pair(SDValue(), SDValue());
5058 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
5060 MachineFunction &MF = DAG.getMachineFunction();
5061 unsigned MemSize = DstTy.getSizeInBits()/8;
5062 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5063 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5066 switch (DstTy.getSimpleVT()) {
5067 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
5068 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
5069 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
5070 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
5073 SDValue Chain = DAG.getEntryNode();
5074 SDValue Value = Op.getOperand(0);
5075 if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) {
5076 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
5077 Chain = DAG.getStore(Chain, dl, Value, StackSlot,
5078 PseudoSourceValue::getFixedStack(SSFI), 0);
5079 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
5081 Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType())
5083 Value = DAG.getNode(X86ISD::FLD, dl, Tys, Ops, 3);
5084 Chain = Value.getValue(1);
5085 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
5086 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
5089 // Build the FP_TO_INT*_IN_MEM
5090 SDValue Ops[] = { Chain, Value, StackSlot };
5091 SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3);
5093 return std::make_pair(FIST, StackSlot);
5096 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
5097 if (Op.getValueType().isVector()) {
5098 if (Op.getValueType() == MVT::v2i32 &&
5099 Op.getOperand(0).getValueType() == MVT::v2f64) {
5105 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true);
5106 SDValue FIST = Vals.first, StackSlot = Vals.second;
5107 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
5108 if (FIST.getNode() == 0) return Op;
5111 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5112 FIST, StackSlot, NULL, 0);
5115 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) {
5116 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false);
5117 SDValue FIST = Vals.first, StackSlot = Vals.second;
5118 assert(FIST.getNode() && "Unexpected failure");
5121 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
5122 FIST, StackSlot, NULL, 0);
5125 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) {
5126 LLVMContext *Context = DAG.getContext();
5127 DebugLoc dl = Op.getDebugLoc();
5128 MVT VT = Op.getValueType();
5131 EltVT = VT.getVectorElementType();
5132 std::vector<Constant*> CV;
5133 if (EltVT == MVT::f64) {
5134 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))));
5138 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))));
5144 Constant *C = ConstantVector::get(CV);
5145 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5146 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5147 PseudoSourceValue::getConstantPool(), 0,
5149 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
5152 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) {
5153 LLVMContext *Context = DAG.getContext();
5154 DebugLoc dl = Op.getDebugLoc();
5155 MVT VT = Op.getValueType();
5157 unsigned EltNum = 1;
5158 if (VT.isVector()) {
5159 EltVT = VT.getVectorElementType();
5160 EltNum = VT.getVectorNumElements();
5162 std::vector<Constant*> CV;
5163 if (EltVT == MVT::f64) {
5164 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)));
5168 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)));
5174 Constant *C = ConstantVector::get(CV);
5175 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5176 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5177 PseudoSourceValue::getConstantPool(), 0,
5179 if (VT.isVector()) {
5180 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
5181 DAG.getNode(ISD::XOR, dl, MVT::v2i64,
5182 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64,
5184 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask)));
5186 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
5190 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
5191 LLVMContext *Context = DAG.getContext();
5192 SDValue Op0 = Op.getOperand(0);
5193 SDValue Op1 = Op.getOperand(1);
5194 DebugLoc dl = Op.getDebugLoc();
5195 MVT VT = Op.getValueType();
5196 MVT SrcVT = Op1.getValueType();
5198 // If second operand is smaller, extend it first.
5199 if (SrcVT.bitsLT(VT)) {
5200 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
5203 // And if it is bigger, shrink it first.
5204 if (SrcVT.bitsGT(VT)) {
5205 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
5209 // At this point the operands and the result should have the same
5210 // type, and that won't be f80 since that is not custom lowered.
5212 // First get the sign bit of second operand.
5213 std::vector<Constant*> CV;
5214 if (SrcVT == MVT::f64) {
5215 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))));
5216 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5218 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))));
5219 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5220 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5221 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5223 Constant *C = ConstantVector::get(CV);
5224 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5225 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
5226 PseudoSourceValue::getConstantPool(), 0,
5228 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
5230 // Shift sign bit right or left if the two operands have different types.
5231 if (SrcVT.bitsGT(VT)) {
5232 // Op0 is MVT::f32, Op1 is MVT::f64.
5233 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
5234 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
5235 DAG.getConstant(32, MVT::i32));
5236 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit);
5237 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
5238 DAG.getIntPtrConstant(0));
5241 // Clear first operand sign bit.
5243 if (VT == MVT::f64) {
5244 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))));
5245 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0))));
5247 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))));
5248 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5249 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5250 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0))));
5252 C = ConstantVector::get(CV);
5253 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
5254 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5255 PseudoSourceValue::getConstantPool(), 0,
5257 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
5259 // Or the value with the sign bit.
5260 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
5263 /// Emit nodes that will be selected as "test Op0,Op0", or something
5265 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
5266 SelectionDAG &DAG) {
5267 DebugLoc dl = Op.getDebugLoc();
5269 // CF and OF aren't always set the way we want. Determine which
5270 // of these we need.
5271 bool NeedCF = false;
5272 bool NeedOF = false;
5274 case X86::COND_A: case X86::COND_AE:
5275 case X86::COND_B: case X86::COND_BE:
5278 case X86::COND_G: case X86::COND_GE:
5279 case X86::COND_L: case X86::COND_LE:
5280 case X86::COND_O: case X86::COND_NO:
5286 // See if we can use the EFLAGS value from the operand instead of
5287 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
5288 // we prove that the arithmetic won't overflow, we can't use OF or CF.
5289 if (Op.getResNo() == 0 && !NeedOF && !NeedCF) {
5290 unsigned Opcode = 0;
5291 unsigned NumOperands = 0;
5292 switch (Op.getNode()->getOpcode()) {
5294 // Due to an isel shortcoming, be conservative if this add is likely to
5295 // be selected as part of a load-modify-store instruction. When the root
5296 // node in a match is a store, isel doesn't know how to remap non-chain
5297 // non-flag uses of other nodes in the match, such as the ADD in this
5298 // case. This leads to the ADD being left around and reselected, with
5299 // the result being two adds in the output.
5300 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5301 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5302 if (UI->getOpcode() == ISD::STORE)
5304 if (ConstantSDNode *C =
5305 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) {
5306 // An add of one will be selected as an INC.
5307 if (C->getAPIntValue() == 1) {
5308 Opcode = X86ISD::INC;
5312 // An add of negative one (subtract of one) will be selected as a DEC.
5313 if (C->getAPIntValue().isAllOnesValue()) {
5314 Opcode = X86ISD::DEC;
5319 // Otherwise use a regular EFLAGS-setting add.
5320 Opcode = X86ISD::ADD;
5324 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5325 // likely to be selected as part of a load-modify-store instruction.
5326 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5327 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5328 if (UI->getOpcode() == ISD::STORE)
5330 // Otherwise use a regular EFLAGS-setting sub.
5331 Opcode = X86ISD::SUB;
5338 return SDValue(Op.getNode(), 1);
5344 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
5345 SmallVector<SDValue, 4> Ops;
5346 for (unsigned i = 0; i != NumOperands; ++i)
5347 Ops.push_back(Op.getOperand(i));
5348 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
5349 DAG.ReplaceAllUsesWith(Op, New);
5350 return SDValue(New.getNode(), 1);
5354 // Otherwise just emit a CMP with 0, which is the TEST pattern.
5355 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
5356 DAG.getConstant(0, Op.getValueType()));
5359 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
5361 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
5362 SelectionDAG &DAG) {
5363 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
5364 if (C->getAPIntValue() == 0)
5365 return EmitTest(Op0, X86CC, DAG);
5367 DebugLoc dl = Op0.getDebugLoc();
5368 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
5371 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
5372 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer");
5373 SDValue Op0 = Op.getOperand(0);
5374 SDValue Op1 = Op.getOperand(1);
5375 DebugLoc dl = Op.getDebugLoc();
5376 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
5378 // Lower (X & (1 << N)) == 0 to BT(X, N).
5379 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
5380 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
5381 if (Op0.getOpcode() == ISD::AND &&
5383 Op1.getOpcode() == ISD::Constant &&
5384 cast<ConstantSDNode>(Op1)->getZExtValue() == 0 &&
5385 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
5387 if (Op0.getOperand(1).getOpcode() == ISD::SHL) {
5388 if (ConstantSDNode *Op010C =
5389 dyn_cast<ConstantSDNode>(Op0.getOperand(1).getOperand(0)))
5390 if (Op010C->getZExtValue() == 1) {
5391 LHS = Op0.getOperand(0);
5392 RHS = Op0.getOperand(1).getOperand(1);
5394 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL) {
5395 if (ConstantSDNode *Op000C =
5396 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(0)))
5397 if (Op000C->getZExtValue() == 1) {
5398 LHS = Op0.getOperand(1);
5399 RHS = Op0.getOperand(0).getOperand(1);
5401 } else if (Op0.getOperand(1).getOpcode() == ISD::Constant) {
5402 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op0.getOperand(1));
5403 SDValue AndLHS = Op0.getOperand(0);
5404 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) {
5405 LHS = AndLHS.getOperand(0);
5406 RHS = AndLHS.getOperand(1);
5410 if (LHS.getNode()) {
5411 // If LHS is i8, promote it to i16 with any_extend. There is no i8 BT
5412 // instruction. Since the shift amount is in-range-or-undefined, we know
5413 // that doing a bittest on the i16 value is ok. We extend to i32 because
5414 // the encoding for the i16 version is larger than the i32 version.
5415 if (LHS.getValueType() == MVT::i8)
5416 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
5418 // If the operand types disagree, extend the shift amount to match. Since
5419 // BT ignores high bits (like shifts) we can use anyextend.
5420 if (LHS.getValueType() != RHS.getValueType())
5421 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
5423 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
5424 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
5425 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5426 DAG.getConstant(Cond, MVT::i8), BT);
5430 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5431 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
5433 SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG);
5434 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
5435 DAG.getConstant(X86CC, MVT::i8), Cond);
5438 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
5440 SDValue Op0 = Op.getOperand(0);
5441 SDValue Op1 = Op.getOperand(1);
5442 SDValue CC = Op.getOperand(2);
5443 MVT VT = Op.getValueType();
5444 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
5445 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
5446 DebugLoc dl = Op.getDebugLoc();
5450 MVT VT0 = Op0.getValueType();
5451 assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64);
5452 unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD;
5455 switch (SetCCOpcode) {
5458 case ISD::SETEQ: SSECC = 0; break;
5460 case ISD::SETGT: Swap = true; // Fallthrough
5462 case ISD::SETOLT: SSECC = 1; break;
5464 case ISD::SETGE: Swap = true; // Fallthrough
5466 case ISD::SETOLE: SSECC = 2; break;
5467 case ISD::SETUO: SSECC = 3; break;
5469 case ISD::SETNE: SSECC = 4; break;
5470 case ISD::SETULE: Swap = true;
5471 case ISD::SETUGE: SSECC = 5; break;
5472 case ISD::SETULT: Swap = true;
5473 case ISD::SETUGT: SSECC = 6; break;
5474 case ISD::SETO: SSECC = 7; break;
5477 std::swap(Op0, Op1);
5479 // In the two special cases we can't handle, emit two comparisons.
5481 if (SetCCOpcode == ISD::SETUEQ) {
5483 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
5484 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
5485 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
5487 else if (SetCCOpcode == ISD::SETONE) {
5489 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
5490 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
5491 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
5493 llvm_unreachable("Illegal FP comparison");
5495 // Handle all other FP comparisons here.
5496 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
5499 // We are handling one of the integer comparisons here. Since SSE only has
5500 // GT and EQ comparisons for integer, swapping operands and multiple
5501 // operations may be required for some comparisons.
5502 unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
5503 bool Swap = false, Invert = false, FlipSigns = false;
5505 switch (VT.getSimpleVT()) {
5508 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
5510 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
5512 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
5513 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
5516 switch (SetCCOpcode) {
5518 case ISD::SETNE: Invert = true;
5519 case ISD::SETEQ: Opc = EQOpc; break;
5520 case ISD::SETLT: Swap = true;
5521 case ISD::SETGT: Opc = GTOpc; break;
5522 case ISD::SETGE: Swap = true;
5523 case ISD::SETLE: Opc = GTOpc; Invert = true; break;
5524 case ISD::SETULT: Swap = true;
5525 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
5526 case ISD::SETUGE: Swap = true;
5527 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
5530 std::swap(Op0, Op1);
5532 // Since SSE has no unsigned integer comparisons, we need to flip the sign
5533 // bits of the inputs before performing those operations.
5535 MVT EltVT = VT.getVectorElementType();
5536 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
5538 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
5539 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
5541 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
5542 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
5545 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
5547 // If the logical-not of the result is required, perform that now.
5549 Result = DAG.getNOT(dl, Result, VT);
5554 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
5555 static bool isX86LogicalCmp(SDValue Op) {
5556 unsigned Opc = Op.getNode()->getOpcode();
5557 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI)
5559 if (Op.getResNo() == 1 &&
5560 (Opc == X86ISD::ADD ||
5561 Opc == X86ISD::SUB ||
5562 Opc == X86ISD::SMUL ||
5563 Opc == X86ISD::UMUL ||
5564 Opc == X86ISD::INC ||
5565 Opc == X86ISD::DEC))
5571 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
5572 bool addTest = true;
5573 SDValue Cond = Op.getOperand(0);
5574 DebugLoc dl = Op.getDebugLoc();
5577 if (Cond.getOpcode() == ISD::SETCC)
5578 Cond = LowerSETCC(Cond, DAG);
5580 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5581 // setting operand in place of the X86ISD::SETCC.
5582 if (Cond.getOpcode() == X86ISD::SETCC) {
5583 CC = Cond.getOperand(0);
5585 SDValue Cmp = Cond.getOperand(1);
5586 unsigned Opc = Cmp.getOpcode();
5587 MVT VT = Op.getValueType();
5589 bool IllegalFPCMov = false;
5590 if (VT.isFloatingPoint() && !VT.isVector() &&
5591 !isScalarFPTypeInSSEReg(VT)) // FPStack?
5592 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
5594 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
5595 Opc == X86ISD::BT) { // FIXME
5602 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5603 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5606 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
5607 SmallVector<SDValue, 4> Ops;
5608 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
5609 // condition is true.
5610 Ops.push_back(Op.getOperand(2));
5611 Ops.push_back(Op.getOperand(1));
5613 Ops.push_back(Cond);
5614 return DAG.getNode(X86ISD::CMOV, dl, VTs, &Ops[0], Ops.size());
5617 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
5618 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
5619 // from the AND / OR.
5620 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
5621 Opc = Op.getOpcode();
5622 if (Opc != ISD::OR && Opc != ISD::AND)
5624 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5625 Op.getOperand(0).hasOneUse() &&
5626 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
5627 Op.getOperand(1).hasOneUse());
5630 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
5631 // 1 and that the SETCC node has a single use.
5632 static bool isXor1OfSetCC(SDValue Op) {
5633 if (Op.getOpcode() != ISD::XOR)
5635 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
5636 if (N1C && N1C->getAPIntValue() == 1) {
5637 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
5638 Op.getOperand(0).hasOneUse();
5643 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
5644 bool addTest = true;
5645 SDValue Chain = Op.getOperand(0);
5646 SDValue Cond = Op.getOperand(1);
5647 SDValue Dest = Op.getOperand(2);
5648 DebugLoc dl = Op.getDebugLoc();
5651 if (Cond.getOpcode() == ISD::SETCC)
5652 Cond = LowerSETCC(Cond, DAG);
5654 // FIXME: LowerXALUO doesn't handle these!!
5655 else if (Cond.getOpcode() == X86ISD::ADD ||
5656 Cond.getOpcode() == X86ISD::SUB ||
5657 Cond.getOpcode() == X86ISD::SMUL ||
5658 Cond.getOpcode() == X86ISD::UMUL)
5659 Cond = LowerXALUO(Cond, DAG);
5662 // If condition flag is set by a X86ISD::CMP, then use it as the condition
5663 // setting operand in place of the X86ISD::SETCC.
5664 if (Cond.getOpcode() == X86ISD::SETCC) {
5665 CC = Cond.getOperand(0);
5667 SDValue Cmp = Cond.getOperand(1);
5668 unsigned Opc = Cmp.getOpcode();
5669 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
5670 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
5674 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
5678 // These can only come from an arithmetic instruction with overflow,
5679 // e.g. SADDO, UADDO.
5680 Cond = Cond.getNode()->getOperand(1);
5687 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
5688 SDValue Cmp = Cond.getOperand(0).getOperand(1);
5689 if (CondOpc == ISD::OR) {
5690 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
5691 // two branches instead of an explicit OR instruction with a
5693 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5694 isX86LogicalCmp(Cmp)) {
5695 CC = Cond.getOperand(0).getOperand(0);
5696 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5697 Chain, Dest, CC, Cmp);
5698 CC = Cond.getOperand(1).getOperand(0);
5702 } else { // ISD::AND
5703 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
5704 // two branches instead of an explicit AND instruction with a
5705 // separate test. However, we only do this if this block doesn't
5706 // have a fall-through edge, because this requires an explicit
5707 // jmp when the condition is false.
5708 if (Cmp == Cond.getOperand(1).getOperand(1) &&
5709 isX86LogicalCmp(Cmp) &&
5710 Op.getNode()->hasOneUse()) {
5711 X86::CondCode CCode =
5712 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5713 CCode = X86::GetOppositeBranchCondition(CCode);
5714 CC = DAG.getConstant(CCode, MVT::i8);
5715 SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
5716 // Look for an unconditional branch following this conditional branch.
5717 // We need this because we need to reverse the successors in order
5718 // to implement FCMP_OEQ.
5719 if (User.getOpcode() == ISD::BR) {
5720 SDValue FalseBB = User.getOperand(1);
5722 DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
5723 assert(NewBR == User);
5726 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5727 Chain, Dest, CC, Cmp);
5728 X86::CondCode CCode =
5729 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
5730 CCode = X86::GetOppositeBranchCondition(CCode);
5731 CC = DAG.getConstant(CCode, MVT::i8);
5737 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
5738 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
5739 // It should be transformed during dag combiner except when the condition
5740 // is set by a arithmetics with overflow node.
5741 X86::CondCode CCode =
5742 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
5743 CCode = X86::GetOppositeBranchCondition(CCode);
5744 CC = DAG.getConstant(CCode, MVT::i8);
5745 Cond = Cond.getOperand(0).getOperand(1);
5751 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
5752 Cond = EmitTest(Cond, X86::COND_NE, DAG);
5754 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
5755 Chain, Dest, CC, Cond);
5759 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
5760 // Calls to _alloca is needed to probe the stack when allocating more than 4k
5761 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
5762 // that the guard pages used by the OS virtual memory manager are allocated in
5763 // correct sequence.
5765 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5766 SelectionDAG &DAG) {
5767 assert(Subtarget->isTargetCygMing() &&
5768 "This should be used only on Cygwin/Mingw targets");
5769 DebugLoc dl = Op.getDebugLoc();
5772 SDValue Chain = Op.getOperand(0);
5773 SDValue Size = Op.getOperand(1);
5774 // FIXME: Ensure alignment here
5778 MVT IntPtr = getPointerTy();
5779 MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
5781 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
5783 Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag);
5784 Flag = Chain.getValue(1);
5786 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
5787 SDValue Ops[] = { Chain,
5788 DAG.getTargetExternalSymbol("_alloca", IntPtr),
5789 DAG.getRegister(X86::EAX, IntPtr),
5790 DAG.getRegister(X86StackPtr, SPTy),
5792 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops, 5);
5793 Flag = Chain.getValue(1);
5795 Chain = DAG.getCALLSEQ_END(Chain,
5796 DAG.getIntPtrConstant(0, true),
5797 DAG.getIntPtrConstant(0, true),
5800 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1);
5802 SDValue Ops1[2] = { Chain.getValue(0), Chain };
5803 return DAG.getMergeValues(Ops1, 2, dl);
5807 X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
5809 SDValue Dst, SDValue Src,
5810 SDValue Size, unsigned Align,
5812 uint64_t DstSVOff) {
5813 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5815 // If not DWORD aligned or size is more than the threshold, call the library.
5816 // The libc version is likely to be faster for these cases. It can use the
5817 // address value and run time information about the CPU.
5818 if ((Align & 3) != 0 ||
5820 ConstantSize->getZExtValue() >
5821 getSubtarget()->getMaxInlineSizeThreshold()) {
5822 SDValue InFlag(0, 0);
5824 // Check to see if there is a specialized entry-point for memory zeroing.
5825 ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
5827 if (const char *bzeroEntry = V &&
5828 V->isNullValue() ? Subtarget->getBZeroEntry() : 0) {
5829 MVT IntPtr = getPointerTy();
5830 const Type *IntPtrTy = TD->getIntPtrType();
5831 TargetLowering::ArgListTy Args;
5832 TargetLowering::ArgListEntry Entry;
5834 Entry.Ty = IntPtrTy;
5835 Args.push_back(Entry);
5837 Args.push_back(Entry);
5838 std::pair<SDValue,SDValue> CallResult =
5839 LowerCallTo(Chain, Type::VoidTy, false, false, false, false,
5840 0, CallingConv::C, false, /*isReturnValueUsed=*/false,
5841 DAG.getExternalSymbol(bzeroEntry, IntPtr), Args, DAG, dl);
5842 return CallResult.second;
5845 // Otherwise have the target-independent code call memset.
5849 uint64_t SizeVal = ConstantSize->getZExtValue();
5850 SDValue InFlag(0, 0);
5853 ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
5854 unsigned BytesLeft = 0;
5855 bool TwoRepStos = false;
5858 uint64_t Val = ValC->getZExtValue() & 255;
5860 // If the value is a constant, then we can potentially use larger sets.
5861 switch (Align & 3) {
5862 case 2: // WORD aligned
5865 Val = (Val << 8) | Val;
5867 case 0: // DWORD aligned
5870 Val = (Val << 8) | Val;
5871 Val = (Val << 16) | Val;
5872 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
5875 Val = (Val << 32) | Val;
5878 default: // Byte aligned
5881 Count = DAG.getIntPtrConstant(SizeVal);
5885 if (AVT.bitsGT(MVT::i8)) {
5886 unsigned UBytes = AVT.getSizeInBits() / 8;
5887 Count = DAG.getIntPtrConstant(SizeVal / UBytes);
5888 BytesLeft = SizeVal % UBytes;
5891 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),
5893 InFlag = Chain.getValue(1);
5896 Count = DAG.getIntPtrConstant(SizeVal);
5897 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
5898 InFlag = Chain.getValue(1);
5901 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5904 InFlag = Chain.getValue(1);
5905 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5908 InFlag = Chain.getValue(1);
5910 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5911 SmallVector<SDValue, 8> Ops;
5912 Ops.push_back(Chain);
5913 Ops.push_back(DAG.getValueType(AVT));
5914 Ops.push_back(InFlag);
5915 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5918 InFlag = Chain.getValue(1);
5920 MVT CVT = Count.getValueType();
5921 SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
5922 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
5923 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
5926 InFlag = Chain.getValue(1);
5927 Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5929 Ops.push_back(Chain);
5930 Ops.push_back(DAG.getValueType(MVT::i8));
5931 Ops.push_back(InFlag);
5932 Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size());
5933 } else if (BytesLeft) {
5934 // Handle the last 1 - 7 bytes.
5935 unsigned Offset = SizeVal - BytesLeft;
5936 MVT AddrVT = Dst.getValueType();
5937 MVT SizeVT = Size.getValueType();
5939 Chain = DAG.getMemset(Chain, dl,
5940 DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
5941 DAG.getConstant(Offset, AddrVT)),
5943 DAG.getConstant(BytesLeft, SizeVT),
5944 Align, DstSV, DstSVOff + Offset);
5947 // TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
5952 X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
5953 SDValue Chain, SDValue Dst, SDValue Src,
5954 SDValue Size, unsigned Align,
5956 const Value *DstSV, uint64_t DstSVOff,
5957 const Value *SrcSV, uint64_t SrcSVOff) {
5958 // This requires the copy size to be a constant, preferrably
5959 // within a subtarget-specific limit.
5960 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
5963 uint64_t SizeVal = ConstantSize->getZExtValue();
5964 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
5967 /// If not DWORD aligned, call the library.
5968 if ((Align & 3) != 0)
5973 if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned
5976 unsigned UBytes = AVT.getSizeInBits() / 8;
5977 unsigned CountVal = SizeVal / UBytes;
5978 SDValue Count = DAG.getIntPtrConstant(CountVal);
5979 unsigned BytesLeft = SizeVal % UBytes;
5981 SDValue InFlag(0, 0);
5982 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RCX :
5985 InFlag = Chain.getValue(1);
5986 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RDI :
5989 InFlag = Chain.getValue(1);
5990 Chain = DAG.getCopyToReg(Chain, dl, Subtarget->is64Bit() ? X86::RSI :
5993 InFlag = Chain.getValue(1);
5995 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
5996 SmallVector<SDValue, 8> Ops;
5997 Ops.push_back(Chain);
5998 Ops.push_back(DAG.getValueType(AVT));
5999 Ops.push_back(InFlag);
6000 SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, &Ops[0], Ops.size());
6002 SmallVector<SDValue, 4> Results;
6003 Results.push_back(RepMovs);
6005 // Handle the last 1 - 7 bytes.
6006 unsigned Offset = SizeVal - BytesLeft;
6007 MVT DstVT = Dst.getValueType();
6008 MVT SrcVT = Src.getValueType();
6009 MVT SizeVT = Size.getValueType();
6010 Results.push_back(DAG.getMemcpy(Chain, dl,
6011 DAG.getNode(ISD::ADD, dl, DstVT, Dst,
6012 DAG.getConstant(Offset, DstVT)),
6013 DAG.getNode(ISD::ADD, dl, SrcVT, Src,
6014 DAG.getConstant(Offset, SrcVT)),
6015 DAG.getConstant(BytesLeft, SizeVT),
6016 Align, AlwaysInline,
6017 DstSV, DstSVOff + Offset,
6018 SrcSV, SrcSVOff + Offset));
6021 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6022 &Results[0], Results.size());
6025 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
6026 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
6027 DebugLoc dl = Op.getDebugLoc();
6029 if (!Subtarget->is64Bit()) {
6030 // vastart just stores the address of the VarArgsFrameIndex slot into the
6031 // memory location argument.
6032 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6033 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
6037 // gp_offset (0 - 6 * 8)
6038 // fp_offset (48 - 48 + 8 * 16)
6039 // overflow_arg_area (point to parameters coming in memory).
6041 SmallVector<SDValue, 8> MemOps;
6042 SDValue FIN = Op.getOperand(1);
6044 SDValue Store = DAG.getStore(Op.getOperand(0), dl,
6045 DAG.getConstant(VarArgsGPOffset, MVT::i32),
6047 MemOps.push_back(Store);
6050 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6051 FIN, DAG.getIntPtrConstant(4));
6052 Store = DAG.getStore(Op.getOperand(0), dl,
6053 DAG.getConstant(VarArgsFPOffset, MVT::i32),
6055 MemOps.push_back(Store);
6057 // Store ptr to overflow_arg_area
6058 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6059 FIN, DAG.getIntPtrConstant(4));
6060 SDValue OVFIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
6061 Store = DAG.getStore(Op.getOperand(0), dl, OVFIN, FIN, SV, 0);
6062 MemOps.push_back(Store);
6064 // Store ptr to reg_save_area.
6065 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(),
6066 FIN, DAG.getIntPtrConstant(8));
6067 SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy());
6068 Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0);
6069 MemOps.push_back(Store);
6070 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6071 &MemOps[0], MemOps.size());
6074 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) {
6075 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6076 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_arg!");
6077 SDValue Chain = Op.getOperand(0);
6078 SDValue SrcPtr = Op.getOperand(1);
6079 SDValue SrcSV = Op.getOperand(2);
6081 llvm_report_error("VAArgInst is not yet implemented for x86-64!");
6085 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) {
6086 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
6087 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
6088 SDValue Chain = Op.getOperand(0);
6089 SDValue DstPtr = Op.getOperand(1);
6090 SDValue SrcPtr = Op.getOperand(2);
6091 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
6092 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6093 DebugLoc dl = Op.getDebugLoc();
6095 return DAG.getMemcpy(Chain, dl, DstPtr, SrcPtr,
6096 DAG.getIntPtrConstant(24), 8, false,
6097 DstSV, 0, SrcSV, 0);
6101 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
6102 DebugLoc dl = Op.getDebugLoc();
6103 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6105 default: return SDValue(); // Don't custom lower most intrinsics.
6106 // Comparison intrinsics.
6107 case Intrinsic::x86_sse_comieq_ss:
6108 case Intrinsic::x86_sse_comilt_ss:
6109 case Intrinsic::x86_sse_comile_ss:
6110 case Intrinsic::x86_sse_comigt_ss:
6111 case Intrinsic::x86_sse_comige_ss:
6112 case Intrinsic::x86_sse_comineq_ss:
6113 case Intrinsic::x86_sse_ucomieq_ss:
6114 case Intrinsic::x86_sse_ucomilt_ss:
6115 case Intrinsic::x86_sse_ucomile_ss:
6116 case Intrinsic::x86_sse_ucomigt_ss:
6117 case Intrinsic::x86_sse_ucomige_ss:
6118 case Intrinsic::x86_sse_ucomineq_ss:
6119 case Intrinsic::x86_sse2_comieq_sd:
6120 case Intrinsic::x86_sse2_comilt_sd:
6121 case Intrinsic::x86_sse2_comile_sd:
6122 case Intrinsic::x86_sse2_comigt_sd:
6123 case Intrinsic::x86_sse2_comige_sd:
6124 case Intrinsic::x86_sse2_comineq_sd:
6125 case Intrinsic::x86_sse2_ucomieq_sd:
6126 case Intrinsic::x86_sse2_ucomilt_sd:
6127 case Intrinsic::x86_sse2_ucomile_sd:
6128 case Intrinsic::x86_sse2_ucomigt_sd:
6129 case Intrinsic::x86_sse2_ucomige_sd:
6130 case Intrinsic::x86_sse2_ucomineq_sd: {
6132 ISD::CondCode CC = ISD::SETCC_INVALID;
6135 case Intrinsic::x86_sse_comieq_ss:
6136 case Intrinsic::x86_sse2_comieq_sd:
6140 case Intrinsic::x86_sse_comilt_ss:
6141 case Intrinsic::x86_sse2_comilt_sd:
6145 case Intrinsic::x86_sse_comile_ss:
6146 case Intrinsic::x86_sse2_comile_sd:
6150 case Intrinsic::x86_sse_comigt_ss:
6151 case Intrinsic::x86_sse2_comigt_sd:
6155 case Intrinsic::x86_sse_comige_ss:
6156 case Intrinsic::x86_sse2_comige_sd:
6160 case Intrinsic::x86_sse_comineq_ss:
6161 case Intrinsic::x86_sse2_comineq_sd:
6165 case Intrinsic::x86_sse_ucomieq_ss:
6166 case Intrinsic::x86_sse2_ucomieq_sd:
6167 Opc = X86ISD::UCOMI;
6170 case Intrinsic::x86_sse_ucomilt_ss:
6171 case Intrinsic::x86_sse2_ucomilt_sd:
6172 Opc = X86ISD::UCOMI;
6175 case Intrinsic::x86_sse_ucomile_ss:
6176 case Intrinsic::x86_sse2_ucomile_sd:
6177 Opc = X86ISD::UCOMI;
6180 case Intrinsic::x86_sse_ucomigt_ss:
6181 case Intrinsic::x86_sse2_ucomigt_sd:
6182 Opc = X86ISD::UCOMI;
6185 case Intrinsic::x86_sse_ucomige_ss:
6186 case Intrinsic::x86_sse2_ucomige_sd:
6187 Opc = X86ISD::UCOMI;
6190 case Intrinsic::x86_sse_ucomineq_ss:
6191 case Intrinsic::x86_sse2_ucomineq_sd:
6192 Opc = X86ISD::UCOMI;
6197 SDValue LHS = Op.getOperand(1);
6198 SDValue RHS = Op.getOperand(2);
6199 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
6200 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
6201 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
6202 DAG.getConstant(X86CC, MVT::i8), Cond);
6203 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6205 // ptest intrinsics. The intrinsic these come from are designed to return
6206 // an integer value, not just an instruction so lower it to the ptest
6207 // pattern and a setcc for the result.
6208 case Intrinsic::x86_sse41_ptestz:
6209 case Intrinsic::x86_sse41_ptestc:
6210 case Intrinsic::x86_sse41_ptestnzc:{
6213 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
6214 case Intrinsic::x86_sse41_ptestz:
6216 X86CC = X86::COND_E;
6218 case Intrinsic::x86_sse41_ptestc:
6220 X86CC = X86::COND_B;
6222 case Intrinsic::x86_sse41_ptestnzc:
6224 X86CC = X86::COND_A;
6228 SDValue LHS = Op.getOperand(1);
6229 SDValue RHS = Op.getOperand(2);
6230 SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS);
6231 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
6232 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
6233 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
6236 // Fix vector shift instructions where the last operand is a non-immediate
6238 case Intrinsic::x86_sse2_pslli_w:
6239 case Intrinsic::x86_sse2_pslli_d:
6240 case Intrinsic::x86_sse2_pslli_q:
6241 case Intrinsic::x86_sse2_psrli_w:
6242 case Intrinsic::x86_sse2_psrli_d:
6243 case Intrinsic::x86_sse2_psrli_q:
6244 case Intrinsic::x86_sse2_psrai_w:
6245 case Intrinsic::x86_sse2_psrai_d:
6246 case Intrinsic::x86_mmx_pslli_w:
6247 case Intrinsic::x86_mmx_pslli_d:
6248 case Intrinsic::x86_mmx_pslli_q:
6249 case Intrinsic::x86_mmx_psrli_w:
6250 case Intrinsic::x86_mmx_psrli_d:
6251 case Intrinsic::x86_mmx_psrli_q:
6252 case Intrinsic::x86_mmx_psrai_w:
6253 case Intrinsic::x86_mmx_psrai_d: {
6254 SDValue ShAmt = Op.getOperand(2);
6255 if (isa<ConstantSDNode>(ShAmt))
6258 unsigned NewIntNo = 0;
6259 MVT ShAmtVT = MVT::v4i32;
6261 case Intrinsic::x86_sse2_pslli_w:
6262 NewIntNo = Intrinsic::x86_sse2_psll_w;
6264 case Intrinsic::x86_sse2_pslli_d:
6265 NewIntNo = Intrinsic::x86_sse2_psll_d;
6267 case Intrinsic::x86_sse2_pslli_q:
6268 NewIntNo = Intrinsic::x86_sse2_psll_q;
6270 case Intrinsic::x86_sse2_psrli_w:
6271 NewIntNo = Intrinsic::x86_sse2_psrl_w;
6273 case Intrinsic::x86_sse2_psrli_d:
6274 NewIntNo = Intrinsic::x86_sse2_psrl_d;
6276 case Intrinsic::x86_sse2_psrli_q:
6277 NewIntNo = Intrinsic::x86_sse2_psrl_q;
6279 case Intrinsic::x86_sse2_psrai_w:
6280 NewIntNo = Intrinsic::x86_sse2_psra_w;
6282 case Intrinsic::x86_sse2_psrai_d:
6283 NewIntNo = Intrinsic::x86_sse2_psra_d;
6286 ShAmtVT = MVT::v2i32;
6288 case Intrinsic::x86_mmx_pslli_w:
6289 NewIntNo = Intrinsic::x86_mmx_psll_w;
6291 case Intrinsic::x86_mmx_pslli_d:
6292 NewIntNo = Intrinsic::x86_mmx_psll_d;
6294 case Intrinsic::x86_mmx_pslli_q:
6295 NewIntNo = Intrinsic::x86_mmx_psll_q;
6297 case Intrinsic::x86_mmx_psrli_w:
6298 NewIntNo = Intrinsic::x86_mmx_psrl_w;
6300 case Intrinsic::x86_mmx_psrli_d:
6301 NewIntNo = Intrinsic::x86_mmx_psrl_d;
6303 case Intrinsic::x86_mmx_psrli_q:
6304 NewIntNo = Intrinsic::x86_mmx_psrl_q;
6306 case Intrinsic::x86_mmx_psrai_w:
6307 NewIntNo = Intrinsic::x86_mmx_psra_w;
6309 case Intrinsic::x86_mmx_psrai_d:
6310 NewIntNo = Intrinsic::x86_mmx_psra_d;
6312 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
6317 MVT VT = Op.getValueType();
6318 ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
6319 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
6320 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6321 DAG.getConstant(NewIntNo, MVT::i32),
6322 Op.getOperand(1), ShAmt);
6327 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
6328 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6329 DebugLoc dl = Op.getDebugLoc();
6332 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6334 DAG.getConstant(TD->getPointerSize(),
6335 Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
6336 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6337 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6342 // Just load the return address.
6343 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
6344 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6345 RetAddrFI, NULL, 0);
6348 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
6349 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6350 MFI->setFrameAddressIsTaken(true);
6351 MVT VT = Op.getValueType();
6352 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
6353 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6354 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP;
6355 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
6357 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
6361 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
6362 SelectionDAG &DAG) {
6363 return DAG.getIntPtrConstant(2*TD->getPointerSize());
6366 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
6368 MachineFunction &MF = DAG.getMachineFunction();
6369 SDValue Chain = Op.getOperand(0);
6370 SDValue Offset = Op.getOperand(1);
6371 SDValue Handler = Op.getOperand(2);
6372 DebugLoc dl = Op.getDebugLoc();
6374 SDValue Frame = DAG.getRegister(Subtarget->is64Bit() ? X86::RBP : X86::EBP,
6376 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX);
6378 SDValue StoreAddr = DAG.getNode(ISD::SUB, dl, getPointerTy(), Frame,
6379 DAG.getIntPtrConstant(-TD->getPointerSize()));
6380 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset);
6381 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, NULL, 0);
6382 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
6383 MF.getRegInfo().addLiveOut(StoreAddrReg);
6385 return DAG.getNode(X86ISD::EH_RETURN, dl,
6387 Chain, DAG.getRegister(StoreAddrReg, getPointerTy()));
6390 SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op,
6391 SelectionDAG &DAG) {
6392 SDValue Root = Op.getOperand(0);
6393 SDValue Trmp = Op.getOperand(1); // trampoline
6394 SDValue FPtr = Op.getOperand(2); // nested function
6395 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
6396 DebugLoc dl = Op.getDebugLoc();
6398 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
6400 const X86InstrInfo *TII =
6401 ((X86TargetMachine&)getTargetMachine()).getInstrInfo();
6403 if (Subtarget->is64Bit()) {
6404 SDValue OutChains[6];
6406 // Large code-model.
6408 const unsigned char JMP64r = TII->getBaseOpcodeFor(X86::JMP64r);
6409 const unsigned char MOV64ri = TII->getBaseOpcodeFor(X86::MOV64ri);
6411 const unsigned char N86R10 = RegInfo->getX86RegNum(X86::R10);
6412 const unsigned char N86R11 = RegInfo->getX86RegNum(X86::R11);
6414 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
6416 // Load the pointer to the nested function into R11.
6417 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
6418 SDValue Addr = Trmp;
6419 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6422 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6423 DAG.getConstant(2, MVT::i64));
6424 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2);
6426 // Load the 'nest' parameter value into R10.
6427 // R10 is specified in X86CallingConv.td
6428 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
6429 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6430 DAG.getConstant(10, MVT::i64));
6431 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6432 Addr, TrmpAddr, 10);
6434 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6435 DAG.getConstant(12, MVT::i64));
6436 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2);
6438 // Jump to the nested function.
6439 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
6440 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6441 DAG.getConstant(20, MVT::i64));
6442 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
6443 Addr, TrmpAddr, 20);
6445 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
6446 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
6447 DAG.getConstant(22, MVT::i64));
6448 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
6452 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) };
6453 return DAG.getMergeValues(Ops, 2, dl);
6455 const Function *Func =
6456 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
6457 unsigned CC = Func->getCallingConv();
6462 llvm_unreachable("Unsupported calling convention");
6463 case CallingConv::C:
6464 case CallingConv::X86_StdCall: {
6465 // Pass 'nest' parameter in ECX.
6466 // Must be kept in sync with X86CallingConv.td
6469 // Check that ECX wasn't needed by an 'inreg' parameter.
6470 const FunctionType *FTy = Func->getFunctionType();
6471 const AttrListPtr &Attrs = Func->getAttributes();
6473 if (!Attrs.isEmpty() && !Func->isVarArg()) {
6474 unsigned InRegCount = 0;
6477 for (FunctionType::param_iterator I = FTy->param_begin(),
6478 E = FTy->param_end(); I != E; ++I, ++Idx)
6479 if (Attrs.paramHasAttr(Idx, Attribute::InReg))
6480 // FIXME: should only count parameters that are lowered to integers.
6481 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
6483 if (InRegCount > 2) {
6484 llvm_report_error("Nest register in use - reduce number of inreg parameters!");
6489 case CallingConv::X86_FastCall:
6490 case CallingConv::Fast:
6491 // Pass 'nest' parameter in EAX.
6492 // Must be kept in sync with X86CallingConv.td
6497 SDValue OutChains[4];
6500 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6501 DAG.getConstant(10, MVT::i32));
6502 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
6504 const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri);
6505 const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg);
6506 OutChains[0] = DAG.getStore(Root, dl,
6507 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
6510 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6511 DAG.getConstant(1, MVT::i32));
6512 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1);
6514 const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP);
6515 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6516 DAG.getConstant(5, MVT::i32));
6517 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
6518 TrmpAddr, 5, false, 1);
6520 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
6521 DAG.getConstant(6, MVT::i32));
6522 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1);
6525 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) };
6526 return DAG.getMergeValues(Ops, 2, dl);
6530 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
6532 The rounding mode is in bits 11:10 of FPSR, and has the following
6539 FLT_ROUNDS, on the other hand, expects the following:
6546 To perform the conversion, we do:
6547 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
6550 MachineFunction &MF = DAG.getMachineFunction();
6551 const TargetMachine &TM = MF.getTarget();
6552 const TargetFrameInfo &TFI = *TM.getFrameInfo();
6553 unsigned StackAlignment = TFI.getStackAlignment();
6554 MVT VT = Op.getValueType();
6555 DebugLoc dl = Op.getDebugLoc();
6557 // Save FP Control Word to stack slot
6558 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment);
6559 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
6561 SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other,
6562 DAG.getEntryNode(), StackSlot);
6564 // Load FP Control Word from stack slot
6565 SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0);
6567 // Transform as necessary
6569 DAG.getNode(ISD::SRL, dl, MVT::i16,
6570 DAG.getNode(ISD::AND, dl, MVT::i16,
6571 CWD, DAG.getConstant(0x800, MVT::i16)),
6572 DAG.getConstant(11, MVT::i8));
6574 DAG.getNode(ISD::SRL, dl, MVT::i16,
6575 DAG.getNode(ISD::AND, dl, MVT::i16,
6576 CWD, DAG.getConstant(0x400, MVT::i16)),
6577 DAG.getConstant(9, MVT::i8));
6580 DAG.getNode(ISD::AND, dl, MVT::i16,
6581 DAG.getNode(ISD::ADD, dl, MVT::i16,
6582 DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2),
6583 DAG.getConstant(1, MVT::i16)),
6584 DAG.getConstant(3, MVT::i16));
6587 return DAG.getNode((VT.getSizeInBits() < 16 ?
6588 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6591 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
6592 MVT VT = Op.getValueType();
6594 unsigned NumBits = VT.getSizeInBits();
6595 DebugLoc dl = Op.getDebugLoc();
6597 Op = Op.getOperand(0);
6598 if (VT == MVT::i8) {
6599 // Zero extend to i32 since there is not an i8 bsr.
6601 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6604 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
6605 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6606 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
6608 // If src is zero (i.e. bsr sets ZF), returns NumBits.
6609 SmallVector<SDValue, 4> Ops;
6611 Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT));
6612 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6613 Ops.push_back(Op.getValue(1));
6614 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6616 // Finally xor with NumBits-1.
6617 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
6620 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6624 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
6625 MVT VT = Op.getValueType();
6627 unsigned NumBits = VT.getSizeInBits();
6628 DebugLoc dl = Op.getDebugLoc();
6630 Op = Op.getOperand(0);
6631 if (VT == MVT::i8) {
6633 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
6636 // Issue a bsf (scan bits forward) which also sets EFLAGS.
6637 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
6638 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
6640 // If src is zero (i.e. bsf sets ZF), returns NumBits.
6641 SmallVector<SDValue, 4> Ops;
6643 Ops.push_back(DAG.getConstant(NumBits, OpVT));
6644 Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8));
6645 Ops.push_back(Op.getValue(1));
6646 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4);
6649 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
6653 SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) {
6654 MVT VT = Op.getValueType();
6655 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply");
6656 DebugLoc dl = Op.getDebugLoc();
6658 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32);
6659 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32);
6660 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b );
6661 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi );
6662 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b );
6664 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 );
6665 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
6666 // return AloBlo + AloBhi + AhiBlo;
6668 SDValue A = Op.getOperand(0);
6669 SDValue B = Op.getOperand(1);
6671 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6672 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6673 A, DAG.getConstant(32, MVT::i32));
6674 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6675 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
6676 B, DAG.getConstant(32, MVT::i32));
6677 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6678 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6680 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6681 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6683 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6684 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
6686 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6687 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6688 AloBhi, DAG.getConstant(32, MVT::i32));
6689 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
6690 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
6691 AhiBlo, DAG.getConstant(32, MVT::i32));
6692 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
6693 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
6698 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) {
6699 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
6700 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
6701 // looks for this combo and may remove the "setcc" instruction if the "setcc"
6702 // has only one use.
6703 SDNode *N = Op.getNode();
6704 SDValue LHS = N->getOperand(0);
6705 SDValue RHS = N->getOperand(1);
6706 unsigned BaseOp = 0;
6708 DebugLoc dl = Op.getDebugLoc();
6710 switch (Op.getOpcode()) {
6711 default: llvm_unreachable("Unknown ovf instruction!");
6713 // A subtract of one will be selected as a INC. Note that INC doesn't
6714 // set CF, so we can't do this for UADDO.
6715 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6716 if (C->getAPIntValue() == 1) {
6717 BaseOp = X86ISD::INC;
6721 BaseOp = X86ISD::ADD;
6725 BaseOp = X86ISD::ADD;
6729 // A subtract of one will be selected as a DEC. Note that DEC doesn't
6730 // set CF, so we can't do this for USUBO.
6731 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
6732 if (C->getAPIntValue() == 1) {
6733 BaseOp = X86ISD::DEC;
6737 BaseOp = X86ISD::SUB;
6741 BaseOp = X86ISD::SUB;
6745 BaseOp = X86ISD::SMUL;
6749 BaseOp = X86ISD::UMUL;
6754 // Also sets EFLAGS.
6755 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
6756 SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS);
6759 DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1),
6760 DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1));
6762 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC);
6766 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) {
6767 MVT T = Op.getValueType();
6768 DebugLoc dl = Op.getDebugLoc();
6771 switch(T.getSimpleVT()) {
6773 assert(false && "Invalid value type!");
6774 case MVT::i8: Reg = X86::AL; size = 1; break;
6775 case MVT::i16: Reg = X86::AX; size = 2; break;
6776 case MVT::i32: Reg = X86::EAX; size = 4; break;
6778 assert(Subtarget->is64Bit() && "Node not type legal!");
6779 Reg = X86::RAX; size = 8;
6782 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), dl, Reg,
6783 Op.getOperand(2), SDValue());
6784 SDValue Ops[] = { cpIn.getValue(0),
6787 DAG.getTargetConstant(size, MVT::i8),
6789 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6790 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5);
6792 DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1));
6796 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op,
6797 SelectionDAG &DAG) {
6798 assert(Subtarget->is64Bit() && "Result not type legalized?");
6799 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6800 SDValue TheChain = Op.getOperand(0);
6801 DebugLoc dl = Op.getDebugLoc();
6802 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6803 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
6804 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
6806 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
6807 DAG.getConstant(32, MVT::i8));
6809 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
6812 return DAG.getMergeValues(Ops, 2, dl);
6815 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
6816 SDNode *Node = Op.getNode();
6817 DebugLoc dl = Node->getDebugLoc();
6818 MVT T = Node->getValueType(0);
6819 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
6820 DAG.getConstant(0, T), Node->getOperand(2));
6821 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
6822 cast<AtomicSDNode>(Node)->getMemoryVT(),
6823 Node->getOperand(0),
6824 Node->getOperand(1), negOp,
6825 cast<AtomicSDNode>(Node)->getSrcValue(),
6826 cast<AtomicSDNode>(Node)->getAlignment());
6829 /// LowerOperation - Provide custom lowering hooks for some operations.
6831 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
6832 switch (Op.getOpcode()) {
6833 default: llvm_unreachable("Should not custom lower this!");
6834 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG);
6835 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
6836 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6837 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6838 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6839 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6840 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6841 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6842 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6843 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6844 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
6845 case ISD::SHL_PARTS:
6846 case ISD::SRA_PARTS:
6847 case ISD::SRL_PARTS: return LowerShift(Op, DAG);
6848 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
6849 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
6850 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
6851 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
6852 case ISD::FABS: return LowerFABS(Op, DAG);
6853 case ISD::FNEG: return LowerFNEG(Op, DAG);
6854 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6855 case ISD::SETCC: return LowerSETCC(Op, DAG);
6856 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
6857 case ISD::SELECT: return LowerSELECT(Op, DAG);
6858 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
6859 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6860 case ISD::VASTART: return LowerVASTART(Op, DAG);
6861 case ISD::VAARG: return LowerVAARG(Op, DAG);
6862 case ISD::VACOPY: return LowerVACOPY(Op, DAG);
6863 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6864 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6865 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6866 case ISD::FRAME_TO_ARGS_OFFSET:
6867 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
6868 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
6869 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
6870 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
6871 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6872 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
6873 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
6874 case ISD::MUL: return LowerMUL_V2I64(Op, DAG);
6880 case ISD::UMULO: return LowerXALUO(Op, DAG);
6881 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG);
6885 void X86TargetLowering::
6886 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
6887 SelectionDAG &DAG, unsigned NewOp) {
6888 MVT T = Node->getValueType(0);
6889 DebugLoc dl = Node->getDebugLoc();
6890 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
6892 SDValue Chain = Node->getOperand(0);
6893 SDValue In1 = Node->getOperand(1);
6894 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6895 Node->getOperand(2), DAG.getIntPtrConstant(0));
6896 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6897 Node->getOperand(2), DAG.getIntPtrConstant(1));
6898 // This is a generalized SDNode, not an AtomicSDNode, so it doesn't
6899 // have a MemOperand. Pass the info through as a normal operand.
6900 SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand());
6901 SDValue Ops[] = { Chain, In1, In2L, In2H, LSI };
6902 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6903 SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5);
6904 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
6905 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6906 Results.push_back(Result.getValue(2));
6909 /// ReplaceNodeResults - Replace a node with an illegal result type
6910 /// with a new node built out of custom code.
6911 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
6912 SmallVectorImpl<SDValue>&Results,
6913 SelectionDAG &DAG) {
6914 DebugLoc dl = N->getDebugLoc();
6915 switch (N->getOpcode()) {
6917 assert(false && "Do not know how to custom type legalize this operation!");
6919 case ISD::FP_TO_SINT: {
6920 std::pair<SDValue,SDValue> Vals =
6921 FP_TO_INTHelper(SDValue(N, 0), DAG, true);
6922 SDValue FIST = Vals.first, StackSlot = Vals.second;
6923 if (FIST.getNode() != 0) {
6924 MVT VT = N->getValueType(0);
6925 // Return a load from the stack slot.
6926 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0));
6930 case ISD::READCYCLECOUNTER: {
6931 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6932 SDValue TheChain = N->getOperand(0);
6933 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
6934 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
6936 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
6938 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
6939 SDValue Ops[] = { eax, edx };
6940 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2));
6941 Results.push_back(edx.getValue(1));
6944 case ISD::ATOMIC_CMP_SWAP: {
6945 MVT T = N->getValueType(0);
6946 assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
6947 SDValue cpInL, cpInH;
6948 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6949 DAG.getConstant(0, MVT::i32));
6950 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2),
6951 DAG.getConstant(1, MVT::i32));
6952 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue());
6953 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH,
6955 SDValue swapInL, swapInH;
6956 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6957 DAG.getConstant(0, MVT::i32));
6958 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3),
6959 DAG.getConstant(1, MVT::i32));
6960 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL,
6962 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH,
6963 swapInL.getValue(1));
6964 SDValue Ops[] = { swapInH.getValue(0),
6966 swapInH.getValue(1) };
6967 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag);
6968 SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3);
6969 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX,
6970 MVT::i32, Result.getValue(1));
6971 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX,
6972 MVT::i32, cpOutL.getValue(2));
6973 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
6974 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6975 Results.push_back(cpOutH.getValue(1));
6978 case ISD::ATOMIC_LOAD_ADD:
6979 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
6981 case ISD::ATOMIC_LOAD_AND:
6982 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
6984 case ISD::ATOMIC_LOAD_NAND:
6985 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
6987 case ISD::ATOMIC_LOAD_OR:
6988 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
6990 case ISD::ATOMIC_LOAD_SUB:
6991 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
6993 case ISD::ATOMIC_LOAD_XOR:
6994 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
6996 case ISD::ATOMIC_SWAP:
6997 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
7002 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
7004 default: return NULL;
7005 case X86ISD::BSF: return "X86ISD::BSF";
7006 case X86ISD::BSR: return "X86ISD::BSR";
7007 case X86ISD::SHLD: return "X86ISD::SHLD";
7008 case X86ISD::SHRD: return "X86ISD::SHRD";
7009 case X86ISD::FAND: return "X86ISD::FAND";
7010 case X86ISD::FOR: return "X86ISD::FOR";
7011 case X86ISD::FXOR: return "X86ISD::FXOR";
7012 case X86ISD::FSRL: return "X86ISD::FSRL";
7013 case X86ISD::FILD: return "X86ISD::FILD";
7014 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
7015 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
7016 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
7017 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
7018 case X86ISD::FLD: return "X86ISD::FLD";
7019 case X86ISD::FST: return "X86ISD::FST";
7020 case X86ISD::CALL: return "X86ISD::CALL";
7021 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
7022 case X86ISD::BT: return "X86ISD::BT";
7023 case X86ISD::CMP: return "X86ISD::CMP";
7024 case X86ISD::COMI: return "X86ISD::COMI";
7025 case X86ISD::UCOMI: return "X86ISD::UCOMI";
7026 case X86ISD::SETCC: return "X86ISD::SETCC";
7027 case X86ISD::CMOV: return "X86ISD::CMOV";
7028 case X86ISD::BRCOND: return "X86ISD::BRCOND";
7029 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
7030 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
7031 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
7032 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
7033 case X86ISD::Wrapper: return "X86ISD::Wrapper";
7034 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
7035 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
7036 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
7037 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
7038 case X86ISD::PINSRB: return "X86ISD::PINSRB";
7039 case X86ISD::PINSRW: return "X86ISD::PINSRW";
7040 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
7041 case X86ISD::FMAX: return "X86ISD::FMAX";
7042 case X86ISD::FMIN: return "X86ISD::FMIN";
7043 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
7044 case X86ISD::FRCP: return "X86ISD::FRCP";
7045 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
7046 case X86ISD::SegmentBaseAddress: return "X86ISD::SegmentBaseAddress";
7047 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
7048 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
7049 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
7050 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
7051 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
7052 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
7053 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
7054 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
7055 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
7056 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
7057 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
7058 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
7059 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
7060 case X86ISD::VSHL: return "X86ISD::VSHL";
7061 case X86ISD::VSRL: return "X86ISD::VSRL";
7062 case X86ISD::CMPPD: return "X86ISD::CMPPD";
7063 case X86ISD::CMPPS: return "X86ISD::CMPPS";
7064 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
7065 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
7066 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
7067 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
7068 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
7069 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
7070 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
7071 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
7072 case X86ISD::ADD: return "X86ISD::ADD";
7073 case X86ISD::SUB: return "X86ISD::SUB";
7074 case X86ISD::SMUL: return "X86ISD::SMUL";
7075 case X86ISD::UMUL: return "X86ISD::UMUL";
7076 case X86ISD::INC: return "X86ISD::INC";
7077 case X86ISD::DEC: return "X86ISD::DEC";
7078 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
7079 case X86ISD::PTEST: return "X86ISD::PTEST";
7083 // isLegalAddressingMode - Return true if the addressing mode represented
7084 // by AM is legal for this target, for a load/store of the specified type.
7085 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
7086 const Type *Ty) const {
7087 // X86 supports extremely general addressing modes.
7088 CodeModel::Model M = getTargetMachine().getCodeModel();
7090 // X86 allows a sign-extended 32-bit immediate field as a displacement.
7091 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
7096 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
7098 // If a reference to this global requires an extra load, we can't fold it.
7099 if (isGlobalStubReference(GVFlags))
7102 // If BaseGV requires a register for the PIC base, we cannot also have a
7103 // BaseReg specified.
7104 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
7107 // If lower 4G is not available, then we must use rip-relative addressing.
7108 if (Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
7118 // These scales always work.
7123 // These scales are formed with basereg+scalereg. Only accept if there is
7128 default: // Other stuff never works.
7136 bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const {
7137 if (!Ty1->isInteger() || !Ty2->isInteger())
7139 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
7140 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
7141 if (NumBits1 <= NumBits2)
7143 return Subtarget->is64Bit() || NumBits1 < 64;
7146 bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const {
7147 if (!VT1.isInteger() || !VT2.isInteger())
7149 unsigned NumBits1 = VT1.getSizeInBits();
7150 unsigned NumBits2 = VT2.getSizeInBits();
7151 if (NumBits1 <= NumBits2)
7153 return Subtarget->is64Bit() || NumBits1 < 64;
7156 bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const {
7157 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7158 return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit();
7161 bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const {
7162 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
7163 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
7166 bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const {
7167 // i16 instructions are longer (0x66 prefix) and potentially slower.
7168 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
7171 /// isShuffleMaskLegal - Targets can use this to indicate that they only
7172 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
7173 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
7174 /// are assumed to be legal.
7176 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
7178 // Only do shuffles on 128-bit vector types for now.
7179 if (VT.getSizeInBits() == 64)
7182 // FIXME: pshufb, blends, palignr, shifts.
7183 return (VT.getVectorNumElements() == 2 ||
7184 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
7185 isMOVLMask(M, VT) ||
7186 isSHUFPMask(M, VT) ||
7187 isPSHUFDMask(M, VT) ||
7188 isPSHUFHWMask(M, VT) ||
7189 isPSHUFLWMask(M, VT) ||
7190 isUNPCKLMask(M, VT) ||
7191 isUNPCKHMask(M, VT) ||
7192 isUNPCKL_v_undef_Mask(M, VT) ||
7193 isUNPCKH_v_undef_Mask(M, VT));
7197 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
7199 unsigned NumElts = VT.getVectorNumElements();
7200 // FIXME: This collection of masks seems suspect.
7203 if (NumElts == 4 && VT.getSizeInBits() == 128) {
7204 return (isMOVLMask(Mask, VT) ||
7205 isCommutedMOVLMask(Mask, VT, true) ||
7206 isSHUFPMask(Mask, VT) ||
7207 isCommutedSHUFPMask(Mask, VT));
7212 //===----------------------------------------------------------------------===//
7213 // X86 Scheduler Hooks
7214 //===----------------------------------------------------------------------===//
7216 // private utility function
7218 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
7219 MachineBasicBlock *MBB,
7227 TargetRegisterClass *RC,
7228 bool invSrc) const {
7229 // For the atomic bitwise operator, we generate
7232 // ld t1 = [bitinstr.addr]
7233 // op t2 = t1, [bitinstr.val]
7235 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7237 // fallthrough -->nextMBB
7238 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7239 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7240 MachineFunction::iterator MBBIter = MBB;
7243 /// First build the CFG
7244 MachineFunction *F = MBB->getParent();
7245 MachineBasicBlock *thisMBB = MBB;
7246 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7247 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7248 F->insert(MBBIter, newMBB);
7249 F->insert(MBBIter, nextMBB);
7251 // Move all successors to thisMBB to nextMBB
7252 nextMBB->transferSuccessors(thisMBB);
7254 // Update thisMBB to fall through to newMBB
7255 thisMBB->addSuccessor(newMBB);
7257 // newMBB jumps to itself and fall through to nextMBB
7258 newMBB->addSuccessor(nextMBB);
7259 newMBB->addSuccessor(newMBB);
7261 // Insert instructions into newMBB based on incoming instruction
7262 assert(bInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7263 "unexpected number of operands");
7264 DebugLoc dl = bInstr->getDebugLoc();
7265 MachineOperand& destOper = bInstr->getOperand(0);
7266 MachineOperand* argOpers[2 + X86AddrNumOperands];
7267 int numArgs = bInstr->getNumOperands() - 1;
7268 for (int i=0; i < numArgs; ++i)
7269 argOpers[i] = &bInstr->getOperand(i+1);
7271 // x86 address has 4 operands: base, index, scale, and displacement
7272 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7273 int valArgIndx = lastAddrIndx + 1;
7275 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7276 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1);
7277 for (int i=0; i <= lastAddrIndx; ++i)
7278 (*MIB).addOperand(*argOpers[i]);
7280 unsigned tt = F->getRegInfo().createVirtualRegister(RC);
7282 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
7287 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7288 assert((argOpers[valArgIndx]->isReg() ||
7289 argOpers[valArgIndx]->isImm()) &&
7291 if (argOpers[valArgIndx]->isReg())
7292 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
7294 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
7296 (*MIB).addOperand(*argOpers[valArgIndx]);
7298 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), EAXreg);
7301 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
7302 for (int i=0; i <= lastAddrIndx; ++i)
7303 (*MIB).addOperand(*argOpers[i]);
7305 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7306 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7308 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), destOper.getReg());
7312 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7314 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7318 // private utility function: 64 bit atomics on 32 bit host.
7320 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
7321 MachineBasicBlock *MBB,
7326 bool invSrc) const {
7327 // For the atomic bitwise operator, we generate
7328 // thisMBB (instructions are in pairs, except cmpxchg8b)
7329 // ld t1,t2 = [bitinstr.addr]
7331 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
7332 // op t5, t6 <- out1, out2, [bitinstr.val]
7333 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
7334 // mov ECX, EBX <- t5, t6
7335 // mov EAX, EDX <- t1, t2
7336 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
7337 // mov t3, t4 <- EAX, EDX
7339 // result in out1, out2
7340 // fallthrough -->nextMBB
7342 const TargetRegisterClass *RC = X86::GR32RegisterClass;
7343 const unsigned LoadOpc = X86::MOV32rm;
7344 const unsigned copyOpc = X86::MOV32rr;
7345 const unsigned NotOpc = X86::NOT32r;
7346 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7347 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7348 MachineFunction::iterator MBBIter = MBB;
7351 /// First build the CFG
7352 MachineFunction *F = MBB->getParent();
7353 MachineBasicBlock *thisMBB = MBB;
7354 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7355 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7356 F->insert(MBBIter, newMBB);
7357 F->insert(MBBIter, nextMBB);
7359 // Move all successors to thisMBB to nextMBB
7360 nextMBB->transferSuccessors(thisMBB);
7362 // Update thisMBB to fall through to newMBB
7363 thisMBB->addSuccessor(newMBB);
7365 // newMBB jumps to itself and fall through to nextMBB
7366 newMBB->addSuccessor(nextMBB);
7367 newMBB->addSuccessor(newMBB);
7369 DebugLoc dl = bInstr->getDebugLoc();
7370 // Insert instructions into newMBB based on incoming instruction
7371 // There are 8 "real" operands plus 9 implicit def/uses, ignored here.
7372 assert(bInstr->getNumOperands() < X86AddrNumOperands + 14 &&
7373 "unexpected number of operands");
7374 MachineOperand& dest1Oper = bInstr->getOperand(0);
7375 MachineOperand& dest2Oper = bInstr->getOperand(1);
7376 MachineOperand* argOpers[2 + X86AddrNumOperands];
7377 for (int i=0; i < 2 + X86AddrNumOperands; ++i)
7378 argOpers[i] = &bInstr->getOperand(i+2);
7380 // x86 address has 4 operands: base, index, scale, and displacement
7381 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7383 unsigned t1 = F->getRegInfo().createVirtualRegister(RC);
7384 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1);
7385 for (int i=0; i <= lastAddrIndx; ++i)
7386 (*MIB).addOperand(*argOpers[i]);
7387 unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
7388 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2);
7389 // add 4 to displacement.
7390 for (int i=0; i <= lastAddrIndx-2; ++i)
7391 (*MIB).addOperand(*argOpers[i]);
7392 MachineOperand newOp3 = *(argOpers[3]);
7394 newOp3.setImm(newOp3.getImm()+4);
7396 newOp3.setOffset(newOp3.getOffset()+4);
7397 (*MIB).addOperand(newOp3);
7398 (*MIB).addOperand(*argOpers[lastAddrIndx]);
7400 // t3/4 are defined later, at the bottom of the loop
7401 unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
7402 unsigned t4 = F->getRegInfo().createVirtualRegister(RC);
7403 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg())
7404 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB);
7405 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg())
7406 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
7408 unsigned tt1 = F->getRegInfo().createVirtualRegister(RC);
7409 unsigned tt2 = F->getRegInfo().createVirtualRegister(RC);
7411 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt1).addReg(t1);
7412 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), tt2).addReg(t2);
7418 int valArgIndx = lastAddrIndx + 1;
7419 assert((argOpers[valArgIndx]->isReg() ||
7420 argOpers[valArgIndx]->isImm()) &&
7422 unsigned t5 = F->getRegInfo().createVirtualRegister(RC);
7423 unsigned t6 = F->getRegInfo().createVirtualRegister(RC);
7424 if (argOpers[valArgIndx]->isReg())
7425 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5);
7427 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5);
7428 if (regOpcL != X86::MOV32rr)
7430 (*MIB).addOperand(*argOpers[valArgIndx]);
7431 assert(argOpers[valArgIndx + 1]->isReg() ==
7432 argOpers[valArgIndx]->isReg());
7433 assert(argOpers[valArgIndx + 1]->isImm() ==
7434 argOpers[valArgIndx]->isImm());
7435 if (argOpers[valArgIndx + 1]->isReg())
7436 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6);
7438 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6);
7439 if (regOpcH != X86::MOV32rr)
7441 (*MIB).addOperand(*argOpers[valArgIndx + 1]);
7443 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EAX);
7445 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EDX);
7448 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::EBX);
7450 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), X86::ECX);
7453 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
7454 for (int i=0; i <= lastAddrIndx; ++i)
7455 (*MIB).addOperand(*argOpers[i]);
7457 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7458 (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
7460 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t3);
7461 MIB.addReg(X86::EAX);
7462 MIB = BuildMI(newMBB, dl, TII->get(copyOpc), t4);
7463 MIB.addReg(X86::EDX);
7466 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7468 F->DeleteMachineInstr(bInstr); // The pseudo instruction is gone now.
7472 // private utility function
7474 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr,
7475 MachineBasicBlock *MBB,
7476 unsigned cmovOpc) const {
7477 // For the atomic min/max operator, we generate
7480 // ld t1 = [min/max.addr]
7481 // mov t2 = [min/max.val]
7483 // cmov[cond] t2 = t1
7485 // lcs dest = [bitinstr.addr], t2 [EAX is implicit]
7487 // fallthrough -->nextMBB
7489 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7490 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
7491 MachineFunction::iterator MBBIter = MBB;
7494 /// First build the CFG
7495 MachineFunction *F = MBB->getParent();
7496 MachineBasicBlock *thisMBB = MBB;
7497 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB);
7498 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB);
7499 F->insert(MBBIter, newMBB);
7500 F->insert(MBBIter, nextMBB);
7502 // Move all successors to thisMBB to nextMBB
7503 nextMBB->transferSuccessors(thisMBB);
7505 // Update thisMBB to fall through to newMBB
7506 thisMBB->addSuccessor(newMBB);
7508 // newMBB jumps to newMBB and fall through to nextMBB
7509 newMBB->addSuccessor(nextMBB);
7510 newMBB->addSuccessor(newMBB);
7512 DebugLoc dl = mInstr->getDebugLoc();
7513 // Insert instructions into newMBB based on incoming instruction
7514 assert(mInstr->getNumOperands() < X86AddrNumOperands + 4 &&
7515 "unexpected number of operands");
7516 MachineOperand& destOper = mInstr->getOperand(0);
7517 MachineOperand* argOpers[2 + X86AddrNumOperands];
7518 int numArgs = mInstr->getNumOperands() - 1;
7519 for (int i=0; i < numArgs; ++i)
7520 argOpers[i] = &mInstr->getOperand(i+1);
7522 // x86 address has 4 operands: base, index, scale, and displacement
7523 int lastAddrIndx = X86AddrNumOperands - 1; // [0,3]
7524 int valArgIndx = lastAddrIndx + 1;
7526 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7527 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1);
7528 for (int i=0; i <= lastAddrIndx; ++i)
7529 (*MIB).addOperand(*argOpers[i]);
7531 // We only support register and immediate values
7532 assert((argOpers[valArgIndx]->isReg() ||
7533 argOpers[valArgIndx]->isImm()) &&
7536 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7537 if (argOpers[valArgIndx]->isReg())
7538 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7540 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2);
7541 (*MIB).addOperand(*argOpers[valArgIndx]);
7543 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), X86::EAX);
7546 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr));
7551 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass);
7552 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3);
7556 // Cmp and exchange if none has modified the memory location
7557 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32));
7558 for (int i=0; i <= lastAddrIndx; ++i)
7559 (*MIB).addOperand(*argOpers[i]);
7561 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
7562 (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
7564 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), destOper.getReg());
7565 MIB.addReg(X86::EAX);
7568 BuildMI(newMBB, dl, TII->get(X86::JNE)).addMBB(newMBB);
7570 F->DeleteMachineInstr(mInstr); // The pseudo instruction is gone now.
7576 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7577 MachineBasicBlock *BB) const {
7578 DebugLoc dl = MI->getDebugLoc();
7579 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7580 switch (MI->getOpcode()) {
7581 default: assert(false && "Unexpected instr type to insert");
7582 case X86::CMOV_V1I64:
7583 case X86::CMOV_FR32:
7584 case X86::CMOV_FR64:
7585 case X86::CMOV_V4F32:
7586 case X86::CMOV_V2F64:
7587 case X86::CMOV_V2I64: {
7588 // To "insert" a SELECT_CC instruction, we actually have to insert the
7589 // diamond control-flow pattern. The incoming instruction knows the
7590 // destination vreg to set, the condition code register to branch on, the
7591 // true/false values to select between, and a branch opcode to use.
7592 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7593 MachineFunction::iterator It = BB;
7599 // cmpTY ccX, r1, r2
7601 // fallthrough --> copy0MBB
7602 MachineBasicBlock *thisMBB = BB;
7603 MachineFunction *F = BB->getParent();
7604 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7605 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7607 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
7608 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
7609 F->insert(It, copy0MBB);
7610 F->insert(It, sinkMBB);
7611 // Update machine-CFG edges by transferring all successors of the current
7612 // block to the new block which will contain the Phi node for the select.
7613 sinkMBB->transferSuccessors(BB);
7615 // Add the true and fallthrough blocks as its successors.
7616 BB->addSuccessor(copy0MBB);
7617 BB->addSuccessor(sinkMBB);
7620 // %FalseValue = ...
7621 // # fallthrough to sinkMBB
7624 // Update machine-CFG edges
7625 BB->addSuccessor(sinkMBB);
7628 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7631 BuildMI(BB, dl, TII->get(X86::PHI), MI->getOperand(0).getReg())
7632 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7633 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7635 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7639 case X86::FP32_TO_INT16_IN_MEM:
7640 case X86::FP32_TO_INT32_IN_MEM:
7641 case X86::FP32_TO_INT64_IN_MEM:
7642 case X86::FP64_TO_INT16_IN_MEM:
7643 case X86::FP64_TO_INT32_IN_MEM:
7644 case X86::FP64_TO_INT64_IN_MEM:
7645 case X86::FP80_TO_INT16_IN_MEM:
7646 case X86::FP80_TO_INT32_IN_MEM:
7647 case X86::FP80_TO_INT64_IN_MEM: {
7648 // Change the floating point control register to use "round towards zero"
7649 // mode when truncating to an integer value.
7650 MachineFunction *F = BB->getParent();
7651 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2);
7652 addFrameReference(BuildMI(BB, dl, TII->get(X86::FNSTCW16m)), CWFrameIdx);
7654 // Load the old value of the high byte of the control word...
7656 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
7657 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16rm), OldCW),
7660 // Set the high part to be round to zero...
7661 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mi)), CWFrameIdx)
7664 // Reload the modified control word now...
7665 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7667 // Restore the memory image of control word to original value
7668 addFrameReference(BuildMI(BB, dl, TII->get(X86::MOV16mr)), CWFrameIdx)
7671 // Get the X86 opcode to use.
7673 switch (MI->getOpcode()) {
7674 default: llvm_unreachable("illegal opcode!");
7675 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
7676 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
7677 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
7678 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
7679 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
7680 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
7681 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
7682 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
7683 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
7687 MachineOperand &Op = MI->getOperand(0);
7689 AM.BaseType = X86AddressMode::RegBase;
7690 AM.Base.Reg = Op.getReg();
7692 AM.BaseType = X86AddressMode::FrameIndexBase;
7693 AM.Base.FrameIndex = Op.getIndex();
7695 Op = MI->getOperand(1);
7697 AM.Scale = Op.getImm();
7698 Op = MI->getOperand(2);
7700 AM.IndexReg = Op.getImm();
7701 Op = MI->getOperand(3);
7702 if (Op.isGlobal()) {
7703 AM.GV = Op.getGlobal();
7705 AM.Disp = Op.getImm();
7707 addFullAddress(BuildMI(BB, dl, TII->get(Opc)), AM)
7708 .addReg(MI->getOperand(X86AddrNumOperands).getReg());
7710 // Reload the original control word now.
7711 addFrameReference(BuildMI(BB, dl, TII->get(X86::FLDCW16m)), CWFrameIdx);
7713 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
7716 case X86::ATOMAND32:
7717 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7718 X86::AND32ri, X86::MOV32rm,
7719 X86::LCMPXCHG32, X86::MOV32rr,
7720 X86::NOT32r, X86::EAX,
7721 X86::GR32RegisterClass);
7723 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
7724 X86::OR32ri, X86::MOV32rm,
7725 X86::LCMPXCHG32, X86::MOV32rr,
7726 X86::NOT32r, X86::EAX,
7727 X86::GR32RegisterClass);
7728 case X86::ATOMXOR32:
7729 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
7730 X86::XOR32ri, X86::MOV32rm,
7731 X86::LCMPXCHG32, X86::MOV32rr,
7732 X86::NOT32r, X86::EAX,
7733 X86::GR32RegisterClass);
7734 case X86::ATOMNAND32:
7735 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
7736 X86::AND32ri, X86::MOV32rm,
7737 X86::LCMPXCHG32, X86::MOV32rr,
7738 X86::NOT32r, X86::EAX,
7739 X86::GR32RegisterClass, true);
7740 case X86::ATOMMIN32:
7741 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
7742 case X86::ATOMMAX32:
7743 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
7744 case X86::ATOMUMIN32:
7745 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
7746 case X86::ATOMUMAX32:
7747 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
7749 case X86::ATOMAND16:
7750 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7751 X86::AND16ri, X86::MOV16rm,
7752 X86::LCMPXCHG16, X86::MOV16rr,
7753 X86::NOT16r, X86::AX,
7754 X86::GR16RegisterClass);
7756 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
7757 X86::OR16ri, X86::MOV16rm,
7758 X86::LCMPXCHG16, X86::MOV16rr,
7759 X86::NOT16r, X86::AX,
7760 X86::GR16RegisterClass);
7761 case X86::ATOMXOR16:
7762 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
7763 X86::XOR16ri, X86::MOV16rm,
7764 X86::LCMPXCHG16, X86::MOV16rr,
7765 X86::NOT16r, X86::AX,
7766 X86::GR16RegisterClass);
7767 case X86::ATOMNAND16:
7768 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
7769 X86::AND16ri, X86::MOV16rm,
7770 X86::LCMPXCHG16, X86::MOV16rr,
7771 X86::NOT16r, X86::AX,
7772 X86::GR16RegisterClass, true);
7773 case X86::ATOMMIN16:
7774 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
7775 case X86::ATOMMAX16:
7776 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
7777 case X86::ATOMUMIN16:
7778 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
7779 case X86::ATOMUMAX16:
7780 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
7783 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7784 X86::AND8ri, X86::MOV8rm,
7785 X86::LCMPXCHG8, X86::MOV8rr,
7786 X86::NOT8r, X86::AL,
7787 X86::GR8RegisterClass);
7789 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
7790 X86::OR8ri, X86::MOV8rm,
7791 X86::LCMPXCHG8, X86::MOV8rr,
7792 X86::NOT8r, X86::AL,
7793 X86::GR8RegisterClass);
7795 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
7796 X86::XOR8ri, X86::MOV8rm,
7797 X86::LCMPXCHG8, X86::MOV8rr,
7798 X86::NOT8r, X86::AL,
7799 X86::GR8RegisterClass);
7800 case X86::ATOMNAND8:
7801 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
7802 X86::AND8ri, X86::MOV8rm,
7803 X86::LCMPXCHG8, X86::MOV8rr,
7804 X86::NOT8r, X86::AL,
7805 X86::GR8RegisterClass, true);
7806 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
7807 // This group is for 64-bit host.
7808 case X86::ATOMAND64:
7809 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7810 X86::AND64ri32, X86::MOV64rm,
7811 X86::LCMPXCHG64, X86::MOV64rr,
7812 X86::NOT64r, X86::RAX,
7813 X86::GR64RegisterClass);
7815 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
7816 X86::OR64ri32, X86::MOV64rm,
7817 X86::LCMPXCHG64, X86::MOV64rr,
7818 X86::NOT64r, X86::RAX,
7819 X86::GR64RegisterClass);
7820 case X86::ATOMXOR64:
7821 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
7822 X86::XOR64ri32, X86::MOV64rm,
7823 X86::LCMPXCHG64, X86::MOV64rr,
7824 X86::NOT64r, X86::RAX,
7825 X86::GR64RegisterClass);
7826 case X86::ATOMNAND64:
7827 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
7828 X86::AND64ri32, X86::MOV64rm,
7829 X86::LCMPXCHG64, X86::MOV64rr,
7830 X86::NOT64r, X86::RAX,
7831 X86::GR64RegisterClass, true);
7832 case X86::ATOMMIN64:
7833 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
7834 case X86::ATOMMAX64:
7835 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
7836 case X86::ATOMUMIN64:
7837 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
7838 case X86::ATOMUMAX64:
7839 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
7841 // This group does 64-bit operations on a 32-bit host.
7842 case X86::ATOMAND6432:
7843 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7844 X86::AND32rr, X86::AND32rr,
7845 X86::AND32ri, X86::AND32ri,
7847 case X86::ATOMOR6432:
7848 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7849 X86::OR32rr, X86::OR32rr,
7850 X86::OR32ri, X86::OR32ri,
7852 case X86::ATOMXOR6432:
7853 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7854 X86::XOR32rr, X86::XOR32rr,
7855 X86::XOR32ri, X86::XOR32ri,
7857 case X86::ATOMNAND6432:
7858 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7859 X86::AND32rr, X86::AND32rr,
7860 X86::AND32ri, X86::AND32ri,
7862 case X86::ATOMADD6432:
7863 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7864 X86::ADD32rr, X86::ADC32rr,
7865 X86::ADD32ri, X86::ADC32ri,
7867 case X86::ATOMSUB6432:
7868 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7869 X86::SUB32rr, X86::SBB32rr,
7870 X86::SUB32ri, X86::SBB32ri,
7872 case X86::ATOMSWAP6432:
7873 return EmitAtomicBit6432WithCustomInserter(MI, BB,
7874 X86::MOV32rr, X86::MOV32rr,
7875 X86::MOV32ri, X86::MOV32ri,
7880 //===----------------------------------------------------------------------===//
7881 // X86 Optimization Hooks
7882 //===----------------------------------------------------------------------===//
7884 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7888 const SelectionDAG &DAG,
7889 unsigned Depth) const {
7890 unsigned Opc = Op.getOpcode();
7891 assert((Opc >= ISD::BUILTIN_OP_END ||
7892 Opc == ISD::INTRINSIC_WO_CHAIN ||
7893 Opc == ISD::INTRINSIC_W_CHAIN ||
7894 Opc == ISD::INTRINSIC_VOID) &&
7895 "Should use MaskedValueIsZero if you don't know whether Op"
7896 " is a target node!");
7898 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
7907 // These nodes' second result is a boolean.
7908 if (Op.getResNo() == 0)
7912 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
7913 Mask.getBitWidth() - 1);
7918 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
7919 /// node is a GlobalAddress + offset.
7920 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
7921 GlobalValue* &GA, int64_t &Offset) const{
7922 if (N->getOpcode() == X86ISD::Wrapper) {
7923 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
7924 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
7925 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
7929 return TargetLowering::isGAPlusOffset(N, GA, Offset);
7932 static bool isBaseAlignmentOfN(unsigned N, SDNode *Base,
7933 const TargetLowering &TLI) {
7936 if (TLI.isGAPlusOffset(Base, GV, Offset))
7937 return (GV->getAlignment() >= N && (Offset % N) == 0);
7938 // DAG combine handles the stack object case.
7942 static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems,
7943 MVT EVT, LoadSDNode *&LDBase,
7944 unsigned &LastLoadedElt,
7945 SelectionDAG &DAG, MachineFrameInfo *MFI,
7946 const TargetLowering &TLI) {
7948 LastLoadedElt = -1U;
7949 for (unsigned i = 0; i < NumElems; ++i) {
7950 if (N->getMaskElt(i) < 0) {
7956 SDValue Elt = DAG.getShuffleScalarElt(N, i);
7957 if (!Elt.getNode() ||
7958 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
7961 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
7963 LDBase = cast<LoadSDNode>(Elt.getNode());
7967 if (Elt.getOpcode() == ISD::UNDEF)
7970 LoadSDNode *LD = cast<LoadSDNode>(Elt);
7971 if (!TLI.isConsecutiveLoad(LD, LDBase, EVT.getSizeInBits()/8, i, MFI))
7978 /// PerformShuffleCombine - Combine a vector_shuffle that is equal to
7979 /// build_vector load1, load2, load3, load4, <0, 1, 2, 3> into a 128-bit load
7980 /// if the load addresses are consecutive, non-overlapping, and in the right
7981 /// order. In the case of v2i64, it will see if it can rewrite the
7982 /// shuffle to be an appropriate build vector so it can take advantage of
7983 // performBuildVectorCombine.
7984 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
7985 const TargetLowering &TLI) {
7986 DebugLoc dl = N->getDebugLoc();
7987 MVT VT = N->getValueType(0);
7988 MVT EVT = VT.getVectorElementType();
7989 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7990 unsigned NumElems = VT.getVectorNumElements();
7992 if (VT.getSizeInBits() != 128)
7995 // Try to combine a vector_shuffle into a 128-bit load.
7996 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7997 LoadSDNode *LD = NULL;
7998 unsigned LastLoadedElt;
7999 if (!EltsFromConsecutiveLoads(SVN, NumElems, EVT, LD, LastLoadedElt, DAG,
8003 if (LastLoadedElt == NumElems - 1) {
8004 if (isBaseAlignmentOfN(16, LD->getBasePtr().getNode(), TLI))
8005 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8006 LD->getSrcValue(), LD->getSrcValueOffset(),
8008 return DAG.getLoad(VT, dl, LD->getChain(), LD->getBasePtr(),
8009 LD->getSrcValue(), LD->getSrcValueOffset(),
8010 LD->isVolatile(), LD->getAlignment());
8011 } else if (NumElems == 4 && LastLoadedElt == 1) {
8012 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
8013 SDValue Ops[] = { LD->getChain(), LD->getBasePtr() };
8014 SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2);
8015 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode);
8020 /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes.
8021 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
8022 const X86Subtarget *Subtarget) {
8023 DebugLoc DL = N->getDebugLoc();
8024 SDValue Cond = N->getOperand(0);
8025 // Get the LHS/RHS of the select.
8026 SDValue LHS = N->getOperand(1);
8027 SDValue RHS = N->getOperand(2);
8029 // If we have SSE[12] support, try to form min/max nodes.
8030 if (Subtarget->hasSSE2() &&
8031 (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) &&
8032 Cond.getOpcode() == ISD::SETCC) {
8033 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
8035 unsigned Opcode = 0;
8036 if (LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
8039 case ISD::SETOLE: // (X <= Y) ? X : Y -> min
8042 if (!UnsafeFPMath) break;
8044 case ISD::SETOLT: // (X olt/lt Y) ? X : Y -> min
8046 Opcode = X86ISD::FMIN;
8049 case ISD::SETOGT: // (X > Y) ? X : Y -> max
8052 if (!UnsafeFPMath) break;
8054 case ISD::SETUGE: // (X uge/ge Y) ? X : Y -> max
8056 Opcode = X86ISD::FMAX;
8059 } else if (LHS == Cond.getOperand(1) && RHS == Cond.getOperand(0)) {
8062 case ISD::SETOGT: // (X > Y) ? Y : X -> min
8065 if (!UnsafeFPMath) break;
8067 case ISD::SETUGE: // (X uge/ge Y) ? Y : X -> min
8069 Opcode = X86ISD::FMIN;
8072 case ISD::SETOLE: // (X <= Y) ? Y : X -> max
8075 if (!UnsafeFPMath) break;
8077 case ISD::SETOLT: // (X olt/lt Y) ? Y : X -> max
8079 Opcode = X86ISD::FMAX;
8085 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
8088 // If this is a select between two integer constants, try to do some
8090 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
8091 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
8092 // Don't do this for crazy integer types.
8093 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
8094 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
8095 // so that TrueC (the true value) is larger than FalseC.
8096 bool NeedsCondInvert = false;
8098 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
8099 // Efficiently invertible.
8100 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
8101 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
8102 isa<ConstantSDNode>(Cond.getOperand(1))))) {
8103 NeedsCondInvert = true;
8104 std::swap(TrueC, FalseC);
8107 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
8108 if (FalseC->getAPIntValue() == 0 &&
8109 TrueC->getAPIntValue().isPowerOf2()) {
8110 if (NeedsCondInvert) // Invert the condition if needed.
8111 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8112 DAG.getConstant(1, Cond.getValueType()));
8114 // Zero extend the condition if needed.
8115 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
8117 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8118 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
8119 DAG.getConstant(ShAmt, MVT::i8));
8122 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
8123 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8124 if (NeedsCondInvert) // Invert the condition if needed.
8125 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8126 DAG.getConstant(1, Cond.getValueType()));
8128 // Zero extend the condition if needed.
8129 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8130 FalseC->getValueType(0), Cond);
8131 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8132 SDValue(FalseC, 0));
8135 // Optimize cases that will turn into an LEA instruction. This requires
8136 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8137 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8138 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8139 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8141 bool isFastMultiplier = false;
8143 switch ((unsigned char)Diff) {
8145 case 1: // result = add base, cond
8146 case 2: // result = lea base( , cond*2)
8147 case 3: // result = lea base(cond, cond*2)
8148 case 4: // result = lea base( , cond*4)
8149 case 5: // result = lea base(cond, cond*4)
8150 case 8: // result = lea base( , cond*8)
8151 case 9: // result = lea base(cond, cond*8)
8152 isFastMultiplier = true;
8157 if (isFastMultiplier) {
8158 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8159 if (NeedsCondInvert) // Invert the condition if needed.
8160 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
8161 DAG.getConstant(1, Cond.getValueType()));
8163 // Zero extend the condition if needed.
8164 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8166 // Scale the condition by the difference.
8168 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8169 DAG.getConstant(Diff, Cond.getValueType()));
8171 // Add the base if non-zero.
8172 if (FalseC->getAPIntValue() != 0)
8173 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8174 SDValue(FalseC, 0));
8184 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
8185 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
8186 TargetLowering::DAGCombinerInfo &DCI) {
8187 DebugLoc DL = N->getDebugLoc();
8189 // If the flag operand isn't dead, don't touch this CMOV.
8190 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
8193 // If this is a select between two integer constants, try to do some
8194 // optimizations. Note that the operands are ordered the opposite of SELECT
8196 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
8197 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8198 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
8199 // larger than FalseC (the false value).
8200 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
8202 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
8203 CC = X86::GetOppositeBranchCondition(CC);
8204 std::swap(TrueC, FalseC);
8207 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
8208 // This is efficient for any integer data type (including i8/i16) and
8210 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
8211 SDValue Cond = N->getOperand(3);
8212 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8213 DAG.getConstant(CC, MVT::i8), Cond);
8215 // Zero extend the condition if needed.
8216 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
8218 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
8219 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
8220 DAG.getConstant(ShAmt, MVT::i8));
8221 if (N->getNumValues() == 2) // Dead flag value?
8222 return DCI.CombineTo(N, Cond, SDValue());
8226 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
8227 // for any integer data type, including i8/i16.
8228 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
8229 SDValue Cond = N->getOperand(3);
8230 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8231 DAG.getConstant(CC, MVT::i8), Cond);
8233 // Zero extend the condition if needed.
8234 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
8235 FalseC->getValueType(0), Cond);
8236 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8237 SDValue(FalseC, 0));
8239 if (N->getNumValues() == 2) // Dead flag value?
8240 return DCI.CombineTo(N, Cond, SDValue());
8244 // Optimize cases that will turn into an LEA instruction. This requires
8245 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
8246 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
8247 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
8248 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
8250 bool isFastMultiplier = false;
8252 switch ((unsigned char)Diff) {
8254 case 1: // result = add base, cond
8255 case 2: // result = lea base( , cond*2)
8256 case 3: // result = lea base(cond, cond*2)
8257 case 4: // result = lea base( , cond*4)
8258 case 5: // result = lea base(cond, cond*4)
8259 case 8: // result = lea base( , cond*8)
8260 case 9: // result = lea base(cond, cond*8)
8261 isFastMultiplier = true;
8266 if (isFastMultiplier) {
8267 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
8268 SDValue Cond = N->getOperand(3);
8269 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
8270 DAG.getConstant(CC, MVT::i8), Cond);
8271 // Zero extend the condition if needed.
8272 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
8274 // Scale the condition by the difference.
8276 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
8277 DAG.getConstant(Diff, Cond.getValueType()));
8279 // Add the base if non-zero.
8280 if (FalseC->getAPIntValue() != 0)
8281 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
8282 SDValue(FalseC, 0));
8283 if (N->getNumValues() == 2) // Dead flag value?
8284 return DCI.CombineTo(N, Cond, SDValue());
8294 /// PerformMulCombine - Optimize a single multiply with constant into two
8295 /// in order to implement it with two cheaper instructions, e.g.
8296 /// LEA + SHL, LEA + LEA.
8297 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
8298 TargetLowering::DAGCombinerInfo &DCI) {
8299 if (DAG.getMachineFunction().
8300 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
8303 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8306 MVT VT = N->getValueType(0);
8310 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8313 uint64_t MulAmt = C->getZExtValue();
8314 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
8317 uint64_t MulAmt1 = 0;
8318 uint64_t MulAmt2 = 0;
8319 if ((MulAmt % 9) == 0) {
8321 MulAmt2 = MulAmt / 9;
8322 } else if ((MulAmt % 5) == 0) {
8324 MulAmt2 = MulAmt / 5;
8325 } else if ((MulAmt % 3) == 0) {
8327 MulAmt2 = MulAmt / 3;
8330 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
8331 DebugLoc DL = N->getDebugLoc();
8333 if (isPowerOf2_64(MulAmt2) &&
8334 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
8335 // If second multiplifer is pow2, issue it first. We want the multiply by
8336 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
8338 std::swap(MulAmt1, MulAmt2);
8341 if (isPowerOf2_64(MulAmt1))
8342 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
8343 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
8345 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
8346 DAG.getConstant(MulAmt1, VT));
8348 if (isPowerOf2_64(MulAmt2))
8349 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
8350 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
8352 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
8353 DAG.getConstant(MulAmt2, VT));
8355 // Do not add new nodes to DAG combiner worklist.
8356 DCI.CombineTo(N, NewMul, false);
8362 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
8364 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
8365 const X86Subtarget *Subtarget) {
8366 // On X86 with SSE2 support, we can transform this to a vector shift if
8367 // all elements are shifted by the same amount. We can't do this in legalize
8368 // because the a constant vector is typically transformed to a constant pool
8369 // so we have no knowledge of the shift amount.
8370 if (!Subtarget->hasSSE2())
8373 MVT VT = N->getValueType(0);
8374 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
8377 SDValue ShAmtOp = N->getOperand(1);
8378 MVT EltVT = VT.getVectorElementType();
8379 DebugLoc DL = N->getDebugLoc();
8381 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
8382 unsigned NumElts = VT.getVectorNumElements();
8384 for (; i != NumElts; ++i) {
8385 SDValue Arg = ShAmtOp.getOperand(i);
8386 if (Arg.getOpcode() == ISD::UNDEF) continue;
8390 for (; i != NumElts; ++i) {
8391 SDValue Arg = ShAmtOp.getOperand(i);
8392 if (Arg.getOpcode() == ISD::UNDEF) continue;
8393 if (Arg != BaseShAmt) {
8397 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
8398 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
8399 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
8400 DAG.getIntPtrConstant(0));
8404 if (EltVT.bitsGT(MVT::i32))
8405 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
8406 else if (EltVT.bitsLT(MVT::i32))
8407 BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
8409 // The shift amount is identical so we can do a vector shift.
8410 SDValue ValOp = N->getOperand(0);
8411 switch (N->getOpcode()) {
8413 llvm_unreachable("Unknown shift opcode!");
8416 if (VT == MVT::v2i64)
8417 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8418 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
8420 if (VT == MVT::v4i32)
8421 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8422 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32),
8424 if (VT == MVT::v8i16)
8425 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8426 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32),
8430 if (VT == MVT::v4i32)
8431 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8432 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32),
8434 if (VT == MVT::v8i16)
8435 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8436 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32),
8440 if (VT == MVT::v2i64)
8441 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8442 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
8444 if (VT == MVT::v4i32)
8445 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8446 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32),
8448 if (VT == MVT::v8i16)
8449 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
8450 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32),
8457 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
8458 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
8459 const X86Subtarget *Subtarget) {
8460 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
8461 // the FP state in cases where an emms may be missing.
8462 // A preferable solution to the general problem is to figure out the right
8463 // places to insert EMMS. This qualifies as a quick hack.
8465 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
8466 StoreSDNode *St = cast<StoreSDNode>(N);
8467 MVT VT = St->getValue().getValueType();
8468 if (VT.getSizeInBits() != 64)
8471 const Function *F = DAG.getMachineFunction().getFunction();
8472 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat);
8473 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps
8474 && Subtarget->hasSSE2();
8475 if ((VT.isVector() ||
8476 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
8477 isa<LoadSDNode>(St->getValue()) &&
8478 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
8479 St->getChain().hasOneUse() && !St->isVolatile()) {
8480 SDNode* LdVal = St->getValue().getNode();
8482 int TokenFactorIndex = -1;
8483 SmallVector<SDValue, 8> Ops;
8484 SDNode* ChainVal = St->getChain().getNode();
8485 // Must be a store of a load. We currently handle two cases: the load
8486 // is a direct child, and it's under an intervening TokenFactor. It is
8487 // possible to dig deeper under nested TokenFactors.
8488 if (ChainVal == LdVal)
8489 Ld = cast<LoadSDNode>(St->getChain());
8490 else if (St->getValue().hasOneUse() &&
8491 ChainVal->getOpcode() == ISD::TokenFactor) {
8492 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) {
8493 if (ChainVal->getOperand(i).getNode() == LdVal) {
8494 TokenFactorIndex = i;
8495 Ld = cast<LoadSDNode>(St->getValue());
8497 Ops.push_back(ChainVal->getOperand(i));
8501 if (!Ld || !ISD::isNormalLoad(Ld))
8504 // If this is not the MMX case, i.e. we are just turning i64 load/store
8505 // into f64 load/store, avoid the transformation if there are multiple
8506 // uses of the loaded value.
8507 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
8510 DebugLoc LdDL = Ld->getDebugLoc();
8511 DebugLoc StDL = N->getDebugLoc();
8512 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
8513 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
8515 if (Subtarget->is64Bit() || F64IsLegal) {
8516 MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
8517 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(),
8518 Ld->getBasePtr(), Ld->getSrcValue(),
8519 Ld->getSrcValueOffset(), Ld->isVolatile(),
8520 Ld->getAlignment());
8521 SDValue NewChain = NewLd.getValue(1);
8522 if (TokenFactorIndex != -1) {
8523 Ops.push_back(NewChain);
8524 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8527 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
8528 St->getSrcValue(), St->getSrcValueOffset(),
8529 St->isVolatile(), St->getAlignment());
8532 // Otherwise, lower to two pairs of 32-bit loads / stores.
8533 SDValue LoAddr = Ld->getBasePtr();
8534 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
8535 DAG.getConstant(4, MVT::i32));
8537 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
8538 Ld->getSrcValue(), Ld->getSrcValueOffset(),
8539 Ld->isVolatile(), Ld->getAlignment());
8540 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
8541 Ld->getSrcValue(), Ld->getSrcValueOffset()+4,
8543 MinAlign(Ld->getAlignment(), 4));
8545 SDValue NewChain = LoLd.getValue(1);
8546 if (TokenFactorIndex != -1) {
8547 Ops.push_back(LoLd);
8548 Ops.push_back(HiLd);
8549 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
8553 LoAddr = St->getBasePtr();
8554 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
8555 DAG.getConstant(4, MVT::i32));
8557 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
8558 St->getSrcValue(), St->getSrcValueOffset(),
8559 St->isVolatile(), St->getAlignment());
8560 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
8562 St->getSrcValueOffset() + 4,
8564 MinAlign(St->getAlignment(), 4));
8565 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
8570 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
8571 /// X86ISD::FXOR nodes.
8572 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
8573 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
8574 // F[X]OR(0.0, x) -> x
8575 // F[X]OR(x, 0.0) -> x
8576 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8577 if (C->getValueAPF().isPosZero())
8578 return N->getOperand(1);
8579 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8580 if (C->getValueAPF().isPosZero())
8581 return N->getOperand(0);
8585 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
8586 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
8587 // FAND(0.0, x) -> 0.0
8588 // FAND(x, 0.0) -> 0.0
8589 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
8590 if (C->getValueAPF().isPosZero())
8591 return N->getOperand(0);
8592 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
8593 if (C->getValueAPF().isPosZero())
8594 return N->getOperand(1);
8598 static SDValue PerformBTCombine(SDNode *N,
8600 TargetLowering::DAGCombinerInfo &DCI) {
8601 // BT ignores high bits in the bit index operand.
8602 SDValue Op1 = N->getOperand(1);
8603 if (Op1.hasOneUse()) {
8604 unsigned BitWidth = Op1.getValueSizeInBits();
8605 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
8606 APInt KnownZero, KnownOne;
8607 TargetLowering::TargetLoweringOpt TLO(DAG);
8608 TargetLowering &TLI = DAG.getTargetLoweringInfo();
8609 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
8610 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
8611 DCI.CommitTargetLoweringOpt(TLO);
8616 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
8617 SDValue Op = N->getOperand(0);
8618 if (Op.getOpcode() == ISD::BIT_CONVERT)
8619 Op = Op.getOperand(0);
8620 MVT VT = N->getValueType(0), OpVT = Op.getValueType();
8621 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
8622 VT.getVectorElementType().getSizeInBits() ==
8623 OpVT.getVectorElementType().getSizeInBits()) {
8624 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
8629 // On X86 and X86-64, atomic operations are lowered to locked instructions.
8630 // Locked instructions, in turn, have implicit fence semantics (all memory
8631 // operations are flushed before issuing the locked instruction, and the
8632 // are not buffered), so we can fold away the common pattern of
8633 // fence-atomic-fence.
8634 static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
8635 SDValue atomic = N->getOperand(0);
8636 switch (atomic.getOpcode()) {
8637 case ISD::ATOMIC_CMP_SWAP:
8638 case ISD::ATOMIC_SWAP:
8639 case ISD::ATOMIC_LOAD_ADD:
8640 case ISD::ATOMIC_LOAD_SUB:
8641 case ISD::ATOMIC_LOAD_AND:
8642 case ISD::ATOMIC_LOAD_OR:
8643 case ISD::ATOMIC_LOAD_XOR:
8644 case ISD::ATOMIC_LOAD_NAND:
8645 case ISD::ATOMIC_LOAD_MIN:
8646 case ISD::ATOMIC_LOAD_MAX:
8647 case ISD::ATOMIC_LOAD_UMIN:
8648 case ISD::ATOMIC_LOAD_UMAX:
8654 SDValue fence = atomic.getOperand(0);
8655 if (fence.getOpcode() != ISD::MEMBARRIER)
8658 switch (atomic.getOpcode()) {
8659 case ISD::ATOMIC_CMP_SWAP:
8660 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8661 atomic.getOperand(1), atomic.getOperand(2),
8662 atomic.getOperand(3));
8663 case ISD::ATOMIC_SWAP:
8664 case ISD::ATOMIC_LOAD_ADD:
8665 case ISD::ATOMIC_LOAD_SUB:
8666 case ISD::ATOMIC_LOAD_AND:
8667 case ISD::ATOMIC_LOAD_OR:
8668 case ISD::ATOMIC_LOAD_XOR:
8669 case ISD::ATOMIC_LOAD_NAND:
8670 case ISD::ATOMIC_LOAD_MIN:
8671 case ISD::ATOMIC_LOAD_MAX:
8672 case ISD::ATOMIC_LOAD_UMIN:
8673 case ISD::ATOMIC_LOAD_UMAX:
8674 return DAG.UpdateNodeOperands(atomic, fence.getOperand(0),
8675 atomic.getOperand(1), atomic.getOperand(2));
8681 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
8682 DAGCombinerInfo &DCI) const {
8683 SelectionDAG &DAG = DCI.DAG;
8684 switch (N->getOpcode()) {
8686 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, *this);
8687 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
8688 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI);
8689 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
8692 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
8693 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
8695 case X86ISD::FOR: return PerformFORCombine(N, DAG);
8696 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
8697 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
8698 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
8699 case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
8705 //===----------------------------------------------------------------------===//
8706 // X86 Inline Assembly Support
8707 //===----------------------------------------------------------------------===//
8709 static bool LowerToBSwap(CallInst *CI) {
8710 // FIXME: this should verify that we are targetting a 486 or better. If not,
8711 // we will turn this bswap into something that will be lowered to logical ops
8712 // instead of emitting the bswap asm. For now, we don't support 486 or lower
8713 // so don't worry about this.
8715 // Verify this is a simple bswap.
8716 if (CI->getNumOperands() != 2 ||
8717 CI->getType() != CI->getOperand(1)->getType() ||
8718 !CI->getType()->isInteger())
8721 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8722 if (!Ty || Ty->getBitWidth() % 16 != 0)
8725 // Okay, we can do this xform, do so now.
8726 const Type *Tys[] = { Ty };
8727 Module *M = CI->getParent()->getParent()->getParent();
8728 Constant *Int = Intrinsic::getDeclaration(M, Intrinsic::bswap, Tys, 1);
8730 Value *Op = CI->getOperand(1);
8731 Op = CallInst::Create(Int, Op, CI->getName(), CI);
8733 CI->replaceAllUsesWith(Op);
8734 CI->eraseFromParent();
8738 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
8739 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8740 std::vector<InlineAsm::ConstraintInfo> Constraints = IA->ParseConstraints();
8742 std::string AsmStr = IA->getAsmString();
8744 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
8745 std::vector<std::string> AsmPieces;
8746 SplitString(AsmStr, AsmPieces, "\n"); // ; as separator?
8748 switch (AsmPieces.size()) {
8749 default: return false;
8751 AsmStr = AsmPieces[0];
8753 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace.
8756 if (AsmPieces.size() == 2 &&
8757 (AsmPieces[0] == "bswap" ||
8758 AsmPieces[0] == "bswapq" ||
8759 AsmPieces[0] == "bswapl") &&
8760 (AsmPieces[1] == "$0" ||
8761 AsmPieces[1] == "${0:q}")) {
8762 // No need to check constraints, nothing other than the equivalent of
8763 // "=r,0" would be valid here.
8764 return LowerToBSwap(CI);
8766 // rorw $$8, ${0:w} --> llvm.bswap.i16
8767 if (CI->getType() == Type::Int16Ty &&
8768 AsmPieces.size() == 3 &&
8769 AsmPieces[0] == "rorw" &&
8770 AsmPieces[1] == "$$8," &&
8771 AsmPieces[2] == "${0:w}" &&
8772 IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
8773 return LowerToBSwap(CI);
8777 if (CI->getType() == Type::Int64Ty && Constraints.size() >= 2 &&
8778 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
8779 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
8780 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
8781 std::vector<std::string> Words;
8782 SplitString(AsmPieces[0], Words, " \t");
8783 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") {
8785 SplitString(AsmPieces[1], Words, " \t");
8786 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") {
8788 SplitString(AsmPieces[2], Words, " \t,");
8789 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" &&
8790 Words[2] == "%edx") {
8791 return LowerToBSwap(CI);
8803 /// getConstraintType - Given a constraint letter, return the type of
8804 /// constraint it is for this target.
8805 X86TargetLowering::ConstraintType
8806 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
8807 if (Constraint.size() == 1) {
8808 switch (Constraint[0]) {
8820 return C_RegisterClass;
8828 return TargetLowering::getConstraintType(Constraint);
8831 /// LowerXConstraint - try to replace an X constraint, which matches anything,
8832 /// with another that has more specific requirements based on the type of the
8833 /// corresponding operand.
8834 const char *X86TargetLowering::
8835 LowerXConstraint(MVT ConstraintVT) const {
8836 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
8837 // 'f' like normal targets.
8838 if (ConstraintVT.isFloatingPoint()) {
8839 if (Subtarget->hasSSE2())
8841 if (Subtarget->hasSSE1())
8845 return TargetLowering::LowerXConstraint(ConstraintVT);
8848 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8849 /// vector. If it is invalid, don't add anything to Ops.
8850 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8853 std::vector<SDValue>&Ops,
8854 SelectionDAG &DAG) const {
8855 SDValue Result(0, 0);
8857 switch (Constraint) {
8860 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8861 if (C->getZExtValue() <= 31) {
8862 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8868 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8869 if (C->getZExtValue() <= 63) {
8870 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8876 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8877 if ((int8_t)C->getSExtValue() == C->getSExtValue()) {
8878 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8884 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8885 if (C->getZExtValue() <= 255) {
8886 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8892 // 32-bit signed value
8893 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8894 const ConstantInt *CI = C->getConstantIntValue();
8895 if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) {
8896 // Widen to 64 bits here to get it sign extended.
8897 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
8900 // FIXME gcc accepts some relocatable values here too, but only in certain
8901 // memory models; it's complicated.
8906 // 32-bit unsigned value
8907 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
8908 const ConstantInt *CI = C->getConstantIntValue();
8909 if (CI->isValueValidForType(Type::Int32Ty, C->getZExtValue())) {
8910 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
8914 // FIXME gcc accepts some relocatable values here too, but only in certain
8915 // memory models; it's complicated.
8919 // Literal immediates are always ok.
8920 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
8921 // Widen to 64 bits here to get it sign extended.
8922 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
8926 // If we are in non-pic codegen mode, we allow the address of a global (with
8927 // an optional displacement) to be used with 'i'.
8928 GlobalAddressSDNode *GA = 0;
8931 // Match either (GA), (GA+C), (GA+C1+C2), etc.
8933 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
8934 Offset += GA->getOffset();
8936 } else if (Op.getOpcode() == ISD::ADD) {
8937 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8938 Offset += C->getZExtValue();
8939 Op = Op.getOperand(0);
8942 } else if (Op.getOpcode() == ISD::SUB) {
8943 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
8944 Offset += -C->getZExtValue();
8945 Op = Op.getOperand(0);
8950 // Otherwise, this isn't something we can handle, reject it.
8954 GlobalValue *GV = GA->getGlobal();
8955 // If we require an extra load to get this address, as in PIC mode, we
8957 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
8958 getTargetMachine())))
8962 Op = LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
8964 Op = DAG.getTargetGlobalAddress(GV, GA->getValueType(0), Offset);
8970 if (Result.getNode()) {
8971 Ops.push_back(Result);
8974 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
8978 std::vector<unsigned> X86TargetLowering::
8979 getRegClassForInlineAsmConstraint(const std::string &Constraint,
8981 if (Constraint.size() == 1) {
8982 // FIXME: not handling fp-stack yet!
8983 switch (Constraint[0]) { // GCC X86 Constraint Letters
8984 default: break; // Unknown constraint letter
8985 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
8986 if (Subtarget->is64Bit()) {
8988 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX,
8989 X86::ESI, X86::EDI, X86::R8D, X86::R9D,
8990 X86::R10D,X86::R11D,X86::R12D,
8991 X86::R13D,X86::R14D,X86::R15D,
8992 X86::EBP, X86::ESP, 0);
8993 else if (VT == MVT::i16)
8994 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX,
8995 X86::SI, X86::DI, X86::R8W,X86::R9W,
8996 X86::R10W,X86::R11W,X86::R12W,
8997 X86::R13W,X86::R14W,X86::R15W,
8998 X86::BP, X86::SP, 0);
8999 else if (VT == MVT::i8)
9000 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL,
9001 X86::SIL, X86::DIL, X86::R8B,X86::R9B,
9002 X86::R10B,X86::R11B,X86::R12B,
9003 X86::R13B,X86::R14B,X86::R15B,
9004 X86::BPL, X86::SPL, 0);
9006 else if (VT == MVT::i64)
9007 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX,
9008 X86::RSI, X86::RDI, X86::R8, X86::R9,
9009 X86::R10, X86::R11, X86::R12,
9010 X86::R13, X86::R14, X86::R15,
9011 X86::RBP, X86::RSP, 0);
9015 // 32-bit fallthrough
9018 return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0);
9019 else if (VT == MVT::i16)
9020 return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
9021 else if (VT == MVT::i8)
9022 return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
9023 else if (VT == MVT::i64)
9024 return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
9029 return std::vector<unsigned>();
9032 std::pair<unsigned, const TargetRegisterClass*>
9033 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9035 // First, see if this is a constraint that directly corresponds to an LLVM
9037 if (Constraint.size() == 1) {
9038 // GCC Constraint Letters
9039 switch (Constraint[0]) {
9041 case 'r': // GENERAL_REGS
9042 case 'R': // LEGACY_REGS
9043 case 'l': // INDEX_REGS
9045 return std::make_pair(0U, X86::GR8RegisterClass);
9047 return std::make_pair(0U, X86::GR16RegisterClass);
9048 if (VT == MVT::i32 || !Subtarget->is64Bit())
9049 return std::make_pair(0U, X86::GR32RegisterClass);
9050 return std::make_pair(0U, X86::GR64RegisterClass);
9051 case 'f': // FP Stack registers.
9052 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
9053 // value to the correct fpstack register class.
9054 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
9055 return std::make_pair(0U, X86::RFP32RegisterClass);
9056 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
9057 return std::make_pair(0U, X86::RFP64RegisterClass);
9058 return std::make_pair(0U, X86::RFP80RegisterClass);
9059 case 'y': // MMX_REGS if MMX allowed.
9060 if (!Subtarget->hasMMX()) break;
9061 return std::make_pair(0U, X86::VR64RegisterClass);
9062 case 'Y': // SSE_REGS if SSE2 allowed
9063 if (!Subtarget->hasSSE2()) break;
9065 case 'x': // SSE_REGS if SSE1 allowed
9066 if (!Subtarget->hasSSE1()) break;
9068 switch (VT.getSimpleVT()) {
9070 // Scalar SSE types.
9073 return std::make_pair(0U, X86::FR32RegisterClass);
9076 return std::make_pair(0U, X86::FR64RegisterClass);
9084 return std::make_pair(0U, X86::VR128RegisterClass);
9090 // Use the default implementation in TargetLowering to convert the register
9091 // constraint into a member of a register class.
9092 std::pair<unsigned, const TargetRegisterClass*> Res;
9093 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9095 // Not found as a standard register?
9096 if (Res.second == 0) {
9097 // GCC calls "st(0)" just plain "st".
9098 if (StringsEqualNoCase("{st}", Constraint)) {
9099 Res.first = X86::ST0;
9100 Res.second = X86::RFP80RegisterClass;
9102 // 'A' means EAX + EDX.
9103 if (Constraint == "A") {
9104 Res.first = X86::EAX;
9105 Res.second = X86::GR32_ADRegisterClass;
9110 // Otherwise, check to see if this is a register class of the wrong value
9111 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
9112 // turn into {ax},{dx}.
9113 if (Res.second->hasType(VT))
9114 return Res; // Correct type already, nothing to do.
9116 // All of the single-register GCC register classes map their values onto
9117 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
9118 // really want an 8-bit or 32-bit register, map to the appropriate register
9119 // class and return the appropriate register.
9120 if (Res.second == X86::GR16RegisterClass) {
9121 if (VT == MVT::i8) {
9122 unsigned DestReg = 0;
9123 switch (Res.first) {
9125 case X86::AX: DestReg = X86::AL; break;
9126 case X86::DX: DestReg = X86::DL; break;
9127 case X86::CX: DestReg = X86::CL; break;
9128 case X86::BX: DestReg = X86::BL; break;
9131 Res.first = DestReg;
9132 Res.second = X86::GR8RegisterClass;
9134 } else if (VT == MVT::i32) {
9135 unsigned DestReg = 0;
9136 switch (Res.first) {
9138 case X86::AX: DestReg = X86::EAX; break;
9139 case X86::DX: DestReg = X86::EDX; break;
9140 case X86::CX: DestReg = X86::ECX; break;
9141 case X86::BX: DestReg = X86::EBX; break;
9142 case X86::SI: DestReg = X86::ESI; break;
9143 case X86::DI: DestReg = X86::EDI; break;
9144 case X86::BP: DestReg = X86::EBP; break;
9145 case X86::SP: DestReg = X86::ESP; break;
9148 Res.first = DestReg;
9149 Res.second = X86::GR32RegisterClass;
9151 } else if (VT == MVT::i64) {
9152 unsigned DestReg = 0;
9153 switch (Res.first) {
9155 case X86::AX: DestReg = X86::RAX; break;
9156 case X86::DX: DestReg = X86::RDX; break;
9157 case X86::CX: DestReg = X86::RCX; break;
9158 case X86::BX: DestReg = X86::RBX; break;
9159 case X86::SI: DestReg = X86::RSI; break;
9160 case X86::DI: DestReg = X86::RDI; break;
9161 case X86::BP: DestReg = X86::RBP; break;
9162 case X86::SP: DestReg = X86::RSP; break;
9165 Res.first = DestReg;
9166 Res.second = X86::GR64RegisterClass;
9169 } else if (Res.second == X86::FR32RegisterClass ||
9170 Res.second == X86::FR64RegisterClass ||
9171 Res.second == X86::VR128RegisterClass) {
9172 // Handle references to XMM physical registers that got mapped into the
9173 // wrong class. This can happen with constraints like {xmm0} where the
9174 // target independent register mapper will just pick the first match it can
9175 // find, ignoring the required type.
9177 Res.second = X86::FR32RegisterClass;
9178 else if (VT == MVT::f64)
9179 Res.second = X86::FR64RegisterClass;
9180 else if (X86::VR128RegisterClass->hasType(VT))
9181 Res.second = X86::VR128RegisterClass;
9187 //===----------------------------------------------------------------------===//
9188 // X86 Widen vector type
9189 //===----------------------------------------------------------------------===//
9191 /// getWidenVectorType: given a vector type, returns the type to widen
9192 /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
9193 /// If there is no vector type that we want to widen to, returns MVT::Other
9194 /// When and where to widen is target dependent based on the cost of
9195 /// scalarizing vs using the wider vector type.
9197 MVT X86TargetLowering::getWidenVectorType(MVT VT) const {
9198 assert(VT.isVector());
9199 if (isTypeLegal(VT))
9202 // TODO: In computeRegisterProperty, we can compute the list of legal vector
9203 // type based on element type. This would speed up our search (though
9204 // it may not be worth it since the size of the list is relatively
9206 MVT EltVT = VT.getVectorElementType();
9207 unsigned NElts = VT.getVectorNumElements();
9209 // On X86, it make sense to widen any vector wider than 1
9213 for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE;
9214 nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
9215 MVT SVT = (MVT::SimpleValueType)nVT;
9217 if (isTypeLegal(SVT) &&
9218 SVT.getVectorElementType() == EltVT &&
9219 SVT.getVectorNumElements() > NElts)