1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "X86ISelLowering.h"
16 #include "Utils/X86ShuffleDecode.h"
17 #include "X86CallingConv.h"
18 #include "X86FrameLowering.h"
19 #include "X86InstrBuilder.h"
20 #include "X86MachineFunctionInfo.h"
21 #include "X86TargetMachine.h"
22 #include "X86TargetObjectFile.h"
23 #include "llvm/ADT/SmallBitVector.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/ADT/StringExtras.h"
27 #include "llvm/ADT/StringSwitch.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineModuleInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/WinEHFuncInfo.h"
36 #include "llvm/IR/CallSite.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/DerivedTypes.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/IR/GlobalAlias.h"
42 #include "llvm/IR/GlobalVariable.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/Intrinsics.h"
45 #include "llvm/MC/MCAsmInfo.h"
46 #include "llvm/MC/MCContext.h"
47 #include "llvm/MC/MCExpr.h"
48 #include "llvm/MC/MCSymbol.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Target/TargetOptions.h"
54 #include "X86IntrinsicsInfo.h"
60 #define DEBUG_TYPE "x86-isel"
62 STATISTIC(NumTailCalls, "Number of tail calls");
64 static cl::opt<bool> ExperimentalVectorWideningLegalization(
65 "x86-experimental-vector-widening-legalization", cl::init(false),
66 cl::desc("Enable an experimental vector type legalization through widening "
67 "rather than promotion."),
70 // Forward declarations.
71 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
74 X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
75 const X86Subtarget &STI)
76 : TargetLowering(TM), Subtarget(&STI) {
77 X86ScalarSSEf64 = Subtarget->hasSSE2();
78 X86ScalarSSEf32 = Subtarget->hasSSE1();
81 // Set up the TargetLowering object.
82 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
84 // X86 is weird. It always uses i8 for shift amounts and setcc results.
85 setBooleanContents(ZeroOrOneBooleanContent);
86 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
87 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
89 // For 64-bit, since we have so many registers, use the ILP scheduler.
90 // For 32-bit, use the register pressure specific scheduling.
91 // For Atom, always use ILP scheduling.
92 if (Subtarget->isAtom())
93 setSchedulingPreference(Sched::ILP);
94 else if (Subtarget->is64Bit())
95 setSchedulingPreference(Sched::ILP);
97 setSchedulingPreference(Sched::RegPressure);
98 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
99 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
101 // Bypass expensive divides on Atom when compiling with O2.
102 if (TM.getOptLevel() >= CodeGenOpt::Default) {
103 if (Subtarget->hasSlowDivide32())
104 addBypassSlowDiv(32, 8);
105 if (Subtarget->hasSlowDivide64() && Subtarget->is64Bit())
106 addBypassSlowDiv(64, 16);
109 if (Subtarget->isTargetKnownWindowsMSVC()) {
110 // Setup Windows compiler runtime calls.
111 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
112 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
113 setLibcallName(RTLIB::SREM_I64, "_allrem");
114 setLibcallName(RTLIB::UREM_I64, "_aullrem");
115 setLibcallName(RTLIB::MUL_I64, "_allmul");
116 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
117 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
118 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
119 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
120 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
122 // The _ftol2 runtime function has an unusual calling conv, which
123 // is modeled by a special pseudo-instruction.
124 setLibcallName(RTLIB::FPTOUINT_F64_I64, nullptr);
125 setLibcallName(RTLIB::FPTOUINT_F32_I64, nullptr);
126 setLibcallName(RTLIB::FPTOUINT_F64_I32, nullptr);
127 setLibcallName(RTLIB::FPTOUINT_F32_I32, nullptr);
130 if (Subtarget->isTargetDarwin()) {
131 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
132 setUseUnderscoreSetJmp(false);
133 setUseUnderscoreLongJmp(false);
134 } else if (Subtarget->isTargetWindowsGNU()) {
135 // MS runtime is weird: it exports _setjmp, but longjmp!
136 setUseUnderscoreSetJmp(true);
137 setUseUnderscoreLongJmp(false);
139 setUseUnderscoreSetJmp(true);
140 setUseUnderscoreLongJmp(true);
143 // Set up the register classes.
144 addRegisterClass(MVT::i8, &X86::GR8RegClass);
145 addRegisterClass(MVT::i16, &X86::GR16RegClass);
146 addRegisterClass(MVT::i32, &X86::GR32RegClass);
147 if (Subtarget->is64Bit())
148 addRegisterClass(MVT::i64, &X86::GR64RegClass);
150 for (MVT VT : MVT::integer_valuetypes())
151 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
153 // We don't accept any truncstore of integer registers.
154 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
155 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
156 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
157 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
158 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
159 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
161 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
163 // SETOEQ and SETUNE require checking two conditions.
164 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
165 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
166 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
167 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
168 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
169 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
171 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
173 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
174 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
175 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
177 if (Subtarget->is64Bit()) {
178 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
179 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
180 } else if (!Subtarget->useSoftFloat()) {
181 // We have an algorithm for SSE2->double, and we turn this into a
182 // 64-bit FILD followed by conditional FADD for other targets.
183 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
184 // We have an algorithm for SSE2, and we turn this into a 64-bit
185 // FILD for other targets.
186 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
189 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
191 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
192 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
194 if (!Subtarget->useSoftFloat()) {
195 // SSE has no i16 to fp conversion, only i32
196 if (X86ScalarSSEf32) {
197 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
198 // f32 and f64 cases are Legal, f80 case is not
199 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
201 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
202 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
205 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
206 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
209 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
210 // are Legal, f80 is custom lowered.
211 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
212 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
214 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
216 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
217 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
219 if (X86ScalarSSEf32) {
220 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
221 // f32 and f64 cases are Legal, f80 case is not
222 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
224 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
225 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
228 // Handle FP_TO_UINT by promoting the destination to a larger signed
230 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
231 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
232 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
234 if (Subtarget->is64Bit()) {
235 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
236 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
237 } else if (!Subtarget->useSoftFloat()) {
238 // Since AVX is a superset of SSE3, only check for SSE here.
239 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
240 // Expand FP_TO_UINT into a select.
241 // FIXME: We would like to use a Custom expander here eventually to do
242 // the optimal thing for SSE vs. the default expansion in the legalizer.
243 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
245 // With SSE3 we can use fisttpll to convert to a signed i64; without
246 // SSE, we're stuck with a fistpll.
247 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
250 if (isTargetFTOL()) {
251 // Use the _ftol2 runtime function, which has a pseudo-instruction
252 // to handle its weird calling convention.
253 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
256 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
257 if (!X86ScalarSSEf64) {
258 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
259 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
260 if (Subtarget->is64Bit()) {
261 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
262 // Without SSE, i64->f64 goes through memory.
263 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
267 // Scalar integer divide and remainder are lowered to use operations that
268 // produce two results, to match the available instructions. This exposes
269 // the two-result form to trivial CSE, which is able to combine x/y and x%y
270 // into a single instruction.
272 // Scalar integer multiply-high is also lowered to use two-result
273 // operations, to match the available instructions. However, plain multiply
274 // (low) operations are left as Legal, as there are single-result
275 // instructions for this in x86. Using the two-result multiply instructions
276 // when both high and low results are needed must be arranged by dagcombine.
277 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
279 setOperationAction(ISD::MULHS, VT, Expand);
280 setOperationAction(ISD::MULHU, VT, Expand);
281 setOperationAction(ISD::SDIV, VT, Expand);
282 setOperationAction(ISD::UDIV, VT, Expand);
283 setOperationAction(ISD::SREM, VT, Expand);
284 setOperationAction(ISD::UREM, VT, Expand);
286 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
287 setOperationAction(ISD::ADDC, VT, Custom);
288 setOperationAction(ISD::ADDE, VT, Custom);
289 setOperationAction(ISD::SUBC, VT, Custom);
290 setOperationAction(ISD::SUBE, VT, Custom);
293 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
294 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
295 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
296 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
297 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
298 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
299 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
300 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
301 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
302 setOperationAction(ISD::SELECT_CC , MVT::f32, Expand);
303 setOperationAction(ISD::SELECT_CC , MVT::f64, Expand);
304 setOperationAction(ISD::SELECT_CC , MVT::f80, Expand);
305 setOperationAction(ISD::SELECT_CC , MVT::i8, Expand);
306 setOperationAction(ISD::SELECT_CC , MVT::i16, Expand);
307 setOperationAction(ISD::SELECT_CC , MVT::i32, Expand);
308 setOperationAction(ISD::SELECT_CC , MVT::i64, Expand);
309 if (Subtarget->is64Bit())
310 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
311 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
312 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
313 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
314 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
315 setOperationAction(ISD::FREM , MVT::f32 , Expand);
316 setOperationAction(ISD::FREM , MVT::f64 , Expand);
317 setOperationAction(ISD::FREM , MVT::f80 , Expand);
318 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
320 // Promote the i8 variants and force them on up to i32 which has a shorter
322 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
323 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
325 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
326 if (Subtarget->hasBMI()) {
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
328 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
329 if (Subtarget->is64Bit())
330 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
332 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
333 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
334 if (Subtarget->is64Bit())
335 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
338 if (Subtarget->hasLZCNT()) {
339 // When promoting the i8 variants, force them to i32 for a shorter
341 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
342 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
344 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
345 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
347 if (Subtarget->is64Bit())
348 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
350 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
351 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
352 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
353 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
354 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
355 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
356 if (Subtarget->is64Bit()) {
357 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
358 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
362 // Special handling for half-precision floating point conversions.
363 // If we don't have F16C support, then lower half float conversions
364 // into library calls.
365 if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {
366 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
367 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
370 // There's never any support for operations beyond MVT::f32.
371 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
372 setOperationAction(ISD::FP16_TO_FP, MVT::f80, Expand);
373 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
374 setOperationAction(ISD::FP_TO_FP16, MVT::f80, Expand);
376 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
377 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
378 setLoadExtAction(ISD::EXTLOAD, MVT::f80, MVT::f16, Expand);
379 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
380 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
381 setTruncStoreAction(MVT::f80, MVT::f16, Expand);
383 if (Subtarget->hasPOPCNT()) {
384 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
386 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
387 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
388 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
389 if (Subtarget->is64Bit())
390 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
393 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
395 if (!Subtarget->hasMOVBE())
396 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
398 // These should be promoted to a larger select which is supported.
399 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
400 // X86 wants to expand cmov itself.
401 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
402 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
403 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
404 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
405 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
406 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
407 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
408 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
409 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
410 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
411 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
412 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
413 if (Subtarget->is64Bit()) {
414 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
415 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
417 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
418 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
419 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
420 // support continuation, user-level threading, and etc.. As a result, no
421 // other SjLj exception interfaces are implemented and please don't build
422 // your own exception handling based on them.
423 // LLVM/Clang supports zero-cost DWARF exception handling.
424 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
425 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
428 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
429 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
430 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
431 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
432 if (Subtarget->is64Bit())
433 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
434 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
435 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
436 if (Subtarget->is64Bit()) {
437 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
438 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
439 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
440 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
441 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
443 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
444 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
445 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
446 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
447 if (Subtarget->is64Bit()) {
448 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
449 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
450 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
453 if (Subtarget->hasSSE1())
454 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
456 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
458 // Expand certain atomics
459 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
461 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Custom);
462 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
463 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
466 if (Subtarget->hasCmpxchg16b()) {
467 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i128, Custom);
470 // FIXME - use subtarget debug flags
471 if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() &&
472 !Subtarget->isTargetCygMing() && !Subtarget->isTargetWin64()) {
473 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
476 if (Subtarget->is64Bit()) {
477 setExceptionPointerRegister(X86::RAX);
478 setExceptionSelectorRegister(X86::RDX);
480 setExceptionPointerRegister(X86::EAX);
481 setExceptionSelectorRegister(X86::EDX);
483 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
484 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
486 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
487 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
489 setOperationAction(ISD::TRAP, MVT::Other, Legal);
490 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
492 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
493 setOperationAction(ISD::VASTART , MVT::Other, Custom);
494 setOperationAction(ISD::VAEND , MVT::Other, Expand);
495 if (Subtarget->is64Bit() && !Subtarget->isTargetWin64()) {
496 // TargetInfo::X86_64ABIBuiltinVaList
497 setOperationAction(ISD::VAARG , MVT::Other, Custom);
498 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
500 // TargetInfo::CharPtrBuiltinVaList
501 setOperationAction(ISD::VAARG , MVT::Other, Expand);
502 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
505 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
506 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
508 setOperationAction(ISD::DYNAMIC_STACKALLOC, getPointerTy(), Custom);
510 // GC_TRANSITION_START and GC_TRANSITION_END need custom lowering.
511 setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);
512 setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);
514 if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {
515 // f32 and f64 use SSE.
516 // Set up the FP register classes.
517 addRegisterClass(MVT::f32, &X86::FR32RegClass);
518 addRegisterClass(MVT::f64, &X86::FR64RegClass);
520 // Use ANDPD to simulate FABS.
521 setOperationAction(ISD::FABS , MVT::f64, Custom);
522 setOperationAction(ISD::FABS , MVT::f32, Custom);
524 // Use XORP to simulate FNEG.
525 setOperationAction(ISD::FNEG , MVT::f64, Custom);
526 setOperationAction(ISD::FNEG , MVT::f32, Custom);
528 // Use ANDPD and ORPD to simulate FCOPYSIGN.
529 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
530 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
532 // Lower this to FGETSIGNx86 plus an AND.
533 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
534 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
536 // We don't support sin/cos/fmod
537 setOperationAction(ISD::FSIN , MVT::f64, Expand);
538 setOperationAction(ISD::FCOS , MVT::f64, Expand);
539 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
540 setOperationAction(ISD::FSIN , MVT::f32, Expand);
541 setOperationAction(ISD::FCOS , MVT::f32, Expand);
542 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
544 // Expand FP immediates into loads from the stack, except for the special
546 addLegalFPImmediate(APFloat(+0.0)); // xorpd
547 addLegalFPImmediate(APFloat(+0.0f)); // xorps
548 } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {
549 // Use SSE for f32, x87 for f64.
550 // Set up the FP register classes.
551 addRegisterClass(MVT::f32, &X86::FR32RegClass);
552 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
554 // Use ANDPS to simulate FABS.
555 setOperationAction(ISD::FABS , MVT::f32, Custom);
557 // Use XORP to simulate FNEG.
558 setOperationAction(ISD::FNEG , MVT::f32, Custom);
560 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
562 // Use ANDPS and ORPS to simulate FCOPYSIGN.
563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
566 // We don't support sin/cos/fmod
567 setOperationAction(ISD::FSIN , MVT::f32, Expand);
568 setOperationAction(ISD::FCOS , MVT::f32, Expand);
569 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
571 // Special cases we handle for FP constants.
572 addLegalFPImmediate(APFloat(+0.0f)); // xorps
573 addLegalFPImmediate(APFloat(+0.0)); // FLD0
574 addLegalFPImmediate(APFloat(+1.0)); // FLD1
575 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
576 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
578 if (!TM.Options.UnsafeFPMath) {
579 setOperationAction(ISD::FSIN , MVT::f64, Expand);
580 setOperationAction(ISD::FCOS , MVT::f64, Expand);
581 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
583 } else if (!Subtarget->useSoftFloat()) {
584 // f32 and f64 in x87.
585 // Set up the FP register classes.
586 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
587 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
589 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
590 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
591 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
592 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
594 if (!TM.Options.UnsafeFPMath) {
595 setOperationAction(ISD::FSIN , MVT::f64, Expand);
596 setOperationAction(ISD::FSIN , MVT::f32, Expand);
597 setOperationAction(ISD::FCOS , MVT::f64, Expand);
598 setOperationAction(ISD::FCOS , MVT::f32, Expand);
599 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
600 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
602 addLegalFPImmediate(APFloat(+0.0)); // FLD0
603 addLegalFPImmediate(APFloat(+1.0)); // FLD1
604 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
605 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
606 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
607 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
608 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
609 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
612 // We don't support FMA.
613 setOperationAction(ISD::FMA, MVT::f64, Expand);
614 setOperationAction(ISD::FMA, MVT::f32, Expand);
616 // Long double always uses X87.
617 if (!Subtarget->useSoftFloat()) {
618 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
619 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
620 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
622 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
623 addLegalFPImmediate(TmpFlt); // FLD0
625 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
628 APFloat TmpFlt2(+1.0);
629 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
631 addLegalFPImmediate(TmpFlt2); // FLD1
632 TmpFlt2.changeSign();
633 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
636 if (!TM.Options.UnsafeFPMath) {
637 setOperationAction(ISD::FSIN , MVT::f80, Expand);
638 setOperationAction(ISD::FCOS , MVT::f80, Expand);
639 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
642 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
643 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
644 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
645 setOperationAction(ISD::FRINT, MVT::f80, Expand);
646 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
647 setOperationAction(ISD::FMA, MVT::f80, Expand);
650 // Always use a library call for pow.
651 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
652 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
653 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
655 setOperationAction(ISD::FLOG, MVT::f80, Expand);
656 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
657 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
658 setOperationAction(ISD::FEXP, MVT::f80, Expand);
659 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
660 setOperationAction(ISD::FMINNUM, MVT::f80, Expand);
661 setOperationAction(ISD::FMAXNUM, MVT::f80, Expand);
663 // First set operation action for all vector types to either promote
664 // (for widening) or expand (for scalarization). Then we will selectively
665 // turn on ones that can be effectively codegen'd.
666 for (MVT VT : MVT::vector_valuetypes()) {
667 setOperationAction(ISD::ADD , VT, Expand);
668 setOperationAction(ISD::SUB , VT, Expand);
669 setOperationAction(ISD::FADD, VT, Expand);
670 setOperationAction(ISD::FNEG, VT, Expand);
671 setOperationAction(ISD::FSUB, VT, Expand);
672 setOperationAction(ISD::MUL , VT, Expand);
673 setOperationAction(ISD::FMUL, VT, Expand);
674 setOperationAction(ISD::SDIV, VT, Expand);
675 setOperationAction(ISD::UDIV, VT, Expand);
676 setOperationAction(ISD::FDIV, VT, Expand);
677 setOperationAction(ISD::SREM, VT, Expand);
678 setOperationAction(ISD::UREM, VT, Expand);
679 setOperationAction(ISD::LOAD, VT, Expand);
680 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
682 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
683 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
684 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
685 setOperationAction(ISD::FABS, VT, Expand);
686 setOperationAction(ISD::FSIN, VT, Expand);
687 setOperationAction(ISD::FSINCOS, VT, Expand);
688 setOperationAction(ISD::FCOS, VT, Expand);
689 setOperationAction(ISD::FSINCOS, VT, Expand);
690 setOperationAction(ISD::FREM, VT, Expand);
691 setOperationAction(ISD::FMA, VT, Expand);
692 setOperationAction(ISD::FPOWI, VT, Expand);
693 setOperationAction(ISD::FSQRT, VT, Expand);
694 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
695 setOperationAction(ISD::FFLOOR, VT, Expand);
696 setOperationAction(ISD::FCEIL, VT, Expand);
697 setOperationAction(ISD::FTRUNC, VT, Expand);
698 setOperationAction(ISD::FRINT, VT, Expand);
699 setOperationAction(ISD::FNEARBYINT, VT, Expand);
700 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
701 setOperationAction(ISD::MULHS, VT, Expand);
702 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
703 setOperationAction(ISD::MULHU, VT, Expand);
704 setOperationAction(ISD::SDIVREM, VT, Expand);
705 setOperationAction(ISD::UDIVREM, VT, Expand);
706 setOperationAction(ISD::FPOW, VT, Expand);
707 setOperationAction(ISD::CTPOP, VT, Expand);
708 setOperationAction(ISD::CTTZ, VT, Expand);
709 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
710 setOperationAction(ISD::CTLZ, VT, Expand);
711 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
712 setOperationAction(ISD::SHL, VT, Expand);
713 setOperationAction(ISD::SRA, VT, Expand);
714 setOperationAction(ISD::SRL, VT, Expand);
715 setOperationAction(ISD::ROTL, VT, Expand);
716 setOperationAction(ISD::ROTR, VT, Expand);
717 setOperationAction(ISD::BSWAP, VT, Expand);
718 setOperationAction(ISD::SETCC, VT, Expand);
719 setOperationAction(ISD::FLOG, VT, Expand);
720 setOperationAction(ISD::FLOG2, VT, Expand);
721 setOperationAction(ISD::FLOG10, VT, Expand);
722 setOperationAction(ISD::FEXP, VT, Expand);
723 setOperationAction(ISD::FEXP2, VT, Expand);
724 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
725 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
726 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
727 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
728 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
729 setOperationAction(ISD::TRUNCATE, VT, Expand);
730 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
731 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
732 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
733 setOperationAction(ISD::VSELECT, VT, Expand);
734 setOperationAction(ISD::SELECT_CC, VT, Expand);
735 for (MVT InnerVT : MVT::vector_valuetypes()) {
736 setTruncStoreAction(InnerVT, VT, Expand);
738 setLoadExtAction(ISD::SEXTLOAD, InnerVT, VT, Expand);
739 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
741 // N.b. ISD::EXTLOAD legality is basically ignored except for i1-like
742 // types, we have to deal with them whether we ask for Expansion or not.
743 // Setting Expand causes its own optimisation problems though, so leave
745 if (VT.getVectorElementType() == MVT::i1)
746 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
748 // EXTLOAD for MVT::f16 vectors is not legal because f16 vectors are
749 // split/scalarized right now.
750 if (VT.getVectorElementType() == MVT::f16)
751 setLoadExtAction(ISD::EXTLOAD, InnerVT, VT, Expand);
755 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
756 // with -msoft-float, disable use of MMX as well.
757 if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {
758 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
759 // No operations on x86mmx supported, everything uses intrinsics.
762 // MMX-sized vectors (other than x86mmx) are expected to be expanded
763 // into smaller operations.
764 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) {
765 setOperationAction(ISD::MULHS, MMXTy, Expand);
766 setOperationAction(ISD::AND, MMXTy, Expand);
767 setOperationAction(ISD::OR, MMXTy, Expand);
768 setOperationAction(ISD::XOR, MMXTy, Expand);
769 setOperationAction(ISD::SCALAR_TO_VECTOR, MMXTy, Expand);
770 setOperationAction(ISD::SELECT, MMXTy, Expand);
771 setOperationAction(ISD::BITCAST, MMXTy, Expand);
773 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
775 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {
776 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
778 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
779 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
780 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
782 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
783 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
784 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
785 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
786 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
787 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
788 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
789 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
790 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
791 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);
794 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {
795 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
797 // FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM
798 // registers cannot be used even for integer operations.
799 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
800 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
801 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
802 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
804 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
805 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
806 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
807 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
808 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
809 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
810 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
811 setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom);
812 setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom);
813 setOperationAction(ISD::MULHU, MVT::v8i16, Legal);
814 setOperationAction(ISD::MULHS, MVT::v8i16, Legal);
815 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
816 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
817 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
818 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
819 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
820 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
821 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
822 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
823 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
824 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
825 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
826 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
828 setOperationAction(ISD::SMAX, MVT::v8i16, Legal);
829 setOperationAction(ISD::UMAX, MVT::v16i8, Legal);
830 setOperationAction(ISD::SMIN, MVT::v8i16, Legal);
831 setOperationAction(ISD::UMIN, MVT::v16i8, Legal);
833 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
834 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
835 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
836 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
844 setOperationAction(ISD::CTPOP, MVT::v16i8, Custom);
845 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
846 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
847 setOperationAction(ISD::CTPOP, MVT::v2i64, Custom);
849 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
850 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
851 MVT VT = (MVT::SimpleValueType)i;
852 // Do not attempt to custom lower non-power-of-2 vectors
853 if (!isPowerOf2_32(VT.getVectorNumElements()))
855 // Do not attempt to custom lower non-128-bit vectors
856 if (!VT.is128BitVector())
858 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
859 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
860 setOperationAction(ISD::VSELECT, VT, Custom);
861 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
864 // We support custom legalizing of sext and anyext loads for specific
865 // memory vector types which we can load as a scalar (or sequence of
866 // scalars) and extend in-register to a legal 128-bit vector type. For sext
867 // loads these must work with a single scalar load.
868 for (MVT VT : MVT::integer_vector_valuetypes()) {
869 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Custom);
870 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom);
871 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v8i8, Custom);
872 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Custom);
873 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Custom);
874 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i32, Custom);
875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Custom);
876 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom);
877 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
880 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
881 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
882 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
883 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
884 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
885 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
886 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
887 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
889 if (Subtarget->is64Bit()) {
890 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
891 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
894 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
895 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
896 MVT VT = (MVT::SimpleValueType)i;
898 // Do not attempt to promote non-128-bit vectors
899 if (!VT.is128BitVector())
902 setOperationAction(ISD::AND, VT, Promote);
903 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
904 setOperationAction(ISD::OR, VT, Promote);
905 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
906 setOperationAction(ISD::XOR, VT, Promote);
907 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
908 setOperationAction(ISD::LOAD, VT, Promote);
909 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
910 setOperationAction(ISD::SELECT, VT, Promote);
911 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
914 // Custom lower v2i64 and v2f64 selects.
915 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
916 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
917 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
918 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
920 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
921 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
923 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
925 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
926 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
927 // As there is no 64-bit GPR available, we need build a special custom
928 // sequence to convert from v2i32 to v2f32.
929 if (!Subtarget->is64Bit())
930 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
932 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
933 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
935 for (MVT VT : MVT::fp_vector_valuetypes())
936 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2f32, Legal);
938 setOperationAction(ISD::BITCAST, MVT::v2i32, Custom);
939 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom);
940 setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);
943 if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {
944 for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {
945 setOperationAction(ISD::FFLOOR, RoundedTy, Legal);
946 setOperationAction(ISD::FCEIL, RoundedTy, Legal);
947 setOperationAction(ISD::FTRUNC, RoundedTy, Legal);
948 setOperationAction(ISD::FRINT, RoundedTy, Legal);
949 setOperationAction(ISD::FNEARBYINT, RoundedTy, Legal);
952 setOperationAction(ISD::SMAX, MVT::v16i8, Legal);
953 setOperationAction(ISD::SMAX, MVT::v4i32, Legal);
954 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
955 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
956 setOperationAction(ISD::SMIN, MVT::v16i8, Legal);
957 setOperationAction(ISD::SMIN, MVT::v4i32, Legal);
958 setOperationAction(ISD::UMIN, MVT::v8i16, Legal);
959 setOperationAction(ISD::UMIN, MVT::v4i32, Legal);
961 // FIXME: Do we need to handle scalar-to-vector here?
962 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
964 // We directly match byte blends in the backend as they match the VSELECT
966 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
968 // SSE41 brings specific instructions for doing vector sign extend even in
969 // cases where we don't have SRA.
970 for (MVT VT : MVT::integer_vector_valuetypes()) {
971 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Custom);
972 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Custom);
973 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i32, Custom);
976 // SSE41 also has vector sign/zero extending loads, PMOV[SZ]X
977 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
978 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
979 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
980 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
981 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
982 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
984 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i16, MVT::v8i8, Legal);
985 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i8, Legal);
986 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i8, Legal);
987 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal);
988 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i16, Legal);
989 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i64, MVT::v2i32, Legal);
991 // i8 and i16 vectors are custom because the source register and source
992 // source memory operand types are not the same width. f32 vectors are
993 // custom since the immediate controlling the insert encodes additional
995 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
996 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
997 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
998 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1000 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1001 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1002 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1003 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1005 // FIXME: these should be Legal, but that's only for the case where
1006 // the index is constant. For now custom expand to deal with that.
1007 if (Subtarget->is64Bit()) {
1008 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1009 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1013 if (Subtarget->hasSSE2()) {
1014 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom);
1015 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom);
1016 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom);
1018 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1019 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1021 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1022 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1024 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1025 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1027 // In the customized shift lowering, the legal cases in AVX2 will be
1029 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1030 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1032 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1033 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1035 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1036 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1039 if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {
1040 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1041 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1042 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1043 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1044 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1045 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1047 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1048 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1049 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1051 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1052 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1053 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1054 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1055 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1056 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1057 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1058 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1059 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1060 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1061 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1062 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1064 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1065 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1066 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1067 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1068 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1069 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1070 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1071 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1072 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1073 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1074 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1075 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1077 // (fp_to_int:v8i16 (v8f32 ..)) requires the result type to be promoted
1078 // even though v8i16 is a legal type.
1079 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote);
1080 setOperationAction(ISD::FP_TO_UINT, MVT::v8i16, Promote);
1081 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1083 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1084 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1085 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1087 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1088 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1090 for (MVT VT : MVT::fp_vector_valuetypes())
1091 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4f32, Legal);
1093 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1094 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1096 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1097 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1099 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1100 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1102 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1103 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1104 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1105 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1107 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1108 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1109 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1111 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1112 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1113 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1114 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1115 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1116 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i16, Custom);
1117 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1118 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1119 setOperationAction(ISD::ANY_EXTEND, MVT::v16i16, Custom);
1120 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1121 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1122 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1124 setOperationAction(ISD::CTPOP, MVT::v32i8, Custom);
1125 setOperationAction(ISD::CTPOP, MVT::v16i16, Custom);
1126 setOperationAction(ISD::CTPOP, MVT::v8i32, Custom);
1127 setOperationAction(ISD::CTPOP, MVT::v4i64, Custom);
1129 if (Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()) {
1130 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1131 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1132 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1133 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1134 setOperationAction(ISD::FMA, MVT::f32, Legal);
1135 setOperationAction(ISD::FMA, MVT::f64, Legal);
1138 if (Subtarget->hasInt256()) {
1139 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1140 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1141 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1142 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1144 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1145 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1146 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1147 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1149 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1150 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1151 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1152 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1154 setOperationAction(ISD::UMUL_LOHI, MVT::v8i32, Custom);
1155 setOperationAction(ISD::SMUL_LOHI, MVT::v8i32, Custom);
1156 setOperationAction(ISD::MULHU, MVT::v16i16, Legal);
1157 setOperationAction(ISD::MULHS, MVT::v16i16, Legal);
1159 setOperationAction(ISD::SMAX, MVT::v32i8, Legal);
1160 setOperationAction(ISD::SMAX, MVT::v16i16, Legal);
1161 setOperationAction(ISD::SMAX, MVT::v8i32, Legal);
1162 setOperationAction(ISD::UMAX, MVT::v32i8, Legal);
1163 setOperationAction(ISD::UMAX, MVT::v16i16, Legal);
1164 setOperationAction(ISD::UMAX, MVT::v8i32, Legal);
1165 setOperationAction(ISD::SMIN, MVT::v32i8, Legal);
1166 setOperationAction(ISD::SMIN, MVT::v16i16, Legal);
1167 setOperationAction(ISD::SMIN, MVT::v8i32, Legal);
1168 setOperationAction(ISD::UMIN, MVT::v32i8, Legal);
1169 setOperationAction(ISD::UMIN, MVT::v16i16, Legal);
1170 setOperationAction(ISD::UMIN, MVT::v8i32, Legal);
1172 // The custom lowering for UINT_TO_FP for v8i32 becomes interesting
1173 // when we have a 256bit-wide blend with immediate.
1174 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Custom);
1176 // AVX2 also has wider vector sign/zero extending loads, VPMOV[SZ]X
1177 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1178 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1179 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1180 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1181 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1182 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1184 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i16, MVT::v16i8, Legal);
1185 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i8, Legal);
1186 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i8, Legal);
1187 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i32, MVT::v8i16, Legal);
1188 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal);
1189 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i32, Legal);
1191 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1192 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1193 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1194 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1196 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1197 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1198 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1199 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1201 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1202 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1203 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1204 setOperationAction(ISD::MUL, MVT::v32i8, Custom);
1207 // In the customized shift lowering, the legal cases in AVX2 will be
1209 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1210 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1212 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1213 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1215 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1216 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1218 // Custom lower several nodes for 256-bit types.
1219 for (MVT VT : MVT::vector_valuetypes()) {
1220 if (VT.getScalarSizeInBits() >= 32) {
1221 setOperationAction(ISD::MLOAD, VT, Legal);
1222 setOperationAction(ISD::MSTORE, VT, Legal);
1224 // Extract subvector is special because the value type
1225 // (result) is 128-bit but the source is 256-bit wide.
1226 if (VT.is128BitVector()) {
1227 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1229 // Do not attempt to custom lower other non-256-bit vectors
1230 if (!VT.is256BitVector())
1233 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1234 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1235 setOperationAction(ISD::VSELECT, VT, Custom);
1236 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1237 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1238 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1239 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1240 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1243 if (Subtarget->hasInt256())
1244 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1247 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1248 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1249 MVT VT = (MVT::SimpleValueType)i;
1251 // Do not attempt to promote non-256-bit vectors
1252 if (!VT.is256BitVector())
1255 setOperationAction(ISD::AND, VT, Promote);
1256 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1257 setOperationAction(ISD::OR, VT, Promote);
1258 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1259 setOperationAction(ISD::XOR, VT, Promote);
1260 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1261 setOperationAction(ISD::LOAD, VT, Promote);
1262 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1263 setOperationAction(ISD::SELECT, VT, Promote);
1264 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1268 if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {
1269 addRegisterClass(MVT::v16i32, &X86::VR512RegClass);
1270 addRegisterClass(MVT::v16f32, &X86::VR512RegClass);
1271 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1272 addRegisterClass(MVT::v8f64, &X86::VR512RegClass);
1274 addRegisterClass(MVT::i1, &X86::VK1RegClass);
1275 addRegisterClass(MVT::v8i1, &X86::VK8RegClass);
1276 addRegisterClass(MVT::v16i1, &X86::VK16RegClass);
1278 for (MVT VT : MVT::fp_vector_valuetypes())
1279 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8f32, Legal);
1281 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1282 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i8, Legal);
1283 setLoadExtAction(ISD::ZEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1284 setLoadExtAction(ISD::SEXTLOAD, MVT::v16i32, MVT::v16i16, Legal);
1285 setLoadExtAction(ISD::ZEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1286 setLoadExtAction(ISD::SEXTLOAD, MVT::v32i16, MVT::v32i8, Legal);
1287 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1288 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1289 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1290 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1291 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1292 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1294 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
1295 setOperationAction(ISD::SETCC, MVT::i1, Custom);
1296 setOperationAction(ISD::XOR, MVT::i1, Legal);
1297 setOperationAction(ISD::OR, MVT::i1, Legal);
1298 setOperationAction(ISD::AND, MVT::i1, Legal);
1299 setOperationAction(ISD::SUB, MVT::i1, Custom);
1300 setOperationAction(ISD::ADD, MVT::i1, Custom);
1301 setOperationAction(ISD::MUL, MVT::i1, Custom);
1302 setOperationAction(ISD::LOAD, MVT::v16f32, Legal);
1303 setOperationAction(ISD::LOAD, MVT::v8f64, Legal);
1304 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1305 setOperationAction(ISD::LOAD, MVT::v16i32, Legal);
1306 setOperationAction(ISD::LOAD, MVT::v16i1, Legal);
1308 setOperationAction(ISD::FADD, MVT::v16f32, Legal);
1309 setOperationAction(ISD::FSUB, MVT::v16f32, Legal);
1310 setOperationAction(ISD::FMUL, MVT::v16f32, Legal);
1311 setOperationAction(ISD::FDIV, MVT::v16f32, Legal);
1312 setOperationAction(ISD::FSQRT, MVT::v16f32, Legal);
1313 setOperationAction(ISD::FNEG, MVT::v16f32, Custom);
1315 setOperationAction(ISD::FADD, MVT::v8f64, Legal);
1316 setOperationAction(ISD::FSUB, MVT::v8f64, Legal);
1317 setOperationAction(ISD::FMUL, MVT::v8f64, Legal);
1318 setOperationAction(ISD::FDIV, MVT::v8f64, Legal);
1319 setOperationAction(ISD::FSQRT, MVT::v8f64, Legal);
1320 setOperationAction(ISD::FNEG, MVT::v8f64, Custom);
1321 setOperationAction(ISD::FMA, MVT::v8f64, Legal);
1322 setOperationAction(ISD::FMA, MVT::v16f32, Legal);
1324 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal);
1325 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Legal);
1326 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Legal);
1327 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
1328 if (Subtarget->is64Bit()) {
1329 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Legal);
1330 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal);
1331 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Legal);
1332 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Legal);
1334 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal);
1335 setOperationAction(ISD::FP_TO_UINT, MVT::v16i32, Legal);
1336 setOperationAction(ISD::FP_TO_UINT, MVT::v8i32, Legal);
1337 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
1338 setOperationAction(ISD::SINT_TO_FP, MVT::v16i32, Legal);
1339 setOperationAction(ISD::SINT_TO_FP, MVT::v8i1, Custom);
1340 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom);
1341 setOperationAction(ISD::SINT_TO_FP, MVT::v16i8, Promote);
1342 setOperationAction(ISD::SINT_TO_FP, MVT::v16i16, Promote);
1343 setOperationAction(ISD::UINT_TO_FP, MVT::v16i32, Legal);
1344 setOperationAction(ISD::UINT_TO_FP, MVT::v8i32, Legal);
1345 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
1346 setOperationAction(ISD::UINT_TO_FP, MVT::v16i8, Custom);
1347 setOperationAction(ISD::UINT_TO_FP, MVT::v16i16, Custom);
1348 setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);
1349 setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);
1351 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
1352 setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);
1353 setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);
1354 if (Subtarget->hasDQI()) {
1355 setOperationAction(ISD::TRUNCATE, MVT::v2i1, Custom);
1356 setOperationAction(ISD::TRUNCATE, MVT::v4i1, Custom);
1358 setOperationAction(ISD::TRUNCATE, MVT::v8i1, Custom);
1359 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom);
1360 setOperationAction(ISD::TRUNCATE, MVT::v16i16, Custom);
1361 setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
1362 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1363 setOperationAction(ISD::ANY_EXTEND, MVT::v16i32, Custom);
1364 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1365 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i32, Custom);
1366 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1367 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i8, Custom);
1368 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i16, Custom);
1369 setOperationAction(ISD::SIGN_EXTEND, MVT::v16i16, Custom);
1370 if (Subtarget->hasDQI()) {
1371 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i32, Custom);
1372 setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Custom);
1374 setOperationAction(ISD::FFLOOR, MVT::v16f32, Legal);
1375 setOperationAction(ISD::FFLOOR, MVT::v8f64, Legal);
1376 setOperationAction(ISD::FCEIL, MVT::v16f32, Legal);
1377 setOperationAction(ISD::FCEIL, MVT::v8f64, Legal);
1378 setOperationAction(ISD::FTRUNC, MVT::v16f32, Legal);
1379 setOperationAction(ISD::FTRUNC, MVT::v8f64, Legal);
1380 setOperationAction(ISD::FRINT, MVT::v16f32, Legal);
1381 setOperationAction(ISD::FRINT, MVT::v8f64, Legal);
1382 setOperationAction(ISD::FNEARBYINT, MVT::v16f32, Legal);
1383 setOperationAction(ISD::FNEARBYINT, MVT::v8f64, Legal);
1385 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f64, Custom);
1386 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1387 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16f32, Custom);
1388 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i32, Custom);
1389 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal);
1391 setOperationAction(ISD::SETCC, MVT::v16i1, Custom);
1392 setOperationAction(ISD::SETCC, MVT::v8i1, Custom);
1394 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1396 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i1, Custom);
1397 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom);
1398 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom);
1399 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i1, Custom);
1400 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom);
1401 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom);
1402 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
1403 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1404 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
1405 setOperationAction(ISD::SELECT, MVT::v16i1, Custom);
1406 setOperationAction(ISD::SELECT, MVT::v8i1, Custom);
1408 setOperationAction(ISD::SMAX, MVT::v16i32, Legal);
1409 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1410 setOperationAction(ISD::UMAX, MVT::v16i32, Legal);
1411 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1412 setOperationAction(ISD::SMIN, MVT::v16i32, Legal);
1413 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1414 setOperationAction(ISD::UMIN, MVT::v16i32, Legal);
1415 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1417 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1418 setOperationAction(ISD::ADD, MVT::v16i32, Legal);
1420 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1421 setOperationAction(ISD::SUB, MVT::v16i32, Legal);
1423 setOperationAction(ISD::MUL, MVT::v16i32, Legal);
1425 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1426 setOperationAction(ISD::SRL, MVT::v16i32, Custom);
1428 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1429 setOperationAction(ISD::SHL, MVT::v16i32, Custom);
1431 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1432 setOperationAction(ISD::SRA, MVT::v16i32, Custom);
1434 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1435 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1436 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1437 setOperationAction(ISD::AND, MVT::v16i32, Legal);
1438 setOperationAction(ISD::OR, MVT::v16i32, Legal);
1439 setOperationAction(ISD::XOR, MVT::v16i32, Legal);
1441 if (Subtarget->hasCDI()) {
1442 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1443 setOperationAction(ISD::CTLZ, MVT::v16i32, Legal);
1445 if (Subtarget->hasDQI()) {
1446 setOperationAction(ISD::MUL, MVT::v2i64, Legal);
1447 setOperationAction(ISD::MUL, MVT::v4i64, Legal);
1448 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1450 // Custom lower several nodes.
1451 for (MVT VT : MVT::vector_valuetypes()) {
1452 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1454 setOperationAction(ISD::AND, VT, Legal);
1455 setOperationAction(ISD::OR, VT, Legal);
1456 setOperationAction(ISD::XOR, VT, Legal);
1458 if (EltSize >= 32 && VT.getSizeInBits() <= 512) {
1459 setOperationAction(ISD::MGATHER, VT, Custom);
1460 setOperationAction(ISD::MSCATTER, VT, Custom);
1462 // Extract subvector is special because the value type
1463 // (result) is 256/128-bit but the source is 512-bit wide.
1464 if (VT.is128BitVector() || VT.is256BitVector()) {
1465 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1467 if (VT.getVectorElementType() == MVT::i1)
1468 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
1470 // Do not attempt to custom lower other non-512-bit vectors
1471 if (!VT.is512BitVector())
1474 if (EltSize >= 32) {
1475 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1476 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1477 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1478 setOperationAction(ISD::VSELECT, VT, Legal);
1479 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1480 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1481 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1482 setOperationAction(ISD::MLOAD, VT, Legal);
1483 setOperationAction(ISD::MSTORE, VT, Legal);
1486 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1487 MVT VT = (MVT::SimpleValueType)i;
1489 // Do not attempt to promote non-512-bit vectors.
1490 if (!VT.is512BitVector())
1493 setOperationAction(ISD::SELECT, VT, Promote);
1494 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1498 if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {
1499 addRegisterClass(MVT::v32i16, &X86::VR512RegClass);
1500 addRegisterClass(MVT::v64i8, &X86::VR512RegClass);
1502 addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
1503 addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
1505 setOperationAction(ISD::LOAD, MVT::v32i16, Legal);
1506 setOperationAction(ISD::LOAD, MVT::v64i8, Legal);
1507 setOperationAction(ISD::SETCC, MVT::v32i1, Custom);
1508 setOperationAction(ISD::SETCC, MVT::v64i1, Custom);
1509 setOperationAction(ISD::ADD, MVT::v32i16, Legal);
1510 setOperationAction(ISD::ADD, MVT::v64i8, Legal);
1511 setOperationAction(ISD::SUB, MVT::v32i16, Legal);
1512 setOperationAction(ISD::SUB, MVT::v64i8, Legal);
1513 setOperationAction(ISD::MUL, MVT::v32i16, Legal);
1514 setOperationAction(ISD::MULHS, MVT::v32i16, Legal);
1515 setOperationAction(ISD::MULHU, MVT::v32i16, Legal);
1516 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom);
1517 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i1, Custom);
1518 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom);
1519 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v64i1, Custom);
1520 setOperationAction(ISD::SELECT, MVT::v32i1, Custom);
1521 setOperationAction(ISD::SELECT, MVT::v64i1, Custom);
1522 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i8, Custom);
1523 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i8, Custom);
1524 setOperationAction(ISD::SIGN_EXTEND, MVT::v32i16, Custom);
1525 setOperationAction(ISD::ZERO_EXTEND, MVT::v32i16, Custom);
1526 setOperationAction(ISD::SIGN_EXTEND, MVT::v64i8, Custom);
1527 setOperationAction(ISD::ZERO_EXTEND, MVT::v64i8, Custom);
1528 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom);
1529 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v64i1, Custom);
1530 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1531 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1532 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);
1533 setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);
1535 setOperationAction(ISD::SMAX, MVT::v64i8, Legal);
1536 setOperationAction(ISD::SMAX, MVT::v32i16, Legal);
1537 setOperationAction(ISD::UMAX, MVT::v64i8, Legal);
1538 setOperationAction(ISD::UMAX, MVT::v32i16, Legal);
1539 setOperationAction(ISD::SMIN, MVT::v64i8, Legal);
1540 setOperationAction(ISD::SMIN, MVT::v32i16, Legal);
1541 setOperationAction(ISD::UMIN, MVT::v64i8, Legal);
1542 setOperationAction(ISD::UMIN, MVT::v32i16, Legal);
1544 for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {
1545 const MVT VT = (MVT::SimpleValueType)i;
1547 const unsigned EltSize = VT.getVectorElementType().getSizeInBits();
1549 // Do not attempt to promote non-512-bit vectors.
1550 if (!VT.is512BitVector())
1554 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1555 setOperationAction(ISD::VSELECT, VT, Legal);
1560 if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {
1561 addRegisterClass(MVT::v4i1, &X86::VK4RegClass);
1562 addRegisterClass(MVT::v2i1, &X86::VK2RegClass);
1564 setOperationAction(ISD::SETCC, MVT::v4i1, Custom);
1565 setOperationAction(ISD::SETCC, MVT::v2i1, Custom);
1566 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i1, Custom);
1567 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i1, Custom);
1568 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v8i1, Custom);
1569 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v4i1, Custom);
1570 setOperationAction(ISD::SELECT, MVT::v4i1, Custom);
1571 setOperationAction(ISD::SELECT, MVT::v2i1, Custom);
1572 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
1573 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i1, Custom);
1575 setOperationAction(ISD::AND, MVT::v8i32, Legal);
1576 setOperationAction(ISD::OR, MVT::v8i32, Legal);
1577 setOperationAction(ISD::XOR, MVT::v8i32, Legal);
1578 setOperationAction(ISD::AND, MVT::v4i32, Legal);
1579 setOperationAction(ISD::OR, MVT::v4i32, Legal);
1580 setOperationAction(ISD::XOR, MVT::v4i32, Legal);
1581 setOperationAction(ISD::SRA, MVT::v2i64, Custom);
1582 setOperationAction(ISD::SRA, MVT::v4i64, Custom);
1584 setOperationAction(ISD::SMAX, MVT::v2i64, Legal);
1585 setOperationAction(ISD::SMAX, MVT::v4i64, Legal);
1586 setOperationAction(ISD::UMAX, MVT::v2i64, Legal);
1587 setOperationAction(ISD::UMAX, MVT::v4i64, Legal);
1588 setOperationAction(ISD::SMIN, MVT::v2i64, Legal);
1589 setOperationAction(ISD::SMIN, MVT::v4i64, Legal);
1590 setOperationAction(ISD::UMIN, MVT::v2i64, Legal);
1591 setOperationAction(ISD::UMIN, MVT::v4i64, Legal);
1594 // We want to custom lower some of our intrinsics.
1595 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1596 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1597 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
1598 if (!Subtarget->is64Bit())
1599 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
1601 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1602 // handle type legalization for these operations here.
1604 // FIXME: We really should do custom legalization for addition and
1605 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1606 // than generic legalization for 64-bit multiplication-with-overflow, though.
1607 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1608 // Add/Sub/Mul with overflow operations are custom lowered.
1610 setOperationAction(ISD::SADDO, VT, Custom);
1611 setOperationAction(ISD::UADDO, VT, Custom);
1612 setOperationAction(ISD::SSUBO, VT, Custom);
1613 setOperationAction(ISD::USUBO, VT, Custom);
1614 setOperationAction(ISD::SMULO, VT, Custom);
1615 setOperationAction(ISD::UMULO, VT, Custom);
1619 if (!Subtarget->is64Bit()) {
1620 // These libcalls are not available in 32-bit.
1621 setLibcallName(RTLIB::SHL_I128, nullptr);
1622 setLibcallName(RTLIB::SRL_I128, nullptr);
1623 setLibcallName(RTLIB::SRA_I128, nullptr);
1626 // Combine sin / cos into one node or libcall if possible.
1627 if (Subtarget->hasSinCos()) {
1628 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1629 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1630 if (Subtarget->isTargetDarwin()) {
1631 // For MacOSX, we don't want the normal expansion of a libcall to sincos.
1632 // We want to issue a libcall to __sincos_stret to avoid memory traffic.
1633 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1634 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1638 if (Subtarget->isTargetWin64()) {
1639 setOperationAction(ISD::SDIV, MVT::i128, Custom);
1640 setOperationAction(ISD::UDIV, MVT::i128, Custom);
1641 setOperationAction(ISD::SREM, MVT::i128, Custom);
1642 setOperationAction(ISD::UREM, MVT::i128, Custom);
1643 setOperationAction(ISD::SDIVREM, MVT::i128, Custom);
1644 setOperationAction(ISD::UDIVREM, MVT::i128, Custom);
1647 // We have target-specific dag combine patterns for the following nodes:
1648 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1649 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1650 setTargetDAGCombine(ISD::BITCAST);
1651 setTargetDAGCombine(ISD::VSELECT);
1652 setTargetDAGCombine(ISD::SELECT);
1653 setTargetDAGCombine(ISD::SHL);
1654 setTargetDAGCombine(ISD::SRA);
1655 setTargetDAGCombine(ISD::SRL);
1656 setTargetDAGCombine(ISD::OR);
1657 setTargetDAGCombine(ISD::AND);
1658 setTargetDAGCombine(ISD::ADD);
1659 setTargetDAGCombine(ISD::FADD);
1660 setTargetDAGCombine(ISD::FSUB);
1661 setTargetDAGCombine(ISD::FMA);
1662 setTargetDAGCombine(ISD::SUB);
1663 setTargetDAGCombine(ISD::LOAD);
1664 setTargetDAGCombine(ISD::MLOAD);
1665 setTargetDAGCombine(ISD::STORE);
1666 setTargetDAGCombine(ISD::MSTORE);
1667 setTargetDAGCombine(ISD::ZERO_EXTEND);
1668 setTargetDAGCombine(ISD::ANY_EXTEND);
1669 setTargetDAGCombine(ISD::SIGN_EXTEND);
1670 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1671 setTargetDAGCombine(ISD::SINT_TO_FP);
1672 setTargetDAGCombine(ISD::UINT_TO_FP);
1673 setTargetDAGCombine(ISD::SETCC);
1674 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
1675 setTargetDAGCombine(ISD::BUILD_VECTOR);
1676 setTargetDAGCombine(ISD::MUL);
1677 setTargetDAGCombine(ISD::XOR);
1679 computeRegisterProperties(Subtarget->getRegisterInfo());
1681 // On Darwin, -Os means optimize for size without hurting performance,
1682 // do not reduce the limit.
1683 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1684 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1685 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1686 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1687 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1688 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1689 setPrefLoopAlignment(4); // 2^4 bytes.
1691 // Predictable cmov don't hurt on atom because it's in-order.
1692 PredictableSelectIsExpensive = !Subtarget->isAtom();
1693 EnableExtLdPromotion = true;
1694 setPrefFunctionAlignment(4); // 2^4 bytes.
1696 verifyIntrinsicTables();
1699 // This has so far only been implemented for 64-bit MachO.
1700 bool X86TargetLowering::useLoadStackGuardNode() const {
1701 return Subtarget->isTargetMachO() && Subtarget->is64Bit();
1704 TargetLoweringBase::LegalizeTypeAction
1705 X86TargetLowering::getPreferredVectorAction(EVT VT) const {
1706 if (ExperimentalVectorWideningLegalization &&
1707 VT.getVectorNumElements() != 1 &&
1708 VT.getVectorElementType().getSimpleVT() != MVT::i1)
1709 return TypeWidenVector;
1711 return TargetLoweringBase::getPreferredVectorAction(VT);
1714 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1716 return Subtarget->hasAVX512() ? MVT::i1: MVT::i8;
1718 const unsigned NumElts = VT.getVectorNumElements();
1719 const EVT EltVT = VT.getVectorElementType();
1720 if (VT.is512BitVector()) {
1721 if (Subtarget->hasAVX512())
1722 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1723 EltVT == MVT::f32 || EltVT == MVT::f64)
1725 case 8: return MVT::v8i1;
1726 case 16: return MVT::v16i1;
1728 if (Subtarget->hasBWI())
1729 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1731 case 32: return MVT::v32i1;
1732 case 64: return MVT::v64i1;
1736 if (VT.is256BitVector() || VT.is128BitVector()) {
1737 if (Subtarget->hasVLX())
1738 if (EltVT == MVT::i32 || EltVT == MVT::i64 ||
1739 EltVT == MVT::f32 || EltVT == MVT::f64)
1741 case 2: return MVT::v2i1;
1742 case 4: return MVT::v4i1;
1743 case 8: return MVT::v8i1;
1745 if (Subtarget->hasBWI() && Subtarget->hasVLX())
1746 if (EltVT == MVT::i8 || EltVT == MVT::i16)
1748 case 8: return MVT::v8i1;
1749 case 16: return MVT::v16i1;
1750 case 32: return MVT::v32i1;
1754 return VT.changeVectorElementTypeToInteger();
1757 /// Helper for getByValTypeAlignment to determine
1758 /// the desired ByVal argument alignment.
1759 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1762 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1763 if (VTy->getBitWidth() == 128)
1765 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1766 unsigned EltAlign = 0;
1767 getMaxByValAlign(ATy->getElementType(), EltAlign);
1768 if (EltAlign > MaxAlign)
1769 MaxAlign = EltAlign;
1770 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1771 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1772 unsigned EltAlign = 0;
1773 getMaxByValAlign(STy->getElementType(i), EltAlign);
1774 if (EltAlign > MaxAlign)
1775 MaxAlign = EltAlign;
1782 /// Return the desired alignment for ByVal aggregate
1783 /// function arguments in the caller parameter area. For X86, aggregates
1784 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1785 /// are at 4-byte boundaries.
1786 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1787 if (Subtarget->is64Bit()) {
1788 // Max of 8 and alignment of type.
1789 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1796 if (Subtarget->hasSSE1())
1797 getMaxByValAlign(Ty, Align);
1801 /// Returns the target specific optimal type for load
1802 /// and store operations as a result of memset, memcpy, and memmove
1803 /// lowering. If DstAlign is zero that means it's safe to destination
1804 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1805 /// means there isn't a need to check it against alignment requirement,
1806 /// probably because the source does not need to be loaded. If 'IsMemset' is
1807 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1808 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1809 /// source is constant so it does not need to be loaded.
1810 /// It returns EVT::Other if the type should be determined using generic
1811 /// target-independent logic.
1813 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1814 unsigned DstAlign, unsigned SrcAlign,
1815 bool IsMemset, bool ZeroMemset,
1817 MachineFunction &MF) const {
1818 const Function *F = MF.getFunction();
1819 if ((!IsMemset || ZeroMemset) &&
1820 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
1822 (Subtarget->isUnalignedMemAccessFast() ||
1823 ((DstAlign == 0 || DstAlign >= 16) &&
1824 (SrcAlign == 0 || SrcAlign >= 16)))) {
1826 if (Subtarget->hasInt256())
1828 if (Subtarget->hasFp256())
1831 if (Subtarget->hasSSE2())
1833 if (Subtarget->hasSSE1())
1835 } else if (!MemcpyStrSrc && Size >= 8 &&
1836 !Subtarget->is64Bit() &&
1837 Subtarget->hasSSE2()) {
1838 // Do not use f64 to lower memcpy if source is string constant. It's
1839 // better to use i32 to avoid the loads.
1843 if (Subtarget->is64Bit() && Size >= 8)
1848 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1850 return X86ScalarSSEf32;
1851 else if (VT == MVT::f64)
1852 return X86ScalarSSEf64;
1857 X86TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
1862 *Fast = Subtarget->isUnalignedMemAccessFast();
1866 /// Return the entry encoding for a jump table in the
1867 /// current function. The returned value is a member of the
1868 /// MachineJumpTableInfo::JTEntryKind enum.
1869 unsigned X86TargetLowering::getJumpTableEncoding() const {
1870 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1872 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1873 Subtarget->isPICStyleGOT())
1874 return MachineJumpTableInfo::EK_Custom32;
1876 // Otherwise, use the normal jump table encoding heuristics.
1877 return TargetLowering::getJumpTableEncoding();
1880 bool X86TargetLowering::useSoftFloat() const {
1881 return Subtarget->useSoftFloat();
1885 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1886 const MachineBasicBlock *MBB,
1887 unsigned uid,MCContext &Ctx) const{
1888 assert(MBB->getParent()->getTarget().getRelocationModel() == Reloc::PIC_ &&
1889 Subtarget->isPICStyleGOT());
1890 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1892 return MCSymbolRefExpr::create(MBB->getSymbol(),
1893 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1896 /// Returns relocation base for the given PIC jumptable.
1897 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1898 SelectionDAG &DAG) const {
1899 if (!Subtarget->is64Bit())
1900 // This doesn't have SDLoc associated with it, but is not really the
1901 // same as a Register.
1902 return DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy());
1906 /// This returns the relocation base for the given PIC jumptable,
1907 /// the same as getPICJumpTableRelocBase, but as an MCExpr.
1908 const MCExpr *X86TargetLowering::
1909 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1910 MCContext &Ctx) const {
1911 // X86-64 uses RIP relative addressing based on the jump table label.
1912 if (Subtarget->isPICStyleRIPRel())
1913 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1915 // Otherwise, the reference is relative to the PIC base.
1916 return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
1919 std::pair<const TargetRegisterClass *, uint8_t>
1920 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1922 const TargetRegisterClass *RRC = nullptr;
1924 switch (VT.SimpleTy) {
1926 return TargetLowering::findRepresentativeClass(TRI, VT);
1927 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1928 RRC = Subtarget->is64Bit() ? &X86::GR64RegClass : &X86::GR32RegClass;
1931 RRC = &X86::VR64RegClass;
1933 case MVT::f32: case MVT::f64:
1934 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1935 case MVT::v4f32: case MVT::v2f64:
1936 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1938 RRC = &X86::VR128RegClass;
1941 return std::make_pair(RRC, Cost);
1944 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1945 unsigned &Offset) const {
1946 if (!Subtarget->isTargetLinux())
1949 if (Subtarget->is64Bit()) {
1950 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1952 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1964 bool X86TargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
1965 unsigned DestAS) const {
1966 assert(SrcAS != DestAS && "Expected different address spaces!");
1968 return SrcAS < 256 && DestAS < 256;
1971 //===----------------------------------------------------------------------===//
1972 // Return Value Calling Convention Implementation
1973 //===----------------------------------------------------------------------===//
1975 #include "X86GenCallingConv.inc"
1978 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1979 MachineFunction &MF, bool isVarArg,
1980 const SmallVectorImpl<ISD::OutputArg> &Outs,
1981 LLVMContext &Context) const {
1982 SmallVector<CCValAssign, 16> RVLocs;
1983 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1984 return CCInfo.CheckReturn(Outs, RetCC_X86);
1987 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1988 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
1993 X86TargetLowering::LowerReturn(SDValue Chain,
1994 CallingConv::ID CallConv, bool isVarArg,
1995 const SmallVectorImpl<ISD::OutputArg> &Outs,
1996 const SmallVectorImpl<SDValue> &OutVals,
1997 SDLoc dl, SelectionDAG &DAG) const {
1998 MachineFunction &MF = DAG.getMachineFunction();
1999 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2001 SmallVector<CCValAssign, 16> RVLocs;
2002 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, *DAG.getContext());
2003 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
2006 SmallVector<SDValue, 6> RetOps;
2007 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2008 // Operand #1 = Bytes To Pop
2009 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,
2012 // Copy the result values into the output registers.
2013 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2014 CCValAssign &VA = RVLocs[i];
2015 assert(VA.isRegLoc() && "Can only return in registers!");
2016 SDValue ValToCopy = OutVals[i];
2017 EVT ValVT = ValToCopy.getValueType();
2019 // Promote values to the appropriate types.
2020 if (VA.getLocInfo() == CCValAssign::SExt)
2021 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2022 else if (VA.getLocInfo() == CCValAssign::ZExt)
2023 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
2024 else if (VA.getLocInfo() == CCValAssign::AExt) {
2025 if (ValVT.isVector() && ValVT.getScalarType() == MVT::i1)
2026 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
2028 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
2030 else if (VA.getLocInfo() == CCValAssign::BCvt)
2031 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy);
2033 assert(VA.getLocInfo() != CCValAssign::FPExt &&
2034 "Unexpected FP-extend for return value.");
2036 // If this is x86-64, and we disabled SSE, we can't return FP values,
2037 // or SSE or MMX vectors.
2038 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
2039 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
2040 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
2041 report_fatal_error("SSE register return with SSE disabled");
2043 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
2044 // llvm-gcc has never done it right and no one has noticed, so this
2045 // should be OK for now.
2046 if (ValVT == MVT::f64 &&
2047 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
2048 report_fatal_error("SSE2 register return with SSE2 disabled");
2050 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
2051 // the RET instruction and handled by the FP Stackifier.
2052 if (VA.getLocReg() == X86::FP0 ||
2053 VA.getLocReg() == X86::FP1) {
2054 // If this is a copy from an xmm register to ST(0), use an FPExtend to
2055 // change the value to the FP stack register class.
2056 if (isScalarFPTypeInSSEReg(VA.getValVT()))
2057 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
2058 RetOps.push_back(ValToCopy);
2059 // Don't emit a copytoreg.
2063 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
2064 // which is returned in RAX / RDX.
2065 if (Subtarget->is64Bit()) {
2066 if (ValVT == MVT::x86mmx) {
2067 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
2068 ValToCopy = DAG.getBitcast(MVT::i64, ValToCopy);
2069 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
2071 // If we don't have SSE2 available, convert to v4f32 so the generated
2072 // register is legal.
2073 if (!Subtarget->hasSSE2())
2074 ValToCopy = DAG.getBitcast(MVT::v4f32, ValToCopy);
2079 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
2080 Flag = Chain.getValue(1);
2081 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2084 // All x86 ABIs require that for returning structs by value we copy
2085 // the sret argument into %rax/%eax (depending on ABI) for the return.
2086 // We saved the argument into a virtual register in the entry block,
2087 // so now we copy the value out and into %rax/%eax.
2089 // Checking Function.hasStructRetAttr() here is insufficient because the IR
2090 // may not have an explicit sret argument. If FuncInfo.CanLowerReturn is
2091 // false, then an sret argument may be implicitly inserted in the SelDAG. In
2092 // either case FuncInfo->setSRetReturnReg() will have been called.
2093 if (unsigned SRetReg = FuncInfo->getSRetReturnReg()) {
2094 SDValue Val = DAG.getCopyFromReg(Chain, dl, SRetReg, getPointerTy());
2097 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
2098 X86::RAX : X86::EAX;
2099 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
2100 Flag = Chain.getValue(1);
2102 // RAX/EAX now acts like a return value.
2103 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
2106 RetOps[0] = Chain; // Update chain.
2108 // Add the flag if we have it.
2110 RetOps.push_back(Flag);
2112 return DAG.getNode(X86ISD::RET_FLAG, dl, MVT::Other, RetOps);
2115 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2116 if (N->getNumValues() != 1)
2118 if (!N->hasNUsesOfValue(1, 0))
2121 SDValue TCChain = Chain;
2122 SDNode *Copy = *N->use_begin();
2123 if (Copy->getOpcode() == ISD::CopyToReg) {
2124 // If the copy has a glue operand, we conservatively assume it isn't safe to
2125 // perform a tail call.
2126 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2128 TCChain = Copy->getOperand(0);
2129 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
2132 bool HasRet = false;
2133 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2135 if (UI->getOpcode() != X86ISD::RET_FLAG)
2137 // If we are returning more than one value, we can definitely
2138 // not make a tail call see PR19530
2139 if (UI->getNumOperands() > 4)
2141 if (UI->getNumOperands() == 4 &&
2142 UI->getOperand(UI->getNumOperands()-1).getValueType() != MVT::Glue)
2155 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2156 ISD::NodeType ExtendKind) const {
2158 // TODO: Is this also valid on 32-bit?
2159 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
2160 ReturnMVT = MVT::i8;
2162 ReturnMVT = MVT::i32;
2164 EVT MinVT = getRegisterType(Context, ReturnMVT);
2165 return VT.bitsLT(MinVT) ? MinVT : VT;
2168 /// Lower the result values of a call into the
2169 /// appropriate copies out of appropriate physical registers.
2172 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2173 CallingConv::ID CallConv, bool isVarArg,
2174 const SmallVectorImpl<ISD::InputArg> &Ins,
2175 SDLoc dl, SelectionDAG &DAG,
2176 SmallVectorImpl<SDValue> &InVals) const {
2178 // Assign locations to each value returned by this call.
2179 SmallVector<CCValAssign, 16> RVLocs;
2180 bool Is64Bit = Subtarget->is64Bit();
2181 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2183 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2185 // Copy all of the result registers out of their specified physreg.
2186 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2187 CCValAssign &VA = RVLocs[i];
2188 EVT CopyVT = VA.getLocVT();
2190 // If this is x86-64, and we disabled SSE, we can't return FP values
2191 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
2192 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
2193 report_fatal_error("SSE register return with SSE disabled");
2196 // If we prefer to use the value in xmm registers, copy it out as f80 and
2197 // use a truncate to move it from fp stack reg to xmm reg.
2198 bool RoundAfterCopy = false;
2199 if ((VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) &&
2200 isScalarFPTypeInSSEReg(VA.getValVT())) {
2202 RoundAfterCopy = (CopyVT != VA.getLocVT());
2205 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
2206 CopyVT, InFlag).getValue(1);
2207 SDValue Val = Chain.getValue(0);
2210 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
2211 // This truncation won't change the value.
2212 DAG.getIntPtrConstant(1, dl));
2214 if (VA.isExtInLoc() && VA.getValVT().getScalarType() == MVT::i1)
2215 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
2217 InFlag = Chain.getValue(2);
2218 InVals.push_back(Val);
2224 //===----------------------------------------------------------------------===//
2225 // C & StdCall & Fast Calling Convention implementation
2226 //===----------------------------------------------------------------------===//
2227 // StdCall calling convention seems to be standard for many Windows' API
2228 // routines and around. It differs from C calling convention just a little:
2229 // callee should clean up the stack, not caller. Symbols should be also
2230 // decorated in some fancy way :) It doesn't support any vector arguments.
2231 // For info on fast calling convention see Fast Calling Convention (tail call)
2232 // implementation LowerX86_32FastCCCallTo.
2234 /// CallIsStructReturn - Determines whether a call uses struct return
2236 enum StructReturnType {
2241 static StructReturnType
2242 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
2244 return NotStructReturn;
2246 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
2247 if (!Flags.isSRet())
2248 return NotStructReturn;
2249 if (Flags.isInReg())
2250 return RegStructReturn;
2251 return StackStructReturn;
2254 /// Determines whether a function uses struct return semantics.
2255 static StructReturnType
2256 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
2258 return NotStructReturn;
2260 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
2261 if (!Flags.isSRet())
2262 return NotStructReturn;
2263 if (Flags.isInReg())
2264 return RegStructReturn;
2265 return StackStructReturn;
2268 /// Make a copy of an aggregate at address specified by "Src" to address
2269 /// "Dst" with size and alignment information specified by the specific
2270 /// parameter attribute. The copy will be passed as a byval function parameter.
2272 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2273 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2275 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
2277 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2278 /*isVolatile*/false, /*AlwaysInline=*/true,
2279 /*isTailCall*/false,
2280 MachinePointerInfo(), MachinePointerInfo());
2283 /// Return true if the calling convention is one that
2284 /// supports tail call optimization.
2285 static bool IsTailCallConvention(CallingConv::ID CC) {
2286 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
2287 CC == CallingConv::HiPE);
2290 /// \brief Return true if the calling convention is a C calling convention.
2291 static bool IsCCallConvention(CallingConv::ID CC) {
2292 return (CC == CallingConv::C || CC == CallingConv::X86_64_Win64 ||
2293 CC == CallingConv::X86_64_SysV);
2296 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2298 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2299 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2303 CallingConv::ID CalleeCC = CS.getCallingConv();
2304 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
2310 /// Return true if the function is being made into
2311 /// a tailcall target by changing its ABI.
2312 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
2313 bool GuaranteedTailCallOpt) {
2314 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
2318 X86TargetLowering::LowerMemArgument(SDValue Chain,
2319 CallingConv::ID CallConv,
2320 const SmallVectorImpl<ISD::InputArg> &Ins,
2321 SDLoc dl, SelectionDAG &DAG,
2322 const CCValAssign &VA,
2323 MachineFrameInfo *MFI,
2325 // Create the nodes corresponding to a load from this parameter slot.
2326 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2327 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(
2328 CallConv, DAG.getTarget().Options.GuaranteedTailCallOpt);
2329 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
2332 // If value is passed by pointer we have address passed instead of the value
2334 bool ExtendedInMem = VA.isExtInLoc() &&
2335 VA.getValVT().getScalarType() == MVT::i1;
2337 if (VA.getLocInfo() == CCValAssign::Indirect || ExtendedInMem)
2338 ValVT = VA.getLocVT();
2340 ValVT = VA.getValVT();
2342 // FIXME: For now, all byval parameter objects are marked mutable. This can be
2343 // changed with more analysis.
2344 // In case of tail call optimization mark all arguments mutable. Since they
2345 // could be overwritten by lowering of arguments in case of a tail call.
2346 if (Flags.isByVal()) {
2347 unsigned Bytes = Flags.getByValSize();
2348 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2349 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
2350 return DAG.getFrameIndex(FI, getPointerTy());
2352 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
2353 VA.getLocMemOffset(), isImmutable);
2354 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2355 SDValue Val = DAG.getLoad(ValVT, dl, Chain, FIN,
2356 MachinePointerInfo::getFixedStack(FI),
2357 false, false, false, 0);
2358 return ExtendedInMem ?
2359 DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val) : Val;
2363 // FIXME: Get this from tablegen.
2364 static ArrayRef<MCPhysReg> get64BitArgumentGPRs(CallingConv::ID CallConv,
2365 const X86Subtarget *Subtarget) {
2366 assert(Subtarget->is64Bit());
2368 if (Subtarget->isCallingConvWin64(CallConv)) {
2369 static const MCPhysReg GPR64ArgRegsWin64[] = {
2370 X86::RCX, X86::RDX, X86::R8, X86::R9
2372 return makeArrayRef(std::begin(GPR64ArgRegsWin64), std::end(GPR64ArgRegsWin64));
2375 static const MCPhysReg GPR64ArgRegs64Bit[] = {
2376 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2378 return makeArrayRef(std::begin(GPR64ArgRegs64Bit), std::end(GPR64ArgRegs64Bit));
2381 // FIXME: Get this from tablegen.
2382 static ArrayRef<MCPhysReg> get64BitArgumentXMMs(MachineFunction &MF,
2383 CallingConv::ID CallConv,
2384 const X86Subtarget *Subtarget) {
2385 assert(Subtarget->is64Bit());
2386 if (Subtarget->isCallingConvWin64(CallConv)) {
2387 // The XMM registers which might contain var arg parameters are shadowed
2388 // in their paired GPR. So we only need to save the GPR to their home
2390 // TODO: __vectorcall will change this.
2394 const Function *Fn = MF.getFunction();
2395 bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);
2396 bool isSoftFloat = Subtarget->useSoftFloat();
2397 assert(!(isSoftFloat && NoImplicitFloatOps) &&
2398 "SSE register cannot be used when SSE is disabled!");
2399 if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())
2400 // Kernel mode asks for SSE to be disabled, so there are no XMM argument
2404 static const MCPhysReg XMMArgRegs64Bit[] = {
2405 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2406 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2408 return makeArrayRef(std::begin(XMMArgRegs64Bit), std::end(XMMArgRegs64Bit));
2412 X86TargetLowering::LowerFormalArguments(SDValue Chain,
2413 CallingConv::ID CallConv,
2415 const SmallVectorImpl<ISD::InputArg> &Ins,
2418 SmallVectorImpl<SDValue> &InVals)
2420 MachineFunction &MF = DAG.getMachineFunction();
2421 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2422 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
2424 const Function* Fn = MF.getFunction();
2425 if (Fn->hasExternalLinkage() &&
2426 Subtarget->isTargetCygMing() &&
2427 Fn->getName() == "main")
2428 FuncInfo->setForceFramePointer(true);
2430 MachineFrameInfo *MFI = MF.getFrameInfo();
2431 bool Is64Bit = Subtarget->is64Bit();
2432 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2434 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2435 "Var args not supported with calling convention fastcc, ghc or hipe");
2437 // Assign locations to all of the incoming arguments.
2438 SmallVector<CCValAssign, 16> ArgLocs;
2439 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2441 // Allocate shadow area for Win64
2443 CCInfo.AllocateStack(32, 8);
2445 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
2447 unsigned LastVal = ~0U;
2449 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2450 CCValAssign &VA = ArgLocs[i];
2451 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
2453 assert(VA.getValNo() != LastVal &&
2454 "Don't support value assigned to multiple locs yet");
2456 LastVal = VA.getValNo();
2458 if (VA.isRegLoc()) {
2459 EVT RegVT = VA.getLocVT();
2460 const TargetRegisterClass *RC;
2461 if (RegVT == MVT::i32)
2462 RC = &X86::GR32RegClass;
2463 else if (Is64Bit && RegVT == MVT::i64)
2464 RC = &X86::GR64RegClass;
2465 else if (RegVT == MVT::f32)
2466 RC = &X86::FR32RegClass;
2467 else if (RegVT == MVT::f64)
2468 RC = &X86::FR64RegClass;
2469 else if (RegVT.is512BitVector())
2470 RC = &X86::VR512RegClass;
2471 else if (RegVT.is256BitVector())
2472 RC = &X86::VR256RegClass;
2473 else if (RegVT.is128BitVector())
2474 RC = &X86::VR128RegClass;
2475 else if (RegVT == MVT::x86mmx)
2476 RC = &X86::VR64RegClass;
2477 else if (RegVT == MVT::i1)
2478 RC = &X86::VK1RegClass;
2479 else if (RegVT == MVT::v8i1)
2480 RC = &X86::VK8RegClass;
2481 else if (RegVT == MVT::v16i1)
2482 RC = &X86::VK16RegClass;
2483 else if (RegVT == MVT::v32i1)
2484 RC = &X86::VK32RegClass;
2485 else if (RegVT == MVT::v64i1)
2486 RC = &X86::VK64RegClass;
2488 llvm_unreachable("Unknown argument type!");
2490 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2491 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2493 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2494 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2496 if (VA.getLocInfo() == CCValAssign::SExt)
2497 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2498 DAG.getValueType(VA.getValVT()));
2499 else if (VA.getLocInfo() == CCValAssign::ZExt)
2500 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2501 DAG.getValueType(VA.getValVT()));
2502 else if (VA.getLocInfo() == CCValAssign::BCvt)
2503 ArgValue = DAG.getBitcast(VA.getValVT(), ArgValue);
2505 if (VA.isExtInLoc()) {
2506 // Handle MMX values passed in XMM regs.
2507 if (RegVT.isVector() && VA.getValVT().getScalarType() != MVT::i1)
2508 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2510 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2513 assert(VA.isMemLoc());
2514 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2517 // If value is passed via pointer - do a load.
2518 if (VA.getLocInfo() == CCValAssign::Indirect)
2519 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2520 MachinePointerInfo(), false, false, false, 0);
2522 InVals.push_back(ArgValue);
2525 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2526 // All x86 ABIs require that for returning structs by value we copy the
2527 // sret argument into %rax/%eax (depending on ABI) for the return. Save
2528 // the argument into a virtual register so that we can access it from the
2530 if (Ins[i].Flags.isSRet()) {
2531 unsigned Reg = FuncInfo->getSRetReturnReg();
2533 MVT PtrTy = getPointerTy();
2534 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2535 FuncInfo->setSRetReturnReg(Reg);
2537 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[i]);
2538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2543 unsigned StackSize = CCInfo.getNextStackOffset();
2544 // Align stack specially for tail calls.
2545 if (FuncIsMadeTailCallSafe(CallConv,
2546 MF.getTarget().Options.GuaranteedTailCallOpt))
2547 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2549 // If the function takes variable number of arguments, make a frame index for
2550 // the start of the first vararg value... for expansion of llvm.va_start. We
2551 // can skip this if there are no va_start calls.
2552 if (MFI->hasVAStart() &&
2553 (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2554 CallConv != CallingConv::X86_ThisCall))) {
2555 FuncInfo->setVarArgsFrameIndex(
2556 MFI->CreateFixedObject(1, StackSize, true));
2559 MachineModuleInfo &MMI = MF.getMMI();
2560 const Function *WinEHParent = nullptr;
2561 if (IsWin64 && MMI.hasWinEHFuncInfo(Fn))
2562 WinEHParent = MMI.getWinEHParent(Fn);
2563 bool IsWinEHOutlined = WinEHParent && WinEHParent != Fn;
2564 bool IsWinEHParent = WinEHParent && WinEHParent == Fn;
2566 // Figure out if XMM registers are in use.
2567 assert(!(Subtarget->useSoftFloat() &&
2568 Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&
2569 "SSE register cannot be used when SSE is disabled!");
2571 // 64-bit calling conventions support varargs and register parameters, so we
2572 // have to do extra work to spill them in the prologue.
2573 if (Is64Bit && isVarArg && MFI->hasVAStart()) {
2574 // Find the first unallocated argument registers.
2575 ArrayRef<MCPhysReg> ArgGPRs = get64BitArgumentGPRs(CallConv, Subtarget);
2576 ArrayRef<MCPhysReg> ArgXMMs = get64BitArgumentXMMs(MF, CallConv, Subtarget);
2577 unsigned NumIntRegs = CCInfo.getFirstUnallocated(ArgGPRs);
2578 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(ArgXMMs);
2579 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2580 "SSE register cannot be used when SSE is disabled!");
2582 // Gather all the live in physical registers.
2583 SmallVector<SDValue, 6> LiveGPRs;
2584 SmallVector<SDValue, 8> LiveXMMRegs;
2586 for (MCPhysReg Reg : ArgGPRs.slice(NumIntRegs)) {
2587 unsigned GPR = MF.addLiveIn(Reg, &X86::GR64RegClass);
2589 DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64));
2591 if (!ArgXMMs.empty()) {
2592 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2593 ALVal = DAG.getCopyFromReg(Chain, dl, AL, MVT::i8);
2594 for (MCPhysReg Reg : ArgXMMs.slice(NumXMMRegs)) {
2595 unsigned XMMReg = MF.addLiveIn(Reg, &X86::VR128RegClass);
2596 LiveXMMRegs.push_back(
2597 DAG.getCopyFromReg(Chain, dl, XMMReg, MVT::v4f32));
2602 // Get to the caller-allocated home save location. Add 8 to account
2603 // for the return address.
2604 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2605 FuncInfo->setRegSaveFrameIndex(
2606 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2607 // Fixup to set vararg frame on shadow area (4 x i64).
2609 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2611 // For X86-64, if there are vararg parameters that are passed via
2612 // registers, then we must store them to their spots on the stack so
2613 // they may be loaded by deferencing the result of va_next.
2614 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2615 FuncInfo->setVarArgsFPOffset(ArgGPRs.size() * 8 + NumXMMRegs * 16);
2616 FuncInfo->setRegSaveFrameIndex(MFI->CreateStackObject(
2617 ArgGPRs.size() * 8 + ArgXMMs.size() * 16, 16, false));
2620 // Store the integer parameter registers.
2621 SmallVector<SDValue, 8> MemOps;
2622 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2624 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2625 for (SDValue Val : LiveGPRs) {
2626 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2627 DAG.getIntPtrConstant(Offset, dl));
2629 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2630 MachinePointerInfo::getFixedStack(
2631 FuncInfo->getRegSaveFrameIndex(), Offset),
2633 MemOps.push_back(Store);
2637 if (!ArgXMMs.empty() && NumXMMRegs != ArgXMMs.size()) {
2638 // Now store the XMM (fp + vector) parameter registers.
2639 SmallVector<SDValue, 12> SaveXMMOps;
2640 SaveXMMOps.push_back(Chain);
2641 SaveXMMOps.push_back(ALVal);
2642 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2643 FuncInfo->getRegSaveFrameIndex(), dl));
2644 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2645 FuncInfo->getVarArgsFPOffset(), dl));
2646 SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),
2648 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2649 MVT::Other, SaveXMMOps));
2652 if (!MemOps.empty())
2653 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2654 } else if (IsWinEHOutlined) {
2655 // Get to the caller-allocated home save location. Add 8 to account
2656 // for the return address.
2657 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2658 FuncInfo->setRegSaveFrameIndex(MFI->CreateFixedObject(
2659 /*Size=*/1, /*SPOffset=*/HomeOffset + 8, /*Immutable=*/false));
2661 MMI.getWinEHFuncInfo(Fn)
2662 .CatchHandlerParentFrameObjIdx[const_cast<Function *>(Fn)] =
2663 FuncInfo->getRegSaveFrameIndex();
2665 // Store the second integer parameter (rdx) into rsp+16 relative to the
2666 // stack pointer at the entry of the function.
2668 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), getPointerTy());
2669 unsigned GPR = MF.addLiveIn(X86::RDX, &X86::GR64RegClass);
2670 SDValue Val = DAG.getCopyFromReg(Chain, dl, GPR, MVT::i64);
2671 Chain = DAG.getStore(
2672 Val.getValue(1), dl, Val, RSFIN,
2673 MachinePointerInfo::getFixedStack(FuncInfo->getRegSaveFrameIndex()),
2674 /*isVolatile=*/true, /*isNonTemporal=*/false, /*Alignment=*/0);
2677 if (isVarArg && MFI->hasMustTailInVarArgFunc()) {
2678 // Find the largest legal vector type.
2679 MVT VecVT = MVT::Other;
2680 // FIXME: Only some x86_32 calling conventions support AVX512.
2681 if (Subtarget->hasAVX512() &&
2682 (Is64Bit || (CallConv == CallingConv::X86_VectorCall ||
2683 CallConv == CallingConv::Intel_OCL_BI)))
2684 VecVT = MVT::v16f32;
2685 else if (Subtarget->hasAVX())
2687 else if (Subtarget->hasSSE2())
2690 // We forward some GPRs and some vector types.
2691 SmallVector<MVT, 2> RegParmTypes;
2692 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32;
2693 RegParmTypes.push_back(IntVT);
2694 if (VecVT != MVT::Other)
2695 RegParmTypes.push_back(VecVT);
2697 // Compute the set of forwarded registers. The rest are scratch.
2698 SmallVectorImpl<ForwardedRegister> &Forwards =
2699 FuncInfo->getForwardedMustTailRegParms();
2700 CCInfo.analyzeMustTailForwardedRegisters(Forwards, RegParmTypes, CC_X86);
2702 // Conservatively forward AL on x86_64, since it might be used for varargs.
2703 if (Is64Bit && !CCInfo.isAllocated(X86::AL)) {
2704 unsigned ALVReg = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2705 Forwards.push_back(ForwardedRegister(ALVReg, X86::AL, MVT::i8));
2708 // Copy all forwards from physical to virtual registers.
2709 for (ForwardedRegister &F : Forwards) {
2710 // FIXME: Can we use a less constrained schedule?
2711 SDValue RegVal = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
2712 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT));
2713 Chain = DAG.getCopyToReg(Chain, dl, F.VReg, RegVal);
2717 // Some CCs need callee pop.
2718 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2719 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2720 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2722 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2723 // If this is an sret function, the return should pop the hidden pointer.
2724 if (!Is64Bit && !IsTailCallConvention(CallConv) &&
2725 !Subtarget->getTargetTriple().isOSMSVCRT() &&
2726 argsAreStructReturn(Ins) == StackStructReturn)
2727 FuncInfo->setBytesToPopOnReturn(4);
2731 // RegSaveFrameIndex is X86-64 only.
2732 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2733 if (CallConv == CallingConv::X86_FastCall ||
2734 CallConv == CallingConv::X86_ThisCall)
2735 // fastcc functions can't have varargs.
2736 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2739 FuncInfo->setArgumentStackSize(StackSize);
2741 if (IsWinEHParent) {
2742 int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);
2743 SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);
2744 MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;
2745 SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);
2746 Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,
2747 MachinePointerInfo::getFixedStack(UnwindHelpFI),
2748 /*isVolatile=*/true,
2749 /*isNonTemporal=*/false, /*Alignment=*/0);
2756 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2757 SDValue StackPtr, SDValue Arg,
2758 SDLoc dl, SelectionDAG &DAG,
2759 const CCValAssign &VA,
2760 ISD::ArgFlagsTy Flags) const {
2761 unsigned LocMemOffset = VA.getLocMemOffset();
2762 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
2763 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2764 if (Flags.isByVal())
2765 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2767 return DAG.getStore(Chain, dl, Arg, PtrOff,
2768 MachinePointerInfo::getStack(LocMemOffset),
2772 /// Emit a load of return address if tail call
2773 /// optimization is performed and it is required.
2775 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2776 SDValue &OutRetAddr, SDValue Chain,
2777 bool IsTailCall, bool Is64Bit,
2778 int FPDiff, SDLoc dl) const {
2779 // Adjust the Return address stack slot.
2780 EVT VT = getPointerTy();
2781 OutRetAddr = getReturnAddressFrameIndex(DAG);
2783 // Load the "old" Return address.
2784 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2785 false, false, false, 0);
2786 return SDValue(OutRetAddr.getNode(), 1);
2789 /// Emit a store of the return address if tail call
2790 /// optimization is performed and it is required (FPDiff!=0).
2791 static SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunction &MF,
2792 SDValue Chain, SDValue RetAddrFrIdx,
2793 EVT PtrVT, unsigned SlotSize,
2794 int FPDiff, SDLoc dl) {
2795 // Store the return address to the appropriate stack slot.
2796 if (!FPDiff) return Chain;
2797 // Calculate the new stack slot for the return address.
2798 int NewReturnAddrFI =
2799 MF.getFrameInfo()->CreateFixedObject(SlotSize, (int64_t)FPDiff - SlotSize,
2801 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2802 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2803 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2809 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2810 SmallVectorImpl<SDValue> &InVals) const {
2811 SelectionDAG &DAG = CLI.DAG;
2813 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2814 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2815 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2816 SDValue Chain = CLI.Chain;
2817 SDValue Callee = CLI.Callee;
2818 CallingConv::ID CallConv = CLI.CallConv;
2819 bool &isTailCall = CLI.IsTailCall;
2820 bool isVarArg = CLI.IsVarArg;
2822 MachineFunction &MF = DAG.getMachineFunction();
2823 bool Is64Bit = Subtarget->is64Bit();
2824 bool IsWin64 = Subtarget->isCallingConvWin64(CallConv);
2825 StructReturnType SR = callIsStructReturn(Outs);
2826 bool IsSibcall = false;
2827 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2828 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
2830 if (Attr.getValueAsString() == "true")
2833 if (Subtarget->isPICStyleGOT() &&
2834 !MF.getTarget().Options.GuaranteedTailCallOpt) {
2835 // If we are using a GOT, disable tail calls to external symbols with
2836 // default visibility. Tail calling such a symbol requires using a GOT
2837 // relocation, which forces early binding of the symbol. This breaks code
2838 // that require lazy function symbol resolution. Using musttail or
2839 // GuaranteedTailCallOpt will override this.
2840 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2841 if (!G || (!G->getGlobal()->hasLocalLinkage() &&
2842 G->getGlobal()->hasDefaultVisibility()))
2846 bool IsMustTail = CLI.CS && CLI.CS->isMustTailCall();
2848 // Force this to be a tail call. The verifier rules are enough to ensure
2849 // that we can lower this successfully without moving the return address
2852 } else if (isTailCall) {
2853 // Check if it's really possible to do a tail call.
2854 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2855 isVarArg, SR != NotStructReturn,
2856 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2857 Outs, OutVals, Ins, DAG);
2859 // Sibcalls are automatically detected tailcalls which do not require
2861 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2868 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2869 "Var args not supported with calling convention fastcc, ghc or hipe");
2871 // Analyze operands of the call, assigning locations to each operand.
2872 SmallVector<CCValAssign, 16> ArgLocs;
2873 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
2875 // Allocate shadow area for Win64
2877 CCInfo.AllocateStack(32, 8);
2879 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2881 // Get a count of how many bytes are to be pushed on the stack.
2882 unsigned NumBytes = CCInfo.getNextStackOffset();
2884 // This is a sibcall. The memory operands are available in caller's
2885 // own caller's stack.
2887 else if (MF.getTarget().Options.GuaranteedTailCallOpt &&
2888 IsTailCallConvention(CallConv))
2889 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2892 if (isTailCall && !IsSibcall && !IsMustTail) {
2893 // Lower arguments at fp - stackoffset + fpdiff.
2894 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2896 FPDiff = NumBytesCallerPushed - NumBytes;
2898 // Set the delta of movement of the returnaddr stackslot.
2899 // But only set if delta is greater than previous delta.
2900 if (FPDiff < X86Info->getTCReturnAddrDelta())
2901 X86Info->setTCReturnAddrDelta(FPDiff);
2904 unsigned NumBytesToPush = NumBytes;
2905 unsigned NumBytesToPop = NumBytes;
2907 // If we have an inalloca argument, all stack space has already been allocated
2908 // for us and be right at the top of the stack. We don't support multiple
2909 // arguments passed in memory when using inalloca.
2910 if (!Outs.empty() && Outs.back().Flags.isInAlloca()) {
2912 if (!ArgLocs.back().isMemLoc())
2913 report_fatal_error("cannot use inalloca attribute on a register "
2915 if (ArgLocs.back().getLocMemOffset() != 0)
2916 report_fatal_error("any parameter with the inalloca attribute must be "
2917 "the only memory argument");
2921 Chain = DAG.getCALLSEQ_START(
2922 Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);
2924 SDValue RetAddrFrIdx;
2925 // Load return address for tail calls.
2926 if (isTailCall && FPDiff)
2927 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2928 Is64Bit, FPDiff, dl);
2930 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2931 SmallVector<SDValue, 8> MemOpChains;
2934 // Walk the register/memloc assignments, inserting copies/loads. In the case
2935 // of tail call optimization arguments are handle later.
2936 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
2937 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2938 // Skip inalloca arguments, they have already been written.
2939 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2940 if (Flags.isInAlloca())
2943 CCValAssign &VA = ArgLocs[i];
2944 EVT RegVT = VA.getLocVT();
2945 SDValue Arg = OutVals[i];
2946 bool isByVal = Flags.isByVal();
2948 // Promote the value if needed.
2949 switch (VA.getLocInfo()) {
2950 default: llvm_unreachable("Unknown loc info!");
2951 case CCValAssign::Full: break;
2952 case CCValAssign::SExt:
2953 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2955 case CCValAssign::ZExt:
2956 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2958 case CCValAssign::AExt:
2959 if (Arg.getValueType().isVector() &&
2960 Arg.getValueType().getScalarType() == MVT::i1)
2961 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2962 else if (RegVT.is128BitVector()) {
2963 // Special case: passing MMX values in XMM registers.
2964 Arg = DAG.getBitcast(MVT::i64, Arg);
2965 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2966 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2968 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2970 case CCValAssign::BCvt:
2971 Arg = DAG.getBitcast(RegVT, Arg);
2973 case CCValAssign::Indirect: {
2974 // Store the argument.
2975 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2976 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2977 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2978 MachinePointerInfo::getFixedStack(FI),
2985 if (VA.isRegLoc()) {
2986 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2987 if (isVarArg && IsWin64) {
2988 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2989 // shadow reg if callee is a varargs function.
2990 unsigned ShadowReg = 0;
2991 switch (VA.getLocReg()) {
2992 case X86::XMM0: ShadowReg = X86::RCX; break;
2993 case X86::XMM1: ShadowReg = X86::RDX; break;
2994 case X86::XMM2: ShadowReg = X86::R8; break;
2995 case X86::XMM3: ShadowReg = X86::R9; break;
2998 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
3000 } else if (!IsSibcall && (!isTailCall || isByVal)) {
3001 assert(VA.isMemLoc());
3002 if (!StackPtr.getNode())
3003 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
3005 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
3006 dl, DAG, VA, Flags));
3010 if (!MemOpChains.empty())
3011 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3013 if (Subtarget->isPICStyleGOT()) {
3014 // ELF / PIC requires GOT in the EBX register before function calls via PLT
3017 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
3018 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), getPointerTy())));
3020 // If we are tail calling and generating PIC/GOT style code load the
3021 // address of the callee into ECX. The value in ecx is used as target of
3022 // the tail jump. This is done to circumvent the ebx/callee-saved problem
3023 // for tail calls on PIC/GOT architectures. Normally we would just put the
3024 // address of GOT into ebx and then call target@PLT. But for tail calls
3025 // ebx would be restored (since ebx is callee saved) before jumping to the
3028 // Note: The actual moving to ECX is done further down.
3029 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
3030 if (G && !G->getGlobal()->hasLocalLinkage() &&
3031 G->getGlobal()->hasDefaultVisibility())
3032 Callee = LowerGlobalAddress(Callee, DAG);
3033 else if (isa<ExternalSymbolSDNode>(Callee))
3034 Callee = LowerExternalSymbol(Callee, DAG);
3038 if (Is64Bit && isVarArg && !IsWin64 && !IsMustTail) {
3039 // From AMD64 ABI document:
3040 // For calls that may call functions that use varargs or stdargs
3041 // (prototype-less calls or calls to functions containing ellipsis (...) in
3042 // the declaration) %al is used as hidden argument to specify the number
3043 // of SSE registers used. The contents of %al do not need to match exactly
3044 // the number of registers, but must be an ubound on the number of SSE
3045 // registers used and is in the range 0 - 8 inclusive.
3047 // Count the number of XMM registers allocated.
3048 static const MCPhysReg XMMArgRegs[] = {
3049 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
3050 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
3052 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs);
3053 assert((Subtarget->hasSSE1() || !NumXMMRegs)
3054 && "SSE registers cannot be used when SSE is disabled");
3056 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
3057 DAG.getConstant(NumXMMRegs, dl,
3061 if (isVarArg && IsMustTail) {
3062 const auto &Forwards = X86Info->getForwardedMustTailRegParms();
3063 for (const auto &F : Forwards) {
3064 SDValue Val = DAG.getCopyFromReg(Chain, dl, F.VReg, F.VT);
3065 RegsToPass.push_back(std::make_pair(unsigned(F.PReg), Val));
3069 // For tail calls lower the arguments to the 'real' stack slots. Sibcalls
3070 // don't need this because the eligibility check rejects calls that require
3071 // shuffling arguments passed in memory.
3072 if (!IsSibcall && isTailCall) {
3073 // Force all the incoming stack arguments to be loaded from the stack
3074 // before any new outgoing arguments are stored to the stack, because the
3075 // outgoing stack slots may alias the incoming argument stack slots, and
3076 // the alias isn't otherwise explicit. This is slightly more conservative
3077 // than necessary, because it means that each store effectively depends
3078 // on every argument instead of just those arguments it would clobber.
3079 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
3081 SmallVector<SDValue, 8> MemOpChains2;
3084 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3085 CCValAssign &VA = ArgLocs[i];
3088 assert(VA.isMemLoc());
3089 SDValue Arg = OutVals[i];
3090 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3091 // Skip inalloca arguments. They don't require any work.
3092 if (Flags.isInAlloca())
3094 // Create frame index.
3095 int32_t Offset = VA.getLocMemOffset()+FPDiff;
3096 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
3097 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3098 FIN = DAG.getFrameIndex(FI, getPointerTy());
3100 if (Flags.isByVal()) {
3101 // Copy relative to framepointer.
3102 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);
3103 if (!StackPtr.getNode())
3104 StackPtr = DAG.getCopyFromReg(Chain, dl,
3105 RegInfo->getStackRegister(),
3107 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
3109 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
3113 // Store relative to framepointer.
3114 MemOpChains2.push_back(
3115 DAG.getStore(ArgChain, dl, Arg, FIN,
3116 MachinePointerInfo::getFixedStack(FI),
3121 if (!MemOpChains2.empty())
3122 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3124 // Store the return address to the appropriate stack slot.
3125 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
3126 getPointerTy(), RegInfo->getSlotSize(),
3130 // Build a sequence of copy-to-reg nodes chained together with token chain
3131 // and flag operands which copy the outgoing args into registers.
3133 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3134 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3135 RegsToPass[i].second, InFlag);
3136 InFlag = Chain.getValue(1);
3139 if (DAG.getTarget().getCodeModel() == CodeModel::Large) {
3140 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
3141 // In the 64-bit large code model, we have to make all calls
3142 // through a register, since the call instruction's 32-bit
3143 // pc-relative offset may not be large enough to hold the whole
3145 } else if (Callee->getOpcode() == ISD::GlobalAddress) {
3146 // If the callee is a GlobalAddress node (quite common, every direct call
3147 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
3149 GlobalAddressSDNode* G = cast<GlobalAddressSDNode>(Callee);
3151 // We should use extra load for direct calls to dllimported functions in
3153 const GlobalValue *GV = G->getGlobal();
3154 if (!GV->hasDLLImportStorageClass()) {
3155 unsigned char OpFlags = 0;
3156 bool ExtraLoad = false;
3157 unsigned WrapperKind = ISD::DELETED_NODE;
3159 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
3160 // external symbols most go through the PLT in PIC mode. If the symbol
3161 // has hidden or protected visibility, or if it is static or local, then
3162 // we don't need to use the PLT - we can directly call it.
3163 if (Subtarget->isTargetELF() &&
3164 DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
3165 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
3166 OpFlags = X86II::MO_PLT;
3167 } else if (Subtarget->isPICStyleStubAny() &&
3168 !GV->isStrongDefinitionForLinker() &&
3169 (!Subtarget->getTargetTriple().isMacOSX() ||
3170 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3171 // PC-relative references to external symbols should go through $stub,
3172 // unless we're building with the leopard linker or later, which
3173 // automatically synthesizes these stubs.
3174 OpFlags = X86II::MO_DARWIN_STUB;
3175 } else if (Subtarget->isPICStyleRIPRel() && isa<Function>(GV) &&
3176 cast<Function>(GV)->hasFnAttribute(Attribute::NonLazyBind)) {
3177 // If the function is marked as non-lazy, generate an indirect call
3178 // which loads from the GOT directly. This avoids runtime overhead
3179 // at the cost of eager binding (and one extra byte of encoding).
3180 OpFlags = X86II::MO_GOTPCREL;
3181 WrapperKind = X86ISD::WrapperRIP;
3185 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
3186 G->getOffset(), OpFlags);
3188 // Add a wrapper if needed.
3189 if (WrapperKind != ISD::DELETED_NODE)
3190 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
3191 // Add extra indirection if needed.
3193 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
3194 MachinePointerInfo::getGOT(),
3195 false, false, false, 0);
3197 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3198 unsigned char OpFlags = 0;
3200 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
3201 // external symbols should go through the PLT.
3202 if (Subtarget->isTargetELF() &&
3203 DAG.getTarget().getRelocationModel() == Reloc::PIC_) {
3204 OpFlags = X86II::MO_PLT;
3205 } else if (Subtarget->isPICStyleStubAny() &&
3206 (!Subtarget->getTargetTriple().isMacOSX() ||
3207 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
3208 // PC-relative references to external symbols should go through $stub,
3209 // unless we're building with the leopard linker or later, which
3210 // automatically synthesizes these stubs.
3211 OpFlags = X86II::MO_DARWIN_STUB;
3214 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
3216 } else if (Subtarget->isTarget64BitILP32() &&
3217 Callee->getValueType(0) == MVT::i32) {
3218 // Zero-extend the 32-bit Callee address into a 64-bit according to x32 ABI
3219 Callee = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Callee);
3222 // Returns a chain & a flag for retval copy to use.
3223 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3224 SmallVector<SDValue, 8> Ops;
3226 if (!IsSibcall && isTailCall) {
3227 Chain = DAG.getCALLSEQ_END(Chain,
3228 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3229 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
3230 InFlag = Chain.getValue(1);
3233 Ops.push_back(Chain);
3234 Ops.push_back(Callee);
3237 Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));
3239 // Add argument registers to the end of the list so that they are known live
3241 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3242 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3243 RegsToPass[i].second.getValueType()));
3245 // Add a register mask operand representing the call-preserved registers.
3246 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
3247 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
3248 assert(Mask && "Missing call preserved mask for calling convention");
3249 Ops.push_back(DAG.getRegisterMask(Mask));
3251 if (InFlag.getNode())
3252 Ops.push_back(InFlag);
3256 //// If this is the first return lowered for this function, add the regs
3257 //// to the liveout set for the function.
3258 // This isn't right, although it's probably harmless on x86; liveouts
3259 // should be computed from returns not tail calls. Consider a void
3260 // function making a tail call to a function returning int.
3261 MF.getFrameInfo()->setHasTailCall();
3262 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
3265 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, Ops);
3266 InFlag = Chain.getValue(1);
3268 // Create the CALLSEQ_END node.
3269 unsigned NumBytesForCalleeToPop;
3270 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
3271 DAG.getTarget().Options.GuaranteedTailCallOpt))
3272 NumBytesForCalleeToPop = NumBytes; // Callee pops everything
3273 else if (!Is64Bit && !IsTailCallConvention(CallConv) &&
3274 !Subtarget->getTargetTriple().isOSMSVCRT() &&
3275 SR == StackStructReturn)
3276 // If this is a call to a struct-return function, the callee
3277 // pops the hidden struct pointer, so we have to push it back.
3278 // This is common for Darwin/X86, Linux & Mingw32 targets.
3279 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
3280 NumBytesForCalleeToPop = 4;
3282 NumBytesForCalleeToPop = 0; // Callee pops nothing.
3284 // Returns a flag for retval copy to use.
3286 Chain = DAG.getCALLSEQ_END(Chain,
3287 DAG.getIntPtrConstant(NumBytesToPop, dl, true),
3288 DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,
3291 InFlag = Chain.getValue(1);
3294 // Handle result values, copying them out of physregs into vregs that we
3296 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3297 Ins, dl, DAG, InVals);
3300 //===----------------------------------------------------------------------===//
3301 // Fast Calling Convention (tail call) implementation
3302 //===----------------------------------------------------------------------===//
3304 // Like std call, callee cleans arguments, convention except that ECX is
3305 // reserved for storing the tail called function address. Only 2 registers are
3306 // free for argument passing (inreg). Tail call optimization is performed
3308 // * tailcallopt is enabled
3309 // * caller/callee are fastcc
3310 // On X86_64 architecture with GOT-style position independent code only local
3311 // (within module) calls are supported at the moment.
3312 // To keep the stack aligned according to platform abi the function
3313 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
3314 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
3315 // If a tail called function callee has more arguments than the caller the
3316 // caller needs to make sure that there is room to move the RETADDR to. This is
3317 // achieved by reserving an area the size of the argument delta right after the
3318 // original RETADDR, but before the saved framepointer or the spilled registers
3319 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
3331 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
3332 /// for a 16 byte align requirement.
3334 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
3335 SelectionDAG& DAG) const {
3336 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3337 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
3338 unsigned StackAlignment = TFI.getStackAlignment();
3339 uint64_t AlignMask = StackAlignment - 1;
3340 int64_t Offset = StackSize;
3341 unsigned SlotSize = RegInfo->getSlotSize();
3342 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
3343 // Number smaller than 12 so just add the difference.
3344 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
3346 // Mask out lower bits, add stackalignment once plus the 12 bytes.
3347 Offset = ((~AlignMask) & Offset) + StackAlignment +
3348 (StackAlignment-SlotSize);
3353 /// MatchingStackOffset - Return true if the given stack call argument is
3354 /// already available in the same position (relatively) of the caller's
3355 /// incoming argument stack.
3357 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
3358 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
3359 const X86InstrInfo *TII) {
3360 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
3362 if (Arg.getOpcode() == ISD::CopyFromReg) {
3363 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
3364 if (!TargetRegisterInfo::isVirtualRegister(VR))
3366 MachineInstr *Def = MRI->getVRegDef(VR);
3369 if (!Flags.isByVal()) {
3370 if (!TII->isLoadFromStackSlot(Def, FI))
3373 unsigned Opcode = Def->getOpcode();
3374 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
3375 Opcode == X86::LEA64_32r) &&
3376 Def->getOperand(1).isFI()) {
3377 FI = Def->getOperand(1).getIndex();
3378 Bytes = Flags.getByValSize();
3382 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
3383 if (Flags.isByVal())
3384 // ByVal argument is passed in as a pointer but it's now being
3385 // dereferenced. e.g.
3386 // define @foo(%struct.X* %A) {
3387 // tail call @bar(%struct.X* byval %A)
3390 SDValue Ptr = Ld->getBasePtr();
3391 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
3394 FI = FINode->getIndex();
3395 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
3396 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
3397 FI = FINode->getIndex();
3398 Bytes = Flags.getByValSize();
3402 assert(FI != INT_MAX);
3403 if (!MFI->isFixedObjectIndex(FI))
3405 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
3408 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3409 /// for tail call optimization. Targets which want to do tail call
3410 /// optimization should implement this function.
3412 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3413 CallingConv::ID CalleeCC,
3415 bool isCalleeStructRet,
3416 bool isCallerStructRet,
3418 const SmallVectorImpl<ISD::OutputArg> &Outs,
3419 const SmallVectorImpl<SDValue> &OutVals,
3420 const SmallVectorImpl<ISD::InputArg> &Ins,
3421 SelectionDAG &DAG) const {
3422 if (!IsTailCallConvention(CalleeCC) && !IsCCallConvention(CalleeCC))
3425 // If -tailcallopt is specified, make fastcc functions tail-callable.
3426 const MachineFunction &MF = DAG.getMachineFunction();
3427 const Function *CallerF = MF.getFunction();
3429 // If the function return type is x86_fp80 and the callee return type is not,
3430 // then the FP_EXTEND of the call result is not a nop. It's not safe to
3431 // perform a tailcall optimization here.
3432 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
3435 CallingConv::ID CallerCC = CallerF->getCallingConv();
3436 bool CCMatch = CallerCC == CalleeCC;
3437 bool IsCalleeWin64 = Subtarget->isCallingConvWin64(CalleeCC);
3438 bool IsCallerWin64 = Subtarget->isCallingConvWin64(CallerCC);
3440 // Win64 functions have extra shadow space for argument homing. Don't do the
3441 // sibcall if the caller and callee have mismatched expectations for this
3443 if (IsCalleeWin64 != IsCallerWin64)
3446 if (DAG.getTarget().Options.GuaranteedTailCallOpt) {
3447 if (IsTailCallConvention(CalleeCC) && CCMatch)
3452 // Look for obvious safe cases to perform tail call optimization that do not
3453 // require ABI changes. This is what gcc calls sibcall.
3455 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
3456 // emit a special epilogue.
3457 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3458 if (RegInfo->needsStackRealignment(MF))
3461 // Also avoid sibcall optimization if either caller or callee uses struct
3462 // return semantics.
3463 if (isCalleeStructRet || isCallerStructRet)
3466 // An stdcall/thiscall caller is expected to clean up its arguments; the
3467 // callee isn't going to do that.
3468 // FIXME: this is more restrictive than needed. We could produce a tailcall
3469 // when the stack adjustment matches. For example, with a thiscall that takes
3470 // only one argument.
3471 if (!CCMatch && (CallerCC == CallingConv::X86_StdCall ||
3472 CallerCC == CallingConv::X86_ThisCall))
3475 // Do not sibcall optimize vararg calls unless all arguments are passed via
3477 if (isVarArg && !Outs.empty()) {
3479 // Optimizing for varargs on Win64 is unlikely to be safe without
3480 // additional testing.
3481 if (IsCalleeWin64 || IsCallerWin64)
3484 SmallVector<CCValAssign, 16> ArgLocs;
3485 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3488 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3489 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
3490 if (!ArgLocs[i].isRegLoc())
3494 // If the call result is in ST0 / ST1, it needs to be popped off the x87
3495 // stack. Therefore, if it's not used by the call it is not safe to optimize
3496 // this into a sibcall.
3497 bool Unused = false;
3498 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3505 SmallVector<CCValAssign, 16> RVLocs;
3506 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), RVLocs,
3508 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
3509 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3510 CCValAssign &VA = RVLocs[i];
3511 if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1)
3516 // If the calling conventions do not match, then we'd better make sure the
3517 // results are returned in the same way as what the caller expects.
3519 SmallVector<CCValAssign, 16> RVLocs1;
3520 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
3522 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
3524 SmallVector<CCValAssign, 16> RVLocs2;
3525 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
3527 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
3529 if (RVLocs1.size() != RVLocs2.size())
3531 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
3532 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
3534 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
3536 if (RVLocs1[i].isRegLoc()) {
3537 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
3540 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
3546 // If the callee takes no arguments then go on to check the results of the
3548 if (!Outs.empty()) {
3549 // Check if stack adjustment is needed. For now, do not do this if any
3550 // argument is passed on the stack.
3551 SmallVector<CCValAssign, 16> ArgLocs;
3552 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
3555 // Allocate shadow area for Win64
3557 CCInfo.AllocateStack(32, 8);
3559 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
3560 if (CCInfo.getNextStackOffset()) {
3561 MachineFunction &MF = DAG.getMachineFunction();
3562 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
3565 // Check if the arguments are already laid out in the right way as
3566 // the caller's fixed stack objects.
3567 MachineFrameInfo *MFI = MF.getFrameInfo();
3568 const MachineRegisterInfo *MRI = &MF.getRegInfo();
3569 const X86InstrInfo *TII = Subtarget->getInstrInfo();
3570 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3571 CCValAssign &VA = ArgLocs[i];
3572 SDValue Arg = OutVals[i];
3573 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3574 if (VA.getLocInfo() == CCValAssign::Indirect)
3576 if (!VA.isRegLoc()) {
3577 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
3584 // If the tailcall address may be in a register, then make sure it's
3585 // possible to register allocate for it. In 32-bit, the call address can
3586 // only target EAX, EDX, or ECX since the tail call must be scheduled after
3587 // callee-saved registers are restored. These happen to be the same
3588 // registers used to pass 'inreg' arguments so watch out for those.
3589 if (!Subtarget->is64Bit() &&
3590 ((!isa<GlobalAddressSDNode>(Callee) &&
3591 !isa<ExternalSymbolSDNode>(Callee)) ||
3592 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3593 unsigned NumInRegs = 0;
3594 // In PIC we need an extra register to formulate the address computation
3596 unsigned MaxInRegs =
3597 (DAG.getTarget().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3599 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3600 CCValAssign &VA = ArgLocs[i];
3603 unsigned Reg = VA.getLocReg();
3606 case X86::EAX: case X86::EDX: case X86::ECX:
3607 if (++NumInRegs == MaxInRegs)
3619 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3620 const TargetLibraryInfo *libInfo) const {
3621 return X86::createFastISel(funcInfo, libInfo);
3624 //===----------------------------------------------------------------------===//
3625 // Other Lowering Hooks
3626 //===----------------------------------------------------------------------===//
3628 static bool MayFoldLoad(SDValue Op) {
3629 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3632 static bool MayFoldIntoStore(SDValue Op) {
3633 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3636 static bool isTargetShuffle(unsigned Opcode) {
3638 default: return false;
3639 case X86ISD::BLENDI:
3640 case X86ISD::PSHUFB:
3641 case X86ISD::PSHUFD:
3642 case X86ISD::PSHUFHW:
3643 case X86ISD::PSHUFLW:
3645 case X86ISD::PALIGNR:
3646 case X86ISD::MOVLHPS:
3647 case X86ISD::MOVLHPD:
3648 case X86ISD::MOVHLPS:
3649 case X86ISD::MOVLPS:
3650 case X86ISD::MOVLPD:
3651 case X86ISD::MOVSHDUP:
3652 case X86ISD::MOVSLDUP:
3653 case X86ISD::MOVDDUP:
3656 case X86ISD::UNPCKL:
3657 case X86ISD::UNPCKH:
3658 case X86ISD::VPERMILPI:
3659 case X86ISD::VPERM2X128:
3660 case X86ISD::VPERMI:
3665 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3666 SDValue V1, unsigned TargetMask,
3667 SelectionDAG &DAG) {
3669 default: llvm_unreachable("Unknown x86 shuffle node");
3670 case X86ISD::PSHUFD:
3671 case X86ISD::PSHUFHW:
3672 case X86ISD::PSHUFLW:
3673 case X86ISD::VPERMILPI:
3674 case X86ISD::VPERMI:
3675 return DAG.getNode(Opc, dl, VT, V1,
3676 DAG.getConstant(TargetMask, dl, MVT::i8));
3680 static SDValue getTargetShuffleNode(unsigned Opc, SDLoc dl, EVT VT,
3681 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3683 default: llvm_unreachable("Unknown x86 shuffle node");
3684 case X86ISD::MOVLHPS:
3685 case X86ISD::MOVLHPD:
3686 case X86ISD::MOVHLPS:
3687 case X86ISD::MOVLPS:
3688 case X86ISD::MOVLPD:
3691 case X86ISD::UNPCKL:
3692 case X86ISD::UNPCKH:
3693 return DAG.getNode(Opc, dl, VT, V1, V2);
3697 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3698 MachineFunction &MF = DAG.getMachineFunction();
3699 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
3700 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3701 int ReturnAddrIndex = FuncInfo->getRAIndex();
3703 if (ReturnAddrIndex == 0) {
3704 // Set up a frame object for the return address.
3705 unsigned SlotSize = RegInfo->getSlotSize();
3706 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3709 FuncInfo->setRAIndex(ReturnAddrIndex);
3712 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3715 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3716 bool hasSymbolicDisplacement) {
3717 // Offset should fit into 32 bit immediate field.
3718 if (!isInt<32>(Offset))
3721 // If we don't have a symbolic displacement - we don't have any extra
3723 if (!hasSymbolicDisplacement)
3726 // FIXME: Some tweaks might be needed for medium code model.
3727 if (M != CodeModel::Small && M != CodeModel::Kernel)
3730 // For small code model we assume that latest object is 16MB before end of 31
3731 // bits boundary. We may also accept pretty large negative constants knowing
3732 // that all objects are in the positive half of address space.
3733 if (M == CodeModel::Small && Offset < 16*1024*1024)
3736 // For kernel code model we know that all object resist in the negative half
3737 // of 32bits address space. We may not accept negative offsets, since they may
3738 // be just off and we may accept pretty large positive ones.
3739 if (M == CodeModel::Kernel && Offset >= 0)
3745 /// isCalleePop - Determines whether the callee is required to pop its
3746 /// own arguments. Callee pop is necessary to support tail calls.
3747 bool X86::isCalleePop(CallingConv::ID CallingConv,
3748 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3749 switch (CallingConv) {
3752 case CallingConv::X86_StdCall:
3753 case CallingConv::X86_FastCall:
3754 case CallingConv::X86_ThisCall:
3756 case CallingConv::Fast:
3757 case CallingConv::GHC:
3758 case CallingConv::HiPE:
3765 /// \brief Return true if the condition is an unsigned comparison operation.
3766 static bool isX86CCUnsigned(unsigned X86CC) {
3768 default: llvm_unreachable("Invalid integer condition!");
3769 case X86::COND_E: return true;
3770 case X86::COND_G: return false;
3771 case X86::COND_GE: return false;
3772 case X86::COND_L: return false;
3773 case X86::COND_LE: return false;
3774 case X86::COND_NE: return true;
3775 case X86::COND_B: return true;
3776 case X86::COND_A: return true;
3777 case X86::COND_BE: return true;
3778 case X86::COND_AE: return true;
3780 llvm_unreachable("covered switch fell through?!");
3783 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3784 /// specific condition code, returning the condition code and the LHS/RHS of the
3785 /// comparison to make.
3786 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,
3787 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3789 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3790 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3791 // X > -1 -> X == 0, jump !sign.
3792 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3793 return X86::COND_NS;
3795 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3796 // X < 0 -> X == 0, jump on sign.
3799 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3801 RHS = DAG.getConstant(0, DL, RHS.getValueType());
3802 return X86::COND_LE;
3806 switch (SetCCOpcode) {
3807 default: llvm_unreachable("Invalid integer condition!");
3808 case ISD::SETEQ: return X86::COND_E;
3809 case ISD::SETGT: return X86::COND_G;
3810 case ISD::SETGE: return X86::COND_GE;
3811 case ISD::SETLT: return X86::COND_L;
3812 case ISD::SETLE: return X86::COND_LE;
3813 case ISD::SETNE: return X86::COND_NE;
3814 case ISD::SETULT: return X86::COND_B;
3815 case ISD::SETUGT: return X86::COND_A;
3816 case ISD::SETULE: return X86::COND_BE;
3817 case ISD::SETUGE: return X86::COND_AE;
3821 // First determine if it is required or is profitable to flip the operands.
3823 // If LHS is a foldable load, but RHS is not, flip the condition.
3824 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3825 !ISD::isNON_EXTLoad(RHS.getNode())) {
3826 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3827 std::swap(LHS, RHS);
3830 switch (SetCCOpcode) {
3836 std::swap(LHS, RHS);
3840 // On a floating point condition, the flags are set as follows:
3842 // 0 | 0 | 0 | X > Y
3843 // 0 | 0 | 1 | X < Y
3844 // 1 | 0 | 0 | X == Y
3845 // 1 | 1 | 1 | unordered
3846 switch (SetCCOpcode) {
3847 default: llvm_unreachable("Condcode should be pre-legalized away");
3849 case ISD::SETEQ: return X86::COND_E;
3850 case ISD::SETOLT: // flipped
3852 case ISD::SETGT: return X86::COND_A;
3853 case ISD::SETOLE: // flipped
3855 case ISD::SETGE: return X86::COND_AE;
3856 case ISD::SETUGT: // flipped
3858 case ISD::SETLT: return X86::COND_B;
3859 case ISD::SETUGE: // flipped
3861 case ISD::SETLE: return X86::COND_BE;
3863 case ISD::SETNE: return X86::COND_NE;
3864 case ISD::SETUO: return X86::COND_P;
3865 case ISD::SETO: return X86::COND_NP;
3867 case ISD::SETUNE: return X86::COND_INVALID;
3871 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3872 /// code. Current x86 isa includes the following FP cmov instructions:
3873 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3874 static bool hasFPCMov(unsigned X86CC) {
3890 /// isFPImmLegal - Returns true if the target can instruction select the
3891 /// specified FP immediate natively. If false, the legalizer will
3892 /// materialize the FP immediate as a load from a constant pool.
3893 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3894 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3895 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3901 bool X86TargetLowering::shouldReduceLoadWidth(SDNode *Load,
3902 ISD::LoadExtType ExtTy,
3904 // "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF
3905 // relocation target a movq or addq instruction: don't let the load shrink.
3906 SDValue BasePtr = cast<LoadSDNode>(Load)->getBasePtr();
3907 if (BasePtr.getOpcode() == X86ISD::WrapperRIP)
3908 if (const auto *GA = dyn_cast<GlobalAddressSDNode>(BasePtr.getOperand(0)))
3909 return GA->getTargetFlags() != X86II::MO_GOTTPOFF;
3913 /// \brief Returns true if it is beneficial to convert a load of a constant
3914 /// to just the constant itself.
3915 bool X86TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
3917 assert(Ty->isIntegerTy());
3919 unsigned BitSize = Ty->getPrimitiveSizeInBits();
3920 if (BitSize == 0 || BitSize > 64)
3925 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,
3926 unsigned Index) const {
3927 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
3930 return (Index == 0 || Index == ResVT.getVectorNumElements());
3933 bool X86TargetLowering::isCheapToSpeculateCttz() const {
3934 // Speculate cttz only if we can directly use TZCNT.
3935 return Subtarget->hasBMI();
3938 bool X86TargetLowering::isCheapToSpeculateCtlz() const {
3939 // Speculate ctlz only if we can directly use LZCNT.
3940 return Subtarget->hasLZCNT();
3943 /// isUndefInRange - Return true if every element in Mask, beginning
3944 /// from position Pos and ending in Pos+Size is undef.
3945 static bool isUndefInRange(ArrayRef<int> Mask, unsigned Pos, unsigned Size) {
3946 for (unsigned i = Pos, e = Pos + Size; i != e; ++i)
3952 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3953 /// the specified range (L, H].
3954 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3955 return (Val < 0) || (Val >= Low && Val < Hi);
3958 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3959 /// specified value.
3960 static bool isUndefOrEqual(int Val, int CmpVal) {
3961 return (Val < 0 || Val == CmpVal);
3964 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3965 /// from position Pos and ending in Pos+Size, falls within the specified
3966 /// sequential range (Low, Low+Size]. or is undef.
3967 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3968 unsigned Pos, unsigned Size, int Low) {
3969 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3970 if (!isUndefOrEqual(Mask[i], Low))
3975 /// isVEXTRACTIndex - Return true if the specified
3976 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
3977 /// suitable for instruction that extract 128 or 256 bit vectors
3978 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
3979 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3980 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
3983 // The index should be aligned on a vecWidth-bit boundary.
3985 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
3987 MVT VT = N->getSimpleValueType(0);
3988 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
3989 bool Result = (Index * ElSize) % vecWidth == 0;
3994 /// isVINSERTIndex - Return true if the specified INSERT_SUBVECTOR
3995 /// operand specifies a subvector insert that is suitable for input to
3996 /// insertion of 128 or 256-bit subvectors
3997 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
3998 assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
3999 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4001 // The index should be aligned on a vecWidth-bit boundary.
4003 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4005 MVT VT = N->getSimpleValueType(0);
4006 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4007 bool Result = (Index * ElSize) % vecWidth == 0;
4012 bool X86::isVINSERT128Index(SDNode *N) {
4013 return isVINSERTIndex(N, 128);
4016 bool X86::isVINSERT256Index(SDNode *N) {
4017 return isVINSERTIndex(N, 256);
4020 bool X86::isVEXTRACT128Index(SDNode *N) {
4021 return isVEXTRACTIndex(N, 128);
4024 bool X86::isVEXTRACT256Index(SDNode *N) {
4025 return isVEXTRACTIndex(N, 256);
4028 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
4029 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4030 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4031 llvm_unreachable("Illegal extract subvector for VEXTRACT");
4034 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4036 MVT VecVT = N->getOperand(0).getSimpleValueType();
4037 MVT ElVT = VecVT.getVectorElementType();
4039 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4040 return Index / NumElemsPerChunk;
4043 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
4044 assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
4045 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4046 llvm_unreachable("Illegal insert subvector for VINSERT");
4049 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4051 MVT VecVT = N->getSimpleValueType(0);
4052 MVT ElVT = VecVT.getVectorElementType();
4054 unsigned NumElemsPerChunk = vecWidth / ElVT.getSizeInBits();
4055 return Index / NumElemsPerChunk;
4058 /// getExtractVEXTRACT128Immediate - Return the appropriate immediate
4059 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4060 /// and VINSERTI128 instructions.
4061 unsigned X86::getExtractVEXTRACT128Immediate(SDNode *N) {
4062 return getExtractVEXTRACTImmediate(N, 128);
4065 /// getExtractVEXTRACT256Immediate - Return the appropriate immediate
4066 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF64x4
4067 /// and VINSERTI64x4 instructions.
4068 unsigned X86::getExtractVEXTRACT256Immediate(SDNode *N) {
4069 return getExtractVEXTRACTImmediate(N, 256);
4072 /// getInsertVINSERT128Immediate - Return the appropriate immediate
4073 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4074 /// and VINSERTI128 instructions.
4075 unsigned X86::getInsertVINSERT128Immediate(SDNode *N) {
4076 return getInsertVINSERTImmediate(N, 128);
4079 /// getInsertVINSERT256Immediate - Return the appropriate immediate
4080 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF46x4
4081 /// and VINSERTI64x4 instructions.
4082 unsigned X86::getInsertVINSERT256Immediate(SDNode *N) {
4083 return getInsertVINSERTImmediate(N, 256);
4086 /// isZero - Returns true if Elt is a constant integer zero
4087 static bool isZero(SDValue V) {
4088 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
4089 return C && C->isNullValue();
4092 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4094 bool X86::isZeroNode(SDValue Elt) {
4097 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4098 return CFP->getValueAPF().isPosZero();
4102 /// getZeroVector - Returns a vector of specified type with all zero elements.
4104 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4105 SelectionDAG &DAG, SDLoc dl) {
4106 assert(VT.isVector() && "Expected a vector type");
4108 // Always build SSE zero vectors as <4 x i32> bitcasted
4109 // to their dest type. This ensures they get CSE'd.
4111 if (VT.is128BitVector()) { // SSE
4112 if (Subtarget->hasSSE2()) { // SSE2
4113 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4114 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4116 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4117 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4119 } else if (VT.is256BitVector()) { // AVX
4120 if (Subtarget->hasInt256()) { // AVX2
4121 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4122 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4123 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4125 // 256-bit logic and arithmetic instructions in AVX are all
4126 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4127 SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);
4128 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4129 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);
4131 } else if (VT.is512BitVector()) { // AVX-512
4132 SDValue Cst = DAG.getConstant(0, dl, MVT::i32);
4133 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,
4134 Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4135 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);
4136 } else if (VT.getScalarType() == MVT::i1) {
4138 assert((Subtarget->hasBWI() || VT.getVectorNumElements() <= 16)
4139 && "Unexpected vector type");
4140 assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)
4141 && "Unexpected vector type");
4142 SDValue Cst = DAG.getConstant(0, dl, MVT::i1);
4143 SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);
4144 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
4146 llvm_unreachable("Unexpected vector type");
4148 return DAG.getBitcast(VT, Vec);
4151 static SDValue ExtractSubVector(SDValue Vec, unsigned IdxVal,
4152 SelectionDAG &DAG, SDLoc dl,
4153 unsigned vectorWidth) {
4154 assert((vectorWidth == 128 || vectorWidth == 256) &&
4155 "Unsupported vector width");
4156 EVT VT = Vec.getValueType();
4157 EVT ElVT = VT.getVectorElementType();
4158 unsigned Factor = VT.getSizeInBits()/vectorWidth;
4159 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
4160 VT.getVectorNumElements()/Factor);
4162 // Extract from UNDEF is UNDEF.
4163 if (Vec.getOpcode() == ISD::UNDEF)
4164 return DAG.getUNDEF(ResultVT);
4166 // Extract the relevant vectorWidth bits. Generate an EXTRACT_SUBVECTOR
4167 unsigned ElemsPerChunk = vectorWidth / ElVT.getSizeInBits();
4169 // This is the index of the first element of the vectorWidth-bit chunk
4171 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / vectorWidth)
4174 // If the input is a buildvector just emit a smaller one.
4175 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
4176 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
4177 makeArrayRef(Vec->op_begin() + NormalizedIdxVal,
4180 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4181 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);
4184 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
4185 /// sets things up to match to an AVX VEXTRACTF128 / VEXTRACTI128
4186 /// or AVX-512 VEXTRACTF32x4 / VEXTRACTI32x4
4187 /// instructions or a simple subregister reference. Idx is an index in the
4188 /// 128 bits we want. It need not be aligned to a 128-bit boundary. That makes
4189 /// lowering EXTRACT_VECTOR_ELT operations easier.
4190 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
4191 SelectionDAG &DAG, SDLoc dl) {
4192 assert((Vec.getValueType().is256BitVector() ||
4193 Vec.getValueType().is512BitVector()) && "Unexpected vector size!");
4194 return ExtractSubVector(Vec, IdxVal, DAG, dl, 128);
4197 /// Generate a DAG to grab 256-bits from a 512-bit vector.
4198 static SDValue Extract256BitVector(SDValue Vec, unsigned IdxVal,
4199 SelectionDAG &DAG, SDLoc dl) {
4200 assert(Vec.getValueType().is512BitVector() && "Unexpected vector size!");
4201 return ExtractSubVector(Vec, IdxVal, DAG, dl, 256);
4204 static SDValue InsertSubVector(SDValue Result, SDValue Vec,
4205 unsigned IdxVal, SelectionDAG &DAG,
4206 SDLoc dl, unsigned vectorWidth) {
4207 assert((vectorWidth == 128 || vectorWidth == 256) &&
4208 "Unsupported vector width");
4209 // Inserting UNDEF is Result
4210 if (Vec.getOpcode() == ISD::UNDEF)
4212 EVT VT = Vec.getValueType();
4213 EVT ElVT = VT.getVectorElementType();
4214 EVT ResultVT = Result.getValueType();
4216 // Insert the relevant vectorWidth bits.
4217 unsigned ElemsPerChunk = vectorWidth/ElVT.getSizeInBits();
4219 // This is the index of the first element of the vectorWidth-bit chunk
4221 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)
4224 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);
4225 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);
4228 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
4229 /// sets things up to match to an AVX VINSERTF128/VINSERTI128 or
4230 /// AVX-512 VINSERTF32x4/VINSERTI32x4 instructions or a
4231 /// simple superregister reference. Idx is an index in the 128 bits
4232 /// we want. It need not be aligned to a 128-bit boundary. That makes
4233 /// lowering INSERT_VECTOR_ELT operations easier.
4234 static SDValue Insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4235 SelectionDAG &DAG, SDLoc dl) {
4236 assert(Vec.getValueType().is128BitVector() && "Unexpected vector size!");
4238 // For insertion into the zero index (low half) of a 256-bit vector, it is
4239 // more efficient to generate a blend with immediate instead of an insert*128.
4240 // We are still creating an INSERT_SUBVECTOR below with an undef node to
4241 // extend the subvector to the size of the result vector. Make sure that
4242 // we are not recursing on that node by checking for undef here.
4243 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4244 Result.getOpcode() != ISD::UNDEF) {
4245 EVT ResultVT = Result.getValueType();
4246 SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);
4247 SDValue Undef = DAG.getUNDEF(ResultVT);
4248 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,
4251 // The blend instruction, and therefore its mask, depend on the data type.
4252 MVT ScalarType = ResultVT.getScalarType().getSimpleVT();
4253 if (ScalarType.isFloatingPoint()) {
4254 // Choose either vblendps (float) or vblendpd (double).
4255 unsigned ScalarSize = ScalarType.getSizeInBits();
4256 assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");
4257 unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;
4258 SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);
4259 return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);
4262 const X86Subtarget &Subtarget =
4263 static_cast<const X86Subtarget &>(DAG.getSubtarget());
4265 // AVX2 is needed for 256-bit integer blend support.
4266 // Integers must be cast to 32-bit because there is only vpblendd;
4267 // vpblendw can't be used for this because it has a handicapped mask.
4269 // If we don't have AVX2, then cast to float. Using a wrong domain blend
4270 // is still more efficient than using the wrong domain vinsertf128 that
4271 // will be created by InsertSubVector().
4272 MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;
4274 SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);
4275 Vec256 = DAG.getBitcast(CastVT, Vec256);
4276 Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);
4277 return DAG.getBitcast(ResultVT, Vec256);
4280 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4283 static SDValue Insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4284 SelectionDAG &DAG, SDLoc dl) {
4285 assert(Vec.getValueType().is256BitVector() && "Unexpected vector size!");
4286 return InsertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4289 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
4290 /// instructions. This is used because creating CONCAT_VECTOR nodes of
4291 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
4292 /// large BUILD_VECTORS.
4293 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
4294 unsigned NumElems, SelectionDAG &DAG,
4296 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4297 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
4300 static SDValue Concat256BitVectors(SDValue V1, SDValue V2, EVT VT,
4301 unsigned NumElems, SelectionDAG &DAG,
4303 SDValue V = Insert256BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
4304 return Insert256BitVector(V, V2, NumElems/2, DAG, dl);
4307 /// getOnesVector - Returns a vector of specified type with all bits set.
4308 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4309 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4310 /// Then bitcast to their original type, ensuring they get CSE'd.
4311 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4313 assert(VT.isVector() && "Expected a vector type");
4315 SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);
4317 if (VT.is256BitVector()) {
4318 if (HasInt256) { // AVX2
4319 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4320 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);
4322 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4323 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4325 } else if (VT.is128BitVector()) {
4326 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4328 llvm_unreachable("Unexpected vector type");
4330 return DAG.getBitcast(VT, Vec);
4333 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4334 /// operation of specified width.
4335 static SDValue getMOVL(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue V1,
4337 unsigned NumElems = VT.getVectorNumElements();
4338 SmallVector<int, 8> Mask;
4339 Mask.push_back(NumElems);
4340 for (unsigned i = 1; i != NumElems; ++i)
4342 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4345 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4346 static SDValue getUnpackl(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4348 unsigned NumElems = VT.getVectorNumElements();
4349 SmallVector<int, 8> Mask;
4350 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4352 Mask.push_back(i + NumElems);
4354 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4357 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4358 static SDValue getUnpackh(SelectionDAG &DAG, SDLoc dl, MVT VT, SDValue V1,
4360 unsigned NumElems = VT.getVectorNumElements();
4361 SmallVector<int, 8> Mask;
4362 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4363 Mask.push_back(i + Half);
4364 Mask.push_back(i + NumElems + Half);
4366 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4369 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4370 /// vector of zero or undef vector. This produces a shuffle where the low
4371 /// element of V2 is swizzled into the zero/undef vector, landing at element
4372 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4373 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4375 const X86Subtarget *Subtarget,
4376 SelectionDAG &DAG) {
4377 MVT VT = V2.getSimpleValueType();
4379 ? getZeroVector(VT, Subtarget, DAG, SDLoc(V2)) : DAG.getUNDEF(VT);
4380 unsigned NumElems = VT.getVectorNumElements();
4381 SmallVector<int, 16> MaskVec;
4382 for (unsigned i = 0; i != NumElems; ++i)
4383 // If this is the insertion idx, put the low elt of V2 here.
4384 MaskVec.push_back(i == Idx ? NumElems : i);
4385 return DAG.getVectorShuffle(VT, SDLoc(V2), V1, V2, &MaskVec[0]);
4388 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4389 /// target specific opcode. Returns true if the Mask could be calculated. Sets
4390 /// IsUnary to true if only uses one source. Note that this will set IsUnary for
4391 /// shuffles which use a single input multiple times, and in those cases it will
4392 /// adjust the mask to only have indices within that single input.
4393 /// FIXME: Add support for Decode*Mask functions that return SM_SentinelZero.
4394 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4395 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4396 unsigned NumElems = VT.getVectorNumElements();
4400 bool IsFakeUnary = false;
4401 switch(N->getOpcode()) {
4402 case X86ISD::BLENDI:
4403 ImmN = N->getOperand(N->getNumOperands()-1);
4404 DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4407 ImmN = N->getOperand(N->getNumOperands()-1);
4408 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4409 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4411 case X86ISD::UNPCKH:
4412 DecodeUNPCKHMask(VT, Mask);
4413 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4415 case X86ISD::UNPCKL:
4416 DecodeUNPCKLMask(VT, Mask);
4417 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4419 case X86ISD::MOVHLPS:
4420 DecodeMOVHLPSMask(NumElems, Mask);
4421 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4423 case X86ISD::MOVLHPS:
4424 DecodeMOVLHPSMask(NumElems, Mask);
4425 IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
4427 case X86ISD::PALIGNR:
4428 ImmN = N->getOperand(N->getNumOperands()-1);
4429 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4431 case X86ISD::PSHUFD:
4432 case X86ISD::VPERMILPI:
4433 ImmN = N->getOperand(N->getNumOperands()-1);
4434 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4437 case X86ISD::PSHUFHW:
4438 ImmN = N->getOperand(N->getNumOperands()-1);
4439 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4442 case X86ISD::PSHUFLW:
4443 ImmN = N->getOperand(N->getNumOperands()-1);
4444 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4447 case X86ISD::PSHUFB: {
4449 SDValue MaskNode = N->getOperand(1);
4450 while (MaskNode->getOpcode() == ISD::BITCAST)
4451 MaskNode = MaskNode->getOperand(0);
4453 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) {
4454 // If we have a build-vector, then things are easy.
4455 EVT VT = MaskNode.getValueType();
4456 assert(VT.isVector() &&
4457 "Can't produce a non-vector with a build_vector!");
4458 if (!VT.isInteger())
4461 int NumBytesPerElement = VT.getVectorElementType().getSizeInBits() / 8;
4463 SmallVector<uint64_t, 32> RawMask;
4464 for (int i = 0, e = MaskNode->getNumOperands(); i < e; ++i) {
4465 SDValue Op = MaskNode->getOperand(i);
4466 if (Op->getOpcode() == ISD::UNDEF) {
4467 RawMask.push_back((uint64_t)SM_SentinelUndef);
4470 auto *CN = dyn_cast<ConstantSDNode>(Op.getNode());
4473 APInt MaskElement = CN->getAPIntValue();
4475 // We now have to decode the element which could be any integer size and
4476 // extract each byte of it.
4477 for (int j = 0; j < NumBytesPerElement; ++j) {
4478 // Note that this is x86 and so always little endian: the low byte is
4479 // the first byte of the mask.
4480 RawMask.push_back(MaskElement.getLoBits(8).getZExtValue());
4481 MaskElement = MaskElement.lshr(8);
4484 DecodePSHUFBMask(RawMask, Mask);
4488 auto *MaskLoad = dyn_cast<LoadSDNode>(MaskNode);
4492 SDValue Ptr = MaskLoad->getBasePtr();
4493 if (Ptr->getOpcode() == X86ISD::Wrapper ||
4494 Ptr->getOpcode() == X86ISD::WrapperRIP)
4495 Ptr = Ptr->getOperand(0);
4497 auto *MaskCP = dyn_cast<ConstantPoolSDNode>(Ptr);
4498 if (!MaskCP || MaskCP->isMachineConstantPoolEntry())
4501 if (auto *C = dyn_cast<Constant>(MaskCP->getConstVal())) {
4502 DecodePSHUFBMask(C, Mask);
4510 case X86ISD::VPERMI:
4511 ImmN = N->getOperand(N->getNumOperands()-1);
4512 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4517 DecodeScalarMoveMask(VT, /* IsLoad */ false, Mask);
4519 case X86ISD::VPERM2X128:
4520 ImmN = N->getOperand(N->getNumOperands()-1);
4521 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4522 if (Mask.empty()) return false;
4523 // Mask only contains negative index if an element is zero.
4524 if (std::any_of(Mask.begin(), Mask.end(),
4525 [](int M){ return M == SM_SentinelZero; }))
4528 case X86ISD::MOVSLDUP:
4529 DecodeMOVSLDUPMask(VT, Mask);
4532 case X86ISD::MOVSHDUP:
4533 DecodeMOVSHDUPMask(VT, Mask);
4536 case X86ISD::MOVDDUP:
4537 DecodeMOVDDUPMask(VT, Mask);
4540 case X86ISD::MOVLHPD:
4541 case X86ISD::MOVLPD:
4542 case X86ISD::MOVLPS:
4543 // Not yet implemented
4545 default: llvm_unreachable("unknown target shuffle node");
4548 // If we have a fake unary shuffle, the shuffle mask is spread across two
4549 // inputs that are actually the same node. Re-map the mask to always point
4550 // into the first input.
4553 if (M >= (int)Mask.size())
4559 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4560 /// element of the result of the vector shuffle.
4561 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4564 return SDValue(); // Limit search depth.
4566 SDValue V = SDValue(N, 0);
4567 EVT VT = V.getValueType();
4568 unsigned Opcode = V.getOpcode();
4570 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4571 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4572 int Elt = SV->getMaskElt(Index);
4575 return DAG.getUNDEF(VT.getVectorElementType());
4577 unsigned NumElems = VT.getVectorNumElements();
4578 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4579 : SV->getOperand(1);
4580 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4583 // Recurse into target specific vector shuffles to find scalars.
4584 if (isTargetShuffle(Opcode)) {
4585 MVT ShufVT = V.getSimpleValueType();
4586 unsigned NumElems = ShufVT.getVectorNumElements();
4587 SmallVector<int, 16> ShuffleMask;
4590 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4593 int Elt = ShuffleMask[Index];
4595 return DAG.getUNDEF(ShufVT.getVectorElementType());
4597 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4599 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4603 // Actual nodes that may contain scalar elements
4604 if (Opcode == ISD::BITCAST) {
4605 V = V.getOperand(0);
4606 EVT SrcVT = V.getValueType();
4607 unsigned NumElems = VT.getVectorNumElements();
4609 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4613 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4614 return (Index == 0) ? V.getOperand(0)
4615 : DAG.getUNDEF(VT.getVectorElementType());
4617 if (V.getOpcode() == ISD::BUILD_VECTOR)
4618 return V.getOperand(Index);
4623 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4625 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4626 unsigned NumNonZero, unsigned NumZero,
4628 const X86Subtarget* Subtarget,
4629 const TargetLowering &TLI) {
4637 // SSE4.1 - use PINSRB to insert each byte directly.
4638 if (Subtarget->hasSSE41()) {
4639 for (unsigned i = 0; i < 16; ++i) {
4640 bool isNonZero = (NonZeros & (1 << i)) != 0;
4644 V = getZeroVector(MVT::v16i8, Subtarget, DAG, dl);
4646 V = DAG.getUNDEF(MVT::v16i8);
4649 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4650 MVT::v16i8, V, Op.getOperand(i),
4651 DAG.getIntPtrConstant(i, dl));
4658 // Pre-SSE4.1 - merge byte pairs and insert with PINSRW.
4659 for (unsigned i = 0; i < 16; ++i) {
4660 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4661 if (ThisIsNonZero && First) {
4663 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4665 V = DAG.getUNDEF(MVT::v8i16);
4670 SDValue ThisElt, LastElt;
4671 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4672 if (LastIsNonZero) {
4673 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4674 MVT::i16, Op.getOperand(i-1));
4676 if (ThisIsNonZero) {
4677 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4678 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4679 ThisElt, DAG.getConstant(8, dl, MVT::i8));
4681 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4685 if (ThisElt.getNode())
4686 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4687 DAG.getIntPtrConstant(i/2, dl));
4691 return DAG.getBitcast(MVT::v16i8, V);
4694 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4696 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4697 unsigned NumNonZero, unsigned NumZero,
4699 const X86Subtarget* Subtarget,
4700 const TargetLowering &TLI) {
4707 for (unsigned i = 0; i < 8; ++i) {
4708 bool isNonZero = (NonZeros & (1 << i)) != 0;
4712 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4714 V = DAG.getUNDEF(MVT::v8i16);
4717 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4718 MVT::v8i16, V, Op.getOperand(i),
4719 DAG.getIntPtrConstant(i, dl));
4726 /// LowerBuildVectorv4x32 - Custom lower build_vector of v4i32 or v4f32.
4727 static SDValue LowerBuildVectorv4x32(SDValue Op, SelectionDAG &DAG,
4728 const X86Subtarget *Subtarget,
4729 const TargetLowering &TLI) {
4730 // Find all zeroable elements.
4731 std::bitset<4> Zeroable;
4732 for (int i=0; i < 4; ++i) {
4733 SDValue Elt = Op->getOperand(i);
4734 Zeroable[i] = (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt));
4736 assert(Zeroable.size() - Zeroable.count() > 1 &&
4737 "We expect at least two non-zero elements!");
4739 // We only know how to deal with build_vector nodes where elements are either
4740 // zeroable or extract_vector_elt with constant index.
4741 SDValue FirstNonZero;
4742 unsigned FirstNonZeroIdx;
4743 for (unsigned i=0; i < 4; ++i) {
4746 SDValue Elt = Op->getOperand(i);
4747 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4748 !isa<ConstantSDNode>(Elt.getOperand(1)))
4750 // Make sure that this node is extracting from a 128-bit vector.
4751 MVT VT = Elt.getOperand(0).getSimpleValueType();
4752 if (!VT.is128BitVector())
4754 if (!FirstNonZero.getNode()) {
4756 FirstNonZeroIdx = i;
4760 assert(FirstNonZero.getNode() && "Unexpected build vector of all zeros!");
4761 SDValue V1 = FirstNonZero.getOperand(0);
4762 MVT VT = V1.getSimpleValueType();
4764 // See if this build_vector can be lowered as a blend with zero.
4766 unsigned EltMaskIdx, EltIdx;
4768 for (EltIdx = 0; EltIdx < 4; ++EltIdx) {
4769 if (Zeroable[EltIdx]) {
4770 // The zero vector will be on the right hand side.
4771 Mask[EltIdx] = EltIdx+4;
4775 Elt = Op->getOperand(EltIdx);
4776 // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
4777 EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
4778 if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
4780 Mask[EltIdx] = EltIdx;
4784 // Let the shuffle legalizer deal with blend operations.
4785 SDValue VZero = getZeroVector(VT, Subtarget, DAG, SDLoc(Op));
4786 if (V1.getSimpleValueType() != VT)
4787 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), VT, V1);
4788 return DAG.getVectorShuffle(VT, SDLoc(V1), V1, VZero, &Mask[0]);
4791 // See if we can lower this build_vector to a INSERTPS.
4792 if (!Subtarget->hasSSE41())
4795 SDValue V2 = Elt.getOperand(0);
4796 if (Elt == FirstNonZero && EltIdx == FirstNonZeroIdx)
4799 bool CanFold = true;
4800 for (unsigned i = EltIdx + 1; i < 4 && CanFold; ++i) {
4804 SDValue Current = Op->getOperand(i);
4805 SDValue SrcVector = Current->getOperand(0);
4808 CanFold = SrcVector == V1 &&
4809 cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
4815 assert(V1.getNode() && "Expected at least two non-zero elements!");
4816 if (V1.getSimpleValueType() != MVT::v4f32)
4817 V1 = DAG.getNode(ISD::BITCAST, SDLoc(V1), MVT::v4f32, V1);
4818 if (V2.getSimpleValueType() != MVT::v4f32)
4819 V2 = DAG.getNode(ISD::BITCAST, SDLoc(V2), MVT::v4f32, V2);
4821 // Ok, we can emit an INSERTPS instruction.
4822 unsigned ZMask = Zeroable.to_ulong();
4824 unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;
4825 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
4827 SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
4828 DAG.getIntPtrConstant(InsertPSMask, DL));
4829 return DAG.getBitcast(VT, Result);
4832 /// Return a vector logical shift node.
4833 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4834 unsigned NumBits, SelectionDAG &DAG,
4835 const TargetLowering &TLI, SDLoc dl) {
4836 assert(VT.is128BitVector() && "Unknown type for VShift");
4837 MVT ShVT = MVT::v2i64;
4838 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4839 SrcOp = DAG.getBitcast(ShVT, SrcOp);
4840 MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());
4841 assert(NumBits % 8 == 0 && "Only support byte sized shifts");
4842 SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);
4843 return DAG.getBitcast(VT, DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));
4847 LowerAsSplatVectorLoad(SDValue SrcOp, MVT VT, SDLoc dl, SelectionDAG &DAG) {
4849 // Check if the scalar load can be widened into a vector load. And if
4850 // the address is "base + cst" see if the cst can be "absorbed" into
4851 // the shuffle mask.
4852 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4853 SDValue Ptr = LD->getBasePtr();
4854 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
4856 EVT PVT = LD->getValueType(0);
4857 if (PVT != MVT::i32 && PVT != MVT::f32)
4862 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
4863 FI = FINode->getIndex();
4865 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
4866 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4867 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4868 Offset = Ptr.getConstantOperandVal(1);
4869 Ptr = Ptr.getOperand(0);
4874 // FIXME: 256-bit vector instructions don't require a strict alignment,
4875 // improve this code to support it better.
4876 unsigned RequiredAlign = VT.getSizeInBits()/8;
4877 SDValue Chain = LD->getChain();
4878 // Make sure the stack object alignment is at least 16 or 32.
4879 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
4880 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
4881 if (MFI->isFixedObjectIndex(FI)) {
4882 // Can't change the alignment. FIXME: It's possible to compute
4883 // the exact stack offset and reference FI + adjust offset instead.
4884 // If someone *really* cares about this. That's the way to implement it.
4887 MFI->setObjectAlignment(FI, RequiredAlign);
4891 // (Offset % 16 or 32) must be multiple of 4. Then address is then
4892 // Ptr + (Offset & ~15).
4895 if ((Offset % RequiredAlign) & 3)
4897 int64_t StartOffset = Offset & ~(RequiredAlign-1);
4900 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
4901 DAG.getConstant(StartOffset, DL, Ptr.getValueType()));
4904 int EltNo = (Offset - StartOffset) >> 2;
4905 unsigned NumElems = VT.getVectorNumElements();
4907 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
4908 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
4909 LD->getPointerInfo().getWithOffset(StartOffset),
4910 false, false, false, 0);
4912 SmallVector<int, 8> Mask(NumElems, EltNo);
4914 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
4920 /// Given the initializing elements 'Elts' of a vector of type 'VT', see if the
4921 /// elements can be replaced by a single large load which has the same value as
4922 /// a build_vector or insert_subvector whose loaded operands are 'Elts'.
4924 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
4926 /// FIXME: we'd also like to handle the case where the last elements are zero
4927 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
4928 /// There's even a handy isZeroNode for that purpose.
4929 static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
4930 SDLoc &DL, SelectionDAG &DAG,
4931 bool isAfterLegalize) {
4932 unsigned NumElems = Elts.size();
4934 LoadSDNode *LDBase = nullptr;
4935 unsigned LastLoadedElt = -1U;
4937 // For each element in the initializer, see if we've found a load or an undef.
4938 // If we don't find an initial load element, or later load elements are
4939 // non-consecutive, bail out.
4940 for (unsigned i = 0; i < NumElems; ++i) {
4941 SDValue Elt = Elts[i];
4942 // Look through a bitcast.
4943 if (Elt.getNode() && Elt.getOpcode() == ISD::BITCAST)
4944 Elt = Elt.getOperand(0);
4945 if (!Elt.getNode() ||
4946 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
4949 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
4951 LDBase = cast<LoadSDNode>(Elt.getNode());
4955 if (Elt.getOpcode() == ISD::UNDEF)
4958 LoadSDNode *LD = cast<LoadSDNode>(Elt);
4959 EVT LdVT = Elt.getValueType();
4960 // Each loaded element must be the correct fractional portion of the
4961 // requested vector load.
4962 if (LdVT.getSizeInBits() != VT.getSizeInBits() / NumElems)
4964 if (!DAG.isConsecutiveLoad(LD, LDBase, LdVT.getSizeInBits() / 8, i))
4969 // If we have found an entire vector of loads and undefs, then return a large
4970 // load of the entire vector width starting at the base pointer. If we found
4971 // consecutive loads for the low half, generate a vzext_load node.
4972 if (LastLoadedElt == NumElems - 1) {
4973 assert(LDBase && "Did not find base load for merging consecutive loads");
4974 EVT EltVT = LDBase->getValueType(0);
4975 // Ensure that the input vector size for the merged loads matches the
4976 // cumulative size of the input elements.
4977 if (VT.getSizeInBits() != EltVT.getSizeInBits() * NumElems)
4980 if (isAfterLegalize &&
4981 !DAG.getTargetLoweringInfo().isOperationLegal(ISD::LOAD, VT))
4984 SDValue NewLd = SDValue();
4986 NewLd = DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
4987 LDBase->getPointerInfo(), LDBase->isVolatile(),
4988 LDBase->isNonTemporal(), LDBase->isInvariant(),
4989 LDBase->getAlignment());
4991 if (LDBase->hasAnyUseOfValue(1)) {
4992 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
4994 SDValue(NewLd.getNode(), 1));
4995 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
4996 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
4997 SDValue(NewLd.getNode(), 1));
5003 //TODO: The code below fires only for for loading the low v2i32 / v2f32
5004 //of a v4i32 / v4f32. It's probably worth generalizing.
5005 EVT EltVT = VT.getVectorElementType();
5006 if (NumElems == 4 && LastLoadedElt == 1 && (EltVT.getSizeInBits() == 32) &&
5007 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5008 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5009 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5011 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, MVT::i64,
5012 LDBase->getPointerInfo(),
5013 LDBase->getAlignment(),
5014 false/*isVolatile*/, true/*ReadMem*/,
5017 // Make sure the newly-created LOAD is in the same position as LDBase in
5018 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5019 // update uses of LDBase's output chain to use the TokenFactor.
5020 if (LDBase->hasAnyUseOfValue(1)) {
5021 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5022 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5023 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5024 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5025 SDValue(ResNode.getNode(), 1));
5028 return DAG.getBitcast(VT, ResNode);
5033 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5034 /// to generate a splat value for the following cases:
5035 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5036 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5037 /// a scalar load, or a constant.
5038 /// The VBROADCAST node is returned when a pattern is found,
5039 /// or SDValue() otherwise.
5040 static SDValue LowerVectorBroadcast(SDValue Op, const X86Subtarget* Subtarget,
5041 SelectionDAG &DAG) {
5042 // VBROADCAST requires AVX.
5043 // TODO: Splats could be generated for non-AVX CPUs using SSE
5044 // instructions, but there's less potential gain for only 128-bit vectors.
5045 if (!Subtarget->hasAVX())
5048 MVT VT = Op.getSimpleValueType();
5051 assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) &&
5052 "Unsupported vector type for broadcast.");
5057 switch (Op.getOpcode()) {
5059 // Unknown pattern found.
5062 case ISD::BUILD_VECTOR: {
5063 auto *BVOp = cast<BuildVectorSDNode>(Op.getNode());
5064 BitVector UndefElements;
5065 SDValue Splat = BVOp->getSplatValue(&UndefElements);
5067 // We need a splat of a single value to use broadcast, and it doesn't
5068 // make any sense if the value is only in one element of the vector.
5069 if (!Splat || (VT.getVectorNumElements() - UndefElements.count()) <= 1)
5073 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5074 Ld.getOpcode() == ISD::ConstantFP);
5076 // Make sure that all of the users of a non-constant load are from the
5077 // BUILD_VECTOR node.
5078 if (!ConstSplatVal && !BVOp->isOnlyUserOf(Ld.getNode()))
5083 case ISD::VECTOR_SHUFFLE: {
5084 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5086 // Shuffles must have a splat mask where the first element is
5088 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5091 SDValue Sc = Op.getOperand(0);
5092 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5093 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5095 if (!Subtarget->hasInt256())
5098 // Use the register form of the broadcast instruction available on AVX2.
5099 if (VT.getSizeInBits() >= 256)
5100 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5101 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5104 Ld = Sc.getOperand(0);
5105 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5106 Ld.getOpcode() == ISD::ConstantFP);
5108 // The scalar_to_vector node and the suspected
5109 // load node must have exactly one user.
5110 // Constants may have multiple users.
5112 // AVX-512 has register version of the broadcast
5113 bool hasRegVer = Subtarget->hasAVX512() && VT.is512BitVector() &&
5114 Ld.getValueType().getSizeInBits() >= 32;
5115 if (!ConstSplatVal && ((!Sc.hasOneUse() || !Ld.hasOneUse()) &&
5122 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5123 bool IsGE256 = (VT.getSizeInBits() >= 256);
5125 // When optimizing for size, generate up to 5 extra bytes for a broadcast
5126 // instruction to save 8 or more bytes of constant pool data.
5127 // TODO: If multiple splats are generated to load the same constant,
5128 // it may be detrimental to overall size. There needs to be a way to detect
5129 // that condition to know if this is truly a size win.
5130 const Function *F = DAG.getMachineFunction().getFunction();
5131 bool OptForSize = F->hasFnAttribute(Attribute::OptimizeForSize);
5133 // Handle broadcasting a single constant scalar from the constant pool
5135 // On Sandybridge (no AVX2), it is still better to load a constant vector
5136 // from the constant pool and not to broadcast it from a scalar.
5137 // But override that restriction when optimizing for size.
5138 // TODO: Check if splatting is recommended for other AVX-capable CPUs.
5139 if (ConstSplatVal && (Subtarget->hasAVX2() || OptForSize)) {
5140 EVT CVT = Ld.getValueType();
5141 assert(!CVT.isVector() && "Must not broadcast a vector type");
5143 // Splat f32, i32, v4f64, v4i64 in all cases with AVX2.
5144 // For size optimization, also splat v2f64 and v2i64, and for size opt
5145 // with AVX2, also splat i8 and i16.
5146 // With pattern matching, the VBROADCAST node may become a VMOVDDUP.
5147 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5148 (OptForSize && (ScalarSize == 64 || Subtarget->hasAVX2()))) {
5149 const Constant *C = nullptr;
5150 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5151 C = CI->getConstantIntValue();
5152 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5153 C = CF->getConstantFPValue();
5155 assert(C && "Invalid constant type");
5157 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5158 SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());
5159 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5160 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5161 MachinePointerInfo::getConstantPool(),
5162 false, false, false, Alignment);
5164 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5168 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5170 // Handle AVX2 in-register broadcasts.
5171 if (!IsLoad && Subtarget->hasInt256() &&
5172 (ScalarSize == 32 || (IsGE256 && ScalarSize == 64)))
5173 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5175 // The scalar source must be a normal load.
5179 if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
5180 (Subtarget->hasVLX() && ScalarSize == 64))
5181 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5183 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5184 // double since there is no vbroadcastsd xmm
5185 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5186 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5187 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5190 // Unsupported broadcast.
5194 /// \brief For an EXTRACT_VECTOR_ELT with a constant index return the real
5195 /// underlying vector and index.
5197 /// Modifies \p ExtractedFromVec to the real vector and returns the real
5199 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
5201 int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5202 if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
5205 // For 256-bit vectors, LowerEXTRACT_VECTOR_ELT_SSE4 may have already
5207 // (extract_vector_elt (v8f32 %vreg1), Constant<6>)
5209 // (extract_vector_elt (vector_shuffle<2,u,u,u>
5210 // (extract_subvector (v8f32 %vreg0), Constant<4>),
5213 // In this case the vector is the extract_subvector expression and the index
5214 // is 2, as specified by the shuffle.
5215 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(ExtractedFromVec);
5216 SDValue ShuffleVec = SVOp->getOperand(0);
5217 MVT ShuffleVecVT = ShuffleVec.getSimpleValueType();
5218 assert(ShuffleVecVT.getVectorElementType() ==
5219 ExtractedFromVec.getSimpleValueType().getVectorElementType());
5221 int ShuffleIdx = SVOp->getMaskElt(Idx);
5222 if (isUndefOrInRange(ShuffleIdx, 0, ShuffleVecVT.getVectorNumElements())) {
5223 ExtractedFromVec = ShuffleVec;
5229 static SDValue buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) {
5230 MVT VT = Op.getSimpleValueType();
5232 // Skip if insert_vec_elt is not supported.
5233 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5234 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5238 unsigned NumElems = Op.getNumOperands();
5242 SmallVector<unsigned, 4> InsertIndices;
5243 SmallVector<int, 8> Mask(NumElems, -1);
5245 for (unsigned i = 0; i != NumElems; ++i) {
5246 unsigned Opc = Op.getOperand(i).getOpcode();
5248 if (Opc == ISD::UNDEF)
5251 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5252 // Quit if more than 1 elements need inserting.
5253 if (InsertIndices.size() > 1)
5256 InsertIndices.push_back(i);
5260 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5261 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5262 // Quit if non-constant index.
5263 if (!isa<ConstantSDNode>(ExtIdx))
5265 int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
5267 // Quit if extracted from vector of different type.
5268 if (ExtractedFromVec.getValueType() != VT)
5271 if (!VecIn1.getNode())
5272 VecIn1 = ExtractedFromVec;
5273 else if (VecIn1 != ExtractedFromVec) {
5274 if (!VecIn2.getNode())
5275 VecIn2 = ExtractedFromVec;
5276 else if (VecIn2 != ExtractedFromVec)
5277 // Quit if more than 2 vectors to shuffle
5281 if (ExtractedFromVec == VecIn1)
5283 else if (ExtractedFromVec == VecIn2)
5284 Mask[i] = Idx + NumElems;
5287 if (!VecIn1.getNode())
5290 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5291 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5292 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5293 unsigned Idx = InsertIndices[i];
5294 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5295 DAG.getIntPtrConstant(Idx, DL));
5301 static SDValue ConvertI1VectorToInterger(SDValue Op, SelectionDAG &DAG) {
5302 assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
5303 Op.getScalarValueSizeInBits() == 1 &&
5304 "Can not convert non-constant vector");
5305 uint64_t Immediate = 0;
5306 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5307 SDValue In = Op.getOperand(idx);
5308 if (In.getOpcode() != ISD::UNDEF)
5309 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5313 MVT::getIntegerVT(std::max((int)Op.getValueType().getSizeInBits(), 8));
5314 return DAG.getConstant(Immediate, dl, VT);
5316 // Lower BUILD_VECTOR operation for v8i1 and v16i1 types.
5318 X86TargetLowering::LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const {
5320 MVT VT = Op.getSimpleValueType();
5321 assert((VT.getVectorElementType() == MVT::i1) &&
5322 "Unexpected type in LowerBUILD_VECTORvXi1!");
5325 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5326 SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);
5327 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5328 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5331 if (ISD::isBuildVectorAllOnes(Op.getNode())) {
5332 SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);
5333 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);
5334 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
5337 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
5338 SDValue Imm = ConvertI1VectorToInterger(Op, DAG);
5339 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5340 return DAG.getBitcast(VT, Imm);
5341 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5342 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5343 DAG.getIntPtrConstant(0, dl));
5346 // Vector has one or more non-const elements
5347 uint64_t Immediate = 0;
5348 SmallVector<unsigned, 16> NonConstIdx;
5349 bool IsSplat = true;
5350 bool HasConstElts = false;
5352 for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
5353 SDValue In = Op.getOperand(idx);
5354 if (In.getOpcode() == ISD::UNDEF)
5356 if (!isa<ConstantSDNode>(In))
5357 NonConstIdx.push_back(idx);
5359 Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
5360 HasConstElts = true;
5364 else if (In != Op.getOperand(SplatIdx))
5368 // for splat use " (select i1 splat_elt, all-ones, all-zeroes)"
5370 return DAG.getNode(ISD::SELECT, dl, VT, Op.getOperand(SplatIdx),
5371 DAG.getConstant(1, dl, VT),
5372 DAG.getConstant(0, dl, VT));
5374 // insert elements one by one
5378 MVT ImmVT = MVT::getIntegerVT(std::max((int)VT.getSizeInBits(), 8));
5379 Imm = DAG.getConstant(Immediate, dl, ImmVT);
5381 else if (HasConstElts)
5382 Imm = DAG.getConstant(0, dl, VT);
5384 Imm = DAG.getUNDEF(VT);
5385 if (Imm.getValueSizeInBits() == VT.getSizeInBits())
5386 DstVec = DAG.getBitcast(VT, Imm);
5388 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm);
5389 DstVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec,
5390 DAG.getIntPtrConstant(0, dl));
5393 for (unsigned i = 0; i < NonConstIdx.size(); ++i) {
5394 unsigned InsertIdx = NonConstIdx[i];
5395 DstVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,
5396 Op.getOperand(InsertIdx),
5397 DAG.getIntPtrConstant(InsertIdx, dl));
5402 /// \brief Return true if \p N implements a horizontal binop and return the
5403 /// operands for the horizontal binop into V0 and V1.
5405 /// This is a helper function of LowerToHorizontalOp().
5406 /// This function checks that the build_vector \p N in input implements a
5407 /// horizontal operation. Parameter \p Opcode defines the kind of horizontal
5408 /// operation to match.
5409 /// For example, if \p Opcode is equal to ISD::ADD, then this function
5410 /// checks if \p N implements a horizontal arithmetic add; if instead \p Opcode
5411 /// is equal to ISD::SUB, then this function checks if this is a horizontal
5414 /// This function only analyzes elements of \p N whose indices are
5415 /// in range [BaseIdx, LastIdx).
5416 static bool isHorizontalBinOp(const BuildVectorSDNode *N, unsigned Opcode,
5418 unsigned BaseIdx, unsigned LastIdx,
5419 SDValue &V0, SDValue &V1) {
5420 EVT VT = N->getValueType(0);
5422 assert(BaseIdx * 2 <= LastIdx && "Invalid Indices in input!");
5423 assert(VT.isVector() && VT.getVectorNumElements() >= LastIdx &&
5424 "Invalid Vector in input!");
5426 bool IsCommutable = (Opcode == ISD::ADD || Opcode == ISD::FADD);
5427 bool CanFold = true;
5428 unsigned ExpectedVExtractIdx = BaseIdx;
5429 unsigned NumElts = LastIdx - BaseIdx;
5430 V0 = DAG.getUNDEF(VT);
5431 V1 = DAG.getUNDEF(VT);
5433 // Check if N implements a horizontal binop.
5434 for (unsigned i = 0, e = NumElts; i != e && CanFold; ++i) {
5435 SDValue Op = N->getOperand(i + BaseIdx);
5438 if (Op->getOpcode() == ISD::UNDEF) {
5439 // Update the expected vector extract index.
5440 if (i * 2 == NumElts)
5441 ExpectedVExtractIdx = BaseIdx;
5442 ExpectedVExtractIdx += 2;
5446 CanFold = Op->getOpcode() == Opcode && Op->hasOneUse();
5451 SDValue Op0 = Op.getOperand(0);
5452 SDValue Op1 = Op.getOperand(1);
5454 // Try to match the following pattern:
5455 // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
5456 CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5457 Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5458 Op0.getOperand(0) == Op1.getOperand(0) &&
5459 isa<ConstantSDNode>(Op0.getOperand(1)) &&
5460 isa<ConstantSDNode>(Op1.getOperand(1)));
5464 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5465 unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
5467 if (i * 2 < NumElts) {
5468 if (V0.getOpcode() == ISD::UNDEF) {
5469 V0 = Op0.getOperand(0);
5470 if (V0.getValueType() != VT)
5474 if (V1.getOpcode() == ISD::UNDEF) {
5475 V1 = Op0.getOperand(0);
5476 if (V1.getValueType() != VT)
5479 if (i * 2 == NumElts)
5480 ExpectedVExtractIdx = BaseIdx;
5483 SDValue Expected = (i * 2 < NumElts) ? V0 : V1;
5484 if (I0 == ExpectedVExtractIdx)
5485 CanFold = I1 == I0 + 1 && Op0.getOperand(0) == Expected;
5486 else if (IsCommutable && I1 == ExpectedVExtractIdx) {
5487 // Try to match the following dag sequence:
5488 // (BINOP (extract_vector_elt A, I+1), (extract_vector_elt A, I))
5489 CanFold = I0 == I1 + 1 && Op1.getOperand(0) == Expected;
5493 ExpectedVExtractIdx += 2;
5499 /// \brief Emit a sequence of two 128-bit horizontal add/sub followed by
5500 /// a concat_vector.
5502 /// This is a helper function of LowerToHorizontalOp().
5503 /// This function expects two 256-bit vectors called V0 and V1.
5504 /// At first, each vector is split into two separate 128-bit vectors.
5505 /// Then, the resulting 128-bit vectors are used to implement two
5506 /// horizontal binary operations.
5508 /// The kind of horizontal binary operation is defined by \p X86Opcode.
5510 /// \p Mode specifies how the 128-bit parts of V0 and V1 are passed in input to
5511 /// the two new horizontal binop.
5512 /// When Mode is set, the first horizontal binop dag node would take as input
5513 /// the lower 128-bit of V0 and the upper 128-bit of V0. The second
5514 /// horizontal binop dag node would take as input the lower 128-bit of V1
5515 /// and the upper 128-bit of V1.
5517 /// HADD V0_LO, V0_HI
5518 /// HADD V1_LO, V1_HI
5520 /// Otherwise, the first horizontal binop dag node takes as input the lower
5521 /// 128-bit of V0 and the lower 128-bit of V1, and the second horizontal binop
5522 /// dag node takes the upper 128-bit of V0 and the upper 128-bit of V1.
5524 /// HADD V0_LO, V1_LO
5525 /// HADD V0_HI, V1_HI
5527 /// If \p isUndefLO is set, then the algorithm propagates UNDEF to the lower
5528 /// 128-bits of the result. If \p isUndefHI is set, then UNDEF is propagated to
5529 /// the upper 128-bits of the result.
5530 static SDValue ExpandHorizontalBinOp(const SDValue &V0, const SDValue &V1,
5531 SDLoc DL, SelectionDAG &DAG,
5532 unsigned X86Opcode, bool Mode,
5533 bool isUndefLO, bool isUndefHI) {
5534 EVT VT = V0.getValueType();
5535 assert(VT.is256BitVector() && VT == V1.getValueType() &&
5536 "Invalid nodes in input!");
5538 unsigned NumElts = VT.getVectorNumElements();
5539 SDValue V0_LO = Extract128BitVector(V0, 0, DAG, DL);
5540 SDValue V0_HI = Extract128BitVector(V0, NumElts/2, DAG, DL);
5541 SDValue V1_LO = Extract128BitVector(V1, 0, DAG, DL);
5542 SDValue V1_HI = Extract128BitVector(V1, NumElts/2, DAG, DL);
5543 EVT NewVT = V0_LO.getValueType();
5545 SDValue LO = DAG.getUNDEF(NewVT);
5546 SDValue HI = DAG.getUNDEF(NewVT);
5549 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5550 if (!isUndefLO && V0->getOpcode() != ISD::UNDEF)
5551 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V0_HI);
5552 if (!isUndefHI && V1->getOpcode() != ISD::UNDEF)
5553 HI = DAG.getNode(X86Opcode, DL, NewVT, V1_LO, V1_HI);
5555 // Don't emit a horizontal binop if the result is expected to be UNDEF.
5556 if (!isUndefLO && (V0_LO->getOpcode() != ISD::UNDEF ||
5557 V1_LO->getOpcode() != ISD::UNDEF))
5558 LO = DAG.getNode(X86Opcode, DL, NewVT, V0_LO, V1_LO);
5560 if (!isUndefHI && (V0_HI->getOpcode() != ISD::UNDEF ||
5561 V1_HI->getOpcode() != ISD::UNDEF))
5562 HI = DAG.getNode(X86Opcode, DL, NewVT, V0_HI, V1_HI);
5565 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LO, HI);
5568 /// Try to fold a build_vector that performs an 'addsub' to an X86ISD::ADDSUB
5570 static SDValue LowerToAddSub(const BuildVectorSDNode *BV,
5571 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5572 EVT VT = BV->getValueType(0);
5573 if ((!Subtarget->hasSSE3() || (VT != MVT::v4f32 && VT != MVT::v2f64)) &&
5574 (!Subtarget->hasAVX() || (VT != MVT::v8f32 && VT != MVT::v4f64)))
5578 unsigned NumElts = VT.getVectorNumElements();
5579 SDValue InVec0 = DAG.getUNDEF(VT);
5580 SDValue InVec1 = DAG.getUNDEF(VT);
5582 assert((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v4f32 ||
5583 VT == MVT::v2f64) && "build_vector with an invalid type found!");
5585 // Odd-numbered elements in the input build vector are obtained from
5586 // adding two integer/float elements.
5587 // Even-numbered elements in the input build vector are obtained from
5588 // subtracting two integer/float elements.
5589 unsigned ExpectedOpcode = ISD::FSUB;
5590 unsigned NextExpectedOpcode = ISD::FADD;
5591 bool AddFound = false;
5592 bool SubFound = false;
5594 for (unsigned i = 0, e = NumElts; i != e; ++i) {
5595 SDValue Op = BV->getOperand(i);
5597 // Skip 'undef' values.
5598 unsigned Opcode = Op.getOpcode();
5599 if (Opcode == ISD::UNDEF) {
5600 std::swap(ExpectedOpcode, NextExpectedOpcode);
5604 // Early exit if we found an unexpected opcode.
5605 if (Opcode != ExpectedOpcode)
5608 SDValue Op0 = Op.getOperand(0);
5609 SDValue Op1 = Op.getOperand(1);
5611 // Try to match the following pattern:
5612 // (BINOP (extract_vector_elt A, i), (extract_vector_elt B, i))
5613 // Early exit if we cannot match that sequence.
5614 if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5615 Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5616 !isa<ConstantSDNode>(Op0.getOperand(1)) ||
5617 !isa<ConstantSDNode>(Op1.getOperand(1)) ||
5618 Op0.getOperand(1) != Op1.getOperand(1))
5621 unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
5625 // We found a valid add/sub node. Update the information accordingly.
5631 // Update InVec0 and InVec1.
5632 if (InVec0.getOpcode() == ISD::UNDEF) {
5633 InVec0 = Op0.getOperand(0);
5634 if (InVec0.getValueType() != VT)
5637 if (InVec1.getOpcode() == ISD::UNDEF) {
5638 InVec1 = Op1.getOperand(0);
5639 if (InVec1.getValueType() != VT)
5643 // Make sure that operands in input to each add/sub node always
5644 // come from a same pair of vectors.
5645 if (InVec0 != Op0.getOperand(0)) {
5646 if (ExpectedOpcode == ISD::FSUB)
5649 // FADD is commutable. Try to commute the operands
5650 // and then test again.
5651 std::swap(Op0, Op1);
5652 if (InVec0 != Op0.getOperand(0))
5656 if (InVec1 != Op1.getOperand(0))
5659 // Update the pair of expected opcodes.
5660 std::swap(ExpectedOpcode, NextExpectedOpcode);
5663 // Don't try to fold this build_vector into an ADDSUB if the inputs are undef.
5664 if (AddFound && SubFound && InVec0.getOpcode() != ISD::UNDEF &&
5665 InVec1.getOpcode() != ISD::UNDEF)
5666 return DAG.getNode(X86ISD::ADDSUB, DL, VT, InVec0, InVec1);
5671 /// Lower BUILD_VECTOR to a horizontal add/sub operation if possible.
5672 static SDValue LowerToHorizontalOp(const BuildVectorSDNode *BV,
5673 const X86Subtarget *Subtarget,
5674 SelectionDAG &DAG) {
5675 EVT VT = BV->getValueType(0);
5676 unsigned NumElts = VT.getVectorNumElements();
5677 unsigned NumUndefsLO = 0;
5678 unsigned NumUndefsHI = 0;
5679 unsigned Half = NumElts/2;
5681 // Count the number of UNDEF operands in the build_vector in input.
5682 for (unsigned i = 0, e = Half; i != e; ++i)
5683 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5686 for (unsigned i = Half, e = NumElts; i != e; ++i)
5687 if (BV->getOperand(i)->getOpcode() == ISD::UNDEF)
5690 // Early exit if this is either a build_vector of all UNDEFs or all the
5691 // operands but one are UNDEF.
5692 if (NumUndefsLO + NumUndefsHI + 1 >= NumElts)
5696 SDValue InVec0, InVec1;
5697 if ((VT == MVT::v4f32 || VT == MVT::v2f64) && Subtarget->hasSSE3()) {
5698 // Try to match an SSE3 float HADD/HSUB.
5699 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5700 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5702 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5703 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5704 } else if ((VT == MVT::v4i32 || VT == MVT::v8i16) && Subtarget->hasSSSE3()) {
5705 // Try to match an SSSE3 integer HADD/HSUB.
5706 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5707 return DAG.getNode(X86ISD::HADD, DL, VT, InVec0, InVec1);
5709 if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5710 return DAG.getNode(X86ISD::HSUB, DL, VT, InVec0, InVec1);
5713 if (!Subtarget->hasAVX())
5716 if ((VT == MVT::v8f32 || VT == MVT::v4f64)) {
5717 // Try to match an AVX horizontal add/sub of packed single/double
5718 // precision floating point values from 256-bit vectors.
5719 SDValue InVec2, InVec3;
5720 if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, Half, InVec0, InVec1) &&
5721 isHorizontalBinOp(BV, ISD::FADD, DAG, Half, NumElts, InVec2, InVec3) &&
5722 ((InVec0.getOpcode() == ISD::UNDEF ||
5723 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5724 ((InVec1.getOpcode() == ISD::UNDEF ||
5725 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5726 return DAG.getNode(X86ISD::FHADD, DL, VT, InVec0, InVec1);
5728 if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, Half, InVec0, InVec1) &&
5729 isHorizontalBinOp(BV, ISD::FSUB, DAG, Half, NumElts, InVec2, InVec3) &&
5730 ((InVec0.getOpcode() == ISD::UNDEF ||
5731 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5732 ((InVec1.getOpcode() == ISD::UNDEF ||
5733 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5734 return DAG.getNode(X86ISD::FHSUB, DL, VT, InVec0, InVec1);
5735 } else if (VT == MVT::v8i32 || VT == MVT::v16i16) {
5736 // Try to match an AVX2 horizontal add/sub of signed integers.
5737 SDValue InVec2, InVec3;
5739 bool CanFold = true;
5741 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, Half, InVec0, InVec1) &&
5742 isHorizontalBinOp(BV, ISD::ADD, DAG, Half, NumElts, InVec2, InVec3) &&
5743 ((InVec0.getOpcode() == ISD::UNDEF ||
5744 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5745 ((InVec1.getOpcode() == ISD::UNDEF ||
5746 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5747 X86Opcode = X86ISD::HADD;
5748 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, Half, InVec0, InVec1) &&
5749 isHorizontalBinOp(BV, ISD::SUB, DAG, Half, NumElts, InVec2, InVec3) &&
5750 ((InVec0.getOpcode() == ISD::UNDEF ||
5751 InVec2.getOpcode() == ISD::UNDEF) || InVec0 == InVec2) &&
5752 ((InVec1.getOpcode() == ISD::UNDEF ||
5753 InVec3.getOpcode() == ISD::UNDEF) || InVec1 == InVec3))
5754 X86Opcode = X86ISD::HSUB;
5759 // Fold this build_vector into a single horizontal add/sub.
5760 // Do this only if the target has AVX2.
5761 if (Subtarget->hasAVX2())
5762 return DAG.getNode(X86Opcode, DL, VT, InVec0, InVec1);
5764 // Do not try to expand this build_vector into a pair of horizontal
5765 // add/sub if we can emit a pair of scalar add/sub.
5766 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5769 // Convert this build_vector into a pair of horizontal binop followed by
5771 bool isUndefLO = NumUndefsLO == Half;
5772 bool isUndefHI = NumUndefsHI == Half;
5773 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, false,
5774 isUndefLO, isUndefHI);
5778 if ((VT == MVT::v8f32 || VT == MVT::v4f64 || VT == MVT::v8i32 ||
5779 VT == MVT::v16i16) && Subtarget->hasAVX()) {
5781 if (isHorizontalBinOp(BV, ISD::ADD, DAG, 0, NumElts, InVec0, InVec1))
5782 X86Opcode = X86ISD::HADD;
5783 else if (isHorizontalBinOp(BV, ISD::SUB, DAG, 0, NumElts, InVec0, InVec1))
5784 X86Opcode = X86ISD::HSUB;
5785 else if (isHorizontalBinOp(BV, ISD::FADD, DAG, 0, NumElts, InVec0, InVec1))
5786 X86Opcode = X86ISD::FHADD;
5787 else if (isHorizontalBinOp(BV, ISD::FSUB, DAG, 0, NumElts, InVec0, InVec1))
5788 X86Opcode = X86ISD::FHSUB;
5792 // Don't try to expand this build_vector into a pair of horizontal add/sub
5793 // if we can simply emit a pair of scalar add/sub.
5794 if (NumUndefsLO + 1 == Half || NumUndefsHI + 1 == Half)
5797 // Convert this build_vector into two horizontal add/sub followed by
5799 bool isUndefLO = NumUndefsLO == Half;
5800 bool isUndefHI = NumUndefsHI == Half;
5801 return ExpandHorizontalBinOp(InVec0, InVec1, DL, DAG, X86Opcode, true,
5802 isUndefLO, isUndefHI);
5809 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5812 MVT VT = Op.getSimpleValueType();
5813 MVT ExtVT = VT.getVectorElementType();
5814 unsigned NumElems = Op.getNumOperands();
5816 // Generate vectors for predicate vectors.
5817 if (VT.getScalarType() == MVT::i1 && Subtarget->hasAVX512())
5818 return LowerBUILD_VECTORvXi1(Op, DAG);
5820 // Vectors containing all zeros can be matched by pxor and xorps later
5821 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5822 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5823 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5824 if (VT == MVT::v4i32 || VT == MVT::v8i32 || VT == MVT::v16i32)
5827 return getZeroVector(VT, Subtarget, DAG, dl);
5830 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5831 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5832 // vpcmpeqd on 256-bit vectors.
5833 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5834 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5837 if (!VT.is512BitVector())
5838 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5841 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(Op.getNode());
5842 if (SDValue AddSub = LowerToAddSub(BV, Subtarget, DAG))
5844 if (SDValue HorizontalOp = LowerToHorizontalOp(BV, Subtarget, DAG))
5845 return HorizontalOp;
5846 if (SDValue Broadcast = LowerVectorBroadcast(Op, Subtarget, DAG))
5849 unsigned EVTBits = ExtVT.getSizeInBits();
5851 unsigned NumZero = 0;
5852 unsigned NumNonZero = 0;
5853 unsigned NonZeros = 0;
5854 bool IsAllConstants = true;
5855 SmallSet<SDValue, 8> Values;
5856 for (unsigned i = 0; i < NumElems; ++i) {
5857 SDValue Elt = Op.getOperand(i);
5858 if (Elt.getOpcode() == ISD::UNDEF)
5861 if (Elt.getOpcode() != ISD::Constant &&
5862 Elt.getOpcode() != ISD::ConstantFP)
5863 IsAllConstants = false;
5864 if (X86::isZeroNode(Elt))
5867 NonZeros |= (1 << i);
5872 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5873 if (NumNonZero == 0)
5874 return DAG.getUNDEF(VT);
5876 // Special case for single non-zero, non-undef, element.
5877 if (NumNonZero == 1) {
5878 unsigned Idx = countTrailingZeros(NonZeros);
5879 SDValue Item = Op.getOperand(Idx);
5881 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5882 // the value are obviously zero, truncate the value to i32 and do the
5883 // insertion that way. Only do this if the value is non-constant or if the
5884 // value is a constant being inserted into element 0. It is cheaper to do
5885 // a constant pool load than it is to do a movd + shuffle.
5886 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5887 (!IsAllConstants || Idx == 0)) {
5888 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5890 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5891 EVT VecVT = MVT::v4i32;
5893 // Truncate the value (which may itself be a constant) to i32, and
5894 // convert it to a vector with movd (S2V+shuffle to zero extend).
5895 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5896 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5897 return DAG.getBitcast(VT, getShuffleVectorZeroOrUndef(
5898 Item, Idx * 2, true, Subtarget, DAG));
5902 // If we have a constant or non-constant insertion into the low element of
5903 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5904 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5905 // depending on what the source datatype is.
5908 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5910 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5911 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5912 if (VT.is512BitVector()) {
5913 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5914 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5915 Item, DAG.getIntPtrConstant(0, dl));
5917 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5918 "Expected an SSE value type!");
5919 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5920 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5921 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5924 // We can't directly insert an i8 or i16 into a vector, so zero extend
5926 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5927 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5928 if (VT.is256BitVector()) {
5929 if (Subtarget->hasAVX()) {
5930 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v8i32, Item);
5931 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5933 // Without AVX, we need to extend to a 128-bit vector and then
5934 // insert into the 256-bit vector.
5935 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5936 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5937 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5940 assert(VT.is128BitVector() && "Expected an SSE value type!");
5941 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5942 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5944 return DAG.getBitcast(VT, Item);
5948 // Is it a vector logical left shift?
5949 if (NumElems == 2 && Idx == 1 &&
5950 X86::isZeroNode(Op.getOperand(0)) &&
5951 !X86::isZeroNode(Op.getOperand(1))) {
5952 unsigned NumBits = VT.getSizeInBits();
5953 return getVShift(true, VT,
5954 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5955 VT, Op.getOperand(1)),
5956 NumBits/2, DAG, *this, dl);
5959 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5962 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5963 // is a non-constant being inserted into an element other than the low one,
5964 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5965 // movd/movss) to move this into the low element, then shuffle it into
5967 if (EVTBits == 32) {
5968 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5969 return getShuffleVectorZeroOrUndef(Item, Idx, NumZero > 0, Subtarget, DAG);
5973 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5974 if (Values.size() == 1) {
5975 if (EVTBits == 32) {
5976 // Instead of a shuffle like this:
5977 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5978 // Check if it's possible to issue this instead.
5979 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5980 unsigned Idx = countTrailingZeros(NonZeros);
5981 SDValue Item = Op.getOperand(Idx);
5982 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5983 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5988 // A vector full of immediates; various special cases are already
5989 // handled, so this is best done with a single constant-pool load.
5993 // For AVX-length vectors, see if we can use a vector load to get all of the
5994 // elements, otherwise build the individual 128-bit pieces and use
5995 // shuffles to put them in place.
5996 if (VT.is256BitVector() || VT.is512BitVector()) {
5997 SmallVector<SDValue, 64> V(Op->op_begin(), Op->op_begin() + NumElems);
5999 // Check for a build vector of consecutive loads.
6000 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6003 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
6005 // Build both the lower and upper subvector.
6006 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6007 makeArrayRef(&V[0], NumElems/2));
6008 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT,
6009 makeArrayRef(&V[NumElems / 2], NumElems/2));
6011 // Recreate the wider vector with the lower and upper part.
6012 if (VT.is256BitVector())
6013 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6014 return Concat256BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
6017 // Let legalizer expand 2-wide build_vectors.
6018 if (EVTBits == 64) {
6019 if (NumNonZero == 1) {
6020 // One half is zero or undef.
6021 unsigned Idx = countTrailingZeros(NonZeros);
6022 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
6023 Op.getOperand(Idx));
6024 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
6029 // If element VT is < 32 bits, convert it to inserts into a zero vector.
6030 if (EVTBits == 8 && NumElems == 16)
6031 if (SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
6035 if (EVTBits == 16 && NumElems == 8)
6036 if (SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
6040 // If element VT is == 32 bits and has 4 elems, try to generate an INSERTPS
6041 if (EVTBits == 32 && NumElems == 4)
6042 if (SDValue V = LowerBuildVectorv4x32(Op, DAG, Subtarget, *this))
6045 // If element VT is == 32 bits, turn it into a number of shuffles.
6046 SmallVector<SDValue, 8> V(NumElems);
6047 if (NumElems == 4 && NumZero > 0) {
6048 for (unsigned i = 0; i < 4; ++i) {
6049 bool isZero = !(NonZeros & (1 << i));
6051 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
6053 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6056 for (unsigned i = 0; i < 2; ++i) {
6057 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
6060 V[i] = V[i*2]; // Must be a zero vector.
6063 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
6066 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
6069 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
6074 bool Reverse1 = (NonZeros & 0x3) == 2;
6075 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
6079 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
6080 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
6082 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
6085 if (Values.size() > 1 && VT.is128BitVector()) {
6086 // Check for a build vector of consecutive loads.
6087 for (unsigned i = 0; i < NumElems; ++i)
6088 V[i] = Op.getOperand(i);
6090 // Check for elements which are consecutive loads.
6091 if (SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG, false))
6094 // Check for a build vector from mostly shuffle plus few inserting.
6095 if (SDValue Sh = buildFromShuffleMostly(Op, DAG))
6098 // For SSE 4.1, use insertps to put the high elements into the low element.
6099 if (Subtarget->hasSSE41()) {
6101 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
6102 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
6104 Result = DAG.getUNDEF(VT);
6106 for (unsigned i = 1; i < NumElems; ++i) {
6107 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
6108 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
6109 Op.getOperand(i), DAG.getIntPtrConstant(i, dl));
6114 // Otherwise, expand into a number of unpckl*, start by extending each of
6115 // our (non-undef) elements to the full vector width with the element in the
6116 // bottom slot of the vector (which generates no code for SSE).
6117 for (unsigned i = 0; i < NumElems; ++i) {
6118 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
6119 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
6121 V[i] = DAG.getUNDEF(VT);
6124 // Next, we iteratively mix elements, e.g. for v4f32:
6125 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
6126 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
6127 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
6128 unsigned EltStride = NumElems >> 1;
6129 while (EltStride != 0) {
6130 for (unsigned i = 0; i < EltStride; ++i) {
6131 // If V[i+EltStride] is undef and this is the first round of mixing,
6132 // then it is safe to just drop this shuffle: V[i] is already in the
6133 // right place, the one element (since it's the first round) being
6134 // inserted as undef can be dropped. This isn't safe for successive
6135 // rounds because they will permute elements within both vectors.
6136 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
6137 EltStride == NumElems/2)
6140 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
6149 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
6150 // to create 256-bit vectors from two other 128-bit ones.
6151 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6153 MVT ResVT = Op.getSimpleValueType();
6155 assert((ResVT.is256BitVector() ||
6156 ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");
6158 SDValue V1 = Op.getOperand(0);
6159 SDValue V2 = Op.getOperand(1);
6160 unsigned NumElems = ResVT.getVectorNumElements();
6161 if (ResVT.is256BitVector())
6162 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6164 if (Op.getNumOperands() == 4) {
6165 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6166 ResVT.getVectorNumElements()/2);
6167 SDValue V3 = Op.getOperand(2);
6168 SDValue V4 = Op.getOperand(3);
6169 return Concat256BitVectors(Concat128BitVectors(V1, V2, HalfVT, NumElems/2, DAG, dl),
6170 Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);
6172 return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
6175 static SDValue LowerCONCAT_VECTORSvXi1(SDValue Op,
6176 const X86Subtarget *Subtarget,
6177 SelectionDAG & DAG) {
6179 MVT ResVT = Op.getSimpleValueType();
6180 unsigned NumOfOperands = Op.getNumOperands();
6182 assert(isPowerOf2_32(NumOfOperands) &&
6183 "Unexpected number of operands in CONCAT_VECTORS");
6185 if (NumOfOperands > 2) {
6186 MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),
6187 ResVT.getVectorNumElements()/2);
6188 SmallVector<SDValue, 2> Ops;
6189 for (unsigned i = 0; i < NumOfOperands/2; i++)
6190 Ops.push_back(Op.getOperand(i));
6191 SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6193 for (unsigned i = NumOfOperands/2; i < NumOfOperands; i++)
6194 Ops.push_back(Op.getOperand(i));
6195 SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HalfVT, Ops);
6196 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);
6199 SDValue V1 = Op.getOperand(0);
6200 SDValue V2 = Op.getOperand(1);
6201 bool IsZeroV1 = ISD::isBuildVectorAllZeros(V1.getNode());
6202 bool IsZeroV2 = ISD::isBuildVectorAllZeros(V2.getNode());
6204 if (IsZeroV1 && IsZeroV2)
6205 return getZeroVector(ResVT, Subtarget, DAG, dl);
6207 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
6208 SDValue Undef = DAG.getUNDEF(ResVT);
6209 unsigned NumElems = ResVT.getVectorNumElements();
6210 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
6212 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);
6213 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);
6217 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);
6218 // Zero the upper bits of V1
6219 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);
6220 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);
6223 return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);
6226 static SDValue LowerCONCAT_VECTORS(SDValue Op,
6227 const X86Subtarget *Subtarget,
6228 SelectionDAG &DAG) {
6229 MVT VT = Op.getSimpleValueType();
6230 if (VT.getVectorElementType() == MVT::i1)
6231 return LowerCONCAT_VECTORSvXi1(Op, Subtarget, DAG);
6233 assert((VT.is256BitVector() && Op.getNumOperands() == 2) ||
6234 (VT.is512BitVector() && (Op.getNumOperands() == 2 ||
6235 Op.getNumOperands() == 4)));
6237 // AVX can use the vinsertf128 instruction to create 256-bit vectors
6238 // from two other 128-bit ones.
6240 // 512-bit vector may contain 2 256-bit vectors or 4 128-bit vectors
6241 return LowerAVXCONCAT_VECTORS(Op, DAG);
6245 //===----------------------------------------------------------------------===//
6246 // Vector shuffle lowering
6248 // This is an experimental code path for lowering vector shuffles on x86. It is
6249 // designed to handle arbitrary vector shuffles and blends, gracefully
6250 // degrading performance as necessary. It works hard to recognize idiomatic
6251 // shuffles and lower them to optimal instruction patterns without leaving
6252 // a framework that allows reasonably efficient handling of all vector shuffle
6254 //===----------------------------------------------------------------------===//
6256 /// \brief Tiny helper function to identify a no-op mask.
6258 /// This is a somewhat boring predicate function. It checks whether the mask
6259 /// array input, which is assumed to be a single-input shuffle mask of the kind
6260 /// used by the X86 shuffle instructions (not a fully general
6261 /// ShuffleVectorSDNode mask) requires any shuffles to occur. Both undef and an
6262 /// in-place shuffle are 'no-op's.
6263 static bool isNoopShuffleMask(ArrayRef<int> Mask) {
6264 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6265 if (Mask[i] != -1 && Mask[i] != i)
6270 /// \brief Helper function to classify a mask as a single-input mask.
6272 /// This isn't a generic single-input test because in the vector shuffle
6273 /// lowering we canonicalize single inputs to be the first input operand. This
6274 /// means we can more quickly test for a single input by only checking whether
6275 /// an input from the second operand exists. We also assume that the size of
6276 /// mask corresponds to the size of the input vectors which isn't true in the
6277 /// fully general case.
6278 static bool isSingleInputShuffleMask(ArrayRef<int> Mask) {
6280 if (M >= (int)Mask.size())
6285 /// \brief Test whether there are elements crossing 128-bit lanes in this
6288 /// X86 divides up its shuffles into in-lane and cross-lane shuffle operations
6289 /// and we routinely test for these.
6290 static bool is128BitLaneCrossingShuffleMask(MVT VT, ArrayRef<int> Mask) {
6291 int LaneSize = 128 / VT.getScalarSizeInBits();
6292 int Size = Mask.size();
6293 for (int i = 0; i < Size; ++i)
6294 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
6299 /// \brief Test whether a shuffle mask is equivalent within each 128-bit lane.
6301 /// This checks a shuffle mask to see if it is performing the same
6302 /// 128-bit lane-relative shuffle in each 128-bit lane. This trivially implies
6303 /// that it is also not lane-crossing. It may however involve a blend from the
6304 /// same lane of a second vector.
6306 /// The specific repeated shuffle mask is populated in \p RepeatedMask, as it is
6307 /// non-trivial to compute in the face of undef lanes. The representation is
6308 /// *not* suitable for use with existing 128-bit shuffles as it will contain
6309 /// entries from both V1 and V2 inputs to the wider mask.
6311 is128BitLaneRepeatedShuffleMask(MVT VT, ArrayRef<int> Mask,
6312 SmallVectorImpl<int> &RepeatedMask) {
6313 int LaneSize = 128 / VT.getScalarSizeInBits();
6314 RepeatedMask.resize(LaneSize, -1);
6315 int Size = Mask.size();
6316 for (int i = 0; i < Size; ++i) {
6319 if ((Mask[i] % Size) / LaneSize != i / LaneSize)
6320 // This entry crosses lanes, so there is no way to model this shuffle.
6323 // Ok, handle the in-lane shuffles by detecting if and when they repeat.
6324 if (RepeatedMask[i % LaneSize] == -1)
6325 // This is the first non-undef entry in this slot of a 128-bit lane.
6326 RepeatedMask[i % LaneSize] =
6327 Mask[i] < Size ? Mask[i] % LaneSize : Mask[i] % LaneSize + Size;
6328 else if (RepeatedMask[i % LaneSize] + (i / LaneSize) * LaneSize != Mask[i])
6329 // Found a mismatch with the repeated mask.
6335 /// \brief Checks whether a shuffle mask is equivalent to an explicit list of
6338 /// This is a fast way to test a shuffle mask against a fixed pattern:
6340 /// if (isShuffleEquivalent(Mask, 3, 2, {1, 0})) { ... }
6342 /// It returns true if the mask is exactly as wide as the argument list, and
6343 /// each element of the mask is either -1 (signifying undef) or the value given
6344 /// in the argument.
6345 static bool isShuffleEquivalent(SDValue V1, SDValue V2, ArrayRef<int> Mask,
6346 ArrayRef<int> ExpectedMask) {
6347 if (Mask.size() != ExpectedMask.size())
6350 int Size = Mask.size();
6352 // If the values are build vectors, we can look through them to find
6353 // equivalent inputs that make the shuffles equivalent.
6354 auto *BV1 = dyn_cast<BuildVectorSDNode>(V1);
6355 auto *BV2 = dyn_cast<BuildVectorSDNode>(V2);
6357 for (int i = 0; i < Size; ++i)
6358 if (Mask[i] != -1 && Mask[i] != ExpectedMask[i]) {
6359 auto *MaskBV = Mask[i] < Size ? BV1 : BV2;
6360 auto *ExpectedBV = ExpectedMask[i] < Size ? BV1 : BV2;
6361 if (!MaskBV || !ExpectedBV ||
6362 MaskBV->getOperand(Mask[i] % Size) !=
6363 ExpectedBV->getOperand(ExpectedMask[i] % Size))
6370 /// \brief Get a 4-lane 8-bit shuffle immediate for a mask.
6372 /// This helper function produces an 8-bit shuffle immediate corresponding to
6373 /// the ubiquitous shuffle encoding scheme used in x86 instructions for
6374 /// shuffling 4 lanes. It can be used with most of the PSHUF instructions for
6377 /// NB: We rely heavily on "undef" masks preserving the input lane.
6378 static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,
6379 SelectionDAG &DAG) {
6380 assert(Mask.size() == 4 && "Only 4-lane shuffle masks");
6381 assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");
6382 assert(Mask[1] >= -1 && Mask[1] < 4 && "Out of bound mask element!");
6383 assert(Mask[2] >= -1 && Mask[2] < 4 && "Out of bound mask element!");
6384 assert(Mask[3] >= -1 && Mask[3] < 4 && "Out of bound mask element!");
6387 Imm |= (Mask[0] == -1 ? 0 : Mask[0]) << 0;
6388 Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;
6389 Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;
6390 Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;
6391 return DAG.getConstant(Imm, DL, MVT::i8);
6394 /// \brief Try to emit a blend instruction for a shuffle using bit math.
6396 /// This is used as a fallback approach when first class blend instructions are
6397 /// unavailable. Currently it is only suitable for integer vectors, but could
6398 /// be generalized for floating point vectors if desirable.
6399 static SDValue lowerVectorShuffleAsBitBlend(SDLoc DL, MVT VT, SDValue V1,
6400 SDValue V2, ArrayRef<int> Mask,
6401 SelectionDAG &DAG) {
6402 assert(VT.isInteger() && "Only supports integer vector types!");
6403 MVT EltVT = VT.getScalarType();
6404 int NumEltBits = EltVT.getSizeInBits();
6405 SDValue Zero = DAG.getConstant(0, DL, EltVT);
6406 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6408 SmallVector<SDValue, 16> MaskOps;
6409 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6410 if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)
6411 return SDValue(); // Shuffled input!
6412 MaskOps.push_back(Mask[i] < Size ? AllOnes : Zero);
6415 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps);
6416 V1 = DAG.getNode(ISD::AND, DL, VT, V1, V1Mask);
6417 // We have to cast V2 around.
6418 MVT MaskVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
6419 V2 = DAG.getBitcast(VT, DAG.getNode(X86ISD::ANDNP, DL, MaskVT,
6420 DAG.getBitcast(MaskVT, V1Mask),
6421 DAG.getBitcast(MaskVT, V2)));
6422 return DAG.getNode(ISD::OR, DL, VT, V1, V2);
6425 /// \brief Try to emit a blend instruction for a shuffle.
6427 /// This doesn't do any checks for the availability of instructions for blending
6428 /// these values. It relies on the availability of the X86ISD::BLENDI pattern to
6429 /// be matched in the backend with the type given. What it does check for is
6430 /// that the shuffle mask is in fact a blend.
6431 static SDValue lowerVectorShuffleAsBlend(SDLoc DL, MVT VT, SDValue V1,
6432 SDValue V2, ArrayRef<int> Mask,
6433 const X86Subtarget *Subtarget,
6434 SelectionDAG &DAG) {
6435 unsigned BlendMask = 0;
6436 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6437 if (Mask[i] >= Size) {
6438 if (Mask[i] != i + Size)
6439 return SDValue(); // Shuffled V2 input!
6440 BlendMask |= 1u << i;
6443 if (Mask[i] >= 0 && Mask[i] != i)
6444 return SDValue(); // Shuffled V1 input!
6446 switch (VT.SimpleTy) {
6451 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,
6452 DAG.getConstant(BlendMask, DL, MVT::i8));
6456 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6460 // If we have AVX2 it is faster to use VPBLENDD when the shuffle fits into
6461 // that instruction.
6462 if (Subtarget->hasAVX2()) {
6463 // Scale the blend by the number of 32-bit dwords per element.
6464 int Scale = VT.getScalarSizeInBits() / 32;
6466 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6467 if (Mask[i] >= Size)
6468 for (int j = 0; j < Scale; ++j)
6469 BlendMask |= 1u << (i * Scale + j);
6471 MVT BlendVT = VT.getSizeInBits() > 128 ? MVT::v8i32 : MVT::v4i32;
6472 V1 = DAG.getBitcast(BlendVT, V1);
6473 V2 = DAG.getBitcast(BlendVT, V2);
6474 return DAG.getBitcast(
6475 VT, DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,
6476 DAG.getConstant(BlendMask, DL, MVT::i8)));
6480 // For integer shuffles we need to expand the mask and cast the inputs to
6481 // v8i16s prior to blending.
6482 int Scale = 8 / VT.getVectorNumElements();
6484 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6485 if (Mask[i] >= Size)
6486 for (int j = 0; j < Scale; ++j)
6487 BlendMask |= 1u << (i * Scale + j);
6489 V1 = DAG.getBitcast(MVT::v8i16, V1);
6490 V2 = DAG.getBitcast(MVT::v8i16, V2);
6491 return DAG.getBitcast(VT,
6492 DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,
6493 DAG.getConstant(BlendMask, DL, MVT::i8)));
6497 assert(Subtarget->hasAVX2() && "256-bit integer blends require AVX2!");
6498 SmallVector<int, 8> RepeatedMask;
6499 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
6500 // We can lower these with PBLENDW which is mirrored across 128-bit lanes.
6501 assert(RepeatedMask.size() == 8 && "Repeated mask size doesn't match!");
6503 for (int i = 0; i < 8; ++i)
6504 if (RepeatedMask[i] >= 16)
6505 BlendMask |= 1u << i;
6506 return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,
6507 DAG.getConstant(BlendMask, DL, MVT::i8));
6513 assert((VT.getSizeInBits() == 128 || Subtarget->hasAVX2()) &&
6514 "256-bit byte-blends require AVX2 support!");
6516 // Scale the blend by the number of bytes per element.
6517 int Scale = VT.getScalarSizeInBits() / 8;
6519 // This form of blend is always done on bytes. Compute the byte vector
6521 MVT BlendVT = MVT::getVectorVT(MVT::i8, VT.getSizeInBits() / 8);
6523 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
6524 // mix of LLVM's code generator and the x86 backend. We tell the code
6525 // generator that boolean values in the elements of an x86 vector register
6526 // are -1 for true and 0 for false. We then use the LLVM semantics of 'true'
6527 // mapping a select to operand #1, and 'false' mapping to operand #2. The
6528 // reality in x86 is that vector masks (pre-AVX-512) use only the high bit
6529 // of the element (the remaining are ignored) and 0 in that high bit would
6530 // mean operand #1 while 1 in the high bit would mean operand #2. So while
6531 // the LLVM model for boolean values in vector elements gets the relevant
6532 // bit set, it is set backwards and over constrained relative to x86's
6534 SmallVector<SDValue, 32> VSELECTMask;
6535 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6536 for (int j = 0; j < Scale; ++j)
6537 VSELECTMask.push_back(
6538 Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)
6539 : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,
6542 V1 = DAG.getBitcast(BlendVT, V1);
6543 V2 = DAG.getBitcast(BlendVT, V2);
6544 return DAG.getBitcast(VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
6545 DAG.getNode(ISD::BUILD_VECTOR, DL,
6546 BlendVT, VSELECTMask),
6551 llvm_unreachable("Not a supported integer vector type!");
6555 /// \brief Try to lower as a blend of elements from two inputs followed by
6556 /// a single-input permutation.
6558 /// This matches the pattern where we can blend elements from two inputs and
6559 /// then reduce the shuffle to a single-input permutation.
6560 static SDValue lowerVectorShuffleAsBlendAndPermute(SDLoc DL, MVT VT, SDValue V1,
6563 SelectionDAG &DAG) {
6564 // We build up the blend mask while checking whether a blend is a viable way
6565 // to reduce the shuffle.
6566 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6567 SmallVector<int, 32> PermuteMask(Mask.size(), -1);
6569 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6573 assert(Mask[i] < Size * 2 && "Shuffle input is out of bounds.");
6575 if (BlendMask[Mask[i] % Size] == -1)
6576 BlendMask[Mask[i] % Size] = Mask[i];
6577 else if (BlendMask[Mask[i] % Size] != Mask[i])
6578 return SDValue(); // Can't blend in the needed input!
6580 PermuteMask[i] = Mask[i] % Size;
6583 SDValue V = DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6584 return DAG.getVectorShuffle(VT, DL, V, DAG.getUNDEF(VT), PermuteMask);
6587 /// \brief Generic routine to decompose a shuffle and blend into indepndent
6588 /// blends and permutes.
6590 /// This matches the extremely common pattern for handling combined
6591 /// shuffle+blend operations on newer X86 ISAs where we have very fast blend
6592 /// operations. It will try to pick the best arrangement of shuffles and
6594 static SDValue lowerVectorShuffleAsDecomposedShuffleBlend(SDLoc DL, MVT VT,
6598 SelectionDAG &DAG) {
6599 // Shuffle the input elements into the desired positions in V1 and V2 and
6600 // blend them together.
6601 SmallVector<int, 32> V1Mask(Mask.size(), -1);
6602 SmallVector<int, 32> V2Mask(Mask.size(), -1);
6603 SmallVector<int, 32> BlendMask(Mask.size(), -1);
6604 for (int i = 0, Size = Mask.size(); i < Size; ++i)
6605 if (Mask[i] >= 0 && Mask[i] < Size) {
6606 V1Mask[i] = Mask[i];
6608 } else if (Mask[i] >= Size) {
6609 V2Mask[i] = Mask[i] - Size;
6610 BlendMask[i] = i + Size;
6613 // Try to lower with the simpler initial blend strategy unless one of the
6614 // input shuffles would be a no-op. We prefer to shuffle inputs as the
6615 // shuffle may be able to fold with a load or other benefit. However, when
6616 // we'll have to do 2x as many shuffles in order to achieve this, blending
6617 // first is a better strategy.
6618 if (!isNoopShuffleMask(V1Mask) && !isNoopShuffleMask(V2Mask))
6619 if (SDValue BlendPerm =
6620 lowerVectorShuffleAsBlendAndPermute(DL, VT, V1, V2, Mask, DAG))
6623 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
6624 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
6625 return DAG.getVectorShuffle(VT, DL, V1, V2, BlendMask);
6628 /// \brief Try to lower a vector shuffle as a byte rotation.
6630 /// SSSE3 has a generic PALIGNR instruction in x86 that will do an arbitrary
6631 /// byte-rotation of the concatenation of two vectors; pre-SSSE3 can use
6632 /// a PSRLDQ/PSLLDQ/POR pattern to get a similar effect. This routine will
6633 /// try to generically lower a vector shuffle through such an pattern. It
6634 /// does not check for the profitability of lowering either as PALIGNR or
6635 /// PSRLDQ/PSLLDQ/POR, only whether the mask is valid to lower in that form.
6636 /// This matches shuffle vectors that look like:
6638 /// v8i16 [11, 12, 13, 14, 15, 0, 1, 2]
6640 /// Essentially it concatenates V1 and V2, shifts right by some number of
6641 /// elements, and takes the low elements as the result. Note that while this is
6642 /// specified as a *right shift* because x86 is little-endian, it is a *left
6643 /// rotate* of the vector lanes.
6644 static SDValue lowerVectorShuffleAsByteRotate(SDLoc DL, MVT VT, SDValue V1,
6647 const X86Subtarget *Subtarget,
6648 SelectionDAG &DAG) {
6649 assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
6651 int NumElts = Mask.size();
6652 int NumLanes = VT.getSizeInBits() / 128;
6653 int NumLaneElts = NumElts / NumLanes;
6655 // We need to detect various ways of spelling a rotation:
6656 // [11, 12, 13, 14, 15, 0, 1, 2]
6657 // [-1, 12, 13, 14, -1, -1, 1, -1]
6658 // [-1, -1, -1, -1, -1, -1, 1, 2]
6659 // [ 3, 4, 5, 6, 7, 8, 9, 10]
6660 // [-1, 4, 5, 6, -1, -1, 9, -1]
6661 // [-1, 4, 5, 6, -1, -1, -1, -1]
6664 for (int l = 0; l < NumElts; l += NumLaneElts) {
6665 for (int i = 0; i < NumLaneElts; ++i) {
6666 if (Mask[l + i] == -1)
6668 assert(Mask[l + i] >= 0 && "Only -1 is a valid negative mask element!");
6670 // Get the mod-Size index and lane correct it.
6671 int LaneIdx = (Mask[l + i] % NumElts) - l;
6672 // Make sure it was in this lane.
6673 if (LaneIdx < 0 || LaneIdx >= NumLaneElts)
6676 // Determine where a rotated vector would have started.
6677 int StartIdx = i - LaneIdx;
6679 // The identity rotation isn't interesting, stop.
6682 // If we found the tail of a vector the rotation must be the missing
6683 // front. If we found the head of a vector, it must be how much of the
6685 int CandidateRotation = StartIdx < 0 ? -StartIdx : NumLaneElts - StartIdx;
6688 Rotation = CandidateRotation;
6689 else if (Rotation != CandidateRotation)
6690 // The rotations don't match, so we can't match this mask.
6693 // Compute which value this mask is pointing at.
6694 SDValue MaskV = Mask[l + i] < NumElts ? V1 : V2;
6696 // Compute which of the two target values this index should be assigned
6697 // to. This reflects whether the high elements are remaining or the low
6698 // elements are remaining.
6699 SDValue &TargetV = StartIdx < 0 ? Hi : Lo;
6701 // Either set up this value if we've not encountered it before, or check
6702 // that it remains consistent.
6705 else if (TargetV != MaskV)
6706 // This may be a rotation, but it pulls from the inputs in some
6707 // unsupported interleaving.
6712 // Check that we successfully analyzed the mask, and normalize the results.
6713 assert(Rotation != 0 && "Failed to locate a viable rotation!");
6714 assert((Lo || Hi) && "Failed to find a rotated input vector!");
6720 // The actual rotate instruction rotates bytes, so we need to scale the
6721 // rotation based on how many bytes are in the vector lane.
6722 int Scale = 16 / NumLaneElts;
6724 // SSSE3 targets can use the palignr instruction.
6725 if (Subtarget->hasSSSE3()) {
6726 // Cast the inputs to i8 vector of correct length to match PALIGNR.
6727 MVT AlignVT = MVT::getVectorVT(MVT::i8, 16 * NumLanes);
6728 Lo = DAG.getBitcast(AlignVT, Lo);
6729 Hi = DAG.getBitcast(AlignVT, Hi);
6731 return DAG.getBitcast(
6732 VT, DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,
6733 DAG.getConstant(Rotation * Scale, DL, MVT::i8)));
6736 assert(VT.getSizeInBits() == 128 &&
6737 "Rotate-based lowering only supports 128-bit lowering!");
6738 assert(Mask.size() <= 16 &&
6739 "Can shuffle at most 16 bytes in a 128-bit vector!");
6741 // Default SSE2 implementation
6742 int LoByteShift = 16 - Rotation * Scale;
6743 int HiByteShift = Rotation * Scale;
6745 // Cast the inputs to v2i64 to match PSLLDQ/PSRLDQ.
6746 Lo = DAG.getBitcast(MVT::v2i64, Lo);
6747 Hi = DAG.getBitcast(MVT::v2i64, Hi);
6749 SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,
6750 DAG.getConstant(LoByteShift, DL, MVT::i8));
6751 SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,
6752 DAG.getConstant(HiByteShift, DL, MVT::i8));
6753 return DAG.getBitcast(VT,
6754 DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));
6757 /// \brief Compute whether each element of a shuffle is zeroable.
6759 /// A "zeroable" vector shuffle element is one which can be lowered to zero.
6760 /// Either it is an undef element in the shuffle mask, the element of the input
6761 /// referenced is undef, or the element of the input referenced is known to be
6762 /// zero. Many x86 shuffles can zero lanes cheaply and we often want to handle
6763 /// as many lanes with this technique as possible to simplify the remaining
6765 static SmallBitVector computeZeroableShuffleElements(ArrayRef<int> Mask,
6766 SDValue V1, SDValue V2) {
6767 SmallBitVector Zeroable(Mask.size(), false);
6769 while (V1.getOpcode() == ISD::BITCAST)
6770 V1 = V1->getOperand(0);
6771 while (V2.getOpcode() == ISD::BITCAST)
6772 V2 = V2->getOperand(0);
6774 bool V1IsZero = ISD::isBuildVectorAllZeros(V1.getNode());
6775 bool V2IsZero = ISD::isBuildVectorAllZeros(V2.getNode());
6777 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6779 // Handle the easy cases.
6780 if (M < 0 || (M >= 0 && M < Size && V1IsZero) || (M >= Size && V2IsZero)) {
6785 // If this is an index into a build_vector node (which has the same number
6786 // of elements), dig out the input value and use it.
6787 SDValue V = M < Size ? V1 : V2;
6788 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands())
6791 SDValue Input = V.getOperand(M % Size);
6792 // The UNDEF opcode check really should be dead code here, but not quite
6793 // worth asserting on (it isn't invalid, just unexpected).
6794 if (Input.getOpcode() == ISD::UNDEF || X86::isZeroNode(Input))
6801 /// \brief Try to emit a bitmask instruction for a shuffle.
6803 /// This handles cases where we can model a blend exactly as a bitmask due to
6804 /// one of the inputs being zeroable.
6805 static SDValue lowerVectorShuffleAsBitMask(SDLoc DL, MVT VT, SDValue V1,
6806 SDValue V2, ArrayRef<int> Mask,
6807 SelectionDAG &DAG) {
6808 MVT EltVT = VT.getScalarType();
6809 int NumEltBits = EltVT.getSizeInBits();
6810 MVT IntEltVT = MVT::getIntegerVT(NumEltBits);
6811 SDValue Zero = DAG.getConstant(0, DL, IntEltVT);
6812 SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,
6814 if (EltVT.isFloatingPoint()) {
6815 Zero = DAG.getBitcast(EltVT, Zero);
6816 AllOnes = DAG.getBitcast(EltVT, AllOnes);
6818 SmallVector<SDValue, 16> VMaskOps(Mask.size(), Zero);
6819 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6821 for (int i = 0, Size = Mask.size(); i < Size; ++i) {
6824 if (Mask[i] % Size != i)
6825 return SDValue(); // Not a blend.
6827 V = Mask[i] < Size ? V1 : V2;
6828 else if (V != (Mask[i] < Size ? V1 : V2))
6829 return SDValue(); // Can only let one input through the mask.
6831 VMaskOps[i] = AllOnes;
6834 return SDValue(); // No non-zeroable elements!
6836 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps);
6837 V = DAG.getNode(VT.isFloatingPoint()
6838 ? (unsigned) X86ISD::FAND : (unsigned) ISD::AND,
6843 /// \brief Try to lower a vector shuffle as a bit shift (shifts in zeros).
6845 /// Attempts to match a shuffle mask against the PSLL(W/D/Q/DQ) and
6846 /// PSRL(W/D/Q/DQ) SSE2 and AVX2 logical bit-shift instructions. The function
6847 /// matches elements from one of the input vectors shuffled to the left or
6848 /// right with zeroable elements 'shifted in'. It handles both the strictly
6849 /// bit-wise element shifts and the byte shift across an entire 128-bit double
6852 /// PSHL : (little-endian) left bit shift.
6853 /// [ zz, 0, zz, 2 ]
6854 /// [ -1, 4, zz, -1 ]
6855 /// PSRL : (little-endian) right bit shift.
6857 /// [ -1, -1, 7, zz]
6858 /// PSLLDQ : (little-endian) left byte shift
6859 /// [ zz, 0, 1, 2, 3, 4, 5, 6]
6860 /// [ zz, zz, -1, -1, 2, 3, 4, -1]
6861 /// [ zz, zz, zz, zz, zz, zz, -1, 1]
6862 /// PSRLDQ : (little-endian) right byte shift
6863 /// [ 5, 6, 7, zz, zz, zz, zz, zz]
6864 /// [ -1, 5, 6, 7, zz, zz, zz, zz]
6865 /// [ 1, 2, -1, -1, -1, -1, zz, zz]
6866 static SDValue lowerVectorShuffleAsShift(SDLoc DL, MVT VT, SDValue V1,
6867 SDValue V2, ArrayRef<int> Mask,
6868 SelectionDAG &DAG) {
6869 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6871 int Size = Mask.size();
6872 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6874 auto CheckZeros = [&](int Shift, int Scale, bool Left) {
6875 for (int i = 0; i < Size; i += Scale)
6876 for (int j = 0; j < Shift; ++j)
6877 if (!Zeroable[i + j + (Left ? 0 : (Scale - Shift))])
6883 auto MatchShift = [&](int Shift, int Scale, bool Left, SDValue V) {
6884 for (int i = 0; i != Size; i += Scale) {
6885 unsigned Pos = Left ? i + Shift : i;
6886 unsigned Low = Left ? i : i + Shift;
6887 unsigned Len = Scale - Shift;
6888 if (!isSequentialOrUndefInRange(Mask, Pos, Len,
6889 Low + (V == V1 ? 0 : Size)))
6893 int ShiftEltBits = VT.getScalarSizeInBits() * Scale;
6894 bool ByteShift = ShiftEltBits > 64;
6895 unsigned OpCode = Left ? (ByteShift ? X86ISD::VSHLDQ : X86ISD::VSHLI)
6896 : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);
6897 int ShiftAmt = Shift * VT.getScalarSizeInBits() / (ByteShift ? 8 : 1);
6899 // Normalize the scale for byte shifts to still produce an i64 element
6901 Scale = ByteShift ? Scale / 2 : Scale;
6903 // We need to round trip through the appropriate type for the shift.
6904 MVT ShiftSVT = MVT::getIntegerVT(VT.getScalarSizeInBits() * Scale);
6905 MVT ShiftVT = MVT::getVectorVT(ShiftSVT, Size / Scale);
6906 assert(DAG.getTargetLoweringInfo().isTypeLegal(ShiftVT) &&
6907 "Illegal integer vector type");
6908 V = DAG.getBitcast(ShiftVT, V);
6910 V = DAG.getNode(OpCode, DL, ShiftVT, V,
6911 DAG.getConstant(ShiftAmt, DL, MVT::i8));
6912 return DAG.getBitcast(VT, V);
6915 // SSE/AVX supports logical shifts up to 64-bit integers - so we can just
6916 // keep doubling the size of the integer elements up to that. We can
6917 // then shift the elements of the integer vector by whole multiples of
6918 // their width within the elements of the larger integer vector. Test each
6919 // multiple to see if we can find a match with the moved element indices
6920 // and that the shifted in elements are all zeroable.
6921 for (int Scale = 2; Scale * VT.getScalarSizeInBits() <= 128; Scale *= 2)
6922 for (int Shift = 1; Shift != Scale; ++Shift)
6923 for (bool Left : {true, false})
6924 if (CheckZeros(Shift, Scale, Left))
6925 for (SDValue V : {V1, V2})
6926 if (SDValue Match = MatchShift(Shift, Scale, Left, V))
6933 /// \brief Try to lower a vector shuffle using SSE4a EXTRQ/INSERTQ.
6934 static SDValue lowerVectorShuffleWithSSE4A(SDLoc DL, MVT VT, SDValue V1,
6935 SDValue V2, ArrayRef<int> Mask,
6936 SelectionDAG &DAG) {
6937 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
6938 assert(!Zeroable.all() && "Fully zeroable shuffle mask");
6940 int Size = Mask.size();
6941 int HalfSize = Size / 2;
6942 assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
6944 // Upper half must be undefined.
6945 if (!isUndefInRange(Mask, HalfSize, HalfSize))
6948 // EXTRQ: Extract Len elements from lower half of source, starting at Idx.
6949 // Remainder of lower half result is zero and upper half is all undef.
6950 auto LowerAsEXTRQ = [&]() {
6951 // Determine the extraction length from the part of the
6952 // lower half that isn't zeroable.
6954 for (; Len >= 0; --Len)
6955 if (!Zeroable[Len - 1])
6957 assert(Len > 0 && "Zeroable shuffle mask");
6959 // Attempt to match first Len sequential elements from the lower half.
6962 for (int i = 0; i != Len; ++i) {
6966 SDValue &V = (M < Size ? V1 : V2);
6969 // All mask elements must be in the lower half.
6973 if (Idx < 0 || (Src == V && Idx == (M - i))) {
6984 assert((Idx + Len) <= HalfSize && "Illegal extraction mask");
6985 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
6986 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
6987 return DAG.getNode(X86ISD::EXTRQI, DL, VT, Src,
6988 DAG.getConstant(BitLen, DL, MVT::i8),
6989 DAG.getConstant(BitIdx, DL, MVT::i8));
6992 if (SDValue ExtrQ = LowerAsEXTRQ())
6995 // INSERTQ: Extract lowest Len elements from lower half of second source and
6996 // insert over first source, starting at Idx.
6997 // { A[0], .., A[Idx-1], B[0], .., B[Len-1], A[Idx+Len], .., UNDEF, ... }
6998 auto LowerAsInsertQ = [&]() {
6999 for (int Idx = 0; Idx != HalfSize; ++Idx) {
7002 // Attempt to match first source from mask before insertion point.
7003 if (isUndefInRange(Mask, 0, Idx)) {
7005 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, 0)) {
7007 } else if (isSequentialOrUndefInRange(Mask, 0, Idx, Size)) {
7013 // Extend the extraction length looking to match both the insertion of
7014 // the second source and the remaining elements of the first.
7015 for (int Hi = Idx + 1; Hi <= HalfSize; ++Hi) {
7020 if (isSequentialOrUndefInRange(Mask, Idx, Len, 0)) {
7022 } else if (isSequentialOrUndefInRange(Mask, Idx, Len, Size)) {
7028 // Match the remaining elements of the lower half.
7029 if (isUndefInRange(Mask, Hi, HalfSize - Hi)) {
7031 } else if ((!Base || (Base == V1)) &&
7032 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi, Hi)) {
7034 } else if ((!Base || (Base == V2)) &&
7035 isSequentialOrUndefInRange(Mask, Hi, HalfSize - Hi,
7042 // We may not have a base (first source) - this can safely be undefined.
7044 Base = DAG.getUNDEF(VT);
7046 int BitLen = (Len * VT.getScalarSizeInBits()) & 0x3f;
7047 int BitIdx = (Idx * VT.getScalarSizeInBits()) & 0x3f;
7048 return DAG.getNode(X86ISD::INSERTQI, DL, VT, Base, Insert,
7049 DAG.getConstant(BitLen, DL, MVT::i8),
7050 DAG.getConstant(BitIdx, DL, MVT::i8));
7057 if (SDValue InsertQ = LowerAsInsertQ())
7063 /// \brief Lower a vector shuffle as a zero or any extension.
7065 /// Given a specific number of elements, element bit width, and extension
7066 /// stride, produce either a zero or any extension based on the available
7067 /// features of the subtarget.
7068 static SDValue lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7069 SDLoc DL, MVT VT, int Scale, bool AnyExt, SDValue InputV,
7070 ArrayRef<int> Mask, const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7071 assert(Scale > 1 && "Need a scale to extend.");
7072 int NumElements = VT.getVectorNumElements();
7073 int EltBits = VT.getScalarSizeInBits();
7074 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
7075 "Only 8, 16, and 32 bit elements can be extended.");
7076 assert(Scale * EltBits <= 64 && "Cannot zero extend past 64 bits.");
7078 // Found a valid zext mask! Try various lowering strategies based on the
7079 // input type and available ISA extensions.
7080 if (Subtarget->hasSSE41()) {
7081 MVT ExtVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits * Scale),
7082 NumElements / Scale);
7083 return DAG.getBitcast(VT, DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV));
7086 // For any extends we can cheat for larger element sizes and use shuffle
7087 // instructions that can fold with a load and/or copy.
7088 if (AnyExt && EltBits == 32) {
7089 int PSHUFDMask[4] = {0, -1, 1, -1};
7090 return DAG.getBitcast(
7091 VT, DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7092 DAG.getBitcast(MVT::v4i32, InputV),
7093 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
7095 if (AnyExt && EltBits == 16 && Scale > 2) {
7096 int PSHUFDMask[4] = {0, -1, 0, -1};
7097 InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,
7098 DAG.getBitcast(MVT::v4i32, InputV),
7099 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));
7100 int PSHUFHWMask[4] = {1, -1, -1, -1};
7101 return DAG.getBitcast(
7102 VT, DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,
7103 DAG.getBitcast(MVT::v8i16, InputV),
7104 getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));
7107 // The SSE4A EXTRQ instruction can efficiently extend the first 2 lanes
7109 if ((Scale * EltBits) == 64 && EltBits < 32 && Subtarget->hasSSE4A()) {
7110 assert(NumElements == (int)Mask.size() && "Unexpected shuffle mask size!");
7111 assert(VT.getSizeInBits() == 128 && "Unexpected vector width!");
7113 SDValue Lo = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7114 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7115 DAG.getConstant(EltBits, DL, MVT::i8),
7116 DAG.getConstant(0, DL, MVT::i8)));
7117 if (isUndefInRange(Mask, NumElements/2, NumElements/2))
7118 return DAG.getNode(ISD::BITCAST, DL, VT, Lo);
7121 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64,
7122 DAG.getNode(X86ISD::EXTRQI, DL, VT, InputV,
7123 DAG.getConstant(EltBits, DL, MVT::i8),
7124 DAG.getConstant(EltBits, DL, MVT::i8)));
7125 return DAG.getNode(ISD::BITCAST, DL, VT,
7126 DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, Lo, Hi));
7129 // If this would require more than 2 unpack instructions to expand, use
7130 // pshufb when available. We can only use more than 2 unpack instructions
7131 // when zero extending i8 elements which also makes it easier to use pshufb.
7132 if (Scale > 4 && EltBits == 8 && Subtarget->hasSSSE3()) {
7133 assert(NumElements == 16 && "Unexpected byte vector width!");
7134 SDValue PSHUFBMask[16];
7135 for (int i = 0; i < 16; ++i)
7137 DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);
7138 InputV = DAG.getBitcast(MVT::v16i8, InputV);
7139 return DAG.getBitcast(VT,
7140 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,
7141 DAG.getNode(ISD::BUILD_VECTOR, DL,
7142 MVT::v16i8, PSHUFBMask)));
7145 // Otherwise emit a sequence of unpacks.
7147 MVT InputVT = MVT::getVectorVT(MVT::getIntegerVT(EltBits), NumElements);
7148 SDValue Ext = AnyExt ? DAG.getUNDEF(InputVT)
7149 : getZeroVector(InputVT, Subtarget, DAG, DL);
7150 InputV = DAG.getBitcast(InputVT, InputV);
7151 InputV = DAG.getNode(X86ISD::UNPCKL, DL, InputVT, InputV, Ext);
7155 } while (Scale > 1);
7156 return DAG.getBitcast(VT, InputV);
7159 /// \brief Try to lower a vector shuffle as a zero extension on any microarch.
7161 /// This routine will try to do everything in its power to cleverly lower
7162 /// a shuffle which happens to match the pattern of a zero extend. It doesn't
7163 /// check for the profitability of this lowering, it tries to aggressively
7164 /// match this pattern. It will use all of the micro-architectural details it
7165 /// can to emit an efficient lowering. It handles both blends with all-zero
7166 /// inputs to explicitly zero-extend and undef-lanes (sometimes undef due to
7167 /// masking out later).
7169 /// The reason we have dedicated lowering for zext-style shuffles is that they
7170 /// are both incredibly common and often quite performance sensitive.
7171 static SDValue lowerVectorShuffleAsZeroOrAnyExtend(
7172 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7173 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7174 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7176 int Bits = VT.getSizeInBits();
7177 int NumElements = VT.getVectorNumElements();
7178 assert(VT.getScalarSizeInBits() <= 32 &&
7179 "Exceeds 32-bit integer zero extension limit");
7180 assert((int)Mask.size() == NumElements && "Unexpected shuffle mask size");
7182 // Define a helper function to check a particular ext-scale and lower to it if
7184 auto Lower = [&](int Scale) -> SDValue {
7187 for (int i = 0; i < NumElements; ++i) {
7189 continue; // Valid anywhere but doesn't tell us anything.
7190 if (i % Scale != 0) {
7191 // Each of the extended elements need to be zeroable.
7195 // We no longer are in the anyext case.
7200 // Each of the base elements needs to be consecutive indices into the
7201 // same input vector.
7202 SDValue V = Mask[i] < NumElements ? V1 : V2;
7205 else if (InputV != V)
7206 return SDValue(); // Flip-flopping inputs.
7208 if (Mask[i] % NumElements != i / Scale)
7209 return SDValue(); // Non-consecutive strided elements.
7212 // If we fail to find an input, we have a zero-shuffle which should always
7213 // have already been handled.
7214 // FIXME: Maybe handle this here in case during blending we end up with one?
7218 return lowerVectorShuffleAsSpecificZeroOrAnyExtend(
7219 DL, VT, Scale, AnyExt, InputV, Mask, Subtarget, DAG);
7222 // The widest scale possible for extending is to a 64-bit integer.
7223 assert(Bits % 64 == 0 &&
7224 "The number of bits in a vector must be divisible by 64 on x86!");
7225 int NumExtElements = Bits / 64;
7227 // Each iteration, try extending the elements half as much, but into twice as
7229 for (; NumExtElements < NumElements; NumExtElements *= 2) {
7230 assert(NumElements % NumExtElements == 0 &&
7231 "The input vector size must be divisible by the extended size.");
7232 if (SDValue V = Lower(NumElements / NumExtElements))
7236 // General extends failed, but 128-bit vectors may be able to use MOVQ.
7240 // Returns one of the source operands if the shuffle can be reduced to a
7241 // MOVQ, copying the lower 64-bits and zero-extending to the upper 64-bits.
7242 auto CanZExtLowHalf = [&]() {
7243 for (int i = NumElements / 2; i != NumElements; ++i)
7246 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, 0))
7248 if (isSequentialOrUndefInRange(Mask, 0, NumElements / 2, NumElements))
7253 if (SDValue V = CanZExtLowHalf()) {
7254 V = DAG.getBitcast(MVT::v2i64, V);
7255 V = DAG.getNode(X86ISD::VZEXT_MOVL, DL, MVT::v2i64, V);
7256 return DAG.getBitcast(VT, V);
7259 // No viable ext lowering found.
7263 /// \brief Try to get a scalar value for a specific element of a vector.
7265 /// Looks through BUILD_VECTOR and SCALAR_TO_VECTOR nodes to find a scalar.
7266 static SDValue getScalarValueForVectorElement(SDValue V, int Idx,
7267 SelectionDAG &DAG) {
7268 MVT VT = V.getSimpleValueType();
7269 MVT EltVT = VT.getVectorElementType();
7270 while (V.getOpcode() == ISD::BITCAST)
7271 V = V.getOperand(0);
7272 // If the bitcasts shift the element size, we can't extract an equivalent
7274 MVT NewVT = V.getSimpleValueType();
7275 if (!NewVT.isVector() || NewVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
7278 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7279 (Idx == 0 && V.getOpcode() == ISD::SCALAR_TO_VECTOR)) {
7280 // Ensure the scalar operand is the same size as the destination.
7281 // FIXME: Add support for scalar truncation where possible.
7282 SDValue S = V.getOperand(Idx);
7283 if (EltVT.getSizeInBits() == S.getSimpleValueType().getSizeInBits())
7284 return DAG.getNode(ISD::BITCAST, SDLoc(V), EltVT, S);
7290 /// \brief Helper to test for a load that can be folded with x86 shuffles.
7292 /// This is particularly important because the set of instructions varies
7293 /// significantly based on whether the operand is a load or not.
7294 static bool isShuffleFoldableLoad(SDValue V) {
7295 while (V.getOpcode() == ISD::BITCAST)
7296 V = V.getOperand(0);
7298 return ISD::isNON_EXTLoad(V.getNode());
7301 /// \brief Try to lower insertion of a single element into a zero vector.
7303 /// This is a common pattern that we have especially efficient patterns to lower
7304 /// across all subtarget feature sets.
7305 static SDValue lowerVectorShuffleAsElementInsertion(
7306 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
7307 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
7308 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7310 MVT EltVT = VT.getVectorElementType();
7312 int V2Index = std::find_if(Mask.begin(), Mask.end(),
7313 [&Mask](int M) { return M >= (int)Mask.size(); }) -
7315 bool IsV1Zeroable = true;
7316 for (int i = 0, Size = Mask.size(); i < Size; ++i)
7317 if (i != V2Index && !Zeroable[i]) {
7318 IsV1Zeroable = false;
7322 // Check for a single input from a SCALAR_TO_VECTOR node.
7323 // FIXME: All of this should be canonicalized into INSERT_VECTOR_ELT and
7324 // all the smarts here sunk into that routine. However, the current
7325 // lowering of BUILD_VECTOR makes that nearly impossible until the old
7326 // vector shuffle lowering is dead.
7327 if (SDValue V2S = getScalarValueForVectorElement(
7328 V2, Mask[V2Index] - Mask.size(), DAG)) {
7329 // We need to zext the scalar if it is smaller than an i32.
7330 V2S = DAG.getBitcast(EltVT, V2S);
7331 if (EltVT == MVT::i8 || EltVT == MVT::i16) {
7332 // Using zext to expand a narrow element won't work for non-zero
7337 // Zero-extend directly to i32.
7339 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
7341 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);
7342 } else if (Mask[V2Index] != (int)Mask.size() || EltVT == MVT::i8 ||
7343 EltVT == MVT::i16) {
7344 // Either not inserting from the low element of the input or the input
7345 // element size is too small to use VZEXT_MOVL to clear the high bits.
7349 if (!IsV1Zeroable) {
7350 // If V1 can't be treated as a zero vector we have fewer options to lower
7351 // this. We can't support integer vectors or non-zero targets cheaply, and
7352 // the V1 elements can't be permuted in any way.
7353 assert(VT == ExtVT && "Cannot change extended type when non-zeroable!");
7354 if (!VT.isFloatingPoint() || V2Index != 0)
7356 SmallVector<int, 8> V1Mask(Mask.begin(), Mask.end());
7357 V1Mask[V2Index] = -1;
7358 if (!isNoopShuffleMask(V1Mask))
7360 // This is essentially a special case blend operation, but if we have
7361 // general purpose blend operations, they are always faster. Bail and let
7362 // the rest of the lowering handle these as blends.
7363 if (Subtarget->hasSSE41())
7366 // Otherwise, use MOVSD or MOVSS.
7367 assert((EltVT == MVT::f32 || EltVT == MVT::f64) &&
7368 "Only two types of floating point element types to handle!");
7369 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
7373 // This lowering only works for the low element with floating point vectors.
7374 if (VT.isFloatingPoint() && V2Index != 0)
7377 V2 = DAG.getNode(X86ISD::VZEXT_MOVL, DL, ExtVT, V2);
7379 V2 = DAG.getBitcast(VT, V2);
7382 // If we have 4 or fewer lanes we can cheaply shuffle the element into
7383 // the desired position. Otherwise it is more efficient to do a vector
7384 // shift left. We know that we can do a vector shift left because all
7385 // the inputs are zero.
7386 if (VT.isFloatingPoint() || VT.getVectorNumElements() <= 4) {
7387 SmallVector<int, 4> V2Shuffle(Mask.size(), 1);
7388 V2Shuffle[V2Index] = 0;
7389 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Shuffle);
7391 V2 = DAG.getBitcast(MVT::v2i64, V2);
7393 X86ISD::VSHLDQ, DL, MVT::v2i64, V2,
7395 V2Index * EltVT.getSizeInBits()/8, DL,
7396 DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));
7397 V2 = DAG.getBitcast(VT, V2);
7403 /// \brief Try to lower broadcast of a single element.
7405 /// For convenience, this code also bundles all of the subtarget feature set
7406 /// filtering. While a little annoying to re-dispatch on type here, there isn't
7407 /// a convenient way to factor it out.
7408 static SDValue lowerVectorShuffleAsBroadcast(SDLoc DL, MVT VT, SDValue V,
7410 const X86Subtarget *Subtarget,
7411 SelectionDAG &DAG) {
7412 if (!Subtarget->hasAVX())
7414 if (VT.isInteger() && !Subtarget->hasAVX2())
7417 // Check that the mask is a broadcast.
7418 int BroadcastIdx = -1;
7420 if (M >= 0 && BroadcastIdx == -1)
7422 else if (M >= 0 && M != BroadcastIdx)
7425 assert(BroadcastIdx < (int)Mask.size() && "We only expect to be called with "
7426 "a sorted mask where the broadcast "
7429 // Go up the chain of (vector) values to find a scalar load that we can
7430 // combine with the broadcast.
7432 switch (V.getOpcode()) {
7433 case ISD::CONCAT_VECTORS: {
7434 int OperandSize = Mask.size() / V.getNumOperands();
7435 V = V.getOperand(BroadcastIdx / OperandSize);
7436 BroadcastIdx %= OperandSize;
7440 case ISD::INSERT_SUBVECTOR: {
7441 SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
7442 auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
7446 int BeginIdx = (int)ConstantIdx->getZExtValue();
7448 BeginIdx + (int)VInner.getValueType().getVectorNumElements();
7449 if (BroadcastIdx >= BeginIdx && BroadcastIdx < EndIdx) {
7450 BroadcastIdx -= BeginIdx;
7461 // Check if this is a broadcast of a scalar. We special case lowering
7462 // for scalars so that we can more effectively fold with loads.
7463 if (V.getOpcode() == ISD::BUILD_VECTOR ||
7464 (V.getOpcode() == ISD::SCALAR_TO_VECTOR && BroadcastIdx == 0)) {
7465 V = V.getOperand(BroadcastIdx);
7467 // If the scalar isn't a load, we can't broadcast from it in AVX1.
7468 // Only AVX2 has register broadcasts.
7469 if (!Subtarget->hasAVX2() && !isShuffleFoldableLoad(V))
7471 } else if (BroadcastIdx != 0 || !Subtarget->hasAVX2()) {
7472 // We can't broadcast from a vector register without AVX2, and we can only
7473 // broadcast from the zero-element of a vector register.
7477 return DAG.getNode(X86ISD::VBROADCAST, DL, VT, V);
7480 // Check for whether we can use INSERTPS to perform the shuffle. We only use
7481 // INSERTPS when the V1 elements are already in the correct locations
7482 // because otherwise we can just always use two SHUFPS instructions which
7483 // are much smaller to encode than a SHUFPS and an INSERTPS. We can also
7484 // perform INSERTPS if a single V1 element is out of place and all V2
7485 // elements are zeroable.
7486 static SDValue lowerVectorShuffleAsInsertPS(SDValue Op, SDValue V1, SDValue V2,
7488 SelectionDAG &DAG) {
7489 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7490 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7491 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7492 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7494 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
7497 int V1DstIndex = -1;
7498 int V2DstIndex = -1;
7499 bool V1UsedInPlace = false;
7501 for (int i = 0; i < 4; ++i) {
7502 // Synthesize a zero mask from the zeroable elements (includes undefs).
7508 // Flag if we use any V1 inputs in place.
7510 V1UsedInPlace = true;
7514 // We can only insert a single non-zeroable element.
7515 if (V1DstIndex != -1 || V2DstIndex != -1)
7519 // V1 input out of place for insertion.
7522 // V2 input for insertion.
7527 // Don't bother if we have no (non-zeroable) element for insertion.
7528 if (V1DstIndex == -1 && V2DstIndex == -1)
7531 // Determine element insertion src/dst indices. The src index is from the
7532 // start of the inserted vector, not the start of the concatenated vector.
7533 unsigned V2SrcIndex = 0;
7534 if (V1DstIndex != -1) {
7535 // If we have a V1 input out of place, we use V1 as the V2 element insertion
7536 // and don't use the original V2 at all.
7537 V2SrcIndex = Mask[V1DstIndex];
7538 V2DstIndex = V1DstIndex;
7541 V2SrcIndex = Mask[V2DstIndex] - 4;
7544 // If no V1 inputs are used in place, then the result is created only from
7545 // the zero mask and the V2 insertion - so remove V1 dependency.
7547 V1 = DAG.getUNDEF(MVT::v4f32);
7549 unsigned InsertPSMask = V2SrcIndex << 6 | V2DstIndex << 4 | ZMask;
7550 assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");
7552 // Insert the V2 element into the desired position.
7554 return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,
7555 DAG.getConstant(InsertPSMask, DL, MVT::i8));
7558 /// \brief Try to lower a shuffle as a permute of the inputs followed by an
7559 /// UNPCK instruction.
7561 /// This specifically targets cases where we end up with alternating between
7562 /// the two inputs, and so can permute them into something that feeds a single
7563 /// UNPCK instruction. Note that this routine only targets integer vectors
7564 /// because for floating point vectors we have a generalized SHUFPS lowering
7565 /// strategy that handles everything that doesn't *exactly* match an unpack,
7566 /// making this clever lowering unnecessary.
7567 static SDValue lowerVectorShuffleAsUnpack(SDLoc DL, MVT VT, SDValue V1,
7568 SDValue V2, ArrayRef<int> Mask,
7569 SelectionDAG &DAG) {
7570 assert(!VT.isFloatingPoint() &&
7571 "This routine only supports integer vectors.");
7572 assert(!isSingleInputShuffleMask(Mask) &&
7573 "This routine should only be used when blending two inputs.");
7574 assert(Mask.size() >= 2 && "Single element masks are invalid.");
7576 int Size = Mask.size();
7578 int NumLoInputs = std::count_if(Mask.begin(), Mask.end(), [Size](int M) {
7579 return M >= 0 && M % Size < Size / 2;
7581 int NumHiInputs = std::count_if(
7582 Mask.begin(), Mask.end(), [Size](int M) { return M % Size >= Size / 2; });
7584 bool UnpackLo = NumLoInputs >= NumHiInputs;
7586 auto TryUnpack = [&](MVT UnpackVT, int Scale) {
7587 SmallVector<int, 32> V1Mask(Mask.size(), -1);
7588 SmallVector<int, 32> V2Mask(Mask.size(), -1);
7590 for (int i = 0; i < Size; ++i) {
7594 // Each element of the unpack contains Scale elements from this mask.
7595 int UnpackIdx = i / Scale;
7597 // We only handle the case where V1 feeds the first slots of the unpack.
7598 // We rely on canonicalization to ensure this is the case.
7599 if ((UnpackIdx % 2 == 0) != (Mask[i] < Size))
7602 // Setup the mask for this input. The indexing is tricky as we have to
7603 // handle the unpack stride.
7604 SmallVectorImpl<int> &VMask = (UnpackIdx % 2 == 0) ? V1Mask : V2Mask;
7605 VMask[(UnpackIdx / 2) * Scale + i % Scale + (UnpackLo ? 0 : Size / 2)] =
7609 // If we will have to shuffle both inputs to use the unpack, check whether
7610 // we can just unpack first and shuffle the result. If so, skip this unpack.
7611 if ((NumLoInputs == 0 || NumHiInputs == 0) && !isNoopShuffleMask(V1Mask) &&
7612 !isNoopShuffleMask(V2Mask))
7615 // Shuffle the inputs into place.
7616 V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
7617 V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
7619 // Cast the inputs to the type we will use to unpack them.
7620 V1 = DAG.getBitcast(UnpackVT, V1);
7621 V2 = DAG.getBitcast(UnpackVT, V2);
7623 // Unpack the inputs and cast the result back to the desired type.
7624 return DAG.getBitcast(
7625 VT, DAG.getNode(UnpackLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
7629 // We try each unpack from the largest to the smallest to try and find one
7630 // that fits this mask.
7631 int OrigNumElements = VT.getVectorNumElements();
7632 int OrigScalarSize = VT.getScalarSizeInBits();
7633 for (int ScalarSize = 64; ScalarSize >= OrigScalarSize; ScalarSize /= 2) {
7634 int Scale = ScalarSize / OrigScalarSize;
7635 int NumElements = OrigNumElements / Scale;
7636 MVT UnpackVT = MVT::getVectorVT(MVT::getIntegerVT(ScalarSize), NumElements);
7637 if (SDValue Unpack = TryUnpack(UnpackVT, Scale))
7641 // If none of the unpack-rooted lowerings worked (or were profitable) try an
7643 if (NumLoInputs == 0 || NumHiInputs == 0) {
7644 assert((NumLoInputs > 0 || NumHiInputs > 0) &&
7645 "We have to have *some* inputs!");
7646 int HalfOffset = NumLoInputs == 0 ? Size / 2 : 0;
7648 // FIXME: We could consider the total complexity of the permute of each
7649 // possible unpacking. Or at the least we should consider how many
7650 // half-crossings are created.
7651 // FIXME: We could consider commuting the unpacks.
7653 SmallVector<int, 32> PermMask;
7654 PermMask.assign(Size, -1);
7655 for (int i = 0; i < Size; ++i) {
7659 assert(Mask[i] % Size >= HalfOffset && "Found input from wrong half!");
7662 2 * ((Mask[i] % Size) - HalfOffset) + (Mask[i] < Size ? 0 : 1);
7664 return DAG.getVectorShuffle(
7665 VT, DL, DAG.getNode(NumLoInputs == 0 ? X86ISD::UNPCKH : X86ISD::UNPCKL,
7667 DAG.getUNDEF(VT), PermMask);
7673 /// \brief Handle lowering of 2-lane 64-bit floating point shuffles.
7675 /// This is the basis function for the 2-lane 64-bit shuffles as we have full
7676 /// support for floating point shuffles but not integer shuffles. These
7677 /// instructions will incur a domain crossing penalty on some chips though so
7678 /// it is better to avoid lowering through this for integer vectors where
7680 static SDValue lowerV2F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7681 const X86Subtarget *Subtarget,
7682 SelectionDAG &DAG) {
7684 assert(Op.getSimpleValueType() == MVT::v2f64 && "Bad shuffle type!");
7685 assert(V1.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7686 assert(V2.getSimpleValueType() == MVT::v2f64 && "Bad operand type!");
7687 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7688 ArrayRef<int> Mask = SVOp->getMask();
7689 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7691 if (isSingleInputShuffleMask(Mask)) {
7692 // Use low duplicate instructions for masks that match their pattern.
7693 if (Subtarget->hasSSE3())
7694 if (isShuffleEquivalent(V1, V2, Mask, {0, 0}))
7695 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v2f64, V1);
7697 // Straight shuffle of a single input vector. Simulate this by using the
7698 // single input as both of the "inputs" to this instruction..
7699 unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1);
7701 if (Subtarget->hasAVX()) {
7702 // If we have AVX, we can use VPERMILPS which will allow folding a load
7703 // into the shuffle.
7704 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,
7705 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7708 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,
7709 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7711 assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");
7712 assert(Mask[1] >= 2 && "Non-canonicalized blend!");
7714 // If we have a single input, insert that into V1 if we can do so cheaply.
7715 if ((Mask[0] >= 2) + (Mask[1] >= 2) == 1) {
7716 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7717 DL, MVT::v2f64, V1, V2, Mask, Subtarget, DAG))
7719 // Try inverting the insertion since for v2 masks it is easy to do and we
7720 // can't reliably sort the mask one way or the other.
7721 int InverseMask[2] = {Mask[0] < 0 ? -1 : (Mask[0] ^ 2),
7722 Mask[1] < 0 ? -1 : (Mask[1] ^ 2)};
7723 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7724 DL, MVT::v2f64, V2, V1, InverseMask, Subtarget, DAG))
7728 // Try to use one of the special instruction patterns to handle two common
7729 // blend patterns if a zero-blend above didn't work.
7730 if (isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
7731 isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7732 if (SDValue V1S = getScalarValueForVectorElement(V1, Mask[0], DAG))
7733 // We can either use a special instruction to load over the low double or
7734 // to move just the low double.
7736 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
7738 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64, V1S));
7740 if (Subtarget->hasSSE41())
7741 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2f64, V1, V2, Mask,
7745 // Use dedicated unpack instructions for masks that match their pattern.
7746 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7747 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2f64, V1, V2);
7748 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7749 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);
7751 unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);
7752 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,
7753 DAG.getConstant(SHUFPDMask, DL, MVT::i8));
7756 /// \brief Handle lowering of 2-lane 64-bit integer shuffles.
7758 /// Tries to lower a 2-lane 64-bit shuffle using shuffle operations provided by
7759 /// the integer unit to minimize domain crossing penalties. However, for blends
7760 /// it falls back to the floating point shuffle operation with appropriate bit
7762 static SDValue lowerV2I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7763 const X86Subtarget *Subtarget,
7764 SelectionDAG &DAG) {
7766 assert(Op.getSimpleValueType() == MVT::v2i64 && "Bad shuffle type!");
7767 assert(V1.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7768 assert(V2.getSimpleValueType() == MVT::v2i64 && "Bad operand type!");
7769 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7770 ArrayRef<int> Mask = SVOp->getMask();
7771 assert(Mask.size() == 2 && "Unexpected mask size for v2 shuffle!");
7773 if (isSingleInputShuffleMask(Mask)) {
7774 // Check for being able to broadcast a single element.
7775 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v2i64, V1,
7776 Mask, Subtarget, DAG))
7779 // Straight shuffle of a single input vector. For everything from SSE2
7780 // onward this has a single fast instruction with no scary immediates.
7781 // We have to map the mask as it is actually a v4i32 shuffle instruction.
7782 V1 = DAG.getBitcast(MVT::v4i32, V1);
7783 int WidenedMask[4] = {
7784 std::max(Mask[0], 0) * 2, std::max(Mask[0], 0) * 2 + 1,
7785 std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};
7786 return DAG.getBitcast(
7788 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
7789 getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));
7791 assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");
7792 assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");
7793 assert(Mask[0] < 2 && "We sort V1 to be the first input.");
7794 assert(Mask[1] >= 2 && "We sort V2 to be the second input.");
7796 // If we have a blend of two PACKUS operations an the blend aligns with the
7797 // low and half halves, we can just merge the PACKUS operations. This is
7798 // particularly important as it lets us merge shuffles that this routine itself
7800 auto GetPackNode = [](SDValue V) {
7801 while (V.getOpcode() == ISD::BITCAST)
7802 V = V.getOperand(0);
7804 return V.getOpcode() == X86ISD::PACKUS ? V : SDValue();
7806 if (SDValue V1Pack = GetPackNode(V1))
7807 if (SDValue V2Pack = GetPackNode(V2))
7808 return DAG.getBitcast(MVT::v2i64,
7809 DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8,
7810 Mask[0] == 0 ? V1Pack.getOperand(0)
7811 : V1Pack.getOperand(1),
7812 Mask[1] == 2 ? V2Pack.getOperand(0)
7813 : V2Pack.getOperand(1)));
7815 // Try to use shift instructions.
7817 lowerVectorShuffleAsShift(DL, MVT::v2i64, V1, V2, Mask, DAG))
7820 // When loading a scalar and then shuffling it into a vector we can often do
7821 // the insertion cheaply.
7822 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7823 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7825 // Try inverting the insertion since for v2 masks it is easy to do and we
7826 // can't reliably sort the mask one way or the other.
7827 int InverseMask[2] = {Mask[0] ^ 2, Mask[1] ^ 2};
7828 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
7829 DL, MVT::v2i64, V2, V1, InverseMask, Subtarget, DAG))
7832 // We have different paths for blend lowering, but they all must use the
7833 // *exact* same predicate.
7834 bool IsBlendSupported = Subtarget->hasSSE41();
7835 if (IsBlendSupported)
7836 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v2i64, V1, V2, Mask,
7840 // Use dedicated unpack instructions for masks that match their pattern.
7841 if (isShuffleEquivalent(V1, V2, Mask, {0, 2}))
7842 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v2i64, V1, V2);
7843 if (isShuffleEquivalent(V1, V2, Mask, {1, 3}))
7844 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2i64, V1, V2);
7846 // Try to use byte rotation instructions.
7847 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
7848 if (Subtarget->hasSSSE3())
7849 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
7850 DL, MVT::v2i64, V1, V2, Mask, Subtarget, DAG))
7853 // If we have direct support for blends, we should lower by decomposing into
7854 // a permute. That will be faster than the domain cross.
7855 if (IsBlendSupported)
7856 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v2i64, V1, V2,
7859 // We implement this with SHUFPD which is pretty lame because it will likely
7860 // incur 2 cycles of stall for integer vectors on Nehalem and older chips.
7861 // However, all the alternatives are still more cycles and newer chips don't
7862 // have this problem. It would be really nice if x86 had better shuffles here.
7863 V1 = DAG.getBitcast(MVT::v2f64, V1);
7864 V2 = DAG.getBitcast(MVT::v2f64, V2);
7865 return DAG.getBitcast(MVT::v2i64,
7866 DAG.getVectorShuffle(MVT::v2f64, DL, V1, V2, Mask));
7869 /// \brief Test whether this can be lowered with a single SHUFPS instruction.
7871 /// This is used to disable more specialized lowerings when the shufps lowering
7872 /// will happen to be efficient.
7873 static bool isSingleSHUFPSMask(ArrayRef<int> Mask) {
7874 // This routine only handles 128-bit shufps.
7875 assert(Mask.size() == 4 && "Unsupported mask size!");
7877 // To lower with a single SHUFPS we need to have the low half and high half
7878 // each requiring a single input.
7879 if (Mask[0] != -1 && Mask[1] != -1 && (Mask[0] < 4) != (Mask[1] < 4))
7881 if (Mask[2] != -1 && Mask[3] != -1 && (Mask[2] < 4) != (Mask[3] < 4))
7887 /// \brief Lower a vector shuffle using the SHUFPS instruction.
7889 /// This is a helper routine dedicated to lowering vector shuffles using SHUFPS.
7890 /// It makes no assumptions about whether this is the *best* lowering, it simply
7892 static SDValue lowerVectorShuffleWithSHUFPS(SDLoc DL, MVT VT,
7893 ArrayRef<int> Mask, SDValue V1,
7894 SDValue V2, SelectionDAG &DAG) {
7895 SDValue LowV = V1, HighV = V2;
7896 int NewMask[4] = {Mask[0], Mask[1], Mask[2], Mask[3]};
7899 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7901 if (NumV2Elements == 1) {
7903 std::find_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; }) -
7906 // Compute the index adjacent to V2Index and in the same half by toggling
7908 int V2AdjIndex = V2Index ^ 1;
7910 if (Mask[V2AdjIndex] == -1) {
7911 // Handles all the cases where we have a single V2 element and an undef.
7912 // This will only ever happen in the high lanes because we commute the
7913 // vector otherwise.
7915 std::swap(LowV, HighV);
7916 NewMask[V2Index] -= 4;
7918 // Handle the case where the V2 element ends up adjacent to a V1 element.
7919 // To make this work, blend them together as the first step.
7920 int V1Index = V2AdjIndex;
7921 int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};
7922 V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
7923 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7925 // Now proceed to reconstruct the final blend as we have the necessary
7926 // high or low half formed.
7933 NewMask[V1Index] = 2; // We put the V1 element in V2[2].
7934 NewMask[V2Index] = 0; // We shifted the V2 element into V2[0].
7936 } else if (NumV2Elements == 2) {
7937 if (Mask[0] < 4 && Mask[1] < 4) {
7938 // Handle the easy case where we have V1 in the low lanes and V2 in the
7942 } else if (Mask[2] < 4 && Mask[3] < 4) {
7943 // We also handle the reversed case because this utility may get called
7944 // when we detect a SHUFPS pattern but can't easily commute the shuffle to
7945 // arrange things in the right direction.
7951 // We have a mixture of V1 and V2 in both low and high lanes. Rather than
7952 // trying to place elements directly, just blend them and set up the final
7953 // shuffle to place them.
7955 // The first two blend mask elements are for V1, the second two are for
7957 int BlendMask[4] = {Mask[0] < 4 ? Mask[0] : Mask[1],
7958 Mask[2] < 4 ? Mask[2] : Mask[3],
7959 (Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,
7960 (Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};
7961 V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
7962 getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));
7964 // Now we do a normal shuffle of V1 by giving V1 as both operands to
7967 NewMask[0] = Mask[0] < 4 ? 0 : 2;
7968 NewMask[1] = Mask[0] < 4 ? 2 : 0;
7969 NewMask[2] = Mask[2] < 4 ? 1 : 3;
7970 NewMask[3] = Mask[2] < 4 ? 3 : 1;
7973 return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,
7974 getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));
7977 /// \brief Lower 4-lane 32-bit floating point shuffles.
7979 /// Uses instructions exclusively from the floating point unit to minimize
7980 /// domain crossing penalties, as these are sufficient to implement all v4f32
7982 static SDValue lowerV4F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
7983 const X86Subtarget *Subtarget,
7984 SelectionDAG &DAG) {
7986 assert(Op.getSimpleValueType() == MVT::v4f32 && "Bad shuffle type!");
7987 assert(V1.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7988 assert(V2.getSimpleValueType() == MVT::v4f32 && "Bad operand type!");
7989 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7990 ArrayRef<int> Mask = SVOp->getMask();
7991 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
7994 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
7996 if (NumV2Elements == 0) {
7997 // Check for being able to broadcast a single element.
7998 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f32, V1,
7999 Mask, Subtarget, DAG))
8002 // Use even/odd duplicate instructions for masks that match their pattern.
8003 if (Subtarget->hasSSE3()) {
8004 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
8005 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v4f32, V1);
8006 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3}))
8007 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v4f32, V1);
8010 if (Subtarget->hasAVX()) {
8011 // If we have AVX, we can use VPERMILPS which will allow folding a load
8012 // into the shuffle.
8013 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,
8014 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8017 // Otherwise, use a straight shuffle of a single input vector. We pass the
8018 // input vector to both operands to simulate this with a SHUFPS.
8019 return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,
8020 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8023 // There are special ways we can lower some single-element blends. However, we
8024 // have custom ways we can lower more complex single-element blends below that
8025 // we defer to if both this and BLENDPS fail to match, so restrict this to
8026 // when the V2 input is targeting element 0 of the mask -- that is the fast
8028 if (NumV2Elements == 1 && Mask[0] >= 4)
8029 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4f32, V1, V2,
8030 Mask, Subtarget, DAG))
8033 if (Subtarget->hasSSE41()) {
8034 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f32, V1, V2, Mask,
8038 // Use INSERTPS if we can complete the shuffle efficiently.
8039 if (SDValue V = lowerVectorShuffleAsInsertPS(Op, V1, V2, Mask, DAG))
8042 if (!isSingleSHUFPSMask(Mask))
8043 if (SDValue BlendPerm = lowerVectorShuffleAsBlendAndPermute(
8044 DL, MVT::v4f32, V1, V2, Mask, DAG))
8048 // Use dedicated unpack instructions for masks that match their pattern.
8049 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8050 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V1, V2);
8051 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8052 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V1, V2);
8053 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8054 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f32, V2, V1);
8055 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8056 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f32, V2, V1);
8058 // Otherwise fall back to a SHUFPS lowering strategy.
8059 return lowerVectorShuffleWithSHUFPS(DL, MVT::v4f32, Mask, V1, V2, DAG);
8062 /// \brief Lower 4-lane i32 vector shuffles.
8064 /// We try to handle these with integer-domain shuffles where we can, but for
8065 /// blends we use the floating point domain blend instructions.
8066 static SDValue lowerV4I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8067 const X86Subtarget *Subtarget,
8068 SelectionDAG &DAG) {
8070 assert(Op.getSimpleValueType() == MVT::v4i32 && "Bad shuffle type!");
8071 assert(V1.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8072 assert(V2.getSimpleValueType() == MVT::v4i32 && "Bad operand type!");
8073 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8074 ArrayRef<int> Mask = SVOp->getMask();
8075 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
8077 // Whenever we can lower this as a zext, that instruction is strictly faster
8078 // than any alternative. It also allows us to fold memory operands into the
8079 // shuffle in many cases.
8080 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v4i32, V1, V2,
8081 Mask, Subtarget, DAG))
8085 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 4; });
8087 if (NumV2Elements == 0) {
8088 // Check for being able to broadcast a single element.
8089 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i32, V1,
8090 Mask, Subtarget, DAG))
8093 // Straight shuffle of a single input vector. For everything from SSE2
8094 // onward this has a single fast instruction with no scary immediates.
8095 // We coerce the shuffle pattern to be compatible with UNPCK instructions
8096 // but we aren't actually going to use the UNPCK instruction because doing
8097 // so prevents folding a load into this instruction or making a copy.
8098 const int UnpackLoMask[] = {0, 0, 1, 1};
8099 const int UnpackHiMask[] = {2, 2, 3, 3};
8100 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 1, 1}))
8101 Mask = UnpackLoMask;
8102 else if (isShuffleEquivalent(V1, V2, Mask, {2, 2, 3, 3}))
8103 Mask = UnpackHiMask;
8105 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,
8106 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
8109 // Try to use shift instructions.
8111 lowerVectorShuffleAsShift(DL, MVT::v4i32, V1, V2, Mask, DAG))
8114 // There are special ways we can lower some single-element blends.
8115 if (NumV2Elements == 1)
8116 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v4i32, V1, V2,
8117 Mask, Subtarget, DAG))
8120 // We have different paths for blend lowering, but they all must use the
8121 // *exact* same predicate.
8122 bool IsBlendSupported = Subtarget->hasSSE41();
8123 if (IsBlendSupported)
8124 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i32, V1, V2, Mask,
8128 if (SDValue Masked =
8129 lowerVectorShuffleAsBitMask(DL, MVT::v4i32, V1, V2, Mask, DAG))
8132 // Use dedicated unpack instructions for masks that match their pattern.
8133 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 1, 5}))
8134 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V1, V2);
8135 if (isShuffleEquivalent(V1, V2, Mask, {2, 6, 3, 7}))
8136 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V1, V2);
8137 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 5, 1}))
8138 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i32, V2, V1);
8139 if (isShuffleEquivalent(V1, V2, Mask, {6, 2, 7, 3}))
8140 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i32, V2, V1);
8142 // Try to use byte rotation instructions.
8143 // Its more profitable for pre-SSSE3 to use shuffles/unpacks.
8144 if (Subtarget->hasSSSE3())
8145 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8146 DL, MVT::v4i32, V1, V2, Mask, Subtarget, DAG))
8149 // If we have direct support for blends, we should lower by decomposing into
8150 // a permute. That will be faster than the domain cross.
8151 if (IsBlendSupported)
8152 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i32, V1, V2,
8155 // Try to lower by permuting the inputs into an unpack instruction.
8156 if (SDValue Unpack =
8157 lowerVectorShuffleAsUnpack(DL, MVT::v4i32, V1, V2, Mask, DAG))
8160 // We implement this with SHUFPS because it can blend from two vectors.
8161 // Because we're going to eventually use SHUFPS, we use SHUFPS even to build
8162 // up the inputs, bypassing domain shift penalties that we would encur if we
8163 // directly used PSHUFD on Nehalem and older. For newer chips, this isn't
8165 return DAG.getBitcast(
8167 DAG.getVectorShuffle(MVT::v4f32, DL, DAG.getBitcast(MVT::v4f32, V1),
8168 DAG.getBitcast(MVT::v4f32, V2), Mask));
8171 /// \brief Lowering of single-input v8i16 shuffles is the cornerstone of SSE2
8172 /// shuffle lowering, and the most complex part.
8174 /// The lowering strategy is to try to form pairs of input lanes which are
8175 /// targeted at the same half of the final vector, and then use a dword shuffle
8176 /// to place them onto the right half, and finally unpack the paired lanes into
8177 /// their final position.
8179 /// The exact breakdown of how to form these dword pairs and align them on the
8180 /// correct sides is really tricky. See the comments within the function for
8181 /// more of the details.
8183 /// This code also handles repeated 128-bit lanes of v8i16 shuffles, but each
8184 /// lane must shuffle the *exact* same way. In fact, you must pass a v8 Mask to
8185 /// this routine for it to work correctly. To shuffle a 256-bit or 512-bit i16
8186 /// vector, form the analogous 128-bit 8-element Mask.
8187 static SDValue lowerV8I16GeneralSingleInputVectorShuffle(
8188 SDLoc DL, MVT VT, SDValue V, MutableArrayRef<int> Mask,
8189 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
8190 assert(VT.getScalarType() == MVT::i16 && "Bad input type!");
8191 MVT PSHUFDVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
8193 assert(Mask.size() == 8 && "Shuffle mask length doen't match!");
8194 MutableArrayRef<int> LoMask = Mask.slice(0, 4);
8195 MutableArrayRef<int> HiMask = Mask.slice(4, 4);
8197 SmallVector<int, 4> LoInputs;
8198 std::copy_if(LoMask.begin(), LoMask.end(), std::back_inserter(LoInputs),
8199 [](int M) { return M >= 0; });
8200 std::sort(LoInputs.begin(), LoInputs.end());
8201 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()), LoInputs.end());
8202 SmallVector<int, 4> HiInputs;
8203 std::copy_if(HiMask.begin(), HiMask.end(), std::back_inserter(HiInputs),
8204 [](int M) { return M >= 0; });
8205 std::sort(HiInputs.begin(), HiInputs.end());
8206 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()), HiInputs.end());
8208 std::lower_bound(LoInputs.begin(), LoInputs.end(), 4) - LoInputs.begin();
8209 int NumHToL = LoInputs.size() - NumLToL;
8211 std::lower_bound(HiInputs.begin(), HiInputs.end(), 4) - HiInputs.begin();
8212 int NumHToH = HiInputs.size() - NumLToH;
8213 MutableArrayRef<int> LToLInputs(LoInputs.data(), NumLToL);
8214 MutableArrayRef<int> LToHInputs(HiInputs.data(), NumLToH);
8215 MutableArrayRef<int> HToLInputs(LoInputs.data() + NumLToL, NumHToL);
8216 MutableArrayRef<int> HToHInputs(HiInputs.data() + NumLToH, NumHToH);
8218 // Simplify the 1-into-3 and 3-into-1 cases with a single pshufd. For all
8219 // such inputs we can swap two of the dwords across the half mark and end up
8220 // with <=2 inputs to each half in each half. Once there, we can fall through
8221 // to the generic code below. For example:
8223 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8224 // Mask: [0, 1, 2, 7, 4, 5, 6, 3] -----------------> [0, 1, 4, 7, 2, 3, 6, 5]
8226 // However in some very rare cases we have a 1-into-3 or 3-into-1 on one half
8227 // and an existing 2-into-2 on the other half. In this case we may have to
8228 // pre-shuffle the 2-into-2 half to avoid turning it into a 3-into-1 or
8229 // 1-into-3 which could cause us to cycle endlessly fixing each side in turn.
8230 // Fortunately, we don't have to handle anything but a 2-into-2 pattern
8231 // because any other situation (including a 3-into-1 or 1-into-3 in the other
8232 // half than the one we target for fixing) will be fixed when we re-enter this
8233 // path. We will also combine away any sequence of PSHUFD instructions that
8234 // result into a single instruction. Here is an example of the tricky case:
8236 // Input: [a, b, c, d, e, f, g, h] -PSHUFD[0,2,1,3]-> [a, b, e, f, c, d, g, h]
8237 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -THIS-IS-BAD!!!!-> [5, 7, 1, 0, 4, 7, 5, 3]
8239 // This now has a 1-into-3 in the high half! Instead, we do two shuffles:
8241 // Input: [a, b, c, d, e, f, g, h] PSHUFHW[0,2,1,3]-> [a, b, c, d, e, g, f, h]
8242 // Mask: [3, 7, 1, 0, 2, 7, 3, 5] -----------------> [3, 7, 1, 0, 2, 7, 3, 6]
8244 // Input: [a, b, c, d, e, g, f, h] -PSHUFD[0,2,1,3]-> [a, b, e, g, c, d, f, h]
8245 // Mask: [3, 7, 1, 0, 2, 7, 3, 6] -----------------> [5, 7, 1, 0, 4, 7, 5, 6]
8247 // The result is fine to be handled by the generic logic.
8248 auto balanceSides = [&](ArrayRef<int> AToAInputs, ArrayRef<int> BToAInputs,
8249 ArrayRef<int> BToBInputs, ArrayRef<int> AToBInputs,
8250 int AOffset, int BOffset) {
8251 assert((AToAInputs.size() == 3 || AToAInputs.size() == 1) &&
8252 "Must call this with A having 3 or 1 inputs from the A half.");
8253 assert((BToAInputs.size() == 1 || BToAInputs.size() == 3) &&
8254 "Must call this with B having 1 or 3 inputs from the B half.");
8255 assert(AToAInputs.size() + BToAInputs.size() == 4 &&
8256 "Must call this with either 3:1 or 1:3 inputs (summing to 4).");
8258 // Compute the index of dword with only one word among the three inputs in
8259 // a half by taking the sum of the half with three inputs and subtracting
8260 // the sum of the actual three inputs. The difference is the remaining
8263 int &TripleDWord = AToAInputs.size() == 3 ? ADWord : BDWord;
8264 int &OneInputDWord = AToAInputs.size() == 3 ? BDWord : ADWord;
8265 int TripleInputOffset = AToAInputs.size() == 3 ? AOffset : BOffset;
8266 ArrayRef<int> TripleInputs = AToAInputs.size() == 3 ? AToAInputs : BToAInputs;
8267 int OneInput = AToAInputs.size() == 3 ? BToAInputs[0] : AToAInputs[0];
8268 int TripleInputSum = 0 + 1 + 2 + 3 + (4 * TripleInputOffset);
8269 int TripleNonInputIdx =
8270 TripleInputSum - std::accumulate(TripleInputs.begin(), TripleInputs.end(), 0);
8271 TripleDWord = TripleNonInputIdx / 2;
8273 // We use xor with one to compute the adjacent DWord to whichever one the
8275 OneInputDWord = (OneInput / 2) ^ 1;
8277 // Check for one tricky case: We're fixing a 3<-1 or a 1<-3 shuffle for AToA
8278 // and BToA inputs. If there is also such a problem with the BToB and AToB
8279 // inputs, we don't try to fix it necessarily -- we'll recurse and see it in
8280 // the next pass. However, if we have a 2<-2 in the BToB and AToB inputs, it
8281 // is essential that we don't *create* a 3<-1 as then we might oscillate.
8282 if (BToBInputs.size() == 2 && AToBInputs.size() == 2) {
8283 // Compute how many inputs will be flipped by swapping these DWords. We
8285 // to balance this to ensure we don't form a 3-1 shuffle in the other
8287 int NumFlippedAToBInputs =
8288 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) +
8289 std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1);
8290 int NumFlippedBToBInputs =
8291 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) +
8292 std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1);
8293 if ((NumFlippedAToBInputs == 1 &&
8294 (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) ||
8295 (NumFlippedBToBInputs == 1 &&
8296 (NumFlippedAToBInputs == 0 || NumFlippedAToBInputs == 2))) {
8297 // We choose whether to fix the A half or B half based on whether that
8298 // half has zero flipped inputs. At zero, we may not be able to fix it
8299 // with that half. We also bias towards fixing the B half because that
8300 // will more commonly be the high half, and we have to bias one way.
8301 auto FixFlippedInputs = [&V, &DL, &Mask, &DAG](int PinnedIdx, int DWord,
8302 ArrayRef<int> Inputs) {
8303 int FixIdx = PinnedIdx ^ 1; // The adjacent slot to the pinned slot.
8304 bool IsFixIdxInput = std::find(Inputs.begin(), Inputs.end(),
8305 PinnedIdx ^ 1) != Inputs.end();
8306 // Determine whether the free index is in the flipped dword or the
8307 // unflipped dword based on where the pinned index is. We use this bit
8308 // in an xor to conditionally select the adjacent dword.
8309 int FixFreeIdx = 2 * (DWord ^ (PinnedIdx / 2 == DWord));
8310 bool IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8311 FixFreeIdx) != Inputs.end();
8312 if (IsFixIdxInput == IsFixFreeIdxInput)
8314 IsFixFreeIdxInput = std::find(Inputs.begin(), Inputs.end(),
8315 FixFreeIdx) != Inputs.end();
8316 assert(IsFixIdxInput != IsFixFreeIdxInput &&
8317 "We need to be changing the number of flipped inputs!");
8318 int PSHUFHalfMask[] = {0, 1, 2, 3};
8319 std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);
8320 V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,
8322 getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));
8325 if (M != -1 && M == FixIdx)
8327 else if (M != -1 && M == FixFreeIdx)
8330 if (NumFlippedBToBInputs != 0) {
8332 BToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8333 FixFlippedInputs(BPinnedIdx, BDWord, BToBInputs);
8335 assert(NumFlippedAToBInputs != 0 && "Impossible given predicates!");
8337 AToAInputs.size() == 3 ? TripleNonInputIdx : OneInput;
8338 FixFlippedInputs(APinnedIdx, ADWord, AToBInputs);
8343 int PSHUFDMask[] = {0, 1, 2, 3};
8344 PSHUFDMask[ADWord] = BDWord;
8345 PSHUFDMask[BDWord] = ADWord;
8348 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8349 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8351 // Adjust the mask to match the new locations of A and B.
8353 if (M != -1 && M/2 == ADWord)
8354 M = 2 * BDWord + M % 2;
8355 else if (M != -1 && M/2 == BDWord)
8356 M = 2 * ADWord + M % 2;
8358 // Recurse back into this routine to re-compute state now that this isn't
8359 // a 3 and 1 problem.
8360 return lowerV8I16GeneralSingleInputVectorShuffle(DL, VT, V, Mask, Subtarget,
8363 if ((NumLToL == 3 && NumHToL == 1) || (NumLToL == 1 && NumHToL == 3))
8364 return balanceSides(LToLInputs, HToLInputs, HToHInputs, LToHInputs, 0, 4);
8365 else if ((NumHToH == 3 && NumLToH == 1) || (NumHToH == 1 && NumLToH == 3))
8366 return balanceSides(HToHInputs, LToHInputs, LToLInputs, HToLInputs, 4, 0);
8368 // At this point there are at most two inputs to the low and high halves from
8369 // each half. That means the inputs can always be grouped into dwords and
8370 // those dwords can then be moved to the correct half with a dword shuffle.
8371 // We use at most one low and one high word shuffle to collect these paired
8372 // inputs into dwords, and finally a dword shuffle to place them.
8373 int PSHUFLMask[4] = {-1, -1, -1, -1};
8374 int PSHUFHMask[4] = {-1, -1, -1, -1};
8375 int PSHUFDMask[4] = {-1, -1, -1, -1};
8377 // First fix the masks for all the inputs that are staying in their
8378 // original halves. This will then dictate the targets of the cross-half
8380 auto fixInPlaceInputs =
8381 [&PSHUFDMask](ArrayRef<int> InPlaceInputs, ArrayRef<int> IncomingInputs,
8382 MutableArrayRef<int> SourceHalfMask,
8383 MutableArrayRef<int> HalfMask, int HalfOffset) {
8384 if (InPlaceInputs.empty())
8386 if (InPlaceInputs.size() == 1) {
8387 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8388 InPlaceInputs[0] - HalfOffset;
8389 PSHUFDMask[InPlaceInputs[0] / 2] = InPlaceInputs[0] / 2;
8392 if (IncomingInputs.empty()) {
8393 // Just fix all of the in place inputs.
8394 for (int Input : InPlaceInputs) {
8395 SourceHalfMask[Input - HalfOffset] = Input - HalfOffset;
8396 PSHUFDMask[Input / 2] = Input / 2;
8401 assert(InPlaceInputs.size() == 2 && "Cannot handle 3 or 4 inputs!");
8402 SourceHalfMask[InPlaceInputs[0] - HalfOffset] =
8403 InPlaceInputs[0] - HalfOffset;
8404 // Put the second input next to the first so that they are packed into
8405 // a dword. We find the adjacent index by toggling the low bit.
8406 int AdjIndex = InPlaceInputs[0] ^ 1;
8407 SourceHalfMask[AdjIndex - HalfOffset] = InPlaceInputs[1] - HalfOffset;
8408 std::replace(HalfMask.begin(), HalfMask.end(), InPlaceInputs[1], AdjIndex);
8409 PSHUFDMask[AdjIndex / 2] = AdjIndex / 2;
8411 fixInPlaceInputs(LToLInputs, HToLInputs, PSHUFLMask, LoMask, 0);
8412 fixInPlaceInputs(HToHInputs, LToHInputs, PSHUFHMask, HiMask, 4);
8414 // Now gather the cross-half inputs and place them into a free dword of
8415 // their target half.
8416 // FIXME: This operation could almost certainly be simplified dramatically to
8417 // look more like the 3-1 fixing operation.
8418 auto moveInputsToRightHalf = [&PSHUFDMask](
8419 MutableArrayRef<int> IncomingInputs, ArrayRef<int> ExistingInputs,
8420 MutableArrayRef<int> SourceHalfMask, MutableArrayRef<int> HalfMask,
8421 MutableArrayRef<int> FinalSourceHalfMask, int SourceOffset,
8423 auto isWordClobbered = [](ArrayRef<int> SourceHalfMask, int Word) {
8424 return SourceHalfMask[Word] != -1 && SourceHalfMask[Word] != Word;
8426 auto isDWordClobbered = [&isWordClobbered](ArrayRef<int> SourceHalfMask,
8428 int LowWord = Word & ~1;
8429 int HighWord = Word | 1;
8430 return isWordClobbered(SourceHalfMask, LowWord) ||
8431 isWordClobbered(SourceHalfMask, HighWord);
8434 if (IncomingInputs.empty())
8437 if (ExistingInputs.empty()) {
8438 // Map any dwords with inputs from them into the right half.
8439 for (int Input : IncomingInputs) {
8440 // If the source half mask maps over the inputs, turn those into
8441 // swaps and use the swapped lane.
8442 if (isWordClobbered(SourceHalfMask, Input - SourceOffset)) {
8443 if (SourceHalfMask[SourceHalfMask[Input - SourceOffset]] == -1) {
8444 SourceHalfMask[SourceHalfMask[Input - SourceOffset]] =
8445 Input - SourceOffset;
8446 // We have to swap the uses in our half mask in one sweep.
8447 for (int &M : HalfMask)
8448 if (M == SourceHalfMask[Input - SourceOffset] + SourceOffset)
8450 else if (M == Input)
8451 M = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8453 assert(SourceHalfMask[SourceHalfMask[Input - SourceOffset]] ==
8454 Input - SourceOffset &&
8455 "Previous placement doesn't match!");
8457 // Note that this correctly re-maps both when we do a swap and when
8458 // we observe the other side of the swap above. We rely on that to
8459 // avoid swapping the members of the input list directly.
8460 Input = SourceHalfMask[Input - SourceOffset] + SourceOffset;
8463 // Map the input's dword into the correct half.
8464 if (PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] == -1)
8465 PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] = Input / 2;
8467 assert(PSHUFDMask[(Input - SourceOffset + DestOffset) / 2] ==
8469 "Previous placement doesn't match!");
8472 // And just directly shift any other-half mask elements to be same-half
8473 // as we will have mirrored the dword containing the element into the
8474 // same position within that half.
8475 for (int &M : HalfMask)
8476 if (M >= SourceOffset && M < SourceOffset + 4) {
8477 M = M - SourceOffset + DestOffset;
8478 assert(M >= 0 && "This should never wrap below zero!");
8483 // Ensure we have the input in a viable dword of its current half. This
8484 // is particularly tricky because the original position may be clobbered
8485 // by inputs being moved and *staying* in that half.
8486 if (IncomingInputs.size() == 1) {
8487 if (isWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8488 int InputFixed = std::find(std::begin(SourceHalfMask),
8489 std::end(SourceHalfMask), -1) -
8490 std::begin(SourceHalfMask) + SourceOffset;
8491 SourceHalfMask[InputFixed - SourceOffset] =
8492 IncomingInputs[0] - SourceOffset;
8493 std::replace(HalfMask.begin(), HalfMask.end(), IncomingInputs[0],
8495 IncomingInputs[0] = InputFixed;
8497 } else if (IncomingInputs.size() == 2) {
8498 if (IncomingInputs[0] / 2 != IncomingInputs[1] / 2 ||
8499 isDWordClobbered(SourceHalfMask, IncomingInputs[0] - SourceOffset)) {
8500 // We have two non-adjacent or clobbered inputs we need to extract from
8501 // the source half. To do this, we need to map them into some adjacent
8502 // dword slot in the source mask.
8503 int InputsFixed[2] = {IncomingInputs[0] - SourceOffset,
8504 IncomingInputs[1] - SourceOffset};
8506 // If there is a free slot in the source half mask adjacent to one of
8507 // the inputs, place the other input in it. We use (Index XOR 1) to
8508 // compute an adjacent index.
8509 if (!isWordClobbered(SourceHalfMask, InputsFixed[0]) &&
8510 SourceHalfMask[InputsFixed[0] ^ 1] == -1) {
8511 SourceHalfMask[InputsFixed[0]] = InputsFixed[0];
8512 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8513 InputsFixed[1] = InputsFixed[0] ^ 1;
8514 } else if (!isWordClobbered(SourceHalfMask, InputsFixed[1]) &&
8515 SourceHalfMask[InputsFixed[1] ^ 1] == -1) {
8516 SourceHalfMask[InputsFixed[1]] = InputsFixed[1];
8517 SourceHalfMask[InputsFixed[1] ^ 1] = InputsFixed[0];
8518 InputsFixed[0] = InputsFixed[1] ^ 1;
8519 } else if (SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] == -1 &&
8520 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] == -1) {
8521 // The two inputs are in the same DWord but it is clobbered and the
8522 // adjacent DWord isn't used at all. Move both inputs to the free
8524 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1)] = InputsFixed[0];
8525 SourceHalfMask[2 * ((InputsFixed[0] / 2) ^ 1) + 1] = InputsFixed[1];
8526 InputsFixed[0] = 2 * ((InputsFixed[0] / 2) ^ 1);
8527 InputsFixed[1] = 2 * ((InputsFixed[0] / 2) ^ 1) + 1;
8529 // The only way we hit this point is if there is no clobbering
8530 // (because there are no off-half inputs to this half) and there is no
8531 // free slot adjacent to one of the inputs. In this case, we have to
8532 // swap an input with a non-input.
8533 for (int i = 0; i < 4; ++i)
8534 assert((SourceHalfMask[i] == -1 || SourceHalfMask[i] == i) &&
8535 "We can't handle any clobbers here!");
8536 assert(InputsFixed[1] != (InputsFixed[0] ^ 1) &&
8537 "Cannot have adjacent inputs here!");
8539 SourceHalfMask[InputsFixed[0] ^ 1] = InputsFixed[1];
8540 SourceHalfMask[InputsFixed[1]] = InputsFixed[0] ^ 1;
8542 // We also have to update the final source mask in this case because
8543 // it may need to undo the above swap.
8544 for (int &M : FinalSourceHalfMask)
8545 if (M == (InputsFixed[0] ^ 1) + SourceOffset)
8546 M = InputsFixed[1] + SourceOffset;
8547 else if (M == InputsFixed[1] + SourceOffset)
8548 M = (InputsFixed[0] ^ 1) + SourceOffset;
8550 InputsFixed[1] = InputsFixed[0] ^ 1;
8553 // Point everything at the fixed inputs.
8554 for (int &M : HalfMask)
8555 if (M == IncomingInputs[0])
8556 M = InputsFixed[0] + SourceOffset;
8557 else if (M == IncomingInputs[1])
8558 M = InputsFixed[1] + SourceOffset;
8560 IncomingInputs[0] = InputsFixed[0] + SourceOffset;
8561 IncomingInputs[1] = InputsFixed[1] + SourceOffset;
8564 llvm_unreachable("Unhandled input size!");
8567 // Now hoist the DWord down to the right half.
8568 int FreeDWord = (PSHUFDMask[DestOffset / 2] == -1 ? 0 : 1) + DestOffset / 2;
8569 assert(PSHUFDMask[FreeDWord] == -1 && "DWord not free");
8570 PSHUFDMask[FreeDWord] = IncomingInputs[0] / 2;
8571 for (int &M : HalfMask)
8572 for (int Input : IncomingInputs)
8574 M = FreeDWord * 2 + Input % 2;
8576 moveInputsToRightHalf(HToLInputs, LToLInputs, PSHUFHMask, LoMask, HiMask,
8577 /*SourceOffset*/ 4, /*DestOffset*/ 0);
8578 moveInputsToRightHalf(LToHInputs, HToHInputs, PSHUFLMask, HiMask, LoMask,
8579 /*SourceOffset*/ 0, /*DestOffset*/ 4);
8581 // Now enact all the shuffles we've computed to move the inputs into their
8583 if (!isNoopShuffleMask(PSHUFLMask))
8584 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8585 getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));
8586 if (!isNoopShuffleMask(PSHUFHMask))
8587 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8588 getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));
8589 if (!isNoopShuffleMask(PSHUFDMask))
8592 DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT, DAG.getBitcast(PSHUFDVT, V),
8593 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
8595 // At this point, each half should contain all its inputs, and we can then
8596 // just shuffle them into their final position.
8597 assert(std::count_if(LoMask.begin(), LoMask.end(),
8598 [](int M) { return M >= 4; }) == 0 &&
8599 "Failed to lift all the high half inputs to the low mask!");
8600 assert(std::count_if(HiMask.begin(), HiMask.end(),
8601 [](int M) { return M >= 0 && M < 4; }) == 0 &&
8602 "Failed to lift all the low half inputs to the high mask!");
8604 // Do a half shuffle for the low mask.
8605 if (!isNoopShuffleMask(LoMask))
8606 V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,
8607 getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));
8609 // Do a half shuffle with the high mask after shifting its values down.
8610 for (int &M : HiMask)
8613 if (!isNoopShuffleMask(HiMask))
8614 V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,
8615 getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));
8620 /// \brief Helper to form a PSHUFB-based shuffle+blend.
8621 static SDValue lowerVectorShuffleAsPSHUFB(SDLoc DL, MVT VT, SDValue V1,
8622 SDValue V2, ArrayRef<int> Mask,
8623 SelectionDAG &DAG, bool &V1InUse,
8625 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
8631 int Size = Mask.size();
8632 int Scale = 16 / Size;
8633 for (int i = 0; i < 16; ++i) {
8634 if (Mask[i / Scale] == -1) {
8635 V1Mask[i] = V2Mask[i] = DAG.getUNDEF(MVT::i8);
8637 const int ZeroMask = 0x80;
8638 int V1Idx = Mask[i / Scale] < Size ? Mask[i / Scale] * Scale + i % Scale
8640 int V2Idx = Mask[i / Scale] < Size
8642 : (Mask[i / Scale] - Size) * Scale + i % Scale;
8643 if (Zeroable[i / Scale])
8644 V1Idx = V2Idx = ZeroMask;
8645 V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);
8646 V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);
8647 V1InUse |= (ZeroMask != V1Idx);
8648 V2InUse |= (ZeroMask != V2Idx);
8653 V1 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8654 DAG.getBitcast(MVT::v16i8, V1),
8655 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask));
8657 V2 = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8,
8658 DAG.getBitcast(MVT::v16i8, V2),
8659 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask));
8661 // If we need shuffled inputs from both, blend the two.
8663 if (V1InUse && V2InUse)
8664 V = DAG.getNode(ISD::OR, DL, MVT::v16i8, V1, V2);
8666 V = V1InUse ? V1 : V2;
8668 // Cast the result back to the correct type.
8669 return DAG.getBitcast(VT, V);
8672 /// \brief Generic lowering of 8-lane i16 shuffles.
8674 /// This handles both single-input shuffles and combined shuffle/blends with
8675 /// two inputs. The single input shuffles are immediately delegated to
8676 /// a dedicated lowering routine.
8678 /// The blends are lowered in one of three fundamental ways. If there are few
8679 /// enough inputs, it delegates to a basic UNPCK-based strategy. If the shuffle
8680 /// of the input is significantly cheaper when lowered as an interleaving of
8681 /// the two inputs, try to interleave them. Otherwise, blend the low and high
8682 /// halves of the inputs separately (making them have relatively few inputs)
8683 /// and then concatenate them.
8684 static SDValue lowerV8I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8685 const X86Subtarget *Subtarget,
8686 SelectionDAG &DAG) {
8688 assert(Op.getSimpleValueType() == MVT::v8i16 && "Bad shuffle type!");
8689 assert(V1.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8690 assert(V2.getSimpleValueType() == MVT::v8i16 && "Bad operand type!");
8691 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8692 ArrayRef<int> OrigMask = SVOp->getMask();
8693 int MaskStorage[8] = {OrigMask[0], OrigMask[1], OrigMask[2], OrigMask[3],
8694 OrigMask[4], OrigMask[5], OrigMask[6], OrigMask[7]};
8695 MutableArrayRef<int> Mask(MaskStorage);
8697 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
8699 // Whenever we can lower this as a zext, that instruction is strictly faster
8700 // than any alternative.
8701 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8702 DL, MVT::v8i16, V1, V2, OrigMask, Subtarget, DAG))
8705 auto isV1 = [](int M) { return M >= 0 && M < 8; };
8707 auto isV2 = [](int M) { return M >= 8; };
8709 int NumV2Inputs = std::count_if(Mask.begin(), Mask.end(), isV2);
8711 if (NumV2Inputs == 0) {
8712 // Check for being able to broadcast a single element.
8713 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i16, V1,
8714 Mask, Subtarget, DAG))
8717 // Try to use shift instructions.
8719 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V1, Mask, DAG))
8722 // Use dedicated unpack instructions for masks that match their pattern.
8723 if (isShuffleEquivalent(V1, V1, Mask, {0, 0, 1, 1, 2, 2, 3, 3}))
8724 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V1);
8725 if (isShuffleEquivalent(V1, V1, Mask, {4, 4, 5, 5, 6, 6, 7, 7}))
8726 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V1);
8728 // Try to use byte rotation instructions.
8729 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(DL, MVT::v8i16, V1, V1,
8730 Mask, Subtarget, DAG))
8733 return lowerV8I16GeneralSingleInputVectorShuffle(DL, MVT::v8i16, V1, Mask,
8737 assert(std::any_of(Mask.begin(), Mask.end(), isV1) &&
8738 "All single-input shuffles should be canonicalized to be V1-input "
8741 // Try to use shift instructions.
8743 lowerVectorShuffleAsShift(DL, MVT::v8i16, V1, V2, Mask, DAG))
8746 // See if we can use SSE4A Extraction / Insertion.
8747 if (Subtarget->hasSSE4A())
8748 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v8i16, V1, V2, Mask, DAG))
8751 // There are special ways we can lower some single-element blends.
8752 if (NumV2Inputs == 1)
8753 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v8i16, V1, V2,
8754 Mask, Subtarget, DAG))
8757 // We have different paths for blend lowering, but they all must use the
8758 // *exact* same predicate.
8759 bool IsBlendSupported = Subtarget->hasSSE41();
8760 if (IsBlendSupported)
8761 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i16, V1, V2, Mask,
8765 if (SDValue Masked =
8766 lowerVectorShuffleAsBitMask(DL, MVT::v8i16, V1, V2, Mask, DAG))
8769 // Use dedicated unpack instructions for masks that match their pattern.
8770 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 2, 10, 3, 11}))
8771 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i16, V1, V2);
8772 if (isShuffleEquivalent(V1, V2, Mask, {4, 12, 5, 13, 6, 14, 7, 15}))
8773 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i16, V1, V2);
8775 // Try to use byte rotation instructions.
8776 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8777 DL, MVT::v8i16, V1, V2, Mask, Subtarget, DAG))
8780 if (SDValue BitBlend =
8781 lowerVectorShuffleAsBitBlend(DL, MVT::v8i16, V1, V2, Mask, DAG))
8784 if (SDValue Unpack =
8785 lowerVectorShuffleAsUnpack(DL, MVT::v8i16, V1, V2, Mask, DAG))
8788 // If we can't directly blend but can use PSHUFB, that will be better as it
8789 // can both shuffle and set up the inefficient blend.
8790 if (!IsBlendSupported && Subtarget->hasSSSE3()) {
8791 bool V1InUse, V2InUse;
8792 return lowerVectorShuffleAsPSHUFB(DL, MVT::v8i16, V1, V2, Mask, DAG,
8796 // We can always bit-blend if we have to so the fallback strategy is to
8797 // decompose into single-input permutes and blends.
8798 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i16, V1, V2,
8802 /// \brief Check whether a compaction lowering can be done by dropping even
8803 /// elements and compute how many times even elements must be dropped.
8805 /// This handles shuffles which take every Nth element where N is a power of
8806 /// two. Example shuffle masks:
8808 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 0, 2, 4, 6, 8, 10, 12, 14
8809 /// N = 1: 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30
8810 /// N = 2: 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12, 0, 4, 8, 12
8811 /// N = 2: 0, 4, 8, 12, 16, 20, 24, 28, 0, 4, 8, 12, 16, 20, 24, 28
8812 /// N = 3: 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8, 0, 8
8813 /// N = 3: 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24, 0, 8, 16, 24
8815 /// Any of these lanes can of course be undef.
8817 /// This routine only supports N <= 3.
8818 /// FIXME: Evaluate whether either AVX or AVX-512 have any opportunities here
8821 /// \returns N above, or the number of times even elements must be dropped if
8822 /// there is such a number. Otherwise returns zero.
8823 static int canLowerByDroppingEvenElements(ArrayRef<int> Mask) {
8824 // Figure out whether we're looping over two inputs or just one.
8825 bool IsSingleInput = isSingleInputShuffleMask(Mask);
8827 // The modulus for the shuffle vector entries is based on whether this is
8828 // a single input or not.
8829 int ShuffleModulus = Mask.size() * (IsSingleInput ? 1 : 2);
8830 assert(isPowerOf2_32((uint32_t)ShuffleModulus) &&
8831 "We should only be called with masks with a power-of-2 size!");
8833 uint64_t ModMask = (uint64_t)ShuffleModulus - 1;
8835 // We track whether the input is viable for all power-of-2 strides 2^1, 2^2,
8836 // and 2^3 simultaneously. This is because we may have ambiguity with
8837 // partially undef inputs.
8838 bool ViableForN[3] = {true, true, true};
8840 for (int i = 0, e = Mask.size(); i < e; ++i) {
8841 // Ignore undef lanes, we'll optimistically collapse them to the pattern we
8846 bool IsAnyViable = false;
8847 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8848 if (ViableForN[j]) {
8851 // The shuffle mask must be equal to (i * 2^N) % M.
8852 if ((uint64_t)Mask[i] == (((uint64_t)i << N) & ModMask))
8855 ViableForN[j] = false;
8857 // Early exit if we exhaust the possible powers of two.
8862 for (unsigned j = 0; j != array_lengthof(ViableForN); ++j)
8866 // Return 0 as there is no viable power of two.
8870 /// \brief Generic lowering of v16i8 shuffles.
8872 /// This is a hybrid strategy to lower v16i8 vectors. It first attempts to
8873 /// detect any complexity reducing interleaving. If that doesn't help, it uses
8874 /// UNPCK to spread the i8 elements across two i16-element vectors, and uses
8875 /// the existing lowering for v8i16 blends on each half, finally PACK-ing them
8877 static SDValue lowerV16I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
8878 const X86Subtarget *Subtarget,
8879 SelectionDAG &DAG) {
8881 assert(Op.getSimpleValueType() == MVT::v16i8 && "Bad shuffle type!");
8882 assert(V1.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8883 assert(V2.getSimpleValueType() == MVT::v16i8 && "Bad operand type!");
8884 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
8885 ArrayRef<int> Mask = SVOp->getMask();
8886 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
8888 // Try to use shift instructions.
8890 lowerVectorShuffleAsShift(DL, MVT::v16i8, V1, V2, Mask, DAG))
8893 // Try to use byte rotation instructions.
8894 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
8895 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8898 // Try to use a zext lowering.
8899 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(
8900 DL, MVT::v16i8, V1, V2, Mask, Subtarget, DAG))
8903 // See if we can use SSE4A Extraction / Insertion.
8904 if (Subtarget->hasSSE4A())
8905 if (SDValue V = lowerVectorShuffleWithSSE4A(DL, MVT::v16i8, V1, V2, Mask, DAG))
8909 std::count_if(Mask.begin(), Mask.end(), [](int M) { return M >= 16; });
8911 // For single-input shuffles, there are some nicer lowering tricks we can use.
8912 if (NumV2Elements == 0) {
8913 // Check for being able to broadcast a single element.
8914 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i8, V1,
8915 Mask, Subtarget, DAG))
8918 // Check whether we can widen this to an i16 shuffle by duplicating bytes.
8919 // Notably, this handles splat and partial-splat shuffles more efficiently.
8920 // However, it only makes sense if the pre-duplication shuffle simplifies
8921 // things significantly. Currently, this means we need to be able to
8922 // express the pre-duplication shuffle as an i16 shuffle.
8924 // FIXME: We should check for other patterns which can be widened into an
8925 // i16 shuffle as well.
8926 auto canWidenViaDuplication = [](ArrayRef<int> Mask) {
8927 for (int i = 0; i < 16; i += 2)
8928 if (Mask[i] != -1 && Mask[i + 1] != -1 && Mask[i] != Mask[i + 1])
8933 auto tryToWidenViaDuplication = [&]() -> SDValue {
8934 if (!canWidenViaDuplication(Mask))
8936 SmallVector<int, 4> LoInputs;
8937 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(LoInputs),
8938 [](int M) { return M >= 0 && M < 8; });
8939 std::sort(LoInputs.begin(), LoInputs.end());
8940 LoInputs.erase(std::unique(LoInputs.begin(), LoInputs.end()),
8942 SmallVector<int, 4> HiInputs;
8943 std::copy_if(Mask.begin(), Mask.end(), std::back_inserter(HiInputs),
8944 [](int M) { return M >= 8; });
8945 std::sort(HiInputs.begin(), HiInputs.end());
8946 HiInputs.erase(std::unique(HiInputs.begin(), HiInputs.end()),
8949 bool TargetLo = LoInputs.size() >= HiInputs.size();
8950 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs;
8951 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs;
8953 int PreDupI16Shuffle[] = {-1, -1, -1, -1, -1, -1, -1, -1};
8954 SmallDenseMap<int, int, 8> LaneMap;
8955 for (int I : InPlaceInputs) {
8956 PreDupI16Shuffle[I/2] = I/2;
8959 int j = TargetLo ? 0 : 4, je = j + 4;
8960 for (int i = 0, ie = MovingInputs.size(); i < ie; ++i) {
8961 // Check if j is already a shuffle of this input. This happens when
8962 // there are two adjacent bytes after we move the low one.
8963 if (PreDupI16Shuffle[j] != MovingInputs[i] / 2) {
8964 // If we haven't yet mapped the input, search for a slot into which
8966 while (j < je && PreDupI16Shuffle[j] != -1)
8970 // We can't place the inputs into a single half with a simple i16 shuffle, so bail.
8973 // Map this input with the i16 shuffle.
8974 PreDupI16Shuffle[j] = MovingInputs[i] / 2;
8977 // Update the lane map based on the mapping we ended up with.
8978 LaneMap[MovingInputs[i]] = 2 * j + MovingInputs[i] % 2;
8980 V1 = DAG.getBitcast(
8982 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
8983 DAG.getUNDEF(MVT::v8i16), PreDupI16Shuffle));
8985 // Unpack the bytes to form the i16s that will be shuffled into place.
8986 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL,
8987 MVT::v16i8, V1, V1);
8989 int PostDupI16Shuffle[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
8990 for (int i = 0; i < 16; ++i)
8991 if (Mask[i] != -1) {
8992 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8);
8993 assert(MappedMask < 8 && "Invalid v8 shuffle mask!");
8994 if (PostDupI16Shuffle[i / 2] == -1)
8995 PostDupI16Shuffle[i / 2] = MappedMask;
8997 assert(PostDupI16Shuffle[i / 2] == MappedMask &&
8998 "Conflicting entrties in the original shuffle!");
9000 return DAG.getBitcast(
9002 DAG.getVectorShuffle(MVT::v8i16, DL, DAG.getBitcast(MVT::v8i16, V1),
9003 DAG.getUNDEF(MVT::v8i16), PostDupI16Shuffle));
9005 if (SDValue V = tryToWidenViaDuplication())
9009 // Use dedicated unpack instructions for masks that match their pattern.
9010 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9011 0, 16, 1, 17, 2, 18, 3, 19,
9013 4, 20, 5, 21, 6, 22, 7, 23}))
9014 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V1, V2);
9015 if (isShuffleEquivalent(V1, V2, Mask, {// Low half.
9016 8, 24, 9, 25, 10, 26, 11, 27,
9018 12, 28, 13, 29, 14, 30, 15, 31}))
9019 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V1, V2);
9021 // Check for SSSE3 which lets us lower all v16i8 shuffles much more directly
9022 // with PSHUFB. It is important to do this before we attempt to generate any
9023 // blends but after all of the single-input lowerings. If the single input
9024 // lowerings can find an instruction sequence that is faster than a PSHUFB, we
9025 // want to preserve that and we can DAG combine any longer sequences into
9026 // a PSHUFB in the end. But once we start blending from multiple inputs,
9027 // the complexity of DAG combining bad patterns back into PSHUFB is too high,
9028 // and there are *very* few patterns that would actually be faster than the
9029 // PSHUFB approach because of its ability to zero lanes.
9031 // FIXME: The only exceptions to the above are blends which are exact
9032 // interleavings with direct instructions supporting them. We currently don't
9033 // handle those well here.
9034 if (Subtarget->hasSSSE3()) {
9035 bool V1InUse = false;
9036 bool V2InUse = false;
9038 SDValue PSHUFB = lowerVectorShuffleAsPSHUFB(DL, MVT::v16i8, V1, V2, Mask,
9039 DAG, V1InUse, V2InUse);
9041 // If both V1 and V2 are in use and we can use a direct blend or an unpack,
9042 // do so. This avoids using them to handle blends-with-zero which is
9043 // important as a single pshufb is significantly faster for that.
9044 if (V1InUse && V2InUse) {
9045 if (Subtarget->hasSSE41())
9046 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i8, V1, V2,
9047 Mask, Subtarget, DAG))
9050 // We can use an unpack to do the blending rather than an or in some
9051 // cases. Even though the or may be (very minorly) more efficient, we
9052 // preference this lowering because there are common cases where part of
9053 // the complexity of the shuffles goes away when we do the final blend as
9055 // FIXME: It might be worth trying to detect if the unpack-feeding
9056 // shuffles will both be pshufb, in which case we shouldn't bother with
9058 if (SDValue Unpack =
9059 lowerVectorShuffleAsUnpack(DL, MVT::v16i8, V1, V2, Mask, DAG))
9066 // There are special ways we can lower some single-element blends.
9067 if (NumV2Elements == 1)
9068 if (SDValue V = lowerVectorShuffleAsElementInsertion(DL, MVT::v16i8, V1, V2,
9069 Mask, Subtarget, DAG))
9072 if (SDValue BitBlend =
9073 lowerVectorShuffleAsBitBlend(DL, MVT::v16i8, V1, V2, Mask, DAG))
9076 // Check whether a compaction lowering can be done. This handles shuffles
9077 // which take every Nth element for some even N. See the helper function for
9080 // We special case these as they can be particularly efficiently handled with
9081 // the PACKUSB instruction on x86 and they show up in common patterns of
9082 // rearranging bytes to truncate wide elements.
9083 if (int NumEvenDrops = canLowerByDroppingEvenElements(Mask)) {
9084 // NumEvenDrops is the power of two stride of the elements. Another way of
9085 // thinking about it is that we need to drop the even elements this many
9086 // times to get the original input.
9087 bool IsSingleInput = isSingleInputShuffleMask(Mask);
9089 // First we need to zero all the dropped bytes.
9090 assert(NumEvenDrops <= 3 &&
9091 "No support for dropping even elements more than 3 times.");
9092 // We use the mask type to pick which bytes are preserved based on how many
9093 // elements are dropped.
9094 MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };
9095 SDValue ByteClearMask = DAG.getBitcast(
9096 MVT::v16i8, DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));
9097 V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);
9099 V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);
9101 // Now pack things back together.
9102 V1 = DAG.getBitcast(MVT::v8i16, V1);
9103 V2 = IsSingleInput ? V1 : DAG.getBitcast(MVT::v8i16, V2);
9104 SDValue Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, V1, V2);
9105 for (int i = 1; i < NumEvenDrops; ++i) {
9106 Result = DAG.getBitcast(MVT::v8i16, Result);
9107 Result = DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, Result, Result);
9113 // Handle multi-input cases by blending single-input shuffles.
9114 if (NumV2Elements > 0)
9115 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v16i8, V1, V2,
9118 // The fallback path for single-input shuffles widens this into two v8i16
9119 // vectors with unpacks, shuffles those, and then pulls them back together
9123 int LoBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9124 int HiBlendMask[8] = {-1, -1, -1, -1, -1, -1, -1, -1};
9125 for (int i = 0; i < 16; ++i)
9127 (i < 8 ? LoBlendMask[i] : HiBlendMask[i % 8]) = Mask[i];
9129 SDValue Zero = getZeroVector(MVT::v8i16, Subtarget, DAG, DL);
9131 SDValue VLoHalf, VHiHalf;
9132 // Check if any of the odd lanes in the v16i8 are used. If not, we can mask
9133 // them out and avoid using UNPCK{L,H} to extract the elements of V as
9135 if (std::none_of(std::begin(LoBlendMask), std::end(LoBlendMask),
9136 [](int M) { return M >= 0 && M % 2 == 1; }) &&
9137 std::none_of(std::begin(HiBlendMask), std::end(HiBlendMask),
9138 [](int M) { return M >= 0 && M % 2 == 1; })) {
9139 // Use a mask to drop the high bytes.
9140 VLoHalf = DAG.getBitcast(MVT::v8i16, V);
9141 VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,
9142 DAG.getConstant(0x00FF, DL, MVT::v8i16));
9144 // This will be a single vector shuffle instead of a blend so nuke VHiHalf.
9145 VHiHalf = DAG.getUNDEF(MVT::v8i16);
9147 // Squash the masks to point directly into VLoHalf.
9148 for (int &M : LoBlendMask)
9151 for (int &M : HiBlendMask)
9155 // Otherwise just unpack the low half of V into VLoHalf and the high half into
9156 // VHiHalf so that we can blend them as i16s.
9157 VLoHalf = DAG.getBitcast(
9158 MVT::v8i16, DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i8, V, Zero));
9159 VHiHalf = DAG.getBitcast(
9160 MVT::v8i16, DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i8, V, Zero));
9163 SDValue LoV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, LoBlendMask);
9164 SDValue HiV = DAG.getVectorShuffle(MVT::v8i16, DL, VLoHalf, VHiHalf, HiBlendMask);
9166 return DAG.getNode(X86ISD::PACKUS, DL, MVT::v16i8, LoV, HiV);
9169 /// \brief Dispatching routine to lower various 128-bit x86 vector shuffles.
9171 /// This routine breaks down the specific type of 128-bit shuffle and
9172 /// dispatches to the lowering routines accordingly.
9173 static SDValue lower128BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9174 MVT VT, const X86Subtarget *Subtarget,
9175 SelectionDAG &DAG) {
9176 switch (VT.SimpleTy) {
9178 return lowerV2I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9180 return lowerV2F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
9182 return lowerV4I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9184 return lowerV4F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
9186 return lowerV8I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
9188 return lowerV16I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
9191 llvm_unreachable("Unimplemented!");
9195 /// \brief Helper function to test whether a shuffle mask could be
9196 /// simplified by widening the elements being shuffled.
9198 /// Appends the mask for wider elements in WidenedMask if valid. Otherwise
9199 /// leaves it in an unspecified state.
9201 /// NOTE: This must handle normal vector shuffle masks and *target* vector
9202 /// shuffle masks. The latter have the special property of a '-2' representing
9203 /// a zero-ed lane of a vector.
9204 static bool canWidenShuffleElements(ArrayRef<int> Mask,
9205 SmallVectorImpl<int> &WidenedMask) {
9206 for (int i = 0, Size = Mask.size(); i < Size; i += 2) {
9207 // If both elements are undef, its trivial.
9208 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] == SM_SentinelUndef) {
9209 WidenedMask.push_back(SM_SentinelUndef);
9213 // Check for an undef mask and a mask value properly aligned to fit with
9214 // a pair of values. If we find such a case, use the non-undef mask's value.
9215 if (Mask[i] == SM_SentinelUndef && Mask[i + 1] >= 0 && Mask[i + 1] % 2 == 1) {
9216 WidenedMask.push_back(Mask[i + 1] / 2);
9219 if (Mask[i + 1] == SM_SentinelUndef && Mask[i] >= 0 && Mask[i] % 2 == 0) {
9220 WidenedMask.push_back(Mask[i] / 2);
9224 // When zeroing, we need to spread the zeroing across both lanes to widen.
9225 if (Mask[i] == SM_SentinelZero || Mask[i + 1] == SM_SentinelZero) {
9226 if ((Mask[i] == SM_SentinelZero || Mask[i] == SM_SentinelUndef) &&
9227 (Mask[i + 1] == SM_SentinelZero || Mask[i + 1] == SM_SentinelUndef)) {
9228 WidenedMask.push_back(SM_SentinelZero);
9234 // Finally check if the two mask values are adjacent and aligned with
9236 if (Mask[i] != SM_SentinelUndef && Mask[i] % 2 == 0 && Mask[i] + 1 == Mask[i + 1]) {
9237 WidenedMask.push_back(Mask[i] / 2);
9241 // Otherwise we can't safely widen the elements used in this shuffle.
9244 assert(WidenedMask.size() == Mask.size() / 2 &&
9245 "Incorrect size of mask after widening the elements!");
9250 /// \brief Generic routine to split vector shuffle into half-sized shuffles.
9252 /// This routine just extracts two subvectors, shuffles them independently, and
9253 /// then concatenates them back together. This should work effectively with all
9254 /// AVX vector shuffle types.
9255 static SDValue splitAndLowerVectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9256 SDValue V2, ArrayRef<int> Mask,
9257 SelectionDAG &DAG) {
9258 assert(VT.getSizeInBits() >= 256 &&
9259 "Only for 256-bit or wider vector shuffles!");
9260 assert(V1.getSimpleValueType() == VT && "Bad operand type!");
9261 assert(V2.getSimpleValueType() == VT && "Bad operand type!");
9263 ArrayRef<int> LoMask = Mask.slice(0, Mask.size() / 2);
9264 ArrayRef<int> HiMask = Mask.slice(Mask.size() / 2);
9266 int NumElements = VT.getVectorNumElements();
9267 int SplitNumElements = NumElements / 2;
9268 MVT ScalarVT = VT.getScalarType();
9269 MVT SplitVT = MVT::getVectorVT(ScalarVT, NumElements / 2);
9271 // Rather than splitting build-vectors, just build two narrower build
9272 // vectors. This helps shuffling with splats and zeros.
9273 auto SplitVector = [&](SDValue V) {
9274 while (V.getOpcode() == ISD::BITCAST)
9275 V = V->getOperand(0);
9277 MVT OrigVT = V.getSimpleValueType();
9278 int OrigNumElements = OrigVT.getVectorNumElements();
9279 int OrigSplitNumElements = OrigNumElements / 2;
9280 MVT OrigScalarVT = OrigVT.getScalarType();
9281 MVT OrigSplitVT = MVT::getVectorVT(OrigScalarVT, OrigNumElements / 2);
9285 auto *BV = dyn_cast<BuildVectorSDNode>(V);
9287 LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9288 DAG.getIntPtrConstant(0, DL));
9289 HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,
9290 DAG.getIntPtrConstant(OrigSplitNumElements, DL));
9293 SmallVector<SDValue, 16> LoOps, HiOps;
9294 for (int i = 0; i < OrigSplitNumElements; ++i) {
9295 LoOps.push_back(BV->getOperand(i));
9296 HiOps.push_back(BV->getOperand(i + OrigSplitNumElements));
9298 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps);
9299 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps);
9301 return std::make_pair(DAG.getBitcast(SplitVT, LoV),
9302 DAG.getBitcast(SplitVT, HiV));
9305 SDValue LoV1, HiV1, LoV2, HiV2;
9306 std::tie(LoV1, HiV1) = SplitVector(V1);
9307 std::tie(LoV2, HiV2) = SplitVector(V2);
9309 // Now create two 4-way blends of these half-width vectors.
9310 auto HalfBlend = [&](ArrayRef<int> HalfMask) {
9311 bool UseLoV1 = false, UseHiV1 = false, UseLoV2 = false, UseHiV2 = false;
9312 SmallVector<int, 32> V1BlendMask, V2BlendMask, BlendMask;
9313 for (int i = 0; i < SplitNumElements; ++i) {
9314 int M = HalfMask[i];
9315 if (M >= NumElements) {
9316 if (M >= NumElements + SplitNumElements)
9320 V2BlendMask.push_back(M - NumElements);
9321 V1BlendMask.push_back(-1);
9322 BlendMask.push_back(SplitNumElements + i);
9323 } else if (M >= 0) {
9324 if (M >= SplitNumElements)
9328 V2BlendMask.push_back(-1);
9329 V1BlendMask.push_back(M);
9330 BlendMask.push_back(i);
9332 V2BlendMask.push_back(-1);
9333 V1BlendMask.push_back(-1);
9334 BlendMask.push_back(-1);
9338 // Because the lowering happens after all combining takes place, we need to
9339 // manually combine these blend masks as much as possible so that we create
9340 // a minimal number of high-level vector shuffle nodes.
9342 // First try just blending the halves of V1 or V2.
9343 if (!UseLoV1 && !UseHiV1 && !UseLoV2 && !UseHiV2)
9344 return DAG.getUNDEF(SplitVT);
9345 if (!UseLoV2 && !UseHiV2)
9346 return DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9347 if (!UseLoV1 && !UseHiV1)
9348 return DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9350 SDValue V1Blend, V2Blend;
9351 if (UseLoV1 && UseHiV1) {
9353 DAG.getVectorShuffle(SplitVT, DL, LoV1, HiV1, V1BlendMask);
9355 // We only use half of V1 so map the usage down into the final blend mask.
9356 V1Blend = UseLoV1 ? LoV1 : HiV1;
9357 for (int i = 0; i < SplitNumElements; ++i)
9358 if (BlendMask[i] >= 0 && BlendMask[i] < SplitNumElements)
9359 BlendMask[i] = V1BlendMask[i] - (UseLoV1 ? 0 : SplitNumElements);
9361 if (UseLoV2 && UseHiV2) {
9363 DAG.getVectorShuffle(SplitVT, DL, LoV2, HiV2, V2BlendMask);
9365 // We only use half of V2 so map the usage down into the final blend mask.
9366 V2Blend = UseLoV2 ? LoV2 : HiV2;
9367 for (int i = 0; i < SplitNumElements; ++i)
9368 if (BlendMask[i] >= SplitNumElements)
9369 BlendMask[i] = V2BlendMask[i] + (UseLoV2 ? SplitNumElements : 0);
9371 return DAG.getVectorShuffle(SplitVT, DL, V1Blend, V2Blend, BlendMask);
9373 SDValue Lo = HalfBlend(LoMask);
9374 SDValue Hi = HalfBlend(HiMask);
9375 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
9378 /// \brief Either split a vector in halves or decompose the shuffles and the
9381 /// This is provided as a good fallback for many lowerings of non-single-input
9382 /// shuffles with more than one 128-bit lane. In those cases, we want to select
9383 /// between splitting the shuffle into 128-bit components and stitching those
9384 /// back together vs. extracting the single-input shuffles and blending those
9386 static SDValue lowerVectorShuffleAsSplitOrBlend(SDLoc DL, MVT VT, SDValue V1,
9387 SDValue V2, ArrayRef<int> Mask,
9388 SelectionDAG &DAG) {
9389 assert(!isSingleInputShuffleMask(Mask) && "This routine must not be used to "
9390 "lower single-input shuffles as it "
9391 "could then recurse on itself.");
9392 int Size = Mask.size();
9394 // If this can be modeled as a broadcast of two elements followed by a blend,
9395 // prefer that lowering. This is especially important because broadcasts can
9396 // often fold with memory operands.
9397 auto DoBothBroadcast = [&] {
9398 int V1BroadcastIdx = -1, V2BroadcastIdx = -1;
9401 if (V2BroadcastIdx == -1)
9402 V2BroadcastIdx = M - Size;
9403 else if (M - Size != V2BroadcastIdx)
9405 } else if (M >= 0) {
9406 if (V1BroadcastIdx == -1)
9408 else if (M != V1BroadcastIdx)
9413 if (DoBothBroadcast())
9414 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask,
9417 // If the inputs all stem from a single 128-bit lane of each input, then we
9418 // split them rather than blending because the split will decompose to
9419 // unusually few instructions.
9420 int LaneCount = VT.getSizeInBits() / 128;
9421 int LaneSize = Size / LaneCount;
9422 SmallBitVector LaneInputs[2];
9423 LaneInputs[0].resize(LaneCount, false);
9424 LaneInputs[1].resize(LaneCount, false);
9425 for (int i = 0; i < Size; ++i)
9427 LaneInputs[Mask[i] / Size][(Mask[i] % Size) / LaneSize] = true;
9428 if (LaneInputs[0].count() <= 1 && LaneInputs[1].count() <= 1)
9429 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9431 // Otherwise, just fall back to decomposed shuffles and a blend. This requires
9432 // that the decomposed single-input shuffles don't end up here.
9433 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9436 /// \brief Lower a vector shuffle crossing multiple 128-bit lanes as
9437 /// a permutation and blend of those lanes.
9439 /// This essentially blends the out-of-lane inputs to each lane into the lane
9440 /// from a permuted copy of the vector. This lowering strategy results in four
9441 /// instructions in the worst case for a single-input cross lane shuffle which
9442 /// is lower than any other fully general cross-lane shuffle strategy I'm aware
9443 /// of. Special cases for each particular shuffle pattern should be handled
9444 /// prior to trying this lowering.
9445 static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
9446 SDValue V1, SDValue V2,
9448 SelectionDAG &DAG) {
9449 // FIXME: This should probably be generalized for 512-bit vectors as well.
9450 assert(VT.getSizeInBits() == 256 && "Only for 256-bit vector shuffles!");
9451 int LaneSize = Mask.size() / 2;
9453 // If there are only inputs from one 128-bit lane, splitting will in fact be
9454 // less expensive. The flags track whether the given lane contains an element
9455 // that crosses to another lane.
9456 bool LaneCrossing[2] = {false, false};
9457 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9458 if (Mask[i] >= 0 && (Mask[i] % Size) / LaneSize != i / LaneSize)
9459 LaneCrossing[(Mask[i] % Size) / LaneSize] = true;
9460 if (!LaneCrossing[0] || !LaneCrossing[1])
9461 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
9463 if (isSingleInputShuffleMask(Mask)) {
9464 SmallVector<int, 32> FlippedBlendMask;
9465 for (int i = 0, Size = Mask.size(); i < Size; ++i)
9466 FlippedBlendMask.push_back(
9467 Mask[i] < 0 ? -1 : (((Mask[i] % Size) / LaneSize == i / LaneSize)
9469 : Mask[i] % LaneSize +
9470 (i / LaneSize) * LaneSize + Size));
9472 // Flip the vector, and blend the results which should now be in-lane. The
9473 // VPERM2X128 mask uses the low 2 bits for the low source and bits 4 and
9474 // 5 for the high source. The value 3 selects the high half of source 2 and
9475 // the value 2 selects the low half of source 2. We only use source 2 to
9476 // allow folding it into a memory operand.
9477 unsigned PERMMask = 3 | 2 << 4;
9478 SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),
9479 V1, DAG.getConstant(PERMMask, DL, MVT::i8));
9480 return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);
9483 // This now reduces to two single-input shuffles of V1 and V2 which at worst
9484 // will be handled by the above logic and a blend of the results, much like
9485 // other patterns in AVX.
9486 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, VT, V1, V2, Mask, DAG);
9489 /// \brief Handle lowering 2-lane 128-bit shuffles.
9490 static SDValue lowerV2X128VectorShuffle(SDLoc DL, MVT VT, SDValue V1,
9491 SDValue V2, ArrayRef<int> Mask,
9492 const X86Subtarget *Subtarget,
9493 SelectionDAG &DAG) {
9494 // TODO: If minimizing size and one of the inputs is a zero vector and the
9495 // the zero vector has only one use, we could use a VPERM2X128 to save the
9496 // instruction bytes needed to explicitly generate the zero vector.
9498 // Blends are faster and handle all the non-lane-crossing cases.
9499 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, VT, V1, V2, Mask,
9503 bool IsV1Zero = ISD::isBuildVectorAllZeros(V1.getNode());
9504 bool IsV2Zero = ISD::isBuildVectorAllZeros(V2.getNode());
9506 // If either input operand is a zero vector, use VPERM2X128 because its mask
9507 // allows us to replace the zero input with an implicit zero.
9508 if (!IsV1Zero && !IsV2Zero) {
9509 // Check for patterns which can be matched with a single insert of a 128-bit
9511 bool OnlyUsesV1 = isShuffleEquivalent(V1, V2, Mask, {0, 1, 0, 1});
9512 if (OnlyUsesV1 || isShuffleEquivalent(V1, V2, Mask, {0, 1, 4, 5})) {
9513 MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),
9514 VT.getVectorNumElements() / 2);
9515 SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,
9516 DAG.getIntPtrConstant(0, DL));
9517 SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,
9518 OnlyUsesV1 ? V1 : V2,
9519 DAG.getIntPtrConstant(0, DL));
9520 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);
9524 // Otherwise form a 128-bit permutation. After accounting for undefs,
9525 // convert the 64-bit shuffle mask selection values into 128-bit
9526 // selection bits by dividing the indexes by 2 and shifting into positions
9527 // defined by a vperm2*128 instruction's immediate control byte.
9529 // The immediate permute control byte looks like this:
9530 // [1:0] - select 128 bits from sources for low half of destination
9532 // [3] - zero low half of destination
9533 // [5:4] - select 128 bits from sources for high half of destination
9535 // [7] - zero high half of destination
9537 int MaskLO = Mask[0];
9538 if (MaskLO == SM_SentinelUndef)
9539 MaskLO = Mask[1] == SM_SentinelUndef ? 0 : Mask[1];
9541 int MaskHI = Mask[2];
9542 if (MaskHI == SM_SentinelUndef)
9543 MaskHI = Mask[3] == SM_SentinelUndef ? 0 : Mask[3];
9545 unsigned PermMask = MaskLO / 2 | (MaskHI / 2) << 4;
9547 // If either input is a zero vector, replace it with an undef input.
9548 // Shuffle mask values < 4 are selecting elements of V1.
9549 // Shuffle mask values >= 4 are selecting elements of V2.
9550 // Adjust each half of the permute mask by clearing the half that was
9551 // selecting the zero vector and setting the zero mask bit.
9553 V1 = DAG.getUNDEF(VT);
9555 PermMask = (PermMask & 0xf0) | 0x08;
9557 PermMask = (PermMask & 0x0f) | 0x80;
9560 V2 = DAG.getUNDEF(VT);
9562 PermMask = (PermMask & 0xf0) | 0x08;
9564 PermMask = (PermMask & 0x0f) | 0x80;
9567 return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,
9568 DAG.getConstant(PermMask, DL, MVT::i8));
9571 /// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then
9572 /// shuffling each lane.
9574 /// This will only succeed when the result of fixing the 128-bit lanes results
9575 /// in a single-input non-lane-crossing shuffle with a repeating shuffle mask in
9576 /// each 128-bit lanes. This handles many cases where we can quickly blend away
9577 /// the lane crosses early and then use simpler shuffles within each lane.
9579 /// FIXME: It might be worthwhile at some point to support this without
9580 /// requiring the 128-bit lane-relative shuffles to be repeating, but currently
9581 /// in x86 only floating point has interesting non-repeating shuffles, and even
9582 /// those are still *marginally* more expensive.
9583 static SDValue lowerVectorShuffleByMerging128BitLanes(
9584 SDLoc DL, MVT VT, SDValue V1, SDValue V2, ArrayRef<int> Mask,
9585 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
9586 assert(!isSingleInputShuffleMask(Mask) &&
9587 "This is only useful with multiple inputs.");
9589 int Size = Mask.size();
9590 int LaneSize = 128 / VT.getScalarSizeInBits();
9591 int NumLanes = Size / LaneSize;
9592 assert(NumLanes > 1 && "Only handles 256-bit and wider shuffles.");
9594 // See if we can build a hypothetical 128-bit lane-fixing shuffle mask. Also
9595 // check whether the in-128-bit lane shuffles share a repeating pattern.
9596 SmallVector<int, 4> Lanes;
9597 Lanes.resize(NumLanes, -1);
9598 SmallVector<int, 4> InLaneMask;
9599 InLaneMask.resize(LaneSize, -1);
9600 for (int i = 0; i < Size; ++i) {
9604 int j = i / LaneSize;
9607 // First entry we've seen for this lane.
9608 Lanes[j] = Mask[i] / LaneSize;
9609 } else if (Lanes[j] != Mask[i] / LaneSize) {
9610 // This doesn't match the lane selected previously!
9614 // Check that within each lane we have a consistent shuffle mask.
9615 int k = i % LaneSize;
9616 if (InLaneMask[k] < 0) {
9617 InLaneMask[k] = Mask[i] % LaneSize;
9618 } else if (InLaneMask[k] != Mask[i] % LaneSize) {
9619 // This doesn't fit a repeating in-lane mask.
9624 // First shuffle the lanes into place.
9625 MVT LaneVT = MVT::getVectorVT(VT.isFloatingPoint() ? MVT::f64 : MVT::i64,
9626 VT.getSizeInBits() / 64);
9627 SmallVector<int, 8> LaneMask;
9628 LaneMask.resize(NumLanes * 2, -1);
9629 for (int i = 0; i < NumLanes; ++i)
9630 if (Lanes[i] >= 0) {
9631 LaneMask[2 * i + 0] = 2*Lanes[i] + 0;
9632 LaneMask[2 * i + 1] = 2*Lanes[i] + 1;
9635 V1 = DAG.getBitcast(LaneVT, V1);
9636 V2 = DAG.getBitcast(LaneVT, V2);
9637 SDValue LaneShuffle = DAG.getVectorShuffle(LaneVT, DL, V1, V2, LaneMask);
9639 // Cast it back to the type we actually want.
9640 LaneShuffle = DAG.getBitcast(VT, LaneShuffle);
9642 // Now do a simple shuffle that isn't lane crossing.
9643 SmallVector<int, 8> NewMask;
9644 NewMask.resize(Size, -1);
9645 for (int i = 0; i < Size; ++i)
9647 NewMask[i] = (i / LaneSize) * LaneSize + Mask[i] % LaneSize;
9648 assert(!is128BitLaneCrossingShuffleMask(VT, NewMask) &&
9649 "Must not introduce lane crosses at this point!");
9651 return DAG.getVectorShuffle(VT, DL, LaneShuffle, DAG.getUNDEF(VT), NewMask);
9654 /// \brief Test whether the specified input (0 or 1) is in-place blended by the
9657 /// This returns true if the elements from a particular input are already in the
9658 /// slot required by the given mask and require no permutation.
9659 static bool isShuffleMaskInputInPlace(int Input, ArrayRef<int> Mask) {
9660 assert((Input == 0 || Input == 1) && "Only two inputs to shuffles.");
9661 int Size = Mask.size();
9662 for (int i = 0; i < Size; ++i)
9663 if (Mask[i] >= 0 && Mask[i] / Size == Input && Mask[i] % Size != i)
9669 static SDValue lowerVectorShuffleWithSHUFPD(SDLoc DL, MVT VT,
9670 ArrayRef<int> Mask, SDValue V1,
9671 SDValue V2, SelectionDAG &DAG) {
9673 // Mask for V8F64: 0/1, 8/9, 2/3, 10/11, 4/5, ..
9674 // Mask for V4F64; 0/1, 4/5, 2/3, 6/7..
9675 assert(VT.getScalarSizeInBits() == 64 && "Unexpected data type for VSHUFPD");
9676 int NumElts = VT.getVectorNumElements();
9677 bool ShufpdMask = true;
9678 bool CommutableMask = true;
9679 unsigned Immediate = 0;
9680 for (int i = 0; i < NumElts; ++i) {
9683 int Val = (i & 6) + NumElts * (i & 1);
9684 int CommutVal = (i & 0xe) + NumElts * ((i & 1)^1);
9685 if (Mask[i] < Val || Mask[i] > Val + 1)
9687 if (Mask[i] < CommutVal || Mask[i] > CommutVal + 1)
9688 CommutableMask = false;
9689 Immediate |= (Mask[i] % 2) << i;
9692 return DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,
9693 DAG.getConstant(Immediate, DL, MVT::i8));
9695 return DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,
9696 DAG.getConstant(Immediate, DL, MVT::i8));
9700 /// \brief Handle lowering of 4-lane 64-bit floating point shuffles.
9702 /// Also ends up handling lowering of 4-lane 64-bit integer shuffles when AVX2
9703 /// isn't available.
9704 static SDValue lowerV4F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9705 const X86Subtarget *Subtarget,
9706 SelectionDAG &DAG) {
9708 assert(V1.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9709 assert(V2.getSimpleValueType() == MVT::v4f64 && "Bad operand type!");
9710 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9711 ArrayRef<int> Mask = SVOp->getMask();
9712 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9714 SmallVector<int, 4> WidenedMask;
9715 if (canWidenShuffleElements(Mask, WidenedMask))
9716 return lowerV2X128VectorShuffle(DL, MVT::v4f64, V1, V2, Mask, Subtarget,
9719 if (isSingleInputShuffleMask(Mask)) {
9720 // Check for being able to broadcast a single element.
9721 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4f64, V1,
9722 Mask, Subtarget, DAG))
9725 // Use low duplicate instructions for masks that match their pattern.
9726 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2}))
9727 return DAG.getNode(X86ISD::MOVDDUP, DL, MVT::v4f64, V1);
9729 if (!is128BitLaneCrossingShuffleMask(MVT::v4f64, Mask)) {
9730 // Non-half-crossing single input shuffles can be lowerid with an
9731 // interleaved permutation.
9732 unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |
9733 ((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);
9734 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,
9735 DAG.getConstant(VPERMILPMask, DL, MVT::i8));
9738 // With AVX2 we have direct support for this permutation.
9739 if (Subtarget->hasAVX2())
9740 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,
9741 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9743 // Otherwise, fall back.
9744 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,
9748 // X86 has dedicated unpack instructions that can handle specific blend
9749 // operations: UNPCKH and UNPCKL.
9750 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9751 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V1, V2);
9752 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9753 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V1, V2);
9754 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9755 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4f64, V2, V1);
9756 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9757 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4f64, V2, V1);
9759 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4f64, V1, V2, Mask,
9763 // Check if the blend happens to exactly fit that of SHUFPD.
9765 lowerVectorShuffleWithSHUFPD(DL, MVT::v4f64, Mask, V1, V2, DAG))
9768 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9769 // shuffle. However, if we have AVX2 and either inputs are already in place,
9770 // we will be able to shuffle even across lanes the other input in a single
9771 // instruction so skip this pattern.
9772 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9773 isShuffleMaskInputInPlace(1, Mask))))
9774 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9775 DL, MVT::v4f64, V1, V2, Mask, Subtarget, DAG))
9778 // If we have AVX2 then we always want to lower with a blend because an v4 we
9779 // can fully permute the elements.
9780 if (Subtarget->hasAVX2())
9781 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4f64, V1, V2,
9784 // Otherwise fall back on generic lowering.
9785 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v4f64, V1, V2, Mask, DAG);
9788 /// \brief Handle lowering of 4-lane 64-bit integer shuffles.
9790 /// This routine is only called when we have AVX2 and thus a reasonable
9791 /// instruction set for v4i64 shuffling..
9792 static SDValue lowerV4I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9793 const X86Subtarget *Subtarget,
9794 SelectionDAG &DAG) {
9796 assert(V1.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9797 assert(V2.getSimpleValueType() == MVT::v4i64 && "Bad operand type!");
9798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9799 ArrayRef<int> Mask = SVOp->getMask();
9800 assert(Mask.size() == 4 && "Unexpected mask size for v4 shuffle!");
9801 assert(Subtarget->hasAVX2() && "We can only lower v4i64 with AVX2!");
9803 SmallVector<int, 4> WidenedMask;
9804 if (canWidenShuffleElements(Mask, WidenedMask))
9805 return lowerV2X128VectorShuffle(DL, MVT::v4i64, V1, V2, Mask, Subtarget,
9808 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v4i64, V1, V2, Mask,
9812 // Check for being able to broadcast a single element.
9813 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v4i64, V1,
9814 Mask, Subtarget, DAG))
9817 // When the shuffle is mirrored between the 128-bit lanes of the unit, we can
9818 // use lower latency instructions that will operate on both 128-bit lanes.
9819 SmallVector<int, 2> RepeatedMask;
9820 if (is128BitLaneRepeatedShuffleMask(MVT::v4i64, Mask, RepeatedMask)) {
9821 if (isSingleInputShuffleMask(Mask)) {
9822 int PSHUFDMask[] = {-1, -1, -1, -1};
9823 for (int i = 0; i < 2; ++i)
9824 if (RepeatedMask[i] >= 0) {
9825 PSHUFDMask[2 * i] = 2 * RepeatedMask[i];
9826 PSHUFDMask[2 * i + 1] = 2 * RepeatedMask[i] + 1;
9828 return DAG.getBitcast(
9830 DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,
9831 DAG.getBitcast(MVT::v8i32, V1),
9832 getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));
9836 // AVX2 provides a direct instruction for permuting a single input across
9838 if (isSingleInputShuffleMask(Mask))
9839 return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,
9840 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
9842 // Try to use shift instructions.
9844 lowerVectorShuffleAsShift(DL, MVT::v4i64, V1, V2, Mask, DAG))
9847 // Use dedicated unpack instructions for masks that match their pattern.
9848 if (isShuffleEquivalent(V1, V2, Mask, {0, 4, 2, 6}))
9849 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V1, V2);
9850 if (isShuffleEquivalent(V1, V2, Mask, {1, 5, 3, 7}))
9851 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V1, V2);
9852 if (isShuffleEquivalent(V1, V2, Mask, {4, 0, 6, 2}))
9853 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v4i64, V2, V1);
9854 if (isShuffleEquivalent(V1, V2, Mask, {5, 1, 7, 3}))
9855 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v4i64, V2, V1);
9857 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9858 // shuffle. However, if we have AVX2 and either inputs are already in place,
9859 // we will be able to shuffle even across lanes the other input in a single
9860 // instruction so skip this pattern.
9861 if (!(Subtarget->hasAVX2() && (isShuffleMaskInputInPlace(0, Mask) ||
9862 isShuffleMaskInputInPlace(1, Mask))))
9863 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9864 DL, MVT::v4i64, V1, V2, Mask, Subtarget, DAG))
9867 // Otherwise fall back on generic blend lowering.
9868 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v4i64, V1, V2,
9872 /// \brief Handle lowering of 8-lane 32-bit floating point shuffles.
9874 /// Also ends up handling lowering of 8-lane 32-bit integer shuffles when AVX2
9875 /// isn't available.
9876 static SDValue lowerV8F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9877 const X86Subtarget *Subtarget,
9878 SelectionDAG &DAG) {
9880 assert(V1.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9881 assert(V2.getSimpleValueType() == MVT::v8f32 && "Bad operand type!");
9882 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9883 ArrayRef<int> Mask = SVOp->getMask();
9884 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9886 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8f32, V1, V2, Mask,
9890 // Check for being able to broadcast a single element.
9891 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8f32, V1,
9892 Mask, Subtarget, DAG))
9895 // If the shuffle mask is repeated in each 128-bit lane, we have many more
9896 // options to efficiently lower the shuffle.
9897 SmallVector<int, 4> RepeatedMask;
9898 if (is128BitLaneRepeatedShuffleMask(MVT::v8f32, Mask, RepeatedMask)) {
9899 assert(RepeatedMask.size() == 4 &&
9900 "Repeated masks must be half the mask width!");
9902 // Use even/odd duplicate instructions for masks that match their pattern.
9903 if (isShuffleEquivalent(V1, V2, Mask, {0, 0, 2, 2, 4, 4, 6, 6}))
9904 return DAG.getNode(X86ISD::MOVSLDUP, DL, MVT::v8f32, V1);
9905 if (isShuffleEquivalent(V1, V2, Mask, {1, 1, 3, 3, 5, 5, 7, 7}))
9906 return DAG.getNode(X86ISD::MOVSHDUP, DL, MVT::v8f32, V1);
9908 if (isSingleInputShuffleMask(Mask))
9909 return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,
9910 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
9912 // Use dedicated unpack instructions for masks that match their pattern.
9913 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
9914 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V1, V2);
9915 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
9916 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V1, V2);
9917 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
9918 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f32, V2, V1);
9919 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
9920 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f32, V2, V1);
9922 // Otherwise, fall back to a SHUFPS sequence. Here it is important that we
9923 // have already handled any direct blends. We also need to squash the
9924 // repeated mask into a simulated v4f32 mask.
9925 for (int i = 0; i < 4; ++i)
9926 if (RepeatedMask[i] >= 8)
9927 RepeatedMask[i] -= 4;
9928 return lowerVectorShuffleWithSHUFPS(DL, MVT::v8f32, RepeatedMask, V1, V2, DAG);
9931 // If we have a single input shuffle with different shuffle patterns in the
9932 // two 128-bit lanes use the variable mask to VPERMILPS.
9933 if (isSingleInputShuffleMask(Mask)) {
9934 SDValue VPermMask[8];
9935 for (int i = 0; i < 8; ++i)
9936 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
9937 : DAG.getConstant(Mask[i], DL, MVT::i32);
9938 if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))
9940 X86ISD::VPERMILPV, DL, MVT::v8f32, V1,
9941 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask));
9943 if (Subtarget->hasAVX2())
9945 X86ISD::VPERMV, DL, MVT::v8f32,
9946 DAG.getBitcast(MVT::v8f32, DAG.getNode(ISD::BUILD_VECTOR, DL,
9947 MVT::v8i32, VPermMask)),
9950 // Otherwise, fall back.
9951 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v8f32, V1, V2, Mask,
9955 // Try to simplify this by merging 128-bit lanes to enable a lane-based
9957 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
9958 DL, MVT::v8f32, V1, V2, Mask, Subtarget, DAG))
9961 // If we have AVX2 then we always want to lower with a blend because at v8 we
9962 // can fully permute the elements.
9963 if (Subtarget->hasAVX2())
9964 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8f32, V1, V2,
9967 // Otherwise fall back on generic lowering.
9968 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v8f32, V1, V2, Mask, DAG);
9971 /// \brief Handle lowering of 8-lane 32-bit integer shuffles.
9973 /// This routine is only called when we have AVX2 and thus a reasonable
9974 /// instruction set for v8i32 shuffling..
9975 static SDValue lowerV8I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
9976 const X86Subtarget *Subtarget,
9977 SelectionDAG &DAG) {
9979 assert(V1.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9980 assert(V2.getSimpleValueType() == MVT::v8i32 && "Bad operand type!");
9981 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
9982 ArrayRef<int> Mask = SVOp->getMask();
9983 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
9984 assert(Subtarget->hasAVX2() && "We can only lower v8i32 with AVX2!");
9986 // Whenever we can lower this as a zext, that instruction is strictly faster
9987 // than any alternative. It also allows us to fold memory operands into the
9988 // shuffle in many cases.
9989 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v8i32, V1, V2,
9990 Mask, Subtarget, DAG))
9993 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v8i32, V1, V2, Mask,
9997 // Check for being able to broadcast a single element.
9998 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v8i32, V1,
9999 Mask, Subtarget, DAG))
10002 // If the shuffle mask is repeated in each 128-bit lane we can use more
10003 // efficient instructions that mirror the shuffles across the two 128-bit
10005 SmallVector<int, 4> RepeatedMask;
10006 if (is128BitLaneRepeatedShuffleMask(MVT::v8i32, Mask, RepeatedMask)) {
10007 assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");
10008 if (isSingleInputShuffleMask(Mask))
10009 return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,
10010 getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));
10012 // Use dedicated unpack instructions for masks that match their pattern.
10013 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))
10014 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V1, V2);
10015 if (isShuffleEquivalent(V1, V2, Mask, {2, 10, 3, 11, 6, 14, 7, 15}))
10016 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V1, V2);
10017 if (isShuffleEquivalent(V1, V2, Mask, {8, 0, 9, 1, 12, 4, 13, 5}))
10018 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i32, V2, V1);
10019 if (isShuffleEquivalent(V1, V2, Mask, {10, 2, 11, 3, 14, 6, 15, 7}))
10020 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i32, V2, V1);
10023 // Try to use shift instructions.
10024 if (SDValue Shift =
10025 lowerVectorShuffleAsShift(DL, MVT::v8i32, V1, V2, Mask, DAG))
10028 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10029 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10032 // If the shuffle patterns aren't repeated but it is a single input, directly
10033 // generate a cross-lane VPERMD instruction.
10034 if (isSingleInputShuffleMask(Mask)) {
10035 SDValue VPermMask[8];
10036 for (int i = 0; i < 8; ++i)
10037 VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)
10038 : DAG.getConstant(Mask[i], DL, MVT::i32);
10039 return DAG.getNode(
10040 X86ISD::VPERMV, DL, MVT::v8i32,
10041 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);
10044 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10046 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10047 DL, MVT::v8i32, V1, V2, Mask, Subtarget, DAG))
10050 // Otherwise fall back on generic blend lowering.
10051 return lowerVectorShuffleAsDecomposedShuffleBlend(DL, MVT::v8i32, V1, V2,
10055 /// \brief Handle lowering of 16-lane 16-bit integer shuffles.
10057 /// This routine is only called when we have AVX2 and thus a reasonable
10058 /// instruction set for v16i16 shuffling..
10059 static SDValue lowerV16I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10060 const X86Subtarget *Subtarget,
10061 SelectionDAG &DAG) {
10063 assert(V1.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10064 assert(V2.getSimpleValueType() == MVT::v16i16 && "Bad operand type!");
10065 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10066 ArrayRef<int> Mask = SVOp->getMask();
10067 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10068 assert(Subtarget->hasAVX2() && "We can only lower v16i16 with AVX2!");
10070 // Whenever we can lower this as a zext, that instruction is strictly faster
10071 // than any alternative. It also allows us to fold memory operands into the
10072 // shuffle in many cases.
10073 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v16i16, V1, V2,
10074 Mask, Subtarget, DAG))
10077 // Check for being able to broadcast a single element.
10078 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v16i16, V1,
10079 Mask, Subtarget, DAG))
10082 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v16i16, V1, V2, Mask,
10086 // Use dedicated unpack instructions for masks that match their pattern.
10087 if (isShuffleEquivalent(V1, V2, Mask,
10088 {// First 128-bit lane:
10089 0, 16, 1, 17, 2, 18, 3, 19,
10090 // Second 128-bit lane:
10091 8, 24, 9, 25, 10, 26, 11, 27}))
10092 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i16, V1, V2);
10093 if (isShuffleEquivalent(V1, V2, Mask,
10094 {// First 128-bit lane:
10095 4, 20, 5, 21, 6, 22, 7, 23,
10096 // Second 128-bit lane:
10097 12, 28, 13, 29, 14, 30, 15, 31}))
10098 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i16, V1, V2);
10100 // Try to use shift instructions.
10101 if (SDValue Shift =
10102 lowerVectorShuffleAsShift(DL, MVT::v16i16, V1, V2, Mask, DAG))
10105 // Try to use byte rotation instructions.
10106 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10107 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10110 if (isSingleInputShuffleMask(Mask)) {
10111 // There are no generalized cross-lane shuffle operations available on i16
10113 if (is128BitLaneCrossingShuffleMask(MVT::v16i16, Mask))
10114 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v16i16, V1, V2,
10117 SmallVector<int, 8> RepeatedMask;
10118 if (is128BitLaneRepeatedShuffleMask(MVT::v16i16, Mask, RepeatedMask)) {
10119 // As this is a single-input shuffle, the repeated mask should be
10120 // a strictly valid v8i16 mask that we can pass through to the v8i16
10121 // lowering to handle even the v16 case.
10122 return lowerV8I16GeneralSingleInputVectorShuffle(
10123 DL, MVT::v16i16, V1, RepeatedMask, Subtarget, DAG);
10126 SDValue PSHUFBMask[32];
10127 for (int i = 0; i < 16; ++i) {
10128 if (Mask[i] == -1) {
10129 PSHUFBMask[2 * i] = PSHUFBMask[2 * i + 1] = DAG.getUNDEF(MVT::i8);
10133 int M = i < 8 ? Mask[i] : Mask[i] - 8;
10134 assert(M >= 0 && M < 8 && "Invalid single-input mask!");
10135 PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);
10136 PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);
10138 return DAG.getBitcast(MVT::v16i16,
10139 DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8,
10140 DAG.getBitcast(MVT::v32i8, V1),
10141 DAG.getNode(ISD::BUILD_VECTOR, DL,
10142 MVT::v32i8, PSHUFBMask)));
10145 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10147 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10148 DL, MVT::v16i16, V1, V2, Mask, Subtarget, DAG))
10151 // Otherwise fall back on generic lowering.
10152 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v16i16, V1, V2, Mask, DAG);
10155 /// \brief Handle lowering of 32-lane 8-bit integer shuffles.
10157 /// This routine is only called when we have AVX2 and thus a reasonable
10158 /// instruction set for v32i8 shuffling..
10159 static SDValue lowerV32I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10160 const X86Subtarget *Subtarget,
10161 SelectionDAG &DAG) {
10163 assert(V1.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10164 assert(V2.getSimpleValueType() == MVT::v32i8 && "Bad operand type!");
10165 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10166 ArrayRef<int> Mask = SVOp->getMask();
10167 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10168 assert(Subtarget->hasAVX2() && "We can only lower v32i8 with AVX2!");
10170 // Whenever we can lower this as a zext, that instruction is strictly faster
10171 // than any alternative. It also allows us to fold memory operands into the
10172 // shuffle in many cases.
10173 if (SDValue ZExt = lowerVectorShuffleAsZeroOrAnyExtend(DL, MVT::v32i8, V1, V2,
10174 Mask, Subtarget, DAG))
10177 // Check for being able to broadcast a single element.
10178 if (SDValue Broadcast = lowerVectorShuffleAsBroadcast(DL, MVT::v32i8, V1,
10179 Mask, Subtarget, DAG))
10182 if (SDValue Blend = lowerVectorShuffleAsBlend(DL, MVT::v32i8, V1, V2, Mask,
10186 // Use dedicated unpack instructions for masks that match their pattern.
10187 // Note that these are repeated 128-bit lane unpacks, not unpacks across all
10189 if (isShuffleEquivalent(
10191 {// First 128-bit lane:
10192 0, 32, 1, 33, 2, 34, 3, 35, 4, 36, 5, 37, 6, 38, 7, 39,
10193 // Second 128-bit lane:
10194 16, 48, 17, 49, 18, 50, 19, 51, 20, 52, 21, 53, 22, 54, 23, 55}))
10195 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v32i8, V1, V2);
10196 if (isShuffleEquivalent(
10198 {// First 128-bit lane:
10199 8, 40, 9, 41, 10, 42, 11, 43, 12, 44, 13, 45, 14, 46, 15, 47,
10200 // Second 128-bit lane:
10201 24, 56, 25, 57, 26, 58, 27, 59, 28, 60, 29, 61, 30, 62, 31, 63}))
10202 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v32i8, V1, V2);
10204 // Try to use shift instructions.
10205 if (SDValue Shift =
10206 lowerVectorShuffleAsShift(DL, MVT::v32i8, V1, V2, Mask, DAG))
10209 // Try to use byte rotation instructions.
10210 if (SDValue Rotate = lowerVectorShuffleAsByteRotate(
10211 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10214 if (isSingleInputShuffleMask(Mask)) {
10215 // There are no generalized cross-lane shuffle operations available on i8
10217 if (is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask))
10218 return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v32i8, V1, V2,
10221 SDValue PSHUFBMask[32];
10222 for (int i = 0; i < 32; ++i)
10225 ? DAG.getUNDEF(MVT::i8)
10226 : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,
10229 return DAG.getNode(
10230 X86ISD::PSHUFB, DL, MVT::v32i8, V1,
10231 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask));
10234 // Try to simplify this by merging 128-bit lanes to enable a lane-based
10236 if (SDValue Result = lowerVectorShuffleByMerging128BitLanes(
10237 DL, MVT::v32i8, V1, V2, Mask, Subtarget, DAG))
10240 // Otherwise fall back on generic lowering.
10241 return lowerVectorShuffleAsSplitOrBlend(DL, MVT::v32i8, V1, V2, Mask, DAG);
10244 /// \brief High-level routine to lower various 256-bit x86 vector shuffles.
10246 /// This routine either breaks down the specific type of a 256-bit x86 vector
10247 /// shuffle or splits it into two 128-bit shuffles and fuses the results back
10248 /// together based on the available instructions.
10249 static SDValue lower256BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10250 MVT VT, const X86Subtarget *Subtarget,
10251 SelectionDAG &DAG) {
10253 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10254 ArrayRef<int> Mask = SVOp->getMask();
10256 // If we have a single input to the zero element, insert that into V1 if we
10257 // can do so cheaply.
10258 int NumElts = VT.getVectorNumElements();
10259 int NumV2Elements = std::count_if(Mask.begin(), Mask.end(), [NumElts](int M) {
10260 return M >= NumElts;
10263 if (NumV2Elements == 1 && Mask[0] >= NumElts)
10264 if (SDValue Insertion = lowerVectorShuffleAsElementInsertion(
10265 DL, VT, V1, V2, Mask, Subtarget, DAG))
10268 // There is a really nice hard cut-over between AVX1 and AVX2 that means we can
10269 // check for those subtargets here and avoid much of the subtarget querying in
10270 // the per-vector-type lowering routines. With AVX1 we have essentially *zero*
10271 // ability to manipulate a 256-bit vector with integer types. Since we'll use
10272 // floating point types there eventually, just immediately cast everything to
10273 // a float and operate entirely in that domain.
10274 if (VT.isInteger() && !Subtarget->hasAVX2()) {
10275 int ElementBits = VT.getScalarSizeInBits();
10276 if (ElementBits < 32)
10277 // No floating point type available, decompose into 128-bit vectors.
10278 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10280 MVT FpVT = MVT::getVectorVT(MVT::getFloatingPointVT(ElementBits),
10281 VT.getVectorNumElements());
10282 V1 = DAG.getBitcast(FpVT, V1);
10283 V2 = DAG.getBitcast(FpVT, V2);
10284 return DAG.getBitcast(VT, DAG.getVectorShuffle(FpVT, DL, V1, V2, Mask));
10287 switch (VT.SimpleTy) {
10289 return lowerV4F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10291 return lowerV4I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10293 return lowerV8F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10295 return lowerV8I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10297 return lowerV16I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10299 return lowerV32I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10302 llvm_unreachable("Not a valid 256-bit x86 vector type!");
10306 /// \brief Handle lowering of 8-lane 64-bit floating point shuffles.
10307 static SDValue lowerV8F64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10308 const X86Subtarget *Subtarget,
10309 SelectionDAG &DAG) {
10311 assert(V1.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10312 assert(V2.getSimpleValueType() == MVT::v8f64 && "Bad operand type!");
10313 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10314 ArrayRef<int> Mask = SVOp->getMask();
10315 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10317 // X86 has dedicated unpack instructions that can handle specific blend
10318 // operations: UNPCKH and UNPCKL.
10319 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10320 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8f64, V1, V2);
10321 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10322 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8f64, V1, V2);
10324 // FIXME: Implement direct support for this type!
10325 return splitAndLowerVectorShuffle(DL, MVT::v8f64, V1, V2, Mask, DAG);
10328 /// \brief Handle lowering of 16-lane 32-bit floating point shuffles.
10329 static SDValue lowerV16F32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10330 const X86Subtarget *Subtarget,
10331 SelectionDAG &DAG) {
10333 assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10334 assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");
10335 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10336 ArrayRef<int> Mask = SVOp->getMask();
10337 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10339 // Use dedicated unpack instructions for masks that match their pattern.
10340 if (isShuffleEquivalent(V1, V2, Mask,
10341 {// First 128-bit lane.
10342 0, 16, 1, 17, 4, 20, 5, 21,
10343 // Second 128-bit lane.
10344 8, 24, 9, 25, 12, 28, 13, 29}))
10345 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);
10346 if (isShuffleEquivalent(V1, V2, Mask,
10347 {// First 128-bit lane.
10348 2, 18, 3, 19, 6, 22, 7, 23,
10349 // Second 128-bit lane.
10350 10, 26, 11, 27, 14, 30, 15, 31}))
10351 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);
10353 // FIXME: Implement direct support for this type!
10354 return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);
10357 /// \brief Handle lowering of 8-lane 64-bit integer shuffles.
10358 static SDValue lowerV8I64VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10359 const X86Subtarget *Subtarget,
10360 SelectionDAG &DAG) {
10362 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10363 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
10364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10365 ArrayRef<int> Mask = SVOp->getMask();
10366 assert(Mask.size() == 8 && "Unexpected mask size for v8 shuffle!");
10368 // X86 has dedicated unpack instructions that can handle specific blend
10369 // operations: UNPCKH and UNPCKL.
10370 if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 2, 10, 4, 12, 6, 14}))
10371 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);
10372 if (isShuffleEquivalent(V1, V2, Mask, {1, 9, 3, 11, 5, 13, 7, 15}))
10373 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);
10375 // FIXME: Implement direct support for this type!
10376 return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);
10379 /// \brief Handle lowering of 16-lane 32-bit integer shuffles.
10380 static SDValue lowerV16I32VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10381 const X86Subtarget *Subtarget,
10382 SelectionDAG &DAG) {
10384 assert(V1.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10385 assert(V2.getSimpleValueType() == MVT::v16i32 && "Bad operand type!");
10386 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10387 ArrayRef<int> Mask = SVOp->getMask();
10388 assert(Mask.size() == 16 && "Unexpected mask size for v16 shuffle!");
10390 // Use dedicated unpack instructions for masks that match their pattern.
10391 if (isShuffleEquivalent(V1, V2, Mask,
10392 {// First 128-bit lane.
10393 0, 16, 1, 17, 4, 20, 5, 21,
10394 // Second 128-bit lane.
10395 8, 24, 9, 25, 12, 28, 13, 29}))
10396 return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16i32, V1, V2);
10397 if (isShuffleEquivalent(V1, V2, Mask,
10398 {// First 128-bit lane.
10399 2, 18, 3, 19, 6, 22, 7, 23,
10400 // Second 128-bit lane.
10401 10, 26, 11, 27, 14, 30, 15, 31}))
10402 return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16i32, V1, V2);
10404 // FIXME: Implement direct support for this type!
10405 return splitAndLowerVectorShuffle(DL, MVT::v16i32, V1, V2, Mask, DAG);
10408 /// \brief Handle lowering of 32-lane 16-bit integer shuffles.
10409 static SDValue lowerV32I16VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10410 const X86Subtarget *Subtarget,
10411 SelectionDAG &DAG) {
10413 assert(V1.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10414 assert(V2.getSimpleValueType() == MVT::v32i16 && "Bad operand type!");
10415 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10416 ArrayRef<int> Mask = SVOp->getMask();
10417 assert(Mask.size() == 32 && "Unexpected mask size for v32 shuffle!");
10418 assert(Subtarget->hasBWI() && "We can only lower v32i16 with AVX-512-BWI!");
10420 // FIXME: Implement direct support for this type!
10421 return splitAndLowerVectorShuffle(DL, MVT::v32i16, V1, V2, Mask, DAG);
10424 /// \brief Handle lowering of 64-lane 8-bit integer shuffles.
10425 static SDValue lowerV64I8VectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10426 const X86Subtarget *Subtarget,
10427 SelectionDAG &DAG) {
10429 assert(V1.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10430 assert(V2.getSimpleValueType() == MVT::v64i8 && "Bad operand type!");
10431 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10432 ArrayRef<int> Mask = SVOp->getMask();
10433 assert(Mask.size() == 64 && "Unexpected mask size for v64 shuffle!");
10434 assert(Subtarget->hasBWI() && "We can only lower v64i8 with AVX-512-BWI!");
10436 // FIXME: Implement direct support for this type!
10437 return splitAndLowerVectorShuffle(DL, MVT::v64i8, V1, V2, Mask, DAG);
10440 /// \brief High-level routine to lower various 512-bit x86 vector shuffles.
10442 /// This routine either breaks down the specific type of a 512-bit x86 vector
10443 /// shuffle or splits it into two 256-bit shuffles and fuses the results back
10444 /// together based on the available instructions.
10445 static SDValue lower512BitVectorShuffle(SDValue Op, SDValue V1, SDValue V2,
10446 MVT VT, const X86Subtarget *Subtarget,
10447 SelectionDAG &DAG) {
10449 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10450 ArrayRef<int> Mask = SVOp->getMask();
10451 assert(Subtarget->hasAVX512() &&
10452 "Cannot lower 512-bit vectors w/ basic ISA!");
10454 // Check for being able to broadcast a single element.
10455 if (SDValue Broadcast =
10456 lowerVectorShuffleAsBroadcast(DL, VT, V1, Mask, Subtarget, DAG))
10459 // Dispatch to each element type for lowering. If we don't have supprot for
10460 // specific element type shuffles at 512 bits, immediately split them and
10461 // lower them. Each lowering routine of a given type is allowed to assume that
10462 // the requisite ISA extensions for that element type are available.
10463 switch (VT.SimpleTy) {
10465 return lowerV8F64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10467 return lowerV16F32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10469 return lowerV8I64VectorShuffle(Op, V1, V2, Subtarget, DAG);
10471 return lowerV16I32VectorShuffle(Op, V1, V2, Subtarget, DAG);
10473 if (Subtarget->hasBWI())
10474 return lowerV32I16VectorShuffle(Op, V1, V2, Subtarget, DAG);
10477 if (Subtarget->hasBWI())
10478 return lowerV64I8VectorShuffle(Op, V1, V2, Subtarget, DAG);
10482 llvm_unreachable("Not a valid 512-bit x86 vector type!");
10485 // Otherwise fall back on splitting.
10486 return splitAndLowerVectorShuffle(DL, VT, V1, V2, Mask, DAG);
10489 /// \brief Top-level lowering for x86 vector shuffles.
10491 /// This handles decomposition, canonicalization, and lowering of all x86
10492 /// vector shuffles. Most of the specific lowering strategies are encapsulated
10493 /// above in helper routines. The canonicalization attempts to widen shuffles
10494 /// to involve fewer lanes of wider elements, consolidate symmetric patterns
10495 /// s.t. only one of the two inputs needs to be tested, etc.
10496 static SDValue lowerVectorShuffle(SDValue Op, const X86Subtarget *Subtarget,
10497 SelectionDAG &DAG) {
10498 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
10499 ArrayRef<int> Mask = SVOp->getMask();
10500 SDValue V1 = Op.getOperand(0);
10501 SDValue V2 = Op.getOperand(1);
10502 MVT VT = Op.getSimpleValueType();
10503 int NumElements = VT.getVectorNumElements();
10506 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
10508 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
10509 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
10510 if (V1IsUndef && V2IsUndef)
10511 return DAG.getUNDEF(VT);
10513 // When we create a shuffle node we put the UNDEF node to second operand,
10514 // but in some cases the first operand may be transformed to UNDEF.
10515 // In this case we should just commute the node.
10517 return DAG.getCommutedVectorShuffle(*SVOp);
10519 // Check for non-undef masks pointing at an undef vector and make the masks
10520 // undef as well. This makes it easier to match the shuffle based solely on
10524 if (M >= NumElements) {
10525 SmallVector<int, 8> NewMask(Mask.begin(), Mask.end());
10526 for (int &M : NewMask)
10527 if (M >= NumElements)
10529 return DAG.getVectorShuffle(VT, dl, V1, V2, NewMask);
10532 // We actually see shuffles that are entirely re-arrangements of a set of
10533 // zero inputs. This mostly happens while decomposing complex shuffles into
10534 // simple ones. Directly lower these as a buildvector of zeros.
10535 SmallBitVector Zeroable = computeZeroableShuffleElements(Mask, V1, V2);
10536 if (Zeroable.all())
10537 return getZeroVector(VT, Subtarget, DAG, dl);
10539 // Try to collapse shuffles into using a vector type with fewer elements but
10540 // wider element types. We cap this to not form integers or floating point
10541 // elements wider than 64 bits, but it might be interesting to form i128
10542 // integers to handle flipping the low and high halves of AVX 256-bit vectors.
10543 SmallVector<int, 16> WidenedMask;
10544 if (VT.getScalarSizeInBits() < 64 &&
10545 canWidenShuffleElements(Mask, WidenedMask)) {
10546 MVT NewEltVT = VT.isFloatingPoint()
10547 ? MVT::getFloatingPointVT(VT.getScalarSizeInBits() * 2)
10548 : MVT::getIntegerVT(VT.getScalarSizeInBits() * 2);
10549 MVT NewVT = MVT::getVectorVT(NewEltVT, VT.getVectorNumElements() / 2);
10550 // Make sure that the new vector type is legal. For example, v2f64 isn't
10552 if (DAG.getTargetLoweringInfo().isTypeLegal(NewVT)) {
10553 V1 = DAG.getBitcast(NewVT, V1);
10554 V2 = DAG.getBitcast(NewVT, V2);
10555 return DAG.getBitcast(
10556 VT, DAG.getVectorShuffle(NewVT, dl, V1, V2, WidenedMask));
10560 int NumV1Elements = 0, NumUndefElements = 0, NumV2Elements = 0;
10561 for (int M : SVOp->getMask())
10563 ++NumUndefElements;
10564 else if (M < NumElements)
10569 // Commute the shuffle as needed such that more elements come from V1 than
10570 // V2. This allows us to match the shuffle pattern strictly on how many
10571 // elements come from V1 without handling the symmetric cases.
10572 if (NumV2Elements > NumV1Elements)
10573 return DAG.getCommutedVectorShuffle(*SVOp);
10575 // When the number of V1 and V2 elements are the same, try to minimize the
10576 // number of uses of V2 in the low half of the vector. When that is tied,
10577 // ensure that the sum of indices for V1 is equal to or lower than the sum
10578 // indices for V2. When those are equal, try to ensure that the number of odd
10579 // indices for V1 is lower than the number of odd indices for V2.
10580 if (NumV1Elements == NumV2Elements) {
10581 int LowV1Elements = 0, LowV2Elements = 0;
10582 for (int M : SVOp->getMask().slice(0, NumElements / 2))
10583 if (M >= NumElements)
10587 if (LowV2Elements > LowV1Elements) {
10588 return DAG.getCommutedVectorShuffle(*SVOp);
10589 } else if (LowV2Elements == LowV1Elements) {
10590 int SumV1Indices = 0, SumV2Indices = 0;
10591 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10592 if (SVOp->getMask()[i] >= NumElements)
10594 else if (SVOp->getMask()[i] >= 0)
10596 if (SumV2Indices < SumV1Indices) {
10597 return DAG.getCommutedVectorShuffle(*SVOp);
10598 } else if (SumV2Indices == SumV1Indices) {
10599 int NumV1OddIndices = 0, NumV2OddIndices = 0;
10600 for (int i = 0, Size = SVOp->getMask().size(); i < Size; ++i)
10601 if (SVOp->getMask()[i] >= NumElements)
10602 NumV2OddIndices += i % 2;
10603 else if (SVOp->getMask()[i] >= 0)
10604 NumV1OddIndices += i % 2;
10605 if (NumV2OddIndices < NumV1OddIndices)
10606 return DAG.getCommutedVectorShuffle(*SVOp);
10611 // For each vector width, delegate to a specialized lowering routine.
10612 if (VT.getSizeInBits() == 128)
10613 return lower128BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10615 if (VT.getSizeInBits() == 256)
10616 return lower256BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10618 // Force AVX-512 vectors to be scalarized for now.
10619 // FIXME: Implement AVX-512 support!
10620 if (VT.getSizeInBits() == 512)
10621 return lower512BitVectorShuffle(Op, V1, V2, VT, Subtarget, DAG);
10623 llvm_unreachable("Unimplemented!");
10626 // This function assumes its argument is a BUILD_VECTOR of constants or
10627 // undef SDNodes. i.e: ISD::isBuildVectorOfConstantSDNodes(BuildVector) is
10629 static bool BUILD_VECTORtoBlendMask(BuildVectorSDNode *BuildVector,
10630 unsigned &MaskValue) {
10632 unsigned NumElems = BuildVector->getNumOperands();
10633 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
10634 unsigned NumLanes = (NumElems - 1) / 8 + 1;
10635 unsigned NumElemsInLane = NumElems / NumLanes;
10637 // Blend for v16i16 should be symetric for the both lanes.
10638 for (unsigned i = 0; i < NumElemsInLane; ++i) {
10639 SDValue EltCond = BuildVector->getOperand(i);
10640 SDValue SndLaneEltCond =
10641 (NumLanes == 2) ? BuildVector->getOperand(i + NumElemsInLane) : EltCond;
10643 int Lane1Cond = -1, Lane2Cond = -1;
10644 if (isa<ConstantSDNode>(EltCond))
10645 Lane1Cond = !isZero(EltCond);
10646 if (isa<ConstantSDNode>(SndLaneEltCond))
10647 Lane2Cond = !isZero(SndLaneEltCond);
10649 if (Lane1Cond == Lane2Cond || Lane2Cond < 0)
10650 // Lane1Cond != 0, means we want the first argument.
10651 // Lane1Cond == 0, means we want the second argument.
10652 // The encoding of this argument is 0 for the first argument, 1
10653 // for the second. Therefore, invert the condition.
10654 MaskValue |= !Lane1Cond << i;
10655 else if (Lane1Cond < 0)
10656 MaskValue |= !Lane2Cond << i;
10663 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
10664 static SDValue lowerVSELECTtoVectorShuffle(SDValue Op,
10665 const X86Subtarget *Subtarget,
10666 SelectionDAG &DAG) {
10667 SDValue Cond = Op.getOperand(0);
10668 SDValue LHS = Op.getOperand(1);
10669 SDValue RHS = Op.getOperand(2);
10671 MVT VT = Op.getSimpleValueType();
10673 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
10675 auto *CondBV = cast<BuildVectorSDNode>(Cond);
10677 // Only non-legal VSELECTs reach this lowering, convert those into generic
10678 // shuffles and re-use the shuffle lowering path for blends.
10679 SmallVector<int, 32> Mask;
10680 for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
10681 SDValue CondElt = CondBV->getOperand(i);
10683 isa<ConstantSDNode>(CondElt) ? i + (isZero(CondElt) ? Size : 0) : -1);
10685 return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
10688 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
10689 // A vselect where all conditions and data are constants can be optimized into
10690 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
10691 if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
10692 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
10693 ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
10696 // Try to lower this to a blend-style vector shuffle. This can handle all
10697 // constant condition cases.
10698 if (SDValue BlendOp = lowerVSELECTtoVectorShuffle(Op, Subtarget, DAG))
10701 // Variable blends are only legal from SSE4.1 onward.
10702 if (!Subtarget->hasSSE41())
10705 // Only some types will be legal on some subtargets. If we can emit a legal
10706 // VSELECT-matching blend, return Op, and but if we need to expand, return
10708 switch (Op.getSimpleValueType().SimpleTy) {
10710 // Most of the vector types have blends past SSE4.1.
10714 // The byte blends for AVX vectors were introduced only in AVX2.
10715 if (Subtarget->hasAVX2())
10722 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
10723 if (Subtarget->hasBWI() && Subtarget->hasVLX())
10726 // FIXME: We should custom lower this by fixing the condition and using i8
10732 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
10733 MVT VT = Op.getSimpleValueType();
10736 if (!Op.getOperand(0).getSimpleValueType().is128BitVector())
10739 if (VT.getSizeInBits() == 8) {
10740 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
10741 Op.getOperand(0), Op.getOperand(1));
10742 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10743 DAG.getValueType(VT));
10744 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10747 if (VT.getSizeInBits() == 16) {
10748 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10749 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
10751 return DAG.getNode(
10752 ISD::TRUNCATE, dl, MVT::i16,
10753 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10754 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10755 Op.getOperand(1)));
10756 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
10757 Op.getOperand(0), Op.getOperand(1));
10758 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
10759 DAG.getValueType(VT));
10760 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10763 if (VT == MVT::f32) {
10764 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
10765 // the result back to FR32 register. It's only worth matching if the
10766 // result has a single use which is a store or a bitcast to i32. And in
10767 // the case of a store, it's not worth it if the index is a constant 0,
10768 // because a MOVSSmr can be used instead, which is smaller and faster.
10769 if (!Op.hasOneUse())
10771 SDNode *User = *Op.getNode()->use_begin();
10772 if ((User->getOpcode() != ISD::STORE ||
10773 (isa<ConstantSDNode>(Op.getOperand(1)) &&
10774 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
10775 (User->getOpcode() != ISD::BITCAST ||
10776 User->getValueType(0) != MVT::i32))
10778 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10779 DAG.getBitcast(MVT::v4i32, Op.getOperand(0)),
10781 return DAG.getBitcast(MVT::f32, Extract);
10784 if (VT == MVT::i32 || VT == MVT::i64) {
10785 // ExtractPS/pextrq works with constant index.
10786 if (isa<ConstantSDNode>(Op.getOperand(1)))
10792 /// Extract one bit from mask vector, like v16i1 or v8i1.
10793 /// AVX-512 feature.
10795 X86TargetLowering::ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const {
10796 SDValue Vec = Op.getOperand(0);
10798 MVT VecVT = Vec.getSimpleValueType();
10799 SDValue Idx = Op.getOperand(1);
10800 MVT EltVT = Op.getSimpleValueType();
10802 assert((EltVT == MVT::i1) && "Unexpected operands in ExtractBitFromMaskVector");
10803 assert((VecVT.getVectorNumElements() <= 16 || Subtarget->hasBWI()) &&
10804 "Unexpected vector type in ExtractBitFromMaskVector");
10806 // variable index can't be handled in mask registers,
10807 // extend vector to VR512
10808 if (!isa<ConstantSDNode>(Idx)) {
10809 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10810 SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
10811 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
10812 ExtVT.getVectorElementType(), Ext, Idx);
10813 return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
10816 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10817 const TargetRegisterClass* rc = getRegClassFor(VecVT);
10818 if (!Subtarget->hasDQI() && (VecVT.getVectorNumElements() <= 8))
10819 rc = getRegClassFor(MVT::v16i1);
10820 unsigned MaxSift = rc->getSize()*8 - 1;
10821 Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,
10822 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
10823 Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,
10824 DAG.getConstant(MaxSift, dl, MVT::i8));
10825 return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,
10826 DAG.getIntPtrConstant(0, dl));
10830 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
10831 SelectionDAG &DAG) const {
10833 SDValue Vec = Op.getOperand(0);
10834 MVT VecVT = Vec.getSimpleValueType();
10835 SDValue Idx = Op.getOperand(1);
10837 if (Op.getSimpleValueType() == MVT::i1)
10838 return ExtractBitFromMaskVector(Op, DAG);
10840 if (!isa<ConstantSDNode>(Idx)) {
10841 if (VecVT.is512BitVector() ||
10842 (VecVT.is256BitVector() && Subtarget->hasInt256() &&
10843 VecVT.getVectorElementType().getSizeInBits() == 32)) {
10846 MVT::getIntegerVT(VecVT.getVectorElementType().getSizeInBits());
10847 MVT MaskVT = MVT::getVectorVT(MaskEltVT, VecVT.getSizeInBits() /
10848 MaskEltVT.getSizeInBits());
10850 Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);
10851 SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,
10852 getZeroVector(MaskVT, Subtarget, DAG, dl),
10853 Idx, DAG.getConstant(0, dl, getPointerTy()));
10854 SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);
10855 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),
10856 Perm, DAG.getConstant(0, dl, getPointerTy()));
10861 // If this is a 256-bit vector result, first extract the 128-bit vector and
10862 // then extract the element from the 128-bit vector.
10863 if (VecVT.is256BitVector() || VecVT.is512BitVector()) {
10865 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10866 // Get the 128-bit vector.
10867 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
10868 MVT EltVT = VecVT.getVectorElementType();
10870 unsigned ElemsPerChunk = 128 / EltVT.getSizeInBits();
10872 //if (IdxVal >= NumElems/2)
10873 // IdxVal -= NumElems/2;
10874 IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;
10875 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
10876 DAG.getConstant(IdxVal, dl, MVT::i32));
10879 assert(VecVT.is128BitVector() && "Unexpected vector length");
10881 if (Subtarget->hasSSE41())
10882 if (SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG))
10885 MVT VT = Op.getSimpleValueType();
10886 // TODO: handle v16i8.
10887 if (VT.getSizeInBits() == 16) {
10888 SDValue Vec = Op.getOperand(0);
10889 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10891 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
10892 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
10893 DAG.getBitcast(MVT::v4i32, Vec),
10894 Op.getOperand(1)));
10895 // Transform it so it match pextrw which produces a 32-bit result.
10896 MVT EltVT = MVT::i32;
10897 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
10898 Op.getOperand(0), Op.getOperand(1));
10899 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
10900 DAG.getValueType(VT));
10901 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
10904 if (VT.getSizeInBits() == 32) {
10905 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10909 // SHUFPS the element to the lowest double word, then movss.
10910 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
10911 MVT VVT = Op.getOperand(0).getSimpleValueType();
10912 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10913 DAG.getUNDEF(VVT), Mask);
10914 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10915 DAG.getIntPtrConstant(0, dl));
10918 if (VT.getSizeInBits() == 64) {
10919 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
10920 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
10921 // to match extract_elt for f64.
10922 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10926 // UNPCKHPD the element to the lowest double word, then movsd.
10927 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
10928 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
10929 int Mask[2] = { 1, -1 };
10930 MVT VVT = Op.getOperand(0).getSimpleValueType();
10931 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
10932 DAG.getUNDEF(VVT), Mask);
10933 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
10934 DAG.getIntPtrConstant(0, dl));
10940 /// Insert one bit to mask vector, like v16i1 or v8i1.
10941 /// AVX-512 feature.
10943 X86TargetLowering::InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const {
10945 SDValue Vec = Op.getOperand(0);
10946 SDValue Elt = Op.getOperand(1);
10947 SDValue Idx = Op.getOperand(2);
10948 MVT VecVT = Vec.getSimpleValueType();
10950 if (!isa<ConstantSDNode>(Idx)) {
10951 // Non constant index. Extend source and destination,
10952 // insert element and then truncate the result.
10953 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
10954 MVT ExtEltVT = (VecVT == MVT::v8i1 ? MVT::i64 : MVT::i32);
10955 SDValue ExtOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ExtVecVT,
10956 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVecVT, Vec),
10957 DAG.getNode(ISD::ZERO_EXTEND, dl, ExtEltVT, Elt), Idx);
10958 return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
10961 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
10962 SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
10964 EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,
10965 DAG.getConstant(IdxVal, dl, MVT::i8));
10966 if (Vec.getOpcode() == ISD::UNDEF)
10968 return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);
10971 SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
10972 SelectionDAG &DAG) const {
10973 MVT VT = Op.getSimpleValueType();
10974 MVT EltVT = VT.getVectorElementType();
10976 if (EltVT == MVT::i1)
10977 return InsertBitToMaskVector(Op, DAG);
10980 SDValue N0 = Op.getOperand(0);
10981 SDValue N1 = Op.getOperand(1);
10982 SDValue N2 = Op.getOperand(2);
10983 if (!isa<ConstantSDNode>(N2))
10985 auto *N2C = cast<ConstantSDNode>(N2);
10986 unsigned IdxVal = N2C->getZExtValue();
10988 // If the vector is wider than 128 bits, extract the 128-bit subvector, insert
10989 // into that, and then insert the subvector back into the result.
10990 if (VT.is256BitVector() || VT.is512BitVector()) {
10991 // With a 256-bit vector, we can insert into the zero element efficiently
10992 // using a blend if we have AVX or AVX2 and the right data type.
10993 if (VT.is256BitVector() && IdxVal == 0) {
10994 // TODO: It is worthwhile to cast integer to floating point and back
10995 // and incur a domain crossing penalty if that's what we'll end up
10996 // doing anyway after extracting to a 128-bit vector.
10997 if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||
10998 (Subtarget->hasAVX2() && EltVT == MVT::i32)) {
10999 SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);
11000 N2 = DAG.getIntPtrConstant(1, dl);
11001 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);
11005 // Get the desired 128-bit vector chunk.
11006 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
11008 // Insert the element into the desired chunk.
11009 unsigned NumEltsIn128 = 128 / EltVT.getSizeInBits();
11010 unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;
11012 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
11013 DAG.getConstant(IdxIn128, dl, MVT::i32));
11015 // Insert the changed part back into the bigger vector
11016 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
11018 assert(VT.is128BitVector() && "Only 128-bit vector types should be left!");
11020 if (Subtarget->hasSSE41()) {
11021 if (EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) {
11023 if (VT == MVT::v8i16) {
11024 Opc = X86ISD::PINSRW;
11026 assert(VT == MVT::v16i8);
11027 Opc = X86ISD::PINSRB;
11030 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
11032 if (N1.getValueType() != MVT::i32)
11033 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11034 if (N2.getValueType() != MVT::i32)
11035 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11036 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
11039 if (EltVT == MVT::f32) {
11040 // Bits [7:6] of the constant are the source select. This will always be
11041 // zero here. The DAG Combiner may combine an extract_elt index into
11042 // these bits. For example (insert (extract, 3), 2) could be matched by
11043 // putting the '3' into bits [7:6] of X86ISD::INSERTPS.
11044 // Bits [5:4] of the constant are the destination select. This is the
11045 // value of the incoming immediate.
11046 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
11047 // combine either bitwise AND or insert of float 0.0 to set these bits.
11049 const Function *F = DAG.getMachineFunction().getFunction();
11050 bool MinSize = F->hasFnAttribute(Attribute::MinSize);
11051 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
11052 // If this is an insertion of 32-bits into the low 32-bits of
11053 // a vector, we prefer to generate a blend with immediate rather
11054 // than an insertps. Blends are simpler operations in hardware and so
11055 // will always have equal or better performance than insertps.
11056 // But if optimizing for size and there's a load folding opportunity,
11057 // generate insertps because blendps does not have a 32-bit memory
11059 N2 = DAG.getIntPtrConstant(1, dl);
11060 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11061 return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);
11063 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
11064 // Create this as a scalar to vector..
11065 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
11066 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
11069 if (EltVT == MVT::i32 || EltVT == MVT::i64) {
11070 // PINSR* works with constant index.
11075 if (EltVT == MVT::i8)
11078 if (EltVT.getSizeInBits() == 16) {
11079 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
11080 // as its second argument.
11081 if (N1.getValueType() != MVT::i32)
11082 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
11083 if (N2.getValueType() != MVT::i32)
11084 N2 = DAG.getIntPtrConstant(IdxVal, dl);
11085 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
11090 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
11092 MVT OpVT = Op.getSimpleValueType();
11094 // If this is a 256-bit vector result, first insert into a 128-bit
11095 // vector and then insert into the 256-bit vector.
11096 if (!OpVT.is128BitVector()) {
11097 // Insert into a 128-bit vector.
11098 unsigned SizeFactor = OpVT.getSizeInBits()/128;
11099 MVT VT128 = MVT::getVectorVT(OpVT.getVectorElementType(),
11100 OpVT.getVectorNumElements() / SizeFactor);
11102 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
11104 // Insert the 128-bit vector.
11105 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
11108 if (OpVT == MVT::v1i64 &&
11109 Op.getOperand(0).getValueType() == MVT::i64)
11110 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
11112 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
11113 assert(OpVT.is128BitVector() && "Expected an SSE type!");
11114 return DAG.getBitcast(
11115 OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, AnyExt));
11118 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
11119 // a simple subregister reference or explicit instructions to grab
11120 // upper bits of a vector.
11121 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11122 SelectionDAG &DAG) {
11124 SDValue In = Op.getOperand(0);
11125 SDValue Idx = Op.getOperand(1);
11126 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11127 MVT ResVT = Op.getSimpleValueType();
11128 MVT InVT = In.getSimpleValueType();
11130 if (Subtarget->hasFp256()) {
11131 if (ResVT.is128BitVector() &&
11132 (InVT.is256BitVector() || InVT.is512BitVector()) &&
11133 isa<ConstantSDNode>(Idx)) {
11134 return Extract128BitVector(In, IdxVal, DAG, dl);
11136 if (ResVT.is256BitVector() && InVT.is512BitVector() &&
11137 isa<ConstantSDNode>(Idx)) {
11138 return Extract256BitVector(In, IdxVal, DAG, dl);
11144 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
11145 // simple superregister reference or explicit instructions to insert
11146 // the upper bits of a vector.
11147 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
11148 SelectionDAG &DAG) {
11149 if (!Subtarget->hasAVX())
11153 SDValue Vec = Op.getOperand(0);
11154 SDValue SubVec = Op.getOperand(1);
11155 SDValue Idx = Op.getOperand(2);
11157 if (!isa<ConstantSDNode>(Idx))
11160 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
11161 MVT OpVT = Op.getSimpleValueType();
11162 MVT SubVecVT = SubVec.getSimpleValueType();
11164 // Fold two 16-byte subvector loads into one 32-byte load:
11165 // (insert_subvector (insert_subvector undef, (load addr), 0),
11166 // (load addr + 16), Elts/2)
11168 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
11169 Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
11170 OpVT.is256BitVector() && SubVecVT.is128BitVector() &&
11171 !Subtarget->isUnalignedMem32Slow()) {
11172 SDValue SubVec2 = Vec.getOperand(1);
11173 if (auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2))) {
11174 if (Idx2->getZExtValue() == 0) {
11175 SDValue Ops[] = { SubVec2, SubVec };
11176 if (SDValue Ld = EltsFromConsecutiveLoads(OpVT, Ops, dl, DAG, false))
11182 if ((OpVT.is256BitVector() || OpVT.is512BitVector()) &&
11183 SubVecVT.is128BitVector())
11184 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
11186 if (OpVT.is512BitVector() && SubVecVT.is256BitVector())
11187 return Insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
11189 if (OpVT.getVectorElementType() == MVT::i1) {
11190 if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal
11192 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);
11193 SDValue Undef = DAG.getUNDEF(OpVT);
11194 unsigned NumElems = OpVT.getVectorNumElements();
11195 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);
11197 if (IdxVal == OpVT.getVectorNumElements() / 2) {
11198 // Zero upper bits of the Vec
11199 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11200 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11202 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11204 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11205 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11208 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef,
11210 // Zero upper bits of the Vec2
11211 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits);
11212 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);
11213 // Zero lower bits of the Vec
11214 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);
11215 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits);
11216 // Merge them together
11217 return DAG.getNode(ISD::OR, dl, OpVT, Vec, Vec2);
11223 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
11224 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
11225 // one of the above mentioned nodes. It has to be wrapped because otherwise
11226 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
11227 // be used to form addressing mode. These wrapped nodes will be selected
11230 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
11231 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
11233 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11234 // global base reg.
11235 unsigned char OpFlag = 0;
11236 unsigned WrapperKind = X86ISD::Wrapper;
11237 CodeModel::Model M = DAG.getTarget().getCodeModel();
11239 if (Subtarget->isPICStyleRIPRel() &&
11240 (M == CodeModel::Small || M == CodeModel::Kernel))
11241 WrapperKind = X86ISD::WrapperRIP;
11242 else if (Subtarget->isPICStyleGOT())
11243 OpFlag = X86II::MO_GOTOFF;
11244 else if (Subtarget->isPICStyleStubPIC())
11245 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11247 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
11248 CP->getAlignment(),
11249 CP->getOffset(), OpFlag);
11251 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11252 // With PIC, the address is actually $g + Offset.
11254 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11255 DAG.getNode(X86ISD::GlobalBaseReg,
11256 SDLoc(), getPointerTy()),
11263 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
11264 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
11266 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11267 // global base reg.
11268 unsigned char OpFlag = 0;
11269 unsigned WrapperKind = X86ISD::Wrapper;
11270 CodeModel::Model M = DAG.getTarget().getCodeModel();
11272 if (Subtarget->isPICStyleRIPRel() &&
11273 (M == CodeModel::Small || M == CodeModel::Kernel))
11274 WrapperKind = X86ISD::WrapperRIP;
11275 else if (Subtarget->isPICStyleGOT())
11276 OpFlag = X86II::MO_GOTOFF;
11277 else if (Subtarget->isPICStyleStubPIC())
11278 OpFlag = X86II::MO_PIC_BASE_OFFSET;
11280 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
11283 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11285 // With PIC, the address is actually $g + Offset.
11287 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11288 DAG.getNode(X86ISD::GlobalBaseReg,
11289 SDLoc(), getPointerTy()),
11296 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
11297 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
11299 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11300 // global base reg.
11301 unsigned char OpFlag = 0;
11302 unsigned WrapperKind = X86ISD::Wrapper;
11303 CodeModel::Model M = DAG.getTarget().getCodeModel();
11305 if (Subtarget->isPICStyleRIPRel() &&
11306 (M == CodeModel::Small || M == CodeModel::Kernel)) {
11307 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
11308 OpFlag = X86II::MO_GOTPCREL;
11309 WrapperKind = X86ISD::WrapperRIP;
11310 } else if (Subtarget->isPICStyleGOT()) {
11311 OpFlag = X86II::MO_GOT;
11312 } else if (Subtarget->isPICStyleStubPIC()) {
11313 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
11314 } else if (Subtarget->isPICStyleStubNoDynamic()) {
11315 OpFlag = X86II::MO_DARWIN_NONLAZY;
11318 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
11321 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11323 // With PIC, the address is actually $g + Offset.
11324 if (DAG.getTarget().getRelocationModel() == Reloc::PIC_ &&
11325 !Subtarget->is64Bit()) {
11326 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11327 DAG.getNode(X86ISD::GlobalBaseReg,
11328 SDLoc(), getPointerTy()),
11332 // For symbols that require a load from a stub to get the address, emit the
11334 if (isGlobalStubReference(OpFlag))
11335 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
11336 MachinePointerInfo::getGOT(), false, false, false, 0);
11342 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
11343 // Create the TargetBlockAddressAddress node.
11344 unsigned char OpFlags =
11345 Subtarget->ClassifyBlockAddressReference();
11346 CodeModel::Model M = DAG.getTarget().getCodeModel();
11347 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
11348 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
11350 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
11353 if (Subtarget->isPICStyleRIPRel() &&
11354 (M == CodeModel::Small || M == CodeModel::Kernel))
11355 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11357 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11359 // With PIC, the address is actually $g + Offset.
11360 if (isGlobalRelativeToPICBase(OpFlags)) {
11361 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11362 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11370 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, SDLoc dl,
11371 int64_t Offset, SelectionDAG &DAG) const {
11372 // Create the TargetGlobalAddress node, folding in the constant
11373 // offset if it is legal.
11374 unsigned char OpFlags =
11375 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget());
11376 CodeModel::Model M = DAG.getTarget().getCodeModel();
11378 if (OpFlags == X86II::MO_NO_FLAG &&
11379 X86::isOffsetSuitableForCodeModel(Offset, M)) {
11380 // A direct static reference to a global.
11381 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
11384 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
11387 if (Subtarget->isPICStyleRIPRel() &&
11388 (M == CodeModel::Small || M == CodeModel::Kernel))
11389 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
11391 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
11393 // With PIC, the address is actually $g + Offset.
11394 if (isGlobalRelativeToPICBase(OpFlags)) {
11395 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
11396 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
11400 // For globals that require a load from a stub to get the address, emit the
11402 if (isGlobalStubReference(OpFlags))
11403 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
11404 MachinePointerInfo::getGOT(), false, false, false, 0);
11406 // If there was a non-zero offset that we didn't fold, create an explicit
11407 // addition for it.
11409 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
11410 DAG.getConstant(Offset, dl, getPointerTy()));
11416 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
11417 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
11418 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
11419 return LowerGlobalAddress(GV, SDLoc(Op), Offset, DAG);
11423 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
11424 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
11425 unsigned char OperandFlags, bool LocalDynamic = false) {
11426 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11427 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11429 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11430 GA->getValueType(0),
11434 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
11438 SDValue Ops[] = { Chain, TGA, *InFlag };
11439 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11441 SDValue Ops[] = { Chain, TGA };
11442 Chain = DAG.getNode(CallType, dl, NodeTys, Ops);
11445 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
11446 MFI->setAdjustsStack(true);
11447 MFI->setHasCalls(true);
11449 SDValue Flag = Chain.getValue(1);
11450 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
11453 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
11455 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11458 SDLoc dl(GA); // ? function entry point might be better
11459 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11460 DAG.getNode(X86ISD::GlobalBaseReg,
11461 SDLoc(), PtrVT), InFlag);
11462 InFlag = Chain.getValue(1);
11464 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
11467 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
11469 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11471 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT,
11472 X86::RAX, X86II::MO_TLSGD);
11475 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
11481 // Get the start address of the TLS block for this module.
11482 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
11483 .getInfo<X86MachineFunctionInfo>();
11484 MFI->incNumLocalDynamicTLSAccesses();
11488 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, nullptr, PtrVT, X86::RAX,
11489 X86II::MO_TLSLD, /*LocalDynamic=*/true);
11492 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
11493 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT), InFlag);
11494 InFlag = Chain.getValue(1);
11495 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
11496 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
11499 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
11503 unsigned char OperandFlags = X86II::MO_DTPOFF;
11504 unsigned WrapperKind = X86ISD::Wrapper;
11505 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11506 GA->getValueType(0),
11507 GA->getOffset(), OperandFlags);
11508 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11510 // Add x@dtpoff with the base.
11511 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
11514 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
11515 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
11516 const EVT PtrVT, TLSModel::Model model,
11517 bool is64Bit, bool isPIC) {
11520 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
11521 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
11522 is64Bit ? 257 : 256));
11524 SDValue ThreadPointer =
11525 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),
11526 MachinePointerInfo(Ptr), false, false, false, 0);
11528 unsigned char OperandFlags = 0;
11529 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
11531 unsigned WrapperKind = X86ISD::Wrapper;
11532 if (model == TLSModel::LocalExec) {
11533 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
11534 } else if (model == TLSModel::InitialExec) {
11536 OperandFlags = X86II::MO_GOTTPOFF;
11537 WrapperKind = X86ISD::WrapperRIP;
11539 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
11542 llvm_unreachable("Unexpected model");
11545 // emit "addl x@ntpoff,%eax" (local exec)
11546 // or "addl x@indntpoff,%eax" (initial exec)
11547 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
11549 DAG.getTargetGlobalAddress(GA->getGlobal(), dl, GA->getValueType(0),
11550 GA->getOffset(), OperandFlags);
11551 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
11553 if (model == TLSModel::InitialExec) {
11554 if (isPIC && !is64Bit) {
11555 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
11556 DAG.getNode(X86ISD::GlobalBaseReg, SDLoc(), PtrVT),
11560 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
11561 MachinePointerInfo::getGOT(), false, false, false, 0);
11564 // The address of the thread local variable is the add of the thread
11565 // pointer with the offset of the variable.
11566 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
11570 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
11572 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
11573 const GlobalValue *GV = GA->getGlobal();
11575 if (Subtarget->isTargetELF()) {
11576 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
11578 case TLSModel::GeneralDynamic:
11579 if (Subtarget->is64Bit())
11580 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
11581 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
11582 case TLSModel::LocalDynamic:
11583 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
11584 Subtarget->is64Bit());
11585 case TLSModel::InitialExec:
11586 case TLSModel::LocalExec:
11587 return LowerToTLSExecModel(
11588 GA, DAG, getPointerTy(), model, Subtarget->is64Bit(),
11589 DAG.getTarget().getRelocationModel() == Reloc::PIC_);
11591 llvm_unreachable("Unknown TLS model.");
11594 if (Subtarget->isTargetDarwin()) {
11595 // Darwin only has one model of TLS. Lower to that.
11596 unsigned char OpFlag = 0;
11597 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
11598 X86ISD::WrapperRIP : X86ISD::Wrapper;
11600 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
11601 // global base reg.
11602 bool PIC32 = (DAG.getTarget().getRelocationModel() == Reloc::PIC_) &&
11603 !Subtarget->is64Bit();
11605 OpFlag = X86II::MO_TLVP_PIC_BASE;
11607 OpFlag = X86II::MO_TLVP;
11609 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
11610 GA->getValueType(0),
11611 GA->getOffset(), OpFlag);
11612 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
11614 // With PIC32, the address is actually $g + Offset.
11616 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
11617 DAG.getNode(X86ISD::GlobalBaseReg,
11618 SDLoc(), getPointerTy()),
11621 // Lowering the machine isd will make sure everything is in the right
11623 SDValue Chain = DAG.getEntryNode();
11624 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11625 SDValue Args[] = { Chain, Offset };
11626 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args);
11628 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
11629 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11630 MFI->setAdjustsStack(true);
11632 // And our return value (tls address) is in the standard call return value
11634 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
11635 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
11636 Chain.getValue(1));
11639 if (Subtarget->isTargetKnownWindowsMSVC() ||
11640 Subtarget->isTargetWindowsGNU()) {
11641 // Just use the implicit TLS architecture
11642 // Need to generate someting similar to:
11643 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
11645 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
11646 // mov rcx, qword [rdx+rcx*8]
11647 // mov eax, .tls$:tlsvar
11648 // [rax+rcx] contains the address
11649 // Windows 64bit: gs:0x58
11650 // Windows 32bit: fs:__tls_array
11653 SDValue Chain = DAG.getEntryNode();
11655 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
11656 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
11657 // use its literal value of 0x2C.
11658 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
11659 ? Type::getInt8PtrTy(*DAG.getContext(),
11661 : Type::getInt32PtrTy(*DAG.getContext(),
11665 Subtarget->is64Bit()
11666 ? DAG.getIntPtrConstant(0x58, dl)
11667 : (Subtarget->isTargetWindowsGNU()
11668 ? DAG.getIntPtrConstant(0x2C, dl)
11669 : DAG.getExternalSymbol("_tls_array", getPointerTy()));
11671 SDValue ThreadPointer =
11672 DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
11673 MachinePointerInfo(Ptr), false, false, false, 0);
11676 if (GV->getThreadLocalMode() == GlobalVariable::LocalExecTLSModel) {
11677 res = ThreadPointer;
11679 // Load the _tls_index variable
11680 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
11681 if (Subtarget->is64Bit())
11682 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain, IDX,
11683 MachinePointerInfo(), MVT::i32, false, false,
11686 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
11687 false, false, false, 0);
11689 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,
11691 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
11693 res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
11696 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
11697 false, false, false, 0);
11699 // Get the offset of start of .tls section
11700 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
11701 GA->getValueType(0),
11702 GA->getOffset(), X86II::MO_SECREL);
11703 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
11705 // The address of the thread local variable is the add of the thread
11706 // pointer with the offset of the variable.
11707 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
11710 llvm_unreachable("TLS not implemented for this target.");
11713 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11714 /// and take a 2 x i32 value to shift plus a shift amount.
11715 static SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) {
11716 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
11717 MVT VT = Op.getSimpleValueType();
11718 unsigned VTBits = VT.getSizeInBits();
11720 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
11721 SDValue ShOpLo = Op.getOperand(0);
11722 SDValue ShOpHi = Op.getOperand(1);
11723 SDValue ShAmt = Op.getOperand(2);
11724 // X86ISD::SHLD and X86ISD::SHRD have defined overflow behavior but the
11725 // generic ISD nodes haven't. Insert an AND to be safe, it's optimized away
11727 SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11728 DAG.getConstant(VTBits - 1, dl, MVT::i8));
11729 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
11730 DAG.getConstant(VTBits - 1, dl, MVT::i8))
11731 : DAG.getConstant(0, dl, VT);
11733 SDValue Tmp2, Tmp3;
11734 if (Op.getOpcode() == ISD::SHL_PARTS) {
11735 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
11736 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, SafeShAmt);
11738 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
11739 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, SafeShAmt);
11742 // If the shift amount is larger or equal than the width of a part we can't
11743 // rely on the results of shld/shrd. Insert a test and select the appropriate
11744 // values for large shift amounts.
11745 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
11746 DAG.getConstant(VTBits, dl, MVT::i8));
11747 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
11748 AndNode, DAG.getConstant(0, dl, MVT::i8));
11751 SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
11752 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
11753 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
11755 if (Op.getOpcode() == ISD::SHL_PARTS) {
11756 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11757 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11759 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0);
11760 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1);
11763 SDValue Ops[2] = { Lo, Hi };
11764 return DAG.getMergeValues(Ops, dl);
11767 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
11768 SelectionDAG &DAG) const {
11769 SDValue Src = Op.getOperand(0);
11770 MVT SrcVT = Src.getSimpleValueType();
11771 MVT VT = Op.getSimpleValueType();
11774 if (SrcVT.isVector()) {
11775 if (SrcVT == MVT::v2i32 && VT == MVT::v2f64) {
11776 return DAG.getNode(X86ISD::CVTDQ2PD, dl, VT,
11777 DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4i32, Src,
11778 DAG.getUNDEF(SrcVT)));
11780 if (SrcVT.getVectorElementType() == MVT::i1) {
11781 MVT IntegerVT = MVT::getVectorVT(MVT::i32, SrcVT.getVectorNumElements());
11782 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
11783 DAG.getNode(ISD::SIGN_EXTEND, dl, IntegerVT, Src));
11788 assert(SrcVT <= MVT::i64 && SrcVT >= MVT::i16 &&
11789 "Unknown SINT_TO_FP to lower!");
11791 // These are really Legal; return the operand so the caller accepts it as
11793 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
11795 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
11796 Subtarget->is64Bit()) {
11800 unsigned Size = SrcVT.getSizeInBits()/8;
11801 MachineFunction &MF = DAG.getMachineFunction();
11802 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
11803 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11804 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
11806 MachinePointerInfo::getFixedStack(SSFI),
11808 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
11811 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
11813 SelectionDAG &DAG) const {
11817 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
11819 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
11821 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
11823 unsigned ByteSize = SrcVT.getSizeInBits()/8;
11825 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
11826 MachineMemOperand *MMO;
11828 int SSFI = FI->getIndex();
11830 DAG.getMachineFunction()
11831 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11832 MachineMemOperand::MOLoad, ByteSize, ByteSize);
11834 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
11835 StackSlot = StackSlot.getOperand(1);
11837 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
11838 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
11840 Tys, Ops, SrcVT, MMO);
11843 Chain = Result.getValue(1);
11844 SDValue InFlag = Result.getValue(2);
11846 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
11847 // shouldn't be necessary except that RFP cannot be live across
11848 // multiple blocks. When stackifier is fixed, they can be uncoupled.
11849 MachineFunction &MF = DAG.getMachineFunction();
11850 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
11851 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
11852 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11853 Tys = DAG.getVTList(MVT::Other);
11855 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
11857 MachineMemOperand *MMO =
11858 DAG.getMachineFunction()
11859 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11860 MachineMemOperand::MOStore, SSFISize, SSFISize);
11862 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
11863 Ops, Op.getValueType(), MMO);
11864 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
11865 MachinePointerInfo::getFixedStack(SSFI),
11866 false, false, false, 0);
11872 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
11873 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
11874 SelectionDAG &DAG) const {
11875 // This algorithm is not obvious. Here it is what we're trying to output:
11878 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
11879 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
11881 haddpd %xmm0, %xmm0
11883 pshufd $0x4e, %xmm0, %xmm1
11889 LLVMContext *Context = DAG.getContext();
11891 // Build some magic constants.
11892 static const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
11893 Constant *C0 = ConstantDataVector::get(*Context, CV0);
11894 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
11896 SmallVector<Constant*,2> CV1;
11898 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11899 APInt(64, 0x4330000000000000ULL))));
11901 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
11902 APInt(64, 0x4530000000000000ULL))));
11903 Constant *C1 = ConstantVector::get(CV1);
11904 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
11906 // Load the 64-bit value into an XMM register.
11907 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
11909 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
11910 MachinePointerInfo::getConstantPool(),
11911 false, false, false, 16);
11913 getUnpackl(DAG, dl, MVT::v4i32, DAG.getBitcast(MVT::v4i32, XR1), CLod0);
11915 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
11916 MachinePointerInfo::getConstantPool(),
11917 false, false, false, 16);
11918 SDValue XR2F = DAG.getBitcast(MVT::v2f64, Unpck1);
11919 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
11922 if (Subtarget->hasSSE3()) {
11923 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
11924 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
11926 SDValue S2F = DAG.getBitcast(MVT::v4i32, Sub);
11927 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
11929 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
11930 DAG.getBitcast(MVT::v2f64, Shuffle), Sub);
11933 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
11934 DAG.getIntPtrConstant(0, dl));
11937 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
11938 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
11939 SelectionDAG &DAG) const {
11941 // FP constant to bias correct the final result.
11942 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
11945 // Load the 32-bit value into an XMM register.
11946 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
11949 // Zero out the upper parts of the register.
11950 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
11952 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11953 DAG.getBitcast(MVT::v2f64, Load),
11954 DAG.getIntPtrConstant(0, dl));
11956 // Or the load with the bias.
11957 SDValue Or = DAG.getNode(
11958 ISD::OR, dl, MVT::v2i64,
11959 DAG.getBitcast(MVT::v2i64,
11960 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Load)),
11961 DAG.getBitcast(MVT::v2i64,
11962 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, Bias)));
11964 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
11965 DAG.getBitcast(MVT::v2f64, Or), DAG.getIntPtrConstant(0, dl));
11967 // Subtract the bias.
11968 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
11970 // Handle final rounding.
11971 EVT DestVT = Op.getValueType();
11973 if (DestVT.bitsLT(MVT::f64))
11974 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
11975 DAG.getIntPtrConstant(0, dl));
11976 if (DestVT.bitsGT(MVT::f64))
11977 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
11979 // Handle final rounding.
11983 static SDValue lowerUINT_TO_FP_vXi32(SDValue Op, SelectionDAG &DAG,
11984 const X86Subtarget &Subtarget) {
11985 // The algorithm is the following:
11986 // #ifdef __SSE4_1__
11987 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
11988 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
11989 // (uint4) 0x53000000, 0xaa);
11991 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
11992 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
11994 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
11995 // return (float4) lo + fhi;
11998 SDValue V = Op->getOperand(0);
11999 EVT VecIntVT = V.getValueType();
12000 bool Is128 = VecIntVT == MVT::v4i32;
12001 EVT VecFloatVT = Is128 ? MVT::v4f32 : MVT::v8f32;
12002 // If we convert to something else than the supported type, e.g., to v4f64,
12004 if (VecFloatVT != Op->getValueType(0))
12007 unsigned NumElts = VecIntVT.getVectorNumElements();
12008 assert((VecIntVT == MVT::v4i32 || VecIntVT == MVT::v8i32) &&
12009 "Unsupported custom type");
12010 assert(NumElts <= 8 && "The size of the constant array must be fixed");
12012 // In the #idef/#else code, we have in common:
12013 // - The vector of constants:
12019 // Create the splat vector for 0x4b000000.
12020 SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);
12021 SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,
12022 CstLow, CstLow, CstLow, CstLow};
12023 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12024 makeArrayRef(&CstLowArray[0], NumElts));
12025 // Create the splat vector for 0x53000000.
12026 SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);
12027 SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,
12028 CstHigh, CstHigh, CstHigh, CstHigh};
12029 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12030 makeArrayRef(&CstHighArray[0], NumElts));
12032 // Create the right shift.
12033 SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);
12034 SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,
12035 CstShift, CstShift, CstShift, CstShift};
12036 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,
12037 makeArrayRef(&CstShiftArray[0], NumElts));
12038 SDValue HighShift = DAG.getNode(ISD::SRL, DL, VecIntVT, V, VecCstShift);
12041 if (Subtarget.hasSSE41()) {
12042 EVT VecI16VT = Is128 ? MVT::v8i16 : MVT::v16i16;
12043 // uint4 lo = _mm_blend_epi16( v, (uint4) 0x4b000000, 0xaa);
12044 SDValue VecCstLowBitcast = DAG.getBitcast(VecI16VT, VecCstLow);
12045 SDValue VecBitcast = DAG.getBitcast(VecI16VT, V);
12046 // Low will be bitcasted right away, so do not bother bitcasting back to its
12048 Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,
12049 VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12050 // uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),
12051 // (uint4) 0x53000000, 0xaa);
12052 SDValue VecCstHighBitcast = DAG.getBitcast(VecI16VT, VecCstHigh);
12053 SDValue VecShiftBitcast = DAG.getBitcast(VecI16VT, HighShift);
12054 // High will be bitcasted right away, so do not bother bitcasting back to
12055 // its original type.
12056 High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,
12057 VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));
12059 SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);
12060 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,
12061 CstMask, CstMask, CstMask);
12062 // uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;
12063 SDValue LowAnd = DAG.getNode(ISD::AND, DL, VecIntVT, V, VecCstMask);
12064 Low = DAG.getNode(ISD::OR, DL, VecIntVT, LowAnd, VecCstLow);
12066 // uint4 hi = (v >> 16) | (uint4) 0x53000000;
12067 High = DAG.getNode(ISD::OR, DL, VecIntVT, HighShift, VecCstHigh);
12070 // Create the vector constant for -(0x1.0p39f + 0x1.0p23f).
12071 SDValue CstFAdd = DAG.getConstantFP(
12072 APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);
12073 SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,
12074 CstFAdd, CstFAdd, CstFAdd, CstFAdd};
12075 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,
12076 makeArrayRef(&CstFAddArray[0], NumElts));
12078 // float4 fhi = (float4) hi - (0x1.0p39f + 0x1.0p23f);
12079 SDValue HighBitcast = DAG.getBitcast(VecFloatVT, High);
12081 DAG.getNode(ISD::FADD, DL, VecFloatVT, HighBitcast, VecCstFAdd);
12082 // return (float4) lo + fhi;
12083 SDValue LowBitcast = DAG.getBitcast(VecFloatVT, Low);
12084 return DAG.getNode(ISD::FADD, DL, VecFloatVT, LowBitcast, FHigh);
12087 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
12088 SelectionDAG &DAG) const {
12089 SDValue N0 = Op.getOperand(0);
12090 MVT SVT = N0.getSimpleValueType();
12093 switch (SVT.SimpleTy) {
12095 llvm_unreachable("Custom UINT_TO_FP is not supported!");
12100 MVT NVT = MVT::getVectorVT(MVT::i32, SVT.getVectorNumElements());
12101 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
12102 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
12106 return lowerUINT_TO_FP_vXi32(Op, DAG, *Subtarget);
12109 if (Subtarget->hasAVX512())
12110 return DAG.getNode(ISD::UINT_TO_FP, dl, Op.getValueType(),
12111 DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v16i32, N0));
12113 llvm_unreachable(nullptr);
12116 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
12117 SelectionDAG &DAG) const {
12118 SDValue N0 = Op.getOperand(0);
12121 if (Op.getValueType().isVector())
12122 return lowerUINT_TO_FP_vec(Op, DAG);
12124 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
12125 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
12126 // the optimization here.
12127 if (DAG.SignBitIsZero(N0))
12128 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
12130 MVT SrcVT = N0.getSimpleValueType();
12131 MVT DstVT = Op.getSimpleValueType();
12132 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
12133 return LowerUINT_TO_FP_i64(Op, DAG);
12134 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
12135 return LowerUINT_TO_FP_i32(Op, DAG);
12136 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
12139 // Make a 64-bit buffer, and use it to build an FILD.
12140 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
12141 if (SrcVT == MVT::i32) {
12142 SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());
12143 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
12144 getPointerTy(), StackSlot, WordOff);
12145 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12146 StackSlot, MachinePointerInfo(),
12148 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),
12149 OffsetSlot, MachinePointerInfo(),
12151 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
12155 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
12156 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
12157 StackSlot, MachinePointerInfo(),
12159 // For i64 source, we need to add the appropriate power of 2 if the input
12160 // was negative. This is the same as the optimization in
12161 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
12162 // we must be careful to do the computation in x87 extended precision, not
12163 // in SSE. (The generic code can't know it's OK to do this, or how to.)
12164 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
12165 MachineMemOperand *MMO =
12166 DAG.getMachineFunction()
12167 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12168 MachineMemOperand::MOLoad, 8, 8);
12170 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
12171 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
12172 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
12175 APInt FF(32, 0x5F800000ULL);
12177 // Check whether the sign bit is set.
12178 SDValue SignSet = DAG.getSetCC(dl,
12179 getSetCCResultType(*DAG.getContext(), MVT::i64),
12181 DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
12183 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
12184 SDValue FudgePtr = DAG.getConstantPool(
12185 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
12188 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
12189 SDValue Zero = DAG.getIntPtrConstant(0, dl);
12190 SDValue Four = DAG.getIntPtrConstant(4, dl);
12191 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
12193 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
12195 // Load the value out, extending it from f32 to f80.
12196 // FIXME: Avoid the extend by constructing the right constant pool?
12197 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
12198 FudgePtr, MachinePointerInfo::getConstantPool(),
12199 MVT::f32, false, false, false, 4);
12200 // Extend everything to 80 bits to force it to be done on x87.
12201 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
12202 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,
12203 DAG.getIntPtrConstant(0, dl));
12206 std::pair<SDValue,SDValue>
12207 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
12208 bool IsSigned, bool IsReplace) const {
12211 EVT DstTy = Op.getValueType();
12213 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
12214 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
12218 assert(DstTy.getSimpleVT() <= MVT::i64 &&
12219 DstTy.getSimpleVT() >= MVT::i16 &&
12220 "Unknown FP_TO_INT to lower!");
12222 // These are really Legal.
12223 if (DstTy == MVT::i32 &&
12224 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12225 return std::make_pair(SDValue(), SDValue());
12226 if (Subtarget->is64Bit() &&
12227 DstTy == MVT::i64 &&
12228 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
12229 return std::make_pair(SDValue(), SDValue());
12231 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
12232 // stack slot, or into the FTOL runtime function.
12233 MachineFunction &MF = DAG.getMachineFunction();
12234 unsigned MemSize = DstTy.getSizeInBits()/8;
12235 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12236 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12239 if (!IsSigned && isIntegerTypeFTOL(DstTy))
12240 Opc = X86ISD::WIN_FTOL;
12242 switch (DstTy.getSimpleVT().SimpleTy) {
12243 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
12244 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
12245 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
12246 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
12249 SDValue Chain = DAG.getEntryNode();
12250 SDValue Value = Op.getOperand(0);
12251 EVT TheVT = Op.getOperand(0).getValueType();
12252 // FIXME This causes a redundant load/store if the SSE-class value is already
12253 // in memory, such as if it is on the callstack.
12254 if (isScalarFPTypeInSSEReg(TheVT)) {
12255 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
12256 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
12257 MachinePointerInfo::getFixedStack(SSFI),
12259 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
12261 Chain, StackSlot, DAG.getValueType(TheVT)
12264 MachineMemOperand *MMO =
12265 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12266 MachineMemOperand::MOLoad, MemSize, MemSize);
12267 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, DstTy, MMO);
12268 Chain = Value.getValue(1);
12269 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
12270 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
12273 MachineMemOperand *MMO =
12274 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
12275 MachineMemOperand::MOStore, MemSize, MemSize);
12277 if (Opc != X86ISD::WIN_FTOL) {
12278 // Build the FP_TO_INT*_IN_MEM
12279 SDValue Ops[] = { Chain, Value, StackSlot };
12280 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
12282 return std::make_pair(FIST, StackSlot);
12284 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
12285 DAG.getVTList(MVT::Other, MVT::Glue),
12287 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
12288 MVT::i32, ftol.getValue(1));
12289 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
12290 MVT::i32, eax.getValue(2));
12291 SDValue Ops[] = { eax, edx };
12292 SDValue pair = IsReplace
12293 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops)
12294 : DAG.getMergeValues(Ops, DL);
12295 return std::make_pair(pair, SDValue());
12299 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
12300 const X86Subtarget *Subtarget) {
12301 MVT VT = Op->getSimpleValueType(0);
12302 SDValue In = Op->getOperand(0);
12303 MVT InVT = In.getSimpleValueType();
12306 if (VT.is512BitVector() || InVT.getScalarType() == MVT::i1)
12307 return DAG.getNode(ISD::ZERO_EXTEND, dl, VT, In);
12309 // Optimize vectors in AVX mode:
12312 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
12313 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
12314 // Concat upper and lower parts.
12317 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
12318 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
12319 // Concat upper and lower parts.
12322 if (((VT != MVT::v16i16) || (InVT != MVT::v16i8)) &&
12323 ((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
12324 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
12327 if (Subtarget->hasInt256())
12328 return DAG.getNode(X86ISD::VZEXT, dl, VT, In);
12330 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
12331 SDValue Undef = DAG.getUNDEF(InVT);
12332 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
12333 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12334 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
12336 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
12337 VT.getVectorNumElements()/2);
12339 OpLo = DAG.getBitcast(HVT, OpLo);
12340 OpHi = DAG.getBitcast(HVT, OpHi);
12342 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
12345 static SDValue LowerZERO_EXTEND_AVX512(SDValue Op,
12346 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
12347 MVT VT = Op->getSimpleValueType(0);
12348 SDValue In = Op->getOperand(0);
12349 MVT InVT = In.getSimpleValueType();
12351 unsigned int NumElts = VT.getVectorNumElements();
12352 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
12355 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1)
12356 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
12358 assert(InVT.getVectorElementType() == MVT::i1);
12359 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
12361 DAG.getConstant(APInt(ExtVT.getScalarSizeInBits(), 1), DL, ExtVT);
12363 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), DL, ExtVT);
12365 SDValue V = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
12366 if (VT.is512BitVector())
12368 return DAG.getNode(X86ISD::VTRUNC, DL, VT, V);
12371 static SDValue LowerANY_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12372 SelectionDAG &DAG) {
12373 if (Subtarget->hasFp256())
12374 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12380 static SDValue LowerZERO_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
12381 SelectionDAG &DAG) {
12383 MVT VT = Op.getSimpleValueType();
12384 SDValue In = Op.getOperand(0);
12385 MVT SVT = In.getSimpleValueType();
12387 if (VT.is512BitVector() || SVT.getVectorElementType() == MVT::i1)
12388 return LowerZERO_EXTEND_AVX512(Op, Subtarget, DAG);
12390 if (Subtarget->hasFp256())
12391 if (SDValue Res = LowerAVXExtend(Op, DAG, Subtarget))
12394 assert(!VT.is256BitVector() || !SVT.is128BitVector() ||
12395 VT.getVectorNumElements() != SVT.getVectorNumElements());
12399 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
12401 MVT VT = Op.getSimpleValueType();
12402 SDValue In = Op.getOperand(0);
12403 MVT InVT = In.getSimpleValueType();
12405 if (VT == MVT::i1) {
12406 assert((InVT.isInteger() && (InVT.getSizeInBits() <= 64)) &&
12407 "Invalid scalar TRUNCATE operation");
12408 if (InVT.getSizeInBits() >= 32)
12410 In = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, In);
12411 return DAG.getNode(ISD::TRUNCATE, DL, VT, In);
12413 assert(VT.getVectorNumElements() == InVT.getVectorNumElements() &&
12414 "Invalid TRUNCATE operation");
12416 // move vector to mask - truncate solution for SKX
12417 if (VT.getVectorElementType() == MVT::i1) {
12418 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() <= 16 &&
12419 Subtarget->hasBWI())
12420 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12421 if ((InVT.is256BitVector() || InVT.is128BitVector())
12422 && InVT.getScalarSizeInBits() <= 16 &&
12423 Subtarget->hasBWI() && Subtarget->hasVLX())
12424 return Op; // legal, will go to VPMOVB2M, VPMOVW2M
12425 if (InVT.is512BitVector() && InVT.getScalarSizeInBits() >= 32 &&
12426 Subtarget->hasDQI())
12427 return Op; // legal, will go to VPMOVD2M, VPMOVQ2M
12428 if ((InVT.is256BitVector() || InVT.is128BitVector())
12429 && InVT.getScalarSizeInBits() >= 32 &&
12430 Subtarget->hasDQI() && Subtarget->hasVLX())
12431 return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
12433 if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {
12434 if (VT.getVectorElementType().getSizeInBits() >=8)
12435 return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);
12437 assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
12438 unsigned NumElts = InVT.getVectorNumElements();
12439 assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");
12440 if (InVT.getSizeInBits() < 512) {
12441 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
12442 In = DAG.getNode(ISD::SIGN_EXTEND, DL, ExtVT, In);
12447 DAG.getConstant(APInt::getSignBit(InVT.getScalarSizeInBits()), DL, InVT);
12448 SDValue And = DAG.getNode(ISD::AND, DL, InVT, OneV, In);
12449 return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);
12452 if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {
12453 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
12454 if (Subtarget->hasInt256()) {
12455 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
12456 In = DAG.getBitcast(MVT::v8i32, In);
12457 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
12459 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
12460 DAG.getIntPtrConstant(0, DL));
12463 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12464 DAG.getIntPtrConstant(0, DL));
12465 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12466 DAG.getIntPtrConstant(2, DL));
12467 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12468 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12469 static const int ShufMask[] = {0, 2, 4, 6};
12470 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask);
12473 if ((VT == MVT::v8i16) && (InVT == MVT::v8i32)) {
12474 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
12475 if (Subtarget->hasInt256()) {
12476 In = DAG.getBitcast(MVT::v32i8, In);
12478 SmallVector<SDValue,32> pshufbMask;
12479 for (unsigned i = 0; i < 2; ++i) {
12480 pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));
12481 pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));
12482 pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));
12483 pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));
12484 pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));
12485 pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));
12486 pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));
12487 pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));
12488 for (unsigned j = 0; j < 8; ++j)
12489 pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));
12491 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);
12492 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
12493 In = DAG.getBitcast(MVT::v4i64, In);
12495 static const int ShufMask[] = {0, 2, -1, -1};
12496 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
12498 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
12499 DAG.getIntPtrConstant(0, DL));
12500 return DAG.getBitcast(VT, In);
12503 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12504 DAG.getIntPtrConstant(0, DL));
12506 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
12507 DAG.getIntPtrConstant(4, DL));
12509 OpLo = DAG.getBitcast(MVT::v16i8, OpLo);
12510 OpHi = DAG.getBitcast(MVT::v16i8, OpHi);
12512 // The PSHUFB mask:
12513 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
12514 -1, -1, -1, -1, -1, -1, -1, -1};
12516 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
12517 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
12518 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
12520 OpLo = DAG.getBitcast(MVT::v4i32, OpLo);
12521 OpHi = DAG.getBitcast(MVT::v4i32, OpHi);
12523 // The MOVLHPS Mask:
12524 static const int ShufMask2[] = {0, 1, 4, 5};
12525 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
12526 return DAG.getBitcast(MVT::v8i16, res);
12529 // Handle truncation of V256 to V128 using shuffles.
12530 if (!VT.is128BitVector() || !InVT.is256BitVector())
12533 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
12535 unsigned NumElems = VT.getVectorNumElements();
12536 MVT NVT = MVT::getVectorVT(VT.getVectorElementType(), NumElems * 2);
12538 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
12539 // Prepare truncation shuffle mask
12540 for (unsigned i = 0; i != NumElems; ++i)
12541 MaskVec[i] = i * 2;
12542 SDValue V = DAG.getVectorShuffle(NVT, DL, DAG.getBitcast(NVT, In),
12543 DAG.getUNDEF(NVT), &MaskVec[0]);
12544 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
12545 DAG.getIntPtrConstant(0, DL));
12548 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
12549 SelectionDAG &DAG) const {
12550 assert(!Op.getSimpleValueType().isVector());
12552 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12553 /*IsSigned=*/ true, /*IsReplace=*/ false);
12554 SDValue FIST = Vals.first, StackSlot = Vals.second;
12555 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
12556 if (!FIST.getNode()) return Op;
12558 if (StackSlot.getNode())
12559 // Load the result.
12560 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12561 FIST, StackSlot, MachinePointerInfo(),
12562 false, false, false, 0);
12564 // The node is the result.
12568 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
12569 SelectionDAG &DAG) const {
12570 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
12571 /*IsSigned=*/ false, /*IsReplace=*/ false);
12572 SDValue FIST = Vals.first, StackSlot = Vals.second;
12573 assert(FIST.getNode() && "Unexpected failure");
12575 if (StackSlot.getNode())
12576 // Load the result.
12577 return DAG.getLoad(Op.getValueType(), SDLoc(Op),
12578 FIST, StackSlot, MachinePointerInfo(),
12579 false, false, false, 0);
12581 // The node is the result.
12585 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
12587 MVT VT = Op.getSimpleValueType();
12588 SDValue In = Op.getOperand(0);
12589 MVT SVT = In.getSimpleValueType();
12591 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
12593 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
12594 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
12595 In, DAG.getUNDEF(SVT)));
12598 /// The only differences between FABS and FNEG are the mask and the logic op.
12599 /// FNEG also has a folding opportunity for FNEG(FABS(x)).
12600 static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {
12601 assert((Op.getOpcode() == ISD::FABS || Op.getOpcode() == ISD::FNEG) &&
12602 "Wrong opcode for lowering FABS or FNEG.");
12604 bool IsFABS = (Op.getOpcode() == ISD::FABS);
12606 // If this is a FABS and it has an FNEG user, bail out to fold the combination
12607 // into an FNABS. We'll lower the FABS after that if it is still in use.
12609 for (SDNode *User : Op->uses())
12610 if (User->getOpcode() == ISD::FNEG)
12613 SDValue Op0 = Op.getOperand(0);
12614 bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);
12617 MVT VT = Op.getSimpleValueType();
12618 // Assume scalar op for initialization; update for vector if needed.
12619 // Note that there are no scalar bitwise logical SSE/AVX instructions, so we
12620 // generate a 16-byte vector constant and logic op even for the scalar case.
12621 // Using a 16-byte mask allows folding the load of the mask with
12622 // the logic op, so it can save (~4 bytes) on code size.
12624 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
12625 // FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to
12626 // decide if we should generate a 16-byte constant mask when we only need 4 or
12627 // 8 bytes for the scalar case.
12628 if (VT.isVector()) {
12629 EltVT = VT.getVectorElementType();
12630 NumElts = VT.getVectorNumElements();
12633 unsigned EltBits = EltVT.getSizeInBits();
12634 LLVMContext *Context = DAG.getContext();
12635 // For FABS, mask is 0x7f...; for FNEG, mask is 0x80...
12637 IsFABS ? APInt::getSignedMaxValue(EltBits) : APInt::getSignBit(EltBits);
12638 Constant *C = ConstantInt::get(*Context, MaskElt);
12639 C = ConstantVector::getSplat(NumElts, C);
12640 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12641 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy());
12642 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
12643 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12644 MachinePointerInfo::getConstantPool(),
12645 false, false, false, Alignment);
12647 if (VT.isVector()) {
12648 // For a vector, cast operands to a vector type, perform the logic op,
12649 // and cast the result back to the original value type.
12650 MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);
12651 SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);
12652 SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))
12653 : DAG.getBitcast(VecVT, Op0);
12654 unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;
12655 return DAG.getBitcast(VT,
12656 DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));
12659 // If not vector, then scalar.
12660 unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;
12661 SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;
12662 return DAG.getNode(BitOp, dl, VT, Operand, Mask);
12665 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
12666 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12667 LLVMContext *Context = DAG.getContext();
12668 SDValue Op0 = Op.getOperand(0);
12669 SDValue Op1 = Op.getOperand(1);
12671 MVT VT = Op.getSimpleValueType();
12672 MVT SrcVT = Op1.getSimpleValueType();
12674 // If second operand is smaller, extend it first.
12675 if (SrcVT.bitsLT(VT)) {
12676 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
12679 // And if it is bigger, shrink it first.
12680 if (SrcVT.bitsGT(VT)) {
12681 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));
12685 // At this point the operands and the result should have the same
12686 // type, and that won't be f80 since that is not custom lowered.
12688 const fltSemantics &Sem =
12689 VT == MVT::f64 ? APFloat::IEEEdouble : APFloat::IEEEsingle;
12690 const unsigned SizeInBits = VT.getSizeInBits();
12692 SmallVector<Constant *, 4> CV(
12693 VT == MVT::f64 ? 2 : 4,
12694 ConstantFP::get(*Context, APFloat(Sem, APInt(SizeInBits, 0))));
12696 // First, clear all bits but the sign bit from the second operand (sign).
12697 CV[0] = ConstantFP::get(*Context,
12698 APFloat(Sem, APInt::getHighBitsSet(SizeInBits, 1)));
12699 Constant *C = ConstantVector::get(CV);
12700 SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12701 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
12702 MachinePointerInfo::getConstantPool(),
12703 false, false, false, 16);
12704 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
12706 // Next, clear the sign bit from the first operand (magnitude).
12707 // If it's a constant, we can clear it here.
12708 if (ConstantFPSDNode *Op0CN = dyn_cast<ConstantFPSDNode>(Op0)) {
12709 APFloat APF = Op0CN->getValueAPF();
12710 // If the magnitude is a positive zero, the sign bit alone is enough.
12711 if (APF.isPosZero())
12714 CV[0] = ConstantFP::get(*Context, APF);
12716 CV[0] = ConstantFP::get(
12718 APFloat(Sem, APInt::getLowBitsSet(SizeInBits, SizeInBits - 1)));
12720 C = ConstantVector::get(CV);
12721 CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(), 16);
12722 SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
12723 MachinePointerInfo::getConstantPool(),
12724 false, false, false, 16);
12725 // If the magnitude operand wasn't a constant, we need to AND out the sign.
12726 if (!isa<ConstantFPSDNode>(Op0))
12727 Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);
12729 // OR the magnitude value with the sign bit.
12730 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
12733 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
12734 SDValue N0 = Op.getOperand(0);
12736 MVT VT = Op.getSimpleValueType();
12738 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
12739 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
12740 DAG.getConstant(1, dl, VT));
12741 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));
12744 // Check whether an OR'd tree is PTEST-able.
12745 static SDValue LowerVectorAllZeroTest(SDValue Op, const X86Subtarget *Subtarget,
12746 SelectionDAG &DAG) {
12747 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
12749 if (!Subtarget->hasSSE41())
12752 if (!Op->hasOneUse())
12755 SDNode *N = Op.getNode();
12758 SmallVector<SDValue, 8> Opnds;
12759 DenseMap<SDValue, unsigned> VecInMap;
12760 SmallVector<SDValue, 8> VecIns;
12761 EVT VT = MVT::Other;
12763 // Recognize a special case where a vector is casted into wide integer to
12765 Opnds.push_back(N->getOperand(0));
12766 Opnds.push_back(N->getOperand(1));
12768 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
12769 SmallVectorImpl<SDValue>::const_iterator I = Opnds.begin() + Slot;
12770 // BFS traverse all OR'd operands.
12771 if (I->getOpcode() == ISD::OR) {
12772 Opnds.push_back(I->getOperand(0));
12773 Opnds.push_back(I->getOperand(1));
12774 // Re-evaluate the number of nodes to be traversed.
12775 e += 2; // 2 more nodes (LHS and RHS) are pushed.
12779 // Quit if a non-EXTRACT_VECTOR_ELT
12780 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
12783 // Quit if without a constant index.
12784 SDValue Idx = I->getOperand(1);
12785 if (!isa<ConstantSDNode>(Idx))
12788 SDValue ExtractedFromVec = I->getOperand(0);
12789 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
12790 if (M == VecInMap.end()) {
12791 VT = ExtractedFromVec.getValueType();
12792 // Quit if not 128/256-bit vector.
12793 if (!VT.is128BitVector() && !VT.is256BitVector())
12795 // Quit if not the same type.
12796 if (VecInMap.begin() != VecInMap.end() &&
12797 VT != VecInMap.begin()->first.getValueType())
12799 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
12800 VecIns.push_back(ExtractedFromVec);
12802 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
12805 assert((VT.is128BitVector() || VT.is256BitVector()) &&
12806 "Not extracted from 128-/256-bit vector.");
12808 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
12810 for (DenseMap<SDValue, unsigned>::const_iterator
12811 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
12812 // Quit if not all elements are used.
12813 if (I->second != FullMask)
12817 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
12819 // Cast all vectors into TestVT for PTEST.
12820 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
12821 VecIns[i] = DAG.getBitcast(TestVT, VecIns[i]);
12823 // If more than one full vectors are evaluated, OR them first before PTEST.
12824 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
12825 // Each iteration will OR 2 nodes and append the result until there is only
12826 // 1 node left, i.e. the final OR'd value of all vectors.
12827 SDValue LHS = VecIns[Slot];
12828 SDValue RHS = VecIns[Slot + 1];
12829 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
12832 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
12833 VecIns.back(), VecIns.back());
12836 /// \brief return true if \c Op has a use that doesn't just read flags.
12837 static bool hasNonFlagsUse(SDValue Op) {
12838 for (SDNode::use_iterator UI = Op->use_begin(), UE = Op->use_end(); UI != UE;
12840 SDNode *User = *UI;
12841 unsigned UOpNo = UI.getOperandNo();
12842 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
12843 // Look pass truncate.
12844 UOpNo = User->use_begin().getOperandNo();
12845 User = *User->use_begin();
12848 if (User->getOpcode() != ISD::BRCOND && User->getOpcode() != ISD::SETCC &&
12849 !(User->getOpcode() == ISD::SELECT && UOpNo == 0))
12855 /// Emit nodes that will be selected as "test Op0,Op0", or something
12857 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, SDLoc dl,
12858 SelectionDAG &DAG) const {
12859 if (Op.getValueType() == MVT::i1) {
12860 SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);
12861 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,
12862 DAG.getConstant(0, dl, MVT::i8));
12864 // CF and OF aren't always set the way we want. Determine which
12865 // of these we need.
12866 bool NeedCF = false;
12867 bool NeedOF = false;
12870 case X86::COND_A: case X86::COND_AE:
12871 case X86::COND_B: case X86::COND_BE:
12874 case X86::COND_G: case X86::COND_GE:
12875 case X86::COND_L: case X86::COND_LE:
12876 case X86::COND_O: case X86::COND_NO: {
12877 // Check if we really need to set the
12878 // Overflow flag. If NoSignedWrap is present
12879 // that is not actually needed.
12880 switch (Op->getOpcode()) {
12885 const auto *BinNode = cast<BinaryWithFlagsSDNode>(Op.getNode());
12886 if (BinNode->Flags.hasNoSignedWrap())
12896 // See if we can use the EFLAGS value from the operand instead of
12897 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
12898 // we prove that the arithmetic won't overflow, we can't use OF or CF.
12899 if (Op.getResNo() != 0 || NeedOF || NeedCF) {
12900 // Emit a CMP with 0, which is the TEST pattern.
12901 //if (Op.getValueType() == MVT::i1)
12902 // return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,
12903 // DAG.getConstant(0, MVT::i1));
12904 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
12905 DAG.getConstant(0, dl, Op.getValueType()));
12907 unsigned Opcode = 0;
12908 unsigned NumOperands = 0;
12910 // Truncate operations may prevent the merge of the SETCC instruction
12911 // and the arithmetic instruction before it. Attempt to truncate the operands
12912 // of the arithmetic instruction and use a reduced bit-width instruction.
12913 bool NeedTruncation = false;
12914 SDValue ArithOp = Op;
12915 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
12916 SDValue Arith = Op->getOperand(0);
12917 // Both the trunc and the arithmetic op need to have one user each.
12918 if (Arith->hasOneUse())
12919 switch (Arith.getOpcode()) {
12926 NeedTruncation = true;
12932 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
12933 // which may be the result of a CAST. We use the variable 'Op', which is the
12934 // non-casted variable when we check for possible users.
12935 switch (ArithOp.getOpcode()) {
12937 // Due to an isel shortcoming, be conservative if this add is likely to be
12938 // selected as part of a load-modify-store instruction. When the root node
12939 // in a match is a store, isel doesn't know how to remap non-chain non-flag
12940 // uses of other nodes in the match, such as the ADD in this case. This
12941 // leads to the ADD being left around and reselected, with the result being
12942 // two adds in the output. Alas, even if none our users are stores, that
12943 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
12944 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
12945 // climbing the DAG back to the root, and it doesn't seem to be worth the
12947 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
12948 UE = Op.getNode()->use_end(); UI != UE; ++UI)
12949 if (UI->getOpcode() != ISD::CopyToReg &&
12950 UI->getOpcode() != ISD::SETCC &&
12951 UI->getOpcode() != ISD::STORE)
12954 if (ConstantSDNode *C =
12955 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
12956 // An add of one will be selected as an INC.
12957 if (C->getAPIntValue() == 1 && !Subtarget->slowIncDec()) {
12958 Opcode = X86ISD::INC;
12963 // An add of negative one (subtract of one) will be selected as a DEC.
12964 if (C->getAPIntValue().isAllOnesValue() && !Subtarget->slowIncDec()) {
12965 Opcode = X86ISD::DEC;
12971 // Otherwise use a regular EFLAGS-setting add.
12972 Opcode = X86ISD::ADD;
12977 // If we have a constant logical shift that's only used in a comparison
12978 // against zero turn it into an equivalent AND. This allows turning it into
12979 // a TEST instruction later.
12980 if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
12981 isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
12982 EVT VT = Op.getValueType();
12983 unsigned BitWidth = VT.getSizeInBits();
12984 unsigned ShAmt = Op->getConstantOperandVal(1);
12985 if (ShAmt >= BitWidth) // Avoid undefined shifts.
12987 APInt Mask = ArithOp.getOpcode() == ISD::SRL
12988 ? APInt::getHighBitsSet(BitWidth, BitWidth - ShAmt)
12989 : APInt::getLowBitsSet(BitWidth, BitWidth - ShAmt);
12990 if (!Mask.isSignedIntN(32)) // Avoid large immediates.
12992 SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),
12993 DAG.getConstant(Mask, dl, VT));
12994 DAG.ReplaceAllUsesWith(Op, New);
13000 // If the primary and result isn't used, don't bother using X86ISD::AND,
13001 // because a TEST instruction will be better.
13002 if (!hasNonFlagsUse(Op))
13008 // Due to the ISEL shortcoming noted above, be conservative if this op is
13009 // likely to be selected as part of a load-modify-store instruction.
13010 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
13011 UE = Op.getNode()->use_end(); UI != UE; ++UI)
13012 if (UI->getOpcode() == ISD::STORE)
13015 // Otherwise use a regular EFLAGS-setting instruction.
13016 switch (ArithOp.getOpcode()) {
13017 default: llvm_unreachable("unexpected operator!");
13018 case ISD::SUB: Opcode = X86ISD::SUB; break;
13019 case ISD::XOR: Opcode = X86ISD::XOR; break;
13020 case ISD::AND: Opcode = X86ISD::AND; break;
13022 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
13023 SDValue EFLAGS = LowerVectorAllZeroTest(Op, Subtarget, DAG);
13024 if (EFLAGS.getNode())
13027 Opcode = X86ISD::OR;
13041 return SDValue(Op.getNode(), 1);
13047 // If we found that truncation is beneficial, perform the truncation and
13049 if (NeedTruncation) {
13050 EVT VT = Op.getValueType();
13051 SDValue WideVal = Op->getOperand(0);
13052 EVT WideVT = WideVal.getValueType();
13053 unsigned ConvertedOp = 0;
13054 // Use a target machine opcode to prevent further DAGCombine
13055 // optimizations that may separate the arithmetic operations
13056 // from the setcc node.
13057 switch (WideVal.getOpcode()) {
13059 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
13060 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
13061 case ISD::AND: ConvertedOp = X86ISD::AND; break;
13062 case ISD::OR: ConvertedOp = X86ISD::OR; break;
13063 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
13067 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
13068 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
13069 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
13070 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
13071 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
13077 // Emit a CMP with 0, which is the TEST pattern.
13078 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
13079 DAG.getConstant(0, dl, Op.getValueType()));
13081 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
13082 SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);
13084 SDValue New = DAG.getNode(Opcode, dl, VTs, Ops);
13085 DAG.ReplaceAllUsesWith(Op, New);
13086 return SDValue(New.getNode(), 1);
13089 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
13091 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
13092 SDLoc dl, SelectionDAG &DAG) const {
13093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) {
13094 if (C->getAPIntValue() == 0)
13095 return EmitTest(Op0, X86CC, dl, DAG);
13097 if (Op0.getValueType() == MVT::i1)
13098 llvm_unreachable("Unexpected comparison operation for MVT::i1 operands");
13101 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
13102 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
13103 // Do the comparison at i32 if it's smaller, besides the Atom case.
13104 // This avoids subregister aliasing issues. Keep the smaller reference
13105 // if we're optimizing for size, however, as that'll allow better folding
13106 // of memory operations.
13107 if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
13108 !DAG.getMachineFunction().getFunction()->hasFnAttribute(
13109 Attribute::MinSize) &&
13110 !Subtarget->isAtom()) {
13111 unsigned ExtendOp =
13112 isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
13113 Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);
13114 Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);
13116 // Use SUB instead of CMP to enable CSE between SUB and CMP.
13117 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
13118 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
13120 return SDValue(Sub.getNode(), 1);
13122 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
13125 /// Convert a comparison if required by the subtarget.
13126 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
13127 SelectionDAG &DAG) const {
13128 // If the subtarget does not support the FUCOMI instruction, floating-point
13129 // comparisons have to be converted.
13130 if (Subtarget->hasCMov() ||
13131 Cmp.getOpcode() != X86ISD::CMP ||
13132 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
13133 !Cmp.getOperand(1).getValueType().isFloatingPoint())
13136 // The instruction selector will select an FUCOM instruction instead of
13137 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
13138 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
13139 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
13141 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
13142 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
13143 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
13144 DAG.getConstant(8, dl, MVT::i8));
13145 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
13146 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
13149 /// The minimum architected relative accuracy is 2^-12. We need one
13150 /// Newton-Raphson step to have a good float result (24 bits of precision).
13151 SDValue X86TargetLowering::getRsqrtEstimate(SDValue Op,
13152 DAGCombinerInfo &DCI,
13153 unsigned &RefinementSteps,
13154 bool &UseOneConstNR) const {
13155 EVT VT = Op.getValueType();
13156 const char *RecipOp;
13158 // SSE1 has rsqrtss and rsqrtps. AVX adds a 256-bit variant for rsqrtps.
13159 // TODO: Add support for AVX512 (v16f32).
13160 // It is likely not profitable to do this for f64 because a double-precision
13161 // rsqrt estimate with refinement on x86 prior to FMA requires at least 16
13162 // instructions: convert to single, rsqrtss, convert back to double, refine
13163 // (3 steps = at least 13 insts). If an 'rsqrtsd' variant was added to the ISA
13164 // along with FMA, this could be a throughput win.
13165 if (VT == MVT::f32 && Subtarget->hasSSE1())
13167 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13168 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13169 RecipOp = "vec-sqrtf";
13173 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13174 if (!Recips.isEnabled(RecipOp))
13177 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13178 UseOneConstNR = false;
13179 return DCI.DAG.getNode(X86ISD::FRSQRT, SDLoc(Op), VT, Op);
13182 /// The minimum architected relative accuracy is 2^-12. We need one
13183 /// Newton-Raphson step to have a good float result (24 bits of precision).
13184 SDValue X86TargetLowering::getRecipEstimate(SDValue Op,
13185 DAGCombinerInfo &DCI,
13186 unsigned &RefinementSteps) const {
13187 EVT VT = Op.getValueType();
13188 const char *RecipOp;
13190 // SSE1 has rcpss and rcpps. AVX adds a 256-bit variant for rcpps.
13191 // TODO: Add support for AVX512 (v16f32).
13192 // It is likely not profitable to do this for f64 because a double-precision
13193 // reciprocal estimate with refinement on x86 prior to FMA requires
13194 // 15 instructions: convert to single, rcpss, convert back to double, refine
13195 // (3 steps = 12 insts). If an 'rcpsd' variant was added to the ISA
13196 // along with FMA, this could be a throughput win.
13197 if (VT == MVT::f32 && Subtarget->hasSSE1())
13199 else if ((VT == MVT::v4f32 && Subtarget->hasSSE1()) ||
13200 (VT == MVT::v8f32 && Subtarget->hasAVX()))
13201 RecipOp = "vec-divf";
13205 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
13206 if (!Recips.isEnabled(RecipOp))
13209 RefinementSteps = Recips.getRefinementSteps(RecipOp);
13210 return DCI.DAG.getNode(X86ISD::FRCP, SDLoc(Op), VT, Op);
13213 /// If we have at least two divisions that use the same divisor, convert to
13214 /// multplication by a reciprocal. This may need to be adjusted for a given
13215 /// CPU if a division's cost is not at least twice the cost of a multiplication.
13216 /// This is because we still need one division to calculate the reciprocal and
13217 /// then we need two multiplies by that reciprocal as replacements for the
13218 /// original divisions.
13219 bool X86TargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
13220 return NumUsers > 1;
13223 static bool isAllOnes(SDValue V) {
13224 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
13225 return C && C->isAllOnesValue();
13228 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
13229 /// if it's possible.
13230 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
13231 SDLoc dl, SelectionDAG &DAG) const {
13232 SDValue Op0 = And.getOperand(0);
13233 SDValue Op1 = And.getOperand(1);
13234 if (Op0.getOpcode() == ISD::TRUNCATE)
13235 Op0 = Op0.getOperand(0);
13236 if (Op1.getOpcode() == ISD::TRUNCATE)
13237 Op1 = Op1.getOperand(0);
13240 if (Op1.getOpcode() == ISD::SHL)
13241 std::swap(Op0, Op1);
13242 if (Op0.getOpcode() == ISD::SHL) {
13243 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
13244 if (And00C->getZExtValue() == 1) {
13245 // If we looked past a truncate, check that it's only truncating away
13247 unsigned BitWidth = Op0.getValueSizeInBits();
13248 unsigned AndBitWidth = And.getValueSizeInBits();
13249 if (BitWidth > AndBitWidth) {
13251 DAG.computeKnownBits(Op0, Zeros, Ones);
13252 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
13256 RHS = Op0.getOperand(1);
13258 } else if (Op1.getOpcode() == ISD::Constant) {
13259 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
13260 uint64_t AndRHSVal = AndRHS->getZExtValue();
13261 SDValue AndLHS = Op0;
13263 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
13264 LHS = AndLHS.getOperand(0);
13265 RHS = AndLHS.getOperand(1);
13268 // Use BT if the immediate can't be encoded in a TEST instruction.
13269 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
13271 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());
13275 if (LHS.getNode()) {
13276 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
13277 // instruction. Since the shift amount is in-range-or-undefined, we know
13278 // that doing a bittest on the i32 value is ok. We extend to i32 because
13279 // the encoding for the i16 version is larger than the i32 version.
13280 // Also promote i16 to i32 for performance / code size reason.
13281 if (LHS.getValueType() == MVT::i8 ||
13282 LHS.getValueType() == MVT::i16)
13283 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
13285 // If the operand types disagree, extend the shift amount to match. Since
13286 // BT ignores high bits (like shifts) we can use anyextend.
13287 if (LHS.getValueType() != RHS.getValueType())
13288 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
13290 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
13291 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
13292 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13293 DAG.getConstant(Cond, dl, MVT::i8), BT);
13299 /// \brief - Turns an ISD::CondCode into a value suitable for SSE floating point
13301 static int translateX86FSETCC(ISD::CondCode SetCCOpcode, SDValue &Op0,
13306 // SSE Condition code mapping:
13315 switch (SetCCOpcode) {
13316 default: llvm_unreachable("Unexpected SETCC condition");
13318 case ISD::SETEQ: SSECC = 0; break;
13320 case ISD::SETGT: Swap = true; // Fallthrough
13322 case ISD::SETOLT: SSECC = 1; break;
13324 case ISD::SETGE: Swap = true; // Fallthrough
13326 case ISD::SETOLE: SSECC = 2; break;
13327 case ISD::SETUO: SSECC = 3; break;
13329 case ISD::SETNE: SSECC = 4; break;
13330 case ISD::SETULE: Swap = true; // Fallthrough
13331 case ISD::SETUGE: SSECC = 5; break;
13332 case ISD::SETULT: Swap = true; // Fallthrough
13333 case ISD::SETUGT: SSECC = 6; break;
13334 case ISD::SETO: SSECC = 7; break;
13336 case ISD::SETONE: SSECC = 8; break;
13339 std::swap(Op0, Op1);
13344 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
13345 // ones, and then concatenate the result back.
13346 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
13347 MVT VT = Op.getSimpleValueType();
13349 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
13350 "Unsupported value type for operation");
13352 unsigned NumElems = VT.getVectorNumElements();
13354 SDValue CC = Op.getOperand(2);
13356 // Extract the LHS vectors
13357 SDValue LHS = Op.getOperand(0);
13358 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
13359 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
13361 // Extract the RHS vectors
13362 SDValue RHS = Op.getOperand(1);
13363 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
13364 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
13366 // Issue the operation on the smaller types and concatenate the result back
13367 MVT EltVT = VT.getVectorElementType();
13368 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
13369 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
13370 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
13371 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
13374 static SDValue LowerBoolVSETCC_AVX512(SDValue Op, SelectionDAG &DAG) {
13375 SDValue Op0 = Op.getOperand(0);
13376 SDValue Op1 = Op.getOperand(1);
13377 SDValue CC = Op.getOperand(2);
13378 MVT VT = Op.getSimpleValueType();
13381 assert(Op0.getValueType().getVectorElementType() == MVT::i1 &&
13382 "Unexpected type for boolean compare operation");
13383 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13384 SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,
13385 DAG.getConstant(-1, dl, VT));
13386 SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,
13387 DAG.getConstant(-1, dl, VT));
13388 switch (SetCCOpcode) {
13389 default: llvm_unreachable("Unexpected SETCC condition");
13391 // (x == y) -> ~(x ^ y)
13392 return DAG.getNode(ISD::XOR, dl, VT,
13393 DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),
13394 DAG.getConstant(-1, dl, VT));
13396 // (x != y) -> (x ^ y)
13397 return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);
13400 // (x > y) -> (x & ~y)
13401 return DAG.getNode(ISD::AND, dl, VT, Op0, NotOp1);
13404 // (x < y) -> (~x & y)
13405 return DAG.getNode(ISD::AND, dl, VT, NotOp0, Op1);
13408 // (x <= y) -> (~x | y)
13409 return DAG.getNode(ISD::OR, dl, VT, NotOp0, Op1);
13412 // (x >=y) -> (x | ~y)
13413 return DAG.getNode(ISD::OR, dl, VT, Op0, NotOp1);
13417 static SDValue LowerIntVSETCC_AVX512(SDValue Op, SelectionDAG &DAG,
13418 const X86Subtarget *Subtarget) {
13419 SDValue Op0 = Op.getOperand(0);
13420 SDValue Op1 = Op.getOperand(1);
13421 SDValue CC = Op.getOperand(2);
13422 MVT VT = Op.getSimpleValueType();
13425 assert(Op0.getValueType().getVectorElementType().getSizeInBits() >= 8 &&
13426 Op.getValueType().getScalarType() == MVT::i1 &&
13427 "Cannot set masked compare for this operation");
13429 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13431 bool Unsigned = false;
13434 switch (SetCCOpcode) {
13435 default: llvm_unreachable("Unexpected SETCC condition");
13436 case ISD::SETNE: SSECC = 4; break;
13437 case ISD::SETEQ: Opc = X86ISD::PCMPEQM; break;
13438 case ISD::SETUGT: SSECC = 6; Unsigned = true; break;
13439 case ISD::SETLT: Swap = true; //fall-through
13440 case ISD::SETGT: Opc = X86ISD::PCMPGTM; break;
13441 case ISD::SETULT: SSECC = 1; Unsigned = true; break;
13442 case ISD::SETUGE: SSECC = 5; Unsigned = true; break; //NLT
13443 case ISD::SETGE: Swap = true; SSECC = 2; break; // LE + swap
13444 case ISD::SETULE: Unsigned = true; //fall-through
13445 case ISD::SETLE: SSECC = 2; break;
13449 std::swap(Op0, Op1);
13451 return DAG.getNode(Opc, dl, VT, Op0, Op1);
13452 Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;
13453 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13454 DAG.getConstant(SSECC, dl, MVT::i8));
13457 /// \brief Try to turn a VSETULT into a VSETULE by modifying its second
13458 /// operand \p Op1. If non-trivial (for example because it's not constant)
13459 /// return an empty value.
13460 static SDValue ChangeVSETULTtoVSETULE(SDLoc dl, SDValue Op1, SelectionDAG &DAG)
13462 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Op1.getNode());
13466 MVT VT = Op1.getSimpleValueType();
13467 MVT EVT = VT.getVectorElementType();
13468 unsigned n = VT.getVectorNumElements();
13469 SmallVector<SDValue, 8> ULTOp1;
13471 for (unsigned i = 0; i < n; ++i) {
13472 ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
13473 if (!Elt || Elt->isOpaque() || Elt->getValueType(0) != EVT)
13476 // Avoid underflow.
13477 APInt Val = Elt->getAPIntValue();
13481 ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));
13484 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);
13487 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
13488 SelectionDAG &DAG) {
13489 SDValue Op0 = Op.getOperand(0);
13490 SDValue Op1 = Op.getOperand(1);
13491 SDValue CC = Op.getOperand(2);
13492 MVT VT = Op.getSimpleValueType();
13493 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
13494 bool isFP = Op.getOperand(1).getSimpleValueType().isFloatingPoint();
13499 MVT EltVT = Op0.getSimpleValueType().getVectorElementType();
13500 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
13503 unsigned SSECC = translateX86FSETCC(SetCCOpcode, Op0, Op1);
13504 unsigned Opc = X86ISD::CMPP;
13505 if (Subtarget->hasAVX512() && VT.getVectorElementType() == MVT::i1) {
13506 assert(VT.getVectorNumElements() <= 16);
13507 Opc = X86ISD::CMPM;
13509 // In the two special cases we can't handle, emit two comparisons.
13512 unsigned CombineOpc;
13513 if (SetCCOpcode == ISD::SETUEQ) {
13514 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
13516 assert(SetCCOpcode == ISD::SETONE);
13517 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
13520 SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13521 DAG.getConstant(CC0, dl, MVT::i8));
13522 SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,
13523 DAG.getConstant(CC1, dl, MVT::i8));
13524 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
13526 // Handle all other FP comparisons here.
13527 return DAG.getNode(Opc, dl, VT, Op0, Op1,
13528 DAG.getConstant(SSECC, dl, MVT::i8));
13531 // Break 256-bit integer vector compare into smaller ones.
13532 if (VT.is256BitVector() && !Subtarget->hasInt256())
13533 return Lower256IntVSETCC(Op, DAG);
13535 EVT OpVT = Op1.getValueType();
13536 if (OpVT.getVectorElementType() == MVT::i1)
13537 return LowerBoolVSETCC_AVX512(Op, DAG);
13539 bool MaskResult = (VT.getVectorElementType() == MVT::i1);
13540 if (Subtarget->hasAVX512()) {
13541 if (Op1.getValueType().is512BitVector() ||
13542 (Subtarget->hasBWI() && Subtarget->hasVLX()) ||
13543 (MaskResult && OpVT.getVectorElementType().getSizeInBits() >= 32))
13544 return LowerIntVSETCC_AVX512(Op, DAG, Subtarget);
13546 // In AVX-512 architecture setcc returns mask with i1 elements,
13547 // But there is no compare instruction for i8 and i16 elements in KNL.
13548 // We are not talking about 512-bit operands in this case, these
13549 // types are illegal.
13551 (OpVT.getVectorElementType().getSizeInBits() < 32 &&
13552 OpVT.getVectorElementType().getSizeInBits() >= 8))
13553 return DAG.getNode(ISD::TRUNCATE, dl, VT,
13554 DAG.getNode(ISD::SETCC, dl, OpVT, Op0, Op1, CC));
13557 // We are handling one of the integer comparisons here. Since SSE only has
13558 // GT and EQ comparisons for integer, swapping operands and multiple
13559 // operations may be required for some comparisons.
13561 bool Swap = false, Invert = false, FlipSigns = false, MinMax = false;
13562 bool Subus = false;
13564 switch (SetCCOpcode) {
13565 default: llvm_unreachable("Unexpected SETCC condition");
13566 case ISD::SETNE: Invert = true;
13567 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
13568 case ISD::SETLT: Swap = true;
13569 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
13570 case ISD::SETGE: Swap = true;
13571 case ISD::SETLE: Opc = X86ISD::PCMPGT;
13572 Invert = true; break;
13573 case ISD::SETULT: Swap = true;
13574 case ISD::SETUGT: Opc = X86ISD::PCMPGT;
13575 FlipSigns = true; break;
13576 case ISD::SETUGE: Swap = true;
13577 case ISD::SETULE: Opc = X86ISD::PCMPGT;
13578 FlipSigns = true; Invert = true; break;
13581 // Special case: Use min/max operations for SETULE/SETUGE
13582 MVT VET = VT.getVectorElementType();
13584 (Subtarget->hasSSE41() && (VET >= MVT::i8 && VET <= MVT::i32))
13585 || (Subtarget->hasSSE2() && (VET == MVT::i8));
13588 switch (SetCCOpcode) {
13590 case ISD::SETULE: Opc = ISD::UMIN; MinMax = true; break;
13591 case ISD::SETUGE: Opc = ISD::UMAX; MinMax = true; break;
13594 if (MinMax) { Swap = false; Invert = false; FlipSigns = false; }
13597 bool hasSubus = Subtarget->hasSSE2() && (VET == MVT::i8 || VET == MVT::i16);
13598 if (!MinMax && hasSubus) {
13599 // As another special case, use PSUBUS[BW] when it's profitable. E.g. for
13601 // t = psubus Op0, Op1
13602 // pcmpeq t, <0..0>
13603 switch (SetCCOpcode) {
13605 case ISD::SETULT: {
13606 // If the comparison is against a constant we can turn this into a
13607 // setule. With psubus, setule does not require a swap. This is
13608 // beneficial because the constant in the register is no longer
13609 // destructed as the destination so it can be hoisted out of a loop.
13610 // Only do this pre-AVX since vpcmp* is no longer destructive.
13611 if (Subtarget->hasAVX())
13613 SDValue ULEOp1 = ChangeVSETULTtoVSETULE(dl, Op1, DAG);
13614 if (ULEOp1.getNode()) {
13616 Subus = true; Invert = false; Swap = false;
13620 // Psubus is better than flip-sign because it requires no inversion.
13621 case ISD::SETUGE: Subus = true; Invert = false; Swap = true; break;
13622 case ISD::SETULE: Subus = true; Invert = false; Swap = false; break;
13626 Opc = X86ISD::SUBUS;
13632 std::swap(Op0, Op1);
13634 // Check that the operation in question is available (most are plain SSE2,
13635 // but PCMPGTQ and PCMPEQQ have different requirements).
13636 if (VT == MVT::v2i64) {
13637 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
13638 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
13640 // First cast everything to the right type.
13641 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13642 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13644 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13645 // bits of the inputs before performing those operations. The lower
13646 // compare is always unsigned.
13649 SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);
13651 SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);
13652 SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);
13653 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
13654 Sign, Zero, Sign, Zero);
13656 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
13657 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
13659 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
13660 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
13661 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
13663 // Create masks for only the low parts/high parts of the 64 bit integers.
13664 static const int MaskHi[] = { 1, 1, 3, 3 };
13665 static const int MaskLo[] = { 0, 0, 2, 2 };
13666 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
13667 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
13668 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
13670 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
13671 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
13674 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13676 return DAG.getBitcast(VT, Result);
13679 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
13680 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
13681 // pcmpeqd + pshufd + pand.
13682 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
13684 // First cast everything to the right type.
13685 Op0 = DAG.getBitcast(MVT::v4i32, Op0);
13686 Op1 = DAG.getBitcast(MVT::v4i32, Op1);
13689 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
13691 // Make sure the lower and upper halves are both all-ones.
13692 static const int Mask[] = { 1, 0, 3, 2 };
13693 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
13694 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
13697 Result = DAG.getNOT(dl, Result, MVT::v4i32);
13699 return DAG.getBitcast(VT, Result);
13703 // Since SSE has no unsigned integer comparisons, we need to flip the sign
13704 // bits of the inputs before performing those operations.
13706 EVT EltVT = VT.getVectorElementType();
13707 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,
13709 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
13710 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
13713 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
13715 // If the logical-not of the result is required, perform that now.
13717 Result = DAG.getNOT(dl, Result, VT);
13720 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Op0, Result);
13723 Result = DAG.getNode(X86ISD::PCMPEQ, dl, VT, Result,
13724 getZeroVector(VT, Subtarget, DAG, dl));
13729 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
13731 MVT VT = Op.getSimpleValueType();
13733 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
13735 assert(((!Subtarget->hasAVX512() && VT == MVT::i8) || (VT == MVT::i1))
13736 && "SetCC type must be 8-bit or 1-bit integer");
13737 SDValue Op0 = Op.getOperand(0);
13738 SDValue Op1 = Op.getOperand(1);
13740 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
13742 // Optimize to BT if possible.
13743 // Lower (X & (1 << N)) == 0 to BT(X, N).
13744 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
13745 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
13746 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
13747 Op1.getOpcode() == ISD::Constant &&
13748 cast<ConstantSDNode>(Op1)->isNullValue() &&
13749 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13750 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
13751 if (NewSetCC.getNode()) {
13753 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewSetCC);
13758 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
13760 if (Op1.getOpcode() == ISD::Constant &&
13761 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
13762 cast<ConstantSDNode>(Op1)->isNullValue()) &&
13763 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13765 // If the input is a setcc, then reuse the input setcc or use a new one with
13766 // the inverted condition.
13767 if (Op0.getOpcode() == X86ISD::SETCC) {
13768 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
13769 bool Invert = (CC == ISD::SETNE) ^
13770 cast<ConstantSDNode>(Op1)->isNullValue();
13774 CCode = X86::GetOppositeBranchCondition(CCode);
13775 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13776 DAG.getConstant(CCode, dl, MVT::i8),
13777 Op0.getOperand(1));
13779 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13783 if ((Op0.getValueType() == MVT::i1) && (Op1.getOpcode() == ISD::Constant) &&
13784 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1) &&
13785 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
13787 ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);
13788 return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);
13791 bool isFP = Op1.getSimpleValueType().isFloatingPoint();
13792 unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);
13793 if (X86CC == X86::COND_INVALID)
13796 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);
13797 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
13798 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
13799 DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);
13801 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);
13805 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
13806 static bool isX86LogicalCmp(SDValue Op) {
13807 unsigned Opc = Op.getNode()->getOpcode();
13808 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
13809 Opc == X86ISD::SAHF)
13811 if (Op.getResNo() == 1 &&
13812 (Opc == X86ISD::ADD ||
13813 Opc == X86ISD::SUB ||
13814 Opc == X86ISD::ADC ||
13815 Opc == X86ISD::SBB ||
13816 Opc == X86ISD::SMUL ||
13817 Opc == X86ISD::UMUL ||
13818 Opc == X86ISD::INC ||
13819 Opc == X86ISD::DEC ||
13820 Opc == X86ISD::OR ||
13821 Opc == X86ISD::XOR ||
13822 Opc == X86ISD::AND))
13825 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
13831 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
13832 if (V.getOpcode() != ISD::TRUNCATE)
13835 SDValue VOp0 = V.getOperand(0);
13836 unsigned InBits = VOp0.getValueSizeInBits();
13837 unsigned Bits = V.getValueSizeInBits();
13838 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
13841 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
13842 bool addTest = true;
13843 SDValue Cond = Op.getOperand(0);
13844 SDValue Op1 = Op.getOperand(1);
13845 SDValue Op2 = Op.getOperand(2);
13847 EVT VT = Op1.getValueType();
13850 // Lower FP selects into a CMP/AND/ANDN/OR sequence when the necessary SSE ops
13851 // are available or VBLENDV if AVX is available.
13852 // Otherwise FP cmovs get lowered into a less efficient branch sequence later.
13853 if (Cond.getOpcode() == ISD::SETCC &&
13854 ((Subtarget->hasSSE2() && (VT == MVT::f32 || VT == MVT::f64)) ||
13855 (Subtarget->hasSSE1() && VT == MVT::f32)) &&
13856 VT == Cond.getOperand(0).getValueType() && Cond->hasOneUse()) {
13857 SDValue CondOp0 = Cond.getOperand(0), CondOp1 = Cond.getOperand(1);
13858 int SSECC = translateX86FSETCC(
13859 cast<CondCodeSDNode>(Cond.getOperand(2))->get(), CondOp0, CondOp1);
13862 if (Subtarget->hasAVX512()) {
13863 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,
13864 DAG.getConstant(SSECC, DL, MVT::i8));
13865 return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);
13868 SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
13869 DAG.getConstant(SSECC, DL, MVT::i8));
13871 // If we have AVX, we can use a variable vector select (VBLENDV) instead
13872 // of 3 logic instructions for size savings and potentially speed.
13873 // Unfortunately, there is no scalar form of VBLENDV.
13875 // If either operand is a constant, don't try this. We can expect to
13876 // optimize away at least one of the logic instructions later in that
13877 // case, so that sequence would be faster than a variable blend.
13879 // BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
13880 // uses XMM0 as the selection register. That may need just as many
13881 // instructions as the AND/ANDN/OR sequence due to register moves, so
13884 if (Subtarget->hasAVX() &&
13885 !isa<ConstantFPSDNode>(Op1) && !isa<ConstantFPSDNode>(Op2)) {
13887 // Convert to vectors, do a VSELECT, and convert back to scalar.
13888 // All of the conversions should be optimized away.
13890 EVT VecVT = VT == MVT::f32 ? MVT::v4f32 : MVT::v2f64;
13891 SDValue VOp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op1);
13892 SDValue VOp2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Op2);
13893 SDValue VCmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, Cmp);
13895 EVT VCmpVT = VT == MVT::f32 ? MVT::v4i32 : MVT::v2i64;
13896 VCmp = DAG.getBitcast(VCmpVT, VCmp);
13898 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
13900 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,
13901 VSel, DAG.getIntPtrConstant(0, DL));
13903 SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);
13904 SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);
13905 return DAG.getNode(X86ISD::FOR, DL, VT, AndN, And);
13909 if (VT.isVector() && VT.getScalarType() == MVT::i1) {
13911 if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
13912 Op1Scalar = ConvertI1VectorToInterger(Op1, DAG);
13913 else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
13914 Op1Scalar = Op1.getOperand(0);
13916 if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
13917 Op2Scalar = ConvertI1VectorToInterger(Op2, DAG);
13918 else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
13919 Op2Scalar = Op2.getOperand(0);
13920 if (Op1Scalar.getNode() && Op2Scalar.getNode()) {
13921 SDValue newSelect = DAG.getNode(ISD::SELECT, DL,
13922 Op1Scalar.getValueType(),
13923 Cond, Op1Scalar, Op2Scalar);
13924 if (newSelect.getValueSizeInBits() == VT.getSizeInBits())
13925 return DAG.getBitcast(VT, newSelect);
13926 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, newSelect);
13927 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, ExtVec,
13928 DAG.getIntPtrConstant(0, DL));
13932 if (VT == MVT::v4i1 || VT == MVT::v2i1) {
13933 SDValue zeroConst = DAG.getIntPtrConstant(0, DL);
13934 Op1 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13935 DAG.getUNDEF(MVT::v8i1), Op1, zeroConst);
13936 Op2 = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, MVT::v8i1,
13937 DAG.getUNDEF(MVT::v8i1), Op2, zeroConst);
13938 SDValue newSelect = DAG.getNode(ISD::SELECT, DL, MVT::v8i1,
13940 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, newSelect, zeroConst);
13943 if (Cond.getOpcode() == ISD::SETCC) {
13944 SDValue NewCond = LowerSETCC(Cond, DAG);
13945 if (NewCond.getNode())
13949 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
13950 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
13951 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
13952 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
13953 if (Cond.getOpcode() == X86ISD::SETCC &&
13954 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
13955 isZero(Cond.getOperand(1).getOperand(1))) {
13956 SDValue Cmp = Cond.getOperand(1);
13958 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
13960 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
13961 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
13962 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
13964 SDValue CmpOp0 = Cmp.getOperand(0);
13965 // Apply further optimizations for special cases
13966 // (select (x != 0), -1, 0) -> neg & sbb
13967 // (select (x == 0), 0, -1) -> neg & sbb
13968 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
13969 if (YC->isNullValue() &&
13970 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
13971 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
13972 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
13973 DAG.getConstant(0, DL,
13974 CmpOp0.getValueType()),
13976 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13977 DAG.getConstant(X86::COND_B, DL, MVT::i8),
13978 SDValue(Neg.getNode(), 1));
13982 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
13983 CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));
13984 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
13986 SDValue Res = // Res = 0 or -1.
13987 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
13988 DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);
13990 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
13991 Res = DAG.getNOT(DL, Res, Res.getValueType());
13993 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
13994 if (!N2C || !N2C->isNullValue())
13995 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
14000 // Look past (and (setcc_carry (cmp ...)), 1).
14001 if (Cond.getOpcode() == ISD::AND &&
14002 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14003 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14004 if (C && C->getAPIntValue() == 1)
14005 Cond = Cond.getOperand(0);
14008 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14009 // setting operand in place of the X86ISD::SETCC.
14010 unsigned CondOpcode = Cond.getOpcode();
14011 if (CondOpcode == X86ISD::SETCC ||
14012 CondOpcode == X86ISD::SETCC_CARRY) {
14013 CC = Cond.getOperand(0);
14015 SDValue Cmp = Cond.getOperand(1);
14016 unsigned Opc = Cmp.getOpcode();
14017 MVT VT = Op.getSimpleValueType();
14019 bool IllegalFPCMov = false;
14020 if (VT.isFloatingPoint() && !VT.isVector() &&
14021 !isScalarFPTypeInSSEReg(VT)) // FPStack?
14022 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
14024 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
14025 Opc == X86ISD::BT) { // FIXME
14029 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14030 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14031 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14032 Cond.getOperand(0).getValueType() != MVT::i8)) {
14033 SDValue LHS = Cond.getOperand(0);
14034 SDValue RHS = Cond.getOperand(1);
14035 unsigned X86Opcode;
14038 switch (CondOpcode) {
14039 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14040 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14041 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14042 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14043 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14044 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14045 default: llvm_unreachable("unexpected overflowing operator");
14047 if (CondOpcode == ISD::UMULO)
14048 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14051 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14053 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
14055 if (CondOpcode == ISD::UMULO)
14056 Cond = X86Op.getValue(2);
14058 Cond = X86Op.getValue(1);
14060 CC = DAG.getConstant(X86Cond, DL, MVT::i8);
14065 // Look pass the truncate if the high bits are known zero.
14066 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14067 Cond = Cond.getOperand(0);
14069 // We know the result of AND is compared against zero. Try to match
14071 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14072 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
14073 if (NewSetCC.getNode()) {
14074 CC = NewSetCC.getOperand(0);
14075 Cond = NewSetCC.getOperand(1);
14082 CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);
14083 Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);
14086 // a < b ? -1 : 0 -> RES = ~setcc_carry
14087 // a < b ? 0 : -1 -> RES = setcc_carry
14088 // a >= b ? -1 : 0 -> RES = setcc_carry
14089 // a >= b ? 0 : -1 -> RES = ~setcc_carry
14090 if (Cond.getOpcode() == X86ISD::SUB) {
14091 Cond = ConvertCmpIfNecessary(Cond, DAG);
14092 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
14094 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
14095 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
14096 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
14097 DAG.getConstant(X86::COND_B, DL, MVT::i8),
14099 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
14100 return DAG.getNOT(DL, Res, Res.getValueType());
14105 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
14106 // widen the cmov and push the truncate through. This avoids introducing a new
14107 // branch during isel and doesn't add any extensions.
14108 if (Op.getValueType() == MVT::i8 &&
14109 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
14110 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
14111 if (T1.getValueType() == T2.getValueType() &&
14112 // Blacklist CopyFromReg to avoid partial register stalls.
14113 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
14114 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
14115 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
14116 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
14120 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
14121 // condition is true.
14122 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
14123 SDValue Ops[] = { Op2, Op1, CC, Cond };
14124 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops);
14127 static SDValue LowerSIGN_EXTEND_AVX512(SDValue Op,
14128 const X86Subtarget *Subtarget,
14129 SelectionDAG &DAG) {
14130 MVT VT = Op->getSimpleValueType(0);
14131 SDValue In = Op->getOperand(0);
14132 MVT InVT = In.getSimpleValueType();
14133 MVT VTElt = VT.getVectorElementType();
14134 MVT InVTElt = InVT.getVectorElementType();
14138 if ((InVTElt == MVT::i1) &&
14139 (((Subtarget->hasBWI() && Subtarget->hasVLX() &&
14140 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() <= 16)) ||
14142 ((Subtarget->hasBWI() && VT.is512BitVector() &&
14143 VTElt.getSizeInBits() <= 16)) ||
14145 ((Subtarget->hasDQI() && Subtarget->hasVLX() &&
14146 VT.getSizeInBits() <= 256 && VTElt.getSizeInBits() >= 32)) ||
14148 ((Subtarget->hasDQI() && VT.is512BitVector() &&
14149 VTElt.getSizeInBits() >= 32))))
14150 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14152 unsigned int NumElts = VT.getVectorNumElements();
14154 if (NumElts != 8 && NumElts != 16 && !Subtarget->hasBWI())
14157 if (VT.is512BitVector() && InVT.getVectorElementType() != MVT::i1) {
14158 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT)
14159 return DAG.getNode(In.getOpcode(), dl, VT, In.getOperand(0));
14160 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14163 assert (InVT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
14164 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
14166 DAG.getConstant(APInt::getAllOnesValue(ExtVT.getScalarSizeInBits()), dl,
14169 DAG.getConstant(APInt::getNullValue(ExtVT.getScalarSizeInBits()), dl, ExtVT);
14171 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
14172 if (VT.is512BitVector())
14174 return DAG.getNode(X86ISD::VTRUNC, dl, VT, V);
14177 static SDValue LowerSIGN_EXTEND_VECTOR_INREG(SDValue Op,
14178 const X86Subtarget *Subtarget,
14179 SelectionDAG &DAG) {
14180 SDValue In = Op->getOperand(0);
14181 MVT VT = Op->getSimpleValueType(0);
14182 MVT InVT = In.getSimpleValueType();
14183 assert(VT.getSizeInBits() == InVT.getSizeInBits());
14185 MVT InSVT = InVT.getScalarType();
14186 assert(VT.getScalarType().getScalarSizeInBits() > InSVT.getScalarSizeInBits());
14188 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16)
14190 if (InSVT != MVT::i32 && InSVT != MVT::i16 && InSVT != MVT::i8)
14195 // SSE41 targets can use the pmovsx* instructions directly.
14196 if (Subtarget->hasSSE41())
14197 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14199 // pre-SSE41 targets unpack lower lanes and then sign-extend using SRAI.
14203 // As SRAI is only available on i16/i32 types, we expand only up to i32
14204 // and handle i64 separately.
14205 while (CurrVT != VT && CurrVT.getScalarType() != MVT::i32) {
14206 Curr = DAG.getNode(X86ISD::UNPCKL, dl, CurrVT, DAG.getUNDEF(CurrVT), Curr);
14207 MVT CurrSVT = MVT::getIntegerVT(CurrVT.getScalarSizeInBits() * 2);
14208 CurrVT = MVT::getVectorVT(CurrSVT, CurrVT.getVectorNumElements() / 2);
14209 Curr = DAG.getBitcast(CurrVT, Curr);
14212 SDValue SignExt = Curr;
14213 if (CurrVT != InVT) {
14214 unsigned SignExtShift =
14215 CurrVT.getScalarSizeInBits() - InSVT.getScalarSizeInBits();
14216 SignExt = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14217 DAG.getConstant(SignExtShift, dl, MVT::i8));
14223 if (VT == MVT::v2i64 && CurrVT == MVT::v4i32) {
14224 SDValue Sign = DAG.getNode(X86ISD::VSRAI, dl, CurrVT, Curr,
14225 DAG.getConstant(31, dl, MVT::i8));
14226 SDValue Ext = DAG.getVectorShuffle(CurrVT, dl, SignExt, Sign, {0, 4, 1, 5});
14227 return DAG.getBitcast(VT, Ext);
14233 static SDValue LowerSIGN_EXTEND(SDValue Op, const X86Subtarget *Subtarget,
14234 SelectionDAG &DAG) {
14235 MVT VT = Op->getSimpleValueType(0);
14236 SDValue In = Op->getOperand(0);
14237 MVT InVT = In.getSimpleValueType();
14240 if (VT.is512BitVector() || InVT.getVectorElementType() == MVT::i1)
14241 return LowerSIGN_EXTEND_AVX512(Op, Subtarget, DAG);
14243 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
14244 (VT != MVT::v8i32 || InVT != MVT::v8i16) &&
14245 (VT != MVT::v16i16 || InVT != MVT::v16i8))
14248 if (Subtarget->hasInt256())
14249 return DAG.getNode(X86ISD::VSEXT, dl, VT, In);
14251 // Optimize vectors in AVX mode
14252 // Sign extend v8i16 to v8i32 and
14255 // Divide input vector into two parts
14256 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14257 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14258 // concat the vectors to original VT
14260 unsigned NumElems = InVT.getVectorNumElements();
14261 SDValue Undef = DAG.getUNDEF(InVT);
14263 SmallVector<int,8> ShufMask1(NumElems, -1);
14264 for (unsigned i = 0; i != NumElems/2; ++i)
14267 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
14269 SmallVector<int,8> ShufMask2(NumElems, -1);
14270 for (unsigned i = 0; i != NumElems/2; ++i)
14271 ShufMask2[i] = i + NumElems/2;
14273 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
14275 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
14276 VT.getVectorNumElements()/2);
14278 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo);
14279 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi);
14281 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
14284 // Lower vector extended loads using a shuffle. If SSSE3 is not available we
14285 // may emit an illegal shuffle but the expansion is still better than scalar
14286 // code. We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise
14287 // we'll emit a shuffle and a arithmetic shift.
14288 // FIXME: Is the expansion actually better than scalar code? It doesn't seem so.
14289 // TODO: It is possible to support ZExt by zeroing the undef values during
14290 // the shuffle phase or after the shuffle.
14291 static SDValue LowerExtendedLoad(SDValue Op, const X86Subtarget *Subtarget,
14292 SelectionDAG &DAG) {
14293 MVT RegVT = Op.getSimpleValueType();
14294 assert(RegVT.isVector() && "We only custom lower vector sext loads.");
14295 assert(RegVT.isInteger() &&
14296 "We only custom lower integer vector sext loads.");
14298 // Nothing useful we can do without SSE2 shuffles.
14299 assert(Subtarget->hasSSE2() && "We only custom lower sext loads with SSE2.");
14301 LoadSDNode *Ld = cast<LoadSDNode>(Op.getNode());
14303 EVT MemVT = Ld->getMemoryVT();
14304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14305 unsigned RegSz = RegVT.getSizeInBits();
14307 ISD::LoadExtType Ext = Ld->getExtensionType();
14309 assert((Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)
14310 && "Only anyext and sext are currently implemented.");
14311 assert(MemVT != RegVT && "Cannot extend to the same type");
14312 assert(MemVT.isVector() && "Must load a vector from memory");
14314 unsigned NumElems = RegVT.getVectorNumElements();
14315 unsigned MemSz = MemVT.getSizeInBits();
14316 assert(RegSz > MemSz && "Register size must be greater than the mem size");
14318 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256()) {
14319 // The only way in which we have a legal 256-bit vector result but not the
14320 // integer 256-bit operations needed to directly lower a sextload is if we
14321 // have AVX1 but not AVX2. In that case, we can always emit a sextload to
14322 // a 128-bit vector and a normal sign_extend to 256-bits that should get
14323 // correctly legalized. We do this late to allow the canonical form of
14324 // sextload to persist throughout the rest of the DAG combiner -- it wants
14325 // to fold together any extensions it can, and so will fuse a sign_extend
14326 // of an sextload into a sextload targeting a wider value.
14328 if (MemSz == 128) {
14329 // Just switch this to a normal load.
14330 assert(TLI.isTypeLegal(MemVT) && "If the memory type is a 128-bit type, "
14331 "it must be a legal 128-bit vector "
14333 Load = DAG.getLoad(MemVT, dl, Ld->getChain(), Ld->getBasePtr(),
14334 Ld->getPointerInfo(), Ld->isVolatile(), Ld->isNonTemporal(),
14335 Ld->isInvariant(), Ld->getAlignment());
14337 assert(MemSz < 128 &&
14338 "Can't extend a type wider than 128 bits to a 256 bit vector!");
14339 // Do an sext load to a 128-bit vector type. We want to use the same
14340 // number of elements, but elements half as wide. This will end up being
14341 // recursively lowered by this routine, but will succeed as we definitely
14342 // have all the necessary features if we're using AVX1.
14344 EVT::getIntegerVT(*DAG.getContext(), RegVT.getScalarSizeInBits() / 2);
14345 EVT HalfVecVT = EVT::getVectorVT(*DAG.getContext(), HalfEltVT, NumElems);
14347 DAG.getExtLoad(Ext, dl, HalfVecVT, Ld->getChain(), Ld->getBasePtr(),
14348 Ld->getPointerInfo(), MemVT, Ld->isVolatile(),
14349 Ld->isNonTemporal(), Ld->isInvariant(),
14350 Ld->getAlignment());
14353 // Replace chain users with the new chain.
14354 assert(Load->getNumValues() == 2 && "Loads must carry a chain!");
14355 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Load.getValue(1));
14357 // Finally, do a normal sign-extend to the desired register.
14358 return DAG.getSExtOrTrunc(Load, dl, RegVT);
14361 // All sizes must be a power of two.
14362 assert(isPowerOf2_32(RegSz * MemSz * NumElems) &&
14363 "Non-power-of-two elements are not custom lowered!");
14365 // Attempt to load the original value using scalar loads.
14366 // Find the largest scalar type that divides the total loaded size.
14367 MVT SclrLoadTy = MVT::i8;
14368 for (MVT Tp : MVT::integer_valuetypes()) {
14369 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
14374 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
14375 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
14377 SclrLoadTy = MVT::f64;
14379 // Calculate the number of scalar loads that we need to perform
14380 // in order to load our vector from memory.
14381 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
14383 assert((Ext != ISD::SEXTLOAD || NumLoads == 1) &&
14384 "Can only lower sext loads with a single scalar load!");
14386 unsigned loadRegZize = RegSz;
14387 if (Ext == ISD::SEXTLOAD && RegSz >= 256)
14390 // Represent our vector as a sequence of elements which are the
14391 // largest scalar that we can load.
14392 EVT LoadUnitVecVT = EVT::getVectorVT(
14393 *DAG.getContext(), SclrLoadTy, loadRegZize / SclrLoadTy.getSizeInBits());
14395 // Represent the data using the same element type that is stored in
14396 // memory. In practice, we ''widen'' MemVT.
14398 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
14399 loadRegZize / MemVT.getScalarType().getSizeInBits());
14401 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
14402 "Invalid vector type");
14404 // We can't shuffle using an illegal type.
14405 assert(TLI.isTypeLegal(WideVecVT) &&
14406 "We only lower types that form legal widened vector types");
14408 SmallVector<SDValue, 8> Chains;
14409 SDValue Ptr = Ld->getBasePtr();
14410 SDValue Increment =
14411 DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());
14412 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
14414 for (unsigned i = 0; i < NumLoads; ++i) {
14415 // Perform a single load.
14416 SDValue ScalarLoad =
14417 DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), Ptr, Ld->getPointerInfo(),
14418 Ld->isVolatile(), Ld->isNonTemporal(), Ld->isInvariant(),
14419 Ld->getAlignment());
14420 Chains.push_back(ScalarLoad.getValue(1));
14421 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
14422 // another round of DAGCombining.
14424 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
14426 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
14427 ScalarLoad, DAG.getIntPtrConstant(i, dl));
14429 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
14432 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
14434 // Bitcast the loaded value to a vector of the original element type, in
14435 // the size of the target vector type.
14436 SDValue SlicedVec = DAG.getBitcast(WideVecVT, Res);
14437 unsigned SizeRatio = RegSz / MemSz;
14439 if (Ext == ISD::SEXTLOAD) {
14440 // If we have SSE4.1, we can directly emit a VSEXT node.
14441 if (Subtarget->hasSSE41()) {
14442 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
14443 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14447 // Otherwise we'll shuffle the small elements in the high bits of the
14448 // larger type and perform an arithmetic shift. If the shift is not legal
14449 // it's better to scalarize.
14450 assert(TLI.isOperationLegalOrCustom(ISD::SRA, RegVT) &&
14451 "We can't implement a sext load without an arithmetic right shift!");
14453 // Redistribute the loaded elements into the different locations.
14454 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14455 for (unsigned i = 0; i != NumElems; ++i)
14456 ShuffleVec[i * SizeRatio + SizeRatio - 1] = i;
14458 SDValue Shuff = DAG.getVectorShuffle(
14459 WideVecVT, dl, SlicedVec, DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14461 Shuff = DAG.getBitcast(RegVT, Shuff);
14463 // Build the arithmetic shift.
14464 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
14465 MemVT.getVectorElementType().getSizeInBits();
14467 DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
14468 DAG.getConstant(Amt, dl, RegVT));
14470 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14474 // Redistribute the loaded elements into the different locations.
14475 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
14476 for (unsigned i = 0; i != NumElems; ++i)
14477 ShuffleVec[i * SizeRatio] = i;
14479 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
14480 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
14482 // Bitcast to the requested type.
14483 Shuff = DAG.getBitcast(RegVT, Shuff);
14484 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);
14488 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
14489 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
14490 // from the AND / OR.
14491 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
14492 Opc = Op.getOpcode();
14493 if (Opc != ISD::OR && Opc != ISD::AND)
14495 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14496 Op.getOperand(0).hasOneUse() &&
14497 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
14498 Op.getOperand(1).hasOneUse());
14501 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
14502 // 1 and that the SETCC node has a single use.
14503 static bool isXor1OfSetCC(SDValue Op) {
14504 if (Op.getOpcode() != ISD::XOR)
14506 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
14507 if (N1C && N1C->getAPIntValue() == 1) {
14508 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
14509 Op.getOperand(0).hasOneUse();
14514 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
14515 bool addTest = true;
14516 SDValue Chain = Op.getOperand(0);
14517 SDValue Cond = Op.getOperand(1);
14518 SDValue Dest = Op.getOperand(2);
14521 bool Inverted = false;
14523 if (Cond.getOpcode() == ISD::SETCC) {
14524 // Check for setcc([su]{add,sub,mul}o == 0).
14525 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
14526 isa<ConstantSDNode>(Cond.getOperand(1)) &&
14527 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
14528 Cond.getOperand(0).getResNo() == 1 &&
14529 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
14530 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
14531 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
14532 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
14533 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
14534 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
14536 Cond = Cond.getOperand(0);
14538 SDValue NewCond = LowerSETCC(Cond, DAG);
14539 if (NewCond.getNode())
14544 // FIXME: LowerXALUO doesn't handle these!!
14545 else if (Cond.getOpcode() == X86ISD::ADD ||
14546 Cond.getOpcode() == X86ISD::SUB ||
14547 Cond.getOpcode() == X86ISD::SMUL ||
14548 Cond.getOpcode() == X86ISD::UMUL)
14549 Cond = LowerXALUO(Cond, DAG);
14552 // Look pass (and (setcc_carry (cmp ...)), 1).
14553 if (Cond.getOpcode() == ISD::AND &&
14554 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
14555 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
14556 if (C && C->getAPIntValue() == 1)
14557 Cond = Cond.getOperand(0);
14560 // If condition flag is set by a X86ISD::CMP, then use it as the condition
14561 // setting operand in place of the X86ISD::SETCC.
14562 unsigned CondOpcode = Cond.getOpcode();
14563 if (CondOpcode == X86ISD::SETCC ||
14564 CondOpcode == X86ISD::SETCC_CARRY) {
14565 CC = Cond.getOperand(0);
14567 SDValue Cmp = Cond.getOperand(1);
14568 unsigned Opc = Cmp.getOpcode();
14569 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
14570 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
14574 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
14578 // These can only come from an arithmetic instruction with overflow,
14579 // e.g. SADDO, UADDO.
14580 Cond = Cond.getNode()->getOperand(1);
14586 CondOpcode = Cond.getOpcode();
14587 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
14588 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
14589 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
14590 Cond.getOperand(0).getValueType() != MVT::i8)) {
14591 SDValue LHS = Cond.getOperand(0);
14592 SDValue RHS = Cond.getOperand(1);
14593 unsigned X86Opcode;
14596 // Keep this in sync with LowerXALUO, otherwise we might create redundant
14597 // instructions that can't be removed afterwards (i.e. X86ISD::ADD and
14599 switch (CondOpcode) {
14600 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
14602 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14604 X86Opcode = X86ISD::INC; X86Cond = X86::COND_O;
14607 X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
14608 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
14610 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
14612 X86Opcode = X86ISD::DEC; X86Cond = X86::COND_O;
14615 X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
14616 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
14617 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
14618 default: llvm_unreachable("unexpected overflowing operator");
14621 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
14622 if (CondOpcode == ISD::UMULO)
14623 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
14626 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
14628 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
14630 if (CondOpcode == ISD::UMULO)
14631 Cond = X86Op.getValue(2);
14633 Cond = X86Op.getValue(1);
14635 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14639 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
14640 SDValue Cmp = Cond.getOperand(0).getOperand(1);
14641 if (CondOpc == ISD::OR) {
14642 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
14643 // two branches instead of an explicit OR instruction with a
14645 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14646 isX86LogicalCmp(Cmp)) {
14647 CC = Cond.getOperand(0).getOperand(0);
14648 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14649 Chain, Dest, CC, Cmp);
14650 CC = Cond.getOperand(1).getOperand(0);
14654 } else { // ISD::AND
14655 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
14656 // two branches instead of an explicit AND instruction with a
14657 // separate test. However, we only do this if this block doesn't
14658 // have a fall-through edge, because this requires an explicit
14659 // jmp when the condition is false.
14660 if (Cmp == Cond.getOperand(1).getOperand(1) &&
14661 isX86LogicalCmp(Cmp) &&
14662 Op.getNode()->hasOneUse()) {
14663 X86::CondCode CCode =
14664 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14665 CCode = X86::GetOppositeBranchCondition(CCode);
14666 CC = DAG.getConstant(CCode, dl, MVT::i8);
14667 SDNode *User = *Op.getNode()->use_begin();
14668 // Look for an unconditional branch following this conditional branch.
14669 // We need this because we need to reverse the successors in order
14670 // to implement FCMP_OEQ.
14671 if (User->getOpcode() == ISD::BR) {
14672 SDValue FalseBB = User->getOperand(1);
14674 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14675 assert(NewBR == User);
14679 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14680 Chain, Dest, CC, Cmp);
14681 X86::CondCode CCode =
14682 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
14683 CCode = X86::GetOppositeBranchCondition(CCode);
14684 CC = DAG.getConstant(CCode, dl, MVT::i8);
14690 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
14691 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
14692 // It should be transformed during dag combiner except when the condition
14693 // is set by a arithmetics with overflow node.
14694 X86::CondCode CCode =
14695 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
14696 CCode = X86::GetOppositeBranchCondition(CCode);
14697 CC = DAG.getConstant(CCode, dl, MVT::i8);
14698 Cond = Cond.getOperand(0).getOperand(1);
14700 } else if (Cond.getOpcode() == ISD::SETCC &&
14701 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
14702 // For FCMP_OEQ, we can emit
14703 // two branches instead of an explicit AND instruction with a
14704 // separate test. However, we only do this if this block doesn't
14705 // have a fall-through edge, because this requires an explicit
14706 // jmp when the condition is false.
14707 if (Op.getNode()->hasOneUse()) {
14708 SDNode *User = *Op.getNode()->use_begin();
14709 // Look for an unconditional branch following this conditional branch.
14710 // We need this because we need to reverse the successors in order
14711 // to implement FCMP_OEQ.
14712 if (User->getOpcode() == ISD::BR) {
14713 SDValue FalseBB = User->getOperand(1);
14715 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14716 assert(NewBR == User);
14720 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14721 Cond.getOperand(0), Cond.getOperand(1));
14722 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14723 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14724 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14725 Chain, Dest, CC, Cmp);
14726 CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);
14731 } else if (Cond.getOpcode() == ISD::SETCC &&
14732 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
14733 // For FCMP_UNE, we can emit
14734 // two branches instead of an explicit AND instruction with a
14735 // separate test. However, we only do this if this block doesn't
14736 // have a fall-through edge, because this requires an explicit
14737 // jmp when the condition is false.
14738 if (Op.getNode()->hasOneUse()) {
14739 SDNode *User = *Op.getNode()->use_begin();
14740 // Look for an unconditional branch following this conditional branch.
14741 // We need this because we need to reverse the successors in order
14742 // to implement FCMP_UNE.
14743 if (User->getOpcode() == ISD::BR) {
14744 SDValue FalseBB = User->getOperand(1);
14746 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
14747 assert(NewBR == User);
14750 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
14751 Cond.getOperand(0), Cond.getOperand(1));
14752 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
14753 CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);
14754 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14755 Chain, Dest, CC, Cmp);
14756 CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);
14766 // Look pass the truncate if the high bits are known zero.
14767 if (isTruncWithZeroHighBitsInput(Cond, DAG))
14768 Cond = Cond.getOperand(0);
14770 // We know the result of AND is compared against zero. Try to match
14772 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
14773 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
14774 if (NewSetCC.getNode()) {
14775 CC = NewSetCC.getOperand(0);
14776 Cond = NewSetCC.getOperand(1);
14783 X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;
14784 CC = DAG.getConstant(X86Cond, dl, MVT::i8);
14785 Cond = EmitTest(Cond, X86Cond, dl, DAG);
14787 Cond = ConvertCmpIfNecessary(Cond, DAG);
14788 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
14789 Chain, Dest, CC, Cond);
14792 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
14793 // Calls to _alloca are needed to probe the stack when allocating more than 4k
14794 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
14795 // that the guard pages used by the OS virtual memory manager are allocated in
14796 // correct sequence.
14798 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
14799 SelectionDAG &DAG) const {
14800 MachineFunction &MF = DAG.getMachineFunction();
14801 bool SplitStack = MF.shouldSplitStack();
14802 bool Lower = (Subtarget->isOSWindows() && !Subtarget->isTargetMachO()) ||
14807 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
14808 SDNode* Node = Op.getNode();
14810 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
14811 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
14812 " not tell us which reg is the stack pointer!");
14813 EVT VT = Node->getValueType(0);
14814 SDValue Tmp1 = SDValue(Node, 0);
14815 SDValue Tmp2 = SDValue(Node, 1);
14816 SDValue Tmp3 = Node->getOperand(2);
14817 SDValue Chain = Tmp1.getOperand(0);
14819 // Chain the dynamic stack allocation so that it doesn't modify the stack
14820 // pointer when other instructions are using the stack.
14821 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),
14824 SDValue Size = Tmp2.getOperand(1);
14825 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
14826 Chain = SP.getValue(1);
14827 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
14828 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
14829 unsigned StackAlign = TFI.getStackAlignment();
14830 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
14831 if (Align > StackAlign)
14832 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
14833 DAG.getConstant(-(uint64_t)Align, dl, VT));
14834 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
14836 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
14837 DAG.getIntPtrConstant(0, dl, true), SDValue(),
14840 SDValue Ops[2] = { Tmp1, Tmp2 };
14841 return DAG.getMergeValues(Ops, dl);
14845 SDValue Chain = Op.getOperand(0);
14846 SDValue Size = Op.getOperand(1);
14847 unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
14848 EVT VT = Op.getNode()->getValueType(0);
14850 bool Is64Bit = Subtarget->is64Bit();
14851 EVT SPTy = getPointerTy();
14854 MachineRegisterInfo &MRI = MF.getRegInfo();
14857 // The 64 bit implementation of segmented stacks needs to clobber both r10
14858 // r11. This makes it impossible to use it along with nested parameters.
14859 const Function *F = MF.getFunction();
14861 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
14863 if (I->hasNestAttr())
14864 report_fatal_error("Cannot use segmented stacks with functions that "
14865 "have nested arguments.");
14868 const TargetRegisterClass *AddrRegClass =
14869 getRegClassFor(getPointerTy());
14870 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
14871 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
14872 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
14873 DAG.getRegister(Vreg, SPTy));
14874 SDValue Ops1[2] = { Value, Chain };
14875 return DAG.getMergeValues(Ops1, dl);
14878 const unsigned Reg = (Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX);
14880 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
14881 Flag = Chain.getValue(1);
14882 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
14884 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
14886 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
14887 unsigned SPReg = RegInfo->getStackRegister();
14888 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, SPTy);
14889 Chain = SP.getValue(1);
14892 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
14893 DAG.getConstant(-(uint64_t)Align, dl, VT));
14894 Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);
14897 SDValue Ops1[2] = { SP, Chain };
14898 return DAG.getMergeValues(Ops1, dl);
14902 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
14903 MachineFunction &MF = DAG.getMachineFunction();
14904 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
14906 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14909 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
14910 // vastart just stores the address of the VarArgsFrameIndex slot into the
14911 // memory location argument.
14912 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14914 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
14915 MachinePointerInfo(SV), false, false, 0);
14919 // gp_offset (0 - 6 * 8)
14920 // fp_offset (48 - 48 + 8 * 16)
14921 // overflow_arg_area (point to parameters coming in memory).
14923 SmallVector<SDValue, 8> MemOps;
14924 SDValue FIN = Op.getOperand(1);
14926 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
14927 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
14929 FIN, MachinePointerInfo(SV), false, false, 0);
14930 MemOps.push_back(Store);
14933 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14934 FIN, DAG.getIntPtrConstant(4, DL));
14935 Store = DAG.getStore(Op.getOperand(0), DL,
14936 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,
14938 FIN, MachinePointerInfo(SV, 4), false, false, 0);
14939 MemOps.push_back(Store);
14941 // Store ptr to overflow_arg_area
14942 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14943 FIN, DAG.getIntPtrConstant(4, DL));
14944 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
14946 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
14947 MachinePointerInfo(SV, 8),
14949 MemOps.push_back(Store);
14951 // Store ptr to reg_save_area.
14952 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
14953 FIN, DAG.getIntPtrConstant(8, DL));
14954 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
14956 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
14957 MachinePointerInfo(SV, 16), false, false, 0);
14958 MemOps.push_back(Store);
14959 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
14962 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
14963 assert(Subtarget->is64Bit() &&
14964 "LowerVAARG only handles 64-bit va_arg!");
14965 assert((Subtarget->isTargetLinux() ||
14966 Subtarget->isTargetDarwin()) &&
14967 "Unhandled target in LowerVAARG");
14968 assert(Op.getNode()->getNumOperands() == 4);
14969 SDValue Chain = Op.getOperand(0);
14970 SDValue SrcPtr = Op.getOperand(1);
14971 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
14972 unsigned Align = Op.getConstantOperandVal(3);
14975 EVT ArgVT = Op.getNode()->getValueType(0);
14976 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
14977 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
14980 // Decide which area this value should be read from.
14981 // TODO: Implement the AMD64 ABI in its entirety. This simple
14982 // selection mechanism works only for the basic types.
14983 if (ArgVT == MVT::f80) {
14984 llvm_unreachable("va_arg for f80 not yet implemented");
14985 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
14986 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
14987 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
14988 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
14990 llvm_unreachable("Unhandled argument type in LowerVAARG");
14993 if (ArgMode == 2) {
14994 // Sanity Check: Make sure using fp_offset makes sense.
14995 assert(!Subtarget->useSoftFloat() &&
14996 !(DAG.getMachineFunction().getFunction()->hasFnAttribute(
14997 Attribute::NoImplicitFloat)) &&
14998 Subtarget->hasSSE1());
15001 // Insert VAARG_64 node into the DAG
15002 // VAARG_64 returns two values: Variable Argument Address, Chain
15003 SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),
15004 DAG.getConstant(ArgMode, dl, MVT::i8),
15005 DAG.getConstant(Align, dl, MVT::i32)};
15006 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
15007 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
15008 VTs, InstOps, MVT::i64,
15009 MachinePointerInfo(SV),
15011 /*Volatile=*/false,
15013 /*WriteMem=*/true);
15014 Chain = VAARG.getValue(1);
15016 // Load the next argument and return it
15017 return DAG.getLoad(ArgVT, dl,
15020 MachinePointerInfo(),
15021 false, false, false, 0);
15024 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
15025 SelectionDAG &DAG) {
15026 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
15027 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
15028 SDValue Chain = Op.getOperand(0);
15029 SDValue DstPtr = Op.getOperand(1);
15030 SDValue SrcPtr = Op.getOperand(2);
15031 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
15032 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
15035 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
15036 DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,
15038 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
15041 // getTargetVShiftByConstNode - Handle vector element shifts where the shift
15042 // amount is a constant. Takes immediate version of shift as input.
15043 static SDValue getTargetVShiftByConstNode(unsigned Opc, SDLoc dl, MVT VT,
15044 SDValue SrcOp, uint64_t ShiftAmt,
15045 SelectionDAG &DAG) {
15046 MVT ElementType = VT.getVectorElementType();
15048 // Fold this packed shift into its first operand if ShiftAmt is 0.
15052 // Check for ShiftAmt >= element width
15053 if (ShiftAmt >= ElementType.getSizeInBits()) {
15054 if (Opc == X86ISD::VSRAI)
15055 ShiftAmt = ElementType.getSizeInBits() - 1;
15057 return DAG.getConstant(0, dl, VT);
15060 assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)
15061 && "Unknown target vector shift-by-constant node");
15063 // Fold this packed vector shift into a build vector if SrcOp is a
15064 // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
15065 if (VT == SrcOp.getSimpleValueType() &&
15066 ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
15067 SmallVector<SDValue, 8> Elts;
15068 unsigned NumElts = SrcOp->getNumOperands();
15069 ConstantSDNode *ND;
15072 default: llvm_unreachable(nullptr);
15073 case X86ISD::VSHLI:
15074 for (unsigned i=0; i!=NumElts; ++i) {
15075 SDValue CurrentOp = SrcOp->getOperand(i);
15076 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15077 Elts.push_back(CurrentOp);
15080 ND = cast<ConstantSDNode>(CurrentOp);
15081 const APInt &C = ND->getAPIntValue();
15082 Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
15085 case X86ISD::VSRLI:
15086 for (unsigned i=0; i!=NumElts; ++i) {
15087 SDValue CurrentOp = SrcOp->getOperand(i);
15088 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15089 Elts.push_back(CurrentOp);
15092 ND = cast<ConstantSDNode>(CurrentOp);
15093 const APInt &C = ND->getAPIntValue();
15094 Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
15097 case X86ISD::VSRAI:
15098 for (unsigned i=0; i!=NumElts; ++i) {
15099 SDValue CurrentOp = SrcOp->getOperand(i);
15100 if (CurrentOp->getOpcode() == ISD::UNDEF) {
15101 Elts.push_back(CurrentOp);
15104 ND = cast<ConstantSDNode>(CurrentOp);
15105 const APInt &C = ND->getAPIntValue();
15106 Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
15111 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
15114 return DAG.getNode(Opc, dl, VT, SrcOp,
15115 DAG.getConstant(ShiftAmt, dl, MVT::i8));
15118 // getTargetVShiftNode - Handle vector element shifts where the shift amount
15119 // may or may not be a constant. Takes immediate version of shift as input.
15120 static SDValue getTargetVShiftNode(unsigned Opc, SDLoc dl, MVT VT,
15121 SDValue SrcOp, SDValue ShAmt,
15122 SelectionDAG &DAG) {
15123 MVT SVT = ShAmt.getSimpleValueType();
15124 assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
15126 // Catch shift-by-constant.
15127 if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
15128 return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
15129 CShAmt->getZExtValue(), DAG);
15131 // Change opcode to non-immediate version
15133 default: llvm_unreachable("Unknown target vector shift node");
15134 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
15135 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
15136 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
15139 const X86Subtarget &Subtarget =
15140 static_cast<const X86Subtarget &>(DAG.getSubtarget());
15141 if (Subtarget.hasSSE41() && ShAmt.getOpcode() == ISD::ZERO_EXTEND &&
15142 ShAmt.getOperand(0).getSimpleValueType() == MVT::i16) {
15143 // Let the shuffle legalizer expand this shift amount node.
15144 SDValue Op0 = ShAmt.getOperand(0);
15145 Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(Op0), MVT::v8i16, Op0);
15146 ShAmt = getShuffleVectorZeroOrUndef(Op0, 0, true, &Subtarget, DAG);
15148 // Need to build a vector containing shift amount.
15149 // SSE/AVX packed shifts only use the lower 64-bit of the shift count.
15150 SmallVector<SDValue, 4> ShOps;
15151 ShOps.push_back(ShAmt);
15152 if (SVT == MVT::i32) {
15153 ShOps.push_back(DAG.getConstant(0, dl, SVT));
15154 ShOps.push_back(DAG.getUNDEF(SVT));
15156 ShOps.push_back(DAG.getUNDEF(SVT));
15158 MVT BVT = SVT == MVT::i32 ? MVT::v4i32 : MVT::v2i64;
15159 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps);
15162 // The return type has to be a 128-bit type with the same element
15163 // type as the input type.
15164 MVT EltVT = VT.getVectorElementType();
15165 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
15167 ShAmt = DAG.getBitcast(ShVT, ShAmt);
15168 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
15171 /// \brief Return (and \p Op, \p Mask) for compare instructions or
15172 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
15173 /// necessary casting for \p Mask when lowering masking intrinsics.
15174 static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,
15175 SDValue PreservedSrc,
15176 const X86Subtarget *Subtarget,
15177 SelectionDAG &DAG) {
15178 EVT VT = Op.getValueType();
15179 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),
15180 MVT::i1, VT.getVectorNumElements());
15181 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15182 Mask.getValueType().getSizeInBits());
15185 assert(MaskVT.isSimple() && "invalid mask type");
15187 if (isAllOnes(Mask))
15190 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15191 // are extracted by EXTRACT_SUBVECTOR.
15192 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15193 DAG.getBitcast(BitcastVT, Mask),
15194 DAG.getIntPtrConstant(0, dl));
15196 switch (Op.getOpcode()) {
15198 case X86ISD::PCMPEQM:
15199 case X86ISD::PCMPGTM:
15201 case X86ISD::CMPMU:
15202 return DAG.getNode(ISD::AND, dl, VT, Op, VMask);
15204 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15205 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15206 return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);
15209 /// \brief Creates an SDNode for a predicated scalar operation.
15210 /// \returns (X86vselect \p Mask, \p Op, \p PreservedSrc).
15211 /// The mask is comming as MVT::i8 and it should be truncated
15212 /// to MVT::i1 while lowering masking intrinsics.
15213 /// The main difference between ScalarMaskingNode and VectorMaskingNode is using
15214 /// "X86select" instead of "vselect". We just can't create the "vselect" node for
15215 /// a scalar instruction.
15216 static SDValue getScalarMaskingNode(SDValue Op, SDValue Mask,
15217 SDValue PreservedSrc,
15218 const X86Subtarget *Subtarget,
15219 SelectionDAG &DAG) {
15220 if (isAllOnes(Mask))
15223 EVT VT = Op.getValueType();
15225 // The mask should be of type MVT::i1
15226 SDValue IMask = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Mask);
15228 if (PreservedSrc.getOpcode() == ISD::UNDEF)
15229 PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);
15230 return DAG.getNode(X86ISD::SELECT, dl, VT, IMask, Op, PreservedSrc);
15233 /// When the 32-bit MSVC runtime transfers control to us, either to an outlined
15234 /// function or when returning to a parent frame after catching an exception, we
15235 /// recover the parent frame pointer by doing arithmetic on the incoming EBP.
15236 /// Here's the math:
15237 /// RegNodeBase = EntryEBP - RegNodeSize
15238 /// ParentFP = RegNodeBase - RegNodeFrameOffset
15239 /// Subtracting RegNodeSize takes us to the offset of the registration node, and
15240 /// subtracting the offset (negative on x86) takes us back to the parent FP.
15241 static SDValue recoverFramePointer(SelectionDAG &DAG, const Function *Fn,
15242 SDValue EntryEBP) {
15243 MachineFunction &MF = DAG.getMachineFunction();
15246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15247 MVT PtrVT = TLI.getPointerTy();
15249 // It's possible that the parent function no longer has a personality function
15250 // if the exceptional code was optimized away, in which case we just return
15251 // the incoming EBP.
15252 if (!Fn->hasPersonalityFn())
15255 // The RegNodeSize is 6 32-bit words for SEH and 4 for C++ EH. See
15256 // WinEHStatePass for the full struct definition.
15258 switch (classifyEHPersonality(Fn->getPersonalityFn())) {
15260 report_fatal_error("can only recover FP for MSVC EH personality functions");
15261 case EHPersonality::MSVC_X86SEH: RegNodeSize = 24; break;
15262 case EHPersonality::MSVC_CXX: RegNodeSize = 16; break;
15265 // Get an MCSymbol that will ultimately resolve to the frame offset of the EH
15267 MCSymbol *OffsetSym =
15268 MF.getMMI().getContext().getOrCreateParentFrameOffsetSymbol(
15269 GlobalValue::getRealLinkageName(Fn->getName()));
15270 SDValue OffsetSymVal = DAG.getMCSymbol(OffsetSym, PtrVT);
15271 SDValue RegNodeFrameOffset =
15272 DAG.getNode(ISD::LOCAL_RECOVER, dl, PtrVT, OffsetSymVal);
15274 // RegNodeBase = EntryEBP - RegNodeSize
15275 // ParentFP = RegNodeBase - RegNodeFrameOffset
15276 SDValue RegNodeBase = DAG.getNode(ISD::SUB, dl, PtrVT, EntryEBP,
15277 DAG.getConstant(RegNodeSize, dl, PtrVT));
15278 return DAG.getNode(ISD::SUB, dl, PtrVT, RegNodeBase, RegNodeFrameOffset);
15281 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15282 SelectionDAG &DAG) {
15284 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
15285 EVT VT = Op.getValueType();
15286 const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
15288 switch(IntrData->Type) {
15289 case INTR_TYPE_1OP:
15290 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
15291 case INTR_TYPE_2OP:
15292 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15294 case INTR_TYPE_3OP:
15295 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15296 Op.getOperand(2), Op.getOperand(3));
15297 case INTR_TYPE_4OP:
15298 return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
15299 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4));
15300 case INTR_TYPE_1OP_MASK_RM: {
15301 SDValue Src = Op.getOperand(1);
15302 SDValue PassThru = Op.getOperand(2);
15303 SDValue Mask = Op.getOperand(3);
15304 SDValue RoundingMode;
15305 if (Op.getNumOperands() == 4)
15306 RoundingMode = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15308 RoundingMode = Op.getOperand(4);
15309 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15310 if (IntrWithRoundingModeOpcode != 0) {
15311 unsigned Round = cast<ConstantSDNode>(RoundingMode)->getZExtValue();
15312 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION)
15313 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15314 dl, Op.getValueType(), Src, RoundingMode),
15315 Mask, PassThru, Subtarget, DAG);
15317 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src,
15319 Mask, PassThru, Subtarget, DAG);
15321 case INTR_TYPE_1OP_MASK: {
15322 SDValue Src = Op.getOperand(1);
15323 SDValue Passthru = Op.getOperand(2);
15324 SDValue Mask = Op.getOperand(3);
15325 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src),
15326 Mask, Passthru, Subtarget, DAG);
15328 case INTR_TYPE_SCALAR_MASK_RM: {
15329 SDValue Src1 = Op.getOperand(1);
15330 SDValue Src2 = Op.getOperand(2);
15331 SDValue Src0 = Op.getOperand(3);
15332 SDValue Mask = Op.getOperand(4);
15333 // There are 2 kinds of intrinsics in this group:
15334 // (1) With supress-all-exceptions (sae) or rounding mode- 6 operands
15335 // (2) With rounding mode and sae - 7 operands.
15336 if (Op.getNumOperands() == 6) {
15337 SDValue Sae = Op.getOperand(5);
15338 unsigned Opc = IntrData->Opc1 ? IntrData->Opc1 : IntrData->Opc0;
15339 return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2,
15341 Mask, Src0, Subtarget, DAG);
15343 assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");
15344 SDValue RoundingMode = Op.getOperand(5);
15345 SDValue Sae = Op.getOperand(6);
15346 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
15347 RoundingMode, Sae),
15348 Mask, Src0, Subtarget, DAG);
15350 case INTR_TYPE_2OP_MASK: {
15351 SDValue Src1 = Op.getOperand(1);
15352 SDValue Src2 = Op.getOperand(2);
15353 SDValue PassThru = Op.getOperand(3);
15354 SDValue Mask = Op.getOperand(4);
15355 // We specify 2 possible opcodes for intrinsics with rounding modes.
15356 // First, we check if the intrinsic may have non-default rounding mode,
15357 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15358 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15359 if (IntrWithRoundingModeOpcode != 0) {
15360 SDValue Rnd = Op.getOperand(5);
15361 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15362 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15363 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15364 dl, Op.getValueType(),
15366 Mask, PassThru, Subtarget, DAG);
15369 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15371 Mask, PassThru, Subtarget, DAG);
15373 case INTR_TYPE_2OP_MASK_RM: {
15374 SDValue Src1 = Op.getOperand(1);
15375 SDValue Src2 = Op.getOperand(2);
15376 SDValue PassThru = Op.getOperand(3);
15377 SDValue Mask = Op.getOperand(4);
15378 // We specify 2 possible modes for intrinsics, with/without rounding modes.
15379 // First, we check if the intrinsic have rounding mode (6 operands),
15380 // if not, we set rounding mode to "current".
15382 if (Op.getNumOperands() == 6)
15383 Rnd = Op.getOperand(5);
15385 Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
15386 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15388 Mask, PassThru, Subtarget, DAG);
15390 case INTR_TYPE_3OP_MASK: {
15391 SDValue Src1 = Op.getOperand(1);
15392 SDValue Src2 = Op.getOperand(2);
15393 SDValue Src3 = Op.getOperand(3);
15394 SDValue PassThru = Op.getOperand(4);
15395 SDValue Mask = Op.getOperand(5);
15396 // We specify 2 possible opcodes for intrinsics with rounding modes.
15397 // First, we check if the intrinsic may have non-default rounding mode,
15398 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15399 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15400 if (IntrWithRoundingModeOpcode != 0) {
15401 SDValue Rnd = Op.getOperand(6);
15402 unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
15403 if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
15404 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15405 dl, Op.getValueType(),
15406 Src1, Src2, Src3, Rnd),
15407 Mask, PassThru, Subtarget, DAG);
15410 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15412 Mask, PassThru, Subtarget, DAG);
15414 case VPERM_3OP_MASKZ:
15415 case VPERM_3OP_MASK:
15418 case FMA_OP_MASK: {
15419 SDValue Src1 = Op.getOperand(1);
15420 SDValue Src2 = Op.getOperand(2);
15421 SDValue Src3 = Op.getOperand(3);
15422 SDValue Mask = Op.getOperand(4);
15423 EVT VT = Op.getValueType();
15424 SDValue PassThru = SDValue();
15426 // set PassThru element
15427 if (IntrData->Type == VPERM_3OP_MASKZ || IntrData->Type == FMA_OP_MASKZ)
15428 PassThru = getZeroVector(VT, Subtarget, DAG, dl);
15429 else if (IntrData->Type == FMA_OP_MASK3)
15434 // We specify 2 possible opcodes for intrinsics with rounding modes.
15435 // First, we check if the intrinsic may have non-default rounding mode,
15436 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15437 unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
15438 if (IntrWithRoundingModeOpcode != 0) {
15439 SDValue Rnd = Op.getOperand(5);
15440 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15441 X86::STATIC_ROUNDING::CUR_DIRECTION)
15442 return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
15443 dl, Op.getValueType(),
15444 Src1, Src2, Src3, Rnd),
15445 Mask, PassThru, Subtarget, DAG);
15447 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0,
15448 dl, Op.getValueType(),
15450 Mask, PassThru, Subtarget, DAG);
15453 case CMP_MASK_CC: {
15454 // Comparison intrinsics with masks.
15455 // Example of transformation:
15456 // (i8 (int_x86_avx512_mask_pcmpeq_q_128
15457 // (v2i64 %a), (v2i64 %b), (i8 %mask))) ->
15459 // (v8i1 (insert_subvector undef,
15460 // (v2i1 (and (PCMPEQM %a, %b),
15461 // (extract_subvector
15462 // (v8i1 (bitcast %mask)), 0))), 0))))
15463 EVT VT = Op.getOperand(1).getValueType();
15464 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15465 VT.getVectorNumElements());
15466 SDValue Mask = Op.getOperand((IntrData->Type == CMP_MASK_CC) ? 4 : 3);
15467 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15468 Mask.getValueType().getSizeInBits());
15470 if (IntrData->Type == CMP_MASK_CC) {
15471 SDValue CC = Op.getOperand(3);
15472 CC = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, CC);
15473 // We specify 2 possible opcodes for intrinsics with rounding modes.
15474 // First, we check if the intrinsic may have non-default rounding mode,
15475 // (IntrData->Opc1 != 0), then we check the rounding mode operand.
15476 if (IntrData->Opc1 != 0) {
15477 SDValue Rnd = Op.getOperand(5);
15478 if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
15479 X86::STATIC_ROUNDING::CUR_DIRECTION)
15480 Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
15481 Op.getOperand(2), CC, Rnd);
15483 //default rounding mode
15485 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15486 Op.getOperand(2), CC);
15489 assert(IntrData->Type == CMP_MASK && "Unexpected intrinsic type!");
15490 Cmp = DAG.getNode(IntrData->Opc0, dl, MaskVT, Op.getOperand(1),
15493 SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,
15494 DAG.getTargetConstant(0, dl,
15497 SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,
15498 DAG.getUNDEF(BitcastVT), CmpMask,
15499 DAG.getIntPtrConstant(0, dl));
15500 return DAG.getBitcast(Op.getValueType(), Res);
15502 case COMI: { // Comparison intrinsics
15503 ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
15504 SDValue LHS = Op.getOperand(1);
15505 SDValue RHS = Op.getOperand(2);
15506 unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);
15507 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
15508 SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
15509 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15510 DAG.getConstant(X86CC, dl, MVT::i8), Cond);
15511 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15514 return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
15515 Op.getOperand(1), Op.getOperand(2), DAG);
15517 return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl,
15518 Op.getSimpleValueType(),
15520 Op.getOperand(2), DAG),
15521 Op.getOperand(4), Op.getOperand(3), Subtarget,
15523 case COMPRESS_EXPAND_IN_REG: {
15524 SDValue Mask = Op.getOperand(3);
15525 SDValue DataToCompress = Op.getOperand(1);
15526 SDValue PassThru = Op.getOperand(2);
15527 if (isAllOnes(Mask)) // return data as is
15528 return Op.getOperand(1);
15530 return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
15532 Mask, PassThru, Subtarget, DAG);
15535 SDValue Mask = Op.getOperand(3);
15536 EVT VT = Op.getValueType();
15537 EVT MaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15538 VT.getVectorNumElements());
15539 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15540 Mask.getValueType().getSizeInBits());
15542 SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15543 DAG.getBitcast(BitcastVT, Mask),
15544 DAG.getIntPtrConstant(0, dl));
15545 return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),
15554 default: return SDValue(); // Don't custom lower most intrinsics.
15556 case Intrinsic::x86_avx2_permd:
15557 case Intrinsic::x86_avx2_permps:
15558 // Operands intentionally swapped. Mask is last operand to intrinsic,
15559 // but second operand for node/instruction.
15560 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
15561 Op.getOperand(2), Op.getOperand(1));
15563 // ptest and testp intrinsics. The intrinsic these come from are designed to
15564 // return an integer value, not just an instruction so lower it to the ptest
15565 // or testp pattern and a setcc for the result.
15566 case Intrinsic::x86_sse41_ptestz:
15567 case Intrinsic::x86_sse41_ptestc:
15568 case Intrinsic::x86_sse41_ptestnzc:
15569 case Intrinsic::x86_avx_ptestz_256:
15570 case Intrinsic::x86_avx_ptestc_256:
15571 case Intrinsic::x86_avx_ptestnzc_256:
15572 case Intrinsic::x86_avx_vtestz_ps:
15573 case Intrinsic::x86_avx_vtestc_ps:
15574 case Intrinsic::x86_avx_vtestnzc_ps:
15575 case Intrinsic::x86_avx_vtestz_pd:
15576 case Intrinsic::x86_avx_vtestc_pd:
15577 case Intrinsic::x86_avx_vtestnzc_pd:
15578 case Intrinsic::x86_avx_vtestz_ps_256:
15579 case Intrinsic::x86_avx_vtestc_ps_256:
15580 case Intrinsic::x86_avx_vtestnzc_ps_256:
15581 case Intrinsic::x86_avx_vtestz_pd_256:
15582 case Intrinsic::x86_avx_vtestc_pd_256:
15583 case Intrinsic::x86_avx_vtestnzc_pd_256: {
15584 bool IsTestPacked = false;
15587 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
15588 case Intrinsic::x86_avx_vtestz_ps:
15589 case Intrinsic::x86_avx_vtestz_pd:
15590 case Intrinsic::x86_avx_vtestz_ps_256:
15591 case Intrinsic::x86_avx_vtestz_pd_256:
15592 IsTestPacked = true; // Fallthrough
15593 case Intrinsic::x86_sse41_ptestz:
15594 case Intrinsic::x86_avx_ptestz_256:
15596 X86CC = X86::COND_E;
15598 case Intrinsic::x86_avx_vtestc_ps:
15599 case Intrinsic::x86_avx_vtestc_pd:
15600 case Intrinsic::x86_avx_vtestc_ps_256:
15601 case Intrinsic::x86_avx_vtestc_pd_256:
15602 IsTestPacked = true; // Fallthrough
15603 case Intrinsic::x86_sse41_ptestc:
15604 case Intrinsic::x86_avx_ptestc_256:
15606 X86CC = X86::COND_B;
15608 case Intrinsic::x86_avx_vtestnzc_ps:
15609 case Intrinsic::x86_avx_vtestnzc_pd:
15610 case Intrinsic::x86_avx_vtestnzc_ps_256:
15611 case Intrinsic::x86_avx_vtestnzc_pd_256:
15612 IsTestPacked = true; // Fallthrough
15613 case Intrinsic::x86_sse41_ptestnzc:
15614 case Intrinsic::x86_avx_ptestnzc_256:
15616 X86CC = X86::COND_A;
15620 SDValue LHS = Op.getOperand(1);
15621 SDValue RHS = Op.getOperand(2);
15622 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
15623 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
15624 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15625 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
15626 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15628 case Intrinsic::x86_avx512_kortestz_w:
15629 case Intrinsic::x86_avx512_kortestc_w: {
15630 unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;
15631 SDValue LHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(1));
15632 SDValue RHS = DAG.getBitcast(MVT::v16i1, Op.getOperand(2));
15633 SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);
15634 SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);
15635 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);
15636 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15639 case Intrinsic::x86_sse42_pcmpistria128:
15640 case Intrinsic::x86_sse42_pcmpestria128:
15641 case Intrinsic::x86_sse42_pcmpistric128:
15642 case Intrinsic::x86_sse42_pcmpestric128:
15643 case Intrinsic::x86_sse42_pcmpistrio128:
15644 case Intrinsic::x86_sse42_pcmpestrio128:
15645 case Intrinsic::x86_sse42_pcmpistris128:
15646 case Intrinsic::x86_sse42_pcmpestris128:
15647 case Intrinsic::x86_sse42_pcmpistriz128:
15648 case Intrinsic::x86_sse42_pcmpestriz128: {
15652 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
15653 case Intrinsic::x86_sse42_pcmpistria128:
15654 Opcode = X86ISD::PCMPISTRI;
15655 X86CC = X86::COND_A;
15657 case Intrinsic::x86_sse42_pcmpestria128:
15658 Opcode = X86ISD::PCMPESTRI;
15659 X86CC = X86::COND_A;
15661 case Intrinsic::x86_sse42_pcmpistric128:
15662 Opcode = X86ISD::PCMPISTRI;
15663 X86CC = X86::COND_B;
15665 case Intrinsic::x86_sse42_pcmpestric128:
15666 Opcode = X86ISD::PCMPESTRI;
15667 X86CC = X86::COND_B;
15669 case Intrinsic::x86_sse42_pcmpistrio128:
15670 Opcode = X86ISD::PCMPISTRI;
15671 X86CC = X86::COND_O;
15673 case Intrinsic::x86_sse42_pcmpestrio128:
15674 Opcode = X86ISD::PCMPESTRI;
15675 X86CC = X86::COND_O;
15677 case Intrinsic::x86_sse42_pcmpistris128:
15678 Opcode = X86ISD::PCMPISTRI;
15679 X86CC = X86::COND_S;
15681 case Intrinsic::x86_sse42_pcmpestris128:
15682 Opcode = X86ISD::PCMPESTRI;
15683 X86CC = X86::COND_S;
15685 case Intrinsic::x86_sse42_pcmpistriz128:
15686 Opcode = X86ISD::PCMPISTRI;
15687 X86CC = X86::COND_E;
15689 case Intrinsic::x86_sse42_pcmpestriz128:
15690 Opcode = X86ISD::PCMPESTRI;
15691 X86CC = X86::COND_E;
15694 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15695 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15696 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);
15697 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
15698 DAG.getConstant(X86CC, dl, MVT::i8),
15699 SDValue(PCMP.getNode(), 1));
15700 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
15703 case Intrinsic::x86_sse42_pcmpistri128:
15704 case Intrinsic::x86_sse42_pcmpestri128: {
15706 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
15707 Opcode = X86ISD::PCMPISTRI;
15709 Opcode = X86ISD::PCMPESTRI;
15711 SmallVector<SDValue, 5> NewOps(Op->op_begin()+1, Op->op_end());
15712 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
15713 return DAG.getNode(Opcode, dl, VTs, NewOps);
15716 case Intrinsic::x86_seh_lsda: {
15717 // Compute the symbol for the LSDA. We know it'll get emitted later.
15718 MachineFunction &MF = DAG.getMachineFunction();
15719 SDValue Op1 = Op.getOperand(1);
15720 auto *Fn = cast<Function>(cast<GlobalAddressSDNode>(Op1)->getGlobal());
15721 MCSymbol *LSDASym = MF.getMMI().getContext().getOrCreateLSDASymbol(
15722 GlobalValue::getRealLinkageName(Fn->getName()));
15724 // Generate a simple absolute symbol reference. This intrinsic is only
15725 // supported on 32-bit Windows, which isn't PIC.
15726 SDValue Result = DAG.getMCSymbol(LSDASym, VT);
15727 return DAG.getNode(X86ISD::Wrapper, dl, VT, Result);
15730 case Intrinsic::x86_seh_recoverfp: {
15731 SDValue FnOp = Op.getOperand(1);
15732 SDValue IncomingFPOp = Op.getOperand(2);
15733 GlobalAddressSDNode *GSD = dyn_cast<GlobalAddressSDNode>(FnOp);
15734 auto *Fn = dyn_cast_or_null<Function>(GSD ? GSD->getGlobal() : nullptr);
15736 report_fatal_error(
15737 "llvm.x86.seh.recoverfp must take a function as the first argument");
15738 return recoverFramePointer(DAG, Fn, IncomingFPOp);
15743 static SDValue getGatherNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15744 SDValue Src, SDValue Mask, SDValue Base,
15745 SDValue Index, SDValue ScaleOp, SDValue Chain,
15746 const X86Subtarget * Subtarget) {
15748 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15750 llvm_unreachable("Invalid scale type");
15751 unsigned ScaleVal = C->getZExtValue();
15752 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15753 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15755 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15756 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15757 Index.getSimpleValueType().getVectorNumElements());
15759 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15761 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15763 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15764 Mask.getValueType().getSizeInBits());
15766 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15767 // are extracted by EXTRACT_SUBVECTOR.
15768 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15769 DAG.getBitcast(BitcastVT, Mask),
15770 DAG.getIntPtrConstant(0, dl));
15772 SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);
15773 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15774 SDValue Segment = DAG.getRegister(0, MVT::i32);
15775 if (Src.getOpcode() == ISD::UNDEF)
15776 Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);
15777 SDValue Ops[] = {Src, MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15778 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15779 SDValue RetOps[] = { SDValue(Res, 0), SDValue(Res, 2) };
15780 return DAG.getMergeValues(RetOps, dl);
15783 static SDValue getScatterNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15784 SDValue Src, SDValue Mask, SDValue Base,
15785 SDValue Index, SDValue ScaleOp, SDValue Chain) {
15787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15789 llvm_unreachable("Invalid scale type");
15790 unsigned ScaleVal = C->getZExtValue();
15791 if (ScaleVal > 2 && ScaleVal != 4 && ScaleVal != 8)
15792 llvm_unreachable("Valid scale values are 1, 2, 4, 8");
15794 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15795 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15796 SDValue Segment = DAG.getRegister(0, MVT::i32);
15797 EVT MaskVT = MVT::getVectorVT(MVT::i1,
15798 Index.getSimpleValueType().getVectorNumElements());
15800 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15802 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15804 EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
15805 Mask.getValueType().getSizeInBits());
15807 // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements
15808 // are extracted by EXTRACT_SUBVECTOR.
15809 MaskInReg = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,
15810 DAG.getBitcast(BitcastVT, Mask),
15811 DAG.getIntPtrConstant(0, dl));
15813 SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);
15814 SDValue Ops[] = {Base, Scale, Index, Disp, Segment, MaskInReg, Src, Chain};
15815 SDNode *Res = DAG.getMachineNode(Opc, dl, VTs, Ops);
15816 return SDValue(Res, 1);
15819 static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
15820 SDValue Mask, SDValue Base, SDValue Index,
15821 SDValue ScaleOp, SDValue Chain) {
15823 ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);
15824 assert(C && "Invalid scale type");
15825 SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
15826 SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
15827 SDValue Segment = DAG.getRegister(0, MVT::i32);
15829 MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
15831 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);
15833 MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);
15835 MaskInReg = DAG.getBitcast(MaskVT, Mask);
15836 //SDVTList VTs = DAG.getVTList(MVT::Other);
15837 SDValue Ops[] = {MaskInReg, Base, Scale, Index, Disp, Segment, Chain};
15838 SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
15839 return SDValue(Res, 0);
15842 // getReadPerformanceCounter - Handles the lowering of builtin intrinsics that
15843 // read performance monitor counters (x86_rdpmc).
15844 static void getReadPerformanceCounter(SDNode *N, SDLoc DL,
15845 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15846 SmallVectorImpl<SDValue> &Results) {
15847 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15848 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15851 // The ECX register is used to select the index of the performance counter
15853 SDValue Chain = DAG.getCopyToReg(N->getOperand(0), DL, X86::ECX,
15855 SDValue rd = DAG.getNode(X86ISD::RDPMC_DAG, DL, Tys, Chain);
15857 // Reads the content of a 64-bit performance counter and returns it in the
15858 // registers EDX:EAX.
15859 if (Subtarget->is64Bit()) {
15860 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15861 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15864 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15865 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15868 Chain = HI.getValue(1);
15870 if (Subtarget->is64Bit()) {
15871 // The EAX register is loaded with the low-order 32 bits. The EDX register
15872 // is loaded with the supported high-order bits of the counter.
15873 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15874 DAG.getConstant(32, DL, MVT::i8));
15875 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15876 Results.push_back(Chain);
15880 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15881 SDValue Ops[] = { LO, HI };
15882 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15883 Results.push_back(Pair);
15884 Results.push_back(Chain);
15887 // getReadTimeStampCounter - Handles the lowering of builtin intrinsics that
15888 // read the time stamp counter (x86_rdtsc and x86_rdtscp). This function is
15889 // also used to custom lower READCYCLECOUNTER nodes.
15890 static void getReadTimeStampCounter(SDNode *N, SDLoc DL, unsigned Opcode,
15891 SelectionDAG &DAG, const X86Subtarget *Subtarget,
15892 SmallVectorImpl<SDValue> &Results) {
15893 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
15894 SDValue rd = DAG.getNode(Opcode, DL, Tys, N->getOperand(0));
15897 // The processor's time-stamp counter (a 64-bit MSR) is stored into the
15898 // EDX:EAX registers. EDX is loaded with the high-order 32 bits of the MSR
15899 // and the EAX register is loaded with the low-order 32 bits.
15900 if (Subtarget->is64Bit()) {
15901 LO = DAG.getCopyFromReg(rd, DL, X86::RAX, MVT::i64, rd.getValue(1));
15902 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::RDX, MVT::i64,
15905 LO = DAG.getCopyFromReg(rd, DL, X86::EAX, MVT::i32, rd.getValue(1));
15906 HI = DAG.getCopyFromReg(LO.getValue(1), DL, X86::EDX, MVT::i32,
15909 SDValue Chain = HI.getValue(1);
15911 if (Opcode == X86ISD::RDTSCP_DAG) {
15912 assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
15914 // Instruction RDTSCP loads the IA32:TSC_AUX_MSR (address C000_0103H) into
15915 // the ECX register. Add 'ecx' explicitly to the chain.
15916 SDValue ecx = DAG.getCopyFromReg(Chain, DL, X86::ECX, MVT::i32,
15918 // Explicitly store the content of ECX at the location passed in input
15919 // to the 'rdtscp' intrinsic.
15920 Chain = DAG.getStore(ecx.getValue(1), DL, ecx, N->getOperand(2),
15921 MachinePointerInfo(), false, false, 0);
15924 if (Subtarget->is64Bit()) {
15925 // The EDX register is loaded with the high-order 32 bits of the MSR, and
15926 // the EAX register is loaded with the low-order 32 bits.
15927 SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,
15928 DAG.getConstant(32, DL, MVT::i8));
15929 Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));
15930 Results.push_back(Chain);
15934 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
15935 SDValue Ops[] = { LO, HI };
15936 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops);
15937 Results.push_back(Pair);
15938 Results.push_back(Chain);
15941 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
15942 SelectionDAG &DAG) {
15943 SmallVector<SDValue, 2> Results;
15945 getReadTimeStampCounter(Op.getNode(), DL, X86ISD::RDTSC_DAG, DAG, Subtarget,
15947 return DAG.getMergeValues(Results, DL);
15950 static SDValue LowerSEHRESTOREFRAME(SDValue Op, const X86Subtarget *Subtarget,
15951 SelectionDAG &DAG) {
15952 MachineFunction &MF = DAG.getMachineFunction();
15954 SDValue Chain = Op.getOperand(0);
15956 assert(Subtarget->getFrameLowering()->hasFP(MF) &&
15957 "using llvm.x86.seh.restoreframe requires a frame pointer");
15959 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15960 MVT VT = TLI.getPointerTy();
15962 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
15963 unsigned FrameReg =
15964 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
15965 unsigned SPReg = RegInfo->getStackRegister();
15967 // Get incoming EBP.
15968 SDValue IncomingEBP =
15969 DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
15971 // Load [EBP-24] into SP.
15973 DAG.getNode(ISD::ADD, dl, VT, IncomingEBP, DAG.getConstant(-24, dl, VT));
15975 DAG.getLoad(VT, dl, Chain, SPAddr, MachinePointerInfo(), false, false,
15976 false, VT.getScalarSizeInBits() / 8);
15977 Chain = DAG.getCopyToReg(Chain, dl, SPReg, NewSP);
15979 // FIXME: Restore the base pointer in case of stack realignment!
15980 if (RegInfo->needsStackRealignment(MF))
15981 report_fatal_error("SEH with stack realignment not yet implemented");
15983 // Adjust EBP to point back to the original frame position.
15984 SDValue NewFP = recoverFramePointer(DAG, MF.getFunction(), IncomingEBP);
15985 Chain = DAG.getCopyToReg(Chain, dl, FrameReg, NewFP);
15989 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
15990 SelectionDAG &DAG) {
15991 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
15993 const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
15995 if (IntNo == llvm::Intrinsic::x86_seh_restoreframe)
15996 return LowerSEHRESTOREFRAME(Op, Subtarget, DAG);
16001 switch(IntrData->Type) {
16003 llvm_unreachable("Unknown Intrinsic Type");
16007 // Emit the node with the right value type.
16008 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
16009 SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16011 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
16012 // Otherwise return the value from Rand, which is always 0, casted to i32.
16013 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
16014 DAG.getConstant(1, dl, Op->getValueType(1)),
16015 DAG.getConstant(X86::COND_B, dl, MVT::i32),
16016 SDValue(Result.getNode(), 1) };
16017 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
16018 DAG.getVTList(Op->getValueType(1), MVT::Glue),
16021 // Return { result, isValid, chain }.
16022 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
16023 SDValue(Result.getNode(), 2));
16026 //gather(v1, mask, index, base, scale);
16027 SDValue Chain = Op.getOperand(0);
16028 SDValue Src = Op.getOperand(2);
16029 SDValue Base = Op.getOperand(3);
16030 SDValue Index = Op.getOperand(4);
16031 SDValue Mask = Op.getOperand(5);
16032 SDValue Scale = Op.getOperand(6);
16033 return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale,
16037 //scatter(base, mask, index, v1, scale);
16038 SDValue Chain = Op.getOperand(0);
16039 SDValue Base = Op.getOperand(2);
16040 SDValue Mask = Op.getOperand(3);
16041 SDValue Index = Op.getOperand(4);
16042 SDValue Src = Op.getOperand(5);
16043 SDValue Scale = Op.getOperand(6);
16044 return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index,
16048 SDValue Hint = Op.getOperand(6);
16049 unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
16050 assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
16051 unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
16052 SDValue Chain = Op.getOperand(0);
16053 SDValue Mask = Op.getOperand(2);
16054 SDValue Index = Op.getOperand(3);
16055 SDValue Base = Op.getOperand(4);
16056 SDValue Scale = Op.getOperand(5);
16057 return getPrefetchNode(Opcode, Op, DAG, Mask, Base, Index, Scale, Chain);
16059 // Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
16061 SmallVector<SDValue, 2> Results;
16062 getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget,
16064 return DAG.getMergeValues(Results, dl);
16066 // Read Performance Monitoring Counters.
16068 SmallVector<SDValue, 2> Results;
16069 getReadPerformanceCounter(Op.getNode(), dl, DAG, Subtarget, Results);
16070 return DAG.getMergeValues(Results, dl);
16072 // XTEST intrinsics.
16074 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16075 SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
16076 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16077 DAG.getConstant(X86::COND_NE, dl, MVT::i8),
16079 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
16080 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
16081 Ret, SDValue(InTrans.getNode(), 1));
16085 SmallVector<SDValue, 2> Results;
16086 SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
16087 SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);
16088 SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),
16089 DAG.getConstant(-1, dl, MVT::i8));
16090 SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),
16091 Op.getOperand(4), GenCF.getValue(1));
16092 SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),
16093 Op.getOperand(5), MachinePointerInfo(),
16095 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
16096 DAG.getConstant(X86::COND_B, dl, MVT::i8),
16098 Results.push_back(SetCC);
16099 Results.push_back(Store);
16100 return DAG.getMergeValues(Results, dl);
16102 case COMPRESS_TO_MEM: {
16104 SDValue Mask = Op.getOperand(4);
16105 SDValue DataToCompress = Op.getOperand(3);
16106 SDValue Addr = Op.getOperand(2);
16107 SDValue Chain = Op.getOperand(0);
16109 EVT VT = DataToCompress.getValueType();
16110 if (isAllOnes(Mask)) // return just a store
16111 return DAG.getStore(Chain, dl, DataToCompress, Addr,
16112 MachinePointerInfo(), false, false,
16113 VT.getScalarSizeInBits()/8);
16115 SDValue Compressed =
16116 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToCompress),
16117 Mask, DAG.getUNDEF(VT), Subtarget, DAG);
16118 return DAG.getStore(Chain, dl, Compressed, Addr,
16119 MachinePointerInfo(), false, false,
16120 VT.getScalarSizeInBits()/8);
16122 case EXPAND_FROM_MEM: {
16124 SDValue Mask = Op.getOperand(4);
16125 SDValue PassThru = Op.getOperand(3);
16126 SDValue Addr = Op.getOperand(2);
16127 SDValue Chain = Op.getOperand(0);
16128 EVT VT = Op.getValueType();
16130 if (isAllOnes(Mask)) // return just a load
16131 return DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(), false, false,
16132 false, VT.getScalarSizeInBits()/8);
16134 SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),
16135 false, false, false,
16136 VT.getScalarSizeInBits()/8);
16138 SDValue Results[] = {
16139 getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, DataToExpand),
16140 Mask, PassThru, Subtarget, DAG), Chain};
16141 return DAG.getMergeValues(Results, dl);
16146 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
16147 SelectionDAG &DAG) const {
16148 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
16149 MFI->setReturnAddressIsTaken(true);
16151 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
16154 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16156 EVT PtrVT = getPointerTy();
16159 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
16160 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16161 SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);
16162 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16163 DAG.getNode(ISD::ADD, dl, PtrVT,
16164 FrameAddr, Offset),
16165 MachinePointerInfo(), false, false, false, 0);
16168 // Just load the return address.
16169 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
16170 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
16171 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
16174 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
16175 MachineFunction &MF = DAG.getMachineFunction();
16176 MachineFrameInfo *MFI = MF.getFrameInfo();
16177 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
16178 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16179 EVT VT = Op.getValueType();
16181 MFI->setFrameAddressIsTaken(true);
16183 if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI()) {
16184 // Depth > 0 makes no sense on targets which use Windows unwind codes. It
16185 // is not possible to crawl up the stack without looking at the unwind codes
16187 int FrameAddrIndex = FuncInfo->getFAIndex();
16188 if (!FrameAddrIndex) {
16189 // Set up a frame object for the return address.
16190 unsigned SlotSize = RegInfo->getSlotSize();
16191 FrameAddrIndex = MF.getFrameInfo()->CreateFixedObject(
16192 SlotSize, /*Offset=*/0, /*IsImmutable=*/false);
16193 FuncInfo->setFAIndex(FrameAddrIndex);
16195 return DAG.getFrameIndex(FrameAddrIndex, VT);
16198 unsigned FrameReg =
16199 RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
16200 SDLoc dl(Op); // FIXME probably not meaningful
16201 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
16202 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
16203 (FrameReg == X86::EBP && VT == MVT::i32)) &&
16204 "Invalid Frame Register!");
16205 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
16207 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
16208 MachinePointerInfo(),
16209 false, false, false, 0);
16213 // FIXME? Maybe this could be a TableGen attribute on some registers and
16214 // this table could be generated automatically from RegInfo.
16215 unsigned X86TargetLowering::getRegisterByName(const char* RegName,
16217 unsigned Reg = StringSwitch<unsigned>(RegName)
16218 .Case("esp", X86::ESP)
16219 .Case("rsp", X86::RSP)
16223 report_fatal_error("Invalid register name global variable");
16226 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
16227 SelectionDAG &DAG) const {
16228 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16229 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));
16232 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
16233 SDValue Chain = Op.getOperand(0);
16234 SDValue Offset = Op.getOperand(1);
16235 SDValue Handler = Op.getOperand(2);
16238 EVT PtrVT = getPointerTy();
16239 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
16240 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
16241 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
16242 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
16243 "Invalid Frame Register!");
16244 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
16245 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
16247 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
16248 DAG.getIntPtrConstant(RegInfo->getSlotSize(),
16250 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
16251 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
16253 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
16255 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
16256 DAG.getRegister(StoreAddrReg, PtrVT));
16259 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
16260 SelectionDAG &DAG) const {
16262 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
16263 DAG.getVTList(MVT::i32, MVT::Other),
16264 Op.getOperand(0), Op.getOperand(1));
16267 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
16268 SelectionDAG &DAG) const {
16270 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
16271 Op.getOperand(0), Op.getOperand(1));
16274 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
16275 return Op.getOperand(0);
16278 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
16279 SelectionDAG &DAG) const {
16280 SDValue Root = Op.getOperand(0);
16281 SDValue Trmp = Op.getOperand(1); // trampoline
16282 SDValue FPtr = Op.getOperand(2); // nested function
16283 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
16286 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
16287 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
16289 if (Subtarget->is64Bit()) {
16290 SDValue OutChains[6];
16292 // Large code-model.
16293 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
16294 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
16296 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
16297 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
16299 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
16301 // Load the pointer to the nested function into R11.
16302 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
16303 SDValue Addr = Trmp;
16304 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16305 Addr, MachinePointerInfo(TrmpAddr),
16308 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16309 DAG.getConstant(2, dl, MVT::i64));
16310 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
16311 MachinePointerInfo(TrmpAddr, 2),
16314 // Load the 'nest' parameter value into R10.
16315 // R10 is specified in X86CallingConv.td
16316 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
16317 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16318 DAG.getConstant(10, dl, MVT::i64));
16319 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16320 Addr, MachinePointerInfo(TrmpAddr, 10),
16323 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16324 DAG.getConstant(12, dl, MVT::i64));
16325 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
16326 MachinePointerInfo(TrmpAddr, 12),
16329 // Jump to the nested function.
16330 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
16331 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16332 DAG.getConstant(20, dl, MVT::i64));
16333 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),
16334 Addr, MachinePointerInfo(TrmpAddr, 20),
16337 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
16338 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
16339 DAG.getConstant(22, dl, MVT::i64));
16340 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),
16341 Addr, MachinePointerInfo(TrmpAddr, 22),
16344 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16346 const Function *Func =
16347 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
16348 CallingConv::ID CC = Func->getCallingConv();
16353 llvm_unreachable("Unsupported calling convention");
16354 case CallingConv::C:
16355 case CallingConv::X86_StdCall: {
16356 // Pass 'nest' parameter in ECX.
16357 // Must be kept in sync with X86CallingConv.td
16358 NestReg = X86::ECX;
16360 // Check that ECX wasn't needed by an 'inreg' parameter.
16361 FunctionType *FTy = Func->getFunctionType();
16362 const AttributeSet &Attrs = Func->getAttributes();
16364 if (!Attrs.isEmpty() && !Func->isVarArg()) {
16365 unsigned InRegCount = 0;
16368 for (FunctionType::param_iterator I = FTy->param_begin(),
16369 E = FTy->param_end(); I != E; ++I, ++Idx)
16370 if (Attrs.hasAttribute(Idx, Attribute::InReg))
16371 // FIXME: should only count parameters that are lowered to integers.
16372 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
16374 if (InRegCount > 2) {
16375 report_fatal_error("Nest register in use - reduce number of inreg"
16381 case CallingConv::X86_FastCall:
16382 case CallingConv::X86_ThisCall:
16383 case CallingConv::Fast:
16384 // Pass 'nest' parameter in EAX.
16385 // Must be kept in sync with X86CallingConv.td
16386 NestReg = X86::EAX;
16390 SDValue OutChains[4];
16391 SDValue Addr, Disp;
16393 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16394 DAG.getConstant(10, dl, MVT::i32));
16395 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
16397 // This is storing the opcode for MOV32ri.
16398 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
16399 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
16400 OutChains[0] = DAG.getStore(Root, dl,
16401 DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),
16402 Trmp, MachinePointerInfo(TrmpAddr),
16405 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16406 DAG.getConstant(1, dl, MVT::i32));
16407 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
16408 MachinePointerInfo(TrmpAddr, 1),
16411 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
16412 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16413 DAG.getConstant(5, dl, MVT::i32));
16414 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),
16415 Addr, MachinePointerInfo(TrmpAddr, 5),
16418 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
16419 DAG.getConstant(6, dl, MVT::i32));
16420 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
16421 MachinePointerInfo(TrmpAddr, 6),
16424 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
16428 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
16429 SelectionDAG &DAG) const {
16431 The rounding mode is in bits 11:10 of FPSR, and has the following
16433 00 Round to nearest
16438 FLT_ROUNDS, on the other hand, expects the following:
16445 To perform the conversion, we do:
16446 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
16449 MachineFunction &MF = DAG.getMachineFunction();
16450 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering();
16451 unsigned StackAlignment = TFI.getStackAlignment();
16452 MVT VT = Op.getSimpleValueType();
16455 // Save FP Control Word to stack slot
16456 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
16457 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
16459 MachineMemOperand *MMO =
16460 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
16461 MachineMemOperand::MOStore, 2, 2);
16463 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
16464 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
16465 DAG.getVTList(MVT::Other),
16466 Ops, MVT::i16, MMO);
16468 // Load FP Control Word from stack slot
16469 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
16470 MachinePointerInfo(), false, false, false, 0);
16472 // Transform as necessary
16474 DAG.getNode(ISD::SRL, DL, MVT::i16,
16475 DAG.getNode(ISD::AND, DL, MVT::i16,
16476 CWD, DAG.getConstant(0x800, DL, MVT::i16)),
16477 DAG.getConstant(11, DL, MVT::i8));
16479 DAG.getNode(ISD::SRL, DL, MVT::i16,
16480 DAG.getNode(ISD::AND, DL, MVT::i16,
16481 CWD, DAG.getConstant(0x400, DL, MVT::i16)),
16482 DAG.getConstant(9, DL, MVT::i8));
16485 DAG.getNode(ISD::AND, DL, MVT::i16,
16486 DAG.getNode(ISD::ADD, DL, MVT::i16,
16487 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
16488 DAG.getConstant(1, DL, MVT::i16)),
16489 DAG.getConstant(3, DL, MVT::i16));
16491 return DAG.getNode((VT.getSizeInBits() < 16 ?
16492 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
16495 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
16496 MVT VT = Op.getSimpleValueType();
16498 unsigned NumBits = VT.getSizeInBits();
16501 Op = Op.getOperand(0);
16502 if (VT == MVT::i8) {
16503 // Zero extend to i32 since there is not an i8 bsr.
16505 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16508 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
16509 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16510 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16512 // If src is zero (i.e. bsr sets ZF), returns NumBits.
16515 DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),
16516 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16519 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);
16521 // Finally xor with NumBits-1.
16522 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16523 DAG.getConstant(NumBits - 1, dl, OpVT));
16526 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16530 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
16531 MVT VT = Op.getSimpleValueType();
16533 unsigned NumBits = VT.getSizeInBits();
16536 Op = Op.getOperand(0);
16537 if (VT == MVT::i8) {
16538 // Zero extend to i32 since there is not an i8 bsr.
16540 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
16543 // Issue a bsr (scan bits in reverse).
16544 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
16545 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
16547 // And xor with NumBits-1.
16548 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,
16549 DAG.getConstant(NumBits - 1, dl, OpVT));
16552 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
16556 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
16557 MVT VT = Op.getSimpleValueType();
16558 unsigned NumBits = VT.getSizeInBits();
16560 Op = Op.getOperand(0);
16562 // Issue a bsf (scan bits forward) which also sets EFLAGS.
16563 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
16564 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
16566 // If src is zero (i.e. bsf sets ZF), returns NumBits.
16569 DAG.getConstant(NumBits, dl, VT),
16570 DAG.getConstant(X86::COND_E, dl, MVT::i8),
16573 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);
16576 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
16577 // ones, and then concatenate the result back.
16578 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
16579 MVT VT = Op.getSimpleValueType();
16581 assert(VT.is256BitVector() && VT.isInteger() &&
16582 "Unsupported value type for operation");
16584 unsigned NumElems = VT.getVectorNumElements();
16587 // Extract the LHS vectors
16588 SDValue LHS = Op.getOperand(0);
16589 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
16590 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
16592 // Extract the RHS vectors
16593 SDValue RHS = Op.getOperand(1);
16594 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
16595 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
16597 MVT EltVT = VT.getVectorElementType();
16598 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
16600 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16601 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
16602 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
16605 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
16606 if (Op.getValueType() == MVT::i1)
16607 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16608 Op.getOperand(0), Op.getOperand(1));
16609 assert(Op.getSimpleValueType().is256BitVector() &&
16610 Op.getSimpleValueType().isInteger() &&
16611 "Only handle AVX 256-bit vector integer operation");
16612 return Lower256IntArith(Op, DAG);
16615 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
16616 if (Op.getValueType() == MVT::i1)
16617 return DAG.getNode(ISD::XOR, SDLoc(Op), Op.getValueType(),
16618 Op.getOperand(0), Op.getOperand(1));
16619 assert(Op.getSimpleValueType().is256BitVector() &&
16620 Op.getSimpleValueType().isInteger() &&
16621 "Only handle AVX 256-bit vector integer operation");
16622 return Lower256IntArith(Op, DAG);
16625 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
16626 SelectionDAG &DAG) {
16628 MVT VT = Op.getSimpleValueType();
16631 return DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), Op.getOperand(1));
16633 // Decompose 256-bit ops into smaller 128-bit ops.
16634 if (VT.is256BitVector() && !Subtarget->hasInt256())
16635 return Lower256IntArith(Op, DAG);
16637 SDValue A = Op.getOperand(0);
16638 SDValue B = Op.getOperand(1);
16640 // Lower v16i8/v32i8 mul as promotion to v8i16/v16i16 vector
16641 // pairs, multiply and truncate.
16642 if (VT == MVT::v16i8 || VT == MVT::v32i8) {
16643 if (Subtarget->hasInt256()) {
16644 if (VT == MVT::v32i8) {
16645 MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);
16646 SDValue Lo = DAG.getIntPtrConstant(0, dl);
16647 SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);
16648 SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);
16649 SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);
16650 SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);
16651 SDValue BHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Hi);
16652 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
16653 DAG.getNode(ISD::MUL, dl, SubVT, ALo, BLo),
16654 DAG.getNode(ISD::MUL, dl, SubVT, AHi, BHi));
16657 MVT ExVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements());
16658 return DAG.getNode(
16659 ISD::TRUNCATE, dl, VT,
16660 DAG.getNode(ISD::MUL, dl, ExVT,
16661 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, A),
16662 DAG.getNode(ISD::SIGN_EXTEND, dl, ExVT, B)));
16665 assert(VT == MVT::v16i8 &&
16666 "Pre-AVX2 support only supports v16i8 multiplication");
16667 MVT ExVT = MVT::v8i16;
16669 // Extract the lo parts and sign extend to i16
16671 if (Subtarget->hasSSE41()) {
16672 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A);
16673 BLo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, B);
16675 const int ShufMask[] = {-1, 0, -1, 1, -1, 2, -1, 3,
16676 -1, 4, -1, 5, -1, 6, -1, 7};
16677 ALo = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16678 BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16679 ALo = DAG.getBitcast(ExVT, ALo);
16680 BLo = DAG.getBitcast(ExVT, BLo);
16681 ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));
16682 BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));
16685 // Extract the hi parts and sign extend to i16
16687 if (Subtarget->hasSSE41()) {
16688 const int ShufMask[] = {8, 9, 10, 11, 12, 13, 14, 15,
16689 -1, -1, -1, -1, -1, -1, -1, -1};
16690 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16691 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16692 AHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, AHi);
16693 BHi = DAG.getNode(X86ISD::VSEXT, dl, ExVT, BHi);
16695 const int ShufMask[] = {-1, 8, -1, 9, -1, 10, -1, 11,
16696 -1, 12, -1, 13, -1, 14, -1, 15};
16697 AHi = DAG.getVectorShuffle(VT, dl, A, A, ShufMask);
16698 BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);
16699 AHi = DAG.getBitcast(ExVT, AHi);
16700 BHi = DAG.getBitcast(ExVT, BHi);
16701 AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));
16702 BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));
16705 // Multiply, mask the lower 8bits of the lo/hi results and pack
16706 SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);
16707 SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);
16708 RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));
16709 RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));
16710 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
16713 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
16714 if (VT == MVT::v4i32) {
16715 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
16716 "Should not custom lower when pmuldq is available!");
16718 // Extract the odd parts.
16719 static const int UnpackMask[] = { 1, -1, 3, -1 };
16720 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
16721 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
16723 // Multiply the even parts.
16724 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
16725 // Now multiply odd parts.
16726 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
16728 Evens = DAG.getBitcast(VT, Evens);
16729 Odds = DAG.getBitcast(VT, Odds);
16731 // Merge the two vectors back together with a shuffle. This expands into 2
16733 static const int ShufMask[] = { 0, 4, 2, 6 };
16734 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
16737 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
16738 "Only know how to lower V2I64/V4I64/V8I64 multiply");
16740 // Ahi = psrlqi(a, 32);
16741 // Bhi = psrlqi(b, 32);
16743 // AloBlo = pmuludq(a, b);
16744 // AloBhi = pmuludq(a, Bhi);
16745 // AhiBlo = pmuludq(Ahi, b);
16747 // AloBhi = psllqi(AloBhi, 32);
16748 // AhiBlo = psllqi(AhiBlo, 32);
16749 // return AloBlo + AloBhi + AhiBlo;
16751 SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);
16752 SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);
16754 SDValue AhiBlo = Ahi;
16755 SDValue AloBhi = Bhi;
16756 // Bit cast to 32-bit vectors for MULUDQ
16757 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 :
16758 (VT == MVT::v4i64) ? MVT::v8i32 : MVT::v16i32;
16759 A = DAG.getBitcast(MulVT, A);
16760 B = DAG.getBitcast(MulVT, B);
16761 Ahi = DAG.getBitcast(MulVT, Ahi);
16762 Bhi = DAG.getBitcast(MulVT, Bhi);
16764 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
16765 // After shifting right const values the result may be all-zero.
16766 if (!ISD::isBuildVectorAllZeros(Ahi.getNode())) {
16767 AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
16768 AhiBlo = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AhiBlo, 32, DAG);
16770 if (!ISD::isBuildVectorAllZeros(Bhi.getNode())) {
16771 AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
16772 AloBhi = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, VT, AloBhi, 32, DAG);
16775 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
16776 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
16779 SDValue X86TargetLowering::LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const {
16780 assert(Subtarget->isTargetWin64() && "Unexpected target");
16781 EVT VT = Op.getValueType();
16782 assert(VT.isInteger() && VT.getSizeInBits() == 128 &&
16783 "Unexpected return type for lowering");
16787 switch (Op->getOpcode()) {
16788 default: llvm_unreachable("Unexpected request for libcall!");
16789 case ISD::SDIV: isSigned = true; LC = RTLIB::SDIV_I128; break;
16790 case ISD::UDIV: isSigned = false; LC = RTLIB::UDIV_I128; break;
16791 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
16792 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
16793 case ISD::SDIVREM: isSigned = true; LC = RTLIB::SDIVREM_I128; break;
16794 case ISD::UDIVREM: isSigned = false; LC = RTLIB::UDIVREM_I128; break;
16798 SDValue InChain = DAG.getEntryNode();
16800 TargetLowering::ArgListTy Args;
16801 TargetLowering::ArgListEntry Entry;
16802 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
16803 EVT ArgVT = Op->getOperand(i).getValueType();
16804 assert(ArgVT.isInteger() && ArgVT.getSizeInBits() == 128 &&
16805 "Unexpected argument type for lowering");
16806 SDValue StackPtr = DAG.CreateStackTemporary(ArgVT, 16);
16807 Entry.Node = StackPtr;
16808 InChain = DAG.getStore(InChain, dl, Op->getOperand(i), StackPtr, MachinePointerInfo(),
16810 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
16811 Entry.Ty = PointerType::get(ArgTy,0);
16812 Entry.isSExt = false;
16813 Entry.isZExt = false;
16814 Args.push_back(Entry);
16817 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
16820 TargetLowering::CallLoweringInfo CLI(DAG);
16821 CLI.setDebugLoc(dl).setChain(InChain)
16822 .setCallee(getLibcallCallingConv(LC),
16823 static_cast<EVT>(MVT::v2i64).getTypeForEVT(*DAG.getContext()),
16824 Callee, std::move(Args), 0)
16825 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
16827 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
16828 return DAG.getBitcast(VT, CallInfo.first);
16831 static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget,
16832 SelectionDAG &DAG) {
16833 SDValue Op0 = Op.getOperand(0), Op1 = Op.getOperand(1);
16834 EVT VT = Op0.getValueType();
16837 assert((VT == MVT::v4i32 && Subtarget->hasSSE2()) ||
16838 (VT == MVT::v8i32 && Subtarget->hasInt256()));
16840 // PMULxD operations multiply each even value (starting at 0) of LHS with
16841 // the related value of RHS and produce a widen result.
16842 // E.g., PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16843 // => <2 x i64> <ae|cg>
16845 // In other word, to have all the results, we need to perform two PMULxD:
16846 // 1. one with the even values.
16847 // 2. one with the odd values.
16848 // To achieve #2, with need to place the odd values at an even position.
16850 // Place the odd value at an even position (basically, shift all values 1
16851 // step to the left):
16852 const int Mask[] = {1, -1, 3, -1, 5, -1, 7, -1};
16853 // <a|b|c|d> => <b|undef|d|undef>
16854 SDValue Odd0 = DAG.getVectorShuffle(VT, dl, Op0, Op0, Mask);
16855 // <e|f|g|h> => <f|undef|h|undef>
16856 SDValue Odd1 = DAG.getVectorShuffle(VT, dl, Op1, Op1, Mask);
16858 // Emit two multiplies, one for the lower 2 ints and one for the higher 2
16860 MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64;
16861 bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI;
16863 (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ;
16864 // PMULUDQ <4 x i32> <a|b|c|d>, <4 x i32> <e|f|g|h>
16865 // => <2 x i64> <ae|cg>
16866 SDValue Mul1 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Op0, Op1));
16867 // PMULUDQ <4 x i32> <b|undef|d|undef>, <4 x i32> <f|undef|h|undef>
16868 // => <2 x i64> <bf|dh>
16869 SDValue Mul2 = DAG.getBitcast(VT, DAG.getNode(Opcode, dl, MulVT, Odd0, Odd1));
16871 // Shuffle it back into the right order.
16872 SDValue Highs, Lows;
16873 if (VT == MVT::v8i32) {
16874 const int HighMask[] = {1, 9, 3, 11, 5, 13, 7, 15};
16875 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16876 const int LowMask[] = {0, 8, 2, 10, 4, 12, 6, 14};
16877 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16879 const int HighMask[] = {1, 5, 3, 7};
16880 Highs = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, HighMask);
16881 const int LowMask[] = {0, 4, 2, 6};
16882 Lows = DAG.getVectorShuffle(VT, dl, Mul1, Mul2, LowMask);
16885 // If we have a signed multiply but no PMULDQ fix up the high parts of a
16886 // unsigned multiply.
16887 if (IsSigned && !Subtarget->hasSSE41()) {
16889 DAG.getConstant(31, dl,
16890 DAG.getTargetLoweringInfo().getShiftAmountTy(VT));
16891 SDValue T1 = DAG.getNode(ISD::AND, dl, VT,
16892 DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);
16893 SDValue T2 = DAG.getNode(ISD::AND, dl, VT,
16894 DAG.getNode(ISD::SRA, dl, VT, Op1, ShAmt), Op0);
16896 SDValue Fixup = DAG.getNode(ISD::ADD, dl, VT, T1, T2);
16897 Highs = DAG.getNode(ISD::SUB, dl, VT, Highs, Fixup);
16900 // The first result of MUL_LOHI is actually the low value, followed by the
16902 SDValue Ops[] = {Lows, Highs};
16903 return DAG.getMergeValues(Ops, dl);
16906 // Return true if the requred (according to Opcode) shift-imm form is natively
16907 // supported by the Subtarget
16908 static bool SupportedVectorShiftWithImm(MVT VT, const X86Subtarget *Subtarget,
16910 if (VT.getScalarSizeInBits() < 16)
16913 if (VT.is512BitVector() &&
16914 (VT.getScalarSizeInBits() > 16 || Subtarget->hasBWI()))
16917 bool LShift = VT.is128BitVector() ||
16918 (VT.is256BitVector() && Subtarget->hasInt256());
16920 bool AShift = LShift && (Subtarget->hasVLX() ||
16921 (VT != MVT::v2i64 && VT != MVT::v4i64));
16922 return (Opcode == ISD::SRA) ? AShift : LShift;
16925 // The shift amount is a variable, but it is the same for all vector lanes.
16926 // These instrcutions are defined together with shift-immediate.
16928 bool SupportedVectorShiftWithBaseAmnt(MVT VT, const X86Subtarget *Subtarget,
16930 return SupportedVectorShiftWithImm(VT, Subtarget, Opcode);
16933 // Return true if the requred (according to Opcode) variable-shift form is
16934 // natively supported by the Subtarget
16935 static bool SupportedVectorVarShift(MVT VT, const X86Subtarget *Subtarget,
16938 if (!Subtarget->hasInt256() || VT.getScalarSizeInBits() < 16)
16941 // vXi16 supported only on AVX-512, BWI
16942 if (VT.getScalarSizeInBits() == 16 && !Subtarget->hasBWI())
16945 if (VT.is512BitVector() || Subtarget->hasVLX())
16948 bool LShift = VT.is128BitVector() || VT.is256BitVector();
16949 bool AShift = LShift && VT != MVT::v2i64 && VT != MVT::v4i64;
16950 return (Opcode == ISD::SRA) ? AShift : LShift;
16953 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
16954 const X86Subtarget *Subtarget) {
16955 MVT VT = Op.getSimpleValueType();
16957 SDValue R = Op.getOperand(0);
16958 SDValue Amt = Op.getOperand(1);
16960 unsigned X86Opc = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
16961 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
16963 auto ArithmeticShiftRight64 = [&](uint64_t ShiftAmt) {
16964 assert((VT == MVT::v2i64 || VT == MVT::v4i64) && "Unexpected SRA type");
16965 MVT ExVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() * 2);
16966 SDValue Ex = DAG.getBitcast(ExVT, R);
16968 if (ShiftAmt >= 32) {
16969 // Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
16971 getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex, 31, DAG);
16972 SDValue Lower = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
16973 ShiftAmt - 32, DAG);
16974 if (VT == MVT::v2i64)
16975 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {5, 1, 7, 3});
16976 if (VT == MVT::v4i64)
16977 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
16978 {9, 1, 11, 3, 13, 5, 15, 7});
16980 // SRA upper i32, SHL whole i64 and select lower i32.
16981 SDValue Upper = getTargetVShiftByConstNode(X86ISD::VSRAI, dl, ExVT, Ex,
16984 getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt, DAG);
16985 Lower = DAG.getBitcast(ExVT, Lower);
16986 if (VT == MVT::v2i64)
16987 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower, {4, 1, 6, 3});
16988 if (VT == MVT::v4i64)
16989 Ex = DAG.getVectorShuffle(ExVT, dl, Upper, Lower,
16990 {8, 1, 10, 3, 12, 5, 14, 7});
16992 return DAG.getBitcast(VT, Ex);
16995 // Optimize shl/srl/sra with constant shift amount.
16996 if (auto *BVAmt = dyn_cast<BuildVectorSDNode>(Amt)) {
16997 if (auto *ShiftConst = BVAmt->getConstantSplatNode()) {
16998 uint64_t ShiftAmt = ShiftConst->getZExtValue();
17000 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17001 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17003 // i64 SRA needs to be performed as partial shifts.
17004 if ((VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17005 Op.getOpcode() == ISD::SRA)
17006 return ArithmeticShiftRight64(ShiftAmt);
17008 if (VT == MVT::v16i8 || (Subtarget->hasInt256() && VT == MVT::v32i8)) {
17009 unsigned NumElts = VT.getVectorNumElements();
17010 MVT ShiftVT = MVT::getVectorVT(MVT::i16, NumElts / 2);
17012 if (Op.getOpcode() == ISD::SHL) {
17013 // Simple i8 add case
17015 return DAG.getNode(ISD::ADD, dl, VT, R, R);
17017 // Make a large shift.
17018 SDValue SHL = getTargetVShiftByConstNode(X86ISD::VSHLI, dl, ShiftVT,
17020 SHL = DAG.getBitcast(VT, SHL);
17021 // Zero out the rightmost bits.
17022 SmallVector<SDValue, 32> V(
17023 NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));
17024 return DAG.getNode(ISD::AND, dl, VT, SHL,
17025 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17027 if (Op.getOpcode() == ISD::SRL) {
17028 // Make a large shift.
17029 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,
17031 SRL = DAG.getBitcast(VT, SRL);
17032 // Zero out the leftmost bits.
17033 SmallVector<SDValue, 32> V(
17034 NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));
17035 return DAG.getNode(ISD::AND, dl, VT, SRL,
17036 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));
17038 if (Op.getOpcode() == ISD::SRA) {
17039 if (ShiftAmt == 7) {
17040 // R s>> 7 === R s< 0
17041 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
17042 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
17045 // R s>> a === ((R u>> a) ^ m) - m
17046 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
17047 SmallVector<SDValue, 32> V(NumElts,
17048 DAG.getConstant(128 >> ShiftAmt, dl,
17050 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);
17051 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
17052 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
17055 llvm_unreachable("Unknown shift opcode.");
17060 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17061 if (!Subtarget->is64Bit() &&
17062 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
17063 Amt.getOpcode() == ISD::BITCAST &&
17064 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17065 Amt = Amt.getOperand(0);
17066 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17067 VT.getVectorNumElements();
17068 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
17069 uint64_t ShiftAmt = 0;
17070 for (unsigned i = 0; i != Ratio; ++i) {
17071 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
17075 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
17077 // Check remaining shift amounts.
17078 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17079 uint64_t ShAmt = 0;
17080 for (unsigned j = 0; j != Ratio; ++j) {
17081 ConstantSDNode *C =
17082 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
17086 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
17088 if (ShAmt != ShiftAmt)
17092 if (SupportedVectorShiftWithImm(VT, Subtarget, Op.getOpcode()))
17093 return getTargetVShiftByConstNode(X86Opc, dl, VT, R, ShiftAmt, DAG);
17095 if (Op.getOpcode() == ISD::SRA)
17096 return ArithmeticShiftRight64(ShiftAmt);
17102 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
17103 const X86Subtarget* Subtarget) {
17104 MVT VT = Op.getSimpleValueType();
17106 SDValue R = Op.getOperand(0);
17107 SDValue Amt = Op.getOperand(1);
17109 unsigned X86OpcI = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHLI :
17110 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRLI : X86ISD::VSRAI;
17112 unsigned X86OpcV = (Op.getOpcode() == ISD::SHL) ? X86ISD::VSHL :
17113 (Op.getOpcode() == ISD::SRL) ? X86ISD::VSRL : X86ISD::VSRA;
17115 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode())) {
17117 EVT EltVT = VT.getVectorElementType();
17119 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(Amt)) {
17120 // Check if this build_vector node is doing a splat.
17121 // If so, then set BaseShAmt equal to the splat value.
17122 BaseShAmt = BV->getSplatValue();
17123 if (BaseShAmt && BaseShAmt.getOpcode() == ISD::UNDEF)
17124 BaseShAmt = SDValue();
17126 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
17127 Amt = Amt.getOperand(0);
17129 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Amt);
17130 if (SVN && SVN->isSplat()) {
17131 unsigned SplatIdx = (unsigned)SVN->getSplatIndex();
17132 SDValue InVec = Amt.getOperand(0);
17133 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
17134 assert((SplatIdx < InVec.getValueType().getVectorNumElements()) &&
17135 "Unexpected shuffle index found!");
17136 BaseShAmt = InVec.getOperand(SplatIdx);
17137 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
17138 if (ConstantSDNode *C =
17139 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
17140 if (C->getZExtValue() == SplatIdx)
17141 BaseShAmt = InVec.getOperand(1);
17146 // Avoid introducing an extract element from a shuffle.
17147 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,
17148 DAG.getIntPtrConstant(SplatIdx, dl));
17152 if (BaseShAmt.getNode()) {
17153 assert(EltVT.bitsLE(MVT::i64) && "Unexpected element type!");
17154 if (EltVT != MVT::i64 && EltVT.bitsGT(MVT::i32))
17155 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, BaseShAmt);
17156 else if (EltVT.bitsLT(MVT::i32))
17157 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
17159 return getTargetVShiftNode(X86OpcI, dl, VT, R, BaseShAmt, DAG);
17163 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
17164 if (!Subtarget->is64Bit() && VT == MVT::v2i64 &&
17165 Amt.getOpcode() == ISD::BITCAST &&
17166 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
17167 Amt = Amt.getOperand(0);
17168 unsigned Ratio = Amt.getSimpleValueType().getVectorNumElements() /
17169 VT.getVectorNumElements();
17170 std::vector<SDValue> Vals(Ratio);
17171 for (unsigned i = 0; i != Ratio; ++i)
17172 Vals[i] = Amt.getOperand(i);
17173 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
17174 for (unsigned j = 0; j != Ratio; ++j)
17175 if (Vals[j] != Amt.getOperand(i + j))
17179 if (SupportedVectorShiftWithBaseAmnt(VT, Subtarget, Op.getOpcode()))
17180 return DAG.getNode(X86OpcV, dl, VT, R, Op.getOperand(1));
17185 static SDValue LowerShift(SDValue Op, const X86Subtarget* Subtarget,
17186 SelectionDAG &DAG) {
17187 MVT VT = Op.getSimpleValueType();
17189 SDValue R = Op.getOperand(0);
17190 SDValue Amt = Op.getOperand(1);
17192 assert(VT.isVector() && "Custom lowering only for vector shifts!");
17193 assert(Subtarget->hasSSE2() && "Only custom lower when we have SSE2!");
17195 if (SDValue V = LowerScalarImmediateShift(Op, DAG, Subtarget))
17198 if (SDValue V = LowerScalarVariableShift(Op, DAG, Subtarget))
17201 if (SupportedVectorVarShift(VT, Subtarget, Op.getOpcode()))
17204 // 2i64 vector logical shifts can efficiently avoid scalarization - do the
17205 // shifts per-lane and then shuffle the partial results back together.
17206 if (VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) {
17207 // Splat the shift amounts so the scalar shifts above will catch it.
17208 SDValue Amt0 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {0, 0});
17209 SDValue Amt1 = DAG.getVectorShuffle(VT, dl, Amt, Amt, {1, 1});
17210 SDValue R0 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt0);
17211 SDValue R1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Amt1);
17212 return DAG.getVectorShuffle(VT, dl, R0, R1, {0, 3});
17215 // If possible, lower this packed shift into a vector multiply instead of
17216 // expanding it into a sequence of scalar shifts.
17217 // Do this only if the vector shift count is a constant build_vector.
17218 if (Op.getOpcode() == ISD::SHL &&
17219 (VT == MVT::v8i16 || VT == MVT::v4i32 ||
17220 (Subtarget->hasInt256() && VT == MVT::v16i16)) &&
17221 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17222 SmallVector<SDValue, 8> Elts;
17223 EVT SVT = VT.getScalarType();
17224 unsigned SVTBits = SVT.getSizeInBits();
17225 const APInt &One = APInt(SVTBits, 1);
17226 unsigned NumElems = VT.getVectorNumElements();
17228 for (unsigned i=0; i !=NumElems; ++i) {
17229 SDValue Op = Amt->getOperand(i);
17230 if (Op->getOpcode() == ISD::UNDEF) {
17231 Elts.push_back(Op);
17235 ConstantSDNode *ND = cast<ConstantSDNode>(Op);
17236 const APInt &C = APInt(SVTBits, ND->getAPIntValue().getZExtValue());
17237 uint64_t ShAmt = C.getZExtValue();
17238 if (ShAmt >= SVTBits) {
17239 Elts.push_back(DAG.getUNDEF(SVT));
17242 Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));
17244 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);
17245 return DAG.getNode(ISD::MUL, dl, VT, R, BV);
17248 // Lower SHL with variable shift amount.
17249 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
17250 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));
17252 Op = DAG.getNode(ISD::ADD, dl, VT, Op,
17253 DAG.getConstant(0x3f800000U, dl, VT));
17254 Op = DAG.getBitcast(MVT::v4f32, Op);
17255 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
17256 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
17259 // If possible, lower this shift as a sequence of two shifts by
17260 // constant plus a MOVSS/MOVSD instead of scalarizing it.
17262 // (v4i32 (srl A, (build_vector < X, Y, Y, Y>)))
17264 // Could be rewritten as:
17265 // (v4i32 (MOVSS (srl A, <Y,Y,Y,Y>), (srl A, <X,X,X,X>)))
17267 // The advantage is that the two shifts from the example would be
17268 // lowered as X86ISD::VSRLI nodes. This would be cheaper than scalarizing
17269 // the vector shift into four scalar shifts plus four pairs of vector
17271 if ((VT == MVT::v8i16 || VT == MVT::v4i32) &&
17272 ISD::isBuildVectorOfConstantSDNodes(Amt.getNode())) {
17273 unsigned TargetOpcode = X86ISD::MOVSS;
17274 bool CanBeSimplified;
17275 // The splat value for the first packed shift (the 'X' from the example).
17276 SDValue Amt1 = Amt->getOperand(0);
17277 // The splat value for the second packed shift (the 'Y' from the example).
17278 SDValue Amt2 = (VT == MVT::v4i32) ? Amt->getOperand(1) :
17279 Amt->getOperand(2);
17281 // See if it is possible to replace this node with a sequence of
17282 // two shifts followed by a MOVSS/MOVSD
17283 if (VT == MVT::v4i32) {
17284 // Check if it is legal to use a MOVSS.
17285 CanBeSimplified = Amt2 == Amt->getOperand(2) &&
17286 Amt2 == Amt->getOperand(3);
17287 if (!CanBeSimplified) {
17288 // Otherwise, check if we can still simplify this node using a MOVSD.
17289 CanBeSimplified = Amt1 == Amt->getOperand(1) &&
17290 Amt->getOperand(2) == Amt->getOperand(3);
17291 TargetOpcode = X86ISD::MOVSD;
17292 Amt2 = Amt->getOperand(2);
17295 // Do similar checks for the case where the machine value type
17297 CanBeSimplified = Amt1 == Amt->getOperand(1);
17298 for (unsigned i=3; i != 8 && CanBeSimplified; ++i)
17299 CanBeSimplified = Amt2 == Amt->getOperand(i);
17301 if (!CanBeSimplified) {
17302 TargetOpcode = X86ISD::MOVSD;
17303 CanBeSimplified = true;
17304 Amt2 = Amt->getOperand(4);
17305 for (unsigned i=0; i != 4 && CanBeSimplified; ++i)
17306 CanBeSimplified = Amt1 == Amt->getOperand(i);
17307 for (unsigned j=4; j != 8 && CanBeSimplified; ++j)
17308 CanBeSimplified = Amt2 == Amt->getOperand(j);
17312 if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
17313 isa<ConstantSDNode>(Amt2)) {
17314 // Replace this node with two shifts followed by a MOVSS/MOVSD.
17315 EVT CastVT = MVT::v4i32;
17317 DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
17318 SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
17320 DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
17321 SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
17322 if (TargetOpcode == X86ISD::MOVSD)
17323 CastVT = MVT::v2i64;
17324 SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
17325 SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
17326 SDValue Result = getTargetShuffleNode(TargetOpcode, dl, CastVT, BitCast2,
17328 return DAG.getBitcast(VT, Result);
17332 if (VT == MVT::v16i8 || (VT == MVT::v32i8 && Subtarget->hasInt256())) {
17333 MVT ExtVT = MVT::getVectorVT(MVT::i16, VT.getVectorNumElements() / 2);
17334 unsigned ShiftOpcode = Op->getOpcode();
17336 auto SignBitSelect = [&](MVT SelVT, SDValue Sel, SDValue V0, SDValue V1) {
17337 // On SSE41 targets we make use of the fact that VSELECT lowers
17338 // to PBLENDVB which selects bytes based just on the sign bit.
17339 if (Subtarget->hasSSE41()) {
17340 V0 = DAG.getBitcast(VT, V0);
17341 V1 = DAG.getBitcast(VT, V1);
17342 Sel = DAG.getBitcast(VT, Sel);
17343 return DAG.getBitcast(SelVT,
17344 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
17346 // On pre-SSE41 targets we test for the sign bit by comparing to
17347 // zero - a negative value will set all bits of the lanes to true
17348 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
17349 SDValue Z = getZeroVector(SelVT, Subtarget, DAG, dl);
17350 SDValue C = DAG.getNode(X86ISD::PCMPGT, dl, SelVT, Z, Sel);
17351 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
17354 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
17355 // We can safely do this using i16 shifts as we're only interested in
17356 // the 3 lower bits of each byte.
17357 Amt = DAG.getBitcast(ExtVT, Amt);
17358 Amt = DAG.getNode(ISD::SHL, dl, ExtVT, Amt, DAG.getConstant(5, dl, ExtVT));
17359 Amt = DAG.getBitcast(VT, Amt);
17361 if (Op->getOpcode() == ISD::SHL || Op->getOpcode() == ISD::SRL) {
17362 // r = VSELECT(r, shift(r, 4), a);
17364 DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17365 R = SignBitSelect(VT, Amt, M, R);
17368 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17370 // r = VSELECT(r, shift(r, 2), a);
17371 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17372 R = SignBitSelect(VT, Amt, M, R);
17375 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17377 // return VSELECT(r, shift(r, 1), a);
17378 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17379 R = SignBitSelect(VT, Amt, M, R);
17383 if (Op->getOpcode() == ISD::SRA) {
17384 // For SRA we need to unpack each byte to the higher byte of a i16 vector
17385 // so we can correctly sign extend. We don't care what happens to the
17387 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), Amt);
17388 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), Amt);
17389 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, DAG.getUNDEF(VT), R);
17390 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, DAG.getUNDEF(VT), R);
17391 ALo = DAG.getBitcast(ExtVT, ALo);
17392 AHi = DAG.getBitcast(ExtVT, AHi);
17393 RLo = DAG.getBitcast(ExtVT, RLo);
17394 RHi = DAG.getBitcast(ExtVT, RHi);
17396 // r = VSELECT(r, shift(r, 4), a);
17397 SDValue MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17398 DAG.getConstant(4, dl, ExtVT));
17399 SDValue MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17400 DAG.getConstant(4, dl, ExtVT));
17401 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17402 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17405 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17406 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17408 // r = VSELECT(r, shift(r, 2), a);
17409 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17410 DAG.getConstant(2, dl, ExtVT));
17411 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17412 DAG.getConstant(2, dl, ExtVT));
17413 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17414 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17417 ALo = DAG.getNode(ISD::ADD, dl, ExtVT, ALo, ALo);
17418 AHi = DAG.getNode(ISD::ADD, dl, ExtVT, AHi, AHi);
17420 // r = VSELECT(r, shift(r, 1), a);
17421 MLo = DAG.getNode(ShiftOpcode, dl, ExtVT, RLo,
17422 DAG.getConstant(1, dl, ExtVT));
17423 MHi = DAG.getNode(ShiftOpcode, dl, ExtVT, RHi,
17424 DAG.getConstant(1, dl, ExtVT));
17425 RLo = SignBitSelect(ExtVT, ALo, MLo, RLo);
17426 RHi = SignBitSelect(ExtVT, AHi, MHi, RHi);
17428 // Logical shift the result back to the lower byte, leaving a zero upper
17430 // meaning that we can safely pack with PACKUSWB.
17432 DAG.getNode(ISD::SRL, dl, ExtVT, RLo, DAG.getConstant(8, dl, ExtVT));
17434 DAG.getNode(ISD::SRL, dl, ExtVT, RHi, DAG.getConstant(8, dl, ExtVT));
17435 return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);
17439 // It's worth extending once and using the v8i32 shifts for 16-bit types, but
17440 // the extra overheads to get from v16i8 to v8i32 make the existing SSE
17441 // solution better.
17442 if (Subtarget->hasInt256() && VT == MVT::v8i16) {
17443 MVT ExtVT = MVT::v8i32;
17445 Op.getOpcode() == ISD::SRA ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
17446 R = DAG.getNode(ExtOpc, dl, ExtVT, R);
17447 Amt = DAG.getNode(ISD::ANY_EXTEND, dl, ExtVT, Amt);
17448 return DAG.getNode(ISD::TRUNCATE, dl, VT,
17449 DAG.getNode(Op.getOpcode(), dl, ExtVT, R, Amt));
17452 if (Subtarget->hasInt256() && VT == MVT::v16i16) {
17453 MVT ExtVT = MVT::v8i32;
17454 SDValue Z = getZeroVector(VT, Subtarget, DAG, dl);
17455 SDValue ALo = DAG.getNode(X86ISD::UNPCKL, dl, VT, Amt, Z);
17456 SDValue AHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, Amt, Z);
17457 SDValue RLo = DAG.getNode(X86ISD::UNPCKL, dl, VT, R, R);
17458 SDValue RHi = DAG.getNode(X86ISD::UNPCKH, dl, VT, R, R);
17459 ALo = DAG.getBitcast(ExtVT, ALo);
17460 AHi = DAG.getBitcast(ExtVT, AHi);
17461 RLo = DAG.getBitcast(ExtVT, RLo);
17462 RHi = DAG.getBitcast(ExtVT, RHi);
17463 SDValue Lo = DAG.getNode(Op.getOpcode(), dl, ExtVT, RLo, ALo);
17464 SDValue Hi = DAG.getNode(Op.getOpcode(), dl, ExtVT, RHi, AHi);
17465 Lo = DAG.getNode(ISD::SRL, dl, ExtVT, Lo, DAG.getConstant(16, dl, ExtVT));
17466 Hi = DAG.getNode(ISD::SRL, dl, ExtVT, Hi, DAG.getConstant(16, dl, ExtVT));
17467 return DAG.getNode(X86ISD::PACKUS, dl, VT, Lo, Hi);
17470 if (VT == MVT::v8i16) {
17471 unsigned ShiftOpcode = Op->getOpcode();
17473 auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
17474 // On SSE41 targets we make use of the fact that VSELECT lowers
17475 // to PBLENDVB which selects bytes based just on the sign bit.
17476 if (Subtarget->hasSSE41()) {
17477 MVT ExtVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() * 2);
17478 V0 = DAG.getBitcast(ExtVT, V0);
17479 V1 = DAG.getBitcast(ExtVT, V1);
17480 Sel = DAG.getBitcast(ExtVT, Sel);
17481 return DAG.getBitcast(
17482 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
17484 // On pre-SSE41 targets we splat the sign bit - a negative value will
17485 // set all bits of the lanes to true and VSELECT uses that in
17486 // its OR(AND(V0,C),AND(V1,~C)) lowering.
17488 DAG.getNode(ISD::SRA, dl, VT, Sel, DAG.getConstant(15, dl, VT));
17489 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
17492 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
17493 if (Subtarget->hasSSE41()) {
17494 // On SSE41 targets we need to replicate the shift mask in both
17495 // bytes for PBLENDVB.
17498 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(4, dl, VT)),
17499 DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT)));
17501 Amt = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(12, dl, VT));
17504 // r = VSELECT(r, shift(r, 8), a);
17505 SDValue M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(8, dl, VT));
17506 R = SignBitSelect(Amt, M, R);
17509 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17511 // r = VSELECT(r, shift(r, 4), a);
17512 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(4, dl, VT));
17513 R = SignBitSelect(Amt, M, R);
17516 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17518 // r = VSELECT(r, shift(r, 2), a);
17519 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(2, dl, VT));
17520 R = SignBitSelect(Amt, M, R);
17523 Amt = DAG.getNode(ISD::ADD, dl, VT, Amt, Amt);
17525 // return VSELECT(r, shift(r, 1), a);
17526 M = DAG.getNode(ShiftOpcode, dl, VT, R, DAG.getConstant(1, dl, VT));
17527 R = SignBitSelect(Amt, M, R);
17531 // Decompose 256-bit shifts into smaller 128-bit shifts.
17532 if (VT.is256BitVector()) {
17533 unsigned NumElems = VT.getVectorNumElements();
17534 MVT EltVT = VT.getVectorElementType();
17535 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
17537 // Extract the two vectors
17538 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
17539 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
17541 // Recreate the shift amount vectors
17542 SDValue Amt1, Amt2;
17543 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
17544 // Constant shift amount
17545 SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
17546 ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
17547 ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
17549 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
17550 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
17552 // Variable shift amount
17553 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
17554 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
17557 // Issue new vector shifts for the smaller types
17558 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
17559 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
17561 // Concatenate the result back
17562 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
17568 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
17569 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
17570 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
17571 // looks for this combo and may remove the "setcc" instruction if the "setcc"
17572 // has only one use.
17573 SDNode *N = Op.getNode();
17574 SDValue LHS = N->getOperand(0);
17575 SDValue RHS = N->getOperand(1);
17576 unsigned BaseOp = 0;
17579 switch (Op.getOpcode()) {
17580 default: llvm_unreachable("Unknown ovf instruction!");
17582 // A subtract of one will be selected as a INC. Note that INC doesn't
17583 // set CF, so we can't do this for UADDO.
17584 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17586 BaseOp = X86ISD::INC;
17587 Cond = X86::COND_O;
17590 BaseOp = X86ISD::ADD;
17591 Cond = X86::COND_O;
17594 BaseOp = X86ISD::ADD;
17595 Cond = X86::COND_B;
17598 // A subtract of one will be selected as a DEC. Note that DEC doesn't
17599 // set CF, so we can't do this for USUBO.
17600 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
17602 BaseOp = X86ISD::DEC;
17603 Cond = X86::COND_O;
17606 BaseOp = X86ISD::SUB;
17607 Cond = X86::COND_O;
17610 BaseOp = X86ISD::SUB;
17611 Cond = X86::COND_B;
17614 BaseOp = N->getValueType(0) == MVT::i8 ? X86ISD::SMUL8 : X86ISD::SMUL;
17615 Cond = X86::COND_O;
17617 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
17618 if (N->getValueType(0) == MVT::i8) {
17619 BaseOp = X86ISD::UMUL8;
17620 Cond = X86::COND_O;
17623 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
17625 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
17628 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
17629 DAG.getConstant(X86::COND_O, DL, MVT::i32),
17630 SDValue(Sum.getNode(), 2));
17632 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17636 // Also sets EFLAGS.
17637 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
17638 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
17641 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
17642 DAG.getConstant(Cond, DL, MVT::i32),
17643 SDValue(Sum.getNode(), 1));
17645 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
17648 /// Returns true if the operand type is exactly twice the native width, and
17649 /// the corresponding cmpxchg8b or cmpxchg16b instruction is available.
17650 /// Used to know whether to use cmpxchg8/16b when expanding atomic operations
17651 /// (otherwise we leave them alone to become __sync_fetch_and_... calls).
17652 bool X86TargetLowering::needsCmpXchgNb(const Type *MemType) const {
17653 unsigned OpWidth = MemType->getPrimitiveSizeInBits();
17656 return !Subtarget->is64Bit(); // FIXME this should be Subtarget.hasCmpxchg8b
17657 else if (OpWidth == 128)
17658 return Subtarget->hasCmpxchg16b();
17663 bool X86TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
17664 return needsCmpXchgNb(SI->getValueOperand()->getType());
17667 // Note: this turns large loads into lock cmpxchg8b/16b.
17668 // FIXME: On 32 bits x86, fild/movq might be faster than lock cmpxchg8b.
17669 bool X86TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
17670 auto PTy = cast<PointerType>(LI->getPointerOperand()->getType());
17671 return needsCmpXchgNb(PTy->getElementType());
17674 TargetLoweringBase::AtomicRMWExpansionKind
17675 X86TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
17676 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17677 const Type *MemType = AI->getType();
17679 // If the operand is too big, we must see if cmpxchg8/16b is available
17680 // and default to library calls otherwise.
17681 if (MemType->getPrimitiveSizeInBits() > NativeWidth) {
17682 return needsCmpXchgNb(MemType) ? AtomicRMWExpansionKind::CmpXChg
17683 : AtomicRMWExpansionKind::None;
17686 AtomicRMWInst::BinOp Op = AI->getOperation();
17689 llvm_unreachable("Unknown atomic operation");
17690 case AtomicRMWInst::Xchg:
17691 case AtomicRMWInst::Add:
17692 case AtomicRMWInst::Sub:
17693 // It's better to use xadd, xsub or xchg for these in all cases.
17694 return AtomicRMWExpansionKind::None;
17695 case AtomicRMWInst::Or:
17696 case AtomicRMWInst::And:
17697 case AtomicRMWInst::Xor:
17698 // If the atomicrmw's result isn't actually used, we can just add a "lock"
17699 // prefix to a normal instruction for these operations.
17700 return !AI->use_empty() ? AtomicRMWExpansionKind::CmpXChg
17701 : AtomicRMWExpansionKind::None;
17702 case AtomicRMWInst::Nand:
17703 case AtomicRMWInst::Max:
17704 case AtomicRMWInst::Min:
17705 case AtomicRMWInst::UMax:
17706 case AtomicRMWInst::UMin:
17707 // These always require a non-trivial set of data operations on x86. We must
17708 // use a cmpxchg loop.
17709 return AtomicRMWExpansionKind::CmpXChg;
17713 static bool hasMFENCE(const X86Subtarget& Subtarget) {
17714 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
17715 // no-sse2). There isn't any reason to disable it if the target processor
17717 return Subtarget.hasSSE2() || Subtarget.is64Bit();
17721 X86TargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
17722 unsigned NativeWidth = Subtarget->is64Bit() ? 64 : 32;
17723 const Type *MemType = AI->getType();
17724 // Accesses larger than the native width are turned into cmpxchg/libcalls, so
17725 // there is no benefit in turning such RMWs into loads, and it is actually
17726 // harmful as it introduces a mfence.
17727 if (MemType->getPrimitiveSizeInBits() > NativeWidth)
17730 auto Builder = IRBuilder<>(AI);
17731 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
17732 auto SynchScope = AI->getSynchScope();
17733 // We must restrict the ordering to avoid generating loads with Release or
17734 // ReleaseAcquire orderings.
17735 auto Order = AtomicCmpXchgInst::getStrongestFailureOrdering(AI->getOrdering());
17736 auto Ptr = AI->getPointerOperand();
17738 // Before the load we need a fence. Here is an example lifted from
17739 // http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf showing why a fence
17742 // x.store(1, relaxed);
17743 // r1 = y.fetch_add(0, release);
17745 // y.fetch_add(42, acquire);
17746 // r2 = x.load(relaxed);
17747 // r1 = r2 = 0 is impossible, but becomes possible if the idempotent rmw is
17748 // lowered to just a load without a fence. A mfence flushes the store buffer,
17749 // making the optimization clearly correct.
17750 // FIXME: it is required if isAtLeastRelease(Order) but it is not clear
17751 // otherwise, we might be able to be more agressive on relaxed idempotent
17752 // rmw. In practice, they do not look useful, so we don't try to be
17753 // especially clever.
17754 if (SynchScope == SingleThread)
17755 // FIXME: we could just insert an X86ISD::MEMBARRIER here, except we are at
17756 // the IR level, so we must wrap it in an intrinsic.
17759 if (!hasMFENCE(*Subtarget))
17760 // FIXME: it might make sense to use a locked operation here but on a
17761 // different cache-line to prevent cache-line bouncing. In practice it
17762 // is probably a small win, and x86 processors without mfence are rare
17763 // enough that we do not bother.
17767 llvm::Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_mfence);
17768 Builder.CreateCall(MFence, {});
17770 // Finally we can emit the atomic load.
17771 LoadInst *Loaded = Builder.CreateAlignedLoad(Ptr,
17772 AI->getType()->getPrimitiveSizeInBits());
17773 Loaded->setAtomic(Order, SynchScope);
17774 AI->replaceAllUsesWith(Loaded);
17775 AI->eraseFromParent();
17779 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
17780 SelectionDAG &DAG) {
17782 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
17783 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
17784 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
17785 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
17787 // The only fence that needs an instruction is a sequentially-consistent
17788 // cross-thread fence.
17789 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
17790 if (hasMFENCE(*Subtarget))
17791 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
17793 SDValue Chain = Op.getOperand(0);
17794 SDValue Zero = DAG.getConstant(0, dl, MVT::i32);
17796 DAG.getRegister(X86::ESP, MVT::i32), // Base
17797 DAG.getTargetConstant(1, dl, MVT::i8), // Scale
17798 DAG.getRegister(0, MVT::i32), // Index
17799 DAG.getTargetConstant(0, dl, MVT::i32), // Disp
17800 DAG.getRegister(0, MVT::i32), // Segment.
17804 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
17805 return SDValue(Res, 0);
17808 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
17809 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
17812 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
17813 SelectionDAG &DAG) {
17814 MVT T = Op.getSimpleValueType();
17818 switch(T.SimpleTy) {
17819 default: llvm_unreachable("Invalid value type!");
17820 case MVT::i8: Reg = X86::AL; size = 1; break;
17821 case MVT::i16: Reg = X86::AX; size = 2; break;
17822 case MVT::i32: Reg = X86::EAX; size = 4; break;
17824 assert(Subtarget->is64Bit() && "Node not type legal!");
17825 Reg = X86::RAX; size = 8;
17828 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
17829 Op.getOperand(2), SDValue());
17830 SDValue Ops[] = { cpIn.getValue(0),
17833 DAG.getTargetConstant(size, DL, MVT::i8),
17834 cpIn.getValue(1) };
17835 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
17836 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
17837 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
17841 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
17842 SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,
17843 MVT::i32, cpOut.getValue(2));
17844 SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),
17845 DAG.getConstant(X86::COND_E, DL, MVT::i8),
17848 DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);
17849 DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);
17850 DAG.ReplaceAllUsesOfValueWith(Op.getValue(2), EFLAGS.getValue(1));
17854 static SDValue LowerBITCAST(SDValue Op, const X86Subtarget *Subtarget,
17855 SelectionDAG &DAG) {
17856 MVT SrcVT = Op.getOperand(0).getSimpleValueType();
17857 MVT DstVT = Op.getSimpleValueType();
17859 if (SrcVT == MVT::v2i32 || SrcVT == MVT::v4i16 || SrcVT == MVT::v8i8) {
17860 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
17861 if (DstVT != MVT::f64)
17862 // This conversion needs to be expanded.
17865 SDValue InVec = Op->getOperand(0);
17867 unsigned NumElts = SrcVT.getVectorNumElements();
17868 EVT SVT = SrcVT.getVectorElementType();
17870 // Widen the vector in input in the case of MVT::v2i32.
17871 // Example: from MVT::v2i32 to MVT::v4i32.
17872 SmallVector<SDValue, 16> Elts;
17873 for (unsigned i = 0, e = NumElts; i != e; ++i)
17874 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,
17875 DAG.getIntPtrConstant(i, dl)));
17877 // Explicitly mark the extra elements as Undef.
17878 Elts.append(NumElts, DAG.getUNDEF(SVT));
17880 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
17881 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);
17882 SDValue ToV2F64 = DAG.getBitcast(MVT::v2f64, BV);
17883 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,
17884 DAG.getIntPtrConstant(0, dl));
17887 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
17888 Subtarget->hasMMX() && "Unexpected custom BITCAST");
17889 assert((DstVT == MVT::i64 ||
17890 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
17891 "Unexpected custom BITCAST");
17892 // i64 <=> MMX conversions are Legal.
17893 if (SrcVT==MVT::i64 && DstVT.isVector())
17895 if (DstVT==MVT::i64 && SrcVT.isVector())
17897 // MMX <=> MMX conversions are Legal.
17898 if (SrcVT.isVector() && DstVT.isVector())
17900 // All other conversions need to be expanded.
17904 /// Compute the horizontal sum of bytes in V for the elements of VT.
17906 /// Requires V to be a byte vector and VT to be an integer vector type with
17907 /// wider elements than V's type. The width of the elements of VT determines
17908 /// how many bytes of V are summed horizontally to produce each element of the
17910 static SDValue LowerHorizontalByteSum(SDValue V, MVT VT,
17911 const X86Subtarget *Subtarget,
17912 SelectionDAG &DAG) {
17914 MVT ByteVecVT = V.getSimpleValueType();
17915 MVT EltVT = VT.getVectorElementType();
17916 int NumElts = VT.getVectorNumElements();
17917 assert(ByteVecVT.getVectorElementType() == MVT::i8 &&
17918 "Expected value to have byte element type.");
17919 assert(EltVT != MVT::i8 &&
17920 "Horizontal byte sum only makes sense for wider elements!");
17921 unsigned VecSize = VT.getSizeInBits();
17922 assert(ByteVecVT.getSizeInBits() == VecSize && "Cannot change vector size!");
17924 // PSADBW instruction horizontally add all bytes and leave the result in i64
17925 // chunks, thus directly computes the pop count for v2i64 and v4i64.
17926 if (EltVT == MVT::i64) {
17927 SDValue Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17928 V = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT, V, Zeros);
17929 return DAG.getBitcast(VT, V);
17932 if (EltVT == MVT::i32) {
17933 // We unpack the low half and high half into i32s interleaved with zeros so
17934 // that we can use PSADBW to horizontally sum them. The most useful part of
17935 // this is that it lines up the results of two PSADBW instructions to be
17936 // two v2i64 vectors which concatenated are the 4 population counts. We can
17937 // then use PACKUSWB to shrink and concatenate them into a v4i32 again.
17938 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, DL);
17939 SDValue Low = DAG.getNode(X86ISD::UNPCKL, DL, VT, V, Zeros);
17940 SDValue High = DAG.getNode(X86ISD::UNPCKH, DL, VT, V, Zeros);
17942 // Do the horizontal sums into two v2i64s.
17943 Zeros = getZeroVector(ByteVecVT, Subtarget, DAG, DL);
17944 Low = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17945 DAG.getBitcast(ByteVecVT, Low), Zeros);
17946 High = DAG.getNode(X86ISD::PSADBW, DL, ByteVecVT,
17947 DAG.getBitcast(ByteVecVT, High), Zeros);
17949 // Merge them together.
17950 MVT ShortVecVT = MVT::getVectorVT(MVT::i16, VecSize / 16);
17951 V = DAG.getNode(X86ISD::PACKUS, DL, ByteVecVT,
17952 DAG.getBitcast(ShortVecVT, Low),
17953 DAG.getBitcast(ShortVecVT, High));
17955 return DAG.getBitcast(VT, V);
17958 // The only element type left is i16.
17959 assert(EltVT == MVT::i16 && "Unknown how to handle type");
17961 // To obtain pop count for each i16 element starting from the pop count for
17962 // i8 elements, shift the i16s left by 8, sum as i8s, and then shift as i16s
17963 // right by 8. It is important to shift as i16s as i8 vector shift isn't
17964 // directly supported.
17965 SmallVector<SDValue, 16> Shifters(NumElts, DAG.getConstant(8, DL, EltVT));
17966 SDValue Shifter = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters);
17967 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17968 V = DAG.getNode(ISD::ADD, DL, ByteVecVT, DAG.getBitcast(ByteVecVT, Shl),
17969 DAG.getBitcast(ByteVecVT, V));
17970 return DAG.getNode(ISD::SRL, DL, VT, DAG.getBitcast(VT, V), Shifter);
17973 static SDValue LowerVectorCTPOPInRegLUT(SDValue Op, SDLoc DL,
17974 const X86Subtarget *Subtarget,
17975 SelectionDAG &DAG) {
17976 MVT VT = Op.getSimpleValueType();
17977 MVT EltVT = VT.getVectorElementType();
17978 unsigned VecSize = VT.getSizeInBits();
17980 // Implement a lookup table in register by using an algorithm based on:
17981 // http://wm.ite.pl/articles/sse-popcount.html
17983 // The general idea is that every lower byte nibble in the input vector is an
17984 // index into a in-register pre-computed pop count table. We then split up the
17985 // input vector in two new ones: (1) a vector with only the shifted-right
17986 // higher nibbles for each byte and (2) a vector with the lower nibbles (and
17987 // masked out higher ones) for each byte. PSHUB is used separately with both
17988 // to index the in-register table. Next, both are added and the result is a
17989 // i8 vector where each element contains the pop count for input byte.
17991 // To obtain the pop count for elements != i8, we follow up with the same
17992 // approach and use additional tricks as described below.
17994 const int LUT[16] = {/* 0 */ 0, /* 1 */ 1, /* 2 */ 1, /* 3 */ 2,
17995 /* 4 */ 1, /* 5 */ 2, /* 6 */ 2, /* 7 */ 3,
17996 /* 8 */ 1, /* 9 */ 2, /* a */ 2, /* b */ 3,
17997 /* c */ 2, /* d */ 3, /* e */ 3, /* f */ 4};
17999 int NumByteElts = VecSize / 8;
18000 MVT ByteVecVT = MVT::getVectorVT(MVT::i8, NumByteElts);
18001 SDValue In = DAG.getBitcast(ByteVecVT, Op);
18002 SmallVector<SDValue, 16> LUTVec;
18003 for (int i = 0; i < NumByteElts; ++i)
18004 LUTVec.push_back(DAG.getConstant(LUT[i % 16], DL, MVT::i8));
18005 SDValue InRegLUT = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, LUTVec);
18006 SmallVector<SDValue, 16> Mask0F(NumByteElts,
18007 DAG.getConstant(0x0F, DL, MVT::i8));
18008 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Mask0F);
18011 SmallVector<SDValue, 16> Four(NumByteElts, DAG.getConstant(4, DL, MVT::i8));
18012 SDValue FourV = DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVecVT, Four);
18013 SDValue HighNibbles = DAG.getNode(ISD::SRL, DL, ByteVecVT, In, FourV);
18016 SDValue LowNibbles = DAG.getNode(ISD::AND, DL, ByteVecVT, In, M0F);
18018 // The input vector is used as the shuffle mask that index elements into the
18019 // LUT. After counting low and high nibbles, add the vector to obtain the
18020 // final pop count per i8 element.
18021 SDValue HighPopCnt =
18022 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, HighNibbles);
18023 SDValue LowPopCnt =
18024 DAG.getNode(X86ISD::PSHUFB, DL, ByteVecVT, InRegLUT, LowNibbles);
18025 SDValue PopCnt = DAG.getNode(ISD::ADD, DL, ByteVecVT, HighPopCnt, LowPopCnt);
18027 if (EltVT == MVT::i8)
18030 return LowerHorizontalByteSum(PopCnt, VT, Subtarget, DAG);
18033 static SDValue LowerVectorCTPOPBitmath(SDValue Op, SDLoc DL,
18034 const X86Subtarget *Subtarget,
18035 SelectionDAG &DAG) {
18036 MVT VT = Op.getSimpleValueType();
18037 assert(VT.is128BitVector() &&
18038 "Only 128-bit vector bitmath lowering supported.");
18040 int VecSize = VT.getSizeInBits();
18041 MVT EltVT = VT.getVectorElementType();
18042 int Len = EltVT.getSizeInBits();
18044 // This is the vectorized version of the "best" algorithm from
18045 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
18046 // with a minor tweak to use a series of adds + shifts instead of vector
18047 // multiplications. Implemented for all integer vector types. We only use
18048 // this when we don't have SSSE3 which allows a LUT-based lowering that is
18049 // much faster, even faster than using native popcnt instructions.
18051 auto GetShift = [&](unsigned OpCode, SDValue V, int Shifter) {
18052 MVT VT = V.getSimpleValueType();
18053 SmallVector<SDValue, 32> Shifters(
18054 VT.getVectorNumElements(),
18055 DAG.getConstant(Shifter, DL, VT.getVectorElementType()));
18056 return DAG.getNode(OpCode, DL, VT, V,
18057 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Shifters));
18059 auto GetMask = [&](SDValue V, APInt Mask) {
18060 MVT VT = V.getSimpleValueType();
18061 SmallVector<SDValue, 32> Masks(
18062 VT.getVectorNumElements(),
18063 DAG.getConstant(Mask, DL, VT.getVectorElementType()));
18064 return DAG.getNode(ISD::AND, DL, VT, V,
18065 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Masks));
18068 // We don't want to incur the implicit masks required to SRL vNi8 vectors on
18069 // x86, so set the SRL type to have elements at least i16 wide. This is
18070 // correct because all of our SRLs are followed immediately by a mask anyways
18071 // that handles any bits that sneak into the high bits of the byte elements.
18072 MVT SrlVT = Len > 8 ? VT : MVT::getVectorVT(MVT::i16, VecSize / 16);
18076 // v = v - ((v >> 1) & 0x55555555...)
18078 DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 1));
18079 SDValue And = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x55)));
18080 V = DAG.getNode(ISD::SUB, DL, VT, V, And);
18082 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
18083 SDValue AndLHS = GetMask(V, APInt::getSplat(Len, APInt(8, 0x33)));
18084 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 2));
18085 SDValue AndRHS = GetMask(Srl, APInt::getSplat(Len, APInt(8, 0x33)));
18086 V = DAG.getNode(ISD::ADD, DL, VT, AndLHS, AndRHS);
18088 // v = (v + (v >> 4)) & 0x0F0F0F0F...
18089 Srl = DAG.getBitcast(VT, GetShift(ISD::SRL, DAG.getBitcast(SrlVT, V), 4));
18090 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, V, Srl);
18091 V = GetMask(Add, APInt::getSplat(Len, APInt(8, 0x0F)));
18093 // At this point, V contains the byte-wise population count, and we are
18094 // merely doing a horizontal sum if necessary to get the wider element
18096 if (EltVT == MVT::i8)
18099 return LowerHorizontalByteSum(
18100 DAG.getBitcast(MVT::getVectorVT(MVT::i8, VecSize / 8), V), VT, Subtarget,
18104 static SDValue LowerVectorCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18105 SelectionDAG &DAG) {
18106 MVT VT = Op.getSimpleValueType();
18107 // FIXME: Need to add AVX-512 support here!
18108 assert((VT.is256BitVector() || VT.is128BitVector()) &&
18109 "Unknown CTPOP type to handle");
18110 SDLoc DL(Op.getNode());
18111 SDValue Op0 = Op.getOperand(0);
18113 if (!Subtarget->hasSSSE3()) {
18114 // We can't use the fast LUT approach, so fall back on vectorized bitmath.
18115 assert(VT.is128BitVector() && "Only 128-bit vectors supported in SSE!");
18116 return LowerVectorCTPOPBitmath(Op0, DL, Subtarget, DAG);
18119 if (VT.is256BitVector() && !Subtarget->hasInt256()) {
18120 unsigned NumElems = VT.getVectorNumElements();
18122 // Extract each 128-bit vector, compute pop count and concat the result.
18123 SDValue LHS = Extract128BitVector(Op0, 0, DAG, DL);
18124 SDValue RHS = Extract128BitVector(Op0, NumElems/2, DAG, DL);
18126 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT,
18127 LowerVectorCTPOPInRegLUT(LHS, DL, Subtarget, DAG),
18128 LowerVectorCTPOPInRegLUT(RHS, DL, Subtarget, DAG));
18131 return LowerVectorCTPOPInRegLUT(Op0, DL, Subtarget, DAG);
18134 static SDValue LowerCTPOP(SDValue Op, const X86Subtarget *Subtarget,
18135 SelectionDAG &DAG) {
18136 assert(Op.getValueType().isVector() &&
18137 "We only do custom lowering for vector population count.");
18138 return LowerVectorCTPOP(Op, Subtarget, DAG);
18141 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
18142 SDNode *Node = Op.getNode();
18144 EVT T = Node->getValueType(0);
18145 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
18146 DAG.getConstant(0, dl, T), Node->getOperand(2));
18147 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
18148 cast<AtomicSDNode>(Node)->getMemoryVT(),
18149 Node->getOperand(0),
18150 Node->getOperand(1), negOp,
18151 cast<AtomicSDNode>(Node)->getMemOperand(),
18152 cast<AtomicSDNode>(Node)->getOrdering(),
18153 cast<AtomicSDNode>(Node)->getSynchScope());
18156 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
18157 SDNode *Node = Op.getNode();
18159 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
18161 // Convert seq_cst store -> xchg
18162 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
18163 // FIXME: On 32-bit, store -> fist or movq would be more efficient
18164 // (The only way to get a 16-byte store is cmpxchg16b)
18165 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
18166 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
18167 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
18168 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
18169 cast<AtomicSDNode>(Node)->getMemoryVT(),
18170 Node->getOperand(0),
18171 Node->getOperand(1), Node->getOperand(2),
18172 cast<AtomicSDNode>(Node)->getMemOperand(),
18173 cast<AtomicSDNode>(Node)->getOrdering(),
18174 cast<AtomicSDNode>(Node)->getSynchScope());
18175 return Swap.getValue(1);
18177 // Other atomic stores have a simple pattern.
18181 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
18182 EVT VT = Op.getNode()->getSimpleValueType(0);
18184 // Let legalize expand this if it isn't a legal type yet.
18185 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
18188 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
18191 bool ExtraOp = false;
18192 switch (Op.getOpcode()) {
18193 default: llvm_unreachable("Invalid code");
18194 case ISD::ADDC: Opc = X86ISD::ADD; break;
18195 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
18196 case ISD::SUBC: Opc = X86ISD::SUB; break;
18197 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
18201 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18203 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
18204 Op.getOperand(1), Op.getOperand(2));
18207 static SDValue LowerFSINCOS(SDValue Op, const X86Subtarget *Subtarget,
18208 SelectionDAG &DAG) {
18209 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
18211 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
18212 // which returns the values as { float, float } (in XMM0) or
18213 // { double, double } (which is returned in XMM0, XMM1).
18215 SDValue Arg = Op.getOperand(0);
18216 EVT ArgVT = Arg.getValueType();
18217 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
18219 TargetLowering::ArgListTy Args;
18220 TargetLowering::ArgListEntry Entry;
18224 Entry.isSExt = false;
18225 Entry.isZExt = false;
18226 Args.push_back(Entry);
18228 bool isF64 = ArgVT == MVT::f64;
18229 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
18230 // the small struct {f32, f32} is returned in (eax, edx). For f64,
18231 // the results are returned via SRet in memory.
18232 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
18233 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18234 SDValue Callee = DAG.getExternalSymbol(LibcallName, TLI.getPointerTy());
18236 Type *RetTy = isF64
18237 ? (Type*)StructType::get(ArgTy, ArgTy, nullptr)
18238 : (Type*)VectorType::get(ArgTy, 4);
18240 TargetLowering::CallLoweringInfo CLI(DAG);
18241 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
18242 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
18244 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
18247 // Returned in xmm0 and xmm1.
18248 return CallResult.first;
18250 // Returned in bits 0:31 and 32:64 xmm0.
18251 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18252 CallResult.first, DAG.getIntPtrConstant(0, dl));
18253 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
18254 CallResult.first, DAG.getIntPtrConstant(1, dl));
18255 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
18256 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
18259 static SDValue LowerMSCATTER(SDValue Op, const X86Subtarget *Subtarget,
18260 SelectionDAG &DAG) {
18261 assert(Subtarget->hasAVX512() &&
18262 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18264 MaskedScatterSDNode *N = cast<MaskedScatterSDNode>(Op.getNode());
18265 EVT VT = N->getValue().getValueType();
18266 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported scatter op");
18269 // X86 scatter kills mask register, so its type should be added to
18270 // the list of return values
18271 if (N->getNumValues() == 1) {
18272 SDValue Index = N->getIndex();
18273 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18274 !Index.getValueType().is512BitVector())
18275 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18277 SDVTList VTs = DAG.getVTList(N->getMask().getValueType(), MVT::Other);
18278 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18279 N->getOperand(3), Index };
18281 SDValue NewScatter = DAG.getMaskedScatter(VTs, VT, dl, Ops, N->getMemOperand());
18282 DAG.ReplaceAllUsesWith(Op, SDValue(NewScatter.getNode(), 1));
18283 return SDValue(NewScatter.getNode(), 0);
18288 static SDValue LowerMGATHER(SDValue Op, const X86Subtarget *Subtarget,
18289 SelectionDAG &DAG) {
18290 assert(Subtarget->hasAVX512() &&
18291 "MGATHER/MSCATTER are supported on AVX-512 arch only");
18293 MaskedGatherSDNode *N = cast<MaskedGatherSDNode>(Op.getNode());
18294 EVT VT = Op.getValueType();
18295 assert(VT.getScalarSizeInBits() >= 32 && "Unsupported gather op");
18298 SDValue Index = N->getIndex();
18299 if (!Subtarget->hasVLX() && !VT.is512BitVector() &&
18300 !Index.getValueType().is512BitVector()) {
18301 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
18302 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
18303 N->getOperand(3), Index };
18304 DAG.UpdateNodeOperands(N, Ops);
18309 SDValue X86TargetLowering::LowerGC_TRANSITION_START(SDValue Op,
18310 SelectionDAG &DAG) const {
18311 // TODO: Eventually, the lowering of these nodes should be informed by or
18312 // deferred to the GC strategy for the function in which they appear. For
18313 // now, however, they must be lowered to something. Since they are logically
18314 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18315 // require special handling for these nodes), lower them as literal NOOPs for
18317 SmallVector<SDValue, 2> Ops;
18319 Ops.push_back(Op.getOperand(0));
18320 if (Op->getGluedNode())
18321 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18324 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18325 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18330 SDValue X86TargetLowering::LowerGC_TRANSITION_END(SDValue Op,
18331 SelectionDAG &DAG) const {
18332 // TODO: Eventually, the lowering of these nodes should be informed by or
18333 // deferred to the GC strategy for the function in which they appear. For
18334 // now, however, they must be lowered to something. Since they are logically
18335 // no-ops in the case of a null GC strategy (or a GC strategy which does not
18336 // require special handling for these nodes), lower them as literal NOOPs for
18338 SmallVector<SDValue, 2> Ops;
18340 Ops.push_back(Op.getOperand(0));
18341 if (Op->getGluedNode())
18342 Ops.push_back(Op->getOperand(Op->getNumOperands() - 1));
18345 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
18346 SDValue NOOP(DAG.getMachineNode(X86::NOOP, SDLoc(Op), VTs, Ops), 0);
18351 /// LowerOperation - Provide custom lowering hooks for some operations.
18353 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
18354 switch (Op.getOpcode()) {
18355 default: llvm_unreachable("Should not custom lower this!");
18356 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
18357 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
18358 return LowerCMP_SWAP(Op, Subtarget, DAG);
18359 case ISD::CTPOP: return LowerCTPOP(Op, Subtarget, DAG);
18360 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
18361 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
18362 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
18363 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, Subtarget, DAG);
18364 case ISD::VECTOR_SHUFFLE: return lowerVectorShuffle(Op, Subtarget, DAG);
18365 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
18366 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
18367 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
18368 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
18369 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
18370 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
18371 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
18372 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
18373 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
18374 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
18375 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
18376 case ISD::SHL_PARTS:
18377 case ISD::SRA_PARTS:
18378 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
18379 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
18380 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
18381 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
18382 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, Subtarget, DAG);
18383 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, Subtarget, DAG);
18384 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, Subtarget, DAG);
18385 case ISD::SIGN_EXTEND_VECTOR_INREG:
18386 return LowerSIGN_EXTEND_VECTOR_INREG(Op, Subtarget, DAG);
18387 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
18388 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
18389 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
18390 case ISD::LOAD: return LowerExtendedLoad(Op, Subtarget, DAG);
18392 case ISD::FNEG: return LowerFABSorFNEG(Op, DAG);
18393 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
18394 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
18395 case ISD::SETCC: return LowerSETCC(Op, DAG);
18396 case ISD::SELECT: return LowerSELECT(Op, DAG);
18397 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
18398 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
18399 case ISD::VASTART: return LowerVASTART(Op, DAG);
18400 case ISD::VAARG: return LowerVAARG(Op, DAG);
18401 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
18402 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, Subtarget, DAG);
18403 case ISD::INTRINSIC_VOID:
18404 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, Subtarget, DAG);
18405 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
18406 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
18407 case ISD::FRAME_TO_ARGS_OFFSET:
18408 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
18409 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
18410 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
18411 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
18412 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
18413 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
18414 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
18415 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
18416 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
18417 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
18418 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
18419 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
18420 case ISD::UMUL_LOHI:
18421 case ISD::SMUL_LOHI: return LowerMUL_LOHI(Op, Subtarget, DAG);
18424 case ISD::SHL: return LowerShift(Op, Subtarget, DAG);
18430 case ISD::UMULO: return LowerXALUO(Op, DAG);
18431 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
18432 case ISD::BITCAST: return LowerBITCAST(Op, Subtarget, DAG);
18436 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
18437 case ISD::ADD: return LowerADD(Op, DAG);
18438 case ISD::SUB: return LowerSUB(Op, DAG);
18439 case ISD::FSINCOS: return LowerFSINCOS(Op, Subtarget, DAG);
18440 case ISD::MGATHER: return LowerMGATHER(Op, Subtarget, DAG);
18441 case ISD::MSCATTER: return LowerMSCATTER(Op, Subtarget, DAG);
18442 case ISD::GC_TRANSITION_START:
18443 return LowerGC_TRANSITION_START(Op, DAG);
18444 case ISD::GC_TRANSITION_END: return LowerGC_TRANSITION_END(Op, DAG);
18448 /// ReplaceNodeResults - Replace a node with an illegal result type
18449 /// with a new node built out of custom code.
18450 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
18451 SmallVectorImpl<SDValue>&Results,
18452 SelectionDAG &DAG) const {
18454 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
18455 switch (N->getOpcode()) {
18457 llvm_unreachable("Do not know how to custom type legalize this operation!");
18458 // We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
18459 case X86ISD::FMINC:
18461 case X86ISD::FMAXC:
18462 case X86ISD::FMAX: {
18463 EVT VT = N->getValueType(0);
18464 if (VT != MVT::v2f32)
18465 llvm_unreachable("Unexpected type (!= v2f32) on FMIN/FMAX.");
18466 SDValue UNDEF = DAG.getUNDEF(VT);
18467 SDValue LHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18468 N->getOperand(0), UNDEF);
18469 SDValue RHS = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
18470 N->getOperand(1), UNDEF);
18471 Results.push_back(DAG.getNode(N->getOpcode(), dl, MVT::v4f32, LHS, RHS));
18474 case ISD::SIGN_EXTEND_INREG:
18479 // We don't want to expand or promote these.
18486 case ISD::UDIVREM: {
18487 SDValue V = LowerWin64_i128OP(SDValue(N,0), DAG);
18488 Results.push_back(V);
18491 case ISD::FP_TO_SINT:
18492 // FP_TO_INT*_IN_MEM is not legal for f16 inputs. Do not convert
18493 // (FP_TO_SINT (load f16)) to FP_TO_INT*.
18494 if (N->getOperand(0).getValueType() == MVT::f16)
18497 case ISD::FP_TO_UINT: {
18498 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
18500 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
18503 std::pair<SDValue,SDValue> Vals =
18504 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
18505 SDValue FIST = Vals.first, StackSlot = Vals.second;
18506 if (FIST.getNode()) {
18507 EVT VT = N->getValueType(0);
18508 // Return a load from the stack slot.
18509 if (StackSlot.getNode())
18510 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
18511 MachinePointerInfo(),
18512 false, false, false, 0));
18514 Results.push_back(FIST);
18518 case ISD::UINT_TO_FP: {
18519 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18520 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
18521 N->getValueType(0) != MVT::v2f32)
18523 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
18525 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,
18527 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
18528 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
18529 DAG.getBitcast(MVT::v2i64, VBias));
18530 Or = DAG.getBitcast(MVT::v2f64, Or);
18531 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
18532 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
18535 case ISD::FP_ROUND: {
18536 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
18538 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
18539 Results.push_back(V);
18542 case ISD::FP_EXTEND: {
18543 // Right now, only MVT::v2f32 has OperationAction for FP_EXTEND.
18544 // No other ValueType for FP_EXTEND should reach this point.
18545 assert(N->getValueType(0) == MVT::v2f32 &&
18546 "Do not know how to legalize this Node");
18549 case ISD::INTRINSIC_W_CHAIN: {
18550 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
18552 default : llvm_unreachable("Do not know how to custom type "
18553 "legalize this intrinsic operation!");
18554 case Intrinsic::x86_rdtsc:
18555 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18557 case Intrinsic::x86_rdtscp:
18558 return getReadTimeStampCounter(N, dl, X86ISD::RDTSCP_DAG, DAG, Subtarget,
18560 case Intrinsic::x86_rdpmc:
18561 return getReadPerformanceCounter(N, dl, DAG, Subtarget, Results);
18564 case ISD::READCYCLECOUNTER: {
18565 return getReadTimeStampCounter(N, dl, X86ISD::RDTSC_DAG, DAG, Subtarget,
18568 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
18569 EVT T = N->getValueType(0);
18570 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
18571 bool Regs64bit = T == MVT::i128;
18572 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
18573 SDValue cpInL, cpInH;
18574 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18575 DAG.getConstant(0, dl, HalfT));
18576 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
18577 DAG.getConstant(1, dl, HalfT));
18578 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
18579 Regs64bit ? X86::RAX : X86::EAX,
18581 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
18582 Regs64bit ? X86::RDX : X86::EDX,
18583 cpInH, cpInL.getValue(1));
18584 SDValue swapInL, swapInH;
18585 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18586 DAG.getConstant(0, dl, HalfT));
18587 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
18588 DAG.getConstant(1, dl, HalfT));
18589 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
18590 Regs64bit ? X86::RBX : X86::EBX,
18591 swapInL, cpInH.getValue(1));
18592 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
18593 Regs64bit ? X86::RCX : X86::ECX,
18594 swapInH, swapInL.getValue(1));
18595 SDValue Ops[] = { swapInH.getValue(0),
18597 swapInH.getValue(1) };
18598 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
18599 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
18600 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
18601 X86ISD::LCMPXCHG8_DAG;
18602 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, Ops, T, MMO);
18603 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
18604 Regs64bit ? X86::RAX : X86::EAX,
18605 HalfT, Result.getValue(1));
18606 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
18607 Regs64bit ? X86::RDX : X86::EDX,
18608 HalfT, cpOutL.getValue(2));
18609 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
18611 SDValue EFLAGS = DAG.getCopyFromReg(cpOutH.getValue(1), dl, X86::EFLAGS,
18612 MVT::i32, cpOutH.getValue(2));
18614 DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
18615 DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);
18616 Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));
18618 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));
18619 Results.push_back(Success);
18620 Results.push_back(EFLAGS.getValue(1));
18623 case ISD::ATOMIC_SWAP:
18624 case ISD::ATOMIC_LOAD_ADD:
18625 case ISD::ATOMIC_LOAD_SUB:
18626 case ISD::ATOMIC_LOAD_AND:
18627 case ISD::ATOMIC_LOAD_OR:
18628 case ISD::ATOMIC_LOAD_XOR:
18629 case ISD::ATOMIC_LOAD_NAND:
18630 case ISD::ATOMIC_LOAD_MIN:
18631 case ISD::ATOMIC_LOAD_MAX:
18632 case ISD::ATOMIC_LOAD_UMIN:
18633 case ISD::ATOMIC_LOAD_UMAX:
18634 case ISD::ATOMIC_LOAD: {
18635 // Delegate to generic TypeLegalization. Situations we can really handle
18636 // should have already been dealt with by AtomicExpandPass.cpp.
18639 case ISD::BITCAST: {
18640 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
18641 EVT DstVT = N->getValueType(0);
18642 EVT SrcVT = N->getOperand(0)->getValueType(0);
18644 if (SrcVT != MVT::f64 ||
18645 (DstVT != MVT::v2i32 && DstVT != MVT::v4i16 && DstVT != MVT::v8i8))
18648 unsigned NumElts = DstVT.getVectorNumElements();
18649 EVT SVT = DstVT.getVectorElementType();
18650 EVT WiderVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumElts * 2);
18651 SDValue Expanded = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
18652 MVT::v2f64, N->getOperand(0));
18653 SDValue ToVecInt = DAG.getBitcast(WiderVT, Expanded);
18655 if (ExperimentalVectorWideningLegalization) {
18656 // If we are legalizing vectors by widening, we already have the desired
18657 // legal vector type, just return it.
18658 Results.push_back(ToVecInt);
18662 SmallVector<SDValue, 8> Elts;
18663 for (unsigned i = 0, e = NumElts; i != e; ++i)
18664 Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,
18665 ToVecInt, DAG.getIntPtrConstant(i, dl)));
18667 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));
18672 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
18673 switch ((X86ISD::NodeType)Opcode) {
18674 case X86ISD::FIRST_NUMBER: break;
18675 case X86ISD::BSF: return "X86ISD::BSF";
18676 case X86ISD::BSR: return "X86ISD::BSR";
18677 case X86ISD::SHLD: return "X86ISD::SHLD";
18678 case X86ISD::SHRD: return "X86ISD::SHRD";
18679 case X86ISD::FAND: return "X86ISD::FAND";
18680 case X86ISD::FANDN: return "X86ISD::FANDN";
18681 case X86ISD::FOR: return "X86ISD::FOR";
18682 case X86ISD::FXOR: return "X86ISD::FXOR";
18683 case X86ISD::FILD: return "X86ISD::FILD";
18684 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
18685 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
18686 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
18687 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
18688 case X86ISD::FLD: return "X86ISD::FLD";
18689 case X86ISD::FST: return "X86ISD::FST";
18690 case X86ISD::CALL: return "X86ISD::CALL";
18691 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
18692 case X86ISD::RDTSCP_DAG: return "X86ISD::RDTSCP_DAG";
18693 case X86ISD::RDPMC_DAG: return "X86ISD::RDPMC_DAG";
18694 case X86ISD::BT: return "X86ISD::BT";
18695 case X86ISD::CMP: return "X86ISD::CMP";
18696 case X86ISD::COMI: return "X86ISD::COMI";
18697 case X86ISD::UCOMI: return "X86ISD::UCOMI";
18698 case X86ISD::CMPM: return "X86ISD::CMPM";
18699 case X86ISD::CMPMU: return "X86ISD::CMPMU";
18700 case X86ISD::CMPM_RND: return "X86ISD::CMPM_RND";
18701 case X86ISD::SETCC: return "X86ISD::SETCC";
18702 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
18703 case X86ISD::FSETCC: return "X86ISD::FSETCC";
18704 case X86ISD::FGETSIGNx86: return "X86ISD::FGETSIGNx86";
18705 case X86ISD::CMOV: return "X86ISD::CMOV";
18706 case X86ISD::BRCOND: return "X86ISD::BRCOND";
18707 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
18708 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
18709 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
18710 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
18711 case X86ISD::Wrapper: return "X86ISD::Wrapper";
18712 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
18713 case X86ISD::MOVDQ2Q: return "X86ISD::MOVDQ2Q";
18714 case X86ISD::MMX_MOVD2W: return "X86ISD::MMX_MOVD2W";
18715 case X86ISD::MMX_MOVW2D: return "X86ISD::MMX_MOVW2D";
18716 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
18717 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
18718 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
18719 case X86ISD::PINSRB: return "X86ISD::PINSRB";
18720 case X86ISD::PINSRW: return "X86ISD::PINSRW";
18721 case X86ISD::MMX_PINSRW: return "X86ISD::MMX_PINSRW";
18722 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
18723 case X86ISD::ANDNP: return "X86ISD::ANDNP";
18724 case X86ISD::PSIGN: return "X86ISD::PSIGN";
18725 case X86ISD::BLENDI: return "X86ISD::BLENDI";
18726 case X86ISD::SHRUNKBLEND: return "X86ISD::SHRUNKBLEND";
18727 case X86ISD::ADDUS: return "X86ISD::ADDUS";
18728 case X86ISD::SUBUS: return "X86ISD::SUBUS";
18729 case X86ISD::HADD: return "X86ISD::HADD";
18730 case X86ISD::HSUB: return "X86ISD::HSUB";
18731 case X86ISD::FHADD: return "X86ISD::FHADD";
18732 case X86ISD::FHSUB: return "X86ISD::FHSUB";
18733 case X86ISD::ABS: return "X86ISD::ABS";
18734 case X86ISD::FMAX: return "X86ISD::FMAX";
18735 case X86ISD::FMAX_RND: return "X86ISD::FMAX_RND";
18736 case X86ISD::FMIN: return "X86ISD::FMIN";
18737 case X86ISD::FMIN_RND: return "X86ISD::FMIN_RND";
18738 case X86ISD::FMAXC: return "X86ISD::FMAXC";
18739 case X86ISD::FMINC: return "X86ISD::FMINC";
18740 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
18741 case X86ISD::FRCP: return "X86ISD::FRCP";
18742 case X86ISD::EXTRQI: return "X86ISD::EXTRQI";
18743 case X86ISD::INSERTQI: return "X86ISD::INSERTQI";
18744 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
18745 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
18746 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
18747 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
18748 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
18749 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
18750 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
18751 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
18752 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
18753 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
18754 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
18755 case X86ISD::LCMPXCHG16_DAG: return "X86ISD::LCMPXCHG16_DAG";
18756 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
18757 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
18758 case X86ISD::VZEXT: return "X86ISD::VZEXT";
18759 case X86ISD::VSEXT: return "X86ISD::VSEXT";
18760 case X86ISD::VTRUNC: return "X86ISD::VTRUNC";
18761 case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";
18762 case X86ISD::VINSERT: return "X86ISD::VINSERT";
18763 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
18764 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
18765 case X86ISD::CVTDQ2PD: return "X86ISD::CVTDQ2PD";
18766 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
18767 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
18768 case X86ISD::VSHL: return "X86ISD::VSHL";
18769 case X86ISD::VSRL: return "X86ISD::VSRL";
18770 case X86ISD::VSRA: return "X86ISD::VSRA";
18771 case X86ISD::VSHLI: return "X86ISD::VSHLI";
18772 case X86ISD::VSRLI: return "X86ISD::VSRLI";
18773 case X86ISD::VSRAI: return "X86ISD::VSRAI";
18774 case X86ISD::CMPP: return "X86ISD::CMPP";
18775 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
18776 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
18777 case X86ISD::PCMPEQM: return "X86ISD::PCMPEQM";
18778 case X86ISD::PCMPGTM: return "X86ISD::PCMPGTM";
18779 case X86ISD::ADD: return "X86ISD::ADD";
18780 case X86ISD::SUB: return "X86ISD::SUB";
18781 case X86ISD::ADC: return "X86ISD::ADC";
18782 case X86ISD::SBB: return "X86ISD::SBB";
18783 case X86ISD::SMUL: return "X86ISD::SMUL";
18784 case X86ISD::UMUL: return "X86ISD::UMUL";
18785 case X86ISD::SMUL8: return "X86ISD::SMUL8";
18786 case X86ISD::UMUL8: return "X86ISD::UMUL8";
18787 case X86ISD::SDIVREM8_SEXT_HREG: return "X86ISD::SDIVREM8_SEXT_HREG";
18788 case X86ISD::UDIVREM8_ZEXT_HREG: return "X86ISD::UDIVREM8_ZEXT_HREG";
18789 case X86ISD::INC: return "X86ISD::INC";
18790 case X86ISD::DEC: return "X86ISD::DEC";
18791 case X86ISD::OR: return "X86ISD::OR";
18792 case X86ISD::XOR: return "X86ISD::XOR";
18793 case X86ISD::AND: return "X86ISD::AND";
18794 case X86ISD::BEXTR: return "X86ISD::BEXTR";
18795 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
18796 case X86ISD::PTEST: return "X86ISD::PTEST";
18797 case X86ISD::TESTP: return "X86ISD::TESTP";
18798 case X86ISD::TESTM: return "X86ISD::TESTM";
18799 case X86ISD::TESTNM: return "X86ISD::TESTNM";
18800 case X86ISD::KORTEST: return "X86ISD::KORTEST";
18801 case X86ISD::PACKSS: return "X86ISD::PACKSS";
18802 case X86ISD::PACKUS: return "X86ISD::PACKUS";
18803 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
18804 case X86ISD::VALIGN: return "X86ISD::VALIGN";
18805 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
18806 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
18807 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
18808 case X86ISD::SHUFP: return "X86ISD::SHUFP";
18809 case X86ISD::SHUF128: return "X86ISD::SHUF128";
18810 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
18811 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
18812 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
18813 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
18814 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
18815 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
18816 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
18817 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
18818 case X86ISD::MOVSD: return "X86ISD::MOVSD";
18819 case X86ISD::MOVSS: return "X86ISD::MOVSS";
18820 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
18821 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
18822 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
18823 case X86ISD::SUBV_BROADCAST: return "X86ISD::SUBV_BROADCAST";
18824 case X86ISD::VEXTRACT: return "X86ISD::VEXTRACT";
18825 case X86ISD::VPERMILPV: return "X86ISD::VPERMILPV";
18826 case X86ISD::VPERMILPI: return "X86ISD::VPERMILPI";
18827 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
18828 case X86ISD::VPERMV: return "X86ISD::VPERMV";
18829 case X86ISD::VPERMV3: return "X86ISD::VPERMV3";
18830 case X86ISD::VPERMIV3: return "X86ISD::VPERMIV3";
18831 case X86ISD::VPERMI: return "X86ISD::VPERMI";
18832 case X86ISD::VFIXUPIMM: return "X86ISD::VFIXUPIMM";
18833 case X86ISD::VRANGE: return "X86ISD::VRANGE";
18834 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
18835 case X86ISD::PMULDQ: return "X86ISD::PMULDQ";
18836 case X86ISD::PSADBW: return "X86ISD::PSADBW";
18837 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
18838 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
18839 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
18840 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
18841 case X86ISD::MFENCE: return "X86ISD::MFENCE";
18842 case X86ISD::SFENCE: return "X86ISD::SFENCE";
18843 case X86ISD::LFENCE: return "X86ISD::LFENCE";
18844 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
18845 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
18846 case X86ISD::SAHF: return "X86ISD::SAHF";
18847 case X86ISD::RDRAND: return "X86ISD::RDRAND";
18848 case X86ISD::RDSEED: return "X86ISD::RDSEED";
18849 case X86ISD::FMADD: return "X86ISD::FMADD";
18850 case X86ISD::FMSUB: return "X86ISD::FMSUB";
18851 case X86ISD::FNMADD: return "X86ISD::FNMADD";
18852 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
18853 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
18854 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
18855 case X86ISD::FMADD_RND: return "X86ISD::FMADD_RND";
18856 case X86ISD::FNMADD_RND: return "X86ISD::FNMADD_RND";
18857 case X86ISD::FMSUB_RND: return "X86ISD::FMSUB_RND";
18858 case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
18859 case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
18860 case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
18861 case X86ISD::RNDSCALE: return "X86ISD::RNDSCALE";
18862 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
18863 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
18864 case X86ISD::XTEST: return "X86ISD::XTEST";
18865 case X86ISD::COMPRESS: return "X86ISD::COMPRESS";
18866 case X86ISD::EXPAND: return "X86ISD::EXPAND";
18867 case X86ISD::SELECT: return "X86ISD::SELECT";
18868 case X86ISD::ADDSUB: return "X86ISD::ADDSUB";
18869 case X86ISD::RCP28: return "X86ISD::RCP28";
18870 case X86ISD::EXP2: return "X86ISD::EXP2";
18871 case X86ISD::RSQRT28: return "X86ISD::RSQRT28";
18872 case X86ISD::FADD_RND: return "X86ISD::FADD_RND";
18873 case X86ISD::FSUB_RND: return "X86ISD::FSUB_RND";
18874 case X86ISD::FMUL_RND: return "X86ISD::FMUL_RND";
18875 case X86ISD::FDIV_RND: return "X86ISD::FDIV_RND";
18876 case X86ISD::FSQRT_RND: return "X86ISD::FSQRT_RND";
18877 case X86ISD::FGETEXP_RND: return "X86ISD::FGETEXP_RND";
18878 case X86ISD::SCALEF: return "X86ISD::SCALEF";
18879 case X86ISD::ADDS: return "X86ISD::ADDS";
18880 case X86ISD::SUBS: return "X86ISD::SUBS";
18881 case X86ISD::AVG: return "X86ISD::AVG";
18882 case X86ISD::MULHRS: return "X86ISD::MULHRS";
18883 case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
18884 case X86ISD::UINT_TO_FP_RND: return "X86ISD::UINT_TO_FP_RND";
18889 // isLegalAddressingMode - Return true if the addressing mode represented
18890 // by AM is legal for this target, for a load/store of the specified type.
18891 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
18893 unsigned AS) const {
18894 // X86 supports extremely general addressing modes.
18895 CodeModel::Model M = getTargetMachine().getCodeModel();
18896 Reloc::Model R = getTargetMachine().getRelocationModel();
18898 // X86 allows a sign-extended 32-bit immediate field as a displacement.
18899 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != nullptr))
18904 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
18906 // If a reference to this global requires an extra load, we can't fold it.
18907 if (isGlobalStubReference(GVFlags))
18910 // If BaseGV requires a register for the PIC base, we cannot also have a
18911 // BaseReg specified.
18912 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
18915 // If lower 4G is not available, then we must use rip-relative addressing.
18916 if ((M != CodeModel::Small || R != Reloc::Static) &&
18917 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
18921 switch (AM.Scale) {
18927 // These scales always work.
18932 // These scales are formed with basereg+scalereg. Only accept if there is
18937 default: // Other stuff never works.
18944 bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
18945 unsigned Bits = Ty->getScalarSizeInBits();
18947 // 8-bit shifts are always expensive, but versions with a scalar amount aren't
18948 // particularly cheaper than those without.
18952 // On AVX2 there are new vpsllv[dq] instructions (and other shifts), that make
18953 // variable shifts just as cheap as scalar ones.
18954 if (Subtarget->hasInt256() && (Bits == 32 || Bits == 64))
18957 // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
18958 // fully general vector.
18962 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
18963 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18965 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
18966 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
18967 return NumBits1 > NumBits2;
18970 bool X86TargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
18971 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
18974 if (!isTypeLegal(EVT::getEVT(Ty1)))
18977 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
18979 // Assuming the caller doesn't have a zeroext or signext return parameter,
18980 // truncation all the way down to i1 is valid.
18984 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
18985 return isInt<32>(Imm);
18988 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
18989 // Can also use sub to handle negated immediates.
18990 return isInt<32>(Imm);
18993 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
18994 if (!VT1.isInteger() || !VT2.isInteger())
18996 unsigned NumBits1 = VT1.getSizeInBits();
18997 unsigned NumBits2 = VT2.getSizeInBits();
18998 return NumBits1 > NumBits2;
19001 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
19002 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19003 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
19006 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
19007 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
19008 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
19011 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
19012 EVT VT1 = Val.getValueType();
19013 if (isZExtFree(VT1, VT2))
19016 if (Val.getOpcode() != ISD::LOAD)
19019 if (!VT1.isSimple() || !VT1.isInteger() ||
19020 !VT2.isSimple() || !VT2.isInteger())
19023 switch (VT1.getSimpleVT().SimpleTy) {
19028 // X86 has 8, 16, and 32-bit zero-extending loads.
19035 bool X86TargetLowering::isVectorLoadExtDesirable(SDValue) const { return true; }
19038 X86TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
19039 if (!(Subtarget->hasFMA() || Subtarget->hasFMA4() || Subtarget->hasAVX512()))
19042 VT = VT.getScalarType();
19044 if (!VT.isSimple())
19047 switch (VT.getSimpleVT().SimpleTy) {
19058 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
19059 // i16 instructions are longer (0x66 prefix) and potentially slower.
19060 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
19063 /// isShuffleMaskLegal - Targets can use this to indicate that they only
19064 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
19065 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
19066 /// are assumed to be legal.
19068 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
19070 if (!VT.isSimple())
19073 // Not for i1 vectors
19074 if (VT.getScalarType() == MVT::i1)
19077 // Very little shuffling can be done for 64-bit vectors right now.
19078 if (VT.getSizeInBits() == 64)
19081 // We only care that the types being shuffled are legal. The lowering can
19082 // handle any possible shuffle mask that results.
19083 return isTypeLegal(VT.getSimpleVT());
19087 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
19089 // Just delegate to the generic legality, clear masks aren't special.
19090 return isShuffleMaskLegal(Mask, VT);
19093 //===----------------------------------------------------------------------===//
19094 // X86 Scheduler Hooks
19095 //===----------------------------------------------------------------------===//
19097 /// Utility function to emit xbegin specifying the start of an RTM region.
19098 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
19099 const TargetInstrInfo *TII) {
19100 DebugLoc DL = MI->getDebugLoc();
19102 const BasicBlock *BB = MBB->getBasicBlock();
19103 MachineFunction::iterator I = MBB;
19106 // For the v = xbegin(), we generate
19117 MachineBasicBlock *thisMBB = MBB;
19118 MachineFunction *MF = MBB->getParent();
19119 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
19120 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
19121 MF->insert(I, mainMBB);
19122 MF->insert(I, sinkMBB);
19124 // Transfer the remainder of BB and its successor edges to sinkMBB.
19125 sinkMBB->splice(sinkMBB->begin(), MBB,
19126 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19127 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
19131 // # fallthrough to mainMBB
19132 // # abortion to sinkMBB
19133 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
19134 thisMBB->addSuccessor(mainMBB);
19135 thisMBB->addSuccessor(sinkMBB);
19139 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
19140 mainMBB->addSuccessor(sinkMBB);
19143 // EAX is live into the sinkMBB
19144 sinkMBB->addLiveIn(X86::EAX);
19145 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
19146 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19149 MI->eraseFromParent();
19153 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
19154 // or XMM0_V32I8 in AVX all of this code can be replaced with that
19155 // in the .td file.
19156 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
19157 const TargetInstrInfo *TII) {
19159 switch (MI->getOpcode()) {
19160 default: llvm_unreachable("illegal opcode!");
19161 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
19162 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
19163 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
19164 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
19165 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
19166 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
19167 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
19168 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
19171 DebugLoc dl = MI->getDebugLoc();
19172 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19174 unsigned NumArgs = MI->getNumOperands();
19175 for (unsigned i = 1; i < NumArgs; ++i) {
19176 MachineOperand &Op = MI->getOperand(i);
19177 if (!(Op.isReg() && Op.isImplicit()))
19178 MIB.addOperand(Op);
19180 if (MI->hasOneMemOperand())
19181 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19183 BuildMI(*BB, MI, dl,
19184 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19185 .addReg(X86::XMM0);
19187 MI->eraseFromParent();
19191 // FIXME: Custom handling because TableGen doesn't support multiple implicit
19192 // defs in an instruction pattern
19193 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
19194 const TargetInstrInfo *TII) {
19196 switch (MI->getOpcode()) {
19197 default: llvm_unreachable("illegal opcode!");
19198 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
19199 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
19200 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
19201 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
19202 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
19203 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
19204 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
19205 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
19208 DebugLoc dl = MI->getDebugLoc();
19209 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
19211 unsigned NumArgs = MI->getNumOperands(); // remove the results
19212 for (unsigned i = 1; i < NumArgs; ++i) {
19213 MachineOperand &Op = MI->getOperand(i);
19214 if (!(Op.isReg() && Op.isImplicit()))
19215 MIB.addOperand(Op);
19217 if (MI->hasOneMemOperand())
19218 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
19220 BuildMI(*BB, MI, dl,
19221 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
19224 MI->eraseFromParent();
19228 static MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
19229 const X86Subtarget *Subtarget) {
19230 DebugLoc dl = MI->getDebugLoc();
19231 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19232 // Address into RAX/EAX, other two args into ECX, EDX.
19233 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19234 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
19235 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
19236 for (int i = 0; i < X86::AddrNumOperands; ++i)
19237 MIB.addOperand(MI->getOperand(i));
19239 unsigned ValOps = X86::AddrNumOperands;
19240 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
19241 .addReg(MI->getOperand(ValOps).getReg());
19242 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
19243 .addReg(MI->getOperand(ValOps+1).getReg());
19245 // The instruction doesn't actually take any operands though.
19246 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
19248 MI->eraseFromParent(); // The pseudo is gone now.
19252 MachineBasicBlock *
19253 X86TargetLowering::EmitVAARG64WithCustomInserter(MachineInstr *MI,
19254 MachineBasicBlock *MBB) const {
19255 // Emit va_arg instruction on X86-64.
19257 // Operands to this pseudo-instruction:
19258 // 0 ) Output : destination address (reg)
19259 // 1-5) Input : va_list address (addr, i64mem)
19260 // 6 ) ArgSize : Size (in bytes) of vararg type
19261 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
19262 // 8 ) Align : Alignment of type
19263 // 9 ) EFLAGS (implicit-def)
19265 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
19266 static_assert(X86::AddrNumOperands == 5,
19267 "VAARG_64 assumes 5 address operands");
19269 unsigned DestReg = MI->getOperand(0).getReg();
19270 MachineOperand &Base = MI->getOperand(1);
19271 MachineOperand &Scale = MI->getOperand(2);
19272 MachineOperand &Index = MI->getOperand(3);
19273 MachineOperand &Disp = MI->getOperand(4);
19274 MachineOperand &Segment = MI->getOperand(5);
19275 unsigned ArgSize = MI->getOperand(6).getImm();
19276 unsigned ArgMode = MI->getOperand(7).getImm();
19277 unsigned Align = MI->getOperand(8).getImm();
19279 // Memory Reference
19280 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
19281 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
19282 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
19284 // Machine Information
19285 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19286 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
19287 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
19288 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
19289 DebugLoc DL = MI->getDebugLoc();
19291 // struct va_list {
19294 // i64 overflow_area (address)
19295 // i64 reg_save_area (address)
19297 // sizeof(va_list) = 24
19298 // alignment(va_list) = 8
19300 unsigned TotalNumIntRegs = 6;
19301 unsigned TotalNumXMMRegs = 8;
19302 bool UseGPOffset = (ArgMode == 1);
19303 bool UseFPOffset = (ArgMode == 2);
19304 unsigned MaxOffset = TotalNumIntRegs * 8 +
19305 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
19307 /* Align ArgSize to a multiple of 8 */
19308 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
19309 bool NeedsAlign = (Align > 8);
19311 MachineBasicBlock *thisMBB = MBB;
19312 MachineBasicBlock *overflowMBB;
19313 MachineBasicBlock *offsetMBB;
19314 MachineBasicBlock *endMBB;
19316 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
19317 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
19318 unsigned OffsetReg = 0;
19320 if (!UseGPOffset && !UseFPOffset) {
19321 // If we only pull from the overflow region, we don't create a branch.
19322 // We don't need to alter control flow.
19323 OffsetDestReg = 0; // unused
19324 OverflowDestReg = DestReg;
19326 offsetMBB = nullptr;
19327 overflowMBB = thisMBB;
19330 // First emit code to check if gp_offset (or fp_offset) is below the bound.
19331 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
19332 // If not, pull from overflow_area. (branch to overflowMBB)
19337 // offsetMBB overflowMBB
19342 // Registers for the PHI in endMBB
19343 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
19344 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
19346 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19347 MachineFunction *MF = MBB->getParent();
19348 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19349 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19350 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19352 MachineFunction::iterator MBBIter = MBB;
19355 // Insert the new basic blocks
19356 MF->insert(MBBIter, offsetMBB);
19357 MF->insert(MBBIter, overflowMBB);
19358 MF->insert(MBBIter, endMBB);
19360 // Transfer the remainder of MBB and its successor edges to endMBB.
19361 endMBB->splice(endMBB->begin(), thisMBB,
19362 std::next(MachineBasicBlock::iterator(MI)), thisMBB->end());
19363 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
19365 // Make offsetMBB and overflowMBB successors of thisMBB
19366 thisMBB->addSuccessor(offsetMBB);
19367 thisMBB->addSuccessor(overflowMBB);
19369 // endMBB is a successor of both offsetMBB and overflowMBB
19370 offsetMBB->addSuccessor(endMBB);
19371 overflowMBB->addSuccessor(endMBB);
19373 // Load the offset value into a register
19374 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19375 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
19379 .addDisp(Disp, UseFPOffset ? 4 : 0)
19380 .addOperand(Segment)
19381 .setMemRefs(MMOBegin, MMOEnd);
19383 // Check if there is enough room left to pull this argument.
19384 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
19386 .addImm(MaxOffset + 8 - ArgSizeA8);
19388 // Branch to "overflowMBB" if offset >= max
19389 // Fall through to "offsetMBB" otherwise
19390 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
19391 .addMBB(overflowMBB);
19394 // In offsetMBB, emit code to use the reg_save_area.
19396 assert(OffsetReg != 0);
19398 // Read the reg_save_area address.
19399 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
19400 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
19405 .addOperand(Segment)
19406 .setMemRefs(MMOBegin, MMOEnd);
19408 // Zero-extend the offset
19409 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
19410 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
19413 .addImm(X86::sub_32bit);
19415 // Add the offset to the reg_save_area to get the final address.
19416 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
19417 .addReg(OffsetReg64)
19418 .addReg(RegSaveReg);
19420 // Compute the offset for the next argument
19421 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
19422 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
19424 .addImm(UseFPOffset ? 16 : 8);
19426 // Store it back into the va_list.
19427 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
19431 .addDisp(Disp, UseFPOffset ? 4 : 0)
19432 .addOperand(Segment)
19433 .addReg(NextOffsetReg)
19434 .setMemRefs(MMOBegin, MMOEnd);
19437 BuildMI(offsetMBB, DL, TII->get(X86::JMP_1))
19442 // Emit code to use overflow area
19445 // Load the overflow_area address into a register.
19446 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
19447 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
19452 .addOperand(Segment)
19453 .setMemRefs(MMOBegin, MMOEnd);
19455 // If we need to align it, do so. Otherwise, just copy the address
19456 // to OverflowDestReg.
19458 // Align the overflow address
19459 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
19460 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
19462 // aligned_addr = (addr + (align-1)) & ~(align-1)
19463 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
19464 .addReg(OverflowAddrReg)
19467 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
19469 .addImm(~(uint64_t)(Align-1));
19471 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
19472 .addReg(OverflowAddrReg);
19475 // Compute the next overflow address after this argument.
19476 // (the overflow address should be kept 8-byte aligned)
19477 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
19478 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
19479 .addReg(OverflowDestReg)
19480 .addImm(ArgSizeA8);
19482 // Store the new overflow address.
19483 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
19488 .addOperand(Segment)
19489 .addReg(NextAddrReg)
19490 .setMemRefs(MMOBegin, MMOEnd);
19492 // If we branched, emit the PHI to the front of endMBB.
19494 BuildMI(*endMBB, endMBB->begin(), DL,
19495 TII->get(X86::PHI), DestReg)
19496 .addReg(OffsetDestReg).addMBB(offsetMBB)
19497 .addReg(OverflowDestReg).addMBB(overflowMBB);
19500 // Erase the pseudo instruction
19501 MI->eraseFromParent();
19506 MachineBasicBlock *
19507 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
19509 MachineBasicBlock *MBB) const {
19510 // Emit code to save XMM registers to the stack. The ABI says that the
19511 // number of registers to save is given in %al, so it's theoretically
19512 // possible to do an indirect jump trick to avoid saving all of them,
19513 // however this code takes a simpler approach and just executes all
19514 // of the stores if %al is non-zero. It's less code, and it's probably
19515 // easier on the hardware branch predictor, and stores aren't all that
19516 // expensive anyway.
19518 // Create the new basic blocks. One block contains all the XMM stores,
19519 // and one block is the final destination regardless of whether any
19520 // stores were performed.
19521 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
19522 MachineFunction *F = MBB->getParent();
19523 MachineFunction::iterator MBBIter = MBB;
19525 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
19526 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
19527 F->insert(MBBIter, XMMSaveMBB);
19528 F->insert(MBBIter, EndMBB);
19530 // Transfer the remainder of MBB and its successor edges to EndMBB.
19531 EndMBB->splice(EndMBB->begin(), MBB,
19532 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
19533 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
19535 // The original block will now fall through to the XMM save block.
19536 MBB->addSuccessor(XMMSaveMBB);
19537 // The XMMSaveMBB will fall through to the end block.
19538 XMMSaveMBB->addSuccessor(EndMBB);
19540 // Now add the instructions.
19541 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19542 DebugLoc DL = MI->getDebugLoc();
19544 unsigned CountReg = MI->getOperand(0).getReg();
19545 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
19546 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
19548 if (!Subtarget->isTargetWin64()) {
19549 // If %al is 0, branch around the XMM save block.
19550 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
19551 BuildMI(MBB, DL, TII->get(X86::JE_1)).addMBB(EndMBB);
19552 MBB->addSuccessor(EndMBB);
19555 // Make sure the last operand is EFLAGS, which gets clobbered by the branch
19556 // that was just emitted, but clearly shouldn't be "saved".
19557 assert((MI->getNumOperands() <= 3 ||
19558 !MI->getOperand(MI->getNumOperands() - 1).isReg() ||
19559 MI->getOperand(MI->getNumOperands() - 1).getReg() == X86::EFLAGS)
19560 && "Expected last argument to be EFLAGS");
19561 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
19562 // In the XMM save block, save all the XMM argument registers.
19563 for (int i = 3, e = MI->getNumOperands() - 1; i != e; ++i) {
19564 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
19565 MachineMemOperand *MMO =
19566 F->getMachineMemOperand(
19567 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
19568 MachineMemOperand::MOStore,
19569 /*Size=*/16, /*Align=*/16);
19570 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
19571 .addFrameIndex(RegSaveFrameIndex)
19572 .addImm(/*Scale=*/1)
19573 .addReg(/*IndexReg=*/0)
19574 .addImm(/*Disp=*/Offset)
19575 .addReg(/*Segment=*/0)
19576 .addReg(MI->getOperand(i).getReg())
19577 .addMemOperand(MMO);
19580 MI->eraseFromParent(); // The pseudo instruction is gone now.
19585 // The EFLAGS operand of SelectItr might be missing a kill marker
19586 // because there were multiple uses of EFLAGS, and ISel didn't know
19587 // which to mark. Figure out whether SelectItr should have had a
19588 // kill marker, and set it if it should. Returns the correct kill
19590 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
19591 MachineBasicBlock* BB,
19592 const TargetRegisterInfo* TRI) {
19593 // Scan forward through BB for a use/def of EFLAGS.
19594 MachineBasicBlock::iterator miI(std::next(SelectItr));
19595 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
19596 const MachineInstr& mi = *miI;
19597 if (mi.readsRegister(X86::EFLAGS))
19599 if (mi.definesRegister(X86::EFLAGS))
19600 break; // Should have kill-flag - update below.
19603 // If we hit the end of the block, check whether EFLAGS is live into a
19605 if (miI == BB->end()) {
19606 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
19607 sEnd = BB->succ_end();
19608 sItr != sEnd; ++sItr) {
19609 MachineBasicBlock* succ = *sItr;
19610 if (succ->isLiveIn(X86::EFLAGS))
19615 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
19616 // out. SelectMI should have a kill flag on EFLAGS.
19617 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
19621 MachineBasicBlock *
19622 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
19623 MachineBasicBlock *BB) const {
19624 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19625 DebugLoc DL = MI->getDebugLoc();
19627 // To "insert" a SELECT_CC instruction, we actually have to insert the
19628 // diamond control-flow pattern. The incoming instruction knows the
19629 // destination vreg to set, the condition code register to branch on, the
19630 // true/false values to select between, and a branch opcode to use.
19631 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19632 MachineFunction::iterator It = BB;
19638 // cmpTY ccX, r1, r2
19640 // fallthrough --> copy0MBB
19641 MachineBasicBlock *thisMBB = BB;
19642 MachineFunction *F = BB->getParent();
19644 // We also lower double CMOVs:
19645 // (CMOV (CMOV F, T, cc1), T, cc2)
19646 // to two successives branches. For that, we look for another CMOV as the
19647 // following instruction.
19649 // Without this, we would add a PHI between the two jumps, which ends up
19650 // creating a few copies all around. For instance, for
19652 // (sitofp (zext (fcmp une)))
19654 // we would generate:
19656 // ucomiss %xmm1, %xmm0
19657 // movss <1.0f>, %xmm0
19658 // movaps %xmm0, %xmm1
19660 // xorps %xmm1, %xmm1
19663 // movaps %xmm1, %xmm0
19667 // because this custom-inserter would have generated:
19679 // A: X = ...; Y = ...
19681 // C: Z = PHI [X, A], [Y, B]
19683 // E: PHI [X, C], [Z, D]
19685 // If we lower both CMOVs in a single step, we can instead generate:
19697 // A: X = ...; Y = ...
19699 // E: PHI [X, A], [X, C], [Y, D]
19701 // Which, in our sitofp/fcmp example, gives us something like:
19703 // ucomiss %xmm1, %xmm0
19704 // movss <1.0f>, %xmm0
19707 // xorps %xmm0, %xmm0
19711 MachineInstr *NextCMOV = nullptr;
19712 MachineBasicBlock::iterator NextMIIt =
19713 std::next(MachineBasicBlock::iterator(MI));
19714 if (NextMIIt != BB->end() && NextMIIt->getOpcode() == MI->getOpcode() &&
19715 NextMIIt->getOperand(2).getReg() == MI->getOperand(2).getReg() &&
19716 NextMIIt->getOperand(1).getReg() == MI->getOperand(0).getReg())
19717 NextCMOV = &*NextMIIt;
19719 MachineBasicBlock *jcc1MBB = nullptr;
19721 // If we have a double CMOV, we lower it to two successive branches to
19722 // the same block. EFLAGS is used by both, so mark it as live in the second.
19724 jcc1MBB = F->CreateMachineBasicBlock(LLVM_BB);
19725 F->insert(It, jcc1MBB);
19726 jcc1MBB->addLiveIn(X86::EFLAGS);
19729 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
19730 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
19731 F->insert(It, copy0MBB);
19732 F->insert(It, sinkMBB);
19734 // If the EFLAGS register isn't dead in the terminator, then claim that it's
19735 // live into the sink and copy blocks.
19736 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
19738 MachineInstr *LastEFLAGSUser = NextCMOV ? NextCMOV : MI;
19739 if (!LastEFLAGSUser->killsRegister(X86::EFLAGS) &&
19740 !checkAndUpdateEFLAGSKill(LastEFLAGSUser, BB, TRI)) {
19741 copy0MBB->addLiveIn(X86::EFLAGS);
19742 sinkMBB->addLiveIn(X86::EFLAGS);
19745 // Transfer the remainder of BB and its successor edges to sinkMBB.
19746 sinkMBB->splice(sinkMBB->begin(), BB,
19747 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19748 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
19750 // Add the true and fallthrough blocks as its successors.
19752 // The fallthrough block may be jcc1MBB, if we have a double CMOV.
19753 BB->addSuccessor(jcc1MBB);
19755 // In that case, jcc1MBB will itself fallthrough the copy0MBB, and
19756 // jump to the sinkMBB.
19757 jcc1MBB->addSuccessor(copy0MBB);
19758 jcc1MBB->addSuccessor(sinkMBB);
19760 BB->addSuccessor(copy0MBB);
19763 // The true block target of the first (or only) branch is always sinkMBB.
19764 BB->addSuccessor(sinkMBB);
19766 // Create the conditional branch instruction.
19768 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
19769 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
19772 unsigned Opc2 = X86::GetCondBranchFromCond(
19773 (X86::CondCode)NextCMOV->getOperand(3).getImm());
19774 BuildMI(jcc1MBB, DL, TII->get(Opc2)).addMBB(sinkMBB);
19778 // %FalseValue = ...
19779 // # fallthrough to sinkMBB
19780 copy0MBB->addSuccessor(sinkMBB);
19783 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
19785 MachineInstrBuilder MIB =
19786 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI),
19787 MI->getOperand(0).getReg())
19788 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
19789 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
19791 // If we have a double CMOV, the second Jcc provides the same incoming
19792 // value as the first Jcc (the True operand of the SELECT_CC/CMOV nodes).
19794 MIB.addReg(MI->getOperand(2).getReg()).addMBB(jcc1MBB);
19795 // Copy the PHI result to the register defined by the second CMOV.
19796 BuildMI(*sinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())),
19797 DL, TII->get(TargetOpcode::COPY), NextCMOV->getOperand(0).getReg())
19798 .addReg(MI->getOperand(0).getReg());
19799 NextCMOV->eraseFromParent();
19802 MI->eraseFromParent(); // The pseudo instruction is gone now.
19806 MachineBasicBlock *
19807 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI,
19808 MachineBasicBlock *BB) const {
19809 MachineFunction *MF = BB->getParent();
19810 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
19811 DebugLoc DL = MI->getDebugLoc();
19812 const BasicBlock *LLVM_BB = BB->getBasicBlock();
19814 assert(MF->shouldSplitStack());
19816 const bool Is64Bit = Subtarget->is64Bit();
19817 const bool IsLP64 = Subtarget->isTarget64BitLP64();
19819 const unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
19820 const unsigned TlsOffset = IsLP64 ? 0x70 : Is64Bit ? 0x40 : 0x30;
19823 // ... [Till the alloca]
19824 // If stacklet is not large enough, jump to mallocMBB
19827 // Allocate by subtracting from RSP
19828 // Jump to continueMBB
19831 // Allocate by call to runtime
19835 // [rest of original BB]
19838 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19839 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19840 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
19842 MachineRegisterInfo &MRI = MF->getRegInfo();
19843 const TargetRegisterClass *AddrRegClass =
19844 getRegClassFor(getPointerTy());
19846 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19847 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
19848 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
19849 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
19850 sizeVReg = MI->getOperand(1).getReg(),
19851 physSPReg = IsLP64 || Subtarget->isTargetNaCl64() ? X86::RSP : X86::ESP;
19853 MachineFunction::iterator MBBIter = BB;
19856 MF->insert(MBBIter, bumpMBB);
19857 MF->insert(MBBIter, mallocMBB);
19858 MF->insert(MBBIter, continueMBB);
19860 continueMBB->splice(continueMBB->begin(), BB,
19861 std::next(MachineBasicBlock::iterator(MI)), BB->end());
19862 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
19864 // Add code to the main basic block to check if the stack limit has been hit,
19865 // and if so, jump to mallocMBB otherwise to bumpMBB.
19866 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
19867 BuildMI(BB, DL, TII->get(IsLP64 ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
19868 .addReg(tmpSPVReg).addReg(sizeVReg);
19869 BuildMI(BB, DL, TII->get(IsLP64 ? X86::CMP64mr:X86::CMP32mr))
19870 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
19871 .addReg(SPLimitVReg);
19872 BuildMI(BB, DL, TII->get(X86::JG_1)).addMBB(mallocMBB);
19874 // bumpMBB simply decreases the stack pointer, since we know the current
19875 // stacklet has enough space.
19876 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
19877 .addReg(SPLimitVReg);
19878 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
19879 .addReg(SPLimitVReg);
19880 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19882 // Calls into a routine in libgcc to allocate more space from the heap.
19883 const uint32_t *RegMask =
19884 Subtarget->getRegisterInfo()->getCallPreservedMask(*MF, CallingConv::C);
19886 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
19888 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19889 .addExternalSymbol("__morestack_allocate_stack_space")
19890 .addRegMask(RegMask)
19891 .addReg(X86::RDI, RegState::Implicit)
19892 .addReg(X86::RAX, RegState::ImplicitDefine);
19893 } else if (Is64Bit) {
19894 BuildMI(mallocMBB, DL, TII->get(X86::MOV32rr), X86::EDI)
19896 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
19897 .addExternalSymbol("__morestack_allocate_stack_space")
19898 .addRegMask(RegMask)
19899 .addReg(X86::EDI, RegState::Implicit)
19900 .addReg(X86::EAX, RegState::ImplicitDefine);
19902 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
19904 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
19905 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
19906 .addExternalSymbol("__morestack_allocate_stack_space")
19907 .addRegMask(RegMask)
19908 .addReg(X86::EAX, RegState::ImplicitDefine);
19912 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
19915 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
19916 .addReg(IsLP64 ? X86::RAX : X86::EAX);
19917 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
19919 // Set up the CFG correctly.
19920 BB->addSuccessor(bumpMBB);
19921 BB->addSuccessor(mallocMBB);
19922 mallocMBB->addSuccessor(continueMBB);
19923 bumpMBB->addSuccessor(continueMBB);
19925 // Take care of the PHI nodes.
19926 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
19927 MI->getOperand(0).getReg())
19928 .addReg(mallocPtrVReg).addMBB(mallocMBB)
19929 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
19931 // Delete the original pseudo instruction.
19932 MI->eraseFromParent();
19935 return continueMBB;
19938 MachineBasicBlock *
19939 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
19940 MachineBasicBlock *BB) const {
19941 DebugLoc DL = MI->getDebugLoc();
19943 assert(!Subtarget->isTargetMachO());
19945 Subtarget->getFrameLowering()->emitStackProbeCall(*BB->getParent(), *BB, MI,
19948 MI->eraseFromParent(); // The pseudo instruction is gone now.
19952 MachineBasicBlock *
19953 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
19954 MachineBasicBlock *BB) const {
19955 // This is pretty easy. We're taking the value that we received from
19956 // our load from the relocation, sticking it in either RDI (x86-64)
19957 // or EAX and doing an indirect call. The return value will then
19958 // be in the normal return register.
19959 MachineFunction *F = BB->getParent();
19960 const X86InstrInfo *TII = Subtarget->getInstrInfo();
19961 DebugLoc DL = MI->getDebugLoc();
19963 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
19964 assert(MI->getOperand(3).isGlobal() && "This should be a global");
19966 // Get a register mask for the lowered call.
19967 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
19968 // proper register mask.
19969 const uint32_t *RegMask =
19970 Subtarget->getRegisterInfo()->getCallPreservedMask(*F, CallingConv::C);
19971 if (Subtarget->is64Bit()) {
19972 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19973 TII->get(X86::MOV64rm), X86::RDI)
19975 .addImm(0).addReg(0)
19976 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19977 MI->getOperand(3).getTargetFlags())
19979 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
19980 addDirectMem(MIB, X86::RDI);
19981 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
19982 } else if (F->getTarget().getRelocationModel() != Reloc::PIC_) {
19983 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19984 TII->get(X86::MOV32rm), X86::EAX)
19986 .addImm(0).addReg(0)
19987 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19988 MI->getOperand(3).getTargetFlags())
19990 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
19991 addDirectMem(MIB, X86::EAX);
19992 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
19994 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
19995 TII->get(X86::MOV32rm), X86::EAX)
19996 .addReg(TII->getGlobalBaseReg(F))
19997 .addImm(0).addReg(0)
19998 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
19999 MI->getOperand(3).getTargetFlags())
20001 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
20002 addDirectMem(MIB, X86::EAX);
20003 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
20006 MI->eraseFromParent(); // The pseudo instruction is gone now.
20010 MachineBasicBlock *
20011 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
20012 MachineBasicBlock *MBB) const {
20013 DebugLoc DL = MI->getDebugLoc();
20014 MachineFunction *MF = MBB->getParent();
20015 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20016 MachineRegisterInfo &MRI = MF->getRegInfo();
20018 const BasicBlock *BB = MBB->getBasicBlock();
20019 MachineFunction::iterator I = MBB;
20022 // Memory Reference
20023 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20024 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20027 unsigned MemOpndSlot = 0;
20029 unsigned CurOp = 0;
20031 DstReg = MI->getOperand(CurOp++).getReg();
20032 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
20033 assert(RC->hasType(MVT::i32) && "Invalid destination!");
20034 unsigned mainDstReg = MRI.createVirtualRegister(RC);
20035 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
20037 MemOpndSlot = CurOp;
20039 MVT PVT = getPointerTy();
20040 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20041 "Invalid Pointer Size!");
20043 // For v = setjmp(buf), we generate
20046 // buf[LabelOffset] = restoreMBB
20047 // SjLjSetup restoreMBB
20053 // v = phi(main, restore)
20056 // if base pointer being used, load it from frame
20059 MachineBasicBlock *thisMBB = MBB;
20060 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
20061 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
20062 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
20063 MF->insert(I, mainMBB);
20064 MF->insert(I, sinkMBB);
20065 MF->push_back(restoreMBB);
20067 MachineInstrBuilder MIB;
20069 // Transfer the remainder of BB and its successor edges to sinkMBB.
20070 sinkMBB->splice(sinkMBB->begin(), MBB,
20071 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
20072 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
20075 unsigned PtrStoreOpc = 0;
20076 unsigned LabelReg = 0;
20077 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20078 Reloc::Model RM = MF->getTarget().getRelocationModel();
20079 bool UseImmLabel = (MF->getTarget().getCodeModel() == CodeModel::Small) &&
20080 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
20082 // Prepare IP either in reg or imm.
20083 if (!UseImmLabel) {
20084 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
20085 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
20086 LabelReg = MRI.createVirtualRegister(PtrRC);
20087 if (Subtarget->is64Bit()) {
20088 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
20092 .addMBB(restoreMBB)
20095 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
20096 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
20097 .addReg(XII->getGlobalBaseReg(MF))
20100 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
20104 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
20106 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
20107 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20108 if (i == X86::AddrDisp)
20109 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
20111 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
20114 MIB.addReg(LabelReg);
20116 MIB.addMBB(restoreMBB);
20117 MIB.setMemRefs(MMOBegin, MMOEnd);
20119 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
20120 .addMBB(restoreMBB);
20122 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20123 MIB.addRegMask(RegInfo->getNoPreservedMask());
20124 thisMBB->addSuccessor(mainMBB);
20125 thisMBB->addSuccessor(restoreMBB);
20129 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
20130 mainMBB->addSuccessor(sinkMBB);
20133 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
20134 TII->get(X86::PHI), DstReg)
20135 .addReg(mainDstReg).addMBB(mainMBB)
20136 .addReg(restoreDstReg).addMBB(restoreMBB);
20139 if (RegInfo->hasBasePointer(*MF)) {
20140 const bool Uses64BitFramePtr =
20141 Subtarget->isTarget64BitLP64() || Subtarget->isTargetNaCl64();
20142 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
20143 X86FI->setRestoreBasePointer(MF);
20144 unsigned FramePtr = RegInfo->getFrameRegister(*MF);
20145 unsigned BasePtr = RegInfo->getBaseRegister();
20146 unsigned Opm = Uses64BitFramePtr ? X86::MOV64rm : X86::MOV32rm;
20147 addRegOffset(BuildMI(restoreMBB, DL, TII->get(Opm), BasePtr),
20148 FramePtr, true, X86FI->getRestoreBasePointerOffset())
20149 .setMIFlag(MachineInstr::FrameSetup);
20151 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
20152 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
20153 restoreMBB->addSuccessor(sinkMBB);
20155 MI->eraseFromParent();
20159 MachineBasicBlock *
20160 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
20161 MachineBasicBlock *MBB) const {
20162 DebugLoc DL = MI->getDebugLoc();
20163 MachineFunction *MF = MBB->getParent();
20164 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20165 MachineRegisterInfo &MRI = MF->getRegInfo();
20167 // Memory Reference
20168 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
20169 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
20171 MVT PVT = getPointerTy();
20172 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
20173 "Invalid Pointer Size!");
20175 const TargetRegisterClass *RC =
20176 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
20177 unsigned Tmp = MRI.createVirtualRegister(RC);
20178 // Since FP is only updated here but NOT referenced, it's treated as GPR.
20179 const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();
20180 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
20181 unsigned SP = RegInfo->getStackRegister();
20183 MachineInstrBuilder MIB;
20185 const int64_t LabelOffset = 1 * PVT.getStoreSize();
20186 const int64_t SPOffset = 2 * PVT.getStoreSize();
20188 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
20189 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
20192 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
20193 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
20194 MIB.addOperand(MI->getOperand(i));
20195 MIB.setMemRefs(MMOBegin, MMOEnd);
20197 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
20198 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20199 if (i == X86::AddrDisp)
20200 MIB.addDisp(MI->getOperand(i), LabelOffset);
20202 MIB.addOperand(MI->getOperand(i));
20204 MIB.setMemRefs(MMOBegin, MMOEnd);
20206 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
20207 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
20208 if (i == X86::AddrDisp)
20209 MIB.addDisp(MI->getOperand(i), SPOffset);
20211 MIB.addOperand(MI->getOperand(i));
20213 MIB.setMemRefs(MMOBegin, MMOEnd);
20215 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
20217 MI->eraseFromParent();
20221 // Replace 213-type (isel default) FMA3 instructions with 231-type for
20222 // accumulator loops. Writing back to the accumulator allows the coalescer
20223 // to remove extra copies in the loop.
20224 // FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
20225 MachineBasicBlock *
20226 X86TargetLowering::emitFMA3Instr(MachineInstr *MI,
20227 MachineBasicBlock *MBB) const {
20228 MachineOperand &AddendOp = MI->getOperand(3);
20230 // Bail out early if the addend isn't a register - we can't switch these.
20231 if (!AddendOp.isReg())
20234 MachineFunction &MF = *MBB->getParent();
20235 MachineRegisterInfo &MRI = MF.getRegInfo();
20237 // Check whether the addend is defined by a PHI:
20238 assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
20239 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
20240 if (!AddendDef.isPHI())
20243 // Look for the following pattern:
20245 // %addend = phi [%entry, 0], [%loop, %result]
20247 // %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
20251 // %addend = phi [%entry, 0], [%loop, %result]
20253 // %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
20255 for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
20256 assert(AddendDef.getOperand(i).isReg());
20257 MachineOperand PHISrcOp = AddendDef.getOperand(i);
20258 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
20259 if (&PHISrcInst == MI) {
20260 // Found a matching instruction.
20261 unsigned NewFMAOpc = 0;
20262 switch (MI->getOpcode()) {
20263 case X86::VFMADDPDr213r: NewFMAOpc = X86::VFMADDPDr231r; break;
20264 case X86::VFMADDPSr213r: NewFMAOpc = X86::VFMADDPSr231r; break;
20265 case X86::VFMADDSDr213r: NewFMAOpc = X86::VFMADDSDr231r; break;
20266 case X86::VFMADDSSr213r: NewFMAOpc = X86::VFMADDSSr231r; break;
20267 case X86::VFMSUBPDr213r: NewFMAOpc = X86::VFMSUBPDr231r; break;
20268 case X86::VFMSUBPSr213r: NewFMAOpc = X86::VFMSUBPSr231r; break;
20269 case X86::VFMSUBSDr213r: NewFMAOpc = X86::VFMSUBSDr231r; break;
20270 case X86::VFMSUBSSr213r: NewFMAOpc = X86::VFMSUBSSr231r; break;
20271 case X86::VFNMADDPDr213r: NewFMAOpc = X86::VFNMADDPDr231r; break;
20272 case X86::VFNMADDPSr213r: NewFMAOpc = X86::VFNMADDPSr231r; break;
20273 case X86::VFNMADDSDr213r: NewFMAOpc = X86::VFNMADDSDr231r; break;
20274 case X86::VFNMADDSSr213r: NewFMAOpc = X86::VFNMADDSSr231r; break;
20275 case X86::VFNMSUBPDr213r: NewFMAOpc = X86::VFNMSUBPDr231r; break;
20276 case X86::VFNMSUBPSr213r: NewFMAOpc = X86::VFNMSUBPSr231r; break;
20277 case X86::VFNMSUBSDr213r: NewFMAOpc = X86::VFNMSUBSDr231r; break;
20278 case X86::VFNMSUBSSr213r: NewFMAOpc = X86::VFNMSUBSSr231r; break;
20279 case X86::VFMADDSUBPDr213r: NewFMAOpc = X86::VFMADDSUBPDr231r; break;
20280 case X86::VFMADDSUBPSr213r: NewFMAOpc = X86::VFMADDSUBPSr231r; break;
20281 case X86::VFMSUBADDPDr213r: NewFMAOpc = X86::VFMSUBADDPDr231r; break;
20282 case X86::VFMSUBADDPSr213r: NewFMAOpc = X86::VFMSUBADDPSr231r; break;
20284 case X86::VFMADDPDr213rY: NewFMAOpc = X86::VFMADDPDr231rY; break;
20285 case X86::VFMADDPSr213rY: NewFMAOpc = X86::VFMADDPSr231rY; break;
20286 case X86::VFMSUBPDr213rY: NewFMAOpc = X86::VFMSUBPDr231rY; break;
20287 case X86::VFMSUBPSr213rY: NewFMAOpc = X86::VFMSUBPSr231rY; break;
20288 case X86::VFNMADDPDr213rY: NewFMAOpc = X86::VFNMADDPDr231rY; break;
20289 case X86::VFNMADDPSr213rY: NewFMAOpc = X86::VFNMADDPSr231rY; break;
20290 case X86::VFNMSUBPDr213rY: NewFMAOpc = X86::VFNMSUBPDr231rY; break;
20291 case X86::VFNMSUBPSr213rY: NewFMAOpc = X86::VFNMSUBPSr231rY; break;
20292 case X86::VFMADDSUBPDr213rY: NewFMAOpc = X86::VFMADDSUBPDr231rY; break;
20293 case X86::VFMADDSUBPSr213rY: NewFMAOpc = X86::VFMADDSUBPSr231rY; break;
20294 case X86::VFMSUBADDPDr213rY: NewFMAOpc = X86::VFMSUBADDPDr231rY; break;
20295 case X86::VFMSUBADDPSr213rY: NewFMAOpc = X86::VFMSUBADDPSr231rY; break;
20296 default: llvm_unreachable("Unrecognized FMA variant.");
20299 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
20300 MachineInstrBuilder MIB =
20301 BuildMI(MF, MI->getDebugLoc(), TII.get(NewFMAOpc))
20302 .addOperand(MI->getOperand(0))
20303 .addOperand(MI->getOperand(3))
20304 .addOperand(MI->getOperand(2))
20305 .addOperand(MI->getOperand(1));
20306 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
20307 MI->eraseFromParent();
20314 MachineBasicBlock *
20315 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
20316 MachineBasicBlock *BB) const {
20317 switch (MI->getOpcode()) {
20318 default: llvm_unreachable("Unexpected instr type to insert");
20319 case X86::TAILJMPd64:
20320 case X86::TAILJMPr64:
20321 case X86::TAILJMPm64:
20322 case X86::TAILJMPd64_REX:
20323 case X86::TAILJMPr64_REX:
20324 case X86::TAILJMPm64_REX:
20325 llvm_unreachable("TAILJMP64 would not be touched here.");
20326 case X86::TCRETURNdi64:
20327 case X86::TCRETURNri64:
20328 case X86::TCRETURNmi64:
20330 case X86::WIN_ALLOCA:
20331 return EmitLoweredWinAlloca(MI, BB);
20332 case X86::SEG_ALLOCA_32:
20333 case X86::SEG_ALLOCA_64:
20334 return EmitLoweredSegAlloca(MI, BB);
20335 case X86::TLSCall_32:
20336 case X86::TLSCall_64:
20337 return EmitLoweredTLSCall(MI, BB);
20338 case X86::CMOV_GR8:
20339 case X86::CMOV_FR32:
20340 case X86::CMOV_FR64:
20341 case X86::CMOV_V4F32:
20342 case X86::CMOV_V2F64:
20343 case X86::CMOV_V2I64:
20344 case X86::CMOV_V8F32:
20345 case X86::CMOV_V4F64:
20346 case X86::CMOV_V4I64:
20347 case X86::CMOV_V16F32:
20348 case X86::CMOV_V8F64:
20349 case X86::CMOV_V8I64:
20350 case X86::CMOV_GR16:
20351 case X86::CMOV_GR32:
20352 case X86::CMOV_RFP32:
20353 case X86::CMOV_RFP64:
20354 case X86::CMOV_RFP80:
20355 case X86::CMOV_V8I1:
20356 case X86::CMOV_V16I1:
20357 case X86::CMOV_V32I1:
20358 case X86::CMOV_V64I1:
20359 return EmitLoweredSelect(MI, BB);
20361 case X86::FP32_TO_INT16_IN_MEM:
20362 case X86::FP32_TO_INT32_IN_MEM:
20363 case X86::FP32_TO_INT64_IN_MEM:
20364 case X86::FP64_TO_INT16_IN_MEM:
20365 case X86::FP64_TO_INT32_IN_MEM:
20366 case X86::FP64_TO_INT64_IN_MEM:
20367 case X86::FP80_TO_INT16_IN_MEM:
20368 case X86::FP80_TO_INT32_IN_MEM:
20369 case X86::FP80_TO_INT64_IN_MEM: {
20370 MachineFunction *F = BB->getParent();
20371 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
20372 DebugLoc DL = MI->getDebugLoc();
20374 // Change the floating point control register to use "round towards zero"
20375 // mode when truncating to an integer value.
20376 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
20377 addFrameReference(BuildMI(*BB, MI, DL,
20378 TII->get(X86::FNSTCW16m)), CWFrameIdx);
20380 // Load the old value of the high byte of the control word...
20382 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
20383 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
20386 // Set the high part to be round to zero...
20387 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
20390 // Reload the modified control word now...
20391 addFrameReference(BuildMI(*BB, MI, DL,
20392 TII->get(X86::FLDCW16m)), CWFrameIdx);
20394 // Restore the memory image of control word to original value
20395 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
20398 // Get the X86 opcode to use.
20400 switch (MI->getOpcode()) {
20401 default: llvm_unreachable("illegal opcode!");
20402 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
20403 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
20404 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
20405 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
20406 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
20407 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
20408 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
20409 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
20410 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
20414 MachineOperand &Op = MI->getOperand(0);
20416 AM.BaseType = X86AddressMode::RegBase;
20417 AM.Base.Reg = Op.getReg();
20419 AM.BaseType = X86AddressMode::FrameIndexBase;
20420 AM.Base.FrameIndex = Op.getIndex();
20422 Op = MI->getOperand(1);
20424 AM.Scale = Op.getImm();
20425 Op = MI->getOperand(2);
20427 AM.IndexReg = Op.getImm();
20428 Op = MI->getOperand(3);
20429 if (Op.isGlobal()) {
20430 AM.GV = Op.getGlobal();
20432 AM.Disp = Op.getImm();
20434 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
20435 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
20437 // Reload the original control word now.
20438 addFrameReference(BuildMI(*BB, MI, DL,
20439 TII->get(X86::FLDCW16m)), CWFrameIdx);
20441 MI->eraseFromParent(); // The pseudo instruction is gone now.
20444 // String/text processing lowering.
20445 case X86::PCMPISTRM128REG:
20446 case X86::VPCMPISTRM128REG:
20447 case X86::PCMPISTRM128MEM:
20448 case X86::VPCMPISTRM128MEM:
20449 case X86::PCMPESTRM128REG:
20450 case X86::VPCMPESTRM128REG:
20451 case X86::PCMPESTRM128MEM:
20452 case X86::VPCMPESTRM128MEM:
20453 assert(Subtarget->hasSSE42() &&
20454 "Target must have SSE4.2 or AVX features enabled");
20455 return EmitPCMPSTRM(MI, BB, Subtarget->getInstrInfo());
20457 // String/text processing lowering.
20458 case X86::PCMPISTRIREG:
20459 case X86::VPCMPISTRIREG:
20460 case X86::PCMPISTRIMEM:
20461 case X86::VPCMPISTRIMEM:
20462 case X86::PCMPESTRIREG:
20463 case X86::VPCMPESTRIREG:
20464 case X86::PCMPESTRIMEM:
20465 case X86::VPCMPESTRIMEM:
20466 assert(Subtarget->hasSSE42() &&
20467 "Target must have SSE4.2 or AVX features enabled");
20468 return EmitPCMPSTRI(MI, BB, Subtarget->getInstrInfo());
20470 // Thread synchronization.
20472 return EmitMonitor(MI, BB, Subtarget);
20476 return EmitXBegin(MI, BB, Subtarget->getInstrInfo());
20478 case X86::VASTART_SAVE_XMM_REGS:
20479 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
20481 case X86::VAARG_64:
20482 return EmitVAARG64WithCustomInserter(MI, BB);
20484 case X86::EH_SjLj_SetJmp32:
20485 case X86::EH_SjLj_SetJmp64:
20486 return emitEHSjLjSetJmp(MI, BB);
20488 case X86::EH_SjLj_LongJmp32:
20489 case X86::EH_SjLj_LongJmp64:
20490 return emitEHSjLjLongJmp(MI, BB);
20492 case TargetOpcode::STATEPOINT:
20493 // As an implementation detail, STATEPOINT shares the STACKMAP format at
20494 // this point in the process. We diverge later.
20495 return emitPatchPoint(MI, BB);
20497 case TargetOpcode::STACKMAP:
20498 case TargetOpcode::PATCHPOINT:
20499 return emitPatchPoint(MI, BB);
20501 case X86::VFMADDPDr213r:
20502 case X86::VFMADDPSr213r:
20503 case X86::VFMADDSDr213r:
20504 case X86::VFMADDSSr213r:
20505 case X86::VFMSUBPDr213r:
20506 case X86::VFMSUBPSr213r:
20507 case X86::VFMSUBSDr213r:
20508 case X86::VFMSUBSSr213r:
20509 case X86::VFNMADDPDr213r:
20510 case X86::VFNMADDPSr213r:
20511 case X86::VFNMADDSDr213r:
20512 case X86::VFNMADDSSr213r:
20513 case X86::VFNMSUBPDr213r:
20514 case X86::VFNMSUBPSr213r:
20515 case X86::VFNMSUBSDr213r:
20516 case X86::VFNMSUBSSr213r:
20517 case X86::VFMADDSUBPDr213r:
20518 case X86::VFMADDSUBPSr213r:
20519 case X86::VFMSUBADDPDr213r:
20520 case X86::VFMSUBADDPSr213r:
20521 case X86::VFMADDPDr213rY:
20522 case X86::VFMADDPSr213rY:
20523 case X86::VFMSUBPDr213rY:
20524 case X86::VFMSUBPSr213rY:
20525 case X86::VFNMADDPDr213rY:
20526 case X86::VFNMADDPSr213rY:
20527 case X86::VFNMSUBPDr213rY:
20528 case X86::VFNMSUBPSr213rY:
20529 case X86::VFMADDSUBPDr213rY:
20530 case X86::VFMADDSUBPSr213rY:
20531 case X86::VFMSUBADDPDr213rY:
20532 case X86::VFMSUBADDPSr213rY:
20533 return emitFMA3Instr(MI, BB);
20537 //===----------------------------------------------------------------------===//
20538 // X86 Optimization Hooks
20539 //===----------------------------------------------------------------------===//
20541 void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
20544 const SelectionDAG &DAG,
20545 unsigned Depth) const {
20546 unsigned BitWidth = KnownZero.getBitWidth();
20547 unsigned Opc = Op.getOpcode();
20548 assert((Opc >= ISD::BUILTIN_OP_END ||
20549 Opc == ISD::INTRINSIC_WO_CHAIN ||
20550 Opc == ISD::INTRINSIC_W_CHAIN ||
20551 Opc == ISD::INTRINSIC_VOID) &&
20552 "Should use MaskedValueIsZero if you don't know whether Op"
20553 " is a target node!");
20555 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
20569 // These nodes' second result is a boolean.
20570 if (Op.getResNo() == 0)
20573 case X86ISD::SETCC:
20574 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
20576 case ISD::INTRINSIC_WO_CHAIN: {
20577 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
20578 unsigned NumLoBits = 0;
20581 case Intrinsic::x86_sse_movmsk_ps:
20582 case Intrinsic::x86_avx_movmsk_ps_256:
20583 case Intrinsic::x86_sse2_movmsk_pd:
20584 case Intrinsic::x86_avx_movmsk_pd_256:
20585 case Intrinsic::x86_mmx_pmovmskb:
20586 case Intrinsic::x86_sse2_pmovmskb_128:
20587 case Intrinsic::x86_avx2_pmovmskb: {
20588 // High bits of movmskp{s|d}, pmovmskb are known zero.
20590 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
20591 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
20592 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
20593 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
20594 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
20595 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
20596 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
20597 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
20599 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
20608 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(
20610 const SelectionDAG &,
20611 unsigned Depth) const {
20612 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
20613 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
20614 return Op.getValueType().getScalarType().getSizeInBits();
20620 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
20621 /// node is a GlobalAddress + offset.
20622 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
20623 const GlobalValue* &GA,
20624 int64_t &Offset) const {
20625 if (N->getOpcode() == X86ISD::Wrapper) {
20626 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
20627 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
20628 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
20632 return TargetLowering::isGAPlusOffset(N, GA, Offset);
20635 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
20636 /// same as extracting the high 128-bit part of 256-bit vector and then
20637 /// inserting the result into the low part of a new 256-bit vector
20638 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
20639 EVT VT = SVOp->getValueType(0);
20640 unsigned NumElems = VT.getVectorNumElements();
20642 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20643 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
20644 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20645 SVOp->getMaskElt(j) >= 0)
20651 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
20652 /// same as extracting the low 128-bit part of 256-bit vector and then
20653 /// inserting the result into the high part of a new 256-bit vector
20654 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
20655 EVT VT = SVOp->getValueType(0);
20656 unsigned NumElems = VT.getVectorNumElements();
20658 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20659 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
20660 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
20661 SVOp->getMaskElt(j) >= 0)
20667 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
20668 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
20669 TargetLowering::DAGCombinerInfo &DCI,
20670 const X86Subtarget* Subtarget) {
20672 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
20673 SDValue V1 = SVOp->getOperand(0);
20674 SDValue V2 = SVOp->getOperand(1);
20675 EVT VT = SVOp->getValueType(0);
20676 unsigned NumElems = VT.getVectorNumElements();
20678 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
20679 V2.getOpcode() == ISD::CONCAT_VECTORS) {
20683 // V UNDEF BUILD_VECTOR UNDEF
20685 // CONCAT_VECTOR CONCAT_VECTOR
20688 // RESULT: V + zero extended
20690 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
20691 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
20692 V1.getOperand(1).getOpcode() != ISD::UNDEF)
20695 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
20698 // To match the shuffle mask, the first half of the mask should
20699 // be exactly the first vector, and all the rest a splat with the
20700 // first element of the second one.
20701 for (unsigned i = 0; i != NumElems/2; ++i)
20702 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
20703 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
20706 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
20707 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
20708 if (Ld->hasNUsesOfValue(1, 0)) {
20709 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
20710 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
20712 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
20714 Ld->getPointerInfo(),
20715 Ld->getAlignment(),
20716 false/*isVolatile*/, true/*ReadMem*/,
20717 false/*WriteMem*/);
20719 // Make sure the newly-created LOAD is in the same position as Ld in
20720 // terms of dependency. We create a TokenFactor for Ld and ResNode,
20721 // and update uses of Ld's output chain to use the TokenFactor.
20722 if (Ld->hasAnyUseOfValue(1)) {
20723 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
20724 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
20725 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
20726 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
20727 SDValue(ResNode.getNode(), 1));
20730 return DAG.getBitcast(VT, ResNode);
20734 // Emit a zeroed vector and insert the desired subvector on its
20736 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
20737 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
20738 return DCI.CombineTo(N, InsV);
20741 //===--------------------------------------------------------------------===//
20742 // Combine some shuffles into subvector extracts and inserts:
20745 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
20746 if (isShuffleHigh128VectorInsertLow(SVOp)) {
20747 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
20748 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
20749 return DCI.CombineTo(N, InsV);
20752 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
20753 if (isShuffleLow128VectorInsertHigh(SVOp)) {
20754 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
20755 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
20756 return DCI.CombineTo(N, InsV);
20762 /// \brief Combine an arbitrary chain of shuffles into a single instruction if
20765 /// This is the leaf of the recursive combinine below. When we have found some
20766 /// chain of single-use x86 shuffle instructions and accumulated the combined
20767 /// shuffle mask represented by them, this will try to pattern match that mask
20768 /// into either a single instruction if there is a special purpose instruction
20769 /// for this operation, or into a PSHUFB instruction which is a fully general
20770 /// instruction but should only be used to replace chains over a certain depth.
20771 static bool combineX86ShuffleChain(SDValue Op, SDValue Root, ArrayRef<int> Mask,
20772 int Depth, bool HasPSHUFB, SelectionDAG &DAG,
20773 TargetLowering::DAGCombinerInfo &DCI,
20774 const X86Subtarget *Subtarget) {
20775 assert(!Mask.empty() && "Cannot combine an empty shuffle mask!");
20777 // Find the operand that enters the chain. Note that multiple uses are OK
20778 // here, we're not going to remove the operand we find.
20779 SDValue Input = Op.getOperand(0);
20780 while (Input.getOpcode() == ISD::BITCAST)
20781 Input = Input.getOperand(0);
20783 MVT VT = Input.getSimpleValueType();
20784 MVT RootVT = Root.getSimpleValueType();
20787 // Just remove no-op shuffle masks.
20788 if (Mask.size() == 1) {
20789 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Input),
20794 // Use the float domain if the operand type is a floating point type.
20795 bool FloatDomain = VT.isFloatingPoint();
20797 // For floating point shuffles, we don't have free copies in the shuffle
20798 // instructions or the ability to load as part of the instruction, so
20799 // canonicalize their shuffles to UNPCK or MOV variants.
20801 // Note that even with AVX we prefer the PSHUFD form of shuffle for integer
20802 // vectors because it can have a load folded into it that UNPCK cannot. This
20803 // doesn't preclude something switching to the shorter encoding post-RA.
20805 // FIXME: Should teach these routines about AVX vector widths.
20806 if (FloatDomain && VT.getSizeInBits() == 128) {
20807 if (Mask.equals({0, 0}) || Mask.equals({1, 1})) {
20808 bool Lo = Mask.equals({0, 0});
20811 // Check if we have SSE3 which will let us use MOVDDUP. That instruction
20812 // is no slower than UNPCKLPD but has the option to fold the input operand
20813 // into even an unaligned memory load.
20814 if (Lo && Subtarget->hasSSE3()) {
20815 Shuffle = X86ISD::MOVDDUP;
20816 ShuffleVT = MVT::v2f64;
20818 // We have MOVLHPS and MOVHLPS throughout SSE and they encode smaller
20819 // than the UNPCK variants.
20820 Shuffle = Lo ? X86ISD::MOVLHPS : X86ISD::MOVHLPS;
20821 ShuffleVT = MVT::v4f32;
20823 if (Depth == 1 && Root->getOpcode() == Shuffle)
20824 return false; // Nothing to do!
20825 Op = DAG.getBitcast(ShuffleVT, Input);
20826 DCI.AddToWorklist(Op.getNode());
20827 if (Shuffle == X86ISD::MOVDDUP)
20828 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20830 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20831 DCI.AddToWorklist(Op.getNode());
20832 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20836 if (Subtarget->hasSSE3() &&
20837 (Mask.equals({0, 0, 2, 2}) || Mask.equals({1, 1, 3, 3}))) {
20838 bool Lo = Mask.equals({0, 0, 2, 2});
20839 unsigned Shuffle = Lo ? X86ISD::MOVSLDUP : X86ISD::MOVSHDUP;
20840 MVT ShuffleVT = MVT::v4f32;
20841 if (Depth == 1 && Root->getOpcode() == Shuffle)
20842 return false; // Nothing to do!
20843 Op = DAG.getBitcast(ShuffleVT, Input);
20844 DCI.AddToWorklist(Op.getNode());
20845 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op);
20846 DCI.AddToWorklist(Op.getNode());
20847 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20851 if (Mask.equals({0, 0, 1, 1}) || Mask.equals({2, 2, 3, 3})) {
20852 bool Lo = Mask.equals({0, 0, 1, 1});
20853 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20854 MVT ShuffleVT = MVT::v4f32;
20855 if (Depth == 1 && Root->getOpcode() == Shuffle)
20856 return false; // Nothing to do!
20857 Op = DAG.getBitcast(ShuffleVT, Input);
20858 DCI.AddToWorklist(Op.getNode());
20859 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20860 DCI.AddToWorklist(Op.getNode());
20861 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20867 // We always canonicalize the 8 x i16 and 16 x i8 shuffles into their UNPCK
20868 // variants as none of these have single-instruction variants that are
20869 // superior to the UNPCK formulation.
20870 if (!FloatDomain && VT.getSizeInBits() == 128 &&
20871 (Mask.equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
20872 Mask.equals({4, 4, 5, 5, 6, 6, 7, 7}) ||
20873 Mask.equals({0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7}) ||
20875 {8, 8, 9, 9, 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15}))) {
20876 bool Lo = Mask[0] == 0;
20877 unsigned Shuffle = Lo ? X86ISD::UNPCKL : X86ISD::UNPCKH;
20878 if (Depth == 1 && Root->getOpcode() == Shuffle)
20879 return false; // Nothing to do!
20881 switch (Mask.size()) {
20883 ShuffleVT = MVT::v8i16;
20886 ShuffleVT = MVT::v16i8;
20889 llvm_unreachable("Impossible mask size!");
20891 Op = DAG.getBitcast(ShuffleVT, Input);
20892 DCI.AddToWorklist(Op.getNode());
20893 Op = DAG.getNode(Shuffle, DL, ShuffleVT, Op, Op);
20894 DCI.AddToWorklist(Op.getNode());
20895 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20900 // Don't try to re-form single instruction chains under any circumstances now
20901 // that we've done encoding canonicalization for them.
20905 // If we have 3 or more shuffle instructions or a chain involving PSHUFB, we
20906 // can replace them with a single PSHUFB instruction profitably. Intel's
20907 // manuals suggest only using PSHUFB if doing so replacing 5 instructions, but
20908 // in practice PSHUFB tends to be *very* fast so we're more aggressive.
20909 if ((Depth >= 3 || HasPSHUFB) && Subtarget->hasSSSE3()) {
20910 SmallVector<SDValue, 16> PSHUFBMask;
20911 int NumBytes = VT.getSizeInBits() / 8;
20912 int Ratio = NumBytes / Mask.size();
20913 for (int i = 0; i < NumBytes; ++i) {
20914 if (Mask[i / Ratio] == SM_SentinelUndef) {
20915 PSHUFBMask.push_back(DAG.getUNDEF(MVT::i8));
20918 int M = Mask[i / Ratio] != SM_SentinelZero
20919 ? Ratio * Mask[i / Ratio] + i % Ratio
20921 PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));
20923 MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
20924 Op = DAG.getBitcast(ByteVT, Input);
20925 DCI.AddToWorklist(Op.getNode());
20926 SDValue PSHUFBMaskOp =
20927 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask);
20928 DCI.AddToWorklist(PSHUFBMaskOp.getNode());
20929 Op = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Op, PSHUFBMaskOp);
20930 DCI.AddToWorklist(Op.getNode());
20931 DCI.CombineTo(Root.getNode(), DAG.getBitcast(RootVT, Op),
20936 // Failed to find any combines.
20940 /// \brief Fully generic combining of x86 shuffle instructions.
20942 /// This should be the last combine run over the x86 shuffle instructions. Once
20943 /// they have been fully optimized, this will recursively consider all chains
20944 /// of single-use shuffle instructions, build a generic model of the cumulative
20945 /// shuffle operation, and check for simpler instructions which implement this
20946 /// operation. We use this primarily for two purposes:
20948 /// 1) Collapse generic shuffles to specialized single instructions when
20949 /// equivalent. In most cases, this is just an encoding size win, but
20950 /// sometimes we will collapse multiple generic shuffles into a single
20951 /// special-purpose shuffle.
20952 /// 2) Look for sequences of shuffle instructions with 3 or more total
20953 /// instructions, and replace them with the slightly more expensive SSSE3
20954 /// PSHUFB instruction if available. We do this as the last combining step
20955 /// to ensure we avoid using PSHUFB if we can implement the shuffle with
20956 /// a suitable short sequence of other instructions. The PHUFB will either
20957 /// use a register or have to read from memory and so is slightly (but only
20958 /// slightly) more expensive than the other shuffle instructions.
20960 /// Because this is inherently a quadratic operation (for each shuffle in
20961 /// a chain, we recurse up the chain), the depth is limited to 8 instructions.
20962 /// This should never be an issue in practice as the shuffle lowering doesn't
20963 /// produce sequences of more than 8 instructions.
20965 /// FIXME: We will currently miss some cases where the redundant shuffling
20966 /// would simplify under the threshold for PSHUFB formation because of
20967 /// combine-ordering. To fix this, we should do the redundant instruction
20968 /// combining in this recursive walk.
20969 static bool combineX86ShufflesRecursively(SDValue Op, SDValue Root,
20970 ArrayRef<int> RootMask,
20971 int Depth, bool HasPSHUFB,
20973 TargetLowering::DAGCombinerInfo &DCI,
20974 const X86Subtarget *Subtarget) {
20975 // Bound the depth of our recursive combine because this is ultimately
20976 // quadratic in nature.
20980 // Directly rip through bitcasts to find the underlying operand.
20981 while (Op.getOpcode() == ISD::BITCAST && Op.getOperand(0).hasOneUse())
20982 Op = Op.getOperand(0);
20984 MVT VT = Op.getSimpleValueType();
20985 if (!VT.isVector())
20986 return false; // Bail if we hit a non-vector.
20988 assert(Root.getSimpleValueType().isVector() &&
20989 "Shuffles operate on vector types!");
20990 assert(VT.getSizeInBits() == Root.getSimpleValueType().getSizeInBits() &&
20991 "Can only combine shuffles of the same vector register size.");
20993 if (!isTargetShuffle(Op.getOpcode()))
20995 SmallVector<int, 16> OpMask;
20997 bool HaveMask = getTargetShuffleMask(Op.getNode(), VT, OpMask, IsUnary);
20998 // We only can combine unary shuffles which we can decode the mask for.
20999 if (!HaveMask || !IsUnary)
21002 assert(VT.getVectorNumElements() == OpMask.size() &&
21003 "Different mask size from vector size!");
21004 assert(((RootMask.size() > OpMask.size() &&
21005 RootMask.size() % OpMask.size() == 0) ||
21006 (OpMask.size() > RootMask.size() &&
21007 OpMask.size() % RootMask.size() == 0) ||
21008 OpMask.size() == RootMask.size()) &&
21009 "The smaller number of elements must divide the larger.");
21010 int RootRatio = std::max<int>(1, OpMask.size() / RootMask.size());
21011 int OpRatio = std::max<int>(1, RootMask.size() / OpMask.size());
21012 assert(((RootRatio == 1 && OpRatio == 1) ||
21013 (RootRatio == 1) != (OpRatio == 1)) &&
21014 "Must not have a ratio for both incoming and op masks!");
21016 SmallVector<int, 16> Mask;
21017 Mask.reserve(std::max(OpMask.size(), RootMask.size()));
21019 // Merge this shuffle operation's mask into our accumulated mask. Note that
21020 // this shuffle's mask will be the first applied to the input, followed by the
21021 // root mask to get us all the way to the root value arrangement. The reason
21022 // for this order is that we are recursing up the operation chain.
21023 for (int i = 0, e = std::max(OpMask.size(), RootMask.size()); i < e; ++i) {
21024 int RootIdx = i / RootRatio;
21025 if (RootMask[RootIdx] < 0) {
21026 // This is a zero or undef lane, we're done.
21027 Mask.push_back(RootMask[RootIdx]);
21031 int RootMaskedIdx = RootMask[RootIdx] * RootRatio + i % RootRatio;
21032 int OpIdx = RootMaskedIdx / OpRatio;
21033 if (OpMask[OpIdx] < 0) {
21034 // The incoming lanes are zero or undef, it doesn't matter which ones we
21036 Mask.push_back(OpMask[OpIdx]);
21040 // Ok, we have non-zero lanes, map them through.
21041 Mask.push_back(OpMask[OpIdx] * OpRatio +
21042 RootMaskedIdx % OpRatio);
21045 // See if we can recurse into the operand to combine more things.
21046 switch (Op.getOpcode()) {
21047 case X86ISD::PSHUFB:
21049 case X86ISD::PSHUFD:
21050 case X86ISD::PSHUFHW:
21051 case X86ISD::PSHUFLW:
21052 if (Op.getOperand(0).hasOneUse() &&
21053 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21054 HasPSHUFB, DAG, DCI, Subtarget))
21058 case X86ISD::UNPCKL:
21059 case X86ISD::UNPCKH:
21060 assert(Op.getOperand(0) == Op.getOperand(1) && "We only combine unary shuffles!");
21061 // We can't check for single use, we have to check that this shuffle is the only user.
21062 if (Op->isOnlyUserOf(Op.getOperand(0).getNode()) &&
21063 combineX86ShufflesRecursively(Op.getOperand(0), Root, Mask, Depth + 1,
21064 HasPSHUFB, DAG, DCI, Subtarget))
21069 // Minor canonicalization of the accumulated shuffle mask to make it easier
21070 // to match below. All this does is detect masks with squential pairs of
21071 // elements, and shrink them to the half-width mask. It does this in a loop
21072 // so it will reduce the size of the mask to the minimal width mask which
21073 // performs an equivalent shuffle.
21074 SmallVector<int, 16> WidenedMask;
21075 while (Mask.size() > 1 && canWidenShuffleElements(Mask, WidenedMask)) {
21076 Mask = std::move(WidenedMask);
21077 WidenedMask.clear();
21080 return combineX86ShuffleChain(Op, Root, Mask, Depth, HasPSHUFB, DAG, DCI,
21084 /// \brief Get the PSHUF-style mask from PSHUF node.
21086 /// This is a very minor wrapper around getTargetShuffleMask to easy forming v4
21087 /// PSHUF-style masks that can be reused with such instructions.
21088 static SmallVector<int, 4> getPSHUFShuffleMask(SDValue N) {
21089 MVT VT = N.getSimpleValueType();
21090 SmallVector<int, 4> Mask;
21092 bool HaveMask = getTargetShuffleMask(N.getNode(), VT, Mask, IsUnary);
21096 // If we have more than 128-bits, only the low 128-bits of shuffle mask
21097 // matter. Check that the upper masks are repeats and remove them.
21098 if (VT.getSizeInBits() > 128) {
21099 int LaneElts = 128 / VT.getScalarSizeInBits();
21101 for (int i = 1, NumLanes = VT.getSizeInBits() / 128; i < NumLanes; ++i)
21102 for (int j = 0; j < LaneElts; ++j)
21103 assert(Mask[j] == Mask[i * LaneElts + j] - (LaneElts * i) &&
21104 "Mask doesn't repeat in high 128-bit lanes!");
21106 Mask.resize(LaneElts);
21109 switch (N.getOpcode()) {
21110 case X86ISD::PSHUFD:
21112 case X86ISD::PSHUFLW:
21115 case X86ISD::PSHUFHW:
21116 Mask.erase(Mask.begin(), Mask.begin() + 4);
21117 for (int &M : Mask)
21121 llvm_unreachable("No valid shuffle instruction found!");
21125 /// \brief Search for a combinable shuffle across a chain ending in pshufd.
21127 /// We walk up the chain and look for a combinable shuffle, skipping over
21128 /// shuffles that we could hoist this shuffle's transformation past without
21129 /// altering anything.
21131 combineRedundantDWordShuffle(SDValue N, MutableArrayRef<int> Mask,
21133 TargetLowering::DAGCombinerInfo &DCI) {
21134 assert(N.getOpcode() == X86ISD::PSHUFD &&
21135 "Called with something other than an x86 128-bit half shuffle!");
21138 // Walk up a single-use chain looking for a combinable shuffle. Keep a stack
21139 // of the shuffles in the chain so that we can form a fresh chain to replace
21141 SmallVector<SDValue, 8> Chain;
21142 SDValue V = N.getOperand(0);
21143 for (; V.hasOneUse(); V = V.getOperand(0)) {
21144 switch (V.getOpcode()) {
21146 return SDValue(); // Nothing combined!
21149 // Skip bitcasts as we always know the type for the target specific
21153 case X86ISD::PSHUFD:
21154 // Found another dword shuffle.
21157 case X86ISD::PSHUFLW:
21158 // Check that the low words (being shuffled) are the identity in the
21159 // dword shuffle, and the high words are self-contained.
21160 if (Mask[0] != 0 || Mask[1] != 1 ||
21161 !(Mask[2] >= 2 && Mask[2] < 4 && Mask[3] >= 2 && Mask[3] < 4))
21164 Chain.push_back(V);
21167 case X86ISD::PSHUFHW:
21168 // Check that the high words (being shuffled) are the identity in the
21169 // dword shuffle, and the low words are self-contained.
21170 if (Mask[2] != 2 || Mask[3] != 3 ||
21171 !(Mask[0] >= 0 && Mask[0] < 2 && Mask[1] >= 0 && Mask[1] < 2))
21174 Chain.push_back(V);
21177 case X86ISD::UNPCKL:
21178 case X86ISD::UNPCKH:
21179 // For either i8 -> i16 or i16 -> i32 unpacks, we can combine a dword
21180 // shuffle into a preceding word shuffle.
21181 if (V.getSimpleValueType().getScalarType() != MVT::i8 &&
21182 V.getSimpleValueType().getScalarType() != MVT::i16)
21185 // Search for a half-shuffle which we can combine with.
21186 unsigned CombineOp =
21187 V.getOpcode() == X86ISD::UNPCKL ? X86ISD::PSHUFLW : X86ISD::PSHUFHW;
21188 if (V.getOperand(0) != V.getOperand(1) ||
21189 !V->isOnlyUserOf(V.getOperand(0).getNode()))
21191 Chain.push_back(V);
21192 V = V.getOperand(0);
21194 switch (V.getOpcode()) {
21196 return SDValue(); // Nothing to combine.
21198 case X86ISD::PSHUFLW:
21199 case X86ISD::PSHUFHW:
21200 if (V.getOpcode() == CombineOp)
21203 Chain.push_back(V);
21207 V = V.getOperand(0);
21211 } while (V.hasOneUse());
21214 // Break out of the loop if we break out of the switch.
21218 if (!V.hasOneUse())
21219 // We fell out of the loop without finding a viable combining instruction.
21222 // Merge this node's mask and our incoming mask.
21223 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21224 for (int &M : Mask)
21226 V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),
21227 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21229 // Rebuild the chain around this new shuffle.
21230 while (!Chain.empty()) {
21231 SDValue W = Chain.pop_back_val();
21233 if (V.getValueType() != W.getOperand(0).getValueType())
21234 V = DAG.getBitcast(W.getOperand(0).getValueType(), V);
21236 switch (W.getOpcode()) {
21238 llvm_unreachable("Only PSHUF and UNPCK instructions get here!");
21240 case X86ISD::UNPCKL:
21241 case X86ISD::UNPCKH:
21242 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, V);
21245 case X86ISD::PSHUFD:
21246 case X86ISD::PSHUFLW:
21247 case X86ISD::PSHUFHW:
21248 V = DAG.getNode(W.getOpcode(), DL, W.getValueType(), V, W.getOperand(1));
21252 if (V.getValueType() != N.getValueType())
21253 V = DAG.getBitcast(N.getValueType(), V);
21255 // Return the new chain to replace N.
21259 /// \brief Search for a combinable shuffle across a chain ending in pshuflw or pshufhw.
21261 /// We walk up the chain, skipping shuffles of the other half and looking
21262 /// through shuffles which switch halves trying to find a shuffle of the same
21263 /// pair of dwords.
21264 static bool combineRedundantHalfShuffle(SDValue N, MutableArrayRef<int> Mask,
21266 TargetLowering::DAGCombinerInfo &DCI) {
21268 (N.getOpcode() == X86ISD::PSHUFLW || N.getOpcode() == X86ISD::PSHUFHW) &&
21269 "Called with something other than an x86 128-bit half shuffle!");
21271 unsigned CombineOpcode = N.getOpcode();
21273 // Walk up a single-use chain looking for a combinable shuffle.
21274 SDValue V = N.getOperand(0);
21275 for (; V.hasOneUse(); V = V.getOperand(0)) {
21276 switch (V.getOpcode()) {
21278 return false; // Nothing combined!
21281 // Skip bitcasts as we always know the type for the target specific
21285 case X86ISD::PSHUFLW:
21286 case X86ISD::PSHUFHW:
21287 if (V.getOpcode() == CombineOpcode)
21290 // Other-half shuffles are no-ops.
21293 // Break out of the loop if we break out of the switch.
21297 if (!V.hasOneUse())
21298 // We fell out of the loop without finding a viable combining instruction.
21301 // Combine away the bottom node as its shuffle will be accumulated into
21302 // a preceding shuffle.
21303 DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21305 // Record the old value.
21308 // Merge this node's mask and our incoming mask (adjusted to account for all
21309 // the pshufd instructions encountered).
21310 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21311 for (int &M : Mask)
21313 V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),
21314 getV4X86ShuffleImm8ForMask(Mask, DL, DAG));
21316 // Check that the shuffles didn't cancel each other out. If not, we need to
21317 // combine to the new one.
21319 // Replace the combinable shuffle with the combined one, updating all users
21320 // so that we re-evaluate the chain here.
21321 DCI.CombineTo(Old.getNode(), V, /*AddTo*/ true);
21326 /// \brief Try to combine x86 target specific shuffles.
21327 static SDValue PerformTargetShuffleCombine(SDValue N, SelectionDAG &DAG,
21328 TargetLowering::DAGCombinerInfo &DCI,
21329 const X86Subtarget *Subtarget) {
21331 MVT VT = N.getSimpleValueType();
21332 SmallVector<int, 4> Mask;
21334 switch (N.getOpcode()) {
21335 case X86ISD::PSHUFD:
21336 case X86ISD::PSHUFLW:
21337 case X86ISD::PSHUFHW:
21338 Mask = getPSHUFShuffleMask(N);
21339 assert(Mask.size() == 4);
21345 // Nuke no-op shuffles that show up after combining.
21346 if (isNoopShuffleMask(Mask))
21347 return DCI.CombineTo(N.getNode(), N.getOperand(0), /*AddTo*/ true);
21349 // Look for simplifications involving one or two shuffle instructions.
21350 SDValue V = N.getOperand(0);
21351 switch (N.getOpcode()) {
21354 case X86ISD::PSHUFLW:
21355 case X86ISD::PSHUFHW:
21356 assert(VT.getScalarType() == MVT::i16 && "Bad word shuffle type!");
21358 if (combineRedundantHalfShuffle(N, Mask, DAG, DCI))
21359 return SDValue(); // We combined away this shuffle, so we're done.
21361 // See if this reduces to a PSHUFD which is no more expensive and can
21362 // combine with more operations. Note that it has to at least flip the
21363 // dwords as otherwise it would have been removed as a no-op.
21364 if (makeArrayRef(Mask).equals({2, 3, 0, 1})) {
21365 int DMask[] = {0, 1, 2, 3};
21366 int DOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 2;
21367 DMask[DOffset + 0] = DOffset + 1;
21368 DMask[DOffset + 1] = DOffset + 0;
21369 MVT DVT = MVT::getVectorVT(MVT::i32, VT.getVectorNumElements() / 2);
21370 V = DAG.getBitcast(DVT, V);
21371 DCI.AddToWorklist(V.getNode());
21372 V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,
21373 getV4X86ShuffleImm8ForMask(DMask, DL, DAG));
21374 DCI.AddToWorklist(V.getNode());
21375 return DAG.getBitcast(VT, V);
21378 // Look for shuffle patterns which can be implemented as a single unpack.
21379 // FIXME: This doesn't handle the location of the PSHUFD generically, and
21380 // only works when we have a PSHUFD followed by two half-shuffles.
21381 if (Mask[0] == Mask[1] && Mask[2] == Mask[3] &&
21382 (V.getOpcode() == X86ISD::PSHUFLW ||
21383 V.getOpcode() == X86ISD::PSHUFHW) &&
21384 V.getOpcode() != N.getOpcode() &&
21386 SDValue D = V.getOperand(0);
21387 while (D.getOpcode() == ISD::BITCAST && D.hasOneUse())
21388 D = D.getOperand(0);
21389 if (D.getOpcode() == X86ISD::PSHUFD && D.hasOneUse()) {
21390 SmallVector<int, 4> VMask = getPSHUFShuffleMask(V);
21391 SmallVector<int, 4> DMask = getPSHUFShuffleMask(D);
21392 int NOffset = N.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21393 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4;
21395 for (int i = 0; i < 4; ++i) {
21396 WordMask[i + NOffset] = Mask[i] + NOffset;
21397 WordMask[i + VOffset] = VMask[i] + VOffset;
21399 // Map the word mask through the DWord mask.
21401 for (int i = 0; i < 8; ++i)
21402 MappedMask[i] = 2 * DMask[WordMask[i] / 2] + WordMask[i] % 2;
21403 if (makeArrayRef(MappedMask).equals({0, 0, 1, 1, 2, 2, 3, 3}) ||
21404 makeArrayRef(MappedMask).equals({4, 4, 5, 5, 6, 6, 7, 7})) {
21405 // We can replace all three shuffles with an unpack.
21406 V = DAG.getBitcast(VT, D.getOperand(0));
21407 DCI.AddToWorklist(V.getNode());
21408 return DAG.getNode(MappedMask[0] == 0 ? X86ISD::UNPCKL
21417 case X86ISD::PSHUFD:
21418 if (SDValue NewN = combineRedundantDWordShuffle(N, Mask, DAG, DCI))
21427 /// \brief Try to combine a shuffle into a target-specific add-sub node.
21429 /// We combine this directly on the abstract vector shuffle nodes so it is
21430 /// easier to generically match. We also insert dummy vector shuffle nodes for
21431 /// the operands which explicitly discard the lanes which are unused by this
21432 /// operation to try to flow through the rest of the combiner the fact that
21433 /// they're unused.
21434 static SDValue combineShuffleToAddSub(SDNode *N, SelectionDAG &DAG) {
21436 EVT VT = N->getValueType(0);
21438 // We only handle target-independent shuffles.
21439 // FIXME: It would be easy and harmless to use the target shuffle mask
21440 // extraction tool to support more.
21441 if (N->getOpcode() != ISD::VECTOR_SHUFFLE)
21444 auto *SVN = cast<ShuffleVectorSDNode>(N);
21445 ArrayRef<int> Mask = SVN->getMask();
21446 SDValue V1 = N->getOperand(0);
21447 SDValue V2 = N->getOperand(1);
21449 // We require the first shuffle operand to be the SUB node, and the second to
21450 // be the ADD node.
21451 // FIXME: We should support the commuted patterns.
21452 if (V1->getOpcode() != ISD::FSUB || V2->getOpcode() != ISD::FADD)
21455 // If there are other uses of these operations we can't fold them.
21456 if (!V1->hasOneUse() || !V2->hasOneUse())
21459 // Ensure that both operations have the same operands. Note that we can
21460 // commute the FADD operands.
21461 SDValue LHS = V1->getOperand(0), RHS = V1->getOperand(1);
21462 if ((V2->getOperand(0) != LHS || V2->getOperand(1) != RHS) &&
21463 (V2->getOperand(0) != RHS || V2->getOperand(1) != LHS))
21466 // We're looking for blends between FADD and FSUB nodes. We insist on these
21467 // nodes being lined up in a specific expected pattern.
21468 if (!(isShuffleEquivalent(V1, V2, Mask, {0, 3}) ||
21469 isShuffleEquivalent(V1, V2, Mask, {0, 5, 2, 7}) ||
21470 isShuffleEquivalent(V1, V2, Mask, {0, 9, 2, 11, 4, 13, 6, 15})))
21473 // Only specific types are legal at this point, assert so we notice if and
21474 // when these change.
21475 assert((VT == MVT::v4f32 || VT == MVT::v2f64 || VT == MVT::v8f32 ||
21476 VT == MVT::v4f64) &&
21477 "Unknown vector type encountered!");
21479 return DAG.getNode(X86ISD::ADDSUB, DL, VT, LHS, RHS);
21482 /// PerformShuffleCombine - Performs several different shuffle combines.
21483 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
21484 TargetLowering::DAGCombinerInfo &DCI,
21485 const X86Subtarget *Subtarget) {
21487 SDValue N0 = N->getOperand(0);
21488 SDValue N1 = N->getOperand(1);
21489 EVT VT = N->getValueType(0);
21491 // Don't create instructions with illegal types after legalize types has run.
21492 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21493 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
21496 // If we have legalized the vector types, look for blends of FADD and FSUB
21497 // nodes that we can fuse into an ADDSUB node.
21498 if (TLI.isTypeLegal(VT) && Subtarget->hasSSE3())
21499 if (SDValue AddSub = combineShuffleToAddSub(N, DAG))
21502 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
21503 if (Subtarget->hasFp256() && VT.is256BitVector() &&
21504 N->getOpcode() == ISD::VECTOR_SHUFFLE)
21505 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
21507 // During Type Legalization, when promoting illegal vector types,
21508 // the backend might introduce new shuffle dag nodes and bitcasts.
21510 // This code performs the following transformation:
21511 // fold: (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
21512 // (shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
21514 // We do this only if both the bitcast and the BINOP dag nodes have
21515 // one use. Also, perform this transformation only if the new binary
21516 // operation is legal. This is to avoid introducing dag nodes that
21517 // potentially need to be further expanded (or custom lowered) into a
21518 // less optimal sequence of dag nodes.
21519 if (!DCI.isBeforeLegalize() && DCI.isBeforeLegalizeOps() &&
21520 N1.getOpcode() == ISD::UNDEF && N0.hasOneUse() &&
21521 N0.getOpcode() == ISD::BITCAST) {
21522 SDValue BC0 = N0.getOperand(0);
21523 EVT SVT = BC0.getValueType();
21524 unsigned Opcode = BC0.getOpcode();
21525 unsigned NumElts = VT.getVectorNumElements();
21527 if (BC0.hasOneUse() && SVT.isVector() &&
21528 SVT.getVectorNumElements() * 2 == NumElts &&
21529 TLI.isOperationLegal(Opcode, VT)) {
21530 bool CanFold = false;
21542 unsigned SVTNumElts = SVT.getVectorNumElements();
21543 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
21544 for (unsigned i = 0, e = SVTNumElts; i != e && CanFold; ++i)
21545 CanFold = SVOp->getMaskElt(i) == (int)(i * 2);
21546 for (unsigned i = SVTNumElts, e = NumElts; i != e && CanFold; ++i)
21547 CanFold = SVOp->getMaskElt(i) < 0;
21550 SDValue BC00 = DAG.getBitcast(VT, BC0.getOperand(0));
21551 SDValue BC01 = DAG.getBitcast(VT, BC0.getOperand(1));
21552 SDValue NewBinOp = DAG.getNode(BC0.getOpcode(), dl, VT, BC00, BC01);
21553 return DAG.getVectorShuffle(VT, dl, NewBinOp, N1, &SVOp->getMask()[0]);
21558 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
21559 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
21560 // consecutive, non-overlapping, and in the right order.
21561 SmallVector<SDValue, 16> Elts;
21562 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
21563 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
21565 if (SDValue LD = EltsFromConsecutiveLoads(VT, Elts, dl, DAG, true))
21568 if (isTargetShuffle(N->getOpcode())) {
21570 PerformTargetShuffleCombine(SDValue(N, 0), DAG, DCI, Subtarget);
21571 if (Shuffle.getNode())
21574 // Try recursively combining arbitrary sequences of x86 shuffle
21575 // instructions into higher-order shuffles. We do this after combining
21576 // specific PSHUF instruction sequences into their minimal form so that we
21577 // can evaluate how many specialized shuffle instructions are involved in
21578 // a particular chain.
21579 SmallVector<int, 1> NonceMask; // Just a placeholder.
21580 NonceMask.push_back(0);
21581 if (combineX86ShufflesRecursively(SDValue(N, 0), SDValue(N, 0), NonceMask,
21582 /*Depth*/ 1, /*HasPSHUFB*/ false, DAG,
21584 return SDValue(); // This routine will use CombineTo to replace N.
21590 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
21591 /// specific shuffle of a load can be folded into a single element load.
21592 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
21593 /// shuffles have been custom lowered so we need to handle those here.
21594 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
21595 TargetLowering::DAGCombinerInfo &DCI) {
21596 if (DCI.isBeforeLegalizeOps())
21599 SDValue InVec = N->getOperand(0);
21600 SDValue EltNo = N->getOperand(1);
21602 if (!isa<ConstantSDNode>(EltNo))
21605 EVT OriginalVT = InVec.getValueType();
21607 if (InVec.getOpcode() == ISD::BITCAST) {
21608 // Don't duplicate a load with other uses.
21609 if (!InVec.hasOneUse())
21611 EVT BCVT = InVec.getOperand(0).getValueType();
21612 if (!BCVT.isVector() ||
21613 BCVT.getVectorNumElements() != OriginalVT.getVectorNumElements())
21615 InVec = InVec.getOperand(0);
21618 EVT CurrentVT = InVec.getValueType();
21620 if (!isTargetShuffle(InVec.getOpcode()))
21623 // Don't duplicate a load with other uses.
21624 if (!InVec.hasOneUse())
21627 SmallVector<int, 16> ShuffleMask;
21629 if (!getTargetShuffleMask(InVec.getNode(), CurrentVT.getSimpleVT(),
21630 ShuffleMask, UnaryShuffle))
21633 // Select the input vector, guarding against out of range extract vector.
21634 unsigned NumElems = CurrentVT.getVectorNumElements();
21635 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
21636 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
21637 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
21638 : InVec.getOperand(1);
21640 // If inputs to shuffle are the same for both ops, then allow 2 uses
21641 unsigned AllowedUses = InVec.getNumOperands() > 1 &&
21642 InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
21644 if (LdNode.getOpcode() == ISD::BITCAST) {
21645 // Don't duplicate a load with other uses.
21646 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
21649 AllowedUses = 1; // only allow 1 load use if we have a bitcast
21650 LdNode = LdNode.getOperand(0);
21653 if (!ISD::isNormalLoad(LdNode.getNode()))
21656 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
21658 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
21661 EVT EltVT = N->getValueType(0);
21662 // If there's a bitcast before the shuffle, check if the load type and
21663 // alignment is valid.
21664 unsigned Align = LN0->getAlignment();
21665 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21666 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
21667 EltVT.getTypeForEVT(*DAG.getContext()));
21669 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, EltVT))
21672 // All checks match so transform back to vector_shuffle so that DAG combiner
21673 // can finish the job
21676 // Create shuffle node taking into account the case that its a unary shuffle
21677 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(CurrentVT)
21678 : InVec.getOperand(1);
21679 Shuffle = DAG.getVectorShuffle(CurrentVT, dl,
21680 InVec.getOperand(0), Shuffle,
21682 Shuffle = DAG.getBitcast(OriginalVT, Shuffle);
21683 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
21687 /// \brief Detect bitcasts between i32 to x86mmx low word. Since MMX types are
21688 /// special and don't usually play with other vector types, it's better to
21689 /// handle them early to be sure we emit efficient code by avoiding
21690 /// store-load conversions.
21691 static SDValue PerformBITCASTCombine(SDNode *N, SelectionDAG &DAG) {
21692 if (N->getValueType(0) != MVT::x86mmx ||
21693 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR ||
21694 N->getOperand(0)->getValueType(0) != MVT::v2i32)
21697 SDValue V = N->getOperand(0);
21698 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(1));
21699 if (C && C->getZExtValue() == 0 && V.getOperand(0).getValueType() == MVT::i32)
21700 return DAG.getNode(X86ISD::MMX_MOVW2D, SDLoc(V.getOperand(0)),
21701 N->getValueType(0), V.getOperand(0));
21706 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
21707 /// generation and convert it from being a bunch of shuffles and extracts
21708 /// into a somewhat faster sequence. For i686, the best sequence is apparently
21709 /// storing the value and loading scalars back, while for x64 we should
21710 /// use 64-bit extracts and shifts.
21711 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
21712 TargetLowering::DAGCombinerInfo &DCI) {
21713 if (SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI))
21716 SDValue InputVector = N->getOperand(0);
21717 SDLoc dl(InputVector);
21718 // Detect mmx to i32 conversion through a v2i32 elt extract.
21719 if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
21720 N->getValueType(0) == MVT::i32 &&
21721 InputVector.getValueType() == MVT::v2i32) {
21723 // The bitcast source is a direct mmx result.
21724 SDValue MMXSrc = InputVector.getNode()->getOperand(0);
21725 if (MMXSrc.getValueType() == MVT::x86mmx)
21726 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21727 N->getValueType(0),
21728 InputVector.getNode()->getOperand(0));
21730 // The mmx is indirect: (i64 extract_elt (v1i64 bitcast (x86mmx ...))).
21731 SDValue MMXSrcOp = MMXSrc.getOperand(0);
21732 if (MMXSrc.getOpcode() == ISD::EXTRACT_VECTOR_ELT && MMXSrc.hasOneUse() &&
21733 MMXSrc.getValueType() == MVT::i64 && MMXSrcOp.hasOneUse() &&
21734 MMXSrcOp.getOpcode() == ISD::BITCAST &&
21735 MMXSrcOp.getValueType() == MVT::v1i64 &&
21736 MMXSrcOp.getOperand(0).getValueType() == MVT::x86mmx)
21737 return DAG.getNode(X86ISD::MMX_MOVD2W, SDLoc(InputVector),
21738 N->getValueType(0),
21739 MMXSrcOp.getOperand(0));
21742 EVT VT = N->getValueType(0);
21744 if (VT == MVT::i1 && dyn_cast<ConstantSDNode>(N->getOperand(1)) &&
21745 InputVector.getOpcode() == ISD::BITCAST &&
21746 dyn_cast<ConstantSDNode>(InputVector.getOperand(0))) {
21747 uint64_t ExtractedElt =
21748 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
21749 uint64_t InputValue =
21750 cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
21751 uint64_t Res = (InputValue >> ExtractedElt) & 1;
21752 return DAG.getConstant(Res, dl, MVT::i1);
21754 // Only operate on vectors of 4 elements, where the alternative shuffling
21755 // gets to be more expensive.
21756 if (InputVector.getValueType() != MVT::v4i32)
21759 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
21760 // single use which is a sign-extend or zero-extend, and all elements are
21762 SmallVector<SDNode *, 4> Uses;
21763 unsigned ExtractedElements = 0;
21764 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
21765 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
21766 if (UI.getUse().getResNo() != InputVector.getResNo())
21769 SDNode *Extract = *UI;
21770 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
21773 if (Extract->getValueType(0) != MVT::i32)
21775 if (!Extract->hasOneUse())
21777 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
21778 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
21780 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
21783 // Record which element was extracted.
21784 ExtractedElements |=
21785 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
21787 Uses.push_back(Extract);
21790 // If not all the elements were used, this may not be worthwhile.
21791 if (ExtractedElements != 15)
21794 // Ok, we've now decided to do the transformation.
21795 // If 64-bit shifts are legal, use the extract-shift sequence,
21796 // otherwise bounce the vector off the cache.
21797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21800 if (TLI.isOperationLegal(ISD::SRA, MVT::i64)) {
21801 SDValue Cst = DAG.getBitcast(MVT::v2i64, InputVector);
21802 EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();
21803 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21804 DAG.getConstant(0, dl, VecIdxTy));
21805 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,
21806 DAG.getConstant(1, dl, VecIdxTy));
21808 SDValue ShAmt = DAG.getConstant(32, dl,
21809 DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));
21810 Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);
21811 Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21812 DAG.getNode(ISD::SRA, dl, MVT::i64, BottomHalf, ShAmt));
21813 Vals[2] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, TopHalf);
21814 Vals[3] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
21815 DAG.getNode(ISD::SRA, dl, MVT::i64, TopHalf, ShAmt));
21817 // Store the value to a temporary stack slot.
21818 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
21819 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
21820 MachinePointerInfo(), false, false, 0);
21822 EVT ElementType = InputVector.getValueType().getVectorElementType();
21823 unsigned EltSize = ElementType.getSizeInBits() / 8;
21825 // Replace each use (extract) with a load of the appropriate element.
21826 for (unsigned i = 0; i < 4; ++i) {
21827 uint64_t Offset = EltSize * i;
21828 SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());
21830 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
21831 StackPtr, OffsetVal);
21833 // Load the scalar.
21834 Vals[i] = DAG.getLoad(ElementType, dl, Ch,
21835 ScalarAddr, MachinePointerInfo(),
21836 false, false, false, 0);
21841 // Replace the extracts
21842 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
21843 UE = Uses.end(); UI != UE; ++UI) {
21844 SDNode *Extract = *UI;
21846 SDValue Idx = Extract->getOperand(1);
21847 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
21848 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
21851 // The replacement was made in place; don't return anything.
21855 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
21856 static std::pair<unsigned, bool>
21857 matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
21858 SelectionDAG &DAG, const X86Subtarget *Subtarget) {
21859 if (!VT.isVector())
21860 return std::make_pair(0, false);
21862 bool NeedSplit = false;
21863 switch (VT.getSimpleVT().SimpleTy) {
21864 default: return std::make_pair(0, false);
21867 if (!Subtarget->hasVLX())
21868 return std::make_pair(0, false);
21872 if (!Subtarget->hasBWI())
21873 return std::make_pair(0, false);
21877 if (!Subtarget->hasAVX512())
21878 return std::make_pair(0, false);
21883 if (!Subtarget->hasAVX2())
21885 if (!Subtarget->hasAVX())
21886 return std::make_pair(0, false);
21891 if (!Subtarget->hasSSE2())
21892 return std::make_pair(0, false);
21895 // SSE2 has only a small subset of the operations.
21896 bool hasUnsigned = Subtarget->hasSSE41() ||
21897 (Subtarget->hasSSE2() && VT == MVT::v16i8);
21898 bool hasSigned = Subtarget->hasSSE41() ||
21899 (Subtarget->hasSSE2() && VT == MVT::v8i16);
21901 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
21904 // Check for x CC y ? x : y.
21905 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
21906 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
21911 Opc = hasUnsigned ? ISD::UMIN : 0; break;
21914 Opc = hasUnsigned ? ISD::UMAX : 0; break;
21917 Opc = hasSigned ? ISD::SMIN : 0; break;
21920 Opc = hasSigned ? ISD::SMAX : 0; break;
21922 // Check for x CC y ? y : x -- a min/max with reversed arms.
21923 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
21924 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
21929 Opc = hasUnsigned ? ISD::UMAX : 0; break;
21932 Opc = hasUnsigned ? ISD::UMIN : 0; break;
21935 Opc = hasSigned ? ISD::SMAX : 0; break;
21938 Opc = hasSigned ? ISD::SMIN : 0; break;
21942 return std::make_pair(Opc, NeedSplit);
21946 transformVSELECTtoBlendVECTOR_SHUFFLE(SDNode *N, SelectionDAG &DAG,
21947 const X86Subtarget *Subtarget) {
21949 SDValue Cond = N->getOperand(0);
21950 SDValue LHS = N->getOperand(1);
21951 SDValue RHS = N->getOperand(2);
21953 if (Cond.getOpcode() == ISD::SIGN_EXTEND) {
21954 SDValue CondSrc = Cond->getOperand(0);
21955 if (CondSrc->getOpcode() == ISD::SIGN_EXTEND_INREG)
21956 Cond = CondSrc->getOperand(0);
21959 if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
21962 // A vselect where all conditions and data are constants can be optimized into
21963 // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
21964 if (ISD::isBuildVectorOfConstantSDNodes(LHS.getNode()) &&
21965 ISD::isBuildVectorOfConstantSDNodes(RHS.getNode()))
21968 unsigned MaskValue = 0;
21969 if (!BUILD_VECTORtoBlendMask(cast<BuildVectorSDNode>(Cond), MaskValue))
21972 MVT VT = N->getSimpleValueType(0);
21973 unsigned NumElems = VT.getVectorNumElements();
21974 SmallVector<int, 8> ShuffleMask(NumElems, -1);
21975 for (unsigned i = 0; i < NumElems; ++i) {
21976 // Be sure we emit undef where we can.
21977 if (Cond.getOperand(i)->getOpcode() == ISD::UNDEF)
21978 ShuffleMask[i] = -1;
21980 ShuffleMask[i] = i + NumElems * ((MaskValue >> i) & 1);
21983 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
21984 if (!TLI.isShuffleMaskLegal(ShuffleMask, VT))
21986 return DAG.getVectorShuffle(VT, dl, LHS, RHS, &ShuffleMask[0]);
21989 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
21991 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
21992 TargetLowering::DAGCombinerInfo &DCI,
21993 const X86Subtarget *Subtarget) {
21995 SDValue Cond = N->getOperand(0);
21996 // Get the LHS/RHS of the select.
21997 SDValue LHS = N->getOperand(1);
21998 SDValue RHS = N->getOperand(2);
21999 EVT VT = LHS.getValueType();
22000 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
22002 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
22003 // instructions match the semantics of the common C idiom x<y?x:y but not
22004 // x<=y?x:y, because of how they handle negative zero (which can be
22005 // ignored in unsafe-math mode).
22006 // We also try to create v2f32 min/max nodes, which we later widen to v4f32.
22007 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
22008 VT != MVT::f80 && (TLI.isTypeLegal(VT) || VT == MVT::v2f32) &&
22009 (Subtarget->hasSSE2() ||
22010 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
22011 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22013 unsigned Opcode = 0;
22014 // Check for x CC y ? x : y.
22015 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22016 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22020 // Converting this to a min would handle NaNs incorrectly, and swapping
22021 // the operands would cause it to handle comparisons between positive
22022 // and negative zero incorrectly.
22023 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22024 if (!DAG.getTarget().Options.UnsafeFPMath &&
22025 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22027 std::swap(LHS, RHS);
22029 Opcode = X86ISD::FMIN;
22032 // Converting this to a min would handle comparisons between positive
22033 // and negative zero incorrectly.
22034 if (!DAG.getTarget().Options.UnsafeFPMath &&
22035 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22037 Opcode = X86ISD::FMIN;
22040 // Converting this to a min would handle both negative zeros and NaNs
22041 // incorrectly, but we can swap the operands to fix both.
22042 std::swap(LHS, RHS);
22046 Opcode = X86ISD::FMIN;
22050 // Converting this to a max would handle comparisons between positive
22051 // and negative zero incorrectly.
22052 if (!DAG.getTarget().Options.UnsafeFPMath &&
22053 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
22055 Opcode = X86ISD::FMAX;
22058 // Converting this to a max would handle NaNs incorrectly, and swapping
22059 // the operands would cause it to handle comparisons between positive
22060 // and negative zero incorrectly.
22061 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
22062 if (!DAG.getTarget().Options.UnsafeFPMath &&
22063 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
22065 std::swap(LHS, RHS);
22067 Opcode = X86ISD::FMAX;
22070 // Converting this to a max would handle both negative zeros and NaNs
22071 // incorrectly, but we can swap the operands to fix both.
22072 std::swap(LHS, RHS);
22076 Opcode = X86ISD::FMAX;
22079 // Check for x CC y ? y : x -- a min/max with reversed arms.
22080 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
22081 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
22085 // Converting this to a min would handle comparisons between positive
22086 // and negative zero incorrectly, and swapping the operands would
22087 // cause it to handle NaNs incorrectly.
22088 if (!DAG.getTarget().Options.UnsafeFPMath &&
22089 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
22090 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22092 std::swap(LHS, RHS);
22094 Opcode = X86ISD::FMIN;
22097 // Converting this to a min would handle NaNs incorrectly.
22098 if (!DAG.getTarget().Options.UnsafeFPMath &&
22099 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
22101 Opcode = X86ISD::FMIN;
22104 // Converting this to a min would handle both negative zeros and NaNs
22105 // incorrectly, but we can swap the operands to fix both.
22106 std::swap(LHS, RHS);
22110 Opcode = X86ISD::FMIN;
22114 // Converting this to a max would handle NaNs incorrectly.
22115 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22117 Opcode = X86ISD::FMAX;
22120 // Converting this to a max would handle comparisons between positive
22121 // and negative zero incorrectly, and swapping the operands would
22122 // cause it to handle NaNs incorrectly.
22123 if (!DAG.getTarget().Options.UnsafeFPMath &&
22124 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
22125 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
22127 std::swap(LHS, RHS);
22129 Opcode = X86ISD::FMAX;
22132 // Converting this to a max would handle both negative zeros and NaNs
22133 // incorrectly, but we can swap the operands to fix both.
22134 std::swap(LHS, RHS);
22138 Opcode = X86ISD::FMAX;
22144 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
22147 EVT CondVT = Cond.getValueType();
22148 if (Subtarget->hasAVX512() && VT.isVector() && CondVT.isVector() &&
22149 CondVT.getVectorElementType() == MVT::i1) {
22150 // v16i8 (select v16i1, v16i8, v16i8) does not have a proper
22151 // lowering on KNL. In this case we convert it to
22152 // v16i8 (select v16i8, v16i8, v16i8) and use AVX instruction.
22153 // The same situation for all 128 and 256-bit vectors of i8 and i16.
22154 // Since SKX these selects have a proper lowering.
22155 EVT OpVT = LHS.getValueType();
22156 if ((OpVT.is128BitVector() || OpVT.is256BitVector()) &&
22157 (OpVT.getVectorElementType() == MVT::i8 ||
22158 OpVT.getVectorElementType() == MVT::i16) &&
22159 !(Subtarget->hasBWI() && Subtarget->hasVLX())) {
22160 Cond = DAG.getNode(ISD::SIGN_EXTEND, DL, OpVT, Cond);
22161 DCI.AddToWorklist(Cond.getNode());
22162 return DAG.getNode(N->getOpcode(), DL, OpVT, Cond, LHS, RHS);
22165 // If this is a select between two integer constants, try to do some
22167 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
22168 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
22169 // Don't do this for crazy integer types.
22170 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
22171 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
22172 // so that TrueC (the true value) is larger than FalseC.
22173 bool NeedsCondInvert = false;
22175 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
22176 // Efficiently invertible.
22177 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
22178 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
22179 isa<ConstantSDNode>(Cond.getOperand(1))))) {
22180 NeedsCondInvert = true;
22181 std::swap(TrueC, FalseC);
22184 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
22185 if (FalseC->getAPIntValue() == 0 &&
22186 TrueC->getAPIntValue().isPowerOf2()) {
22187 if (NeedsCondInvert) // Invert the condition if needed.
22188 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22189 DAG.getConstant(1, DL, Cond.getValueType()));
22191 // Zero extend the condition if needed.
22192 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
22194 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22195 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
22196 DAG.getConstant(ShAmt, DL, MVT::i8));
22199 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
22200 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22201 if (NeedsCondInvert) // Invert the condition if needed.
22202 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22203 DAG.getConstant(1, DL, Cond.getValueType()));
22205 // Zero extend the condition if needed.
22206 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22207 FalseC->getValueType(0), Cond);
22208 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22209 SDValue(FalseC, 0));
22212 // Optimize cases that will turn into an LEA instruction. This requires
22213 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22214 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22215 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22216 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22218 bool isFastMultiplier = false;
22220 switch ((unsigned char)Diff) {
22222 case 1: // result = add base, cond
22223 case 2: // result = lea base( , cond*2)
22224 case 3: // result = lea base(cond, cond*2)
22225 case 4: // result = lea base( , cond*4)
22226 case 5: // result = lea base(cond, cond*4)
22227 case 8: // result = lea base( , cond*8)
22228 case 9: // result = lea base(cond, cond*8)
22229 isFastMultiplier = true;
22234 if (isFastMultiplier) {
22235 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22236 if (NeedsCondInvert) // Invert the condition if needed.
22237 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
22238 DAG.getConstant(1, DL, Cond.getValueType()));
22240 // Zero extend the condition if needed.
22241 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22243 // Scale the condition by the difference.
22245 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22246 DAG.getConstant(Diff, DL,
22247 Cond.getValueType()));
22249 // Add the base if non-zero.
22250 if (FalseC->getAPIntValue() != 0)
22251 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22252 SDValue(FalseC, 0));
22259 // Canonicalize max and min:
22260 // (x > y) ? x : y -> (x >= y) ? x : y
22261 // (x < y) ? x : y -> (x <= y) ? x : y
22262 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
22263 // the need for an extra compare
22264 // against zero. e.g.
22265 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
22267 // testl %edi, %edi
22269 // cmovgl %edi, %eax
22273 // cmovsl %eax, %edi
22274 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
22275 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
22276 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
22277 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22282 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
22283 Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
22284 Cond.getOperand(0), Cond.getOperand(1), NewCC);
22285 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
22290 // Early exit check
22291 if (!TLI.isTypeLegal(VT))
22294 // Match VSELECTs into subs with unsigned saturation.
22295 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
22296 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
22297 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
22298 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
22299 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
22301 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
22302 // left side invert the predicate to simplify logic below.
22304 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
22306 CC = ISD::getSetCCInverse(CC, true);
22307 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
22311 if (Other.getNode() && Other->getNumOperands() == 2 &&
22312 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
22313 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
22314 SDValue CondRHS = Cond->getOperand(1);
22316 // Look for a general sub with unsigned saturation first.
22317 // x >= y ? x-y : 0 --> subus x, y
22318 // x > y ? x-y : 0 --> subus x, y
22319 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
22320 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
22321 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
22323 if (auto *OpRHSBV = dyn_cast<BuildVectorSDNode>(OpRHS))
22324 if (auto *OpRHSConst = OpRHSBV->getConstantSplatNode()) {
22325 if (auto *CondRHSBV = dyn_cast<BuildVectorSDNode>(CondRHS))
22326 if (auto *CondRHSConst = CondRHSBV->getConstantSplatNode())
22327 // If the RHS is a constant we have to reverse the const
22328 // canonicalization.
22329 // x > C-1 ? x+-C : 0 --> subus x, C
22330 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
22331 CondRHSConst->getAPIntValue() ==
22332 (-OpRHSConst->getAPIntValue() - 1))
22333 return DAG.getNode(
22334 X86ISD::SUBUS, DL, VT, OpLHS,
22335 DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));
22337 // Another special case: If C was a sign bit, the sub has been
22338 // canonicalized into a xor.
22339 // FIXME: Would it be better to use computeKnownBits to determine
22340 // whether it's safe to decanonicalize the xor?
22341 // x s< 0 ? x^C : 0 --> subus x, C
22342 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
22343 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
22344 OpRHSConst->getAPIntValue().isSignBit())
22345 // Note that we have to rebuild the RHS constant here to ensure we
22346 // don't rely on particular values of undef lanes.
22347 return DAG.getNode(
22348 X86ISD::SUBUS, DL, VT, OpLHS,
22349 DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));
22354 // Try to match a min/max vector operation.
22355 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC) {
22356 std::pair<unsigned, bool> ret = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget);
22357 unsigned Opc = ret.first;
22358 bool NeedSplit = ret.second;
22360 if (Opc && NeedSplit) {
22361 unsigned NumElems = VT.getVectorNumElements();
22362 // Extract the LHS vectors
22363 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, DL);
22364 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, DL);
22366 // Extract the RHS vectors
22367 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, DL);
22368 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, DL);
22370 // Create min/max for each subvector
22371 LHS = DAG.getNode(Opc, DL, LHS1.getValueType(), LHS1, RHS1);
22372 RHS = DAG.getNode(Opc, DL, LHS2.getValueType(), LHS2, RHS2);
22374 // Merge the result
22375 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LHS, RHS);
22377 return DAG.getNode(Opc, DL, VT, LHS, RHS);
22380 // Simplify vector selection if condition value type matches vselect
22382 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
22383 assert(Cond.getValueType().isVector() &&
22384 "vector select expects a vector selector!");
22386 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
22387 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
22389 // Try invert the condition if true value is not all 1s and false value
22391 if (!TValIsAllOnes && !FValIsAllZeros &&
22392 // Check if the selector will be produced by CMPP*/PCMP*
22393 Cond.getOpcode() == ISD::SETCC &&
22394 // Check if SETCC has already been promoted
22395 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT) {
22396 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
22397 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
22399 if (TValIsAllZeros || FValIsAllOnes) {
22400 SDValue CC = Cond.getOperand(2);
22401 ISD::CondCode NewCC =
22402 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
22403 Cond.getOperand(0).getValueType().isInteger());
22404 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
22405 std::swap(LHS, RHS);
22406 TValIsAllOnes = FValIsAllOnes;
22407 FValIsAllZeros = TValIsAllZeros;
22411 if (TValIsAllOnes || FValIsAllZeros) {
22414 if (TValIsAllOnes && FValIsAllZeros)
22416 else if (TValIsAllOnes)
22418 DAG.getNode(ISD::OR, DL, CondVT, Cond, DAG.getBitcast(CondVT, RHS));
22419 else if (FValIsAllZeros)
22420 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
22421 DAG.getBitcast(CondVT, LHS));
22423 return DAG.getBitcast(VT, Ret);
22427 // We should generate an X86ISD::BLENDI from a vselect if its argument
22428 // is a sign_extend_inreg of an any_extend of a BUILD_VECTOR of
22429 // constants. This specific pattern gets generated when we split a
22430 // selector for a 512 bit vector in a machine without AVX512 (but with
22431 // 256-bit vectors), during legalization:
22433 // (vselect (sign_extend (any_extend (BUILD_VECTOR)) i1) LHS RHS)
22435 // Iff we find this pattern and the build_vectors are built from
22436 // constants, we translate the vselect into a shuffle_vector that we
22437 // know will be matched by LowerVECTOR_SHUFFLEtoBlend.
22438 if ((N->getOpcode() == ISD::VSELECT ||
22439 N->getOpcode() == X86ISD::SHRUNKBLEND) &&
22440 !DCI.isBeforeLegalize() && !VT.is512BitVector()) {
22441 SDValue Shuffle = transformVSELECTtoBlendVECTOR_SHUFFLE(N, DAG, Subtarget);
22442 if (Shuffle.getNode())
22446 // If this is a *dynamic* select (non-constant condition) and we can match
22447 // this node with one of the variable blend instructions, restructure the
22448 // condition so that the blends can use the high bit of each element and use
22449 // SimplifyDemandedBits to simplify the condition operand.
22450 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
22451 !DCI.isBeforeLegalize() &&
22452 !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
22453 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
22455 // Don't optimize vector selects that map to mask-registers.
22459 // We can only handle the cases where VSELECT is directly legal on the
22460 // subtarget. We custom lower VSELECT nodes with constant conditions and
22461 // this makes it hard to see whether a dynamic VSELECT will correctly
22462 // lower, so we both check the operation's status and explicitly handle the
22463 // cases where a *dynamic* blend will fail even though a constant-condition
22464 // blend could be custom lowered.
22465 // FIXME: We should find a better way to handle this class of problems.
22466 // Potentially, we should combine constant-condition vselect nodes
22467 // pre-legalization into shuffles and not mark as many types as custom
22469 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
22471 // FIXME: We don't support i16-element blends currently. We could and
22472 // should support them by making *all* the bits in the condition be set
22473 // rather than just the high bit and using an i8-element blend.
22474 if (VT.getScalarType() == MVT::i16)
22476 // Dynamic blending was only available from SSE4.1 onward.
22477 if (VT.getSizeInBits() == 128 && !Subtarget->hasSSE41())
22479 // Byte blends are only available in AVX2
22480 if (VT.getSizeInBits() == 256 && VT.getScalarType() == MVT::i8 &&
22481 !Subtarget->hasAVX2())
22484 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
22485 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
22487 APInt KnownZero, KnownOne;
22488 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
22489 DCI.isBeforeLegalizeOps());
22490 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
22491 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne,
22493 // If we changed the computation somewhere in the DAG, this change
22494 // will affect all users of Cond.
22495 // Make sure it is fine and update all the nodes so that we do not
22496 // use the generic VSELECT anymore. Otherwise, we may perform
22497 // wrong optimizations as we messed up with the actual expectation
22498 // for the vector boolean values.
22499 if (Cond != TLO.Old) {
22500 // Check all uses of that condition operand to check whether it will be
22501 // consumed by non-BLEND instructions, which may depend on all bits are
22503 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22505 if (I->getOpcode() != ISD::VSELECT)
22506 // TODO: Add other opcodes eventually lowered into BLEND.
22509 // Update all the users of the condition, before committing the change,
22510 // so that the VSELECT optimizations that expect the correct vector
22511 // boolean value will not be triggered.
22512 for (SDNode::use_iterator I = Cond->use_begin(), E = Cond->use_end();
22514 DAG.ReplaceAllUsesOfValueWith(
22516 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(*I), I->getValueType(0),
22517 Cond, I->getOperand(1), I->getOperand(2)));
22518 DCI.CommitTargetLoweringOpt(TLO);
22521 // At this point, only Cond is changed. Change the condition
22522 // just for N to keep the opportunity to optimize all other
22523 // users their own way.
22524 DAG.ReplaceAllUsesOfValueWith(
22526 DAG.getNode(X86ISD::SHRUNKBLEND, SDLoc(N), N->getValueType(0),
22527 TLO.New, N->getOperand(1), N->getOperand(2)));
22535 // Check whether a boolean test is testing a boolean value generated by
22536 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
22539 // Simplify the following patterns:
22540 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
22541 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
22542 // to (Op EFLAGS Cond)
22544 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
22545 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
22546 // to (Op EFLAGS !Cond)
22548 // where Op could be BRCOND or CMOV.
22550 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
22551 // Quit if not CMP and SUB with its value result used.
22552 if (Cmp.getOpcode() != X86ISD::CMP &&
22553 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
22556 // Quit if not used as a boolean value.
22557 if (CC != X86::COND_E && CC != X86::COND_NE)
22560 // Check CMP operands. One of them should be 0 or 1 and the other should be
22561 // an SetCC or extended from it.
22562 SDValue Op1 = Cmp.getOperand(0);
22563 SDValue Op2 = Cmp.getOperand(1);
22566 const ConstantSDNode* C = nullptr;
22567 bool needOppositeCond = (CC == X86::COND_E);
22568 bool checkAgainstTrue = false; // Is it a comparison against 1?
22570 if ((C = dyn_cast<ConstantSDNode>(Op1)))
22572 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
22574 else // Quit if all operands are not constants.
22577 if (C->getZExtValue() == 1) {
22578 needOppositeCond = !needOppositeCond;
22579 checkAgainstTrue = true;
22580 } else if (C->getZExtValue() != 0)
22581 // Quit if the constant is neither 0 or 1.
22584 bool truncatedToBoolWithAnd = false;
22585 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
22586 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
22587 SetCC.getOpcode() == ISD::TRUNCATE ||
22588 SetCC.getOpcode() == ISD::AND) {
22589 if (SetCC.getOpcode() == ISD::AND) {
22591 ConstantSDNode *CS;
22592 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
22593 CS->getZExtValue() == 1)
22595 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
22596 CS->getZExtValue() == 1)
22600 SetCC = SetCC.getOperand(OpIdx);
22601 truncatedToBoolWithAnd = true;
22603 SetCC = SetCC.getOperand(0);
22606 switch (SetCC.getOpcode()) {
22607 case X86ISD::SETCC_CARRY:
22608 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
22609 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
22610 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
22611 // truncated to i1 using 'and'.
22612 if (checkAgainstTrue && !truncatedToBoolWithAnd)
22614 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
22615 "Invalid use of SETCC_CARRY!");
22617 case X86ISD::SETCC:
22618 // Set the condition code or opposite one if necessary.
22619 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
22620 if (needOppositeCond)
22621 CC = X86::GetOppositeBranchCondition(CC);
22622 return SetCC.getOperand(1);
22623 case X86ISD::CMOV: {
22624 // Check whether false/true value has canonical one, i.e. 0 or 1.
22625 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
22626 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
22627 // Quit if true value is not a constant.
22630 // Quit if false value is not a constant.
22632 SDValue Op = SetCC.getOperand(0);
22633 // Skip 'zext' or 'trunc' node.
22634 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
22635 Op.getOpcode() == ISD::TRUNCATE)
22636 Op = Op.getOperand(0);
22637 // A special case for rdrand/rdseed, where 0 is set if false cond is
22639 if ((Op.getOpcode() != X86ISD::RDRAND &&
22640 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
22643 // Quit if false value is not the constant 0 or 1.
22644 bool FValIsFalse = true;
22645 if (FVal && FVal->getZExtValue() != 0) {
22646 if (FVal->getZExtValue() != 1)
22648 // If FVal is 1, opposite cond is needed.
22649 needOppositeCond = !needOppositeCond;
22650 FValIsFalse = false;
22652 // Quit if TVal is not the constant opposite of FVal.
22653 if (FValIsFalse && TVal->getZExtValue() != 1)
22655 if (!FValIsFalse && TVal->getZExtValue() != 0)
22657 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
22658 if (needOppositeCond)
22659 CC = X86::GetOppositeBranchCondition(CC);
22660 return SetCC.getOperand(3);
22667 /// Check whether Cond is an AND/OR of SETCCs off of the same EFLAGS.
22669 /// (X86or (X86setcc) (X86setcc))
22670 /// (X86cmp (and (X86setcc) (X86setcc)), 0)
22671 static bool checkBoolTestAndOrSetCCCombine(SDValue Cond, X86::CondCode &CC0,
22672 X86::CondCode &CC1, SDValue &Flags,
22674 if (Cond->getOpcode() == X86ISD::CMP) {
22675 ConstantSDNode *CondOp1C = dyn_cast<ConstantSDNode>(Cond->getOperand(1));
22676 if (!CondOp1C || !CondOp1C->isNullValue())
22679 Cond = Cond->getOperand(0);
22684 SDValue SetCC0, SetCC1;
22685 switch (Cond->getOpcode()) {
22686 default: return false;
22693 SetCC0 = Cond->getOperand(0);
22694 SetCC1 = Cond->getOperand(1);
22698 // Make sure we have SETCC nodes, using the same flags value.
22699 if (SetCC0.getOpcode() != X86ISD::SETCC ||
22700 SetCC1.getOpcode() != X86ISD::SETCC ||
22701 SetCC0->getOperand(1) != SetCC1->getOperand(1))
22704 CC0 = (X86::CondCode)SetCC0->getConstantOperandVal(0);
22705 CC1 = (X86::CondCode)SetCC1->getConstantOperandVal(0);
22706 Flags = SetCC0->getOperand(1);
22710 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
22711 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
22712 TargetLowering::DAGCombinerInfo &DCI,
22713 const X86Subtarget *Subtarget) {
22716 // If the flag operand isn't dead, don't touch this CMOV.
22717 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
22720 SDValue FalseOp = N->getOperand(0);
22721 SDValue TrueOp = N->getOperand(1);
22722 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
22723 SDValue Cond = N->getOperand(3);
22725 if (CC == X86::COND_E || CC == X86::COND_NE) {
22726 switch (Cond.getOpcode()) {
22730 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
22731 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
22732 return (CC == X86::COND_E) ? FalseOp : TrueOp;
22738 Flags = checkBoolTestSetCCCombine(Cond, CC);
22739 if (Flags.getNode() &&
22740 // Extra check as FCMOV only supports a subset of X86 cond.
22741 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
22742 SDValue Ops[] = { FalseOp, TrueOp,
22743 DAG.getConstant(CC, DL, MVT::i8), Flags };
22744 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22747 // If this is a select between two integer constants, try to do some
22748 // optimizations. Note that the operands are ordered the opposite of SELECT
22750 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
22751 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
22752 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
22753 // larger than FalseC (the false value).
22754 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
22755 CC = X86::GetOppositeBranchCondition(CC);
22756 std::swap(TrueC, FalseC);
22757 std::swap(TrueOp, FalseOp);
22760 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
22761 // This is efficient for any integer data type (including i8/i16) and
22763 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
22764 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22765 DAG.getConstant(CC, DL, MVT::i8), Cond);
22767 // Zero extend the condition if needed.
22768 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
22770 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
22771 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
22772 DAG.getConstant(ShAmt, DL, MVT::i8));
22773 if (N->getNumValues() == 2) // Dead flag value?
22774 return DCI.CombineTo(N, Cond, SDValue());
22778 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
22779 // for any integer data type, including i8/i16.
22780 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
22781 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22782 DAG.getConstant(CC, DL, MVT::i8), Cond);
22784 // Zero extend the condition if needed.
22785 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
22786 FalseC->getValueType(0), Cond);
22787 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22788 SDValue(FalseC, 0));
22790 if (N->getNumValues() == 2) // Dead flag value?
22791 return DCI.CombineTo(N, Cond, SDValue());
22795 // Optimize cases that will turn into an LEA instruction. This requires
22796 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
22797 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
22798 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
22799 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
22801 bool isFastMultiplier = false;
22803 switch ((unsigned char)Diff) {
22805 case 1: // result = add base, cond
22806 case 2: // result = lea base( , cond*2)
22807 case 3: // result = lea base(cond, cond*2)
22808 case 4: // result = lea base( , cond*4)
22809 case 5: // result = lea base(cond, cond*4)
22810 case 8: // result = lea base( , cond*8)
22811 case 9: // result = lea base(cond, cond*8)
22812 isFastMultiplier = true;
22817 if (isFastMultiplier) {
22818 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
22819 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
22820 DAG.getConstant(CC, DL, MVT::i8), Cond);
22821 // Zero extend the condition if needed.
22822 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
22824 // Scale the condition by the difference.
22826 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
22827 DAG.getConstant(Diff, DL, Cond.getValueType()));
22829 // Add the base if non-zero.
22830 if (FalseC->getAPIntValue() != 0)
22831 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
22832 SDValue(FalseC, 0));
22833 if (N->getNumValues() == 2) // Dead flag value?
22834 return DCI.CombineTo(N, Cond, SDValue());
22841 // Handle these cases:
22842 // (select (x != c), e, c) -> select (x != c), e, x),
22843 // (select (x == c), c, e) -> select (x == c), x, e)
22844 // where the c is an integer constant, and the "select" is the combination
22845 // of CMOV and CMP.
22847 // The rationale for this change is that the conditional-move from a constant
22848 // needs two instructions, however, conditional-move from a register needs
22849 // only one instruction.
22851 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
22852 // some instruction-combining opportunities. This opt needs to be
22853 // postponed as late as possible.
22855 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
22856 // the DCI.xxxx conditions are provided to postpone the optimization as
22857 // late as possible.
22859 ConstantSDNode *CmpAgainst = nullptr;
22860 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
22861 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
22862 !isa<ConstantSDNode>(Cond.getOperand(0))) {
22864 if (CC == X86::COND_NE &&
22865 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
22866 CC = X86::GetOppositeBranchCondition(CC);
22867 std::swap(TrueOp, FalseOp);
22870 if (CC == X86::COND_E &&
22871 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
22872 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
22873 DAG.getConstant(CC, DL, MVT::i8), Cond };
22874 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
22879 // Fold and/or of setcc's to double CMOV:
22880 // (CMOV F, T, ((cc1 | cc2) != 0)) -> (CMOV (CMOV F, T, cc1), T, cc2)
22881 // (CMOV F, T, ((cc1 & cc2) != 0)) -> (CMOV (CMOV T, F, !cc1), F, !cc2)
22883 // This combine lets us generate:
22884 // cmovcc1 (jcc1 if we don't have CMOV)
22890 // cmovne (jne if we don't have CMOV)
22891 // When we can't use the CMOV instruction, it might increase branch
22893 // When we can use CMOV, or when there is no mispredict, this improves
22894 // throughput and reduces register pressure.
22896 if (CC == X86::COND_NE) {
22898 X86::CondCode CC0, CC1;
22900 if (checkBoolTestAndOrSetCCCombine(Cond, CC0, CC1, Flags, isAndSetCC)) {
22902 std::swap(FalseOp, TrueOp);
22903 CC0 = X86::GetOppositeBranchCondition(CC0);
22904 CC1 = X86::GetOppositeBranchCondition(CC1);
22907 SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),
22909 SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);
22910 SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};
22911 SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);
22912 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));
22920 static SDValue PerformINTRINSIC_WO_CHAINCombine(SDNode *N, SelectionDAG &DAG,
22921 const X86Subtarget *Subtarget) {
22922 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
22924 default: return SDValue();
22925 // SSE/AVX/AVX2 blend intrinsics.
22926 case Intrinsic::x86_avx2_pblendvb:
22927 // Don't try to simplify this intrinsic if we don't have AVX2.
22928 if (!Subtarget->hasAVX2())
22931 case Intrinsic::x86_avx_blendv_pd_256:
22932 case Intrinsic::x86_avx_blendv_ps_256:
22933 // Don't try to simplify this intrinsic if we don't have AVX.
22934 if (!Subtarget->hasAVX())
22937 case Intrinsic::x86_sse41_blendvps:
22938 case Intrinsic::x86_sse41_blendvpd:
22939 case Intrinsic::x86_sse41_pblendvb: {
22940 SDValue Op0 = N->getOperand(1);
22941 SDValue Op1 = N->getOperand(2);
22942 SDValue Mask = N->getOperand(3);
22944 // Don't try to simplify this intrinsic if we don't have SSE4.1.
22945 if (!Subtarget->hasSSE41())
22948 // fold (blend A, A, Mask) -> A
22951 // fold (blend A, B, allZeros) -> A
22952 if (ISD::isBuildVectorAllZeros(Mask.getNode()))
22954 // fold (blend A, B, allOnes) -> B
22955 if (ISD::isBuildVectorAllOnes(Mask.getNode()))
22958 // Simplify the case where the mask is a constant i32 value.
22959 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mask)) {
22960 if (C->isNullValue())
22962 if (C->isAllOnesValue())
22969 // Packed SSE2/AVX2 arithmetic shift immediate intrinsics.
22970 case Intrinsic::x86_sse2_psrai_w:
22971 case Intrinsic::x86_sse2_psrai_d:
22972 case Intrinsic::x86_avx2_psrai_w:
22973 case Intrinsic::x86_avx2_psrai_d:
22974 case Intrinsic::x86_sse2_psra_w:
22975 case Intrinsic::x86_sse2_psra_d:
22976 case Intrinsic::x86_avx2_psra_w:
22977 case Intrinsic::x86_avx2_psra_d: {
22978 SDValue Op0 = N->getOperand(1);
22979 SDValue Op1 = N->getOperand(2);
22980 EVT VT = Op0.getValueType();
22981 assert(VT.isVector() && "Expected a vector type!");
22983 if (isa<BuildVectorSDNode>(Op1))
22984 Op1 = Op1.getOperand(0);
22986 if (!isa<ConstantSDNode>(Op1))
22989 EVT SVT = VT.getVectorElementType();
22990 unsigned SVTBits = SVT.getSizeInBits();
22992 ConstantSDNode *CND = cast<ConstantSDNode>(Op1);
22993 const APInt &C = APInt(SVTBits, CND->getAPIntValue().getZExtValue());
22994 uint64_t ShAmt = C.getZExtValue();
22996 // Don't try to convert this shift into a ISD::SRA if the shift
22997 // count is bigger than or equal to the element size.
22998 if (ShAmt >= SVTBits)
23001 // Trivial case: if the shift count is zero, then fold this
23002 // into the first operand.
23006 // Replace this packed shift intrinsic with a target independent
23009 SDValue Splat = DAG.getConstant(C, DL, VT);
23010 return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);
23015 /// PerformMulCombine - Optimize a single multiply with constant into two
23016 /// in order to implement it with two cheaper instructions, e.g.
23017 /// LEA + SHL, LEA + LEA.
23018 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
23019 TargetLowering::DAGCombinerInfo &DCI) {
23020 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
23023 EVT VT = N->getValueType(0);
23024 if (VT != MVT::i64 && VT != MVT::i32)
23027 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
23030 uint64_t MulAmt = C->getZExtValue();
23031 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
23034 uint64_t MulAmt1 = 0;
23035 uint64_t MulAmt2 = 0;
23036 if ((MulAmt % 9) == 0) {
23038 MulAmt2 = MulAmt / 9;
23039 } else if ((MulAmt % 5) == 0) {
23041 MulAmt2 = MulAmt / 5;
23042 } else if ((MulAmt % 3) == 0) {
23044 MulAmt2 = MulAmt / 3;
23047 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
23050 if (isPowerOf2_64(MulAmt2) &&
23051 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
23052 // If second multiplifer is pow2, issue it first. We want the multiply by
23053 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
23055 std::swap(MulAmt1, MulAmt2);
23058 if (isPowerOf2_64(MulAmt1))
23059 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
23060 DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));
23062 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
23063 DAG.getConstant(MulAmt1, DL, VT));
23065 if (isPowerOf2_64(MulAmt2))
23066 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
23067 DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));
23069 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
23070 DAG.getConstant(MulAmt2, DL, VT));
23072 // Do not add new nodes to DAG combiner worklist.
23073 DCI.CombineTo(N, NewMul, false);
23078 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
23079 SDValue N0 = N->getOperand(0);
23080 SDValue N1 = N->getOperand(1);
23081 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
23082 EVT VT = N0.getValueType();
23084 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
23085 // since the result of setcc_c is all zero's or all ones.
23086 if (VT.isInteger() && !VT.isVector() &&
23087 N1C && N0.getOpcode() == ISD::AND &&
23088 N0.getOperand(1).getOpcode() == ISD::Constant) {
23089 SDValue N00 = N0.getOperand(0);
23090 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
23091 ((N00.getOpcode() == ISD::ANY_EXTEND ||
23092 N00.getOpcode() == ISD::ZERO_EXTEND) &&
23093 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
23094 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
23095 APInt ShAmt = N1C->getAPIntValue();
23096 Mask = Mask.shl(ShAmt);
23099 return DAG.getNode(ISD::AND, DL, VT,
23100 N00, DAG.getConstant(Mask, DL, VT));
23105 // Hardware support for vector shifts is sparse which makes us scalarize the
23106 // vector operations in many cases. Also, on sandybridge ADD is faster than
23108 // (shl V, 1) -> add V,V
23109 if (auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
23110 if (auto *N1SplatC = N1BV->getConstantSplatNode()) {
23111 assert(N0.getValueType().isVector() && "Invalid vector shift type");
23112 // We shift all of the values by one. In many cases we do not have
23113 // hardware support for this operation. This is better expressed as an ADD
23115 if (N1SplatC->getZExtValue() == 1)
23116 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
23122 /// \brief Returns a vector of 0s if the node in input is a vector logical
23123 /// shift by a constant amount which is known to be bigger than or equal
23124 /// to the vector element size in bits.
23125 static SDValue performShiftToAllZeros(SDNode *N, SelectionDAG &DAG,
23126 const X86Subtarget *Subtarget) {
23127 EVT VT = N->getValueType(0);
23129 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16 &&
23130 (!Subtarget->hasInt256() ||
23131 (VT != MVT::v4i64 && VT != MVT::v8i32 && VT != MVT::v16i16)))
23134 SDValue Amt = N->getOperand(1);
23136 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Amt))
23137 if (auto *AmtSplat = AmtBV->getConstantSplatNode()) {
23138 APInt ShiftAmt = AmtSplat->getAPIntValue();
23139 unsigned MaxAmount = VT.getVectorElementType().getSizeInBits();
23141 // SSE2/AVX2 logical shifts always return a vector of 0s
23142 // if the shift amount is bigger than or equal to
23143 // the element size. The constant shift amount will be
23144 // encoded as a 8-bit immediate.
23145 if (ShiftAmt.trunc(8).uge(MaxAmount))
23146 return getZeroVector(VT, Subtarget, DAG, DL);
23152 /// PerformShiftCombine - Combine shifts.
23153 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
23154 TargetLowering::DAGCombinerInfo &DCI,
23155 const X86Subtarget *Subtarget) {
23156 if (N->getOpcode() == ISD::SHL)
23157 if (SDValue V = PerformSHLCombine(N, DAG))
23160 // Try to fold this logical shift into a zero vector.
23161 if (N->getOpcode() != ISD::SRA)
23162 if (SDValue V = performShiftToAllZeros(N, DAG, Subtarget))
23168 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
23169 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
23170 // and friends. Likewise for OR -> CMPNEQSS.
23171 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
23172 TargetLowering::DAGCombinerInfo &DCI,
23173 const X86Subtarget *Subtarget) {
23176 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
23177 // we're requiring SSE2 for both.
23178 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
23179 SDValue N0 = N->getOperand(0);
23180 SDValue N1 = N->getOperand(1);
23181 SDValue CMP0 = N0->getOperand(1);
23182 SDValue CMP1 = N1->getOperand(1);
23185 // The SETCCs should both refer to the same CMP.
23186 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
23189 SDValue CMP00 = CMP0->getOperand(0);
23190 SDValue CMP01 = CMP0->getOperand(1);
23191 EVT VT = CMP00.getValueType();
23193 if (VT == MVT::f32 || VT == MVT::f64) {
23194 bool ExpectingFlags = false;
23195 // Check for any users that want flags:
23196 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
23197 !ExpectingFlags && UI != UE; ++UI)
23198 switch (UI->getOpcode()) {
23203 ExpectingFlags = true;
23205 case ISD::CopyToReg:
23206 case ISD::SIGN_EXTEND:
23207 case ISD::ZERO_EXTEND:
23208 case ISD::ANY_EXTEND:
23212 if (!ExpectingFlags) {
23213 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
23214 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
23216 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
23217 X86::CondCode tmp = cc0;
23222 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
23223 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
23224 // FIXME: need symbolic constants for these magic numbers.
23225 // See X86ATTInstPrinter.cpp:printSSECC().
23226 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
23227 if (Subtarget->hasAVX512()) {
23228 SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,
23230 DAG.getConstant(x86cc, DL, MVT::i8));
23231 if (N->getValueType(0) != MVT::i1)
23232 return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),
23236 SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,
23237 CMP00.getValueType(), CMP00, CMP01,
23238 DAG.getConstant(x86cc, DL,
23241 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
23242 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;
23244 if (is64BitFP && !Subtarget->is64Bit()) {
23245 // On a 32-bit target, we cannot bitcast the 64-bit float to a
23246 // 64-bit integer, since that's not a legal type. Since
23247 // OnesOrZeroesF is all ones of all zeroes, we don't need all the
23248 // bits, but can do this little dance to extract the lowest 32 bits
23249 // and work with those going forward.
23250 SDValue Vector64 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f64,
23252 SDValue Vector32 = DAG.getBitcast(MVT::v4f32, Vector64);
23253 OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,
23254 Vector32, DAG.getIntPtrConstant(0, DL));
23258 SDValue OnesOrZeroesI = DAG.getBitcast(IntVT, OnesOrZeroesF);
23259 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,
23260 DAG.getConstant(1, DL, IntVT));
23261 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
23263 return OneBitOfTruth;
23271 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
23272 /// so it can be folded inside ANDNP.
23273 static bool CanFoldXORWithAllOnes(const SDNode *N) {
23274 EVT VT = N->getValueType(0);
23276 // Match direct AllOnes for 128 and 256-bit vectors
23277 if (ISD::isBuildVectorAllOnes(N))
23280 // Look through a bit convert.
23281 if (N->getOpcode() == ISD::BITCAST)
23282 N = N->getOperand(0).getNode();
23284 // Sometimes the operand may come from a insert_subvector building a 256-bit
23286 if (VT.is256BitVector() &&
23287 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
23288 SDValue V1 = N->getOperand(0);
23289 SDValue V2 = N->getOperand(1);
23291 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
23292 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
23293 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
23294 ISD::isBuildVectorAllOnes(V2.getNode()))
23301 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
23302 // register. In most cases we actually compare or select YMM-sized registers
23303 // and mixing the two types creates horrible code. This method optimizes
23304 // some of the transition sequences.
23305 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
23306 TargetLowering::DAGCombinerInfo &DCI,
23307 const X86Subtarget *Subtarget) {
23308 EVT VT = N->getValueType(0);
23309 if (!VT.is256BitVector())
23312 assert((N->getOpcode() == ISD::ANY_EXTEND ||
23313 N->getOpcode() == ISD::ZERO_EXTEND ||
23314 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
23316 SDValue Narrow = N->getOperand(0);
23317 EVT NarrowVT = Narrow->getValueType(0);
23318 if (!NarrowVT.is128BitVector())
23321 if (Narrow->getOpcode() != ISD::XOR &&
23322 Narrow->getOpcode() != ISD::AND &&
23323 Narrow->getOpcode() != ISD::OR)
23326 SDValue N0 = Narrow->getOperand(0);
23327 SDValue N1 = Narrow->getOperand(1);
23330 // The Left side has to be a trunc.
23331 if (N0.getOpcode() != ISD::TRUNCATE)
23334 // The type of the truncated inputs.
23335 EVT WideVT = N0->getOperand(0)->getValueType(0);
23339 // The right side has to be a 'trunc' or a constant vector.
23340 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
23341 ConstantSDNode *RHSConstSplat = nullptr;
23342 if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
23343 RHSConstSplat = RHSBV->getConstantSplatNode();
23344 if (!RHSTrunc && !RHSConstSplat)
23347 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23349 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
23352 // Set N0 and N1 to hold the inputs to the new wide operation.
23353 N0 = N0->getOperand(0);
23354 if (RHSConstSplat) {
23355 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
23356 SDValue(RHSConstSplat, 0));
23357 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
23358 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C);
23359 } else if (RHSTrunc) {
23360 N1 = N1->getOperand(0);
23363 // Generate the wide operation.
23364 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
23365 unsigned Opcode = N->getOpcode();
23367 case ISD::ANY_EXTEND:
23369 case ISD::ZERO_EXTEND: {
23370 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
23371 APInt Mask = APInt::getAllOnesValue(InBits);
23372 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
23373 return DAG.getNode(ISD::AND, DL, VT,
23374 Op, DAG.getConstant(Mask, DL, VT));
23376 case ISD::SIGN_EXTEND:
23377 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
23378 Op, DAG.getValueType(NarrowVT));
23380 llvm_unreachable("Unexpected opcode");
23384 static SDValue VectorZextCombine(SDNode *N, SelectionDAG &DAG,
23385 TargetLowering::DAGCombinerInfo &DCI,
23386 const X86Subtarget *Subtarget) {
23387 SDValue N0 = N->getOperand(0);
23388 SDValue N1 = N->getOperand(1);
23391 // A vector zext_in_reg may be represented as a shuffle,
23392 // feeding into a bitcast (this represents anyext) feeding into
23393 // an and with a mask.
23394 // We'd like to try to combine that into a shuffle with zero
23395 // plus a bitcast, removing the and.
23396 if (N0.getOpcode() != ISD::BITCAST ||
23397 N0.getOperand(0).getOpcode() != ISD::VECTOR_SHUFFLE)
23400 // The other side of the AND should be a splat of 2^C, where C
23401 // is the number of bits in the source type.
23402 if (N1.getOpcode() == ISD::BITCAST)
23403 N1 = N1.getOperand(0);
23404 if (N1.getOpcode() != ISD::BUILD_VECTOR)
23406 BuildVectorSDNode *Vector = cast<BuildVectorSDNode>(N1);
23408 ShuffleVectorSDNode *Shuffle = cast<ShuffleVectorSDNode>(N0.getOperand(0));
23409 EVT SrcType = Shuffle->getValueType(0);
23411 // We expect a single-source shuffle
23412 if (Shuffle->getOperand(1)->getOpcode() != ISD::UNDEF)
23415 unsigned SrcSize = SrcType.getScalarSizeInBits();
23417 APInt SplatValue, SplatUndef;
23418 unsigned SplatBitSize;
23420 if (!Vector->isConstantSplat(SplatValue, SplatUndef,
23421 SplatBitSize, HasAnyUndefs))
23424 unsigned ResSize = N1.getValueType().getScalarSizeInBits();
23425 // Make sure the splat matches the mask we expect
23426 if (SplatBitSize > ResSize ||
23427 (SplatValue + 1).exactLogBase2() != (int)SrcSize)
23430 // Make sure the input and output size make sense
23431 if (SrcSize >= ResSize || ResSize % SrcSize)
23434 // We expect a shuffle of the form <0, u, u, u, 1, u, u, u...>
23435 // The number of u's between each two values depends on the ratio between
23436 // the source and dest type.
23437 unsigned ZextRatio = ResSize / SrcSize;
23438 bool IsZext = true;
23439 for (unsigned i = 0; i < SrcType.getVectorNumElements(); ++i) {
23440 if (i % ZextRatio) {
23441 if (Shuffle->getMaskElt(i) > 0) {
23447 if (Shuffle->getMaskElt(i) != (int)(i / ZextRatio)) {
23448 // Expected element number
23458 // Ok, perform the transformation - replace the shuffle with
23459 // a shuffle of the form <0, k, k, k, 1, k, k, k> with zero
23460 // (instead of undef) where the k elements come from the zero vector.
23461 SmallVector<int, 8> Mask;
23462 unsigned NumElems = SrcType.getVectorNumElements();
23463 for (unsigned i = 0; i < NumElems; ++i)
23465 Mask.push_back(NumElems);
23467 Mask.push_back(i / ZextRatio);
23469 SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,
23470 Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);
23471 return DAG.getBitcast(N0.getValueType(), NewShuffle);
23474 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
23475 TargetLowering::DAGCombinerInfo &DCI,
23476 const X86Subtarget *Subtarget) {
23477 if (DCI.isBeforeLegalizeOps())
23480 if (SDValue Zext = VectorZextCombine(N, DAG, DCI, Subtarget))
23483 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23486 EVT VT = N->getValueType(0);
23487 SDValue N0 = N->getOperand(0);
23488 SDValue N1 = N->getOperand(1);
23491 // Create BEXTR instructions
23492 // BEXTR is ((X >> imm) & (2**size-1))
23493 if (VT == MVT::i32 || VT == MVT::i64) {
23494 // Check for BEXTR.
23495 if ((Subtarget->hasBMI() || Subtarget->hasTBM()) &&
23496 (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL)) {
23497 ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
23498 ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
23499 if (MaskNode && ShiftNode) {
23500 uint64_t Mask = MaskNode->getZExtValue();
23501 uint64_t Shift = ShiftNode->getZExtValue();
23502 if (isMask_64(Mask)) {
23503 uint64_t MaskSize = countPopulation(Mask);
23504 if (Shift + MaskSize <= VT.getSizeInBits())
23505 return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),
23506 DAG.getConstant(Shift | (MaskSize << 8), DL,
23515 // Want to form ANDNP nodes:
23516 // 1) In the hopes of then easily combining them with OR and AND nodes
23517 // to form PBLEND/PSIGN.
23518 // 2) To match ANDN packed intrinsics
23519 if (VT != MVT::v2i64 && VT != MVT::v4i64)
23522 // Check LHS for vnot
23523 if (N0.getOpcode() == ISD::XOR &&
23524 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
23525 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
23526 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
23528 // Check RHS for vnot
23529 if (N1.getOpcode() == ISD::XOR &&
23530 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
23531 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
23532 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
23537 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
23538 TargetLowering::DAGCombinerInfo &DCI,
23539 const X86Subtarget *Subtarget) {
23540 if (DCI.isBeforeLegalizeOps())
23543 if (SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget))
23546 SDValue N0 = N->getOperand(0);
23547 SDValue N1 = N->getOperand(1);
23548 EVT VT = N->getValueType(0);
23550 // look for psign/blend
23551 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
23552 if (!Subtarget->hasSSSE3() ||
23553 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
23556 // Canonicalize pandn to RHS
23557 if (N0.getOpcode() == X86ISD::ANDNP)
23559 // or (and (m, y), (pandn m, x))
23560 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
23561 SDValue Mask = N1.getOperand(0);
23562 SDValue X = N1.getOperand(1);
23564 if (N0.getOperand(0) == Mask)
23565 Y = N0.getOperand(1);
23566 if (N0.getOperand(1) == Mask)
23567 Y = N0.getOperand(0);
23569 // Check to see if the mask appeared in both the AND and ANDNP and
23573 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
23574 // Look through mask bitcast.
23575 if (Mask.getOpcode() == ISD::BITCAST)
23576 Mask = Mask.getOperand(0);
23577 if (X.getOpcode() == ISD::BITCAST)
23578 X = X.getOperand(0);
23579 if (Y.getOpcode() == ISD::BITCAST)
23580 Y = Y.getOperand(0);
23582 EVT MaskVT = Mask.getValueType();
23584 // Validate that the Mask operand is a vector sra node.
23585 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
23586 // there is no psrai.b
23587 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
23588 unsigned SraAmt = ~0;
23589 if (Mask.getOpcode() == ISD::SRA) {
23590 if (auto *AmtBV = dyn_cast<BuildVectorSDNode>(Mask.getOperand(1)))
23591 if (auto *AmtConst = AmtBV->getConstantSplatNode())
23592 SraAmt = AmtConst->getZExtValue();
23593 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
23594 SDValue SraC = Mask.getOperand(1);
23595 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
23597 if ((SraAmt + 1) != EltBits)
23602 // Now we know we at least have a plendvb with the mask val. See if
23603 // we can form a psignb/w/d.
23604 // psign = x.type == y.type == mask.type && y = sub(0, x);
23605 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
23606 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
23607 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
23608 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
23609 "Unsupported VT for PSIGN");
23610 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
23611 return DAG.getBitcast(VT, Mask);
23613 // PBLENDVB only available on SSE 4.1
23614 if (!Subtarget->hasSSE41())
23617 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
23619 X = DAG.getBitcast(BlendVT, X);
23620 Y = DAG.getBitcast(BlendVT, Y);
23621 Mask = DAG.getBitcast(BlendVT, Mask);
23622 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
23623 return DAG.getBitcast(VT, Mask);
23627 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
23630 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
23631 MachineFunction &MF = DAG.getMachineFunction();
23633 MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
23635 // SHLD/SHRD instructions have lower register pressure, but on some
23636 // platforms they have higher latency than the equivalent
23637 // series of shifts/or that would otherwise be generated.
23638 // Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
23639 // have higher latencies and we are not optimizing for size.
23640 if (!OptForSize && Subtarget->isSHLDSlow())
23643 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
23645 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
23647 if (!N0.hasOneUse() || !N1.hasOneUse())
23650 SDValue ShAmt0 = N0.getOperand(1);
23651 if (ShAmt0.getValueType() != MVT::i8)
23653 SDValue ShAmt1 = N1.getOperand(1);
23654 if (ShAmt1.getValueType() != MVT::i8)
23656 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
23657 ShAmt0 = ShAmt0.getOperand(0);
23658 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
23659 ShAmt1 = ShAmt1.getOperand(0);
23662 unsigned Opc = X86ISD::SHLD;
23663 SDValue Op0 = N0.getOperand(0);
23664 SDValue Op1 = N1.getOperand(0);
23665 if (ShAmt0.getOpcode() == ISD::SUB) {
23666 Opc = X86ISD::SHRD;
23667 std::swap(Op0, Op1);
23668 std::swap(ShAmt0, ShAmt1);
23671 unsigned Bits = VT.getSizeInBits();
23672 if (ShAmt1.getOpcode() == ISD::SUB) {
23673 SDValue Sum = ShAmt1.getOperand(0);
23674 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
23675 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
23676 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
23677 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
23678 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
23679 return DAG.getNode(Opc, DL, VT,
23681 DAG.getNode(ISD::TRUNCATE, DL,
23684 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
23685 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
23687 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
23688 return DAG.getNode(Opc, DL, VT,
23689 N0.getOperand(0), N1.getOperand(0),
23690 DAG.getNode(ISD::TRUNCATE, DL,
23697 // Generate NEG and CMOV for integer abs.
23698 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
23699 EVT VT = N->getValueType(0);
23701 // Since X86 does not have CMOV for 8-bit integer, we don't convert
23702 // 8-bit integer abs to NEG and CMOV.
23703 if (VT.isInteger() && VT.getSizeInBits() == 8)
23706 SDValue N0 = N->getOperand(0);
23707 SDValue N1 = N->getOperand(1);
23710 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
23711 // and change it to SUB and CMOV.
23712 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
23713 N0.getOpcode() == ISD::ADD &&
23714 N0.getOperand(1) == N1 &&
23715 N1.getOpcode() == ISD::SRA &&
23716 N1.getOperand(0) == N0.getOperand(0))
23717 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
23718 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
23719 // Generate SUB & CMOV.
23720 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
23721 DAG.getConstant(0, DL, VT), N0.getOperand(0));
23723 SDValue Ops[] = { N0.getOperand(0), Neg,
23724 DAG.getConstant(X86::COND_GE, DL, MVT::i8),
23725 SDValue(Neg.getNode(), 1) };
23726 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
23731 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
23732 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
23733 TargetLowering::DAGCombinerInfo &DCI,
23734 const X86Subtarget *Subtarget) {
23735 if (DCI.isBeforeLegalizeOps())
23738 if (Subtarget->hasCMov())
23739 if (SDValue RV = performIntegerAbsCombine(N, DAG))
23745 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
23746 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
23747 TargetLowering::DAGCombinerInfo &DCI,
23748 const X86Subtarget *Subtarget) {
23749 LoadSDNode *Ld = cast<LoadSDNode>(N);
23750 EVT RegVT = Ld->getValueType(0);
23751 EVT MemVT = Ld->getMemoryVT();
23753 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23755 // For chips with slow 32-byte unaligned loads, break the 32-byte operation
23756 // into two 16-byte operations.
23757 ISD::LoadExtType Ext = Ld->getExtensionType();
23758 unsigned Alignment = Ld->getAlignment();
23759 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
23760 if (RegVT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23761 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
23762 unsigned NumElems = RegVT.getVectorNumElements();
23766 SDValue Ptr = Ld->getBasePtr();
23767 SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());
23769 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
23771 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23772 Ld->getPointerInfo(), Ld->isVolatile(),
23773 Ld->isNonTemporal(), Ld->isInvariant(),
23775 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
23776 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
23777 Ld->getPointerInfo(), Ld->isVolatile(),
23778 Ld->isNonTemporal(), Ld->isInvariant(),
23779 std::min(16U, Alignment));
23780 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
23782 Load2.getValue(1));
23784 SDValue NewVec = DAG.getUNDEF(RegVT);
23785 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
23786 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
23787 return DCI.CombineTo(N, NewVec, TF, true);
23793 /// PerformMLOADCombine - Resolve extending loads
23794 static SDValue PerformMLOADCombine(SDNode *N, SelectionDAG &DAG,
23795 TargetLowering::DAGCombinerInfo &DCI,
23796 const X86Subtarget *Subtarget) {
23797 MaskedLoadSDNode *Mld = cast<MaskedLoadSDNode>(N);
23798 if (Mld->getExtensionType() != ISD::SEXTLOAD)
23801 EVT VT = Mld->getValueType(0);
23802 unsigned NumElems = VT.getVectorNumElements();
23803 EVT LdVT = Mld->getMemoryVT();
23806 assert(LdVT != VT && "Cannot extend to the same type");
23807 unsigned ToSz = VT.getVectorElementType().getSizeInBits();
23808 unsigned FromSz = LdVT.getVectorElementType().getSizeInBits();
23809 // From, To sizes and ElemCount must be pow of two
23810 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23811 "Unexpected size for extending masked load");
23813 unsigned SizeRatio = ToSz / FromSz;
23814 assert(SizeRatio * NumElems * FromSz == VT.getSizeInBits());
23816 // Create a type on which we perform the shuffle
23817 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23818 LdVT.getScalarType(), NumElems*SizeRatio);
23819 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23821 // Convert Src0 value
23822 SDValue WideSrc0 = DAG.getBitcast(WideVecVT, Mld->getSrc0());
23823 if (Mld->getSrc0().getOpcode() != ISD::UNDEF) {
23824 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23825 for (unsigned i = 0; i != NumElems; ++i)
23826 ShuffleVec[i] = i * SizeRatio;
23828 // Can't shuffle using an illegal type.
23829 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23830 && "WideVecVT should be legal");
23831 WideSrc0 = DAG.getVectorShuffle(WideVecVT, dl, WideSrc0,
23832 DAG.getUNDEF(WideVecVT), &ShuffleVec[0]);
23834 // Prepare the new mask
23836 SDValue Mask = Mld->getMask();
23837 if (Mask.getValueType() == VT) {
23838 // Mask and original value have the same type
23839 NewMask = DAG.getBitcast(WideVecVT, Mask);
23840 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23841 for (unsigned i = 0; i != NumElems; ++i)
23842 ShuffleVec[i] = i * SizeRatio;
23843 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23844 ShuffleVec[i] = NumElems*SizeRatio;
23845 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23846 DAG.getConstant(0, dl, WideVecVT),
23850 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23851 unsigned WidenNumElts = NumElems*SizeRatio;
23852 unsigned MaskNumElts = VT.getVectorNumElements();
23853 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23856 unsigned NumConcat = WidenNumElts / MaskNumElts;
23857 SmallVector<SDValue, 16> Ops(NumConcat);
23858 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23860 for (unsigned i = 1; i != NumConcat; ++i)
23863 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23866 SDValue WideLd = DAG.getMaskedLoad(WideVecVT, dl, Mld->getChain(),
23867 Mld->getBasePtr(), NewMask, WideSrc0,
23868 Mld->getMemoryVT(), Mld->getMemOperand(),
23870 SDValue NewVec = DAG.getNode(X86ISD::VSEXT, dl, VT, WideLd);
23871 return DCI.CombineTo(N, NewVec, WideLd.getValue(1), true);
23874 /// PerformMSTORECombine - Resolve truncating stores
23875 static SDValue PerformMSTORECombine(SDNode *N, SelectionDAG &DAG,
23876 const X86Subtarget *Subtarget) {
23877 MaskedStoreSDNode *Mst = cast<MaskedStoreSDNode>(N);
23878 if (!Mst->isTruncatingStore())
23881 EVT VT = Mst->getValue().getValueType();
23882 unsigned NumElems = VT.getVectorNumElements();
23883 EVT StVT = Mst->getMemoryVT();
23886 assert(StVT != VT && "Cannot truncate to the same type");
23887 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23888 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
23890 // From, To sizes and ElemCount must be pow of two
23891 assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&
23892 "Unexpected size for truncating masked store");
23893 // We are going to use the original vector elt for storing.
23894 // Accumulated smaller vector elements must be a multiple of the store size.
23895 assert (((NumElems * FromSz) % ToSz) == 0 &&
23896 "Unexpected ratio for truncating masked store");
23898 unsigned SizeRatio = FromSz / ToSz;
23899 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
23901 // Create a type on which we perform the shuffle
23902 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
23903 StVT.getScalarType(), NumElems*SizeRatio);
23905 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
23907 SDValue WideVec = DAG.getBitcast(WideVecVT, Mst->getValue());
23908 SmallVector<int, 16> ShuffleVec(NumElems * SizeRatio, -1);
23909 for (unsigned i = 0; i != NumElems; ++i)
23910 ShuffleVec[i] = i * SizeRatio;
23912 // Can't shuffle using an illegal type.
23913 assert (DAG.getTargetLoweringInfo().isTypeLegal(WideVecVT)
23914 && "WideVecVT should be legal");
23916 SDValue TruncatedVal = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
23917 DAG.getUNDEF(WideVecVT),
23921 SDValue Mask = Mst->getMask();
23922 if (Mask.getValueType() == VT) {
23923 // Mask and original value have the same type
23924 NewMask = DAG.getBitcast(WideVecVT, Mask);
23925 for (unsigned i = 0; i != NumElems; ++i)
23926 ShuffleVec[i] = i * SizeRatio;
23927 for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)
23928 ShuffleVec[i] = NumElems*SizeRatio;
23929 NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,
23930 DAG.getConstant(0, dl, WideVecVT),
23934 assert(Mask.getValueType().getVectorElementType() == MVT::i1);
23935 unsigned WidenNumElts = NumElems*SizeRatio;
23936 unsigned MaskNumElts = VT.getVectorNumElements();
23937 EVT NewMaskVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,
23940 unsigned NumConcat = WidenNumElts / MaskNumElts;
23941 SmallVector<SDValue, 16> Ops(NumConcat);
23942 SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());
23944 for (unsigned i = 1; i != NumConcat; ++i)
23947 NewMask = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewMaskVT, Ops);
23950 return DAG.getMaskedStore(Mst->getChain(), dl, TruncatedVal, Mst->getBasePtr(),
23951 NewMask, StVT, Mst->getMemOperand(), false);
23953 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
23954 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
23955 const X86Subtarget *Subtarget) {
23956 StoreSDNode *St = cast<StoreSDNode>(N);
23957 EVT VT = St->getValue().getValueType();
23958 EVT StVT = St->getMemoryVT();
23960 SDValue StoredVal = St->getOperand(1);
23961 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23963 // If we are saving a concatenation of two XMM registers and 32-byte stores
23964 // are slow, such as on Sandy Bridge, perform two 16-byte stores.
23965 unsigned Alignment = St->getAlignment();
23966 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
23967 if (VT.is256BitVector() && Subtarget->isUnalignedMem32Slow() &&
23968 StVT == VT && !IsAligned) {
23969 unsigned NumElems = VT.getVectorNumElements();
23973 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
23974 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
23976 SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());
23977 SDValue Ptr0 = St->getBasePtr();
23978 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
23980 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
23981 St->getPointerInfo(), St->isVolatile(),
23982 St->isNonTemporal(), Alignment);
23983 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
23984 St->getPointerInfo(), St->isVolatile(),
23985 St->isNonTemporal(),
23986 std::min(16U, Alignment));
23987 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
23990 // Optimize trunc store (of multiple scalars) to shuffle and store.
23991 // First, pack all of the elements in one place. Next, store to memory
23992 // in fewer chunks.
23993 if (St->isTruncatingStore() && VT.isVector()) {
23994 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
23995 unsigned NumElems = VT.getVectorNumElements();
23996 assert(StVT != VT && "Cannot truncate to the same type");
23997 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
23998 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
24000 // From, To sizes and ElemCount must be pow of two
24001 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
24002 // We are going to use the original vector elt for storing.
24003 // Accumulated smaller vector elements must be a multiple of the store size.
24004 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
24006 unsigned SizeRatio = FromSz / ToSz;
24008 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
24010 // Create a type on which we perform the shuffle
24011 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
24012 StVT.getScalarType(), NumElems*SizeRatio);
24014 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
24016 SDValue WideVec = DAG.getBitcast(WideVecVT, St->getValue());
24017 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
24018 for (unsigned i = 0; i != NumElems; ++i)
24019 ShuffleVec[i] = i * SizeRatio;
24021 // Can't shuffle using an illegal type.
24022 if (!TLI.isTypeLegal(WideVecVT))
24025 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
24026 DAG.getUNDEF(WideVecVT),
24028 // At this point all of the data is stored at the bottom of the
24029 // register. We now need to save it to mem.
24031 // Find the largest store unit
24032 MVT StoreType = MVT::i8;
24033 for (MVT Tp : MVT::integer_valuetypes()) {
24034 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
24038 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
24039 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
24040 (64 <= NumElems * ToSz))
24041 StoreType = MVT::f64;
24043 // Bitcast the original vector into a vector of store-size units
24044 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
24045 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
24046 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
24047 SDValue ShuffWide = DAG.getBitcast(StoreVecVT, Shuff);
24048 SmallVector<SDValue, 8> Chains;
24049 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,
24050 TLI.getPointerTy());
24051 SDValue Ptr = St->getBasePtr();
24053 // Perform one or more big stores into memory.
24054 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
24055 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
24056 StoreType, ShuffWide,
24057 DAG.getIntPtrConstant(i, dl));
24058 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
24059 St->getPointerInfo(), St->isVolatile(),
24060 St->isNonTemporal(), St->getAlignment());
24061 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
24062 Chains.push_back(Ch);
24065 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Chains);
24068 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
24069 // the FP state in cases where an emms may be missing.
24070 // A preferable solution to the general problem is to figure out the right
24071 // places to insert EMMS. This qualifies as a quick hack.
24073 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
24074 if (VT.getSizeInBits() != 64)
24077 const Function *F = DAG.getMachineFunction().getFunction();
24078 bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);
24080 !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();
24081 if ((VT.isVector() ||
24082 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
24083 isa<LoadSDNode>(St->getValue()) &&
24084 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
24085 St->getChain().hasOneUse() && !St->isVolatile()) {
24086 SDNode* LdVal = St->getValue().getNode();
24087 LoadSDNode *Ld = nullptr;
24088 int TokenFactorIndex = -1;
24089 SmallVector<SDValue, 8> Ops;
24090 SDNode* ChainVal = St->getChain().getNode();
24091 // Must be a store of a load. We currently handle two cases: the load
24092 // is a direct child, and it's under an intervening TokenFactor. It is
24093 // possible to dig deeper under nested TokenFactors.
24094 if (ChainVal == LdVal)
24095 Ld = cast<LoadSDNode>(St->getChain());
24096 else if (St->getValue().hasOneUse() &&
24097 ChainVal->getOpcode() == ISD::TokenFactor) {
24098 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
24099 if (ChainVal->getOperand(i).getNode() == LdVal) {
24100 TokenFactorIndex = i;
24101 Ld = cast<LoadSDNode>(St->getValue());
24103 Ops.push_back(ChainVal->getOperand(i));
24107 if (!Ld || !ISD::isNormalLoad(Ld))
24110 // If this is not the MMX case, i.e. we are just turning i64 load/store
24111 // into f64 load/store, avoid the transformation if there are multiple
24112 // uses of the loaded value.
24113 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
24118 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
24119 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
24121 if (Subtarget->is64Bit() || F64IsLegal) {
24122 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
24123 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
24124 Ld->getPointerInfo(), Ld->isVolatile(),
24125 Ld->isNonTemporal(), Ld->isInvariant(),
24126 Ld->getAlignment());
24127 SDValue NewChain = NewLd.getValue(1);
24128 if (TokenFactorIndex != -1) {
24129 Ops.push_back(NewChain);
24130 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24132 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
24133 St->getPointerInfo(),
24134 St->isVolatile(), St->isNonTemporal(),
24135 St->getAlignment());
24138 // Otherwise, lower to two pairs of 32-bit loads / stores.
24139 SDValue LoAddr = Ld->getBasePtr();
24140 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
24141 DAG.getConstant(4, LdDL, MVT::i32));
24143 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
24144 Ld->getPointerInfo(),
24145 Ld->isVolatile(), Ld->isNonTemporal(),
24146 Ld->isInvariant(), Ld->getAlignment());
24147 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
24148 Ld->getPointerInfo().getWithOffset(4),
24149 Ld->isVolatile(), Ld->isNonTemporal(),
24151 MinAlign(Ld->getAlignment(), 4));
24153 SDValue NewChain = LoLd.getValue(1);
24154 if (TokenFactorIndex != -1) {
24155 Ops.push_back(LoLd);
24156 Ops.push_back(HiLd);
24157 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, Ops);
24160 LoAddr = St->getBasePtr();
24161 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
24162 DAG.getConstant(4, StDL, MVT::i32));
24164 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
24165 St->getPointerInfo(),
24166 St->isVolatile(), St->isNonTemporal(),
24167 St->getAlignment());
24168 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
24169 St->getPointerInfo().getWithOffset(4),
24171 St->isNonTemporal(),
24172 MinAlign(St->getAlignment(), 4));
24173 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
24176 // This is similar to the above case, but here we handle a scalar 64-bit
24177 // integer store that is extracted from a vector on a 32-bit target.
24178 // If we have SSE2, then we can treat it like a floating-point double
24179 // to get past legalization. The execution dependencies fixup pass will
24180 // choose the optimal machine instruction for the store if this really is
24181 // an integer or v2f32 rather than an f64.
24182 if (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit() &&
24183 St->getOperand(1).getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
24184 SDValue OldExtract = St->getOperand(1);
24185 SDValue ExtOp0 = OldExtract.getOperand(0);
24186 unsigned VecSize = ExtOp0.getValueSizeInBits();
24187 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, VecSize / 64);
24188 SDValue BitCast = DAG.getBitcast(VecVT, ExtOp0);
24189 SDValue NewExtract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
24190 BitCast, OldExtract.getOperand(1));
24191 return DAG.getStore(St->getChain(), dl, NewExtract, St->getBasePtr(),
24192 St->getPointerInfo(), St->isVolatile(),
24193 St->isNonTemporal(), St->getAlignment());
24199 /// Return 'true' if this vector operation is "horizontal"
24200 /// and return the operands for the horizontal operation in LHS and RHS. A
24201 /// horizontal operation performs the binary operation on successive elements
24202 /// of its first operand, then on successive elements of its second operand,
24203 /// returning the resulting values in a vector. For example, if
24204 /// A = < float a0, float a1, float a2, float a3 >
24206 /// B = < float b0, float b1, float b2, float b3 >
24207 /// then the result of doing a horizontal operation on A and B is
24208 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
24209 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
24210 /// A horizontal-op B, for some already available A and B, and if so then LHS is
24211 /// set to A, RHS to B, and the routine returns 'true'.
24212 /// Note that the binary operation should have the property that if one of the
24213 /// operands is UNDEF then the result is UNDEF.
24214 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
24215 // Look for the following pattern: if
24216 // A = < float a0, float a1, float a2, float a3 >
24217 // B = < float b0, float b1, float b2, float b3 >
24219 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
24220 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
24221 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
24222 // which is A horizontal-op B.
24224 // At least one of the operands should be a vector shuffle.
24225 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
24226 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
24229 MVT VT = LHS.getSimpleValueType();
24231 assert((VT.is128BitVector() || VT.is256BitVector()) &&
24232 "Unsupported vector type for horizontal add/sub");
24234 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
24235 // operate independently on 128-bit lanes.
24236 unsigned NumElts = VT.getVectorNumElements();
24237 unsigned NumLanes = VT.getSizeInBits()/128;
24238 unsigned NumLaneElts = NumElts / NumLanes;
24239 assert((NumLaneElts % 2 == 0) &&
24240 "Vector type should have an even number of elements in each lane");
24241 unsigned HalfLaneElts = NumLaneElts/2;
24243 // View LHS in the form
24244 // LHS = VECTOR_SHUFFLE A, B, LMask
24245 // If LHS is not a shuffle then pretend it is the shuffle
24246 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
24247 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
24250 SmallVector<int, 16> LMask(NumElts);
24251 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24252 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
24253 A = LHS.getOperand(0);
24254 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
24255 B = LHS.getOperand(1);
24256 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
24257 std::copy(Mask.begin(), Mask.end(), LMask.begin());
24259 if (LHS.getOpcode() != ISD::UNDEF)
24261 for (unsigned i = 0; i != NumElts; ++i)
24265 // Likewise, view RHS in the form
24266 // RHS = VECTOR_SHUFFLE C, D, RMask
24268 SmallVector<int, 16> RMask(NumElts);
24269 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
24270 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
24271 C = RHS.getOperand(0);
24272 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
24273 D = RHS.getOperand(1);
24274 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
24275 std::copy(Mask.begin(), Mask.end(), RMask.begin());
24277 if (RHS.getOpcode() != ISD::UNDEF)
24279 for (unsigned i = 0; i != NumElts; ++i)
24283 // Check that the shuffles are both shuffling the same vectors.
24284 if (!(A == C && B == D) && !(A == D && B == C))
24287 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
24288 if (!A.getNode() && !B.getNode())
24291 // If A and B occur in reverse order in RHS, then "swap" them (which means
24292 // rewriting the mask).
24294 ShuffleVectorSDNode::commuteMask(RMask);
24296 // At this point LHS and RHS are equivalent to
24297 // LHS = VECTOR_SHUFFLE A, B, LMask
24298 // RHS = VECTOR_SHUFFLE A, B, RMask
24299 // Check that the masks correspond to performing a horizontal operation.
24300 for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
24301 for (unsigned i = 0; i != NumLaneElts; ++i) {
24302 int LIdx = LMask[i+l], RIdx = RMask[i+l];
24304 // Ignore any UNDEF components.
24305 if (LIdx < 0 || RIdx < 0 ||
24306 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
24307 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
24310 // Check that successive elements are being operated on. If not, this is
24311 // not a horizontal operation.
24312 unsigned Src = (i/HalfLaneElts); // each lane is split between srcs
24313 int Index = 2*(i%HalfLaneElts) + NumElts*Src + l;
24314 if (!(LIdx == Index && RIdx == Index + 1) &&
24315 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
24320 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
24321 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
24325 /// Do target-specific dag combines on floating point adds.
24326 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
24327 const X86Subtarget *Subtarget) {
24328 EVT VT = N->getValueType(0);
24329 SDValue LHS = N->getOperand(0);
24330 SDValue RHS = N->getOperand(1);
24332 // Try to synthesize horizontal adds from adds of shuffles.
24333 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24334 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24335 isHorizontalBinOp(LHS, RHS, true))
24336 return DAG.getNode(X86ISD::FHADD, SDLoc(N), VT, LHS, RHS);
24340 /// Do target-specific dag combines on floating point subs.
24341 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
24342 const X86Subtarget *Subtarget) {
24343 EVT VT = N->getValueType(0);
24344 SDValue LHS = N->getOperand(0);
24345 SDValue RHS = N->getOperand(1);
24347 // Try to synthesize horizontal subs from subs of shuffles.
24348 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
24349 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
24350 isHorizontalBinOp(LHS, RHS, false))
24351 return DAG.getNode(X86ISD::FHSUB, SDLoc(N), VT, LHS, RHS);
24355 /// Do target-specific dag combines on X86ISD::FOR and X86ISD::FXOR nodes.
24356 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
24357 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
24359 // F[X]OR(0.0, x) -> x
24360 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24361 if (C->getValueAPF().isPosZero())
24362 return N->getOperand(1);
24364 // F[X]OR(x, 0.0) -> x
24365 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24366 if (C->getValueAPF().isPosZero())
24367 return N->getOperand(0);
24371 /// Do target-specific dag combines on X86ISD::FMIN and X86ISD::FMAX nodes.
24372 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
24373 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
24375 // Only perform optimizations if UnsafeMath is used.
24376 if (!DAG.getTarget().Options.UnsafeFPMath)
24379 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
24380 // into FMINC and FMAXC, which are Commutative operations.
24381 unsigned NewOp = 0;
24382 switch (N->getOpcode()) {
24383 default: llvm_unreachable("unknown opcode");
24384 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
24385 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
24388 return DAG.getNode(NewOp, SDLoc(N), N->getValueType(0),
24389 N->getOperand(0), N->getOperand(1));
24392 /// Do target-specific dag combines on X86ISD::FAND nodes.
24393 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
24394 // FAND(0.0, x) -> 0.0
24395 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24396 if (C->getValueAPF().isPosZero())
24397 return N->getOperand(0);
24399 // FAND(x, 0.0) -> 0.0
24400 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24401 if (C->getValueAPF().isPosZero())
24402 return N->getOperand(1);
24407 /// Do target-specific dag combines on X86ISD::FANDN nodes
24408 static SDValue PerformFANDNCombine(SDNode *N, SelectionDAG &DAG) {
24409 // FANDN(0.0, x) -> x
24410 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
24411 if (C->getValueAPF().isPosZero())
24412 return N->getOperand(1);
24414 // FANDN(x, 0.0) -> 0.0
24415 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
24416 if (C->getValueAPF().isPosZero())
24417 return N->getOperand(1);
24422 static SDValue PerformBTCombine(SDNode *N,
24424 TargetLowering::DAGCombinerInfo &DCI) {
24425 // BT ignores high bits in the bit index operand.
24426 SDValue Op1 = N->getOperand(1);
24427 if (Op1.hasOneUse()) {
24428 unsigned BitWidth = Op1.getValueSizeInBits();
24429 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
24430 APInt KnownZero, KnownOne;
24431 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
24432 !DCI.isBeforeLegalizeOps());
24433 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24434 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
24435 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
24436 DCI.CommitTargetLoweringOpt(TLO);
24441 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
24442 SDValue Op = N->getOperand(0);
24443 if (Op.getOpcode() == ISD::BITCAST)
24444 Op = Op.getOperand(0);
24445 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
24446 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
24447 VT.getVectorElementType().getSizeInBits() ==
24448 OpVT.getVectorElementType().getSizeInBits()) {
24449 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
24454 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
24455 const X86Subtarget *Subtarget) {
24456 EVT VT = N->getValueType(0);
24457 if (!VT.isVector())
24460 SDValue N0 = N->getOperand(0);
24461 SDValue N1 = N->getOperand(1);
24462 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
24465 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
24466 // both SSE and AVX2 since there is no sign-extended shift right
24467 // operation on a vector with 64-bit elements.
24468 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
24469 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
24470 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
24471 N0.getOpcode() == ISD::SIGN_EXTEND)) {
24472 SDValue N00 = N0.getOperand(0);
24474 // EXTLOAD has a better solution on AVX2,
24475 // it may be replaced with X86ISD::VSEXT node.
24476 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
24477 if (!ISD::isNormalLoad(N00.getNode()))
24480 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
24481 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
24483 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
24489 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
24490 TargetLowering::DAGCombinerInfo &DCI,
24491 const X86Subtarget *Subtarget) {
24492 SDValue N0 = N->getOperand(0);
24493 EVT VT = N->getValueType(0);
24494 EVT SVT = VT.getScalarType();
24495 EVT InVT = N0.getValueType();
24496 EVT InSVT = InVT.getScalarType();
24499 // (i8,i32 sext (sdivrem (i8 x, i8 y)) ->
24500 // (i8,i32 (sdivrem_sext_hreg (i8 x, i8 y)
24501 // This exposes the sext to the sdivrem lowering, so that it directly extends
24502 // from AH (which we otherwise need to do contortions to access).
24503 if (N0.getOpcode() == ISD::SDIVREM && N0.getResNo() == 1 &&
24504 InVT == MVT::i8 && VT == MVT::i32) {
24505 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24506 SDValue R = DAG.getNode(X86ISD::SDIVREM8_SEXT_HREG, DL, NodeTys,
24507 N0.getOperand(0), N0.getOperand(1));
24508 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24509 return R.getValue(1);
24512 if (!DCI.isBeforeLegalizeOps()) {
24513 if (InVT == MVT::i1) {
24514 SDValue Zero = DAG.getConstant(0, DL, VT);
24516 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL, VT);
24517 return DAG.getNode(ISD::SELECT, DL, VT, N0, AllOnes, Zero);
24522 if (VT.isVector() && Subtarget->hasSSE2()) {
24523 auto ExtendVecSize = [&DAG](SDLoc DL, SDValue N, unsigned Size) {
24524 EVT InVT = N.getValueType();
24525 EVT OutVT = EVT::getVectorVT(*DAG.getContext(), InVT.getScalarType(),
24526 Size / InVT.getScalarSizeInBits());
24527 SmallVector<SDValue, 8> Opnds(Size / InVT.getSizeInBits(),
24528 DAG.getUNDEF(InVT));
24530 return DAG.getNode(ISD::CONCAT_VECTORS, DL, OutVT, Opnds);
24533 // If target-size is less than 128-bits, extend to a type that would extend
24534 // to 128 bits, extend that and extract the original target vector.
24535 if (VT.getSizeInBits() < 128 && !(128 % VT.getSizeInBits()) &&
24536 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24537 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24538 unsigned Scale = 128 / VT.getSizeInBits();
24540 EVT::getVectorVT(*DAG.getContext(), SVT, 128 / SVT.getSizeInBits());
24541 SDValue Ex = ExtendVecSize(DL, N0, Scale * InVT.getSizeInBits());
24542 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, ExVT, Ex);
24543 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, SExt,
24544 DAG.getIntPtrConstant(0, DL));
24547 // If target-size is 128-bits, then convert to ISD::SIGN_EXTEND_VECTOR_INREG
24548 // which ensures lowering to X86ISD::VSEXT (pmovsx*).
24549 if (VT.getSizeInBits() == 128 &&
24550 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24551 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24552 SDValue ExOp = ExtendVecSize(DL, N0, 128);
24553 return DAG.getSignExtendVectorInReg(ExOp, DL, VT);
24556 // On pre-AVX2 targets, split into 128-bit nodes of
24557 // ISD::SIGN_EXTEND_VECTOR_INREG.
24558 if (!Subtarget->hasInt256() && !(VT.getSizeInBits() % 128) &&
24559 (SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16) &&
24560 (InSVT == MVT::i32 || InSVT == MVT::i16 || InSVT == MVT::i8)) {
24561 unsigned NumVecs = VT.getSizeInBits() / 128;
24562 unsigned NumSubElts = 128 / SVT.getSizeInBits();
24563 EVT SubVT = EVT::getVectorVT(*DAG.getContext(), SVT, NumSubElts);
24564 EVT InSubVT = EVT::getVectorVT(*DAG.getContext(), InSVT, NumSubElts);
24566 SmallVector<SDValue, 8> Opnds;
24567 for (unsigned i = 0, Offset = 0; i != NumVecs;
24568 ++i, Offset += NumSubElts) {
24569 SDValue SrcVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InSubVT, N0,
24570 DAG.getIntPtrConstant(Offset, DL));
24571 SrcVec = ExtendVecSize(DL, SrcVec, 128);
24572 SrcVec = DAG.getSignExtendVectorInReg(SrcVec, DL, SubVT);
24573 Opnds.push_back(SrcVec);
24575 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Opnds);
24579 if (!Subtarget->hasFp256())
24582 if (VT.isVector() && VT.getSizeInBits() == 256)
24583 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24589 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
24590 const X86Subtarget* Subtarget) {
24592 EVT VT = N->getValueType(0);
24594 // Let legalize expand this if it isn't a legal type yet.
24595 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
24598 EVT ScalarVT = VT.getScalarType();
24599 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
24600 (!Subtarget->hasFMA() && !Subtarget->hasFMA4() &&
24601 !Subtarget->hasAVX512()))
24604 SDValue A = N->getOperand(0);
24605 SDValue B = N->getOperand(1);
24606 SDValue C = N->getOperand(2);
24608 bool NegA = (A.getOpcode() == ISD::FNEG);
24609 bool NegB = (B.getOpcode() == ISD::FNEG);
24610 bool NegC = (C.getOpcode() == ISD::FNEG);
24612 // Negative multiplication when NegA xor NegB
24613 bool NegMul = (NegA != NegB);
24615 A = A.getOperand(0);
24617 B = B.getOperand(0);
24619 C = C.getOperand(0);
24623 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
24625 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
24627 return DAG.getNode(Opcode, dl, VT, A, B, C);
24630 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
24631 TargetLowering::DAGCombinerInfo &DCI,
24632 const X86Subtarget *Subtarget) {
24633 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
24634 // (and (i32 x86isd::setcc_carry), 1)
24635 // This eliminates the zext. This transformation is necessary because
24636 // ISD::SETCC is always legalized to i8.
24638 SDValue N0 = N->getOperand(0);
24639 EVT VT = N->getValueType(0);
24641 if (N0.getOpcode() == ISD::AND &&
24643 N0.getOperand(0).hasOneUse()) {
24644 SDValue N00 = N0.getOperand(0);
24645 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24646 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
24647 if (!C || C->getZExtValue() != 1)
24649 return DAG.getNode(ISD::AND, dl, VT,
24650 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24651 N00.getOperand(0), N00.getOperand(1)),
24652 DAG.getConstant(1, dl, VT));
24656 if (N0.getOpcode() == ISD::TRUNCATE &&
24658 N0.getOperand(0).hasOneUse()) {
24659 SDValue N00 = N0.getOperand(0);
24660 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
24661 return DAG.getNode(ISD::AND, dl, VT,
24662 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
24663 N00.getOperand(0), N00.getOperand(1)),
24664 DAG.getConstant(1, dl, VT));
24668 if (VT.is256BitVector())
24669 if (SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget))
24672 // (i8,i32 zext (udivrem (i8 x, i8 y)) ->
24673 // (i8,i32 (udivrem_zext_hreg (i8 x, i8 y)
24674 // This exposes the zext to the udivrem lowering, so that it directly extends
24675 // from AH (which we otherwise need to do contortions to access).
24676 if (N0.getOpcode() == ISD::UDIVREM &&
24677 N0.getResNo() == 1 && N0.getValueType() == MVT::i8 &&
24678 (VT == MVT::i32 || VT == MVT::i64)) {
24679 SDVTList NodeTys = DAG.getVTList(MVT::i8, VT);
24680 SDValue R = DAG.getNode(X86ISD::UDIVREM8_ZEXT_HREG, dl, NodeTys,
24681 N0.getOperand(0), N0.getOperand(1));
24682 DAG.ReplaceAllUsesOfValueWith(N0.getValue(0), R.getValue(0));
24683 return R.getValue(1);
24689 // Optimize x == -y --> x+y == 0
24690 // x != -y --> x+y != 0
24691 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG,
24692 const X86Subtarget* Subtarget) {
24693 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
24694 SDValue LHS = N->getOperand(0);
24695 SDValue RHS = N->getOperand(1);
24696 EVT VT = N->getValueType(0);
24699 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
24700 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
24701 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
24702 SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,
24703 LHS.getOperand(1));
24704 return DAG.getSetCC(DL, N->getValueType(0), addV,
24705 DAG.getConstant(0, DL, addV.getValueType()), CC);
24707 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
24708 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
24709 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
24710 SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,
24711 RHS.getOperand(1));
24712 return DAG.getSetCC(DL, N->getValueType(0), addV,
24713 DAG.getConstant(0, DL, addV.getValueType()), CC);
24716 if (VT.getScalarType() == MVT::i1 &&
24717 (CC == ISD::SETNE || CC == ISD::SETEQ || ISD::isSignedIntSetCC(CC))) {
24719 (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24720 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24721 bool IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24723 if (!IsSEXT0 || !IsVZero1) {
24724 // Swap the operands and update the condition code.
24725 std::swap(LHS, RHS);
24726 CC = ISD::getSetCCSwappedOperands(CC);
24728 IsSEXT0 = (LHS.getOpcode() == ISD::SIGN_EXTEND) &&
24729 (LHS.getOperand(0).getValueType().getScalarType() == MVT::i1);
24730 IsVZero1 = ISD::isBuildVectorAllZeros(RHS.getNode());
24733 if (IsSEXT0 && IsVZero1) {
24734 assert(VT == LHS.getOperand(0).getValueType() &&
24735 "Uexpected operand type");
24736 if (CC == ISD::SETGT)
24737 return DAG.getConstant(0, DL, VT);
24738 if (CC == ISD::SETLE)
24739 return DAG.getConstant(1, DL, VT);
24740 if (CC == ISD::SETEQ || CC == ISD::SETGE)
24741 return DAG.getNOT(DL, LHS.getOperand(0), VT);
24743 assert((CC == ISD::SETNE || CC == ISD::SETLT) &&
24744 "Unexpected condition code!");
24745 return LHS.getOperand(0);
24752 static SDValue NarrowVectorLoadToElement(LoadSDNode *Load, unsigned Index,
24753 SelectionDAG &DAG) {
24755 MVT VT = Load->getSimpleValueType(0);
24756 MVT EVT = VT.getVectorElementType();
24757 SDValue Addr = Load->getOperand(1);
24758 SDValue NewAddr = DAG.getNode(
24759 ISD::ADD, dl, Addr.getSimpleValueType(), Addr,
24760 DAG.getConstant(Index * EVT.getStoreSize(), dl,
24761 Addr.getSimpleValueType()));
24764 DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,
24765 DAG.getMachineFunction().getMachineMemOperand(
24766 Load->getMemOperand(), 0, EVT.getStoreSize()));
24770 static SDValue PerformINSERTPSCombine(SDNode *N, SelectionDAG &DAG,
24771 const X86Subtarget *Subtarget) {
24773 MVT VT = N->getOperand(1)->getSimpleValueType(0);
24774 assert((VT == MVT::v4f32 || VT == MVT::v4i32) &&
24775 "X86insertps is only defined for v4x32");
24777 SDValue Ld = N->getOperand(1);
24778 if (MayFoldLoad(Ld)) {
24779 // Extract the countS bits from the immediate so we can get the proper
24780 // address when narrowing the vector load to a specific element.
24781 // When the second source op is a memory address, insertps doesn't use
24782 // countS and just gets an f32 from that address.
24783 unsigned DestIndex =
24784 cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() >> 6;
24786 Ld = NarrowVectorLoadToElement(cast<LoadSDNode>(Ld), DestIndex, DAG);
24788 // Create this as a scalar to vector to match the instruction pattern.
24789 SDValue LoadScalarToVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Ld);
24790 // countS bits are ignored when loading from memory on insertps, which
24791 // means we don't need to explicitly set them to 0.
24792 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N->getOperand(0),
24793 LoadScalarToVector, N->getOperand(2));
24798 static SDValue PerformBLENDICombine(SDNode *N, SelectionDAG &DAG) {
24799 SDValue V0 = N->getOperand(0);
24800 SDValue V1 = N->getOperand(1);
24802 EVT VT = N->getValueType(0);
24804 // Canonicalize a v2f64 blend with a mask of 2 by swapping the vector
24805 // operands and changing the mask to 1. This saves us a bunch of
24806 // pattern-matching possibilities related to scalar math ops in SSE/AVX.
24807 // x86InstrInfo knows how to commute this back after instruction selection
24808 // if it would help register allocation.
24810 // TODO: If optimizing for size or a processor that doesn't suffer from
24811 // partial register update stalls, this should be transformed into a MOVSD
24812 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
24814 if (VT == MVT::v2f64)
24815 if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
24816 if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
24817 SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
24818 return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
24824 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
24825 // as "sbb reg,reg", since it can be extended without zext and produces
24826 // an all-ones bit which is more useful than 0/1 in some cases.
24827 static SDValue MaterializeSETB(SDLoc DL, SDValue EFLAGS, SelectionDAG &DAG,
24830 return DAG.getNode(ISD::AND, DL, VT,
24831 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24832 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24834 DAG.getConstant(1, DL, VT));
24835 assert (VT == MVT::i1 && "Unexpected type for SECCC node");
24836 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,
24837 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
24838 DAG.getConstant(X86::COND_B, DL, MVT::i8),
24842 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
24843 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
24844 TargetLowering::DAGCombinerInfo &DCI,
24845 const X86Subtarget *Subtarget) {
24847 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
24848 SDValue EFLAGS = N->getOperand(1);
24850 if (CC == X86::COND_A) {
24851 // Try to convert COND_A into COND_B in an attempt to facilitate
24852 // materializing "setb reg".
24854 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
24855 // cannot take an immediate as its first operand.
24857 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
24858 EFLAGS.getValueType().isInteger() &&
24859 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
24860 SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
24861 EFLAGS.getNode()->getVTList(),
24862 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
24863 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
24864 return MaterializeSETB(DL, NewEFLAGS, DAG, N->getSimpleValueType(0));
24868 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
24869 // a zext and produces an all-ones bit which is more useful than 0/1 in some
24871 if (CC == X86::COND_B)
24872 return MaterializeSETB(DL, EFLAGS, DAG, N->getSimpleValueType(0));
24874 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24875 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24876 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
24882 // Optimize branch condition evaluation.
24884 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
24885 TargetLowering::DAGCombinerInfo &DCI,
24886 const X86Subtarget *Subtarget) {
24888 SDValue Chain = N->getOperand(0);
24889 SDValue Dest = N->getOperand(1);
24890 SDValue EFLAGS = N->getOperand(3);
24891 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
24893 if (SDValue Flags = checkBoolTestSetCCCombine(EFLAGS, CC)) {
24894 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);
24895 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
24902 static SDValue performVectorCompareAndMaskUnaryOpCombine(SDNode *N,
24903 SelectionDAG &DAG) {
24904 // Take advantage of vector comparisons producing 0 or -1 in each lane to
24905 // optimize away operation when it's from a constant.
24907 // The general transformation is:
24908 // UNARYOP(AND(VECTOR_CMP(x,y), constant)) -->
24909 // AND(VECTOR_CMP(x,y), constant2)
24910 // constant2 = UNARYOP(constant)
24912 // Early exit if this isn't a vector operation, the operand of the
24913 // unary operation isn't a bitwise AND, or if the sizes of the operations
24914 // aren't the same.
24915 EVT VT = N->getValueType(0);
24916 if (!VT.isVector() || N->getOperand(0)->getOpcode() != ISD::AND ||
24917 N->getOperand(0)->getOperand(0)->getOpcode() != ISD::SETCC ||
24918 VT.getSizeInBits() != N->getOperand(0)->getValueType(0).getSizeInBits())
24921 // Now check that the other operand of the AND is a constant. We could
24922 // make the transformation for non-constant splats as well, but it's unclear
24923 // that would be a benefit as it would not eliminate any operations, just
24924 // perform one more step in scalar code before moving to the vector unit.
24925 if (BuildVectorSDNode *BV =
24926 dyn_cast<BuildVectorSDNode>(N->getOperand(0)->getOperand(1))) {
24927 // Bail out if the vector isn't a constant.
24928 if (!BV->isConstant())
24931 // Everything checks out. Build up the new and improved node.
24933 EVT IntVT = BV->getValueType(0);
24934 // Create a new constant of the appropriate type for the transformed
24936 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0));
24937 // The AND node needs bitcasts to/from an integer vector type around it.
24938 SDValue MaskConst = DAG.getBitcast(IntVT, SourceConst);
24939 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT,
24940 N->getOperand(0)->getOperand(0), MaskConst);
24941 SDValue Res = DAG.getBitcast(VT, NewAnd);
24948 static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24949 const X86Subtarget *Subtarget) {
24950 SDValue Op0 = N->getOperand(0);
24951 EVT VT = N->getValueType(0);
24952 EVT InVT = Op0.getValueType();
24953 EVT InSVT = InVT.getScalarType();
24954 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
24956 // UINT_TO_FP(vXi8) -> SINT_TO_FP(ZEXT(vXi8 to vXi32))
24957 // UINT_TO_FP(vXi16) -> SINT_TO_FP(ZEXT(vXi16 to vXi32))
24958 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
24960 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
24961 InVT.getVectorNumElements());
24962 SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
24964 if (TLI.isOperationLegal(ISD::UINT_TO_FP, DstVT))
24965 return DAG.getNode(ISD::UINT_TO_FP, dl, VT, P);
24967 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
24973 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
24974 const X86Subtarget *Subtarget) {
24975 // First try to optimize away the conversion entirely when it's
24976 // conditionally from a constant. Vectors only.
24977 if (SDValue Res = performVectorCompareAndMaskUnaryOpCombine(N, DAG))
24980 // Now move on to more general possibilities.
24981 SDValue Op0 = N->getOperand(0);
24982 EVT VT = N->getValueType(0);
24983 EVT InVT = Op0.getValueType();
24984 EVT InSVT = InVT.getScalarType();
24986 // SINT_TO_FP(vXi8) -> SINT_TO_FP(SEXT(vXi8 to vXi32))
24987 // SINT_TO_FP(vXi16) -> SINT_TO_FP(SEXT(vXi16 to vXi32))
24988 if (InVT.isVector() && (InSVT == MVT::i8 || InSVT == MVT::i16)) {
24990 EVT DstVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
24991 InVT.getVectorNumElements());
24992 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
24993 return DAG.getNode(ISD::SINT_TO_FP, dl, VT, P);
24996 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
24997 // a 32-bit target where SSE doesn't support i64->FP operations.
24998 if (Op0.getOpcode() == ISD::LOAD) {
24999 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
25000 EVT LdVT = Ld->getValueType(0);
25002 // This transformation is not supported if the result type is f16
25003 if (VT == MVT::f16)
25006 if (!Ld->isVolatile() && !VT.isVector() &&
25007 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
25008 !Subtarget->is64Bit() && LdVT == MVT::i64) {
25009 SDValue FILDChain = Subtarget->getTargetLowering()->BuildFILD(
25010 SDValue(N, 0), LdVT, Ld->getChain(), Op0, DAG);
25011 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
25018 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
25019 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
25020 X86TargetLowering::DAGCombinerInfo &DCI) {
25021 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
25022 // the result is either zero or one (depending on the input carry bit).
25023 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
25024 if (X86::isZeroNode(N->getOperand(0)) &&
25025 X86::isZeroNode(N->getOperand(1)) &&
25026 // We don't have a good way to replace an EFLAGS use, so only do this when
25028 SDValue(N, 1).use_empty()) {
25030 EVT VT = N->getValueType(0);
25031 SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));
25032 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
25033 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
25034 DAG.getConstant(X86::COND_B, DL,
25037 DAG.getConstant(1, DL, VT));
25038 return DCI.CombineTo(N, Res1, CarryOut);
25044 // fold (add Y, (sete X, 0)) -> adc 0, Y
25045 // (add Y, (setne X, 0)) -> sbb -1, Y
25046 // (sub (sete X, 0), Y) -> sbb 0, Y
25047 // (sub (setne X, 0), Y) -> adc -1, Y
25048 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
25051 // Look through ZExts.
25052 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
25053 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
25056 SDValue SetCC = Ext.getOperand(0);
25057 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
25060 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
25061 if (CC != X86::COND_E && CC != X86::COND_NE)
25064 SDValue Cmp = SetCC.getOperand(1);
25065 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
25066 !X86::isZeroNode(Cmp.getOperand(1)) ||
25067 !Cmp.getOperand(0).getValueType().isInteger())
25070 SDValue CmpOp0 = Cmp.getOperand(0);
25071 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
25072 DAG.getConstant(1, DL, CmpOp0.getValueType()));
25074 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
25075 if (CC == X86::COND_NE)
25076 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
25077 DL, OtherVal.getValueType(), OtherVal,
25078 DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),
25080 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
25081 DL, OtherVal.getValueType(), OtherVal,
25082 DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);
25085 /// PerformADDCombine - Do target-specific dag combines on integer adds.
25086 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
25087 const X86Subtarget *Subtarget) {
25088 EVT VT = N->getValueType(0);
25089 SDValue Op0 = N->getOperand(0);
25090 SDValue Op1 = N->getOperand(1);
25092 // Try to synthesize horizontal adds from adds of shuffles.
25093 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25094 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25095 isHorizontalBinOp(Op0, Op1, true))
25096 return DAG.getNode(X86ISD::HADD, SDLoc(N), VT, Op0, Op1);
25098 return OptimizeConditionalInDecrement(N, DAG);
25101 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
25102 const X86Subtarget *Subtarget) {
25103 SDValue Op0 = N->getOperand(0);
25104 SDValue Op1 = N->getOperand(1);
25106 // X86 can't encode an immediate LHS of a sub. See if we can push the
25107 // negation into a preceding instruction.
25108 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
25109 // If the RHS of the sub is a XOR with one use and a constant, invert the
25110 // immediate. Then add one to the LHS of the sub so we can turn
25111 // X-Y -> X+~Y+1, saving one register.
25112 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
25113 isa<ConstantSDNode>(Op1.getOperand(1))) {
25114 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
25115 EVT VT = Op0.getValueType();
25116 SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
25118 DAG.getConstant(~XorC, SDLoc(Op1), VT));
25119 return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,
25120 DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));
25124 // Try to synthesize horizontal adds from adds of shuffles.
25125 EVT VT = N->getValueType(0);
25126 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
25127 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
25128 isHorizontalBinOp(Op0, Op1, true))
25129 return DAG.getNode(X86ISD::HSUB, SDLoc(N), VT, Op0, Op1);
25131 return OptimizeConditionalInDecrement(N, DAG);
25134 /// performVZEXTCombine - Performs build vector combines
25135 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
25136 TargetLowering::DAGCombinerInfo &DCI,
25137 const X86Subtarget *Subtarget) {
25139 MVT VT = N->getSimpleValueType(0);
25140 SDValue Op = N->getOperand(0);
25141 MVT OpVT = Op.getSimpleValueType();
25142 MVT OpEltVT = OpVT.getVectorElementType();
25143 unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
25145 // (vzext (bitcast (vzext (x)) -> (vzext x)
25147 while (V.getOpcode() == ISD::BITCAST)
25148 V = V.getOperand(0);
25150 if (V != Op && V.getOpcode() == X86ISD::VZEXT) {
25151 MVT InnerVT = V.getSimpleValueType();
25152 MVT InnerEltVT = InnerVT.getVectorElementType();
25154 // If the element sizes match exactly, we can just do one larger vzext. This
25155 // is always an exact type match as vzext operates on integer types.
25156 if (OpEltVT == InnerEltVT) {
25157 assert(OpVT == InnerVT && "Types must match for vzext!");
25158 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0));
25161 // The only other way we can combine them is if only a single element of the
25162 // inner vzext is used in the input to the outer vzext.
25163 if (InnerEltVT.getSizeInBits() < InputBits)
25166 // In this case, the inner vzext is completely dead because we're going to
25167 // only look at bits inside of the low element. Just do the outer vzext on
25168 // a bitcast of the input to the inner.
25169 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V));
25172 // Check if we can bypass extracting and re-inserting an element of an input
25173 // vector. Essentialy:
25174 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
25175 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR &&
25176 V.getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
25177 V.getOperand(0).getSimpleValueType().getSizeInBits() == InputBits) {
25178 SDValue ExtractedV = V.getOperand(0);
25179 SDValue OrigV = ExtractedV.getOperand(0);
25180 if (auto *ExtractIdx = dyn_cast<ConstantSDNode>(ExtractedV.getOperand(1)))
25181 if (ExtractIdx->getZExtValue() == 0) {
25182 MVT OrigVT = OrigV.getSimpleValueType();
25183 // Extract a subvector if necessary...
25184 if (OrigVT.getSizeInBits() > OpVT.getSizeInBits()) {
25185 int Ratio = OrigVT.getSizeInBits() / OpVT.getSizeInBits();
25186 OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),
25187 OrigVT.getVectorNumElements() / Ratio);
25188 OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,
25189 DAG.getIntPtrConstant(0, DL));
25191 Op = DAG.getBitcast(OpVT, OrigV);
25192 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);
25199 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
25200 DAGCombinerInfo &DCI) const {
25201 SelectionDAG &DAG = DCI.DAG;
25202 switch (N->getOpcode()) {
25204 case ISD::EXTRACT_VECTOR_ELT:
25205 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
25208 case X86ISD::SHRUNKBLEND:
25209 return PerformSELECTCombine(N, DAG, DCI, Subtarget);
25210 case ISD::BITCAST: return PerformBITCASTCombine(N, DAG);
25211 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
25212 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
25213 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
25214 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
25215 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
25218 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
25219 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
25220 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
25221 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
25222 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
25223 case ISD::MLOAD: return PerformMLOADCombine(N, DAG, DCI, Subtarget);
25224 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
25225 case ISD::MSTORE: return PerformMSTORECombine(N, DAG, Subtarget);
25226 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, Subtarget);
25227 case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, Subtarget);
25228 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
25229 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
25231 case X86ISD::FOR: return PerformFORCombine(N, DAG);
25233 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
25234 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
25235 case X86ISD::FANDN: return PerformFANDNCombine(N, DAG);
25236 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
25237 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
25238 case ISD::ANY_EXTEND:
25239 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
25240 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
25241 case ISD::SIGN_EXTEND_INREG:
25242 return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
25243 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG, Subtarget);
25244 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
25245 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
25246 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
25247 case X86ISD::SHUFP: // Handle all target specific shuffles
25248 case X86ISD::PALIGNR:
25249 case X86ISD::UNPCKH:
25250 case X86ISD::UNPCKL:
25251 case X86ISD::MOVHLPS:
25252 case X86ISD::MOVLHPS:
25253 case X86ISD::PSHUFB:
25254 case X86ISD::PSHUFD:
25255 case X86ISD::PSHUFHW:
25256 case X86ISD::PSHUFLW:
25257 case X86ISD::MOVSS:
25258 case X86ISD::MOVSD:
25259 case X86ISD::VPERMILPI:
25260 case X86ISD::VPERM2X128:
25261 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
25262 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
25263 case ISD::INTRINSIC_WO_CHAIN:
25264 return PerformINTRINSIC_WO_CHAINCombine(N, DAG, Subtarget);
25265 case X86ISD::INSERTPS: {
25266 if (getTargetMachine().getOptLevel() > CodeGenOpt::None)
25267 return PerformINSERTPSCombine(N, DAG, Subtarget);
25270 case X86ISD::BLENDI: return PerformBLENDICombine(N, DAG);
25276 /// isTypeDesirableForOp - Return true if the target has native support for
25277 /// the specified value type and it is 'desirable' to use the type for the
25278 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
25279 /// instruction encodings are longer and some i16 instructions are slow.
25280 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
25281 if (!isTypeLegal(VT))
25283 if (VT != MVT::i16)
25290 case ISD::SIGN_EXTEND:
25291 case ISD::ZERO_EXTEND:
25292 case ISD::ANY_EXTEND:
25305 /// IsDesirableToPromoteOp - This method query the target whether it is
25306 /// beneficial for dag combiner to promote the specified node. If true, it
25307 /// should return the desired promotion type by reference.
25308 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
25309 EVT VT = Op.getValueType();
25310 if (VT != MVT::i16)
25313 bool Promote = false;
25314 bool Commute = false;
25315 switch (Op.getOpcode()) {
25318 LoadSDNode *LD = cast<LoadSDNode>(Op);
25319 // If the non-extending load has a single use and it's not live out, then it
25320 // might be folded.
25321 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
25322 Op.hasOneUse()*/) {
25323 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
25324 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
25325 // The only case where we'd want to promote LOAD (rather then it being
25326 // promoted as an operand is when it's only use is liveout.
25327 if (UI->getOpcode() != ISD::CopyToReg)
25334 case ISD::SIGN_EXTEND:
25335 case ISD::ZERO_EXTEND:
25336 case ISD::ANY_EXTEND:
25341 SDValue N0 = Op.getOperand(0);
25342 // Look out for (store (shl (load), x)).
25343 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
25356 SDValue N0 = Op.getOperand(0);
25357 SDValue N1 = Op.getOperand(1);
25358 if (!Commute && MayFoldLoad(N1))
25360 // Avoid disabling potential load folding opportunities.
25361 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
25363 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
25373 //===----------------------------------------------------------------------===//
25374 // X86 Inline Assembly Support
25375 //===----------------------------------------------------------------------===//
25377 // Helper to match a string separated by whitespace.
25378 static bool matchAsm(StringRef S, ArrayRef<const char *> Pieces) {
25379 S = S.substr(S.find_first_not_of(" \t")); // Skip leading whitespace.
25381 for (StringRef Piece : Pieces) {
25382 if (!S.startswith(Piece)) // Check if the piece matches.
25385 S = S.substr(Piece.size());
25386 StringRef::size_type Pos = S.find_first_not_of(" \t");
25387 if (Pos == 0) // We matched a prefix.
25396 static bool clobbersFlagRegisters(const SmallVector<StringRef, 4> &AsmPieces) {
25398 if (AsmPieces.size() == 3 || AsmPieces.size() == 4) {
25399 if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{cc}") &&
25400 std::count(AsmPieces.begin(), AsmPieces.end(), "~{flags}") &&
25401 std::count(AsmPieces.begin(), AsmPieces.end(), "~{fpsr}")) {
25403 if (AsmPieces.size() == 3)
25405 else if (std::count(AsmPieces.begin(), AsmPieces.end(), "~{dirflag}"))
25412 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
25413 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
25415 std::string AsmStr = IA->getAsmString();
25417 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
25418 if (!Ty || Ty->getBitWidth() % 16 != 0)
25421 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
25422 SmallVector<StringRef, 4> AsmPieces;
25423 SplitString(AsmStr, AsmPieces, ";\n");
25425 switch (AsmPieces.size()) {
25426 default: return false;
25428 // FIXME: this should verify that we are targeting a 486 or better. If not,
25429 // we will turn this bswap into something that will be lowered to logical
25430 // ops instead of emitting the bswap asm. For now, we don't support 486 or
25431 // lower so don't worry about this.
25433 if (matchAsm(AsmPieces[0], {"bswap", "$0"}) ||
25434 matchAsm(AsmPieces[0], {"bswapl", "$0"}) ||
25435 matchAsm(AsmPieces[0], {"bswapq", "$0"}) ||
25436 matchAsm(AsmPieces[0], {"bswap", "${0:q}"}) ||
25437 matchAsm(AsmPieces[0], {"bswapl", "${0:q}"}) ||
25438 matchAsm(AsmPieces[0], {"bswapq", "${0:q}"})) {
25439 // No need to check constraints, nothing other than the equivalent of
25440 // "=r,0" would be valid here.
25441 return IntrinsicLowering::LowerToByteSwap(CI);
25444 // rorw $$8, ${0:w} --> llvm.bswap.i16
25445 if (CI->getType()->isIntegerTy(16) &&
25446 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25447 (matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) ||
25448 matchAsm(AsmPieces[0], {"rolw", "$$8,", "${0:w}"}))) {
25450 StringRef ConstraintsStr = IA->getConstraintString();
25451 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25452 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25453 if (clobbersFlagRegisters(AsmPieces))
25454 return IntrinsicLowering::LowerToByteSwap(CI);
25458 if (CI->getType()->isIntegerTy(32) &&
25459 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
25460 matchAsm(AsmPieces[0], {"rorw", "$$8,", "${0:w}"}) &&
25461 matchAsm(AsmPieces[1], {"rorl", "$$16,", "$0"}) &&
25462 matchAsm(AsmPieces[2], {"rorw", "$$8,", "${0:w}"})) {
25464 StringRef ConstraintsStr = IA->getConstraintString();
25465 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
25466 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
25467 if (clobbersFlagRegisters(AsmPieces))
25468 return IntrinsicLowering::LowerToByteSwap(CI);
25471 if (CI->getType()->isIntegerTy(64)) {
25472 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
25473 if (Constraints.size() >= 2 &&
25474 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
25475 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
25476 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
25477 if (matchAsm(AsmPieces[0], {"bswap", "%eax"}) &&
25478 matchAsm(AsmPieces[1], {"bswap", "%edx"}) &&
25479 matchAsm(AsmPieces[2], {"xchgl", "%eax,", "%edx"}))
25480 return IntrinsicLowering::LowerToByteSwap(CI);
25488 /// getConstraintType - Given a constraint letter, return the type of
25489 /// constraint it is for this target.
25490 X86TargetLowering::ConstraintType
25491 X86TargetLowering::getConstraintType(StringRef Constraint) const {
25492 if (Constraint.size() == 1) {
25493 switch (Constraint[0]) {
25504 return C_RegisterClass;
25528 return TargetLowering::getConstraintType(Constraint);
25531 /// Examine constraint type and operand type and determine a weight value.
25532 /// This object must already have been set up with the operand type
25533 /// and the current alternative constraint selected.
25534 TargetLowering::ConstraintWeight
25535 X86TargetLowering::getSingleConstraintMatchWeight(
25536 AsmOperandInfo &info, const char *constraint) const {
25537 ConstraintWeight weight = CW_Invalid;
25538 Value *CallOperandVal = info.CallOperandVal;
25539 // If we don't have a value, we can't do a match,
25540 // but allow it at the lowest weight.
25541 if (!CallOperandVal)
25543 Type *type = CallOperandVal->getType();
25544 // Look at the constraint type.
25545 switch (*constraint) {
25547 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
25558 if (CallOperandVal->getType()->isIntegerTy())
25559 weight = CW_SpecificReg;
25564 if (type->isFloatingPointTy())
25565 weight = CW_SpecificReg;
25568 if (type->isX86_MMXTy() && Subtarget->hasMMX())
25569 weight = CW_SpecificReg;
25573 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
25574 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
25575 weight = CW_Register;
25578 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
25579 if (C->getZExtValue() <= 31)
25580 weight = CW_Constant;
25584 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25585 if (C->getZExtValue() <= 63)
25586 weight = CW_Constant;
25590 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25591 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
25592 weight = CW_Constant;
25596 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25597 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
25598 weight = CW_Constant;
25602 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25603 if (C->getZExtValue() <= 3)
25604 weight = CW_Constant;
25608 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25609 if (C->getZExtValue() <= 0xff)
25610 weight = CW_Constant;
25615 if (isa<ConstantFP>(CallOperandVal)) {
25616 weight = CW_Constant;
25620 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25621 if ((C->getSExtValue() >= -0x80000000LL) &&
25622 (C->getSExtValue() <= 0x7fffffffLL))
25623 weight = CW_Constant;
25627 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
25628 if (C->getZExtValue() <= 0xffffffff)
25629 weight = CW_Constant;
25636 /// LowerXConstraint - try to replace an X constraint, which matches anything,
25637 /// with another that has more specific requirements based on the type of the
25638 /// corresponding operand.
25639 const char *X86TargetLowering::
25640 LowerXConstraint(EVT ConstraintVT) const {
25641 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
25642 // 'f' like normal targets.
25643 if (ConstraintVT.isFloatingPoint()) {
25644 if (Subtarget->hasSSE2())
25646 if (Subtarget->hasSSE1())
25650 return TargetLowering::LowerXConstraint(ConstraintVT);
25653 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
25654 /// vector. If it is invalid, don't add anything to Ops.
25655 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
25656 std::string &Constraint,
25657 std::vector<SDValue>&Ops,
25658 SelectionDAG &DAG) const {
25661 // Only support length 1 constraints for now.
25662 if (Constraint.length() > 1) return;
25664 char ConstraintLetter = Constraint[0];
25665 switch (ConstraintLetter) {
25668 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25669 if (C->getZExtValue() <= 31) {
25670 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25671 Op.getValueType());
25677 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25678 if (C->getZExtValue() <= 63) {
25679 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25680 Op.getValueType());
25686 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25687 if (isInt<8>(C->getSExtValue())) {
25688 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25689 Op.getValueType());
25695 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25696 if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
25697 (Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {
25698 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
25699 Op.getValueType());
25705 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25706 if (C->getZExtValue() <= 3) {
25707 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25708 Op.getValueType());
25714 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25715 if (C->getZExtValue() <= 255) {
25716 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25717 Op.getValueType());
25723 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25724 if (C->getZExtValue() <= 127) {
25725 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25726 Op.getValueType());
25732 // 32-bit signed value
25733 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25734 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25735 C->getSExtValue())) {
25736 // Widen to 64 bits here to get it sign extended.
25737 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);
25740 // FIXME gcc accepts some relocatable values here too, but only in certain
25741 // memory models; it's complicated.
25746 // 32-bit unsigned value
25747 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
25748 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
25749 C->getZExtValue())) {
25750 Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
25751 Op.getValueType());
25755 // FIXME gcc accepts some relocatable values here too, but only in certain
25756 // memory models; it's complicated.
25760 // Literal immediates are always ok.
25761 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
25762 // Widen to 64 bits here to get it sign extended.
25763 Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
25767 // In any sort of PIC mode addresses need to be computed at runtime by
25768 // adding in a register or some sort of table lookup. These can't
25769 // be used as immediates.
25770 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
25773 // If we are in non-pic codegen mode, we allow the address of a global (with
25774 // an optional displacement) to be used with 'i'.
25775 GlobalAddressSDNode *GA = nullptr;
25776 int64_t Offset = 0;
25778 // Match either (GA), (GA+C), (GA+C1+C2), etc.
25780 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
25781 Offset += GA->getOffset();
25783 } else if (Op.getOpcode() == ISD::ADD) {
25784 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25785 Offset += C->getZExtValue();
25786 Op = Op.getOperand(0);
25789 } else if (Op.getOpcode() == ISD::SUB) {
25790 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
25791 Offset += -C->getZExtValue();
25792 Op = Op.getOperand(0);
25797 // Otherwise, this isn't something we can handle, reject it.
25801 const GlobalValue *GV = GA->getGlobal();
25802 // If we require an extra load to get this address, as in PIC mode, we
25803 // can't accept it.
25804 if (isGlobalStubReference(
25805 Subtarget->ClassifyGlobalReference(GV, DAG.getTarget())))
25808 Result = DAG.getTargetGlobalAddress(GV, SDLoc(Op),
25809 GA->getValueType(0), Offset);
25814 if (Result.getNode()) {
25815 Ops.push_back(Result);
25818 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
25821 std::pair<unsigned, const TargetRegisterClass *>
25822 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
25823 StringRef Constraint,
25825 // First, see if this is a constraint that directly corresponds to an LLVM
25827 if (Constraint.size() == 1) {
25828 // GCC Constraint Letters
25829 switch (Constraint[0]) {
25831 // TODO: Slight differences here in allocation order and leaving
25832 // RIP in the class. Do they matter any more here than they do
25833 // in the normal allocation?
25834 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
25835 if (Subtarget->is64Bit()) {
25836 if (VT == MVT::i32 || VT == MVT::f32)
25837 return std::make_pair(0U, &X86::GR32RegClass);
25838 if (VT == MVT::i16)
25839 return std::make_pair(0U, &X86::GR16RegClass);
25840 if (VT == MVT::i8 || VT == MVT::i1)
25841 return std::make_pair(0U, &X86::GR8RegClass);
25842 if (VT == MVT::i64 || VT == MVT::f64)
25843 return std::make_pair(0U, &X86::GR64RegClass);
25846 // 32-bit fallthrough
25847 case 'Q': // Q_REGS
25848 if (VT == MVT::i32 || VT == MVT::f32)
25849 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
25850 if (VT == MVT::i16)
25851 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
25852 if (VT == MVT::i8 || VT == MVT::i1)
25853 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
25854 if (VT == MVT::i64)
25855 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
25857 case 'r': // GENERAL_REGS
25858 case 'l': // INDEX_REGS
25859 if (VT == MVT::i8 || VT == MVT::i1)
25860 return std::make_pair(0U, &X86::GR8RegClass);
25861 if (VT == MVT::i16)
25862 return std::make_pair(0U, &X86::GR16RegClass);
25863 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
25864 return std::make_pair(0U, &X86::GR32RegClass);
25865 return std::make_pair(0U, &X86::GR64RegClass);
25866 case 'R': // LEGACY_REGS
25867 if (VT == MVT::i8 || VT == MVT::i1)
25868 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
25869 if (VT == MVT::i16)
25870 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
25871 if (VT == MVT::i32 || !Subtarget->is64Bit())
25872 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
25873 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
25874 case 'f': // FP Stack registers.
25875 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
25876 // value to the correct fpstack register class.
25877 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
25878 return std::make_pair(0U, &X86::RFP32RegClass);
25879 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
25880 return std::make_pair(0U, &X86::RFP64RegClass);
25881 return std::make_pair(0U, &X86::RFP80RegClass);
25882 case 'y': // MMX_REGS if MMX allowed.
25883 if (!Subtarget->hasMMX()) break;
25884 return std::make_pair(0U, &X86::VR64RegClass);
25885 case 'Y': // SSE_REGS if SSE2 allowed
25886 if (!Subtarget->hasSSE2()) break;
25888 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
25889 if (!Subtarget->hasSSE1()) break;
25891 switch (VT.SimpleTy) {
25893 // Scalar SSE types.
25896 return std::make_pair(0U, &X86::FR32RegClass);
25899 return std::make_pair(0U, &X86::FR64RegClass);
25907 return std::make_pair(0U, &X86::VR128RegClass);
25915 return std::make_pair(0U, &X86::VR256RegClass);
25920 return std::make_pair(0U, &X86::VR512RegClass);
25926 // Use the default implementation in TargetLowering to convert the register
25927 // constraint into a member of a register class.
25928 std::pair<unsigned, const TargetRegisterClass*> Res;
25929 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
25931 // Not found as a standard register?
25933 // Map st(0) -> st(7) -> ST0
25934 if (Constraint.size() == 7 && Constraint[0] == '{' &&
25935 tolower(Constraint[1]) == 's' &&
25936 tolower(Constraint[2]) == 't' &&
25937 Constraint[3] == '(' &&
25938 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
25939 Constraint[5] == ')' &&
25940 Constraint[6] == '}') {
25942 Res.first = X86::FP0+Constraint[4]-'0';
25943 Res.second = &X86::RFP80RegClass;
25947 // GCC allows "st(0)" to be called just plain "st".
25948 if (StringRef("{st}").equals_lower(Constraint)) {
25949 Res.first = X86::FP0;
25950 Res.second = &X86::RFP80RegClass;
25955 if (StringRef("{flags}").equals_lower(Constraint)) {
25956 Res.first = X86::EFLAGS;
25957 Res.second = &X86::CCRRegClass;
25961 // 'A' means EAX + EDX.
25962 if (Constraint == "A") {
25963 Res.first = X86::EAX;
25964 Res.second = &X86::GR32_ADRegClass;
25970 // Otherwise, check to see if this is a register class of the wrong value
25971 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
25972 // turn into {ax},{dx}.
25973 // MVT::Other is used to specify clobber names.
25974 if (Res.second->hasType(VT) || VT == MVT::Other)
25975 return Res; // Correct type already, nothing to do.
25977 // Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
25978 // return "eax". This should even work for things like getting 64bit integer
25979 // registers when given an f64 type.
25980 const TargetRegisterClass *Class = Res.second;
25981 if (Class == &X86::GR8RegClass || Class == &X86::GR16RegClass ||
25982 Class == &X86::GR32RegClass || Class == &X86::GR64RegClass) {
25983 unsigned Size = VT.getSizeInBits();
25984 MVT::SimpleValueType SimpleTy = Size == 1 || Size == 8 ? MVT::i8
25985 : Size == 16 ? MVT::i16
25986 : Size == 32 ? MVT::i32
25987 : Size == 64 ? MVT::i64
25989 unsigned DestReg = getX86SubSuperRegisterOrZero(Res.first, SimpleTy);
25991 Res.first = DestReg;
25992 Res.second = SimpleTy == MVT::i8 ? &X86::GR8RegClass
25993 : SimpleTy == MVT::i16 ? &X86::GR16RegClass
25994 : SimpleTy == MVT::i32 ? &X86::GR32RegClass
25995 : &X86::GR64RegClass;
25996 assert(Res.second->contains(Res.first) && "Register in register class");
25998 // No register found/type mismatch.
26000 Res.second = nullptr;
26002 } else if (Class == &X86::FR32RegClass || Class == &X86::FR64RegClass ||
26003 Class == &X86::VR128RegClass || Class == &X86::VR256RegClass ||
26004 Class == &X86::FR32XRegClass || Class == &X86::FR64XRegClass ||
26005 Class == &X86::VR128XRegClass || Class == &X86::VR256XRegClass ||
26006 Class == &X86::VR512RegClass) {
26007 // Handle references to XMM physical registers that got mapped into the
26008 // wrong class. This can happen with constraints like {xmm0} where the
26009 // target independent register mapper will just pick the first match it can
26010 // find, ignoring the required type.
26012 if (VT == MVT::f32 || VT == MVT::i32)
26013 Res.second = &X86::FR32RegClass;
26014 else if (VT == MVT::f64 || VT == MVT::i64)
26015 Res.second = &X86::FR64RegClass;
26016 else if (X86::VR128RegClass.hasType(VT))
26017 Res.second = &X86::VR128RegClass;
26018 else if (X86::VR256RegClass.hasType(VT))
26019 Res.second = &X86::VR256RegClass;
26020 else if (X86::VR512RegClass.hasType(VT))
26021 Res.second = &X86::VR512RegClass;
26023 // Type mismatch and not a clobber: Return an error;
26025 Res.second = nullptr;
26032 int X86TargetLowering::getScalingFactorCost(const AddrMode &AM,
26034 unsigned AS) const {
26035 // Scaling factors are not free at all.
26036 // An indexed folded instruction, i.e., inst (reg1, reg2, scale),
26037 // will take 2 allocations in the out of order engine instead of 1
26038 // for plain addressing mode, i.e. inst (reg1).
26040 // vaddps (%rsi,%drx), %ymm0, %ymm1
26041 // Requires two allocations (one for the load, one for the computation)
26043 // vaddps (%rsi), %ymm0, %ymm1
26044 // Requires just 1 allocation, i.e., freeing allocations for other operations
26045 // and having less micro operations to execute.
26047 // For some X86 architectures, this is even worse because for instance for
26048 // stores, the complex addressing mode forces the instruction to use the
26049 // "load" ports instead of the dedicated "store" port.
26050 // E.g., on Haswell:
26051 // vmovaps %ymm1, (%r8, %rdi) can use port 2 or 3.
26052 // vmovaps %ymm1, (%r8) can use port 2, 3, or 7.
26053 if (isLegalAddressingMode(AM, Ty, AS))
26054 // Scale represents reg2 * scale, thus account for 1
26055 // as soon as we use a second register.
26056 return AM.Scale != 0;
26060 bool X86TargetLowering::isTargetFTOL() const {
26061 return Subtarget->isTargetKnownWindowsMSVC() && !Subtarget->is64Bit();