1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that X86 uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "x86-isel"
16 #include "X86ISelLowering.h"
17 #include "Utils/X86ShuffleDecode.h"
19 #include "X86InstrBuilder.h"
20 #include "X86TargetMachine.h"
21 #include "X86TargetObjectFile.h"
22 #include "llvm/ADT/SmallSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/VariadicFunction.h"
26 #include "llvm/CodeGen/IntrinsicLowering.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineJumpTableInfo.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/Constants.h"
35 #include "llvm/IR/DerivedTypes.h"
36 #include "llvm/IR/Function.h"
37 #include "llvm/IR/GlobalAlias.h"
38 #include "llvm/IR/GlobalVariable.h"
39 #include "llvm/IR/Instructions.h"
40 #include "llvm/IR/Intrinsics.h"
41 #include "llvm/IR/LLVMContext.h"
42 #include "llvm/MC/MCAsmInfo.h"
43 #include "llvm/MC/MCContext.h"
44 #include "llvm/MC/MCExpr.h"
45 #include "llvm/MC/MCSymbol.h"
46 #include "llvm/Support/CallSite.h"
47 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Target/TargetOptions.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
57 // Forward declarations.
58 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
61 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This
62 /// sets things up to match to an AVX VEXTRACTF128 instruction or a
63 /// simple subregister reference. Idx is an index in the 128 bits we
64 /// want. It need not be aligned to a 128-bit bounday. That makes
65 /// lowering EXTRACT_VECTOR_ELT operations easier.
66 static SDValue Extract128BitVector(SDValue Vec, unsigned IdxVal,
67 SelectionDAG &DAG, DebugLoc dl) {
68 EVT VT = Vec.getValueType();
69 assert(VT.is256BitVector() && "Unexpected vector size!");
70 EVT ElVT = VT.getVectorElementType();
71 unsigned Factor = VT.getSizeInBits()/128;
72 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT,
73 VT.getVectorNumElements()/Factor);
75 // Extract from UNDEF is UNDEF.
76 if (Vec.getOpcode() == ISD::UNDEF)
77 return DAG.getUNDEF(ResultVT);
79 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR
80 // we can match to VEXTRACTF128.
81 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits();
83 // This is the index of the first element of the 128-bit chunk
85 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128)
88 // If the input is a buildvector just emit a smaller one.
89 if (Vec.getOpcode() == ISD::BUILD_VECTOR)
90 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT,
91 Vec->op_begin()+NormalizedIdxVal, ElemsPerChunk);
93 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
94 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec,
100 /// Generate a DAG to put 128-bits into a vector > 128 bits. This
101 /// sets things up to match to an AVX VINSERTF128 instruction or a
102 /// simple superregister reference. Idx is an index in the 128 bits
103 /// we want. It need not be aligned to a 128-bit bounday. That makes
104 /// lowering INSERT_VECTOR_ELT operations easier.
105 static SDValue Insert128BitVector(SDValue Result, SDValue Vec,
106 unsigned IdxVal, SelectionDAG &DAG,
108 // Inserting UNDEF is Result
109 if (Vec.getOpcode() == ISD::UNDEF)
112 EVT VT = Vec.getValueType();
113 assert(VT.is128BitVector() && "Unexpected vector size!");
115 EVT ElVT = VT.getVectorElementType();
116 EVT ResultVT = Result.getValueType();
118 // Insert the relevant 128 bits.
119 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits();
121 // This is the index of the first element of the 128-bit chunk
123 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128)
126 SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);
127 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec,
131 /// Concat two 128-bit vectors into a 256 bit vector using VINSERTF128
132 /// instructions. This is used because creating CONCAT_VECTOR nodes of
133 /// BUILD_VECTORS returns a larger BUILD_VECTOR while we're trying to lower
134 /// large BUILD_VECTORS.
135 static SDValue Concat128BitVectors(SDValue V1, SDValue V2, EVT VT,
136 unsigned NumElems, SelectionDAG &DAG,
138 SDValue V = Insert128BitVector(DAG.getUNDEF(VT), V1, 0, DAG, dl);
139 return Insert128BitVector(V, V2, NumElems/2, DAG, dl);
142 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
143 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
144 bool is64Bit = Subtarget->is64Bit();
146 if (Subtarget->isTargetEnvMacho()) {
148 return new X86_64MachoTargetObjectFile();
149 return new TargetLoweringObjectFileMachO();
152 if (Subtarget->isTargetLinux())
153 return new X86LinuxTargetObjectFile();
154 if (Subtarget->isTargetELF())
155 return new TargetLoweringObjectFileELF();
156 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
157 return new TargetLoweringObjectFileCOFF();
158 llvm_unreachable("unknown subtarget type");
161 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
162 : TargetLowering(TM, createTLOF(TM)) {
163 Subtarget = &TM.getSubtarget<X86Subtarget>();
164 X86ScalarSSEf64 = Subtarget->hasSSE2();
165 X86ScalarSSEf32 = Subtarget->hasSSE1();
166 RegInfo = TM.getRegisterInfo();
167 TD = getDataLayout();
169 resetOperationActions();
172 void X86TargetLowering::resetOperationActions() {
173 const TargetMachine &TM = getTargetMachine();
174 static bool FirstTimeThrough = true;
176 // If none of the target options have changed, then we don't need to reset the
177 // operation actions.
178 if (!FirstTimeThrough && TO == TM.Options) return;
180 if (!FirstTimeThrough) {
181 // Reinitialize the actions.
183 FirstTimeThrough = false;
188 // Set up the TargetLowering object.
189 static const MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
191 // X86 is weird, it always uses i8 for shift amounts and setcc results.
192 setBooleanContents(ZeroOrOneBooleanContent);
193 // X86-SSE is even stranger. It uses -1 or 0 for vector masks.
194 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
196 // For 64-bit since we have so many registers use the ILP scheduler, for
197 // 32-bit code use the register pressure specific scheduling.
198 // For Atom, always use ILP scheduling.
199 if (Subtarget->isAtom())
200 setSchedulingPreference(Sched::ILP);
201 else if (Subtarget->is64Bit())
202 setSchedulingPreference(Sched::ILP);
204 setSchedulingPreference(Sched::RegPressure);
205 setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
207 // Bypass expensive divides on Atom when compiling with O2
208 if (Subtarget->hasSlowDivide() && TM.getOptLevel() >= CodeGenOpt::Default) {
209 addBypassSlowDiv(32, 8);
210 if (Subtarget->is64Bit())
211 addBypassSlowDiv(64, 16);
214 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) {
215 // Setup Windows compiler runtime calls.
216 setLibcallName(RTLIB::SDIV_I64, "_alldiv");
217 setLibcallName(RTLIB::UDIV_I64, "_aulldiv");
218 setLibcallName(RTLIB::SREM_I64, "_allrem");
219 setLibcallName(RTLIB::UREM_I64, "_aullrem");
220 setLibcallName(RTLIB::MUL_I64, "_allmul");
221 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall);
222 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall);
223 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall);
224 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall);
225 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall);
227 // The _ftol2 runtime function has an unusual calling conv, which
228 // is modeled by a special pseudo-instruction.
229 setLibcallName(RTLIB::FPTOUINT_F64_I64, 0);
230 setLibcallName(RTLIB::FPTOUINT_F32_I64, 0);
231 setLibcallName(RTLIB::FPTOUINT_F64_I32, 0);
232 setLibcallName(RTLIB::FPTOUINT_F32_I32, 0);
235 if (Subtarget->isTargetDarwin()) {
236 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp.
237 setUseUnderscoreSetJmp(false);
238 setUseUnderscoreLongJmp(false);
239 } else if (Subtarget->isTargetMingw()) {
240 // MS runtime is weird: it exports _setjmp, but longjmp!
241 setUseUnderscoreSetJmp(true);
242 setUseUnderscoreLongJmp(false);
244 setUseUnderscoreSetJmp(true);
245 setUseUnderscoreLongJmp(true);
248 // Set up the register classes.
249 addRegisterClass(MVT::i8, &X86::GR8RegClass);
250 addRegisterClass(MVT::i16, &X86::GR16RegClass);
251 addRegisterClass(MVT::i32, &X86::GR32RegClass);
252 if (Subtarget->is64Bit())
253 addRegisterClass(MVT::i64, &X86::GR64RegClass);
255 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
257 // We don't accept any truncstore of integer registers.
258 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
259 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
260 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
261 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
262 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
263 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
265 // SETOEQ and SETUNE require checking two conditions.
266 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
267 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
268 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand);
269 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand);
270 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
271 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand);
273 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
275 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
276 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
277 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
279 if (Subtarget->is64Bit()) {
280 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
281 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
282 } else if (!TM.Options.UseSoftFloat) {
283 // We have an algorithm for SSE2->double, and we turn this into a
284 // 64-bit FILD followed by conditional FADD for other targets.
285 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
286 // We have an algorithm for SSE2, and we turn this into a 64-bit
287 // FILD for other targets.
288 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
291 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
293 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
294 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
296 if (!TM.Options.UseSoftFloat) {
297 // SSE has no i16 to fp conversion, only i32
298 if (X86ScalarSSEf32) {
299 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
300 // f32 and f64 cases are Legal, f80 case is not
301 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
303 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
304 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
307 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
308 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
311 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
312 // are Legal, f80 is custom lowered.
313 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
314 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
316 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
318 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
319 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
321 if (X86ScalarSSEf32) {
322 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
323 // f32 and f64 cases are Legal, f80 case is not
324 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
326 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
327 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
330 // Handle FP_TO_UINT by promoting the destination to a larger signed
332 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
333 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
334 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
336 if (Subtarget->is64Bit()) {
337 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
338 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
339 } else if (!TM.Options.UseSoftFloat) {
340 // Since AVX is a superset of SSE3, only check for SSE here.
341 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())
342 // Expand FP_TO_UINT into a select.
343 // FIXME: We would like to use a Custom expander here eventually to do
344 // the optimal thing for SSE vs. the default expansion in the legalizer.
345 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
347 // With SSE3 we can use fisttpll to convert to a signed i64; without
348 // SSE, we're stuck with a fistpll.
349 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
352 if (isTargetFTOL()) {
353 // Use the _ftol2 runtime function, which has a pseudo-instruction
354 // to handle its weird calling convention.
355 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
358 // TODO: when we have SSE, these could be more efficient, by using movd/movq.
359 if (!X86ScalarSSEf64) {
360 setOperationAction(ISD::BITCAST , MVT::f32 , Expand);
361 setOperationAction(ISD::BITCAST , MVT::i32 , Expand);
362 if (Subtarget->is64Bit()) {
363 setOperationAction(ISD::BITCAST , MVT::f64 , Expand);
364 // Without SSE, i64->f64 goes through memory.
365 setOperationAction(ISD::BITCAST , MVT::i64 , Expand);
369 // Scalar integer divide and remainder are lowered to use operations that
370 // produce two results, to match the available instructions. This exposes
371 // the two-result form to trivial CSE, which is able to combine x/y and x%y
372 // into a single instruction.
374 // Scalar integer multiply-high is also lowered to use two-result
375 // operations, to match the available instructions. However, plain multiply
376 // (low) operations are left as Legal, as there are single-result
377 // instructions for this in x86. Using the two-result multiply instructions
378 // when both high and low results are needed must be arranged by dagcombine.
379 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
381 setOperationAction(ISD::MULHS, VT, Expand);
382 setOperationAction(ISD::MULHU, VT, Expand);
383 setOperationAction(ISD::SDIV, VT, Expand);
384 setOperationAction(ISD::UDIV, VT, Expand);
385 setOperationAction(ISD::SREM, VT, Expand);
386 setOperationAction(ISD::UREM, VT, Expand);
388 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences.
389 setOperationAction(ISD::ADDC, VT, Custom);
390 setOperationAction(ISD::ADDE, VT, Custom);
391 setOperationAction(ISD::SUBC, VT, Custom);
392 setOperationAction(ISD::SUBE, VT, Custom);
395 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
396 setOperationAction(ISD::BRCOND , MVT::Other, Custom);
397 setOperationAction(ISD::BR_CC , MVT::f32, Expand);
398 setOperationAction(ISD::BR_CC , MVT::f64, Expand);
399 setOperationAction(ISD::BR_CC , MVT::f80, Expand);
400 setOperationAction(ISD::BR_CC , MVT::i8, Expand);
401 setOperationAction(ISD::BR_CC , MVT::i16, Expand);
402 setOperationAction(ISD::BR_CC , MVT::i32, Expand);
403 setOperationAction(ISD::BR_CC , MVT::i64, Expand);
404 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
405 if (Subtarget->is64Bit())
406 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
407 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
408 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
409 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
410 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
411 setOperationAction(ISD::FREM , MVT::f32 , Expand);
412 setOperationAction(ISD::FREM , MVT::f64 , Expand);
413 setOperationAction(ISD::FREM , MVT::f80 , Expand);
414 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
416 // Promote the i8 variants and force them on up to i32 which has a shorter
418 setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
419 AddPromotedToType (ISD::CTTZ , MVT::i8 , MVT::i32);
420 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i8 , Promote);
421 AddPromotedToType (ISD::CTTZ_ZERO_UNDEF , MVT::i8 , MVT::i32);
422 if (Subtarget->hasBMI()) {
423 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Expand);
424 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Expand);
425 if (Subtarget->is64Bit())
426 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
428 setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
429 setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
430 if (Subtarget->is64Bit())
431 setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
434 if (Subtarget->hasLZCNT()) {
435 // When promoting the i8 variants, force them to i32 for a shorter
437 setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
438 AddPromotedToType (ISD::CTLZ , MVT::i8 , MVT::i32);
439 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Promote);
440 AddPromotedToType (ISD::CTLZ_ZERO_UNDEF, MVT::i8 , MVT::i32);
441 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Expand);
442 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Expand);
443 if (Subtarget->is64Bit())
444 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
446 setOperationAction(ISD::CTLZ , MVT::i8 , Custom);
447 setOperationAction(ISD::CTLZ , MVT::i16 , Custom);
448 setOperationAction(ISD::CTLZ , MVT::i32 , Custom);
449 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8 , Custom);
450 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16 , Custom);
451 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32 , Custom);
452 if (Subtarget->is64Bit()) {
453 setOperationAction(ISD::CTLZ , MVT::i64 , Custom);
454 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Custom);
458 if (Subtarget->hasPOPCNT()) {
459 setOperationAction(ISD::CTPOP , MVT::i8 , Promote);
461 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
462 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
463 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
464 if (Subtarget->is64Bit())
465 setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
468 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
469 setOperationAction(ISD::BSWAP , MVT::i16 , Expand);
471 // These should be promoted to a larger select which is supported.
472 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
473 // X86 wants to expand cmov itself.
474 setOperationAction(ISD::SELECT , MVT::i8 , Custom);
475 setOperationAction(ISD::SELECT , MVT::i16 , Custom);
476 setOperationAction(ISD::SELECT , MVT::i32 , Custom);
477 setOperationAction(ISD::SELECT , MVT::f32 , Custom);
478 setOperationAction(ISD::SELECT , MVT::f64 , Custom);
479 setOperationAction(ISD::SELECT , MVT::f80 , Custom);
480 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
481 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
482 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
483 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
484 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
485 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
486 if (Subtarget->is64Bit()) {
487 setOperationAction(ISD::SELECT , MVT::i64 , Custom);
488 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
490 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom);
491 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
492 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
493 // support continuation, user-level threading, and etc.. As a result, no
494 // other SjLj exception interfaces are implemented and please don't build
495 // your own exception handling based on them.
496 // LLVM/Clang supports zero-cost DWARF exception handling.
497 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
498 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
501 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom);
502 setOperationAction(ISD::JumpTable , MVT::i32 , Custom);
503 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom);
504 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom);
505 if (Subtarget->is64Bit())
506 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
507 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom);
508 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom);
509 if (Subtarget->is64Bit()) {
510 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom);
511 setOperationAction(ISD::JumpTable , MVT::i64 , Custom);
512 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom);
513 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom);
514 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom);
516 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
517 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom);
518 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
519 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom);
520 if (Subtarget->is64Bit()) {
521 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom);
522 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
523 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom);
526 if (Subtarget->hasSSE1())
527 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
529 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom);
531 // Expand certain atomics
532 for (unsigned i = 0; i != array_lengthof(IntVTs); ++i) {
534 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom);
535 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
536 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
539 if (!Subtarget->is64Bit()) {
540 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
541 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
542 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
543 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
544 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
545 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
546 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom);
547 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
548 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
549 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
550 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
551 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
554 if (Subtarget->hasCmpxchg16b()) {
555 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
558 // FIXME - use subtarget debug flags
559 if (!Subtarget->isTargetDarwin() &&
560 !Subtarget->isTargetELF() &&
561 !Subtarget->isTargetCygMing()) {
562 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
565 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
566 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
567 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
568 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
569 if (Subtarget->is64Bit()) {
570 setExceptionPointerRegister(X86::RAX);
571 setExceptionSelectorRegister(X86::RDX);
573 setExceptionPointerRegister(X86::EAX);
574 setExceptionSelectorRegister(X86::EDX);
576 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
577 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom);
579 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
580 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
582 setOperationAction(ISD::TRAP, MVT::Other, Legal);
583 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
585 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
586 setOperationAction(ISD::VASTART , MVT::Other, Custom);
587 setOperationAction(ISD::VAEND , MVT::Other, Expand);
588 if (Subtarget->is64Bit()) {
589 setOperationAction(ISD::VAARG , MVT::Other, Custom);
590 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
592 setOperationAction(ISD::VAARG , MVT::Other, Expand);
593 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
596 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
597 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
599 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho())
600 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
601 MVT::i64 : MVT::i32, Custom);
602 else if (TM.Options.EnableSegmentedStacks)
603 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
604 MVT::i64 : MVT::i32, Custom);
606 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ?
607 MVT::i64 : MVT::i32, Expand);
609 if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {
610 // f32 and f64 use SSE.
611 // Set up the FP register classes.
612 addRegisterClass(MVT::f32, &X86::FR32RegClass);
613 addRegisterClass(MVT::f64, &X86::FR64RegClass);
615 // Use ANDPD to simulate FABS.
616 setOperationAction(ISD::FABS , MVT::f64, Custom);
617 setOperationAction(ISD::FABS , MVT::f32, Custom);
619 // Use XORP to simulate FNEG.
620 setOperationAction(ISD::FNEG , MVT::f64, Custom);
621 setOperationAction(ISD::FNEG , MVT::f32, Custom);
623 // Use ANDPD and ORPD to simulate FCOPYSIGN.
624 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
625 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
627 // Lower this to FGETSIGNx86 plus an AND.
628 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom);
629 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom);
631 // We don't support sin/cos/fmod
632 setOperationAction(ISD::FSIN , MVT::f64, Expand);
633 setOperationAction(ISD::FCOS , MVT::f64, Expand);
634 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
635 setOperationAction(ISD::FSIN , MVT::f32, Expand);
636 setOperationAction(ISD::FCOS , MVT::f32, Expand);
637 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
639 // Expand FP immediates into loads from the stack, except for the special
641 addLegalFPImmediate(APFloat(+0.0)); // xorpd
642 addLegalFPImmediate(APFloat(+0.0f)); // xorps
643 } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {
644 // Use SSE for f32, x87 for f64.
645 // Set up the FP register classes.
646 addRegisterClass(MVT::f32, &X86::FR32RegClass);
647 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
649 // Use ANDPS to simulate FABS.
650 setOperationAction(ISD::FABS , MVT::f32, Custom);
652 // Use XORP to simulate FNEG.
653 setOperationAction(ISD::FNEG , MVT::f32, Custom);
655 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
657 // Use ANDPS and ORPS to simulate FCOPYSIGN.
658 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
659 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
661 // We don't support sin/cos/fmod
662 setOperationAction(ISD::FSIN , MVT::f32, Expand);
663 setOperationAction(ISD::FCOS , MVT::f32, Expand);
664 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
666 // Special cases we handle for FP constants.
667 addLegalFPImmediate(APFloat(+0.0f)); // xorps
668 addLegalFPImmediate(APFloat(+0.0)); // FLD0
669 addLegalFPImmediate(APFloat(+1.0)); // FLD1
670 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
671 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
673 if (!TM.Options.UnsafeFPMath) {
674 setOperationAction(ISD::FSIN , MVT::f64, Expand);
675 setOperationAction(ISD::FCOS , MVT::f64, Expand);
676 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
678 } else if (!TM.Options.UseSoftFloat) {
679 // f32 and f64 in x87.
680 // Set up the FP register classes.
681 addRegisterClass(MVT::f64, &X86::RFP64RegClass);
682 addRegisterClass(MVT::f32, &X86::RFP32RegClass);
684 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
685 setOperationAction(ISD::UNDEF, MVT::f32, Expand);
686 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
687 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
689 if (!TM.Options.UnsafeFPMath) {
690 setOperationAction(ISD::FSIN , MVT::f64, Expand);
691 setOperationAction(ISD::FSIN , MVT::f32, Expand);
692 setOperationAction(ISD::FCOS , MVT::f64, Expand);
693 setOperationAction(ISD::FCOS , MVT::f32, Expand);
694 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
695 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
697 addLegalFPImmediate(APFloat(+0.0)); // FLD0
698 addLegalFPImmediate(APFloat(+1.0)); // FLD1
699 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS
700 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS
701 addLegalFPImmediate(APFloat(+0.0f)); // FLD0
702 addLegalFPImmediate(APFloat(+1.0f)); // FLD1
703 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
704 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
707 // We don't support FMA.
708 setOperationAction(ISD::FMA, MVT::f64, Expand);
709 setOperationAction(ISD::FMA, MVT::f32, Expand);
711 // Long double always uses X87.
712 if (!TM.Options.UseSoftFloat) {
713 addRegisterClass(MVT::f80, &X86::RFP80RegClass);
714 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
715 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);
717 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended);
718 addLegalFPImmediate(TmpFlt); // FLD0
720 addLegalFPImmediate(TmpFlt); // FLD0/FCHS
723 APFloat TmpFlt2(+1.0);
724 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven,
726 addLegalFPImmediate(TmpFlt2); // FLD1
727 TmpFlt2.changeSign();
728 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS
731 if (!TM.Options.UnsafeFPMath) {
732 setOperationAction(ISD::FSIN , MVT::f80, Expand);
733 setOperationAction(ISD::FCOS , MVT::f80, Expand);
734 setOperationAction(ISD::FSINCOS, MVT::f80, Expand);
737 setOperationAction(ISD::FFLOOR, MVT::f80, Expand);
738 setOperationAction(ISD::FCEIL, MVT::f80, Expand);
739 setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
740 setOperationAction(ISD::FRINT, MVT::f80, Expand);
741 setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
742 setOperationAction(ISD::FMA, MVT::f80, Expand);
745 // Always use a library call for pow.
746 setOperationAction(ISD::FPOW , MVT::f32 , Expand);
747 setOperationAction(ISD::FPOW , MVT::f64 , Expand);
748 setOperationAction(ISD::FPOW , MVT::f80 , Expand);
750 setOperationAction(ISD::FLOG, MVT::f80, Expand);
751 setOperationAction(ISD::FLOG2, MVT::f80, Expand);
752 setOperationAction(ISD::FLOG10, MVT::f80, Expand);
753 setOperationAction(ISD::FEXP, MVT::f80, Expand);
754 setOperationAction(ISD::FEXP2, MVT::f80, Expand);
756 // First set operation action for all vector types to either promote
757 // (for widening) or expand (for scalarization). Then we will selectively
758 // turn on ones that can be effectively codegen'd.
759 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
760 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
761 MVT VT = (MVT::SimpleValueType)i;
762 setOperationAction(ISD::ADD , VT, Expand);
763 setOperationAction(ISD::SUB , VT, Expand);
764 setOperationAction(ISD::FADD, VT, Expand);
765 setOperationAction(ISD::FNEG, VT, Expand);
766 setOperationAction(ISD::FSUB, VT, Expand);
767 setOperationAction(ISD::MUL , VT, Expand);
768 setOperationAction(ISD::FMUL, VT, Expand);
769 setOperationAction(ISD::SDIV, VT, Expand);
770 setOperationAction(ISD::UDIV, VT, Expand);
771 setOperationAction(ISD::FDIV, VT, Expand);
772 setOperationAction(ISD::SREM, VT, Expand);
773 setOperationAction(ISD::UREM, VT, Expand);
774 setOperationAction(ISD::LOAD, VT, Expand);
775 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
776 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT,Expand);
777 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
778 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT,Expand);
779 setOperationAction(ISD::INSERT_SUBVECTOR, VT,Expand);
780 setOperationAction(ISD::FABS, VT, Expand);
781 setOperationAction(ISD::FSIN, VT, Expand);
782 setOperationAction(ISD::FSINCOS, VT, Expand);
783 setOperationAction(ISD::FCOS, VT, Expand);
784 setOperationAction(ISD::FSINCOS, VT, Expand);
785 setOperationAction(ISD::FREM, VT, Expand);
786 setOperationAction(ISD::FMA, VT, Expand);
787 setOperationAction(ISD::FPOWI, VT, Expand);
788 setOperationAction(ISD::FSQRT, VT, Expand);
789 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
790 setOperationAction(ISD::FFLOOR, VT, Expand);
791 setOperationAction(ISD::FCEIL, VT, Expand);
792 setOperationAction(ISD::FTRUNC, VT, Expand);
793 setOperationAction(ISD::FRINT, VT, Expand);
794 setOperationAction(ISD::FNEARBYINT, VT, Expand);
795 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
796 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
797 setOperationAction(ISD::SDIVREM, VT, Expand);
798 setOperationAction(ISD::UDIVREM, VT, Expand);
799 setOperationAction(ISD::FPOW, VT, Expand);
800 setOperationAction(ISD::CTPOP, VT, Expand);
801 setOperationAction(ISD::CTTZ, VT, Expand);
802 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
803 setOperationAction(ISD::CTLZ, VT, Expand);
804 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
805 setOperationAction(ISD::SHL, VT, Expand);
806 setOperationAction(ISD::SRA, VT, Expand);
807 setOperationAction(ISD::SRL, VT, Expand);
808 setOperationAction(ISD::ROTL, VT, Expand);
809 setOperationAction(ISD::ROTR, VT, Expand);
810 setOperationAction(ISD::BSWAP, VT, Expand);
811 setOperationAction(ISD::SETCC, VT, Expand);
812 setOperationAction(ISD::FLOG, VT, Expand);
813 setOperationAction(ISD::FLOG2, VT, Expand);
814 setOperationAction(ISD::FLOG10, VT, Expand);
815 setOperationAction(ISD::FEXP, VT, Expand);
816 setOperationAction(ISD::FEXP2, VT, Expand);
817 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
818 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
819 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
820 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
821 setOperationAction(ISD::SIGN_EXTEND_INREG, VT,Expand);
822 setOperationAction(ISD::TRUNCATE, VT, Expand);
823 setOperationAction(ISD::SIGN_EXTEND, VT, Expand);
824 setOperationAction(ISD::ZERO_EXTEND, VT, Expand);
825 setOperationAction(ISD::ANY_EXTEND, VT, Expand);
826 setOperationAction(ISD::VSELECT, VT, Expand);
827 for (int InnerVT = MVT::FIRST_VECTOR_VALUETYPE;
828 InnerVT <= MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
829 setTruncStoreAction(VT,
830 (MVT::SimpleValueType)InnerVT, Expand);
831 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
832 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
833 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
836 // FIXME: In order to prevent SSE instructions being expanded to MMX ones
837 // with -msoft-float, disable use of MMX as well.
838 if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {
839 addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);
840 // No operations on x86mmx supported, everything uses intrinsics.
843 // MMX-sized vectors (other than x86mmx) are expected to be expanded
844 // into smaller operations.
845 setOperationAction(ISD::MULHS, MVT::v8i8, Expand);
846 setOperationAction(ISD::MULHS, MVT::v4i16, Expand);
847 setOperationAction(ISD::MULHS, MVT::v2i32, Expand);
848 setOperationAction(ISD::MULHS, MVT::v1i64, Expand);
849 setOperationAction(ISD::AND, MVT::v8i8, Expand);
850 setOperationAction(ISD::AND, MVT::v4i16, Expand);
851 setOperationAction(ISD::AND, MVT::v2i32, Expand);
852 setOperationAction(ISD::AND, MVT::v1i64, Expand);
853 setOperationAction(ISD::OR, MVT::v8i8, Expand);
854 setOperationAction(ISD::OR, MVT::v4i16, Expand);
855 setOperationAction(ISD::OR, MVT::v2i32, Expand);
856 setOperationAction(ISD::OR, MVT::v1i64, Expand);
857 setOperationAction(ISD::XOR, MVT::v8i8, Expand);
858 setOperationAction(ISD::XOR, MVT::v4i16, Expand);
859 setOperationAction(ISD::XOR, MVT::v2i32, Expand);
860 setOperationAction(ISD::XOR, MVT::v1i64, Expand);
861 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand);
862 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand);
863 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand);
864 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand);
865 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);
866 setOperationAction(ISD::SELECT, MVT::v8i8, Expand);
867 setOperationAction(ISD::SELECT, MVT::v4i16, Expand);
868 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
869 setOperationAction(ISD::SELECT, MVT::v1i64, Expand);
870 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand);
871 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand);
872 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand);
873 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand);
875 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {
876 addRegisterClass(MVT::v4f32, &X86::VR128RegClass);
878 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
879 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
880 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
881 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
882 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
883 setOperationAction(ISD::FNEG, MVT::v4f32, Custom);
884 setOperationAction(ISD::FABS, MVT::v4f32, Custom);
885 setOperationAction(ISD::LOAD, MVT::v4f32, Legal);
886 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
887 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
888 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
889 setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
892 if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {
893 addRegisterClass(MVT::v2f64, &X86::VR128RegClass);
895 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM
896 // registers cannot be used even for integer operations.
897 addRegisterClass(MVT::v16i8, &X86::VR128RegClass);
898 addRegisterClass(MVT::v8i16, &X86::VR128RegClass);
899 addRegisterClass(MVT::v4i32, &X86::VR128RegClass);
900 addRegisterClass(MVT::v2i64, &X86::VR128RegClass);
902 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
903 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
904 setOperationAction(ISD::ADD, MVT::v4i32, Legal);
905 setOperationAction(ISD::ADD, MVT::v2i64, Legal);
906 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
907 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
908 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
909 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
910 setOperationAction(ISD::SUB, MVT::v4i32, Legal);
911 setOperationAction(ISD::SUB, MVT::v2i64, Legal);
912 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
913 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
914 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
915 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
916 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
917 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
918 setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
919 setOperationAction(ISD::FABS, MVT::v2f64, Custom);
921 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
922 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
923 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
924 setOperationAction(ISD::SETCC, MVT::v4i32, Custom);
926 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
927 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
928 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
929 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
930 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
932 // Custom lower build_vector, vector_shuffle, and extract_vector_elt.
933 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
934 MVT VT = (MVT::SimpleValueType)i;
935 // Do not attempt to custom lower non-power-of-2 vectors
936 if (!isPowerOf2_32(VT.getVectorNumElements()))
938 // Do not attempt to custom lower non-128-bit vectors
939 if (!VT.is128BitVector())
941 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
942 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
943 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
946 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom);
947 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom);
948 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom);
949 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom);
950 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
951 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
953 if (Subtarget->is64Bit()) {
954 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
955 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
958 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
959 for (int i = MVT::v16i8; i != MVT::v2i64; ++i) {
960 MVT VT = (MVT::SimpleValueType)i;
962 // Do not attempt to promote non-128-bit vectors
963 if (!VT.is128BitVector())
966 setOperationAction(ISD::AND, VT, Promote);
967 AddPromotedToType (ISD::AND, VT, MVT::v2i64);
968 setOperationAction(ISD::OR, VT, Promote);
969 AddPromotedToType (ISD::OR, VT, MVT::v2i64);
970 setOperationAction(ISD::XOR, VT, Promote);
971 AddPromotedToType (ISD::XOR, VT, MVT::v2i64);
972 setOperationAction(ISD::LOAD, VT, Promote);
973 AddPromotedToType (ISD::LOAD, VT, MVT::v2i64);
974 setOperationAction(ISD::SELECT, VT, Promote);
975 AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
978 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
980 // Custom lower v2i64 and v2f64 selects.
981 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
982 setOperationAction(ISD::LOAD, MVT::v2i64, Legal);
983 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
984 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
986 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
987 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
989 setOperationAction(ISD::UINT_TO_FP, MVT::v4i8, Custom);
990 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
991 // As there is no 64-bit GPR available, we need build a special custom
992 // sequence to convert from v2i32 to v2f32.
993 if (!Subtarget->is64Bit())
994 setOperationAction(ISD::UINT_TO_FP, MVT::v2f32, Custom);
996 setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
997 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Custom);
999 setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, Legal);
1002 if (Subtarget->hasSSE41()) {
1003 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
1004 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
1005 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
1006 setOperationAction(ISD::FRINT, MVT::f32, Legal);
1007 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
1008 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
1009 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
1010 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
1011 setOperationAction(ISD::FRINT, MVT::f64, Legal);
1012 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
1014 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
1015 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
1016 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
1017 setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
1018 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
1019 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
1020 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
1021 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
1022 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
1023 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
1025 // FIXME: Do we need to handle scalar-to-vector here?
1026 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
1028 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
1029 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
1030 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1031 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
1032 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
1034 // i8 and i16 vectors are custom , because the source register and source
1035 // source memory operand types are not the same width. f32 vectors are
1036 // custom since the immediate controlling the insert encodes additional
1038 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
1039 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
1040 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
1041 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
1043 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
1044 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
1045 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
1046 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
1048 // FIXME: these should be Legal but thats only for the case where
1049 // the index is constant. For now custom expand to deal with that.
1050 if (Subtarget->is64Bit()) {
1051 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom);
1052 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom);
1056 if (Subtarget->hasSSE2()) {
1057 setOperationAction(ISD::SRL, MVT::v8i16, Custom);
1058 setOperationAction(ISD::SRL, MVT::v16i8, Custom);
1060 setOperationAction(ISD::SHL, MVT::v8i16, Custom);
1061 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
1063 setOperationAction(ISD::SRA, MVT::v8i16, Custom);
1064 setOperationAction(ISD::SRA, MVT::v16i8, Custom);
1066 // In the customized shift lowering, the legal cases in AVX2 will be
1068 setOperationAction(ISD::SRL, MVT::v2i64, Custom);
1069 setOperationAction(ISD::SRL, MVT::v4i32, Custom);
1071 setOperationAction(ISD::SHL, MVT::v2i64, Custom);
1072 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
1074 setOperationAction(ISD::SRA, MVT::v4i32, Custom);
1076 setOperationAction(ISD::SDIV, MVT::v8i16, Custom);
1077 setOperationAction(ISD::SDIV, MVT::v4i32, Custom);
1080 if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {
1081 addRegisterClass(MVT::v32i8, &X86::VR256RegClass);
1082 addRegisterClass(MVT::v16i16, &X86::VR256RegClass);
1083 addRegisterClass(MVT::v8i32, &X86::VR256RegClass);
1084 addRegisterClass(MVT::v8f32, &X86::VR256RegClass);
1085 addRegisterClass(MVT::v4i64, &X86::VR256RegClass);
1086 addRegisterClass(MVT::v4f64, &X86::VR256RegClass);
1088 setOperationAction(ISD::LOAD, MVT::v8f32, Legal);
1089 setOperationAction(ISD::LOAD, MVT::v4f64, Legal);
1090 setOperationAction(ISD::LOAD, MVT::v4i64, Legal);
1092 setOperationAction(ISD::FADD, MVT::v8f32, Legal);
1093 setOperationAction(ISD::FSUB, MVT::v8f32, Legal);
1094 setOperationAction(ISD::FMUL, MVT::v8f32, Legal);
1095 setOperationAction(ISD::FDIV, MVT::v8f32, Legal);
1096 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal);
1097 setOperationAction(ISD::FFLOOR, MVT::v8f32, Legal);
1098 setOperationAction(ISD::FCEIL, MVT::v8f32, Legal);
1099 setOperationAction(ISD::FTRUNC, MVT::v8f32, Legal);
1100 setOperationAction(ISD::FRINT, MVT::v8f32, Legal);
1101 setOperationAction(ISD::FNEARBYINT, MVT::v8f32, Legal);
1102 setOperationAction(ISD::FNEG, MVT::v8f32, Custom);
1103 setOperationAction(ISD::FABS, MVT::v8f32, Custom);
1105 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
1106 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
1107 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
1108 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
1109 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1110 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
1111 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
1112 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
1113 setOperationAction(ISD::FRINT, MVT::v4f64, Legal);
1114 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Legal);
1115 setOperationAction(ISD::FNEG, MVT::v4f64, Custom);
1116 setOperationAction(ISD::FABS, MVT::v4f64, Custom);
1118 setOperationAction(ISD::TRUNCATE, MVT::v8i16, Custom);
1119 setOperationAction(ISD::TRUNCATE, MVT::v4i32, Custom);
1121 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom);
1123 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal);
1124 setOperationAction(ISD::SINT_TO_FP, MVT::v8i16, Promote);
1125 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal);
1126 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal);
1128 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1129 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom);
1130 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom);
1132 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, Legal);
1134 setOperationAction(ISD::SRL, MVT::v16i16, Custom);
1135 setOperationAction(ISD::SRL, MVT::v32i8, Custom);
1137 setOperationAction(ISD::SHL, MVT::v16i16, Custom);
1138 setOperationAction(ISD::SHL, MVT::v32i8, Custom);
1140 setOperationAction(ISD::SRA, MVT::v16i16, Custom);
1141 setOperationAction(ISD::SRA, MVT::v32i8, Custom);
1143 setOperationAction(ISD::SDIV, MVT::v16i16, Custom);
1145 setOperationAction(ISD::SETCC, MVT::v32i8, Custom);
1146 setOperationAction(ISD::SETCC, MVT::v16i16, Custom);
1147 setOperationAction(ISD::SETCC, MVT::v8i32, Custom);
1148 setOperationAction(ISD::SETCC, MVT::v4i64, Custom);
1150 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
1151 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1152 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
1154 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1155 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1156 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1157 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
1159 setOperationAction(ISD::SIGN_EXTEND, MVT::v4i64, Custom);
1160 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i32, Custom);
1161 setOperationAction(ISD::ZERO_EXTEND, MVT::v4i64, Custom);
1162 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i32, Custom);
1163 setOperationAction(ISD::ANY_EXTEND, MVT::v4i64, Custom);
1164 setOperationAction(ISD::ANY_EXTEND, MVT::v8i32, Custom);
1166 if (Subtarget->hasFMA() || Subtarget->hasFMA4()) {
1167 setOperationAction(ISD::FMA, MVT::v8f32, Legal);
1168 setOperationAction(ISD::FMA, MVT::v4f64, Legal);
1169 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
1170 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
1171 setOperationAction(ISD::FMA, MVT::f32, Legal);
1172 setOperationAction(ISD::FMA, MVT::f64, Legal);
1175 if (Subtarget->hasInt256()) {
1176 setOperationAction(ISD::ADD, MVT::v4i64, Legal);
1177 setOperationAction(ISD::ADD, MVT::v8i32, Legal);
1178 setOperationAction(ISD::ADD, MVT::v16i16, Legal);
1179 setOperationAction(ISD::ADD, MVT::v32i8, Legal);
1181 setOperationAction(ISD::SUB, MVT::v4i64, Legal);
1182 setOperationAction(ISD::SUB, MVT::v8i32, Legal);
1183 setOperationAction(ISD::SUB, MVT::v16i16, Legal);
1184 setOperationAction(ISD::SUB, MVT::v32i8, Legal);
1186 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1187 setOperationAction(ISD::MUL, MVT::v8i32, Legal);
1188 setOperationAction(ISD::MUL, MVT::v16i16, Legal);
1189 // Don't lower v32i8 because there is no 128-bit byte mul
1191 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1193 setOperationAction(ISD::SDIV, MVT::v8i32, Custom);
1195 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
1196 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
1197 setOperationAction(ISD::ADD, MVT::v16i16, Custom);
1198 setOperationAction(ISD::ADD, MVT::v32i8, Custom);
1200 setOperationAction(ISD::SUB, MVT::v4i64, Custom);
1201 setOperationAction(ISD::SUB, MVT::v8i32, Custom);
1202 setOperationAction(ISD::SUB, MVT::v16i16, Custom);
1203 setOperationAction(ISD::SUB, MVT::v32i8, Custom);
1205 setOperationAction(ISD::MUL, MVT::v4i64, Custom);
1206 setOperationAction(ISD::MUL, MVT::v8i32, Custom);
1207 setOperationAction(ISD::MUL, MVT::v16i16, Custom);
1208 // Don't lower v32i8 because there is no 128-bit byte mul
1211 // In the customized shift lowering, the legal cases in AVX2 will be
1213 setOperationAction(ISD::SRL, MVT::v4i64, Custom);
1214 setOperationAction(ISD::SRL, MVT::v8i32, Custom);
1216 setOperationAction(ISD::SHL, MVT::v4i64, Custom);
1217 setOperationAction(ISD::SHL, MVT::v8i32, Custom);
1219 setOperationAction(ISD::SRA, MVT::v8i32, Custom);
1221 // Custom lower several nodes for 256-bit types.
1222 for (int i = MVT::FIRST_VECTOR_VALUETYPE;
1223 i <= MVT::LAST_VECTOR_VALUETYPE; ++i) {
1224 MVT VT = (MVT::SimpleValueType)i;
1226 // Extract subvector is special because the value type
1227 // (result) is 128-bit but the source is 256-bit wide.
1228 if (VT.is128BitVector())
1229 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);
1231 // Do not attempt to custom lower other non-256-bit vectors
1232 if (!VT.is256BitVector())
1235 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
1236 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
1237 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
1238 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
1239 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
1240 setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
1241 setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
1244 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64.
1245 for (int i = MVT::v32i8; i != MVT::v4i64; ++i) {
1246 MVT VT = (MVT::SimpleValueType)i;
1248 // Do not attempt to promote non-256-bit vectors
1249 if (!VT.is256BitVector())
1252 setOperationAction(ISD::AND, VT, Promote);
1253 AddPromotedToType (ISD::AND, VT, MVT::v4i64);
1254 setOperationAction(ISD::OR, VT, Promote);
1255 AddPromotedToType (ISD::OR, VT, MVT::v4i64);
1256 setOperationAction(ISD::XOR, VT, Promote);
1257 AddPromotedToType (ISD::XOR, VT, MVT::v4i64);
1258 setOperationAction(ISD::LOAD, VT, Promote);
1259 AddPromotedToType (ISD::LOAD, VT, MVT::v4i64);
1260 setOperationAction(ISD::SELECT, VT, Promote);
1261 AddPromotedToType (ISD::SELECT, VT, MVT::v4i64);
1265 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
1266 // of this type with custom code.
1267 for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
1268 VT != MVT::LAST_VECTOR_VALUETYPE; VT++) {
1269 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,
1273 // We want to custom lower some of our intrinsics.
1274 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
1275 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
1277 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't
1278 // handle type legalization for these operations here.
1280 // FIXME: We really should do custom legalization for addition and
1281 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better
1282 // than generic legalization for 64-bit multiplication-with-overflow, though.
1283 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) {
1284 // Add/Sub/Mul with overflow operations are custom lowered.
1286 setOperationAction(ISD::SADDO, VT, Custom);
1287 setOperationAction(ISD::UADDO, VT, Custom);
1288 setOperationAction(ISD::SSUBO, VT, Custom);
1289 setOperationAction(ISD::USUBO, VT, Custom);
1290 setOperationAction(ISD::SMULO, VT, Custom);
1291 setOperationAction(ISD::UMULO, VT, Custom);
1294 // There are no 8-bit 3-address imul/mul instructions
1295 setOperationAction(ISD::SMULO, MVT::i8, Expand);
1296 setOperationAction(ISD::UMULO, MVT::i8, Expand);
1298 if (!Subtarget->is64Bit()) {
1299 // These libcalls are not available in 32-bit.
1300 setLibcallName(RTLIB::SHL_I128, 0);
1301 setLibcallName(RTLIB::SRL_I128, 0);
1302 setLibcallName(RTLIB::SRA_I128, 0);
1305 // Combine sin / cos into one node or libcall if possible.
1306 if (Subtarget->hasSinCos()) {
1307 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
1308 setLibcallName(RTLIB::SINCOS_F64, "sincos");
1309 if (Subtarget->isTargetDarwin()) {
1310 // For MacOSX, we don't want to the normal expansion of a libcall to
1311 // sincos. We want to issue a libcall to __sincos_stret to avoid memory
1313 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
1314 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
1318 // We have target-specific dag combine patterns for the following nodes:
1319 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
1320 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
1321 setTargetDAGCombine(ISD::VSELECT);
1322 setTargetDAGCombine(ISD::SELECT);
1323 setTargetDAGCombine(ISD::SHL);
1324 setTargetDAGCombine(ISD::SRA);
1325 setTargetDAGCombine(ISD::SRL);
1326 setTargetDAGCombine(ISD::OR);
1327 setTargetDAGCombine(ISD::AND);
1328 setTargetDAGCombine(ISD::ADD);
1329 setTargetDAGCombine(ISD::FADD);
1330 setTargetDAGCombine(ISD::FSUB);
1331 setTargetDAGCombine(ISD::FMA);
1332 setTargetDAGCombine(ISD::SUB);
1333 setTargetDAGCombine(ISD::LOAD);
1334 setTargetDAGCombine(ISD::STORE);
1335 setTargetDAGCombine(ISD::ZERO_EXTEND);
1336 setTargetDAGCombine(ISD::ANY_EXTEND);
1337 setTargetDAGCombine(ISD::SIGN_EXTEND);
1338 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
1339 setTargetDAGCombine(ISD::TRUNCATE);
1340 setTargetDAGCombine(ISD::SINT_TO_FP);
1341 setTargetDAGCombine(ISD::SETCC);
1342 if (Subtarget->is64Bit())
1343 setTargetDAGCombine(ISD::MUL);
1344 setTargetDAGCombine(ISD::XOR);
1346 computeRegisterProperties();
1348 // On Darwin, -Os means optimize for size without hurting performance,
1349 // do not reduce the limit.
1350 MaxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
1351 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8;
1352 MaxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores
1353 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1354 MaxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores
1355 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
1356 setPrefLoopAlignment(4); // 2^4 bytes.
1358 // Predictable cmov don't hurt on atom because it's in-order.
1359 PredictableSelectIsExpensive = !Subtarget->isAtom();
1361 setPrefFunctionAlignment(4); // 2^4 bytes.
1364 EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1365 if (!VT.isVector()) return MVT::i8;
1366 return VT.changeVectorElementTypeToInteger();
1369 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
1370 /// the desired ByVal argument alignment.
1371 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) {
1374 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
1375 if (VTy->getBitWidth() == 128)
1377 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
1378 unsigned EltAlign = 0;
1379 getMaxByValAlign(ATy->getElementType(), EltAlign);
1380 if (EltAlign > MaxAlign)
1381 MaxAlign = EltAlign;
1382 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
1383 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
1384 unsigned EltAlign = 0;
1385 getMaxByValAlign(STy->getElementType(i), EltAlign);
1386 if (EltAlign > MaxAlign)
1387 MaxAlign = EltAlign;
1394 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1395 /// function arguments in the caller parameter area. For X86, aggregates
1396 /// that contain SSE vectors are placed at 16-byte boundaries while the rest
1397 /// are at 4-byte boundaries.
1398 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const {
1399 if (Subtarget->is64Bit()) {
1400 // Max of 8 and alignment of type.
1401 unsigned TyAlign = TD->getABITypeAlignment(Ty);
1408 if (Subtarget->hasSSE1())
1409 getMaxByValAlign(Ty, Align);
1413 /// getOptimalMemOpType - Returns the target specific optimal type for load
1414 /// and store operations as a result of memset, memcpy, and memmove
1415 /// lowering. If DstAlign is zero that means it's safe to destination
1416 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
1417 /// means there isn't a need to check it against alignment requirement,
1418 /// probably because the source does not need to be loaded. If 'IsMemset' is
1419 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
1420 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
1421 /// source is constant so it does not need to be loaded.
1422 /// It returns EVT::Other if the type should be determined using generic
1423 /// target-independent logic.
1425 X86TargetLowering::getOptimalMemOpType(uint64_t Size,
1426 unsigned DstAlign, unsigned SrcAlign,
1427 bool IsMemset, bool ZeroMemset,
1429 MachineFunction &MF) const {
1430 const Function *F = MF.getFunction();
1431 if ((!IsMemset || ZeroMemset) &&
1432 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
1433 Attribute::NoImplicitFloat)) {
1435 (Subtarget->isUnalignedMemAccessFast() ||
1436 ((DstAlign == 0 || DstAlign >= 16) &&
1437 (SrcAlign == 0 || SrcAlign >= 16)))) {
1439 if (Subtarget->hasInt256())
1441 if (Subtarget->hasFp256())
1444 if (Subtarget->hasSSE2())
1446 if (Subtarget->hasSSE1())
1448 } else if (!MemcpyStrSrc && Size >= 8 &&
1449 !Subtarget->is64Bit() &&
1450 Subtarget->hasSSE2()) {
1451 // Do not use f64 to lower memcpy if source is string constant. It's
1452 // better to use i32 to avoid the loads.
1456 if (Subtarget->is64Bit() && Size >= 8)
1461 bool X86TargetLowering::isSafeMemOpType(MVT VT) const {
1463 return X86ScalarSSEf32;
1464 else if (VT == MVT::f64)
1465 return X86ScalarSSEf64;
1470 X86TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
1472 *Fast = Subtarget->isUnalignedMemAccessFast();
1476 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1477 /// current function. The returned value is a member of the
1478 /// MachineJumpTableInfo::JTEntryKind enum.
1479 unsigned X86TargetLowering::getJumpTableEncoding() const {
1480 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF
1482 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1483 Subtarget->isPICStyleGOT())
1484 return MachineJumpTableInfo::EK_Custom32;
1486 // Otherwise, use the normal jump table encoding heuristics.
1487 return TargetLowering::getJumpTableEncoding();
1491 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
1492 const MachineBasicBlock *MBB,
1493 unsigned uid,MCContext &Ctx) const{
1494 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
1495 Subtarget->isPICStyleGOT());
1496 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF
1498 return MCSymbolRefExpr::Create(MBB->getSymbol(),
1499 MCSymbolRefExpr::VK_GOTOFF, Ctx);
1502 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1504 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table,
1505 SelectionDAG &DAG) const {
1506 if (!Subtarget->is64Bit())
1507 // This doesn't have DebugLoc associated with it, but is not really the
1508 // same as a Register.
1509 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy());
1513 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1514 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1516 const MCExpr *X86TargetLowering::
1517 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI,
1518 MCContext &Ctx) const {
1519 // X86-64 uses RIP relative addressing based on the jump table label.
1520 if (Subtarget->isPICStyleRIPRel())
1521 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
1523 // Otherwise, the reference is relative to the PIC base.
1524 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx);
1527 // FIXME: Why this routine is here? Move to RegInfo!
1528 std::pair<const TargetRegisterClass*, uint8_t>
1529 X86TargetLowering::findRepresentativeClass(MVT VT) const{
1530 const TargetRegisterClass *RRC = 0;
1532 switch (VT.SimpleTy) {
1534 return TargetLowering::findRepresentativeClass(VT);
1535 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64:
1536 RRC = Subtarget->is64Bit() ?
1537 (const TargetRegisterClass*)&X86::GR64RegClass :
1538 (const TargetRegisterClass*)&X86::GR32RegClass;
1541 RRC = &X86::VR64RegClass;
1543 case MVT::f32: case MVT::f64:
1544 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1545 case MVT::v4f32: case MVT::v2f64:
1546 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32:
1548 RRC = &X86::VR128RegClass;
1551 return std::make_pair(RRC, Cost);
1554 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
1555 unsigned &Offset) const {
1556 if (!Subtarget->isTargetLinux())
1559 if (Subtarget->is64Bit()) {
1560 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs:
1562 if (getTargetMachine().getCodeModel() == CodeModel::Kernel)
1574 //===----------------------------------------------------------------------===//
1575 // Return Value Calling Convention Implementation
1576 //===----------------------------------------------------------------------===//
1578 #include "X86GenCallingConv.inc"
1581 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv,
1582 MachineFunction &MF, bool isVarArg,
1583 const SmallVectorImpl<ISD::OutputArg> &Outs,
1584 LLVMContext &Context) const {
1585 SmallVector<CCValAssign, 16> RVLocs;
1586 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1588 return CCInfo.CheckReturn(Outs, RetCC_X86);
1592 X86TargetLowering::LowerReturn(SDValue Chain,
1593 CallingConv::ID CallConv, bool isVarArg,
1594 const SmallVectorImpl<ISD::OutputArg> &Outs,
1595 const SmallVectorImpl<SDValue> &OutVals,
1596 DebugLoc dl, SelectionDAG &DAG) const {
1597 MachineFunction &MF = DAG.getMachineFunction();
1598 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1600 SmallVector<CCValAssign, 16> RVLocs;
1601 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1602 RVLocs, *DAG.getContext());
1603 CCInfo.AnalyzeReturn(Outs, RetCC_X86);
1606 SmallVector<SDValue, 6> RetOps;
1607 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1608 // Operand #1 = Bytes To Pop
1609 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),
1612 // Copy the result values into the output registers.
1613 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1614 CCValAssign &VA = RVLocs[i];
1615 assert(VA.isRegLoc() && "Can only return in registers!");
1616 SDValue ValToCopy = OutVals[i];
1617 EVT ValVT = ValToCopy.getValueType();
1619 // Promote values to the appropriate types
1620 if (VA.getLocInfo() == CCValAssign::SExt)
1621 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy);
1622 else if (VA.getLocInfo() == CCValAssign::ZExt)
1623 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy);
1624 else if (VA.getLocInfo() == CCValAssign::AExt)
1625 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy);
1626 else if (VA.getLocInfo() == CCValAssign::BCvt)
1627 ValToCopy = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), ValToCopy);
1629 // If this is x86-64, and we disabled SSE, we can't return FP values,
1630 // or SSE or MMX vectors.
1631 if ((ValVT == MVT::f32 || ValVT == MVT::f64 ||
1632 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) &&
1633 (Subtarget->is64Bit() && !Subtarget->hasSSE1())) {
1634 report_fatal_error("SSE register return with SSE disabled");
1636 // Likewise we can't return F64 values with SSE1 only. gcc does so, but
1637 // llvm-gcc has never done it right and no one has noticed, so this
1638 // should be OK for now.
1639 if (ValVT == MVT::f64 &&
1640 (Subtarget->is64Bit() && !Subtarget->hasSSE2()))
1641 report_fatal_error("SSE2 register return with SSE2 disabled");
1643 // Returns in ST0/ST1 are handled specially: these are pushed as operands to
1644 // the RET instruction and handled by the FP Stackifier.
1645 if (VA.getLocReg() == X86::ST0 ||
1646 VA.getLocReg() == X86::ST1) {
1647 // If this is a copy from an xmm register to ST(0), use an FPExtend to
1648 // change the value to the FP stack register class.
1649 if (isScalarFPTypeInSSEReg(VA.getValVT()))
1650 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy);
1651 RetOps.push_back(ValToCopy);
1652 // Don't emit a copytoreg.
1656 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64
1657 // which is returned in RAX / RDX.
1658 if (Subtarget->is64Bit()) {
1659 if (ValVT == MVT::x86mmx) {
1660 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) {
1661 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy);
1662 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
1664 // If we don't have SSE2 available, convert to v4f32 so the generated
1665 // register is legal.
1666 if (!Subtarget->hasSSE2())
1667 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy);
1672 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
1673 Flag = Chain.getValue(1);
1674 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1677 // The x86-64 ABIs require that for returning structs by value we copy
1678 // the sret argument into %rax/%eax (depending on ABI) for the return.
1679 // Win32 requires us to put the sret argument to %eax as well.
1680 // We saved the argument into a virtual register in the entry block,
1681 // so now we copy the value out and into %rax/%eax.
1682 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr() &&
1683 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
1684 MachineFunction &MF = DAG.getMachineFunction();
1685 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1686 unsigned Reg = FuncInfo->getSRetReturnReg();
1688 "SRetReturnReg should have been set in LowerFormalArguments().");
1689 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
1692 = (Subtarget->is64Bit() && !Subtarget->isTarget64BitILP32()) ?
1693 X86::RAX : X86::EAX;
1694 Chain = DAG.getCopyToReg(Chain, dl, RetValReg, Val, Flag);
1695 Flag = Chain.getValue(1);
1697 // RAX/EAX now acts like a return value.
1698 RetOps.push_back(DAG.getRegister(RetValReg, getPointerTy()));
1701 RetOps[0] = Chain; // Update chain.
1703 // Add the flag if we have it.
1705 RetOps.push_back(Flag);
1707 return DAG.getNode(X86ISD::RET_FLAG, dl,
1708 MVT::Other, &RetOps[0], RetOps.size());
1711 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1712 if (N->getNumValues() != 1)
1714 if (!N->hasNUsesOfValue(1, 0))
1717 SDValue TCChain = Chain;
1718 SDNode *Copy = *N->use_begin();
1719 if (Copy->getOpcode() == ISD::CopyToReg) {
1720 // If the copy has a glue operand, we conservatively assume it isn't safe to
1721 // perform a tail call.
1722 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1724 TCChain = Copy->getOperand(0);
1725 } else if (Copy->getOpcode() != ISD::FP_EXTEND)
1728 bool HasRet = false;
1729 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1731 if (UI->getOpcode() != X86ISD::RET_FLAG)
1744 X86TargetLowering::getTypeForExtArgOrReturn(MVT VT,
1745 ISD::NodeType ExtendKind) const {
1747 // TODO: Is this also valid on 32-bit?
1748 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND)
1749 ReturnMVT = MVT::i8;
1751 ReturnMVT = MVT::i32;
1753 MVT MinVT = getRegisterType(ReturnMVT);
1754 return VT.bitsLT(MinVT) ? MinVT : VT;
1757 /// LowerCallResult - Lower the result values of a call into the
1758 /// appropriate copies out of appropriate physical registers.
1761 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1762 CallingConv::ID CallConv, bool isVarArg,
1763 const SmallVectorImpl<ISD::InputArg> &Ins,
1764 DebugLoc dl, SelectionDAG &DAG,
1765 SmallVectorImpl<SDValue> &InVals) const {
1767 // Assign locations to each value returned by this call.
1768 SmallVector<CCValAssign, 16> RVLocs;
1769 bool Is64Bit = Subtarget->is64Bit();
1770 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1771 getTargetMachine(), RVLocs, *DAG.getContext());
1772 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1774 // Copy all of the result registers out of their specified physreg.
1775 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1776 CCValAssign &VA = RVLocs[i];
1777 EVT CopyVT = VA.getValVT();
1779 // If this is x86-64, and we disabled SSE, we can't return FP values
1780 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) &&
1781 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) {
1782 report_fatal_error("SSE register return with SSE disabled");
1787 // If this is a call to a function that returns an fp value on the floating
1788 // point stack, we must guarantee the value is popped from the stack, so
1789 // a CopyFromReg is not good enough - the copy instruction may be eliminated
1790 // if the return value is not used. We use the FpPOP_RETVAL instruction
1792 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
1793 // If we prefer to use the value in xmm registers, copy it out as f80 and
1794 // use a truncate to move it from fp stack reg to xmm reg.
1795 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
1796 SDValue Ops[] = { Chain, InFlag };
1797 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
1798 MVT::Other, MVT::Glue, Ops), 1);
1799 Val = Chain.getValue(0);
1801 // Round the f80 to the right size, which also moves it to the appropriate
1803 if (CopyVT != VA.getValVT())
1804 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,
1805 // This truncation won't change the value.
1806 DAG.getIntPtrConstant(1));
1808 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
1809 CopyVT, InFlag).getValue(1);
1810 Val = Chain.getValue(0);
1812 InFlag = Chain.getValue(2);
1813 InVals.push_back(Val);
1819 //===----------------------------------------------------------------------===//
1820 // C & StdCall & Fast Calling Convention implementation
1821 //===----------------------------------------------------------------------===//
1822 // StdCall calling convention seems to be standard for many Windows' API
1823 // routines and around. It differs from C calling convention just a little:
1824 // callee should clean up the stack, not caller. Symbols should be also
1825 // decorated in some fancy way :) It doesn't support any vector arguments.
1826 // For info on fast calling convention see Fast Calling Convention (tail call)
1827 // implementation LowerX86_32FastCCCallTo.
1829 /// CallIsStructReturn - Determines whether a call uses struct return
1831 enum StructReturnType {
1836 static StructReturnType
1837 callIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) {
1839 return NotStructReturn;
1841 const ISD::ArgFlagsTy &Flags = Outs[0].Flags;
1842 if (!Flags.isSRet())
1843 return NotStructReturn;
1844 if (Flags.isInReg())
1845 return RegStructReturn;
1846 return StackStructReturn;
1849 /// ArgsAreStructReturn - Determines whether a function uses struct
1850 /// return semantics.
1851 static StructReturnType
1852 argsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) {
1854 return NotStructReturn;
1856 const ISD::ArgFlagsTy &Flags = Ins[0].Flags;
1857 if (!Flags.isSRet())
1858 return NotStructReturn;
1859 if (Flags.isInReg())
1860 return RegStructReturn;
1861 return StackStructReturn;
1864 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1865 /// by "Src" to address "Dst" with size and alignment information specified by
1866 /// the specific parameter attribute. The copy will be passed as a byval
1867 /// function parameter.
1869 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1870 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1872 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1874 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1875 /*isVolatile*/false, /*AlwaysInline=*/true,
1876 MachinePointerInfo(), MachinePointerInfo());
1879 /// IsTailCallConvention - Return true if the calling convention is one that
1880 /// supports tail call optimization.
1881 static bool IsTailCallConvention(CallingConv::ID CC) {
1882 return (CC == CallingConv::Fast || CC == CallingConv::GHC ||
1883 CC == CallingConv::HiPE);
1886 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1887 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
1891 CallingConv::ID CalleeCC = CS.getCallingConv();
1892 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C)
1898 /// FuncIsMadeTailCallSafe - Return true if the function is being made into
1899 /// a tailcall target by changing its ABI.
1900 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC,
1901 bool GuaranteedTailCallOpt) {
1902 return GuaranteedTailCallOpt && IsTailCallConvention(CC);
1906 X86TargetLowering::LowerMemArgument(SDValue Chain,
1907 CallingConv::ID CallConv,
1908 const SmallVectorImpl<ISD::InputArg> &Ins,
1909 DebugLoc dl, SelectionDAG &DAG,
1910 const CCValAssign &VA,
1911 MachineFrameInfo *MFI,
1913 // Create the nodes corresponding to a load from this parameter slot.
1914 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1915 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv,
1916 getTargetMachine().Options.GuaranteedTailCallOpt);
1917 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal();
1920 // If value is passed by pointer we have address passed instead of the value
1922 if (VA.getLocInfo() == CCValAssign::Indirect)
1923 ValVT = VA.getLocVT();
1925 ValVT = VA.getValVT();
1927 // FIXME: For now, all byval parameter objects are marked mutable. This can be
1928 // changed with more analysis.
1929 // In case of tail call optimization mark all arguments mutable. Since they
1930 // could be overwritten by lowering of arguments in case of a tail call.
1931 if (Flags.isByVal()) {
1932 unsigned Bytes = Flags.getByValSize();
1933 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
1934 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable);
1935 return DAG.getFrameIndex(FI, getPointerTy());
1937 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8,
1938 VA.getLocMemOffset(), isImmutable);
1939 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1940 return DAG.getLoad(ValVT, dl, Chain, FIN,
1941 MachinePointerInfo::getFixedStack(FI),
1942 false, false, false, 0);
1947 X86TargetLowering::LowerFormalArguments(SDValue Chain,
1948 CallingConv::ID CallConv,
1950 const SmallVectorImpl<ISD::InputArg> &Ins,
1953 SmallVectorImpl<SDValue> &InVals)
1955 MachineFunction &MF = DAG.getMachineFunction();
1956 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1958 const Function* Fn = MF.getFunction();
1959 if (Fn->hasExternalLinkage() &&
1960 Subtarget->isTargetCygMing() &&
1961 Fn->getName() == "main")
1962 FuncInfo->setForceFramePointer(true);
1964 MachineFrameInfo *MFI = MF.getFrameInfo();
1965 bool Is64Bit = Subtarget->is64Bit();
1966 bool IsWindows = Subtarget->isTargetWindows();
1967 bool IsWin64 = Subtarget->isTargetWin64();
1969 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
1970 "Var args not supported with calling convention fastcc, ghc or hipe");
1972 // Assign locations to all of the incoming arguments.
1973 SmallVector<CCValAssign, 16> ArgLocs;
1974 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
1975 ArgLocs, *DAG.getContext());
1977 // Allocate shadow area for Win64
1979 CCInfo.AllocateStack(32, 8);
1982 CCInfo.AnalyzeFormalArguments(Ins, CC_X86);
1984 unsigned LastVal = ~0U;
1986 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1987 CCValAssign &VA = ArgLocs[i];
1988 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later
1990 assert(VA.getValNo() != LastVal &&
1991 "Don't support value assigned to multiple locs yet");
1993 LastVal = VA.getValNo();
1995 if (VA.isRegLoc()) {
1996 EVT RegVT = VA.getLocVT();
1997 const TargetRegisterClass *RC;
1998 if (RegVT == MVT::i32)
1999 RC = &X86::GR32RegClass;
2000 else if (Is64Bit && RegVT == MVT::i64)
2001 RC = &X86::GR64RegClass;
2002 else if (RegVT == MVT::f32)
2003 RC = &X86::FR32RegClass;
2004 else if (RegVT == MVT::f64)
2005 RC = &X86::FR64RegClass;
2006 else if (RegVT.is256BitVector())
2007 RC = &X86::VR256RegClass;
2008 else if (RegVT.is128BitVector())
2009 RC = &X86::VR128RegClass;
2010 else if (RegVT == MVT::x86mmx)
2011 RC = &X86::VR64RegClass;
2013 llvm_unreachable("Unknown argument type!");
2015 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2016 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2018 // If this is an 8 or 16-bit value, it is really passed promoted to 32
2019 // bits. Insert an assert[sz]ext to capture this, then truncate to the
2021 if (VA.getLocInfo() == CCValAssign::SExt)
2022 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2023 DAG.getValueType(VA.getValVT()));
2024 else if (VA.getLocInfo() == CCValAssign::ZExt)
2025 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2026 DAG.getValueType(VA.getValVT()));
2027 else if (VA.getLocInfo() == CCValAssign::BCvt)
2028 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2030 if (VA.isExtInLoc()) {
2031 // Handle MMX values passed in XMM regs.
2032 if (RegVT.isVector())
2033 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), ArgValue);
2035 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2038 assert(VA.isMemLoc());
2039 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i);
2042 // If value is passed via pointer - do a load.
2043 if (VA.getLocInfo() == CCValAssign::Indirect)
2044 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue,
2045 MachinePointerInfo(), false, false, false, 0);
2047 InVals.push_back(ArgValue);
2050 // The x86-64 ABIs require that for returning structs by value we copy
2051 // the sret argument into %rax/%eax (depending on ABI) for the return.
2052 // Win32 requires us to put the sret argument to %eax as well.
2053 // Save the argument into a virtual register so that we can access it
2054 // from the return points.
2055 if (MF.getFunction()->hasStructRetAttr() &&
2056 (Subtarget->is64Bit() || Subtarget->isTargetWindows())) {
2057 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
2058 unsigned Reg = FuncInfo->getSRetReturnReg();
2060 MVT PtrTy = getPointerTy();
2061 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy));
2062 FuncInfo->setSRetReturnReg(Reg);
2064 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
2065 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
2068 unsigned StackSize = CCInfo.getNextStackOffset();
2069 // Align stack specially for tail calls.
2070 if (FuncIsMadeTailCallSafe(CallConv,
2071 MF.getTarget().Options.GuaranteedTailCallOpt))
2072 StackSize = GetAlignedArgumentStackSize(StackSize, DAG);
2074 // If the function takes variable number of arguments, make a frame index for
2075 // the start of the first vararg value... for expansion of llvm.va_start.
2077 if (Is64Bit || (CallConv != CallingConv::X86_FastCall &&
2078 CallConv != CallingConv::X86_ThisCall)) {
2079 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true));
2082 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
2084 // FIXME: We should really autogenerate these arrays
2085 static const uint16_t GPR64ArgRegsWin64[] = {
2086 X86::RCX, X86::RDX, X86::R8, X86::R9
2088 static const uint16_t GPR64ArgRegs64Bit[] = {
2089 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
2091 static const uint16_t XMMArgRegs64Bit[] = {
2092 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2093 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2095 const uint16_t *GPR64ArgRegs;
2096 unsigned NumXMMRegs = 0;
2099 // The XMM registers which might contain var arg parameters are shadowed
2100 // in their paired GPR. So we only need to save the GPR to their home
2102 TotalNumIntRegs = 4;
2103 GPR64ArgRegs = GPR64ArgRegsWin64;
2105 TotalNumIntRegs = 6; TotalNumXMMRegs = 8;
2106 GPR64ArgRegs = GPR64ArgRegs64Bit;
2108 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit,
2111 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs,
2114 bool NoImplicitFloatOps = Fn->getAttributes().
2115 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
2116 assert(!(NumXMMRegs && !Subtarget->hasSSE1()) &&
2117 "SSE register cannot be used when SSE is disabled!");
2118 assert(!(NumXMMRegs && MF.getTarget().Options.UseSoftFloat &&
2119 NoImplicitFloatOps) &&
2120 "SSE register cannot be used when SSE is disabled!");
2121 if (MF.getTarget().Options.UseSoftFloat || NoImplicitFloatOps ||
2122 !Subtarget->hasSSE1())
2123 // Kernel mode asks for SSE to be disabled, so don't push them
2125 TotalNumXMMRegs = 0;
2128 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering();
2129 // Get to the caller-allocated home save location. Add 8 to account
2130 // for the return address.
2131 int HomeOffset = TFI.getOffsetOfLocalArea() + 8;
2132 FuncInfo->setRegSaveFrameIndex(
2133 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false));
2134 // Fixup to set vararg frame on shadow area (4 x i64).
2136 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex());
2138 // For X86-64, if there are vararg parameters that are passed via
2139 // registers, then we must store them to their spots on the stack so
2140 // they may be loaded by deferencing the result of va_next.
2141 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8);
2142 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16);
2143 FuncInfo->setRegSaveFrameIndex(
2144 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16,
2148 // Store the integer parameter registers.
2149 SmallVector<SDValue, 8> MemOps;
2150 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
2152 unsigned Offset = FuncInfo->getVarArgsGPOffset();
2153 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) {
2154 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
2155 DAG.getIntPtrConstant(Offset));
2156 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
2157 &X86::GR64RegClass);
2158 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2160 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2161 MachinePointerInfo::getFixedStack(
2162 FuncInfo->getRegSaveFrameIndex(), Offset),
2164 MemOps.push_back(Store);
2168 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) {
2169 // Now store the XMM (fp + vector) parameter registers.
2170 SmallVector<SDValue, 11> SaveXMMOps;
2171 SaveXMMOps.push_back(Chain);
2173 unsigned AL = MF.addLiveIn(X86::AL, &X86::GR8RegClass);
2174 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
2175 SaveXMMOps.push_back(ALVal);
2177 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2178 FuncInfo->getRegSaveFrameIndex()));
2179 SaveXMMOps.push_back(DAG.getIntPtrConstant(
2180 FuncInfo->getVarArgsFPOffset()));
2182 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
2183 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
2184 &X86::VR128RegClass);
2185 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
2186 SaveXMMOps.push_back(Val);
2188 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,
2190 &SaveXMMOps[0], SaveXMMOps.size()));
2193 if (!MemOps.empty())
2194 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2195 &MemOps[0], MemOps.size());
2199 // Some CCs need callee pop.
2200 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2201 MF.getTarget().Options.GuaranteedTailCallOpt)) {
2202 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
2204 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
2205 // If this is an sret function, the return should pop the hidden pointer.
2206 if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2207 argsAreStructReturn(Ins) == StackStructReturn)
2208 FuncInfo->setBytesToPopOnReturn(4);
2212 // RegSaveFrameIndex is X86-64 only.
2213 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA);
2214 if (CallConv == CallingConv::X86_FastCall ||
2215 CallConv == CallingConv::X86_ThisCall)
2216 // fastcc functions can't have varargs.
2217 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA);
2220 FuncInfo->setArgumentStackSize(StackSize);
2226 X86TargetLowering::LowerMemOpCallTo(SDValue Chain,
2227 SDValue StackPtr, SDValue Arg,
2228 DebugLoc dl, SelectionDAG &DAG,
2229 const CCValAssign &VA,
2230 ISD::ArgFlagsTy Flags) const {
2231 unsigned LocMemOffset = VA.getLocMemOffset();
2232 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2233 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2234 if (Flags.isByVal())
2235 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
2237 return DAG.getStore(Chain, dl, Arg, PtrOff,
2238 MachinePointerInfo::getStack(LocMemOffset),
2242 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call
2243 /// optimization is performed and it is required.
2245 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG,
2246 SDValue &OutRetAddr, SDValue Chain,
2247 bool IsTailCall, bool Is64Bit,
2248 int FPDiff, DebugLoc dl) const {
2249 // Adjust the Return address stack slot.
2250 EVT VT = getPointerTy();
2251 OutRetAddr = getReturnAddressFrameIndex(DAG);
2253 // Load the "old" Return address.
2254 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(),
2255 false, false, false, 0);
2256 return SDValue(OutRetAddr.getNode(), 1);
2259 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call
2260 /// optimization is performed and it is required (FPDiff!=0).
2262 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
2263 SDValue Chain, SDValue RetAddrFrIdx, EVT PtrVT,
2264 unsigned SlotSize, int FPDiff, DebugLoc dl) {
2265 // Store the return address to the appropriate stack slot.
2266 if (!FPDiff) return Chain;
2267 // Calculate the new stack slot for the return address.
2268 int NewReturnAddrFI =
2269 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false);
2270 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, PtrVT);
2271 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx,
2272 MachinePointerInfo::getFixedStack(NewReturnAddrFI),
2278 X86TargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2279 SmallVectorImpl<SDValue> &InVals) const {
2280 SelectionDAG &DAG = CLI.DAG;
2281 DebugLoc &dl = CLI.DL;
2282 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2283 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2284 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2285 SDValue Chain = CLI.Chain;
2286 SDValue Callee = CLI.Callee;
2287 CallingConv::ID CallConv = CLI.CallConv;
2288 bool &isTailCall = CLI.IsTailCall;
2289 bool isVarArg = CLI.IsVarArg;
2291 MachineFunction &MF = DAG.getMachineFunction();
2292 bool Is64Bit = Subtarget->is64Bit();
2293 bool IsWin64 = Subtarget->isTargetWin64();
2294 bool IsWindows = Subtarget->isTargetWindows();
2295 StructReturnType SR = callIsStructReturn(Outs);
2296 bool IsSibcall = false;
2298 if (MF.getTarget().Options.DisableTailCalls)
2302 // Check if it's really possible to do a tail call.
2303 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
2304 isVarArg, SR != NotStructReturn,
2305 MF.getFunction()->hasStructRetAttr(), CLI.RetTy,
2306 Outs, OutVals, Ins, DAG);
2308 // Sibcalls are automatically detected tailcalls which do not require
2310 if (!MF.getTarget().Options.GuaranteedTailCallOpt && isTailCall)
2317 assert(!(isVarArg && IsTailCallConvention(CallConv)) &&
2318 "Var args not supported with calling convention fastcc, ghc or hipe");
2320 // Analyze operands of the call, assigning locations to each operand.
2321 SmallVector<CCValAssign, 16> ArgLocs;
2322 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
2323 ArgLocs, *DAG.getContext());
2325 // Allocate shadow area for Win64
2327 CCInfo.AllocateStack(32, 8);
2330 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2332 // Get a count of how many bytes are to be pushed on the stack.
2333 unsigned NumBytes = CCInfo.getNextStackOffset();
2335 // This is a sibcall. The memory operands are available in caller's
2336 // own caller's stack.
2338 else if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2339 IsTailCallConvention(CallConv))
2340 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG);
2343 if (isTailCall && !IsSibcall) {
2344 // Lower arguments at fp - stackoffset + fpdiff.
2345 X86MachineFunctionInfo *X86Info = MF.getInfo<X86MachineFunctionInfo>();
2346 unsigned NumBytesCallerPushed = X86Info->getBytesToPopOnReturn();
2348 FPDiff = NumBytesCallerPushed - NumBytes;
2350 // Set the delta of movement of the returnaddr stackslot.
2351 // But only set if delta is greater than previous delta.
2352 if (FPDiff < X86Info->getTCReturnAddrDelta())
2353 X86Info->setTCReturnAddrDelta(FPDiff);
2357 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2359 SDValue RetAddrFrIdx;
2360 // Load return address for tail calls.
2361 if (isTailCall && FPDiff)
2362 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall,
2363 Is64Bit, FPDiff, dl);
2365 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2366 SmallVector<SDValue, 8> MemOpChains;
2369 // Walk the register/memloc assignments, inserting copies/loads. In the case
2370 // of tail call optimization arguments are handle later.
2371 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2372 CCValAssign &VA = ArgLocs[i];
2373 EVT RegVT = VA.getLocVT();
2374 SDValue Arg = OutVals[i];
2375 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2376 bool isByVal = Flags.isByVal();
2378 // Promote the value if needed.
2379 switch (VA.getLocInfo()) {
2380 default: llvm_unreachable("Unknown loc info!");
2381 case CCValAssign::Full: break;
2382 case CCValAssign::SExt:
2383 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg);
2385 case CCValAssign::ZExt:
2386 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg);
2388 case CCValAssign::AExt:
2389 if (RegVT.is128BitVector()) {
2390 // Special case: passing MMX values in XMM registers.
2391 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
2392 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg);
2393 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg);
2395 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
2397 case CCValAssign::BCvt:
2398 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg);
2400 case CCValAssign::Indirect: {
2401 // Store the argument.
2402 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
2403 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
2404 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot,
2405 MachinePointerInfo::getFixedStack(FI),
2412 if (VA.isRegLoc()) {
2413 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2414 if (isVarArg && IsWin64) {
2415 // Win64 ABI requires argument XMM reg to be copied to the corresponding
2416 // shadow reg if callee is a varargs function.
2417 unsigned ShadowReg = 0;
2418 switch (VA.getLocReg()) {
2419 case X86::XMM0: ShadowReg = X86::RCX; break;
2420 case X86::XMM1: ShadowReg = X86::RDX; break;
2421 case X86::XMM2: ShadowReg = X86::R8; break;
2422 case X86::XMM3: ShadowReg = X86::R9; break;
2425 RegsToPass.push_back(std::make_pair(ShadowReg, Arg));
2427 } else if (!IsSibcall && (!isTailCall || isByVal)) {
2428 assert(VA.isMemLoc());
2429 if (StackPtr.getNode() == 0)
2430 StackPtr = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
2432 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
2433 dl, DAG, VA, Flags));
2437 if (!MemOpChains.empty())
2438 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2439 &MemOpChains[0], MemOpChains.size());
2441 if (Subtarget->isPICStyleGOT()) {
2442 // ELF / PIC requires GOT in the EBX register before function calls via PLT
2445 RegsToPass.push_back(std::make_pair(unsigned(X86::EBX),
2446 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy())));
2448 // If we are tail calling and generating PIC/GOT style code load the
2449 // address of the callee into ECX. The value in ecx is used as target of
2450 // the tail jump. This is done to circumvent the ebx/callee-saved problem
2451 // for tail calls on PIC/GOT architectures. Normally we would just put the
2452 // address of GOT into ebx and then call target@PLT. But for tail calls
2453 // ebx would be restored (since ebx is callee saved) before jumping to the
2456 // Note: The actual moving to ECX is done further down.
2457 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
2458 if (G && !G->getGlobal()->hasHiddenVisibility() &&
2459 !G->getGlobal()->hasProtectedVisibility())
2460 Callee = LowerGlobalAddress(Callee, DAG);
2461 else if (isa<ExternalSymbolSDNode>(Callee))
2462 Callee = LowerExternalSymbol(Callee, DAG);
2466 if (Is64Bit && isVarArg && !IsWin64) {
2467 // From AMD64 ABI document:
2468 // For calls that may call functions that use varargs or stdargs
2469 // (prototype-less calls or calls to functions containing ellipsis (...) in
2470 // the declaration) %al is used as hidden argument to specify the number
2471 // of SSE registers used. The contents of %al do not need to match exactly
2472 // the number of registers, but must be an ubound on the number of SSE
2473 // registers used and is in the range 0 - 8 inclusive.
2475 // Count the number of XMM registers allocated.
2476 static const uint16_t XMMArgRegs[] = {
2477 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
2478 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
2480 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8);
2481 assert((Subtarget->hasSSE1() || !NumXMMRegs)
2482 && "SSE registers cannot be used when SSE is disabled");
2484 RegsToPass.push_back(std::make_pair(unsigned(X86::AL),
2485 DAG.getConstant(NumXMMRegs, MVT::i8)));
2488 // For tail calls lower the arguments to the 'real' stack slot.
2490 // Force all the incoming stack arguments to be loaded from the stack
2491 // before any new outgoing arguments are stored to the stack, because the
2492 // outgoing stack slots may alias the incoming argument stack slots, and
2493 // the alias isn't otherwise explicit. This is slightly more conservative
2494 // than necessary, because it means that each store effectively depends
2495 // on every argument instead of just those arguments it would clobber.
2496 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain);
2498 SmallVector<SDValue, 8> MemOpChains2;
2501 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2503 CCValAssign &VA = ArgLocs[i];
2506 assert(VA.isMemLoc());
2507 SDValue Arg = OutVals[i];
2508 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2509 // Create frame index.
2510 int32_t Offset = VA.getLocMemOffset()+FPDiff;
2511 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8;
2512 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2513 FIN = DAG.getFrameIndex(FI, getPointerTy());
2515 if (Flags.isByVal()) {
2516 // Copy relative to framepointer.
2517 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());
2518 if (StackPtr.getNode() == 0)
2519 StackPtr = DAG.getCopyFromReg(Chain, dl,
2520 RegInfo->getStackRegister(),
2522 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source);
2524 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN,
2528 // Store relative to framepointer.
2529 MemOpChains2.push_back(
2530 DAG.getStore(ArgChain, dl, Arg, FIN,
2531 MachinePointerInfo::getFixedStack(FI),
2537 if (!MemOpChains2.empty())
2538 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2539 &MemOpChains2[0], MemOpChains2.size());
2541 // Store the return address to the appropriate stack slot.
2542 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx,
2543 getPointerTy(), RegInfo->getSlotSize(),
2547 // Build a sequence of copy-to-reg nodes chained together with token chain
2548 // and flag operands which copy the outgoing args into registers.
2550 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2551 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2552 RegsToPass[i].second, InFlag);
2553 InFlag = Chain.getValue(1);
2556 if (getTargetMachine().getCodeModel() == CodeModel::Large) {
2557 assert(Is64Bit && "Large code model is only legal in 64-bit mode.");
2558 // In the 64-bit large code model, we have to make all calls
2559 // through a register, since the call instruction's 32-bit
2560 // pc-relative offset may not be large enough to hold the whole
2562 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2563 // If the callee is a GlobalAddress node (quite common, every direct call
2564 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack
2567 // We should use extra load for direct calls to dllimported functions in
2569 const GlobalValue *GV = G->getGlobal();
2570 if (!GV->hasDLLImportLinkage()) {
2571 unsigned char OpFlags = 0;
2572 bool ExtraLoad = false;
2573 unsigned WrapperKind = ISD::DELETED_NODE;
2575 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to
2576 // external symbols most go through the PLT in PIC mode. If the symbol
2577 // has hidden or protected visibility, or if it is static or local, then
2578 // we don't need to use the PLT - we can directly call it.
2579 if (Subtarget->isTargetELF() &&
2580 getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
2581 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) {
2582 OpFlags = X86II::MO_PLT;
2583 } else if (Subtarget->isPICStyleStubAny() &&
2584 (GV->isDeclaration() || GV->isWeakForLinker()) &&
2585 (!Subtarget->getTargetTriple().isMacOSX() ||
2586 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2587 // PC-relative references to external symbols should go through $stub,
2588 // unless we're building with the leopard linker or later, which
2589 // automatically synthesizes these stubs.
2590 OpFlags = X86II::MO_DARWIN_STUB;
2591 } else if (Subtarget->isPICStyleRIPRel() &&
2592 isa<Function>(GV) &&
2593 cast<Function>(GV)->getAttributes().
2594 hasAttribute(AttributeSet::FunctionIndex,
2595 Attribute::NonLazyBind)) {
2596 // If the function is marked as non-lazy, generate an indirect call
2597 // which loads from the GOT directly. This avoids runtime overhead
2598 // at the cost of eager binding (and one extra byte of encoding).
2599 OpFlags = X86II::MO_GOTPCREL;
2600 WrapperKind = X86ISD::WrapperRIP;
2604 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
2605 G->getOffset(), OpFlags);
2607 // Add a wrapper if needed.
2608 if (WrapperKind != ISD::DELETED_NODE)
2609 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee);
2610 // Add extra indirection if needed.
2612 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
2613 MachinePointerInfo::getGOT(),
2614 false, false, false, 0);
2616 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2617 unsigned char OpFlags = 0;
2619 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to
2620 // external symbols should go through the PLT.
2621 if (Subtarget->isTargetELF() &&
2622 getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2623 OpFlags = X86II::MO_PLT;
2624 } else if (Subtarget->isPICStyleStubAny() &&
2625 (!Subtarget->getTargetTriple().isMacOSX() ||
2626 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) {
2627 // PC-relative references to external symbols should go through $stub,
2628 // unless we're building with the leopard linker or later, which
2629 // automatically synthesizes these stubs.
2630 OpFlags = X86II::MO_DARWIN_STUB;
2633 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(),
2637 // Returns a chain & a flag for retval copy to use.
2638 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2639 SmallVector<SDValue, 8> Ops;
2641 if (!IsSibcall && isTailCall) {
2642 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2643 DAG.getIntPtrConstant(0, true), InFlag);
2644 InFlag = Chain.getValue(1);
2647 Ops.push_back(Chain);
2648 Ops.push_back(Callee);
2651 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));
2653 // Add argument registers to the end of the list so that they are known live
2655 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2656 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2657 RegsToPass[i].second.getValueType()));
2659 // Add a register mask operand representing the call-preserved registers.
2660 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2661 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2662 assert(Mask && "Missing call preserved mask for calling convention");
2663 Ops.push_back(DAG.getRegisterMask(Mask));
2665 if (InFlag.getNode())
2666 Ops.push_back(InFlag);
2670 //// If this is the first return lowered for this function, add the regs
2671 //// to the liveout set for the function.
2672 // This isn't right, although it's probably harmless on x86; liveouts
2673 // should be computed from returns not tail calls. Consider a void
2674 // function making a tail call to a function returning int.
2675 return DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
2678 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
2679 InFlag = Chain.getValue(1);
2681 // Create the CALLSEQ_END node.
2682 unsigned NumBytesForCalleeToPush;
2683 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg,
2684 getTargetMachine().Options.GuaranteedTailCallOpt))
2685 NumBytesForCalleeToPush = NumBytes; // Callee pops everything
2686 else if (!Is64Bit && !IsTailCallConvention(CallConv) && !IsWindows &&
2687 SR == StackStructReturn)
2688 // If this is a call to a struct-return function, the callee
2689 // pops the hidden struct pointer, so we have to push it back.
2690 // This is common for Darwin/X86, Linux & Mingw32 targets.
2691 // For MSVC Win32 targets, the caller pops the hidden struct pointer.
2692 NumBytesForCalleeToPush = 4;
2694 NumBytesForCalleeToPush = 0; // Callee pops nothing.
2696 // Returns a flag for retval copy to use.
2698 Chain = DAG.getCALLSEQ_END(Chain,
2699 DAG.getIntPtrConstant(NumBytes, true),
2700 DAG.getIntPtrConstant(NumBytesForCalleeToPush,
2703 InFlag = Chain.getValue(1);
2706 // Handle result values, copying them out of physregs into vregs that we
2708 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2709 Ins, dl, DAG, InVals);
2712 //===----------------------------------------------------------------------===//
2713 // Fast Calling Convention (tail call) implementation
2714 //===----------------------------------------------------------------------===//
2716 // Like std call, callee cleans arguments, convention except that ECX is
2717 // reserved for storing the tail called function address. Only 2 registers are
2718 // free for argument passing (inreg). Tail call optimization is performed
2720 // * tailcallopt is enabled
2721 // * caller/callee are fastcc
2722 // On X86_64 architecture with GOT-style position independent code only local
2723 // (within module) calls are supported at the moment.
2724 // To keep the stack aligned according to platform abi the function
2725 // GetAlignedArgumentStackSize ensures that argument delta is always multiples
2726 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example)
2727 // If a tail called function callee has more arguments than the caller the
2728 // caller needs to make sure that there is room to move the RETADDR to. This is
2729 // achieved by reserving an area the size of the argument delta right after the
2730 // original REtADDR, but before the saved framepointer or the spilled registers
2731 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4)
2743 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned
2744 /// for a 16 byte align requirement.
2746 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
2747 SelectionDAG& DAG) const {
2748 MachineFunction &MF = DAG.getMachineFunction();
2749 const TargetMachine &TM = MF.getTarget();
2750 const TargetFrameLowering &TFI = *TM.getFrameLowering();
2751 unsigned StackAlignment = TFI.getStackAlignment();
2752 uint64_t AlignMask = StackAlignment - 1;
2753 int64_t Offset = StackSize;
2754 unsigned SlotSize = RegInfo->getSlotSize();
2755 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) {
2756 // Number smaller than 12 so just add the difference.
2757 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask));
2759 // Mask out lower bits, add stackalignment once plus the 12 bytes.
2760 Offset = ((~AlignMask) & Offset) + StackAlignment +
2761 (StackAlignment-SlotSize);
2766 /// MatchingStackOffset - Return true if the given stack call argument is
2767 /// already available in the same position (relatively) of the caller's
2768 /// incoming argument stack.
2770 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2771 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2772 const X86InstrInfo *TII) {
2773 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2775 if (Arg.getOpcode() == ISD::CopyFromReg) {
2776 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2777 if (!TargetRegisterInfo::isVirtualRegister(VR))
2779 MachineInstr *Def = MRI->getVRegDef(VR);
2782 if (!Flags.isByVal()) {
2783 if (!TII->isLoadFromStackSlot(Def, FI))
2786 unsigned Opcode = Def->getOpcode();
2787 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
2788 Def->getOperand(1).isFI()) {
2789 FI = Def->getOperand(1).getIndex();
2790 Bytes = Flags.getByValSize();
2794 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2795 if (Flags.isByVal())
2796 // ByVal argument is passed in as a pointer but it's now being
2797 // dereferenced. e.g.
2798 // define @foo(%struct.X* %A) {
2799 // tail call @bar(%struct.X* byval %A)
2802 SDValue Ptr = Ld->getBasePtr();
2803 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2806 FI = FINode->getIndex();
2807 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
2808 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
2809 FI = FINode->getIndex();
2810 Bytes = Flags.getByValSize();
2814 assert(FI != INT_MAX);
2815 if (!MFI->isFixedObjectIndex(FI))
2817 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2820 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2821 /// for tail call optimization. Targets which want to do tail call
2822 /// optimization should implement this function.
2824 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2825 CallingConv::ID CalleeCC,
2827 bool isCalleeStructRet,
2828 bool isCallerStructRet,
2830 const SmallVectorImpl<ISD::OutputArg> &Outs,
2831 const SmallVectorImpl<SDValue> &OutVals,
2832 const SmallVectorImpl<ISD::InputArg> &Ins,
2833 SelectionDAG &DAG) const {
2834 if (!IsTailCallConvention(CalleeCC) &&
2835 CalleeCC != CallingConv::C)
2838 // If -tailcallopt is specified, make fastcc functions tail-callable.
2839 const MachineFunction &MF = DAG.getMachineFunction();
2840 const Function *CallerF = DAG.getMachineFunction().getFunction();
2842 // If the function return type is x86_fp80 and the callee return type is not,
2843 // then the FP_EXTEND of the call result is not a nop. It's not safe to
2844 // perform a tailcall optimization here.
2845 if (CallerF->getReturnType()->isX86_FP80Ty() && !RetTy->isX86_FP80Ty())
2848 CallingConv::ID CallerCC = CallerF->getCallingConv();
2849 bool CCMatch = CallerCC == CalleeCC;
2851 if (getTargetMachine().Options.GuaranteedTailCallOpt) {
2852 if (IsTailCallConvention(CalleeCC) && CCMatch)
2857 // Look for obvious safe cases to perform tail call optimization that do not
2858 // require ABI changes. This is what gcc calls sibcall.
2860 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to
2861 // emit a special epilogue.
2862 if (RegInfo->needsStackRealignment(MF))
2865 // Also avoid sibcall optimization if either caller or callee uses struct
2866 // return semantics.
2867 if (isCalleeStructRet || isCallerStructRet)
2870 // An stdcall caller is expected to clean up its arguments; the callee
2871 // isn't going to do that.
2872 if (!CCMatch && CallerCC == CallingConv::X86_StdCall)
2875 // Do not sibcall optimize vararg calls unless all arguments are passed via
2877 if (isVarArg && !Outs.empty()) {
2879 // Optimizing for varargs on Win64 is unlikely to be safe without
2880 // additional testing.
2881 if (Subtarget->isTargetWin64())
2884 SmallVector<CCValAssign, 16> ArgLocs;
2885 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2886 getTargetMachine(), ArgLocs, *DAG.getContext());
2888 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2889 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i)
2890 if (!ArgLocs[i].isRegLoc())
2894 // If the call result is in ST0 / ST1, it needs to be popped off the x87
2895 // stack. Therefore, if it's not used by the call it is not safe to optimize
2896 // this into a sibcall.
2897 bool Unused = false;
2898 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
2905 SmallVector<CCValAssign, 16> RVLocs;
2906 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(),
2907 getTargetMachine(), RVLocs, *DAG.getContext());
2908 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
2909 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2910 CCValAssign &VA = RVLocs[i];
2911 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
2916 // If the calling conventions do not match, then we'd better make sure the
2917 // results are returned in the same way as what the caller expects.
2919 SmallVector<CCValAssign, 16> RVLocs1;
2920 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2921 getTargetMachine(), RVLocs1, *DAG.getContext());
2922 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86);
2924 SmallVector<CCValAssign, 16> RVLocs2;
2925 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2926 getTargetMachine(), RVLocs2, *DAG.getContext());
2927 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86);
2929 if (RVLocs1.size() != RVLocs2.size())
2931 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2932 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2934 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2936 if (RVLocs1[i].isRegLoc()) {
2937 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2940 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2946 // If the callee takes no arguments then go on to check the results of the
2948 if (!Outs.empty()) {
2949 // Check if stack adjustment is needed. For now, do not do this if any
2950 // argument is passed on the stack.
2951 SmallVector<CCValAssign, 16> ArgLocs;
2952 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2953 getTargetMachine(), ArgLocs, *DAG.getContext());
2955 // Allocate shadow area for Win64
2956 if (Subtarget->isTargetWin64()) {
2957 CCInfo.AllocateStack(32, 8);
2960 CCInfo.AnalyzeCallOperands(Outs, CC_X86);
2961 if (CCInfo.getNextStackOffset()) {
2962 MachineFunction &MF = DAG.getMachineFunction();
2963 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn())
2966 // Check if the arguments are already laid out in the right way as
2967 // the caller's fixed stack objects.
2968 MachineFrameInfo *MFI = MF.getFrameInfo();
2969 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2970 const X86InstrInfo *TII =
2971 ((const X86TargetMachine&)getTargetMachine()).getInstrInfo();
2972 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2973 CCValAssign &VA = ArgLocs[i];
2974 SDValue Arg = OutVals[i];
2975 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2976 if (VA.getLocInfo() == CCValAssign::Indirect)
2978 if (!VA.isRegLoc()) {
2979 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2986 // If the tailcall address may be in a register, then make sure it's
2987 // possible to register allocate for it. In 32-bit, the call address can
2988 // only target EAX, EDX, or ECX since the tail call must be scheduled after
2989 // callee-saved registers are restored. These happen to be the same
2990 // registers used to pass 'inreg' arguments so watch out for those.
2991 if (!Subtarget->is64Bit() &&
2992 ((!isa<GlobalAddressSDNode>(Callee) &&
2993 !isa<ExternalSymbolSDNode>(Callee)) ||
2994 getTargetMachine().getRelocationModel() == Reloc::PIC_)) {
2995 unsigned NumInRegs = 0;
2996 // In PIC we need an extra register to formulate the address computation
2998 unsigned MaxInRegs =
2999 (getTargetMachine().getRelocationModel() == Reloc::PIC_) ? 2 : 3;
3001 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3002 CCValAssign &VA = ArgLocs[i];
3005 unsigned Reg = VA.getLocReg();
3008 case X86::EAX: case X86::EDX: case X86::ECX:
3009 if (++NumInRegs == MaxInRegs)
3021 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
3022 const TargetLibraryInfo *libInfo) const {
3023 return X86::createFastISel(funcInfo, libInfo);
3026 //===----------------------------------------------------------------------===//
3027 // Other Lowering Hooks
3028 //===----------------------------------------------------------------------===//
3030 static bool MayFoldLoad(SDValue Op) {
3031 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode());
3034 static bool MayFoldIntoStore(SDValue Op) {
3035 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin());
3038 static bool isTargetShuffle(unsigned Opcode) {
3040 default: return false;
3041 case X86ISD::PSHUFD:
3042 case X86ISD::PSHUFHW:
3043 case X86ISD::PSHUFLW:
3045 case X86ISD::PALIGNR:
3046 case X86ISD::MOVLHPS:
3047 case X86ISD::MOVLHPD:
3048 case X86ISD::MOVHLPS:
3049 case X86ISD::MOVLPS:
3050 case X86ISD::MOVLPD:
3051 case X86ISD::MOVSHDUP:
3052 case X86ISD::MOVSLDUP:
3053 case X86ISD::MOVDDUP:
3056 case X86ISD::UNPCKL:
3057 case X86ISD::UNPCKH:
3058 case X86ISD::VPERMILP:
3059 case X86ISD::VPERM2X128:
3060 case X86ISD::VPERMI:
3065 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3066 SDValue V1, SelectionDAG &DAG) {
3068 default: llvm_unreachable("Unknown x86 shuffle node");
3069 case X86ISD::MOVSHDUP:
3070 case X86ISD::MOVSLDUP:
3071 case X86ISD::MOVDDUP:
3072 return DAG.getNode(Opc, dl, VT, V1);
3076 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3077 SDValue V1, unsigned TargetMask,
3078 SelectionDAG &DAG) {
3080 default: llvm_unreachable("Unknown x86 shuffle node");
3081 case X86ISD::PSHUFD:
3082 case X86ISD::PSHUFHW:
3083 case X86ISD::PSHUFLW:
3084 case X86ISD::VPERMILP:
3085 case X86ISD::VPERMI:
3086 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));
3090 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3091 SDValue V1, SDValue V2, unsigned TargetMask,
3092 SelectionDAG &DAG) {
3094 default: llvm_unreachable("Unknown x86 shuffle node");
3095 case X86ISD::PALIGNR:
3097 case X86ISD::VPERM2X128:
3098 return DAG.getNode(Opc, dl, VT, V1, V2,
3099 DAG.getConstant(TargetMask, MVT::i8));
3103 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
3104 SDValue V1, SDValue V2, SelectionDAG &DAG) {
3106 default: llvm_unreachable("Unknown x86 shuffle node");
3107 case X86ISD::MOVLHPS:
3108 case X86ISD::MOVLHPD:
3109 case X86ISD::MOVHLPS:
3110 case X86ISD::MOVLPS:
3111 case X86ISD::MOVLPD:
3114 case X86ISD::UNPCKL:
3115 case X86ISD::UNPCKH:
3116 return DAG.getNode(Opc, dl, VT, V1, V2);
3120 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const {
3121 MachineFunction &MF = DAG.getMachineFunction();
3122 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
3123 int ReturnAddrIndex = FuncInfo->getRAIndex();
3125 if (ReturnAddrIndex == 0) {
3126 // Set up a frame object for the return address.
3127 unsigned SlotSize = RegInfo->getSlotSize();
3128 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize,
3130 FuncInfo->setRAIndex(ReturnAddrIndex);
3133 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy());
3136 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
3137 bool hasSymbolicDisplacement) {
3138 // Offset should fit into 32 bit immediate field.
3139 if (!isInt<32>(Offset))
3142 // If we don't have a symbolic displacement - we don't have any extra
3144 if (!hasSymbolicDisplacement)
3147 // FIXME: Some tweaks might be needed for medium code model.
3148 if (M != CodeModel::Small && M != CodeModel::Kernel)
3151 // For small code model we assume that latest object is 16MB before end of 31
3152 // bits boundary. We may also accept pretty large negative constants knowing
3153 // that all objects are in the positive half of address space.
3154 if (M == CodeModel::Small && Offset < 16*1024*1024)
3157 // For kernel code model we know that all object resist in the negative half
3158 // of 32bits address space. We may not accept negative offsets, since they may
3159 // be just off and we may accept pretty large positive ones.
3160 if (M == CodeModel::Kernel && Offset > 0)
3166 /// isCalleePop - Determines whether the callee is required to pop its
3167 /// own arguments. Callee pop is necessary to support tail calls.
3168 bool X86::isCalleePop(CallingConv::ID CallingConv,
3169 bool is64Bit, bool IsVarArg, bool TailCallOpt) {
3173 switch (CallingConv) {
3176 case CallingConv::X86_StdCall:
3178 case CallingConv::X86_FastCall:
3180 case CallingConv::X86_ThisCall:
3182 case CallingConv::Fast:
3184 case CallingConv::GHC:
3186 case CallingConv::HiPE:
3191 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
3192 /// specific condition code, returning the condition code and the LHS/RHS of the
3193 /// comparison to make.
3194 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,
3195 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {
3197 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
3198 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
3199 // X > -1 -> X == 0, jump !sign.
3200 RHS = DAG.getConstant(0, RHS.getValueType());
3201 return X86::COND_NS;
3203 if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {
3204 // X < 0 -> X == 0, jump on sign.
3207 if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {
3209 RHS = DAG.getConstant(0, RHS.getValueType());
3210 return X86::COND_LE;
3214 switch (SetCCOpcode) {
3215 default: llvm_unreachable("Invalid integer condition!");
3216 case ISD::SETEQ: return X86::COND_E;
3217 case ISD::SETGT: return X86::COND_G;
3218 case ISD::SETGE: return X86::COND_GE;
3219 case ISD::SETLT: return X86::COND_L;
3220 case ISD::SETLE: return X86::COND_LE;
3221 case ISD::SETNE: return X86::COND_NE;
3222 case ISD::SETULT: return X86::COND_B;
3223 case ISD::SETUGT: return X86::COND_A;
3224 case ISD::SETULE: return X86::COND_BE;
3225 case ISD::SETUGE: return X86::COND_AE;
3229 // First determine if it is required or is profitable to flip the operands.
3231 // If LHS is a foldable load, but RHS is not, flip the condition.
3232 if (ISD::isNON_EXTLoad(LHS.getNode()) &&
3233 !ISD::isNON_EXTLoad(RHS.getNode())) {
3234 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode);
3235 std::swap(LHS, RHS);
3238 switch (SetCCOpcode) {
3244 std::swap(LHS, RHS);
3248 // On a floating point condition, the flags are set as follows:
3250 // 0 | 0 | 0 | X > Y
3251 // 0 | 0 | 1 | X < Y
3252 // 1 | 0 | 0 | X == Y
3253 // 1 | 1 | 1 | unordered
3254 switch (SetCCOpcode) {
3255 default: llvm_unreachable("Condcode should be pre-legalized away");
3257 case ISD::SETEQ: return X86::COND_E;
3258 case ISD::SETOLT: // flipped
3260 case ISD::SETGT: return X86::COND_A;
3261 case ISD::SETOLE: // flipped
3263 case ISD::SETGE: return X86::COND_AE;
3264 case ISD::SETUGT: // flipped
3266 case ISD::SETLT: return X86::COND_B;
3267 case ISD::SETUGE: // flipped
3269 case ISD::SETLE: return X86::COND_BE;
3271 case ISD::SETNE: return X86::COND_NE;
3272 case ISD::SETUO: return X86::COND_P;
3273 case ISD::SETO: return X86::COND_NP;
3275 case ISD::SETUNE: return X86::COND_INVALID;
3279 /// hasFPCMov - is there a floating point cmov for the specific X86 condition
3280 /// code. Current x86 isa includes the following FP cmov instructions:
3281 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu.
3282 static bool hasFPCMov(unsigned X86CC) {
3298 /// isFPImmLegal - Returns true if the target can instruction select the
3299 /// specified FP immediate natively. If false, the legalizer will
3300 /// materialize the FP immediate as a load from a constant pool.
3301 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3302 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) {
3303 if (Imm.bitwiseIsEqual(LegalFPImmediates[i]))
3309 /// isUndefOrInRange - Return true if Val is undef or if its value falls within
3310 /// the specified range (L, H].
3311 static bool isUndefOrInRange(int Val, int Low, int Hi) {
3312 return (Val < 0) || (Val >= Low && Val < Hi);
3315 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the
3316 /// specified value.
3317 static bool isUndefOrEqual(int Val, int CmpVal) {
3318 return (Val < 0 || Val == CmpVal);
3321 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
3322 /// from position Pos and ending in Pos+Size, falls within the specified
3323 /// sequential range (L, L+Pos]. or is undef.
3324 static bool isSequentialOrUndefInRange(ArrayRef<int> Mask,
3325 unsigned Pos, unsigned Size, int Low) {
3326 for (unsigned i = Pos, e = Pos+Size; i != e; ++i, ++Low)
3327 if (!isUndefOrEqual(Mask[i], Low))
3332 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that
3333 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference
3334 /// the second operand.
3335 static bool isPSHUFDMask(ArrayRef<int> Mask, EVT VT) {
3336 if (VT == MVT::v4f32 || VT == MVT::v4i32 )
3337 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4);
3338 if (VT == MVT::v2f64 || VT == MVT::v2i64)
3339 return (Mask[0] < 2 && Mask[1] < 2);
3343 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that
3344 /// is suitable for input to PSHUFHW.
3345 static bool isPSHUFHWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3346 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3349 // Lower quadword copied in order or undef.
3350 if (!isSequentialOrUndefInRange(Mask, 0, 4, 0))
3353 // Upper quadword shuffled.
3354 for (unsigned i = 4; i != 8; ++i)
3355 if (!isUndefOrInRange(Mask[i], 4, 8))
3358 if (VT == MVT::v16i16) {
3359 // Lower quadword copied in order or undef.
3360 if (!isSequentialOrUndefInRange(Mask, 8, 4, 8))
3363 // Upper quadword shuffled.
3364 for (unsigned i = 12; i != 16; ++i)
3365 if (!isUndefOrInRange(Mask[i], 12, 16))
3372 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that
3373 /// is suitable for input to PSHUFLW.
3374 static bool isPSHUFLWMask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3375 if (VT != MVT::v8i16 && (!HasInt256 || VT != MVT::v16i16))
3378 // Upper quadword copied in order.
3379 if (!isSequentialOrUndefInRange(Mask, 4, 4, 4))
3382 // Lower quadword shuffled.
3383 for (unsigned i = 0; i != 4; ++i)
3384 if (!isUndefOrInRange(Mask[i], 0, 4))
3387 if (VT == MVT::v16i16) {
3388 // Upper quadword copied in order.
3389 if (!isSequentialOrUndefInRange(Mask, 12, 4, 12))
3392 // Lower quadword shuffled.
3393 for (unsigned i = 8; i != 12; ++i)
3394 if (!isUndefOrInRange(Mask[i], 8, 12))
3401 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
3402 /// is suitable for input to PALIGNR.
3403 static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
3404 const X86Subtarget *Subtarget) {
3405 if ((VT.is128BitVector() && !Subtarget->hasSSSE3()) ||
3406 (VT.is256BitVector() && !Subtarget->hasInt256()))
3409 unsigned NumElts = VT.getVectorNumElements();
3410 unsigned NumLanes = VT.getSizeInBits()/128;
3411 unsigned NumLaneElts = NumElts/NumLanes;
3413 // Do not handle 64-bit element shuffles with palignr.
3414 if (NumLaneElts == 2)
3417 for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
3419 for (i = 0; i != NumLaneElts; ++i) {
3424 // Lane is all undef, go to next lane
3425 if (i == NumLaneElts)
3428 int Start = Mask[i+l];
3430 // Make sure its in this lane in one of the sources
3431 if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
3432 !isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
3435 // If not lane 0, then we must match lane 0
3436 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
3439 // Correct second source to be contiguous with first source
3440 if (Start >= (int)NumElts)
3441 Start -= NumElts - NumLaneElts;
3443 // Make sure we're shifting in the right direction.
3444 if (Start <= (int)(i+l))
3449 // Check the rest of the elements to see if they are consecutive.
3450 for (++i; i != NumLaneElts; ++i) {
3451 int Idx = Mask[i+l];
3453 // Make sure its in this lane
3454 if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
3455 !isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
3458 // If not lane 0, then we must match lane 0
3459 if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
3462 if (Idx >= (int)NumElts)
3463 Idx -= NumElts - NumLaneElts;
3465 if (!isUndefOrEqual(Idx, Start+i))
3474 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming
3475 /// the two vector operands have swapped position.
3476 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask,
3477 unsigned NumElems) {
3478 for (unsigned i = 0; i != NumElems; ++i) {
3482 else if (idx < (int)NumElems)
3483 Mask[i] = idx + NumElems;
3485 Mask[i] = idx - NumElems;
3489 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
3490 /// specifies a shuffle of elements that is suitable for input to 128/256-bit
3491 /// SHUFPS and SHUFPD. If Commuted is true, then it checks for sources to be
3492 /// reverse of what x86 shuffles want.
3493 static bool isSHUFPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256,
3494 bool Commuted = false) {
3495 if (!HasFp256 && VT.is256BitVector())
3498 unsigned NumElems = VT.getVectorNumElements();
3499 unsigned NumLanes = VT.getSizeInBits()/128;
3500 unsigned NumLaneElems = NumElems/NumLanes;
3502 if (NumLaneElems != 2 && NumLaneElems != 4)
3505 // VSHUFPSY divides the resulting vector into 4 chunks.
3506 // The sources are also splitted into 4 chunks, and each destination
3507 // chunk must come from a different source chunk.
3509 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0
3510 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9
3512 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4,
3513 // Y3..Y0, Y3..Y0, X3..X0, X3..X0
3515 // VSHUFPDY divides the resulting vector into 4 chunks.
3516 // The sources are also splitted into 4 chunks, and each destination
3517 // chunk must come from a different source chunk.
3519 // SRC1 => X3 X2 X1 X0
3520 // SRC2 => Y3 Y2 Y1 Y0
3522 // DST => Y3..Y2, X3..X2, Y1..Y0, X1..X0
3524 unsigned HalfLaneElems = NumLaneElems/2;
3525 for (unsigned l = 0; l != NumElems; l += NumLaneElems) {
3526 for (unsigned i = 0; i != NumLaneElems; ++i) {
3527 int Idx = Mask[i+l];
3528 unsigned RngStart = l + ((Commuted == (i<HalfLaneElems)) ? NumElems : 0);
3529 if (!isUndefOrInRange(Idx, RngStart, RngStart+NumLaneElems))
3531 // For VSHUFPSY, the mask of the second half must be the same as the
3532 // first but with the appropriate offsets. This works in the same way as
3533 // VPERMILPS works with masks.
3534 if (NumElems != 8 || l == 0 || Mask[i] < 0)
3536 if (!isUndefOrEqual(Idx, Mask[i]+l))
3544 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
3545 /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
3546 static bool isMOVHLPSMask(ArrayRef<int> Mask, EVT VT) {
3547 if (!VT.is128BitVector())
3550 unsigned NumElems = VT.getVectorNumElements();
3555 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3
3556 return isUndefOrEqual(Mask[0], 6) &&
3557 isUndefOrEqual(Mask[1], 7) &&
3558 isUndefOrEqual(Mask[2], 2) &&
3559 isUndefOrEqual(Mask[3], 3);
3562 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
3563 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
3565 static bool isMOVHLPS_v_undef_Mask(ArrayRef<int> Mask, EVT VT) {
3566 if (!VT.is128BitVector())
3569 unsigned NumElems = VT.getVectorNumElements();
3574 return isUndefOrEqual(Mask[0], 2) &&
3575 isUndefOrEqual(Mask[1], 3) &&
3576 isUndefOrEqual(Mask[2], 2) &&
3577 isUndefOrEqual(Mask[3], 3);
3580 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
3581 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}.
3582 static bool isMOVLPMask(ArrayRef<int> Mask, EVT VT) {
3583 if (!VT.is128BitVector())
3586 unsigned NumElems = VT.getVectorNumElements();
3588 if (NumElems != 2 && NumElems != 4)
3591 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3592 if (!isUndefOrEqual(Mask[i], i + NumElems))
3595 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
3596 if (!isUndefOrEqual(Mask[i], i))
3602 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand
3603 /// specifies a shuffle of elements that is suitable for input to MOVLHPS.
3604 static bool isMOVLHPSMask(ArrayRef<int> Mask, EVT VT) {
3605 if (!VT.is128BitVector())
3608 unsigned NumElems = VT.getVectorNumElements();
3610 if (NumElems != 2 && NumElems != 4)
3613 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3614 if (!isUndefOrEqual(Mask[i], i))
3617 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
3618 if (!isUndefOrEqual(Mask[i + e], i + NumElems))
3625 // Some special combinations that can be optimized.
3628 SDValue Compact8x32ShuffleNode(ShuffleVectorSDNode *SVOp,
3629 SelectionDAG &DAG) {
3630 MVT VT = SVOp->getValueType(0).getSimpleVT();
3631 DebugLoc dl = SVOp->getDebugLoc();
3633 if (VT != MVT::v8i32 && VT != MVT::v8f32)
3636 ArrayRef<int> Mask = SVOp->getMask();
3638 // These are the special masks that may be optimized.
3639 static const int MaskToOptimizeEven[] = {0, 8, 2, 10, 4, 12, 6, 14};
3640 static const int MaskToOptimizeOdd[] = {1, 9, 3, 11, 5, 13, 7, 15};
3641 bool MatchEvenMask = true;
3642 bool MatchOddMask = true;
3643 for (int i=0; i<8; ++i) {
3644 if (!isUndefOrEqual(Mask[i], MaskToOptimizeEven[i]))
3645 MatchEvenMask = false;
3646 if (!isUndefOrEqual(Mask[i], MaskToOptimizeOdd[i]))
3647 MatchOddMask = false;
3650 if (!MatchEvenMask && !MatchOddMask)
3653 SDValue UndefNode = DAG.getNode(ISD::UNDEF, dl, VT);
3655 SDValue Op0 = SVOp->getOperand(0);
3656 SDValue Op1 = SVOp->getOperand(1);
3658 if (MatchEvenMask) {
3659 // Shift the second operand right to 32 bits.
3660 static const int ShiftRightMask[] = {-1, 0, -1, 2, -1, 4, -1, 6 };
3661 Op1 = DAG.getVectorShuffle(VT, dl, Op1, UndefNode, ShiftRightMask);
3663 // Shift the first operand left to 32 bits.
3664 static const int ShiftLeftMask[] = {1, -1, 3, -1, 5, -1, 7, -1 };
3665 Op0 = DAG.getVectorShuffle(VT, dl, Op0, UndefNode, ShiftLeftMask);
3667 static const int BlendMask[] = {0, 9, 2, 11, 4, 13, 6, 15};
3668 return DAG.getVectorShuffle(VT, dl, Op0, Op1, BlendMask);
3671 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
3672 /// specifies a shuffle of elements that is suitable for input to UNPCKL.
3673 static bool isUNPCKLMask(ArrayRef<int> Mask, EVT VT,
3674 bool HasInt256, bool V2IsSplat = false) {
3675 unsigned NumElts = VT.getVectorNumElements();
3677 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3678 "Unsupported vector type for unpckh");
3680 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3681 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3684 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3685 // independently on 128-bit lanes.
3686 unsigned NumLanes = VT.getSizeInBits()/128;
3687 unsigned NumLaneElts = NumElts/NumLanes;
3689 for (unsigned l = 0; l != NumLanes; ++l) {
3690 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3691 i != (l+1)*NumLaneElts;
3694 int BitI1 = Mask[i+1];
3695 if (!isUndefOrEqual(BitI, j))
3698 if (!isUndefOrEqual(BitI1, NumElts))
3701 if (!isUndefOrEqual(BitI1, j + NumElts))
3710 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
3711 /// specifies a shuffle of elements that is suitable for input to UNPCKH.
3712 static bool isUNPCKHMask(ArrayRef<int> Mask, EVT VT,
3713 bool HasInt256, bool V2IsSplat = false) {
3714 unsigned NumElts = VT.getVectorNumElements();
3716 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3717 "Unsupported vector type for unpckh");
3719 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3720 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3723 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3724 // independently on 128-bit lanes.
3725 unsigned NumLanes = VT.getSizeInBits()/128;
3726 unsigned NumLaneElts = NumElts/NumLanes;
3728 for (unsigned l = 0; l != NumLanes; ++l) {
3729 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3730 i != (l+1)*NumLaneElts; i += 2, ++j) {
3732 int BitI1 = Mask[i+1];
3733 if (!isUndefOrEqual(BitI, j))
3736 if (isUndefOrEqual(BitI1, NumElts))
3739 if (!isUndefOrEqual(BitI1, j+NumElts))
3747 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
3748 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
3750 static bool isUNPCKL_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3751 unsigned NumElts = VT.getVectorNumElements();
3752 bool Is256BitVec = VT.is256BitVector();
3754 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3755 "Unsupported vector type for unpckh");
3757 if (Is256BitVec && NumElts != 4 && NumElts != 8 &&
3758 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3761 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern
3762 // FIXME: Need a better way to get rid of this, there's no latency difference
3763 // between UNPCKLPD and MOVDDUP, the later should always be checked first and
3764 // the former later. We should also remove the "_undef" special mask.
3765 if (NumElts == 4 && Is256BitVec)
3768 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3769 // independently on 128-bit lanes.
3770 unsigned NumLanes = VT.getSizeInBits()/128;
3771 unsigned NumLaneElts = NumElts/NumLanes;
3773 for (unsigned l = 0; l != NumLanes; ++l) {
3774 for (unsigned i = l*NumLaneElts, j = l*NumLaneElts;
3775 i != (l+1)*NumLaneElts;
3778 int BitI1 = Mask[i+1];
3780 if (!isUndefOrEqual(BitI, j))
3782 if (!isUndefOrEqual(BitI1, j))
3790 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
3791 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
3793 static bool isUNPCKH_v_undef_Mask(ArrayRef<int> Mask, EVT VT, bool HasInt256) {
3794 unsigned NumElts = VT.getVectorNumElements();
3796 assert((VT.is128BitVector() || VT.is256BitVector()) &&
3797 "Unsupported vector type for unpckh");
3799 if (VT.is256BitVector() && NumElts != 4 && NumElts != 8 &&
3800 (!HasInt256 || (NumElts != 16 && NumElts != 32)))
3803 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
3804 // independently on 128-bit lanes.
3805 unsigned NumLanes = VT.getSizeInBits()/128;
3806 unsigned NumLaneElts = NumElts/NumLanes;
3808 for (unsigned l = 0; l != NumLanes; ++l) {
3809 for (unsigned i = l*NumLaneElts, j = (l*NumLaneElts)+NumLaneElts/2;
3810 i != (l+1)*NumLaneElts; i += 2, ++j) {
3812 int BitI1 = Mask[i+1];
3813 if (!isUndefOrEqual(BitI, j))
3815 if (!isUndefOrEqual(BitI1, j))
3822 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
3823 /// specifies a shuffle of elements that is suitable for input to MOVSS,
3824 /// MOVSD, and MOVD, i.e. setting the lowest element.
3825 static bool isMOVLMask(ArrayRef<int> Mask, EVT VT) {
3826 if (VT.getVectorElementType().getSizeInBits() < 32)
3828 if (!VT.is128BitVector())
3831 unsigned NumElts = VT.getVectorNumElements();
3833 if (!isUndefOrEqual(Mask[0], NumElts))
3836 for (unsigned i = 1; i != NumElts; ++i)
3837 if (!isUndefOrEqual(Mask[i], i))
3843 /// isVPERM2X128Mask - Match 256-bit shuffles where the elements are considered
3844 /// as permutations between 128-bit chunks or halves. As an example: this
3846 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15>
3847 /// The first half comes from the second half of V1 and the second half from the
3848 /// the second half of V2.
3849 static bool isVPERM2X128Mask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3850 if (!HasFp256 || !VT.is256BitVector())
3853 // The shuffle result is divided into half A and half B. In total the two
3854 // sources have 4 halves, namely: C, D, E, F. The final values of A and
3855 // B must come from C, D, E or F.
3856 unsigned HalfSize = VT.getVectorNumElements()/2;
3857 bool MatchA = false, MatchB = false;
3859 // Check if A comes from one of C, D, E, F.
3860 for (unsigned Half = 0; Half != 4; ++Half) {
3861 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) {
3867 // Check if B comes from one of C, D, E, F.
3868 for (unsigned Half = 0; Half != 4; ++Half) {
3869 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) {
3875 return MatchA && MatchB;
3878 /// getShuffleVPERM2X128Immediate - Return the appropriate immediate to shuffle
3879 /// the specified VECTOR_MASK mask with VPERM2F128/VPERM2I128 instructions.
3880 static unsigned getShuffleVPERM2X128Immediate(ShuffleVectorSDNode *SVOp) {
3881 MVT VT = SVOp->getValueType(0).getSimpleVT();
3883 unsigned HalfSize = VT.getVectorNumElements()/2;
3885 unsigned FstHalf = 0, SndHalf = 0;
3886 for (unsigned i = 0; i < HalfSize; ++i) {
3887 if (SVOp->getMaskElt(i) > 0) {
3888 FstHalf = SVOp->getMaskElt(i)/HalfSize;
3892 for (unsigned i = HalfSize; i < HalfSize*2; ++i) {
3893 if (SVOp->getMaskElt(i) > 0) {
3894 SndHalf = SVOp->getMaskElt(i)/HalfSize;
3899 return (FstHalf | (SndHalf << 4));
3902 /// isVPERMILPMask - Return true if the specified VECTOR_SHUFFLE operand
3903 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*.
3904 /// Note that VPERMIL mask matching is different depending whether theunderlying
3905 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point
3906 /// to the same elements of the low, but to the higher half of the source.
3907 /// In VPERMILPD the two lanes could be shuffled independently of each other
3908 /// with the same restriction that lanes can't be crossed. Also handles PSHUFDY.
3909 static bool isVPERMILPMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
3913 unsigned NumElts = VT.getVectorNumElements();
3914 // Only match 256-bit with 32/64-bit types
3915 if (!VT.is256BitVector() || (NumElts != 4 && NumElts != 8))
3918 unsigned NumLanes = VT.getSizeInBits()/128;
3919 unsigned LaneSize = NumElts/NumLanes;
3920 for (unsigned l = 0; l != NumElts; l += LaneSize) {
3921 for (unsigned i = 0; i != LaneSize; ++i) {
3922 if (!isUndefOrInRange(Mask[i+l], l, l+LaneSize))
3924 if (NumElts != 8 || l == 0)
3926 // VPERMILPS handling
3929 if (!isUndefOrEqual(Mask[i+l], Mask[i]+l))
3937 /// isCommutedMOVLMask - Returns true if the shuffle mask is except the reverse
3938 /// of what x86 movss want. X86 movs requires the lowest element to be lowest
3939 /// element of vector 2 and the other elements to come from vector 1 in order.
3940 static bool isCommutedMOVLMask(ArrayRef<int> Mask, EVT VT,
3941 bool V2IsSplat = false, bool V2IsUndef = false) {
3942 if (!VT.is128BitVector())
3945 unsigned NumOps = VT.getVectorNumElements();
3946 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16)
3949 if (!isUndefOrEqual(Mask[0], 0))
3952 for (unsigned i = 1; i != NumOps; ++i)
3953 if (!(isUndefOrEqual(Mask[i], i+NumOps) ||
3954 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) ||
3955 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps))))
3961 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3962 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
3963 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7>
3964 static bool isMOVSHDUPMask(ArrayRef<int> Mask, EVT VT,
3965 const X86Subtarget *Subtarget) {
3966 if (!Subtarget->hasSSE3())
3969 unsigned NumElems = VT.getVectorNumElements();
3971 if ((VT.is128BitVector() && NumElems != 4) ||
3972 (VT.is256BitVector() && NumElems != 8))
3975 // "i+1" is the value the indexed mask element must have
3976 for (unsigned i = 0; i != NumElems; i += 2)
3977 if (!isUndefOrEqual(Mask[i], i+1) ||
3978 !isUndefOrEqual(Mask[i+1], i+1))
3984 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
3985 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
3986 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6>
3987 static bool isMOVSLDUPMask(ArrayRef<int> Mask, EVT VT,
3988 const X86Subtarget *Subtarget) {
3989 if (!Subtarget->hasSSE3())
3992 unsigned NumElems = VT.getVectorNumElements();
3994 if ((VT.is128BitVector() && NumElems != 4) ||
3995 (VT.is256BitVector() && NumElems != 8))
3998 // "i" is the value the indexed mask element must have
3999 for (unsigned i = 0; i != NumElems; i += 2)
4000 if (!isUndefOrEqual(Mask[i], i) ||
4001 !isUndefOrEqual(Mask[i+1], i))
4007 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand
4008 /// specifies a shuffle of elements that is suitable for input to 256-bit
4009 /// version of MOVDDUP.
4010 static bool isMOVDDUPYMask(ArrayRef<int> Mask, EVT VT, bool HasFp256) {
4011 if (!HasFp256 || !VT.is256BitVector())
4014 unsigned NumElts = VT.getVectorNumElements();
4018 for (unsigned i = 0; i != NumElts/2; ++i)
4019 if (!isUndefOrEqual(Mask[i], 0))
4021 for (unsigned i = NumElts/2; i != NumElts; ++i)
4022 if (!isUndefOrEqual(Mask[i], NumElts/2))
4027 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
4028 /// specifies a shuffle of elements that is suitable for input to 128-bit
4029 /// version of MOVDDUP.
4030 static bool isMOVDDUPMask(ArrayRef<int> Mask, EVT VT) {
4031 if (!VT.is128BitVector())
4034 unsigned e = VT.getVectorNumElements() / 2;
4035 for (unsigned i = 0; i != e; ++i)
4036 if (!isUndefOrEqual(Mask[i], i))
4038 for (unsigned i = 0; i != e; ++i)
4039 if (!isUndefOrEqual(Mask[e+i], i))
4044 /// isVEXTRACTF128Index - Return true if the specified
4045 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
4046 /// suitable for input to VEXTRACTF128.
4047 bool X86::isVEXTRACTF128Index(SDNode *N) {
4048 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4051 // The index should be aligned on a 128-bit boundary.
4053 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4055 MVT VT = N->getValueType(0).getSimpleVT();
4056 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4057 bool Result = (Index * ElSize) % 128 == 0;
4062 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR
4063 /// operand specifies a subvector insert that is suitable for input to
4065 bool X86::isVINSERTF128Index(SDNode *N) {
4066 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4069 // The index should be aligned on a 128-bit boundary.
4071 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4073 MVT VT = N->getValueType(0).getSimpleVT();
4074 unsigned ElSize = VT.getVectorElementType().getSizeInBits();
4075 bool Result = (Index * ElSize) % 128 == 0;
4080 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
4081 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions.
4082 /// Handles 128-bit and 256-bit.
4083 static unsigned getShuffleSHUFImmediate(ShuffleVectorSDNode *N) {
4084 MVT VT = N->getValueType(0).getSimpleVT();
4086 assert((VT.is128BitVector() || VT.is256BitVector()) &&
4087 "Unsupported vector type for PSHUF/SHUFP");
4089 // Handle 128 and 256-bit vector lengths. AVX defines PSHUF/SHUFP to operate
4090 // independently on 128-bit lanes.
4091 unsigned NumElts = VT.getVectorNumElements();
4092 unsigned NumLanes = VT.getSizeInBits()/128;
4093 unsigned NumLaneElts = NumElts/NumLanes;
4095 assert((NumLaneElts == 2 || NumLaneElts == 4) &&
4096 "Only supports 2 or 4 elements per lane");
4098 unsigned Shift = (NumLaneElts == 4) ? 1 : 0;
4100 for (unsigned i = 0; i != NumElts; ++i) {
4101 int Elt = N->getMaskElt(i);
4102 if (Elt < 0) continue;
4103 Elt &= NumLaneElts - 1;
4104 unsigned ShAmt = (i << Shift) % 8;
4105 Mask |= Elt << ShAmt;
4111 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
4112 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction.
4113 static unsigned getShufflePSHUFHWImmediate(ShuffleVectorSDNode *N) {
4114 MVT VT = N->getValueType(0).getSimpleVT();
4116 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4117 "Unsupported vector type for PSHUFHW");
4119 unsigned NumElts = VT.getVectorNumElements();
4122 for (unsigned l = 0; l != NumElts; l += 8) {
4123 // 8 nodes per lane, but we only care about the last 4.
4124 for (unsigned i = 0; i < 4; ++i) {
4125 int Elt = N->getMaskElt(l+i+4);
4126 if (Elt < 0) continue;
4127 Elt &= 0x3; // only 2-bits.
4128 Mask |= Elt << (i * 2);
4135 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
4136 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction.
4137 static unsigned getShufflePSHUFLWImmediate(ShuffleVectorSDNode *N) {
4138 MVT VT = N->getValueType(0).getSimpleVT();
4140 assert((VT == MVT::v8i16 || VT == MVT::v16i16) &&
4141 "Unsupported vector type for PSHUFHW");
4143 unsigned NumElts = VT.getVectorNumElements();
4146 for (unsigned l = 0; l != NumElts; l += 8) {
4147 // 8 nodes per lane, but we only care about the first 4.
4148 for (unsigned i = 0; i < 4; ++i) {
4149 int Elt = N->getMaskElt(l+i);
4150 if (Elt < 0) continue;
4151 Elt &= 0x3; // only 2-bits
4152 Mask |= Elt << (i * 2);
4159 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
4160 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
4161 static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
4162 MVT VT = SVOp->getValueType(0).getSimpleVT();
4163 unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
4165 unsigned NumElts = VT.getVectorNumElements();
4166 unsigned NumLanes = VT.getSizeInBits()/128;
4167 unsigned NumLaneElts = NumElts/NumLanes;
4171 for (i = 0; i != NumElts; ++i) {
4172 Val = SVOp->getMaskElt(i);
4176 if (Val >= (int)NumElts)
4177 Val -= NumElts - NumLaneElts;
4179 assert(Val - i > 0 && "PALIGNR imm should be positive");
4180 return (Val - i) * EltSize;
4183 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate
4184 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128
4186 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) {
4187 if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
4188 llvm_unreachable("Illegal extract subvector for VEXTRACTF128");
4191 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
4193 MVT VecVT = N->getOperand(0).getValueType().getSimpleVT();
4194 MVT ElVT = VecVT.getVectorElementType();
4196 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4197 return Index / NumElemsPerChunk;
4200 /// getInsertVINSERTF128Immediate - Return the appropriate immediate
4201 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128
4203 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) {
4204 if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
4205 llvm_unreachable("Illegal insert subvector for VINSERTF128");
4208 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
4210 MVT VecVT = N->getValueType(0).getSimpleVT();
4211 MVT ElVT = VecVT.getVectorElementType();
4213 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits();
4214 return Index / NumElemsPerChunk;
4217 /// getShuffleCLImmediate - Return the appropriate immediate to shuffle
4218 /// the specified VECTOR_SHUFFLE mask with VPERMQ and VPERMPD instructions.
4219 /// Handles 256-bit.
4220 static unsigned getShuffleCLImmediate(ShuffleVectorSDNode *N) {
4221 MVT VT = N->getValueType(0).getSimpleVT();
4223 unsigned NumElts = VT.getVectorNumElements();
4225 assert((VT.is256BitVector() && NumElts == 4) &&
4226 "Unsupported vector type for VPERMQ/VPERMPD");
4229 for (unsigned i = 0; i != NumElts; ++i) {
4230 int Elt = N->getMaskElt(i);
4233 Mask |= Elt << (i*2);
4238 /// isZeroNode - Returns true if Elt is a constant zero or a floating point
4240 bool X86::isZeroNode(SDValue Elt) {
4241 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Elt))
4242 return CN->isNullValue();
4243 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Elt))
4244 return CFP->getValueAPF().isPosZero();
4248 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in
4249 /// their permute mask.
4250 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp,
4251 SelectionDAG &DAG) {
4252 MVT VT = SVOp->getValueType(0).getSimpleVT();
4253 unsigned NumElems = VT.getVectorNumElements();
4254 SmallVector<int, 8> MaskVec;
4256 for (unsigned i = 0; i != NumElems; ++i) {
4257 int Idx = SVOp->getMaskElt(i);
4259 if (Idx < (int)NumElems)
4264 MaskVec.push_back(Idx);
4266 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1),
4267 SVOp->getOperand(0), &MaskVec[0]);
4270 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to
4271 /// match movhlps. The lower half elements should come from upper half of
4272 /// V1 (and in order), and the upper half elements should come from the upper
4273 /// half of V2 (and in order).
4274 static bool ShouldXformToMOVHLPS(ArrayRef<int> Mask, EVT VT) {
4275 if (!VT.is128BitVector())
4277 if (VT.getVectorNumElements() != 4)
4279 for (unsigned i = 0, e = 2; i != e; ++i)
4280 if (!isUndefOrEqual(Mask[i], i+2))
4282 for (unsigned i = 2; i != 4; ++i)
4283 if (!isUndefOrEqual(Mask[i], i+4))
4288 /// isScalarLoadToVector - Returns true if the node is a scalar load that
4289 /// is promoted to a vector. It also returns the LoadSDNode by reference if
4291 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) {
4292 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR)
4294 N = N->getOperand(0).getNode();
4295 if (!ISD::isNON_EXTLoad(N))
4298 *LD = cast<LoadSDNode>(N);
4302 // Test whether the given value is a vector value which will be legalized
4304 static bool WillBeConstantPoolLoad(SDNode *N) {
4305 if (N->getOpcode() != ISD::BUILD_VECTOR)
4308 // Check for any non-constant elements.
4309 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
4310 switch (N->getOperand(i).getNode()->getOpcode()) {
4312 case ISD::ConstantFP:
4319 // Vectors of all-zeros and all-ones are materialized with special
4320 // instructions rather than being loaded.
4321 return !ISD::isBuildVectorAllZeros(N) &&
4322 !ISD::isBuildVectorAllOnes(N);
4325 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to
4326 /// match movlp{s|d}. The lower half elements should come from lower half of
4327 /// V1 (and in order), and the upper half elements should come from the upper
4328 /// half of V2 (and in order). And since V1 will become the source of the
4329 /// MOVLP, it must be either a vector load or a scalar load to vector.
4330 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2,
4331 ArrayRef<int> Mask, EVT VT) {
4332 if (!VT.is128BitVector())
4335 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1))
4337 // Is V2 is a vector load, don't do this transformation. We will try to use
4338 // load folding shufps op.
4339 if (ISD::isNON_EXTLoad(V2) || WillBeConstantPoolLoad(V2))
4342 unsigned NumElems = VT.getVectorNumElements();
4344 if (NumElems != 2 && NumElems != 4)
4346 for (unsigned i = 0, e = NumElems/2; i != e; ++i)
4347 if (!isUndefOrEqual(Mask[i], i))
4349 for (unsigned i = NumElems/2, e = NumElems; i != e; ++i)
4350 if (!isUndefOrEqual(Mask[i], i+NumElems))
4355 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
4357 static bool isSplatVector(SDNode *N) {
4358 if (N->getOpcode() != ISD::BUILD_VECTOR)
4361 SDValue SplatValue = N->getOperand(0);
4362 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i)
4363 if (N->getOperand(i) != SplatValue)
4368 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved
4369 /// to an zero vector.
4370 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode
4371 static bool isZeroShuffle(ShuffleVectorSDNode *N) {
4372 SDValue V1 = N->getOperand(0);
4373 SDValue V2 = N->getOperand(1);
4374 unsigned NumElems = N->getValueType(0).getVectorNumElements();
4375 for (unsigned i = 0; i != NumElems; ++i) {
4376 int Idx = N->getMaskElt(i);
4377 if (Idx >= (int)NumElems) {
4378 unsigned Opc = V2.getOpcode();
4379 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode()))
4381 if (Opc != ISD::BUILD_VECTOR ||
4382 !X86::isZeroNode(V2.getOperand(Idx-NumElems)))
4384 } else if (Idx >= 0) {
4385 unsigned Opc = V1.getOpcode();
4386 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode()))
4388 if (Opc != ISD::BUILD_VECTOR ||
4389 !X86::isZeroNode(V1.getOperand(Idx)))
4396 /// getZeroVector - Returns a vector of specified type with all zero elements.
4398 static SDValue getZeroVector(EVT VT, const X86Subtarget *Subtarget,
4399 SelectionDAG &DAG, DebugLoc dl) {
4400 assert(VT.isVector() && "Expected a vector type");
4402 // Always build SSE zero vectors as <4 x i32> bitcasted
4403 // to their dest type. This ensures they get CSE'd.
4405 if (VT.is128BitVector()) { // SSE
4406 if (Subtarget->hasSSE2()) { // SSE2
4407 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4408 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4410 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4411 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
4413 } else if (VT.is256BitVector()) { // AVX
4414 if (Subtarget->hasInt256()) { // AVX2
4415 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
4416 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4417 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4418 array_lengthof(Ops));
4420 // 256-bit logic and arithmetic instructions in AVX are all
4421 // floating-point, no support for integer ops. Emit fp zeroed vectors.
4422 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
4423 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4424 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops,
4425 array_lengthof(Ops));
4428 llvm_unreachable("Unexpected vector type");
4430 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4433 /// getOnesVector - Returns a vector of specified type with all bits set.
4434 /// Always build ones vectors as <4 x i32> or <8 x i32>. For 256-bit types with
4435 /// no AVX2 supprt, use two <4 x i32> inserted in a <8 x i32> appropriately.
4436 /// Then bitcast to their original type, ensuring they get CSE'd.
4437 static SDValue getOnesVector(MVT VT, bool HasInt256, SelectionDAG &DAG,
4439 assert(VT.isVector() && "Expected a vector type");
4441 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
4443 if (VT.is256BitVector()) {
4444 if (HasInt256) { // AVX2
4445 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };
4446 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops,
4447 array_lengthof(Ops));
4449 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4450 Vec = Concat128BitVectors(Vec, Vec, MVT::v8i32, 8, DAG, dl);
4452 } else if (VT.is128BitVector()) {
4453 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
4455 llvm_unreachable("Unexpected vector type");
4457 return DAG.getNode(ISD::BITCAST, dl, VT, Vec);
4460 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements
4461 /// that point to V2 points to its first element.
4462 static void NormalizeMask(SmallVectorImpl<int> &Mask, unsigned NumElems) {
4463 for (unsigned i = 0; i != NumElems; ++i) {
4464 if (Mask[i] > (int)NumElems) {
4470 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd
4471 /// operation of specified width.
4472 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4474 unsigned NumElems = VT.getVectorNumElements();
4475 SmallVector<int, 8> Mask;
4476 Mask.push_back(NumElems);
4477 for (unsigned i = 1; i != NumElems; ++i)
4479 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4482 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation.
4483 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4485 unsigned NumElems = VT.getVectorNumElements();
4486 SmallVector<int, 8> Mask;
4487 for (unsigned i = 0, e = NumElems/2; i != e; ++i) {
4489 Mask.push_back(i + NumElems);
4491 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4494 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation.
4495 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
4497 unsigned NumElems = VT.getVectorNumElements();
4498 SmallVector<int, 8> Mask;
4499 for (unsigned i = 0, Half = NumElems/2; i != Half; ++i) {
4500 Mask.push_back(i + Half);
4501 Mask.push_back(i + NumElems + Half);
4503 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]);
4506 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by
4507 // a generic shuffle instruction because the target has no such instructions.
4508 // Generate shuffles which repeat i16 and i8 several times until they can be
4509 // represented by v4f32 and then be manipulated by target suported shuffles.
4510 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) {
4511 EVT VT = V.getValueType();
4512 int NumElems = VT.getVectorNumElements();
4513 DebugLoc dl = V.getDebugLoc();
4515 while (NumElems > 4) {
4516 if (EltNo < NumElems/2) {
4517 V = getUnpackl(DAG, dl, VT, V, V);
4519 V = getUnpackh(DAG, dl, VT, V, V);
4520 EltNo -= NumElems/2;
4527 /// getLegalSplat - Generate a legal splat with supported x86 shuffles
4528 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
4529 EVT VT = V.getValueType();
4530 DebugLoc dl = V.getDebugLoc();
4532 if (VT.is128BitVector()) {
4533 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V);
4534 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo };
4535 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32),
4537 } else if (VT.is256BitVector()) {
4538 // To use VPERMILPS to splat scalars, the second half of indicies must
4539 // refer to the higher part, which is a duplication of the lower one,
4540 // because VPERMILPS can only handle in-lane permutations.
4541 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo,
4542 EltNo+4, EltNo+4, EltNo+4, EltNo+4 };
4544 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V);
4545 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32),
4548 llvm_unreachable("Vector size not supported");
4550 return DAG.getNode(ISD::BITCAST, dl, VT, V);
4553 /// PromoteSplat - Splat is promoted to target supported vector shuffles.
4554 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
4555 EVT SrcVT = SV->getValueType(0);
4556 SDValue V1 = SV->getOperand(0);
4557 DebugLoc dl = SV->getDebugLoc();
4559 int EltNo = SV->getSplatIndex();
4560 int NumElems = SrcVT.getVectorNumElements();
4561 bool Is256BitVec = SrcVT.is256BitVector();
4563 assert(((SrcVT.is128BitVector() && NumElems > 4) || Is256BitVec) &&
4564 "Unknown how to promote splat for type");
4566 // Extract the 128-bit part containing the splat element and update
4567 // the splat element index when it refers to the higher register.
4569 V1 = Extract128BitVector(V1, EltNo, DAG, dl);
4570 if (EltNo >= NumElems/2)
4571 EltNo -= NumElems/2;
4574 // All i16 and i8 vector types can't be used directly by a generic shuffle
4575 // instruction because the target has no such instruction. Generate shuffles
4576 // which repeat i16 and i8 several times until they fit in i32, and then can
4577 // be manipulated by target suported shuffles.
4578 EVT EltVT = SrcVT.getVectorElementType();
4579 if (EltVT == MVT::i8 || EltVT == MVT::i16)
4580 V1 = PromoteSplati8i16(V1, DAG, EltNo);
4582 // Recreate the 256-bit vector and place the same 128-bit vector
4583 // into the low and high part. This is necessary because we want
4584 // to use VPERM* to shuffle the vectors
4586 V1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, SrcVT, V1, V1);
4589 return getLegalSplat(DAG, V1, EltNo);
4592 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
4593 /// vector of zero or undef vector. This produces a shuffle where the low
4594 /// element of V2 is swizzled into the zero/undef vector, landing at element
4595 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3).
4596 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
4598 const X86Subtarget *Subtarget,
4599 SelectionDAG &DAG) {
4600 EVT VT = V2.getValueType();
4602 ? getZeroVector(VT, Subtarget, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT);
4603 unsigned NumElems = VT.getVectorNumElements();
4604 SmallVector<int, 16> MaskVec;
4605 for (unsigned i = 0; i != NumElems; ++i)
4606 // If this is the insertion idx, put the low elt of V2 here.
4607 MaskVec.push_back(i == Idx ? NumElems : i);
4608 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]);
4611 /// getTargetShuffleMask - Calculates the shuffle mask corresponding to the
4612 /// target specific opcode. Returns true if the Mask could be calculated.
4613 /// Sets IsUnary to true if only uses one source.
4614 static bool getTargetShuffleMask(SDNode *N, MVT VT,
4615 SmallVectorImpl<int> &Mask, bool &IsUnary) {
4616 unsigned NumElems = VT.getVectorNumElements();
4620 switch(N->getOpcode()) {
4622 ImmN = N->getOperand(N->getNumOperands()-1);
4623 DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4625 case X86ISD::UNPCKH:
4626 DecodeUNPCKHMask(VT, Mask);
4628 case X86ISD::UNPCKL:
4629 DecodeUNPCKLMask(VT, Mask);
4631 case X86ISD::MOVHLPS:
4632 DecodeMOVHLPSMask(NumElems, Mask);
4634 case X86ISD::MOVLHPS:
4635 DecodeMOVLHPSMask(NumElems, Mask);
4637 case X86ISD::PALIGNR:
4638 ImmN = N->getOperand(N->getNumOperands()-1);
4639 DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4641 case X86ISD::PSHUFD:
4642 case X86ISD::VPERMILP:
4643 ImmN = N->getOperand(N->getNumOperands()-1);
4644 DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4647 case X86ISD::PSHUFHW:
4648 ImmN = N->getOperand(N->getNumOperands()-1);
4649 DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4652 case X86ISD::PSHUFLW:
4653 ImmN = N->getOperand(N->getNumOperands()-1);
4654 DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4657 case X86ISD::VPERMI:
4658 ImmN = N->getOperand(N->getNumOperands()-1);
4659 DecodeVPERMMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4663 case X86ISD::MOVSD: {
4664 // The index 0 always comes from the first element of the second source,
4665 // this is why MOVSS and MOVSD are used in the first place. The other
4666 // elements come from the other positions of the first source vector
4667 Mask.push_back(NumElems);
4668 for (unsigned i = 1; i != NumElems; ++i) {
4673 case X86ISD::VPERM2X128:
4674 ImmN = N->getOperand(N->getNumOperands()-1);
4675 DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
4676 if (Mask.empty()) return false;
4678 case X86ISD::MOVDDUP:
4679 case X86ISD::MOVLHPD:
4680 case X86ISD::MOVLPD:
4681 case X86ISD::MOVLPS:
4682 case X86ISD::MOVSHDUP:
4683 case X86ISD::MOVSLDUP:
4684 // Not yet implemented
4686 default: llvm_unreachable("unknown target shuffle node");
4692 /// getShuffleScalarElt - Returns the scalar element that will make up the ith
4693 /// element of the result of the vector shuffle.
4694 static SDValue getShuffleScalarElt(SDNode *N, unsigned Index, SelectionDAG &DAG,
4697 return SDValue(); // Limit search depth.
4699 SDValue V = SDValue(N, 0);
4700 EVT VT = V.getValueType();
4701 unsigned Opcode = V.getOpcode();
4703 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars.
4704 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) {
4705 int Elt = SV->getMaskElt(Index);
4708 return DAG.getUNDEF(VT.getVectorElementType());
4710 unsigned NumElems = VT.getVectorNumElements();
4711 SDValue NewV = (Elt < (int)NumElems) ? SV->getOperand(0)
4712 : SV->getOperand(1);
4713 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG, Depth+1);
4716 // Recurse into target specific vector shuffles to find scalars.
4717 if (isTargetShuffle(Opcode)) {
4718 MVT ShufVT = V.getValueType().getSimpleVT();
4719 unsigned NumElems = ShufVT.getVectorNumElements();
4720 SmallVector<int, 16> ShuffleMask;
4723 if (!getTargetShuffleMask(N, ShufVT, ShuffleMask, IsUnary))
4726 int Elt = ShuffleMask[Index];
4728 return DAG.getUNDEF(ShufVT.getVectorElementType());
4730 SDValue NewV = (Elt < (int)NumElems) ? N->getOperand(0)
4732 return getShuffleScalarElt(NewV.getNode(), Elt % NumElems, DAG,
4736 // Actual nodes that may contain scalar elements
4737 if (Opcode == ISD::BITCAST) {
4738 V = V.getOperand(0);
4739 EVT SrcVT = V.getValueType();
4740 unsigned NumElems = VT.getVectorNumElements();
4742 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems)
4746 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR)
4747 return (Index == 0) ? V.getOperand(0)
4748 : DAG.getUNDEF(VT.getVectorElementType());
4750 if (V.getOpcode() == ISD::BUILD_VECTOR)
4751 return V.getOperand(Index);
4756 /// getNumOfConsecutiveZeros - Return the number of elements of a vector
4757 /// shuffle operation which come from a consecutively from a zero. The
4758 /// search can start in two different directions, from left or right.
4759 /// We count undefs as zeros until PreferredNum is reached.
4760 static unsigned getNumOfConsecutiveZeros(ShuffleVectorSDNode *SVOp,
4761 unsigned NumElems, bool ZerosFromLeft,
4763 unsigned PreferredNum = -1U) {
4764 unsigned NumZeros = 0;
4765 for (unsigned i = 0; i != NumElems; ++i) {
4766 unsigned Index = ZerosFromLeft ? i : NumElems - i - 1;
4767 SDValue Elt = getShuffleScalarElt(SVOp, Index, DAG, 0);
4771 if (X86::isZeroNode(Elt))
4773 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
4774 NumZeros = std::min(NumZeros + 1, PreferredNum);
4782 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies [MaskI, MaskE)
4783 /// correspond consecutively to elements from one of the vector operands,
4784 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4786 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp,
4787 unsigned MaskI, unsigned MaskE, unsigned OpIdx,
4788 unsigned NumElems, unsigned &OpNum) {
4789 bool SeenV1 = false;
4790 bool SeenV2 = false;
4792 for (unsigned i = MaskI; i != MaskE; ++i, ++OpIdx) {
4793 int Idx = SVOp->getMaskElt(i);
4794 // Ignore undef indicies
4798 if (Idx < (int)NumElems)
4803 // Only accept consecutive elements from the same vector
4804 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4808 OpNum = SeenV1 ? 0 : 1;
4812 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a
4813 /// logical left shift of a vector.
4814 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4815 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4816 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4817 unsigned NumZeros = getNumOfConsecutiveZeros(
4818 SVOp, NumElems, false /* check zeros from right */, DAG,
4819 SVOp->getMaskElt(0));
4825 // Considering the elements in the mask that are not consecutive zeros,
4826 // check if they consecutively come from only one of the source vectors.
4828 // V1 = {X, A, B, C} 0
4830 // vector_shuffle V1, V2 <1, 2, 3, X>
4832 if (!isShuffleMaskConsecutive(SVOp,
4833 0, // Mask Start Index
4834 NumElems-NumZeros, // Mask End Index(exclusive)
4835 NumZeros, // Where to start looking in the src vector
4836 NumElems, // Number of elements in vector
4837 OpSrc)) // Which source operand ?
4842 ShVal = SVOp->getOperand(OpSrc);
4846 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a
4847 /// logical left shift of a vector.
4848 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4849 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4850 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements();
4851 unsigned NumZeros = getNumOfConsecutiveZeros(
4852 SVOp, NumElems, true /* check zeros from left */, DAG,
4853 NumElems - SVOp->getMaskElt(NumElems - 1) - 1);
4859 // Considering the elements in the mask that are not consecutive zeros,
4860 // check if they consecutively come from only one of the source vectors.
4862 // 0 { A, B, X, X } = V2
4864 // vector_shuffle V1, V2 <X, X, 4, 5>
4866 if (!isShuffleMaskConsecutive(SVOp,
4867 NumZeros, // Mask Start Index
4868 NumElems, // Mask End Index(exclusive)
4869 0, // Where to start looking in the src vector
4870 NumElems, // Number of elements in vector
4871 OpSrc)) // Which source operand ?
4876 ShVal = SVOp->getOperand(OpSrc);
4880 /// isVectorShift - Returns true if the shuffle can be implemented as a
4881 /// logical left or right shift of a vector.
4882 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG,
4883 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) {
4884 // Although the logic below support any bitwidth size, there are no
4885 // shift instructions which handle more than 128-bit vectors.
4886 if (!SVOp->getValueType(0).is128BitVector())
4889 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) ||
4890 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt))
4896 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8.
4898 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros,
4899 unsigned NumNonZero, unsigned NumZero,
4901 const X86Subtarget* Subtarget,
4902 const TargetLowering &TLI) {
4906 DebugLoc dl = Op.getDebugLoc();
4909 for (unsigned i = 0; i < 16; ++i) {
4910 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0;
4911 if (ThisIsNonZero && First) {
4913 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4915 V = DAG.getUNDEF(MVT::v8i16);
4920 SDValue ThisElt(0, 0), LastElt(0, 0);
4921 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0;
4922 if (LastIsNonZero) {
4923 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl,
4924 MVT::i16, Op.getOperand(i-1));
4926 if (ThisIsNonZero) {
4927 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));
4928 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,
4929 ThisElt, DAG.getConstant(8, MVT::i8));
4931 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);
4935 if (ThisElt.getNode())
4936 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,
4937 DAG.getIntPtrConstant(i/2));
4941 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V);
4944 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16.
4946 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros,
4947 unsigned NumNonZero, unsigned NumZero,
4949 const X86Subtarget* Subtarget,
4950 const TargetLowering &TLI) {
4954 DebugLoc dl = Op.getDebugLoc();
4957 for (unsigned i = 0; i < 8; ++i) {
4958 bool isNonZero = (NonZeros & (1 << i)) != 0;
4962 V = getZeroVector(MVT::v8i16, Subtarget, DAG, dl);
4964 V = DAG.getUNDEF(MVT::v8i16);
4967 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,
4968 MVT::v8i16, V, Op.getOperand(i),
4969 DAG.getIntPtrConstant(i));
4976 /// getVShift - Return a vector logical shift node.
4978 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
4979 unsigned NumBits, SelectionDAG &DAG,
4980 const TargetLowering &TLI, DebugLoc dl) {
4981 assert(VT.is128BitVector() && "Unknown type for VShift");
4982 EVT ShVT = MVT::v2i64;
4983 unsigned Opc = isLeft ? X86ISD::VSHLDQ : X86ISD::VSRLDQ;
4984 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);
4985 return DAG.getNode(ISD::BITCAST, dl, VT,
4986 DAG.getNode(Opc, dl, ShVT, SrcOp,
4987 DAG.getConstant(NumBits,
4988 TLI.getScalarShiftAmountTy(SrcOp.getValueType()))));
4992 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
4993 SelectionDAG &DAG) const {
4995 // Check if the scalar load can be widened into a vector load. And if
4996 // the address is "base + cst" see if the cst can be "absorbed" into
4997 // the shuffle mask.
4998 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) {
4999 SDValue Ptr = LD->getBasePtr();
5000 if (!ISD::isNormalLoad(LD) || LD->isVolatile())
5002 EVT PVT = LD->getValueType(0);
5003 if (PVT != MVT::i32 && PVT != MVT::f32)
5008 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) {
5009 FI = FINode->getIndex();
5011 } else if (DAG.isBaseWithConstantOffset(Ptr) &&
5012 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
5013 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
5014 Offset = Ptr.getConstantOperandVal(1);
5015 Ptr = Ptr.getOperand(0);
5020 // FIXME: 256-bit vector instructions don't require a strict alignment,
5021 // improve this code to support it better.
5022 unsigned RequiredAlign = VT.getSizeInBits()/8;
5023 SDValue Chain = LD->getChain();
5024 // Make sure the stack object alignment is at least 16 or 32.
5025 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
5026 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) {
5027 if (MFI->isFixedObjectIndex(FI)) {
5028 // Can't change the alignment. FIXME: It's possible to compute
5029 // the exact stack offset and reference FI + adjust offset instead.
5030 // If someone *really* cares about this. That's the way to implement it.
5033 MFI->setObjectAlignment(FI, RequiredAlign);
5037 // (Offset % 16 or 32) must be multiple of 4. Then address is then
5038 // Ptr + (Offset & ~15).
5041 if ((Offset % RequiredAlign) & 3)
5043 int64_t StartOffset = Offset & ~(RequiredAlign-1);
5045 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(),
5046 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));
5048 int EltNo = (Offset - StartOffset) >> 2;
5049 unsigned NumElems = VT.getVectorNumElements();
5051 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems);
5052 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr,
5053 LD->getPointerInfo().getWithOffset(StartOffset),
5054 false, false, false, 0);
5056 SmallVector<int, 8> Mask;
5057 for (unsigned i = 0; i != NumElems; ++i)
5058 Mask.push_back(EltNo);
5060 return DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &Mask[0]);
5066 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
5067 /// vector of type 'VT', see if the elements can be replaced by a single large
5068 /// load which has the same value as a build_vector whose operands are 'elts'.
5070 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
5072 /// FIXME: we'd also like to handle the case where the last elements are zero
5073 /// rather than undef via VZEXT_LOAD, but we do not detect that case today.
5074 /// There's even a handy isZeroNode for that purpose.
5075 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
5076 DebugLoc &DL, SelectionDAG &DAG) {
5077 EVT EltVT = VT.getVectorElementType();
5078 unsigned NumElems = Elts.size();
5080 LoadSDNode *LDBase = NULL;
5081 unsigned LastLoadedElt = -1U;
5083 // For each element in the initializer, see if we've found a load or an undef.
5084 // If we don't find an initial load element, or later load elements are
5085 // non-consecutive, bail out.
5086 for (unsigned i = 0; i < NumElems; ++i) {
5087 SDValue Elt = Elts[i];
5089 if (!Elt.getNode() ||
5090 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
5093 if (Elt.getNode()->getOpcode() == ISD::UNDEF)
5095 LDBase = cast<LoadSDNode>(Elt.getNode());
5099 if (Elt.getOpcode() == ISD::UNDEF)
5102 LoadSDNode *LD = cast<LoadSDNode>(Elt);
5103 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i))
5108 // If we have found an entire vector of loads and undefs, then return a large
5109 // load of the entire vector width starting at the base pointer. If we found
5110 // consecutive loads for the low half, generate a vzext_load node.
5111 if (LastLoadedElt == NumElems - 1) {
5112 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16)
5113 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5114 LDBase->getPointerInfo(),
5115 LDBase->isVolatile(), LDBase->isNonTemporal(),
5116 LDBase->isInvariant(), 0);
5117 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
5118 LDBase->getPointerInfo(),
5119 LDBase->isVolatile(), LDBase->isNonTemporal(),
5120 LDBase->isInvariant(), LDBase->getAlignment());
5122 if (NumElems == 4 && LastLoadedElt == 1 &&
5123 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) {
5124 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other);
5125 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() };
5127 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops,
5128 array_lengthof(Ops), MVT::i64,
5129 LDBase->getPointerInfo(),
5130 LDBase->getAlignment(),
5131 false/*isVolatile*/, true/*ReadMem*/,
5134 // Make sure the newly-created LOAD is in the same position as LDBase in
5135 // terms of dependency. We create a TokenFactor for LDBase and ResNode, and
5136 // update uses of LDBase's output chain to use the TokenFactor.
5137 if (LDBase->hasAnyUseOfValue(1)) {
5138 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
5139 SDValue(LDBase, 1), SDValue(ResNode.getNode(), 1));
5140 DAG.ReplaceAllUsesOfValueWith(SDValue(LDBase, 1), NewChain);
5141 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(LDBase, 1),
5142 SDValue(ResNode.getNode(), 1));
5145 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode);
5150 /// LowerVectorBroadcast - Attempt to use the vbroadcast instruction
5151 /// to generate a splat value for the following cases:
5152 /// 1. A splat BUILD_VECTOR which uses a single scalar load, or a constant.
5153 /// 2. A splat shuffle which uses a scalar_to_vector node which comes from
5154 /// a scalar load, or a constant.
5155 /// The VBROADCAST node is returned when a pattern is found,
5156 /// or SDValue() otherwise.
5158 X86TargetLowering::LowerVectorBroadcast(SDValue Op, SelectionDAG &DAG) const {
5159 if (!Subtarget->hasFp256())
5162 MVT VT = Op.getValueType().getSimpleVT();
5163 DebugLoc dl = Op.getDebugLoc();
5165 assert((VT.is128BitVector() || VT.is256BitVector()) &&
5166 "Unsupported vector type for broadcast.");
5171 switch (Op.getOpcode()) {
5173 // Unknown pattern found.
5176 case ISD::BUILD_VECTOR: {
5177 // The BUILD_VECTOR node must be a splat.
5178 if (!isSplatVector(Op.getNode()))
5181 Ld = Op.getOperand(0);
5182 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5183 Ld.getOpcode() == ISD::ConstantFP);
5185 // The suspected load node has several users. Make sure that all
5186 // of its users are from the BUILD_VECTOR node.
5187 // Constants may have multiple users.
5188 if (!ConstSplatVal && !Ld->hasNUsesOfValue(VT.getVectorNumElements(), 0))
5193 case ISD::VECTOR_SHUFFLE: {
5194 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5196 // Shuffles must have a splat mask where the first element is
5198 if ((!SVOp->isSplat()) || SVOp->getMaskElt(0) != 0)
5201 SDValue Sc = Op.getOperand(0);
5202 if (Sc.getOpcode() != ISD::SCALAR_TO_VECTOR &&
5203 Sc.getOpcode() != ISD::BUILD_VECTOR) {
5205 if (!Subtarget->hasInt256())
5208 // Use the register form of the broadcast instruction available on AVX2.
5209 if (VT.is256BitVector())
5210 Sc = Extract128BitVector(Sc, 0, DAG, dl);
5211 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Sc);
5214 Ld = Sc.getOperand(0);
5215 ConstSplatVal = (Ld.getOpcode() == ISD::Constant ||
5216 Ld.getOpcode() == ISD::ConstantFP);
5218 // The scalar_to_vector node and the suspected
5219 // load node must have exactly one user.
5220 // Constants may have multiple users.
5221 if (!ConstSplatVal && (!Sc.hasOneUse() || !Ld.hasOneUse()))
5227 bool Is256 = VT.is256BitVector();
5229 // Handle the broadcasting a single constant scalar from the constant pool
5230 // into a vector. On Sandybridge it is still better to load a constant vector
5231 // from the constant pool and not to broadcast it from a scalar.
5232 if (ConstSplatVal && Subtarget->hasInt256()) {
5233 EVT CVT = Ld.getValueType();
5234 assert(!CVT.isVector() && "Must not broadcast a vector type");
5235 unsigned ScalarSize = CVT.getSizeInBits();
5237 if (ScalarSize == 32 || (Is256 && ScalarSize == 64)) {
5238 const Constant *C = 0;
5239 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
5240 C = CI->getConstantIntValue();
5241 else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
5242 C = CF->getConstantFPValue();
5244 assert(C && "Invalid constant type");
5246 SDValue CP = DAG.getConstantPool(C, getPointerTy());
5247 unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();
5248 Ld = DAG.getLoad(CVT, dl, DAG.getEntryNode(), CP,
5249 MachinePointerInfo::getConstantPool(),
5250 false, false, false, Alignment);
5252 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5256 bool IsLoad = ISD::isNormalLoad(Ld.getNode());
5257 unsigned ScalarSize = Ld.getValueType().getSizeInBits();
5259 // Handle AVX2 in-register broadcasts.
5260 if (!IsLoad && Subtarget->hasInt256() &&
5261 (ScalarSize == 32 || (Is256 && ScalarSize == 64)))
5262 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5264 // The scalar source must be a normal load.
5268 if (ScalarSize == 32 || (Is256 && ScalarSize == 64))
5269 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5271 // The integer check is needed for the 64-bit into 128-bit so it doesn't match
5272 // double since there is no vbroadcastsd xmm
5273 if (Subtarget->hasInt256() && Ld.getValueType().isInteger()) {
5274 if (ScalarSize == 8 || ScalarSize == 16 || ScalarSize == 64)
5275 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, Ld);
5278 // Unsupported broadcast.
5283 X86TargetLowering::buildFromShuffleMostly(SDValue Op, SelectionDAG &DAG) const {
5284 EVT VT = Op.getValueType();
5286 // Skip if insert_vec_elt is not supported.
5287 if (!isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT))
5290 DebugLoc DL = Op.getDebugLoc();
5291 unsigned NumElems = Op.getNumOperands();
5295 SmallVector<unsigned, 4> InsertIndices;
5296 SmallVector<int, 8> Mask(NumElems, -1);
5298 for (unsigned i = 0; i != NumElems; ++i) {
5299 unsigned Opc = Op.getOperand(i).getOpcode();
5301 if (Opc == ISD::UNDEF)
5304 if (Opc != ISD::EXTRACT_VECTOR_ELT) {
5305 // Quit if more than 1 elements need inserting.
5306 if (InsertIndices.size() > 1)
5309 InsertIndices.push_back(i);
5313 SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
5314 SDValue ExtIdx = Op.getOperand(i).getOperand(1);
5316 // Quit if extracted from vector of different type.
5317 if (ExtractedFromVec.getValueType() != VT)
5320 // Quit if non-constant index.
5321 if (!isa<ConstantSDNode>(ExtIdx))
5324 if (VecIn1.getNode() == 0)
5325 VecIn1 = ExtractedFromVec;
5326 else if (VecIn1 != ExtractedFromVec) {
5327 if (VecIn2.getNode() == 0)
5328 VecIn2 = ExtractedFromVec;
5329 else if (VecIn2 != ExtractedFromVec)
5330 // Quit if more than 2 vectors to shuffle
5334 unsigned Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
5336 if (ExtractedFromVec == VecIn1)
5338 else if (ExtractedFromVec == VecIn2)
5339 Mask[i] = Idx + NumElems;
5342 if (VecIn1.getNode() == 0)
5345 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5346 SDValue NV = DAG.getVectorShuffle(VT, DL, VecIn1, VecIn2, &Mask[0]);
5347 for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {
5348 unsigned Idx = InsertIndices[i];
5349 NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),
5350 DAG.getIntPtrConstant(Idx));
5357 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
5358 DebugLoc dl = Op.getDebugLoc();
5360 MVT VT = Op.getValueType().getSimpleVT();
5361 MVT ExtVT = VT.getVectorElementType();
5362 unsigned NumElems = Op.getNumOperands();
5364 // Vectors containing all zeros can be matched by pxor and xorps later
5365 if (ISD::isBuildVectorAllZeros(Op.getNode())) {
5366 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd
5367 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts.
5368 if (VT == MVT::v4i32 || VT == MVT::v8i32)
5371 return getZeroVector(VT, Subtarget, DAG, dl);
5374 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width
5375 // vectors or broken into v4i32 operations on 256-bit vectors. AVX2 can use
5376 // vpcmpeqd on 256-bit vectors.
5377 if (Subtarget->hasSSE2() && ISD::isBuildVectorAllOnes(Op.getNode())) {
5378 if (VT == MVT::v4i32 || (VT == MVT::v8i32 && Subtarget->hasInt256()))
5381 return getOnesVector(VT, Subtarget->hasInt256(), DAG, dl);
5384 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
5385 if (Broadcast.getNode())
5388 unsigned EVTBits = ExtVT.getSizeInBits();
5390 unsigned NumZero = 0;
5391 unsigned NumNonZero = 0;
5392 unsigned NonZeros = 0;
5393 bool IsAllConstants = true;
5394 SmallSet<SDValue, 8> Values;
5395 for (unsigned i = 0; i < NumElems; ++i) {
5396 SDValue Elt = Op.getOperand(i);
5397 if (Elt.getOpcode() == ISD::UNDEF)
5400 if (Elt.getOpcode() != ISD::Constant &&
5401 Elt.getOpcode() != ISD::ConstantFP)
5402 IsAllConstants = false;
5403 if (X86::isZeroNode(Elt))
5406 NonZeros |= (1 << i);
5411 // All undef vector. Return an UNDEF. All zero vectors were handled above.
5412 if (NumNonZero == 0)
5413 return DAG.getUNDEF(VT);
5415 // Special case for single non-zero, non-undef, element.
5416 if (NumNonZero == 1) {
5417 unsigned Idx = CountTrailingZeros_32(NonZeros);
5418 SDValue Item = Op.getOperand(Idx);
5420 // If this is an insertion of an i64 value on x86-32, and if the top bits of
5421 // the value are obviously zero, truncate the value to i32 and do the
5422 // insertion that way. Only do this if the value is non-constant or if the
5423 // value is a constant being inserted into element 0. It is cheaper to do
5424 // a constant pool load than it is to do a movd + shuffle.
5425 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() &&
5426 (!IsAllConstants || Idx == 0)) {
5427 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) {
5429 assert(VT == MVT::v2i64 && "Expected an SSE value type!");
5430 EVT VecVT = MVT::v4i32;
5431 unsigned VecElts = 4;
5433 // Truncate the value (which may itself be a constant) to i32, and
5434 // convert it to a vector with movd (S2V+shuffle to zero extend).
5435 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item);
5436 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item);
5437 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5439 // Now we have our 32-bit value zero extended in the low element of
5440 // a vector. If Idx != 0, swizzle it into place.
5442 SmallVector<int, 4> Mask;
5443 Mask.push_back(Idx);
5444 for (unsigned i = 1; i != VecElts; ++i)
5446 Item = DAG.getVectorShuffle(VecVT, dl, Item, DAG.getUNDEF(VecVT),
5449 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5453 // If we have a constant or non-constant insertion into the low element of
5454 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into
5455 // the rest of the elements. This will be matched as movd/movq/movss/movsd
5456 // depending on what the source datatype is.
5459 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5461 if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 ||
5462 (ExtVT == MVT::i64 && Subtarget->is64Bit())) {
5463 if (VT.is256BitVector()) {
5464 SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);
5465 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,
5466 Item, DAG.getIntPtrConstant(0));
5468 assert(VT.is128BitVector() && "Expected an SSE value type!");
5469 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5470 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
5471 return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5474 if (ExtVT == MVT::i16 || ExtVT == MVT::i8) {
5475 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item);
5476 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, Item);
5477 if (VT.is256BitVector()) {
5478 SDValue ZeroVec = getZeroVector(MVT::v8i32, Subtarget, DAG, dl);
5479 Item = Insert128BitVector(ZeroVec, Item, 0, DAG, dl);
5481 assert(VT.is128BitVector() && "Expected an SSE value type!");
5482 Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget, DAG);
5484 return DAG.getNode(ISD::BITCAST, dl, VT, Item);
5488 // Is it a vector logical left shift?
5489 if (NumElems == 2 && Idx == 1 &&
5490 X86::isZeroNode(Op.getOperand(0)) &&
5491 !X86::isZeroNode(Op.getOperand(1))) {
5492 unsigned NumBits = VT.getSizeInBits();
5493 return getVShift(true, VT,
5494 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5495 VT, Op.getOperand(1)),
5496 NumBits/2, DAG, *this, dl);
5499 if (IsAllConstants) // Otherwise, it's better to do a constpool load.
5502 // Otherwise, if this is a vector with i32 or f32 elements, and the element
5503 // is a non-constant being inserted into an element other than the low one,
5504 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka
5505 // movd/movss) to move this into the low element, then shuffle it into
5507 if (EVTBits == 32) {
5508 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item);
5510 // Turn it into a shuffle of zero and zero-extended scalar to vector.
5511 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, Subtarget, DAG);
5512 SmallVector<int, 8> MaskVec;
5513 for (unsigned i = 0; i != NumElems; ++i)
5514 MaskVec.push_back(i == Idx ? 0 : 1);
5515 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]);
5519 // Splat is obviously ok. Let legalizer expand it to a shuffle.
5520 if (Values.size() == 1) {
5521 if (EVTBits == 32) {
5522 // Instead of a shuffle like this:
5523 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
5524 // Check if it's possible to issue this instead.
5525 // shuffle (vload ptr)), undef, <1, 1, 1, 1>
5526 unsigned Idx = CountTrailingZeros_32(NonZeros);
5527 SDValue Item = Op.getOperand(Idx);
5528 if (Op.getNode()->isOnlyUserOf(Item.getNode()))
5529 return LowerAsSplatVectorLoad(Item, VT, dl, DAG);
5534 // A vector full of immediates; various special cases are already
5535 // handled, so this is best done with a single constant-pool load.
5539 // For AVX-length vectors, build the individual 128-bit pieces and use
5540 // shuffles to put them in place.
5541 if (VT.is256BitVector()) {
5542 SmallVector<SDValue, 32> V;
5543 for (unsigned i = 0; i != NumElems; ++i)
5544 V.push_back(Op.getOperand(i));
5546 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2);
5548 // Build both the lower and upper subvector.
5549 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2);
5550 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2],
5553 // Recreate the wider vector with the lower and upper part.
5554 return Concat128BitVectors(Lower, Upper, VT, NumElems, DAG, dl);
5557 // Let legalizer expand 2-wide build_vectors.
5558 if (EVTBits == 64) {
5559 if (NumNonZero == 1) {
5560 // One half is zero or undef.
5561 unsigned Idx = CountTrailingZeros_32(NonZeros);
5562 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT,
5563 Op.getOperand(Idx));
5564 return getShuffleVectorZeroOrUndef(V2, Idx, true, Subtarget, DAG);
5569 // If element VT is < 32 bits, convert it to inserts into a zero vector.
5570 if (EVTBits == 8 && NumElems == 16) {
5571 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG,
5573 if (V.getNode()) return V;
5576 if (EVTBits == 16 && NumElems == 8) {
5577 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG,
5579 if (V.getNode()) return V;
5582 // If element VT is == 32 bits, turn it into a number of shuffles.
5583 SmallVector<SDValue, 8> V(NumElems);
5584 if (NumElems == 4 && NumZero > 0) {
5585 for (unsigned i = 0; i < 4; ++i) {
5586 bool isZero = !(NonZeros & (1 << i));
5588 V[i] = getZeroVector(VT, Subtarget, DAG, dl);
5590 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5593 for (unsigned i = 0; i < 2; ++i) {
5594 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) {
5597 V[i] = V[i*2]; // Must be a zero vector.
5600 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]);
5603 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]);
5606 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]);
5611 bool Reverse1 = (NonZeros & 0x3) == 2;
5612 bool Reverse2 = ((NonZeros & (0x3 << 2)) >> 2) == 2;
5616 static_cast<int>(Reverse2 ? NumElems+1 : NumElems),
5617 static_cast<int>(Reverse2 ? NumElems : NumElems+1)
5619 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]);
5622 if (Values.size() > 1 && VT.is128BitVector()) {
5623 // Check for a build vector of consecutive loads.
5624 for (unsigned i = 0; i < NumElems; ++i)
5625 V[i] = Op.getOperand(i);
5627 // Check for elements which are consecutive loads.
5628 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
5632 // Check for a build vector from mostly shuffle plus few inserting.
5633 SDValue Sh = buildFromShuffleMostly(Op, DAG);
5637 // For SSE 4.1, use insertps to put the high elements into the low element.
5638 if (getSubtarget()->hasSSE41()) {
5640 if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
5641 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
5643 Result = DAG.getUNDEF(VT);
5645 for (unsigned i = 1; i < NumElems; ++i) {
5646 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
5647 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
5648 Op.getOperand(i), DAG.getIntPtrConstant(i));
5653 // Otherwise, expand into a number of unpckl*, start by extending each of
5654 // our (non-undef) elements to the full vector width with the element in the
5655 // bottom slot of the vector (which generates no code for SSE).
5656 for (unsigned i = 0; i < NumElems; ++i) {
5657 if (Op.getOperand(i).getOpcode() != ISD::UNDEF)
5658 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i));
5660 V[i] = DAG.getUNDEF(VT);
5663 // Next, we iteratively mix elements, e.g. for v4f32:
5664 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0>
5665 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1>
5666 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0>
5667 unsigned EltStride = NumElems >> 1;
5668 while (EltStride != 0) {
5669 for (unsigned i = 0; i < EltStride; ++i) {
5670 // If V[i+EltStride] is undef and this is the first round of mixing,
5671 // then it is safe to just drop this shuffle: V[i] is already in the
5672 // right place, the one element (since it's the first round) being
5673 // inserted as undef can be dropped. This isn't safe for successive
5674 // rounds because they will permute elements within both vectors.
5675 if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
5676 EltStride == NumElems/2)
5679 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
5688 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction
5689 // to create 256-bit vectors from two other 128-bit ones.
5690 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5691 DebugLoc dl = Op.getDebugLoc();
5692 MVT ResVT = Op.getValueType().getSimpleVT();
5694 assert(ResVT.is256BitVector() && "Value type must be 256-bit wide");
5696 SDValue V1 = Op.getOperand(0);
5697 SDValue V2 = Op.getOperand(1);
5698 unsigned NumElems = ResVT.getVectorNumElements();
5700 return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);
5703 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5704 assert(Op.getNumOperands() == 2);
5706 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors
5707 // from two other 128-bit ones.
5708 return LowerAVXCONCAT_VECTORS(Op, DAG);
5711 // Try to lower a shuffle node into a simple blend instruction.
5713 LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
5714 const X86Subtarget *Subtarget, SelectionDAG &DAG) {
5715 SDValue V1 = SVOp->getOperand(0);
5716 SDValue V2 = SVOp->getOperand(1);
5717 DebugLoc dl = SVOp->getDebugLoc();
5718 MVT VT = SVOp->getValueType(0).getSimpleVT();
5719 MVT EltVT = VT.getVectorElementType();
5720 unsigned NumElems = VT.getVectorNumElements();
5722 if (!Subtarget->hasSSE41() || EltVT == MVT::i8)
5724 if (!Subtarget->hasInt256() && VT == MVT::v16i16)
5727 // Check the mask for BLEND and build the value.
5728 unsigned MaskValue = 0;
5729 // There are 2 lanes if (NumElems > 8), and 1 lane otherwise.
5730 unsigned NumLanes = (NumElems-1)/8 + 1;
5731 unsigned NumElemsInLane = NumElems / NumLanes;
5733 // Blend for v16i16 should be symetric for the both lanes.
5734 for (unsigned i = 0; i < NumElemsInLane; ++i) {
5736 int SndLaneEltIdx = (NumLanes == 2) ?
5737 SVOp->getMaskElt(i + NumElemsInLane) : -1;
5738 int EltIdx = SVOp->getMaskElt(i);
5740 if ((EltIdx < 0 || EltIdx == (int)i) &&
5741 (SndLaneEltIdx < 0 || SndLaneEltIdx == (int)(i + NumElemsInLane)))
5744 if (((unsigned)EltIdx == (i + NumElems)) &&
5745 (SndLaneEltIdx < 0 ||
5746 (unsigned)SndLaneEltIdx == i + NumElems + NumElemsInLane))
5747 MaskValue |= (1<<i);
5752 // Convert i32 vectors to floating point if it is not AVX2.
5753 // AVX2 introduced VPBLENDD instruction for 128 and 256-bit vectors.
5755 if (EltVT == MVT::i64 || (EltVT == MVT::i32 && !Subtarget->hasInt256())) {
5756 BlendVT = MVT::getVectorVT(MVT::getFloatingPointVT(EltVT.getSizeInBits()),
5758 V1 = DAG.getNode(ISD::BITCAST, dl, VT, V1);
5759 V2 = DAG.getNode(ISD::BITCAST, dl, VT, V2);
5762 SDValue Ret = DAG.getNode(X86ISD::BLENDI, dl, BlendVT, V1, V2,
5763 DAG.getConstant(MaskValue, MVT::i32));
5764 return DAG.getNode(ISD::BITCAST, dl, VT, Ret);
5767 // v8i16 shuffles - Prefer shuffles in the following order:
5768 // 1. [all] pshuflw, pshufhw, optional move
5769 // 2. [ssse3] 1 x pshufb
5770 // 3. [ssse3] 2 x pshufb + 1 x por
5771 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw)
5773 LowerVECTOR_SHUFFLEv8i16(SDValue Op, const X86Subtarget *Subtarget,
5774 SelectionDAG &DAG) {
5775 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5776 SDValue V1 = SVOp->getOperand(0);
5777 SDValue V2 = SVOp->getOperand(1);
5778 DebugLoc dl = SVOp->getDebugLoc();
5779 SmallVector<int, 8> MaskVals;
5781 // Determine if more than 1 of the words in each of the low and high quadwords
5782 // of the result come from the same quadword of one of the two inputs. Undef
5783 // mask values count as coming from any quadword, for better codegen.
5784 unsigned LoQuad[] = { 0, 0, 0, 0 };
5785 unsigned HiQuad[] = { 0, 0, 0, 0 };
5786 std::bitset<4> InputQuads;
5787 for (unsigned i = 0; i < 8; ++i) {
5788 unsigned *Quad = i < 4 ? LoQuad : HiQuad;
5789 int EltIdx = SVOp->getMaskElt(i);
5790 MaskVals.push_back(EltIdx);
5799 InputQuads.set(EltIdx / 4);
5802 int BestLoQuad = -1;
5803 unsigned MaxQuad = 1;
5804 for (unsigned i = 0; i < 4; ++i) {
5805 if (LoQuad[i] > MaxQuad) {
5807 MaxQuad = LoQuad[i];
5811 int BestHiQuad = -1;
5813 for (unsigned i = 0; i < 4; ++i) {
5814 if (HiQuad[i] > MaxQuad) {
5816 MaxQuad = HiQuad[i];
5820 // For SSSE3, If all 8 words of the result come from only 1 quadword of each
5821 // of the two input vectors, shuffle them into one input vector so only a
5822 // single pshufb instruction is necessary. If There are more than 2 input
5823 // quads, disable the next transformation since it does not help SSSE3.
5824 bool V1Used = InputQuads[0] || InputQuads[1];
5825 bool V2Used = InputQuads[2] || InputQuads[3];
5826 if (Subtarget->hasSSSE3()) {
5827 if (InputQuads.count() == 2 && V1Used && V2Used) {
5828 BestLoQuad = InputQuads[0] ? 0 : 1;
5829 BestHiQuad = InputQuads[2] ? 2 : 3;
5831 if (InputQuads.count() > 2) {
5837 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update
5838 // the shuffle mask. If a quad is scored as -1, that means that it contains
5839 // words from all 4 input quadwords.
5841 if (BestLoQuad >= 0 || BestHiQuad >= 0) {
5843 BestLoQuad < 0 ? 0 : BestLoQuad,
5844 BestHiQuad < 0 ? 1 : BestHiQuad
5846 NewV = DAG.getVectorShuffle(MVT::v2i64, dl,
5847 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1),
5848 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]);
5849 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV);
5851 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the
5852 // source words for the shuffle, to aid later transformations.
5853 bool AllWordsInNewV = true;
5854 bool InOrder[2] = { true, true };
5855 for (unsigned i = 0; i != 8; ++i) {
5856 int idx = MaskVals[i];
5858 InOrder[i/4] = false;
5859 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad)
5861 AllWordsInNewV = false;
5865 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV;
5866 if (AllWordsInNewV) {
5867 for (int i = 0; i != 8; ++i) {
5868 int idx = MaskVals[i];
5871 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4;
5872 if ((idx != i) && idx < 4)
5874 if ((idx != i) && idx > 3)
5883 // If we've eliminated the use of V2, and the new mask is a pshuflw or
5884 // pshufhw, that's as cheap as it gets. Return the new shuffle.
5885 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) {
5886 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW;
5887 unsigned TargetMask = 0;
5888 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV,
5889 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]);
5890 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5891 TargetMask = pshufhw ? getShufflePSHUFHWImmediate(SVOp):
5892 getShufflePSHUFLWImmediate(SVOp);
5893 V1 = NewV.getOperand(0);
5894 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG);
5898 // Promote splats to a larger type which usually leads to more efficient code.
5899 // FIXME: Is this true if pshufb is available?
5900 if (SVOp->isSplat())
5901 return PromoteSplat(SVOp, DAG);
5903 // If we have SSSE3, and all words of the result are from 1 input vector,
5904 // case 2 is generated, otherwise case 3 is generated. If no SSSE3
5905 // is present, fall back to case 4.
5906 if (Subtarget->hasSSSE3()) {
5907 SmallVector<SDValue,16> pshufbMask;
5909 // If we have elements from both input vectors, set the high bit of the
5910 // shuffle mask element to zero out elements that come from V2 in the V1
5911 // mask, and elements that come from V1 in the V2 mask, so that the two
5912 // results can be OR'd together.
5913 bool TwoInputs = V1Used && V2Used;
5914 for (unsigned i = 0; i != 8; ++i) {
5915 int EltIdx = MaskVals[i] * 2;
5916 int Idx0 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx;
5917 int Idx1 = (TwoInputs && (EltIdx >= 16)) ? 0x80 : EltIdx+1;
5918 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5919 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5921 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1);
5922 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
5923 DAG.getNode(ISD::BUILD_VECTOR, dl,
5924 MVT::v16i8, &pshufbMask[0], 16));
5926 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5928 // Calculate the shuffle mask for the second input, shuffle it, and
5929 // OR it with the first shuffled input.
5931 for (unsigned i = 0; i != 8; ++i) {
5932 int EltIdx = MaskVals[i] * 2;
5933 int Idx0 = (EltIdx < 16) ? 0x80 : EltIdx - 16;
5934 int Idx1 = (EltIdx < 16) ? 0x80 : EltIdx - 15;
5935 pshufbMask.push_back(DAG.getConstant(Idx0, MVT::i8));
5936 pshufbMask.push_back(DAG.getConstant(Idx1, MVT::i8));
5938 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2);
5939 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
5940 DAG.getNode(ISD::BUILD_VECTOR, dl,
5941 MVT::v16i8, &pshufbMask[0], 16));
5942 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
5943 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
5946 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order,
5947 // and update MaskVals with new element order.
5948 std::bitset<8> InOrder;
5949 if (BestLoQuad >= 0) {
5950 int MaskV[] = { -1, -1, -1, -1, 4, 5, 6, 7 };
5951 for (int i = 0; i != 4; ++i) {
5952 int idx = MaskVals[i];
5955 } else if ((idx / 4) == BestLoQuad) {
5960 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5963 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5964 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5965 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16,
5967 getShufflePSHUFLWImmediate(SVOp), DAG);
5971 // If BestHi >= 0, generate a pshufhw to put the high elements in order,
5972 // and update MaskVals with the new element order.
5973 if (BestHiQuad >= 0) {
5974 int MaskV[] = { 0, 1, 2, 3, -1, -1, -1, -1 };
5975 for (unsigned i = 4; i != 8; ++i) {
5976 int idx = MaskVals[i];
5979 } else if ((idx / 4) == BestHiQuad) {
5980 MaskV[i] = (idx & 3) + 4;
5984 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16),
5987 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && Subtarget->hasSSSE3()) {
5988 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(NewV.getNode());
5989 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16,
5991 getShufflePSHUFHWImmediate(SVOp), DAG);
5995 // In case BestHi & BestLo were both -1, which means each quadword has a word
5996 // from each of the four input quadwords, calculate the InOrder bitvector now
5997 // before falling through to the insert/extract cleanup.
5998 if (BestLoQuad == -1 && BestHiQuad == -1) {
6000 for (int i = 0; i != 8; ++i)
6001 if (MaskVals[i] < 0 || MaskVals[i] == i)
6005 // The other elements are put in the right place using pextrw and pinsrw.
6006 for (unsigned i = 0; i != 8; ++i) {
6009 int EltIdx = MaskVals[i];
6012 SDValue ExtOp = (EltIdx < 8) ?
6013 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1,
6014 DAG.getIntPtrConstant(EltIdx)) :
6015 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2,
6016 DAG.getIntPtrConstant(EltIdx - 8));
6017 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp,
6018 DAG.getIntPtrConstant(i));
6023 // v16i8 shuffles - Prefer shuffles in the following order:
6024 // 1. [ssse3] 1 x pshufb
6025 // 2. [ssse3] 2 x pshufb + 1 x por
6026 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw
6028 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp,
6030 const X86TargetLowering &TLI) {
6031 SDValue V1 = SVOp->getOperand(0);
6032 SDValue V2 = SVOp->getOperand(1);
6033 DebugLoc dl = SVOp->getDebugLoc();
6034 ArrayRef<int> MaskVals = SVOp->getMask();
6036 // Promote splats to a larger type which usually leads to more efficient code.
6037 // FIXME: Is this true if pshufb is available?
6038 if (SVOp->isSplat())
6039 return PromoteSplat(SVOp, DAG);
6041 // If we have SSSE3, case 1 is generated when all result bytes come from
6042 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is
6043 // present, fall back to case 3.
6045 // If SSSE3, use 1 pshufb instruction per vector with elements in the result.
6046 if (TLI.getSubtarget()->hasSSSE3()) {
6047 SmallVector<SDValue,16> pshufbMask;
6049 // If all result elements are from one input vector, then only translate
6050 // undef mask values to 0x80 (zero out result) in the pshufb mask.
6052 // Otherwise, we have elements from both input vectors, and must zero out
6053 // elements that come from V2 in the first mask, and V1 in the second mask
6054 // so that we can OR them together.
6055 for (unsigned i = 0; i != 16; ++i) {
6056 int EltIdx = MaskVals[i];
6057 if (EltIdx < 0 || EltIdx >= 16)
6059 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6061 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
6062 DAG.getNode(ISD::BUILD_VECTOR, dl,
6063 MVT::v16i8, &pshufbMask[0], 16));
6065 // As PSHUFB will zero elements with negative indices, it's safe to ignore
6066 // the 2nd operand if it's undefined or zero.
6067 if (V2.getOpcode() == ISD::UNDEF ||
6068 ISD::isBuildVectorAllZeros(V2.getNode()))
6071 // Calculate the shuffle mask for the second input, shuffle it, and
6072 // OR it with the first shuffled input.
6074 for (unsigned i = 0; i != 16; ++i) {
6075 int EltIdx = MaskVals[i];
6076 EltIdx = (EltIdx < 16) ? 0x80 : EltIdx - 16;
6077 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6079 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
6080 DAG.getNode(ISD::BUILD_VECTOR, dl,
6081 MVT::v16i8, &pshufbMask[0], 16));
6082 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
6085 // No SSSE3 - Calculate in place words and then fix all out of place words
6086 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from
6087 // the 16 different words that comprise the two doublequadword input vectors.
6088 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1);
6089 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2);
6091 for (int i = 0; i != 8; ++i) {
6092 int Elt0 = MaskVals[i*2];
6093 int Elt1 = MaskVals[i*2+1];
6095 // This word of the result is all undef, skip it.
6096 if (Elt0 < 0 && Elt1 < 0)
6099 // This word of the result is already in the correct place, skip it.
6100 if ((Elt0 == i*2) && (Elt1 == i*2+1))
6103 SDValue Elt0Src = Elt0 < 16 ? V1 : V2;
6104 SDValue Elt1Src = Elt1 < 16 ? V1 : V2;
6107 // If Elt0 and Elt1 are defined, are consecutive, and can be load
6108 // using a single extract together, load it and store it.
6109 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) {
6110 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6111 DAG.getIntPtrConstant(Elt1 / 2));
6112 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6113 DAG.getIntPtrConstant(i));
6117 // If Elt1 is defined, extract it from the appropriate source. If the
6118 // source byte is not also odd, shift the extracted word left 8 bits
6119 // otherwise clear the bottom 8 bits if we need to do an or.
6121 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src,
6122 DAG.getIntPtrConstant(Elt1 / 2));
6123 if ((Elt1 & 1) == 0)
6124 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt,
6126 TLI.getShiftAmountTy(InsElt.getValueType())));
6128 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt,
6129 DAG.getConstant(0xFF00, MVT::i16));
6131 // If Elt0 is defined, extract it from the appropriate source. If the
6132 // source byte is not also even, shift the extracted word right 8 bits. If
6133 // Elt1 was also defined, OR the extracted values together before
6134 // inserting them in the result.
6136 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16,
6137 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2));
6138 if ((Elt0 & 1) != 0)
6139 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0,
6141 TLI.getShiftAmountTy(InsElt0.getValueType())));
6143 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0,
6144 DAG.getConstant(0x00FF, MVT::i16));
6145 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0)
6148 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt,
6149 DAG.getIntPtrConstant(i));
6151 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV);
6154 // v32i8 shuffles - Translate to VPSHUFB if possible.
6156 SDValue LowerVECTOR_SHUFFLEv32i8(ShuffleVectorSDNode *SVOp,
6157 const X86Subtarget *Subtarget,
6158 SelectionDAG &DAG) {
6159 MVT VT = SVOp->getValueType(0).getSimpleVT();
6160 SDValue V1 = SVOp->getOperand(0);
6161 SDValue V2 = SVOp->getOperand(1);
6162 DebugLoc dl = SVOp->getDebugLoc();
6163 SmallVector<int, 32> MaskVals(SVOp->getMask().begin(), SVOp->getMask().end());
6165 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6166 bool V1IsAllZero = ISD::isBuildVectorAllZeros(V1.getNode());
6167 bool V2IsAllZero = ISD::isBuildVectorAllZeros(V2.getNode());
6169 // VPSHUFB may be generated if
6170 // (1) one of input vector is undefined or zeroinitializer.
6171 // The mask value 0x80 puts 0 in the corresponding slot of the vector.
6172 // And (2) the mask indexes don't cross the 128-bit lane.
6173 if (VT != MVT::v32i8 || !Subtarget->hasInt256() ||
6174 (!V2IsUndef && !V2IsAllZero && !V1IsAllZero))
6177 if (V1IsAllZero && !V2IsAllZero) {
6178 CommuteVectorShuffleMask(MaskVals, 32);
6181 SmallVector<SDValue, 32> pshufbMask;
6182 for (unsigned i = 0; i != 32; i++) {
6183 int EltIdx = MaskVals[i];
6184 if (EltIdx < 0 || EltIdx >= 32)
6187 if ((EltIdx >= 16 && i < 16) || (EltIdx < 16 && i >= 16))
6188 // Cross lane is not allowed.
6192 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8));
6194 return DAG.getNode(X86ISD::PSHUFB, dl, MVT::v32i8, V1,
6195 DAG.getNode(ISD::BUILD_VECTOR, dl,
6196 MVT::v32i8, &pshufbMask[0], 32));
6199 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide
6200 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be
6201 /// done when every pair / quad of shuffle mask elements point to elements in
6202 /// the right sequence. e.g.
6203 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15>
6205 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp,
6206 SelectionDAG &DAG) {
6207 MVT VT = SVOp->getValueType(0).getSimpleVT();
6208 DebugLoc dl = SVOp->getDebugLoc();
6209 unsigned NumElems = VT.getVectorNumElements();
6212 switch (VT.SimpleTy) {
6213 default: llvm_unreachable("Unexpected!");
6214 case MVT::v4f32: NewVT = MVT::v2f64; Scale = 2; break;
6215 case MVT::v4i32: NewVT = MVT::v2i64; Scale = 2; break;
6216 case MVT::v8i16: NewVT = MVT::v4i32; Scale = 2; break;
6217 case MVT::v16i8: NewVT = MVT::v4i32; Scale = 4; break;
6218 case MVT::v16i16: NewVT = MVT::v8i32; Scale = 2; break;
6219 case MVT::v32i8: NewVT = MVT::v8i32; Scale = 4; break;
6222 SmallVector<int, 8> MaskVec;
6223 for (unsigned i = 0; i != NumElems; i += Scale) {
6225 for (unsigned j = 0; j != Scale; ++j) {
6226 int EltIdx = SVOp->getMaskElt(i+j);
6230 StartIdx = (EltIdx / Scale);
6231 if (EltIdx != (int)(StartIdx*Scale + j))
6234 MaskVec.push_back(StartIdx);
6237 SDValue V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(0));
6238 SDValue V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, SVOp->getOperand(1));
6239 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]);
6242 /// getVZextMovL - Return a zero-extending vector move low node.
6244 static SDValue getVZextMovL(MVT VT, EVT OpVT,
6245 SDValue SrcOp, SelectionDAG &DAG,
6246 const X86Subtarget *Subtarget, DebugLoc dl) {
6247 if (VT == MVT::v2f64 || VT == MVT::v4f32) {
6248 LoadSDNode *LD = NULL;
6249 if (!isScalarLoadToVector(SrcOp.getNode(), &LD))
6250 LD = dyn_cast<LoadSDNode>(SrcOp);
6252 // movssrr and movsdrr do not clear top bits. Try to use movd, movq
6254 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32;
6255 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) &&
6256 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6257 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST &&
6258 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) {
6260 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32;
6261 return DAG.getNode(ISD::BITCAST, dl, VT,
6262 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6263 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
6271 return DAG.getNode(ISD::BITCAST, dl, VT,
6272 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT,
6273 DAG.getNode(ISD::BITCAST, dl,
6277 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles
6278 /// which could not be matched by any known target speficic shuffle
6280 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6282 SDValue NewOp = Compact8x32ShuffleNode(SVOp, DAG);
6283 if (NewOp.getNode())
6286 MVT VT = SVOp->getValueType(0).getSimpleVT();
6288 unsigned NumElems = VT.getVectorNumElements();
6289 unsigned NumLaneElems = NumElems / 2;
6291 DebugLoc dl = SVOp->getDebugLoc();
6292 MVT EltVT = VT.getVectorElementType();
6293 MVT NVT = MVT::getVectorVT(EltVT, NumLaneElems);
6296 SmallVector<int, 16> Mask;
6297 for (unsigned l = 0; l < 2; ++l) {
6298 // Build a shuffle mask for the output, discovering on the fly which
6299 // input vectors to use as shuffle operands (recorded in InputUsed).
6300 // If building a suitable shuffle vector proves too hard, then bail
6301 // out with UseBuildVector set.
6302 bool UseBuildVector = false;
6303 int InputUsed[2] = { -1, -1 }; // Not yet discovered.
6304 unsigned LaneStart = l * NumLaneElems;
6305 for (unsigned i = 0; i != NumLaneElems; ++i) {
6306 // The mask element. This indexes into the input.
6307 int Idx = SVOp->getMaskElt(i+LaneStart);
6309 // the mask element does not index into any input vector.
6314 // The input vector this mask element indexes into.
6315 int Input = Idx / NumLaneElems;
6317 // Turn the index into an offset from the start of the input vector.
6318 Idx -= Input * NumLaneElems;
6320 // Find or create a shuffle vector operand to hold this input.
6322 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) {
6323 if (InputUsed[OpNo] == Input)
6324 // This input vector is already an operand.
6326 if (InputUsed[OpNo] < 0) {
6327 // Create a new operand for this input vector.
6328 InputUsed[OpNo] = Input;
6333 if (OpNo >= array_lengthof(InputUsed)) {
6334 // More than two input vectors used! Give up on trying to create a
6335 // shuffle vector. Insert all elements into a BUILD_VECTOR instead.
6336 UseBuildVector = true;
6340 // Add the mask index for the new shuffle vector.
6341 Mask.push_back(Idx + OpNo * NumLaneElems);
6344 if (UseBuildVector) {
6345 SmallVector<SDValue, 16> SVOps;
6346 for (unsigned i = 0; i != NumLaneElems; ++i) {
6347 // The mask element. This indexes into the input.
6348 int Idx = SVOp->getMaskElt(i+LaneStart);
6350 SVOps.push_back(DAG.getUNDEF(EltVT));
6354 // The input vector this mask element indexes into.
6355 int Input = Idx / NumElems;
6357 // Turn the index into an offset from the start of the input vector.
6358 Idx -= Input * NumElems;
6360 // Extract the vector element by hand.
6361 SVOps.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6362 SVOp->getOperand(Input),
6363 DAG.getIntPtrConstant(Idx)));
6366 // Construct the output using a BUILD_VECTOR.
6367 Output[l] = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, &SVOps[0],
6369 } else if (InputUsed[0] < 0) {
6370 // No input vectors were used! The result is undefined.
6371 Output[l] = DAG.getUNDEF(NVT);
6373 SDValue Op0 = Extract128BitVector(SVOp->getOperand(InputUsed[0] / 2),
6374 (InputUsed[0] % 2) * NumLaneElems,
6376 // If only one input was used, use an undefined vector for the other.
6377 SDValue Op1 = (InputUsed[1] < 0) ? DAG.getUNDEF(NVT) :
6378 Extract128BitVector(SVOp->getOperand(InputUsed[1] / 2),
6379 (InputUsed[1] % 2) * NumLaneElems, DAG, dl);
6380 // At least one input vector was used. Create a new shuffle vector.
6381 Output[l] = DAG.getVectorShuffle(NVT, dl, Op0, Op1, &Mask[0]);
6387 // Concatenate the result back
6388 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Output[0], Output[1]);
6391 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with
6392 /// 4 elements, and match them with several different shuffle types.
6394 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
6395 SDValue V1 = SVOp->getOperand(0);
6396 SDValue V2 = SVOp->getOperand(1);
6397 DebugLoc dl = SVOp->getDebugLoc();
6398 MVT VT = SVOp->getValueType(0).getSimpleVT();
6400 assert(VT.is128BitVector() && "Unsupported vector size");
6402 std::pair<int, int> Locs[4];
6403 int Mask1[] = { -1, -1, -1, -1 };
6404 SmallVector<int, 8> PermMask(SVOp->getMask().begin(), SVOp->getMask().end());
6408 for (unsigned i = 0; i != 4; ++i) {
6409 int Idx = PermMask[i];
6411 Locs[i] = std::make_pair(-1, -1);
6413 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!");
6415 Locs[i] = std::make_pair(0, NumLo);
6419 Locs[i] = std::make_pair(1, NumHi);
6421 Mask1[2+NumHi] = Idx;
6427 if (NumLo <= 2 && NumHi <= 2) {
6428 // If no more than two elements come from either vector. This can be
6429 // implemented with two shuffles. First shuffle gather the elements.
6430 // The second shuffle, which takes the first shuffle as both of its
6431 // vector operands, put the elements into the right order.
6432 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6434 int Mask2[] = { -1, -1, -1, -1 };
6436 for (unsigned i = 0; i != 4; ++i)
6437 if (Locs[i].first != -1) {
6438 unsigned Idx = (i < 2) ? 0 : 4;
6439 Idx += Locs[i].first * 2 + Locs[i].second;
6443 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]);
6446 if (NumLo == 3 || NumHi == 3) {
6447 // Otherwise, we must have three elements from one vector, call it X, and
6448 // one element from the other, call it Y. First, use a shufps to build an
6449 // intermediate vector with the one element from Y and the element from X
6450 // that will be in the same half in the final destination (the indexes don't
6451 // matter). Then, use a shufps to build the final vector, taking the half
6452 // containing the element from Y from the intermediate, and the other half
6455 // Normalize it so the 3 elements come from V1.
6456 CommuteVectorShuffleMask(PermMask, 4);
6460 // Find the element from V2.
6462 for (HiIndex = 0; HiIndex < 3; ++HiIndex) {
6463 int Val = PermMask[HiIndex];
6470 Mask1[0] = PermMask[HiIndex];
6472 Mask1[2] = PermMask[HiIndex^1];
6474 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6477 Mask1[0] = PermMask[0];
6478 Mask1[1] = PermMask[1];
6479 Mask1[2] = HiIndex & 1 ? 6 : 4;
6480 Mask1[3] = HiIndex & 1 ? 4 : 6;
6481 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]);
6484 Mask1[0] = HiIndex & 1 ? 2 : 0;
6485 Mask1[1] = HiIndex & 1 ? 0 : 2;
6486 Mask1[2] = PermMask[2];
6487 Mask1[3] = PermMask[3];
6492 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]);
6495 // Break it into (shuffle shuffle_hi, shuffle_lo).
6496 int LoMask[] = { -1, -1, -1, -1 };
6497 int HiMask[] = { -1, -1, -1, -1 };
6499 int *MaskPtr = LoMask;
6500 unsigned MaskIdx = 0;
6503 for (unsigned i = 0; i != 4; ++i) {
6510 int Idx = PermMask[i];
6512 Locs[i] = std::make_pair(-1, -1);
6513 } else if (Idx < 4) {
6514 Locs[i] = std::make_pair(MaskIdx, LoIdx);
6515 MaskPtr[LoIdx] = Idx;
6518 Locs[i] = std::make_pair(MaskIdx, HiIdx);
6519 MaskPtr[HiIdx] = Idx;
6524 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]);
6525 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]);
6526 int MaskOps[] = { -1, -1, -1, -1 };
6527 for (unsigned i = 0; i != 4; ++i)
6528 if (Locs[i].first != -1)
6529 MaskOps[i] = Locs[i].first * 4 + Locs[i].second;
6530 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]);
6533 static bool MayFoldVectorLoad(SDValue V) {
6534 while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
6535 V = V.getOperand(0);
6537 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
6538 V = V.getOperand(0);
6539 if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
6540 V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
6541 // BUILD_VECTOR (load), undef
6542 V = V.getOperand(0);
6544 return MayFoldLoad(V);
6548 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) {
6549 EVT VT = Op.getValueType();
6551 // Canonizalize to v2f64.
6552 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1);
6553 return DAG.getNode(ISD::BITCAST, dl, VT,
6554 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64,
6559 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG,
6561 SDValue V1 = Op.getOperand(0);
6562 SDValue V2 = Op.getOperand(1);
6563 EVT VT = Op.getValueType();
6565 assert(VT != MVT::v2i64 && "unsupported shuffle type");
6567 if (HasSSE2 && VT == MVT::v2f64)
6568 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG);
6570 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1)
6571 return DAG.getNode(ISD::BITCAST, dl, VT,
6572 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32,
6573 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1),
6574 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG));
6578 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) {
6579 SDValue V1 = Op.getOperand(0);
6580 SDValue V2 = Op.getOperand(1);
6581 EVT VT = Op.getValueType();
6583 assert((VT == MVT::v4i32 || VT == MVT::v4f32) &&
6584 "unsupported shuffle type");
6586 if (V2.getOpcode() == ISD::UNDEF)
6590 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG);
6594 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasSSE2) {
6595 SDValue V1 = Op.getOperand(0);
6596 SDValue V2 = Op.getOperand(1);
6597 EVT VT = Op.getValueType();
6598 unsigned NumElems = VT.getVectorNumElements();
6600 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second
6601 // operand of these instructions is only memory, so check if there's a
6602 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the
6604 bool CanFoldLoad = false;
6606 // Trivial case, when V2 comes from a load.
6607 if (MayFoldVectorLoad(V2))
6610 // When V1 is a load, it can be folded later into a store in isel, example:
6611 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1)
6613 // (MOVLPSmr addr:$src1, VR128:$src2)
6614 // So, recognize this potential and also use MOVLPS or MOVLPD
6615 else if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op))
6618 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6620 if (HasSSE2 && NumElems == 2)
6621 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
6624 // If we don't care about the second element, proceed to use movss.
6625 if (SVOp->getMaskElt(1) != -1)
6626 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
6629 // movl and movlp will both match v2i64, but v2i64 is never matched by
6630 // movl earlier because we make it strict to avoid messing with the movlp load
6631 // folding logic (see the code above getMOVLP call). Match it here then,
6632 // this is horrible, but will stay like this until we move all shuffle
6633 // matching to x86 specific nodes. Note that for the 1st condition all
6634 // types are matched with movsd.
6636 // FIXME: isMOVLMask should be checked and matched before getMOVLP,
6637 // as to remove this logic from here, as much as possible
6638 if (NumElems == 2 || !isMOVLMask(SVOp->getMask(), VT))
6639 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6640 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6643 assert(VT != MVT::v4i32 && "unsupported shuffle type");
6645 // Invert the operand order and use SHUFPS to match it.
6646 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V2, V1,
6647 getShuffleSHUFImmediate(SVOp), DAG);
6650 // Reduce a vector shuffle to zext.
6652 X86TargetLowering::LowerVectorIntExtend(SDValue Op, SelectionDAG &DAG) const {
6653 // PMOVZX is only available from SSE41.
6654 if (!Subtarget->hasSSE41())
6657 EVT VT = Op.getValueType();
6659 // Only AVX2 support 256-bit vector integer extending.
6660 if (!Subtarget->hasInt256() && VT.is256BitVector())
6663 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6664 DebugLoc DL = Op.getDebugLoc();
6665 SDValue V1 = Op.getOperand(0);
6666 SDValue V2 = Op.getOperand(1);
6667 unsigned NumElems = VT.getVectorNumElements();
6669 // Extending is an unary operation and the element type of the source vector
6670 // won't be equal to or larger than i64.
6671 if (V2.getOpcode() != ISD::UNDEF || !VT.isInteger() ||
6672 VT.getVectorElementType() == MVT::i64)
6675 // Find the expansion ratio, e.g. expanding from i8 to i32 has a ratio of 4.
6676 unsigned Shift = 1; // Start from 2, i.e. 1 << 1.
6677 while ((1U << Shift) < NumElems) {
6678 if (SVOp->getMaskElt(1U << Shift) == 1)
6681 // The maximal ratio is 8, i.e. from i8 to i64.
6686 // Check the shuffle mask.
6687 unsigned Mask = (1U << Shift) - 1;
6688 for (unsigned i = 0; i != NumElems; ++i) {
6689 int EltIdx = SVOp->getMaskElt(i);
6690 if ((i & Mask) != 0 && EltIdx != -1)
6692 if ((i & Mask) == 0 && (unsigned)EltIdx != (i >> Shift))
6696 LLVMContext *Context = DAG.getContext();
6697 unsigned NBits = VT.getVectorElementType().getSizeInBits() << Shift;
6698 EVT NeVT = EVT::getIntegerVT(*Context, NBits);
6699 EVT NVT = EVT::getVectorVT(*Context, NeVT, NumElems >> Shift);
6701 if (!isTypeLegal(NVT))
6704 // Simplify the operand as it's prepared to be fed into shuffle.
6705 unsigned SignificantBits = NVT.getSizeInBits() >> Shift;
6706 if (V1.getOpcode() == ISD::BITCAST &&
6707 V1.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR &&
6708 V1.getOperand(0).getOperand(0).getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6710 .getOperand(0).getValueType().getSizeInBits() == SignificantBits) {
6711 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast x)
6712 SDValue V = V1.getOperand(0).getOperand(0).getOperand(0);
6713 ConstantSDNode *CIdx =
6714 dyn_cast<ConstantSDNode>(V1.getOperand(0).getOperand(0).getOperand(1));
6715 // If it's foldable, i.e. normal load with single use, we will let code
6716 // selection to fold it. Otherwise, we will short the conversion sequence.
6717 if (CIdx && CIdx->getZExtValue() == 0 &&
6718 (!ISD::isNormalLoad(V.getNode()) || !V.hasOneUse())) {
6719 if (V.getValueSizeInBits() > V1.getValueSizeInBits()) {
6720 // The "ext_vec_elt" node is wider than the result node.
6721 // In this case we should extract subvector from V.
6722 // (bitcast (sclr2vec (ext_vec_elt x))) -> (bitcast (extract_subvector x)).
6723 unsigned Ratio = V.getValueSizeInBits() / V1.getValueSizeInBits();
6724 EVT FullVT = V.getValueType();
6725 EVT SubVecVT = EVT::getVectorVT(*Context,
6726 FullVT.getVectorElementType(),
6727 FullVT.getVectorNumElements()/Ratio);
6728 V = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVecVT, V,
6729 DAG.getIntPtrConstant(0));
6731 V1 = DAG.getNode(ISD::BITCAST, DL, V1.getValueType(), V);
6735 return DAG.getNode(ISD::BITCAST, DL, VT,
6736 DAG.getNode(X86ISD::VZEXT, DL, NVT, V1));
6740 X86TargetLowering::NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG) const {
6741 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6742 MVT VT = Op.getValueType().getSimpleVT();
6743 DebugLoc dl = Op.getDebugLoc();
6744 SDValue V1 = Op.getOperand(0);
6745 SDValue V2 = Op.getOperand(1);
6747 if (isZeroShuffle(SVOp))
6748 return getZeroVector(VT, Subtarget, DAG, dl);
6750 // Handle splat operations
6751 if (SVOp->isSplat()) {
6752 // Use vbroadcast whenever the splat comes from a foldable load
6753 SDValue Broadcast = LowerVectorBroadcast(Op, DAG);
6754 if (Broadcast.getNode())
6758 // Check integer expanding shuffles.
6759 SDValue NewOp = LowerVectorIntExtend(Op, DAG);
6760 if (NewOp.getNode())
6763 // If the shuffle can be profitably rewritten as a narrower shuffle, then
6765 if (VT == MVT::v8i16 || VT == MVT::v16i8 ||
6766 VT == MVT::v16i16 || VT == MVT::v32i8) {
6767 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6768 if (NewOp.getNode())
6769 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp);
6770 } else if ((VT == MVT::v4i32 ||
6771 (VT == MVT::v4f32 && Subtarget->hasSSE2()))) {
6772 // FIXME: Figure out a cleaner way to do this.
6773 // Try to make use of movq to zero out the top part.
6774 if (ISD::isBuildVectorAllZeros(V2.getNode())) {
6775 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6776 if (NewOp.getNode()) {
6777 MVT NewVT = NewOp.getValueType().getSimpleVT();
6778 if (isCommutedMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(),
6779 NewVT, true, false))
6780 return getVZextMovL(VT, NewVT, NewOp.getOperand(0),
6781 DAG, Subtarget, dl);
6783 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) {
6784 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG);
6785 if (NewOp.getNode()) {
6786 MVT NewVT = NewOp.getValueType().getSimpleVT();
6787 if (isMOVLMask(cast<ShuffleVectorSDNode>(NewOp)->getMask(), NewVT))
6788 return getVZextMovL(VT, NewVT, NewOp.getOperand(1),
6789 DAG, Subtarget, dl);
6797 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
6798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6799 SDValue V1 = Op.getOperand(0);
6800 SDValue V2 = Op.getOperand(1);
6801 MVT VT = Op.getValueType().getSimpleVT();
6802 DebugLoc dl = Op.getDebugLoc();
6803 unsigned NumElems = VT.getVectorNumElements();
6804 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
6805 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
6806 bool V1IsSplat = false;
6807 bool V2IsSplat = false;
6808 bool HasSSE2 = Subtarget->hasSSE2();
6809 bool HasFp256 = Subtarget->hasFp256();
6810 bool HasInt256 = Subtarget->hasInt256();
6811 MachineFunction &MF = DAG.getMachineFunction();
6812 bool OptForSize = MF.getFunction()->getAttributes().
6813 hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
6815 assert(VT.getSizeInBits() != 64 && "Can't lower MMX shuffles");
6817 if (V1IsUndef && V2IsUndef)
6818 return DAG.getUNDEF(VT);
6820 assert(!V1IsUndef && "Op 1 of shuffle should not be undef");
6822 // Vector shuffle lowering takes 3 steps:
6824 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable
6825 // narrowing and commutation of operands should be handled.
6826 // 2) Matching of shuffles with known shuffle masks to x86 target specific
6828 // 3) Rewriting of unmatched masks into new generic shuffle operations,
6829 // so the shuffle can be broken into other shuffles and the legalizer can
6830 // try the lowering again.
6832 // The general idea is that no vector_shuffle operation should be left to
6833 // be matched during isel, all of them must be converted to a target specific
6836 // Normalize the input vectors. Here splats, zeroed vectors, profitable
6837 // narrowing and commutation of operands should be handled. The actual code
6838 // doesn't include all of those, work in progress...
6839 SDValue NewOp = NormalizeVectorShuffle(Op, DAG);
6840 if (NewOp.getNode())
6843 SmallVector<int, 8> M(SVOp->getMask().begin(), SVOp->getMask().end());
6845 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and
6846 // unpckh_undef). Only use pshufd if speed is more important than size.
6847 if (OptForSize && isUNPCKL_v_undef_Mask(M, VT, HasInt256))
6848 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
6849 if (OptForSize && isUNPCKH_v_undef_Mask(M, VT, HasInt256))
6850 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6852 if (isMOVDDUPMask(M, VT) && Subtarget->hasSSE3() &&
6853 V2IsUndef && MayFoldVectorLoad(V1))
6854 return getMOVDDup(Op, dl, V1, DAG);
6856 if (isMOVHLPS_v_undef_Mask(M, VT))
6857 return getMOVHighToLow(Op, dl, DAG);
6859 // Use to match splats
6860 if (HasSSE2 && isUNPCKHMask(M, VT, HasInt256) && V2IsUndef &&
6861 (VT == MVT::v2f64 || VT == MVT::v2i64))
6862 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
6864 if (isPSHUFDMask(M, VT)) {
6865 // The actual implementation will match the mask in the if above and then
6866 // during isel it can match several different instructions, not only pshufd
6867 // as its name says, sad but true, emulate the behavior for now...
6868 if (isMOVDDUPMask(M, VT) && ((VT == MVT::v4f32 || VT == MVT::v2i64)))
6869 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG);
6871 unsigned TargetMask = getShuffleSHUFImmediate(SVOp);
6873 if (HasSSE2 && (VT == MVT::v4f32 || VT == MVT::v4i32))
6874 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG);
6876 if (HasFp256 && (VT == MVT::v4f32 || VT == MVT::v2f64))
6877 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1, TargetMask,
6880 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V1,
6884 if (isPALIGNRMask(M, VT, Subtarget))
6885 return getTargetShuffleNode(X86ISD::PALIGNR, dl, VT, V1, V2,
6886 getShufflePALIGNRImmediate(SVOp),
6889 // Check if this can be converted into a logical shift.
6890 bool isLeft = false;
6893 bool isShift = HasSSE2 && isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt);
6894 if (isShift && ShVal.hasOneUse()) {
6895 // If the shifted value has multiple uses, it may be cheaper to use
6896 // v_set0 + movlhps or movhlps, etc.
6897 MVT EltVT = VT.getVectorElementType();
6898 ShAmt *= EltVT.getSizeInBits();
6899 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6902 if (isMOVLMask(M, VT)) {
6903 if (ISD::isBuildVectorAllZeros(V1.getNode()))
6904 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl);
6905 if (!isMOVLPMask(M, VT)) {
6906 if (HasSSE2 && (VT == MVT::v2i64 || VT == MVT::v2f64))
6907 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG);
6909 if (VT == MVT::v4i32 || VT == MVT::v4f32)
6910 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG);
6914 // FIXME: fold these into legal mask.
6915 if (isMOVLHPSMask(M, VT) && !isUNPCKLMask(M, VT, HasInt256))
6916 return getMOVLowToHigh(Op, dl, DAG, HasSSE2);
6918 if (isMOVHLPSMask(M, VT))
6919 return getMOVHighToLow(Op, dl, DAG);
6921 if (V2IsUndef && isMOVSHDUPMask(M, VT, Subtarget))
6922 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG);
6924 if (V2IsUndef && isMOVSLDUPMask(M, VT, Subtarget))
6925 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG);
6927 if (isMOVLPMask(M, VT))
6928 return getMOVLP(Op, dl, DAG, HasSSE2);
6930 if (ShouldXformToMOVHLPS(M, VT) ||
6931 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), M, VT))
6932 return CommuteVectorShuffle(SVOp, DAG);
6935 // No better options. Use a vshldq / vsrldq.
6936 MVT EltVT = VT.getVectorElementType();
6937 ShAmt *= EltVT.getSizeInBits();
6938 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl);
6941 bool Commuted = false;
6942 // FIXME: This should also accept a bitcast of a splat? Be careful, not
6943 // 1,1,1,1 -> v8i16 though.
6944 V1IsSplat = isSplatVector(V1.getNode());
6945 V2IsSplat = isSplatVector(V2.getNode());
6947 // Canonicalize the splat or undef, if present, to be on the RHS.
6948 if (!V2IsUndef && V1IsSplat && !V2IsSplat) {
6949 CommuteVectorShuffleMask(M, NumElems);
6951 std::swap(V1IsSplat, V2IsSplat);
6955 if (isCommutedMOVLMask(M, VT, V2IsSplat, V2IsUndef)) {
6956 // Shuffling low element of v1 into undef, just return v1.
6959 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which
6960 // the instruction selector will not match, so get a canonical MOVL with
6961 // swapped operands to undo the commute.
6962 return getMOVL(DAG, dl, VT, V2, V1);
6965 if (isUNPCKLMask(M, VT, HasInt256))
6966 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6968 if (isUNPCKHMask(M, VT, HasInt256))
6969 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6972 // Normalize mask so all entries that point to V2 points to its first
6973 // element then try to match unpck{h|l} again. If match, return a
6974 // new vector_shuffle with the corrected mask.p
6975 SmallVector<int, 8> NewMask(M.begin(), M.end());
6976 NormalizeMask(NewMask, NumElems);
6977 if (isUNPCKLMask(NewMask, VT, HasInt256, true))
6978 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6979 if (isUNPCKHMask(NewMask, VT, HasInt256, true))
6980 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6984 // Commute is back and try unpck* again.
6985 // FIXME: this seems wrong.
6986 CommuteVectorShuffleMask(M, NumElems);
6988 std::swap(V1IsSplat, V2IsSplat);
6991 if (isUNPCKLMask(M, VT, HasInt256))
6992 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V2, DAG);
6994 if (isUNPCKHMask(M, VT, HasInt256))
6995 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V2, DAG);
6998 // Normalize the node to match x86 shuffle ops if needed
6999 if (!V2IsUndef && (isSHUFPMask(M, VT, HasFp256, /* Commuted */ true)))
7000 return CommuteVectorShuffle(SVOp, DAG);
7002 // The checks below are all present in isShuffleMaskLegal, but they are
7003 // inlined here right now to enable us to directly emit target specific
7004 // nodes, and remove one by one until they don't return Op anymore.
7006 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) &&
7007 SVOp->getSplatIndex() == 0 && V2IsUndef) {
7008 if (VT == MVT::v2f64 || VT == MVT::v2i64)
7009 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7012 if (isPSHUFHWMask(M, VT, HasInt256))
7013 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1,
7014 getShufflePSHUFHWImmediate(SVOp),
7017 if (isPSHUFLWMask(M, VT, HasInt256))
7018 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1,
7019 getShufflePSHUFLWImmediate(SVOp),
7022 if (isSHUFPMask(M, VT, HasFp256))
7023 return getTargetShuffleNode(X86ISD::SHUFP, dl, VT, V1, V2,
7024 getShuffleSHUFImmediate(SVOp), DAG);
7026 if (isUNPCKL_v_undef_Mask(M, VT, HasInt256))
7027 return getTargetShuffleNode(X86ISD::UNPCKL, dl, VT, V1, V1, DAG);
7028 if (isUNPCKH_v_undef_Mask(M, VT, HasInt256))
7029 return getTargetShuffleNode(X86ISD::UNPCKH, dl, VT, V1, V1, DAG);
7031 //===--------------------------------------------------------------------===//
7032 // Generate target specific nodes for 128 or 256-bit shuffles only
7033 // supported in the AVX instruction set.
7036 // Handle VMOVDDUPY permutations
7037 if (V2IsUndef && isMOVDDUPYMask(M, VT, HasFp256))
7038 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG);
7040 // Handle VPERMILPS/D* permutations
7041 if (isVPERMILPMask(M, VT, HasFp256)) {
7042 if (HasInt256 && VT == MVT::v8i32)
7043 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1,
7044 getShuffleSHUFImmediate(SVOp), DAG);
7045 return getTargetShuffleNode(X86ISD::VPERMILP, dl, VT, V1,
7046 getShuffleSHUFImmediate(SVOp), DAG);
7049 // Handle VPERM2F128/VPERM2I128 permutations
7050 if (isVPERM2X128Mask(M, VT, HasFp256))
7051 return getTargetShuffleNode(X86ISD::VPERM2X128, dl, VT, V1,
7052 V2, getShuffleVPERM2X128Immediate(SVOp), DAG);
7054 SDValue BlendOp = LowerVECTOR_SHUFFLEtoBlend(SVOp, Subtarget, DAG);
7055 if (BlendOp.getNode())
7058 if (V2IsUndef && HasInt256 && (VT == MVT::v8i32 || VT == MVT::v8f32)) {
7059 SmallVector<SDValue, 8> permclMask;
7060 for (unsigned i = 0; i != 8; ++i) {
7061 permclMask.push_back(DAG.getConstant((M[i]>=0) ? M[i] : 0, MVT::i32));
7063 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32,
7065 // Bitcast is for VPERMPS since mask is v8i32 but node takes v8f32
7066 return DAG.getNode(X86ISD::VPERMV, dl, VT,
7067 DAG.getNode(ISD::BITCAST, dl, VT, Mask), V1);
7070 if (V2IsUndef && HasInt256 && (VT == MVT::v4i64 || VT == MVT::v4f64))
7071 return getTargetShuffleNode(X86ISD::VPERMI, dl, VT, V1,
7072 getShuffleCLImmediate(SVOp), DAG);
7074 //===--------------------------------------------------------------------===//
7075 // Since no target specific shuffle was selected for this generic one,
7076 // lower it into other known shuffles. FIXME: this isn't true yet, but
7077 // this is the plan.
7080 // Handle v8i16 specifically since SSE can do byte extraction and insertion.
7081 if (VT == MVT::v8i16) {
7082 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, Subtarget, DAG);
7083 if (NewOp.getNode())
7087 if (VT == MVT::v16i8) {
7088 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this);
7089 if (NewOp.getNode())
7093 if (VT == MVT::v32i8) {
7094 SDValue NewOp = LowerVECTOR_SHUFFLEv32i8(SVOp, Subtarget, DAG);
7095 if (NewOp.getNode())
7099 // Handle all 128-bit wide vectors with 4 elements, and match them with
7100 // several different shuffle types.
7101 if (NumElems == 4 && VT.is128BitVector())
7102 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG);
7104 // Handle general 256-bit shuffles
7105 if (VT.is256BitVector())
7106 return LowerVECTOR_SHUFFLE_256(SVOp, DAG);
7111 static SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7112 MVT VT = Op.getValueType().getSimpleVT();
7113 DebugLoc dl = Op.getDebugLoc();
7115 if (!Op.getOperand(0).getValueType().getSimpleVT().is128BitVector())
7118 if (VT.getSizeInBits() == 8) {
7119 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32,
7120 Op.getOperand(0), Op.getOperand(1));
7121 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7122 DAG.getValueType(VT));
7123 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7126 if (VT.getSizeInBits() == 16) {
7127 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7128 // If Idx is 0, it's cheaper to do a move instead of a pextrw.
7130 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7131 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7132 DAG.getNode(ISD::BITCAST, dl,
7136 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32,
7137 Op.getOperand(0), Op.getOperand(1));
7138 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract,
7139 DAG.getValueType(VT));
7140 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7143 if (VT == MVT::f32) {
7144 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy
7145 // the result back to FR32 register. It's only worth matching if the
7146 // result has a single use which is a store or a bitcast to i32. And in
7147 // the case of a store, it's not worth it if the index is a constant 0,
7148 // because a MOVSSmr can be used instead, which is smaller and faster.
7149 if (!Op.hasOneUse())
7151 SDNode *User = *Op.getNode()->use_begin();
7152 if ((User->getOpcode() != ISD::STORE ||
7153 (isa<ConstantSDNode>(Op.getOperand(1)) &&
7154 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) &&
7155 (User->getOpcode() != ISD::BITCAST ||
7156 User->getValueType(0) != MVT::i32))
7158 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7159 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32,
7162 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract);
7165 if (VT == MVT::i32 || VT == MVT::i64) {
7166 // ExtractPS/pextrq works with constant index.
7167 if (isa<ConstantSDNode>(Op.getOperand(1)))
7174 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7175 SelectionDAG &DAG) const {
7176 if (!isa<ConstantSDNode>(Op.getOperand(1)))
7179 SDValue Vec = Op.getOperand(0);
7180 MVT VecVT = Vec.getValueType().getSimpleVT();
7182 // If this is a 256-bit vector result, first extract the 128-bit vector and
7183 // then extract the element from the 128-bit vector.
7184 if (VecVT.is256BitVector()) {
7185 DebugLoc dl = Op.getNode()->getDebugLoc();
7186 unsigned NumElems = VecVT.getVectorNumElements();
7187 SDValue Idx = Op.getOperand(1);
7188 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7190 // Get the 128-bit vector.
7191 Vec = Extract128BitVector(Vec, IdxVal, DAG, dl);
7193 if (IdxVal >= NumElems/2)
7194 IdxVal -= NumElems/2;
7195 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,
7196 DAG.getConstant(IdxVal, MVT::i32));
7199 assert(VecVT.is128BitVector() && "Unexpected vector length");
7201 if (Subtarget->hasSSE41()) {
7202 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG);
7207 MVT VT = Op.getValueType().getSimpleVT();
7208 DebugLoc dl = Op.getDebugLoc();
7209 // TODO: handle v16i8.
7210 if (VT.getSizeInBits() == 16) {
7211 SDValue Vec = Op.getOperand(0);
7212 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7214 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16,
7215 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32,
7216 DAG.getNode(ISD::BITCAST, dl,
7219 // Transform it so it match pextrw which produces a 32-bit result.
7220 MVT EltVT = MVT::i32;
7221 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT,
7222 Op.getOperand(0), Op.getOperand(1));
7223 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract,
7224 DAG.getValueType(VT));
7225 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert);
7228 if (VT.getSizeInBits() == 32) {
7229 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7233 // SHUFPS the element to the lowest double word, then movss.
7234 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 };
7235 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7236 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7237 DAG.getUNDEF(VVT), Mask);
7238 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7239 DAG.getIntPtrConstant(0));
7242 if (VT.getSizeInBits() == 64) {
7243 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b
7244 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught
7245 // to match extract_elt for f64.
7246 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
7250 // UNPCKHPD the element to the lowest double word, then movsd.
7251 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored
7252 // to a f64mem, the whole operation is folded into a single MOVHPDmr.
7253 int Mask[2] = { 1, -1 };
7254 MVT VVT = Op.getOperand(0).getValueType().getSimpleVT();
7255 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),
7256 DAG.getUNDEF(VVT), Mask);
7257 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,
7258 DAG.getIntPtrConstant(0));
7264 static SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) {
7265 MVT VT = Op.getValueType().getSimpleVT();
7266 MVT EltVT = VT.getVectorElementType();
7267 DebugLoc dl = Op.getDebugLoc();
7269 SDValue N0 = Op.getOperand(0);
7270 SDValue N1 = Op.getOperand(1);
7271 SDValue N2 = Op.getOperand(2);
7273 if (!VT.is128BitVector())
7276 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) &&
7277 isa<ConstantSDNode>(N2)) {
7279 if (VT == MVT::v8i16)
7280 Opc = X86ISD::PINSRW;
7281 else if (VT == MVT::v16i8)
7282 Opc = X86ISD::PINSRB;
7284 Opc = X86ISD::PINSRB;
7286 // Transform it so it match pinsr{b,w} which expects a GR32 as its second
7288 if (N1.getValueType() != MVT::i32)
7289 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7290 if (N2.getValueType() != MVT::i32)
7291 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7292 return DAG.getNode(Opc, dl, VT, N0, N1, N2);
7295 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) {
7296 // Bits [7:6] of the constant are the source select. This will always be
7297 // zero here. The DAG Combiner may combine an extract_elt index into these
7298 // bits. For example (insert (extract, 3), 2) could be matched by putting
7299 // the '3' into bits [7:6] of X86ISD::INSERTPS.
7300 // Bits [5:4] of the constant are the destination select. This is the
7301 // value of the incoming immediate.
7302 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may
7303 // combine either bitwise AND or insert of float 0.0 to set these bits.
7304 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
7305 // Create this as a scalar to vector..
7306 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);
7307 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);
7310 if ((EltVT == MVT::i32 || EltVT == MVT::i64) && isa<ConstantSDNode>(N2)) {
7311 // PINSR* works with constant index.
7318 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
7319 MVT VT = Op.getValueType().getSimpleVT();
7320 MVT EltVT = VT.getVectorElementType();
7322 DebugLoc dl = Op.getDebugLoc();
7323 SDValue N0 = Op.getOperand(0);
7324 SDValue N1 = Op.getOperand(1);
7325 SDValue N2 = Op.getOperand(2);
7327 // If this is a 256-bit vector result, first extract the 128-bit vector,
7328 // insert the element into the extracted half and then place it back.
7329 if (VT.is256BitVector()) {
7330 if (!isa<ConstantSDNode>(N2))
7333 // Get the desired 128-bit vector half.
7334 unsigned NumElems = VT.getVectorNumElements();
7335 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue();
7336 SDValue V = Extract128BitVector(N0, IdxVal, DAG, dl);
7338 // Insert the element into the desired half.
7339 bool Upper = IdxVal >= NumElems/2;
7340 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,
7341 DAG.getConstant(Upper ? IdxVal-NumElems/2 : IdxVal, MVT::i32));
7343 // Insert the changed part back to the 256-bit vector
7344 return Insert128BitVector(N0, V, IdxVal, DAG, dl);
7347 if (Subtarget->hasSSE41())
7348 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG);
7350 if (EltVT == MVT::i8)
7353 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) {
7354 // Transform it so it match pinsrw which expects a 16-bit value in a GR32
7355 // as its second argument.
7356 if (N1.getValueType() != MVT::i32)
7357 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);
7358 if (N2.getValueType() != MVT::i32)
7359 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue());
7360 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);
7365 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
7366 LLVMContext *Context = DAG.getContext();
7367 DebugLoc dl = Op.getDebugLoc();
7368 MVT OpVT = Op.getValueType().getSimpleVT();
7370 // If this is a 256-bit vector result, first insert into a 128-bit
7371 // vector and then insert into the 256-bit vector.
7372 if (!OpVT.is128BitVector()) {
7373 // Insert into a 128-bit vector.
7374 EVT VT128 = EVT::getVectorVT(*Context,
7375 OpVT.getVectorElementType(),
7376 OpVT.getVectorNumElements() / 2);
7378 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0));
7380 // Insert the 128-bit vector.
7381 return Insert128BitVector(DAG.getUNDEF(OpVT), Op, 0, DAG, dl);
7384 if (OpVT == MVT::v1i64 &&
7385 Op.getOperand(0).getValueType() == MVT::i64)
7386 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
7388 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
7389 assert(OpVT.is128BitVector() && "Expected an SSE type!");
7390 return DAG.getNode(ISD::BITCAST, dl, OpVT,
7391 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt));
7394 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in
7395 // a simple subregister reference or explicit instructions to grab
7396 // upper bits of a vector.
7397 static SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7398 SelectionDAG &DAG) {
7399 if (Subtarget->hasFp256()) {
7400 DebugLoc dl = Op.getNode()->getDebugLoc();
7401 SDValue Vec = Op.getNode()->getOperand(0);
7402 SDValue Idx = Op.getNode()->getOperand(1);
7404 if (Op.getNode()->getValueType(0).is128BitVector() &&
7405 Vec.getNode()->getValueType(0).is256BitVector() &&
7406 isa<ConstantSDNode>(Idx)) {
7407 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7408 return Extract128BitVector(Vec, IdxVal, DAG, dl);
7414 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a
7415 // simple superregister reference or explicit instructions to insert
7416 // the upper bits of a vector.
7417 static SDValue LowerINSERT_SUBVECTOR(SDValue Op, const X86Subtarget *Subtarget,
7418 SelectionDAG &DAG) {
7419 if (Subtarget->hasFp256()) {
7420 DebugLoc dl = Op.getNode()->getDebugLoc();
7421 SDValue Vec = Op.getNode()->getOperand(0);
7422 SDValue SubVec = Op.getNode()->getOperand(1);
7423 SDValue Idx = Op.getNode()->getOperand(2);
7425 if (Op.getNode()->getValueType(0).is256BitVector() &&
7426 SubVec.getNode()->getValueType(0).is128BitVector() &&
7427 isa<ConstantSDNode>(Idx)) {
7428 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
7429 return Insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
7435 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
7436 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is
7437 // one of the above mentioned nodes. It has to be wrapped because otherwise
7438 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
7439 // be used to form addressing mode. These wrapped nodes will be selected
7442 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
7443 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
7445 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7447 unsigned char OpFlag = 0;
7448 unsigned WrapperKind = X86ISD::Wrapper;
7449 CodeModel::Model M = getTargetMachine().getCodeModel();
7451 if (Subtarget->isPICStyleRIPRel() &&
7452 (M == CodeModel::Small || M == CodeModel::Kernel))
7453 WrapperKind = X86ISD::WrapperRIP;
7454 else if (Subtarget->isPICStyleGOT())
7455 OpFlag = X86II::MO_GOTOFF;
7456 else if (Subtarget->isPICStyleStubPIC())
7457 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7459 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
7461 CP->getOffset(), OpFlag);
7462 DebugLoc DL = CP->getDebugLoc();
7463 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7464 // With PIC, the address is actually $g + Offset.
7466 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7467 DAG.getNode(X86ISD::GlobalBaseReg,
7468 DebugLoc(), getPointerTy()),
7475 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
7476 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
7478 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7480 unsigned char OpFlag = 0;
7481 unsigned WrapperKind = X86ISD::Wrapper;
7482 CodeModel::Model M = getTargetMachine().getCodeModel();
7484 if (Subtarget->isPICStyleRIPRel() &&
7485 (M == CodeModel::Small || M == CodeModel::Kernel))
7486 WrapperKind = X86ISD::WrapperRIP;
7487 else if (Subtarget->isPICStyleGOT())
7488 OpFlag = X86II::MO_GOTOFF;
7489 else if (Subtarget->isPICStyleStubPIC())
7490 OpFlag = X86II::MO_PIC_BASE_OFFSET;
7492 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(),
7494 DebugLoc DL = JT->getDebugLoc();
7495 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7497 // With PIC, the address is actually $g + Offset.
7499 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7500 DAG.getNode(X86ISD::GlobalBaseReg,
7501 DebugLoc(), getPointerTy()),
7508 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const {
7509 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol();
7511 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7513 unsigned char OpFlag = 0;
7514 unsigned WrapperKind = X86ISD::Wrapper;
7515 CodeModel::Model M = getTargetMachine().getCodeModel();
7517 if (Subtarget->isPICStyleRIPRel() &&
7518 (M == CodeModel::Small || M == CodeModel::Kernel)) {
7519 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF())
7520 OpFlag = X86II::MO_GOTPCREL;
7521 WrapperKind = X86ISD::WrapperRIP;
7522 } else if (Subtarget->isPICStyleGOT()) {
7523 OpFlag = X86II::MO_GOT;
7524 } else if (Subtarget->isPICStyleStubPIC()) {
7525 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE;
7526 } else if (Subtarget->isPICStyleStubNoDynamic()) {
7527 OpFlag = X86II::MO_DARWIN_NONLAZY;
7530 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag);
7532 DebugLoc DL = Op.getDebugLoc();
7533 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7535 // With PIC, the address is actually $g + Offset.
7536 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
7537 !Subtarget->is64Bit()) {
7538 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7539 DAG.getNode(X86ISD::GlobalBaseReg,
7540 DebugLoc(), getPointerTy()),
7544 // For symbols that require a load from a stub to get the address, emit the
7546 if (isGlobalStubReference(OpFlag))
7547 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result,
7548 MachinePointerInfo::getGOT(), false, false, false, 0);
7554 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
7555 // Create the TargetBlockAddressAddress node.
7556 unsigned char OpFlags =
7557 Subtarget->ClassifyBlockAddressReference();
7558 CodeModel::Model M = getTargetMachine().getCodeModel();
7559 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
7560 int64_t Offset = cast<BlockAddressSDNode>(Op)->getOffset();
7561 DebugLoc dl = Op.getDebugLoc();
7562 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy(), Offset,
7565 if (Subtarget->isPICStyleRIPRel() &&
7566 (M == CodeModel::Small || M == CodeModel::Kernel))
7567 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7569 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7571 // With PIC, the address is actually $g + Offset.
7572 if (isGlobalRelativeToPICBase(OpFlags)) {
7573 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7574 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7582 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
7583 int64_t Offset, SelectionDAG &DAG) const {
7584 // Create the TargetGlobalAddress node, folding in the constant
7585 // offset if it is legal.
7586 unsigned char OpFlags =
7587 Subtarget->ClassifyGlobalReference(GV, getTargetMachine());
7588 CodeModel::Model M = getTargetMachine().getCodeModel();
7590 if (OpFlags == X86II::MO_NO_FLAG &&
7591 X86::isOffsetSuitableForCodeModel(Offset, M)) {
7592 // A direct static reference to a global.
7593 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset);
7596 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
7599 if (Subtarget->isPICStyleRIPRel() &&
7600 (M == CodeModel::Small || M == CodeModel::Kernel))
7601 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result);
7603 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result);
7605 // With PIC, the address is actually $g + Offset.
7606 if (isGlobalRelativeToPICBase(OpFlags)) {
7607 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(),
7608 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()),
7612 // For globals that require a load from a stub to get the address, emit the
7614 if (isGlobalStubReference(OpFlags))
7615 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
7616 MachinePointerInfo::getGOT(), false, false, false, 0);
7618 // If there was a non-zero offset that we didn't fold, create an explicit
7621 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
7622 DAG.getConstant(Offset, getPointerTy()));
7628 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
7629 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
7630 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
7631 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG);
7635 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA,
7636 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg,
7637 unsigned char OperandFlags, bool LocalDynamic = false) {
7638 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7639 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7640 DebugLoc dl = GA->getDebugLoc();
7641 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7642 GA->getValueType(0),
7646 X86ISD::NodeType CallType = LocalDynamic ? X86ISD::TLSBASEADDR
7650 SDValue Ops[] = { Chain, TGA, *InFlag };
7651 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
7653 SDValue Ops[] = { Chain, TGA };
7654 Chain = DAG.getNode(CallType, dl, NodeTys, Ops, array_lengthof(Ops));
7657 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls.
7658 MFI->setAdjustsStack(true);
7660 SDValue Flag = Chain.getValue(1);
7661 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag);
7664 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit
7666 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7669 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better
7670 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7671 DAG.getNode(X86ISD::GlobalBaseReg,
7672 DebugLoc(), PtrVT), InFlag);
7673 InFlag = Chain.getValue(1);
7675 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD);
7678 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit
7680 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7682 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT,
7683 X86::RAX, X86II::MO_TLSGD);
7686 static SDValue LowerToTLSLocalDynamicModel(GlobalAddressSDNode *GA,
7690 DebugLoc dl = GA->getDebugLoc();
7692 // Get the start address of the TLS block for this module.
7693 X86MachineFunctionInfo* MFI = DAG.getMachineFunction()
7694 .getInfo<X86MachineFunctionInfo>();
7695 MFI->incNumLocalDynamicTLSAccesses();
7699 Base = GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX,
7700 X86II::MO_TLSLD, /*LocalDynamic=*/true);
7703 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX,
7704 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT), InFlag);
7705 InFlag = Chain.getValue(1);
7706 Base = GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX,
7707 X86II::MO_TLSLDM, /*LocalDynamic=*/true);
7710 // Note: the CleanupLocalDynamicTLSPass will remove redundant computations
7714 unsigned char OperandFlags = X86II::MO_DTPOFF;
7715 unsigned WrapperKind = X86ISD::Wrapper;
7716 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7717 GA->getValueType(0),
7718 GA->getOffset(), OperandFlags);
7719 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7721 // Add x@dtpoff with the base.
7722 return DAG.getNode(ISD::ADD, dl, PtrVT, Offset, Base);
7725 // Lower ISD::GlobalTLSAddress using the "initial exec" or "local exec" model.
7726 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
7727 const EVT PtrVT, TLSModel::Model model,
7728 bool is64Bit, bool isPIC) {
7729 DebugLoc dl = GA->getDebugLoc();
7731 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
7732 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
7733 is64Bit ? 257 : 256));
7735 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
7736 DAG.getIntPtrConstant(0),
7737 MachinePointerInfo(Ptr),
7738 false, false, false, 0);
7740 unsigned char OperandFlags = 0;
7741 // Most TLS accesses are not RIP relative, even on x86-64. One exception is
7743 unsigned WrapperKind = X86ISD::Wrapper;
7744 if (model == TLSModel::LocalExec) {
7745 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF;
7746 } else if (model == TLSModel::InitialExec) {
7748 OperandFlags = X86II::MO_GOTTPOFF;
7749 WrapperKind = X86ISD::WrapperRIP;
7751 OperandFlags = isPIC ? X86II::MO_GOTNTPOFF : X86II::MO_INDNTPOFF;
7754 llvm_unreachable("Unexpected model");
7757 // emit "addl x@ntpoff,%eax" (local exec)
7758 // or "addl x@indntpoff,%eax" (initial exec)
7759 // or "addl x@gotntpoff(%ebx) ,%eax" (initial exec, 32-bit pic)
7760 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7761 GA->getValueType(0),
7762 GA->getOffset(), OperandFlags);
7763 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
7765 if (model == TLSModel::InitialExec) {
7766 if (isPIC && !is64Bit) {
7767 Offset = DAG.getNode(ISD::ADD, dl, PtrVT,
7768 DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), PtrVT),
7772 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset,
7773 MachinePointerInfo::getGOT(), false, false, false,
7777 // The address of the thread local variable is the add of the thread
7778 // pointer with the offset of the variable.
7779 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
7783 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
7785 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
7786 const GlobalValue *GV = GA->getGlobal();
7788 if (Subtarget->isTargetELF()) {
7789 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
7792 case TLSModel::GeneralDynamic:
7793 if (Subtarget->is64Bit())
7794 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
7795 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
7796 case TLSModel::LocalDynamic:
7797 return LowerToTLSLocalDynamicModel(GA, DAG, getPointerTy(),
7798 Subtarget->is64Bit());
7799 case TLSModel::InitialExec:
7800 case TLSModel::LocalExec:
7801 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
7802 Subtarget->is64Bit(),
7803 getTargetMachine().getRelocationModel() == Reloc::PIC_);
7805 llvm_unreachable("Unknown TLS model.");
7808 if (Subtarget->isTargetDarwin()) {
7809 // Darwin only has one model of TLS. Lower to that.
7810 unsigned char OpFlag = 0;
7811 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
7812 X86ISD::WrapperRIP : X86ISD::Wrapper;
7814 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
7816 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
7817 !Subtarget->is64Bit();
7819 OpFlag = X86II::MO_TLVP_PIC_BASE;
7821 OpFlag = X86II::MO_TLVP;
7822 DebugLoc DL = Op.getDebugLoc();
7823 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
7824 GA->getValueType(0),
7825 GA->getOffset(), OpFlag);
7826 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
7828 // With PIC32, the address is actually $g + Offset.
7830 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
7831 DAG.getNode(X86ISD::GlobalBaseReg,
7832 DebugLoc(), getPointerTy()),
7835 // Lowering the machine isd will make sure everything is in the right
7837 SDValue Chain = DAG.getEntryNode();
7838 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
7839 SDValue Args[] = { Chain, Offset };
7840 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2);
7842 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
7843 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7844 MFI->setAdjustsStack(true);
7846 // And our return value (tls address) is in the standard call return value
7848 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
7849 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(),
7853 if (Subtarget->isTargetWindows() || Subtarget->isTargetMingw()) {
7854 // Just use the implicit TLS architecture
7855 // Need to generate someting similar to:
7856 // mov rdx, qword [gs:abs 58H]; Load pointer to ThreadLocalStorage
7858 // mov ecx, dword [rel _tls_index]: Load index (from C runtime)
7859 // mov rcx, qword [rdx+rcx*8]
7860 // mov eax, .tls$:tlsvar
7861 // [rax+rcx] contains the address
7862 // Windows 64bit: gs:0x58
7863 // Windows 32bit: fs:__tls_array
7865 // If GV is an alias then use the aliasee for determining
7866 // thread-localness.
7867 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
7868 GV = GA->resolveAliasedGlobal(false);
7869 DebugLoc dl = GA->getDebugLoc();
7870 SDValue Chain = DAG.getEntryNode();
7872 // Get the Thread Pointer, which is %fs:__tls_array (32-bit) or
7873 // %gs:0x58 (64-bit). On MinGW, __tls_array is not available, so directly
7874 // use its literal value of 0x2C.
7875 Value *Ptr = Constant::getNullValue(Subtarget->is64Bit()
7876 ? Type::getInt8PtrTy(*DAG.getContext(),
7878 : Type::getInt32PtrTy(*DAG.getContext(),
7881 SDValue TlsArray = Subtarget->is64Bit() ? DAG.getIntPtrConstant(0x58) :
7882 (Subtarget->isTargetMingw() ? DAG.getIntPtrConstant(0x2C) :
7883 DAG.getExternalSymbol("_tls_array", getPointerTy()));
7885 SDValue ThreadPointer = DAG.getLoad(getPointerTy(), dl, Chain, TlsArray,
7886 MachinePointerInfo(Ptr),
7887 false, false, false, 0);
7889 // Load the _tls_index variable
7890 SDValue IDX = DAG.getExternalSymbol("_tls_index", getPointerTy());
7891 if (Subtarget->is64Bit())
7892 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, getPointerTy(), Chain,
7893 IDX, MachinePointerInfo(), MVT::i32,
7896 IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),
7897 false, false, false, 0);
7899 SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),
7901 IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);
7903 SDValue res = DAG.getNode(ISD::ADD, dl, getPointerTy(), ThreadPointer, IDX);
7904 res = DAG.getLoad(getPointerTy(), dl, Chain, res, MachinePointerInfo(),
7905 false, false, false, 0);
7907 // Get the offset of start of .tls section
7908 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
7909 GA->getValueType(0),
7910 GA->getOffset(), X86II::MO_SECREL);
7911 SDValue Offset = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), TGA);
7913 // The address of the thread local variable is the add of the thread
7914 // pointer with the offset of the variable.
7915 return DAG.getNode(ISD::ADD, dl, getPointerTy(), res, Offset);
7918 llvm_unreachable("TLS not implemented for this target.");
7921 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
7922 /// and take a 2 x i32 value to shift plus a shift amount.
7923 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const{
7924 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
7925 EVT VT = Op.getValueType();
7926 unsigned VTBits = VT.getSizeInBits();
7927 DebugLoc dl = Op.getDebugLoc();
7928 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
7929 SDValue ShOpLo = Op.getOperand(0);
7930 SDValue ShOpHi = Op.getOperand(1);
7931 SDValue ShAmt = Op.getOperand(2);
7932 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,
7933 DAG.getConstant(VTBits - 1, MVT::i8))
7934 : DAG.getConstant(0, VT);
7937 if (Op.getOpcode() == ISD::SHL_PARTS) {
7938 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt);
7939 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
7941 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt);
7942 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt);
7945 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,
7946 DAG.getConstant(VTBits, MVT::i8));
7947 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
7948 AndNode, DAG.getConstant(0, MVT::i8));
7951 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);
7952 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };
7953 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
7955 if (Op.getOpcode() == ISD::SHL_PARTS) {
7956 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7957 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7959 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4);
7960 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4);
7963 SDValue Ops[2] = { Lo, Hi };
7964 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
7967 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
7968 SelectionDAG &DAG) const {
7969 EVT SrcVT = Op.getOperand(0).getValueType();
7971 if (SrcVT.isVector())
7974 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 &&
7975 "Unknown SINT_TO_FP to lower!");
7977 // These are really Legal; return the operand so the caller accepts it as
7979 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType()))
7981 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) &&
7982 Subtarget->is64Bit()) {
7986 DebugLoc dl = Op.getDebugLoc();
7987 unsigned Size = SrcVT.getSizeInBits()/8;
7988 MachineFunction &MF = DAG.getMachineFunction();
7989 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
7990 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
7991 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
7993 MachinePointerInfo::getFixedStack(SSFI),
7995 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG);
7998 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
8000 SelectionDAG &DAG) const {
8002 DebugLoc DL = Op.getDebugLoc();
8004 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType());
8006 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue);
8008 Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
8010 unsigned ByteSize = SrcVT.getSizeInBits()/8;
8012 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot);
8013 MachineMemOperand *MMO;
8015 int SSFI = FI->getIndex();
8017 DAG.getMachineFunction()
8018 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8019 MachineMemOperand::MOLoad, ByteSize, ByteSize);
8021 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand();
8022 StackSlot = StackSlot.getOperand(1);
8024 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
8025 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
8027 Tys, Ops, array_lengthof(Ops),
8031 Chain = Result.getValue(1);
8032 SDValue InFlag = Result.getValue(2);
8034 // FIXME: Currently the FST is flagged to the FILD_FLAG. This
8035 // shouldn't be necessary except that RFP cannot be live across
8036 // multiple blocks. When stackifier is fixed, they can be uncoupled.
8037 MachineFunction &MF = DAG.getMachineFunction();
8038 unsigned SSFISize = Op.getValueType().getSizeInBits()/8;
8039 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false);
8040 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8041 Tys = DAG.getVTList(MVT::Other);
8043 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag
8045 MachineMemOperand *MMO =
8046 DAG.getMachineFunction()
8047 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8048 MachineMemOperand::MOStore, SSFISize, SSFISize);
8050 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
8051 Ops, array_lengthof(Ops),
8052 Op.getValueType(), MMO);
8053 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot,
8054 MachinePointerInfo::getFixedStack(SSFI),
8055 false, false, false, 0);
8061 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion.
8062 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op,
8063 SelectionDAG &DAG) const {
8064 // This algorithm is not obvious. Here it is what we're trying to output:
8067 punpckldq (c0), %xmm0 // c0: (uint4){ 0x43300000U, 0x45300000U, 0U, 0U }
8068 subpd (c1), %xmm0 // c1: (double2){ 0x1.0p52, 0x1.0p52 * 0x1.0p32 }
8072 pshufd $0x4e, %xmm0, %xmm1
8077 DebugLoc dl = Op.getDebugLoc();
8078 LLVMContext *Context = DAG.getContext();
8080 // Build some magic constants.
8081 const uint32_t CV0[] = { 0x43300000, 0x45300000, 0, 0 };
8082 Constant *C0 = ConstantDataVector::get(*Context, CV0);
8083 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16);
8085 SmallVector<Constant*,2> CV1;
8087 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8088 APInt(64, 0x4330000000000000ULL))));
8090 ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8091 APInt(64, 0x4530000000000000ULL))));
8092 Constant *C1 = ConstantVector::get(CV1);
8093 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16);
8095 // Load the 64-bit value into an XMM register.
8096 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64,
8098 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0,
8099 MachinePointerInfo::getConstantPool(),
8100 false, false, false, 16);
8101 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32,
8102 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, XR1),
8105 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1,
8106 MachinePointerInfo::getConstantPool(),
8107 false, false, false, 16);
8108 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck1);
8109 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1);
8112 if (Subtarget->hasSSE3()) {
8113 // FIXME: The 'haddpd' instruction may be slower than 'movhlps + addsd'.
8114 Result = DAG.getNode(X86ISD::FHADD, dl, MVT::v2f64, Sub, Sub);
8116 SDValue S2F = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Sub);
8117 SDValue Shuffle = getTargetShuffleNode(X86ISD::PSHUFD, dl, MVT::v4i32,
8119 Result = DAG.getNode(ISD::FADD, dl, MVT::v2f64,
8120 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Shuffle),
8124 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,
8125 DAG.getIntPtrConstant(0));
8128 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.
8129 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op,
8130 SelectionDAG &DAG) const {
8131 DebugLoc dl = Op.getDebugLoc();
8132 // FP constant to bias correct the final result.
8133 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
8136 // Load the 32-bit value into an XMM register.
8137 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
8140 // Zero out the upper parts of the register.
8141 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget, DAG);
8143 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8144 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),
8145 DAG.getIntPtrConstant(0));
8147 // Or the load with the bias.
8148 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,
8149 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8150 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8152 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
8153 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
8154 MVT::v2f64, Bias)));
8155 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8156 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),
8157 DAG.getIntPtrConstant(0));
8159 // Subtract the bias.
8160 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);
8162 // Handle final rounding.
8163 EVT DestVT = Op.getValueType();
8165 if (DestVT.bitsLT(MVT::f64))
8166 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
8167 DAG.getIntPtrConstant(0));
8168 if (DestVT.bitsGT(MVT::f64))
8169 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
8171 // Handle final rounding.
8175 SDValue X86TargetLowering::lowerUINT_TO_FP_vec(SDValue Op,
8176 SelectionDAG &DAG) const {
8177 SDValue N0 = Op.getOperand(0);
8178 EVT SVT = N0.getValueType();
8179 DebugLoc dl = Op.getDebugLoc();
8181 assert((SVT == MVT::v4i8 || SVT == MVT::v4i16 ||
8182 SVT == MVT::v8i8 || SVT == MVT::v8i16) &&
8183 "Custom UINT_TO_FP is not supported!");
8185 EVT NVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32,
8186 SVT.getVectorNumElements());
8187 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(),
8188 DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N0));
8191 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
8192 SelectionDAG &DAG) const {
8193 SDValue N0 = Op.getOperand(0);
8194 DebugLoc dl = Op.getDebugLoc();
8196 if (Op.getValueType().isVector())
8197 return lowerUINT_TO_FP_vec(Op, DAG);
8199 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't
8200 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform
8201 // the optimization here.
8202 if (DAG.SignBitIsZero(N0))
8203 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0);
8205 EVT SrcVT = N0.getValueType();
8206 EVT DstVT = Op.getValueType();
8207 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64)
8208 return LowerUINT_TO_FP_i64(Op, DAG);
8209 if (SrcVT == MVT::i32 && X86ScalarSSEf64)
8210 return LowerUINT_TO_FP_i32(Op, DAG);
8211 if (Subtarget->is64Bit() && SrcVT == MVT::i64 && DstVT == MVT::f32)
8214 // Make a 64-bit buffer, and use it to build an FILD.
8215 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);
8216 if (SrcVT == MVT::i32) {
8217 SDValue WordOff = DAG.getConstant(4, getPointerTy());
8218 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,
8219 getPointerTy(), StackSlot, WordOff);
8220 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8221 StackSlot, MachinePointerInfo(),
8223 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),
8224 OffsetSlot, MachinePointerInfo(),
8226 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);
8230 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP");
8231 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
8232 StackSlot, MachinePointerInfo(),
8234 // For i64 source, we need to add the appropriate power of 2 if the input
8235 // was negative. This is the same as the optimization in
8236 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here,
8237 // we must be careful to do the computation in x87 extended precision, not
8238 // in SSE. (The generic code can't know it's OK to do this, or how to.)
8239 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
8240 MachineMemOperand *MMO =
8241 DAG.getMachineFunction()
8242 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8243 MachineMemOperand::MOLoad, 8, 8);
8245 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
8246 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
8247 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops,
8248 array_lengthof(Ops), MVT::i64, MMO);
8250 APInt FF(32, 0x5F800000ULL);
8252 // Check whether the sign bit is set.
8253 SDValue SignSet = DAG.getSetCC(dl,
8254 getSetCCResultType(*DAG.getContext(), MVT::i64),
8255 Op.getOperand(0), DAG.getConstant(0, MVT::i64),
8258 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
8259 SDValue FudgePtr = DAG.getConstantPool(
8260 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
8263 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
8264 SDValue Zero = DAG.getIntPtrConstant(0);
8265 SDValue Four = DAG.getIntPtrConstant(4);
8266 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
8268 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);
8270 // Load the value out, extending it from f32 to f80.
8271 // FIXME: Avoid the extend by constructing the right constant pool?
8272 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(),
8273 FudgePtr, MachinePointerInfo::getConstantPool(),
8274 MVT::f32, false, false, 4);
8275 // Extend everything to 80 bits to force it to be done on x87.
8276 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);
8277 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));
8280 std::pair<SDValue,SDValue>
8281 X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
8282 bool IsSigned, bool IsReplace) const {
8283 DebugLoc DL = Op.getDebugLoc();
8285 EVT DstTy = Op.getValueType();
8287 if (!IsSigned && !isIntegerTypeFTOL(DstTy)) {
8288 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT");
8292 assert(DstTy.getSimpleVT() <= MVT::i64 &&
8293 DstTy.getSimpleVT() >= MVT::i16 &&
8294 "Unknown FP_TO_INT to lower!");
8296 // These are really Legal.
8297 if (DstTy == MVT::i32 &&
8298 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8299 return std::make_pair(SDValue(), SDValue());
8300 if (Subtarget->is64Bit() &&
8301 DstTy == MVT::i64 &&
8302 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType()))
8303 return std::make_pair(SDValue(), SDValue());
8305 // We lower FP->int64 either into FISTP64 followed by a load from a temporary
8306 // stack slot, or into the FTOL runtime function.
8307 MachineFunction &MF = DAG.getMachineFunction();
8308 unsigned MemSize = DstTy.getSizeInBits()/8;
8309 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8310 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8313 if (!IsSigned && isIntegerTypeFTOL(DstTy))
8314 Opc = X86ISD::WIN_FTOL;
8316 switch (DstTy.getSimpleVT().SimpleTy) {
8317 default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
8318 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
8319 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
8320 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
8323 SDValue Chain = DAG.getEntryNode();
8324 SDValue Value = Op.getOperand(0);
8325 EVT TheVT = Op.getOperand(0).getValueType();
8326 // FIXME This causes a redundant load/store if the SSE-class value is already
8327 // in memory, such as if it is on the callstack.
8328 if (isScalarFPTypeInSSEReg(TheVT)) {
8329 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!");
8330 Chain = DAG.getStore(Chain, DL, Value, StackSlot,
8331 MachinePointerInfo::getFixedStack(SSFI),
8333 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other);
8335 Chain, StackSlot, DAG.getValueType(TheVT)
8338 MachineMemOperand *MMO =
8339 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8340 MachineMemOperand::MOLoad, MemSize, MemSize);
8341 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops,
8342 array_lengthof(Ops), DstTy, MMO);
8343 Chain = Value.getValue(1);
8344 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
8345 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
8348 MachineMemOperand *MMO =
8349 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
8350 MachineMemOperand::MOStore, MemSize, MemSize);
8352 if (Opc != X86ISD::WIN_FTOL) {
8353 // Build the FP_TO_INT*_IN_MEM
8354 SDValue Ops[] = { Chain, Value, StackSlot };
8355 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other),
8356 Ops, array_lengthof(Ops), DstTy,
8358 return std::make_pair(FIST, StackSlot);
8360 SDValue ftol = DAG.getNode(X86ISD::WIN_FTOL, DL,
8361 DAG.getVTList(MVT::Other, MVT::Glue),
8363 SDValue eax = DAG.getCopyFromReg(ftol, DL, X86::EAX,
8364 MVT::i32, ftol.getValue(1));
8365 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), DL, X86::EDX,
8366 MVT::i32, eax.getValue(2));
8367 SDValue Ops[] = { eax, edx };
8368 SDValue pair = IsReplace
8369 ? DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Ops, array_lengthof(Ops))
8370 : DAG.getMergeValues(Ops, array_lengthof(Ops), DL);
8371 return std::make_pair(pair, SDValue());
8375 static SDValue LowerAVXExtend(SDValue Op, SelectionDAG &DAG,
8376 const X86Subtarget *Subtarget) {
8377 MVT VT = Op->getValueType(0).getSimpleVT();
8378 SDValue In = Op->getOperand(0);
8379 MVT InVT = In.getValueType().getSimpleVT();
8380 DebugLoc dl = Op->getDebugLoc();
8382 // Optimize vectors in AVX mode:
8385 // Use vpunpcklwd for 4 lower elements v8i16 -> v4i32.
8386 // Use vpunpckhwd for 4 upper elements v8i16 -> v4i32.
8387 // Concat upper and lower parts.
8390 // Use vpunpckldq for 4 lower elements v4i32 -> v2i64.
8391 // Use vpunpckhdq for 4 upper elements v4i32 -> v2i64.
8392 // Concat upper and lower parts.
8395 if (((VT != MVT::v8i32) || (InVT != MVT::v8i16)) &&
8396 ((VT != MVT::v4i64) || (InVT != MVT::v4i32)))
8399 if (Subtarget->hasInt256())
8400 return DAG.getNode(X86ISD::VZEXT_MOVL, dl, VT, In);
8402 SDValue ZeroVec = getZeroVector(InVT, Subtarget, DAG, dl);
8403 SDValue Undef = DAG.getUNDEF(InVT);
8404 bool NeedZero = Op.getOpcode() == ISD::ZERO_EXTEND;
8405 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8406 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8408 MVT HVT = MVT::getVectorVT(VT.getVectorElementType(),
8409 VT.getVectorNumElements()/2);
8411 OpLo = DAG.getNode(ISD::BITCAST, dl, HVT, OpLo);
8412 OpHi = DAG.getNode(ISD::BITCAST, dl, HVT, OpHi);
8414 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
8417 SDValue X86TargetLowering::LowerANY_EXTEND(SDValue Op,
8418 SelectionDAG &DAG) const {
8419 if (Subtarget->hasFp256()) {
8420 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8427 SDValue X86TargetLowering::LowerZERO_EXTEND(SDValue Op,
8428 SelectionDAG &DAG) const {
8429 DebugLoc DL = Op.getDebugLoc();
8430 MVT VT = Op.getValueType().getSimpleVT();
8431 SDValue In = Op.getOperand(0);
8432 MVT SVT = In.getValueType().getSimpleVT();
8434 if (Subtarget->hasFp256()) {
8435 SDValue Res = LowerAVXExtend(Op, DAG, Subtarget);
8440 if (!VT.is256BitVector() || !SVT.is128BitVector() ||
8441 VT.getVectorNumElements() != SVT.getVectorNumElements())
8444 assert(Subtarget->hasFp256() && "256-bit vector is observed without AVX!");
8446 // AVX2 has better support of integer extending.
8447 if (Subtarget->hasInt256())
8448 return DAG.getNode(X86ISD::VZEXT, DL, VT, In);
8450 SDValue Lo = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32, In);
8451 static const int Mask[] = {4, 5, 6, 7, -1, -1, -1, -1};
8452 SDValue Hi = DAG.getNode(X86ISD::VZEXT, DL, MVT::v4i32,
8453 DAG.getVectorShuffle(MVT::v8i16, DL, In,
8454 DAG.getUNDEF(MVT::v8i16),
8457 return DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i32, Lo, Hi);
8460 SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
8461 DebugLoc DL = Op.getDebugLoc();
8462 MVT VT = Op.getValueType().getSimpleVT();
8463 SDValue In = Op.getOperand(0);
8464 MVT SVT = In.getValueType().getSimpleVT();
8466 if ((VT == MVT::v4i32) && (SVT == MVT::v4i64)) {
8467 // On AVX2, v4i64 -> v4i32 becomes VPERMD.
8468 if (Subtarget->hasInt256()) {
8469 static const int ShufMask[] = {0, 2, 4, 6, -1, -1, -1, -1};
8470 In = DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, In);
8471 In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),
8473 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,
8474 DAG.getIntPtrConstant(0));
8477 // On AVX, v4i64 -> v4i32 becomes a sequence that uses PSHUFD and MOVLHPS.
8478 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8479 DAG.getIntPtrConstant(0));
8480 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8481 DAG.getIntPtrConstant(2));
8483 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8484 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8487 static const int ShufMask1[] = {0, 2, 0, 0};
8488 SDValue Undef = DAG.getUNDEF(VT);
8489 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8490 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8492 // The MOVLHPS mask:
8493 static const int ShufMask2[] = {0, 1, 4, 5};
8494 return DAG.getVectorShuffle(VT, DL, OpLo, OpHi, ShufMask2);
8497 if ((VT == MVT::v8i16) && (SVT == MVT::v8i32)) {
8498 // On AVX2, v8i32 -> v8i16 becomed PSHUFB.
8499 if (Subtarget->hasInt256()) {
8500 In = DAG.getNode(ISD::BITCAST, DL, MVT::v32i8, In);
8502 SmallVector<SDValue,32> pshufbMask;
8503 for (unsigned i = 0; i < 2; ++i) {
8504 pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));
8505 pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));
8506 pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));
8507 pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));
8508 pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));
8509 pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));
8510 pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));
8511 pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));
8512 for (unsigned j = 0; j < 8; ++j)
8513 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));
8515 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8,
8516 &pshufbMask[0], 32);
8517 In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);
8518 In = DAG.getNode(ISD::BITCAST, DL, MVT::v4i64, In);
8520 static const int ShufMask[] = {0, 2, -1, -1};
8521 In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),
8523 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,
8524 DAG.getIntPtrConstant(0));
8525 return DAG.getNode(ISD::BITCAST, DL, VT, In);
8528 SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8529 DAG.getIntPtrConstant(0));
8531 SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,
8532 DAG.getIntPtrConstant(4));
8534 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);
8535 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);
8538 static const int ShufMask1[] = {0, 1, 4, 5, 8, 9, 12, 13,
8539 -1, -1, -1, -1, -1, -1, -1, -1};
8541 SDValue Undef = DAG.getUNDEF(MVT::v16i8);
8542 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask1);
8543 OpHi = DAG.getVectorShuffle(MVT::v16i8, DL, OpHi, Undef, ShufMask1);
8545 OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);
8546 OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);
8548 // The MOVLHPS Mask:
8549 static const int ShufMask2[] = {0, 1, 4, 5};
8550 SDValue res = DAG.getVectorShuffle(MVT::v4i32, DL, OpLo, OpHi, ShufMask2);
8551 return DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, res);
8554 // Handle truncation of V256 to V128 using shuffles.
8555 if (!VT.is128BitVector() || !SVT.is256BitVector())
8558 assert(VT.getVectorNumElements() != SVT.getVectorNumElements() &&
8560 assert(Subtarget->hasFp256() && "256-bit vector without AVX!");
8562 unsigned NumElems = VT.getVectorNumElements();
8563 EVT NVT = EVT::getVectorVT(*DAG.getContext(), VT.getVectorElementType(),
8566 SmallVector<int, 16> MaskVec(NumElems * 2, -1);
8567 // Prepare truncation shuffle mask
8568 for (unsigned i = 0; i != NumElems; ++i)
8570 SDValue V = DAG.getVectorShuffle(NVT, DL,
8571 DAG.getNode(ISD::BITCAST, DL, NVT, In),
8572 DAG.getUNDEF(NVT), &MaskVec[0]);
8573 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,
8574 DAG.getIntPtrConstant(0));
8577 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,
8578 SelectionDAG &DAG) const {
8579 MVT VT = Op.getValueType().getSimpleVT();
8580 if (VT.isVector()) {
8581 if (VT == MVT::v8i16)
8582 return DAG.getNode(ISD::TRUNCATE, Op.getDebugLoc(), VT,
8583 DAG.getNode(ISD::FP_TO_SINT, Op.getDebugLoc(),
8584 MVT::v8i32, Op.getOperand(0)));
8588 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8589 /*IsSigned=*/ true, /*IsReplace=*/ false);
8590 SDValue FIST = Vals.first, StackSlot = Vals.second;
8591 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal.
8592 if (FIST.getNode() == 0) return Op;
8594 if (StackSlot.getNode())
8596 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8597 FIST, StackSlot, MachinePointerInfo(),
8598 false, false, false, 0);
8600 // The node is the result.
8604 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op,
8605 SelectionDAG &DAG) const {
8606 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG,
8607 /*IsSigned=*/ false, /*IsReplace=*/ false);
8608 SDValue FIST = Vals.first, StackSlot = Vals.second;
8609 assert(FIST.getNode() && "Unexpected failure");
8611 if (StackSlot.getNode())
8613 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(),
8614 FIST, StackSlot, MachinePointerInfo(),
8615 false, false, false, 0);
8617 // The node is the result.
8621 static SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) {
8622 DebugLoc DL = Op.getDebugLoc();
8623 MVT VT = Op.getValueType().getSimpleVT();
8624 SDValue In = Op.getOperand(0);
8625 MVT SVT = In.getValueType().getSimpleVT();
8627 assert(SVT == MVT::v2f32 && "Only customize MVT::v2f32 type legalization!");
8629 return DAG.getNode(X86ISD::VFPEXT, DL, VT,
8630 DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4f32,
8631 In, DAG.getUNDEF(SVT)));
8634 SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) const {
8635 LLVMContext *Context = DAG.getContext();
8636 DebugLoc dl = Op.getDebugLoc();
8637 MVT VT = Op.getValueType().getSimpleVT();
8639 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8640 if (VT.isVector()) {
8641 EltVT = VT.getVectorElementType();
8642 NumElts = VT.getVectorNumElements();
8645 if (EltVT == MVT::f64)
8646 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8647 APInt(64, ~(1ULL << 63))));
8649 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8650 APInt(32, ~(1U << 31))));
8651 C = ConstantVector::getSplat(NumElts, C);
8652 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8653 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8654 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8655 MachinePointerInfo::getConstantPool(),
8656 false, false, false, Alignment);
8657 if (VT.isVector()) {
8658 MVT ANDVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8659 return DAG.getNode(ISD::BITCAST, dl, VT,
8660 DAG.getNode(ISD::AND, dl, ANDVT,
8661 DAG.getNode(ISD::BITCAST, dl, ANDVT,
8663 DAG.getNode(ISD::BITCAST, dl, ANDVT, Mask)));
8665 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask);
8668 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const {
8669 LLVMContext *Context = DAG.getContext();
8670 DebugLoc dl = Op.getDebugLoc();
8671 MVT VT = Op.getValueType().getSimpleVT();
8673 unsigned NumElts = VT == MVT::f64 ? 2 : 4;
8674 if (VT.isVector()) {
8675 EltVT = VT.getVectorElementType();
8676 NumElts = VT.getVectorNumElements();
8679 if (EltVT == MVT::f64)
8680 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEdouble,
8681 APInt(64, 1ULL << 63)));
8683 C = ConstantFP::get(*Context, APFloat(APFloat::IEEEsingle,
8684 APInt(32, 1U << 31)));
8685 C = ConstantVector::getSplat(NumElts, C);
8686 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy());
8687 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8688 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8689 MachinePointerInfo::getConstantPool(),
8690 false, false, false, Alignment);
8691 if (VT.isVector()) {
8692 MVT XORVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8693 return DAG.getNode(ISD::BITCAST, dl, VT,
8694 DAG.getNode(ISD::XOR, dl, XORVT,
8695 DAG.getNode(ISD::BITCAST, dl, XORVT,
8697 DAG.getNode(ISD::BITCAST, dl, XORVT, Mask)));
8700 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask);
8703 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
8704 LLVMContext *Context = DAG.getContext();
8705 SDValue Op0 = Op.getOperand(0);
8706 SDValue Op1 = Op.getOperand(1);
8707 DebugLoc dl = Op.getDebugLoc();
8708 MVT VT = Op.getValueType().getSimpleVT();
8709 MVT SrcVT = Op1.getValueType().getSimpleVT();
8711 // If second operand is smaller, extend it first.
8712 if (SrcVT.bitsLT(VT)) {
8713 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1);
8716 // And if it is bigger, shrink it first.
8717 if (SrcVT.bitsGT(VT)) {
8718 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));
8722 // At this point the operands and the result should have the same
8723 // type, and that won't be f80 since that is not custom lowered.
8725 // First get the sign bit of second operand.
8726 SmallVector<Constant*,4> CV;
8727 if (SrcVT == MVT::f64) {
8728 const fltSemantics &Sem = APFloat::IEEEdouble;
8729 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 1ULL << 63))));
8730 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
8732 const fltSemantics &Sem = APFloat::IEEEsingle;
8733 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 1U << 31))));
8734 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8735 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8736 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8738 Constant *C = ConstantVector::get(CV);
8739 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8740 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,
8741 MachinePointerInfo::getConstantPool(),
8742 false, false, false, 16);
8743 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);
8745 // Shift sign bit right or left if the two operands have different types.
8746 if (SrcVT.bitsGT(VT)) {
8747 // Op0 is MVT::f32, Op1 is MVT::f64.
8748 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit);
8749 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit,
8750 DAG.getConstant(32, MVT::i32));
8751 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit);
8752 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit,
8753 DAG.getIntPtrConstant(0));
8756 // Clear first operand sign bit.
8758 if (VT == MVT::f64) {
8759 const fltSemantics &Sem = APFloat::IEEEdouble;
8760 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
8761 APInt(64, ~(1ULL << 63)))));
8762 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(64, 0))));
8764 const fltSemantics &Sem = APFloat::IEEEsingle;
8765 CV.push_back(ConstantFP::get(*Context, APFloat(Sem,
8766 APInt(32, ~(1U << 31)))));
8767 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8768 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8769 CV.push_back(ConstantFP::get(*Context, APFloat(Sem, APInt(32, 0))));
8771 C = ConstantVector::get(CV);
8772 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
8773 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
8774 MachinePointerInfo::getConstantPool(),
8775 false, false, false, 16);
8776 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2);
8778 // Or the value with the sign bit.
8779 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);
8782 static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {
8783 SDValue N0 = Op.getOperand(0);
8784 DebugLoc dl = Op.getDebugLoc();
8785 MVT VT = Op.getValueType().getSimpleVT();
8787 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).
8788 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,
8789 DAG.getConstant(1, VT));
8790 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));
8793 // LowerVectorAllZeroTest - Check whether an OR'd tree is PTEST-able.
8795 SDValue X86TargetLowering::LowerVectorAllZeroTest(SDValue Op,
8796 SelectionDAG &DAG) const {
8797 assert(Op.getOpcode() == ISD::OR && "Only check OR'd tree.");
8799 if (!Subtarget->hasSSE41())
8802 if (!Op->hasOneUse())
8805 SDNode *N = Op.getNode();
8806 DebugLoc DL = N->getDebugLoc();
8808 SmallVector<SDValue, 8> Opnds;
8809 DenseMap<SDValue, unsigned> VecInMap;
8810 EVT VT = MVT::Other;
8812 // Recognize a special case where a vector is casted into wide integer to
8814 Opnds.push_back(N->getOperand(0));
8815 Opnds.push_back(N->getOperand(1));
8817 for (unsigned Slot = 0, e = Opnds.size(); Slot < e; ++Slot) {
8818 SmallVector<SDValue, 8>::const_iterator I = Opnds.begin() + Slot;
8819 // BFS traverse all OR'd operands.
8820 if (I->getOpcode() == ISD::OR) {
8821 Opnds.push_back(I->getOperand(0));
8822 Opnds.push_back(I->getOperand(1));
8823 // Re-evaluate the number of nodes to be traversed.
8824 e += 2; // 2 more nodes (LHS and RHS) are pushed.
8828 // Quit if a non-EXTRACT_VECTOR_ELT
8829 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8832 // Quit if without a constant index.
8833 SDValue Idx = I->getOperand(1);
8834 if (!isa<ConstantSDNode>(Idx))
8837 SDValue ExtractedFromVec = I->getOperand(0);
8838 DenseMap<SDValue, unsigned>::iterator M = VecInMap.find(ExtractedFromVec);
8839 if (M == VecInMap.end()) {
8840 VT = ExtractedFromVec.getValueType();
8841 // Quit if not 128/256-bit vector.
8842 if (!VT.is128BitVector() && !VT.is256BitVector())
8844 // Quit if not the same type.
8845 if (VecInMap.begin() != VecInMap.end() &&
8846 VT != VecInMap.begin()->first.getValueType())
8848 M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
8850 M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
8853 assert((VT.is128BitVector() || VT.is256BitVector()) &&
8854 "Not extracted from 128-/256-bit vector.");
8856 unsigned FullMask = (1U << VT.getVectorNumElements()) - 1U;
8857 SmallVector<SDValue, 8> VecIns;
8859 for (DenseMap<SDValue, unsigned>::const_iterator
8860 I = VecInMap.begin(), E = VecInMap.end(); I != E; ++I) {
8861 // Quit if not all elements are used.
8862 if (I->second != FullMask)
8864 VecIns.push_back(I->first);
8867 EVT TestVT = VT.is128BitVector() ? MVT::v2i64 : MVT::v4i64;
8869 // Cast all vectors into TestVT for PTEST.
8870 for (unsigned i = 0, e = VecIns.size(); i < e; ++i)
8871 VecIns[i] = DAG.getNode(ISD::BITCAST, DL, TestVT, VecIns[i]);
8873 // If more than one full vectors are evaluated, OR them first before PTEST.
8874 for (unsigned Slot = 0, e = VecIns.size(); e - Slot > 1; Slot += 2, e += 1) {
8875 // Each iteration will OR 2 nodes and append the result until there is only
8876 // 1 node left, i.e. the final OR'd value of all vectors.
8877 SDValue LHS = VecIns[Slot];
8878 SDValue RHS = VecIns[Slot + 1];
8879 VecIns.push_back(DAG.getNode(ISD::OR, DL, TestVT, LHS, RHS));
8882 return DAG.getNode(X86ISD::PTEST, DL, MVT::i32,
8883 VecIns.back(), VecIns.back());
8886 /// Emit nodes that will be selected as "test Op0,Op0", or something
8888 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC,
8889 SelectionDAG &DAG) const {
8890 DebugLoc dl = Op.getDebugLoc();
8892 // CF and OF aren't always set the way we want. Determine which
8893 // of these we need.
8894 bool NeedCF = false;
8895 bool NeedOF = false;
8898 case X86::COND_A: case X86::COND_AE:
8899 case X86::COND_B: case X86::COND_BE:
8902 case X86::COND_G: case X86::COND_GE:
8903 case X86::COND_L: case X86::COND_LE:
8904 case X86::COND_O: case X86::COND_NO:
8909 // See if we can use the EFLAGS value from the operand instead of
8910 // doing a separate TEST. TEST always sets OF and CF to 0, so unless
8911 // we prove that the arithmetic won't overflow, we can't use OF or CF.
8912 if (Op.getResNo() != 0 || NeedOF || NeedCF)
8913 // Emit a CMP with 0, which is the TEST pattern.
8914 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
8915 DAG.getConstant(0, Op.getValueType()));
8917 unsigned Opcode = 0;
8918 unsigned NumOperands = 0;
8920 // Truncate operations may prevent the merge of the SETCC instruction
8921 // and the arithmetic intruction before it. Attempt to truncate the operands
8922 // of the arithmetic instruction and use a reduced bit-width instruction.
8923 bool NeedTruncation = false;
8924 SDValue ArithOp = Op;
8925 if (Op->getOpcode() == ISD::TRUNCATE && Op->hasOneUse()) {
8926 SDValue Arith = Op->getOperand(0);
8927 // Both the trunc and the arithmetic op need to have one user each.
8928 if (Arith->hasOneUse())
8929 switch (Arith.getOpcode()) {
8936 NeedTruncation = true;
8942 // NOTICE: In the code below we use ArithOp to hold the arithmetic operation
8943 // which may be the result of a CAST. We use the variable 'Op', which is the
8944 // non-casted variable when we check for possible users.
8945 switch (ArithOp.getOpcode()) {
8947 // Due to an isel shortcoming, be conservative if this add is likely to be
8948 // selected as part of a load-modify-store instruction. When the root node
8949 // in a match is a store, isel doesn't know how to remap non-chain non-flag
8950 // uses of other nodes in the match, such as the ADD in this case. This
8951 // leads to the ADD being left around and reselected, with the result being
8952 // two adds in the output. Alas, even if none our users are stores, that
8953 // doesn't prove we're O.K. Ergo, if we have any parents that aren't
8954 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require
8955 // climbing the DAG back to the root, and it doesn't seem to be worth the
8957 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8958 UE = Op.getNode()->use_end(); UI != UE; ++UI)
8959 if (UI->getOpcode() != ISD::CopyToReg &&
8960 UI->getOpcode() != ISD::SETCC &&
8961 UI->getOpcode() != ISD::STORE)
8964 if (ConstantSDNode *C =
8965 dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
8966 // An add of one will be selected as an INC.
8967 if (C->getAPIntValue() == 1) {
8968 Opcode = X86ISD::INC;
8973 // An add of negative one (subtract of one) will be selected as a DEC.
8974 if (C->getAPIntValue().isAllOnesValue()) {
8975 Opcode = X86ISD::DEC;
8981 // Otherwise use a regular EFLAGS-setting add.
8982 Opcode = X86ISD::ADD;
8986 // If the primary and result isn't used, don't bother using X86ISD::AND,
8987 // because a TEST instruction will be better.
8988 bool NonFlagUse = false;
8989 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
8990 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
8992 unsigned UOpNo = UI.getOperandNo();
8993 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) {
8994 // Look pass truncate.
8995 UOpNo = User->use_begin().getOperandNo();
8996 User = *User->use_begin();
8999 if (User->getOpcode() != ISD::BRCOND &&
9000 User->getOpcode() != ISD::SETCC &&
9001 !(User->getOpcode() == ISD::SELECT && UOpNo == 0)) {
9014 // Due to the ISEL shortcoming noted above, be conservative if this op is
9015 // likely to be selected as part of a load-modify-store instruction.
9016 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
9017 UE = Op.getNode()->use_end(); UI != UE; ++UI)
9018 if (UI->getOpcode() == ISD::STORE)
9021 // Otherwise use a regular EFLAGS-setting instruction.
9022 switch (ArithOp.getOpcode()) {
9023 default: llvm_unreachable("unexpected operator!");
9024 case ISD::SUB: Opcode = X86ISD::SUB; break;
9025 case ISD::XOR: Opcode = X86ISD::XOR; break;
9026 case ISD::AND: Opcode = X86ISD::AND; break;
9028 if (!NeedTruncation && (X86CC == X86::COND_E || X86CC == X86::COND_NE)) {
9029 SDValue EFLAGS = LowerVectorAllZeroTest(Op, DAG);
9030 if (EFLAGS.getNode())
9033 Opcode = X86ISD::OR;
9047 return SDValue(Op.getNode(), 1);
9053 // If we found that truncation is beneficial, perform the truncation and
9055 if (NeedTruncation) {
9056 EVT VT = Op.getValueType();
9057 SDValue WideVal = Op->getOperand(0);
9058 EVT WideVT = WideVal.getValueType();
9059 unsigned ConvertedOp = 0;
9060 // Use a target machine opcode to prevent further DAGCombine
9061 // optimizations that may separate the arithmetic operations
9062 // from the setcc node.
9063 switch (WideVal.getOpcode()) {
9065 case ISD::ADD: ConvertedOp = X86ISD::ADD; break;
9066 case ISD::SUB: ConvertedOp = X86ISD::SUB; break;
9067 case ISD::AND: ConvertedOp = X86ISD::AND; break;
9068 case ISD::OR: ConvertedOp = X86ISD::OR; break;
9069 case ISD::XOR: ConvertedOp = X86ISD::XOR; break;
9073 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9074 if (TLI.isOperationLegal(WideVal.getOpcode(), WideVT)) {
9075 SDValue V0 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(0));
9076 SDValue V1 = DAG.getNode(ISD::TRUNCATE, dl, VT, WideVal.getOperand(1));
9077 Op = DAG.getNode(ConvertedOp, dl, VT, V0, V1);
9083 // Emit a CMP with 0, which is the TEST pattern.
9084 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,
9085 DAG.getConstant(0, Op.getValueType()));
9087 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
9088 SmallVector<SDValue, 4> Ops;
9089 for (unsigned i = 0; i != NumOperands; ++i)
9090 Ops.push_back(Op.getOperand(i));
9092 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands);
9093 DAG.ReplaceAllUsesWith(Op, New);
9094 return SDValue(New.getNode(), 1);
9097 /// Emit nodes that will be selected as "cmp Op0,Op1", or something
9099 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
9100 SelectionDAG &DAG) const {
9101 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1))
9102 if (C->getAPIntValue() == 0)
9103 return EmitTest(Op0, X86CC, DAG);
9105 DebugLoc dl = Op0.getDebugLoc();
9106 if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
9107 Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
9108 // Use SUB instead of CMP to enable CSE between SUB and CMP.
9109 SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);
9110 SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,
9112 return SDValue(Sub.getNode(), 1);
9114 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1);
9117 /// Convert a comparison if required by the subtarget.
9118 SDValue X86TargetLowering::ConvertCmpIfNecessary(SDValue Cmp,
9119 SelectionDAG &DAG) const {
9120 // If the subtarget does not support the FUCOMI instruction, floating-point
9121 // comparisons have to be converted.
9122 if (Subtarget->hasCMov() ||
9123 Cmp.getOpcode() != X86ISD::CMP ||
9124 !Cmp.getOperand(0).getValueType().isFloatingPoint() ||
9125 !Cmp.getOperand(1).getValueType().isFloatingPoint())
9128 // The instruction selector will select an FUCOM instruction instead of
9129 // FUCOMI, which writes the comparison result to FPSW instead of EFLAGS. Hence
9130 // build an SDNode sequence that transfers the result from FPSW into EFLAGS:
9131 // (X86sahf (trunc (srl (X86fp_stsw (trunc (X86cmp ...)), 8))))
9132 DebugLoc dl = Cmp.getDebugLoc();
9133 SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);
9134 SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);
9135 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,
9136 DAG.getConstant(8, MVT::i8));
9137 SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);
9138 return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);
9141 static bool isAllOnes(SDValue V) {
9142 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9143 return C && C->isAllOnesValue();
9146 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node
9147 /// if it's possible.
9148 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
9149 DebugLoc dl, SelectionDAG &DAG) const {
9150 SDValue Op0 = And.getOperand(0);
9151 SDValue Op1 = And.getOperand(1);
9152 if (Op0.getOpcode() == ISD::TRUNCATE)
9153 Op0 = Op0.getOperand(0);
9154 if (Op1.getOpcode() == ISD::TRUNCATE)
9155 Op1 = Op1.getOperand(0);
9158 if (Op1.getOpcode() == ISD::SHL)
9159 std::swap(Op0, Op1);
9160 if (Op0.getOpcode() == ISD::SHL) {
9161 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0)))
9162 if (And00C->getZExtValue() == 1) {
9163 // If we looked past a truncate, check that it's only truncating away
9165 unsigned BitWidth = Op0.getValueSizeInBits();
9166 unsigned AndBitWidth = And.getValueSizeInBits();
9167 if (BitWidth > AndBitWidth) {
9169 DAG.ComputeMaskedBits(Op0, Zeros, Ones);
9170 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
9174 RHS = Op0.getOperand(1);
9176 } else if (Op1.getOpcode() == ISD::Constant) {
9177 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
9178 uint64_t AndRHSVal = AndRHS->getZExtValue();
9179 SDValue AndLHS = Op0;
9181 if (AndRHSVal == 1 && AndLHS.getOpcode() == ISD::SRL) {
9182 LHS = AndLHS.getOperand(0);
9183 RHS = AndLHS.getOperand(1);
9186 // Use BT if the immediate can't be encoded in a TEST instruction.
9187 if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {
9189 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());
9193 if (LHS.getNode()) {
9194 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT
9195 // instruction. Since the shift amount is in-range-or-undefined, we know
9196 // that doing a bittest on the i32 value is ok. We extend to i32 because
9197 // the encoding for the i16 version is larger than the i32 version.
9198 // Also promote i16 to i32 for performance / code size reason.
9199 if (LHS.getValueType() == MVT::i8 ||
9200 LHS.getValueType() == MVT::i16)
9201 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS);
9203 // If the operand types disagree, extend the shift amount to match. Since
9204 // BT ignores high bits (like shifts) we can use anyextend.
9205 if (LHS.getValueType() != RHS.getValueType())
9206 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS);
9208 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);
9209 X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
9210 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9211 DAG.getConstant(Cond, MVT::i8), BT);
9217 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128
9218 // ones, and then concatenate the result back.
9219 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) {
9220 MVT VT = Op.getValueType().getSimpleVT();
9222 assert(VT.is256BitVector() && Op.getOpcode() == ISD::SETCC &&
9223 "Unsupported value type for operation");
9225 unsigned NumElems = VT.getVectorNumElements();
9226 DebugLoc dl = Op.getDebugLoc();
9227 SDValue CC = Op.getOperand(2);
9229 // Extract the LHS vectors
9230 SDValue LHS = Op.getOperand(0);
9231 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
9232 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
9234 // Extract the RHS vectors
9235 SDValue RHS = Op.getOperand(1);
9236 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
9237 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
9239 // Issue the operation on the smaller types and concatenate the result back
9240 MVT EltVT = VT.getVectorElementType();
9241 MVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
9242 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
9243 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC),
9244 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC));
9247 static SDValue LowerVSETCC(SDValue Op, const X86Subtarget *Subtarget,
9248 SelectionDAG &DAG) {
9250 SDValue Op0 = Op.getOperand(0);
9251 SDValue Op1 = Op.getOperand(1);
9252 SDValue CC = Op.getOperand(2);
9253 MVT VT = Op.getValueType().getSimpleVT();
9254 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
9255 bool isFP = Op.getOperand(1).getValueType().getSimpleVT().isFloatingPoint();
9256 DebugLoc dl = Op.getDebugLoc();
9260 MVT EltVT = Op0.getValueType().getVectorElementType().getSimpleVT();
9261 assert(EltVT == MVT::f32 || EltVT == MVT::f64);
9267 // SSE Condition code mapping:
9276 switch (SetCCOpcode) {
9277 default: llvm_unreachable("Unexpected SETCC condition");
9279 case ISD::SETEQ: SSECC = 0; break;
9281 case ISD::SETGT: Swap = true; // Fallthrough
9283 case ISD::SETOLT: SSECC = 1; break;
9285 case ISD::SETGE: Swap = true; // Fallthrough
9287 case ISD::SETOLE: SSECC = 2; break;
9288 case ISD::SETUO: SSECC = 3; break;
9290 case ISD::SETNE: SSECC = 4; break;
9291 case ISD::SETULE: Swap = true; // Fallthrough
9292 case ISD::SETUGE: SSECC = 5; break;
9293 case ISD::SETULT: Swap = true; // Fallthrough
9294 case ISD::SETUGT: SSECC = 6; break;
9295 case ISD::SETO: SSECC = 7; break;
9297 case ISD::SETONE: SSECC = 8; break;
9300 std::swap(Op0, Op1);
9302 // In the two special cases we can't handle, emit two comparisons.
9305 unsigned CombineOpc;
9306 if (SetCCOpcode == ISD::SETUEQ) {
9307 CC0 = 3; CC1 = 0; CombineOpc = ISD::OR;
9309 assert(SetCCOpcode == ISD::SETONE);
9310 CC0 = 7; CC1 = 4; CombineOpc = ISD::AND;
9313 SDValue Cmp0 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9314 DAG.getConstant(CC0, MVT::i8));
9315 SDValue Cmp1 = DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9316 DAG.getConstant(CC1, MVT::i8));
9317 return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);
9319 // Handle all other FP comparisons here.
9320 return DAG.getNode(X86ISD::CMPP, dl, VT, Op0, Op1,
9321 DAG.getConstant(SSECC, MVT::i8));
9324 // Break 256-bit integer vector compare into smaller ones.
9325 if (VT.is256BitVector() && !Subtarget->hasInt256())
9326 return Lower256IntVSETCC(Op, DAG);
9328 // We are handling one of the integer comparisons here. Since SSE only has
9329 // GT and EQ comparisons for integer, swapping operands and multiple
9330 // operations may be required for some comparisons.
9332 bool Swap = false, Invert = false, FlipSigns = false;
9334 switch (SetCCOpcode) {
9335 default: llvm_unreachable("Unexpected SETCC condition");
9336 case ISD::SETNE: Invert = true;
9337 case ISD::SETEQ: Opc = X86ISD::PCMPEQ; break;
9338 case ISD::SETLT: Swap = true;
9339 case ISD::SETGT: Opc = X86ISD::PCMPGT; break;
9340 case ISD::SETGE: Swap = true;
9341 case ISD::SETLE: Opc = X86ISD::PCMPGT; Invert = true; break;
9342 case ISD::SETULT: Swap = true;
9343 case ISD::SETUGT: Opc = X86ISD::PCMPGT; FlipSigns = true; break;
9344 case ISD::SETUGE: Swap = true;
9345 case ISD::SETULE: Opc = X86ISD::PCMPGT; FlipSigns = true; Invert = true; break;
9348 std::swap(Op0, Op1);
9350 // Check that the operation in question is available (most are plain SSE2,
9351 // but PCMPGTQ and PCMPEQQ have different requirements).
9352 if (VT == MVT::v2i64) {
9353 if (Opc == X86ISD::PCMPGT && !Subtarget->hasSSE42()) {
9354 assert(Subtarget->hasSSE2() && "Don't know how to lower!");
9356 // First cast everything to the right type.
9357 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9358 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9360 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9361 // bits of the inputs before performing those operations.
9363 SDValue SB = DAG.getConstant(0x80000000U, MVT::v4i32);
9364 Op0 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op0, SB);
9365 Op1 = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Op1, SB);
9368 // Emulate PCMPGTQ with (hi1 > hi2) | ((hi1 == hi2) & (lo1 > lo2))
9369 SDValue GT = DAG.getNode(X86ISD::PCMPGT, dl, MVT::v4i32, Op0, Op1);
9370 SDValue EQ = DAG.getNode(X86ISD::PCMPEQ, dl, MVT::v4i32, Op0, Op1);
9372 // Create masks for only the low parts/high parts of the 64 bit integers.
9373 const int MaskHi[] = { 1, 1, 3, 3 };
9374 const int MaskLo[] = { 0, 0, 2, 2 };
9375 SDValue EQHi = DAG.getVectorShuffle(MVT::v4i32, dl, EQ, EQ, MaskHi);
9376 SDValue GTLo = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskLo);
9377 SDValue GTHi = DAG.getVectorShuffle(MVT::v4i32, dl, GT, GT, MaskHi);
9379 SDValue Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, EQHi, GTLo);
9380 Result = DAG.getNode(ISD::OR, dl, MVT::v4i32, Result, GTHi);
9383 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9385 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9388 if (Opc == X86ISD::PCMPEQ && !Subtarget->hasSSE41()) {
9389 // If pcmpeqq is missing but pcmpeqd is available synthesize pcmpeqq with
9390 // pcmpeqd + pshufd + pand.
9391 assert(Subtarget->hasSSE2() && !FlipSigns && "Don't know how to lower!");
9393 // First cast everything to the right type.
9394 Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op0);
9395 Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op1);
9398 SDValue Result = DAG.getNode(Opc, dl, MVT::v4i32, Op0, Op1);
9400 // Make sure the lower and upper halves are both all-ones.
9401 const int Mask[] = { 1, 0, 3, 2 };
9402 SDValue Shuf = DAG.getVectorShuffle(MVT::v4i32, dl, Result, Result, Mask);
9403 Result = DAG.getNode(ISD::AND, dl, MVT::v4i32, Result, Shuf);
9406 Result = DAG.getNOT(dl, Result, MVT::v4i32);
9408 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
9412 // Since SSE has no unsigned integer comparisons, we need to flip the sign
9413 // bits of the inputs before performing those operations.
9415 EVT EltVT = VT.getVectorElementType();
9416 SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);
9417 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);
9418 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);
9421 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
9423 // If the logical-not of the result is required, perform that now.
9425 Result = DAG.getNOT(dl, Result, VT);
9430 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
9432 MVT VT = Op.getValueType().getSimpleVT();
9434 if (VT.isVector()) return LowerVSETCC(Op, Subtarget, DAG);
9436 assert(VT == MVT::i8 && "SetCC type must be 8-bit integer");
9437 SDValue Op0 = Op.getOperand(0);
9438 SDValue Op1 = Op.getOperand(1);
9439 DebugLoc dl = Op.getDebugLoc();
9440 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
9442 // Optimize to BT if possible.
9443 // Lower (X & (1 << N)) == 0 to BT(X, N).
9444 // Lower ((X >>u N) & 1) != 0 to BT(X, N).
9445 // Lower ((X >>s N) & 1) != 0 to BT(X, N).
9446 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() &&
9447 Op1.getOpcode() == ISD::Constant &&
9448 cast<ConstantSDNode>(Op1)->isNullValue() &&
9449 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9450 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG);
9451 if (NewSetCC.getNode())
9455 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of
9457 if (Op1.getOpcode() == ISD::Constant &&
9458 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 ||
9459 cast<ConstantSDNode>(Op1)->isNullValue()) &&
9460 (CC == ISD::SETEQ || CC == ISD::SETNE)) {
9462 // If the input is a setcc, then reuse the input setcc or use a new one with
9463 // the inverted condition.
9464 if (Op0.getOpcode() == X86ISD::SETCC) {
9465 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0);
9466 bool Invert = (CC == ISD::SETNE) ^
9467 cast<ConstantSDNode>(Op1)->isNullValue();
9468 if (!Invert) return Op0;
9470 CCode = X86::GetOppositeBranchCondition(CCode);
9471 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9472 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1));
9476 bool isFP = Op1.getValueType().getSimpleVT().isFloatingPoint();
9477 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);
9478 if (X86CC == X86::COND_INVALID)
9481 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG);
9482 EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);
9483 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
9484 DAG.getConstant(X86CC, MVT::i8), EFLAGS);
9487 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
9488 static bool isX86LogicalCmp(SDValue Op) {
9489 unsigned Opc = Op.getNode()->getOpcode();
9490 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI ||
9491 Opc == X86ISD::SAHF)
9493 if (Op.getResNo() == 1 &&
9494 (Opc == X86ISD::ADD ||
9495 Opc == X86ISD::SUB ||
9496 Opc == X86ISD::ADC ||
9497 Opc == X86ISD::SBB ||
9498 Opc == X86ISD::SMUL ||
9499 Opc == X86ISD::UMUL ||
9500 Opc == X86ISD::INC ||
9501 Opc == X86ISD::DEC ||
9502 Opc == X86ISD::OR ||
9503 Opc == X86ISD::XOR ||
9504 Opc == X86ISD::AND))
9507 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL)
9513 static bool isZero(SDValue V) {
9514 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V);
9515 return C && C->isNullValue();
9518 static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
9519 if (V.getOpcode() != ISD::TRUNCATE)
9522 SDValue VOp0 = V.getOperand(0);
9523 unsigned InBits = VOp0.getValueSizeInBits();
9524 unsigned Bits = V.getValueSizeInBits();
9525 return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
9528 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
9529 bool addTest = true;
9530 SDValue Cond = Op.getOperand(0);
9531 SDValue Op1 = Op.getOperand(1);
9532 SDValue Op2 = Op.getOperand(2);
9533 DebugLoc DL = Op.getDebugLoc();
9536 if (Cond.getOpcode() == ISD::SETCC) {
9537 SDValue NewCond = LowerSETCC(Cond, DAG);
9538 if (NewCond.getNode())
9542 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y
9543 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y
9544 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y
9545 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y
9546 if (Cond.getOpcode() == X86ISD::SETCC &&
9547 Cond.getOperand(1).getOpcode() == X86ISD::CMP &&
9548 isZero(Cond.getOperand(1).getOperand(1))) {
9549 SDValue Cmp = Cond.getOperand(1);
9551 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
9553 if ((isAllOnes(Op1) || isAllOnes(Op2)) &&
9554 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
9555 SDValue Y = isAllOnes(Op2) ? Op1 : Op2;
9557 SDValue CmpOp0 = Cmp.getOperand(0);
9558 // Apply further optimizations for special cases
9559 // (select (x != 0), -1, 0) -> neg & sbb
9560 // (select (x == 0), 0, -1) -> neg & sbb
9561 if (ConstantSDNode *YC = dyn_cast<ConstantSDNode>(Y))
9562 if (YC->isNullValue() &&
9563 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) {
9564 SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
9565 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,
9566 DAG.getConstant(0, CmpOp0.getValueType()),
9568 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9569 DAG.getConstant(X86::COND_B, MVT::i8),
9570 SDValue(Neg.getNode(), 1));
9574 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,
9575 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));
9576 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9578 SDValue Res = // Res = 0 or -1.
9579 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9580 DAG.getConstant(X86::COND_B, MVT::i8), Cmp);
9582 if (isAllOnes(Op1) != (CondCode == X86::COND_E))
9583 Res = DAG.getNOT(DL, Res, Res.getValueType());
9585 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2);
9586 if (N2C == 0 || !N2C->isNullValue())
9587 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y);
9592 // Look past (and (setcc_carry (cmp ...)), 1).
9593 if (Cond.getOpcode() == ISD::AND &&
9594 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9595 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9596 if (C && C->getAPIntValue() == 1)
9597 Cond = Cond.getOperand(0);
9600 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9601 // setting operand in place of the X86ISD::SETCC.
9602 unsigned CondOpcode = Cond.getOpcode();
9603 if (CondOpcode == X86ISD::SETCC ||
9604 CondOpcode == X86ISD::SETCC_CARRY) {
9605 CC = Cond.getOperand(0);
9607 SDValue Cmp = Cond.getOperand(1);
9608 unsigned Opc = Cmp.getOpcode();
9609 MVT VT = Op.getValueType().getSimpleVT();
9611 bool IllegalFPCMov = false;
9612 if (VT.isFloatingPoint() && !VT.isVector() &&
9613 !isScalarFPTypeInSSEReg(VT)) // FPStack?
9614 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
9616 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
9617 Opc == X86ISD::BT) { // FIXME
9621 } else if (CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9622 CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9623 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9624 Cond.getOperand(0).getValueType() != MVT::i8)) {
9625 SDValue LHS = Cond.getOperand(0);
9626 SDValue RHS = Cond.getOperand(1);
9630 switch (CondOpcode) {
9631 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9632 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9633 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9634 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9635 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9636 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9637 default: llvm_unreachable("unexpected overflowing operator");
9639 if (CondOpcode == ISD::UMULO)
9640 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9643 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9645 SDValue X86Op = DAG.getNode(X86Opcode, DL, VTs, LHS, RHS);
9647 if (CondOpcode == ISD::UMULO)
9648 Cond = X86Op.getValue(2);
9650 Cond = X86Op.getValue(1);
9652 CC = DAG.getConstant(X86Cond, MVT::i8);
9657 // Look pass the truncate if the high bits are known zero.
9658 if (isTruncWithZeroHighBitsInput(Cond, DAG))
9659 Cond = Cond.getOperand(0);
9661 // We know the result of AND is compared against zero. Try to match
9663 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
9664 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG);
9665 if (NewSetCC.getNode()) {
9666 CC = NewSetCC.getOperand(0);
9667 Cond = NewSetCC.getOperand(1);
9674 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9675 Cond = EmitTest(Cond, X86::COND_NE, DAG);
9678 // a < b ? -1 : 0 -> RES = ~setcc_carry
9679 // a < b ? 0 : -1 -> RES = setcc_carry
9680 // a >= b ? -1 : 0 -> RES = setcc_carry
9681 // a >= b ? 0 : -1 -> RES = ~setcc_carry
9682 if (Cond.getOpcode() == X86ISD::SUB) {
9683 Cond = ConvertCmpIfNecessary(Cond, DAG);
9684 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
9686 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
9687 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {
9688 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),
9689 DAG.getConstant(X86::COND_B, MVT::i8), Cond);
9690 if (isAllOnes(Op1) != (CondCode == X86::COND_B))
9691 return DAG.getNOT(DL, Res, Res.getValueType());
9696 // X86 doesn't have an i8 cmov. If both operands are the result of a truncate
9697 // widen the cmov and push the truncate through. This avoids introducing a new
9698 // branch during isel and doesn't add any extensions.
9699 if (Op.getValueType() == MVT::i8 &&
9700 Op1.getOpcode() == ISD::TRUNCATE && Op2.getOpcode() == ISD::TRUNCATE) {
9701 SDValue T1 = Op1.getOperand(0), T2 = Op2.getOperand(0);
9702 if (T1.getValueType() == T2.getValueType() &&
9703 // Blacklist CopyFromReg to avoid partial register stalls.
9704 T1.getOpcode() != ISD::CopyFromReg && T2.getOpcode()!=ISD::CopyFromReg){
9705 SDVTList VTs = DAG.getVTList(T1.getValueType(), MVT::Glue);
9706 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, VTs, T2, T1, CC, Cond);
9707 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov);
9711 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if
9712 // condition is true.
9713 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
9714 SDValue Ops[] = { Op2, Op1, CC, Cond };
9715 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
9718 SDValue X86TargetLowering::LowerSIGN_EXTEND(SDValue Op,
9719 SelectionDAG &DAG) const {
9720 MVT VT = Op->getValueType(0).getSimpleVT();
9721 SDValue In = Op->getOperand(0);
9722 MVT InVT = In.getValueType().getSimpleVT();
9723 DebugLoc dl = Op->getDebugLoc();
9725 if ((VT != MVT::v4i64 || InVT != MVT::v4i32) &&
9726 (VT != MVT::v8i32 || InVT != MVT::v8i16))
9729 if (Subtarget->hasInt256())
9730 return DAG.getNode(X86ISD::VSEXT_MOVL, dl, VT, In);
9732 // Optimize vectors in AVX mode
9733 // Sign extend v8i16 to v8i32 and
9736 // Divide input vector into two parts
9737 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
9738 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
9739 // concat the vectors to original VT
9741 unsigned NumElems = InVT.getVectorNumElements();
9742 SDValue Undef = DAG.getUNDEF(InVT);
9744 SmallVector<int,8> ShufMask1(NumElems, -1);
9745 for (unsigned i = 0; i != NumElems/2; ++i)
9748 SDValue OpLo = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask1[0]);
9750 SmallVector<int,8> ShufMask2(NumElems, -1);
9751 for (unsigned i = 0; i != NumElems/2; ++i)
9752 ShufMask2[i] = i + NumElems/2;
9754 SDValue OpHi = DAG.getVectorShuffle(InVT, dl, In, Undef, &ShufMask2[0]);
9756 MVT HalfVT = MVT::getVectorVT(VT.getScalarType(),
9757 VT.getVectorNumElements()/2);
9759 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
9760 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
9762 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, OpLo, OpHi);
9765 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
9766 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
9767 // from the AND / OR.
9768 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
9769 Opc = Op.getOpcode();
9770 if (Opc != ISD::OR && Opc != ISD::AND)
9772 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9773 Op.getOperand(0).hasOneUse() &&
9774 Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
9775 Op.getOperand(1).hasOneUse());
9778 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and
9779 // 1 and that the SETCC node has a single use.
9780 static bool isXor1OfSetCC(SDValue Op) {
9781 if (Op.getOpcode() != ISD::XOR)
9783 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
9784 if (N1C && N1C->getAPIntValue() == 1) {
9785 return Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
9786 Op.getOperand(0).hasOneUse();
9791 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
9792 bool addTest = true;
9793 SDValue Chain = Op.getOperand(0);
9794 SDValue Cond = Op.getOperand(1);
9795 SDValue Dest = Op.getOperand(2);
9796 DebugLoc dl = Op.getDebugLoc();
9798 bool Inverted = false;
9800 if (Cond.getOpcode() == ISD::SETCC) {
9801 // Check for setcc([su]{add,sub,mul}o == 0).
9802 if (cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETEQ &&
9803 isa<ConstantSDNode>(Cond.getOperand(1)) &&
9804 cast<ConstantSDNode>(Cond.getOperand(1))->isNullValue() &&
9805 Cond.getOperand(0).getResNo() == 1 &&
9806 (Cond.getOperand(0).getOpcode() == ISD::SADDO ||
9807 Cond.getOperand(0).getOpcode() == ISD::UADDO ||
9808 Cond.getOperand(0).getOpcode() == ISD::SSUBO ||
9809 Cond.getOperand(0).getOpcode() == ISD::USUBO ||
9810 Cond.getOperand(0).getOpcode() == ISD::SMULO ||
9811 Cond.getOperand(0).getOpcode() == ISD::UMULO)) {
9813 Cond = Cond.getOperand(0);
9815 SDValue NewCond = LowerSETCC(Cond, DAG);
9816 if (NewCond.getNode())
9821 // FIXME: LowerXALUO doesn't handle these!!
9822 else if (Cond.getOpcode() == X86ISD::ADD ||
9823 Cond.getOpcode() == X86ISD::SUB ||
9824 Cond.getOpcode() == X86ISD::SMUL ||
9825 Cond.getOpcode() == X86ISD::UMUL)
9826 Cond = LowerXALUO(Cond, DAG);
9829 // Look pass (and (setcc_carry (cmp ...)), 1).
9830 if (Cond.getOpcode() == ISD::AND &&
9831 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
9832 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
9833 if (C && C->getAPIntValue() == 1)
9834 Cond = Cond.getOperand(0);
9837 // If condition flag is set by a X86ISD::CMP, then use it as the condition
9838 // setting operand in place of the X86ISD::SETCC.
9839 unsigned CondOpcode = Cond.getOpcode();
9840 if (CondOpcode == X86ISD::SETCC ||
9841 CondOpcode == X86ISD::SETCC_CARRY) {
9842 CC = Cond.getOperand(0);
9844 SDValue Cmp = Cond.getOperand(1);
9845 unsigned Opc = Cmp.getOpcode();
9846 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp??
9847 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) {
9851 switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
9855 // These can only come from an arithmetic instruction with overflow,
9856 // e.g. SADDO, UADDO.
9857 Cond = Cond.getNode()->getOperand(1);
9863 CondOpcode = Cond.getOpcode();
9864 if (CondOpcode == ISD::UADDO || CondOpcode == ISD::SADDO ||
9865 CondOpcode == ISD::USUBO || CondOpcode == ISD::SSUBO ||
9866 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) &&
9867 Cond.getOperand(0).getValueType() != MVT::i8)) {
9868 SDValue LHS = Cond.getOperand(0);
9869 SDValue RHS = Cond.getOperand(1);
9873 switch (CondOpcode) {
9874 case ISD::UADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_B; break;
9875 case ISD::SADDO: X86Opcode = X86ISD::ADD; X86Cond = X86::COND_O; break;
9876 case ISD::USUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_B; break;
9877 case ISD::SSUBO: X86Opcode = X86ISD::SUB; X86Cond = X86::COND_O; break;
9878 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break;
9879 case ISD::SMULO: X86Opcode = X86ISD::SMUL; X86Cond = X86::COND_O; break;
9880 default: llvm_unreachable("unexpected overflowing operator");
9883 X86Cond = X86::GetOppositeBranchCondition((X86::CondCode)X86Cond);
9884 if (CondOpcode == ISD::UMULO)
9885 VTs = DAG.getVTList(LHS.getValueType(), LHS.getValueType(),
9888 VTs = DAG.getVTList(LHS.getValueType(), MVT::i32);
9890 SDValue X86Op = DAG.getNode(X86Opcode, dl, VTs, LHS, RHS);
9892 if (CondOpcode == ISD::UMULO)
9893 Cond = X86Op.getValue(2);
9895 Cond = X86Op.getValue(1);
9897 CC = DAG.getConstant(X86Cond, MVT::i8);
9901 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
9902 SDValue Cmp = Cond.getOperand(0).getOperand(1);
9903 if (CondOpc == ISD::OR) {
9904 // Also, recognize the pattern generated by an FCMP_UNE. We can emit
9905 // two branches instead of an explicit OR instruction with a
9907 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9908 isX86LogicalCmp(Cmp)) {
9909 CC = Cond.getOperand(0).getOperand(0);
9910 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9911 Chain, Dest, CC, Cmp);
9912 CC = Cond.getOperand(1).getOperand(0);
9916 } else { // ISD::AND
9917 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit
9918 // two branches instead of an explicit AND instruction with a
9919 // separate test. However, we only do this if this block doesn't
9920 // have a fall-through edge, because this requires an explicit
9921 // jmp when the condition is false.
9922 if (Cmp == Cond.getOperand(1).getOperand(1) &&
9923 isX86LogicalCmp(Cmp) &&
9924 Op.getNode()->hasOneUse()) {
9925 X86::CondCode CCode =
9926 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9927 CCode = X86::GetOppositeBranchCondition(CCode);
9928 CC = DAG.getConstant(CCode, MVT::i8);
9929 SDNode *User = *Op.getNode()->use_begin();
9930 // Look for an unconditional branch following this conditional branch.
9931 // We need this because we need to reverse the successors in order
9932 // to implement FCMP_OEQ.
9933 if (User->getOpcode() == ISD::BR) {
9934 SDValue FalseBB = User->getOperand(1);
9936 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9937 assert(NewBR == User);
9941 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9942 Chain, Dest, CC, Cmp);
9943 X86::CondCode CCode =
9944 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
9945 CCode = X86::GetOppositeBranchCondition(CCode);
9946 CC = DAG.getConstant(CCode, MVT::i8);
9952 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) {
9953 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition.
9954 // It should be transformed during dag combiner except when the condition
9955 // is set by a arithmetics with overflow node.
9956 X86::CondCode CCode =
9957 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
9958 CCode = X86::GetOppositeBranchCondition(CCode);
9959 CC = DAG.getConstant(CCode, MVT::i8);
9960 Cond = Cond.getOperand(0).getOperand(1);
9962 } else if (Cond.getOpcode() == ISD::SETCC &&
9963 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETOEQ) {
9964 // For FCMP_OEQ, we can emit
9965 // two branches instead of an explicit AND instruction with a
9966 // separate test. However, we only do this if this block doesn't
9967 // have a fall-through edge, because this requires an explicit
9968 // jmp when the condition is false.
9969 if (Op.getNode()->hasOneUse()) {
9970 SDNode *User = *Op.getNode()->use_begin();
9971 // Look for an unconditional branch following this conditional branch.
9972 // We need this because we need to reverse the successors in order
9973 // to implement FCMP_OEQ.
9974 if (User->getOpcode() == ISD::BR) {
9975 SDValue FalseBB = User->getOperand(1);
9977 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
9978 assert(NewBR == User);
9982 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
9983 Cond.getOperand(0), Cond.getOperand(1));
9984 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
9985 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
9986 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
9987 Chain, Dest, CC, Cmp);
9988 CC = DAG.getConstant(X86::COND_P, MVT::i8);
9993 } else if (Cond.getOpcode() == ISD::SETCC &&
9994 cast<CondCodeSDNode>(Cond.getOperand(2))->get() == ISD::SETUNE) {
9995 // For FCMP_UNE, we can emit
9996 // two branches instead of an explicit AND instruction with a
9997 // separate test. However, we only do this if this block doesn't
9998 // have a fall-through edge, because this requires an explicit
9999 // jmp when the condition is false.
10000 if (Op.getNode()->hasOneUse()) {
10001 SDNode *User = *Op.getNode()->use_begin();
10002 // Look for an unconditional branch following this conditional branch.
10003 // We need this because we need to reverse the successors in order
10004 // to implement FCMP_UNE.
10005 if (User->getOpcode() == ISD::BR) {
10006 SDValue FalseBB = User->getOperand(1);
10008 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest);
10009 assert(NewBR == User);
10012 SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,
10013 Cond.getOperand(0), Cond.getOperand(1));
10014 Cmp = ConvertCmpIfNecessary(Cmp, DAG);
10015 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10016 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10017 Chain, Dest, CC, Cmp);
10018 CC = DAG.getConstant(X86::COND_NP, MVT::i8);
10028 // Look pass the truncate if the high bits are known zero.
10029 if (isTruncWithZeroHighBitsInput(Cond, DAG))
10030 Cond = Cond.getOperand(0);
10032 // We know the result of AND is compared against zero. Try to match
10034 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
10035 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
10036 if (NewSetCC.getNode()) {
10037 CC = NewSetCC.getOperand(0);
10038 Cond = NewSetCC.getOperand(1);
10045 CC = DAG.getConstant(X86::COND_NE, MVT::i8);
10046 Cond = EmitTest(Cond, X86::COND_NE, DAG);
10048 Cond = ConvertCmpIfNecessary(Cond, DAG);
10049 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),
10050 Chain, Dest, CC, Cond);
10053 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets.
10054 // Calls to _alloca is needed to probe the stack when allocating more than 4k
10055 // bytes in one go. Touching the stack at 4K increments is necessary to ensure
10056 // that the guard pages used by the OS virtual memory manager are allocated in
10057 // correct sequence.
10059 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
10060 SelectionDAG &DAG) const {
10061 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() ||
10062 getTargetMachine().Options.EnableSegmentedStacks) &&
10063 "This should be used only on Windows targets or when segmented stacks "
10065 assert(!Subtarget->isTargetEnvMacho() && "Not implemented");
10066 DebugLoc dl = Op.getDebugLoc();
10069 SDValue Chain = Op.getOperand(0);
10070 SDValue Size = Op.getOperand(1);
10071 // FIXME: Ensure alignment here
10073 bool Is64Bit = Subtarget->is64Bit();
10074 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32;
10076 if (getTargetMachine().Options.EnableSegmentedStacks) {
10077 MachineFunction &MF = DAG.getMachineFunction();
10078 MachineRegisterInfo &MRI = MF.getRegInfo();
10081 // The 64 bit implementation of segmented stacks needs to clobber both r10
10082 // r11. This makes it impossible to use it along with nested parameters.
10083 const Function *F = MF.getFunction();
10085 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
10087 if (I->hasNestAttr())
10088 report_fatal_error("Cannot use segmented stacks with functions that "
10089 "have nested arguments.");
10092 const TargetRegisterClass *AddrRegClass =
10093 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32);
10094 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass);
10095 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size);
10096 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain,
10097 DAG.getRegister(Vreg, SPTy));
10098 SDValue Ops1[2] = { Value, Chain };
10099 return DAG.getMergeValues(Ops1, 2, dl);
10102 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX);
10104 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag);
10105 Flag = Chain.getValue(1);
10106 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10108 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag);
10109 Flag = Chain.getValue(1);
10111 Chain = DAG.getCopyFromReg(Chain, dl, RegInfo->getStackRegister(),
10114 SDValue Ops1[2] = { Chain.getValue(0), Chain };
10115 return DAG.getMergeValues(Ops1, 2, dl);
10119 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
10120 MachineFunction &MF = DAG.getMachineFunction();
10121 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
10123 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10124 DebugLoc DL = Op.getDebugLoc();
10126 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) {
10127 // vastart just stores the address of the VarArgsFrameIndex slot into the
10128 // memory location argument.
10129 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10131 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1),
10132 MachinePointerInfo(SV), false, false, 0);
10136 // gp_offset (0 - 6 * 8)
10137 // fp_offset (48 - 48 + 8 * 16)
10138 // overflow_arg_area (point to parameters coming in memory).
10140 SmallVector<SDValue, 8> MemOps;
10141 SDValue FIN = Op.getOperand(1);
10143 SDValue Store = DAG.getStore(Op.getOperand(0), DL,
10144 DAG.getConstant(FuncInfo->getVarArgsGPOffset(),
10146 FIN, MachinePointerInfo(SV), false, false, 0);
10147 MemOps.push_back(Store);
10150 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10151 FIN, DAG.getIntPtrConstant(4));
10152 Store = DAG.getStore(Op.getOperand(0), DL,
10153 DAG.getConstant(FuncInfo->getVarArgsFPOffset(),
10155 FIN, MachinePointerInfo(SV, 4), false, false, 0);
10156 MemOps.push_back(Store);
10158 // Store ptr to overflow_arg_area
10159 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10160 FIN, DAG.getIntPtrConstant(4));
10161 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
10163 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,
10164 MachinePointerInfo(SV, 8),
10166 MemOps.push_back(Store);
10168 // Store ptr to reg_save_area.
10169 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),
10170 FIN, DAG.getIntPtrConstant(8));
10171 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),
10173 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,
10174 MachinePointerInfo(SV, 16), false, false, 0);
10175 MemOps.push_back(Store);
10176 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
10177 &MemOps[0], MemOps.size());
10180 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
10181 assert(Subtarget->is64Bit() &&
10182 "LowerVAARG only handles 64-bit va_arg!");
10183 assert((Subtarget->isTargetLinux() ||
10184 Subtarget->isTargetDarwin()) &&
10185 "Unhandled target in LowerVAARG");
10186 assert(Op.getNode()->getNumOperands() == 4);
10187 SDValue Chain = Op.getOperand(0);
10188 SDValue SrcPtr = Op.getOperand(1);
10189 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
10190 unsigned Align = Op.getConstantOperandVal(3);
10191 DebugLoc dl = Op.getDebugLoc();
10193 EVT ArgVT = Op.getNode()->getValueType(0);
10194 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10195 uint32_t ArgSize = getDataLayout()->getTypeAllocSize(ArgTy);
10198 // Decide which area this value should be read from.
10199 // TODO: Implement the AMD64 ABI in its entirety. This simple
10200 // selection mechanism works only for the basic types.
10201 if (ArgVT == MVT::f80) {
10202 llvm_unreachable("va_arg for f80 not yet implemented");
10203 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) {
10204 ArgMode = 2; // Argument passed in XMM register. Use fp_offset.
10205 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) {
10206 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset.
10208 llvm_unreachable("Unhandled argument type in LowerVAARG");
10211 if (ArgMode == 2) {
10212 // Sanity Check: Make sure using fp_offset makes sense.
10213 assert(!getTargetMachine().Options.UseSoftFloat &&
10214 !(DAG.getMachineFunction()
10215 .getFunction()->getAttributes()
10216 .hasAttribute(AttributeSet::FunctionIndex,
10217 Attribute::NoImplicitFloat)) &&
10218 Subtarget->hasSSE1());
10221 // Insert VAARG_64 node into the DAG
10222 // VAARG_64 returns two values: Variable Argument Address, Chain
10223 SmallVector<SDValue, 11> InstOps;
10224 InstOps.push_back(Chain);
10225 InstOps.push_back(SrcPtr);
10226 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32));
10227 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8));
10228 InstOps.push_back(DAG.getConstant(Align, MVT::i32));
10229 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);
10230 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,
10231 VTs, &InstOps[0], InstOps.size(),
10233 MachinePointerInfo(SV),
10235 /*Volatile=*/false,
10237 /*WriteMem=*/true);
10238 Chain = VAARG.getValue(1);
10240 // Load the next argument and return it
10241 return DAG.getLoad(ArgVT, dl,
10244 MachinePointerInfo(),
10245 false, false, false, 0);
10248 static SDValue LowerVACOPY(SDValue Op, const X86Subtarget *Subtarget,
10249 SelectionDAG &DAG) {
10250 // X86-64 va_list is a struct { i32, i32, i8*, i8* }.
10251 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!");
10252 SDValue Chain = Op.getOperand(0);
10253 SDValue DstPtr = Op.getOperand(1);
10254 SDValue SrcPtr = Op.getOperand(2);
10255 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
10256 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
10257 DebugLoc DL = Op.getDebugLoc();
10259 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
10260 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
10262 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
10265 // getTargetVShiftNode - Handle vector element shifts where the shift amount
10266 // may or may not be a constant. Takes immediate version of shift as input.
10267 static SDValue getTargetVShiftNode(unsigned Opc, DebugLoc dl, EVT VT,
10268 SDValue SrcOp, SDValue ShAmt,
10269 SelectionDAG &DAG) {
10270 assert(ShAmt.getValueType() == MVT::i32 && "ShAmt is not i32");
10272 if (isa<ConstantSDNode>(ShAmt)) {
10273 // Constant may be a TargetConstant. Use a regular constant.
10274 uint32_t ShiftAmt = cast<ConstantSDNode>(ShAmt)->getZExtValue();
10276 default: llvm_unreachable("Unknown target vector shift node");
10277 case X86ISD::VSHLI:
10278 case X86ISD::VSRLI:
10279 case X86ISD::VSRAI:
10280 return DAG.getNode(Opc, dl, VT, SrcOp,
10281 DAG.getConstant(ShiftAmt, MVT::i32));
10285 // Change opcode to non-immediate version
10287 default: llvm_unreachable("Unknown target vector shift node");
10288 case X86ISD::VSHLI: Opc = X86ISD::VSHL; break;
10289 case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;
10290 case X86ISD::VSRAI: Opc = X86ISD::VSRA; break;
10293 // Need to build a vector containing shift amount
10294 // Shift amount is 32-bits, but SSE instructions read 64-bit, so fill with 0
10297 ShOps[1] = DAG.getConstant(0, MVT::i32);
10298 ShOps[2] = ShOps[3] = DAG.getUNDEF(MVT::i32);
10299 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &ShOps[0], 4);
10301 // The return type has to be a 128-bit type with the same element
10302 // type as the input type.
10303 MVT EltVT = VT.getVectorElementType().getSimpleVT();
10304 EVT ShVT = MVT::getVectorVT(EltVT, 128/EltVT.getSizeInBits());
10306 ShAmt = DAG.getNode(ISD::BITCAST, dl, ShVT, ShAmt);
10307 return DAG.getNode(Opc, dl, VT, SrcOp, ShAmt);
10310 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
10311 DebugLoc dl = Op.getDebugLoc();
10312 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10314 default: return SDValue(); // Don't custom lower most intrinsics.
10315 // Comparison intrinsics.
10316 case Intrinsic::x86_sse_comieq_ss:
10317 case Intrinsic::x86_sse_comilt_ss:
10318 case Intrinsic::x86_sse_comile_ss:
10319 case Intrinsic::x86_sse_comigt_ss:
10320 case Intrinsic::x86_sse_comige_ss:
10321 case Intrinsic::x86_sse_comineq_ss:
10322 case Intrinsic::x86_sse_ucomieq_ss:
10323 case Intrinsic::x86_sse_ucomilt_ss:
10324 case Intrinsic::x86_sse_ucomile_ss:
10325 case Intrinsic::x86_sse_ucomigt_ss:
10326 case Intrinsic::x86_sse_ucomige_ss:
10327 case Intrinsic::x86_sse_ucomineq_ss:
10328 case Intrinsic::x86_sse2_comieq_sd:
10329 case Intrinsic::x86_sse2_comilt_sd:
10330 case Intrinsic::x86_sse2_comile_sd:
10331 case Intrinsic::x86_sse2_comigt_sd:
10332 case Intrinsic::x86_sse2_comige_sd:
10333 case Intrinsic::x86_sse2_comineq_sd:
10334 case Intrinsic::x86_sse2_ucomieq_sd:
10335 case Intrinsic::x86_sse2_ucomilt_sd:
10336 case Intrinsic::x86_sse2_ucomile_sd:
10337 case Intrinsic::x86_sse2_ucomigt_sd:
10338 case Intrinsic::x86_sse2_ucomige_sd:
10339 case Intrinsic::x86_sse2_ucomineq_sd: {
10343 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10344 case Intrinsic::x86_sse_comieq_ss:
10345 case Intrinsic::x86_sse2_comieq_sd:
10346 Opc = X86ISD::COMI;
10349 case Intrinsic::x86_sse_comilt_ss:
10350 case Intrinsic::x86_sse2_comilt_sd:
10351 Opc = X86ISD::COMI;
10354 case Intrinsic::x86_sse_comile_ss:
10355 case Intrinsic::x86_sse2_comile_sd:
10356 Opc = X86ISD::COMI;
10359 case Intrinsic::x86_sse_comigt_ss:
10360 case Intrinsic::x86_sse2_comigt_sd:
10361 Opc = X86ISD::COMI;
10364 case Intrinsic::x86_sse_comige_ss:
10365 case Intrinsic::x86_sse2_comige_sd:
10366 Opc = X86ISD::COMI;
10369 case Intrinsic::x86_sse_comineq_ss:
10370 case Intrinsic::x86_sse2_comineq_sd:
10371 Opc = X86ISD::COMI;
10374 case Intrinsic::x86_sse_ucomieq_ss:
10375 case Intrinsic::x86_sse2_ucomieq_sd:
10376 Opc = X86ISD::UCOMI;
10379 case Intrinsic::x86_sse_ucomilt_ss:
10380 case Intrinsic::x86_sse2_ucomilt_sd:
10381 Opc = X86ISD::UCOMI;
10384 case Intrinsic::x86_sse_ucomile_ss:
10385 case Intrinsic::x86_sse2_ucomile_sd:
10386 Opc = X86ISD::UCOMI;
10389 case Intrinsic::x86_sse_ucomigt_ss:
10390 case Intrinsic::x86_sse2_ucomigt_sd:
10391 Opc = X86ISD::UCOMI;
10394 case Intrinsic::x86_sse_ucomige_ss:
10395 case Intrinsic::x86_sse2_ucomige_sd:
10396 Opc = X86ISD::UCOMI;
10399 case Intrinsic::x86_sse_ucomineq_ss:
10400 case Intrinsic::x86_sse2_ucomineq_sd:
10401 Opc = X86ISD::UCOMI;
10406 SDValue LHS = Op.getOperand(1);
10407 SDValue RHS = Op.getOperand(2);
10408 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
10409 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
10410 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
10411 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10412 DAG.getConstant(X86CC, MVT::i8), Cond);
10413 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10416 // Arithmetic intrinsics.
10417 case Intrinsic::x86_sse2_pmulu_dq:
10418 case Intrinsic::x86_avx2_pmulu_dq:
10419 return DAG.getNode(X86ISD::PMULUDQ, dl, Op.getValueType(),
10420 Op.getOperand(1), Op.getOperand(2));
10422 // SSE2/AVX2 sub with unsigned saturation intrinsics
10423 case Intrinsic::x86_sse2_psubus_b:
10424 case Intrinsic::x86_sse2_psubus_w:
10425 case Intrinsic::x86_avx2_psubus_b:
10426 case Intrinsic::x86_avx2_psubus_w:
10427 return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
10428 Op.getOperand(1), Op.getOperand(2));
10430 // SSE3/AVX horizontal add/sub intrinsics
10431 case Intrinsic::x86_sse3_hadd_ps:
10432 case Intrinsic::x86_sse3_hadd_pd:
10433 case Intrinsic::x86_avx_hadd_ps_256:
10434 case Intrinsic::x86_avx_hadd_pd_256:
10435 case Intrinsic::x86_sse3_hsub_ps:
10436 case Intrinsic::x86_sse3_hsub_pd:
10437 case Intrinsic::x86_avx_hsub_ps_256:
10438 case Intrinsic::x86_avx_hsub_pd_256:
10439 case Intrinsic::x86_ssse3_phadd_w_128:
10440 case Intrinsic::x86_ssse3_phadd_d_128:
10441 case Intrinsic::x86_avx2_phadd_w:
10442 case Intrinsic::x86_avx2_phadd_d:
10443 case Intrinsic::x86_ssse3_phsub_w_128:
10444 case Intrinsic::x86_ssse3_phsub_d_128:
10445 case Intrinsic::x86_avx2_phsub_w:
10446 case Intrinsic::x86_avx2_phsub_d: {
10449 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10450 case Intrinsic::x86_sse3_hadd_ps:
10451 case Intrinsic::x86_sse3_hadd_pd:
10452 case Intrinsic::x86_avx_hadd_ps_256:
10453 case Intrinsic::x86_avx_hadd_pd_256:
10454 Opcode = X86ISD::FHADD;
10456 case Intrinsic::x86_sse3_hsub_ps:
10457 case Intrinsic::x86_sse3_hsub_pd:
10458 case Intrinsic::x86_avx_hsub_ps_256:
10459 case Intrinsic::x86_avx_hsub_pd_256:
10460 Opcode = X86ISD::FHSUB;
10462 case Intrinsic::x86_ssse3_phadd_w_128:
10463 case Intrinsic::x86_ssse3_phadd_d_128:
10464 case Intrinsic::x86_avx2_phadd_w:
10465 case Intrinsic::x86_avx2_phadd_d:
10466 Opcode = X86ISD::HADD;
10468 case Intrinsic::x86_ssse3_phsub_w_128:
10469 case Intrinsic::x86_ssse3_phsub_d_128:
10470 case Intrinsic::x86_avx2_phsub_w:
10471 case Intrinsic::x86_avx2_phsub_d:
10472 Opcode = X86ISD::HSUB;
10475 return DAG.getNode(Opcode, dl, Op.getValueType(),
10476 Op.getOperand(1), Op.getOperand(2));
10479 // SSE2/SSE41/AVX2 integer max/min intrinsics.
10480 case Intrinsic::x86_sse2_pmaxu_b:
10481 case Intrinsic::x86_sse41_pmaxuw:
10482 case Intrinsic::x86_sse41_pmaxud:
10483 case Intrinsic::x86_avx2_pmaxu_b:
10484 case Intrinsic::x86_avx2_pmaxu_w:
10485 case Intrinsic::x86_avx2_pmaxu_d:
10486 case Intrinsic::x86_sse2_pminu_b:
10487 case Intrinsic::x86_sse41_pminuw:
10488 case Intrinsic::x86_sse41_pminud:
10489 case Intrinsic::x86_avx2_pminu_b:
10490 case Intrinsic::x86_avx2_pminu_w:
10491 case Intrinsic::x86_avx2_pminu_d:
10492 case Intrinsic::x86_sse41_pmaxsb:
10493 case Intrinsic::x86_sse2_pmaxs_w:
10494 case Intrinsic::x86_sse41_pmaxsd:
10495 case Intrinsic::x86_avx2_pmaxs_b:
10496 case Intrinsic::x86_avx2_pmaxs_w:
10497 case Intrinsic::x86_avx2_pmaxs_d:
10498 case Intrinsic::x86_sse41_pminsb:
10499 case Intrinsic::x86_sse2_pmins_w:
10500 case Intrinsic::x86_sse41_pminsd:
10501 case Intrinsic::x86_avx2_pmins_b:
10502 case Intrinsic::x86_avx2_pmins_w:
10503 case Intrinsic::x86_avx2_pmins_d: {
10506 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10507 case Intrinsic::x86_sse2_pmaxu_b:
10508 case Intrinsic::x86_sse41_pmaxuw:
10509 case Intrinsic::x86_sse41_pmaxud:
10510 case Intrinsic::x86_avx2_pmaxu_b:
10511 case Intrinsic::x86_avx2_pmaxu_w:
10512 case Intrinsic::x86_avx2_pmaxu_d:
10513 Opcode = X86ISD::UMAX;
10515 case Intrinsic::x86_sse2_pminu_b:
10516 case Intrinsic::x86_sse41_pminuw:
10517 case Intrinsic::x86_sse41_pminud:
10518 case Intrinsic::x86_avx2_pminu_b:
10519 case Intrinsic::x86_avx2_pminu_w:
10520 case Intrinsic::x86_avx2_pminu_d:
10521 Opcode = X86ISD::UMIN;
10523 case Intrinsic::x86_sse41_pmaxsb:
10524 case Intrinsic::x86_sse2_pmaxs_w:
10525 case Intrinsic::x86_sse41_pmaxsd:
10526 case Intrinsic::x86_avx2_pmaxs_b:
10527 case Intrinsic::x86_avx2_pmaxs_w:
10528 case Intrinsic::x86_avx2_pmaxs_d:
10529 Opcode = X86ISD::SMAX;
10531 case Intrinsic::x86_sse41_pminsb:
10532 case Intrinsic::x86_sse2_pmins_w:
10533 case Intrinsic::x86_sse41_pminsd:
10534 case Intrinsic::x86_avx2_pmins_b:
10535 case Intrinsic::x86_avx2_pmins_w:
10536 case Intrinsic::x86_avx2_pmins_d:
10537 Opcode = X86ISD::SMIN;
10540 return DAG.getNode(Opcode, dl, Op.getValueType(),
10541 Op.getOperand(1), Op.getOperand(2));
10544 // SSE/SSE2/AVX floating point max/min intrinsics.
10545 case Intrinsic::x86_sse_max_ps:
10546 case Intrinsic::x86_sse2_max_pd:
10547 case Intrinsic::x86_avx_max_ps_256:
10548 case Intrinsic::x86_avx_max_pd_256:
10549 case Intrinsic::x86_sse_min_ps:
10550 case Intrinsic::x86_sse2_min_pd:
10551 case Intrinsic::x86_avx_min_ps_256:
10552 case Intrinsic::x86_avx_min_pd_256: {
10555 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10556 case Intrinsic::x86_sse_max_ps:
10557 case Intrinsic::x86_sse2_max_pd:
10558 case Intrinsic::x86_avx_max_ps_256:
10559 case Intrinsic::x86_avx_max_pd_256:
10560 Opcode = X86ISD::FMAX;
10562 case Intrinsic::x86_sse_min_ps:
10563 case Intrinsic::x86_sse2_min_pd:
10564 case Intrinsic::x86_avx_min_ps_256:
10565 case Intrinsic::x86_avx_min_pd_256:
10566 Opcode = X86ISD::FMIN;
10569 return DAG.getNode(Opcode, dl, Op.getValueType(),
10570 Op.getOperand(1), Op.getOperand(2));
10573 // AVX2 variable shift intrinsics
10574 case Intrinsic::x86_avx2_psllv_d:
10575 case Intrinsic::x86_avx2_psllv_q:
10576 case Intrinsic::x86_avx2_psllv_d_256:
10577 case Intrinsic::x86_avx2_psllv_q_256:
10578 case Intrinsic::x86_avx2_psrlv_d:
10579 case Intrinsic::x86_avx2_psrlv_q:
10580 case Intrinsic::x86_avx2_psrlv_d_256:
10581 case Intrinsic::x86_avx2_psrlv_q_256:
10582 case Intrinsic::x86_avx2_psrav_d:
10583 case Intrinsic::x86_avx2_psrav_d_256: {
10586 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10587 case Intrinsic::x86_avx2_psllv_d:
10588 case Intrinsic::x86_avx2_psllv_q:
10589 case Intrinsic::x86_avx2_psllv_d_256:
10590 case Intrinsic::x86_avx2_psllv_q_256:
10593 case Intrinsic::x86_avx2_psrlv_d:
10594 case Intrinsic::x86_avx2_psrlv_q:
10595 case Intrinsic::x86_avx2_psrlv_d_256:
10596 case Intrinsic::x86_avx2_psrlv_q_256:
10599 case Intrinsic::x86_avx2_psrav_d:
10600 case Intrinsic::x86_avx2_psrav_d_256:
10604 return DAG.getNode(Opcode, dl, Op.getValueType(),
10605 Op.getOperand(1), Op.getOperand(2));
10608 case Intrinsic::x86_ssse3_pshuf_b_128:
10609 case Intrinsic::x86_avx2_pshuf_b:
10610 return DAG.getNode(X86ISD::PSHUFB, dl, Op.getValueType(),
10611 Op.getOperand(1), Op.getOperand(2));
10613 case Intrinsic::x86_ssse3_psign_b_128:
10614 case Intrinsic::x86_ssse3_psign_w_128:
10615 case Intrinsic::x86_ssse3_psign_d_128:
10616 case Intrinsic::x86_avx2_psign_b:
10617 case Intrinsic::x86_avx2_psign_w:
10618 case Intrinsic::x86_avx2_psign_d:
10619 return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
10620 Op.getOperand(1), Op.getOperand(2));
10622 case Intrinsic::x86_sse41_insertps:
10623 return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
10624 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10626 case Intrinsic::x86_avx_vperm2f128_ps_256:
10627 case Intrinsic::x86_avx_vperm2f128_pd_256:
10628 case Intrinsic::x86_avx_vperm2f128_si_256:
10629 case Intrinsic::x86_avx2_vperm2i128:
10630 return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
10631 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
10633 case Intrinsic::x86_avx2_permd:
10634 case Intrinsic::x86_avx2_permps:
10635 // Operands intentionally swapped. Mask is last operand to intrinsic,
10636 // but second operand for node/intruction.
10637 return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
10638 Op.getOperand(2), Op.getOperand(1));
10640 case Intrinsic::x86_sse_sqrt_ps:
10641 case Intrinsic::x86_sse2_sqrt_pd:
10642 case Intrinsic::x86_avx_sqrt_ps_256:
10643 case Intrinsic::x86_avx_sqrt_pd_256:
10644 return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
10646 // ptest and testp intrinsics. The intrinsic these come from are designed to
10647 // return an integer value, not just an instruction so lower it to the ptest
10648 // or testp pattern and a setcc for the result.
10649 case Intrinsic::x86_sse41_ptestz:
10650 case Intrinsic::x86_sse41_ptestc:
10651 case Intrinsic::x86_sse41_ptestnzc:
10652 case Intrinsic::x86_avx_ptestz_256:
10653 case Intrinsic::x86_avx_ptestc_256:
10654 case Intrinsic::x86_avx_ptestnzc_256:
10655 case Intrinsic::x86_avx_vtestz_ps:
10656 case Intrinsic::x86_avx_vtestc_ps:
10657 case Intrinsic::x86_avx_vtestnzc_ps:
10658 case Intrinsic::x86_avx_vtestz_pd:
10659 case Intrinsic::x86_avx_vtestc_pd:
10660 case Intrinsic::x86_avx_vtestnzc_pd:
10661 case Intrinsic::x86_avx_vtestz_ps_256:
10662 case Intrinsic::x86_avx_vtestc_ps_256:
10663 case Intrinsic::x86_avx_vtestnzc_ps_256:
10664 case Intrinsic::x86_avx_vtestz_pd_256:
10665 case Intrinsic::x86_avx_vtestc_pd_256:
10666 case Intrinsic::x86_avx_vtestnzc_pd_256: {
10667 bool IsTestPacked = false;
10670 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering.");
10671 case Intrinsic::x86_avx_vtestz_ps:
10672 case Intrinsic::x86_avx_vtestz_pd:
10673 case Intrinsic::x86_avx_vtestz_ps_256:
10674 case Intrinsic::x86_avx_vtestz_pd_256:
10675 IsTestPacked = true; // Fallthrough
10676 case Intrinsic::x86_sse41_ptestz:
10677 case Intrinsic::x86_avx_ptestz_256:
10679 X86CC = X86::COND_E;
10681 case Intrinsic::x86_avx_vtestc_ps:
10682 case Intrinsic::x86_avx_vtestc_pd:
10683 case Intrinsic::x86_avx_vtestc_ps_256:
10684 case Intrinsic::x86_avx_vtestc_pd_256:
10685 IsTestPacked = true; // Fallthrough
10686 case Intrinsic::x86_sse41_ptestc:
10687 case Intrinsic::x86_avx_ptestc_256:
10689 X86CC = X86::COND_B;
10691 case Intrinsic::x86_avx_vtestnzc_ps:
10692 case Intrinsic::x86_avx_vtestnzc_pd:
10693 case Intrinsic::x86_avx_vtestnzc_ps_256:
10694 case Intrinsic::x86_avx_vtestnzc_pd_256:
10695 IsTestPacked = true; // Fallthrough
10696 case Intrinsic::x86_sse41_ptestnzc:
10697 case Intrinsic::x86_avx_ptestnzc_256:
10699 X86CC = X86::COND_A;
10703 SDValue LHS = Op.getOperand(1);
10704 SDValue RHS = Op.getOperand(2);
10705 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;
10706 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);
10707 SDValue CC = DAG.getConstant(X86CC, MVT::i8);
10708 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);
10709 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10712 // SSE/AVX shift intrinsics
10713 case Intrinsic::x86_sse2_psll_w:
10714 case Intrinsic::x86_sse2_psll_d:
10715 case Intrinsic::x86_sse2_psll_q:
10716 case Intrinsic::x86_avx2_psll_w:
10717 case Intrinsic::x86_avx2_psll_d:
10718 case Intrinsic::x86_avx2_psll_q:
10719 case Intrinsic::x86_sse2_psrl_w:
10720 case Intrinsic::x86_sse2_psrl_d:
10721 case Intrinsic::x86_sse2_psrl_q:
10722 case Intrinsic::x86_avx2_psrl_w:
10723 case Intrinsic::x86_avx2_psrl_d:
10724 case Intrinsic::x86_avx2_psrl_q:
10725 case Intrinsic::x86_sse2_psra_w:
10726 case Intrinsic::x86_sse2_psra_d:
10727 case Intrinsic::x86_avx2_psra_w:
10728 case Intrinsic::x86_avx2_psra_d: {
10731 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10732 case Intrinsic::x86_sse2_psll_w:
10733 case Intrinsic::x86_sse2_psll_d:
10734 case Intrinsic::x86_sse2_psll_q:
10735 case Intrinsic::x86_avx2_psll_w:
10736 case Intrinsic::x86_avx2_psll_d:
10737 case Intrinsic::x86_avx2_psll_q:
10738 Opcode = X86ISD::VSHL;
10740 case Intrinsic::x86_sse2_psrl_w:
10741 case Intrinsic::x86_sse2_psrl_d:
10742 case Intrinsic::x86_sse2_psrl_q:
10743 case Intrinsic::x86_avx2_psrl_w:
10744 case Intrinsic::x86_avx2_psrl_d:
10745 case Intrinsic::x86_avx2_psrl_q:
10746 Opcode = X86ISD::VSRL;
10748 case Intrinsic::x86_sse2_psra_w:
10749 case Intrinsic::x86_sse2_psra_d:
10750 case Intrinsic::x86_avx2_psra_w:
10751 case Intrinsic::x86_avx2_psra_d:
10752 Opcode = X86ISD::VSRA;
10755 return DAG.getNode(Opcode, dl, Op.getValueType(),
10756 Op.getOperand(1), Op.getOperand(2));
10759 // SSE/AVX immediate shift intrinsics
10760 case Intrinsic::x86_sse2_pslli_w:
10761 case Intrinsic::x86_sse2_pslli_d:
10762 case Intrinsic::x86_sse2_pslli_q:
10763 case Intrinsic::x86_avx2_pslli_w:
10764 case Intrinsic::x86_avx2_pslli_d:
10765 case Intrinsic::x86_avx2_pslli_q:
10766 case Intrinsic::x86_sse2_psrli_w:
10767 case Intrinsic::x86_sse2_psrli_d:
10768 case Intrinsic::x86_sse2_psrli_q:
10769 case Intrinsic::x86_avx2_psrli_w:
10770 case Intrinsic::x86_avx2_psrli_d:
10771 case Intrinsic::x86_avx2_psrli_q:
10772 case Intrinsic::x86_sse2_psrai_w:
10773 case Intrinsic::x86_sse2_psrai_d:
10774 case Intrinsic::x86_avx2_psrai_w:
10775 case Intrinsic::x86_avx2_psrai_d: {
10778 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10779 case Intrinsic::x86_sse2_pslli_w:
10780 case Intrinsic::x86_sse2_pslli_d:
10781 case Intrinsic::x86_sse2_pslli_q:
10782 case Intrinsic::x86_avx2_pslli_w:
10783 case Intrinsic::x86_avx2_pslli_d:
10784 case Intrinsic::x86_avx2_pslli_q:
10785 Opcode = X86ISD::VSHLI;
10787 case Intrinsic::x86_sse2_psrli_w:
10788 case Intrinsic::x86_sse2_psrli_d:
10789 case Intrinsic::x86_sse2_psrli_q:
10790 case Intrinsic::x86_avx2_psrli_w:
10791 case Intrinsic::x86_avx2_psrli_d:
10792 case Intrinsic::x86_avx2_psrli_q:
10793 Opcode = X86ISD::VSRLI;
10795 case Intrinsic::x86_sse2_psrai_w:
10796 case Intrinsic::x86_sse2_psrai_d:
10797 case Intrinsic::x86_avx2_psrai_w:
10798 case Intrinsic::x86_avx2_psrai_d:
10799 Opcode = X86ISD::VSRAI;
10802 return getTargetVShiftNode(Opcode, dl, Op.getValueType(),
10803 Op.getOperand(1), Op.getOperand(2), DAG);
10806 case Intrinsic::x86_sse42_pcmpistria128:
10807 case Intrinsic::x86_sse42_pcmpestria128:
10808 case Intrinsic::x86_sse42_pcmpistric128:
10809 case Intrinsic::x86_sse42_pcmpestric128:
10810 case Intrinsic::x86_sse42_pcmpistrio128:
10811 case Intrinsic::x86_sse42_pcmpestrio128:
10812 case Intrinsic::x86_sse42_pcmpistris128:
10813 case Intrinsic::x86_sse42_pcmpestris128:
10814 case Intrinsic::x86_sse42_pcmpistriz128:
10815 case Intrinsic::x86_sse42_pcmpestriz128: {
10819 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10820 case Intrinsic::x86_sse42_pcmpistria128:
10821 Opcode = X86ISD::PCMPISTRI;
10822 X86CC = X86::COND_A;
10824 case Intrinsic::x86_sse42_pcmpestria128:
10825 Opcode = X86ISD::PCMPESTRI;
10826 X86CC = X86::COND_A;
10828 case Intrinsic::x86_sse42_pcmpistric128:
10829 Opcode = X86ISD::PCMPISTRI;
10830 X86CC = X86::COND_B;
10832 case Intrinsic::x86_sse42_pcmpestric128:
10833 Opcode = X86ISD::PCMPESTRI;
10834 X86CC = X86::COND_B;
10836 case Intrinsic::x86_sse42_pcmpistrio128:
10837 Opcode = X86ISD::PCMPISTRI;
10838 X86CC = X86::COND_O;
10840 case Intrinsic::x86_sse42_pcmpestrio128:
10841 Opcode = X86ISD::PCMPESTRI;
10842 X86CC = X86::COND_O;
10844 case Intrinsic::x86_sse42_pcmpistris128:
10845 Opcode = X86ISD::PCMPISTRI;
10846 X86CC = X86::COND_S;
10848 case Intrinsic::x86_sse42_pcmpestris128:
10849 Opcode = X86ISD::PCMPESTRI;
10850 X86CC = X86::COND_S;
10852 case Intrinsic::x86_sse42_pcmpistriz128:
10853 Opcode = X86ISD::PCMPISTRI;
10854 X86CC = X86::COND_E;
10856 case Intrinsic::x86_sse42_pcmpestriz128:
10857 Opcode = X86ISD::PCMPESTRI;
10858 X86CC = X86::COND_E;
10861 SmallVector<SDValue, 5> NewOps;
10862 NewOps.append(Op->op_begin()+1, Op->op_end());
10863 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10864 SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10865 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10866 DAG.getConstant(X86CC, MVT::i8),
10867 SDValue(PCMP.getNode(), 1));
10868 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
10871 case Intrinsic::x86_sse42_pcmpistri128:
10872 case Intrinsic::x86_sse42_pcmpestri128: {
10874 if (IntNo == Intrinsic::x86_sse42_pcmpistri128)
10875 Opcode = X86ISD::PCMPISTRI;
10877 Opcode = X86ISD::PCMPESTRI;
10879 SmallVector<SDValue, 5> NewOps;
10880 NewOps.append(Op->op_begin()+1, Op->op_end());
10881 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
10882 return DAG.getNode(Opcode, dl, VTs, NewOps.data(), NewOps.size());
10884 case Intrinsic::x86_fma_vfmadd_ps:
10885 case Intrinsic::x86_fma_vfmadd_pd:
10886 case Intrinsic::x86_fma_vfmsub_ps:
10887 case Intrinsic::x86_fma_vfmsub_pd:
10888 case Intrinsic::x86_fma_vfnmadd_ps:
10889 case Intrinsic::x86_fma_vfnmadd_pd:
10890 case Intrinsic::x86_fma_vfnmsub_ps:
10891 case Intrinsic::x86_fma_vfnmsub_pd:
10892 case Intrinsic::x86_fma_vfmaddsub_ps:
10893 case Intrinsic::x86_fma_vfmaddsub_pd:
10894 case Intrinsic::x86_fma_vfmsubadd_ps:
10895 case Intrinsic::x86_fma_vfmsubadd_pd:
10896 case Intrinsic::x86_fma_vfmadd_ps_256:
10897 case Intrinsic::x86_fma_vfmadd_pd_256:
10898 case Intrinsic::x86_fma_vfmsub_ps_256:
10899 case Intrinsic::x86_fma_vfmsub_pd_256:
10900 case Intrinsic::x86_fma_vfnmadd_ps_256:
10901 case Intrinsic::x86_fma_vfnmadd_pd_256:
10902 case Intrinsic::x86_fma_vfnmsub_ps_256:
10903 case Intrinsic::x86_fma_vfnmsub_pd_256:
10904 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10905 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10906 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10907 case Intrinsic::x86_fma_vfmsubadd_pd_256: {
10910 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
10911 case Intrinsic::x86_fma_vfmadd_ps:
10912 case Intrinsic::x86_fma_vfmadd_pd:
10913 case Intrinsic::x86_fma_vfmadd_ps_256:
10914 case Intrinsic::x86_fma_vfmadd_pd_256:
10915 Opc = X86ISD::FMADD;
10917 case Intrinsic::x86_fma_vfmsub_ps:
10918 case Intrinsic::x86_fma_vfmsub_pd:
10919 case Intrinsic::x86_fma_vfmsub_ps_256:
10920 case Intrinsic::x86_fma_vfmsub_pd_256:
10921 Opc = X86ISD::FMSUB;
10923 case Intrinsic::x86_fma_vfnmadd_ps:
10924 case Intrinsic::x86_fma_vfnmadd_pd:
10925 case Intrinsic::x86_fma_vfnmadd_ps_256:
10926 case Intrinsic::x86_fma_vfnmadd_pd_256:
10927 Opc = X86ISD::FNMADD;
10929 case Intrinsic::x86_fma_vfnmsub_ps:
10930 case Intrinsic::x86_fma_vfnmsub_pd:
10931 case Intrinsic::x86_fma_vfnmsub_ps_256:
10932 case Intrinsic::x86_fma_vfnmsub_pd_256:
10933 Opc = X86ISD::FNMSUB;
10935 case Intrinsic::x86_fma_vfmaddsub_ps:
10936 case Intrinsic::x86_fma_vfmaddsub_pd:
10937 case Intrinsic::x86_fma_vfmaddsub_ps_256:
10938 case Intrinsic::x86_fma_vfmaddsub_pd_256:
10939 Opc = X86ISD::FMADDSUB;
10941 case Intrinsic::x86_fma_vfmsubadd_ps:
10942 case Intrinsic::x86_fma_vfmsubadd_pd:
10943 case Intrinsic::x86_fma_vfmsubadd_ps_256:
10944 case Intrinsic::x86_fma_vfmsubadd_pd_256:
10945 Opc = X86ISD::FMSUBADD;
10949 return DAG.getNode(Opc, dl, Op.getValueType(), Op.getOperand(1),
10950 Op.getOperand(2), Op.getOperand(3));
10955 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
10956 DebugLoc dl = Op.getDebugLoc();
10957 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
10959 default: return SDValue(); // Don't custom lower most intrinsics.
10961 // RDRAND/RDSEED intrinsics.
10962 case Intrinsic::x86_rdrand_16:
10963 case Intrinsic::x86_rdrand_32:
10964 case Intrinsic::x86_rdrand_64:
10965 case Intrinsic::x86_rdseed_16:
10966 case Intrinsic::x86_rdseed_32:
10967 case Intrinsic::x86_rdseed_64: {
10968 unsigned Opcode = (IntNo == Intrinsic::x86_rdseed_16 ||
10969 IntNo == Intrinsic::x86_rdseed_32 ||
10970 IntNo == Intrinsic::x86_rdseed_64) ? X86ISD::RDSEED :
10972 // Emit the node with the right value type.
10973 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
10974 SDValue Result = DAG.getNode(Opcode, dl, VTs, Op.getOperand(0));
10976 // If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
10977 // Otherwise return the value from Rand, which is always 0, casted to i32.
10978 SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),
10979 DAG.getConstant(1, Op->getValueType(1)),
10980 DAG.getConstant(X86::COND_B, MVT::i32),
10981 SDValue(Result.getNode(), 1) };
10982 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,
10983 DAG.getVTList(Op->getValueType(1), MVT::Glue),
10984 Ops, array_lengthof(Ops));
10986 // Return { result, isValid, chain }.
10987 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
10988 SDValue(Result.getNode(), 2));
10991 // XTEST intrinsics.
10992 case Intrinsic::x86_xtest: {
10993 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
10994 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
10995 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10996 DAG.getConstant(X86::COND_NE, MVT::i8),
10998 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
10999 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
11000 Ret, SDValue(InTrans.getNode(), 1));
11005 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
11006 SelectionDAG &DAG) const {
11007 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11008 MFI->setReturnAddressIsTaken(true);
11010 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11011 DebugLoc dl = Op.getDebugLoc();
11012 EVT PtrVT = getPointerTy();
11015 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11017 DAG.getConstant(RegInfo->getSlotSize(), PtrVT);
11018 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11019 DAG.getNode(ISD::ADD, dl, PtrVT,
11020 FrameAddr, Offset),
11021 MachinePointerInfo(), false, false, false, 0);
11024 // Just load the return address.
11025 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG);
11026 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11027 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
11030 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
11031 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11032 MFI->setFrameAddressIsTaken(true);
11034 EVT VT = Op.getValueType();
11035 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
11036 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11037 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11038 assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
11039 (FrameReg == X86::EBP && VT == MVT::i32)) &&
11040 "Invalid Frame Register!");
11041 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
11043 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
11044 MachinePointerInfo(),
11045 false, false, false, 0);
11049 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,
11050 SelectionDAG &DAG) const {
11051 return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());
11054 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
11055 SDValue Chain = Op.getOperand(0);
11056 SDValue Offset = Op.getOperand(1);
11057 SDValue Handler = Op.getOperand(2);
11058 DebugLoc dl = Op.getDebugLoc();
11060 EVT PtrVT = getPointerTy();
11061 unsigned FrameReg = RegInfo->getFrameRegister(DAG.getMachineFunction());
11062 assert(((FrameReg == X86::RBP && PtrVT == MVT::i64) ||
11063 (FrameReg == X86::EBP && PtrVT == MVT::i32)) &&
11064 "Invalid Frame Register!");
11065 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT);
11066 unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;
11068 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,
11069 DAG.getIntPtrConstant(RegInfo->getSlotSize()));
11070 StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);
11071 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
11073 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr);
11075 return DAG.getNode(X86ISD::EH_RETURN, dl, MVT::Other, Chain,
11076 DAG.getRegister(StoreAddrReg, PtrVT));
11079 SDValue X86TargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
11080 SelectionDAG &DAG) const {
11081 DebugLoc DL = Op.getDebugLoc();
11082 return DAG.getNode(X86ISD::EH_SJLJ_SETJMP, DL,
11083 DAG.getVTList(MVT::i32, MVT::Other),
11084 Op.getOperand(0), Op.getOperand(1));
11087 SDValue X86TargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
11088 SelectionDAG &DAG) const {
11089 DebugLoc DL = Op.getDebugLoc();
11090 return DAG.getNode(X86ISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
11091 Op.getOperand(0), Op.getOperand(1));
11094 static SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
11095 return Op.getOperand(0);
11098 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
11099 SelectionDAG &DAG) const {
11100 SDValue Root = Op.getOperand(0);
11101 SDValue Trmp = Op.getOperand(1); // trampoline
11102 SDValue FPtr = Op.getOperand(2); // nested function
11103 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
11104 DebugLoc dl = Op.getDebugLoc();
11106 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
11107 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
11109 if (Subtarget->is64Bit()) {
11110 SDValue OutChains[6];
11112 // Large code-model.
11113 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode.
11114 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode.
11116 const unsigned char N86R10 = TRI->getEncodingValue(X86::R10) & 0x7;
11117 const unsigned char N86R11 = TRI->getEncodingValue(X86::R11) & 0x7;
11119 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix
11121 // Load the pointer to the nested function into R11.
11122 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11
11123 SDValue Addr = Trmp;
11124 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11125 Addr, MachinePointerInfo(TrmpAddr),
11128 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11129 DAG.getConstant(2, MVT::i64));
11130 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,
11131 MachinePointerInfo(TrmpAddr, 2),
11134 // Load the 'nest' parameter value into R10.
11135 // R10 is specified in X86CallingConv.td
11136 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10
11137 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11138 DAG.getConstant(10, MVT::i64));
11139 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11140 Addr, MachinePointerInfo(TrmpAddr, 10),
11143 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11144 DAG.getConstant(12, MVT::i64));
11145 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,
11146 MachinePointerInfo(TrmpAddr, 12),
11149 // Jump to the nested function.
11150 OpCode = (JMP64r << 8) | REX_WB; // jmpq *...
11151 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11152 DAG.getConstant(20, MVT::i64));
11153 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),
11154 Addr, MachinePointerInfo(TrmpAddr, 20),
11157 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11
11158 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
11159 DAG.getConstant(22, MVT::i64));
11160 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,
11161 MachinePointerInfo(TrmpAddr, 22),
11164 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6);
11166 const Function *Func =
11167 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue());
11168 CallingConv::ID CC = Func->getCallingConv();
11173 llvm_unreachable("Unsupported calling convention");
11174 case CallingConv::C:
11175 case CallingConv::X86_StdCall: {
11176 // Pass 'nest' parameter in ECX.
11177 // Must be kept in sync with X86CallingConv.td
11178 NestReg = X86::ECX;
11180 // Check that ECX wasn't needed by an 'inreg' parameter.
11181 FunctionType *FTy = Func->getFunctionType();
11182 const AttributeSet &Attrs = Func->getAttributes();
11184 if (!Attrs.isEmpty() && !Func->isVarArg()) {
11185 unsigned InRegCount = 0;
11188 for (FunctionType::param_iterator I = FTy->param_begin(),
11189 E = FTy->param_end(); I != E; ++I, ++Idx)
11190 if (Attrs.hasAttribute(Idx, Attribute::InReg))
11191 // FIXME: should only count parameters that are lowered to integers.
11192 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32;
11194 if (InRegCount > 2) {
11195 report_fatal_error("Nest register in use - reduce number of inreg"
11201 case CallingConv::X86_FastCall:
11202 case CallingConv::X86_ThisCall:
11203 case CallingConv::Fast:
11204 // Pass 'nest' parameter in EAX.
11205 // Must be kept in sync with X86CallingConv.td
11206 NestReg = X86::EAX;
11210 SDValue OutChains[4];
11211 SDValue Addr, Disp;
11213 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11214 DAG.getConstant(10, MVT::i32));
11215 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);
11217 // This is storing the opcode for MOV32ri.
11218 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.
11219 const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;
11220 OutChains[0] = DAG.getStore(Root, dl,
11221 DAG.getConstant(MOV32ri|N86Reg, MVT::i8),
11222 Trmp, MachinePointerInfo(TrmpAddr),
11225 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11226 DAG.getConstant(1, MVT::i32));
11227 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,
11228 MachinePointerInfo(TrmpAddr, 1),
11231 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.
11232 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11233 DAG.getConstant(5, MVT::i32));
11234 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,
11235 MachinePointerInfo(TrmpAddr, 5),
11238 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
11239 DAG.getConstant(6, MVT::i32));
11240 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,
11241 MachinePointerInfo(TrmpAddr, 6),
11244 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4);
11248 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
11249 SelectionDAG &DAG) const {
11251 The rounding mode is in bits 11:10 of FPSR, and has the following
11253 00 Round to nearest
11258 FLT_ROUNDS, on the other hand, expects the following:
11265 To perform the conversion, we do:
11266 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3)
11269 MachineFunction &MF = DAG.getMachineFunction();
11270 const TargetMachine &TM = MF.getTarget();
11271 const TargetFrameLowering &TFI = *TM.getFrameLowering();
11272 unsigned StackAlignment = TFI.getStackAlignment();
11273 EVT VT = Op.getValueType();
11274 DebugLoc DL = Op.getDebugLoc();
11276 // Save FP Control Word to stack slot
11277 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
11278 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
11280 MachineMemOperand *MMO =
11281 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
11282 MachineMemOperand::MOStore, 2, 2);
11284 SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
11285 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
11286 DAG.getVTList(MVT::Other),
11287 Ops, array_lengthof(Ops), MVT::i16,
11290 // Load FP Control Word from stack slot
11291 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot,
11292 MachinePointerInfo(), false, false, false, 0);
11294 // Transform as necessary
11296 DAG.getNode(ISD::SRL, DL, MVT::i16,
11297 DAG.getNode(ISD::AND, DL, MVT::i16,
11298 CWD, DAG.getConstant(0x800, MVT::i16)),
11299 DAG.getConstant(11, MVT::i8));
11301 DAG.getNode(ISD::SRL, DL, MVT::i16,
11302 DAG.getNode(ISD::AND, DL, MVT::i16,
11303 CWD, DAG.getConstant(0x400, MVT::i16)),
11304 DAG.getConstant(9, MVT::i8));
11307 DAG.getNode(ISD::AND, DL, MVT::i16,
11308 DAG.getNode(ISD::ADD, DL, MVT::i16,
11309 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),
11310 DAG.getConstant(1, MVT::i16)),
11311 DAG.getConstant(3, MVT::i16));
11313 return DAG.getNode((VT.getSizeInBits() < 16 ?
11314 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);
11317 static SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) {
11318 EVT VT = Op.getValueType();
11320 unsigned NumBits = VT.getSizeInBits();
11321 DebugLoc dl = Op.getDebugLoc();
11323 Op = Op.getOperand(0);
11324 if (VT == MVT::i8) {
11325 // Zero extend to i32 since there is not an i8 bsr.
11327 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11330 // Issue a bsr (scan bits in reverse) which also sets EFLAGS.
11331 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11332 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11334 // If src is zero (i.e. bsr sets ZF), returns NumBits.
11337 DAG.getConstant(NumBits+NumBits-1, OpVT),
11338 DAG.getConstant(X86::COND_E, MVT::i8),
11341 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops));
11343 // Finally xor with NumBits-1.
11344 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11347 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11351 static SDValue LowerCTLZ_ZERO_UNDEF(SDValue Op, SelectionDAG &DAG) {
11352 EVT VT = Op.getValueType();
11354 unsigned NumBits = VT.getSizeInBits();
11355 DebugLoc dl = Op.getDebugLoc();
11357 Op = Op.getOperand(0);
11358 if (VT == MVT::i8) {
11359 // Zero extend to i32 since there is not an i8 bsr.
11361 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op);
11364 // Issue a bsr (scan bits in reverse).
11365 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
11366 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
11368 // And xor with NumBits-1.
11369 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));
11372 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);
11376 static SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) {
11377 EVT VT = Op.getValueType();
11378 unsigned NumBits = VT.getSizeInBits();
11379 DebugLoc dl = Op.getDebugLoc();
11380 Op = Op.getOperand(0);
11382 // Issue a bsf (scan bits forward) which also sets EFLAGS.
11383 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
11384 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op);
11386 // If src is zero (i.e. bsf sets ZF), returns NumBits.
11389 DAG.getConstant(NumBits, VT),
11390 DAG.getConstant(X86::COND_E, MVT::i8),
11393 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops, array_lengthof(Ops));
11396 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit
11397 // ones, and then concatenate the result back.
11398 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) {
11399 EVT VT = Op.getValueType();
11401 assert(VT.is256BitVector() && VT.isInteger() &&
11402 "Unsupported value type for operation");
11404 unsigned NumElems = VT.getVectorNumElements();
11405 DebugLoc dl = Op.getDebugLoc();
11407 // Extract the LHS vectors
11408 SDValue LHS = Op.getOperand(0);
11409 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
11410 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
11412 // Extract the RHS vectors
11413 SDValue RHS = Op.getOperand(1);
11414 SDValue RHS1 = Extract128BitVector(RHS, 0, DAG, dl);
11415 SDValue RHS2 = Extract128BitVector(RHS, NumElems/2, DAG, dl);
11417 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11418 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11420 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
11421 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1),
11422 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2));
11425 static SDValue LowerADD(SDValue Op, SelectionDAG &DAG) {
11426 assert(Op.getValueType().is256BitVector() &&
11427 Op.getValueType().isInteger() &&
11428 "Only handle AVX 256-bit vector integer operation");
11429 return Lower256IntArith(Op, DAG);
11432 static SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) {
11433 assert(Op.getValueType().is256BitVector() &&
11434 Op.getValueType().isInteger() &&
11435 "Only handle AVX 256-bit vector integer operation");
11436 return Lower256IntArith(Op, DAG);
11439 static SDValue LowerMUL(SDValue Op, const X86Subtarget *Subtarget,
11440 SelectionDAG &DAG) {
11441 DebugLoc dl = Op.getDebugLoc();
11442 EVT VT = Op.getValueType();
11444 // Decompose 256-bit ops into smaller 128-bit ops.
11445 if (VT.is256BitVector() && !Subtarget->hasInt256())
11446 return Lower256IntArith(Op, DAG);
11448 SDValue A = Op.getOperand(0);
11449 SDValue B = Op.getOperand(1);
11451 // Lower v4i32 mul as 2x shuffle, 2x pmuludq, 2x shuffle.
11452 if (VT == MVT::v4i32) {
11453 assert(Subtarget->hasSSE2() && !Subtarget->hasSSE41() &&
11454 "Should not custom lower when pmuldq is available!");
11456 // Extract the odd parts.
11457 const int UnpackMask[] = { 1, -1, 3, -1 };
11458 SDValue Aodds = DAG.getVectorShuffle(VT, dl, A, A, UnpackMask);
11459 SDValue Bodds = DAG.getVectorShuffle(VT, dl, B, B, UnpackMask);
11461 // Multiply the even parts.
11462 SDValue Evens = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, A, B);
11463 // Now multiply odd parts.
11464 SDValue Odds = DAG.getNode(X86ISD::PMULUDQ, dl, MVT::v2i64, Aodds, Bodds);
11466 Evens = DAG.getNode(ISD::BITCAST, dl, VT, Evens);
11467 Odds = DAG.getNode(ISD::BITCAST, dl, VT, Odds);
11469 // Merge the two vectors back together with a shuffle. This expands into 2
11471 const int ShufMask[] = { 0, 4, 2, 6 };
11472 return DAG.getVectorShuffle(VT, dl, Evens, Odds, ShufMask);
11475 assert((VT == MVT::v2i64 || VT == MVT::v4i64) &&
11476 "Only know how to lower V2I64/V4I64 multiply");
11478 // Ahi = psrlqi(a, 32);
11479 // Bhi = psrlqi(b, 32);
11481 // AloBlo = pmuludq(a, b);
11482 // AloBhi = pmuludq(a, Bhi);
11483 // AhiBlo = pmuludq(Ahi, b);
11485 // AloBhi = psllqi(AloBhi, 32);
11486 // AhiBlo = psllqi(AhiBlo, 32);
11487 // return AloBlo + AloBhi + AhiBlo;
11489 SDValue ShAmt = DAG.getConstant(32, MVT::i32);
11491 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A, ShAmt);
11492 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B, ShAmt);
11494 // Bit cast to 32-bit vectors for MULUDQ
11495 EVT MulVT = (VT == MVT::v2i64) ? MVT::v4i32 : MVT::v8i32;
11496 A = DAG.getNode(ISD::BITCAST, dl, MulVT, A);
11497 B = DAG.getNode(ISD::BITCAST, dl, MulVT, B);
11498 Ahi = DAG.getNode(ISD::BITCAST, dl, MulVT, Ahi);
11499 Bhi = DAG.getNode(ISD::BITCAST, dl, MulVT, Bhi);
11501 SDValue AloBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, B);
11502 SDValue AloBhi = DAG.getNode(X86ISD::PMULUDQ, dl, VT, A, Bhi);
11503 SDValue AhiBlo = DAG.getNode(X86ISD::PMULUDQ, dl, VT, Ahi, B);
11505 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi, ShAmt);
11506 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo, ShAmt);
11508 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
11509 return DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
11512 SDValue X86TargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
11513 EVT VT = Op.getValueType();
11514 EVT EltTy = VT.getVectorElementType();
11515 unsigned NumElts = VT.getVectorNumElements();
11516 SDValue N0 = Op.getOperand(0);
11517 DebugLoc dl = Op.getDebugLoc();
11519 // Lower sdiv X, pow2-const.
11520 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(Op.getOperand(1));
11524 APInt SplatValue, SplatUndef;
11525 unsigned MinSplatBits;
11527 if (!C->isConstantSplat(SplatValue, SplatUndef, MinSplatBits, HasAnyUndefs))
11530 if ((SplatValue != 0) &&
11531 (SplatValue.isPowerOf2() || (-SplatValue).isPowerOf2())) {
11532 unsigned lg2 = SplatValue.countTrailingZeros();
11533 // Splat the sign bit.
11534 SDValue Sz = DAG.getConstant(EltTy.getSizeInBits()-1, MVT::i32);
11535 SDValue SGN = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, N0, Sz, DAG);
11536 // Add (N0 < 0) ? abs2 - 1 : 0;
11537 SDValue Amt = DAG.getConstant(EltTy.getSizeInBits() - lg2, MVT::i32);
11538 SDValue SRL = getTargetVShiftNode(X86ISD::VSRLI, dl, VT, SGN, Amt, DAG);
11539 SDValue ADD = DAG.getNode(ISD::ADD, dl, VT, N0, SRL);
11540 SDValue Lg2Amt = DAG.getConstant(lg2, MVT::i32);
11541 SDValue SRA = getTargetVShiftNode(X86ISD::VSRAI, dl, VT, ADD, Lg2Amt, DAG);
11543 // If we're dividing by a positive value, we're done. Otherwise, we must
11544 // negate the result.
11545 if (SplatValue.isNonNegative())
11548 SmallVector<SDValue, 16> V(NumElts, DAG.getConstant(0, EltTy));
11549 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], NumElts);
11550 return DAG.getNode(ISD::SUB, dl, VT, Zero, SRA);
11555 static SDValue LowerScalarImmediateShift(SDValue Op, SelectionDAG &DAG,
11556 const X86Subtarget *Subtarget) {
11557 EVT VT = Op.getValueType();
11558 DebugLoc dl = Op.getDebugLoc();
11559 SDValue R = Op.getOperand(0);
11560 SDValue Amt = Op.getOperand(1);
11562 // Optimize shl/srl/sra with constant shift amount.
11563 if (isSplatVector(Amt.getNode())) {
11564 SDValue SclrAmt = Amt->getOperand(0);
11565 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) {
11566 uint64_t ShiftAmt = C->getZExtValue();
11568 if (VT == MVT::v2i64 || VT == MVT::v4i32 || VT == MVT::v8i16 ||
11569 (Subtarget->hasInt256() &&
11570 (VT == MVT::v4i64 || VT == MVT::v8i32 || VT == MVT::v16i16))) {
11571 if (Op.getOpcode() == ISD::SHL)
11572 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11573 DAG.getConstant(ShiftAmt, MVT::i32));
11574 if (Op.getOpcode() == ISD::SRL)
11575 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11576 DAG.getConstant(ShiftAmt, MVT::i32));
11577 if (Op.getOpcode() == ISD::SRA && VT != MVT::v2i64 && VT != MVT::v4i64)
11578 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11579 DAG.getConstant(ShiftAmt, MVT::i32));
11582 if (VT == MVT::v16i8) {
11583 if (Op.getOpcode() == ISD::SHL) {
11584 // Make a large shift.
11585 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v8i16, R,
11586 DAG.getConstant(ShiftAmt, MVT::i32));
11587 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11588 // Zero out the rightmost bits.
11589 SmallVector<SDValue, 16> V(16,
11590 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11592 return DAG.getNode(ISD::AND, dl, VT, SHL,
11593 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11595 if (Op.getOpcode() == ISD::SRL) {
11596 // Make a large shift.
11597 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v8i16, R,
11598 DAG.getConstant(ShiftAmt, MVT::i32));
11599 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11600 // Zero out the leftmost bits.
11601 SmallVector<SDValue, 16> V(16,
11602 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11604 return DAG.getNode(ISD::AND, dl, VT, SRL,
11605 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16));
11607 if (Op.getOpcode() == ISD::SRA) {
11608 if (ShiftAmt == 7) {
11609 // R s>> 7 === R s< 0
11610 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11611 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11614 // R s>> a === ((R u>> a) ^ m) - m
11615 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11616 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt,
11618 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 16);
11619 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11620 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11623 llvm_unreachable("Unknown shift opcode.");
11626 if (Subtarget->hasInt256() && VT == MVT::v32i8) {
11627 if (Op.getOpcode() == ISD::SHL) {
11628 // Make a large shift.
11629 SDValue SHL = DAG.getNode(X86ISD::VSHLI, dl, MVT::v16i16, R,
11630 DAG.getConstant(ShiftAmt, MVT::i32));
11631 SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);
11632 // Zero out the rightmost bits.
11633 SmallVector<SDValue, 32> V(32,
11634 DAG.getConstant(uint8_t(-1U << ShiftAmt),
11636 return DAG.getNode(ISD::AND, dl, VT, SHL,
11637 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11639 if (Op.getOpcode() == ISD::SRL) {
11640 // Make a large shift.
11641 SDValue SRL = DAG.getNode(X86ISD::VSRLI, dl, MVT::v16i16, R,
11642 DAG.getConstant(ShiftAmt, MVT::i32));
11643 SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);
11644 // Zero out the leftmost bits.
11645 SmallVector<SDValue, 32> V(32,
11646 DAG.getConstant(uint8_t(-1U) >> ShiftAmt,
11648 return DAG.getNode(ISD::AND, dl, VT, SRL,
11649 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32));
11651 if (Op.getOpcode() == ISD::SRA) {
11652 if (ShiftAmt == 7) {
11653 // R s>> 7 === R s< 0
11654 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
11655 return DAG.getNode(X86ISD::PCMPGT, dl, VT, Zeros, R);
11658 // R s>> a === ((R u>> a) ^ m) - m
11659 SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);
11660 SmallVector<SDValue, 32> V(32, DAG.getConstant(128 >> ShiftAmt,
11662 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &V[0], 32);
11663 Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);
11664 Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);
11667 llvm_unreachable("Unknown shift opcode.");
11672 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
11673 if (!Subtarget->is64Bit() &&
11674 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
11675 Amt.getOpcode() == ISD::BITCAST &&
11676 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
11677 Amt = Amt.getOperand(0);
11678 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
11679 VT.getVectorNumElements();
11680 unsigned RatioInLog2 = Log2_32_Ceil(Ratio);
11681 uint64_t ShiftAmt = 0;
11682 for (unsigned i = 0; i != Ratio; ++i) {
11683 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i));
11687 ShiftAmt |= C->getZExtValue() << (i * (1 << (6 - RatioInLog2)));
11689 // Check remaining shift amounts.
11690 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
11691 uint64_t ShAmt = 0;
11692 for (unsigned j = 0; j != Ratio; ++j) {
11693 ConstantSDNode *C =
11694 dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
11698 ShAmt |= C->getZExtValue() << (j * (1 << (6 - RatioInLog2)));
11700 if (ShAmt != ShiftAmt)
11703 switch (Op.getOpcode()) {
11705 llvm_unreachable("Unknown shift opcode!");
11707 return DAG.getNode(X86ISD::VSHLI, dl, VT, R,
11708 DAG.getConstant(ShiftAmt, MVT::i32));
11710 return DAG.getNode(X86ISD::VSRLI, dl, VT, R,
11711 DAG.getConstant(ShiftAmt, MVT::i32));
11713 return DAG.getNode(X86ISD::VSRAI, dl, VT, R,
11714 DAG.getConstant(ShiftAmt, MVT::i32));
11721 static SDValue LowerScalarVariableShift(SDValue Op, SelectionDAG &DAG,
11722 const X86Subtarget* Subtarget) {
11723 EVT VT = Op.getValueType();
11724 DebugLoc dl = Op.getDebugLoc();
11725 SDValue R = Op.getOperand(0);
11726 SDValue Amt = Op.getOperand(1);
11728 if ((VT == MVT::v2i64 && Op.getOpcode() != ISD::SRA) ||
11729 VT == MVT::v4i32 || VT == MVT::v8i16 ||
11730 (Subtarget->hasInt256() &&
11731 ((VT == MVT::v4i64 && Op.getOpcode() != ISD::SRA) ||
11732 VT == MVT::v8i32 || VT == MVT::v16i16))) {
11734 EVT EltVT = VT.getVectorElementType();
11736 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11737 unsigned NumElts = VT.getVectorNumElements();
11739 for (i = 0; i != NumElts; ++i) {
11740 if (Amt.getOperand(i).getOpcode() == ISD::UNDEF)
11744 for (j = i; j != NumElts; ++j) {
11745 SDValue Arg = Amt.getOperand(j);
11746 if (Arg.getOpcode() == ISD::UNDEF) continue;
11747 if (Arg != Amt.getOperand(i))
11750 if (i != NumElts && j == NumElts)
11751 BaseShAmt = Amt.getOperand(i);
11753 if (Amt.getOpcode() == ISD::EXTRACT_SUBVECTOR)
11754 Amt = Amt.getOperand(0);
11755 if (Amt.getOpcode() == ISD::VECTOR_SHUFFLE &&
11756 cast<ShuffleVectorSDNode>(Amt)->isSplat()) {
11757 SDValue InVec = Amt.getOperand(0);
11758 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
11759 unsigned NumElts = InVec.getValueType().getVectorNumElements();
11761 for (; i != NumElts; ++i) {
11762 SDValue Arg = InVec.getOperand(i);
11763 if (Arg.getOpcode() == ISD::UNDEF) continue;
11767 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
11768 if (ConstantSDNode *C =
11769 dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
11770 unsigned SplatIdx =
11771 cast<ShuffleVectorSDNode>(Amt)->getSplatIndex();
11772 if (C->getZExtValue() == SplatIdx)
11773 BaseShAmt = InVec.getOperand(1);
11776 if (BaseShAmt.getNode() == 0)
11777 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Amt,
11778 DAG.getIntPtrConstant(0));
11782 if (BaseShAmt.getNode()) {
11783 if (EltVT.bitsGT(MVT::i32))
11784 BaseShAmt = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BaseShAmt);
11785 else if (EltVT.bitsLT(MVT::i32))
11786 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, BaseShAmt);
11788 switch (Op.getOpcode()) {
11790 llvm_unreachable("Unknown shift opcode!");
11792 switch (VT.getSimpleVT().SimpleTy) {
11793 default: return SDValue();
11800 return getTargetVShiftNode(X86ISD::VSHLI, dl, VT, R, BaseShAmt, DAG);
11803 switch (VT.getSimpleVT().SimpleTy) {
11804 default: return SDValue();
11809 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, R, BaseShAmt, DAG);
11812 switch (VT.getSimpleVT().SimpleTy) {
11813 default: return SDValue();
11820 return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);
11826 // Special case in 32-bit mode, where i64 is expanded into high and low parts.
11827 if (!Subtarget->is64Bit() &&
11828 (VT == MVT::v2i64 || (Subtarget->hasInt256() && VT == MVT::v4i64)) &&
11829 Amt.getOpcode() == ISD::BITCAST &&
11830 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
11831 Amt = Amt.getOperand(0);
11832 unsigned Ratio = Amt.getValueType().getVectorNumElements() /
11833 VT.getVectorNumElements();
11834 std::vector<SDValue> Vals(Ratio);
11835 for (unsigned i = 0; i != Ratio; ++i)
11836 Vals[i] = Amt.getOperand(i);
11837 for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
11838 for (unsigned j = 0; j != Ratio; ++j)
11839 if (Vals[j] != Amt.getOperand(i + j))
11842 switch (Op.getOpcode()) {
11844 llvm_unreachable("Unknown shift opcode!");
11846 return DAG.getNode(X86ISD::VSHL, dl, VT, R, Op.getOperand(1));
11848 return DAG.getNode(X86ISD::VSRL, dl, VT, R, Op.getOperand(1));
11850 return DAG.getNode(X86ISD::VSRA, dl, VT, R, Op.getOperand(1));
11857 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const {
11859 EVT VT = Op.getValueType();
11860 DebugLoc dl = Op.getDebugLoc();
11861 SDValue R = Op.getOperand(0);
11862 SDValue Amt = Op.getOperand(1);
11865 if (!Subtarget->hasSSE2())
11868 V = LowerScalarImmediateShift(Op, DAG, Subtarget);
11872 V = LowerScalarVariableShift(Op, DAG, Subtarget);
11876 // AVX2 has VPSLLV/VPSRAV/VPSRLV.
11877 if (Subtarget->hasInt256()) {
11878 if (Op.getOpcode() == ISD::SRL &&
11879 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
11880 VT == MVT::v4i64 || VT == MVT::v8i32))
11882 if (Op.getOpcode() == ISD::SHL &&
11883 (VT == MVT::v2i64 || VT == MVT::v4i32 ||
11884 VT == MVT::v4i64 || VT == MVT::v8i32))
11886 if (Op.getOpcode() == ISD::SRA && (VT == MVT::v4i32 || VT == MVT::v8i32))
11890 // Lower SHL with variable shift amount.
11891 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {
11892 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));
11894 Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));
11895 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);
11896 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);
11897 return DAG.getNode(ISD::MUL, dl, VT, Op, R);
11899 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) {
11900 assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");
11903 Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));
11904 Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);
11906 // Turn 'a' into a mask suitable for VSELECT
11907 SDValue VSelM = DAG.getConstant(0x80, VT);
11908 SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11909 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11911 SDValue CM1 = DAG.getConstant(0x0f, VT);
11912 SDValue CM2 = DAG.getConstant(0x3f, VT);
11914 // r = VSELECT(r, psllw(r & (char16)15, 4), a);
11915 SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);
11916 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11917 DAG.getConstant(4, MVT::i32), DAG);
11918 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11919 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11922 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11923 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11924 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11926 // r = VSELECT(r, psllw(r & (char16)63, 2), a);
11927 M = DAG.getNode(ISD::AND, dl, VT, R, CM2);
11928 M = getTargetVShiftNode(X86ISD::VSHLI, dl, MVT::v8i16, M,
11929 DAG.getConstant(2, MVT::i32), DAG);
11930 M = DAG.getNode(ISD::BITCAST, dl, VT, M);
11931 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel, M, R);
11934 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
11935 OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);
11936 OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);
11938 // return VSELECT(r, r+r, a);
11939 R = DAG.getNode(ISD::VSELECT, dl, VT, OpVSel,
11940 DAG.getNode(ISD::ADD, dl, VT, R, R), R);
11944 // Decompose 256-bit shifts into smaller 128-bit shifts.
11945 if (VT.is256BitVector()) {
11946 unsigned NumElems = VT.getVectorNumElements();
11947 MVT EltVT = VT.getVectorElementType().getSimpleVT();
11948 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
11950 // Extract the two vectors
11951 SDValue V1 = Extract128BitVector(R, 0, DAG, dl);
11952 SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
11954 // Recreate the shift amount vectors
11955 SDValue Amt1, Amt2;
11956 if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
11957 // Constant shift amount
11958 SmallVector<SDValue, 4> Amt1Csts;
11959 SmallVector<SDValue, 4> Amt2Csts;
11960 for (unsigned i = 0; i != NumElems/2; ++i)
11961 Amt1Csts.push_back(Amt->getOperand(i));
11962 for (unsigned i = NumElems/2; i != NumElems; ++i)
11963 Amt2Csts.push_back(Amt->getOperand(i));
11965 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11966 &Amt1Csts[0], NumElems/2);
11967 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT,
11968 &Amt2Csts[0], NumElems/2);
11970 // Variable shift amount
11971 Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
11972 Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
11975 // Issue new vector shifts for the smaller types
11976 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);
11977 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2);
11979 // Concatenate the result back
11980 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2);
11986 static SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) {
11987 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus
11988 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering
11989 // looks for this combo and may remove the "setcc" instruction if the "setcc"
11990 // has only one use.
11991 SDNode *N = Op.getNode();
11992 SDValue LHS = N->getOperand(0);
11993 SDValue RHS = N->getOperand(1);
11994 unsigned BaseOp = 0;
11996 DebugLoc DL = Op.getDebugLoc();
11997 switch (Op.getOpcode()) {
11998 default: llvm_unreachable("Unknown ovf instruction!");
12000 // A subtract of one will be selected as a INC. Note that INC doesn't
12001 // set CF, so we can't do this for UADDO.
12002 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12004 BaseOp = X86ISD::INC;
12005 Cond = X86::COND_O;
12008 BaseOp = X86ISD::ADD;
12009 Cond = X86::COND_O;
12012 BaseOp = X86ISD::ADD;
12013 Cond = X86::COND_B;
12016 // A subtract of one will be selected as a DEC. Note that DEC doesn't
12017 // set CF, so we can't do this for USUBO.
12018 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS))
12020 BaseOp = X86ISD::DEC;
12021 Cond = X86::COND_O;
12024 BaseOp = X86ISD::SUB;
12025 Cond = X86::COND_O;
12028 BaseOp = X86ISD::SUB;
12029 Cond = X86::COND_B;
12032 BaseOp = X86ISD::SMUL;
12033 Cond = X86::COND_O;
12035 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs
12036 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0),
12038 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS);
12041 DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
12042 DAG.getConstant(X86::COND_O, MVT::i32),
12043 SDValue(Sum.getNode(), 2));
12045 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12049 // Also sets EFLAGS.
12050 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32);
12051 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS);
12054 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),
12055 DAG.getConstant(Cond, MVT::i32),
12056 SDValue(Sum.getNode(), 1));
12058 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);
12061 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
12062 SelectionDAG &DAG) const {
12063 DebugLoc dl = Op.getDebugLoc();
12064 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
12065 EVT VT = Op.getValueType();
12067 if (!Subtarget->hasSSE2() || !VT.isVector())
12070 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
12071 ExtraVT.getScalarType().getSizeInBits();
12072 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32);
12074 switch (VT.getSimpleVT().SimpleTy) {
12075 default: return SDValue();
12078 if (!Subtarget->hasFp256())
12080 if (!Subtarget->hasInt256()) {
12081 // needs to be split
12082 unsigned NumElems = VT.getVectorNumElements();
12084 // Extract the LHS vectors
12085 SDValue LHS = Op.getOperand(0);
12086 SDValue LHS1 = Extract128BitVector(LHS, 0, DAG, dl);
12087 SDValue LHS2 = Extract128BitVector(LHS, NumElems/2, DAG, dl);
12089 MVT EltVT = VT.getVectorElementType().getSimpleVT();
12090 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2);
12092 EVT ExtraEltVT = ExtraVT.getVectorElementType();
12093 unsigned ExtraNumElems = ExtraVT.getVectorNumElements();
12094 ExtraVT = EVT::getVectorVT(*DAG.getContext(), ExtraEltVT,
12096 SDValue Extra = DAG.getValueType(ExtraVT);
12098 LHS1 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, Extra);
12099 LHS2 = DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, Extra);
12101 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, LHS1, LHS2);
12106 // (sext (vzext x)) -> (vsext x)
12107 SDValue Op0 = Op.getOperand(0);
12108 SDValue Op00 = Op0.getOperand(0);
12110 // Hopefully, this VECTOR_SHUFFLE is just a VZEXT.
12111 if (Op0.getOpcode() == ISD::BITCAST &&
12112 Op00.getOpcode() == ISD::VECTOR_SHUFFLE)
12113 Tmp1 = LowerVectorIntExtend(Op00, DAG);
12114 if (Tmp1.getNode()) {
12115 SDValue Tmp1Op0 = Tmp1.getOperand(0);
12116 assert(Tmp1Op0.getOpcode() == X86ISD::VZEXT &&
12117 "This optimization is invalid without a VZEXT.");
12118 return DAG.getNode(X86ISD::VSEXT, dl, VT, Tmp1Op0.getOperand(0));
12121 // If the above didn't work, then just use Shift-Left + Shift-Right.
12122 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
12123 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
12128 static SDValue LowerATOMIC_FENCE(SDValue Op, const X86Subtarget *Subtarget,
12129 SelectionDAG &DAG) {
12130 DebugLoc dl = Op.getDebugLoc();
12131 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
12132 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
12133 SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
12134 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
12136 // The only fence that needs an instruction is a sequentially-consistent
12137 // cross-thread fence.
12138 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) {
12139 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
12140 // no-sse2). There isn't any reason to disable it if the target processor
12142 if (Subtarget->hasSSE2() || Subtarget->is64Bit())
12143 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
12145 SDValue Chain = Op.getOperand(0);
12146 SDValue Zero = DAG.getConstant(0, MVT::i32);
12148 DAG.getRegister(X86::ESP, MVT::i32), // Base
12149 DAG.getTargetConstant(1, MVT::i8), // Scale
12150 DAG.getRegister(0, MVT::i32), // Index
12151 DAG.getTargetConstant(0, MVT::i32), // Disp
12152 DAG.getRegister(0, MVT::i32), // Segment.
12156 SDNode *Res = DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops);
12157 return SDValue(Res, 0);
12160 // MEMBARRIER is a compiler barrier; it codegens to a no-op.
12161 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
12164 static SDValue LowerCMP_SWAP(SDValue Op, const X86Subtarget *Subtarget,
12165 SelectionDAG &DAG) {
12166 EVT T = Op.getValueType();
12167 DebugLoc DL = Op.getDebugLoc();
12170 switch(T.getSimpleVT().SimpleTy) {
12171 default: llvm_unreachable("Invalid value type!");
12172 case MVT::i8: Reg = X86::AL; size = 1; break;
12173 case MVT::i16: Reg = X86::AX; size = 2; break;
12174 case MVT::i32: Reg = X86::EAX; size = 4; break;
12176 assert(Subtarget->is64Bit() && "Node not type legal!");
12177 Reg = X86::RAX; size = 8;
12180 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg,
12181 Op.getOperand(2), SDValue());
12182 SDValue Ops[] = { cpIn.getValue(0),
12185 DAG.getTargetConstant(size, MVT::i8),
12186 cpIn.getValue(1) };
12187 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12188 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();
12189 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys,
12190 Ops, array_lengthof(Ops), T, MMO);
12192 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1));
12196 static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
12197 SelectionDAG &DAG) {
12198 assert(Subtarget->is64Bit() && "Result not type legalized?");
12199 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12200 SDValue TheChain = Op.getOperand(0);
12201 DebugLoc dl = Op.getDebugLoc();
12202 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12203 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1));
12204 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64,
12206 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx,
12207 DAG.getConstant(32, MVT::i8));
12209 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp),
12212 return DAG.getMergeValues(Ops, array_lengthof(Ops), dl);
12215 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
12216 EVT SrcVT = Op.getOperand(0).getValueType();
12217 EVT DstVT = Op.getValueType();
12218 assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
12219 Subtarget->hasMMX() && "Unexpected custom BITCAST");
12220 assert((DstVT == MVT::i64 ||
12221 (DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
12222 "Unexpected custom BITCAST");
12223 // i64 <=> MMX conversions are Legal.
12224 if (SrcVT==MVT::i64 && DstVT.isVector())
12226 if (DstVT==MVT::i64 && SrcVT.isVector())
12228 // MMX <=> MMX conversions are Legal.
12229 if (SrcVT.isVector() && DstVT.isVector())
12231 // All other conversions need to be expanded.
12235 static SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) {
12236 SDNode *Node = Op.getNode();
12237 DebugLoc dl = Node->getDebugLoc();
12238 EVT T = Node->getValueType(0);
12239 SDValue negOp = DAG.getNode(ISD::SUB, dl, T,
12240 DAG.getConstant(0, T), Node->getOperand(2));
12241 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,
12242 cast<AtomicSDNode>(Node)->getMemoryVT(),
12243 Node->getOperand(0),
12244 Node->getOperand(1), negOp,
12245 cast<AtomicSDNode>(Node)->getSrcValue(),
12246 cast<AtomicSDNode>(Node)->getAlignment(),
12247 cast<AtomicSDNode>(Node)->getOrdering(),
12248 cast<AtomicSDNode>(Node)->getSynchScope());
12251 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) {
12252 SDNode *Node = Op.getNode();
12253 DebugLoc dl = Node->getDebugLoc();
12254 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12256 // Convert seq_cst store -> xchg
12257 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b)
12258 // FIXME: On 32-bit, store -> fist or movq would be more efficient
12259 // (The only way to get a 16-byte store is cmpxchg16b)
12260 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment.
12261 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent ||
12262 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12263 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
12264 cast<AtomicSDNode>(Node)->getMemoryVT(),
12265 Node->getOperand(0),
12266 Node->getOperand(1), Node->getOperand(2),
12267 cast<AtomicSDNode>(Node)->getMemOperand(),
12268 cast<AtomicSDNode>(Node)->getOrdering(),
12269 cast<AtomicSDNode>(Node)->getSynchScope());
12270 return Swap.getValue(1);
12272 // Other atomic stores have a simple pattern.
12276 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
12277 EVT VT = Op.getNode()->getValueType(0);
12279 // Let legalize expand this if it isn't a legal type yet.
12280 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
12283 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
12286 bool ExtraOp = false;
12287 switch (Op.getOpcode()) {
12288 default: llvm_unreachable("Invalid code");
12289 case ISD::ADDC: Opc = X86ISD::ADD; break;
12290 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break;
12291 case ISD::SUBC: Opc = X86ISD::SUB; break;
12292 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
12296 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
12298 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
12299 Op.getOperand(1), Op.getOperand(2));
12302 SDValue X86TargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
12303 assert(Subtarget->isTargetDarwin() && Subtarget->is64Bit());
12305 // For MacOSX, we want to call an alternative entry point: __sincos_stret,
12306 // which returns the values as { float, float } (in XMM0) or
12307 // { double, double } (which is returned in XMM0, XMM1).
12308 DebugLoc dl = Op.getDebugLoc();
12309 SDValue Arg = Op.getOperand(0);
12310 EVT ArgVT = Arg.getValueType();
12311 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
12314 ArgListEntry Entry;
12318 Entry.isSExt = false;
12319 Entry.isZExt = false;
12320 Args.push_back(Entry);
12322 bool isF64 = ArgVT == MVT::f64;
12323 // Only optimize x86_64 for now. i386 is a bit messy. For f32,
12324 // the small struct {f32, f32} is returned in (eax, edx). For f64,
12325 // the results are returned via SRet in memory.
12326 const char *LibcallName = isF64 ? "__sincos_stret" : "__sincosf_stret";
12327 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
12329 Type *RetTy = isF64
12330 ? (Type*)StructType::get(ArgTy, ArgTy, NULL)
12331 : (Type*)VectorType::get(ArgTy, 4);
12333 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy,
12334 false, false, false, false, 0,
12335 CallingConv::C, /*isTaillCall=*/false,
12336 /*doesNotRet=*/false, /*isReturnValueUsed*/true,
12337 Callee, Args, DAG, dl);
12338 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
12341 // Returned in xmm0 and xmm1.
12342 return CallResult.first;
12344 // Returned in bits 0:31 and 32:64 xmm0.
12345 SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12346 CallResult.first, DAG.getIntPtrConstant(0));
12347 SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,
12348 CallResult.first, DAG.getIntPtrConstant(1));
12349 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
12350 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);
12353 /// LowerOperation - Provide custom lowering hooks for some operations.
12355 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
12356 switch (Op.getOpcode()) {
12357 default: llvm_unreachable("Should not custom lower this!");
12358 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG);
12359 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, Subtarget, DAG);
12360 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op, Subtarget, DAG);
12361 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG);
12362 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG);
12363 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
12364 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
12365 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
12366 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
12367 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
12368 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op,Subtarget,DAG);
12369 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, Subtarget,DAG);
12370 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
12371 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
12372 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
12373 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
12374 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG);
12375 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
12376 case ISD::SHL_PARTS:
12377 case ISD::SRA_PARTS:
12378 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG);
12379 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
12380 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
12381 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
12382 case ISD::ZERO_EXTEND: return LowerZERO_EXTEND(Op, DAG);
12383 case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
12384 case ISD::ANY_EXTEND: return LowerANY_EXTEND(Op, DAG);
12385 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
12386 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
12387 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
12388 case ISD::FABS: return LowerFABS(Op, DAG);
12389 case ISD::FNEG: return LowerFNEG(Op, DAG);
12390 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
12391 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
12392 case ISD::SETCC: return LowerSETCC(Op, DAG);
12393 case ISD::SELECT: return LowerSELECT(Op, DAG);
12394 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
12395 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
12396 case ISD::VASTART: return LowerVASTART(Op, DAG);
12397 case ISD::VAARG: return LowerVAARG(Op, DAG);
12398 case ISD::VACOPY: return LowerVACOPY(Op, Subtarget, DAG);
12399 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
12400 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
12401 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
12402 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
12403 case ISD::FRAME_TO_ARGS_OFFSET:
12404 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
12405 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
12406 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
12407 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
12408 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
12409 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
12410 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
12411 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
12412 case ISD::CTLZ: return LowerCTLZ(Op, DAG);
12413 case ISD::CTLZ_ZERO_UNDEF: return LowerCTLZ_ZERO_UNDEF(Op, DAG);
12414 case ISD::CTTZ: return LowerCTTZ(Op, DAG);
12415 case ISD::MUL: return LowerMUL(Op, Subtarget, DAG);
12418 case ISD::SHL: return LowerShift(Op, DAG);
12424 case ISD::UMULO: return LowerXALUO(Op, DAG);
12425 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, Subtarget,DAG);
12426 case ISD::BITCAST: return LowerBITCAST(Op, DAG);
12430 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
12431 case ISD::ADD: return LowerADD(Op, DAG);
12432 case ISD::SUB: return LowerSUB(Op, DAG);
12433 case ISD::SDIV: return LowerSDIV(Op, DAG);
12434 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
12438 static void ReplaceATOMIC_LOAD(SDNode *Node,
12439 SmallVectorImpl<SDValue> &Results,
12440 SelectionDAG &DAG) {
12441 DebugLoc dl = Node->getDebugLoc();
12442 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT();
12444 // Convert wide load -> cmpxchg8b/cmpxchg16b
12445 // FIXME: On 32-bit, load -> fild or movq would be more efficient
12446 // (The only way to get a 16-byte load is cmpxchg16b)
12447 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment.
12448 SDValue Zero = DAG.getConstant(0, VT);
12449 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
12450 Node->getOperand(0),
12451 Node->getOperand(1), Zero, Zero,
12452 cast<AtomicSDNode>(Node)->getMemOperand(),
12453 cast<AtomicSDNode>(Node)->getOrdering(),
12454 cast<AtomicSDNode>(Node)->getSynchScope());
12455 Results.push_back(Swap.getValue(0));
12456 Results.push_back(Swap.getValue(1));
12460 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
12461 SelectionDAG &DAG, unsigned NewOp) {
12462 DebugLoc dl = Node->getDebugLoc();
12463 assert (Node->getValueType(0) == MVT::i64 &&
12464 "Only know how to expand i64 atomics");
12466 SDValue Chain = Node->getOperand(0);
12467 SDValue In1 = Node->getOperand(1);
12468 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12469 Node->getOperand(2), DAG.getIntPtrConstant(0));
12470 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
12471 Node->getOperand(2), DAG.getIntPtrConstant(1));
12472 SDValue Ops[] = { Chain, In1, In2L, In2H };
12473 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
12475 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, array_lengthof(Ops), MVT::i64,
12476 cast<MemSDNode>(Node)->getMemOperand());
12477 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)};
12478 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
12479 Results.push_back(Result.getValue(2));
12482 /// ReplaceNodeResults - Replace a node with an illegal result type
12483 /// with a new node built out of custom code.
12484 void X86TargetLowering::ReplaceNodeResults(SDNode *N,
12485 SmallVectorImpl<SDValue>&Results,
12486 SelectionDAG &DAG) const {
12487 DebugLoc dl = N->getDebugLoc();
12488 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12489 switch (N->getOpcode()) {
12491 llvm_unreachable("Do not know how to custom type legalize this operation!");
12492 case ISD::SIGN_EXTEND_INREG:
12497 // We don't want to expand or promote these.
12499 case ISD::FP_TO_SINT:
12500 case ISD::FP_TO_UINT: {
12501 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT;
12503 if (!IsSigned && !isIntegerTypeFTOL(SDValue(N, 0).getValueType()))
12506 std::pair<SDValue,SDValue> Vals =
12507 FP_TO_INTHelper(SDValue(N, 0), DAG, IsSigned, /*IsReplace=*/ true);
12508 SDValue FIST = Vals.first, StackSlot = Vals.second;
12509 if (FIST.getNode() != 0) {
12510 EVT VT = N->getValueType(0);
12511 // Return a load from the stack slot.
12512 if (StackSlot.getNode() != 0)
12513 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot,
12514 MachinePointerInfo(),
12515 false, false, false, 0));
12517 Results.push_back(FIST);
12521 case ISD::UINT_TO_FP: {
12522 assert(Subtarget->hasSSE2() && "Requires at least SSE2!");
12523 if (N->getOperand(0).getValueType() != MVT::v2i32 ||
12524 N->getValueType(0) != MVT::v2f32)
12526 SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,
12528 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),
12530 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);
12531 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,
12532 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, VBias));
12533 Or = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or);
12534 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, Or, VBias);
12535 Results.push_back(DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Sub));
12538 case ISD::FP_ROUND: {
12539 if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
12541 SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
12542 Results.push_back(V);
12545 case ISD::READCYCLECOUNTER: {
12546 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12547 SDValue TheChain = N->getOperand(0);
12548 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1);
12549 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32,
12551 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32,
12553 // Use a buildpair to merge the two 32-bit values into a 64-bit one.
12554 SDValue Ops[] = { eax, edx };
12555 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops,
12556 array_lengthof(Ops)));
12557 Results.push_back(edx.getValue(1));
12560 case ISD::ATOMIC_CMP_SWAP: {
12561 EVT T = N->getValueType(0);
12562 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair");
12563 bool Regs64bit = T == MVT::i128;
12564 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;
12565 SDValue cpInL, cpInH;
12566 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12567 DAG.getConstant(0, HalfT));
12568 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),
12569 DAG.getConstant(1, HalfT));
12570 cpInL = DAG.getCopyToReg(N->getOperand(0), dl,
12571 Regs64bit ? X86::RAX : X86::EAX,
12573 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl,
12574 Regs64bit ? X86::RDX : X86::EDX,
12575 cpInH, cpInL.getValue(1));
12576 SDValue swapInL, swapInH;
12577 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12578 DAG.getConstant(0, HalfT));
12579 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),
12580 DAG.getConstant(1, HalfT));
12581 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,
12582 Regs64bit ? X86::RBX : X86::EBX,
12583 swapInL, cpInH.getValue(1));
12584 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl,
12585 Regs64bit ? X86::RCX : X86::ECX,
12586 swapInH, swapInL.getValue(1));
12587 SDValue Ops[] = { swapInH.getValue(0),
12589 swapInH.getValue(1) };
12590 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
12591 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand();
12592 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG :
12593 X86ISD::LCMPXCHG8_DAG;
12594 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys,
12595 Ops, array_lengthof(Ops), T, MMO);
12596 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl,
12597 Regs64bit ? X86::RAX : X86::EAX,
12598 HalfT, Result.getValue(1));
12599 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl,
12600 Regs64bit ? X86::RDX : X86::EDX,
12601 HalfT, cpOutL.getValue(2));
12602 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)};
12603 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2));
12604 Results.push_back(cpOutH.getValue(1));
12607 case ISD::ATOMIC_LOAD_ADD:
12608 case ISD::ATOMIC_LOAD_AND:
12609 case ISD::ATOMIC_LOAD_NAND:
12610 case ISD::ATOMIC_LOAD_OR:
12611 case ISD::ATOMIC_LOAD_SUB:
12612 case ISD::ATOMIC_LOAD_XOR:
12613 case ISD::ATOMIC_LOAD_MAX:
12614 case ISD::ATOMIC_LOAD_MIN:
12615 case ISD::ATOMIC_LOAD_UMAX:
12616 case ISD::ATOMIC_LOAD_UMIN:
12617 case ISD::ATOMIC_SWAP: {
12619 switch (N->getOpcode()) {
12620 default: llvm_unreachable("Unexpected opcode");
12621 case ISD::ATOMIC_LOAD_ADD:
12622 Opc = X86ISD::ATOMADD64_DAG;
12624 case ISD::ATOMIC_LOAD_AND:
12625 Opc = X86ISD::ATOMAND64_DAG;
12627 case ISD::ATOMIC_LOAD_NAND:
12628 Opc = X86ISD::ATOMNAND64_DAG;
12630 case ISD::ATOMIC_LOAD_OR:
12631 Opc = X86ISD::ATOMOR64_DAG;
12633 case ISD::ATOMIC_LOAD_SUB:
12634 Opc = X86ISD::ATOMSUB64_DAG;
12636 case ISD::ATOMIC_LOAD_XOR:
12637 Opc = X86ISD::ATOMXOR64_DAG;
12639 case ISD::ATOMIC_LOAD_MAX:
12640 Opc = X86ISD::ATOMMAX64_DAG;
12642 case ISD::ATOMIC_LOAD_MIN:
12643 Opc = X86ISD::ATOMMIN64_DAG;
12645 case ISD::ATOMIC_LOAD_UMAX:
12646 Opc = X86ISD::ATOMUMAX64_DAG;
12648 case ISD::ATOMIC_LOAD_UMIN:
12649 Opc = X86ISD::ATOMUMIN64_DAG;
12651 case ISD::ATOMIC_SWAP:
12652 Opc = X86ISD::ATOMSWAP64_DAG;
12655 ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
12658 case ISD::ATOMIC_LOAD:
12659 ReplaceATOMIC_LOAD(N, Results, DAG);
12663 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
12665 default: return NULL;
12666 case X86ISD::BSF: return "X86ISD::BSF";
12667 case X86ISD::BSR: return "X86ISD::BSR";
12668 case X86ISD::SHLD: return "X86ISD::SHLD";
12669 case X86ISD::SHRD: return "X86ISD::SHRD";
12670 case X86ISD::FAND: return "X86ISD::FAND";
12671 case X86ISD::FOR: return "X86ISD::FOR";
12672 case X86ISD::FXOR: return "X86ISD::FXOR";
12673 case X86ISD::FSRL: return "X86ISD::FSRL";
12674 case X86ISD::FILD: return "X86ISD::FILD";
12675 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG";
12676 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM";
12677 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM";
12678 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM";
12679 case X86ISD::FLD: return "X86ISD::FLD";
12680 case X86ISD::FST: return "X86ISD::FST";
12681 case X86ISD::CALL: return "X86ISD::CALL";
12682 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
12683 case X86ISD::BT: return "X86ISD::BT";
12684 case X86ISD::CMP: return "X86ISD::CMP";
12685 case X86ISD::COMI: return "X86ISD::COMI";
12686 case X86ISD::UCOMI: return "X86ISD::UCOMI";
12687 case X86ISD::SETCC: return "X86ISD::SETCC";
12688 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY";
12689 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd";
12690 case X86ISD::FSETCCss: return "X86ISD::FSETCCss";
12691 case X86ISD::CMOV: return "X86ISD::CMOV";
12692 case X86ISD::BRCOND: return "X86ISD::BRCOND";
12693 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG";
12694 case X86ISD::REP_STOS: return "X86ISD::REP_STOS";
12695 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS";
12696 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg";
12697 case X86ISD::Wrapper: return "X86ISD::Wrapper";
12698 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP";
12699 case X86ISD::PEXTRB: return "X86ISD::PEXTRB";
12700 case X86ISD::PEXTRW: return "X86ISD::PEXTRW";
12701 case X86ISD::INSERTPS: return "X86ISD::INSERTPS";
12702 case X86ISD::PINSRB: return "X86ISD::PINSRB";
12703 case X86ISD::PINSRW: return "X86ISD::PINSRW";
12704 case X86ISD::PSHUFB: return "X86ISD::PSHUFB";
12705 case X86ISD::ANDNP: return "X86ISD::ANDNP";
12706 case X86ISD::PSIGN: return "X86ISD::PSIGN";
12707 case X86ISD::BLENDV: return "X86ISD::BLENDV";
12708 case X86ISD::BLENDI: return "X86ISD::BLENDI";
12709 case X86ISD::SUBUS: return "X86ISD::SUBUS";
12710 case X86ISD::HADD: return "X86ISD::HADD";
12711 case X86ISD::HSUB: return "X86ISD::HSUB";
12712 case X86ISD::FHADD: return "X86ISD::FHADD";
12713 case X86ISD::FHSUB: return "X86ISD::FHSUB";
12714 case X86ISD::UMAX: return "X86ISD::UMAX";
12715 case X86ISD::UMIN: return "X86ISD::UMIN";
12716 case X86ISD::SMAX: return "X86ISD::SMAX";
12717 case X86ISD::SMIN: return "X86ISD::SMIN";
12718 case X86ISD::FMAX: return "X86ISD::FMAX";
12719 case X86ISD::FMIN: return "X86ISD::FMIN";
12720 case X86ISD::FMAXC: return "X86ISD::FMAXC";
12721 case X86ISD::FMINC: return "X86ISD::FMINC";
12722 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
12723 case X86ISD::FRCP: return "X86ISD::FRCP";
12724 case X86ISD::TLSADDR: return "X86ISD::TLSADDR";
12725 case X86ISD::TLSBASEADDR: return "X86ISD::TLSBASEADDR";
12726 case X86ISD::TLSCALL: return "X86ISD::TLSCALL";
12727 case X86ISD::EH_SJLJ_SETJMP: return "X86ISD::EH_SJLJ_SETJMP";
12728 case X86ISD::EH_SJLJ_LONGJMP: return "X86ISD::EH_SJLJ_LONGJMP";
12729 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN";
12730 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN";
12731 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m";
12732 case X86ISD::FNSTSW16r: return "X86ISD::FNSTSW16r";
12733 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG";
12734 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG";
12735 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG";
12736 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG";
12737 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG";
12738 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG";
12739 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG";
12740 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG";
12741 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL";
12742 case X86ISD::VSEXT_MOVL: return "X86ISD::VSEXT_MOVL";
12743 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
12744 case X86ISD::VZEXT: return "X86ISD::VZEXT";
12745 case X86ISD::VSEXT: return "X86ISD::VSEXT";
12746 case X86ISD::VFPEXT: return "X86ISD::VFPEXT";
12747 case X86ISD::VFPROUND: return "X86ISD::VFPROUND";
12748 case X86ISD::VSHLDQ: return "X86ISD::VSHLDQ";
12749 case X86ISD::VSRLDQ: return "X86ISD::VSRLDQ";
12750 case X86ISD::VSHL: return "X86ISD::VSHL";
12751 case X86ISD::VSRL: return "X86ISD::VSRL";
12752 case X86ISD::VSRA: return "X86ISD::VSRA";
12753 case X86ISD::VSHLI: return "X86ISD::VSHLI";
12754 case X86ISD::VSRLI: return "X86ISD::VSRLI";
12755 case X86ISD::VSRAI: return "X86ISD::VSRAI";
12756 case X86ISD::CMPP: return "X86ISD::CMPP";
12757 case X86ISD::PCMPEQ: return "X86ISD::PCMPEQ";
12758 case X86ISD::PCMPGT: return "X86ISD::PCMPGT";
12759 case X86ISD::ADD: return "X86ISD::ADD";
12760 case X86ISD::SUB: return "X86ISD::SUB";
12761 case X86ISD::ADC: return "X86ISD::ADC";
12762 case X86ISD::SBB: return "X86ISD::SBB";
12763 case X86ISD::SMUL: return "X86ISD::SMUL";
12764 case X86ISD::UMUL: return "X86ISD::UMUL";
12765 case X86ISD::INC: return "X86ISD::INC";
12766 case X86ISD::DEC: return "X86ISD::DEC";
12767 case X86ISD::OR: return "X86ISD::OR";
12768 case X86ISD::XOR: return "X86ISD::XOR";
12769 case X86ISD::AND: return "X86ISD::AND";
12770 case X86ISD::BLSI: return "X86ISD::BLSI";
12771 case X86ISD::BLSMSK: return "X86ISD::BLSMSK";
12772 case X86ISD::BLSR: return "X86ISD::BLSR";
12773 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
12774 case X86ISD::PTEST: return "X86ISD::PTEST";
12775 case X86ISD::TESTP: return "X86ISD::TESTP";
12776 case X86ISD::PALIGNR: return "X86ISD::PALIGNR";
12777 case X86ISD::PSHUFD: return "X86ISD::PSHUFD";
12778 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW";
12779 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW";
12780 case X86ISD::SHUFP: return "X86ISD::SHUFP";
12781 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS";
12782 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD";
12783 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS";
12784 case X86ISD::MOVLPS: return "X86ISD::MOVLPS";
12785 case X86ISD::MOVLPD: return "X86ISD::MOVLPD";
12786 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP";
12787 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP";
12788 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP";
12789 case X86ISD::MOVSD: return "X86ISD::MOVSD";
12790 case X86ISD::MOVSS: return "X86ISD::MOVSS";
12791 case X86ISD::UNPCKL: return "X86ISD::UNPCKL";
12792 case X86ISD::UNPCKH: return "X86ISD::UNPCKH";
12793 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST";
12794 case X86ISD::VPERMILP: return "X86ISD::VPERMILP";
12795 case X86ISD::VPERM2X128: return "X86ISD::VPERM2X128";
12796 case X86ISD::VPERMV: return "X86ISD::VPERMV";
12797 case X86ISD::VPERMI: return "X86ISD::VPERMI";
12798 case X86ISD::PMULUDQ: return "X86ISD::PMULUDQ";
12799 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
12800 case X86ISD::VAARG_64: return "X86ISD::VAARG_64";
12801 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA";
12802 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER";
12803 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA";
12804 case X86ISD::WIN_FTOL: return "X86ISD::WIN_FTOL";
12805 case X86ISD::SAHF: return "X86ISD::SAHF";
12806 case X86ISD::RDRAND: return "X86ISD::RDRAND";
12807 case X86ISD::RDSEED: return "X86ISD::RDSEED";
12808 case X86ISD::FMADD: return "X86ISD::FMADD";
12809 case X86ISD::FMSUB: return "X86ISD::FMSUB";
12810 case X86ISD::FNMADD: return "X86ISD::FNMADD";
12811 case X86ISD::FNMSUB: return "X86ISD::FNMSUB";
12812 case X86ISD::FMADDSUB: return "X86ISD::FMADDSUB";
12813 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
12814 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
12815 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
12816 case X86ISD::XTEST: return "X86ISD::XTEST";
12820 // isLegalAddressingMode - Return true if the addressing mode represented
12821 // by AM is legal for this target, for a load/store of the specified type.
12822 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM,
12824 // X86 supports extremely general addressing modes.
12825 CodeModel::Model M = getTargetMachine().getCodeModel();
12826 Reloc::Model R = getTargetMachine().getRelocationModel();
12828 // X86 allows a sign-extended 32-bit immediate field as a displacement.
12829 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL))
12834 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine());
12836 // If a reference to this global requires an extra load, we can't fold it.
12837 if (isGlobalStubReference(GVFlags))
12840 // If BaseGV requires a register for the PIC base, we cannot also have a
12841 // BaseReg specified.
12842 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags))
12845 // If lower 4G is not available, then we must use rip-relative addressing.
12846 if ((M != CodeModel::Small || R != Reloc::Static) &&
12847 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1))
12851 switch (AM.Scale) {
12857 // These scales always work.
12862 // These scales are formed with basereg+scalereg. Only accept if there is
12867 default: // Other stuff never works.
12874 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
12875 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
12877 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
12878 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
12879 return NumBits1 > NumBits2;
12882 bool X86TargetLowering::isLegalICmpImmediate(int64_t Imm) const {
12883 return isInt<32>(Imm);
12886 bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
12887 // Can also use sub to handle negated immediates.
12888 return isInt<32>(Imm);
12891 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
12892 if (!VT1.isInteger() || !VT2.isInteger())
12894 unsigned NumBits1 = VT1.getSizeInBits();
12895 unsigned NumBits2 = VT2.getSizeInBits();
12896 return NumBits1 > NumBits2;
12899 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
12900 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12901 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit();
12904 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
12905 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers.
12906 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit();
12909 bool X86TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
12910 EVT VT1 = Val.getValueType();
12911 if (isZExtFree(VT1, VT2))
12914 if (Val.getOpcode() != ISD::LOAD)
12917 if (!VT1.isSimple() || !VT1.isInteger() ||
12918 !VT2.isSimple() || !VT2.isInteger())
12921 switch (VT1.getSimpleVT().SimpleTy) {
12926 // X86 has 8, 16, and 32-bit zero-extending loads.
12933 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const {
12934 // i16 instructions are longer (0x66 prefix) and potentially slower.
12935 return !(VT1 == MVT::i32 && VT2 == MVT::i16);
12938 /// isShuffleMaskLegal - Targets can use this to indicate that they only
12939 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
12940 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
12941 /// are assumed to be legal.
12943 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
12945 // Very little shuffling can be done for 64-bit vectors right now.
12946 if (VT.getSizeInBits() == 64)
12949 // FIXME: pshufb, blends, shifts.
12950 return (VT.getVectorNumElements() == 2 ||
12951 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
12952 isMOVLMask(M, VT) ||
12953 isSHUFPMask(M, VT, Subtarget->hasFp256()) ||
12954 isPSHUFDMask(M, VT) ||
12955 isPSHUFHWMask(M, VT, Subtarget->hasInt256()) ||
12956 isPSHUFLWMask(M, VT, Subtarget->hasInt256()) ||
12957 isPALIGNRMask(M, VT, Subtarget) ||
12958 isUNPCKLMask(M, VT, Subtarget->hasInt256()) ||
12959 isUNPCKHMask(M, VT, Subtarget->hasInt256()) ||
12960 isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasInt256()) ||
12961 isUNPCKH_v_undef_Mask(M, VT, Subtarget->hasInt256()));
12965 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
12967 unsigned NumElts = VT.getVectorNumElements();
12968 // FIXME: This collection of masks seems suspect.
12971 if (NumElts == 4 && VT.is128BitVector()) {
12972 return (isMOVLMask(Mask, VT) ||
12973 isCommutedMOVLMask(Mask, VT, true) ||
12974 isSHUFPMask(Mask, VT, Subtarget->hasFp256()) ||
12975 isSHUFPMask(Mask, VT, Subtarget->hasFp256(), /* Commuted */ true));
12980 //===----------------------------------------------------------------------===//
12981 // X86 Scheduler Hooks
12982 //===----------------------------------------------------------------------===//
12984 /// Utility function to emit xbegin specifying the start of an RTM region.
12985 static MachineBasicBlock *EmitXBegin(MachineInstr *MI, MachineBasicBlock *MBB,
12986 const TargetInstrInfo *TII) {
12987 DebugLoc DL = MI->getDebugLoc();
12989 const BasicBlock *BB = MBB->getBasicBlock();
12990 MachineFunction::iterator I = MBB;
12993 // For the v = xbegin(), we generate
13004 MachineBasicBlock *thisMBB = MBB;
13005 MachineFunction *MF = MBB->getParent();
13006 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13007 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13008 MF->insert(I, mainMBB);
13009 MF->insert(I, sinkMBB);
13011 // Transfer the remainder of BB and its successor edges to sinkMBB.
13012 sinkMBB->splice(sinkMBB->begin(), MBB,
13013 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13014 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13018 // # fallthrough to mainMBB
13019 // # abortion to sinkMBB
13020 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
13021 thisMBB->addSuccessor(mainMBB);
13022 thisMBB->addSuccessor(sinkMBB);
13026 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
13027 mainMBB->addSuccessor(sinkMBB);
13030 // EAX is live into the sinkMBB
13031 sinkMBB->addLiveIn(X86::EAX);
13032 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13033 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13036 MI->eraseFromParent();
13040 // Get CMPXCHG opcode for the specified data type.
13041 static unsigned getCmpXChgOpcode(EVT VT) {
13042 switch (VT.getSimpleVT().SimpleTy) {
13043 case MVT::i8: return X86::LCMPXCHG8;
13044 case MVT::i16: return X86::LCMPXCHG16;
13045 case MVT::i32: return X86::LCMPXCHG32;
13046 case MVT::i64: return X86::LCMPXCHG64;
13050 llvm_unreachable("Invalid operand size!");
13053 // Get LOAD opcode for the specified data type.
13054 static unsigned getLoadOpcode(EVT VT) {
13055 switch (VT.getSimpleVT().SimpleTy) {
13056 case MVT::i8: return X86::MOV8rm;
13057 case MVT::i16: return X86::MOV16rm;
13058 case MVT::i32: return X86::MOV32rm;
13059 case MVT::i64: return X86::MOV64rm;
13063 llvm_unreachable("Invalid operand size!");
13066 // Get opcode of the non-atomic one from the specified atomic instruction.
13067 static unsigned getNonAtomicOpcode(unsigned Opc) {
13069 case X86::ATOMAND8: return X86::AND8rr;
13070 case X86::ATOMAND16: return X86::AND16rr;
13071 case X86::ATOMAND32: return X86::AND32rr;
13072 case X86::ATOMAND64: return X86::AND64rr;
13073 case X86::ATOMOR8: return X86::OR8rr;
13074 case X86::ATOMOR16: return X86::OR16rr;
13075 case X86::ATOMOR32: return X86::OR32rr;
13076 case X86::ATOMOR64: return X86::OR64rr;
13077 case X86::ATOMXOR8: return X86::XOR8rr;
13078 case X86::ATOMXOR16: return X86::XOR16rr;
13079 case X86::ATOMXOR32: return X86::XOR32rr;
13080 case X86::ATOMXOR64: return X86::XOR64rr;
13082 llvm_unreachable("Unhandled atomic-load-op opcode!");
13085 // Get opcode of the non-atomic one from the specified atomic instruction with
13087 static unsigned getNonAtomicOpcodeWithExtraOpc(unsigned Opc,
13088 unsigned &ExtraOpc) {
13090 case X86::ATOMNAND8: ExtraOpc = X86::NOT8r; return X86::AND8rr;
13091 case X86::ATOMNAND16: ExtraOpc = X86::NOT16r; return X86::AND16rr;
13092 case X86::ATOMNAND32: ExtraOpc = X86::NOT32r; return X86::AND32rr;
13093 case X86::ATOMNAND64: ExtraOpc = X86::NOT64r; return X86::AND64rr;
13094 case X86::ATOMMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVL32rr;
13095 case X86::ATOMMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVL16rr;
13096 case X86::ATOMMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVL32rr;
13097 case X86::ATOMMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVL64rr;
13098 case X86::ATOMMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVG32rr;
13099 case X86::ATOMMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVG16rr;
13100 case X86::ATOMMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVG32rr;
13101 case X86::ATOMMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVG64rr;
13102 case X86::ATOMUMAX8: ExtraOpc = X86::CMP8rr; return X86::CMOVB32rr;
13103 case X86::ATOMUMAX16: ExtraOpc = X86::CMP16rr; return X86::CMOVB16rr;
13104 case X86::ATOMUMAX32: ExtraOpc = X86::CMP32rr; return X86::CMOVB32rr;
13105 case X86::ATOMUMAX64: ExtraOpc = X86::CMP64rr; return X86::CMOVB64rr;
13106 case X86::ATOMUMIN8: ExtraOpc = X86::CMP8rr; return X86::CMOVA32rr;
13107 case X86::ATOMUMIN16: ExtraOpc = X86::CMP16rr; return X86::CMOVA16rr;
13108 case X86::ATOMUMIN32: ExtraOpc = X86::CMP32rr; return X86::CMOVA32rr;
13109 case X86::ATOMUMIN64: ExtraOpc = X86::CMP64rr; return X86::CMOVA64rr;
13111 llvm_unreachable("Unhandled atomic-load-op opcode!");
13114 // Get opcode of the non-atomic one from the specified atomic instruction for
13115 // 64-bit data type on 32-bit target.
13116 static unsigned getNonAtomic6432Opcode(unsigned Opc, unsigned &HiOpc) {
13118 case X86::ATOMAND6432: HiOpc = X86::AND32rr; return X86::AND32rr;
13119 case X86::ATOMOR6432: HiOpc = X86::OR32rr; return X86::OR32rr;
13120 case X86::ATOMXOR6432: HiOpc = X86::XOR32rr; return X86::XOR32rr;
13121 case X86::ATOMADD6432: HiOpc = X86::ADC32rr; return X86::ADD32rr;
13122 case X86::ATOMSUB6432: HiOpc = X86::SBB32rr; return X86::SUB32rr;
13123 case X86::ATOMSWAP6432: HiOpc = X86::MOV32rr; return X86::MOV32rr;
13124 case X86::ATOMMAX6432: HiOpc = X86::SETLr; return X86::SETLr;
13125 case X86::ATOMMIN6432: HiOpc = X86::SETGr; return X86::SETGr;
13126 case X86::ATOMUMAX6432: HiOpc = X86::SETBr; return X86::SETBr;
13127 case X86::ATOMUMIN6432: HiOpc = X86::SETAr; return X86::SETAr;
13129 llvm_unreachable("Unhandled atomic-load-op opcode!");
13132 // Get opcode of the non-atomic one from the specified atomic instruction for
13133 // 64-bit data type on 32-bit target with extra opcode.
13134 static unsigned getNonAtomic6432OpcodeWithExtraOpc(unsigned Opc,
13136 unsigned &ExtraOpc) {
13138 case X86::ATOMNAND6432:
13139 ExtraOpc = X86::NOT32r;
13140 HiOpc = X86::AND32rr;
13141 return X86::AND32rr;
13143 llvm_unreachable("Unhandled atomic-load-op opcode!");
13146 // Get pseudo CMOV opcode from the specified data type.
13147 static unsigned getPseudoCMOVOpc(EVT VT) {
13148 switch (VT.getSimpleVT().SimpleTy) {
13149 case MVT::i8: return X86::CMOV_GR8;
13150 case MVT::i16: return X86::CMOV_GR16;
13151 case MVT::i32: return X86::CMOV_GR32;
13155 llvm_unreachable("Unknown CMOV opcode!");
13158 // EmitAtomicLoadArith - emit the code sequence for pseudo atomic instructions.
13159 // They will be translated into a spin-loop or compare-exchange loop from
13162 // dst = atomic-fetch-op MI.addr, MI.val
13168 // t1 = LOAD MI.addr
13170 // t4 = phi(t1, t3 / loop)
13171 // t2 = OP MI.val, t4
13173 // LCMPXCHG [MI.addr], t2, [EAX is implicitly used & defined]
13179 MachineBasicBlock *
13180 X86TargetLowering::EmitAtomicLoadArith(MachineInstr *MI,
13181 MachineBasicBlock *MBB) const {
13182 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13183 DebugLoc DL = MI->getDebugLoc();
13185 MachineFunction *MF = MBB->getParent();
13186 MachineRegisterInfo &MRI = MF->getRegInfo();
13188 const BasicBlock *BB = MBB->getBasicBlock();
13189 MachineFunction::iterator I = MBB;
13192 assert(MI->getNumOperands() <= X86::AddrNumOperands + 4 &&
13193 "Unexpected number of operands");
13195 assert(MI->hasOneMemOperand() &&
13196 "Expected atomic-load-op to have one memoperand");
13198 // Memory Reference
13199 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13200 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13202 unsigned DstReg, SrcReg;
13203 unsigned MemOpndSlot;
13205 unsigned CurOp = 0;
13207 DstReg = MI->getOperand(CurOp++).getReg();
13208 MemOpndSlot = CurOp;
13209 CurOp += X86::AddrNumOperands;
13210 SrcReg = MI->getOperand(CurOp++).getReg();
13212 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
13213 MVT::SimpleValueType VT = *RC->vt_begin();
13214 unsigned t1 = MRI.createVirtualRegister(RC);
13215 unsigned t2 = MRI.createVirtualRegister(RC);
13216 unsigned t3 = MRI.createVirtualRegister(RC);
13217 unsigned t4 = MRI.createVirtualRegister(RC);
13218 unsigned PhyReg = getX86SubSuperRegister(X86::EAX, VT);
13220 unsigned LCMPXCHGOpc = getCmpXChgOpcode(VT);
13221 unsigned LOADOpc = getLoadOpcode(VT);
13223 // For the atomic load-arith operator, we generate
13226 // t1 = LOAD [MI.addr]
13228 // t4 = phi(t1 / thisMBB, t3 / mainMBB)
13229 // t1 = OP MI.val, EAX
13231 // LCMPXCHG [MI.addr], t1, [EAX is implicitly used & defined]
13237 MachineBasicBlock *thisMBB = MBB;
13238 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13239 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13240 MF->insert(I, mainMBB);
13241 MF->insert(I, sinkMBB);
13243 MachineInstrBuilder MIB;
13245 // Transfer the remainder of BB and its successor edges to sinkMBB.
13246 sinkMBB->splice(sinkMBB->begin(), MBB,
13247 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13248 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13251 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1);
13252 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13253 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13255 NewMO.setIsKill(false);
13256 MIB.addOperand(NewMO);
13258 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
13259 unsigned flags = (*MMOI)->getFlags();
13260 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
13261 MachineMemOperand *MMO =
13262 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
13263 (*MMOI)->getSize(),
13264 (*MMOI)->getBaseAlignment(),
13265 (*MMOI)->getTBAAInfo(),
13266 (*MMOI)->getRanges());
13267 MIB.addMemOperand(MMO);
13270 thisMBB->addSuccessor(mainMBB);
13273 MachineBasicBlock *origMainMBB = mainMBB;
13276 MachineInstr *Phi = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4)
13277 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
13279 unsigned Opc = MI->getOpcode();
13282 llvm_unreachable("Unhandled atomic-load-op opcode!");
13283 case X86::ATOMAND8:
13284 case X86::ATOMAND16:
13285 case X86::ATOMAND32:
13286 case X86::ATOMAND64:
13288 case X86::ATOMOR16:
13289 case X86::ATOMOR32:
13290 case X86::ATOMOR64:
13291 case X86::ATOMXOR8:
13292 case X86::ATOMXOR16:
13293 case X86::ATOMXOR32:
13294 case X86::ATOMXOR64: {
13295 unsigned ARITHOpc = getNonAtomicOpcode(Opc);
13296 BuildMI(mainMBB, DL, TII->get(ARITHOpc), t2).addReg(SrcReg)
13300 case X86::ATOMNAND8:
13301 case X86::ATOMNAND16:
13302 case X86::ATOMNAND32:
13303 case X86::ATOMNAND64: {
13304 unsigned Tmp = MRI.createVirtualRegister(RC);
13306 unsigned ANDOpc = getNonAtomicOpcodeWithExtraOpc(Opc, NOTOpc);
13307 BuildMI(mainMBB, DL, TII->get(ANDOpc), Tmp).addReg(SrcReg)
13309 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2).addReg(Tmp);
13312 case X86::ATOMMAX8:
13313 case X86::ATOMMAX16:
13314 case X86::ATOMMAX32:
13315 case X86::ATOMMAX64:
13316 case X86::ATOMMIN8:
13317 case X86::ATOMMIN16:
13318 case X86::ATOMMIN32:
13319 case X86::ATOMMIN64:
13320 case X86::ATOMUMAX8:
13321 case X86::ATOMUMAX16:
13322 case X86::ATOMUMAX32:
13323 case X86::ATOMUMAX64:
13324 case X86::ATOMUMIN8:
13325 case X86::ATOMUMIN16:
13326 case X86::ATOMUMIN32:
13327 case X86::ATOMUMIN64: {
13329 unsigned CMOVOpc = getNonAtomicOpcodeWithExtraOpc(Opc, CMPOpc);
13331 BuildMI(mainMBB, DL, TII->get(CMPOpc))
13335 if (Subtarget->hasCMov()) {
13336 if (VT != MVT::i8) {
13338 BuildMI(mainMBB, DL, TII->get(CMOVOpc), t2)
13342 // Promote i8 to i32 to use CMOV32
13343 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
13344 const TargetRegisterClass *RC32 =
13345 TRI->getSubClassWithSubReg(getRegClassFor(MVT::i32), X86::sub_8bit);
13346 unsigned SrcReg32 = MRI.createVirtualRegister(RC32);
13347 unsigned AccReg32 = MRI.createVirtualRegister(RC32);
13348 unsigned Tmp = MRI.createVirtualRegister(RC32);
13350 unsigned Undef = MRI.createVirtualRegister(RC32);
13351 BuildMI(mainMBB, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Undef);
13353 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), SrcReg32)
13356 .addImm(X86::sub_8bit);
13357 BuildMI(mainMBB, DL, TII->get(TargetOpcode::INSERT_SUBREG), AccReg32)
13360 .addImm(X86::sub_8bit);
13362 BuildMI(mainMBB, DL, TII->get(CMOVOpc), Tmp)
13366 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t2)
13367 .addReg(Tmp, 0, X86::sub_8bit);
13370 // Use pseudo select and lower them.
13371 assert((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) &&
13372 "Invalid atomic-load-op transformation!");
13373 unsigned SelOpc = getPseudoCMOVOpc(VT);
13374 X86::CondCode CC = X86::getCondFromCMovOpc(CMOVOpc);
13375 assert(CC != X86::COND_INVALID && "Invalid atomic-load-op transformation!");
13376 MIB = BuildMI(mainMBB, DL, TII->get(SelOpc), t2)
13377 .addReg(SrcReg).addReg(t4)
13379 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13380 // Replace the original PHI node as mainMBB is changed after CMOV
13382 BuildMI(*origMainMBB, Phi, DL, TII->get(X86::PHI), t4)
13383 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(mainMBB);
13384 Phi->eraseFromParent();
13390 // Copy PhyReg back from virtual register.
13391 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), PhyReg)
13394 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13395 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13396 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13398 NewMO.setIsKill(false);
13399 MIB.addOperand(NewMO);
13402 MIB.setMemRefs(MMOBegin, MMOEnd);
13404 // Copy PhyReg back to virtual register.
13405 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3)
13408 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13410 mainMBB->addSuccessor(origMainMBB);
13411 mainMBB->addSuccessor(sinkMBB);
13414 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13415 TII->get(TargetOpcode::COPY), DstReg)
13418 MI->eraseFromParent();
13422 // EmitAtomicLoadArith6432 - emit the code sequence for pseudo atomic
13423 // instructions. They will be translated into a spin-loop or compare-exchange
13427 // dst = atomic-fetch-op MI.addr, MI.val
13433 // t1L = LOAD [MI.addr + 0]
13434 // t1H = LOAD [MI.addr + 4]
13436 // t4L = phi(t1L, t3L / loop)
13437 // t4H = phi(t1H, t3H / loop)
13438 // t2L = OP MI.val.lo, t4L
13439 // t2H = OP MI.val.hi, t4H
13444 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13452 MachineBasicBlock *
13453 X86TargetLowering::EmitAtomicLoadArith6432(MachineInstr *MI,
13454 MachineBasicBlock *MBB) const {
13455 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13456 DebugLoc DL = MI->getDebugLoc();
13458 MachineFunction *MF = MBB->getParent();
13459 MachineRegisterInfo &MRI = MF->getRegInfo();
13461 const BasicBlock *BB = MBB->getBasicBlock();
13462 MachineFunction::iterator I = MBB;
13465 assert(MI->getNumOperands() <= X86::AddrNumOperands + 7 &&
13466 "Unexpected number of operands");
13468 assert(MI->hasOneMemOperand() &&
13469 "Expected atomic-load-op32 to have one memoperand");
13471 // Memory Reference
13472 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13473 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13475 unsigned DstLoReg, DstHiReg;
13476 unsigned SrcLoReg, SrcHiReg;
13477 unsigned MemOpndSlot;
13479 unsigned CurOp = 0;
13481 DstLoReg = MI->getOperand(CurOp++).getReg();
13482 DstHiReg = MI->getOperand(CurOp++).getReg();
13483 MemOpndSlot = CurOp;
13484 CurOp += X86::AddrNumOperands;
13485 SrcLoReg = MI->getOperand(CurOp++).getReg();
13486 SrcHiReg = MI->getOperand(CurOp++).getReg();
13488 const TargetRegisterClass *RC = &X86::GR32RegClass;
13489 const TargetRegisterClass *RC8 = &X86::GR8RegClass;
13491 unsigned t1L = MRI.createVirtualRegister(RC);
13492 unsigned t1H = MRI.createVirtualRegister(RC);
13493 unsigned t2L = MRI.createVirtualRegister(RC);
13494 unsigned t2H = MRI.createVirtualRegister(RC);
13495 unsigned t3L = MRI.createVirtualRegister(RC);
13496 unsigned t3H = MRI.createVirtualRegister(RC);
13497 unsigned t4L = MRI.createVirtualRegister(RC);
13498 unsigned t4H = MRI.createVirtualRegister(RC);
13500 unsigned LCMPXCHGOpc = X86::LCMPXCHG8B;
13501 unsigned LOADOpc = X86::MOV32rm;
13503 // For the atomic load-arith operator, we generate
13506 // t1L = LOAD [MI.addr + 0]
13507 // t1H = LOAD [MI.addr + 4]
13509 // t4L = phi(t1L / thisMBB, t3L / mainMBB)
13510 // t4H = phi(t1H / thisMBB, t3H / mainMBB)
13511 // t2L = OP MI.val.lo, t4L
13512 // t2H = OP MI.val.hi, t4H
13515 // LCMPXCHG8B [MI.addr], [ECX:EBX & EDX:EAX are implicitly used and EDX:EAX is implicitly defined]
13523 MachineBasicBlock *thisMBB = MBB;
13524 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
13525 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
13526 MF->insert(I, mainMBB);
13527 MF->insert(I, sinkMBB);
13529 MachineInstrBuilder MIB;
13531 // Transfer the remainder of BB and its successor edges to sinkMBB.
13532 sinkMBB->splice(sinkMBB->begin(), MBB,
13533 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
13534 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
13538 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1L);
13539 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13540 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13542 NewMO.setIsKill(false);
13543 MIB.addOperand(NewMO);
13545 for (MachineInstr::mmo_iterator MMOI = MMOBegin; MMOI != MMOEnd; ++MMOI) {
13546 unsigned flags = (*MMOI)->getFlags();
13547 flags = (flags & ~MachineMemOperand::MOStore) | MachineMemOperand::MOLoad;
13548 MachineMemOperand *MMO =
13549 MF->getMachineMemOperand((*MMOI)->getPointerInfo(), flags,
13550 (*MMOI)->getSize(),
13551 (*MMOI)->getBaseAlignment(),
13552 (*MMOI)->getTBAAInfo(),
13553 (*MMOI)->getRanges());
13554 MIB.addMemOperand(MMO);
13556 MachineInstr *LowMI = MIB;
13559 MIB = BuildMI(thisMBB, DL, TII->get(LOADOpc), t1H);
13560 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13561 if (i == X86::AddrDisp) {
13562 MIB.addDisp(MI->getOperand(MemOpndSlot + i), 4); // 4 == sizeof(i32)
13564 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13566 NewMO.setIsKill(false);
13567 MIB.addOperand(NewMO);
13570 MIB.setMemRefs(LowMI->memoperands_begin(), LowMI->memoperands_end());
13572 thisMBB->addSuccessor(mainMBB);
13575 MachineBasicBlock *origMainMBB = mainMBB;
13578 MachineInstr *PhiL = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4L)
13579 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
13580 MachineInstr *PhiH = BuildMI(mainMBB, DL, TII->get(X86::PHI), t4H)
13581 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
13583 unsigned Opc = MI->getOpcode();
13586 llvm_unreachable("Unhandled atomic-load-op6432 opcode!");
13587 case X86::ATOMAND6432:
13588 case X86::ATOMOR6432:
13589 case X86::ATOMXOR6432:
13590 case X86::ATOMADD6432:
13591 case X86::ATOMSUB6432: {
13593 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13594 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(t4L)
13596 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(t4H)
13600 case X86::ATOMNAND6432: {
13601 unsigned HiOpc, NOTOpc;
13602 unsigned LoOpc = getNonAtomic6432OpcodeWithExtraOpc(Opc, HiOpc, NOTOpc);
13603 unsigned TmpL = MRI.createVirtualRegister(RC);
13604 unsigned TmpH = MRI.createVirtualRegister(RC);
13605 BuildMI(mainMBB, DL, TII->get(LoOpc), TmpL).addReg(SrcLoReg)
13607 BuildMI(mainMBB, DL, TII->get(HiOpc), TmpH).addReg(SrcHiReg)
13609 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2L).addReg(TmpL);
13610 BuildMI(mainMBB, DL, TII->get(NOTOpc), t2H).addReg(TmpH);
13613 case X86::ATOMMAX6432:
13614 case X86::ATOMMIN6432:
13615 case X86::ATOMUMAX6432:
13616 case X86::ATOMUMIN6432: {
13618 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13619 unsigned cL = MRI.createVirtualRegister(RC8);
13620 unsigned cH = MRI.createVirtualRegister(RC8);
13621 unsigned cL32 = MRI.createVirtualRegister(RC);
13622 unsigned cH32 = MRI.createVirtualRegister(RC);
13623 unsigned cc = MRI.createVirtualRegister(RC);
13624 // cl := cmp src_lo, lo
13625 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13626 .addReg(SrcLoReg).addReg(t4L);
13627 BuildMI(mainMBB, DL, TII->get(LoOpc), cL);
13628 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cL32).addReg(cL);
13629 // ch := cmp src_hi, hi
13630 BuildMI(mainMBB, DL, TII->get(X86::CMP32rr))
13631 .addReg(SrcHiReg).addReg(t4H);
13632 BuildMI(mainMBB, DL, TII->get(HiOpc), cH);
13633 BuildMI(mainMBB, DL, TII->get(X86::MOVZX32rr8), cH32).addReg(cH);
13634 // cc := if (src_hi == hi) ? cl : ch;
13635 if (Subtarget->hasCMov()) {
13636 BuildMI(mainMBB, DL, TII->get(X86::CMOVE32rr), cc)
13637 .addReg(cH32).addReg(cL32);
13639 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), cc)
13640 .addReg(cH32).addReg(cL32)
13641 .addImm(X86::COND_E);
13642 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13644 BuildMI(mainMBB, DL, TII->get(X86::TEST32rr)).addReg(cc).addReg(cc);
13645 if (Subtarget->hasCMov()) {
13646 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2L)
13647 .addReg(SrcLoReg).addReg(t4L);
13648 BuildMI(mainMBB, DL, TII->get(X86::CMOVNE32rr), t2H)
13649 .addReg(SrcHiReg).addReg(t4H);
13651 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2L)
13652 .addReg(SrcLoReg).addReg(t4L)
13653 .addImm(X86::COND_NE);
13654 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13655 // As the lowered CMOV won't clobber EFLAGS, we could reuse it for the
13656 // 2nd CMOV lowering.
13657 mainMBB->addLiveIn(X86::EFLAGS);
13658 MIB = BuildMI(mainMBB, DL, TII->get(X86::CMOV_GR32), t2H)
13659 .addReg(SrcHiReg).addReg(t4H)
13660 .addImm(X86::COND_NE);
13661 mainMBB = EmitLoweredSelect(MIB, mainMBB);
13662 // Replace the original PHI node as mainMBB is changed after CMOV
13664 BuildMI(*origMainMBB, PhiL, DL, TII->get(X86::PHI), t4L)
13665 .addReg(t1L).addMBB(thisMBB).addReg(t3L).addMBB(mainMBB);
13666 BuildMI(*origMainMBB, PhiH, DL, TII->get(X86::PHI), t4H)
13667 .addReg(t1H).addMBB(thisMBB).addReg(t3H).addMBB(mainMBB);
13668 PhiL->eraseFromParent();
13669 PhiH->eraseFromParent();
13673 case X86::ATOMSWAP6432: {
13675 unsigned LoOpc = getNonAtomic6432Opcode(Opc, HiOpc);
13676 BuildMI(mainMBB, DL, TII->get(LoOpc), t2L).addReg(SrcLoReg);
13677 BuildMI(mainMBB, DL, TII->get(HiOpc), t2H).addReg(SrcHiReg);
13682 // Copy EDX:EAX back from HiReg:LoReg
13683 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EAX).addReg(t4L);
13684 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EDX).addReg(t4H);
13685 // Copy ECX:EBX from t1H:t1L
13686 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::EBX).addReg(t2L);
13687 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), X86::ECX).addReg(t2H);
13689 MIB = BuildMI(mainMBB, DL, TII->get(LCMPXCHGOpc));
13690 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
13691 MachineOperand NewMO = MI->getOperand(MemOpndSlot + i);
13693 NewMO.setIsKill(false);
13694 MIB.addOperand(NewMO);
13696 MIB.setMemRefs(MMOBegin, MMOEnd);
13698 // Copy EDX:EAX back to t3H:t3L
13699 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3L).addReg(X86::EAX);
13700 BuildMI(mainMBB, DL, TII->get(TargetOpcode::COPY), t3H).addReg(X86::EDX);
13702 BuildMI(mainMBB, DL, TII->get(X86::JNE_4)).addMBB(origMainMBB);
13704 mainMBB->addSuccessor(origMainMBB);
13705 mainMBB->addSuccessor(sinkMBB);
13708 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13709 TII->get(TargetOpcode::COPY), DstLoReg)
13711 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
13712 TII->get(TargetOpcode::COPY), DstHiReg)
13715 MI->eraseFromParent();
13719 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8
13720 // or XMM0_V32I8 in AVX all of this code can be replaced with that
13721 // in the .td file.
13722 static MachineBasicBlock *EmitPCMPSTRM(MachineInstr *MI, MachineBasicBlock *BB,
13723 const TargetInstrInfo *TII) {
13725 switch (MI->getOpcode()) {
13726 default: llvm_unreachable("illegal opcode!");
13727 case X86::PCMPISTRM128REG: Opc = X86::PCMPISTRM128rr; break;
13728 case X86::VPCMPISTRM128REG: Opc = X86::VPCMPISTRM128rr; break;
13729 case X86::PCMPISTRM128MEM: Opc = X86::PCMPISTRM128rm; break;
13730 case X86::VPCMPISTRM128MEM: Opc = X86::VPCMPISTRM128rm; break;
13731 case X86::PCMPESTRM128REG: Opc = X86::PCMPESTRM128rr; break;
13732 case X86::VPCMPESTRM128REG: Opc = X86::VPCMPESTRM128rr; break;
13733 case X86::PCMPESTRM128MEM: Opc = X86::PCMPESTRM128rm; break;
13734 case X86::VPCMPESTRM128MEM: Opc = X86::VPCMPESTRM128rm; break;
13737 DebugLoc dl = MI->getDebugLoc();
13738 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13740 unsigned NumArgs = MI->getNumOperands();
13741 for (unsigned i = 1; i < NumArgs; ++i) {
13742 MachineOperand &Op = MI->getOperand(i);
13743 if (!(Op.isReg() && Op.isImplicit()))
13744 MIB.addOperand(Op);
13746 if (MI->hasOneMemOperand())
13747 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13749 BuildMI(*BB, MI, dl,
13750 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13751 .addReg(X86::XMM0);
13753 MI->eraseFromParent();
13757 // FIXME: Custom handling because TableGen doesn't support multiple implicit
13758 // defs in an instruction pattern
13759 static MachineBasicBlock *EmitPCMPSTRI(MachineInstr *MI, MachineBasicBlock *BB,
13760 const TargetInstrInfo *TII) {
13762 switch (MI->getOpcode()) {
13763 default: llvm_unreachable("illegal opcode!");
13764 case X86::PCMPISTRIREG: Opc = X86::PCMPISTRIrr; break;
13765 case X86::VPCMPISTRIREG: Opc = X86::VPCMPISTRIrr; break;
13766 case X86::PCMPISTRIMEM: Opc = X86::PCMPISTRIrm; break;
13767 case X86::VPCMPISTRIMEM: Opc = X86::VPCMPISTRIrm; break;
13768 case X86::PCMPESTRIREG: Opc = X86::PCMPESTRIrr; break;
13769 case X86::VPCMPESTRIREG: Opc = X86::VPCMPESTRIrr; break;
13770 case X86::PCMPESTRIMEM: Opc = X86::PCMPESTRIrm; break;
13771 case X86::VPCMPESTRIMEM: Opc = X86::VPCMPESTRIrm; break;
13774 DebugLoc dl = MI->getDebugLoc();
13775 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc));
13777 unsigned NumArgs = MI->getNumOperands(); // remove the results
13778 for (unsigned i = 1; i < NumArgs; ++i) {
13779 MachineOperand &Op = MI->getOperand(i);
13780 if (!(Op.isReg() && Op.isImplicit()))
13781 MIB.addOperand(Op);
13783 if (MI->hasOneMemOperand())
13784 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
13786 BuildMI(*BB, MI, dl,
13787 TII->get(TargetOpcode::COPY), MI->getOperand(0).getReg())
13790 MI->eraseFromParent();
13794 static MachineBasicBlock * EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB,
13795 const TargetInstrInfo *TII,
13796 const X86Subtarget* Subtarget) {
13797 DebugLoc dl = MI->getDebugLoc();
13799 // Address into RAX/EAX, other two args into ECX, EDX.
13800 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
13801 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
13802 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
13803 for (int i = 0; i < X86::AddrNumOperands; ++i)
13804 MIB.addOperand(MI->getOperand(i));
13806 unsigned ValOps = X86::AddrNumOperands;
13807 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
13808 .addReg(MI->getOperand(ValOps).getReg());
13809 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX)
13810 .addReg(MI->getOperand(ValOps+1).getReg());
13812 // The instruction doesn't actually take any operands though.
13813 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr));
13815 MI->eraseFromParent(); // The pseudo is gone now.
13819 MachineBasicBlock *
13820 X86TargetLowering::EmitVAARG64WithCustomInserter(
13822 MachineBasicBlock *MBB) const {
13823 // Emit va_arg instruction on X86-64.
13825 // Operands to this pseudo-instruction:
13826 // 0 ) Output : destination address (reg)
13827 // 1-5) Input : va_list address (addr, i64mem)
13828 // 6 ) ArgSize : Size (in bytes) of vararg type
13829 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset
13830 // 8 ) Align : Alignment of type
13831 // 9 ) EFLAGS (implicit-def)
13833 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!");
13834 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands");
13836 unsigned DestReg = MI->getOperand(0).getReg();
13837 MachineOperand &Base = MI->getOperand(1);
13838 MachineOperand &Scale = MI->getOperand(2);
13839 MachineOperand &Index = MI->getOperand(3);
13840 MachineOperand &Disp = MI->getOperand(4);
13841 MachineOperand &Segment = MI->getOperand(5);
13842 unsigned ArgSize = MI->getOperand(6).getImm();
13843 unsigned ArgMode = MI->getOperand(7).getImm();
13844 unsigned Align = MI->getOperand(8).getImm();
13846 // Memory Reference
13847 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand");
13848 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
13849 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
13851 // Machine Information
13852 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
13853 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
13854 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
13855 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
13856 DebugLoc DL = MI->getDebugLoc();
13858 // struct va_list {
13861 // i64 overflow_area (address)
13862 // i64 reg_save_area (address)
13864 // sizeof(va_list) = 24
13865 // alignment(va_list) = 8
13867 unsigned TotalNumIntRegs = 6;
13868 unsigned TotalNumXMMRegs = 8;
13869 bool UseGPOffset = (ArgMode == 1);
13870 bool UseFPOffset = (ArgMode == 2);
13871 unsigned MaxOffset = TotalNumIntRegs * 8 +
13872 (UseFPOffset ? TotalNumXMMRegs * 16 : 0);
13874 /* Align ArgSize to a multiple of 8 */
13875 unsigned ArgSizeA8 = (ArgSize + 7) & ~7;
13876 bool NeedsAlign = (Align > 8);
13878 MachineBasicBlock *thisMBB = MBB;
13879 MachineBasicBlock *overflowMBB;
13880 MachineBasicBlock *offsetMBB;
13881 MachineBasicBlock *endMBB;
13883 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB
13884 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB
13885 unsigned OffsetReg = 0;
13887 if (!UseGPOffset && !UseFPOffset) {
13888 // If we only pull from the overflow region, we don't create a branch.
13889 // We don't need to alter control flow.
13890 OffsetDestReg = 0; // unused
13891 OverflowDestReg = DestReg;
13894 overflowMBB = thisMBB;
13897 // First emit code to check if gp_offset (or fp_offset) is below the bound.
13898 // If so, pull the argument from reg_save_area. (branch to offsetMBB)
13899 // If not, pull from overflow_area. (branch to overflowMBB)
13904 // offsetMBB overflowMBB
13909 // Registers for the PHI in endMBB
13910 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass);
13911 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass);
13913 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
13914 MachineFunction *MF = MBB->getParent();
13915 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13916 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13917 endMBB = MF->CreateMachineBasicBlock(LLVM_BB);
13919 MachineFunction::iterator MBBIter = MBB;
13922 // Insert the new basic blocks
13923 MF->insert(MBBIter, offsetMBB);
13924 MF->insert(MBBIter, overflowMBB);
13925 MF->insert(MBBIter, endMBB);
13927 // Transfer the remainder of MBB and its successor edges to endMBB.
13928 endMBB->splice(endMBB->begin(), thisMBB,
13929 llvm::next(MachineBasicBlock::iterator(MI)),
13931 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB);
13933 // Make offsetMBB and overflowMBB successors of thisMBB
13934 thisMBB->addSuccessor(offsetMBB);
13935 thisMBB->addSuccessor(overflowMBB);
13937 // endMBB is a successor of both offsetMBB and overflowMBB
13938 offsetMBB->addSuccessor(endMBB);
13939 overflowMBB->addSuccessor(endMBB);
13941 // Load the offset value into a register
13942 OffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13943 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg)
13947 .addDisp(Disp, UseFPOffset ? 4 : 0)
13948 .addOperand(Segment)
13949 .setMemRefs(MMOBegin, MMOEnd);
13951 // Check if there is enough room left to pull this argument.
13952 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri))
13954 .addImm(MaxOffset + 8 - ArgSizeA8);
13956 // Branch to "overflowMBB" if offset >= max
13957 // Fall through to "offsetMBB" otherwise
13958 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE)))
13959 .addMBB(overflowMBB);
13962 // In offsetMBB, emit code to use the reg_save_area.
13964 assert(OffsetReg != 0);
13966 // Read the reg_save_area address.
13967 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass);
13968 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg)
13973 .addOperand(Segment)
13974 .setMemRefs(MMOBegin, MMOEnd);
13976 // Zero-extend the offset
13977 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass);
13978 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64)
13981 .addImm(X86::sub_32bit);
13983 // Add the offset to the reg_save_area to get the final address.
13984 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg)
13985 .addReg(OffsetReg64)
13986 .addReg(RegSaveReg);
13988 // Compute the offset for the next argument
13989 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass);
13990 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg)
13992 .addImm(UseFPOffset ? 16 : 8);
13994 // Store it back into the va_list.
13995 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr))
13999 .addDisp(Disp, UseFPOffset ? 4 : 0)
14000 .addOperand(Segment)
14001 .addReg(NextOffsetReg)
14002 .setMemRefs(MMOBegin, MMOEnd);
14005 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4))
14010 // Emit code to use overflow area
14013 // Load the overflow_area address into a register.
14014 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass);
14015 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg)
14020 .addOperand(Segment)
14021 .setMemRefs(MMOBegin, MMOEnd);
14023 // If we need to align it, do so. Otherwise, just copy the address
14024 // to OverflowDestReg.
14026 // Align the overflow address
14027 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2");
14028 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass);
14030 // aligned_addr = (addr + (align-1)) & ~(align-1)
14031 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg)
14032 .addReg(OverflowAddrReg)
14035 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg)
14037 .addImm(~(uint64_t)(Align-1));
14039 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg)
14040 .addReg(OverflowAddrReg);
14043 // Compute the next overflow address after this argument.
14044 // (the overflow address should be kept 8-byte aligned)
14045 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass);
14046 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg)
14047 .addReg(OverflowDestReg)
14048 .addImm(ArgSizeA8);
14050 // Store the new overflow address.
14051 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr))
14056 .addOperand(Segment)
14057 .addReg(NextAddrReg)
14058 .setMemRefs(MMOBegin, MMOEnd);
14060 // If we branched, emit the PHI to the front of endMBB.
14062 BuildMI(*endMBB, endMBB->begin(), DL,
14063 TII->get(X86::PHI), DestReg)
14064 .addReg(OffsetDestReg).addMBB(offsetMBB)
14065 .addReg(OverflowDestReg).addMBB(overflowMBB);
14068 // Erase the pseudo instruction
14069 MI->eraseFromParent();
14074 MachineBasicBlock *
14075 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter(
14077 MachineBasicBlock *MBB) const {
14078 // Emit code to save XMM registers to the stack. The ABI says that the
14079 // number of registers to save is given in %al, so it's theoretically
14080 // possible to do an indirect jump trick to avoid saving all of them,
14081 // however this code takes a simpler approach and just executes all
14082 // of the stores if %al is non-zero. It's less code, and it's probably
14083 // easier on the hardware branch predictor, and stores aren't all that
14084 // expensive anyway.
14086 // Create the new basic blocks. One block contains all the XMM stores,
14087 // and one block is the final destination regardless of whether any
14088 // stores were performed.
14089 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
14090 MachineFunction *F = MBB->getParent();
14091 MachineFunction::iterator MBBIter = MBB;
14093 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB);
14094 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB);
14095 F->insert(MBBIter, XMMSaveMBB);
14096 F->insert(MBBIter, EndMBB);
14098 // Transfer the remainder of MBB and its successor edges to EndMBB.
14099 EndMBB->splice(EndMBB->begin(), MBB,
14100 llvm::next(MachineBasicBlock::iterator(MI)),
14102 EndMBB->transferSuccessorsAndUpdatePHIs(MBB);
14104 // The original block will now fall through to the XMM save block.
14105 MBB->addSuccessor(XMMSaveMBB);
14106 // The XMMSaveMBB will fall through to the end block.
14107 XMMSaveMBB->addSuccessor(EndMBB);
14109 // Now add the instructions.
14110 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14111 DebugLoc DL = MI->getDebugLoc();
14113 unsigned CountReg = MI->getOperand(0).getReg();
14114 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm();
14115 int64_t VarArgsFPOffset = MI->getOperand(2).getImm();
14117 if (!Subtarget->isTargetWin64()) {
14118 // If %al is 0, branch around the XMM save block.
14119 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
14120 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB);
14121 MBB->addSuccessor(EndMBB);
14124 unsigned MOVOpc = Subtarget->hasFp256() ? X86::VMOVAPSmr : X86::MOVAPSmr;
14125 // In the XMM save block, save all the XMM argument registers.
14126 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) {
14127 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset;
14128 MachineMemOperand *MMO =
14129 F->getMachineMemOperand(
14130 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset),
14131 MachineMemOperand::MOStore,
14132 /*Size=*/16, /*Align=*/16);
14133 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc))
14134 .addFrameIndex(RegSaveFrameIndex)
14135 .addImm(/*Scale=*/1)
14136 .addReg(/*IndexReg=*/0)
14137 .addImm(/*Disp=*/Offset)
14138 .addReg(/*Segment=*/0)
14139 .addReg(MI->getOperand(i).getReg())
14140 .addMemOperand(MMO);
14143 MI->eraseFromParent(); // The pseudo instruction is gone now.
14148 // The EFLAGS operand of SelectItr might be missing a kill marker
14149 // because there were multiple uses of EFLAGS, and ISel didn't know
14150 // which to mark. Figure out whether SelectItr should have had a
14151 // kill marker, and set it if it should. Returns the correct kill
14153 static bool checkAndUpdateEFLAGSKill(MachineBasicBlock::iterator SelectItr,
14154 MachineBasicBlock* BB,
14155 const TargetRegisterInfo* TRI) {
14156 // Scan forward through BB for a use/def of EFLAGS.
14157 MachineBasicBlock::iterator miI(llvm::next(SelectItr));
14158 for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) {
14159 const MachineInstr& mi = *miI;
14160 if (mi.readsRegister(X86::EFLAGS))
14162 if (mi.definesRegister(X86::EFLAGS))
14163 break; // Should have kill-flag - update below.
14166 // If we hit the end of the block, check whether EFLAGS is live into a
14168 if (miI == BB->end()) {
14169 for (MachineBasicBlock::succ_iterator sItr = BB->succ_begin(),
14170 sEnd = BB->succ_end();
14171 sItr != sEnd; ++sItr) {
14172 MachineBasicBlock* succ = *sItr;
14173 if (succ->isLiveIn(X86::EFLAGS))
14178 // We found a def, or hit the end of the basic block and EFLAGS wasn't live
14179 // out. SelectMI should have a kill flag on EFLAGS.
14180 SelectItr->addRegisterKilled(X86::EFLAGS, TRI);
14184 MachineBasicBlock *
14185 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI,
14186 MachineBasicBlock *BB) const {
14187 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14188 DebugLoc DL = MI->getDebugLoc();
14190 // To "insert" a SELECT_CC instruction, we actually have to insert the
14191 // diamond control-flow pattern. The incoming instruction knows the
14192 // destination vreg to set, the condition code register to branch on, the
14193 // true/false values to select between, and a branch opcode to use.
14194 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14195 MachineFunction::iterator It = BB;
14201 // cmpTY ccX, r1, r2
14203 // fallthrough --> copy0MBB
14204 MachineBasicBlock *thisMBB = BB;
14205 MachineFunction *F = BB->getParent();
14206 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
14207 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
14208 F->insert(It, copy0MBB);
14209 F->insert(It, sinkMBB);
14211 // If the EFLAGS register isn't dead in the terminator, then claim that it's
14212 // live into the sink and copy blocks.
14213 const TargetRegisterInfo* TRI = getTargetMachine().getRegisterInfo();
14214 if (!MI->killsRegister(X86::EFLAGS) &&
14215 !checkAndUpdateEFLAGSKill(MI, BB, TRI)) {
14216 copy0MBB->addLiveIn(X86::EFLAGS);
14217 sinkMBB->addLiveIn(X86::EFLAGS);
14220 // Transfer the remainder of BB and its successor edges to sinkMBB.
14221 sinkMBB->splice(sinkMBB->begin(), BB,
14222 llvm::next(MachineBasicBlock::iterator(MI)),
14224 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
14226 // Add the true and fallthrough blocks as its successors.
14227 BB->addSuccessor(copy0MBB);
14228 BB->addSuccessor(sinkMBB);
14230 // Create the conditional branch instruction.
14232 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm());
14233 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB);
14236 // %FalseValue = ...
14237 // # fallthrough to sinkMBB
14238 copy0MBB->addSuccessor(sinkMBB);
14241 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
14243 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14244 TII->get(X86::PHI), MI->getOperand(0).getReg())
14245 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
14246 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
14248 MI->eraseFromParent(); // The pseudo instruction is gone now.
14252 MachineBasicBlock *
14253 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB,
14254 bool Is64Bit) const {
14255 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14256 DebugLoc DL = MI->getDebugLoc();
14257 MachineFunction *MF = BB->getParent();
14258 const BasicBlock *LLVM_BB = BB->getBasicBlock();
14260 assert(getTargetMachine().Options.EnableSegmentedStacks);
14262 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS;
14263 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30;
14266 // ... [Till the alloca]
14267 // If stacklet is not large enough, jump to mallocMBB
14270 // Allocate by subtracting from RSP
14271 // Jump to continueMBB
14274 // Allocate by call to runtime
14278 // [rest of original BB]
14281 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14282 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14283 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB);
14285 MachineRegisterInfo &MRI = MF->getRegInfo();
14286 const TargetRegisterClass *AddrRegClass =
14287 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32);
14289 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14290 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass),
14291 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass),
14292 SPLimitVReg = MRI.createVirtualRegister(AddrRegClass),
14293 sizeVReg = MI->getOperand(1).getReg(),
14294 physSPReg = Is64Bit ? X86::RSP : X86::ESP;
14296 MachineFunction::iterator MBBIter = BB;
14299 MF->insert(MBBIter, bumpMBB);
14300 MF->insert(MBBIter, mallocMBB);
14301 MF->insert(MBBIter, continueMBB);
14303 continueMBB->splice(continueMBB->begin(), BB, llvm::next
14304 (MachineBasicBlock::iterator(MI)), BB->end());
14305 continueMBB->transferSuccessorsAndUpdatePHIs(BB);
14307 // Add code to the main basic block to check if the stack limit has been hit,
14308 // and if so, jump to mallocMBB otherwise to bumpMBB.
14309 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
14310 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), SPLimitVReg)
14311 .addReg(tmpSPVReg).addReg(sizeVReg);
14312 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr))
14313 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
14314 .addReg(SPLimitVReg);
14315 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB);
14317 // bumpMBB simply decreases the stack pointer, since we know the current
14318 // stacklet has enough space.
14319 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg)
14320 .addReg(SPLimitVReg);
14321 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg)
14322 .addReg(SPLimitVReg);
14323 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14325 // Calls into a routine in libgcc to allocate more space from the heap.
14326 const uint32_t *RegMask =
14327 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14329 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI)
14331 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32))
14332 .addExternalSymbol("__morestack_allocate_stack_space")
14333 .addRegMask(RegMask)
14334 .addReg(X86::RDI, RegState::Implicit)
14335 .addReg(X86::RAX, RegState::ImplicitDefine);
14337 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
14339 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
14340 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32))
14341 .addExternalSymbol("__morestack_allocate_stack_space")
14342 .addRegMask(RegMask)
14343 .addReg(X86::EAX, RegState::ImplicitDefine);
14347 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
14350 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg)
14351 .addReg(Is64Bit ? X86::RAX : X86::EAX);
14352 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB);
14354 // Set up the CFG correctly.
14355 BB->addSuccessor(bumpMBB);
14356 BB->addSuccessor(mallocMBB);
14357 mallocMBB->addSuccessor(continueMBB);
14358 bumpMBB->addSuccessor(continueMBB);
14360 // Take care of the PHI nodes.
14361 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
14362 MI->getOperand(0).getReg())
14363 .addReg(mallocPtrVReg).addMBB(mallocMBB)
14364 .addReg(bumpSPPtrVReg).addMBB(bumpMBB);
14366 // Delete the original pseudo instruction.
14367 MI->eraseFromParent();
14370 return continueMBB;
14373 MachineBasicBlock *
14374 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI,
14375 MachineBasicBlock *BB) const {
14376 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14377 DebugLoc DL = MI->getDebugLoc();
14379 assert(!Subtarget->isTargetEnvMacho());
14381 // The lowering is pretty easy: we're just emitting the call to _alloca. The
14382 // non-trivial part is impdef of ESP.
14384 if (Subtarget->isTargetWin64()) {
14385 if (Subtarget->isTargetCygMing()) {
14386 // ___chkstk(Mingw64):
14387 // Clobbers R10, R11, RAX and EFLAGS.
14389 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14390 .addExternalSymbol("___chkstk")
14391 .addReg(X86::RAX, RegState::Implicit)
14392 .addReg(X86::RSP, RegState::Implicit)
14393 .addReg(X86::RAX, RegState::Define | RegState::Implicit)
14394 .addReg(X86::RSP, RegState::Define | RegState::Implicit)
14395 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14397 // __chkstk(MSVCRT): does not update stack pointer.
14398 // Clobbers R10, R11 and EFLAGS.
14399 // FIXME: RAX(allocated size) might be reused and not killed.
14400 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA))
14401 .addExternalSymbol("__chkstk")
14402 .addReg(X86::RAX, RegState::Implicit)
14403 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14404 // RAX has the offset to subtracted from RSP.
14405 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP)
14410 const char *StackProbeSymbol =
14411 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca";
14413 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32))
14414 .addExternalSymbol(StackProbeSymbol)
14415 .addReg(X86::EAX, RegState::Implicit)
14416 .addReg(X86::ESP, RegState::Implicit)
14417 .addReg(X86::EAX, RegState::Define | RegState::Implicit)
14418 .addReg(X86::ESP, RegState::Define | RegState::Implicit)
14419 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
14422 MI->eraseFromParent(); // The pseudo instruction is gone now.
14426 MachineBasicBlock *
14427 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
14428 MachineBasicBlock *BB) const {
14429 // This is pretty easy. We're taking the value that we received from
14430 // our load from the relocation, sticking it in either RDI (x86-64)
14431 // or EAX and doing an indirect call. The return value will then
14432 // be in the normal return register.
14433 const X86InstrInfo *TII
14434 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
14435 DebugLoc DL = MI->getDebugLoc();
14436 MachineFunction *F = BB->getParent();
14438 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
14439 assert(MI->getOperand(3).isGlobal() && "This should be a global");
14441 // Get a register mask for the lowered call.
14442 // FIXME: The 32-bit calls have non-standard calling conventions. Use a
14443 // proper register mask.
14444 const uint32_t *RegMask =
14445 getTargetMachine().getRegisterInfo()->getCallPreservedMask(CallingConv::C);
14446 if (Subtarget->is64Bit()) {
14447 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14448 TII->get(X86::MOV64rm), X86::RDI)
14450 .addImm(0).addReg(0)
14451 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14452 MI->getOperand(3).getTargetFlags())
14454 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
14455 addDirectMem(MIB, X86::RDI);
14456 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
14457 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
14458 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14459 TII->get(X86::MOV32rm), X86::EAX)
14461 .addImm(0).addReg(0)
14462 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14463 MI->getOperand(3).getTargetFlags())
14465 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14466 addDirectMem(MIB, X86::EAX);
14467 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14469 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
14470 TII->get(X86::MOV32rm), X86::EAX)
14471 .addReg(TII->getGlobalBaseReg(F))
14472 .addImm(0).addReg(0)
14473 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
14474 MI->getOperand(3).getTargetFlags())
14476 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
14477 addDirectMem(MIB, X86::EAX);
14478 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
14481 MI->eraseFromParent(); // The pseudo instruction is gone now.
14485 MachineBasicBlock *
14486 X86TargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
14487 MachineBasicBlock *MBB) const {
14488 DebugLoc DL = MI->getDebugLoc();
14489 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14491 MachineFunction *MF = MBB->getParent();
14492 MachineRegisterInfo &MRI = MF->getRegInfo();
14494 const BasicBlock *BB = MBB->getBasicBlock();
14495 MachineFunction::iterator I = MBB;
14498 // Memory Reference
14499 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14500 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14503 unsigned MemOpndSlot = 0;
14505 unsigned CurOp = 0;
14507 DstReg = MI->getOperand(CurOp++).getReg();
14508 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
14509 assert(RC->hasType(MVT::i32) && "Invalid destination!");
14510 unsigned mainDstReg = MRI.createVirtualRegister(RC);
14511 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
14513 MemOpndSlot = CurOp;
14515 MVT PVT = getPointerTy();
14516 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14517 "Invalid Pointer Size!");
14519 // For v = setjmp(buf), we generate
14522 // buf[LabelOffset] = restoreMBB
14523 // SjLjSetup restoreMBB
14529 // v = phi(main, restore)
14534 MachineBasicBlock *thisMBB = MBB;
14535 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
14536 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
14537 MachineBasicBlock *restoreMBB = MF->CreateMachineBasicBlock(BB);
14538 MF->insert(I, mainMBB);
14539 MF->insert(I, sinkMBB);
14540 MF->push_back(restoreMBB);
14542 MachineInstrBuilder MIB;
14544 // Transfer the remainder of BB and its successor edges to sinkMBB.
14545 sinkMBB->splice(sinkMBB->begin(), MBB,
14546 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
14547 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
14550 unsigned PtrStoreOpc = 0;
14551 unsigned LabelReg = 0;
14552 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14553 Reloc::Model RM = getTargetMachine().getRelocationModel();
14554 bool UseImmLabel = (getTargetMachine().getCodeModel() == CodeModel::Small) &&
14555 (RM == Reloc::Static || RM == Reloc::DynamicNoPIC);
14557 // Prepare IP either in reg or imm.
14558 if (!UseImmLabel) {
14559 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mr : X86::MOV32mr;
14560 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
14561 LabelReg = MRI.createVirtualRegister(PtrRC);
14562 if (Subtarget->is64Bit()) {
14563 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
14567 .addMBB(restoreMBB)
14570 const X86InstrInfo *XII = static_cast<const X86InstrInfo*>(TII);
14571 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
14572 .addReg(XII->getGlobalBaseReg(MF))
14575 .addMBB(restoreMBB, Subtarget->ClassifyBlockAddressReference())
14579 PtrStoreOpc = (PVT == MVT::i64) ? X86::MOV64mi32 : X86::MOV32mi;
14581 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrStoreOpc));
14582 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14583 if (i == X86::AddrDisp)
14584 MIB.addDisp(MI->getOperand(MemOpndSlot + i), LabelOffset);
14586 MIB.addOperand(MI->getOperand(MemOpndSlot + i));
14589 MIB.addReg(LabelReg);
14591 MIB.addMBB(restoreMBB);
14592 MIB.setMemRefs(MMOBegin, MMOEnd);
14594 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::EH_SjLj_Setup))
14595 .addMBB(restoreMBB);
14596 MIB.addRegMask(RegInfo->getNoPreservedMask());
14597 thisMBB->addSuccessor(mainMBB);
14598 thisMBB->addSuccessor(restoreMBB);
14602 BuildMI(mainMBB, DL, TII->get(X86::MOV32r0), mainDstReg);
14603 mainMBB->addSuccessor(sinkMBB);
14606 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
14607 TII->get(X86::PHI), DstReg)
14608 .addReg(mainDstReg).addMBB(mainMBB)
14609 .addReg(restoreDstReg).addMBB(restoreMBB);
14612 BuildMI(restoreMBB, DL, TII->get(X86::MOV32ri), restoreDstReg).addImm(1);
14613 BuildMI(restoreMBB, DL, TII->get(X86::JMP_4)).addMBB(sinkMBB);
14614 restoreMBB->addSuccessor(sinkMBB);
14616 MI->eraseFromParent();
14620 MachineBasicBlock *
14621 X86TargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
14622 MachineBasicBlock *MBB) const {
14623 DebugLoc DL = MI->getDebugLoc();
14624 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14626 MachineFunction *MF = MBB->getParent();
14627 MachineRegisterInfo &MRI = MF->getRegInfo();
14629 // Memory Reference
14630 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
14631 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
14633 MVT PVT = getPointerTy();
14634 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
14635 "Invalid Pointer Size!");
14637 const TargetRegisterClass *RC =
14638 (PVT == MVT::i64) ? &X86::GR64RegClass : &X86::GR32RegClass;
14639 unsigned Tmp = MRI.createVirtualRegister(RC);
14640 // Since FP is only updated here but NOT referenced, it's treated as GPR.
14641 unsigned FP = (PVT == MVT::i64) ? X86::RBP : X86::EBP;
14642 unsigned SP = RegInfo->getStackRegister();
14644 MachineInstrBuilder MIB;
14646 const int64_t LabelOffset = 1 * PVT.getStoreSize();
14647 const int64_t SPOffset = 2 * PVT.getStoreSize();
14649 unsigned PtrLoadOpc = (PVT == MVT::i64) ? X86::MOV64rm : X86::MOV32rm;
14650 unsigned IJmpOpc = (PVT == MVT::i64) ? X86::JMP64r : X86::JMP32r;
14653 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), FP);
14654 for (unsigned i = 0; i < X86::AddrNumOperands; ++i)
14655 MIB.addOperand(MI->getOperand(i));
14656 MIB.setMemRefs(MMOBegin, MMOEnd);
14658 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
14659 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14660 if (i == X86::AddrDisp)
14661 MIB.addDisp(MI->getOperand(i), LabelOffset);
14663 MIB.addOperand(MI->getOperand(i));
14665 MIB.setMemRefs(MMOBegin, MMOEnd);
14667 MIB = BuildMI(*MBB, MI, DL, TII->get(PtrLoadOpc), SP);
14668 for (unsigned i = 0; i < X86::AddrNumOperands; ++i) {
14669 if (i == X86::AddrDisp)
14670 MIB.addDisp(MI->getOperand(i), SPOffset);
14672 MIB.addOperand(MI->getOperand(i));
14674 MIB.setMemRefs(MMOBegin, MMOEnd);
14676 BuildMI(*MBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
14678 MI->eraseFromParent();
14682 MachineBasicBlock *
14683 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
14684 MachineBasicBlock *BB) const {
14685 switch (MI->getOpcode()) {
14686 default: llvm_unreachable("Unexpected instr type to insert");
14687 case X86::TAILJMPd64:
14688 case X86::TAILJMPr64:
14689 case X86::TAILJMPm64:
14690 llvm_unreachable("TAILJMP64 would not be touched here.");
14691 case X86::TCRETURNdi64:
14692 case X86::TCRETURNri64:
14693 case X86::TCRETURNmi64:
14695 case X86::WIN_ALLOCA:
14696 return EmitLoweredWinAlloca(MI, BB);
14697 case X86::SEG_ALLOCA_32:
14698 return EmitLoweredSegAlloca(MI, BB, false);
14699 case X86::SEG_ALLOCA_64:
14700 return EmitLoweredSegAlloca(MI, BB, true);
14701 case X86::TLSCall_32:
14702 case X86::TLSCall_64:
14703 return EmitLoweredTLSCall(MI, BB);
14704 case X86::CMOV_GR8:
14705 case X86::CMOV_FR32:
14706 case X86::CMOV_FR64:
14707 case X86::CMOV_V4F32:
14708 case X86::CMOV_V2F64:
14709 case X86::CMOV_V2I64:
14710 case X86::CMOV_V8F32:
14711 case X86::CMOV_V4F64:
14712 case X86::CMOV_V4I64:
14713 case X86::CMOV_GR16:
14714 case X86::CMOV_GR32:
14715 case X86::CMOV_RFP32:
14716 case X86::CMOV_RFP64:
14717 case X86::CMOV_RFP80:
14718 return EmitLoweredSelect(MI, BB);
14720 case X86::FP32_TO_INT16_IN_MEM:
14721 case X86::FP32_TO_INT32_IN_MEM:
14722 case X86::FP32_TO_INT64_IN_MEM:
14723 case X86::FP64_TO_INT16_IN_MEM:
14724 case X86::FP64_TO_INT32_IN_MEM:
14725 case X86::FP64_TO_INT64_IN_MEM:
14726 case X86::FP80_TO_INT16_IN_MEM:
14727 case X86::FP80_TO_INT32_IN_MEM:
14728 case X86::FP80_TO_INT64_IN_MEM: {
14729 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
14730 DebugLoc DL = MI->getDebugLoc();
14732 // Change the floating point control register to use "round towards zero"
14733 // mode when truncating to an integer value.
14734 MachineFunction *F = BB->getParent();
14735 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false);
14736 addFrameReference(BuildMI(*BB, MI, DL,
14737 TII->get(X86::FNSTCW16m)), CWFrameIdx);
14739 // Load the old value of the high byte of the control word...
14741 F->getRegInfo().createVirtualRegister(&X86::GR16RegClass);
14742 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW),
14745 // Set the high part to be round to zero...
14746 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx)
14749 // Reload the modified control word now...
14750 addFrameReference(BuildMI(*BB, MI, DL,
14751 TII->get(X86::FLDCW16m)), CWFrameIdx);
14753 // Restore the memory image of control word to original value
14754 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx)
14757 // Get the X86 opcode to use.
14759 switch (MI->getOpcode()) {
14760 default: llvm_unreachable("illegal opcode!");
14761 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break;
14762 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break;
14763 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break;
14764 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break;
14765 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break;
14766 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break;
14767 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break;
14768 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break;
14769 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break;
14773 MachineOperand &Op = MI->getOperand(0);
14775 AM.BaseType = X86AddressMode::RegBase;
14776 AM.Base.Reg = Op.getReg();
14778 AM.BaseType = X86AddressMode::FrameIndexBase;
14779 AM.Base.FrameIndex = Op.getIndex();
14781 Op = MI->getOperand(1);
14783 AM.Scale = Op.getImm();
14784 Op = MI->getOperand(2);
14786 AM.IndexReg = Op.getImm();
14787 Op = MI->getOperand(3);
14788 if (Op.isGlobal()) {
14789 AM.GV = Op.getGlobal();
14791 AM.Disp = Op.getImm();
14793 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM)
14794 .addReg(MI->getOperand(X86::AddrNumOperands).getReg());
14796 // Reload the original control word now.
14797 addFrameReference(BuildMI(*BB, MI, DL,
14798 TII->get(X86::FLDCW16m)), CWFrameIdx);
14800 MI->eraseFromParent(); // The pseudo instruction is gone now.
14803 // String/text processing lowering.
14804 case X86::PCMPISTRM128REG:
14805 case X86::VPCMPISTRM128REG:
14806 case X86::PCMPISTRM128MEM:
14807 case X86::VPCMPISTRM128MEM:
14808 case X86::PCMPESTRM128REG:
14809 case X86::VPCMPESTRM128REG:
14810 case X86::PCMPESTRM128MEM:
14811 case X86::VPCMPESTRM128MEM:
14812 assert(Subtarget->hasSSE42() &&
14813 "Target must have SSE4.2 or AVX features enabled");
14814 return EmitPCMPSTRM(MI, BB, getTargetMachine().getInstrInfo());
14816 // String/text processing lowering.
14817 case X86::PCMPISTRIREG:
14818 case X86::VPCMPISTRIREG:
14819 case X86::PCMPISTRIMEM:
14820 case X86::VPCMPISTRIMEM:
14821 case X86::PCMPESTRIREG:
14822 case X86::VPCMPESTRIREG:
14823 case X86::PCMPESTRIMEM:
14824 case X86::VPCMPESTRIMEM:
14825 assert(Subtarget->hasSSE42() &&
14826 "Target must have SSE4.2 or AVX features enabled");
14827 return EmitPCMPSTRI(MI, BB, getTargetMachine().getInstrInfo());
14829 // Thread synchronization.
14831 return EmitMonitor(MI, BB, getTargetMachine().getInstrInfo(), Subtarget);
14835 return EmitXBegin(MI, BB, getTargetMachine().getInstrInfo());
14837 // Atomic Lowering.
14838 case X86::ATOMAND8:
14839 case X86::ATOMAND16:
14840 case X86::ATOMAND32:
14841 case X86::ATOMAND64:
14844 case X86::ATOMOR16:
14845 case X86::ATOMOR32:
14846 case X86::ATOMOR64:
14848 case X86::ATOMXOR16:
14849 case X86::ATOMXOR8:
14850 case X86::ATOMXOR32:
14851 case X86::ATOMXOR64:
14853 case X86::ATOMNAND8:
14854 case X86::ATOMNAND16:
14855 case X86::ATOMNAND32:
14856 case X86::ATOMNAND64:
14858 case X86::ATOMMAX8:
14859 case X86::ATOMMAX16:
14860 case X86::ATOMMAX32:
14861 case X86::ATOMMAX64:
14863 case X86::ATOMMIN8:
14864 case X86::ATOMMIN16:
14865 case X86::ATOMMIN32:
14866 case X86::ATOMMIN64:
14868 case X86::ATOMUMAX8:
14869 case X86::ATOMUMAX16:
14870 case X86::ATOMUMAX32:
14871 case X86::ATOMUMAX64:
14873 case X86::ATOMUMIN8:
14874 case X86::ATOMUMIN16:
14875 case X86::ATOMUMIN32:
14876 case X86::ATOMUMIN64:
14877 return EmitAtomicLoadArith(MI, BB);
14879 // This group does 64-bit operations on a 32-bit host.
14880 case X86::ATOMAND6432:
14881 case X86::ATOMOR6432:
14882 case X86::ATOMXOR6432:
14883 case X86::ATOMNAND6432:
14884 case X86::ATOMADD6432:
14885 case X86::ATOMSUB6432:
14886 case X86::ATOMMAX6432:
14887 case X86::ATOMMIN6432:
14888 case X86::ATOMUMAX6432:
14889 case X86::ATOMUMIN6432:
14890 case X86::ATOMSWAP6432:
14891 return EmitAtomicLoadArith6432(MI, BB);
14893 case X86::VASTART_SAVE_XMM_REGS:
14894 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
14896 case X86::VAARG_64:
14897 return EmitVAARG64WithCustomInserter(MI, BB);
14899 case X86::EH_SjLj_SetJmp32:
14900 case X86::EH_SjLj_SetJmp64:
14901 return emitEHSjLjSetJmp(MI, BB);
14903 case X86::EH_SjLj_LongJmp32:
14904 case X86::EH_SjLj_LongJmp64:
14905 return emitEHSjLjLongJmp(MI, BB);
14909 //===----------------------------------------------------------------------===//
14910 // X86 Optimization Hooks
14911 //===----------------------------------------------------------------------===//
14913 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
14916 const SelectionDAG &DAG,
14917 unsigned Depth) const {
14918 unsigned BitWidth = KnownZero.getBitWidth();
14919 unsigned Opc = Op.getOpcode();
14920 assert((Opc >= ISD::BUILTIN_OP_END ||
14921 Opc == ISD::INTRINSIC_WO_CHAIN ||
14922 Opc == ISD::INTRINSIC_W_CHAIN ||
14923 Opc == ISD::INTRINSIC_VOID) &&
14924 "Should use MaskedValueIsZero if you don't know whether Op"
14925 " is a target node!");
14927 KnownZero = KnownOne = APInt(BitWidth, 0); // Don't know anything.
14941 // These nodes' second result is a boolean.
14942 if (Op.getResNo() == 0)
14945 case X86ISD::SETCC:
14946 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
14948 case ISD::INTRINSIC_WO_CHAIN: {
14949 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
14950 unsigned NumLoBits = 0;
14953 case Intrinsic::x86_sse_movmsk_ps:
14954 case Intrinsic::x86_avx_movmsk_ps_256:
14955 case Intrinsic::x86_sse2_movmsk_pd:
14956 case Intrinsic::x86_avx_movmsk_pd_256:
14957 case Intrinsic::x86_mmx_pmovmskb:
14958 case Intrinsic::x86_sse2_pmovmskb_128:
14959 case Intrinsic::x86_avx2_pmovmskb: {
14960 // High bits of movmskp{s|d}, pmovmskb are known zero.
14962 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
14963 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
14964 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
14965 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
14966 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
14967 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
14968 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
14969 case Intrinsic::x86_avx2_pmovmskb: NumLoBits = 32; break;
14971 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - NumLoBits);
14980 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
14981 unsigned Depth) const {
14982 // SETCC_CARRY sets the dest to ~0 for true or 0 for false.
14983 if (Op.getOpcode() == X86ISD::SETCC_CARRY)
14984 return Op.getValueType().getScalarType().getSizeInBits();
14990 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
14991 /// node is a GlobalAddress + offset.
14992 bool X86TargetLowering::isGAPlusOffset(SDNode *N,
14993 const GlobalValue* &GA,
14994 int64_t &Offset) const {
14995 if (N->getOpcode() == X86ISD::Wrapper) {
14996 if (isa<GlobalAddressSDNode>(N->getOperand(0))) {
14997 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal();
14998 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset();
15002 return TargetLowering::isGAPlusOffset(N, GA, Offset);
15005 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the
15006 /// same as extracting the high 128-bit part of 256-bit vector and then
15007 /// inserting the result into the low part of a new 256-bit vector
15008 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) {
15009 EVT VT = SVOp->getValueType(0);
15010 unsigned NumElems = VT.getVectorNumElements();
15012 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15013 for (unsigned i = 0, j = NumElems/2; i != NumElems/2; ++i, ++j)
15014 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15015 SVOp->getMaskElt(j) >= 0)
15021 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the
15022 /// same as extracting the low 128-bit part of 256-bit vector and then
15023 /// inserting the result into the high part of a new 256-bit vector
15024 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) {
15025 EVT VT = SVOp->getValueType(0);
15026 unsigned NumElems = VT.getVectorNumElements();
15028 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15029 for (unsigned i = NumElems/2, j = 0; i != NumElems; ++i, ++j)
15030 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) ||
15031 SVOp->getMaskElt(j) >= 0)
15037 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors.
15038 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG,
15039 TargetLowering::DAGCombinerInfo &DCI,
15040 const X86Subtarget* Subtarget) {
15041 DebugLoc dl = N->getDebugLoc();
15042 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
15043 SDValue V1 = SVOp->getOperand(0);
15044 SDValue V2 = SVOp->getOperand(1);
15045 EVT VT = SVOp->getValueType(0);
15046 unsigned NumElems = VT.getVectorNumElements();
15048 if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
15049 V2.getOpcode() == ISD::CONCAT_VECTORS) {
15053 // V UNDEF BUILD_VECTOR UNDEF
15055 // CONCAT_VECTOR CONCAT_VECTOR
15058 // RESULT: V + zero extended
15060 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
15061 V2.getOperand(1).getOpcode() != ISD::UNDEF ||
15062 V1.getOperand(1).getOpcode() != ISD::UNDEF)
15065 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
15068 // To match the shuffle mask, the first half of the mask should
15069 // be exactly the first vector, and all the rest a splat with the
15070 // first element of the second one.
15071 for (unsigned i = 0; i != NumElems/2; ++i)
15072 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
15073 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
15076 // If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
15077 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
15078 if (Ld->hasNUsesOfValue(1, 0)) {
15079 SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
15080 SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
15082 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
15083 array_lengthof(Ops),
15085 Ld->getPointerInfo(),
15086 Ld->getAlignment(),
15087 false/*isVolatile*/, true/*ReadMem*/,
15088 false/*WriteMem*/);
15090 // Make sure the newly-created LOAD is in the same position as Ld in
15091 // terms of dependency. We create a TokenFactor for Ld and ResNode,
15092 // and update uses of Ld's output chain to use the TokenFactor.
15093 if (Ld->hasAnyUseOfValue(1)) {
15094 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
15095 SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
15096 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
15097 DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
15098 SDValue(ResNode.getNode(), 1));
15101 return DAG.getNode(ISD::BITCAST, dl, VT, ResNode);
15105 // Emit a zeroed vector and insert the desired subvector on its
15107 SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
15108 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
15109 return DCI.CombineTo(N, InsV);
15112 //===--------------------------------------------------------------------===//
15113 // Combine some shuffles into subvector extracts and inserts:
15116 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u>
15117 if (isShuffleHigh128VectorInsertLow(SVOp)) {
15118 SDValue V = Extract128BitVector(V1, NumElems/2, DAG, dl);
15119 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, 0, DAG, dl);
15120 return DCI.CombineTo(N, InsV);
15123 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1>
15124 if (isShuffleLow128VectorInsertHigh(SVOp)) {
15125 SDValue V = Extract128BitVector(V1, 0, DAG, dl);
15126 SDValue InsV = Insert128BitVector(DAG.getUNDEF(VT), V, NumElems/2, DAG, dl);
15127 return DCI.CombineTo(N, InsV);
15133 /// PerformShuffleCombine - Performs several different shuffle combines.
15134 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG,
15135 TargetLowering::DAGCombinerInfo &DCI,
15136 const X86Subtarget *Subtarget) {
15137 DebugLoc dl = N->getDebugLoc();
15138 EVT VT = N->getValueType(0);
15140 // Don't create instructions with illegal types after legalize types has run.
15141 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15142 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType()))
15145 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode
15146 if (Subtarget->hasFp256() && VT.is256BitVector() &&
15147 N->getOpcode() == ISD::VECTOR_SHUFFLE)
15148 return PerformShuffleCombine256(N, DAG, DCI, Subtarget);
15150 // Only handle 128 wide vector from here on.
15151 if (!VT.is128BitVector())
15154 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3,
15155 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are
15156 // consecutive, non-overlapping, and in the right order.
15157 SmallVector<SDValue, 16> Elts;
15158 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
15159 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0));
15161 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG);
15164 /// PerformTruncateCombine - Converts truncate operation to
15165 /// a sequence of vector shuffle operations.
15166 /// It is possible when we truncate 256-bit vector to 128-bit vector
15167 static SDValue PerformTruncateCombine(SDNode *N, SelectionDAG &DAG,
15168 TargetLowering::DAGCombinerInfo &DCI,
15169 const X86Subtarget *Subtarget) {
15173 /// XFormVExtractWithShuffleIntoLoad - Check if a vector extract from a target
15174 /// specific shuffle of a load can be folded into a single element load.
15175 /// Similar handling for VECTOR_SHUFFLE is performed by DAGCombiner, but
15176 /// shuffles have been customed lowered so we need to handle those here.
15177 static SDValue XFormVExtractWithShuffleIntoLoad(SDNode *N, SelectionDAG &DAG,
15178 TargetLowering::DAGCombinerInfo &DCI) {
15179 if (DCI.isBeforeLegalizeOps())
15182 SDValue InVec = N->getOperand(0);
15183 SDValue EltNo = N->getOperand(1);
15185 if (!isa<ConstantSDNode>(EltNo))
15188 EVT VT = InVec.getValueType();
15190 bool HasShuffleIntoBitcast = false;
15191 if (InVec.getOpcode() == ISD::BITCAST) {
15192 // Don't duplicate a load with other uses.
15193 if (!InVec.hasOneUse())
15195 EVT BCVT = InVec.getOperand(0).getValueType();
15196 if (BCVT.getVectorNumElements() != VT.getVectorNumElements())
15198 InVec = InVec.getOperand(0);
15199 HasShuffleIntoBitcast = true;
15202 if (!isTargetShuffle(InVec.getOpcode()))
15205 // Don't duplicate a load with other uses.
15206 if (!InVec.hasOneUse())
15209 SmallVector<int, 16> ShuffleMask;
15211 if (!getTargetShuffleMask(InVec.getNode(), VT.getSimpleVT(), ShuffleMask,
15215 // Select the input vector, guarding against out of range extract vector.
15216 unsigned NumElems = VT.getVectorNumElements();
15217 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
15218 int Idx = (Elt > (int)NumElems) ? -1 : ShuffleMask[Elt];
15219 SDValue LdNode = (Idx < (int)NumElems) ? InVec.getOperand(0)
15220 : InVec.getOperand(1);
15222 // If inputs to shuffle are the same for both ops, then allow 2 uses
15223 unsigned AllowedUses = InVec.getOperand(0) == InVec.getOperand(1) ? 2 : 1;
15225 if (LdNode.getOpcode() == ISD::BITCAST) {
15226 // Don't duplicate a load with other uses.
15227 if (!LdNode.getNode()->hasNUsesOfValue(AllowedUses, 0))
15230 AllowedUses = 1; // only allow 1 load use if we have a bitcast
15231 LdNode = LdNode.getOperand(0);
15234 if (!ISD::isNormalLoad(LdNode.getNode()))
15237 LoadSDNode *LN0 = cast<LoadSDNode>(LdNode);
15239 if (!LN0 ||!LN0->hasNUsesOfValue(AllowedUses, 0) || LN0->isVolatile())
15242 if (HasShuffleIntoBitcast) {
15243 // If there's a bitcast before the shuffle, check if the load type and
15244 // alignment is valid.
15245 unsigned Align = LN0->getAlignment();
15246 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15247 unsigned NewAlign = TLI.getDataLayout()->
15248 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
15250 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT))
15254 // All checks match so transform back to vector_shuffle so that DAG combiner
15255 // can finish the job
15256 DebugLoc dl = N->getDebugLoc();
15258 // Create shuffle node taking into account the case that its a unary shuffle
15259 SDValue Shuffle = (UnaryShuffle) ? DAG.getUNDEF(VT) : InVec.getOperand(1);
15260 Shuffle = DAG.getVectorShuffle(InVec.getValueType(), dl,
15261 InVec.getOperand(0), Shuffle,
15263 Shuffle = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
15264 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), Shuffle,
15268 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index
15269 /// generation and convert it from being a bunch of shuffles and extracts
15270 /// to a simple store and scalar loads to extract the elements.
15271 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG,
15272 TargetLowering::DAGCombinerInfo &DCI) {
15273 SDValue NewOp = XFormVExtractWithShuffleIntoLoad(N, DAG, DCI);
15274 if (NewOp.getNode())
15277 SDValue InputVector = N->getOperand(0);
15278 // Detect whether we are trying to convert from mmx to i32 and the bitcast
15279 // from mmx to v2i32 has a single usage.
15280 if (InputVector.getNode()->getOpcode() == llvm::ISD::BITCAST &&
15281 InputVector.getNode()->getOperand(0).getValueType() == MVT::x86mmx &&
15282 InputVector.hasOneUse() && N->getValueType(0) == MVT::i32)
15283 return DAG.getNode(X86ISD::MMX_MOVD2W, InputVector.getDebugLoc(),
15284 N->getValueType(0),
15285 InputVector.getNode()->getOperand(0));
15287 // Only operate on vectors of 4 elements, where the alternative shuffling
15288 // gets to be more expensive.
15289 if (InputVector.getValueType() != MVT::v4i32)
15292 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a
15293 // single use which is a sign-extend or zero-extend, and all elements are
15295 SmallVector<SDNode *, 4> Uses;
15296 unsigned ExtractedElements = 0;
15297 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(),
15298 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) {
15299 if (UI.getUse().getResNo() != InputVector.getResNo())
15302 SDNode *Extract = *UI;
15303 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
15306 if (Extract->getValueType(0) != MVT::i32)
15308 if (!Extract->hasOneUse())
15310 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
15311 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
15313 if (!isa<ConstantSDNode>(Extract->getOperand(1)))
15316 // Record which element was extracted.
15317 ExtractedElements |=
15318 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
15320 Uses.push_back(Extract);
15323 // If not all the elements were used, this may not be worthwhile.
15324 if (ExtractedElements != 15)
15327 // Ok, we've now decided to do the transformation.
15328 DebugLoc dl = InputVector.getDebugLoc();
15330 // Store the value to a temporary stack slot.
15331 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType());
15332 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr,
15333 MachinePointerInfo(), false, false, 0);
15335 // Replace each use (extract) with a load of the appropriate element.
15336 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(),
15337 UE = Uses.end(); UI != UE; ++UI) {
15338 SDNode *Extract = *UI;
15340 // cOMpute the element's address.
15341 SDValue Idx = Extract->getOperand(1);
15343 InputVector.getValueType().getVectorElementType().getSizeInBits()/8;
15344 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue();
15345 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15346 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());
15348 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),
15349 StackPtr, OffsetVal);
15351 // Load the scalar.
15352 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch,
15353 ScalarAddr, MachinePointerInfo(),
15354 false, false, false, 0);
15356 // Replace the exact with the load.
15357 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar);
15360 // The replacement was made in place; don't return anything.
15364 /// \brief Matches a VSELECT onto min/max or return 0 if the node doesn't match.
15365 static unsigned matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS,
15366 SDValue RHS, SelectionDAG &DAG,
15367 const X86Subtarget *Subtarget) {
15368 if (!VT.isVector())
15371 switch (VT.getSimpleVT().SimpleTy) {
15376 if (!Subtarget->hasAVX2())
15381 if (!Subtarget->hasSSE2())
15385 // SSE2 has only a small subset of the operations.
15386 bool hasUnsigned = Subtarget->hasSSE41() ||
15387 (Subtarget->hasSSE2() && VT == MVT::v16i8);
15388 bool hasSigned = Subtarget->hasSSE41() ||
15389 (Subtarget->hasSSE2() && VT == MVT::v8i16);
15391 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15393 // Check for x CC y ? x : y.
15394 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15395 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15400 return hasUnsigned ? X86ISD::UMIN : 0;
15403 return hasUnsigned ? X86ISD::UMAX : 0;
15406 return hasSigned ? X86ISD::SMIN : 0;
15409 return hasSigned ? X86ISD::SMAX : 0;
15411 // Check for x CC y ? y : x -- a min/max with reversed arms.
15412 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15413 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15418 return hasUnsigned ? X86ISD::UMAX : 0;
15421 return hasUnsigned ? X86ISD::UMIN : 0;
15424 return hasSigned ? X86ISD::SMAX : 0;
15427 return hasSigned ? X86ISD::SMIN : 0;
15434 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT
15436 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
15437 TargetLowering::DAGCombinerInfo &DCI,
15438 const X86Subtarget *Subtarget) {
15439 DebugLoc DL = N->getDebugLoc();
15440 SDValue Cond = N->getOperand(0);
15441 // Get the LHS/RHS of the select.
15442 SDValue LHS = N->getOperand(1);
15443 SDValue RHS = N->getOperand(2);
15444 EVT VT = LHS.getValueType();
15446 // If we have SSE[12] support, try to form min/max nodes. SSE min/max
15447 // instructions match the semantics of the common C idiom x<y?x:y but not
15448 // x<=y?x:y, because of how they handle negative zero (which can be
15449 // ignored in unsafe-math mode).
15450 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
15451 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) &&
15452 (Subtarget->hasSSE2() ||
15453 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) {
15454 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15456 unsigned Opcode = 0;
15457 // Check for x CC y ? x : y.
15458 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15459 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15463 // Converting this to a min would handle NaNs incorrectly, and swapping
15464 // the operands would cause it to handle comparisons between positive
15465 // and negative zero incorrectly.
15466 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15467 if (!DAG.getTarget().Options.UnsafeFPMath &&
15468 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15470 std::swap(LHS, RHS);
15472 Opcode = X86ISD::FMIN;
15475 // Converting this to a min would handle comparisons between positive
15476 // and negative zero incorrectly.
15477 if (!DAG.getTarget().Options.UnsafeFPMath &&
15478 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15480 Opcode = X86ISD::FMIN;
15483 // Converting this to a min would handle both negative zeros and NaNs
15484 // incorrectly, but we can swap the operands to fix both.
15485 std::swap(LHS, RHS);
15489 Opcode = X86ISD::FMIN;
15493 // Converting this to a max would handle comparisons between positive
15494 // and negative zero incorrectly.
15495 if (!DAG.getTarget().Options.UnsafeFPMath &&
15496 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS))
15498 Opcode = X86ISD::FMAX;
15501 // Converting this to a max would handle NaNs incorrectly, and swapping
15502 // the operands would cause it to handle comparisons between positive
15503 // and negative zero incorrectly.
15504 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) {
15505 if (!DAG.getTarget().Options.UnsafeFPMath &&
15506 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
15508 std::swap(LHS, RHS);
15510 Opcode = X86ISD::FMAX;
15513 // Converting this to a max would handle both negative zeros and NaNs
15514 // incorrectly, but we can swap the operands to fix both.
15515 std::swap(LHS, RHS);
15519 Opcode = X86ISD::FMAX;
15522 // Check for x CC y ? y : x -- a min/max with reversed arms.
15523 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) &&
15524 DAG.isEqualTo(RHS, Cond.getOperand(0))) {
15528 // Converting this to a min would handle comparisons between positive
15529 // and negative zero incorrectly, and swapping the operands would
15530 // cause it to handle NaNs incorrectly.
15531 if (!DAG.getTarget().Options.UnsafeFPMath &&
15532 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) {
15533 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15535 std::swap(LHS, RHS);
15537 Opcode = X86ISD::FMIN;
15540 // Converting this to a min would handle NaNs incorrectly.
15541 if (!DAG.getTarget().Options.UnsafeFPMath &&
15542 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)))
15544 Opcode = X86ISD::FMIN;
15547 // Converting this to a min would handle both negative zeros and NaNs
15548 // incorrectly, but we can swap the operands to fix both.
15549 std::swap(LHS, RHS);
15553 Opcode = X86ISD::FMIN;
15557 // Converting this to a max would handle NaNs incorrectly.
15558 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15560 Opcode = X86ISD::FMAX;
15563 // Converting this to a max would handle comparisons between positive
15564 // and negative zero incorrectly, and swapping the operands would
15565 // cause it to handle NaNs incorrectly.
15566 if (!DAG.getTarget().Options.UnsafeFPMath &&
15567 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
15568 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))
15570 std::swap(LHS, RHS);
15572 Opcode = X86ISD::FMAX;
15575 // Converting this to a max would handle both negative zeros and NaNs
15576 // incorrectly, but we can swap the operands to fix both.
15577 std::swap(LHS, RHS);
15581 Opcode = X86ISD::FMAX;
15587 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS);
15590 // If this is a select between two integer constants, try to do some
15592 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) {
15593 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS))
15594 // Don't do this for crazy integer types.
15595 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) {
15596 // If this is efficiently invertible, canonicalize the LHSC/RHSC values
15597 // so that TrueC (the true value) is larger than FalseC.
15598 bool NeedsCondInvert = false;
15600 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) &&
15601 // Efficiently invertible.
15602 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
15603 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible.
15604 isa<ConstantSDNode>(Cond.getOperand(1))))) {
15605 NeedsCondInvert = true;
15606 std::swap(TrueC, FalseC);
15609 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0.
15610 if (FalseC->getAPIntValue() == 0 &&
15611 TrueC->getAPIntValue().isPowerOf2()) {
15612 if (NeedsCondInvert) // Invert the condition if needed.
15613 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15614 DAG.getConstant(1, Cond.getValueType()));
15616 // Zero extend the condition if needed.
15617 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);
15619 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
15620 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,
15621 DAG.getConstant(ShAmt, MVT::i8));
15624 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.
15625 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
15626 if (NeedsCondInvert) // Invert the condition if needed.
15627 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15628 DAG.getConstant(1, Cond.getValueType()));
15630 // Zero extend the condition if needed.
15631 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
15632 FalseC->getValueType(0), Cond);
15633 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15634 SDValue(FalseC, 0));
15637 // Optimize cases that will turn into an LEA instruction. This requires
15638 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
15639 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
15640 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
15641 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
15643 bool isFastMultiplier = false;
15645 switch ((unsigned char)Diff) {
15647 case 1: // result = add base, cond
15648 case 2: // result = lea base( , cond*2)
15649 case 3: // result = lea base(cond, cond*2)
15650 case 4: // result = lea base( , cond*4)
15651 case 5: // result = lea base(cond, cond*4)
15652 case 8: // result = lea base( , cond*8)
15653 case 9: // result = lea base(cond, cond*8)
15654 isFastMultiplier = true;
15659 if (isFastMultiplier) {
15660 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
15661 if (NeedsCondInvert) // Invert the condition if needed.
15662 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
15663 DAG.getConstant(1, Cond.getValueType()));
15665 // Zero extend the condition if needed.
15666 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
15668 // Scale the condition by the difference.
15670 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
15671 DAG.getConstant(Diff, Cond.getValueType()));
15673 // Add the base if non-zero.
15674 if (FalseC->getAPIntValue() != 0)
15675 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
15676 SDValue(FalseC, 0));
15683 // Canonicalize max and min:
15684 // (x > y) ? x : y -> (x >= y) ? x : y
15685 // (x < y) ? x : y -> (x <= y) ? x : y
15686 // This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
15687 // the need for an extra compare
15688 // against zero. e.g.
15689 // (x - y) > 0 : (x - y) ? 0 -> (x - y) >= 0 : (x - y) ? 0
15691 // testl %edi, %edi
15693 // cmovgl %edi, %eax
15697 // cmovsl %eax, %edi
15698 if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
15699 DAG.isEqualTo(LHS, Cond.getOperand(0)) &&
15700 DAG.isEqualTo(RHS, Cond.getOperand(1))) {
15701 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15706 ISD::CondCode NewCC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGE;
15707 Cond = DAG.getSetCC(Cond.getDebugLoc(), Cond.getValueType(),
15708 Cond.getOperand(0), Cond.getOperand(1), NewCC);
15709 return DAG.getNode(ISD::SELECT, DL, VT, Cond, LHS, RHS);
15714 // Match VSELECTs into subs with unsigned saturation.
15715 if (!DCI.isBeforeLegalize() &&
15716 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
15717 // psubus is available in SSE2 and AVX2 for i8 and i16 vectors.
15718 ((Subtarget->hasSSE2() && (VT == MVT::v16i8 || VT == MVT::v8i16)) ||
15719 (Subtarget->hasAVX2() && (VT == MVT::v32i8 || VT == MVT::v16i16)))) {
15720 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
15722 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
15723 // left side invert the predicate to simplify logic below.
15725 if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
15727 CC = ISD::getSetCCInverse(CC, true);
15728 } else if (ISD::isBuildVectorAllZeros(RHS.getNode())) {
15732 if (Other.getNode() && Other->getNumOperands() == 2 &&
15733 DAG.isEqualTo(Other->getOperand(0), Cond.getOperand(0))) {
15734 SDValue OpLHS = Other->getOperand(0), OpRHS = Other->getOperand(1);
15735 SDValue CondRHS = Cond->getOperand(1);
15737 // Look for a general sub with unsigned saturation first.
15738 // x >= y ? x-y : 0 --> subus x, y
15739 // x > y ? x-y : 0 --> subus x, y
15740 if ((CC == ISD::SETUGE || CC == ISD::SETUGT) &&
15741 Other->getOpcode() == ISD::SUB && DAG.isEqualTo(OpRHS, CondRHS))
15742 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15744 // If the RHS is a constant we have to reverse the const canonicalization.
15745 // x > C-1 ? x+-C : 0 --> subus x, C
15746 if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
15747 isSplatVector(CondRHS.getNode()) && isSplatVector(OpRHS.getNode())) {
15748 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15749 if (CondRHS.getConstantOperandVal(0) == -A-1)
15750 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS,
15751 DAG.getConstant(-A, VT));
15754 // Another special case: If C was a sign bit, the sub has been
15755 // canonicalized into a xor.
15756 // FIXME: Would it be better to use ComputeMaskedBits to determine whether
15757 // it's safe to decanonicalize the xor?
15758 // x s< 0 ? x^C : 0 --> subus x, C
15759 if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&
15760 ISD::isBuildVectorAllZeros(CondRHS.getNode()) &&
15761 isSplatVector(OpRHS.getNode())) {
15762 APInt A = cast<ConstantSDNode>(OpRHS.getOperand(0))->getAPIntValue();
15764 return DAG.getNode(X86ISD::SUBUS, DL, VT, OpLHS, OpRHS);
15769 // Try to match a min/max vector operation.
15770 if (!DCI.isBeforeLegalize() &&
15771 N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC)
15772 if (unsigned Op = matchIntegerMINMAX(Cond, VT, LHS, RHS, DAG, Subtarget))
15773 return DAG.getNode(Op, DL, N->getValueType(0), LHS, RHS);
15775 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
15776 if (!DCI.isBeforeLegalize() && N->getOpcode() == ISD::VSELECT &&
15777 Cond.getOpcode() == ISD::SETCC) {
15779 assert(Cond.getValueType().isVector() &&
15780 "vector select expects a vector selector!");
15782 EVT IntVT = Cond.getValueType();
15783 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
15784 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
15786 if (!TValIsAllOnes && !FValIsAllZeros) {
15787 // Try invert the condition if true value is not all 1s and false value
15789 bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
15790 bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
15792 if (TValIsAllZeros || FValIsAllOnes) {
15793 SDValue CC = Cond.getOperand(2);
15794 ISD::CondCode NewCC =
15795 ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
15796 Cond.getOperand(0).getValueType().isInteger());
15797 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
15798 std::swap(LHS, RHS);
15799 TValIsAllOnes = FValIsAllOnes;
15800 FValIsAllZeros = TValIsAllZeros;
15804 if (TValIsAllOnes || FValIsAllZeros) {
15807 if (TValIsAllOnes && FValIsAllZeros)
15809 else if (TValIsAllOnes)
15810 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
15811 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
15812 else if (FValIsAllZeros)
15813 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
15814 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
15816 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
15820 // If we know that this node is legal then we know that it is going to be
15821 // matched by one of the SSE/AVX BLEND instructions. These instructions only
15822 // depend on the highest bit in each word. Try to use SimplifyDemandedBits
15823 // to simplify previous instructions.
15824 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
15825 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
15826 !DCI.isBeforeLegalize() && TLI.isOperationLegal(ISD::VSELECT, VT)) {
15827 unsigned BitWidth = Cond.getValueType().getScalarType().getSizeInBits();
15829 // Don't optimize vector selects that map to mask-registers.
15833 assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
15834 APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
15836 APInt KnownZero, KnownOne;
15837 TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
15838 DCI.isBeforeLegalizeOps());
15839 if (TLO.ShrinkDemandedConstant(Cond, DemandedMask) ||
15840 TLI.SimplifyDemandedBits(Cond, DemandedMask, KnownZero, KnownOne, TLO))
15841 DCI.CommitTargetLoweringOpt(TLO);
15847 // Check whether a boolean test is testing a boolean value generated by
15848 // X86ISD::SETCC. If so, return the operand of that SETCC and proper condition
15851 // Simplify the following patterns:
15852 // (Op (CMP (SETCC Cond EFLAGS) 1) EQ) or
15853 // (Op (CMP (SETCC Cond EFLAGS) 0) NEQ)
15854 // to (Op EFLAGS Cond)
15856 // (Op (CMP (SETCC Cond EFLAGS) 0) EQ) or
15857 // (Op (CMP (SETCC Cond EFLAGS) 1) NEQ)
15858 // to (Op EFLAGS !Cond)
15860 // where Op could be BRCOND or CMOV.
15862 static SDValue checkBoolTestSetCCCombine(SDValue Cmp, X86::CondCode &CC) {
15863 // Quit if not CMP and SUB with its value result used.
15864 if (Cmp.getOpcode() != X86ISD::CMP &&
15865 (Cmp.getOpcode() != X86ISD::SUB || Cmp.getNode()->hasAnyUseOfValue(0)))
15868 // Quit if not used as a boolean value.
15869 if (CC != X86::COND_E && CC != X86::COND_NE)
15872 // Check CMP operands. One of them should be 0 or 1 and the other should be
15873 // an SetCC or extended from it.
15874 SDValue Op1 = Cmp.getOperand(0);
15875 SDValue Op2 = Cmp.getOperand(1);
15878 const ConstantSDNode* C = 0;
15879 bool needOppositeCond = (CC == X86::COND_E);
15880 bool checkAgainstTrue = false; // Is it a comparison against 1?
15882 if ((C = dyn_cast<ConstantSDNode>(Op1)))
15884 else if ((C = dyn_cast<ConstantSDNode>(Op2)))
15886 else // Quit if all operands are not constants.
15889 if (C->getZExtValue() == 1) {
15890 needOppositeCond = !needOppositeCond;
15891 checkAgainstTrue = true;
15892 } else if (C->getZExtValue() != 0)
15893 // Quit if the constant is neither 0 or 1.
15896 bool truncatedToBoolWithAnd = false;
15897 // Skip (zext $x), (trunc $x), or (and $x, 1) node.
15898 while (SetCC.getOpcode() == ISD::ZERO_EXTEND ||
15899 SetCC.getOpcode() == ISD::TRUNCATE ||
15900 SetCC.getOpcode() == ISD::AND) {
15901 if (SetCC.getOpcode() == ISD::AND) {
15903 ConstantSDNode *CS;
15904 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(0))) &&
15905 CS->getZExtValue() == 1)
15907 if ((CS = dyn_cast<ConstantSDNode>(SetCC.getOperand(1))) &&
15908 CS->getZExtValue() == 1)
15912 SetCC = SetCC.getOperand(OpIdx);
15913 truncatedToBoolWithAnd = true;
15915 SetCC = SetCC.getOperand(0);
15918 switch (SetCC.getOpcode()) {
15919 case X86ISD::SETCC_CARRY:
15920 // Since SETCC_CARRY gives output based on R = CF ? ~0 : 0, it's unsafe to
15921 // simplify it if the result of SETCC_CARRY is not canonicalized to 0 or 1,
15922 // i.e. it's a comparison against true but the result of SETCC_CARRY is not
15923 // truncated to i1 using 'and'.
15924 if (checkAgainstTrue && !truncatedToBoolWithAnd)
15926 assert(X86::CondCode(SetCC.getConstantOperandVal(0)) == X86::COND_B &&
15927 "Invalid use of SETCC_CARRY!");
15929 case X86ISD::SETCC:
15930 // Set the condition code or opposite one if necessary.
15931 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
15932 if (needOppositeCond)
15933 CC = X86::GetOppositeBranchCondition(CC);
15934 return SetCC.getOperand(1);
15935 case X86ISD::CMOV: {
15936 // Check whether false/true value has canonical one, i.e. 0 or 1.
15937 ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
15938 ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
15939 // Quit if true value is not a constant.
15942 // Quit if false value is not a constant.
15944 SDValue Op = SetCC.getOperand(0);
15945 // Skip 'zext' or 'trunc' node.
15946 if (Op.getOpcode() == ISD::ZERO_EXTEND ||
15947 Op.getOpcode() == ISD::TRUNCATE)
15948 Op = Op.getOperand(0);
15949 // A special case for rdrand/rdseed, where 0 is set if false cond is
15951 if ((Op.getOpcode() != X86ISD::RDRAND &&
15952 Op.getOpcode() != X86ISD::RDSEED) || Op.getResNo() != 0)
15955 // Quit if false value is not the constant 0 or 1.
15956 bool FValIsFalse = true;
15957 if (FVal && FVal->getZExtValue() != 0) {
15958 if (FVal->getZExtValue() != 1)
15960 // If FVal is 1, opposite cond is needed.
15961 needOppositeCond = !needOppositeCond;
15962 FValIsFalse = false;
15964 // Quit if TVal is not the constant opposite of FVal.
15965 if (FValIsFalse && TVal->getZExtValue() != 1)
15967 if (!FValIsFalse && TVal->getZExtValue() != 0)
15969 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
15970 if (needOppositeCond)
15971 CC = X86::GetOppositeBranchCondition(CC);
15972 return SetCC.getOperand(3);
15979 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
15980 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
15981 TargetLowering::DAGCombinerInfo &DCI,
15982 const X86Subtarget *Subtarget) {
15983 DebugLoc DL = N->getDebugLoc();
15985 // If the flag operand isn't dead, don't touch this CMOV.
15986 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty())
15989 SDValue FalseOp = N->getOperand(0);
15990 SDValue TrueOp = N->getOperand(1);
15991 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2);
15992 SDValue Cond = N->getOperand(3);
15994 if (CC == X86::COND_E || CC == X86::COND_NE) {
15995 switch (Cond.getOpcode()) {
15999 // If operand of BSR / BSF are proven never zero, then ZF cannot be set.
16000 if (DAG.isKnownNeverZero(Cond.getOperand(0)))
16001 return (CC == X86::COND_E) ? FalseOp : TrueOp;
16007 Flags = checkBoolTestSetCCCombine(Cond, CC);
16008 if (Flags.getNode() &&
16009 // Extra check as FCMOV only supports a subset of X86 cond.
16010 (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
16011 SDValue Ops[] = { FalseOp, TrueOp,
16012 DAG.getConstant(CC, MVT::i8), Flags };
16013 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
16014 Ops, array_lengthof(Ops));
16017 // If this is a select between two integer constants, try to do some
16018 // optimizations. Note that the operands are ordered the opposite of SELECT
16020 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
16021 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
16022 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
16023 // larger than FalseC (the false value).
16024 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
16025 CC = X86::GetOppositeBranchCondition(CC);
16026 std::swap(TrueC, FalseC);
16027 std::swap(TrueOp, FalseOp);
16030 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0.
16031 // This is efficient for any integer data type (including i8/i16) and
16033 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {
16034 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16035 DAG.getConstant(CC, MVT::i8), Cond);
16037 // Zero extend the condition if needed.
16038 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);
16040 unsigned ShAmt = TrueC->getAPIntValue().logBase2();
16041 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,
16042 DAG.getConstant(ShAmt, MVT::i8));
16043 if (N->getNumValues() == 2) // Dead flag value?
16044 return DCI.CombineTo(N, Cond, SDValue());
16048 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient
16049 // for any integer data type, including i8/i16.
16050 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {
16051 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16052 DAG.getConstant(CC, MVT::i8), Cond);
16054 // Zero extend the condition if needed.
16055 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,
16056 FalseC->getValueType(0), Cond);
16057 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16058 SDValue(FalseC, 0));
16060 if (N->getNumValues() == 2) // Dead flag value?
16061 return DCI.CombineTo(N, Cond, SDValue());
16065 // Optimize cases that will turn into an LEA instruction. This requires
16066 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9).
16067 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) {
16068 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue();
16069 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff;
16071 bool isFastMultiplier = false;
16073 switch ((unsigned char)Diff) {
16075 case 1: // result = add base, cond
16076 case 2: // result = lea base( , cond*2)
16077 case 3: // result = lea base(cond, cond*2)
16078 case 4: // result = lea base( , cond*4)
16079 case 5: // result = lea base(cond, cond*4)
16080 case 8: // result = lea base( , cond*8)
16081 case 9: // result = lea base(cond, cond*8)
16082 isFastMultiplier = true;
16087 if (isFastMultiplier) {
16088 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();
16089 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,
16090 DAG.getConstant(CC, MVT::i8), Cond);
16091 // Zero extend the condition if needed.
16092 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),
16094 // Scale the condition by the difference.
16096 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,
16097 DAG.getConstant(Diff, Cond.getValueType()));
16099 // Add the base if non-zero.
16100 if (FalseC->getAPIntValue() != 0)
16101 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond,
16102 SDValue(FalseC, 0));
16103 if (N->getNumValues() == 2) // Dead flag value?
16104 return DCI.CombineTo(N, Cond, SDValue());
16111 // Handle these cases:
16112 // (select (x != c), e, c) -> select (x != c), e, x),
16113 // (select (x == c), c, e) -> select (x == c), x, e)
16114 // where the c is an integer constant, and the "select" is the combination
16115 // of CMOV and CMP.
16117 // The rationale for this change is that the conditional-move from a constant
16118 // needs two instructions, however, conditional-move from a register needs
16119 // only one instruction.
16121 // CAVEAT: By replacing a constant with a symbolic value, it may obscure
16122 // some instruction-combining opportunities. This opt needs to be
16123 // postponed as late as possible.
16125 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) {
16126 // the DCI.xxxx conditions are provided to postpone the optimization as
16127 // late as possible.
16129 ConstantSDNode *CmpAgainst = 0;
16130 if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
16131 (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
16132 !isa<ConstantSDNode>(Cond.getOperand(0))) {
16134 if (CC == X86::COND_NE &&
16135 CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
16136 CC = X86::GetOppositeBranchCondition(CC);
16137 std::swap(TrueOp, FalseOp);
16140 if (CC == X86::COND_E &&
16141 CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
16142 SDValue Ops[] = { FalseOp, Cond.getOperand(0),
16143 DAG.getConstant(CC, MVT::i8), Cond };
16144 return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops,
16145 array_lengthof(Ops));
16153 /// PerformMulCombine - Optimize a single multiply with constant into two
16154 /// in order to implement it with two cheaper instructions, e.g.
16155 /// LEA + SHL, LEA + LEA.
16156 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG,
16157 TargetLowering::DAGCombinerInfo &DCI) {
16158 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
16161 EVT VT = N->getValueType(0);
16162 if (VT != MVT::i64)
16165 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
16168 uint64_t MulAmt = C->getZExtValue();
16169 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9)
16172 uint64_t MulAmt1 = 0;
16173 uint64_t MulAmt2 = 0;
16174 if ((MulAmt % 9) == 0) {
16176 MulAmt2 = MulAmt / 9;
16177 } else if ((MulAmt % 5) == 0) {
16179 MulAmt2 = MulAmt / 5;
16180 } else if ((MulAmt % 3) == 0) {
16182 MulAmt2 = MulAmt / 3;
16185 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){
16186 DebugLoc DL = N->getDebugLoc();
16188 if (isPowerOf2_64(MulAmt2) &&
16189 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD))
16190 // If second multiplifer is pow2, issue it first. We want the multiply by
16191 // 3, 5, or 9 to be folded into the addressing mode unless the lone use
16193 std::swap(MulAmt1, MulAmt2);
16196 if (isPowerOf2_64(MulAmt1))
16197 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
16198 DAG.getConstant(Log2_64(MulAmt1), MVT::i8));
16200 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),
16201 DAG.getConstant(MulAmt1, VT));
16203 if (isPowerOf2_64(MulAmt2))
16204 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,
16205 DAG.getConstant(Log2_64(MulAmt2), MVT::i8));
16207 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,
16208 DAG.getConstant(MulAmt2, VT));
16210 // Do not add new nodes to DAG combiner worklist.
16211 DCI.CombineTo(N, NewMul, false);
16216 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) {
16217 SDValue N0 = N->getOperand(0);
16218 SDValue N1 = N->getOperand(1);
16219 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
16220 EVT VT = N0.getValueType();
16222 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
16223 // since the result of setcc_c is all zero's or all ones.
16224 if (VT.isInteger() && !VT.isVector() &&
16225 N1C && N0.getOpcode() == ISD::AND &&
16226 N0.getOperand(1).getOpcode() == ISD::Constant) {
16227 SDValue N00 = N0.getOperand(0);
16228 if (N00.getOpcode() == X86ISD::SETCC_CARRY ||
16229 ((N00.getOpcode() == ISD::ANY_EXTEND ||
16230 N00.getOpcode() == ISD::ZERO_EXTEND) &&
16231 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) {
16232 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
16233 APInt ShAmt = N1C->getAPIntValue();
16234 Mask = Mask.shl(ShAmt);
16236 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
16237 N00, DAG.getConstant(Mask, VT));
16241 // Hardware support for vector shifts is sparse which makes us scalarize the
16242 // vector operations in many cases. Also, on sandybridge ADD is faster than
16244 // (shl V, 1) -> add V,V
16245 if (isSplatVector(N1.getNode())) {
16246 assert(N0.getValueType().isVector() && "Invalid vector shift type");
16247 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1->getOperand(0));
16248 // We shift all of the values by one. In many cases we do not have
16249 // hardware support for this operation. This is better expressed as an ADD
16251 if (N1C && (1 == N1C->getZExtValue())) {
16252 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N0);
16259 /// PerformShiftCombine - Combine shifts.
16260 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
16261 TargetLowering::DAGCombinerInfo &DCI,
16262 const X86Subtarget *Subtarget) {
16263 if (N->getOpcode() == ISD::SHL) {
16264 SDValue V = PerformSHLCombine(N, DAG);
16265 if (V.getNode()) return V;
16271 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..))
16272 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS
16273 // and friends. Likewise for OR -> CMPNEQSS.
16274 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG,
16275 TargetLowering::DAGCombinerInfo &DCI,
16276 const X86Subtarget *Subtarget) {
16279 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but
16280 // we're requiring SSE2 for both.
16281 if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) {
16282 SDValue N0 = N->getOperand(0);
16283 SDValue N1 = N->getOperand(1);
16284 SDValue CMP0 = N0->getOperand(1);
16285 SDValue CMP1 = N1->getOperand(1);
16286 DebugLoc DL = N->getDebugLoc();
16288 // The SETCCs should both refer to the same CMP.
16289 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1)
16292 SDValue CMP00 = CMP0->getOperand(0);
16293 SDValue CMP01 = CMP0->getOperand(1);
16294 EVT VT = CMP00.getValueType();
16296 if (VT == MVT::f32 || VT == MVT::f64) {
16297 bool ExpectingFlags = false;
16298 // Check for any users that want flags:
16299 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
16300 !ExpectingFlags && UI != UE; ++UI)
16301 switch (UI->getOpcode()) {
16306 ExpectingFlags = true;
16308 case ISD::CopyToReg:
16309 case ISD::SIGN_EXTEND:
16310 case ISD::ZERO_EXTEND:
16311 case ISD::ANY_EXTEND:
16315 if (!ExpectingFlags) {
16316 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0);
16317 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0);
16319 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) {
16320 X86::CondCode tmp = cc0;
16325 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) ||
16326 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) {
16327 bool is64BitFP = (CMP00.getValueType() == MVT::f64);
16328 X86ISD::NodeType NTOperator = is64BitFP ?
16329 X86ISD::FSETCCsd : X86ISD::FSETCCss;
16330 // FIXME: need symbolic constants for these magic numbers.
16331 // See X86ATTInstPrinter.cpp:printSSECC().
16332 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;
16333 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01,
16334 DAG.getConstant(x86cc, MVT::i8));
16335 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32,
16337 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI,
16338 DAG.getConstant(1, MVT::i32));
16339 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);
16340 return OneBitOfTruth;
16348 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector
16349 /// so it can be folded inside ANDNP.
16350 static bool CanFoldXORWithAllOnes(const SDNode *N) {
16351 EVT VT = N->getValueType(0);
16353 // Match direct AllOnes for 128 and 256-bit vectors
16354 if (ISD::isBuildVectorAllOnes(N))
16357 // Look through a bit convert.
16358 if (N->getOpcode() == ISD::BITCAST)
16359 N = N->getOperand(0).getNode();
16361 // Sometimes the operand may come from a insert_subvector building a 256-bit
16363 if (VT.is256BitVector() &&
16364 N->getOpcode() == ISD::INSERT_SUBVECTOR) {
16365 SDValue V1 = N->getOperand(0);
16366 SDValue V2 = N->getOperand(1);
16368 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
16369 V1.getOperand(0).getOpcode() == ISD::UNDEF &&
16370 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) &&
16371 ISD::isBuildVectorAllOnes(V2.getNode()))
16378 // On AVX/AVX2 the type v8i1 is legalized to v8i16, which is an XMM sized
16379 // register. In most cases we actually compare or select YMM-sized registers
16380 // and mixing the two types creates horrible code. This method optimizes
16381 // some of the transition sequences.
16382 static SDValue WidenMaskArithmetic(SDNode *N, SelectionDAG &DAG,
16383 TargetLowering::DAGCombinerInfo &DCI,
16384 const X86Subtarget *Subtarget) {
16385 EVT VT = N->getValueType(0);
16386 if (!VT.is256BitVector())
16389 assert((N->getOpcode() == ISD::ANY_EXTEND ||
16390 N->getOpcode() == ISD::ZERO_EXTEND ||
16391 N->getOpcode() == ISD::SIGN_EXTEND) && "Invalid Node");
16393 SDValue Narrow = N->getOperand(0);
16394 EVT NarrowVT = Narrow->getValueType(0);
16395 if (!NarrowVT.is128BitVector())
16398 if (Narrow->getOpcode() != ISD::XOR &&
16399 Narrow->getOpcode() != ISD::AND &&
16400 Narrow->getOpcode() != ISD::OR)
16403 SDValue N0 = Narrow->getOperand(0);
16404 SDValue N1 = Narrow->getOperand(1);
16405 DebugLoc DL = Narrow->getDebugLoc();
16407 // The Left side has to be a trunc.
16408 if (N0.getOpcode() != ISD::TRUNCATE)
16411 // The type of the truncated inputs.
16412 EVT WideVT = N0->getOperand(0)->getValueType(0);
16416 // The right side has to be a 'trunc' or a constant vector.
16417 bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
16418 bool RHSConst = (isSplatVector(N1.getNode()) &&
16419 isa<ConstantSDNode>(N1->getOperand(0)));
16420 if (!RHSTrunc && !RHSConst)
16423 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16425 if (!TLI.isOperationLegalOrPromote(Narrow->getOpcode(), WideVT))
16428 // Set N0 and N1 to hold the inputs to the new wide operation.
16429 N0 = N0->getOperand(0);
16431 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT.getScalarType(),
16432 N1->getOperand(0));
16433 SmallVector<SDValue, 8> C(WideVT.getVectorNumElements(), N1);
16434 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, &C[0], C.size());
16435 } else if (RHSTrunc) {
16436 N1 = N1->getOperand(0);
16439 // Generate the wide operation.
16440 SDValue Op = DAG.getNode(Narrow->getOpcode(), DL, WideVT, N0, N1);
16441 unsigned Opcode = N->getOpcode();
16443 case ISD::ANY_EXTEND:
16445 case ISD::ZERO_EXTEND: {
16446 unsigned InBits = NarrowVT.getScalarType().getSizeInBits();
16447 APInt Mask = APInt::getAllOnesValue(InBits);
16448 Mask = Mask.zext(VT.getScalarType().getSizeInBits());
16449 return DAG.getNode(ISD::AND, DL, VT,
16450 Op, DAG.getConstant(Mask, VT));
16452 case ISD::SIGN_EXTEND:
16453 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,
16454 Op, DAG.getValueType(NarrowVT));
16456 llvm_unreachable("Unexpected opcode");
16460 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,
16461 TargetLowering::DAGCombinerInfo &DCI,
16462 const X86Subtarget *Subtarget) {
16463 EVT VT = N->getValueType(0);
16464 if (DCI.isBeforeLegalizeOps())
16467 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16471 // Create BLSI, and BLSR instructions
16472 // BLSI is X & (-X)
16473 // BLSR is X & (X-1)
16474 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) {
16475 SDValue N0 = N->getOperand(0);
16476 SDValue N1 = N->getOperand(1);
16477 DebugLoc DL = N->getDebugLoc();
16479 // Check LHS for neg
16480 if (N0.getOpcode() == ISD::SUB && N0.getOperand(1) == N1 &&
16481 isZero(N0.getOperand(0)))
16482 return DAG.getNode(X86ISD::BLSI, DL, VT, N1);
16484 // Check RHS for neg
16485 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1) == N0 &&
16486 isZero(N1.getOperand(0)))
16487 return DAG.getNode(X86ISD::BLSI, DL, VT, N0);
16489 // Check LHS for X-1
16490 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16491 isAllOnes(N0.getOperand(1)))
16492 return DAG.getNode(X86ISD::BLSR, DL, VT, N1);
16494 // Check RHS for X-1
16495 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16496 isAllOnes(N1.getOperand(1)))
16497 return DAG.getNode(X86ISD::BLSR, DL, VT, N0);
16502 // Want to form ANDNP nodes:
16503 // 1) In the hopes of then easily combining them with OR and AND nodes
16504 // to form PBLEND/PSIGN.
16505 // 2) To match ANDN packed intrinsics
16506 if (VT != MVT::v2i64 && VT != MVT::v4i64)
16509 SDValue N0 = N->getOperand(0);
16510 SDValue N1 = N->getOperand(1);
16511 DebugLoc DL = N->getDebugLoc();
16513 // Check LHS for vnot
16514 if (N0.getOpcode() == ISD::XOR &&
16515 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode()))
16516 CanFoldXORWithAllOnes(N0.getOperand(1).getNode()))
16517 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1);
16519 // Check RHS for vnot
16520 if (N1.getOpcode() == ISD::XOR &&
16521 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode()))
16522 CanFoldXORWithAllOnes(N1.getOperand(1).getNode()))
16523 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0);
16528 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
16529 TargetLowering::DAGCombinerInfo &DCI,
16530 const X86Subtarget *Subtarget) {
16531 EVT VT = N->getValueType(0);
16532 if (DCI.isBeforeLegalizeOps())
16535 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget);
16539 SDValue N0 = N->getOperand(0);
16540 SDValue N1 = N->getOperand(1);
16542 // look for psign/blend
16543 if (VT == MVT::v2i64 || VT == MVT::v4i64) {
16544 if (!Subtarget->hasSSSE3() ||
16545 (VT == MVT::v4i64 && !Subtarget->hasInt256()))
16548 // Canonicalize pandn to RHS
16549 if (N0.getOpcode() == X86ISD::ANDNP)
16551 // or (and (m, y), (pandn m, x))
16552 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) {
16553 SDValue Mask = N1.getOperand(0);
16554 SDValue X = N1.getOperand(1);
16556 if (N0.getOperand(0) == Mask)
16557 Y = N0.getOperand(1);
16558 if (N0.getOperand(1) == Mask)
16559 Y = N0.getOperand(0);
16561 // Check to see if the mask appeared in both the AND and ANDNP and
16565 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them.
16566 // Look through mask bitcast.
16567 if (Mask.getOpcode() == ISD::BITCAST)
16568 Mask = Mask.getOperand(0);
16569 if (X.getOpcode() == ISD::BITCAST)
16570 X = X.getOperand(0);
16571 if (Y.getOpcode() == ISD::BITCAST)
16572 Y = Y.getOperand(0);
16574 EVT MaskVT = Mask.getValueType();
16576 // Validate that the Mask operand is a vector sra node.
16577 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
16578 // there is no psrai.b
16579 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
16580 unsigned SraAmt = ~0;
16581 if (Mask.getOpcode() == ISD::SRA) {
16582 SDValue Amt = Mask.getOperand(1);
16583 if (isSplatVector(Amt.getNode())) {
16584 SDValue SclrAmt = Amt->getOperand(0);
16585 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt))
16586 SraAmt = C->getZExtValue();
16588 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
16589 SDValue SraC = Mask.getOperand(1);
16590 SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
16592 if ((SraAmt + 1) != EltBits)
16595 DebugLoc DL = N->getDebugLoc();
16597 // Now we know we at least have a plendvb with the mask val. See if
16598 // we can form a psignb/w/d.
16599 // psign = x.type == y.type == mask.type && y = sub(0, x);
16600 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X &&
16601 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) &&
16602 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
16603 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
16604 "Unsupported VT for PSIGN");
16605 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
16606 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16608 // PBLENDVB only available on SSE 4.1
16609 if (!Subtarget->hasSSE41())
16612 EVT BlendVT = (VT == MVT::v4i64) ? MVT::v32i8 : MVT::v16i8;
16614 X = DAG.getNode(ISD::BITCAST, DL, BlendVT, X);
16615 Y = DAG.getNode(ISD::BITCAST, DL, BlendVT, Y);
16616 Mask = DAG.getNode(ISD::BITCAST, DL, BlendVT, Mask);
16617 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
16618 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
16622 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64)
16625 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
16626 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
16628 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
16630 if (!N0.hasOneUse() || !N1.hasOneUse())
16633 SDValue ShAmt0 = N0.getOperand(1);
16634 if (ShAmt0.getValueType() != MVT::i8)
16636 SDValue ShAmt1 = N1.getOperand(1);
16637 if (ShAmt1.getValueType() != MVT::i8)
16639 if (ShAmt0.getOpcode() == ISD::TRUNCATE)
16640 ShAmt0 = ShAmt0.getOperand(0);
16641 if (ShAmt1.getOpcode() == ISD::TRUNCATE)
16642 ShAmt1 = ShAmt1.getOperand(0);
16644 DebugLoc DL = N->getDebugLoc();
16645 unsigned Opc = X86ISD::SHLD;
16646 SDValue Op0 = N0.getOperand(0);
16647 SDValue Op1 = N1.getOperand(0);
16648 if (ShAmt0.getOpcode() == ISD::SUB) {
16649 Opc = X86ISD::SHRD;
16650 std::swap(Op0, Op1);
16651 std::swap(ShAmt0, ShAmt1);
16654 unsigned Bits = VT.getSizeInBits();
16655 if (ShAmt1.getOpcode() == ISD::SUB) {
16656 SDValue Sum = ShAmt1.getOperand(0);
16657 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
16658 SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
16659 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE)
16660 ShAmt1Op1 = ShAmt1Op1.getOperand(0);
16661 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0)
16662 return DAG.getNode(Opc, DL, VT,
16664 DAG.getNode(ISD::TRUNCATE, DL,
16667 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
16668 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
16670 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits)
16671 return DAG.getNode(Opc, DL, VT,
16672 N0.getOperand(0), N1.getOperand(0),
16673 DAG.getNode(ISD::TRUNCATE, DL,
16680 // Generate NEG and CMOV for integer abs.
16681 static SDValue performIntegerAbsCombine(SDNode *N, SelectionDAG &DAG) {
16682 EVT VT = N->getValueType(0);
16684 // Since X86 does not have CMOV for 8-bit integer, we don't convert
16685 // 8-bit integer abs to NEG and CMOV.
16686 if (VT.isInteger() && VT.getSizeInBits() == 8)
16689 SDValue N0 = N->getOperand(0);
16690 SDValue N1 = N->getOperand(1);
16691 DebugLoc DL = N->getDebugLoc();
16693 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
16694 // and change it to SUB and CMOV.
16695 if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
16696 N0.getOpcode() == ISD::ADD &&
16697 N0.getOperand(1) == N1 &&
16698 N1.getOpcode() == ISD::SRA &&
16699 N1.getOperand(0) == N0.getOperand(0))
16700 if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
16701 if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
16702 // Generate SUB & CMOV.
16703 SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
16704 DAG.getConstant(0, VT), N0.getOperand(0));
16706 SDValue Ops[] = { N0.getOperand(0), Neg,
16707 DAG.getConstant(X86::COND_GE, MVT::i8),
16708 SDValue(Neg.getNode(), 1) };
16709 return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue),
16710 Ops, array_lengthof(Ops));
16715 // PerformXorCombine - Attempts to turn XOR nodes into BLSMSK nodes
16716 static SDValue PerformXorCombine(SDNode *N, SelectionDAG &DAG,
16717 TargetLowering::DAGCombinerInfo &DCI,
16718 const X86Subtarget *Subtarget) {
16719 EVT VT = N->getValueType(0);
16720 if (DCI.isBeforeLegalizeOps())
16723 if (Subtarget->hasCMov()) {
16724 SDValue RV = performIntegerAbsCombine(N, DAG);
16729 // Try forming BMI if it is available.
16730 if (!Subtarget->hasBMI())
16733 if (VT != MVT::i32 && VT != MVT::i64)
16736 assert(Subtarget->hasBMI() && "Creating BLSMSK requires BMI instructions");
16738 // Create BLSMSK instructions by finding X ^ (X-1)
16739 SDValue N0 = N->getOperand(0);
16740 SDValue N1 = N->getOperand(1);
16741 DebugLoc DL = N->getDebugLoc();
16743 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1 &&
16744 isAllOnes(N0.getOperand(1)))
16745 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N1);
16747 if (N1.getOpcode() == ISD::ADD && N1.getOperand(0) == N0 &&
16748 isAllOnes(N1.getOperand(1)))
16749 return DAG.getNode(X86ISD::BLSMSK, DL, VT, N0);
16754 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes.
16755 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG,
16756 TargetLowering::DAGCombinerInfo &DCI,
16757 const X86Subtarget *Subtarget) {
16758 LoadSDNode *Ld = cast<LoadSDNode>(N);
16759 EVT RegVT = Ld->getValueType(0);
16760 EVT MemVT = Ld->getMemoryVT();
16761 DebugLoc dl = Ld->getDebugLoc();
16762 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16763 unsigned RegSz = RegVT.getSizeInBits();
16765 // On Sandybridge unaligned 256bit loads are inefficient.
16766 ISD::LoadExtType Ext = Ld->getExtensionType();
16767 unsigned Alignment = Ld->getAlignment();
16768 bool IsAligned = Alignment == 0 || Alignment >= MemVT.getSizeInBits()/8;
16769 if (RegVT.is256BitVector() && !Subtarget->hasInt256() &&
16770 !DCI.isBeforeLegalizeOps() && !IsAligned && Ext == ISD::NON_EXTLOAD) {
16771 unsigned NumElems = RegVT.getVectorNumElements();
16775 SDValue Ptr = Ld->getBasePtr();
16776 SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());
16778 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16780 SDValue Load1 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
16781 Ld->getPointerInfo(), Ld->isVolatile(),
16782 Ld->isNonTemporal(), Ld->isInvariant(),
16784 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16785 SDValue Load2 = DAG.getLoad(HalfVT, dl, Ld->getChain(), Ptr,
16786 Ld->getPointerInfo(), Ld->isVolatile(),
16787 Ld->isNonTemporal(), Ld->isInvariant(),
16788 std::min(16U, Alignment));
16789 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
16791 Load2.getValue(1));
16793 SDValue NewVec = DAG.getUNDEF(RegVT);
16794 NewVec = Insert128BitVector(NewVec, Load1, 0, DAG, dl);
16795 NewVec = Insert128BitVector(NewVec, Load2, NumElems/2, DAG, dl);
16796 return DCI.CombineTo(N, NewVec, TF, true);
16799 // If this is a vector EXT Load then attempt to optimize it using a
16800 // shuffle. If SSSE3 is not available we may emit an illegal shuffle but the
16801 // expansion is still better than scalar code.
16802 // We generate X86ISD::VSEXT for SEXTLOADs if it's available, otherwise we'll
16803 // emit a shuffle and a arithmetic shift.
16804 // TODO: It is possible to support ZExt by zeroing the undef values
16805 // during the shuffle phase or after the shuffle.
16806 if (RegVT.isVector() && RegVT.isInteger() && Subtarget->hasSSE2() &&
16807 (Ext == ISD::EXTLOAD || Ext == ISD::SEXTLOAD)) {
16808 assert(MemVT != RegVT && "Cannot extend to the same type");
16809 assert(MemVT.isVector() && "Must load a vector from memory");
16811 unsigned NumElems = RegVT.getVectorNumElements();
16812 unsigned MemSz = MemVT.getSizeInBits();
16813 assert(RegSz > MemSz && "Register size must be greater than the mem size");
16815 if (Ext == ISD::SEXTLOAD && RegSz == 256 && !Subtarget->hasInt256())
16818 // All sizes must be a power of two.
16819 if (!isPowerOf2_32(RegSz * MemSz * NumElems))
16822 // Attempt to load the original value using scalar loads.
16823 // Find the largest scalar type that divides the total loaded size.
16824 MVT SclrLoadTy = MVT::i8;
16825 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
16826 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
16827 MVT Tp = (MVT::SimpleValueType)tp;
16828 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) {
16833 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
16834 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
16836 SclrLoadTy = MVT::f64;
16838 // Calculate the number of scalar loads that we need to perform
16839 // in order to load our vector from memory.
16840 unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
16841 if (Ext == ISD::SEXTLOAD && NumLoads > 1)
16844 unsigned loadRegZize = RegSz;
16845 if (Ext == ISD::SEXTLOAD && RegSz == 256)
16848 // Represent our vector as a sequence of elements which are the
16849 // largest scalar that we can load.
16850 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy,
16851 loadRegZize/SclrLoadTy.getSizeInBits());
16853 // Represent the data using the same element type that is stored in
16854 // memory. In practice, we ''widen'' MemVT.
16856 EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),
16857 loadRegZize/MemVT.getScalarType().getSizeInBits());
16859 assert(WideVecVT.getSizeInBits() == LoadUnitVecVT.getSizeInBits() &&
16860 "Invalid vector type");
16862 // We can't shuffle using an illegal type.
16863 if (!TLI.isTypeLegal(WideVecVT))
16866 SmallVector<SDValue, 8> Chains;
16867 SDValue Ptr = Ld->getBasePtr();
16868 SDValue Increment = DAG.getConstant(SclrLoadTy.getSizeInBits()/8,
16869 TLI.getPointerTy());
16870 SDValue Res = DAG.getUNDEF(LoadUnitVecVT);
16872 for (unsigned i = 0; i < NumLoads; ++i) {
16873 // Perform a single load.
16874 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(),
16875 Ptr, Ld->getPointerInfo(),
16876 Ld->isVolatile(), Ld->isNonTemporal(),
16877 Ld->isInvariant(), Ld->getAlignment());
16878 Chains.push_back(ScalarLoad.getValue(1));
16879 // Create the first element type using SCALAR_TO_VECTOR in order to avoid
16880 // another round of DAGCombining.
16882 Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);
16884 Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,
16885 ScalarLoad, DAG.getIntPtrConstant(i));
16887 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
16890 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
16893 // Bitcast the loaded value to a vector of the original element type, in
16894 // the size of the target vector type.
16895 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, Res);
16896 unsigned SizeRatio = RegSz/MemSz;
16898 if (Ext == ISD::SEXTLOAD) {
16899 // If we have SSE4.1 we can directly emit a VSEXT node.
16900 if (Subtarget->hasSSE41()) {
16901 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec);
16902 return DCI.CombineTo(N, Sext, TF, true);
16905 // Otherwise we'll shuffle the small elements in the high bits of the
16906 // larger type and perform an arithmetic shift. If the shift is not legal
16907 // it's better to scalarize.
16908 if (!TLI.isOperationLegalOrCustom(ISD::SRA, RegVT))
16911 // Redistribute the loaded elements into the different locations.
16912 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16913 for (unsigned i = 0; i != NumElems; ++i)
16914 ShuffleVec[i*SizeRatio + SizeRatio-1] = i;
16916 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16917 DAG.getUNDEF(WideVecVT),
16920 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16922 // Build the arithmetic shift.
16923 unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -
16924 MemVT.getVectorElementType().getSizeInBits();
16925 Shuff = DAG.getNode(ISD::SRA, dl, RegVT, Shuff,
16926 DAG.getConstant(Amt, RegVT));
16928 return DCI.CombineTo(N, Shuff, TF, true);
16931 // Redistribute the loaded elements into the different locations.
16932 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
16933 for (unsigned i = 0; i != NumElems; ++i)
16934 ShuffleVec[i*SizeRatio] = i;
16936 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec,
16937 DAG.getUNDEF(WideVecVT),
16940 // Bitcast to the requested type.
16941 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff);
16942 // Replace the original load with the new sequence
16943 // and return the new chain.
16944 return DCI.CombineTo(N, Shuff, TF, true);
16950 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes.
16951 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG,
16952 const X86Subtarget *Subtarget) {
16953 StoreSDNode *St = cast<StoreSDNode>(N);
16954 EVT VT = St->getValue().getValueType();
16955 EVT StVT = St->getMemoryVT();
16956 DebugLoc dl = St->getDebugLoc();
16957 SDValue StoredVal = St->getOperand(1);
16958 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16960 // If we are saving a concatenation of two XMM registers, perform two stores.
16961 // On Sandy Bridge, 256-bit memory operations are executed by two
16962 // 128-bit ports. However, on Haswell it is better to issue a single 256-bit
16963 // memory operation.
16964 unsigned Alignment = St->getAlignment();
16965 bool IsAligned = Alignment == 0 || Alignment >= VT.getSizeInBits()/8;
16966 if (VT.is256BitVector() && !Subtarget->hasInt256() &&
16967 StVT == VT && !IsAligned) {
16968 unsigned NumElems = VT.getVectorNumElements();
16972 SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);
16973 SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);
16975 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());
16976 SDValue Ptr0 = St->getBasePtr();
16977 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);
16979 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0,
16980 St->getPointerInfo(), St->isVolatile(),
16981 St->isNonTemporal(), Alignment);
16982 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1,
16983 St->getPointerInfo(), St->isVolatile(),
16984 St->isNonTemporal(),
16985 std::min(16U, Alignment));
16986 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1);
16989 // Optimize trunc store (of multiple scalars) to shuffle and store.
16990 // First, pack all of the elements in one place. Next, store to memory
16991 // in fewer chunks.
16992 if (St->isTruncatingStore() && VT.isVector()) {
16993 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
16994 unsigned NumElems = VT.getVectorNumElements();
16995 assert(StVT != VT && "Cannot truncate to the same type");
16996 unsigned FromSz = VT.getVectorElementType().getSizeInBits();
16997 unsigned ToSz = StVT.getVectorElementType().getSizeInBits();
16999 // From, To sizes and ElemCount must be pow of two
17000 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();
17001 // We are going to use the original vector elt for storing.
17002 // Accumulated smaller vector elements must be a multiple of the store size.
17003 if (0 != (NumElems * FromSz) % ToSz) return SDValue();
17005 unsigned SizeRatio = FromSz / ToSz;
17007 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits());
17009 // Create a type on which we perform the shuffle
17010 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(),
17011 StVT.getScalarType(), NumElems*SizeRatio);
17013 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
17015 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue());
17016 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
17017 for (unsigned i = 0; i != NumElems; ++i)
17018 ShuffleVec[i] = i * SizeRatio;
17020 // Can't shuffle using an illegal type.
17021 if (!TLI.isTypeLegal(WideVecVT))
17024 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec,
17025 DAG.getUNDEF(WideVecVT),
17027 // At this point all of the data is stored at the bottom of the
17028 // register. We now need to save it to mem.
17030 // Find the largest store unit
17031 MVT StoreType = MVT::i8;
17032 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
17033 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
17034 MVT Tp = (MVT::SimpleValueType)tp;
17035 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
17039 // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
17040 if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
17041 (64 <= NumElems * ToSz))
17042 StoreType = MVT::f64;
17044 // Bitcast the original vector into a vector of store-size units
17045 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
17046 StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
17047 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
17048 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
17049 SmallVector<SDValue, 8> Chains;
17050 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
17051 TLI.getPointerTy());
17052 SDValue Ptr = St->getBasePtr();
17054 // Perform one or more big stores into memory.
17055 for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {
17056 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
17057 StoreType, ShuffWide,
17058 DAG.getIntPtrConstant(i));
17059 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,
17060 St->getPointerInfo(), St->isVolatile(),
17061 St->isNonTemporal(), St->getAlignment());
17062 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
17063 Chains.push_back(Ch);
17066 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0],
17070 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering
17071 // the FP state in cases where an emms may be missing.
17072 // A preferable solution to the general problem is to figure out the right
17073 // places to insert EMMS. This qualifies as a quick hack.
17075 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode.
17076 if (VT.getSizeInBits() != 64)
17079 const Function *F = DAG.getMachineFunction().getFunction();
17080 bool NoImplicitFloatOps = F->getAttributes().
17081 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
17082 bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps
17083 && Subtarget->hasSSE2();
17084 if ((VT.isVector() ||
17085 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&
17086 isa<LoadSDNode>(St->getValue()) &&
17087 !cast<LoadSDNode>(St->getValue())->isVolatile() &&
17088 St->getChain().hasOneUse() && !St->isVolatile()) {
17089 SDNode* LdVal = St->getValue().getNode();
17090 LoadSDNode *Ld = 0;
17091 int TokenFactorIndex = -1;
17092 SmallVector<SDValue, 8> Ops;
17093 SDNode* ChainVal = St->getChain().getNode();
17094 // Must be a store of a load. We currently handle two cases: the load
17095 // is a direct child, and it's under an intervening TokenFactor. It is
17096 // possible to dig deeper under nested TokenFactors.
17097 if (ChainVal == LdVal)
17098 Ld = cast<LoadSDNode>(St->getChain());
17099 else if (St->getValue().hasOneUse() &&
17100 ChainVal->getOpcode() == ISD::TokenFactor) {
17101 for (unsigned i = 0, e = ChainVal->getNumOperands(); i != e; ++i) {
17102 if (ChainVal->getOperand(i).getNode() == LdVal) {
17103 TokenFactorIndex = i;
17104 Ld = cast<LoadSDNode>(St->getValue());
17106 Ops.push_back(ChainVal->getOperand(i));
17110 if (!Ld || !ISD::isNormalLoad(Ld))
17113 // If this is not the MMX case, i.e. we are just turning i64 load/store
17114 // into f64 load/store, avoid the transformation if there are multiple
17115 // uses of the loaded value.
17116 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0))
17119 DebugLoc LdDL = Ld->getDebugLoc();
17120 DebugLoc StDL = N->getDebugLoc();
17121 // If we are a 64-bit capable x86, lower to a single movq load/store pair.
17122 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store
17124 if (Subtarget->is64Bit() || F64IsLegal) {
17125 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64;
17126 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(),
17127 Ld->getPointerInfo(), Ld->isVolatile(),
17128 Ld->isNonTemporal(), Ld->isInvariant(),
17129 Ld->getAlignment());
17130 SDValue NewChain = NewLd.getValue(1);
17131 if (TokenFactorIndex != -1) {
17132 Ops.push_back(NewChain);
17133 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17136 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(),
17137 St->getPointerInfo(),
17138 St->isVolatile(), St->isNonTemporal(),
17139 St->getAlignment());
17142 // Otherwise, lower to two pairs of 32-bit loads / stores.
17143 SDValue LoAddr = Ld->getBasePtr();
17144 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,
17145 DAG.getConstant(4, MVT::i32));
17147 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,
17148 Ld->getPointerInfo(),
17149 Ld->isVolatile(), Ld->isNonTemporal(),
17150 Ld->isInvariant(), Ld->getAlignment());
17151 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr,
17152 Ld->getPointerInfo().getWithOffset(4),
17153 Ld->isVolatile(), Ld->isNonTemporal(),
17155 MinAlign(Ld->getAlignment(), 4));
17157 SDValue NewChain = LoLd.getValue(1);
17158 if (TokenFactorIndex != -1) {
17159 Ops.push_back(LoLd);
17160 Ops.push_back(HiLd);
17161 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0],
17165 LoAddr = St->getBasePtr();
17166 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,
17167 DAG.getConstant(4, MVT::i32));
17169 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,
17170 St->getPointerInfo(),
17171 St->isVolatile(), St->isNonTemporal(),
17172 St->getAlignment());
17173 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr,
17174 St->getPointerInfo().getWithOffset(4),
17176 St->isNonTemporal(),
17177 MinAlign(St->getAlignment(), 4));
17178 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt);
17183 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal"
17184 /// and return the operands for the horizontal operation in LHS and RHS. A
17185 /// horizontal operation performs the binary operation on successive elements
17186 /// of its first operand, then on successive elements of its second operand,
17187 /// returning the resulting values in a vector. For example, if
17188 /// A = < float a0, float a1, float a2, float a3 >
17190 /// B = < float b0, float b1, float b2, float b3 >
17191 /// then the result of doing a horizontal operation on A and B is
17192 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >.
17193 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form
17194 /// A horizontal-op B, for some already available A and B, and if so then LHS is
17195 /// set to A, RHS to B, and the routine returns 'true'.
17196 /// Note that the binary operation should have the property that if one of the
17197 /// operands is UNDEF then the result is UNDEF.
17198 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool IsCommutative) {
17199 // Look for the following pattern: if
17200 // A = < float a0, float a1, float a2, float a3 >
17201 // B = < float b0, float b1, float b2, float b3 >
17203 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6>
17204 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7>
17205 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >
17206 // which is A horizontal-op B.
17208 // At least one of the operands should be a vector shuffle.
17209 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE &&
17210 RHS.getOpcode() != ISD::VECTOR_SHUFFLE)
17213 EVT VT = LHS.getValueType();
17215 assert((VT.is128BitVector() || VT.is256BitVector()) &&
17216 "Unsupported vector type for horizontal add/sub");
17218 // Handle 128 and 256-bit vector lengths. AVX defines horizontal add/sub to
17219 // operate independently on 128-bit lanes.
17220 unsigned NumElts = VT.getVectorNumElements();
17221 unsigned NumLanes = VT.getSizeInBits()/128;
17222 unsigned NumLaneElts = NumElts / NumLanes;
17223 assert((NumLaneElts % 2 == 0) &&
17224 "Vector type should have an even number of elements in each lane");
17225 unsigned HalfLaneElts = NumLaneElts/2;
17227 // View LHS in the form
17228 // LHS = VECTOR_SHUFFLE A, B, LMask
17229 // If LHS is not a shuffle then pretend it is the shuffle
17230 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1>
17231 // NOTE: in what follows a default initialized SDValue represents an UNDEF of
17234 SmallVector<int, 16> LMask(NumElts);
17235 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17236 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF)
17237 A = LHS.getOperand(0);
17238 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF)
17239 B = LHS.getOperand(1);
17240 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(LHS.getNode())->getMask();
17241 std::copy(Mask.begin(), Mask.end(), LMask.begin());
17243 if (LHS.getOpcode() != ISD::UNDEF)
17245 for (unsigned i = 0; i != NumElts; ++i)
17249 // Likewise, view RHS in the form
17250 // RHS = VECTOR_SHUFFLE C, D, RMask
17252 SmallVector<int, 16> RMask(NumElts);
17253 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) {
17254 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF)
17255 C = RHS.getOperand(0);
17256 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF)
17257 D = RHS.getOperand(1);
17258 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(RHS.getNode())->getMask();
17259 std::copy(Mask.begin(), Mask.end(), RMask.begin());
17261 if (RHS.getOpcode() != ISD::UNDEF)
17263 for (unsigned i = 0; i != NumElts; ++i)
17267 // Check that the shuffles are both shuffling the same vectors.
17268 if (!(A == C && B == D) && !(A == D && B == C))
17271 // If everything is UNDEF then bail out: it would be better to fold to UNDEF.
17272 if (!A.getNode() && !B.getNode())
17275 // If A and B occur in reverse order in RHS, then "swap" them (which means
17276 // rewriting the mask).
17278 CommuteVectorShuffleMask(RMask, NumElts);
17280 // At this point LHS and RHS are equivalent to
17281 // LHS = VECTOR_SHUFFLE A, B, LMask
17282 // RHS = VECTOR_SHUFFLE A, B, RMask
17283 // Check that the masks correspond to performing a horizontal operation.
17284 for (unsigned i = 0; i != NumElts; ++i) {
17285 int LIdx = LMask[i], RIdx = RMask[i];
17287 // Ignore any UNDEF components.
17288 if (LIdx < 0 || RIdx < 0 ||
17289 (!A.getNode() && (LIdx < (int)NumElts || RIdx < (int)NumElts)) ||
17290 (!B.getNode() && (LIdx >= (int)NumElts || RIdx >= (int)NumElts)))
17293 // Check that successive elements are being operated on. If not, this is
17294 // not a horizontal operation.
17295 unsigned Src = (i/HalfLaneElts) % 2; // each lane is split between srcs
17296 unsigned LaneStart = (i/NumLaneElts) * NumLaneElts;
17297 int Index = 2*(i%HalfLaneElts) + NumElts*Src + LaneStart;
17298 if (!(LIdx == Index && RIdx == Index + 1) &&
17299 !(IsCommutative && LIdx == Index + 1 && RIdx == Index))
17303 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it.
17304 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it.
17308 /// PerformFADDCombine - Do target-specific dag combines on floating point adds.
17309 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG,
17310 const X86Subtarget *Subtarget) {
17311 EVT VT = N->getValueType(0);
17312 SDValue LHS = N->getOperand(0);
17313 SDValue RHS = N->getOperand(1);
17315 // Try to synthesize horizontal adds from adds of shuffles.
17316 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17317 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17318 isHorizontalBinOp(LHS, RHS, true))
17319 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS);
17323 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs.
17324 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG,
17325 const X86Subtarget *Subtarget) {
17326 EVT VT = N->getValueType(0);
17327 SDValue LHS = N->getOperand(0);
17328 SDValue RHS = N->getOperand(1);
17330 // Try to synthesize horizontal subs from subs of shuffles.
17331 if (((Subtarget->hasSSE3() && (VT == MVT::v4f32 || VT == MVT::v2f64)) ||
17332 (Subtarget->hasFp256() && (VT == MVT::v8f32 || VT == MVT::v4f64))) &&
17333 isHorizontalBinOp(LHS, RHS, false))
17334 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS);
17338 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
17339 /// X86ISD::FXOR nodes.
17340 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
17341 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
17342 // F[X]OR(0.0, x) -> x
17343 // F[X]OR(x, 0.0) -> x
17344 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
17345 if (C->getValueAPF().isPosZero())
17346 return N->getOperand(1);
17347 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
17348 if (C->getValueAPF().isPosZero())
17349 return N->getOperand(0);
17353 /// PerformFMinFMaxCombine - Do target-specific dag combines on X86ISD::FMIN and
17354 /// X86ISD::FMAX nodes.
17355 static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
17356 assert(N->getOpcode() == X86ISD::FMIN || N->getOpcode() == X86ISD::FMAX);
17358 // Only perform optimizations if UnsafeMath is used.
17359 if (!DAG.getTarget().Options.UnsafeFPMath)
17362 // If we run in unsafe-math mode, then convert the FMAX and FMIN nodes
17363 // into FMINC and FMAXC, which are Commutative operations.
17364 unsigned NewOp = 0;
17365 switch (N->getOpcode()) {
17366 default: llvm_unreachable("unknown opcode");
17367 case X86ISD::FMIN: NewOp = X86ISD::FMINC; break;
17368 case X86ISD::FMAX: NewOp = X86ISD::FMAXC; break;
17371 return DAG.getNode(NewOp, N->getDebugLoc(), N->getValueType(0),
17372 N->getOperand(0), N->getOperand(1));
17375 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes.
17376 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) {
17377 // FAND(0.0, x) -> 0.0
17378 // FAND(x, 0.0) -> 0.0
17379 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
17380 if (C->getValueAPF().isPosZero())
17381 return N->getOperand(0);
17382 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1)))
17383 if (C->getValueAPF().isPosZero())
17384 return N->getOperand(1);
17388 static SDValue PerformBTCombine(SDNode *N,
17390 TargetLowering::DAGCombinerInfo &DCI) {
17391 // BT ignores high bits in the bit index operand.
17392 SDValue Op1 = N->getOperand(1);
17393 if (Op1.hasOneUse()) {
17394 unsigned BitWidth = Op1.getValueSizeInBits();
17395 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth));
17396 APInt KnownZero, KnownOne;
17397 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
17398 !DCI.isBeforeLegalizeOps());
17399 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
17400 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) ||
17401 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO))
17402 DCI.CommitTargetLoweringOpt(TLO);
17407 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
17408 SDValue Op = N->getOperand(0);
17409 if (Op.getOpcode() == ISD::BITCAST)
17410 Op = Op.getOperand(0);
17411 EVT VT = N->getValueType(0), OpVT = Op.getValueType();
17412 if (Op.getOpcode() == X86ISD::VZEXT_LOAD &&
17413 VT.getVectorElementType().getSizeInBits() ==
17414 OpVT.getVectorElementType().getSizeInBits()) {
17415 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
17420 static SDValue PerformSIGN_EXTEND_INREGCombine(SDNode *N, SelectionDAG &DAG,
17421 const X86Subtarget *Subtarget) {
17422 EVT VT = N->getValueType(0);
17423 if (!VT.isVector())
17426 SDValue N0 = N->getOperand(0);
17427 SDValue N1 = N->getOperand(1);
17428 EVT ExtraVT = cast<VTSDNode>(N1)->getVT();
17429 DebugLoc dl = N->getDebugLoc();
17431 // The SIGN_EXTEND_INREG to v4i64 is expensive operation on the
17432 // both SSE and AVX2 since there is no sign-extended shift right
17433 // operation on a vector with 64-bit elements.
17434 //(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) ->
17435 // (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
17436 if (VT == MVT::v4i64 && (N0.getOpcode() == ISD::ANY_EXTEND ||
17437 N0.getOpcode() == ISD::SIGN_EXTEND)) {
17438 SDValue N00 = N0.getOperand(0);
17440 // EXTLOAD has a better solution on AVX2,
17441 // it may be replaced with X86ISD::VSEXT node.
17442 if (N00.getOpcode() == ISD::LOAD && Subtarget->hasInt256())
17443 if (!ISD::isNormalLoad(N00.getNode()))
17446 if (N00.getValueType() == MVT::v4i32 && ExtraVT.getSizeInBits() < 128) {
17447 SDValue Tmp = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32,
17449 return DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i64, Tmp);
17455 static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
17456 TargetLowering::DAGCombinerInfo &DCI,
17457 const X86Subtarget *Subtarget) {
17458 if (!DCI.isBeforeLegalizeOps())
17461 if (!Subtarget->hasFp256())
17464 EVT VT = N->getValueType(0);
17465 if (VT.isVector() && VT.getSizeInBits() == 256) {
17466 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17474 static SDValue PerformFMACombine(SDNode *N, SelectionDAG &DAG,
17475 const X86Subtarget* Subtarget) {
17476 DebugLoc dl = N->getDebugLoc();
17477 EVT VT = N->getValueType(0);
17479 // Let legalize expand this if it isn't a legal type yet.
17480 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
17483 EVT ScalarVT = VT.getScalarType();
17484 if ((ScalarVT != MVT::f32 && ScalarVT != MVT::f64) ||
17485 (!Subtarget->hasFMA() && !Subtarget->hasFMA4()))
17488 SDValue A = N->getOperand(0);
17489 SDValue B = N->getOperand(1);
17490 SDValue C = N->getOperand(2);
17492 bool NegA = (A.getOpcode() == ISD::FNEG);
17493 bool NegB = (B.getOpcode() == ISD::FNEG);
17494 bool NegC = (C.getOpcode() == ISD::FNEG);
17496 // Negative multiplication when NegA xor NegB
17497 bool NegMul = (NegA != NegB);
17499 A = A.getOperand(0);
17501 B = B.getOperand(0);
17503 C = C.getOperand(0);
17507 Opcode = (!NegC) ? X86ISD::FMADD : X86ISD::FMSUB;
17509 Opcode = (!NegC) ? X86ISD::FNMADD : X86ISD::FNMSUB;
17511 return DAG.getNode(Opcode, dl, VT, A, B, C);
17514 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG,
17515 TargetLowering::DAGCombinerInfo &DCI,
17516 const X86Subtarget *Subtarget) {
17517 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
17518 // (and (i32 x86isd::setcc_carry), 1)
17519 // This eliminates the zext. This transformation is necessary because
17520 // ISD::SETCC is always legalized to i8.
17521 DebugLoc dl = N->getDebugLoc();
17522 SDValue N0 = N->getOperand(0);
17523 EVT VT = N->getValueType(0);
17525 if (N0.getOpcode() == ISD::AND &&
17527 N0.getOperand(0).hasOneUse()) {
17528 SDValue N00 = N0.getOperand(0);
17529 if (N00.getOpcode() == X86ISD::SETCC_CARRY) {
17530 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
17531 if (!C || C->getZExtValue() != 1)
17533 return DAG.getNode(ISD::AND, dl, VT,
17534 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,
17535 N00.getOperand(0), N00.getOperand(1)),
17536 DAG.getConstant(1, VT));
17540 if (VT.is256BitVector()) {
17541 SDValue R = WidenMaskArithmetic(N, DAG, DCI, Subtarget);
17549 // Optimize x == -y --> x+y == 0
17550 // x != -y --> x+y != 0
17551 static SDValue PerformISDSETCCCombine(SDNode *N, SelectionDAG &DAG) {
17552 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
17553 SDValue LHS = N->getOperand(0);
17554 SDValue RHS = N->getOperand(1);
17556 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)
17557 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))
17558 if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {
17559 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17560 LHS.getValueType(), RHS, LHS.getOperand(1));
17561 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17562 addV, DAG.getConstant(0, addV.getValueType()), CC);
17564 if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)
17565 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))
17566 if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {
17567 SDValue addV = DAG.getNode(ISD::ADD, N->getDebugLoc(),
17568 RHS.getValueType(), LHS, RHS.getOperand(1));
17569 return DAG.getSetCC(N->getDebugLoc(), N->getValueType(0),
17570 addV, DAG.getConstant(0, addV.getValueType()), CC);
17575 // Helper function of PerformSETCCCombine. It is to materialize "setb reg"
17576 // as "sbb reg,reg", since it can be extended without zext and produces
17577 // an all-ones bit which is more useful than 0/1 in some cases.
17578 static SDValue MaterializeSETB(DebugLoc DL, SDValue EFLAGS, SelectionDAG &DAG) {
17579 return DAG.getNode(ISD::AND, DL, MVT::i8,
17580 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,
17581 DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),
17582 DAG.getConstant(1, MVT::i8));
17585 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT
17586 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG,
17587 TargetLowering::DAGCombinerInfo &DCI,
17588 const X86Subtarget *Subtarget) {
17589 DebugLoc DL = N->getDebugLoc();
17590 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(0));
17591 SDValue EFLAGS = N->getOperand(1);
17593 if (CC == X86::COND_A) {
17594 // Try to convert COND_A into COND_B in an attempt to facilitate
17595 // materializing "setb reg".
17597 // Do not flip "e > c", where "c" is a constant, because Cmp instruction
17598 // cannot take an immediate as its first operand.
17600 if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
17601 EFLAGS.getValueType().isInteger() &&
17602 !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
17603 SDValue NewSub = DAG.getNode(X86ISD::SUB, EFLAGS.getDebugLoc(),
17604 EFLAGS.getNode()->getVTList(),
17605 EFLAGS.getOperand(1), EFLAGS.getOperand(0));
17606 SDValue NewEFLAGS = SDValue(NewSub.getNode(), EFLAGS.getResNo());
17607 return MaterializeSETB(DL, NewEFLAGS, DAG);
17611 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without
17612 // a zext and produces an all-ones bit which is more useful than 0/1 in some
17614 if (CC == X86::COND_B)
17615 return MaterializeSETB(DL, EFLAGS, DAG);
17619 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17620 if (Flags.getNode()) {
17621 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17622 return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);
17628 // Optimize branch condition evaluation.
17630 static SDValue PerformBrCondCombine(SDNode *N, SelectionDAG &DAG,
17631 TargetLowering::DAGCombinerInfo &DCI,
17632 const X86Subtarget *Subtarget) {
17633 DebugLoc DL = N->getDebugLoc();
17634 SDValue Chain = N->getOperand(0);
17635 SDValue Dest = N->getOperand(1);
17636 SDValue EFLAGS = N->getOperand(3);
17637 X86::CondCode CC = X86::CondCode(N->getConstantOperandVal(2));
17641 Flags = checkBoolTestSetCCCombine(EFLAGS, CC);
17642 if (Flags.getNode()) {
17643 SDValue Cond = DAG.getConstant(CC, MVT::i8);
17644 return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,
17651 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
17652 const X86TargetLowering *XTLI) {
17653 SDValue Op0 = N->getOperand(0);
17654 EVT InVT = Op0->getValueType(0);
17656 // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
17657 if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
17658 DebugLoc dl = N->getDebugLoc();
17659 MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
17660 SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
17661 return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
17664 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
17665 // a 32-bit target where SSE doesn't support i64->FP operations.
17666 if (Op0.getOpcode() == ISD::LOAD) {
17667 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
17668 EVT VT = Ld->getValueType(0);
17669 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
17670 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
17671 !XTLI->getSubtarget()->is64Bit() &&
17672 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
17673 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0),
17674 Ld->getChain(), Op0, DAG);
17675 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
17682 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
17683 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
17684 X86TargetLowering::DAGCombinerInfo &DCI) {
17685 // If the LHS and RHS of the ADC node are zero, then it can't overflow and
17686 // the result is either zero or one (depending on the input carry bit).
17687 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1.
17688 if (X86::isZeroNode(N->getOperand(0)) &&
17689 X86::isZeroNode(N->getOperand(1)) &&
17690 // We don't have a good way to replace an EFLAGS use, so only do this when
17692 SDValue(N, 1).use_empty()) {
17693 DebugLoc DL = N->getDebugLoc();
17694 EVT VT = N->getValueType(0);
17695 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));
17696 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,
17697 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,
17698 DAG.getConstant(X86::COND_B,MVT::i8),
17700 DAG.getConstant(1, VT));
17701 return DCI.CombineTo(N, Res1, CarryOut);
17707 // fold (add Y, (sete X, 0)) -> adc 0, Y
17708 // (add Y, (setne X, 0)) -> sbb -1, Y
17709 // (sub (sete X, 0), Y) -> sbb 0, Y
17710 // (sub (setne X, 0), Y) -> adc -1, Y
17711 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) {
17712 DebugLoc DL = N->getDebugLoc();
17714 // Look through ZExts.
17715 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0);
17716 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse())
17719 SDValue SetCC = Ext.getOperand(0);
17720 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse())
17723 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0);
17724 if (CC != X86::COND_E && CC != X86::COND_NE)
17727 SDValue Cmp = SetCC.getOperand(1);
17728 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() ||
17729 !X86::isZeroNode(Cmp.getOperand(1)) ||
17730 !Cmp.getOperand(0).getValueType().isInteger())
17733 SDValue CmpOp0 = Cmp.getOperand(0);
17734 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,
17735 DAG.getConstant(1, CmpOp0.getValueType()));
17737 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);
17738 if (CC == X86::COND_NE)
17739 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,
17740 DL, OtherVal.getValueType(), OtherVal,
17741 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);
17742 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,
17743 DL, OtherVal.getValueType(), OtherVal,
17744 DAG.getConstant(0, OtherVal.getValueType()), NewCmp);
17747 /// PerformADDCombine - Do target-specific dag combines on integer adds.
17748 static SDValue PerformAddCombine(SDNode *N, SelectionDAG &DAG,
17749 const X86Subtarget *Subtarget) {
17750 EVT VT = N->getValueType(0);
17751 SDValue Op0 = N->getOperand(0);
17752 SDValue Op1 = N->getOperand(1);
17754 // Try to synthesize horizontal adds from adds of shuffles.
17755 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17756 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17757 isHorizontalBinOp(Op0, Op1, true))
17758 return DAG.getNode(X86ISD::HADD, N->getDebugLoc(), VT, Op0, Op1);
17760 return OptimizeConditionalInDecrement(N, DAG);
17763 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG,
17764 const X86Subtarget *Subtarget) {
17765 SDValue Op0 = N->getOperand(0);
17766 SDValue Op1 = N->getOperand(1);
17768 // X86 can't encode an immediate LHS of a sub. See if we can push the
17769 // negation into a preceding instruction.
17770 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
17771 // If the RHS of the sub is a XOR with one use and a constant, invert the
17772 // immediate. Then add one to the LHS of the sub so we can turn
17773 // X-Y -> X+~Y+1, saving one register.
17774 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
17775 isa<ConstantSDNode>(Op1.getOperand(1))) {
17776 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
17777 EVT VT = Op0.getValueType();
17778 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT,
17780 DAG.getConstant(~XorC, VT));
17781 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor,
17782 DAG.getConstant(C->getAPIntValue()+1, VT));
17786 // Try to synthesize horizontal adds from adds of shuffles.
17787 EVT VT = N->getValueType(0);
17788 if (((Subtarget->hasSSSE3() && (VT == MVT::v8i16 || VT == MVT::v4i32)) ||
17789 (Subtarget->hasInt256() && (VT == MVT::v16i16 || VT == MVT::v8i32))) &&
17790 isHorizontalBinOp(Op0, Op1, true))
17791 return DAG.getNode(X86ISD::HSUB, N->getDebugLoc(), VT, Op0, Op1);
17793 return OptimizeConditionalInDecrement(N, DAG);
17796 /// performVZEXTCombine - Performs build vector combines
17797 static SDValue performVZEXTCombine(SDNode *N, SelectionDAG &DAG,
17798 TargetLowering::DAGCombinerInfo &DCI,
17799 const X86Subtarget *Subtarget) {
17800 // (vzext (bitcast (vzext (x)) -> (vzext x)
17801 SDValue In = N->getOperand(0);
17802 while (In.getOpcode() == ISD::BITCAST)
17803 In = In.getOperand(0);
17805 if (In.getOpcode() != X86ISD::VZEXT)
17808 return DAG.getNode(X86ISD::VZEXT, N->getDebugLoc(), N->getValueType(0),
17812 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
17813 DAGCombinerInfo &DCI) const {
17814 SelectionDAG &DAG = DCI.DAG;
17815 switch (N->getOpcode()) {
17817 case ISD::EXTRACT_VECTOR_ELT:
17818 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, DCI);
17820 case ISD::SELECT: return PerformSELECTCombine(N, DAG, DCI, Subtarget);
17821 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI, Subtarget);
17822 case ISD::ADD: return PerformAddCombine(N, DAG, Subtarget);
17823 case ISD::SUB: return PerformSubCombine(N, DAG, Subtarget);
17824 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI);
17825 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
17828 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
17829 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
17830 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
17831 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
17832 case ISD::LOAD: return PerformLOADCombine(N, DAG, DCI, Subtarget);
17833 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
17834 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
17835 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
17836 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
17838 case X86ISD::FOR: return PerformFORCombine(N, DAG);
17840 case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
17841 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
17842 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
17843 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
17844 case ISD::ANY_EXTEND:
17845 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG, DCI, Subtarget);
17846 case ISD::SIGN_EXTEND: return PerformSExtCombine(N, DAG, DCI, Subtarget);
17847 case ISD::SIGN_EXTEND_INREG: return PerformSIGN_EXTEND_INREGCombine(N, DAG, Subtarget);
17848 case ISD::TRUNCATE: return PerformTruncateCombine(N, DAG,DCI,Subtarget);
17849 case ISD::SETCC: return PerformISDSETCCCombine(N, DAG);
17850 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG, DCI, Subtarget);
17851 case X86ISD::BRCOND: return PerformBrCondCombine(N, DAG, DCI, Subtarget);
17852 case X86ISD::VZEXT: return performVZEXTCombine(N, DAG, DCI, Subtarget);
17853 case X86ISD::SHUFP: // Handle all target specific shuffles
17854 case X86ISD::PALIGNR:
17855 case X86ISD::UNPCKH:
17856 case X86ISD::UNPCKL:
17857 case X86ISD::MOVHLPS:
17858 case X86ISD::MOVLHPS:
17859 case X86ISD::PSHUFD:
17860 case X86ISD::PSHUFHW:
17861 case X86ISD::PSHUFLW:
17862 case X86ISD::MOVSS:
17863 case X86ISD::MOVSD:
17864 case X86ISD::VPERMILP:
17865 case X86ISD::VPERM2X128:
17866 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget);
17867 case ISD::FMA: return PerformFMACombine(N, DAG, Subtarget);
17873 /// isTypeDesirableForOp - Return true if the target has native support for
17874 /// the specified value type and it is 'desirable' to use the type for the
17875 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
17876 /// instruction encodings are longer and some i16 instructions are slow.
17877 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {
17878 if (!isTypeLegal(VT))
17880 if (VT != MVT::i16)
17887 case ISD::SIGN_EXTEND:
17888 case ISD::ZERO_EXTEND:
17889 case ISD::ANY_EXTEND:
17902 /// IsDesirableToPromoteOp - This method query the target whether it is
17903 /// beneficial for dag combiner to promote the specified node. If true, it
17904 /// should return the desired promotion type by reference.
17905 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
17906 EVT VT = Op.getValueType();
17907 if (VT != MVT::i16)
17910 bool Promote = false;
17911 bool Commute = false;
17912 switch (Op.getOpcode()) {
17915 LoadSDNode *LD = cast<LoadSDNode>(Op);
17916 // If the non-extending load has a single use and it's not live out, then it
17917 // might be folded.
17918 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&&
17919 Op.hasOneUse()*/) {
17920 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
17921 UE = Op.getNode()->use_end(); UI != UE; ++UI) {
17922 // The only case where we'd want to promote LOAD (rather then it being
17923 // promoted as an operand is when it's only use is liveout.
17924 if (UI->getOpcode() != ISD::CopyToReg)
17931 case ISD::SIGN_EXTEND:
17932 case ISD::ZERO_EXTEND:
17933 case ISD::ANY_EXTEND:
17938 SDValue N0 = Op.getOperand(0);
17939 // Look out for (store (shl (load), x)).
17940 if (MayFoldLoad(N0) && MayFoldIntoStore(Op))
17953 SDValue N0 = Op.getOperand(0);
17954 SDValue N1 = Op.getOperand(1);
17955 if (!Commute && MayFoldLoad(N1))
17957 // Avoid disabling potential load folding opportunities.
17958 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
17960 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
17970 //===----------------------------------------------------------------------===//
17971 // X86 Inline Assembly Support
17972 //===----------------------------------------------------------------------===//
17975 // Helper to match a string separated by whitespace.
17976 bool matchAsmImpl(StringRef s, ArrayRef<const StringRef *> args) {
17977 s = s.substr(s.find_first_not_of(" \t")); // Skip leading whitespace.
17979 for (unsigned i = 0, e = args.size(); i != e; ++i) {
17980 StringRef piece(*args[i]);
17981 if (!s.startswith(piece)) // Check if the piece matches.
17984 s = s.substr(piece.size());
17985 StringRef::size_type pos = s.find_first_not_of(" \t");
17986 if (pos == 0) // We matched a prefix.
17994 const VariadicFunction1<bool, StringRef, StringRef, matchAsmImpl> matchAsm={};
17997 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const {
17998 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
18000 std::string AsmStr = IA->getAsmString();
18002 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
18003 if (!Ty || Ty->getBitWidth() % 16 != 0)
18006 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a"
18007 SmallVector<StringRef, 4> AsmPieces;
18008 SplitString(AsmStr, AsmPieces, ";\n");
18010 switch (AsmPieces.size()) {
18011 default: return false;
18013 // FIXME: this should verify that we are targeting a 486 or better. If not,
18014 // we will turn this bswap into something that will be lowered to logical
18015 // ops instead of emitting the bswap asm. For now, we don't support 486 or
18016 // lower so don't worry about this.
18018 if (matchAsm(AsmPieces[0], "bswap", "$0") ||
18019 matchAsm(AsmPieces[0], "bswapl", "$0") ||
18020 matchAsm(AsmPieces[0], "bswapq", "$0") ||
18021 matchAsm(AsmPieces[0], "bswap", "${0:q}") ||
18022 matchAsm(AsmPieces[0], "bswapl", "${0:q}") ||
18023 matchAsm(AsmPieces[0], "bswapq", "${0:q}")) {
18024 // No need to check constraints, nothing other than the equivalent of
18025 // "=r,0" would be valid here.
18026 return IntrinsicLowering::LowerToByteSwap(CI);
18029 // rorw $$8, ${0:w} --> llvm.bswap.i16
18030 if (CI->getType()->isIntegerTy(16) &&
18031 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18032 (matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") ||
18033 matchAsm(AsmPieces[0], "rolw", "$$8,", "${0:w}"))) {
18035 const std::string &ConstraintsStr = IA->getConstraintString();
18036 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18037 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18038 if (AsmPieces.size() == 4 &&
18039 AsmPieces[0] == "~{cc}" &&
18040 AsmPieces[1] == "~{dirflag}" &&
18041 AsmPieces[2] == "~{flags}" &&
18042 AsmPieces[3] == "~{fpsr}")
18043 return IntrinsicLowering::LowerToByteSwap(CI);
18047 if (CI->getType()->isIntegerTy(32) &&
18048 IA->getConstraintString().compare(0, 5, "=r,0,") == 0 &&
18049 matchAsm(AsmPieces[0], "rorw", "$$8,", "${0:w}") &&
18050 matchAsm(AsmPieces[1], "rorl", "$$16,", "$0") &&
18051 matchAsm(AsmPieces[2], "rorw", "$$8,", "${0:w}")) {
18053 const std::string &ConstraintsStr = IA->getConstraintString();
18054 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ",");
18055 array_pod_sort(AsmPieces.begin(), AsmPieces.end());
18056 if (AsmPieces.size() == 4 &&
18057 AsmPieces[0] == "~{cc}" &&
18058 AsmPieces[1] == "~{dirflag}" &&
18059 AsmPieces[2] == "~{flags}" &&
18060 AsmPieces[3] == "~{fpsr}")
18061 return IntrinsicLowering::LowerToByteSwap(CI);
18064 if (CI->getType()->isIntegerTy(64)) {
18065 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints();
18066 if (Constraints.size() >= 2 &&
18067 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" &&
18068 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") {
18069 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64
18070 if (matchAsm(AsmPieces[0], "bswap", "%eax") &&
18071 matchAsm(AsmPieces[1], "bswap", "%edx") &&
18072 matchAsm(AsmPieces[2], "xchgl", "%eax,", "%edx"))
18073 return IntrinsicLowering::LowerToByteSwap(CI);
18081 /// getConstraintType - Given a constraint letter, return the type of
18082 /// constraint it is for this target.
18083 X86TargetLowering::ConstraintType
18084 X86TargetLowering::getConstraintType(const std::string &Constraint) const {
18085 if (Constraint.size() == 1) {
18086 switch (Constraint[0]) {
18097 return C_RegisterClass;
18121 return TargetLowering::getConstraintType(Constraint);
18124 /// Examine constraint type and operand type and determine a weight value.
18125 /// This object must already have been set up with the operand type
18126 /// and the current alternative constraint selected.
18127 TargetLowering::ConstraintWeight
18128 X86TargetLowering::getSingleConstraintMatchWeight(
18129 AsmOperandInfo &info, const char *constraint) const {
18130 ConstraintWeight weight = CW_Invalid;
18131 Value *CallOperandVal = info.CallOperandVal;
18132 // If we don't have a value, we can't do a match,
18133 // but allow it at the lowest weight.
18134 if (CallOperandVal == NULL)
18136 Type *type = CallOperandVal->getType();
18137 // Look at the constraint type.
18138 switch (*constraint) {
18140 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
18151 if (CallOperandVal->getType()->isIntegerTy())
18152 weight = CW_SpecificReg;
18157 if (type->isFloatingPointTy())
18158 weight = CW_SpecificReg;
18161 if (type->isX86_MMXTy() && Subtarget->hasMMX())
18162 weight = CW_SpecificReg;
18166 if (((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasSSE1()) ||
18167 ((type->getPrimitiveSizeInBits() == 256) && Subtarget->hasFp256()))
18168 weight = CW_Register;
18171 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
18172 if (C->getZExtValue() <= 31)
18173 weight = CW_Constant;
18177 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18178 if (C->getZExtValue() <= 63)
18179 weight = CW_Constant;
18183 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18184 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f))
18185 weight = CW_Constant;
18189 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18190 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff))
18191 weight = CW_Constant;
18195 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18196 if (C->getZExtValue() <= 3)
18197 weight = CW_Constant;
18201 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18202 if (C->getZExtValue() <= 0xff)
18203 weight = CW_Constant;
18208 if (dyn_cast<ConstantFP>(CallOperandVal)) {
18209 weight = CW_Constant;
18213 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18214 if ((C->getSExtValue() >= -0x80000000LL) &&
18215 (C->getSExtValue() <= 0x7fffffffLL))
18216 weight = CW_Constant;
18220 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) {
18221 if (C->getZExtValue() <= 0xffffffff)
18222 weight = CW_Constant;
18229 /// LowerXConstraint - try to replace an X constraint, which matches anything,
18230 /// with another that has more specific requirements based on the type of the
18231 /// corresponding operand.
18232 const char *X86TargetLowering::
18233 LowerXConstraint(EVT ConstraintVT) const {
18234 // FP X constraints get lowered to SSE1/2 registers if available, otherwise
18235 // 'f' like normal targets.
18236 if (ConstraintVT.isFloatingPoint()) {
18237 if (Subtarget->hasSSE2())
18239 if (Subtarget->hasSSE1())
18243 return TargetLowering::LowerXConstraint(ConstraintVT);
18246 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
18247 /// vector. If it is invalid, don't add anything to Ops.
18248 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op,
18249 std::string &Constraint,
18250 std::vector<SDValue>&Ops,
18251 SelectionDAG &DAG) const {
18252 SDValue Result(0, 0);
18254 // Only support length 1 constraints for now.
18255 if (Constraint.length() > 1) return;
18257 char ConstraintLetter = Constraint[0];
18258 switch (ConstraintLetter) {
18261 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18262 if (C->getZExtValue() <= 31) {
18263 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18269 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18270 if (C->getZExtValue() <= 63) {
18271 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18277 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18278 if (isInt<8>(C->getSExtValue())) {
18279 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18285 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18286 if (C->getZExtValue() <= 255) {
18287 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18293 // 32-bit signed value
18294 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18295 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18296 C->getSExtValue())) {
18297 // Widen to 64 bits here to get it sign extended.
18298 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);
18301 // FIXME gcc accepts some relocatable values here too, but only in certain
18302 // memory models; it's complicated.
18307 // 32-bit unsigned value
18308 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
18309 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
18310 C->getZExtValue())) {
18311 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());
18315 // FIXME gcc accepts some relocatable values here too, but only in certain
18316 // memory models; it's complicated.
18320 // Literal immediates are always ok.
18321 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
18322 // Widen to 64 bits here to get it sign extended.
18323 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);
18327 // In any sort of PIC mode addresses need to be computed at runtime by
18328 // adding in a register or some sort of table lookup. These can't
18329 // be used as immediates.
18330 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC())
18333 // If we are in non-pic codegen mode, we allow the address of a global (with
18334 // an optional displacement) to be used with 'i'.
18335 GlobalAddressSDNode *GA = 0;
18336 int64_t Offset = 0;
18338 // Match either (GA), (GA+C), (GA+C1+C2), etc.
18340 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) {
18341 Offset += GA->getOffset();
18343 } else if (Op.getOpcode() == ISD::ADD) {
18344 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
18345 Offset += C->getZExtValue();
18346 Op = Op.getOperand(0);
18349 } else if (Op.getOpcode() == ISD::SUB) {
18350 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
18351 Offset += -C->getZExtValue();
18352 Op = Op.getOperand(0);
18357 // Otherwise, this isn't something we can handle, reject it.
18361 const GlobalValue *GV = GA->getGlobal();
18362 // If we require an extra load to get this address, as in PIC mode, we
18363 // can't accept it.
18364 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV,
18365 getTargetMachine())))
18368 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(),
18369 GA->getValueType(0), Offset);
18374 if (Result.getNode()) {
18375 Ops.push_back(Result);
18378 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
18381 std::pair<unsigned, const TargetRegisterClass*>
18382 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
18384 // First, see if this is a constraint that directly corresponds to an LLVM
18386 if (Constraint.size() == 1) {
18387 // GCC Constraint Letters
18388 switch (Constraint[0]) {
18390 // TODO: Slight differences here in allocation order and leaving
18391 // RIP in the class. Do they matter any more here than they do
18392 // in the normal allocation?
18393 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
18394 if (Subtarget->is64Bit()) {
18395 if (VT == MVT::i32 || VT == MVT::f32)
18396 return std::make_pair(0U, &X86::GR32RegClass);
18397 if (VT == MVT::i16)
18398 return std::make_pair(0U, &X86::GR16RegClass);
18399 if (VT == MVT::i8 || VT == MVT::i1)
18400 return std::make_pair(0U, &X86::GR8RegClass);
18401 if (VT == MVT::i64 || VT == MVT::f64)
18402 return std::make_pair(0U, &X86::GR64RegClass);
18405 // 32-bit fallthrough
18406 case 'Q': // Q_REGS
18407 if (VT == MVT::i32 || VT == MVT::f32)
18408 return std::make_pair(0U, &X86::GR32_ABCDRegClass);
18409 if (VT == MVT::i16)
18410 return std::make_pair(0U, &X86::GR16_ABCDRegClass);
18411 if (VT == MVT::i8 || VT == MVT::i1)
18412 return std::make_pair(0U, &X86::GR8_ABCD_LRegClass);
18413 if (VT == MVT::i64)
18414 return std::make_pair(0U, &X86::GR64_ABCDRegClass);
18416 case 'r': // GENERAL_REGS
18417 case 'l': // INDEX_REGS
18418 if (VT == MVT::i8 || VT == MVT::i1)
18419 return std::make_pair(0U, &X86::GR8RegClass);
18420 if (VT == MVT::i16)
18421 return std::make_pair(0U, &X86::GR16RegClass);
18422 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit())
18423 return std::make_pair(0U, &X86::GR32RegClass);
18424 return std::make_pair(0U, &X86::GR64RegClass);
18425 case 'R': // LEGACY_REGS
18426 if (VT == MVT::i8 || VT == MVT::i1)
18427 return std::make_pair(0U, &X86::GR8_NOREXRegClass);
18428 if (VT == MVT::i16)
18429 return std::make_pair(0U, &X86::GR16_NOREXRegClass);
18430 if (VT == MVT::i32 || !Subtarget->is64Bit())
18431 return std::make_pair(0U, &X86::GR32_NOREXRegClass);
18432 return std::make_pair(0U, &X86::GR64_NOREXRegClass);
18433 case 'f': // FP Stack registers.
18434 // If SSE is enabled for this VT, use f80 to ensure the isel moves the
18435 // value to the correct fpstack register class.
18436 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT))
18437 return std::make_pair(0U, &X86::RFP32RegClass);
18438 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT))
18439 return std::make_pair(0U, &X86::RFP64RegClass);
18440 return std::make_pair(0U, &X86::RFP80RegClass);
18441 case 'y': // MMX_REGS if MMX allowed.
18442 if (!Subtarget->hasMMX()) break;
18443 return std::make_pair(0U, &X86::VR64RegClass);
18444 case 'Y': // SSE_REGS if SSE2 allowed
18445 if (!Subtarget->hasSSE2()) break;
18447 case 'x': // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
18448 if (!Subtarget->hasSSE1()) break;
18450 switch (VT.getSimpleVT().SimpleTy) {
18452 // Scalar SSE types.
18455 return std::make_pair(0U, &X86::FR32RegClass);
18458 return std::make_pair(0U, &X86::FR64RegClass);
18466 return std::make_pair(0U, &X86::VR128RegClass);
18474 return std::make_pair(0U, &X86::VR256RegClass);
18480 // Use the default implementation in TargetLowering to convert the register
18481 // constraint into a member of a register class.
18482 std::pair<unsigned, const TargetRegisterClass*> Res;
18483 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
18485 // Not found as a standard register?
18486 if (Res.second == 0) {
18487 // Map st(0) -> st(7) -> ST0
18488 if (Constraint.size() == 7 && Constraint[0] == '{' &&
18489 tolower(Constraint[1]) == 's' &&
18490 tolower(Constraint[2]) == 't' &&
18491 Constraint[3] == '(' &&
18492 (Constraint[4] >= '0' && Constraint[4] <= '7') &&
18493 Constraint[5] == ')' &&
18494 Constraint[6] == '}') {
18496 Res.first = X86::ST0+Constraint[4]-'0';
18497 Res.second = &X86::RFP80RegClass;
18501 // GCC allows "st(0)" to be called just plain "st".
18502 if (StringRef("{st}").equals_lower(Constraint)) {
18503 Res.first = X86::ST0;
18504 Res.second = &X86::RFP80RegClass;
18509 if (StringRef("{flags}").equals_lower(Constraint)) {
18510 Res.first = X86::EFLAGS;
18511 Res.second = &X86::CCRRegClass;
18515 // 'A' means EAX + EDX.
18516 if (Constraint == "A") {
18517 Res.first = X86::EAX;
18518 Res.second = &X86::GR32_ADRegClass;
18524 // Otherwise, check to see if this is a register class of the wrong value
18525 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
18526 // turn into {ax},{dx}.
18527 if (Res.second->hasType(VT))
18528 return Res; // Correct type already, nothing to do.
18530 // All of the single-register GCC register classes map their values onto
18531 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we
18532 // really want an 8-bit or 32-bit register, map to the appropriate register
18533 // class and return the appropriate register.
18534 if (Res.second == &X86::GR16RegClass) {
18535 if (VT == MVT::i8 || VT == MVT::i1) {
18536 unsigned DestReg = 0;
18537 switch (Res.first) {
18539 case X86::AX: DestReg = X86::AL; break;
18540 case X86::DX: DestReg = X86::DL; break;
18541 case X86::CX: DestReg = X86::CL; break;
18542 case X86::BX: DestReg = X86::BL; break;
18545 Res.first = DestReg;
18546 Res.second = &X86::GR8RegClass;
18548 } else if (VT == MVT::i32 || VT == MVT::f32) {
18549 unsigned DestReg = 0;
18550 switch (Res.first) {
18552 case X86::AX: DestReg = X86::EAX; break;
18553 case X86::DX: DestReg = X86::EDX; break;
18554 case X86::CX: DestReg = X86::ECX; break;
18555 case X86::BX: DestReg = X86::EBX; break;
18556 case X86::SI: DestReg = X86::ESI; break;
18557 case X86::DI: DestReg = X86::EDI; break;
18558 case X86::BP: DestReg = X86::EBP; break;
18559 case X86::SP: DestReg = X86::ESP; break;
18562 Res.first = DestReg;
18563 Res.second = &X86::GR32RegClass;
18565 } else if (VT == MVT::i64 || VT == MVT::f64) {
18566 unsigned DestReg = 0;
18567 switch (Res.first) {
18569 case X86::AX: DestReg = X86::RAX; break;
18570 case X86::DX: DestReg = X86::RDX; break;
18571 case X86::CX: DestReg = X86::RCX; break;
18572 case X86::BX: DestReg = X86::RBX; break;
18573 case X86::SI: DestReg = X86::RSI; break;
18574 case X86::DI: DestReg = X86::RDI; break;
18575 case X86::BP: DestReg = X86::RBP; break;
18576 case X86::SP: DestReg = X86::RSP; break;
18579 Res.first = DestReg;
18580 Res.second = &X86::GR64RegClass;
18583 } else if (Res.second == &X86::FR32RegClass ||
18584 Res.second == &X86::FR64RegClass ||
18585 Res.second == &X86::VR128RegClass) {
18586 // Handle references to XMM physical registers that got mapped into the
18587 // wrong class. This can happen with constraints like {xmm0} where the
18588 // target independent register mapper will just pick the first match it can
18589 // find, ignoring the required type.
18591 if (VT == MVT::f32 || VT == MVT::i32)
18592 Res.second = &X86::FR32RegClass;
18593 else if (VT == MVT::f64 || VT == MVT::i64)
18594 Res.second = &X86::FR64RegClass;
18595 else if (X86::VR128RegClass.hasType(VT))
18596 Res.second = &X86::VR128RegClass;
18597 else if (X86::VR256RegClass.hasType(VT))
18598 Res.second = &X86::VR256RegClass;